gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999-2016 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com) and
   5 ;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify it under
  10 ;; the terms of the GNU General Public License as published by the Free
  11 ;; Software Foundation; either version 3, or (at your option) any later
  12 ;; version.
  13
  14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 ;; for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;;
  24 ;; See constraints.md for a description of constraints specific to s390.
  25 ;;
  26
  27 ;; Special formats used for outputting 390 instructions.
  28 ;;
  29 ;;     %C: print opcode suffix for branch condition.
  30 ;;     %D: print opcode suffix for inverse branch condition.
  31 ;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
  32 ;;     %G: print the size of the operand in bytes.
  33 ;;     %O: print only the displacement of a memory reference.
  34 ;;     %R: print only the base register of a memory reference.
  35 ;;     %S: print S-type memory reference (base+displacement).
  36 ;;     %N: print the second word of a DImode operand.
  37 ;;     %M: print the second word of a TImode operand.
  38 ;;     %Y: print shift count operand.
  39 ;;
  40 ;;     %b: print integer X as if it's an unsigned byte.
  41 ;;     %c: print integer X as if it's an signed byte.
  42 ;;     %x: print integer X as if it's an unsigned halfword.
  43 ;;     %h: print integer X as if it's a signed halfword.
  44 ;;     %i: print the first nonzero HImode part of X.
  45 ;;     %j: print the first HImode part unequal to -1 of X.
  46 ;;     %k: print the first nonzero SImode part of X.
  47 ;;     %m: print the first SImode part unequal to -1 of X.
  48 ;;     %o: print integer X as if it's an unsigned 32bit word.
  49 ;;
  50 ;; We have a special constraint for pattern matching.
  51 ;;
  52 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  53 ;;
  54
  55 ;;
  56 ;; UNSPEC usage
  57 ;;
  58
  59 (define_c_enum "unspec" [
  60    ; Miscellaneous
  61    UNSPEC_ROUND
  62    UNSPEC_ICM
  63    UNSPEC_TIE
  64
  65    ; Convert CC into a str comparison result and copy it into an
  66    ; integer register
  67    ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
  68    UNSPEC_STRCMPCC_TO_INT
  69
  70    ; Copy CC as is into the lower 2 bits of an integer register
  71    UNSPEC_CC_TO_INT
  72
  73    ; The right hand side of an setmem
  74    UNSPEC_REPLICATE_BYTE
  75
  76    ; GOT/PLT and lt-relative accesses
  77    UNSPEC_LTREL_OFFSET
  78    UNSPEC_LTREL_BASE
  79    UNSPEC_POOL_OFFSET
  80    UNSPEC_GOTENT
  81    UNSPEC_GOT
  82    UNSPEC_GOTOFF
  83    UNSPEC_PLT
  84    UNSPEC_PLTOFF
  85
  86    ; Literal pool
  87    UNSPEC_RELOAD_BASE
  88    UNSPEC_MAIN_BASE
  89    UNSPEC_LTREF
  90    UNSPEC_INSN
  91    UNSPEC_EXECUTE
  92
  93    ; Atomic Support
  94    UNSPEC_MB
  95    UNSPEC_MOVA
  96
  97    ; TLS relocation specifiers
  98    UNSPEC_TLSGD
  99    UNSPEC_TLSLDM
 100    UNSPEC_NTPOFF
 101    UNSPEC_DTPOFF
 102    UNSPEC_GOTNTPOFF
 103    UNSPEC_INDNTPOFF
 104
 105    ; TLS support
 106    UNSPEC_TLSLDM_NTPOFF
 107    UNSPEC_TLS_LOAD
 108
 109    ; String Functions
 110    UNSPEC_SRST
 111    UNSPEC_MVST
 112
 113    ; Stack Smashing Protector
 114    UNSPEC_SP_SET
 115    UNSPEC_SP_TEST
 116
 117    ; Split stack support
 118    UNSPEC_STACK_CHECK
 119
 120    ; Test Data Class (TDC)
 121    UNSPEC_TDC_INSN
 122
 123    ; Population Count
 124    UNSPEC_POPCNT
 125    UNSPEC_COPYSIGN
 126
 127    ; Load FP Integer
 128    UNSPEC_FPINT_FLOOR
 129    UNSPEC_FPINT_BTRUNC
 130    UNSPEC_FPINT_ROUND
 131    UNSPEC_FPINT_CEIL
 132    UNSPEC_FPINT_NEARBYINT
 133    UNSPEC_FPINT_RINT
 134
 135    UNSPEC_LCBB
 136
 137    ; Vector
 138    UNSPEC_VEC_SMULT_HI
 139    UNSPEC_VEC_UMULT_HI
 140    UNSPEC_VEC_SMULT_LO
 141    UNSPEC_VEC_SMULT_EVEN
 142    UNSPEC_VEC_UMULT_EVEN
 143    UNSPEC_VEC_SMULT_ODD
 144    UNSPEC_VEC_UMULT_ODD
 145
 146    UNSPEC_VEC_VMAL
 147    UNSPEC_VEC_VMAH
 148    UNSPEC_VEC_VMALH
 149    UNSPEC_VEC_VMAE
 150    UNSPEC_VEC_VMALE
 151    UNSPEC_VEC_VMAO
 152    UNSPEC_VEC_VMALO
 153
 154    UNSPEC_VEC_GATHER
 155    UNSPEC_VEC_EXTRACT
 156    UNSPEC_VEC_INSERT_AND_ZERO
 157    UNSPEC_VEC_LOAD_BNDRY
 158    UNSPEC_VEC_LOAD_LEN
 159    UNSPEC_VEC_MERGEH
 160    UNSPEC_VEC_MERGEL
 161    UNSPEC_VEC_PACK
 162    UNSPEC_VEC_PACK_SATURATE
 163    UNSPEC_VEC_PACK_SATURATE_CC
 164    UNSPEC_VEC_PACK_SATURATE_GENCC
 165    UNSPEC_VEC_PACK_UNSIGNED_SATURATE
 166    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
 167    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
 168    UNSPEC_VEC_PERM
 169    UNSPEC_VEC_PERMI
 170    UNSPEC_VEC_EXTEND
 171    UNSPEC_VEC_STORE_LEN
 172    UNSPEC_VEC_UNPACKH
 173    UNSPEC_VEC_UNPACKH_L
 174    UNSPEC_VEC_UNPACKL
 175    UNSPEC_VEC_UNPACKL_L
 176    UNSPEC_VEC_ADDC
 177    UNSPEC_VEC_ADDC_U128
 178    UNSPEC_VEC_ADDE_U128
 179    UNSPEC_VEC_ADDEC_U128
 180    UNSPEC_VEC_AVG
 181    UNSPEC_VEC_AVGU
 182    UNSPEC_VEC_CHECKSUM
 183    UNSPEC_VEC_GFMSUM
 184    UNSPEC_VEC_GFMSUM_128
 185    UNSPEC_VEC_GFMSUM_ACCUM
 186    UNSPEC_VEC_GFMSUM_ACCUM_128
 187    UNSPEC_VEC_SET
 188
 189    UNSPEC_VEC_VSUMG
 190    UNSPEC_VEC_VSUMQ
 191    UNSPEC_VEC_VSUM
 192    UNSPEC_VEC_RL_MASK
 193    UNSPEC_VEC_SLL
 194    UNSPEC_VEC_SLB
 195    UNSPEC_VEC_SLDB
 196    UNSPEC_VEC_SRAL
 197    UNSPEC_VEC_SRAB
 198    UNSPEC_VEC_SRL
 199    UNSPEC_VEC_SRLB
 200
 201    UNSPEC_VEC_SUB_U128
 202    UNSPEC_VEC_SUBC
 203    UNSPEC_VEC_SUBC_U128
 204    UNSPEC_VEC_SUBE_U128
 205    UNSPEC_VEC_SUBEC_U128
 206
 207    UNSPEC_VEC_TEST_MASK
 208
 209    UNSPEC_VEC_VFAE
 210    UNSPEC_VEC_VFAECC
 211
 212    UNSPEC_VEC_VFEE
 213    UNSPEC_VEC_VFEECC
 214    UNSPEC_VEC_VFENE
 215    UNSPEC_VEC_VFENECC
 216
 217    UNSPEC_VEC_VISTR
 218    UNSPEC_VEC_VISTRCC
 219
 220    UNSPEC_VEC_VSTRC
 221    UNSPEC_VEC_VSTRCCC
 222
 223    UNSPEC_VEC_VCDGB
 224    UNSPEC_VEC_VCDLGB
 225
 226    UNSPEC_VEC_VCGDB
 227    UNSPEC_VEC_VCLGDB
 228
 229    UNSPEC_VEC_VFIDB
 230
 231    UNSPEC_VEC_VLDEB
 232    UNSPEC_VEC_VLEDB
 233
 234    UNSPEC_VEC_VFTCIDB
 235    UNSPEC_VEC_VFTCIDBCC
 236 ])
 237
 238 ;;
 239 ;; UNSPEC_VOLATILE usage
 240 ;;
 241
 242 (define_c_enum "unspecv" [
 243    ; Blockage
 244    UNSPECV_BLOCKAGE
 245
 246    ; TPF Support
 247    UNSPECV_TPF_PROLOGUE
 248    UNSPECV_TPF_EPILOGUE
 249
 250    ; Literal pool
 251    UNSPECV_POOL
 252    UNSPECV_POOL_SECTION
 253    UNSPECV_POOL_ALIGN
 254    UNSPECV_POOL_ENTRY
 255    UNSPECV_MAIN_POOL
 256
 257    ; TLS support
 258    UNSPECV_SET_TP
 259
 260    ; Atomic Support
 261    UNSPECV_CAS
 262    UNSPECV_ATOMIC_OP
 263
 264    ; Hotpatching (unremovable NOPs)
 265    UNSPECV_NOP_2_BYTE
 266    UNSPECV_NOP_4_BYTE
 267    UNSPECV_NOP_6_BYTE
 268
 269    ; Transactional Execution support
 270    UNSPECV_TBEGIN
 271    UNSPECV_TBEGIN_TDB
 272    UNSPECV_TBEGINC
 273    UNSPECV_TEND
 274    UNSPECV_TABORT
 275    UNSPECV_ETND
 276    UNSPECV_NTSTG
 277    UNSPECV_PPA
 278
 279    ; Set and get floating point control register
 280    UNSPECV_SFPC
 281    UNSPECV_EFPC
 282
 283    ; Split stack support
 284    UNSPECV_SPLIT_STACK_CALL
 285    UNSPECV_SPLIT_STACK_DATA
 286   ])
 287
 288 ;;
 289 ;; Registers
 290 ;;
 291
 292 ; Registers with special meaning
 293
 294 (define_constants
 295   [
 296    ; Sibling call register.
 297    (SIBCALL_REGNUM               1)
 298    ; Literal pool base register.
 299    (BASE_REGNUM                 13)
 300    ; Return address register.
 301    (RETURN_REGNUM               14)
 302    ; Condition code register.
 303    (CC_REGNUM                   33)
 304    ; Thread local storage pointer register.
 305    (TP_REGNUM                   36)
 306   ])
 307
 308 ; Hardware register names
 309
 310 (define_constants
 311   [
 312    ; General purpose registers
 313    (GPR0_REGNUM                  0)
 314    (GPR1_REGNUM                  1)
 315    (GPR2_REGNUM                  2)
 316    (GPR6_REGNUM                  6)
 317    ; Floating point registers.
 318    (FPR0_REGNUM                 16)
 319    (FPR1_REGNUM                 20)
 320    (FPR2_REGNUM                 17)
 321    (FPR3_REGNUM                 21)
 322    (FPR4_REGNUM                 18)
 323    (FPR5_REGNUM                 22)
 324    (FPR6_REGNUM                 19)
 325    (FPR7_REGNUM                 23)
 326    (FPR8_REGNUM                 24)
 327    (FPR9_REGNUM                 28)
 328    (FPR10_REGNUM                25)
 329    (FPR11_REGNUM                29)
 330    (FPR12_REGNUM                26)
 331    (FPR13_REGNUM                30)
 332    (FPR14_REGNUM                27)
 333    (FPR15_REGNUM                31)
 334    (VR0_REGNUM                  16)
 335    (VR16_REGNUM                 38)
 336    (VR23_REGNUM                 45)
 337    (VR24_REGNUM                 46)
 338    (VR31_REGNUM                 53)
 339   ])
 340
 341 ;;
 342 ;; PFPO GPR0 argument format
 343 ;;
 344
 345 (define_constants
 346   [
 347    ; PFPO operation type
 348    (PFPO_CONVERT          0x1000000)
 349    ; PFPO operand types
 350    (PFPO_OP_TYPE_SF             0x5)
 351    (PFPO_OP_TYPE_DF             0x6)
 352    (PFPO_OP_TYPE_TF             0x7)
 353    (PFPO_OP_TYPE_SD             0x8)
 354    (PFPO_OP_TYPE_DD             0x9)
 355    (PFPO_OP_TYPE_TD             0xa)
 356    ; Bitposition of operand types
 357    (PFPO_OP0_TYPE_SHIFT          16)
 358    (PFPO_OP1_TYPE_SHIFT           8)
 359   ])
 360
 361 ; Immediate operands for tbegin and tbeginc
 362 (define_constants [(TBEGIN_MASK  65292)]) ; 0xff0c
 363 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
 364
 365 ;; Instruction operand type as used in the Principles of Operation.
 366 ;; Used to determine defaults for length and other attribute values.
 367
 368 (define_attr "op_type"
 369   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
 370   (const_string "NN"))
 371
 372 ;; Instruction type attribute used for scheduling.
 373
 374 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 375                      cs,vs,store,sem,idiv,
 376                      imulhi,imulsi,imuldi,
 377                      branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 378                      floadtf,floaddf,floadsf,fstoredf,fstoresf,
 379                      fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 380                      ftoi,fsqrttf,fsqrtdf,fsqrtsf,
 381                      fmadddf,fmaddsf,
 382                      ftrunctf,ftruncdf, ftruncsd, ftruncdd,
 383                      itoftf, itofdf, itofsf, itofdd, itoftd,
 384                      fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
 385                      fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
 386                      ftoidfp, other"
 387   (cond [(eq_attr "op_type" "NN")  (const_string "other")
 388          (eq_attr "op_type" "SS")  (const_string "cs")]
 389     (const_string "integer")))
 390
 391 ;; Another attribute used for scheduling purposes:
 392 ;;   agen: Instruction uses the address generation unit
 393 ;;   reg: Instruction does not use the agen unit
 394
 395 (define_attr "atype" "agen,reg"
 396   (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
 397                 (const_string "reg")
 398                 (const_string "agen")))
 399
 400 ;; Properties concerning Z10 execution grouping and value forwarding.
 401 ;; z10_super: instruction is superscalar.
 402 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
 403 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
 404 ;;   target register.  It can forward this value to a second instruction that reads
 405 ;;   the same register if that second instruction is issued in the same group.
 406 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
 407 ;;   instruction in the S pipe writes to the register, then the T instruction
 408 ;;   can immediately read the new value.
 409 ;; z10_fr: union of Z10_fwd and z10_rec.
 410 ;; z10_c: second operand of instruction is a register and read with complemented bits.
 411 ;;
 412 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
 413
 414
 415 (define_attr "z10prop" "none,
 416                         z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
 417                         z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
 418                         z10_rec,
 419                         z10_fr, z10_fr_A3, z10_fr_E1,
 420                         z10_c"
 421              (const_string "none"))
 422
 423 ;; Properties concerning Z196 decoding
 424 ;; z196_alone: must group alone
 425 ;; z196_end: ends a group
 426 ;; z196_cracked: instruction is cracked or expanded
 427 (define_attr "z196prop" "none,
 428                          z196_alone, z196_ends,
 429                          z196_cracked"
 430              (const_string "none"))
 431
 432 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
 433
 434 ;; Length in bytes.
 435
 436 (define_attr "length" ""
 437   (cond [(eq_attr "op_type" "E,RR")                       (const_int 2)
 438          (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF")  (const_int 4)]
 439     (const_int 6)))
 440
 441
 442 ;; Processor type.  This attribute must exactly match the processor_type
 443 ;; enumeration in s390.h.  The current machine description does not
 444 ;; distinguish between g5 and g6, but there are differences between the two
 445 ;; CPUs could in theory be modeled.
 446
 447 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
 448   (const (symbol_ref "s390_tune_attr")))
 449
 450 (define_attr "cpu_facility"
 451   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
 452   (const_string "standard"))
 453
 454 (define_attr "enabled" ""
 455   (cond [(eq_attr "cpu_facility" "standard")
 456          (const_int 1)
 457
 458          (and (eq_attr "cpu_facility" "ieee")
 459               (match_test "TARGET_CPU_IEEE_FLOAT"))
 460          (const_int 1)
 461
 462          (and (eq_attr "cpu_facility" "zarch")
 463               (match_test "TARGET_ZARCH"))
 464          (const_int 1)
 465
 466          (and (eq_attr "cpu_facility" "longdisp")
 467               (match_test "TARGET_LONG_DISPLACEMENT"))
 468          (const_int 1)
 469
 470          (and (eq_attr "cpu_facility" "extimm")
 471               (match_test "TARGET_EXTIMM"))
 472          (const_int 1)
 473
 474          (and (eq_attr "cpu_facility" "dfp")
 475               (match_test "TARGET_DFP"))
 476          (const_int 1)
 477
 478          (and (eq_attr "cpu_facility" "cpu_zarch")
 479               (match_test "TARGET_CPU_ZARCH"))
 480          (const_int 1)
 481
 482          (and (eq_attr "cpu_facility" "z10")
 483               (match_test "TARGET_Z10"))
 484          (const_int 1)
 485
 486          (and (eq_attr "cpu_facility" "z196")
 487               (match_test "TARGET_Z196"))
 488          (const_int 1)
 489
 490          (and (eq_attr "cpu_facility" "zEC12")
 491               (match_test "TARGET_ZEC12"))
 492          (const_int 1)
 493
 494          (and (eq_attr "cpu_facility" "vec")
 495               (match_test "TARGET_VX"))
 496          (const_int 1)]
 497         (const_int 0)))
 498
 499 ;; Pipeline description for z900.  For lack of anything better,
 500 ;; this description is also used for the g5 and g6.
 501 (include "2064.md")
 502
 503 ;; Pipeline description for z990, z9-109 and z9-ec.
 504 (include "2084.md")
 505
 506 ;; Pipeline description for z10
 507 (include "2097.md")
 508
 509 ;; Pipeline description for z196
 510 (include "2817.md")
 511
 512 ;; Pipeline description for zEC12
 513 (include "2827.md")
 514
 515 ;; Pipeline description for z13
 516 (include "2964.md")
 517
 518 ;; Predicates
 519 (include "predicates.md")
 520
 521 ;; Constraint definitions
 522 (include "constraints.md")
 523
 524 ;; Other includes
 525 (include "tpf.md")
 526
 527 ;; Iterators
 528
 529 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
 530
 531 ;; These mode iterators allow floating point patterns to be generated from the
 532 ;; same template.
 533 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
 534                               (SD "TARGET_HARD_DFP")])
 535 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
 536 (define_mode_iterator BFP [TF DF SF])
 537 (define_mode_iterator DFP [TD DD])
 538 (define_mode_iterator DFP_ALL [TD DD SD])
 539 (define_mode_iterator DSF [DF SF])
 540 (define_mode_iterator SD_SF [SF SD])
 541 (define_mode_iterator DD_DF [DF DD])
 542 (define_mode_iterator TD_TF [TF TD])
 543
 544 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 545 ;; from the same template.
 546 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
 547 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
 548 (define_mode_iterator DSI [DI SI])
 549 (define_mode_iterator TDI [TI DI])
 550
 551 ;; These mode iterators allow :P to be used for patterns that operate on
 552 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 553 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 554
 555 ;; These macros refer to the actual word_mode of the configuration.
 556 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
 557 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
 558 (define_mode_iterator W  [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
 559
 560 ;; Used by the umul pattern to express modes having half the size.
 561 (define_mode_attr DWH [(TI "DI") (DI "SI")])
 562 (define_mode_attr dwh [(TI "di") (DI "si")])
 563
 564 ;; This mode iterator allows the QI and HI patterns to be defined from
 565 ;; the same template.
 566 (define_mode_iterator HQI [HI QI])
 567
 568 ;; This mode iterator allows the integer patterns to be defined from the
 569 ;; same template.
 570 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
 571 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
 572
 573 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 574 ;; the same template.
 575 (define_code_iterator SHIFT [ashift lshiftrt])
 576
 577 ;; This iterator allows r[ox]sbg to be defined with the same template
 578 (define_code_iterator IXOR [ior xor])
 579
 580 ;; This iterator is used to expand the patterns for the nearest
 581 ;; integer functions.
 582 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
 583                             UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
 584                             UNSPEC_FPINT_NEARBYINT])
 585 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
 586                              (UNSPEC_FPINT_BTRUNC "btrunc")
 587                              (UNSPEC_FPINT_ROUND "round")
 588                              (UNSPEC_FPINT_CEIL "ceil")
 589                              (UNSPEC_FPINT_NEARBYINT "nearbyint")])
 590 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
 591                                      (UNSPEC_FPINT_BTRUNC "5")
 592                                      (UNSPEC_FPINT_ROUND "1")
 593                                      (UNSPEC_FPINT_CEIL "6")
 594                                      (UNSPEC_FPINT_NEARBYINT "0")])
 595
 596 ;; This iterator and attribute allow to combine most atomic operations.
 597 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 598 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
 599 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
 600                           (plus "add") (minus "sub") (mult "nand")])
 601 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
 602
 603 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
 604 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
 605 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
 606
 607 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
 608 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
 609 ;; SDmode.
 610 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
 611
 612 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 613 ;; Likewise for "<RXe>".
 614 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 615 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 616
 617 ;; The decimal floating point variants of add, sub, div and mul support 3
 618 ;; fp register operands.  The following attributes allow to merge the bfp and
 619 ;; dfp variants in a single insn definition.
 620
 621 ;; These mode attributes are supposed to be used in the `enabled' insn
 622 ;; attribute to disable certain alternatives for certain modes.
 623 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
 624 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
 625 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
 626 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
 627                         (TD "0") (DD "0") (DD "0")
 628                         (TI "0") (DI "*") (SI "0")])
 629
 630 ;; This attribute is used in the operand constraint list
 631 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
 632 ;; TFmode values are represented by a fp register pair.  Since the
 633 ;; sign bit instructions only handle single source and target fp registers
 634 ;; these instructions can only be used for TFmode values if the source and
 635 ;; target operand uses the same fp register.
 636 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 637
 638 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 639 ;; within instruction mnemonics.
 640 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 641
 642 ;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
 643 ;; modes and to an empty string for bfp modes.
 644 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 645
 646 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 647 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
 648 ;; version only operates on one register.
 649 (define_mode_attr d0 [(DI "d") (SI "0")])
 650
 651 ;; In combination with d0 this allows to combine instructions of which the 31bit
 652 ;; version only operates on one register. The DImode version needs an additional
 653 ;; register for the assembler output.
 654 (define_mode_attr 1 [(DI "%1,") (SI "")])
 655
 656 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 657 ;; 'ashift' and "srdl" in 'lshiftrt'.
 658 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 659
 660 ;; In SHIFT templates, this attribute holds the correct standard name for the
 661 ;; pattern itself and the corresponding function calls.
 662 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 663
 664 ;; This attribute handles differences in the instruction 'type' and will result
 665 ;; in "RRE" for DImode and "RR" for SImode.
 666 (define_mode_attr E [(DI "E") (SI "")])
 667
 668 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
 669 ;; to result in "RXY" for DImode and "RX" for SImode.
 670 (define_mode_attr Y [(DI "Y") (SI "")])
 671
 672 ;; This attribute handles differences in the instruction 'type' and will result
 673 ;; in "RSE" for TImode and "RS" for DImode.
 674 (define_mode_attr TE [(TI "E") (DI "")])
 675
 676 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
 677 ;; and "lcr" in SImode.
 678 (define_mode_attr g [(DI "g") (SI "")])
 679
 680 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
 681 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
 682 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
 683 ;; variant for long displacements.
 684 (define_mode_attr y [(DI "g") (SI "y")])
 685
 686 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
 687 ;; and "cds" in DImode.
 688 (define_mode_attr tg [(TI "g") (DI "")])
 689
 690 ;; In TDI templates, a string like "c<d>sg".
 691 (define_mode_attr td [(TI "d") (DI "")])
 692
 693 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
 694 ;; and "cfdbr" in SImode.
 695 (define_mode_attr gf [(DI "g") (SI "f")])
 696
 697 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
 698 ;; and sllk for SI.  This way it is possible to merge the new z196 SI
 699 ;; 3 operands shift instructions into the existing patterns.
 700 (define_mode_attr gk [(DI "g") (SI "k")])
 701
 702 ;; ICM mask required to load MODE value into the lowest subreg
 703 ;; of a SImode register.
 704 (define_mode_attr icm_lo [(HI "3") (QI "1")])
 705
 706 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
 707 ;; HImode and "llgc" in QImode.
 708 (define_mode_attr hc [(HI "h") (QI "c")])
 709
 710 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
 711 ;; in SImode.
 712 (define_mode_attr DBL [(DI "TI") (SI "DI")])
 713
 714 ;; This attribute expands to DF for TFmode and to DD for TDmode .  It is
 715 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
 716 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
 717
 718 ;; Maximum unsigned integer that fits in MODE.
 719 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 720
 721 ;; Start and end field computations for RISBG et al.
 722 (define_mode_attr bfstart [(DI "s") (SI "t")])
 723 (define_mode_attr bfend   [(DI "e") (SI "f")])
 724
 725 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 726 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
 727
 728 ;; In place of GET_MODE_SIZE (<MODE>mode)
 729 (define_mode_attr modesize [(DI "8") (SI "4")])
 730
 731 ;; Allow return and simple_return to be defined from a single template.
 732 (define_code_iterator ANY_RETURN [return simple_return])
 733
 734
 735
 736 ; Condition code modes generated by vector fp comparisons.  These will
 737 ; be used also in single element mode.
 738 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
 739 ; Used with VFCMP to expand part of the mnemonic
 740 ; For fp we have a mismatch: eq in the insn name - e in asm
 741 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 742 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
 743
 744 ;; Subst pattern definitions
 745 (include "subst.md")
 746
 747 (include "vector.md")
 748
 749 ;;
 750 ;;- Compare instructions.
 751 ;;
 752
 753 ; Test-under-Mask instructions
 754
 755 (define_insn "*tmqi_mem"
 756   [(set (reg CC_REGNUM)
 757         (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
 758                          (match_operand:QI 1 "immediate_operand" "n,n"))
 759                  (match_operand:QI 2 "immediate_operand" "n,n")))]
 760   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
 761   "@
 762    tm\t%S0,%b1
 763    tmy\t%S0,%b1"
 764   [(set_attr "op_type" "SI,SIY")
 765    (set_attr "z10prop" "z10_super,z10_super")])
 766
 767 (define_insn "*tmdi_reg"
 768   [(set (reg CC_REGNUM)
 769         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
 770                          (match_operand:DI 1 "immediate_operand"
 771                                              "N0HD0,N1HD0,N2HD0,N3HD0"))
 772                  (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
 773   "TARGET_ZARCH
 774    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 775    && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
 776   "@
 777    tmhh\t%0,%i1
 778    tmhl\t%0,%i1
 779    tmlh\t%0,%i1
 780    tmll\t%0,%i1"
 781   [(set_attr "op_type" "RI")
 782    (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 783
 784 (define_insn "*tmsi_reg"
 785   [(set (reg CC_REGNUM)
 786         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
 787                          (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
 788                  (match_operand:SI 2 "immediate_operand" "n,n")))]
 789   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 790    && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
 791   "@
 792    tmh\t%0,%i1
 793    tml\t%0,%i1"
 794   [(set_attr "op_type" "RI")
 795    (set_attr "z10prop" "z10_super,z10_super")])
 796
 797 (define_insn "*tm<mode>_full"
 798   [(set (reg CC_REGNUM)
 799         (compare (match_operand:HQI 0 "register_operand" "d")
 800                  (match_operand:HQI 1 "immediate_operand" "n")))]
 801   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
 802   "tml\t%0,<max_uint>"
 803   [(set_attr "op_type" "RI")
 804    (set_attr "z10prop" "z10_super")])
 805
 806
 807 ;
 808 ; Load-and-Test instructions
 809 ;
 810
 811 ; tst(di|si) instruction pattern(s).
 812
 813 (define_insn "*tstdi_sign"
 814   [(set (reg CC_REGNUM)
 815         (compare
 816           (ashiftrt:DI
 817             (ashift:DI
 818               (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
 819               (const_int 32)) (const_int 32))
 820           (match_operand:DI 1 "const0_operand" "")))
 821    (set (match_operand:DI 2 "register_operand" "=d,d")
 822         (sign_extend:DI (match_dup 0)))]
 823   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
 824   "ltgfr\t%2,%0
 825    ltgf\t%2,%0"
 826   [(set_attr "op_type"      "RRE,RXY")
 827    (set_attr "cpu_facility" "*,z10")
 828    (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 829
 830 ; ltr, lt, ltgr, ltg
 831 (define_insn "*tst<mode>_extimm"
 832   [(set (reg CC_REGNUM)
 833         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 834                  (match_operand:GPR 1 "const0_operand" "")))
 835    (set (match_operand:GPR 2 "register_operand" "=d,d")
 836         (match_dup 0))]
 837   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 838   "@
 839    lt<g>r\t%2,%0
 840    lt<g>\t%2,%0"
 841   [(set_attr "op_type" "RR<E>,RXY")
 842    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 843
 844 ; ltr, lt, ltgr, ltg
 845 (define_insn "*tst<mode>_cconly_extimm"
 846   [(set (reg CC_REGNUM)
 847         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 848                  (match_operand:GPR 1 "const0_operand" "")))
 849    (clobber (match_scratch:GPR 2 "=X,d"))]
 850   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 851   "@
 852    lt<g>r\t%0,%0
 853    lt<g>\t%2,%0"
 854   [(set_attr "op_type" "RR<E>,RXY")
 855    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 856
 857 (define_insn "*tstdi"
 858   [(set (reg CC_REGNUM)
 859         (compare (match_operand:DI 0 "register_operand" "d")
 860                  (match_operand:DI 1 "const0_operand" "")))
 861    (set (match_operand:DI 2 "register_operand" "=d")
 862         (match_dup 0))]
 863   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
 864   "ltgr\t%2,%0"
 865   [(set_attr "op_type" "RRE")
 866    (set_attr "z10prop" "z10_fr_E1")])
 867
 868 (define_insn "*tstsi"
 869   [(set (reg CC_REGNUM)
 870         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 871                  (match_operand:SI 1 "const0_operand" "")))
 872    (set (match_operand:SI 2 "register_operand" "=d,d,d")
 873         (match_dup 0))]
 874   "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
 875   "@
 876    ltr\t%2,%0
 877    icm\t%2,15,%S0
 878    icmy\t%2,15,%S0"
 879   [(set_attr "op_type" "RR,RS,RSY")
 880    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 881
 882 (define_insn "*tstsi_cconly"
 883   [(set (reg CC_REGNUM)
 884         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 885                  (match_operand:SI 1 "const0_operand" "")))
 886    (clobber (match_scratch:SI 2 "=X,d,d"))]
 887   "s390_match_ccmode(insn, CCSmode)"
 888   "@
 889    ltr\t%0,%0
 890    icm\t%2,15,%S0
 891    icmy\t%2,15,%S0"
 892   [(set_attr "op_type" "RR,RS,RSY")
 893    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 894
 895 (define_insn "*tstdi_cconly_31"
 896   [(set (reg CC_REGNUM)
 897         (compare (match_operand:DI 0 "register_operand" "d")
 898                  (match_operand:DI 1 "const0_operand" "")))]
 899   "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
 900   "srda\t%0,0"
 901   [(set_attr "op_type" "RS")
 902    (set_attr "atype"   "reg")])
 903
 904 ; ltr, ltgr
 905 (define_insn "*tst<mode>_cconly2"
 906   [(set (reg CC_REGNUM)
 907         (compare (match_operand:GPR 0 "register_operand" "d")
 908                  (match_operand:GPR 1 "const0_operand" "")))]
 909   "s390_match_ccmode(insn, CCSmode)"
 910   "lt<g>r\t%0,%0"
 911   [(set_attr "op_type" "RR<E>")
 912    (set_attr "z10prop" "z10_fr_E1")])
 913
 914 ; tst(hi|qi) instruction pattern(s).
 915
 916 (define_insn "*tst<mode>CCT"
 917   [(set (reg CC_REGNUM)
 918         (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
 919                  (match_operand:HQI 1 "const0_operand" "")))
 920    (set (match_operand:HQI 2 "register_operand" "=d,d,0")
 921         (match_dup 0))]
 922   "s390_match_ccmode(insn, CCTmode)"
 923   "@
 924    icm\t%2,<icm_lo>,%S0
 925    icmy\t%2,<icm_lo>,%S0
 926    tml\t%0,<max_uint>"
 927   [(set_attr "op_type" "RS,RSY,RI")
 928    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 929
 930 (define_insn "*tsthiCCT_cconly"
 931   [(set (reg CC_REGNUM)
 932         (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
 933                  (match_operand:HI 1 "const0_operand" "")))
 934    (clobber (match_scratch:HI 2 "=d,d,X"))]
 935   "s390_match_ccmode(insn, CCTmode)"
 936   "@
 937    icm\t%2,3,%S0
 938    icmy\t%2,3,%S0
 939    tml\t%0,65535"
 940   [(set_attr "op_type" "RS,RSY,RI")
 941    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 942
 943 (define_insn "*tstqiCCT_cconly"
 944   [(set (reg CC_REGNUM)
 945         (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
 946                  (match_operand:QI 1 "const0_operand" "")))]
 947   "s390_match_ccmode(insn, CCTmode)"
 948   "@
 949    cli\t%S0,0
 950    cliy\t%S0,0
 951    tml\t%0,255"
 952   [(set_attr "op_type" "SI,SIY,RI")
 953    (set_attr "z10prop" "z10_super,z10_super,z10_super")])
 954
 955 (define_insn "*tst<mode>"
 956   [(set (reg CC_REGNUM)
 957         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 958                  (match_operand:HQI 1 "const0_operand" "")))
 959    (set (match_operand:HQI 2 "register_operand" "=d,d")
 960         (match_dup 0))]
 961   "s390_match_ccmode(insn, CCSmode)"
 962   "@
 963    icm\t%2,<icm_lo>,%S0
 964    icmy\t%2,<icm_lo>,%S0"
 965   [(set_attr "op_type" "RS,RSY")
 966    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 967
 968 (define_insn "*tst<mode>_cconly"
 969   [(set (reg CC_REGNUM)
 970         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 971                  (match_operand:HQI 1 "const0_operand" "")))
 972    (clobber (match_scratch:HQI 2 "=d,d"))]
 973   "s390_match_ccmode(insn, CCSmode)"
 974   "@
 975    icm\t%2,<icm_lo>,%S0
 976    icmy\t%2,<icm_lo>,%S0"
 977   [(set_attr "op_type" "RS,RSY")
 978    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 979
 980
 981 ; Compare (equality) instructions
 982
 983 (define_insn "*cmpdi_cct"
 984   [(set (reg CC_REGNUM)
 985         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
 986                  (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
 987   "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
 988   "@
 989    cgr\t%0,%1
 990    cghi\t%0,%h1
 991    cgfi\t%0,%1
 992    cg\t%0,%1
 993    #"
 994   [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
 995    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
 996
 997 (define_insn "*cmpsi_cct"
 998   [(set (reg CC_REGNUM)
 999         (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1000                  (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1001   "s390_match_ccmode (insn, CCTmode)"
1002   "@
1003    cr\t%0,%1
1004    chi\t%0,%h1
1005    cfi\t%0,%1
1006    c\t%0,%1
1007    cy\t%0,%1
1008    #"
1009   [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1010    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1011
1012 ; Compare (signed) instructions
1013
1014 (define_insn "*cmpdi_ccs_sign"
1015   [(set (reg CC_REGNUM)
1016         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1017                                                      "d,RT,b"))
1018                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1019   "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1020   "@
1021    cgfr\t%0,%1
1022    cgf\t%0,%1
1023    cgfrl\t%0,%1"
1024   [(set_attr "op_type"      "RRE,RXY,RIL")
1025    (set_attr "z10prop" "z10_c,*,*")
1026    (set_attr "type"         "*,*,larl")])
1027
1028
1029
1030 (define_insn "*cmpsi_ccs_sign"
1031   [(set (reg CC_REGNUM)
1032         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1033                  (match_operand:SI 0 "register_operand" "d,d,d")))]
1034   "s390_match_ccmode(insn, CCSRmode)"
1035   "@
1036    ch\t%0,%1
1037    chy\t%0,%1
1038    chrl\t%0,%1"
1039   [(set_attr "op_type"      "RX,RXY,RIL")
1040    (set_attr "cpu_facility" "*,*,z10")
1041    (set_attr "type"         "*,*,larl")
1042    (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1043
1044 (define_insn "*cmphi_ccs_z10"
1045   [(set (reg CC_REGNUM)
1046         (compare (match_operand:HI 0 "s_operand"         "Q")
1047                  (match_operand:HI 1 "immediate_operand" "K")))]
1048   "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1049   "chhsi\t%0,%1"
1050   [(set_attr "op_type" "SIL")
1051    (set_attr "z196prop" "z196_cracked")])
1052
1053 (define_insn "*cmpdi_ccs_signhi_rl"
1054   [(set (reg CC_REGNUM)
1055         (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
1056                  (match_operand:GPR 0 "register_operand"  "d,d")))]
1057   "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1058   "@
1059    cgh\t%0,%1
1060    cghrl\t%0,%1"
1061   [(set_attr "op_type" "RXY,RIL")
1062    (set_attr "type"    "*,larl")])
1063
1064 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1065 (define_insn "*cmp<mode>_ccs"
1066   [(set (reg CC_REGNUM)
1067         (compare (match_operand:GPR 0 "nonimmediate_operand"
1068                                       "d,d,Q, d,d,d,d")
1069                  (match_operand:GPR 1 "general_operand"
1070                                       "d,K,K,Os,R,T,b")))]
1071   "s390_match_ccmode(insn, CCSmode)"
1072   "@
1073    c<g>r\t%0,%1
1074    c<g>hi\t%0,%h1
1075    c<g>hsi\t%0,%h1
1076    c<g>fi\t%0,%1
1077    c<g>\t%0,%1
1078    c<y>\t%0,%1
1079    c<g>rl\t%0,%1"
1080   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1081    (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
1082    (set_attr "type" "*,*,*,*,*,*,larl")
1083    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1084
1085
1086 ; Compare (unsigned) instructions
1087
1088 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1089   [(set (reg CC_REGNUM)
1090         (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1091                                           "larl_operand" "X")))
1092                  (match_operand:SI 0 "register_operand" "d")))]
1093   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1094   "clhrl\t%0,%1"
1095   [(set_attr "op_type" "RIL")
1096    (set_attr "type"    "larl")
1097    (set_attr "z10prop" "z10_super")])
1098
1099 ; clhrl, clghrl
1100 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1101   [(set (reg CC_REGNUM)
1102         (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1103                                           "larl_operand" "X")))
1104                  (match_operand:GPR 0 "register_operand" "d")))]
1105   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1106   "cl<g>hrl\t%0,%1"
1107   [(set_attr "op_type" "RIL")
1108    (set_attr "type"    "larl")
1109    (set_attr "z10prop" "z10_super")])
1110
1111 (define_insn "*cmpdi_ccu_zero"
1112   [(set (reg CC_REGNUM)
1113         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1114                                                         "d,RT,b"))
1115                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1116   "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1117   "@
1118    clgfr\t%0,%1
1119    clgf\t%0,%1
1120    clgfrl\t%0,%1"
1121   [(set_attr "op_type"      "RRE,RXY,RIL")
1122    (set_attr "cpu_facility" "*,*,z10")
1123    (set_attr "type"         "*,*,larl")
1124    (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1125
1126 (define_insn "*cmpdi_ccu"
1127   [(set (reg CC_REGNUM)
1128         (compare (match_operand:DI 0 "nonimmediate_operand"
1129                                      "d, d,d,Q, d, Q,BQ")
1130                  (match_operand:DI 1 "general_operand"
1131                                      "d,Op,b,D,RT,BQ,Q")))]
1132   "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1133   "@
1134    clgr\t%0,%1
1135    clgfi\t%0,%1
1136    clgrl\t%0,%1
1137    clghsi\t%0,%x1
1138    clg\t%0,%1
1139    #
1140    #"
1141   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1142    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1143    (set_attr "type"         "*,*,larl,*,*,*,*")
1144    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1145
1146 (define_insn "*cmpsi_ccu"
1147   [(set (reg CC_REGNUM)
1148         (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1149                  (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
1150   "s390_match_ccmode (insn, CCUmode)"
1151   "@
1152    clr\t%0,%1
1153    clfi\t%0,%o1
1154    clrl\t%0,%1
1155    clfhsi\t%0,%x1
1156    cl\t%0,%1
1157    cly\t%0,%1
1158    #
1159    #"
1160   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1161    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1162    (set_attr "type"         "*,*,larl,*,*,*,*,*")
1163    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1164
1165 (define_insn "*cmphi_ccu"
1166   [(set (reg CC_REGNUM)
1167         (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1168                  (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
1169   "s390_match_ccmode (insn, CCUmode)
1170    && !register_operand (operands[1], HImode)"
1171   "@
1172    clm\t%0,3,%S1
1173    clmy\t%0,3,%S1
1174    clhhsi\t%0,%1
1175    #
1176    #"
1177   [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1178    (set_attr "cpu_facility" "*,*,z10,*,*")
1179    (set_attr "z10prop" "*,*,z10_super,*,*")])
1180
1181 (define_insn "*cmpqi_ccu"
1182   [(set (reg CC_REGNUM)
1183         (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1184                  (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1185   "s390_match_ccmode (insn, CCUmode)
1186    && !register_operand (operands[1], QImode)"
1187   "@
1188    clm\t%0,1,%S1
1189    clmy\t%0,1,%S1
1190    cli\t%S0,%b1
1191    cliy\t%S0,%b1
1192    #
1193    #"
1194   [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1195    (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1196
1197
1198 ; Block compare (CLC) instruction patterns.
1199
1200 (define_insn "*clc"
1201   [(set (reg CC_REGNUM)
1202         (compare (match_operand:BLK 0 "memory_operand" "Q")
1203                  (match_operand:BLK 1 "memory_operand" "Q")))
1204    (use (match_operand 2 "const_int_operand" "n"))]
1205   "s390_match_ccmode (insn, CCUmode)
1206    && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1207   "clc\t%O0(%2,%R0),%S1"
1208   [(set_attr "op_type" "SS")])
1209
1210 (define_split
1211   [(set (reg CC_REGNUM)
1212         (compare (match_operand 0 "memory_operand" "")
1213                  (match_operand 1 "memory_operand" "")))]
1214   "reload_completed
1215    && s390_match_ccmode (insn, CCUmode)
1216    && GET_MODE (operands[0]) == GET_MODE (operands[1])
1217    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1218   [(parallel
1219     [(set (match_dup 0) (match_dup 1))
1220      (use (match_dup 2))])]
1221 {
1222   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1223   operands[0] = adjust_address (operands[0], BLKmode, 0);
1224   operands[1] = adjust_address (operands[1], BLKmode, 0);
1225
1226   operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1227                                  operands[0], operands[1]);
1228   operands[0] = SET_DEST (PATTERN (curr_insn));
1229 })
1230
1231
1232 ; (TF|DF|SF|TD|DD|SD) instructions
1233
1234 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1235 (define_insn "*cmp<mode>_ccs_0"
1236   [(set (reg CC_REGNUM)
1237         (compare (match_operand:FP 0 "register_operand" "f")
1238                  (match_operand:FP 1 "const0_operand"   "")))]
1239   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1240   "lt<xde><bt>r\t%0,%0"
1241    [(set_attr "op_type" "RRE")
1242     (set_attr "type"  "fsimp<mode>")])
1243
1244 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1245 (define_insn "*cmp<mode>_ccs"
1246   [(set (reg CC_REGNUM)
1247         (compare (match_operand:FP 0 "register_operand" "f,f")
1248                  (match_operand:FP 1 "general_operand"  "f,R")))]
1249   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1250   "@
1251    c<xde><bt>r\t%0,%1
1252    c<xde>b\t%0,%1"
1253    [(set_attr "op_type" "RRE,RXE")
1254     (set_attr "type"  "fsimp<mode>")
1255     (set_attr "enabled" "*,<DSF>")])
1256
1257 ; wfcedbs, wfchdbs, wfchedbs
1258 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1259   [(set (reg:VFCMP CC_REGNUM)
1260         (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1261                        (match_operand:DF 1 "register_operand" "v")))
1262    (clobber (match_scratch:V2DI 2 "=v"))]
1263   "TARGET_Z13 && TARGET_HARD_FLOAT"
1264   "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1265   [(set_attr "op_type" "VRR")])
1266
1267 ; Compare and Branch instructions
1268
1269 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1270 ; The following instructions do a complementary access of their second
1271 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1272 (define_insn "*cmp_and_br_signed_<mode>"
1273   [(set (pc)
1274         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1275                         [(match_operand:GPR 1 "register_operand"  "d,d")
1276                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1277                       (label_ref (match_operand 3 "" ""))
1278                       (pc)))
1279    (clobber (reg:CC CC_REGNUM))]
1280   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1281 {
1282   if (get_attr_length (insn) == 6)
1283     return which_alternative ?
1284       "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1285   else
1286     return which_alternative ?
1287       "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1288 }
1289   [(set_attr "op_type" "RIE")
1290    (set_attr "type"    "branch")
1291    (set_attr "z10prop" "z10_super_c,z10_super")
1292    (set (attr "length")
1293         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1294                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1295                                                        ; 10 byte for cgr/jg
1296
1297 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1298 ; The following instructions do a complementary access of their second
1299 ; operand (z10 only): clrj, clgrj, clr, clgr
1300 (define_insn "*cmp_and_br_unsigned_<mode>"
1301   [(set (pc)
1302         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1303                         [(match_operand:GPR 1 "register_operand"  "d,d")
1304                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1305                       (label_ref (match_operand 3 "" ""))
1306                       (pc)))
1307    (clobber (reg:CC CC_REGNUM))]
1308   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1309 {
1310   if (get_attr_length (insn) == 6)
1311     return which_alternative ?
1312       "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1313   else
1314     return which_alternative ?
1315       "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1316 }
1317   [(set_attr "op_type" "RIE")
1318    (set_attr "type"    "branch")
1319    (set_attr "z10prop" "z10_super_c,z10_super")
1320    (set (attr "length")
1321         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1322                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1323                                                        ; 10 byte for clgr/jg
1324
1325 ; And now the same two patterns as above but with a negated CC mask.
1326
1327 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1328 ; The following instructions do a complementary access of their second
1329 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1330 (define_insn "*icmp_and_br_signed_<mode>"
1331   [(set (pc)
1332         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1333                         [(match_operand:GPR 1 "register_operand"  "d,d")
1334                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1335                       (pc)
1336                       (label_ref (match_operand 3 "" ""))))
1337    (clobber (reg:CC CC_REGNUM))]
1338   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1339 {
1340   if (get_attr_length (insn) == 6)
1341     return which_alternative ?
1342       "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1343   else
1344     return which_alternative ?
1345       "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1346 }
1347   [(set_attr "op_type" "RIE")
1348    (set_attr "type"    "branch")
1349    (set_attr "z10prop" "z10_super_c,z10_super")
1350    (set (attr "length")
1351         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1352                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1353                                                        ; 10 byte for cgr/jg
1354
1355 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1356 ; The following instructions do a complementary access of their second
1357 ; operand (z10 only): clrj, clgrj, clr, clgr
1358 (define_insn "*icmp_and_br_unsigned_<mode>"
1359   [(set (pc)
1360         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1361                         [(match_operand:GPR 1 "register_operand"  "d,d")
1362                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1363                       (pc)
1364                       (label_ref (match_operand 3 "" ""))))
1365    (clobber (reg:CC CC_REGNUM))]
1366   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1367 {
1368   if (get_attr_length (insn) == 6)
1369     return which_alternative ?
1370       "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1371   else
1372     return which_alternative ?
1373       "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1374 }
1375   [(set_attr "op_type" "RIE")
1376    (set_attr "type"    "branch")
1377    (set_attr "z10prop" "z10_super_c,z10_super")
1378    (set (attr "length")
1379         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1380                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1381                                                        ; 10 byte for clgr/jg
1382
1383 ;;
1384 ;;- Move instructions.
1385 ;;
1386
1387 ;
1388 ; movti instruction pattern(s).
1389 ;
1390
1391 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1392 ; for TImode (use double-int for the calculations)
1393 (define_insn "movti"
1394   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v,  v,  v,v,d, v,QR,   d,o")
1395         (match_operand:TI 1 "general_operand"      "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1396   "TARGET_ZARCH"
1397   "@
1398    lmg\t%0,%N0,%S1
1399    stmg\t%1,%N1,%S0
1400    vlr\t%v0,%v1
1401    vzero\t%v0
1402    vone\t%v0
1403    vlvgp\t%v0,%1,%N1
1404    #
1405    vl\t%v0,%1
1406    vst\t%v1,%0
1407    #
1408    #"
1409   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1410    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1411    (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1412
1413 (define_split
1414   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1415         (match_operand:TI 1 "general_operand" ""))]
1416   "TARGET_ZARCH && reload_completed
1417    && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1418   [(set (match_dup 2) (match_dup 4))
1419    (set (match_dup 3) (match_dup 5))]
1420 {
1421   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1422   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1423   operands[4] = operand_subword (operands[1], 0, 0, TImode);
1424   operands[5] = operand_subword (operands[1], 1, 0, TImode);
1425 })
1426
1427 (define_split
1428   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1429         (match_operand:TI 1 "general_operand" ""))]
1430   "TARGET_ZARCH && reload_completed
1431    && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1432   [(set (match_dup 2) (match_dup 4))
1433    (set (match_dup 3) (match_dup 5))]
1434 {
1435   operands[2] = operand_subword (operands[0], 1, 0, TImode);
1436   operands[3] = operand_subword (operands[0], 0, 0, TImode);
1437   operands[4] = operand_subword (operands[1], 1, 0, TImode);
1438   operands[5] = operand_subword (operands[1], 0, 0, TImode);
1439 })
1440
1441 ; Use part of the TImode target reg to perform the address
1442 ; calculation.  If the TImode value is supposed to be copied into a VR
1443 ; this splitter is not necessary.
1444 (define_split
1445   [(set (match_operand:TI 0 "register_operand" "")
1446         (match_operand:TI 1 "memory_operand" ""))]
1447   "TARGET_ZARCH && reload_completed
1448    && !VECTOR_REG_P (operands[0])
1449    && !s_operand (operands[1], VOIDmode)"
1450   [(set (match_dup 0) (match_dup 1))]
1451 {
1452   rtx addr = operand_subword (operands[0], 1, 0, TImode);
1453   addr = gen_lowpart (Pmode, addr);
1454   s390_load_address (addr, XEXP (operands[1], 0));
1455   operands[1] = replace_equiv_address (operands[1], addr);
1456 })
1457
1458
1459 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1460 ; For the higher order bits we do simply a DImode move while the
1461 ; second part is done via vec extract.  Both will end up as vlgvg.
1462 (define_split
1463   [(set (match_operand:TI 0 "register_operand" "")
1464         (match_operand:TI 1 "register_operand" ""))]
1465   "TARGET_VX && reload_completed
1466    && GENERAL_REG_P (operands[0])
1467    && VECTOR_REG_P (operands[1])"
1468   [(set (match_dup 2) (match_dup 4))
1469    (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1470                                  UNSPEC_VEC_EXTRACT))]
1471 {
1472   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1473   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1474   operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1475   operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1476 })
1477
1478 ;
1479 ; Patterns used for secondary reloads
1480 ;
1481
1482 ; z10 provides move instructions accepting larl memory operands.
1483 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1484 ; These patterns are also used for unaligned SI and DI accesses.
1485
1486 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1487   [(parallel [(match_operand:ALL 0 "memory_operand"   "")
1488               (match_operand:ALL 1 "register_operand" "=d")
1489               (match_operand:P   2 "register_operand" "=&a")])]
1490   "TARGET_Z10"
1491 {
1492   s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1493   DONE;
1494 })
1495
1496 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1497   [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1498               (match_operand:ALL 1 "memory_operand"   "")
1499               (match_operand:P   2 "register_operand" "=a")])]
1500   "TARGET_Z10"
1501 {
1502   s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1503   DONE;
1504 })
1505
1506 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1507   [(parallel [(match_operand:P 0 "register_operand" "=d")
1508               (match_operand:P 1 "larl_operand"     "")
1509               (match_operand:P 2 "register_operand" "=a")])]
1510   "TARGET_Z10"
1511 {
1512   s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1513   DONE;
1514 })
1515
1516 ; Handles loading a PLUS (load address) expression
1517
1518 (define_expand "reload<mode>_plus"
1519   [(parallel [(match_operand:P 0 "register_operand"  "=a")
1520               (match_operand:P 1 "s390_plus_operand" "")
1521               (match_operand:P 2 "register_operand"  "=&a")])]
1522   ""
1523 {
1524   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1525   DONE;
1526 })
1527
1528 ; Not all the indirect memory access instructions support the full
1529 ; format (long disp + index + base).  So whenever a move from/to such
1530 ; an address is required and the instruction cannot deal with it we do
1531 ; a load address into a scratch register first and use this as the new
1532 ; base register.
1533 ; This in particular is used for:
1534 ; - non-offsetable memory accesses for multiword moves
1535 ; - full vector reg moves with long displacements
1536
1537 (define_expand "reload<mode>_la_in"
1538   [(parallel [(match_operand 0   "register_operand" "")
1539               (match_operand 1   "" "")
1540               (match_operand:P 2 "register_operand" "=&a")])]
1541   ""
1542 {
1543   gcc_assert (MEM_P (operands[1]));
1544   s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1545   operands[1] = replace_equiv_address (operands[1], operands[2]);
1546   emit_move_insn (operands[0], operands[1]);
1547   DONE;
1548 })
1549
1550 (define_expand "reload<mode>_la_out"
1551   [(parallel [(match_operand   0 "" "")
1552               (match_operand   1 "register_operand" "")
1553               (match_operand:P 2 "register_operand" "=&a")])]
1554   ""
1555 {
1556   gcc_assert (MEM_P (operands[0]));
1557   s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1558   operands[0] = replace_equiv_address (operands[0], operands[2]);
1559   emit_move_insn (operands[0], operands[1]);
1560   DONE;
1561 })
1562
1563 (define_expand "reload<mode>_PIC_addr"
1564   [(parallel [(match_operand   0 "register_operand" "=d")
1565               (match_operand   1 "larl_operand"     "")
1566               (match_operand:P 2 "register_operand" "=a")])]
1567   ""
1568 {
1569   rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1570   emit_move_insn (operands[0], new_rtx);
1571 })
1572
1573 ;
1574 ; movdi instruction pattern(s).
1575 ;
1576
1577 (define_expand "movdi"
1578   [(set (match_operand:DI 0 "general_operand" "")
1579         (match_operand:DI 1 "general_operand" ""))]
1580   ""
1581 {
1582   /* Handle symbolic constants.  */
1583   if (TARGET_64BIT
1584       && (SYMBOLIC_CONST (operands[1])
1585           || (GET_CODE (operands[1]) == PLUS
1586               && XEXP (operands[1], 0) == pic_offset_table_rtx
1587               && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1588     emit_symbolic_move (operands);
1589 })
1590
1591 (define_insn "*movdi_larl"
1592   [(set (match_operand:DI 0 "register_operand" "=d")
1593         (match_operand:DI 1 "larl_operand" "X"))]
1594   "TARGET_64BIT
1595    && !FP_REG_P (operands[0])"
1596   "larl\t%0,%1"
1597    [(set_attr "op_type" "RIL")
1598     (set_attr "type"    "larl")
1599     (set_attr "z10prop" "z10_super_A1")])
1600
1601 (define_insn "*movdi_64"
1602   [(set (match_operand:DI 0 "nonimmediate_operand"
1603          "=d,    d,    d,    d,    d, d,    d,    d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1604         (match_operand:DI 1 "general_operand"
1605          " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f,  R,  T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1606   "TARGET_ZARCH"
1607   "@
1608    lghi\t%0,%h1
1609    llihh\t%0,%i1
1610    llihl\t%0,%i1
1611    llilh\t%0,%i1
1612    llill\t%0,%i1
1613    lgfi\t%0,%1
1614    llihf\t%0,%k1
1615    llilf\t%0,%k1
1616    ldgr\t%0,%1
1617    lgdr\t%0,%1
1618    lay\t%0,%a1
1619    lgrl\t%0,%1
1620    lgr\t%0,%1
1621    lg\t%0,%1
1622    stg\t%1,%0
1623    ldr\t%0,%1
1624    ld\t%0,%1
1625    ldy\t%0,%1
1626    std\t%1,%0
1627    stdy\t%1,%0
1628    stgrl\t%1,%0
1629    mvghi\t%0,%1
1630    #
1631    #
1632    stam\t%1,%N1,%S0
1633    lam\t%0,%N0,%S1
1634    vleig\t%v0,%h1,0
1635    vlr\t%v0,%v1
1636    vlvgg\t%v0,%1,0
1637    vlgvg\t%0,%v1,0
1638    vleg\t%v0,%1,0
1639    vsteg\t%v1,%0,0"
1640   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1641                         RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1642    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1643                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1644                      *,*,*,*,*,*,*")
1645    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1646                              z10,*,*,*,*,*,longdisp,*,longdisp,
1647                              z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1648    (set_attr "z10prop" "z10_fwd_A1,
1649                         z10_fwd_E1,
1650                         z10_fwd_E1,
1651                         z10_fwd_E1,
1652                         z10_fwd_E1,
1653                         z10_fwd_A1,
1654                         z10_fwd_E1,
1655                         z10_fwd_E1,
1656                         *,
1657                         *,
1658                         z10_fwd_A1,
1659                         z10_fwd_A3,
1660                         z10_fr_E1,
1661                         z10_fwd_A3,
1662                         z10_rec,
1663                         *,
1664                         *,
1665                         *,
1666                         *,
1667                         *,
1668                         z10_rec,
1669                         z10_super,
1670                         *,
1671                         *,
1672                         *,
1673                         *,*,*,*,*,*,*")
1674 ])
1675
1676 (define_split
1677   [(set (match_operand:DI 0 "register_operand" "")
1678         (match_operand:DI 1 "register_operand" ""))]
1679   "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1680   [(set (match_dup 2) (match_dup 3))
1681    (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1682    (set (strict_low_part (match_dup 2)) (match_dup 4))]
1683   "operands[2] = gen_lowpart (SImode, operands[0]);
1684    s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1685
1686 (define_split
1687   [(set (match_operand:DI 0 "register_operand" "")
1688         (match_operand:DI 1 "register_operand" ""))]
1689   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1690    && dead_or_set_p (insn, operands[1])"
1691   [(set (match_dup 3) (match_dup 2))
1692    (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1693    (set (match_dup 4) (match_dup 2))]
1694   "operands[2] = gen_lowpart (SImode, operands[1]);
1695    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1696
1697 (define_split
1698   [(set (match_operand:DI 0 "register_operand" "")
1699         (match_operand:DI 1 "register_operand" ""))]
1700   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1701    && !dead_or_set_p (insn, operands[1])"
1702   [(set (match_dup 3) (match_dup 2))
1703    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1704    (set (match_dup 4) (match_dup 2))
1705    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1706   "operands[2] = gen_lowpart (SImode, operands[1]);
1707    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1708
1709 (define_insn "*movdi_31"
1710   [(set (match_operand:DI 0 "nonimmediate_operand"
1711                             "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,d")
1712         (match_operand:DI 1 "general_operand"
1713                             " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,b"))]
1714   "!TARGET_ZARCH"
1715   "@
1716    lm\t%0,%N0,%S1
1717    lmy\t%0,%N0,%S1
1718    stm\t%1,%N1,%S0
1719    stmy\t%1,%N1,%S0
1720    #
1721    #
1722    ldr\t%0,%1
1723    ld\t%0,%1
1724    ldy\t%0,%1
1725    std\t%1,%0
1726    stdy\t%1,%0
1727    #"
1728   [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1729    (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1730    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1731
1732 ; For a load from a symbol ref we can use one of the target registers
1733 ; together with larl to load the address.
1734 (define_split
1735   [(set (match_operand:DI 0 "register_operand" "")
1736         (match_operand:DI 1 "memory_operand" ""))]
1737   "!TARGET_ZARCH && reload_completed && TARGET_Z10
1738    && larl_operand (XEXP (operands[1], 0), SImode)"
1739   [(set (match_dup 2) (match_dup 3))
1740    (set (match_dup 0) (match_dup 1))]
1741 {
1742   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1743   operands[3] = XEXP (operands[1], 0);
1744   operands[1] = replace_equiv_address (operands[1], operands[2]);
1745 })
1746
1747 (define_split
1748   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1749         (match_operand:DI 1 "general_operand" ""))]
1750   "!TARGET_ZARCH && reload_completed
1751    && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1752   [(set (match_dup 2) (match_dup 4))
1753    (set (match_dup 3) (match_dup 5))]
1754 {
1755   operands[2] = operand_subword (operands[0], 0, 0, DImode);
1756   operands[3] = operand_subword (operands[0], 1, 0, DImode);
1757   operands[4] = operand_subword (operands[1], 0, 0, DImode);
1758   operands[5] = operand_subword (operands[1], 1, 0, DImode);
1759 })
1760
1761 (define_split
1762   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1763         (match_operand:DI 1 "general_operand" ""))]
1764   "!TARGET_ZARCH && reload_completed
1765    && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1766   [(set (match_dup 2) (match_dup 4))
1767    (set (match_dup 3) (match_dup 5))]
1768 {
1769   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1770   operands[3] = operand_subword (operands[0], 0, 0, DImode);
1771   operands[4] = operand_subword (operands[1], 1, 0, DImode);
1772   operands[5] = operand_subword (operands[1], 0, 0, DImode);
1773 })
1774
1775 (define_split
1776   [(set (match_operand:DI 0 "register_operand" "")
1777         (match_operand:DI 1 "memory_operand" ""))]
1778   "!TARGET_ZARCH && reload_completed
1779    && !FP_REG_P (operands[0])
1780    && !s_operand (operands[1], VOIDmode)"
1781   [(set (match_dup 0) (match_dup 1))]
1782 {
1783   rtx addr = operand_subword (operands[0], 1, 0, DImode);
1784   s390_load_address (addr, XEXP (operands[1], 0));
1785   operands[1] = replace_equiv_address (operands[1], addr);
1786 })
1787
1788 (define_peephole2
1789   [(set (match_operand:DI 0 "register_operand" "")
1790         (mem:DI (match_operand 1 "address_operand" "")))]
1791   "TARGET_ZARCH
1792    && !FP_REG_P (operands[0])
1793    && GET_CODE (operands[1]) == SYMBOL_REF
1794    && CONSTANT_POOL_ADDRESS_P (operands[1])
1795    && get_pool_mode (operands[1]) == DImode
1796    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1797   [(set (match_dup 0) (match_dup 2))]
1798   "operands[2] = get_pool_constant (operands[1]);")
1799
1800 (define_insn "*la_64"
1801   [(set (match_operand:DI 0 "register_operand" "=d,d")
1802         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1803   "TARGET_64BIT"
1804   "@
1805    la\t%0,%a1
1806    lay\t%0,%a1"
1807   [(set_attr "op_type" "RX,RXY")
1808    (set_attr "type"    "la")
1809    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1810
1811 (define_peephole2
1812   [(parallel
1813     [(set (match_operand:DI 0 "register_operand" "")
1814           (match_operand:QI 1 "address_operand" ""))
1815      (clobber (reg:CC CC_REGNUM))])]
1816   "TARGET_64BIT
1817    && preferred_la_operand_p (operands[1], const0_rtx)"
1818   [(set (match_dup 0) (match_dup 1))]
1819   "")
1820
1821 (define_peephole2
1822   [(set (match_operand:DI 0 "register_operand" "")
1823         (match_operand:DI 1 "register_operand" ""))
1824    (parallel
1825     [(set (match_dup 0)
1826           (plus:DI (match_dup 0)
1827                    (match_operand:DI 2 "nonmemory_operand" "")))
1828      (clobber (reg:CC CC_REGNUM))])]
1829   "TARGET_64BIT
1830    && !reg_overlap_mentioned_p (operands[0], operands[2])
1831    && preferred_la_operand_p (operands[1], operands[2])"
1832   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1833   "")
1834
1835 ;
1836 ; movsi instruction pattern(s).
1837 ;
1838
1839 (define_expand "movsi"
1840   [(set (match_operand:SI 0 "general_operand" "")
1841         (match_operand:SI 1 "general_operand" ""))]
1842   ""
1843 {
1844   /* Handle symbolic constants.  */
1845   if (!TARGET_64BIT
1846       && (SYMBOLIC_CONST (operands[1])
1847           || (GET_CODE (operands[1]) == PLUS
1848               && XEXP (operands[1], 0) == pic_offset_table_rtx
1849               && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1850     emit_symbolic_move (operands);
1851 })
1852
1853 (define_insn "*movsi_larl"
1854   [(set (match_operand:SI 0 "register_operand" "=d")
1855         (match_operand:SI 1 "larl_operand" "X"))]
1856   "!TARGET_64BIT && TARGET_CPU_ZARCH
1857    && !FP_REG_P (operands[0])"
1858   "larl\t%0,%1"
1859    [(set_attr "op_type" "RIL")
1860     (set_attr "type"    "larl")
1861     (set_attr "z10prop" "z10_fwd_A1")])
1862
1863 (define_insn "*movsi_zarch"
1864   [(set (match_operand:SI 0 "nonimmediate_operand"
1865          "=d,    d,    d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1866         (match_operand:SI 1 "general_operand"
1867          " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f,  R,  R,  T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1868   "TARGET_ZARCH"
1869   "@
1870    lhi\t%0,%h1
1871    llilh\t%0,%i1
1872    llill\t%0,%i1
1873    iilf\t%0,%o1
1874    lay\t%0,%a1
1875    lrl\t%0,%1
1876    lr\t%0,%1
1877    l\t%0,%1
1878    ly\t%0,%1
1879    st\t%1,%0
1880    sty\t%1,%0
1881    lder\t%0,%1
1882    ler\t%0,%1
1883    lde\t%0,%1
1884    le\t%0,%1
1885    ley\t%0,%1
1886    ste\t%1,%0
1887    stey\t%1,%0
1888    ear\t%0,%1
1889    sar\t%0,%1
1890    stam\t%1,%1,%S0
1891    strl\t%1,%0
1892    mvhi\t%0,%1
1893    lam\t%0,%0,%S1
1894    vleif\t%v0,%h1,0
1895    vlr\t%v0,%v1
1896    vlvgf\t%v0,%1,0
1897    vlgvf\t%0,%v1,0
1898    vlef\t%v0,%1,0
1899    vstef\t%v1,%0,0"
1900   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1901                         RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1902    (set_attr "type" "*,
1903                      *,
1904                      *,
1905                      *,
1906                      la,
1907                      larl,
1908                      lr,
1909                      load,
1910                      load,
1911                      store,
1912                      store,
1913                      floadsf,
1914                      floadsf,
1915                      floadsf,
1916                      floadsf,
1917                      floadsf,
1918                      fstoresf,
1919                      fstoresf,
1920                      *,
1921                      *,
1922                      *,
1923                      larl,
1924                      *,
1925                      *,*,*,*,*,*,*")
1926    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1927                              vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1928    (set_attr "z10prop" "z10_fwd_A1,
1929                         z10_fwd_E1,
1930                         z10_fwd_E1,
1931                         z10_fwd_A1,
1932                         z10_fwd_A1,
1933                         z10_fwd_A3,
1934                         z10_fr_E1,
1935                         z10_fwd_A3,
1936                         z10_fwd_A3,
1937                         z10_rec,
1938                         z10_rec,
1939                         *,
1940                         *,
1941                         *,
1942                         *,
1943                         *,
1944                         *,
1945                         *,
1946                         z10_super_E1,
1947                         z10_super,
1948                         *,
1949                         z10_rec,
1950                         z10_super,
1951                         *,*,*,*,*,*,*")])
1952
1953 (define_insn "*movsi_esa"
1954   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1955         (match_operand:SI 1 "general_operand"       "K,d,R,d, *f, *f,  R,  R,*f,t,d,t,Q"))]
1956   "!TARGET_ZARCH"
1957   "@
1958    lhi\t%0,%h1
1959    lr\t%0,%1
1960    l\t%0,%1
1961    st\t%1,%0
1962    lder\t%0,%1
1963    ler\t%0,%1
1964    lde\t%0,%1
1965    le\t%0,%1
1966    ste\t%1,%0
1967    ear\t%0,%1
1968    sar\t%0,%1
1969    stam\t%1,%1,%S0
1970    lam\t%0,%0,%S1"
1971   [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1972    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1973    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1974                         z10_super,*,*")
1975    (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1976 ])
1977
1978 (define_peephole2
1979   [(set (match_operand:SI 0 "register_operand" "")
1980         (mem:SI (match_operand 1 "address_operand" "")))]
1981   "!FP_REG_P (operands[0])
1982    && GET_CODE (operands[1]) == SYMBOL_REF
1983    && CONSTANT_POOL_ADDRESS_P (operands[1])
1984    && get_pool_mode (operands[1]) == SImode
1985    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1986   [(set (match_dup 0) (match_dup 2))]
1987   "operands[2] = get_pool_constant (operands[1]);")
1988
1989 (define_insn "*la_31"
1990   [(set (match_operand:SI 0 "register_operand" "=d,d")
1991         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1992   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1993   "@
1994    la\t%0,%a1
1995    lay\t%0,%a1"
1996   [(set_attr "op_type"  "RX,RXY")
1997    (set_attr "type"     "la")
1998    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1999
2000 (define_peephole2
2001   [(parallel
2002     [(set (match_operand:SI 0 "register_operand" "")
2003           (match_operand:QI 1 "address_operand" ""))
2004      (clobber (reg:CC CC_REGNUM))])]
2005   "!TARGET_64BIT
2006    && preferred_la_operand_p (operands[1], const0_rtx)"
2007   [(set (match_dup 0) (match_dup 1))]
2008   "")
2009
2010 (define_peephole2
2011   [(set (match_operand:SI 0 "register_operand" "")
2012         (match_operand:SI 1 "register_operand" ""))
2013    (parallel
2014     [(set (match_dup 0)
2015           (plus:SI (match_dup 0)
2016                    (match_operand:SI 2 "nonmemory_operand" "")))
2017      (clobber (reg:CC CC_REGNUM))])]
2018   "!TARGET_64BIT
2019    && !reg_overlap_mentioned_p (operands[0], operands[2])
2020    && preferred_la_operand_p (operands[1], operands[2])"
2021   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2022   "")
2023
2024 (define_insn "*la_31_and"
2025   [(set (match_operand:SI 0 "register_operand" "=d,d")
2026         (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
2027                 (const_int 2147483647)))]
2028   "!TARGET_64BIT"
2029   "@
2030    la\t%0,%a1
2031    lay\t%0,%a1"
2032   [(set_attr "op_type"  "RX,RXY")
2033    (set_attr "type"     "la")
2034    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2035
2036 (define_insn_and_split "*la_31_and_cc"
2037   [(set (match_operand:SI 0 "register_operand" "=d")
2038         (and:SI (match_operand:QI 1 "address_operand" "p")
2039                 (const_int 2147483647)))
2040    (clobber (reg:CC CC_REGNUM))]
2041   "!TARGET_64BIT"
2042   "#"
2043   "&& reload_completed"
2044   [(set (match_dup 0)
2045         (and:SI (match_dup 1) (const_int 2147483647)))]
2046   ""
2047   [(set_attr "op_type"  "RX")
2048    (set_attr "type"     "la")])
2049
2050 (define_insn "force_la_31"
2051   [(set (match_operand:SI 0 "register_operand" "=d,d")
2052         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
2053    (use (const_int 0))]
2054   "!TARGET_64BIT"
2055   "@
2056    la\t%0,%a1
2057    lay\t%0,%a1"
2058   [(set_attr "op_type"  "RX")
2059    (set_attr "type"     "la")
2060    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2061
2062 ;
2063 ; movhi instruction pattern(s).
2064 ;
2065
2066 (define_expand "movhi"
2067   [(set (match_operand:HI 0 "nonimmediate_operand" "")
2068         (match_operand:HI 1 "general_operand" ""))]
2069   ""
2070 {
2071   /* Make it explicit that loading a register from memory
2072      always sign-extends (at least) to SImode.  */
2073   if (optimize && can_create_pseudo_p ()
2074       && register_operand (operands[0], VOIDmode)
2075       && GET_CODE (operands[1]) == MEM)
2076     {
2077       rtx tmp = gen_reg_rtx (SImode);
2078       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2079       emit_insn (gen_rtx_SET (tmp, ext));
2080       operands[1] = gen_lowpart (HImode, tmp);
2081     }
2082 })
2083
2084 (define_insn "*movhi"
2085   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
2086         (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
2087   ""
2088   "@
2089    lr\t%0,%1
2090    lhi\t%0,%h1
2091    lh\t%0,%1
2092    lhy\t%0,%1
2093    lhrl\t%0,%1
2094    sth\t%1,%0
2095    sthy\t%1,%0
2096    sthrl\t%1,%0
2097    mvhhi\t%0,%1
2098    vleih\t%v0,%h1,0
2099    vlr\t%v0,%v1
2100    vlvgh\t%v0,%1,0
2101    vlgvh\t%0,%v1,0
2102    vleh\t%v0,%1,0
2103    vsteh\t%v1,%0,0"
2104   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2105    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2106    (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
2107    (set_attr "z10prop" "z10_fr_E1,
2108                        z10_fwd_A1,
2109                        z10_super_E1,
2110                        z10_super_E1,
2111                        z10_super_E1,
2112                        z10_rec,
2113                        z10_rec,
2114                        z10_rec,
2115                        z10_super,*,*,*,*,*,*")])
2116
2117 (define_peephole2
2118   [(set (match_operand:HI 0 "register_operand" "")
2119         (mem:HI (match_operand 1 "address_operand" "")))]
2120   "GET_CODE (operands[1]) == SYMBOL_REF
2121    && CONSTANT_POOL_ADDRESS_P (operands[1])
2122    && get_pool_mode (operands[1]) == HImode
2123    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2124   [(set (match_dup 0) (match_dup 2))]
2125   "operands[2] = get_pool_constant (operands[1]);")
2126
2127 ;
2128 ; movqi instruction pattern(s).
2129 ;
2130
2131 (define_expand "movqi"
2132   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2133         (match_operand:QI 1 "general_operand" ""))]
2134   ""
2135 {
2136   /* On z/Architecture, zero-extending from memory to register
2137      is just as fast as a QImode load.  */
2138   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2139       && register_operand (operands[0], VOIDmode)
2140       && GET_CODE (operands[1]) == MEM)
2141     {
2142       rtx tmp = gen_reg_rtx (DImode);
2143       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2144       emit_insn (gen_rtx_SET (tmp, ext));
2145       operands[1] = gen_lowpart (QImode, tmp);
2146     }
2147 })
2148
2149 (define_insn "*movqi"
2150   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2151         (match_operand:QI 1 "general_operand"      " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2152   ""
2153   "@
2154    lr\t%0,%1
2155    lhi\t%0,%b1
2156    ic\t%0,%1
2157    icy\t%0,%1
2158    stc\t%1,%0
2159    stcy\t%1,%0
2160    mvi\t%S0,%b1
2161    mviy\t%S0,%b1
2162    #
2163    vleib\t%v0,%b1,0
2164    vlr\t%v0,%v1
2165    vlvgb\t%v0,%1,0
2166    vlgvb\t%0,%v1,0
2167    vleb\t%v0,%1,0
2168    vsteb\t%v1,%0,0"
2169   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2170    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2171    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2172    (set_attr "z10prop" "z10_fr_E1,
2173                         z10_fwd_A1,
2174                         z10_super_E1,
2175                         z10_super_E1,
2176                         z10_rec,
2177                         z10_rec,
2178                         z10_super,
2179                         z10_super,
2180                         *,*,*,*,*,*,*")])
2181
2182 (define_peephole2
2183   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2184         (mem:QI (match_operand 1 "address_operand" "")))]
2185   "GET_CODE (operands[1]) == SYMBOL_REF
2186    && CONSTANT_POOL_ADDRESS_P (operands[1])
2187    && get_pool_mode (operands[1]) == QImode
2188    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2189   [(set (match_dup 0) (match_dup 2))]
2190   "operands[2] = get_pool_constant (operands[1]);")
2191
2192 ;
2193 ; movstrictqi instruction pattern(s).
2194 ;
2195
2196 (define_insn "*movstrictqi"
2197   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2198                          (match_operand:QI 1 "memory_operand" "R,T"))]
2199   ""
2200   "@
2201    ic\t%0,%1
2202    icy\t%0,%1"
2203   [(set_attr "op_type"  "RX,RXY")
2204    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2205
2206 ;
2207 ; movstricthi instruction pattern(s).
2208 ;
2209
2210 (define_insn "*movstricthi"
2211   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2212                          (match_operand:HI 1 "memory_operand" "Q,S"))
2213    (clobber (reg:CC CC_REGNUM))]
2214   ""
2215   "@
2216    icm\t%0,3,%S1
2217    icmy\t%0,3,%S1"
2218   [(set_attr "op_type" "RS,RSY")
2219    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2220
2221 ;
2222 ; movstrictsi instruction pattern(s).
2223 ;
2224
2225 (define_insn "movstrictsi"
2226   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2227                          (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2228   "TARGET_ZARCH"
2229   "@
2230    lr\t%0,%1
2231    l\t%0,%1
2232    ly\t%0,%1
2233    ear\t%0,%1"
2234   [(set_attr "op_type" "RR,RX,RXY,RRE")
2235    (set_attr "type" "lr,load,load,*")
2236    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2237
2238 ;
2239 ; mov(tf|td) instruction pattern(s).
2240 ;
2241
2242 (define_expand "mov<mode>"
2243   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2244         (match_operand:TD_TF 1 "general_operand"      ""))]
2245   ""
2246   "")
2247
2248 (define_insn "*mov<mode>_64"
2249   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS,  d,o")
2250         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d"))]
2251   "TARGET_ZARCH"
2252   "@
2253    lzxr\t%0
2254    lxr\t%0,%1
2255    #
2256    #
2257    lmg\t%0,%N0,%S1
2258    stmg\t%1,%N1,%S0
2259    #
2260    #"
2261   [(set_attr "op_type"      "RRE,RRE,*,*,RSY,RSY,*,*")
2262    (set_attr "type"         "fsimptf,fsimptf,*,*,lm,stm,*,*")
2263    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2264
2265 (define_insn "*mov<mode>_31"
2266   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2267         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
2268   "!TARGET_ZARCH"
2269   "@
2270    lzxr\t%0
2271    lxr\t%0,%1
2272    #
2273    #"
2274   [(set_attr "op_type"      "RRE,RRE,*,*")
2275    (set_attr "type"         "fsimptf,fsimptf,*,*")
2276    (set_attr "cpu_facility" "z196,*,*,*")])
2277
2278 ; TFmode in GPRs splitters
2279
2280 (define_split
2281   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2282         (match_operand:TD_TF 1 "general_operand"      ""))]
2283   "TARGET_ZARCH && reload_completed
2284    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2285   [(set (match_dup 2) (match_dup 4))
2286    (set (match_dup 3) (match_dup 5))]
2287 {
2288   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2289   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2290   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2291   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2292 })
2293
2294 (define_split
2295   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2296         (match_operand:TD_TF 1 "general_operand"      ""))]
2297   "TARGET_ZARCH && reload_completed
2298    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2299   [(set (match_dup 2) (match_dup 4))
2300    (set (match_dup 3) (match_dup 5))]
2301 {
2302   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2303   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2304   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2305   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2306 })
2307
2308 (define_split
2309   [(set (match_operand:TD_TF 0 "register_operand" "")
2310         (match_operand:TD_TF 1 "memory_operand"   ""))]
2311   "TARGET_ZARCH && reload_completed
2312    && GENERAL_REG_P (operands[0])
2313    && !s_operand (operands[1], VOIDmode)"
2314   [(set (match_dup 0) (match_dup 1))]
2315 {
2316   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2317   addr = gen_lowpart (Pmode, addr);
2318   s390_load_address (addr, XEXP (operands[1], 0));
2319   operands[1] = replace_equiv_address (operands[1], addr);
2320 })
2321
2322 ; TFmode in BFPs splitters
2323
2324 (define_split
2325   [(set (match_operand:TD_TF 0 "register_operand" "")
2326         (match_operand:TD_TF 1 "memory_operand" ""))]
2327   "reload_completed && offsettable_memref_p (operands[1])
2328    && FP_REG_P (operands[0])"
2329   [(set (match_dup 2) (match_dup 4))
2330    (set (match_dup 3) (match_dup 5))]
2331 {
2332   operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2333                                      <MODE>mode, 0);
2334   operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2335                                      <MODE>mode, 8);
2336   operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2337   operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2338 })
2339
2340 (define_split
2341   [(set (match_operand:TD_TF 0 "memory_operand" "")
2342         (match_operand:TD_TF 1 "register_operand" ""))]
2343   "reload_completed && offsettable_memref_p (operands[0])
2344    && FP_REG_P (operands[1])"
2345   [(set (match_dup 2) (match_dup 4))
2346    (set (match_dup 3) (match_dup 5))]
2347 {
2348   operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2349   operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2350   operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2351                                      <MODE>mode, 0);
2352   operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2353                                      <MODE>mode, 8);
2354 })
2355
2356 ;
2357 ; mov(df|dd) instruction pattern(s).
2358 ;
2359
2360 (define_expand "mov<mode>"
2361   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2362         (match_operand:DD_DF 1 "general_operand"  ""))]
2363   ""
2364   "")
2365
2366 (define_insn "*mov<mode>_64dfp"
2367   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2368                                "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2369         (match_operand:DD_DF 1 "general_operand"
2370                                " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2371   "TARGET_DFP"
2372   "@
2373    lzdr\t%0
2374    ldr\t%0,%1
2375    ldgr\t%0,%1
2376    lgdr\t%0,%1
2377    ld\t%0,%1
2378    ldy\t%0,%1
2379    std\t%1,%0
2380    stdy\t%1,%0
2381    lghi\t%0,0
2382    lgr\t%0,%1
2383    lgrl\t%0,%1
2384    lg\t%0,%1
2385    stgrl\t%1,%0
2386    stg\t%1,%0
2387    vlr\t%v0,%v1
2388    vlvgg\t%v0,%1,0
2389    vlgvg\t%0,%v1,0
2390    vleg\t%0,%1,0
2391    vsteg\t%1,%0,0"
2392   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2393    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2394                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2395    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2396    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2397
2398 (define_insn "*mov<mode>_64"
2399   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2400         (match_operand:DD_DF 1 "general_operand"      " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2401   "TARGET_ZARCH"
2402   "@
2403    lzdr\t%0
2404    ldr\t%0,%1
2405    ld\t%0,%1
2406    ldy\t%0,%1
2407    std\t%1,%0
2408    stdy\t%1,%0
2409    lghi\t%0,0
2410    lgr\t%0,%1
2411    lgrl\t%0,%1
2412    lg\t%0,%1
2413    stgrl\t%1,%0
2414    stg\t%1,%0
2415    vlr\t%v0,%v1
2416    vleg\t%v0,%1,0
2417    vsteg\t%v1,%0,0"
2418   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2419    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2420                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2421    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2422    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2423
2424 (define_insn "*mov<mode>_31"
2425   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2426                                "=f,f,f,f,R,T,d,d,Q,S,   d,o")
2427         (match_operand:DD_DF 1 "general_operand"
2428                                " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2429   "!TARGET_ZARCH"
2430   "@
2431    lzdr\t%0
2432    ldr\t%0,%1
2433    ld\t%0,%1
2434    ldy\t%0,%1
2435    std\t%1,%0
2436    stdy\t%1,%0
2437    lm\t%0,%N0,%S1
2438    lmy\t%0,%N0,%S1
2439    stm\t%1,%N1,%S0
2440    stmy\t%1,%N1,%S0
2441    #
2442    #"
2443   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2444    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2445                         fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2446    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2447
2448 (define_split
2449   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2450         (match_operand:DD_DF 1 "general_operand" ""))]
2451   "!TARGET_ZARCH && reload_completed
2452    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2453   [(set (match_dup 2) (match_dup 4))
2454    (set (match_dup 3) (match_dup 5))]
2455 {
2456   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2457   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2458   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2459   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2460 })
2461
2462 (define_split
2463   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2464         (match_operand:DD_DF 1 "general_operand" ""))]
2465   "!TARGET_ZARCH && reload_completed
2466    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2467   [(set (match_dup 2) (match_dup 4))
2468    (set (match_dup 3) (match_dup 5))]
2469 {
2470   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2471   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2472   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2473   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2474 })
2475
2476 (define_split
2477   [(set (match_operand:DD_DF 0 "register_operand" "")
2478         (match_operand:DD_DF 1 "memory_operand" ""))]
2479   "!TARGET_ZARCH && reload_completed
2480    && !FP_REG_P (operands[0])
2481    && !s_operand (operands[1], VOIDmode)"
2482   [(set (match_dup 0) (match_dup 1))]
2483 {
2484   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2485   s390_load_address (addr, XEXP (operands[1], 0));
2486   operands[1] = replace_equiv_address (operands[1], addr);
2487 })
2488
2489 ;
2490 ; mov(sf|sd) instruction pattern(s).
2491 ;
2492
2493 (define_insn "mov<mode>"
2494   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2495                                "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2496         (match_operand:SD_SF 1 "general_operand"
2497                                " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2498   ""
2499   "@
2500    lzer\t%0
2501    lder\t%0,%1
2502    ler\t%0,%1
2503    lde\t%0,%1
2504    le\t%0,%1
2505    ley\t%0,%1
2506    ste\t%1,%0
2507    stey\t%1,%0
2508    lhi\t%0,0
2509    lr\t%0,%1
2510    lrl\t%0,%1
2511    l\t%0,%1
2512    ly\t%0,%1
2513    strl\t%1,%0
2514    st\t%1,%0
2515    sty\t%1,%0
2516    vlr\t%v0,%v1
2517    vleif\t%v0,0
2518    vlvgf\t%v0,%1,0
2519    vlgvf\t%0,%v1,0
2520    vleg\t%0,%1,0
2521    vsteg\t%1,%0,0"
2522   [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2523    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2524                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2525    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2526    (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2527
2528 ;
2529 ; movcc instruction pattern
2530 ;
2531
2532 (define_insn "movcc"
2533   [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2534         (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2535   ""
2536   "@
2537    lr\t%0,%1
2538    tmh\t%1,12288
2539    ipm\t%0
2540    l\t%0,%1
2541    ly\t%0,%1
2542    st\t%1,%0
2543    sty\t%1,%0"
2544   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2545    (set_attr "type" "lr,*,*,load,load,store,store")
2546    (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2547    (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2548
2549 ;
2550 ; Block move (MVC) patterns.
2551 ;
2552
2553 (define_insn "*mvc"
2554   [(set (match_operand:BLK 0 "memory_operand" "=Q")
2555         (match_operand:BLK 1 "memory_operand" "Q"))
2556    (use (match_operand 2 "const_int_operand" "n"))]
2557   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2558   "mvc\t%O0(%2,%R0),%S1"
2559   [(set_attr "op_type" "SS")])
2560
2561 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2562 ; order to have it implemented with mvc.
2563
2564 (define_split
2565   [(set (match_operand:QI 0 "memory_operand" "")
2566         (match_operand:QI 1 "memory_operand" ""))]
2567   "reload_completed"
2568   [(parallel
2569     [(set (match_dup 0) (match_dup 1))
2570      (use (const_int 1))])]
2571 {
2572   operands[0] = adjust_address (operands[0], BLKmode, 0);
2573   operands[1] = adjust_address (operands[1], BLKmode, 0);
2574 })
2575
2576
2577 (define_peephole2
2578   [(parallel
2579     [(set (match_operand:BLK 0 "memory_operand" "")
2580           (match_operand:BLK 1 "memory_operand" ""))
2581      (use (match_operand 2 "const_int_operand" ""))])
2582    (parallel
2583     [(set (match_operand:BLK 3 "memory_operand" "")
2584           (match_operand:BLK 4 "memory_operand" ""))
2585      (use (match_operand 5 "const_int_operand" ""))])]
2586   "s390_offset_p (operands[0], operands[3], operands[2])
2587    && s390_offset_p (operands[1], operands[4], operands[2])
2588    && !s390_overlap_p (operands[0], operands[1],
2589                        INTVAL (operands[2]) + INTVAL (operands[5]))
2590    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2591   [(parallel
2592     [(set (match_dup 6) (match_dup 7))
2593      (use (match_dup 8))])]
2594   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2595    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2596    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2597
2598
2599 ;
2600 ; load_multiple pattern(s).
2601 ;
2602 ; ??? Due to reload problems with replacing registers inside match_parallel
2603 ; we currently support load_multiple/store_multiple only after reload.
2604 ;
2605
2606 (define_expand "load_multiple"
2607   [(match_par_dup 3 [(set (match_operand 0 "" "")
2608                           (match_operand 1 "" ""))
2609                      (use (match_operand 2 "" ""))])]
2610   "reload_completed"
2611 {
2612   machine_mode mode;
2613   int regno;
2614   int count;
2615   rtx from;
2616   int i, off;
2617
2618   /* Support only loading a constant number of fixed-point registers from
2619      memory and only bother with this if more than two */
2620   if (GET_CODE (operands[2]) != CONST_INT
2621       || INTVAL (operands[2]) < 2
2622       || INTVAL (operands[2]) > 16
2623       || GET_CODE (operands[1]) != MEM
2624       || GET_CODE (operands[0]) != REG
2625       || REGNO (operands[0]) >= 16)
2626     FAIL;
2627
2628   count = INTVAL (operands[2]);
2629   regno = REGNO (operands[0]);
2630   mode = GET_MODE (operands[0]);
2631   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2632     FAIL;
2633
2634   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2635   if (!can_create_pseudo_p ())
2636     {
2637       if (GET_CODE (XEXP (operands[1], 0)) == REG)
2638         {
2639           from = XEXP (operands[1], 0);
2640           off = 0;
2641         }
2642       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2643                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2644                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2645         {
2646           from = XEXP (XEXP (operands[1], 0), 0);
2647           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2648         }
2649       else
2650         FAIL;
2651     }
2652   else
2653     {
2654       from = force_reg (Pmode, XEXP (operands[1], 0));
2655       off = 0;
2656     }
2657
2658   for (i = 0; i < count; i++)
2659     XVECEXP (operands[3], 0, i)
2660       = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2661                      change_address (operands[1], mode,
2662                        plus_constant (Pmode, from,
2663                                       off + i * GET_MODE_SIZE (mode))));
2664 })
2665
2666 (define_insn "*load_multiple_di"
2667   [(match_parallel 0 "load_multiple_operation"
2668                    [(set (match_operand:DI 1 "register_operand" "=r")
2669                          (match_operand:DI 2 "s_operand" "QS"))])]
2670   "reload_completed && TARGET_ZARCH"
2671 {
2672   int words = XVECLEN (operands[0], 0);
2673   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2674   return "lmg\t%1,%0,%S2";
2675 }
2676    [(set_attr "op_type" "RSY")
2677     (set_attr "type"    "lm")])
2678
2679 (define_insn "*load_multiple_si"
2680   [(match_parallel 0 "load_multiple_operation"
2681                    [(set (match_operand:SI 1 "register_operand" "=r,r")
2682                          (match_operand:SI 2 "s_operand" "Q,S"))])]
2683   "reload_completed"
2684 {
2685   int words = XVECLEN (operands[0], 0);
2686   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2687   return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2688 }
2689    [(set_attr "op_type" "RS,RSY")
2690     (set_attr "type"    "lm")])
2691
2692 ;
2693 ; store multiple pattern(s).
2694 ;
2695
2696 (define_expand "store_multiple"
2697   [(match_par_dup 3 [(set (match_operand 0 "" "")
2698                           (match_operand 1 "" ""))
2699                      (use (match_operand 2 "" ""))])]
2700   "reload_completed"
2701 {
2702   machine_mode mode;
2703   int regno;
2704   int count;
2705   rtx to;
2706   int i, off;
2707
2708   /* Support only storing a constant number of fixed-point registers to
2709      memory and only bother with this if more than two.  */
2710   if (GET_CODE (operands[2]) != CONST_INT
2711       || INTVAL (operands[2]) < 2
2712       || INTVAL (operands[2]) > 16
2713       || GET_CODE (operands[0]) != MEM
2714       || GET_CODE (operands[1]) != REG
2715       || REGNO (operands[1]) >= 16)
2716     FAIL;
2717
2718   count = INTVAL (operands[2]);
2719   regno = REGNO (operands[1]);
2720   mode = GET_MODE (operands[1]);
2721   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2722     FAIL;
2723
2724   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2725
2726   if (!can_create_pseudo_p ())
2727     {
2728       if (GET_CODE (XEXP (operands[0], 0)) == REG)
2729         {
2730           to = XEXP (operands[0], 0);
2731           off = 0;
2732         }
2733       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2734                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2735                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2736         {
2737           to = XEXP (XEXP (operands[0], 0), 0);
2738           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2739         }
2740       else
2741         FAIL;
2742     }
2743   else
2744     {
2745       to = force_reg (Pmode, XEXP (operands[0], 0));
2746       off = 0;
2747     }
2748
2749   for (i = 0; i < count; i++)
2750     XVECEXP (operands[3], 0, i)
2751       = gen_rtx_SET (change_address (operands[0], mode,
2752                        plus_constant (Pmode, to,
2753                                       off + i * GET_MODE_SIZE (mode))),
2754                      gen_rtx_REG (mode, regno + i));
2755 })
2756
2757 (define_insn "*store_multiple_di"
2758   [(match_parallel 0 "store_multiple_operation"
2759                    [(set (match_operand:DI 1 "s_operand" "=QS")
2760                          (match_operand:DI 2 "register_operand" "r"))])]
2761   "reload_completed && TARGET_ZARCH"
2762 {
2763   int words = XVECLEN (operands[0], 0);
2764   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2765   return "stmg\t%2,%0,%S1";
2766 }
2767    [(set_attr "op_type" "RSY")
2768     (set_attr "type"    "stm")])
2769
2770
2771 (define_insn "*store_multiple_si"
2772   [(match_parallel 0 "store_multiple_operation"
2773                    [(set (match_operand:SI 1 "s_operand" "=Q,S")
2774                          (match_operand:SI 2 "register_operand" "r,r"))])]
2775   "reload_completed"
2776 {
2777   int words = XVECLEN (operands[0], 0);
2778   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2779   return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2780 }
2781    [(set_attr "op_type" "RS,RSY")
2782     (set_attr "type"    "stm")])
2783
2784 ;;
2785 ;; String instructions.
2786 ;;
2787
2788 (define_insn "*execute_rl"
2789   [(match_parallel 0 "execute_operation"
2790     [(unspec [(match_operand 1    "register_operand" "a")
2791               (match_operand 2    "" "")
2792               (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2793   "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2794    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2795   "exrl\t%1,%3"
2796   [(set_attr "op_type" "RIL")
2797    (set_attr "type"    "cs")])
2798
2799 (define_insn "*execute"
2800   [(match_parallel 0 "execute_operation"
2801     [(unspec [(match_operand 1 "register_operand" "a")
2802               (match_operand:BLK 2 "memory_operand" "R")
2803               (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2804   "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2805    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2806   "ex\t%1,%2"
2807   [(set_attr "op_type" "RX")
2808    (set_attr "type" "cs")])
2809
2810
2811 ;
2812 ; strlenM instruction pattern(s).
2813 ;
2814
2815 (define_expand "strlen<mode>"
2816   [(match_operand:P   0 "register_operand" "")  ; result
2817    (match_operand:BLK 1 "memory_operand" "")    ; input string
2818    (match_operand:SI  2 "immediate_operand" "") ; search character
2819    (match_operand:SI  3 "immediate_operand" "")] ; known alignment
2820   ""
2821 {
2822   if (!TARGET_VX || operands[2] != const0_rtx)
2823     emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2824                                       operands[2], operands[3]));
2825   else
2826     s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2827
2828   DONE;
2829 })
2830
2831 (define_expand "strlen_srst<mode>"
2832   [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2833    (parallel
2834     [(set (match_dup 4)
2835           (unspec:P [(const_int 0)
2836                       (match_operand:BLK 1 "memory_operand" "")
2837                       (reg:SI 0)
2838                       (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2839      (clobber (scratch:P))
2840      (clobber (reg:CC CC_REGNUM))])
2841    (parallel
2842     [(set (match_operand:P 0 "register_operand" "")
2843           (minus:P (match_dup 4) (match_dup 5)))
2844      (clobber (reg:CC CC_REGNUM))])]
2845   ""
2846 {
2847   operands[4] = gen_reg_rtx (Pmode);
2848   operands[5] = gen_reg_rtx (Pmode);
2849   emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2850   operands[1] = replace_equiv_address (operands[1], operands[5]);
2851 })
2852
2853 (define_insn "*strlen<mode>"
2854   [(set (match_operand:P 0 "register_operand" "=a")
2855         (unspec:P [(match_operand:P 2 "general_operand" "0")
2856                     (mem:BLK (match_operand:P 3 "register_operand" "1"))
2857                     (reg:SI 0)
2858                     (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2859    (clobber (match_scratch:P 1 "=a"))
2860    (clobber (reg:CC CC_REGNUM))]
2861   ""
2862   "srst\t%0,%1\;jo\t.-4"
2863   [(set_attr "length" "8")
2864    (set_attr "type" "vs")])
2865
2866 ;
2867 ; cmpstrM instruction pattern(s).
2868 ;
2869
2870 (define_expand "cmpstrsi"
2871   [(set (reg:SI 0) (const_int 0))
2872    (parallel
2873     [(clobber (match_operand 3 "" ""))
2874      (clobber (match_dup 4))
2875      (set (reg:CCU CC_REGNUM)
2876           (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2877                        (match_operand:BLK 2 "memory_operand" "")))
2878      (use (reg:SI 0))])
2879    (parallel
2880     [(set (match_operand:SI 0 "register_operand" "=d")
2881           (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2882      (clobber (reg:CC CC_REGNUM))])]
2883   ""
2884 {
2885   /* As the result of CMPINT is inverted compared to what we need,
2886      we have to swap the operands.  */
2887   rtx op1 = operands[2];
2888   rtx op2 = operands[1];
2889   rtx addr1 = gen_reg_rtx (Pmode);
2890   rtx addr2 = gen_reg_rtx (Pmode);
2891
2892   emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2893   emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2894   operands[1] = replace_equiv_address_nv (op1, addr1);
2895   operands[2] = replace_equiv_address_nv (op2, addr2);
2896   operands[3] = addr1;
2897   operands[4] = addr2;
2898 })
2899
2900 (define_insn "*cmpstr<mode>"
2901   [(clobber (match_operand:P 0 "register_operand" "=d"))
2902    (clobber (match_operand:P 1 "register_operand" "=d"))
2903    (set (reg:CCU CC_REGNUM)
2904         (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2905                      (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2906    (use (reg:SI 0))]
2907   ""
2908   "clst\t%0,%1\;jo\t.-4"
2909   [(set_attr "length" "8")
2910    (set_attr "type" "vs")])
2911
2912 ;
2913 ; movstr instruction pattern.
2914 ;
2915
2916 (define_expand "movstr"
2917   [(match_operand 0 "register_operand" "")
2918    (match_operand 1 "memory_operand" "")
2919    (match_operand 2 "memory_operand" "")]
2920   ""
2921 {
2922   if (TARGET_64BIT)
2923     emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2924   else
2925     emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2926   DONE;
2927 })
2928
2929 (define_expand "movstr<P:mode>"
2930   [(set (reg:SI 0) (const_int 0))
2931    (parallel
2932     [(clobber (match_dup 3))
2933      (set (match_operand:BLK 1 "memory_operand" "")
2934           (match_operand:BLK 2 "memory_operand" ""))
2935      (set (match_operand:P 0 "register_operand" "")
2936           (unspec:P [(match_dup 1)
2937                    (match_dup 2)
2938                    (reg:SI 0)] UNSPEC_MVST))
2939      (clobber (reg:CC CC_REGNUM))])]
2940   ""
2941 {
2942   rtx addr1, addr2;
2943
2944   if (TARGET_VX && optimize_function_for_speed_p (cfun))
2945     {
2946       s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
2947       DONE;
2948     }
2949
2950   addr1 = gen_reg_rtx (Pmode);
2951   addr2 = gen_reg_rtx (Pmode);
2952
2953   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2954   emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2955   operands[1] = replace_equiv_address_nv (operands[1], addr1);
2956   operands[2] = replace_equiv_address_nv (operands[2], addr2);
2957   operands[3] = addr2;
2958 })
2959
2960 (define_insn "*movstr"
2961   [(clobber (match_operand:P 2 "register_operand" "=d"))
2962    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2963         (mem:BLK (match_operand:P 3 "register_operand" "2")))
2964    (set (match_operand:P 0 "register_operand" "=d")
2965         (unspec:P [(mem:BLK (match_dup 1))
2966                  (mem:BLK (match_dup 3))
2967                  (reg:SI 0)] UNSPEC_MVST))
2968    (clobber (reg:CC CC_REGNUM))]
2969   ""
2970   "mvst\t%1,%2\;jo\t.-4"
2971   [(set_attr "length" "8")
2972    (set_attr "type" "vs")])
2973
2974
2975 ;
2976 ; movmemM instruction pattern(s).
2977 ;
2978
2979 (define_expand "movmem<mode>"
2980   [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
2981         (match_operand:BLK 1 "memory_operand" ""))  ; source
2982    (use (match_operand:GPR 2 "general_operand" "")) ; count
2983    (match_operand 3 "" "")]
2984   ""
2985 {
2986   if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2987     DONE;
2988   else
2989     FAIL;
2990 })
2991
2992 ; Move a block that is up to 256 bytes in length.
2993 ; The block length is taken as (operands[2] % 256) + 1.
2994
2995 (define_expand "movmem_short"
2996   [(parallel
2997     [(set (match_operand:BLK 0 "memory_operand" "")
2998           (match_operand:BLK 1 "memory_operand" ""))
2999      (use (match_operand 2 "nonmemory_operand" ""))
3000      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3001      (clobber (match_dup 3))])]
3002   ""
3003   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3004
3005 (define_insn "*movmem_short"
3006   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3007         (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3008    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3009    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3010    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3011   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3012   "#"
3013   [(set_attr "type"         "cs")
3014    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3015
3016 (define_split
3017   [(set (match_operand:BLK 0 "memory_operand" "")
3018         (match_operand:BLK 1 "memory_operand" ""))
3019    (use (match_operand 2 "const_int_operand" ""))
3020    (use (match_operand 3 "immediate_operand" ""))
3021    (clobber (scratch))]
3022   "reload_completed"
3023   [(parallel
3024     [(set (match_dup 0) (match_dup 1))
3025      (use (match_dup 2))])]
3026   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3027
3028 (define_split
3029   [(set (match_operand:BLK 0 "memory_operand" "")
3030         (match_operand:BLK 1 "memory_operand" ""))
3031    (use (match_operand 2 "register_operand" ""))
3032    (use (match_operand 3 "memory_operand" ""))
3033    (clobber (scratch))]
3034   "reload_completed"
3035   [(parallel
3036     [(unspec [(match_dup 2) (match_dup 3)
3037               (const_int 0)] UNSPEC_EXECUTE)
3038      (set (match_dup 0) (match_dup 1))
3039      (use (const_int 1))])]
3040   "")
3041
3042 (define_split
3043   [(set (match_operand:BLK 0 "memory_operand" "")
3044         (match_operand:BLK 1 "memory_operand" ""))
3045    (use (match_operand 2 "register_operand" ""))
3046    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3047    (clobber (scratch))]
3048   "TARGET_Z10 && reload_completed"
3049   [(parallel
3050     [(unspec [(match_dup 2) (const_int 0)
3051               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3052      (set (match_dup 0) (match_dup 1))
3053      (use (const_int 1))])]
3054   "operands[3] = gen_label_rtx ();")
3055
3056 (define_split
3057   [(set (match_operand:BLK 0 "memory_operand" "")
3058         (match_operand:BLK 1 "memory_operand" ""))
3059    (use (match_operand 2 "register_operand" ""))
3060    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3061    (clobber (match_operand 3 "register_operand" ""))]
3062   "reload_completed && TARGET_CPU_ZARCH"
3063   [(set (match_dup 3) (label_ref (match_dup 4)))
3064    (parallel
3065     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3066               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3067      (set (match_dup 0) (match_dup 1))
3068      (use (const_int 1))])]
3069   "operands[4] = gen_label_rtx ();")
3070
3071 ; Move a block of arbitrary length.
3072
3073 (define_expand "movmem_long"
3074   [(parallel
3075     [(clobber (match_dup 2))
3076      (clobber (match_dup 3))
3077      (set (match_operand:BLK 0 "memory_operand" "")
3078           (match_operand:BLK 1 "memory_operand" ""))
3079      (use (match_operand 2 "general_operand" ""))
3080      (use (match_dup 3))
3081      (clobber (reg:CC CC_REGNUM))])]
3082   ""
3083 {
3084   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3085   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3086   rtx reg0 = gen_reg_rtx (dreg_mode);
3087   rtx reg1 = gen_reg_rtx (dreg_mode);
3088   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3089   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3090   rtx len0 = gen_lowpart (Pmode, reg0);
3091   rtx len1 = gen_lowpart (Pmode, reg1);
3092
3093   emit_clobber (reg0);
3094   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3095   emit_move_insn (len0, operands[2]);
3096
3097   emit_clobber (reg1);
3098   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3099   emit_move_insn (len1, operands[2]);
3100
3101   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3102   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3103   operands[2] = reg0;
3104   operands[3] = reg1;
3105 })
3106
3107 (define_insn "*movmem_long"
3108   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3109    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3110    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3111         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3112    (use (match_dup 2))
3113    (use (match_dup 3))
3114    (clobber (reg:CC CC_REGNUM))]
3115   "TARGET_64BIT || !TARGET_ZARCH"
3116   "mvcle\t%0,%1,0\;jo\t.-4"
3117   [(set_attr "length" "8")
3118    (set_attr "type" "vs")])
3119
3120 (define_insn "*movmem_long_31z"
3121   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3122    (clobber (match_operand:TI 1 "register_operand" "=d"))
3123    (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3124         (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3125    (use (match_dup 2))
3126    (use (match_dup 3))
3127    (clobber (reg:CC CC_REGNUM))]
3128   "!TARGET_64BIT && TARGET_ZARCH"
3129   "mvcle\t%0,%1,0\;jo\t.-4"
3130   [(set_attr "length" "8")
3131    (set_attr "type" "vs")])
3132
3133
3134 ;
3135 ; Test data class.
3136 ;
3137
3138 (define_expand "signbit<mode>2"
3139   [(set (reg:CCZ CC_REGNUM)
3140         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3141                      (match_dup 2)]
3142                      UNSPEC_TDC_INSN))
3143    (set (match_operand:SI 0 "register_operand" "=d")
3144         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3145   "TARGET_HARD_FLOAT"
3146 {
3147   operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3148 })
3149
3150 (define_expand "isinf<mode>2"
3151   [(set (reg:CCZ CC_REGNUM)
3152         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3153                      (match_dup 2)]
3154                      UNSPEC_TDC_INSN))
3155    (set (match_operand:SI 0 "register_operand" "=d")
3156         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3157   "TARGET_HARD_FLOAT"
3158 {
3159   operands[2] = GEN_INT (S390_TDC_INFINITY);
3160 })
3161
3162 ; This extracts CC into a GPR properly shifted.  The actual IPM
3163 ; instruction will be issued by reload.  The constraint of operand 1
3164 ; forces reload to use a GPR.  So reload will issue a movcc insn for
3165 ; copying CC into a GPR first.
3166 (define_insn_and_split "*cc_to_int"
3167   [(set (match_operand:SI 0 "nonimmediate_operand"     "=d")
3168         (unspec:SI [(match_operand 1 "register_operand" "0")]
3169                    UNSPEC_CC_TO_INT))]
3170   "operands != NULL"
3171   "#"
3172   "reload_completed"
3173   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3174
3175 ; This insn is used to generate all variants of the Test Data Class
3176 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
3177 ; is the register to be tested and the second one is the bit mask
3178 ; specifying the required test(s).
3179 ;
3180 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3181 (define_insn "*TDC_insn_<mode>"
3182   [(set (reg:CCZ CC_REGNUM)
3183         (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3184                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3185   "TARGET_HARD_FLOAT"
3186   "t<_d>c<xde><bt>\t%0,%1"
3187    [(set_attr "op_type" "RXE")
3188     (set_attr "type"  "fsimp<mode>")])
3189
3190
3191
3192 ;
3193 ; setmemM instruction pattern(s).
3194 ;
3195
3196 (define_expand "setmem<mode>"
3197   [(set (match_operand:BLK 0 "memory_operand" "")
3198         (match_operand:QI 2 "general_operand" ""))
3199    (use (match_operand:GPR 1 "general_operand" ""))
3200    (match_operand 3 "" "")]
3201   ""
3202   "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3203
3204 ; Clear a block that is up to 256 bytes in length.
3205 ; The block length is taken as (operands[1] % 256) + 1.
3206
3207 (define_expand "clrmem_short"
3208   [(parallel
3209     [(set (match_operand:BLK 0 "memory_operand" "")
3210           (const_int 0))
3211      (use (match_operand 1 "nonmemory_operand" ""))
3212      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3213      (clobber (match_dup 2))
3214      (clobber (reg:CC CC_REGNUM))])]
3215   ""
3216   "operands[2] = gen_rtx_SCRATCH (Pmode);")
3217
3218 (define_insn "*clrmem_short"
3219   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3220         (const_int 0))
3221    (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3222    (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3223    (clobber (match_scratch:P 3 "=X,X,X,&a"))
3224    (clobber (reg:CC CC_REGNUM))]
3225   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3226   "#"
3227   [(set_attr "type" "cs")
3228    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3229
3230 (define_split
3231   [(set (match_operand:BLK 0 "memory_operand" "")
3232         (const_int 0))
3233    (use (match_operand 1 "const_int_operand" ""))
3234    (use (match_operand 2 "immediate_operand" ""))
3235    (clobber (scratch))
3236    (clobber (reg:CC CC_REGNUM))]
3237   "reload_completed"
3238   [(parallel
3239     [(set (match_dup 0) (const_int 0))
3240      (use (match_dup 1))
3241      (clobber (reg:CC CC_REGNUM))])]
3242   "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3243
3244 (define_split
3245   [(set (match_operand:BLK 0 "memory_operand" "")
3246         (const_int 0))
3247    (use (match_operand 1 "register_operand" ""))
3248    (use (match_operand 2 "memory_operand" ""))
3249    (clobber (scratch))
3250    (clobber (reg:CC CC_REGNUM))]
3251   "reload_completed"
3252   [(parallel
3253     [(unspec [(match_dup 1) (match_dup 2)
3254               (const_int 0)] UNSPEC_EXECUTE)
3255      (set (match_dup 0) (const_int 0))
3256      (use (const_int 1))
3257      (clobber (reg:CC CC_REGNUM))])]
3258   "")
3259
3260 (define_split
3261   [(set (match_operand:BLK 0 "memory_operand" "")
3262         (const_int 0))
3263    (use (match_operand 1 "register_operand" ""))
3264    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3265    (clobber (scratch))
3266    (clobber (reg:CC CC_REGNUM))]
3267   "TARGET_Z10 && reload_completed"
3268   [(parallel
3269     [(unspec [(match_dup 1) (const_int 0)
3270               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3271      (set (match_dup 0) (const_int 0))
3272      (use (const_int 1))
3273      (clobber (reg:CC CC_REGNUM))])]
3274   "operands[3] = gen_label_rtx ();")
3275
3276 (define_split
3277   [(set (match_operand:BLK 0 "memory_operand" "")
3278         (const_int 0))
3279    (use (match_operand 1 "register_operand" ""))
3280    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3281    (clobber (match_operand 2 "register_operand" ""))
3282    (clobber (reg:CC CC_REGNUM))]
3283   "reload_completed && TARGET_CPU_ZARCH"
3284   [(set (match_dup 2) (label_ref (match_dup 3)))
3285    (parallel
3286     [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3287               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3288      (set (match_dup 0) (const_int 0))
3289      (use (const_int 1))
3290      (clobber (reg:CC CC_REGNUM))])]
3291   "operands[3] = gen_label_rtx ();")
3292
3293 ; Initialize a block of arbitrary length with (operands[2] % 256).
3294
3295 (define_expand "setmem_long_<P:mode>"
3296   [(parallel
3297     [(clobber (match_dup 1))
3298      (set (match_operand:BLK 0 "memory_operand" "")
3299           (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "")
3300                       (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3301      (use (match_dup 3))
3302      (clobber (reg:CC CC_REGNUM))])]
3303   ""
3304 {
3305   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3306   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3307   rtx reg0 = gen_reg_rtx (dreg_mode);
3308   rtx reg1 = gen_reg_rtx (dreg_mode);
3309   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3310   rtx len0 = gen_lowpart (Pmode, reg0);
3311
3312   emit_clobber (reg0);
3313   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3314   emit_move_insn (len0, operands[1]);
3315
3316   emit_move_insn (reg1, const0_rtx);
3317
3318   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3319   operands[1] = reg0;
3320   operands[3] = reg1;
3321   operands[4] = gen_lowpart (Pmode, operands[1]);
3322 })
3323
3324 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3325
3326 (define_insn "*setmem_long<setmem_and>"
3327   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3328    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3329         (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y")
3330                      (subreg:P (match_dup 3) <modesize>)]
3331                      UNSPEC_REPLICATE_BYTE))
3332    (use (match_operand:<DBL> 1 "register_operand" "d"))
3333    (clobber (reg:CC CC_REGNUM))]
3334   "TARGET_64BIT || !TARGET_ZARCH"
3335   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3336   [(set_attr "length" "8")
3337    (set_attr "type" "vs")])
3338
3339 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3340 ; of the SImode subregs.
3341
3342 (define_insn "*setmem_long_31z<setmem_and>"
3343   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3344    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3345         (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
3346                      (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3347    (use (match_operand:TI 1 "register_operand" "d"))
3348    (clobber (reg:CC CC_REGNUM))]
3349   "!TARGET_64BIT && TARGET_ZARCH"
3350   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3351   [(set_attr "length" "8")
3352    (set_attr "type" "vs")])
3353
3354 ;
3355 ; cmpmemM instruction pattern(s).
3356 ;
3357
3358 (define_expand "cmpmemsi"
3359   [(set (match_operand:SI 0 "register_operand" "")
3360         (compare:SI (match_operand:BLK 1 "memory_operand" "")
3361                     (match_operand:BLK 2 "memory_operand" "") ) )
3362    (use (match_operand:SI 3 "general_operand" ""))
3363    (use (match_operand:SI 4 "" ""))]
3364   ""
3365 {
3366   if (s390_expand_cmpmem (operands[0], operands[1],
3367                           operands[2], operands[3]))
3368     DONE;
3369   else
3370     FAIL;
3371 })
3372
3373 ; Compare a block that is up to 256 bytes in length.
3374 ; The block length is taken as (operands[2] % 256) + 1.
3375
3376 (define_expand "cmpmem_short"
3377   [(parallel
3378     [(set (reg:CCU CC_REGNUM)
3379           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3380                        (match_operand:BLK 1 "memory_operand" "")))
3381      (use (match_operand 2 "nonmemory_operand" ""))
3382      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3383      (clobber (match_dup 3))])]
3384   ""
3385   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3386
3387 (define_insn "*cmpmem_short"
3388   [(set (reg:CCU CC_REGNUM)
3389         (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3390                      (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3391    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3392    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3393    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3394   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3395   "#"
3396   [(set_attr "type" "cs")
3397    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3398
3399 (define_split
3400   [(set (reg:CCU CC_REGNUM)
3401         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3402                      (match_operand:BLK 1 "memory_operand" "")))
3403    (use (match_operand 2 "const_int_operand" ""))
3404    (use (match_operand 3 "immediate_operand" ""))
3405    (clobber (scratch))]
3406   "reload_completed"
3407   [(parallel
3408     [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3409      (use (match_dup 2))])]
3410   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3411
3412 (define_split
3413   [(set (reg:CCU CC_REGNUM)
3414         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3415                      (match_operand:BLK 1 "memory_operand" "")))
3416    (use (match_operand 2 "register_operand" ""))
3417    (use (match_operand 3 "memory_operand" ""))
3418    (clobber (scratch))]
3419   "reload_completed"
3420   [(parallel
3421     [(unspec [(match_dup 2) (match_dup 3)
3422               (const_int 0)] UNSPEC_EXECUTE)
3423      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3424      (use (const_int 1))])]
3425   "")
3426
3427 (define_split
3428   [(set (reg:CCU CC_REGNUM)
3429         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3430                      (match_operand:BLK 1 "memory_operand" "")))
3431    (use (match_operand 2 "register_operand" ""))
3432    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3433    (clobber (scratch))]
3434   "TARGET_Z10 && reload_completed"
3435   [(parallel
3436     [(unspec [(match_dup 2) (const_int 0)
3437               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3438      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3439      (use (const_int 1))])]
3440   "operands[4] = gen_label_rtx ();")
3441
3442 (define_split
3443   [(set (reg:CCU CC_REGNUM)
3444         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3445                      (match_operand:BLK 1 "memory_operand" "")))
3446    (use (match_operand 2 "register_operand" ""))
3447    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3448    (clobber (match_operand 3 "register_operand" ""))]
3449   "reload_completed && TARGET_CPU_ZARCH"
3450   [(set (match_dup 3) (label_ref (match_dup 4)))
3451    (parallel
3452     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3453               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3454      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3455      (use (const_int 1))])]
3456   "operands[4] = gen_label_rtx ();")
3457
3458 ; Compare a block of arbitrary length.
3459
3460 (define_expand "cmpmem_long"
3461   [(parallel
3462     [(clobber (match_dup 2))
3463      (clobber (match_dup 3))
3464      (set (reg:CCU CC_REGNUM)
3465           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3466                        (match_operand:BLK 1 "memory_operand" "")))
3467      (use (match_operand 2 "general_operand" ""))
3468      (use (match_dup 3))])]
3469   ""
3470 {
3471   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3472   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3473   rtx reg0 = gen_reg_rtx (dreg_mode);
3474   rtx reg1 = gen_reg_rtx (dreg_mode);
3475   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3476   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3477   rtx len0 = gen_lowpart (Pmode, reg0);
3478   rtx len1 = gen_lowpart (Pmode, reg1);
3479
3480   emit_clobber (reg0);
3481   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3482   emit_move_insn (len0, operands[2]);
3483
3484   emit_clobber (reg1);
3485   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3486   emit_move_insn (len1, operands[2]);
3487
3488   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3489   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3490   operands[2] = reg0;
3491   operands[3] = reg1;
3492 })
3493
3494 (define_insn "*cmpmem_long"
3495   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3496    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3497    (set (reg:CCU CC_REGNUM)
3498         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3499                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3500    (use (match_dup 2))
3501    (use (match_dup 3))]
3502   "TARGET_64BIT || !TARGET_ZARCH"
3503   "clcle\t%0,%1,0\;jo\t.-4"
3504   [(set_attr "length" "8")
3505    (set_attr "type" "vs")])
3506
3507 (define_insn "*cmpmem_long_31z"
3508   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3509    (clobber (match_operand:TI 1 "register_operand" "=d"))
3510    (set (reg:CCU CC_REGNUM)
3511         (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3512                      (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3513    (use (match_dup 2))
3514    (use (match_dup 3))]
3515   "!TARGET_64BIT && TARGET_ZARCH"
3516   "clcle\t%0,%1,0\;jo\t.-4"
3517   [(set_attr "op_type" "NN")
3518    (set_attr "type"    "vs")
3519    (set_attr "length"  "8")])
3520
3521 ; Convert CCUmode condition code to integer.
3522 ; Result is zero if EQ, positive if LTU, negative if GTU.
3523
3524 (define_insn_and_split "cmpint"
3525   [(set (match_operand:SI 0 "register_operand" "=d")
3526         (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3527                    UNSPEC_STRCMPCC_TO_INT))
3528    (clobber (reg:CC CC_REGNUM))]
3529   ""
3530   "#"
3531   "reload_completed"
3532   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3533    (parallel
3534     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3535      (clobber (reg:CC CC_REGNUM))])])
3536
3537 (define_insn_and_split "*cmpint_cc"
3538   [(set (reg CC_REGNUM)
3539         (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3540                             UNSPEC_STRCMPCC_TO_INT)
3541                  (const_int 0)))
3542    (set (match_operand:SI 0 "register_operand" "=d")
3543         (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3544   "s390_match_ccmode (insn, CCSmode)"
3545   "#"
3546   "&& reload_completed"
3547   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3548    (parallel
3549     [(set (match_dup 2) (match_dup 3))
3550      (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3551 {
3552   rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3553   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3554   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3555 })
3556
3557 (define_insn_and_split "*cmpint_sign"
3558   [(set (match_operand:DI 0 "register_operand" "=d")
3559         (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3560                                    UNSPEC_STRCMPCC_TO_INT)))
3561    (clobber (reg:CC CC_REGNUM))]
3562   "TARGET_ZARCH"
3563   "#"
3564   "&& reload_completed"
3565   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3566    (parallel
3567     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3568      (clobber (reg:CC CC_REGNUM))])])
3569
3570 (define_insn_and_split "*cmpint_sign_cc"
3571   [(set (reg CC_REGNUM)
3572         (compare (ashiftrt:DI (ashift:DI (subreg:DI
3573                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3574                               UNSPEC_STRCMPCC_TO_INT) 0)
3575                    (const_int 32)) (const_int 32))
3576                  (const_int 0)))
3577    (set (match_operand:DI 0 "register_operand" "=d")
3578         (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3579   "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3580   "#"
3581   "&& reload_completed"
3582   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3583    (parallel
3584     [(set (match_dup 2) (match_dup 3))
3585      (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3586 {
3587   rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3588   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3589   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3590 })
3591
3592
3593 ;;
3594 ;;- Conversion instructions.
3595 ;;
3596
3597 (define_insn "*sethighpartsi"
3598   [(set (match_operand:SI 0 "register_operand" "=d,d")
3599         (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3600                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3601    (clobber (reg:CC CC_REGNUM))]
3602   ""
3603   "@
3604    icm\t%0,%2,%S1
3605    icmy\t%0,%2,%S1"
3606   [(set_attr "op_type" "RS,RSY")
3607    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3608
3609 (define_insn "*sethighpartdi_64"
3610   [(set (match_operand:DI 0 "register_operand" "=d")
3611         (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3612                     (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3613    (clobber (reg:CC CC_REGNUM))]
3614   "TARGET_ZARCH"
3615   "icmh\t%0,%2,%S1"
3616   [(set_attr "op_type" "RSY")
3617    (set_attr "z10prop" "z10_super")])
3618
3619 (define_insn "*sethighpartdi_31"
3620   [(set (match_operand:DI 0 "register_operand" "=d,d")
3621         (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3622                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3623    (clobber (reg:CC CC_REGNUM))]
3624   "!TARGET_ZARCH"
3625   "@
3626    icm\t%0,%2,%S1
3627    icmy\t%0,%2,%S1"
3628   [(set_attr "op_type" "RS,RSY")
3629    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3630
3631 ;
3632 ; extv instruction patterns
3633 ;
3634
3635 ; FIXME: This expander needs to be converted from DI to GPR as well
3636 ; after resolving some issues with it.
3637
3638 (define_expand "extzv"
3639   [(parallel
3640     [(set (match_operand:DI 0 "register_operand" "=d")
3641         (zero_extract:DI
3642          (match_operand:DI 1 "register_operand" "d")
3643          (match_operand 2 "const_int_operand" "")   ; size
3644          (match_operand 3 "const_int_operand" ""))) ; start
3645      (clobber (reg:CC CC_REGNUM))])]
3646   "TARGET_Z10"
3647 {
3648   /* Starting with zEC12 there is risbgn not clobbering CC.  */
3649   if (TARGET_ZEC12)
3650     {
3651       emit_move_insn (operands[0],
3652                     gen_rtx_ZERO_EXTRACT (DImode,
3653                                           operands[1],
3654                                           operands[2],
3655                                           operands[3]));
3656       DONE;
3657     }
3658 })
3659
3660 (define_insn "*extzv<mode>_zEC12"
3661   [(set (match_operand:GPR 0 "register_operand" "=d")
3662       (zero_extract:GPR
3663         (match_operand:GPR 1 "register_operand" "d")
3664         (match_operand 2 "const_int_operand" "")   ; size
3665         (match_operand 3 "const_int_operand" "")))] ; start]
3666   "TARGET_ZEC12"
3667   "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3668   [(set_attr "op_type" "RIE")])
3669
3670 (define_insn "*extzv<mode>_z10"
3671   [(set (match_operand:GPR 0 "register_operand" "=d")
3672       (zero_extract:GPR
3673        (match_operand:GPR 1 "register_operand" "d")
3674        (match_operand 2 "const_int_operand" "")   ; size
3675        (match_operand 3 "const_int_operand" ""))) ; start
3676    (clobber (reg:CC CC_REGNUM))]
3677   "TARGET_Z10"
3678   "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3679   [(set_attr "op_type" "RIE")
3680    (set_attr "z10prop" "z10_super_E1")])
3681
3682 (define_insn_and_split "*pre_z10_extzv<mode>"
3683   [(set (match_operand:GPR 0 "register_operand" "=d")
3684         (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3685                           (match_operand 2 "nonzero_shift_count_operand" "")
3686                           (const_int 0)))
3687    (clobber (reg:CC CC_REGNUM))]
3688   "!TARGET_Z10"
3689   "#"
3690   "&& reload_completed"
3691   [(parallel
3692     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3693      (clobber (reg:CC CC_REGNUM))])
3694    (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3695 {
3696   int bitsize = INTVAL (operands[2]);
3697   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3698   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3699
3700   operands[1] = adjust_address (operands[1], BLKmode, 0);
3701   set_mem_size (operands[1], size);
3702   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3703   operands[3] = GEN_INT (mask);
3704 })
3705
3706 (define_insn_and_split "*pre_z10_extv<mode>"
3707   [(set (match_operand:GPR 0 "register_operand" "=d")
3708         (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3709                           (match_operand 2 "nonzero_shift_count_operand" "")
3710                           (const_int 0)))
3711    (clobber (reg:CC CC_REGNUM))]
3712   ""
3713   "#"
3714   "&& reload_completed"
3715   [(parallel
3716     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3717      (clobber (reg:CC CC_REGNUM))])
3718    (parallel
3719     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3720      (clobber (reg:CC CC_REGNUM))])]
3721 {
3722   int bitsize = INTVAL (operands[2]);
3723   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3724   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3725
3726   operands[1] = adjust_address (operands[1], BLKmode, 0);
3727   set_mem_size (operands[1], size);
3728   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3729   operands[3] = GEN_INT (mask);
3730 })
3731
3732 ;
3733 ; insv instruction patterns
3734 ;
3735
3736 (define_expand "insv"
3737   [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3738                       (match_operand 1 "const_int_operand" "")
3739                       (match_operand 2 "const_int_operand" ""))
3740         (match_operand 3 "general_operand" ""))]
3741   ""
3742 {
3743   if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3744     DONE;
3745   FAIL;
3746 })
3747
3748
3749 ; The normal RTL expansion will never generate a zero_extract where
3750 ; the location operand isn't word mode.  However, we do this in the
3751 ; back-end when generating atomic operations. See s390_two_part_insv.
3752 (define_insn "*insv<mode>_zEC12"
3753   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3754                           (match_operand 1 "const_int_operand"    "I")  ; size
3755                           (match_operand 2 "const_int_operand"    "I")) ; pos
3756         (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3757   "TARGET_ZEC12
3758    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3759   "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3760   [(set_attr "op_type" "RIE")])
3761
3762 (define_insn "*insv<mode>_z10"
3763   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3764                           (match_operand 1 "const_int_operand"    "I")  ; size
3765                           (match_operand 2 "const_int_operand"    "I")) ; pos
3766         (match_operand:GPR 3 "nonimmediate_operand" "d"))
3767    (clobber (reg:CC CC_REGNUM))]
3768   "TARGET_Z10
3769    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3770   "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3771   [(set_attr "op_type" "RIE")
3772    (set_attr "z10prop" "z10_super_E1")])
3773
3774 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3775 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3776 (define_insn "*insv<mode>_zEC12_noshift"
3777   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3778         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3779                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3780                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3781                           (match_operand:GPR 4 "const_int_operand" ""))))]
3782   "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3783   "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3784   [(set_attr "op_type" "RIE")])
3785
3786 (define_insn "*insv<mode>_z10_noshift"
3787   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3788         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3789                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3790                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3791                           (match_operand:GPR 4 "const_int_operand" ""))))
3792    (clobber (reg:CC CC_REGNUM))]
3793   "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3794   "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3795   [(set_attr "op_type" "RIE")
3796    (set_attr "z10prop" "z10_super_E1")])
3797
3798 ; Implement appending Y on the left of S bits of X
3799 ; x = (y << s) | (x & ((1 << s) - 1))
3800 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3801   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3802         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3803                           (match_operand:GPR 2 "immediate_operand" ""))
3804                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3805                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3806   "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3807   "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3808   [(set_attr "op_type" "RIE")
3809    (set_attr "z10prop" "z10_super_E1")])
3810
3811 (define_insn "*insv<mode>_z10_appendbitsleft"
3812   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3813         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3814                           (match_operand:GPR 2 "immediate_operand" ""))
3815                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3816                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3817    (clobber (reg:CC CC_REGNUM))]
3818   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3819   "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3820   [(set_attr "op_type" "RIE")
3821    (set_attr "z10prop" "z10_super_E1")])
3822
3823 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3824 ;  -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3825 ;  -> z = y >> d; z = risbg;
3826
3827 (define_split
3828   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3829         (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3830                                (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3831                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3832                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3833   "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3834   [(set (match_dup 6)
3835         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3836    (set (match_dup 0)
3837         (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3838                  (ashift:GPR (match_dup 3) (match_dup 4))))]
3839 {
3840   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3841   if (rtx_equal_p (operands[0], operands[3]))
3842     {
3843       if (!can_create_pseudo_p ())
3844         FAIL;
3845       operands[6] = gen_reg_rtx (<MODE>mode);
3846     }
3847   else
3848     operands[6] = operands[0];
3849 })
3850
3851 (define_split
3852   [(parallel
3853     [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3854           (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3855                                  (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3856                    (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3857                                (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3858      (clobber (reg:CC CC_REGNUM))])]
3859   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3860   [(set (match_dup 6)
3861         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3862    (parallel
3863     [(set (match_dup 0)
3864           (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3865                    (ashift:GPR (match_dup 3) (match_dup 4))))
3866      (clobber (reg:CC CC_REGNUM))])]
3867 {
3868   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3869   if (rtx_equal_p (operands[0], operands[3]))
3870     {
3871       if (!can_create_pseudo_p ())
3872         FAIL;
3873       operands[6] = gen_reg_rtx (<MODE>mode);
3874     }
3875   else
3876     operands[6] = operands[0];
3877 })
3878
3879 (define_insn "*r<noxa>sbg_<mode>_noshift"
3880   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3881         (IXOR:GPR
3882           (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3883                    (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3884           (match_operand:GPR 3 "nonimmediate_operand" "0")))
3885    (clobber (reg:CC CC_REGNUM))]
3886   "TARGET_Z10"
3887   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3888   [(set_attr "op_type" "RIE")])
3889
3890 (define_insn "*r<noxa>sbg_di_rotl"
3891   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3892         (IXOR:DI
3893           (and:DI
3894             (rotate:DI
3895               (match_operand:DI 1 "nonimmediate_operand" "d")
3896               (match_operand:DI 3 "const_int_operand" ""))
3897             (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3898           (match_operand:DI 4 "nonimmediate_operand" "0")))
3899    (clobber (reg:CC CC_REGNUM))]
3900   "TARGET_Z10"
3901   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3902   [(set_attr "op_type" "RIE")])
3903
3904 (define_insn "*r<noxa>sbg_<mode>_srl"
3905   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3906         (IXOR:GPR
3907           (and:GPR
3908             (lshiftrt:GPR
3909               (match_operand:GPR 1 "nonimmediate_operand" "d")
3910               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3911             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3912           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3913    (clobber (reg:CC CC_REGNUM))]
3914   "TARGET_Z10
3915    && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3916                            INTVAL (operands[2]))"
3917   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3918   [(set_attr "op_type" "RIE")])
3919
3920 (define_insn "*r<noxa>sbg_<mode>_sll"
3921   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3922         (IXOR:GPR
3923           (and:GPR
3924             (ashift:GPR
3925               (match_operand:GPR 1 "nonimmediate_operand" "d")
3926               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3927             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3928           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3929    (clobber (reg:CC CC_REGNUM))]
3930   "TARGET_Z10
3931    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3932                            INTVAL (operands[2]))"
3933   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3934   [(set_attr "op_type" "RIE")])
3935
3936 ;; These two are generated by combine for s.bf &= val.
3937 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3938 ;; shifts and ands, which results in some truly awful patterns
3939 ;; including subregs of operations.  Rather unnecessisarily, IMO.
3940 ;; Instead of
3941 ;;
3942 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3943 ;;        (const_int 24 [0x18])
3944 ;;        (const_int 0 [0]))
3945 ;;    (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3946 ;;                    (const_int 40 [0x28])) 4)
3947 ;;            (reg:SI 4 %r4 [ y+4 ])) 0))
3948 ;;
3949 ;; we should instead generate
3950 ;;
3951 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3952 ;;        (const_int 24 [0x18])
3953 ;;        (const_int 0 [0]))
3954 ;;    (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3955 ;;                    (const_int 40 [0x28]))
3956 ;;            (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3957 ;;
3958 ;; by noticing that we can push down the outer paradoxical subreg
3959 ;; into the operation.
3960
3961 (define_insn "*insv_rnsbg_noshift"
3962   [(set (zero_extract:DI
3963           (match_operand:DI 0 "nonimmediate_operand" "+d")
3964           (match_operand 1 "const_int_operand" "")
3965           (match_operand 2 "const_int_operand" ""))
3966         (and:DI
3967           (match_dup 0)
3968           (match_operand:DI 3 "nonimmediate_operand" "d")))
3969    (clobber (reg:CC CC_REGNUM))]
3970   "TARGET_Z10
3971    && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3972   "rnsbg\t%0,%3,%2,63,0"
3973   [(set_attr "op_type" "RIE")])
3974
3975 (define_insn "*insv_rnsbg_srl"
3976   [(set (zero_extract:DI
3977           (match_operand:DI 0 "nonimmediate_operand" "+d")
3978           (match_operand 1 "const_int_operand" "")
3979           (match_operand 2 "const_int_operand" ""))
3980         (and:DI
3981           (lshiftrt:DI
3982             (match_dup 0)
3983             (match_operand 3 "const_int_operand" ""))
3984           (match_operand:DI 4 "nonimmediate_operand" "d")))
3985    (clobber (reg:CC CC_REGNUM))]
3986   "TARGET_Z10
3987    && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3988   "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3989   [(set_attr "op_type" "RIE")])
3990
3991 (define_insn "*insv<mode>_mem_reg"
3992   [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3993                         (match_operand 1 "const_int_operand" "n,n")
3994                         (const_int 0))
3995         (match_operand:W 2 "register_operand" "d,d"))]
3996   "INTVAL (operands[1]) > 0
3997    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3998    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3999 {
4000     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4001
4002     operands[1] = GEN_INT ((1ul << size) - 1);
4003     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4004                                     : "stcmy\t%2,%1,%S0";
4005 }
4006   [(set_attr "op_type" "RS,RSY")
4007    (set_attr "z10prop" "z10_super,z10_super")])
4008
4009 (define_insn "*insvdi_mem_reghigh"
4010   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
4011                          (match_operand 1 "const_int_operand" "n")
4012                          (const_int 0))
4013         (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4014                      (const_int 32)))]
4015   "TARGET_ZARCH
4016    && INTVAL (operands[1]) > 0
4017    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4018    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4019 {
4020     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4021
4022     operands[1] = GEN_INT ((1ul << size) - 1);
4023     return "stcmh\t%2,%1,%S0";
4024 }
4025 [(set_attr "op_type" "RSY")
4026  (set_attr "z10prop" "z10_super")])
4027
4028 (define_insn "*insvdi_reg_imm"
4029   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4030                          (const_int 16)
4031                          (match_operand 1 "const_int_operand" "n"))
4032         (match_operand:DI 2 "const_int_operand" "n"))]
4033   "TARGET_ZARCH
4034    && INTVAL (operands[1]) >= 0
4035    && INTVAL (operands[1]) < BITS_PER_WORD
4036    && INTVAL (operands[1]) % 16 == 0"
4037 {
4038   switch (BITS_PER_WORD - INTVAL (operands[1]))
4039     {
4040       case 64: return "iihh\t%0,%x2"; break;
4041       case 48: return "iihl\t%0,%x2"; break;
4042       case 32: return "iilh\t%0,%x2"; break;
4043       case 16: return "iill\t%0,%x2"; break;
4044       default: gcc_unreachable();
4045     }
4046 }
4047   [(set_attr "op_type" "RI")
4048    (set_attr "z10prop" "z10_super_E1")])
4049
4050 ; Update the left-most 32 bit of a DI.
4051 (define_insn "*insv_h_di_reg_extimm"
4052   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4053                          (const_int 32)
4054                          (const_int 0))
4055         (match_operand:DI 1 "const_int_operand" "n"))]
4056   "TARGET_EXTIMM"
4057   "iihf\t%0,%o1"
4058   [(set_attr "op_type" "RIL")
4059    (set_attr "z10prop" "z10_fwd_E1")])
4060
4061 ; Update the right-most 32 bit of a DI.
4062 (define_insn "*insv_l_di_reg_extimm"
4063   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4064                          (const_int 32)
4065                          (const_int 32))
4066         (match_operand:DI 1 "const_int_operand" "n"))]
4067   "TARGET_EXTIMM"
4068   "iilf\t%0,%o1"
4069   [(set_attr "op_type" "RIL")
4070    (set_attr "z10prop" "z10_fwd_A1")])
4071
4072 ;
4073 ; extendsidi2 instruction pattern(s).
4074 ;
4075
4076 (define_expand "extendsidi2"
4077   [(set (match_operand:DI 0 "register_operand" "")
4078         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4079   ""
4080 {
4081   if (!TARGET_ZARCH)
4082     {
4083       emit_clobber (operands[0]);
4084       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4085       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4086       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4087       DONE;
4088     }
4089 })
4090
4091 (define_insn "*extendsidi2"
4092   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4093         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4094   "TARGET_ZARCH"
4095   "@
4096    lgfr\t%0,%1
4097    lgf\t%0,%1
4098    lgfrl\t%0,%1"
4099   [(set_attr "op_type"      "RRE,RXY,RIL")
4100    (set_attr "type"         "*,*,larl")
4101    (set_attr "cpu_facility" "*,*,z10")
4102    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4103
4104 ;
4105 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4106 ;
4107
4108 (define_expand "extend<HQI:mode><DSI:mode>2"
4109   [(set (match_operand:DSI 0 "register_operand" "")
4110         (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4111   ""
4112 {
4113   if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4114     {
4115       rtx tmp = gen_reg_rtx (SImode);
4116       emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4117       emit_insn (gen_extendsidi2 (operands[0], tmp));
4118       DONE;
4119     }
4120   else if (!TARGET_EXTIMM)
4121     {
4122       rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4123
4124       operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4125       emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4126       emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4127       DONE;
4128     }
4129 })
4130
4131 ;
4132 ; extendhidi2 instruction pattern(s).
4133 ;
4134
4135 (define_insn "*extendhidi2_extimm"
4136   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4137         (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
4138   "TARGET_ZARCH && TARGET_EXTIMM"
4139   "@
4140    lghr\t%0,%1
4141    lgh\t%0,%1
4142    lghrl\t%0,%1"
4143   [(set_attr "op_type"      "RRE,RXY,RIL")
4144    (set_attr "type"         "*,*,larl")
4145    (set_attr "cpu_facility" "extimm,extimm,z10")
4146    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4147
4148 (define_insn "*extendhidi2"
4149   [(set (match_operand:DI 0 "register_operand" "=d")
4150         (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
4151   "TARGET_ZARCH"
4152   "lgh\t%0,%1"
4153   [(set_attr "op_type" "RXY")
4154    (set_attr "z10prop" "z10_super_E1")])
4155
4156 ;
4157 ; extendhisi2 instruction pattern(s).
4158 ;
4159
4160 (define_insn "*extendhisi2_extimm"
4161   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4162         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4163   "TARGET_EXTIMM"
4164   "@
4165    lhr\t%0,%1
4166    lh\t%0,%1
4167    lhy\t%0,%1
4168    lhrl\t%0,%1"
4169   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
4170    (set_attr "type"         "*,*,*,larl")
4171    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4172    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4173
4174 (define_insn "*extendhisi2"
4175   [(set (match_operand:SI 0 "register_operand" "=d,d")
4176         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4177   "!TARGET_EXTIMM"
4178   "@
4179    lh\t%0,%1
4180    lhy\t%0,%1"
4181   [(set_attr "op_type" "RX,RXY")
4182    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4183
4184 ;
4185 ; extendqi(si|di)2 instruction pattern(s).
4186 ;
4187
4188 ; lbr, lgbr, lb, lgb
4189 (define_insn "*extendqi<mode>2_extimm"
4190   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4191         (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
4192   "TARGET_EXTIMM"
4193   "@
4194    l<g>br\t%0,%1
4195    l<g>b\t%0,%1"
4196   [(set_attr "op_type" "RRE,RXY")
4197    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4198
4199 ; lb, lgb
4200 (define_insn "*extendqi<mode>2"
4201   [(set (match_operand:GPR 0 "register_operand" "=d")
4202         (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
4203   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4204   "l<g>b\t%0,%1"
4205   [(set_attr "op_type" "RXY")
4206    (set_attr "z10prop" "z10_super_E1")])
4207
4208 (define_insn_and_split "*extendqi<mode>2_short_displ"
4209   [(set (match_operand:GPR 0 "register_operand" "=d")
4210         (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4211    (clobber (reg:CC CC_REGNUM))]
4212   "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4213   "#"
4214   "&& reload_completed"
4215   [(parallel
4216     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4217      (clobber (reg:CC CC_REGNUM))])
4218    (parallel
4219     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4220      (clobber (reg:CC CC_REGNUM))])]
4221 {
4222   operands[1] = adjust_address (operands[1], BLKmode, 0);
4223   set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4224   operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4225 })
4226
4227 ;
4228 ; zero_extendsidi2 instruction pattern(s).
4229 ;
4230
4231 (define_expand "zero_extendsidi2"
4232   [(set (match_operand:DI 0 "register_operand" "")
4233         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4234   ""
4235 {
4236   if (!TARGET_ZARCH)
4237     {
4238       emit_clobber (operands[0]);
4239       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4240       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4241       DONE;
4242     }
4243 })
4244
4245 (define_insn "*zero_extendsidi2"
4246   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4247         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4248   "TARGET_ZARCH"
4249   "@
4250    llgfr\t%0,%1
4251    llgf\t%0,%1
4252    llgfrl\t%0,%1"
4253   [(set_attr "op_type"      "RRE,RXY,RIL")
4254    (set_attr "type"         "*,*,larl")
4255    (set_attr "cpu_facility" "*,*,z10")
4256    (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4257
4258 ;
4259 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4260 ;
4261
4262 (define_insn "*llgt_sidi"
4263   [(set (match_operand:DI 0 "register_operand" "=d")
4264         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4265                 (const_int 2147483647)))]
4266   "TARGET_ZARCH"
4267   "llgt\t%0,%1"
4268   [(set_attr "op_type"  "RXE")
4269    (set_attr "z10prop" "z10_super_E1")])
4270
4271 (define_insn_and_split "*llgt_sidi_split"
4272   [(set (match_operand:DI 0 "register_operand" "=d")
4273         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4274                 (const_int 2147483647)))
4275    (clobber (reg:CC CC_REGNUM))]
4276   "TARGET_ZARCH"
4277   "#"
4278   "&& reload_completed"
4279   [(set (match_dup 0)
4280         (and:DI (subreg:DI (match_dup 1) 0)
4281                 (const_int 2147483647)))]
4282   "")
4283
4284 (define_insn "*llgt_sisi"
4285   [(set (match_operand:SI 0 "register_operand" "=d,d")
4286         (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4287                 (const_int 2147483647)))]
4288   "TARGET_ZARCH"
4289   "@
4290    llgtr\t%0,%1
4291    llgt\t%0,%1"
4292   [(set_attr "op_type"  "RRE,RXE")
4293    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4294
4295 (define_insn "*llgt_didi"
4296   [(set (match_operand:DI 0 "register_operand" "=d,d")
4297         (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4298                 (const_int 2147483647)))]
4299   "TARGET_ZARCH"
4300   "@
4301    llgtr\t%0,%1
4302    llgt\t%0,%N1"
4303   [(set_attr "op_type"  "RRE,RXE")
4304    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4305
4306 (define_split
4307   [(set (match_operand:DSI 0 "register_operand" "")
4308         (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4309                  (const_int 2147483647)))
4310    (clobber (reg:CC CC_REGNUM))]
4311   "TARGET_ZARCH && reload_completed"
4312   [(set (match_dup 0)
4313         (and:DSI (match_dup 1)
4314                  (const_int 2147483647)))]
4315   "")
4316
4317 ;
4318 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4319 ;
4320
4321 (define_expand "zero_extend<mode>di2"
4322   [(set (match_operand:DI 0 "register_operand" "")
4323         (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4324   ""
4325 {
4326   if (!TARGET_ZARCH)
4327     {
4328       rtx tmp = gen_reg_rtx (SImode);
4329       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4330       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4331       DONE;
4332     }
4333   else if (!TARGET_EXTIMM)
4334     {
4335       rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4336       operands[1] = gen_lowpart (DImode, operands[1]);
4337       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4338       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4339       DONE;
4340     }
4341 })
4342
4343 (define_expand "zero_extend<mode>si2"
4344   [(set (match_operand:SI 0 "register_operand" "")
4345         (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4346   ""
4347 {
4348   if (!TARGET_EXTIMM)
4349     {
4350       operands[1] = gen_lowpart (SImode, operands[1]);
4351       emit_insn (gen_andsi3 (operands[0], operands[1],
4352                              GEN_INT ((1 << <HQI:bitsize>) - 1)));
4353       DONE;
4354     }
4355 })
4356
4357 ; llhrl, llghrl
4358 (define_insn "*zero_extendhi<mode>2_z10"
4359   [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4360         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4361   "TARGET_Z10"
4362   "@
4363    ll<g>hr\t%0,%1
4364    ll<g>h\t%0,%1
4365    ll<g>hrl\t%0,%1"
4366   [(set_attr "op_type"      "RXY,RRE,RIL")
4367    (set_attr "type"         "*,*,larl")
4368    (set_attr "cpu_facility" "*,*,z10")
4369    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4370
4371 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4372 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4373   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4374         (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4375   "TARGET_EXTIMM"
4376   "@
4377    ll<g><hc>r\t%0,%1
4378    ll<g><hc>\t%0,%1"
4379   [(set_attr "op_type" "RRE,RXY")
4380    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4381
4382 ; llgh, llgc
4383 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4384   [(set (match_operand:GPR 0 "register_operand" "=d")
4385         (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4386   "TARGET_ZARCH && !TARGET_EXTIMM"
4387   "llg<hc>\t%0,%1"
4388   [(set_attr "op_type" "RXY")
4389    (set_attr "z10prop" "z10_fwd_A3")])
4390
4391 (define_insn_and_split "*zero_extendhisi2_31"
4392   [(set (match_operand:SI 0 "register_operand" "=&d")
4393         (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4394    (clobber (reg:CC CC_REGNUM))]
4395   "!TARGET_ZARCH"
4396   "#"
4397   "&& reload_completed"
4398   [(set (match_dup 0) (const_int 0))
4399    (parallel
4400     [(set (strict_low_part (match_dup 2)) (match_dup 1))
4401      (clobber (reg:CC CC_REGNUM))])]
4402   "operands[2] = gen_lowpart (HImode, operands[0]);")
4403
4404 (define_insn_and_split "*zero_extendqisi2_31"
4405   [(set (match_operand:SI 0 "register_operand" "=&d")
4406         (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4407   "!TARGET_ZARCH"
4408   "#"
4409   "&& reload_completed"
4410   [(set (match_dup 0) (const_int 0))
4411    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4412   "operands[2] = gen_lowpart (QImode, operands[0]);")
4413
4414 ;
4415 ; zero_extendqihi2 instruction pattern(s).
4416 ;
4417
4418 (define_expand "zero_extendqihi2"
4419   [(set (match_operand:HI 0 "register_operand" "")
4420         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4421   "TARGET_ZARCH && !TARGET_EXTIMM"
4422 {
4423   operands[1] = gen_lowpart (HImode, operands[1]);
4424   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4425   DONE;
4426 })
4427
4428 (define_insn "*zero_extendqihi2_64"
4429   [(set (match_operand:HI 0 "register_operand" "=d")
4430         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4431   "TARGET_ZARCH && !TARGET_EXTIMM"
4432   "llgc\t%0,%1"
4433   [(set_attr "op_type" "RXY")
4434    (set_attr "z10prop" "z10_fwd_A3")])
4435
4436 (define_insn_and_split "*zero_extendqihi2_31"
4437   [(set (match_operand:HI 0 "register_operand" "=&d")
4438         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4439   "!TARGET_ZARCH"
4440   "#"
4441   "&& reload_completed"
4442   [(set (match_dup 0) (const_int 0))
4443    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4444   "operands[2] = gen_lowpart (QImode, operands[0]);")
4445
4446 ;
4447 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4448 ;
4449
4450 (define_expand "fixuns_truncdddi2"
4451   [(parallel
4452     [(set (match_operand:DI 0 "register_operand" "")
4453           (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4454      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4455      (clobber (reg:CC CC_REGNUM))])]
4456
4457   "TARGET_HARD_DFP"
4458 {
4459   if (!TARGET_Z196)
4460     {
4461       rtx_code_label *label1 = gen_label_rtx ();
4462       rtx_code_label *label2 = gen_label_rtx ();
4463       rtx temp = gen_reg_rtx (TDmode);
4464       REAL_VALUE_TYPE cmp, sub;
4465
4466       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4467       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4468
4469       /* 2^63 can't be represented as 64bit DFP number with full precision.  The
4470          solution is doing the check and the subtraction in TD mode and using a
4471          TD -> DI convert afterwards.  */
4472       emit_insn (gen_extendddtd2 (temp, operands[1]));
4473       temp = force_reg (TDmode, temp);
4474       emit_cmp_and_jump_insns (temp,
4475             const_double_from_real_value (cmp, TDmode),
4476             LT, NULL_RTX, VOIDmode, 0, label1);
4477       emit_insn (gen_subtd3 (temp, temp,
4478             const_double_from_real_value (sub, TDmode)));
4479       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4480       emit_jump (label2);
4481
4482       emit_label (label1);
4483       emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4484       emit_label (label2);
4485       DONE;
4486     }
4487 })
4488
4489 (define_expand "fixuns_trunctddi2"
4490   [(parallel
4491     [(set (match_operand:DI 0 "register_operand" "")
4492           (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4493      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4494      (clobber (reg:CC CC_REGNUM))])]
4495
4496   "TARGET_HARD_DFP"
4497 {
4498   if (!TARGET_Z196)
4499     {
4500       rtx_code_label *label1 = gen_label_rtx ();
4501       rtx_code_label *label2 = gen_label_rtx ();
4502       rtx temp = gen_reg_rtx (TDmode);
4503       REAL_VALUE_TYPE cmp, sub;
4504
4505       operands[1] = force_reg (TDmode, operands[1]);
4506       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4507       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4508
4509       emit_cmp_and_jump_insns (operands[1],
4510             const_double_from_real_value (cmp, TDmode),
4511             LT, NULL_RTX, VOIDmode, 0, label1);
4512       emit_insn (gen_subtd3 (temp, operands[1],
4513             const_double_from_real_value (sub, TDmode)));
4514       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4515       emit_jump (label2);
4516
4517       emit_label (label1);
4518       emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4519       emit_label (label2);
4520       DONE;
4521     }
4522 })
4523
4524 ;
4525 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4526 ; instruction pattern(s).
4527 ;
4528
4529 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4530   [(parallel
4531     [(set (match_operand:GPR 0 "register_operand" "")
4532           (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4533      (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4534      (clobber (reg:CC CC_REGNUM))])]
4535   "TARGET_HARD_FLOAT"
4536 {
4537   if (!TARGET_Z196)
4538     {
4539       rtx_code_label *label1 = gen_label_rtx ();
4540       rtx_code_label *label2 = gen_label_rtx ();
4541       rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4542       REAL_VALUE_TYPE cmp, sub;
4543
4544       operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4545       real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4546       real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4547
4548       emit_cmp_and_jump_insns (operands[1],
4549             const_double_from_real_value (cmp, <BFP:MODE>mode),
4550             LT, NULL_RTX, VOIDmode, 0, label1);
4551       emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4552             const_double_from_real_value (sub, <BFP:MODE>mode)));
4553       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4554             GEN_INT (7)));
4555       emit_jump (label2);
4556
4557       emit_label (label1);
4558       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4559             operands[1], GEN_INT (5)));
4560       emit_label (label2);
4561       DONE;
4562     }
4563 })
4564
4565 ; fixuns_trunc(td|dd)si2 expander
4566 (define_expand "fixuns_trunc<mode>si2"
4567   [(parallel
4568     [(set (match_operand:SI 0 "register_operand" "")
4569           (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4570      (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4571      (clobber (reg:CC CC_REGNUM))])]
4572   "TARGET_Z196 && TARGET_HARD_DFP"
4573   "")
4574
4575 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4576
4577 (define_insn "*fixuns_truncdfdi2_z13"
4578   [(set (match_operand:DI                  0 "register_operand" "=d,v")
4579         (unsigned_fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4580    (unspec:DI [(match_operand:DI           2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4581    (clobber (reg:CC CC_REGNUM))]
4582    "TARGET_Z13 && TARGET_HARD_FLOAT"
4583    "@
4584     clgdbr\t%0,%h2,%1,0
4585     wclgdb\t%v0,%v1,0,%h2"
4586    [(set_attr "op_type" "RRF,VRR")
4587     (set_attr "type"    "ftoi")])
4588
4589 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4590 ;         clfdtr, clfxtr,         clgdtr, clgxtr
4591 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4592   [(set (match_operand:GPR                  0 "register_operand" "=d")
4593         (unsigned_fix:GPR (match_operand:FP 1 "register_operand"  "f")))
4594    (unspec:GPR [(match_operand:GPR          2 "immediate_operand" "K")] UNSPEC_ROUND)
4595    (clobber (reg:CC CC_REGNUM))]
4596    "TARGET_Z196 && TARGET_HARD_FLOAT
4597     && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4598    "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4599    [(set_attr "op_type" "RRF")
4600     (set_attr "type"    "ftoi")])
4601
4602 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4603   [(set (match_operand:GPR 0 "register_operand" "")
4604         (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4605   "TARGET_HARD_FLOAT"
4606 {
4607   emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4608              GEN_INT (5)));
4609   DONE;
4610 })
4611
4612 (define_insn "*fix_truncdfdi2_bfp_z13"
4613   [(set (match_operand:DI         0 "register_operand" "=d,v")
4614         (fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4615    (unspec:DI [(match_operand:DI  2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4616    (clobber (reg:CC CC_REGNUM))]
4617   "TARGET_Z13 && TARGET_HARD_FLOAT"
4618   "@
4619    cgdbr\t%0,%h2,%1
4620    wcgdb\t%v0,%v1,0,%h2"
4621   [(set_attr "op_type" "RRE,VRR")
4622    (set_attr "type"    "ftoi")])
4623
4624 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4625 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4626   [(set (match_operand:GPR          0 "register_operand" "=d")
4627         (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4628    (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4629    (clobber (reg:CC CC_REGNUM))]
4630   "TARGET_HARD_FLOAT
4631     && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4632   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4633   [(set_attr "op_type" "RRE")
4634    (set_attr "type"    "ftoi")])
4635
4636 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4637   [(parallel
4638     [(set (match_operand:GPR          0 "register_operand" "=d")
4639           (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4640      (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4641      (clobber (reg:CC CC_REGNUM))])]
4642   "TARGET_HARD_FLOAT")
4643 ;
4644 ; fix_trunc(td|dd)di2 instruction pattern(s).
4645 ;
4646
4647 (define_expand "fix_trunc<mode>di2"
4648   [(set (match_operand:DI 0 "register_operand" "")
4649         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4650   "TARGET_ZARCH && TARGET_HARD_DFP"
4651 {
4652   operands[1] = force_reg (<MODE>mode, operands[1]);
4653   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4654       GEN_INT (9)));
4655   DONE;
4656 })
4657
4658 ; cgxtr, cgdtr
4659 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4660   [(set (match_operand:DI 0 "register_operand" "=d")
4661         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4662    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4663    (clobber (reg:CC CC_REGNUM))]
4664   "TARGET_ZARCH && TARGET_HARD_DFP"
4665   "cg<DFP:xde>tr\t%0,%h2,%1"
4666   [(set_attr "op_type" "RRF")
4667    (set_attr "type"    "ftoidfp")])
4668
4669
4670 ;
4671 ; fix_trunctf(si|di)2 instruction pattern(s).
4672 ;
4673
4674 (define_expand "fix_trunctf<mode>2"
4675   [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4676                    (fix:GPR (match_operand:TF 1 "register_operand" "")))
4677               (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4678               (clobber (reg:CC CC_REGNUM))])]
4679   "TARGET_HARD_FLOAT"
4680   "")
4681
4682
4683 ;
4684 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4685 ;
4686
4687 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4688 (define_insn "floatdi<mode>2"
4689   [(set (match_operand:FP           0 "register_operand" "=f,v")
4690         (float:FP (match_operand:DI 1 "register_operand"  "d,v")))]
4691   "TARGET_ZARCH && TARGET_HARD_FLOAT"
4692   "@
4693    c<xde>g<bt>r\t%0,%1
4694    wcdgb\t%v0,%v1,0,0"
4695   [(set_attr "op_type"      "RRE,VRR")
4696    (set_attr "type"         "itof<mode>" )
4697    (set_attr "cpu_facility" "*,vec")
4698    (set_attr "enabled"      "*,<DFDI>")])
4699
4700 ; cxfbr, cdfbr, cefbr
4701 (define_insn "floatsi<mode>2"
4702   [(set (match_operand:BFP 0 "register_operand" "=f")
4703         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4704   "TARGET_HARD_FLOAT"
4705   "c<xde>fbr\t%0,%1"
4706   [(set_attr "op_type" "RRE")
4707    (set_attr "type"   "itof<mode>" )])
4708
4709 ; cxftr, cdftr
4710 (define_insn "floatsi<mode>2"
4711   [(set (match_operand:DFP 0 "register_operand" "=f")
4712         (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4713   "TARGET_Z196 && TARGET_HARD_FLOAT"
4714   "c<xde>ftr\t%0,0,%1,0"
4715   [(set_attr "op_type" "RRE")
4716    (set_attr "type"   "itof<mode>" )])
4717
4718 ;
4719 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4720 ;
4721
4722 (define_insn "*floatunsdidf2_z13"
4723   [(set (match_operand:DF                    0 "register_operand" "=f,v")
4724         (unsigned_float:DF (match_operand:DI 1 "register_operand"  "d,v")))]
4725   "TARGET_Z13 && TARGET_HARD_FLOAT"
4726   "@
4727    cdlgbr\t%0,0,%1,0
4728    wcdlgb\t%v0,%v1,0,0"
4729   [(set_attr "op_type" "RRE,VRR")
4730    (set_attr "type"    "itofdf")])
4731
4732 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4733 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4734 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4735   [(set (match_operand:FP                     0 "register_operand" "=f")
4736         (unsigned_float:FP (match_operand:GPR 1 "register_operand"  "d")))]
4737   "TARGET_Z196 && TARGET_HARD_FLOAT
4738    && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4739   "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4740   [(set_attr "op_type" "RRE")
4741    (set_attr "type"    "itof<FP:mode>")])
4742
4743 (define_expand "floatuns<GPR:mode><FP:mode>2"
4744   [(set (match_operand:FP                     0 "register_operand" "")
4745         (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4746   "TARGET_Z196 && TARGET_HARD_FLOAT")
4747
4748 ;
4749 ; truncdfsf2 instruction pattern(s).
4750 ;
4751
4752 (define_insn "truncdfsf2"
4753   [(set (match_operand:SF                    0 "register_operand" "=f,v")
4754         (float_truncate:SF (match_operand:DF 1 "register_operand"  "f,v")))]
4755   "TARGET_HARD_FLOAT"
4756   "@
4757    ledbr\t%0,%1
4758    wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4759                        ; According to BFP rounding mode
4760   [(set_attr "op_type"      "RRE,VRR")
4761    (set_attr "type"         "ftruncdf")
4762    (set_attr "cpu_facility" "*,vec")])
4763
4764 ;
4765 ; trunctf(df|sf)2 instruction pattern(s).
4766 ;
4767
4768 ; ldxbr, lexbr
4769 (define_insn "trunctf<mode>2"
4770   [(set (match_operand:DSF 0 "register_operand" "=f")
4771         (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4772    (clobber (match_scratch:TF 2 "=f"))]
4773   "TARGET_HARD_FLOAT"
4774   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4775   [(set_attr "length" "6")
4776    (set_attr "type"   "ftrunctf")])
4777
4778 ;
4779 ; trunctddd2 and truncddsd2 instruction pattern(s).
4780 ;
4781
4782 (define_insn "trunctddd2"
4783   [(set (match_operand:DD 0 "register_operand" "=f")
4784         (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4785    (clobber (match_scratch:TD 2 "=f"))]
4786   "TARGET_HARD_DFP"
4787   "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4788   [(set_attr "length"  "6")
4789    (set_attr "type"    "ftruncdd")])
4790
4791 (define_insn "truncddsd2"
4792   [(set (match_operand:SD 0 "register_operand" "=f")
4793         (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4794   "TARGET_HARD_DFP"
4795   "ledtr\t%0,0,%1,0"
4796   [(set_attr "op_type" "RRF")
4797    (set_attr "type"    "ftruncsd")])
4798
4799 (define_expand "trunctdsd2"
4800   [(parallel
4801     [(set (match_dup 3)
4802           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4803      (clobber (match_scratch:TD 2 ""))])
4804    (set (match_operand:SD 0 "register_operand" "")
4805         (float_truncate:SD (match_dup 3)))]
4806   "TARGET_HARD_DFP"
4807 {
4808   operands[3] = gen_reg_rtx (DDmode);
4809 })
4810
4811 ;
4812 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4813 ;
4814
4815 (define_insn "*extendsfdf2_z13"
4816   [(set (match_operand:DF                  0 "register_operand"     "=f,f,v")
4817         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R,v")))]
4818   "TARGET_Z13 && TARGET_HARD_FLOAT"
4819   "@
4820    ldebr\t%0,%1
4821    ldeb\t%0,%1
4822    wldeb\t%v0,%v1"
4823   [(set_attr "op_type" "RRE,RXE,VRR")
4824    (set_attr "type"    "fsimpdf, floaddf,fsimpdf")])
4825
4826 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4827 (define_insn "*extend<DSF:mode><BFP:mode>2"
4828   [(set (match_operand:BFP                   0 "register_operand"     "=f,f")
4829         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
4830   "TARGET_HARD_FLOAT
4831    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4832    && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4833   "@
4834    l<BFP:xde><DSF:xde>br\t%0,%1
4835    l<BFP:xde><DSF:xde>b\t%0,%1"
4836   [(set_attr "op_type" "RRE,RXE")
4837    (set_attr "type"    "fsimp<BFP:mode>, fload<BFP:mode>")])
4838
4839 (define_expand "extend<DSF:mode><BFP:mode>2"
4840   [(set (match_operand:BFP                   0 "register_operand"     "")
4841         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4842   "TARGET_HARD_FLOAT
4843    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4844
4845 ;
4846 ; extendddtd2 and extendsddd2 instruction pattern(s).
4847 ;
4848
4849 (define_insn "extendddtd2"
4850   [(set (match_operand:TD 0 "register_operand" "=f")
4851         (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4852   "TARGET_HARD_DFP"
4853   "lxdtr\t%0,%1,0"
4854   [(set_attr "op_type" "RRF")
4855    (set_attr "type"    "fsimptf")])
4856
4857 (define_insn "extendsddd2"
4858   [(set (match_operand:DD 0 "register_operand" "=f")
4859         (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4860   "TARGET_HARD_DFP"
4861   "ldetr\t%0,%1,0"
4862   [(set_attr "op_type" "RRF")
4863    (set_attr "type"    "fsimptf")])
4864
4865 (define_expand "extendsdtd2"
4866   [(set (match_dup 2)
4867         (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4868    (set (match_operand:TD 0 "register_operand" "")
4869         (float_extend:TD (match_dup 2)))]
4870   "TARGET_HARD_DFP"
4871 {
4872   operands[2] = gen_reg_rtx (DDmode);
4873 })
4874
4875 ; Binary Floating Point - load fp integer
4876
4877 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4878 ; For all of them the inexact exceptions are suppressed.
4879
4880 ; fiebra, fidbra, fixbra
4881 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4882   [(set (match_operand:BFP 0 "register_operand" "=f")
4883         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4884                     FPINT))]
4885   "TARGET_Z196"
4886   "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4887   [(set_attr "op_type"   "RRF")
4888    (set_attr "type"      "fsimp<BFP:mode>")])
4889
4890 ; rint is supposed to raise an inexact exception so we can use the
4891 ; older instructions.
4892
4893 ; fiebr, fidbr, fixbr
4894 (define_insn "rint<BFP:mode>2"
4895   [(set (match_operand:BFP 0 "register_operand" "=f")
4896         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4897                     UNSPEC_FPINT_RINT))]
4898   ""
4899   "fi<BFP:xde>br\t%0,0,%1"
4900   [(set_attr "op_type"   "RRF")
4901    (set_attr "type"      "fsimp<BFP:mode>")])
4902
4903
4904 ; Decimal Floating Point - load fp integer
4905
4906 ; fidtr, fixtr
4907 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4908   [(set (match_operand:DFP 0 "register_operand" "=f")
4909         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4910                     FPINT))]
4911   "TARGET_HARD_DFP"
4912   "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4913   [(set_attr "op_type"   "RRF")
4914    (set_attr "type"      "fsimp<DFP:mode>")])
4915
4916 ; fidtr, fixtr
4917 (define_insn "rint<DFP:mode>2"
4918   [(set (match_operand:DFP 0 "register_operand" "=f")
4919         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4920                     UNSPEC_FPINT_RINT))]
4921   "TARGET_HARD_DFP"
4922   "fi<DFP:xde>tr\t%0,0,%1,0"
4923   [(set_attr "op_type"   "RRF")
4924    (set_attr "type"      "fsimp<DFP:mode>")])
4925
4926 ;
4927 ; Binary <-> Decimal floating point trunc patterns
4928 ;
4929
4930 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4931   [(set (reg:DFP_ALL FPR0_REGNUM)
4932         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4933    (use (reg:SI GPR0_REGNUM))
4934    (clobber (reg:CC CC_REGNUM))
4935    (clobber (reg:SI GPR1_REGNUM))]
4936   "TARGET_HARD_DFP"
4937   "pfpo")
4938
4939 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4940   [(set (reg:BFP FPR0_REGNUM)
4941         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4942    (use (reg:SI GPR0_REGNUM))
4943    (clobber (reg:CC CC_REGNUM))
4944    (clobber (reg:SI GPR1_REGNUM))]
4945   "TARGET_HARD_DFP"
4946   "pfpo")
4947
4948 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4949   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4950    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4951    (parallel
4952     [(set (reg:DFP_ALL FPR0_REGNUM)
4953           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4954      (use (reg:SI GPR0_REGNUM))
4955      (clobber (reg:CC CC_REGNUM))
4956      (clobber (reg:SI GPR1_REGNUM))])
4957    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4958         (reg:DFP_ALL FPR0_REGNUM))]
4959   "TARGET_HARD_DFP
4960    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4961 {
4962   HOST_WIDE_INT flags;
4963
4964   flags = (PFPO_CONVERT |
4965            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4966            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4967
4968   operands[2] = GEN_INT (flags);
4969 })
4970
4971 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4972   [(set (reg:DFP_ALL FPR4_REGNUM)
4973         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4974    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4975    (parallel
4976     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4977      (use (reg:SI GPR0_REGNUM))
4978      (clobber (reg:CC CC_REGNUM))
4979      (clobber (reg:SI GPR1_REGNUM))])
4980    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4981   "TARGET_HARD_DFP
4982    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4983 {
4984   HOST_WIDE_INT flags;
4985
4986   flags = (PFPO_CONVERT |
4987            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4988            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4989
4990   operands[2] = GEN_INT (flags);
4991 })
4992
4993 ;
4994 ; Binary <-> Decimal floating point extend patterns
4995 ;
4996
4997 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4998   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4999    (use (reg:SI GPR0_REGNUM))
5000    (clobber (reg:CC CC_REGNUM))
5001    (clobber (reg:SI GPR1_REGNUM))]
5002   "TARGET_HARD_DFP"
5003   "pfpo")
5004
5005 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5006   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5007    (use (reg:SI GPR0_REGNUM))
5008    (clobber (reg:CC CC_REGNUM))
5009    (clobber (reg:SI GPR1_REGNUM))]
5010   "TARGET_HARD_DFP"
5011   "pfpo")
5012
5013 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5014   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5015    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5016    (parallel
5017     [(set (reg:DFP_ALL FPR0_REGNUM)
5018           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5019      (use (reg:SI GPR0_REGNUM))
5020      (clobber (reg:CC CC_REGNUM))
5021      (clobber (reg:SI GPR1_REGNUM))])
5022    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5023         (reg:DFP_ALL FPR0_REGNUM))]
5024   "TARGET_HARD_DFP
5025    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5026 {
5027   HOST_WIDE_INT flags;
5028
5029   flags = (PFPO_CONVERT |
5030            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5031            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5032
5033   operands[2] = GEN_INT (flags);
5034 })
5035
5036 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5037   [(set (reg:DFP_ALL FPR4_REGNUM)
5038         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5039    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5040    (parallel
5041     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5042      (use (reg:SI GPR0_REGNUM))
5043      (clobber (reg:CC CC_REGNUM))
5044      (clobber (reg:SI GPR1_REGNUM))])
5045    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5046   "TARGET_HARD_DFP
5047    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5048 {
5049   HOST_WIDE_INT flags;
5050
5051   flags = (PFPO_CONVERT |
5052            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5053            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5054
5055   operands[2] = GEN_INT (flags);
5056 })
5057
5058
5059 ;;
5060 ;; ARITHMETIC OPERATIONS
5061 ;;
5062 ;  arithmetic operations set the ConditionCode,
5063 ;  because of unpredictable Bits in Register for Halfword and Byte
5064 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
5065
5066 ;;
5067 ;;- Add instructions.
5068 ;;
5069
5070 ;
5071 ; addti3 instruction pattern(s).
5072 ;
5073
5074 (define_expand "addti3"
5075   [(parallel
5076     [(set (match_operand:TI          0 "register_operand"     "")
5077           (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5078                    (match_operand:TI 2 "general_operand"      "") ) )
5079      (clobber (reg:CC CC_REGNUM))])]
5080   "TARGET_ZARCH"
5081 {
5082   /* For z13 we have vaq which doesn't set CC.  */
5083   if (TARGET_VX)
5084     {
5085       emit_insn (gen_rtx_SET (operands[0],
5086                               gen_rtx_PLUS (TImode,
5087                                             copy_to_mode_reg (TImode, operands[1]),
5088                                             copy_to_mode_reg (TImode, operands[2]))));
5089       DONE;
5090     }
5091 })
5092
5093 (define_insn_and_split "*addti3"
5094   [(set (match_operand:TI          0 "register_operand"    "=&d")
5095         (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5096                  (match_operand:TI 2 "general_operand"      "do") ) )
5097    (clobber (reg:CC CC_REGNUM))]
5098   "TARGET_ZARCH"
5099   "#"
5100   "&& reload_completed"
5101   [(parallel
5102     [(set (reg:CCL1 CC_REGNUM)
5103           (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5104                         (match_dup 7)))
5105      (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5106    (parallel
5107     [(set (match_dup 3) (plus:DI
5108                           (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5109                                    (match_dup 4)) (match_dup 5)))
5110      (clobber (reg:CC CC_REGNUM))])]
5111   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5112    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5113    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5114    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5115    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5116    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5117   [(set_attr "op_type"  "*")
5118    (set_attr "cpu_facility" "*")])
5119
5120 ;
5121 ; adddi3 instruction pattern(s).
5122 ;
5123
5124 (define_expand "adddi3"
5125   [(parallel
5126     [(set (match_operand:DI 0 "nonimmediate_operand" "")
5127           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5128                    (match_operand:DI 2 "general_operand" "")))
5129      (clobber (reg:CC CC_REGNUM))])]
5130   ""
5131   "")
5132
5133 (define_insn "*adddi3_sign"
5134   [(set (match_operand:DI 0 "register_operand" "=d,d")
5135         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5136                  (match_operand:DI 1 "register_operand" "0,0")))
5137    (clobber (reg:CC CC_REGNUM))]
5138   "TARGET_ZARCH"
5139   "@
5140    agfr\t%0,%2
5141    agf\t%0,%2"
5142   [(set_attr "op_type"  "RRE,RXY")
5143    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5144
5145 (define_insn "*adddi3_zero_cc"
5146   [(set (reg CC_REGNUM)
5147         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5148                           (match_operand:DI 1 "register_operand" "0,0"))
5149                  (const_int 0)))
5150    (set (match_operand:DI 0 "register_operand" "=d,d")
5151         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5152   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5153   "@
5154    algfr\t%0,%2
5155    algf\t%0,%2"
5156   [(set_attr "op_type"  "RRE,RXY")
5157    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5158
5159 (define_insn "*adddi3_zero_cconly"
5160   [(set (reg CC_REGNUM)
5161         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5162                           (match_operand:DI 1 "register_operand" "0,0"))
5163                  (const_int 0)))
5164    (clobber (match_scratch:DI 0 "=d,d"))]
5165   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5166   "@
5167    algfr\t%0,%2
5168    algf\t%0,%2"
5169   [(set_attr "op_type"  "RRE,RXY")
5170    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5171
5172 (define_insn "*adddi3_zero"
5173   [(set (match_operand:DI 0 "register_operand" "=d,d")
5174         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5175                  (match_operand:DI 1 "register_operand" "0,0")))
5176    (clobber (reg:CC CC_REGNUM))]
5177   "TARGET_ZARCH"
5178   "@
5179    algfr\t%0,%2
5180    algf\t%0,%2"
5181   [(set_attr "op_type"  "RRE,RXY")
5182    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5183
5184 (define_insn_and_split "*adddi3_31z"
5185   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5186         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5187                  (match_operand:DI 2 "general_operand" "do") ) )
5188    (clobber (reg:CC CC_REGNUM))]
5189   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5190   "#"
5191   "&& reload_completed"
5192   [(parallel
5193     [(set (reg:CCL1 CC_REGNUM)
5194           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5195                         (match_dup 7)))
5196      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5197    (parallel
5198     [(set (match_dup 3) (plus:SI
5199                           (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5200                                    (match_dup 4)) (match_dup 5)))
5201      (clobber (reg:CC CC_REGNUM))])]
5202   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5203    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5204    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5205    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5206    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5207    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5208
5209 (define_insn_and_split "*adddi3_31"
5210   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5211         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5212                  (match_operand:DI 2 "general_operand" "do") ) )
5213    (clobber (reg:CC CC_REGNUM))]
5214   "!TARGET_CPU_ZARCH"
5215   "#"
5216   "&& reload_completed"
5217   [(parallel
5218     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5219      (clobber (reg:CC CC_REGNUM))])
5220    (parallel
5221     [(set (reg:CCL1 CC_REGNUM)
5222           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5223                         (match_dup 7)))
5224      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5225    (set (pc)
5226         (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5227                       (pc)
5228                       (label_ref (match_dup 9))))
5229    (parallel
5230     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5231      (clobber (reg:CC CC_REGNUM))])
5232    (match_dup 9)]
5233   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5234    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5235    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5236    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5237    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5238    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5239    operands[9] = gen_label_rtx ();")
5240
5241 ;
5242 ; addsi3 instruction pattern(s).
5243 ;
5244
5245 (define_expand "addsi3"
5246   [(parallel
5247     [(set (match_operand:SI 0 "nonimmediate_operand" "")
5248           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5249                    (match_operand:SI 2 "general_operand" "")))
5250      (clobber (reg:CC CC_REGNUM))])]
5251   ""
5252   "")
5253
5254 (define_insn "*addsi3_sign"
5255   [(set (match_operand:SI 0 "register_operand" "=d,d")
5256         (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5257                  (match_operand:SI 1 "register_operand" "0,0")))
5258    (clobber (reg:CC CC_REGNUM))]
5259   ""
5260   "@
5261    ah\t%0,%2
5262    ahy\t%0,%2"
5263   [(set_attr "op_type"  "RX,RXY")
5264    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5265
5266 ;
5267 ; add(di|si)3 instruction pattern(s).
5268 ;
5269
5270 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5271 (define_insn "*add<mode>3"
5272   [(set (match_operand:GPR 0 "nonimmediate_operand"           "=d,d,d,d, d, d,d,d,QS")
5273         (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
5274                   (match_operand:GPR 2 "general_operand"      " d,d,K,K,Op,On,R,T, C") ) )
5275    (clobber (reg:CC CC_REGNUM))]
5276   ""
5277   "@
5278    a<g>r\t%0,%2
5279    a<g>rk\t%0,%1,%2
5280    a<g>hi\t%0,%h2
5281    a<g>hik\t%0,%1,%h2
5282    al<g>fi\t%0,%2
5283    sl<g>fi\t%0,%n2
5284    a<g>\t%0,%2
5285    a<y>\t%0,%2
5286    a<g>si\t%0,%c2"
5287   [(set_attr "op_type"  "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5288    (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
5289    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5290                         z10_super_E1,z10_super_E1,z10_super_E1")])
5291
5292 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5293 (define_insn "*add<mode>3_carry1_cc"
5294   [(set (reg CC_REGNUM)
5295         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5296                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5297                  (match_dup 1)))
5298    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,d")
5299         (plus:GPR (match_dup 1) (match_dup 2)))]
5300   "s390_match_ccmode (insn, CCL1mode)"
5301   "@
5302    al<g>r\t%0,%2
5303    al<g>rk\t%0,%1,%2
5304    al<g>fi\t%0,%2
5305    sl<g>fi\t%0,%n2
5306    al<g>hsik\t%0,%1,%h2
5307    al<g>\t%0,%2
5308    al<y>\t%0,%2
5309    al<g>si\t%0,%c2"
5310   [(set_attr "op_type"      "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5311    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5312    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5313                         z10_super_E1,z10_super_E1,z10_super_E1")])
5314
5315 ; alr, al, aly, algr, alg, alrk, algrk
5316 (define_insn "*add<mode>3_carry1_cconly"
5317   [(set (reg CC_REGNUM)
5318         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5319                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5320                  (match_dup 1)))
5321    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5322   "s390_match_ccmode (insn, CCL1mode)"
5323   "@
5324    al<g>r\t%0,%2
5325    al<g>rk\t%0,%1,%2
5326    al<g>\t%0,%2
5327    al<y>\t%0,%2"
5328   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5329    (set_attr "cpu_facility" "*,z196,*,*")
5330    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5331
5332 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5333 (define_insn "*add<mode>3_carry2_cc"
5334   [(set (reg CC_REGNUM)
5335         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5336                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5337                  (match_dup 2)))
5338    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5339         (plus:GPR (match_dup 1) (match_dup 2)))]
5340   "s390_match_ccmode (insn, CCL1mode)"
5341   "@
5342    al<g>r\t%0,%2
5343    al<g>rk\t%0,%1,%2
5344    al<g>fi\t%0,%2
5345    sl<g>fi\t%0,%n2
5346    al<g>hsik\t%0,%1,%h2
5347    al<g>\t%0,%2
5348    al<y>\t%0,%2
5349    al<g>si\t%0,%c2"
5350   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5351    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5352    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5353                         z10_super_E1,z10_super_E1,z10_super_E1")])
5354
5355 ; alr, al, aly, algr, alg, alrk, algrk
5356 (define_insn "*add<mode>3_carry2_cconly"
5357   [(set (reg CC_REGNUM)
5358         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5359                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5360                  (match_dup 2)))
5361    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5362   "s390_match_ccmode (insn, CCL1mode)"
5363   "@
5364    al<g>r\t%0,%2
5365    al<g>rk\t%0,%1,%2
5366    al<g>\t%0,%2
5367    al<y>\t%0,%2"
5368   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5369    (set_attr "cpu_facility" "*,z196,*,*")
5370    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5371
5372 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5373 (define_insn "*add<mode>3_cc"
5374   [(set (reg CC_REGNUM)
5375         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5376                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5377                  (const_int 0)))
5378    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5379         (plus:GPR (match_dup 1) (match_dup 2)))]
5380   "s390_match_ccmode (insn, CCLmode)"
5381   "@
5382    al<g>r\t%0,%2
5383    al<g>rk\t%0,%1,%2
5384    al<g>fi\t%0,%2
5385    sl<g>fi\t%0,%n2
5386    al<g>hsik\t%0,%1,%h2
5387    al<g>\t%0,%2
5388    al<y>\t%0,%2
5389    al<g>si\t%0,%c2"
5390   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5391    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5392    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5393                         *,z10_super_E1,z10_super_E1,z10_super_E1")])
5394
5395 ; alr, al, aly, algr, alg, alrk, algrk
5396 (define_insn "*add<mode>3_cconly"
5397   [(set (reg CC_REGNUM)
5398         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5399                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5400                  (const_int 0)))
5401    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5402   "s390_match_ccmode (insn, CCLmode)"
5403   "@
5404    al<g>r\t%0,%2
5405    al<g>rk\t%0,%1,%2
5406    al<g>\t%0,%2
5407    al<y>\t%0,%2"
5408   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5409    (set_attr "cpu_facility" "*,z196,*,*")
5410    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5411
5412 ; alr, al, aly, algr, alg, alrk, algrk
5413 (define_insn "*add<mode>3_cconly2"
5414   [(set (reg CC_REGNUM)
5415         (compare (match_operand:GPR 1 "nonimmediate_operand"    "%0,d,0,0")
5416                  (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5417    (clobber (match_scratch:GPR 0                                "=d,d,d,d"))]
5418   "s390_match_ccmode(insn, CCLmode)"
5419   "@
5420    al<g>r\t%0,%2
5421    al<g>rk\t%0,%1,%2
5422    al<g>\t%0,%2
5423    al<y>\t%0,%2"
5424   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5425    (set_attr "cpu_facility" "*,z196,*,*")
5426    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5427
5428 ; ahi, afi, aghi, agfi, asi, agsi
5429 (define_insn "*add<mode>3_imm_cc"
5430   [(set (reg CC_REGNUM)
5431         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5432                            (match_operand:GPR 2 "const_int_operand"    " K, K,Os, C"))
5433                  (const_int 0)))
5434    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d, d,d,QS")
5435         (plus:GPR (match_dup 1) (match_dup 2)))]
5436   "s390_match_ccmode (insn, CCAmode)
5437    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5438        || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5439            /* Avoid INT32_MIN on 32 bit.  */
5440            && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5441   "@
5442    a<g>hi\t%0,%h2
5443    a<g>hik\t%0,%1,%h2
5444    a<g>fi\t%0,%2
5445    a<g>si\t%0,%c2"
5446   [(set_attr "op_type"      "RI,RIE,RIL,SIY")
5447    (set_attr "cpu_facility" "*,z196,extimm,z10")
5448    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5449
5450 ;
5451 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5452 ;
5453
5454 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5455 ; FIXME: wfadb does not clobber cc
5456 (define_insn "add<mode>3"
5457   [(set (match_operand:FP 0 "register_operand"              "=f,f,f,v")
5458         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5459                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))
5460    (clobber (reg:CC CC_REGNUM))]
5461   "TARGET_HARD_FLOAT"
5462   "@
5463    a<xde>tr\t%0,%1,%2
5464    a<xde>br\t%0,%2
5465    a<xde>b\t%0,%2
5466    wfadb\t%v0,%v1,%v2"
5467   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
5468    (set_attr "type"         "fsimp<mode>")
5469    (set_attr "cpu_facility" "*,*,*,vec")
5470    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5471
5472 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5473 (define_insn "*add<mode>3_cc"
5474   [(set (reg CC_REGNUM)
5475         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5476                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5477                  (match_operand:FP 3 "const0_operand" "")))
5478    (set (match_operand:FP 0 "register_operand" "=f,f,f")
5479         (plus:FP (match_dup 1) (match_dup 2)))]
5480   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5481   "@
5482    a<xde>tr\t%0,%1,%2
5483    a<xde>br\t%0,%2
5484    a<xde>b\t%0,%2"
5485   [(set_attr "op_type"  "RRF,RRE,RXE")
5486    (set_attr "type"     "fsimp<mode>")
5487    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5488
5489 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5490 (define_insn "*add<mode>3_cconly"
5491   [(set (reg CC_REGNUM)
5492         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5493                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5494                  (match_operand:FP 3 "const0_operand" "")))
5495    (clobber (match_scratch:FP 0 "=f,f,f"))]
5496   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5497   "@
5498    a<xde>tr\t%0,%1,%2
5499    a<xde>br\t%0,%2
5500    a<xde>b\t%0,%2"
5501   [(set_attr "op_type"  "RRF,RRE,RXE")
5502    (set_attr "type"     "fsimp<mode>")
5503    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5504
5505 ;
5506 ; Pointer add instruction patterns
5507 ;
5508
5509 ; This will match "*la_64"
5510 (define_expand "addptrdi3"
5511   [(set (match_operand:DI 0 "register_operand" "")
5512         (plus:DI (match_operand:DI 1 "register_operand" "")
5513                  (match_operand:DI 2 "nonmemory_operand" "")))]
5514   "TARGET_64BIT"
5515 {
5516   if (GET_CODE (operands[2]) == CONST_INT)
5517     {
5518       HOST_WIDE_INT c = INTVAL (operands[2]);
5519
5520       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5521           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5522         {
5523           operands[2] = force_const_mem (DImode, operands[2]);
5524           operands[2] = force_reg (DImode, operands[2]);
5525         }
5526       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5527         operands[2] = force_reg (DImode, operands[2]);
5528     }
5529 })
5530
5531 ; For 31 bit we have to prevent the generated pattern from matching
5532 ; normal ADDs since la only does a 31 bit add.  This is supposed to
5533 ; match "force_la_31".
5534 (define_expand "addptrsi3"
5535   [(parallel
5536     [(set (match_operand:SI 0 "register_operand" "")
5537           (plus:SI (match_operand:SI 1 "register_operand" "")
5538                    (match_operand:SI 2 "nonmemory_operand" "")))
5539                    (use (const_int 0))])]
5540   "!TARGET_64BIT"
5541 {
5542   if (GET_CODE (operands[2]) == CONST_INT)
5543     {
5544       HOST_WIDE_INT c = INTVAL (operands[2]);
5545
5546       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5547           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5548         {
5549           operands[2] = force_const_mem (SImode, operands[2]);
5550           operands[2] = force_reg (SImode, operands[2]);
5551         }
5552       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5553         operands[2] = force_reg (SImode, operands[2]);
5554     }
5555 })
5556
5557 ;;
5558 ;;- Subtract instructions.
5559 ;;
5560
5561 ;
5562 ; subti3 instruction pattern(s).
5563 ;
5564
5565 (define_expand "subti3"
5566   [(parallel
5567     [(set (match_operand:TI           0 "register_operand" "")
5568           (minus:TI (match_operand:TI 1 "register_operand" "")
5569                     (match_operand:TI 2 "general_operand"  "") ) )
5570      (clobber (reg:CC CC_REGNUM))])]
5571   "TARGET_ZARCH"
5572 {
5573   /* For z13 we have vaq which doesn't set CC.  */
5574   if (TARGET_VX)
5575     {
5576       emit_insn (gen_rtx_SET (operands[0],
5577                               gen_rtx_MINUS (TImode,
5578                                             operands[1],
5579                                             copy_to_mode_reg (TImode, operands[2]))));
5580       DONE;
5581     }
5582 })
5583
5584 (define_insn_and_split "*subti3"
5585   [(set (match_operand:TI           0 "register_operand" "=&d")
5586         (minus:TI (match_operand:TI 1 "register_operand"   "0")
5587                   (match_operand:TI 2 "general_operand"   "do") ) )
5588    (clobber (reg:CC CC_REGNUM))]
5589   "TARGET_ZARCH"
5590   "#"
5591   "&& reload_completed"
5592   [(parallel
5593     [(set (reg:CCL2 CC_REGNUM)
5594           (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5595                         (match_dup 7)))
5596      (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5597    (parallel
5598     [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5599                                   (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5600      (clobber (reg:CC CC_REGNUM))])]
5601   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5602    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5603    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5604    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5605    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5606    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5607   [(set_attr "op_type"      "*")
5608    (set_attr "cpu_facility" "*")])
5609
5610 ;
5611 ; subdi3 instruction pattern(s).
5612 ;
5613
5614 (define_expand "subdi3"
5615   [(parallel
5616     [(set (match_operand:DI 0 "register_operand" "")
5617           (minus:DI (match_operand:DI 1 "register_operand" "")
5618                     (match_operand:DI 2 "general_operand" "")))
5619      (clobber (reg:CC CC_REGNUM))])]
5620   ""
5621   "")
5622
5623 (define_insn "*subdi3_sign"
5624   [(set (match_operand:DI 0 "register_operand" "=d,d")
5625         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5626                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5627    (clobber (reg:CC CC_REGNUM))]
5628   "TARGET_ZARCH"
5629   "@
5630    sgfr\t%0,%2
5631    sgf\t%0,%2"
5632   [(set_attr "op_type"  "RRE,RXY")
5633    (set_attr "z10prop" "z10_c,*")
5634    (set_attr "z196prop" "z196_cracked")])
5635
5636 (define_insn "*subdi3_zero_cc"
5637   [(set (reg CC_REGNUM)
5638         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5639                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5640                  (const_int 0)))
5641    (set (match_operand:DI 0 "register_operand" "=d,d")
5642         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5643   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5644   "@
5645    slgfr\t%0,%2
5646    slgf\t%0,%2"
5647   [(set_attr "op_type"  "RRE,RXY")
5648    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5649
5650 (define_insn "*subdi3_zero_cconly"
5651   [(set (reg CC_REGNUM)
5652         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5653                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5654                  (const_int 0)))
5655    (clobber (match_scratch:DI 0 "=d,d"))]
5656   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5657   "@
5658    slgfr\t%0,%2
5659    slgf\t%0,%2"
5660   [(set_attr "op_type"  "RRE,RXY")
5661    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5662
5663 (define_insn "*subdi3_zero"
5664   [(set (match_operand:DI 0 "register_operand" "=d,d")
5665         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5666                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5667    (clobber (reg:CC CC_REGNUM))]
5668   "TARGET_ZARCH"
5669   "@
5670    slgfr\t%0,%2
5671    slgf\t%0,%2"
5672   [(set_attr "op_type"  "RRE,RXY")
5673    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5674
5675 (define_insn_and_split "*subdi3_31z"
5676   [(set (match_operand:DI 0 "register_operand" "=&d")
5677         (minus:DI (match_operand:DI 1 "register_operand" "0")
5678                   (match_operand:DI 2 "general_operand" "do") ) )
5679    (clobber (reg:CC CC_REGNUM))]
5680   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5681   "#"
5682   "&& reload_completed"
5683   [(parallel
5684     [(set (reg:CCL2 CC_REGNUM)
5685           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5686                         (match_dup 7)))
5687      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5688    (parallel
5689     [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5690                                   (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5691      (clobber (reg:CC CC_REGNUM))])]
5692   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5693    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5694    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5695    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5696    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5697    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5698
5699 (define_insn_and_split "*subdi3_31"
5700   [(set (match_operand:DI 0 "register_operand" "=&d")
5701         (minus:DI (match_operand:DI 1 "register_operand" "0")
5702                   (match_operand:DI 2 "general_operand" "do") ) )
5703    (clobber (reg:CC CC_REGNUM))]
5704   "!TARGET_CPU_ZARCH"
5705   "#"
5706   "&& reload_completed"
5707   [(parallel
5708     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5709      (clobber (reg:CC CC_REGNUM))])
5710    (parallel
5711     [(set (reg:CCL2 CC_REGNUM)
5712           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5713                         (match_dup 7)))
5714      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5715    (set (pc)
5716         (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5717                       (pc)
5718                       (label_ref (match_dup 9))))
5719    (parallel
5720     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5721      (clobber (reg:CC CC_REGNUM))])
5722    (match_dup 9)]
5723   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5724    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5725    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5726    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5727    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5728    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5729    operands[9] = gen_label_rtx ();")
5730
5731 ;
5732 ; subsi3 instruction pattern(s).
5733 ;
5734
5735 (define_expand "subsi3"
5736   [(parallel
5737     [(set (match_operand:SI 0 "register_operand" "")
5738           (minus:SI (match_operand:SI 1 "register_operand" "")
5739                     (match_operand:SI 2 "general_operand" "")))
5740      (clobber (reg:CC CC_REGNUM))])]
5741   ""
5742   "")
5743
5744 (define_insn "*subsi3_sign"
5745   [(set (match_operand:SI 0 "register_operand" "=d,d")
5746         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5747                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5748    (clobber (reg:CC CC_REGNUM))]
5749   ""
5750   "@
5751    sh\t%0,%2
5752    shy\t%0,%2"
5753   [(set_attr "op_type"  "RX,RXY")
5754    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5755
5756 ;
5757 ; sub(di|si)3 instruction pattern(s).
5758 ;
5759
5760 ; sr, s, sy, sgr, sg, srk, sgrk
5761 (define_insn "*sub<mode>3"
5762   [(set (match_operand:GPR 0 "register_operand"           "=d,d,d,d")
5763         (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5764                    (match_operand:GPR 2 "general_operand"  "d,d,R,T") ) )
5765    (clobber (reg:CC CC_REGNUM))]
5766   ""
5767   "@
5768    s<g>r\t%0,%2
5769    s<g>rk\t%0,%1,%2
5770    s<g>\t%0,%2
5771    s<y>\t%0,%2"
5772   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5773    (set_attr "cpu_facility" "*,z196,*,*")
5774    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5775
5776 ; slr, sl, sly, slgr, slg, slrk, slgrk
5777 (define_insn "*sub<mode>3_borrow_cc"
5778   [(set (reg CC_REGNUM)
5779         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5780                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5781                  (match_dup 1)))
5782    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5783         (minus:GPR (match_dup 1) (match_dup 2)))]
5784   "s390_match_ccmode (insn, CCL2mode)"
5785   "@
5786    sl<g>r\t%0,%2
5787    sl<g>rk\t%0,%1,%2
5788    sl<g>\t%0,%2
5789    sl<y>\t%0,%2"
5790   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5791    (set_attr "cpu_facility" "*,z196,*,*")
5792    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5793
5794 ; slr, sl, sly, slgr, slg, slrk, slgrk
5795 (define_insn "*sub<mode>3_borrow_cconly"
5796   [(set (reg CC_REGNUM)
5797         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5798                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5799                  (match_dup 1)))
5800    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5801   "s390_match_ccmode (insn, CCL2mode)"
5802   "@
5803    sl<g>r\t%0,%2
5804    sl<g>rk\t%0,%1,%2
5805    sl<g>\t%0,%2
5806    sl<y>\t%0,%2"
5807   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5808    (set_attr "cpu_facility" "*,z196,*,*")
5809    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5810
5811 ; slr, sl, sly, slgr, slg, slrk, slgrk
5812 (define_insn "*sub<mode>3_cc"
5813   [(set (reg CC_REGNUM)
5814         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5815                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5816                  (const_int 0)))
5817    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5818         (minus:GPR (match_dup 1) (match_dup 2)))]
5819   "s390_match_ccmode (insn, CCLmode)"
5820   "@
5821    sl<g>r\t%0,%2
5822    sl<g>rk\t%0,%1,%2
5823    sl<g>\t%0,%2
5824    sl<y>\t%0,%2"
5825   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5826    (set_attr "cpu_facility" "*,z196,*,*")
5827    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5828
5829 ; slr, sl, sly, slgr, slg, slrk, slgrk
5830 (define_insn "*sub<mode>3_cc2"
5831   [(set (reg CC_REGNUM)
5832         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5833                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5834    (set (match_operand:GPR 0 "register_operand"         "=d,d,d,d")
5835         (minus:GPR (match_dup 1) (match_dup 2)))]
5836   "s390_match_ccmode (insn, CCL3mode)"
5837   "@
5838    sl<g>r\t%0,%2
5839    sl<g>rk\t%0,%1,%2
5840    sl<g>\t%0,%2
5841    sl<y>\t%0,%2"
5842   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5843    (set_attr "cpu_facility" "*,z196,*,*")
5844    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5845
5846 ; slr, sl, sly, slgr, slg, slrk, slgrk
5847 (define_insn "*sub<mode>3_cconly"
5848   [(set (reg CC_REGNUM)
5849         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5850                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5851                  (const_int 0)))
5852    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5853   "s390_match_ccmode (insn, CCLmode)"
5854   "@
5855    sl<g>r\t%0,%2
5856    sl<g>rk\t%0,%1,%2
5857    sl<g>\t%0,%2
5858    sl<y>\t%0,%2"
5859   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5860    (set_attr "cpu_facility" "*,z196,*,*")
5861    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5862
5863
5864 ; slr, sl, sly, slgr, slg, slrk, slgrk
5865 (define_insn "*sub<mode>3_cconly2"
5866   [(set (reg CC_REGNUM)
5867         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5868                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5869    (clobber (match_scratch:GPR 0                        "=d,d,d,d"))]
5870   "s390_match_ccmode (insn, CCL3mode)"
5871   "@
5872    sl<g>r\t%0,%2
5873    sl<g>rk\t%0,%1,%2
5874    sl<g>\t%0,%2
5875    sl<y>\t%0,%2"
5876   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5877    (set_attr "cpu_facility" "*,z196,*,*")
5878    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5879
5880
5881 ;
5882 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5883 ;
5884
5885 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5886 (define_insn "sub<mode>3"
5887   [(set (match_operand:FP           0 "register_operand" "=f,f,f,v")
5888         (minus:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
5889                   (match_operand:FP 2 "general_operand"   "f,f,R,v")))
5890    (clobber (reg:CC CC_REGNUM))]
5891   "TARGET_HARD_FLOAT"
5892   "@
5893    s<xde>tr\t%0,%1,%2
5894    s<xde>br\t%0,%2
5895    s<xde>b\t%0,%2
5896    wfsdb\t%v0,%v1,%v2"
5897   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
5898    (set_attr "type"         "fsimp<mode>")
5899    (set_attr "cpu_facility" "*,*,*,vec")
5900    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5901
5902 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5903 (define_insn "*sub<mode>3_cc"
5904   [(set (reg CC_REGNUM)
5905         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
5906                            (match_operand:FP 2 "general_operand"      "f,f,R"))
5907                  (match_operand:FP 3 "const0_operand" "")))
5908    (set (match_operand:FP 0 "register_operand" "=f,f,f")
5909         (minus:FP (match_dup 1) (match_dup 2)))]
5910   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5911   "@
5912    s<xde>tr\t%0,%1,%2
5913    s<xde>br\t%0,%2
5914    s<xde>b\t%0,%2"
5915   [(set_attr "op_type"  "RRF,RRE,RXE")
5916    (set_attr "type"     "fsimp<mode>")
5917    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5918
5919 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5920 (define_insn "*sub<mode>3_cconly"
5921   [(set (reg CC_REGNUM)
5922         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
5923                            (match_operand:FP 2 "general_operand"      "f,f,R"))
5924                  (match_operand:FP 3 "const0_operand" "")))
5925    (clobber (match_scratch:FP 0 "=f,f,f"))]
5926   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5927   "@
5928    s<xde>tr\t%0,%1,%2
5929    s<xde>br\t%0,%2
5930    s<xde>b\t%0,%2"
5931   [(set_attr "op_type"  "RRF,RRE,RXE")
5932    (set_attr "type"     "fsimp<mode>")
5933    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5934
5935
5936 ;;
5937 ;;- Conditional add/subtract instructions.
5938 ;;
5939
5940 ;
5941 ; add(di|si)cc instruction pattern(s).
5942 ;
5943
5944 ; the following 4 patterns are used when the result of an add with
5945 ; carry is checked for an overflow condition
5946
5947 ; op1 + op2 + c < op1
5948
5949 ; alcr, alc, alcgr, alcg
5950 (define_insn "*add<mode>3_alc_carry1_cc"
5951   [(set (reg CC_REGNUM)
5952         (compare
5953           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5954                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5955                     (match_operand:GPR 2 "general_operand" "d,RT"))
5956           (match_dup 1)))
5957    (set (match_operand:GPR 0 "register_operand" "=d,d")
5958         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5959   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5960   "@
5961    alc<g>r\t%0,%2
5962    alc<g>\t%0,%2"
5963   [(set_attr "op_type"  "RRE,RXY")
5964    (set_attr "z196prop" "z196_alone,z196_alone")])
5965
5966 ; alcr, alc, alcgr, alcg
5967 (define_insn "*add<mode>3_alc_carry1_cconly"
5968   [(set (reg CC_REGNUM)
5969         (compare
5970           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5971                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5972                     (match_operand:GPR 2 "general_operand" "d,RT"))
5973           (match_dup 1)))
5974    (clobber (match_scratch:GPR 0 "=d,d"))]
5975   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5976   "@
5977    alc<g>r\t%0,%2
5978    alc<g>\t%0,%2"
5979   [(set_attr "op_type"  "RRE,RXY")
5980    (set_attr "z196prop" "z196_alone,z196_alone")])
5981
5982 ; op1 + op2 + c < op2
5983
5984 ; alcr, alc, alcgr, alcg
5985 (define_insn "*add<mode>3_alc_carry2_cc"
5986   [(set (reg CC_REGNUM)
5987         (compare
5988           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5989                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5990                     (match_operand:GPR 2 "general_operand" "d,RT"))
5991           (match_dup 2)))
5992    (set (match_operand:GPR 0 "register_operand" "=d,d")
5993         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5994   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5995   "@
5996    alc<g>r\t%0,%2
5997    alc<g>\t%0,%2"
5998   [(set_attr "op_type"  "RRE,RXY")])
5999
6000 ; alcr, alc, alcgr, alcg
6001 (define_insn "*add<mode>3_alc_carry2_cconly"
6002   [(set (reg CC_REGNUM)
6003         (compare
6004           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6005                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6006                     (match_operand:GPR 2 "general_operand" "d,RT"))
6007           (match_dup 2)))
6008    (clobber (match_scratch:GPR 0 "=d,d"))]
6009   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6010   "@
6011    alc<g>r\t%0,%2
6012    alc<g>\t%0,%2"
6013   [(set_attr "op_type"  "RRE,RXY")])
6014
6015 ; alcr, alc, alcgr, alcg
6016 (define_insn "*add<mode>3_alc_cc"
6017   [(set (reg CC_REGNUM)
6018         (compare
6019           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6020                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6021                     (match_operand:GPR 2 "general_operand" "d,RT"))
6022           (const_int 0)))
6023    (set (match_operand:GPR 0 "register_operand" "=d,d")
6024         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6025   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6026   "@
6027    alc<g>r\t%0,%2
6028    alc<g>\t%0,%2"
6029   [(set_attr "op_type"  "RRE,RXY")])
6030
6031 ; alcr, alc, alcgr, alcg
6032 (define_insn "*add<mode>3_alc"
6033   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6034         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6035                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6036                   (match_operand:GPR 2 "general_operand" "d,RT")))
6037    (clobber (reg:CC CC_REGNUM))]
6038   "TARGET_CPU_ZARCH"
6039   "@
6040    alc<g>r\t%0,%2
6041    alc<g>\t%0,%2"
6042   [(set_attr "op_type"  "RRE,RXY")])
6043
6044 ; slbr, slb, slbgr, slbg
6045 (define_insn "*sub<mode>3_slb_cc"
6046   [(set (reg CC_REGNUM)
6047         (compare
6048           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6049                                 (match_operand:GPR 2 "general_operand" "d,RT"))
6050                      (match_operand:GPR 3 "s390_slb_comparison" ""))
6051           (const_int 0)))
6052    (set (match_operand:GPR 0 "register_operand" "=d,d")
6053         (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6054   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6055   "@
6056    slb<g>r\t%0,%2
6057    slb<g>\t%0,%2"
6058   [(set_attr "op_type"  "RRE,RXY")
6059    (set_attr "z10prop" "z10_c,*")])
6060
6061 ; slbr, slb, slbgr, slbg
6062 (define_insn "*sub<mode>3_slb"
6063   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6064         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6065                               (match_operand:GPR 2 "general_operand" "d,RT"))
6066                    (match_operand:GPR 3 "s390_slb_comparison" "")))
6067    (clobber (reg:CC CC_REGNUM))]
6068   "TARGET_CPU_ZARCH"
6069   "@
6070    slb<g>r\t%0,%2
6071    slb<g>\t%0,%2"
6072   [(set_attr "op_type"  "RRE,RXY")
6073    (set_attr "z10prop" "z10_c,*")])
6074
6075 (define_expand "add<mode>cc"
6076   [(match_operand:GPR 0 "register_operand" "")
6077    (match_operand 1 "comparison_operator" "")
6078    (match_operand:GPR 2 "register_operand" "")
6079    (match_operand:GPR 3 "const_int_operand" "")]
6080   "TARGET_CPU_ZARCH"
6081   "if (!s390_expand_addcc (GET_CODE (operands[1]),
6082                            XEXP (operands[1], 0), XEXP (operands[1], 1),
6083                            operands[0], operands[2],
6084                            operands[3])) FAIL; DONE;")
6085
6086 ;
6087 ; scond instruction pattern(s).
6088 ;
6089
6090 (define_insn_and_split "*scond<mode>"
6091   [(set (match_operand:GPR 0 "register_operand" "=&d")
6092         (match_operand:GPR 1 "s390_alc_comparison" ""))
6093    (clobber (reg:CC CC_REGNUM))]
6094   "TARGET_CPU_ZARCH"
6095   "#"
6096   "&& reload_completed"
6097   [(set (match_dup 0) (const_int 0))
6098    (parallel
6099     [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6100                                   (match_dup 0)))
6101      (clobber (reg:CC CC_REGNUM))])]
6102   "")
6103
6104 (define_insn_and_split "*scond<mode>_neg"
6105   [(set (match_operand:GPR 0 "register_operand" "=&d")
6106         (match_operand:GPR 1 "s390_slb_comparison" ""))
6107    (clobber (reg:CC CC_REGNUM))]
6108   "TARGET_CPU_ZARCH"
6109   "#"
6110   "&& reload_completed"
6111   [(set (match_dup 0) (const_int 0))
6112    (parallel
6113     [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6114                                    (match_dup 1)))
6115      (clobber (reg:CC CC_REGNUM))])
6116    (parallel
6117     [(set (match_dup 0) (neg:GPR (match_dup 0)))
6118      (clobber (reg:CC CC_REGNUM))])]
6119   "")
6120
6121
6122 (define_expand "cstore<mode>4"
6123   [(set (match_operand:SI 0 "register_operand" "")
6124         (match_operator:SI 1 "s390_scond_operator"
6125          [(match_operand:GPR 2 "register_operand" "")
6126           (match_operand:GPR 3 "general_operand" "")]))]
6127   "TARGET_CPU_ZARCH"
6128   "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6129                            operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6130
6131 (define_expand "cstorecc4"
6132   [(parallel
6133     [(set (match_operand:SI 0 "register_operand" "")
6134           (match_operator:SI 1 "s390_eqne_operator"
6135            [(match_operand:CCZ1 2 "register_operand")
6136             (match_operand 3 "const0_operand")]))
6137      (clobber (reg:CC CC_REGNUM))])]
6138   ""
6139   "emit_insn (gen_sne (operands[0], operands[2]));
6140    if (GET_CODE (operands[1]) == EQ)
6141      emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6142    DONE;")
6143
6144 (define_insn_and_split "sne"
6145   [(set (match_operand:SI 0 "register_operand" "=d")
6146         (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6147                (const_int 0)))
6148    (clobber (reg:CC CC_REGNUM))]
6149   ""
6150   "#"
6151   "reload_completed"
6152   [(parallel
6153     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6154      (clobber (reg:CC CC_REGNUM))])])
6155
6156
6157 ;;
6158 ;; - Conditional move instructions (introduced with z196)
6159 ;;
6160
6161 (define_expand "mov<mode>cc"
6162   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6163         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6164                           (match_operand:GPR 2 "nonimmediate_operand" "")
6165                           (match_operand:GPR 3 "nonimmediate_operand" "")))]
6166   "TARGET_Z196"
6167 {
6168   /* Emit the comparison insn in case we do not already have a comparison result.  */
6169   if (!s390_comparison (operands[1], VOIDmode))
6170     operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6171                                      XEXP (operands[1], 0),
6172                                      XEXP (operands[1], 1));
6173 })
6174
6175 ; locr, loc, stoc, locgr, locg, stocg
6176 (define_insn_and_split "*mov<mode>cc"
6177   [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d, d, d,QS,QS,&d")
6178         (if_then_else:GPR
6179           (match_operator 1 "s390_comparison"
6180             [(match_operand 2 "cc_reg_operand"        " c,c, c, c, c, c, c")
6181              (match_operand 5 "const_int_operand"     "")])
6182           (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
6183           (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
6184   "TARGET_Z196"
6185   "@
6186    loc<g>r%C1\t%0,%3
6187    loc<g>r%D1\t%0,%4
6188    loc<g>%C1\t%0,%3
6189    loc<g>%D1\t%0,%4
6190    stoc<g>%C1\t%3,%0
6191    stoc<g>%D1\t%4,%0
6192    #"
6193   "&& reload_completed
6194    && MEM_P (operands[3]) && MEM_P (operands[4])"
6195   [(set (match_dup 0)
6196         (if_then_else:GPR
6197          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6198          (match_dup 3)
6199          (match_dup 0)))
6200    (set (match_dup 0)
6201         (if_then_else:GPR
6202          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6203          (match_dup 0)
6204          (match_dup 4)))]
6205   ""
6206   [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
6207
6208 ;;
6209 ;;- Multiply instructions.
6210 ;;
6211
6212 ;
6213 ; muldi3 instruction pattern(s).
6214 ;
6215
6216 (define_insn "*muldi3_sign"
6217   [(set (match_operand:DI 0 "register_operand" "=d,d")
6218         (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
6219                  (match_operand:DI 1 "register_operand" "0,0")))]
6220   "TARGET_ZARCH"
6221   "@
6222    msgfr\t%0,%2
6223    msgf\t%0,%2"
6224   [(set_attr "op_type"      "RRE,RXY")
6225    (set_attr "type"         "imuldi")])
6226
6227 (define_insn "muldi3"
6228   [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6229         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6230                  (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
6231   "TARGET_ZARCH"
6232   "@
6233    msgr\t%0,%2
6234    mghi\t%0,%h2
6235    msg\t%0,%2
6236    msgfi\t%0,%2"
6237   [(set_attr "op_type"      "RRE,RI,RXY,RIL")
6238    (set_attr "type"         "imuldi")
6239    (set_attr "cpu_facility" "*,*,*,z10")])
6240
6241 ;
6242 ; mulsi3 instruction pattern(s).
6243 ;
6244
6245 (define_insn "*mulsi3_sign"
6246   [(set (match_operand:SI 0 "register_operand" "=d,d")
6247         (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6248                  (match_operand:SI 1 "register_operand" "0,0")))]
6249   ""
6250   "@
6251    mh\t%0,%2
6252    mhy\t%0,%2"
6253   [(set_attr "op_type"      "RX,RXY")
6254    (set_attr "type"         "imulhi")
6255    (set_attr "cpu_facility" "*,z10")])
6256
6257 (define_insn "mulsi3"
6258   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6259         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6260                   (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6261   ""
6262   "@
6263    msr\t%0,%2
6264    mhi\t%0,%h2
6265    ms\t%0,%2
6266    msy\t%0,%2
6267    msfi\t%0,%2"
6268   [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
6269    (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
6270    (set_attr "cpu_facility" "*,*,*,*,z10")])
6271
6272 ;
6273 ; mulsidi3 instruction pattern(s).
6274 ;
6275
6276 (define_insn "mulsidi3"
6277   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6278         (mult:DI (sign_extend:DI
6279                    (match_operand:SI 1 "register_operand" "%0,0,0"))
6280                  (sign_extend:DI
6281                    (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6282   "!TARGET_ZARCH"
6283   "@
6284    mr\t%0,%2
6285    m\t%0,%2
6286    mfy\t%0,%2"
6287   [(set_attr "op_type"      "RR,RX,RXY")
6288    (set_attr "type"         "imulsi")
6289    (set_attr "cpu_facility" "*,*,z10")])
6290
6291 ;
6292 ; umul instruction pattern(s).
6293 ;
6294
6295 ; mlr, ml, mlgr, mlg
6296 (define_insn "umul<dwh><mode>3"
6297   [(set (match_operand:DW 0 "register_operand"                   "=d, d")
6298         (mult:DW (zero_extend:DW
6299                    (match_operand:<DWH> 1 "register_operand"     "%0, 0"))
6300                  (zero_extend:DW
6301                    (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
6302   "TARGET_CPU_ZARCH"
6303   "@
6304    ml<tg>r\t%0,%2
6305    ml<tg>\t%0,%2"
6306   [(set_attr "op_type"  "RRE,RXY")
6307    (set_attr "type"     "imul<dwh>")])
6308
6309 ;
6310 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6311 ;
6312
6313 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6314 (define_insn "mul<mode>3"
6315   [(set (match_operand:FP          0 "register_operand"     "=f,f,f,v")
6316         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6317                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))]
6318   "TARGET_HARD_FLOAT"
6319   "@
6320    m<xdee>tr\t%0,%1,%2
6321    m<xdee>br\t%0,%2
6322    m<xdee>b\t%0,%2
6323    wfmdb\t%v0,%v1,%v2"
6324   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6325    (set_attr "type"         "fmul<mode>")
6326    (set_attr "cpu_facility" "*,*,*,vec")
6327    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6328
6329 ; madbr, maebr, maxb, madb, maeb
6330 (define_insn "fma<mode>4"
6331   [(set (match_operand:DSF          0 "register_operand"     "=f,f,v")
6332         (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6333                  (match_operand:DSF 2 "nonimmediate_operand"  "f,R,v")
6334                  (match_operand:DSF 3 "register_operand"      "0,0,v")))]
6335   "TARGET_HARD_FLOAT"
6336   "@
6337    ma<xde>br\t%0,%1,%2
6338    ma<xde>b\t%0,%1,%2
6339    wfmadb\t%v0,%v1,%v2,%v3"
6340   [(set_attr "op_type"      "RRE,RXE,VRR")
6341    (set_attr "type"         "fmadd<mode>")
6342    (set_attr "cpu_facility" "*,*,vec")
6343    (set_attr "enabled"      "*,*,<DFDI>")])
6344
6345 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6346 (define_insn "fms<mode>4"
6347   [(set (match_operand:DSF                   0 "register_operand"     "=f,f,v")
6348         (fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,v")
6349                  (match_operand:DSF          2 "nonimmediate_operand"  "f,R,v")
6350                  (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,v"))))]
6351   "TARGET_HARD_FLOAT"
6352   "@
6353    ms<xde>br\t%0,%1,%2
6354    ms<xde>b\t%0,%1,%2
6355    wfmsdb\t%v0,%v1,%v2,%v3"
6356   [(set_attr "op_type"      "RRE,RXE,VRR")
6357    (set_attr "type"         "fmadd<mode>")
6358    (set_attr "cpu_facility" "*,*,vec")
6359    (set_attr "enabled"      "*,*,<DFDI>")])
6360
6361 ;;
6362 ;;- Divide and modulo instructions.
6363 ;;
6364
6365 ;
6366 ; divmoddi4 instruction pattern(s).
6367 ;
6368
6369 (define_expand "divmoddi4"
6370   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6371                    (div:DI (match_operand:DI 1 "register_operand" "")
6372                            (match_operand:DI 2 "general_operand" "")))
6373               (set (match_operand:DI 3 "general_operand" "")
6374                    (mod:DI (match_dup 1) (match_dup 2)))])
6375    (clobber (match_dup 4))]
6376   "TARGET_ZARCH"
6377 {
6378   rtx insn, div_equal, mod_equal;
6379
6380   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6381   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6382
6383   operands[4] = gen_reg_rtx(TImode);
6384   emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6385
6386   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6387   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6388
6389   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6390   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6391
6392   DONE;
6393 })
6394
6395 (define_insn "divmodtidi3"
6396   [(set (match_operand:TI 0 "register_operand" "=d,d")
6397         (ior:TI
6398           (ashift:TI
6399             (zero_extend:TI
6400               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6401                       (match_operand:DI 2 "general_operand" "d,RT")))
6402             (const_int 64))
6403           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6404   "TARGET_ZARCH"
6405   "@
6406    dsgr\t%0,%2
6407    dsg\t%0,%2"
6408   [(set_attr "op_type"  "RRE,RXY")
6409    (set_attr "type"     "idiv")])
6410
6411 (define_insn "divmodtisi3"
6412   [(set (match_operand:TI 0 "register_operand" "=d,d")
6413         (ior:TI
6414           (ashift:TI
6415             (zero_extend:TI
6416               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6417                       (sign_extend:DI
6418                         (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6419             (const_int 64))
6420           (zero_extend:TI
6421             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6422   "TARGET_ZARCH"
6423   "@
6424    dsgfr\t%0,%2
6425    dsgf\t%0,%2"
6426   [(set_attr "op_type"  "RRE,RXY")
6427    (set_attr "type"     "idiv")])
6428
6429 ;
6430 ; udivmoddi4 instruction pattern(s).
6431 ;
6432
6433 (define_expand "udivmoddi4"
6434   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6435                    (udiv:DI (match_operand:DI 1 "general_operand" "")
6436                             (match_operand:DI 2 "nonimmediate_operand" "")))
6437               (set (match_operand:DI 3 "general_operand" "")
6438                    (umod:DI (match_dup 1) (match_dup 2)))])
6439    (clobber (match_dup 4))]
6440   "TARGET_ZARCH"
6441 {
6442   rtx insn, div_equal, mod_equal, equal;
6443
6444   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6445   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6446   equal = gen_rtx_IOR (TImode,
6447                        gen_rtx_ASHIFT (TImode,
6448                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6449                                        GEN_INT (64)),
6450                        gen_rtx_ZERO_EXTEND (TImode, div_equal));
6451
6452   operands[4] = gen_reg_rtx(TImode);
6453   emit_clobber (operands[4]);
6454   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6455   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6456
6457   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6458   set_unique_reg_note (insn, REG_EQUAL, equal);
6459
6460   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6461   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6462
6463   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6464   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6465
6466   DONE;
6467 })
6468
6469 (define_insn "udivmodtidi3"
6470   [(set (match_operand:TI 0 "register_operand" "=d,d")
6471         (ior:TI
6472           (ashift:TI
6473             (zero_extend:TI
6474               (truncate:DI
6475                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6476                          (zero_extend:TI
6477                            (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6478             (const_int 64))
6479           (zero_extend:TI
6480             (truncate:DI
6481               (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6482   "TARGET_ZARCH"
6483   "@
6484    dlgr\t%0,%2
6485    dlg\t%0,%2"
6486   [(set_attr "op_type"  "RRE,RXY")
6487    (set_attr "type"     "idiv")])
6488
6489 ;
6490 ; divmodsi4 instruction pattern(s).
6491 ;
6492
6493 (define_expand "divmodsi4"
6494   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6495                    (div:SI (match_operand:SI 1 "general_operand" "")
6496                            (match_operand:SI 2 "nonimmediate_operand" "")))
6497               (set (match_operand:SI 3 "general_operand" "")
6498                    (mod:SI (match_dup 1) (match_dup 2)))])
6499    (clobber (match_dup 4))]
6500   "!TARGET_ZARCH"
6501 {
6502   rtx insn, div_equal, mod_equal, equal;
6503
6504   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6505   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6506   equal = gen_rtx_IOR (DImode,
6507                        gen_rtx_ASHIFT (DImode,
6508                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6509                                        GEN_INT (32)),
6510                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6511
6512   operands[4] = gen_reg_rtx(DImode);
6513   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6514
6515   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6516   set_unique_reg_note (insn, REG_EQUAL, equal);
6517
6518   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6519   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6520
6521   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6522   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6523
6524   DONE;
6525 })
6526
6527 (define_insn "divmoddisi3"
6528   [(set (match_operand:DI 0 "register_operand" "=d,d")
6529         (ior:DI
6530           (ashift:DI
6531             (zero_extend:DI
6532               (truncate:SI
6533                 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6534                         (sign_extend:DI
6535                           (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6536             (const_int 32))
6537           (zero_extend:DI
6538             (truncate:SI
6539               (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6540   "!TARGET_ZARCH"
6541   "@
6542    dr\t%0,%2
6543    d\t%0,%2"
6544   [(set_attr "op_type"  "RR,RX")
6545    (set_attr "type"     "idiv")])
6546
6547 ;
6548 ; udivsi3 and umodsi3 instruction pattern(s).
6549 ;
6550
6551 (define_expand "udivmodsi4"
6552   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6553                    (udiv:SI (match_operand:SI 1 "general_operand" "")
6554                             (match_operand:SI 2 "nonimmediate_operand" "")))
6555               (set (match_operand:SI 3 "general_operand" "")
6556                    (umod:SI (match_dup 1) (match_dup 2)))])
6557    (clobber (match_dup 4))]
6558   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6559 {
6560   rtx insn, div_equal, mod_equal, equal;
6561
6562   div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6563   mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6564   equal = gen_rtx_IOR (DImode,
6565                        gen_rtx_ASHIFT (DImode,
6566                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6567                                        GEN_INT (32)),
6568                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6569
6570   operands[4] = gen_reg_rtx(DImode);
6571   emit_clobber (operands[4]);
6572   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6573   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6574
6575   insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6576   set_unique_reg_note (insn, REG_EQUAL, equal);
6577
6578   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6579   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6580
6581   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6582   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6583
6584   DONE;
6585 })
6586
6587 (define_insn "udivmoddisi3"
6588   [(set (match_operand:DI 0 "register_operand" "=d,d")
6589         (ior:DI
6590           (ashift:DI
6591             (zero_extend:DI
6592               (truncate:SI
6593                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6594                          (zero_extend:DI
6595                            (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6596             (const_int 32))
6597           (zero_extend:DI
6598             (truncate:SI
6599               (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6600   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6601   "@
6602    dlr\t%0,%2
6603    dl\t%0,%2"
6604   [(set_attr "op_type"  "RRE,RXY")
6605    (set_attr "type"     "idiv")])
6606
6607 (define_expand "udivsi3"
6608   [(set (match_operand:SI 0 "register_operand" "=d")
6609         (udiv:SI (match_operand:SI 1 "general_operand" "")
6610                  (match_operand:SI 2 "general_operand" "")))
6611    (clobber (match_dup 3))]
6612   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6613 {
6614   rtx insn, udiv_equal, umod_equal, equal;
6615
6616   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6617   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6618   equal = gen_rtx_IOR (DImode,
6619                        gen_rtx_ASHIFT (DImode,
6620                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6621                                        GEN_INT (32)),
6622                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6623
6624   operands[3] = gen_reg_rtx (DImode);
6625
6626   if (CONSTANT_P (operands[2]))
6627     {
6628       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6629         {
6630           rtx_code_label *label1 = gen_label_rtx ();
6631
6632           operands[1] = make_safe_from (operands[1], operands[0]);
6633           emit_move_insn (operands[0], const0_rtx);
6634           emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6635                                    SImode, 1, label1);
6636           emit_move_insn (operands[0], const1_rtx);
6637           emit_label (label1);
6638         }
6639       else
6640         {
6641           operands[2] = force_reg (SImode, operands[2]);
6642           operands[2] = make_safe_from (operands[2], operands[0]);
6643
6644           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6645           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6646                                              operands[2]));
6647           set_unique_reg_note (insn, REG_EQUAL, equal);
6648
6649           insn = emit_move_insn (operands[0],
6650                                  gen_lowpart (SImode, operands[3]));
6651           set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6652         }
6653     }
6654   else
6655     {
6656       rtx_code_label *label1 = gen_label_rtx ();
6657       rtx_code_label *label2 = gen_label_rtx ();
6658       rtx_code_label *label3 = gen_label_rtx ();
6659
6660       operands[1] = force_reg (SImode, operands[1]);
6661       operands[1] = make_safe_from (operands[1], operands[0]);
6662       operands[2] = force_reg (SImode, operands[2]);
6663       operands[2] = make_safe_from (operands[2], operands[0]);
6664
6665       emit_move_insn (operands[0], const0_rtx);
6666       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6667                                SImode, 1, label3);
6668       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6669                                SImode, 0, label2);
6670       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6671                                SImode, 0, label1);
6672       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6673       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6674                                          operands[2]));
6675       set_unique_reg_note (insn, REG_EQUAL, equal);
6676
6677       insn = emit_move_insn (operands[0],
6678                              gen_lowpart (SImode, operands[3]));
6679       set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6680
6681       emit_jump (label3);
6682       emit_label (label1);
6683       emit_move_insn (operands[0], operands[1]);
6684       emit_jump (label3);
6685       emit_label (label2);
6686       emit_move_insn (operands[0], const1_rtx);
6687       emit_label (label3);
6688     }
6689   emit_move_insn (operands[0], operands[0]);
6690   DONE;
6691 })
6692
6693 (define_expand "umodsi3"
6694   [(set (match_operand:SI 0 "register_operand" "=d")
6695         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6696                  (match_operand:SI 2 "nonimmediate_operand" "")))
6697    (clobber (match_dup 3))]
6698   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6699 {
6700   rtx insn, udiv_equal, umod_equal, equal;
6701
6702   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6703   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6704   equal = gen_rtx_IOR (DImode,
6705                        gen_rtx_ASHIFT (DImode,
6706                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6707                                        GEN_INT (32)),
6708                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6709
6710   operands[3] = gen_reg_rtx (DImode);
6711
6712   if (CONSTANT_P (operands[2]))
6713     {
6714       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6715         {
6716           rtx_code_label *label1 = gen_label_rtx ();
6717
6718           operands[1] = make_safe_from (operands[1], operands[0]);
6719           emit_move_insn (operands[0], operands[1]);
6720           emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6721                                    SImode, 1, label1);
6722           emit_insn (gen_abssi2 (operands[0], operands[2]));
6723           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6724           emit_label (label1);
6725         }
6726       else
6727         {
6728           operands[2] = force_reg (SImode, operands[2]);
6729           operands[2] = make_safe_from (operands[2], operands[0]);
6730
6731           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6732           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6733                                              operands[2]));
6734           set_unique_reg_note (insn, REG_EQUAL, equal);
6735
6736           insn = emit_move_insn (operands[0],
6737                                  gen_highpart (SImode, operands[3]));
6738           set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6739         }
6740     }
6741   else
6742     {
6743       rtx_code_label *label1 = gen_label_rtx ();
6744       rtx_code_label *label2 = gen_label_rtx ();
6745       rtx_code_label *label3 = gen_label_rtx ();
6746
6747       operands[1] = force_reg (SImode, operands[1]);
6748       operands[1] = make_safe_from (operands[1], operands[0]);
6749       operands[2] = force_reg (SImode, operands[2]);
6750       operands[2] = make_safe_from (operands[2], operands[0]);
6751
6752       emit_move_insn(operands[0], operands[1]);
6753       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6754                                SImode, 1, label3);
6755       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6756                                SImode, 0, label2);
6757       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6758                                SImode, 0, label1);
6759       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6760       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6761                                          operands[2]));
6762       set_unique_reg_note (insn, REG_EQUAL, equal);
6763
6764       insn = emit_move_insn (operands[0],
6765                              gen_highpart (SImode, operands[3]));
6766       set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6767
6768       emit_jump (label3);
6769       emit_label (label1);
6770       emit_move_insn (operands[0], const0_rtx);
6771       emit_jump (label3);
6772       emit_label (label2);
6773       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6774       emit_label (label3);
6775     }
6776   DONE;
6777 })
6778
6779 ;
6780 ; div(df|sf)3 instruction pattern(s).
6781 ;
6782
6783 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6784 (define_insn "div<mode>3"
6785   [(set (match_operand:FP         0 "register_operand" "=f,f,f,v")
6786         (div:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
6787                 (match_operand:FP 2 "general_operand"   "f,f,R,v")))]
6788   "TARGET_HARD_FLOAT"
6789   "@
6790    d<xde>tr\t%0,%1,%2
6791    d<xde>br\t%0,%2
6792    d<xde>b\t%0,%2
6793    wfddb\t%v0,%v1,%v2"
6794   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6795    (set_attr "type"         "fdiv<mode>")
6796    (set_attr "cpu_facility" "*,*,*,vec")
6797    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6798
6799
6800 ;;
6801 ;;- And instructions.
6802 ;;
6803
6804 (define_expand "and<mode>3"
6805   [(set (match_operand:INT 0 "nonimmediate_operand" "")
6806         (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6807                  (match_operand:INT 2 "general_operand" "")))
6808    (clobber (reg:CC CC_REGNUM))]
6809   ""
6810   "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6811
6812 ;
6813 ; anddi3 instruction pattern(s).
6814 ;
6815
6816 (define_insn "*anddi3_cc"
6817   [(set (reg CC_REGNUM)
6818         (compare
6819           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6820                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6821           (const_int 0)))
6822    (set (match_operand:DI 0 "register_operand"               "=d,d, d,    d")
6823         (and:DI (match_dup 1) (match_dup 2)))]
6824   "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6825   "@
6826    ngr\t%0,%2
6827    ngrk\t%0,%1,%2
6828    ng\t%0,%2
6829    risbg\t%0,%1,%s2,128+%e2,0"
6830   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6831    (set_attr "cpu_facility" "*,z196,*,z10")
6832    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6833
6834 (define_insn "*anddi3_cconly"
6835   [(set (reg CC_REGNUM)
6836         (compare
6837           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6838                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6839                  (const_int 0)))
6840    (clobber (match_scratch:DI 0                              "=d,d, d,    d"))]
6841   "TARGET_ZARCH
6842    && s390_match_ccmode(insn, CCTmode)
6843    /* Do not steal TM patterns.  */
6844    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6845   "@
6846    ngr\t%0,%2
6847    ngrk\t%0,%1,%2
6848    ng\t%0,%2
6849    risbg\t%0,%1,%s2,128+%e2,0"
6850   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6851    (set_attr "cpu_facility" "*,z196,*,z10")
6852    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6853
6854 (define_insn "*anddi3"
6855   [(set (match_operand:DI 0 "nonimmediate_operand"
6856             "=d,d,    d,    d,    d,    d,    d,    d,d,d, d,    d,   AQ,Q")
6857         (and:DI
6858           (match_operand:DI 1 "nonimmediate_operand"
6859             "%d,o,    0,    0,    0,    0,    0,    0,0,d, 0,    d,    0,0")
6860           (match_operand:DI 2 "general_operand"
6861             "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6862    (clobber (reg:CC CC_REGNUM))]
6863   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6864   "@
6865    #
6866    #
6867    nihh\t%0,%j2
6868    nihl\t%0,%j2
6869    nilh\t%0,%j2
6870    nill\t%0,%j2
6871    nihf\t%0,%m2
6872    nilf\t%0,%m2
6873    ngr\t%0,%2
6874    ngrk\t%0,%1,%2
6875    ng\t%0,%2
6876    risbg\t%0,%1,%s2,128+%e2,0
6877    #
6878    #"
6879   [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6880    (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6881    (set_attr "z10prop" "*,
6882                         *,
6883                         z10_super_E1,
6884                         z10_super_E1,
6885                         z10_super_E1,
6886                         z10_super_E1,
6887                         z10_super_E1,
6888                         z10_super_E1,
6889                         z10_super_E1,
6890                         *,
6891                         z10_super_E1,
6892                         z10_super_E1,
6893                         *,
6894                         *")])
6895
6896 (define_split
6897   [(set (match_operand:DI 0 "s_operand" "")
6898         (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6899    (clobber (reg:CC CC_REGNUM))]
6900   "reload_completed"
6901   [(parallel
6902     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6903      (clobber (reg:CC CC_REGNUM))])]
6904   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6905
6906 ;; These two are what combine generates for (ashift (zero_extract)).
6907 (define_insn "*extzv_<mode>_srl"
6908   [(set (match_operand:GPR 0 "register_operand" "=d")
6909         (and:GPR (lshiftrt:GPR
6910                    (match_operand:GPR 1 "register_operand" "d")
6911                    (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6912                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6913    (clobber (reg:CC CC_REGNUM))]
6914   "TARGET_Z10
6915    /* Note that even for the SImode pattern, the rotate is always DImode.  */
6916    && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6917                            INTVAL (operands[3]))"
6918   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6919   [(set_attr "op_type" "RIE")
6920    (set_attr "z10prop" "z10_super_E1")])
6921
6922 (define_insn "*extzv_<mode>_sll"
6923   [(set (match_operand:GPR 0 "register_operand" "=d")
6924         (and:GPR (ashift:GPR
6925                   (match_operand:GPR 1 "register_operand" "d")
6926                   (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6927                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6928    (clobber (reg:CC CC_REGNUM))]
6929   "TARGET_Z10
6930    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6931                            INTVAL (operands[3]))"
6932   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6933   [(set_attr "op_type" "RIE")
6934    (set_attr "z10prop" "z10_super_E1")])
6935
6936
6937 ;
6938 ; andsi3 instruction pattern(s).
6939 ;
6940
6941 (define_insn "*andsi3_cc"
6942   [(set (reg CC_REGNUM)
6943         (compare
6944           (and:SI
6945             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6946             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6947           (const_int 0)))
6948    (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
6949         (and:SI (match_dup 1) (match_dup 2)))]
6950   "s390_match_ccmode(insn, CCTmode)"
6951   "@
6952    nilf\t%0,%o2
6953    nr\t%0,%2
6954    nrk\t%0,%1,%2
6955    n\t%0,%2
6956    ny\t%0,%2
6957    risbg\t%0,%1,%t2,128+%f2,0"
6958   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6959    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6960    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6961                         z10_super_E1,z10_super_E1,z10_super_E1")])
6962
6963 (define_insn "*andsi3_cconly"
6964   [(set (reg CC_REGNUM)
6965         (compare
6966           (and:SI
6967             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6968             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6969           (const_int 0)))
6970    (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
6971   "s390_match_ccmode(insn, CCTmode)
6972    /* Do not steal TM patterns.  */
6973    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6974   "@
6975    nilf\t%0,%o2
6976    nr\t%0,%2
6977    nrk\t%0,%1,%2
6978    n\t%0,%2
6979    ny\t%0,%2
6980    risbg\t%0,%1,%t2,128+%f2,0"
6981   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6982    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6983    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6984                         z10_super_E1,z10_super_E1,z10_super_E1")])
6985
6986 (define_insn "*andsi3_zarch"
6987   [(set (match_operand:SI 0 "nonimmediate_operand"
6988                             "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
6989         (and:SI (match_operand:SI 1 "nonimmediate_operand"
6990                             "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
6991                 (match_operand:SI 2 "general_operand"
6992                             " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6993    (clobber (reg:CC CC_REGNUM))]
6994   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6995   "@
6996    #
6997    #
6998    nilh\t%0,%j2
6999    nill\t%0,%j2
7000    nilf\t%0,%o2
7001    nr\t%0,%2
7002    nrk\t%0,%1,%2
7003    n\t%0,%2
7004    ny\t%0,%2
7005    risbg\t%0,%1,%t2,128+%f2,0
7006    #
7007    #"
7008   [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7009    (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
7010    (set_attr "z10prop" "*,
7011                         *,
7012                         z10_super_E1,
7013                         z10_super_E1,
7014                         z10_super_E1,
7015                         z10_super_E1,
7016                         *,
7017                         z10_super_E1,
7018                         z10_super_E1,
7019                         z10_super_E1,
7020                         *,
7021                         *")])
7022
7023 (define_insn "*andsi3_esa"
7024   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,   AQ,Q")
7025         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,    0,0")
7026                 (match_operand:SI 2 "general_operand"      " d,R,NxQSF,Q")))
7027    (clobber (reg:CC CC_REGNUM))]
7028   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7029   "@
7030    nr\t%0,%2
7031    n\t%0,%2
7032    #
7033    #"
7034   [(set_attr "op_type"  "RR,RX,SI,SS")
7035    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7036
7037
7038 (define_split
7039   [(set (match_operand:SI 0 "s_operand" "")
7040         (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7041    (clobber (reg:CC CC_REGNUM))]
7042   "reload_completed"
7043   [(parallel
7044     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7045      (clobber (reg:CC CC_REGNUM))])]
7046   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7047
7048 ;
7049 ; andhi3 instruction pattern(s).
7050 ;
7051
7052 (define_insn "*andhi3_zarch"
7053   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7054         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7055                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQHF,Q")))
7056    (clobber (reg:CC CC_REGNUM))]
7057   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7058   "@
7059    nr\t%0,%2
7060    nrk\t%0,%1,%2
7061    nill\t%0,%x2
7062    #
7063    #"
7064   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7065    (set_attr "cpu_facility" "*,z196,*,*,*")
7066    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7067 ])
7068
7069 (define_insn "*andhi3_esa"
7070   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7071         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7072                 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7073    (clobber (reg:CC CC_REGNUM))]
7074   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7075   "@
7076    nr\t%0,%2
7077    #
7078    #"
7079   [(set_attr "op_type"  "RR,SI,SS")
7080    (set_attr "z10prop" "z10_super_E1,*,*")
7081 ])
7082
7083 (define_split
7084   [(set (match_operand:HI 0 "s_operand" "")
7085         (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7086    (clobber (reg:CC CC_REGNUM))]
7087   "reload_completed"
7088   [(parallel
7089     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7090      (clobber (reg:CC CC_REGNUM))])]
7091   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7092
7093 ;
7094 ; andqi3 instruction pattern(s).
7095 ;
7096
7097 (define_insn "*andqi3_zarch"
7098   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7099         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7100                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7101    (clobber (reg:CC CC_REGNUM))]
7102   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7103   "@
7104    nr\t%0,%2
7105    nrk\t%0,%1,%2
7106    nill\t%0,%b2
7107    ni\t%S0,%b2
7108    niy\t%S0,%b2
7109    #"
7110   [(set_attr "op_type"  "RR,RRF,RI,SI,SIY,SS")
7111    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7112    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7113
7114 (define_insn "*andqi3_esa"
7115   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7116         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7117                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7118    (clobber (reg:CC CC_REGNUM))]
7119   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7120   "@
7121    nr\t%0,%2
7122    ni\t%S0,%b2
7123    #"
7124   [(set_attr "op_type"  "RR,SI,SS")
7125    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7126
7127 ;
7128 ; Block and (NC) patterns.
7129 ;
7130
7131 (define_insn "*nc"
7132   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7133         (and:BLK (match_dup 0)
7134                  (match_operand:BLK 1 "memory_operand" "Q")))
7135    (use (match_operand 2 "const_int_operand" "n"))
7136    (clobber (reg:CC CC_REGNUM))]
7137   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7138   "nc\t%O0(%2,%R0),%S1"
7139   [(set_attr "op_type" "SS")
7140    (set_attr "z196prop" "z196_cracked")])
7141
7142 (define_split
7143   [(set (match_operand 0 "memory_operand" "")
7144         (and (match_dup 0)
7145              (match_operand 1 "memory_operand" "")))
7146    (clobber (reg:CC CC_REGNUM))]
7147   "reload_completed
7148    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7149    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7150   [(parallel
7151     [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7152      (use (match_dup 2))
7153      (clobber (reg:CC CC_REGNUM))])]
7154 {
7155   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7156   operands[0] = adjust_address (operands[0], BLKmode, 0);
7157   operands[1] = adjust_address (operands[1], BLKmode, 0);
7158 })
7159
7160 (define_peephole2
7161   [(parallel
7162     [(set (match_operand:BLK 0 "memory_operand" "")
7163           (and:BLK (match_dup 0)
7164                    (match_operand:BLK 1 "memory_operand" "")))
7165      (use (match_operand 2 "const_int_operand" ""))
7166      (clobber (reg:CC CC_REGNUM))])
7167    (parallel
7168     [(set (match_operand:BLK 3 "memory_operand" "")
7169           (and:BLK (match_dup 3)
7170                    (match_operand:BLK 4 "memory_operand" "")))
7171      (use (match_operand 5 "const_int_operand" ""))
7172      (clobber (reg:CC CC_REGNUM))])]
7173   "s390_offset_p (operands[0], operands[3], operands[2])
7174    && s390_offset_p (operands[1], operands[4], operands[2])
7175    && !s390_overlap_p (operands[0], operands[1],
7176                        INTVAL (operands[2]) + INTVAL (operands[5]))
7177    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7178   [(parallel
7179     [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7180      (use (match_dup 8))
7181      (clobber (reg:CC CC_REGNUM))])]
7182   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7183    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7184    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7185
7186
7187 ;;
7188 ;;- Bit set (inclusive or) instructions.
7189 ;;
7190
7191 (define_expand "ior<mode>3"
7192   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7193         (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7194                  (match_operand:INT 2 "general_operand" "")))
7195    (clobber (reg:CC CC_REGNUM))]
7196   ""
7197   "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7198
7199 ;
7200 ; iordi3 instruction pattern(s).
7201 ;
7202
7203 (define_insn "*iordi3_cc"
7204   [(set (reg CC_REGNUM)
7205         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7206                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7207                  (const_int 0)))
7208    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7209         (ior:DI (match_dup 1) (match_dup 2)))]
7210   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7211   "@
7212    ogr\t%0,%2
7213    ogrk\t%0,%1,%2
7214    og\t%0,%2"
7215   [(set_attr "op_type"  "RRE,RRF,RXY")
7216    (set_attr "cpu_facility" "*,z196,*")
7217    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7218
7219 (define_insn "*iordi3_cconly"
7220   [(set (reg CC_REGNUM)
7221         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7222                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7223                  (const_int 0)))
7224    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7225   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7226   "@
7227    ogr\t%0,%2
7228    ogrk\t%0,%1,%2
7229    og\t%0,%2"
7230   [(set_attr "op_type"  "RRE,RRF,RXY")
7231    (set_attr "cpu_facility" "*,z196,*")
7232    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7233
7234 (define_insn "*iordi3"
7235   [(set (match_operand:DI 0 "nonimmediate_operand"
7236                                "=d,    d,    d,    d,    d,    d,d,d, d,   AQ,Q")
7237         (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7238                             "   %0,    0,    0,    0,    0,    0,0,d, 0,    0,0")
7239                 (match_operand:DI 2 "general_operand"
7240                             "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7241    (clobber (reg:CC CC_REGNUM))]
7242   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7243   "@
7244    oihh\t%0,%i2
7245    oihl\t%0,%i2
7246    oilh\t%0,%i2
7247    oill\t%0,%i2
7248    oihf\t%0,%k2
7249    oilf\t%0,%k2
7250    ogr\t%0,%2
7251    ogrk\t%0,%1,%2
7252    og\t%0,%2
7253    #
7254    #"
7255   [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7256    (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7257    (set_attr "z10prop" "z10_super_E1,
7258                         z10_super_E1,
7259                         z10_super_E1,
7260                         z10_super_E1,
7261                         z10_super_E1,
7262                         z10_super_E1,
7263                         z10_super_E1,
7264                         *,
7265                         z10_super_E1,
7266                         *,
7267                         *")])
7268
7269 (define_split
7270   [(set (match_operand:DI 0 "s_operand" "")
7271         (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7272    (clobber (reg:CC CC_REGNUM))]
7273   "reload_completed"
7274   [(parallel
7275     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7276      (clobber (reg:CC CC_REGNUM))])]
7277   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7278
7279 ;
7280 ; iorsi3 instruction pattern(s).
7281 ;
7282
7283 (define_insn "*iorsi3_cc"
7284   [(set (reg CC_REGNUM)
7285         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7286                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7287                  (const_int 0)))
7288    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7289         (ior:SI (match_dup 1) (match_dup 2)))]
7290   "s390_match_ccmode(insn, CCTmode)"
7291   "@
7292    oilf\t%0,%o2
7293    or\t%0,%2
7294    ork\t%0,%1,%2
7295    o\t%0,%2
7296    oy\t%0,%2"
7297   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7298    (set_attr "cpu_facility" "*,*,z196,*,*")
7299    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7300
7301 (define_insn "*iorsi3_cconly"
7302   [(set (reg CC_REGNUM)
7303         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7304                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7305                  (const_int 0)))
7306    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7307   "s390_match_ccmode(insn, CCTmode)"
7308   "@
7309    oilf\t%0,%o2
7310    or\t%0,%2
7311    ork\t%0,%1,%2
7312    o\t%0,%2
7313    oy\t%0,%2"
7314   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7315    (set_attr "cpu_facility" "*,*,z196,*,*")
7316    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7317
7318 (define_insn "*iorsi3_zarch"
7319   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,    d, d,d,d,d,d,   AQ,Q")
7320         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,    0, 0,0,d,0,0,    0,0")
7321                 (match_operand:SI 2 "general_operand"   "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7322    (clobber (reg:CC CC_REGNUM))]
7323   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7324   "@
7325    oilh\t%0,%i2
7326    oill\t%0,%i2
7327    oilf\t%0,%o2
7328    or\t%0,%2
7329    ork\t%0,%1,%2
7330    o\t%0,%2
7331    oy\t%0,%2
7332    #
7333    #"
7334   [(set_attr "op_type"  "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7335    (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7336    (set_attr "z10prop" "z10_super_E1,
7337                         z10_super_E1,
7338                         z10_super_E1,
7339                         z10_super_E1,
7340                         *,
7341                         z10_super_E1,
7342                         z10_super_E1,
7343                         *,
7344                         *")])
7345
7346 (define_insn "*iorsi3_esa"
7347   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7348         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7349                 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7350    (clobber (reg:CC CC_REGNUM))]
7351   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7352   "@
7353    or\t%0,%2
7354    o\t%0,%2
7355    #
7356    #"
7357   [(set_attr "op_type"  "RR,RX,SI,SS")
7358    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7359
7360 (define_split
7361   [(set (match_operand:SI 0 "s_operand" "")
7362         (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7363    (clobber (reg:CC CC_REGNUM))]
7364   "reload_completed"
7365   [(parallel
7366     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7367      (clobber (reg:CC CC_REGNUM))])]
7368   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7369
7370 ;
7371 ; iorhi3 instruction pattern(s).
7372 ;
7373
7374 (define_insn "*iorhi3_zarch"
7375   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7376         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7377                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQH0,Q")))
7378    (clobber (reg:CC CC_REGNUM))]
7379   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7380   "@
7381    or\t%0,%2
7382    ork\t%0,%1,%2
7383    oill\t%0,%x2
7384    #
7385    #"
7386   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7387    (set_attr "cpu_facility" "*,z196,*,*,*")
7388    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7389
7390 (define_insn "*iorhi3_esa"
7391   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7392         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7393                 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7394    (clobber (reg:CC CC_REGNUM))]
7395   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7396   "@
7397    or\t%0,%2
7398    #
7399    #"
7400   [(set_attr "op_type"  "RR,SI,SS")
7401    (set_attr "z10prop" "z10_super_E1,*,*")])
7402
7403 (define_split
7404   [(set (match_operand:HI 0 "s_operand" "")
7405         (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7406    (clobber (reg:CC CC_REGNUM))]
7407   "reload_completed"
7408   [(parallel
7409     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7410      (clobber (reg:CC CC_REGNUM))])]
7411   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7412
7413 ;
7414 ; iorqi3 instruction pattern(s).
7415 ;
7416
7417 (define_insn "*iorqi3_zarch"
7418   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7419         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7420                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7421    (clobber (reg:CC CC_REGNUM))]
7422   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7423   "@
7424    or\t%0,%2
7425    ork\t%0,%1,%2
7426    oill\t%0,%b2
7427    oi\t%S0,%b2
7428    oiy\t%S0,%b2
7429    #"
7430   [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7431    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7432    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7433                         z10_super,z10_super,*")])
7434
7435 (define_insn "*iorqi3_esa"
7436   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7437         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7438                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7439    (clobber (reg:CC CC_REGNUM))]
7440   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7441   "@
7442    or\t%0,%2
7443    oi\t%S0,%b2
7444    #"
7445   [(set_attr "op_type"  "RR,SI,SS")
7446    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7447
7448 ;
7449 ; Block inclusive or (OC) patterns.
7450 ;
7451
7452 (define_insn "*oc"
7453   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7454         (ior:BLK (match_dup 0)
7455                  (match_operand:BLK 1 "memory_operand" "Q")))
7456    (use (match_operand 2 "const_int_operand" "n"))
7457    (clobber (reg:CC CC_REGNUM))]
7458   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7459   "oc\t%O0(%2,%R0),%S1"
7460   [(set_attr "op_type" "SS")
7461    (set_attr "z196prop" "z196_cracked")])
7462
7463 (define_split
7464   [(set (match_operand 0 "memory_operand" "")
7465         (ior (match_dup 0)
7466              (match_operand 1 "memory_operand" "")))
7467    (clobber (reg:CC CC_REGNUM))]
7468   "reload_completed
7469    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7470    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7471   [(parallel
7472     [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7473      (use (match_dup 2))
7474      (clobber (reg:CC CC_REGNUM))])]
7475 {
7476   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7477   operands[0] = adjust_address (operands[0], BLKmode, 0);
7478   operands[1] = adjust_address (operands[1], BLKmode, 0);
7479 })
7480
7481 (define_peephole2
7482   [(parallel
7483     [(set (match_operand:BLK 0 "memory_operand" "")
7484           (ior:BLK (match_dup 0)
7485                    (match_operand:BLK 1 "memory_operand" "")))
7486      (use (match_operand 2 "const_int_operand" ""))
7487      (clobber (reg:CC CC_REGNUM))])
7488    (parallel
7489     [(set (match_operand:BLK 3 "memory_operand" "")
7490           (ior:BLK (match_dup 3)
7491                    (match_operand:BLK 4 "memory_operand" "")))
7492      (use (match_operand 5 "const_int_operand" ""))
7493      (clobber (reg:CC CC_REGNUM))])]
7494   "s390_offset_p (operands[0], operands[3], operands[2])
7495    && s390_offset_p (operands[1], operands[4], operands[2])
7496    && !s390_overlap_p (operands[0], operands[1],
7497                        INTVAL (operands[2]) + INTVAL (operands[5]))
7498    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7499   [(parallel
7500     [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7501      (use (match_dup 8))
7502      (clobber (reg:CC CC_REGNUM))])]
7503   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7504    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7505    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7506
7507
7508 ;;
7509 ;;- Xor instructions.
7510 ;;
7511
7512 (define_expand "xor<mode>3"
7513   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7514         (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7515                  (match_operand:INT 2 "general_operand" "")))
7516    (clobber (reg:CC CC_REGNUM))]
7517   ""
7518   "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7519
7520 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7521 ; simplifications.  So its better to have something matching.
7522 (define_split
7523   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7524         (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7525   ""
7526   [(parallel
7527     [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7528      (clobber (reg:CC CC_REGNUM))])]
7529 {
7530   operands[2] = constm1_rtx;
7531   if (!s390_logical_operator_ok_p (operands))
7532     FAIL;
7533 })
7534
7535 ;
7536 ; xordi3 instruction pattern(s).
7537 ;
7538
7539 (define_insn "*xordi3_cc"
7540   [(set (reg CC_REGNUM)
7541         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7542                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7543                  (const_int 0)))
7544    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7545         (xor:DI (match_dup 1) (match_dup 2)))]
7546   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7547   "@
7548    xgr\t%0,%2
7549    xgrk\t%0,%1,%2
7550    xg\t%0,%2"
7551   [(set_attr "op_type" "RRE,RRF,RXY")
7552    (set_attr "cpu_facility" "*,z196,*")
7553    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7554
7555 (define_insn "*xordi3_cconly"
7556   [(set (reg CC_REGNUM)
7557         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7558                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7559                  (const_int 0)))
7560    (clobber (match_scratch:DI 0                                     "=d,d, d"))]
7561   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7562   "@
7563    xgr\t%0,%2
7564    xgrk\t%0,%1,%2
7565    xg\t%0,%2"
7566   [(set_attr "op_type" "RRE,RRF,RXY")
7567    (set_attr "cpu_facility" "*,z196,*")
7568    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7569
7570 (define_insn "*xordi3"
7571   [(set (match_operand:DI 0 "nonimmediate_operand"         "=d,    d,d,d, d,   AQ,Q")
7572         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,    0,0,d, 0,    0,0")
7573                 (match_operand:DI 2 "general_operand"   "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7574    (clobber (reg:CC CC_REGNUM))]
7575   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7576   "@
7577    xihf\t%0,%k2
7578    xilf\t%0,%k2
7579    xgr\t%0,%2
7580    xgrk\t%0,%1,%2
7581    xg\t%0,%2
7582    #
7583    #"
7584   [(set_attr "op_type"  "RIL,RIL,RRE,RRF,RXY,SI,SS")
7585    (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7586    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7587                         *,z10_super_E1,*,*")])
7588
7589 (define_split
7590   [(set (match_operand:DI 0 "s_operand" "")
7591         (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7592    (clobber (reg:CC CC_REGNUM))]
7593   "reload_completed"
7594   [(parallel
7595     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7596      (clobber (reg:CC CC_REGNUM))])]
7597   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7598
7599 ;
7600 ; xorsi3 instruction pattern(s).
7601 ;
7602
7603 (define_insn "*xorsi3_cc"
7604   [(set (reg CC_REGNUM)
7605         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7606                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7607                  (const_int 0)))
7608    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7609         (xor:SI (match_dup 1) (match_dup 2)))]
7610   "s390_match_ccmode(insn, CCTmode)"
7611   "@
7612    xilf\t%0,%o2
7613    xr\t%0,%2
7614    xrk\t%0,%1,%2
7615    x\t%0,%2
7616    xy\t%0,%2"
7617   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7618    (set_attr "cpu_facility" "*,*,z196,*,*")
7619    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7620                         z10_super_E1,z10_super_E1")])
7621
7622 (define_insn "*xorsi3_cconly"
7623   [(set (reg CC_REGNUM)
7624         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7625                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7626                  (const_int 0)))
7627    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7628   "s390_match_ccmode(insn, CCTmode)"
7629   "@
7630    xilf\t%0,%o2
7631    xr\t%0,%2
7632    xrk\t%0,%1,%2
7633    x\t%0,%2
7634    xy\t%0,%2"
7635   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7636    (set_attr "cpu_facility" "*,*,z196,*,*")
7637    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7638                         z10_super_E1,z10_super_E1")])
7639
7640 (define_insn "*xorsi3"
7641   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,d,d,d,   AQ,Q")
7642         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    0,0")
7643                 (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxQS0,Q")))
7644    (clobber (reg:CC CC_REGNUM))]
7645   "s390_logical_operator_ok_p (operands)"
7646   "@
7647    xilf\t%0,%o2
7648    xr\t%0,%2
7649    xrk\t%0,%1,%2
7650    x\t%0,%2
7651    xy\t%0,%2
7652    #
7653    #"
7654   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,SI,SS")
7655    (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7656    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7657                         z10_super_E1,z10_super_E1,*,*")])
7658
7659 (define_split
7660   [(set (match_operand:SI 0 "s_operand" "")
7661         (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7662    (clobber (reg:CC CC_REGNUM))]
7663   "reload_completed"
7664   [(parallel
7665     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7666      (clobber (reg:CC CC_REGNUM))])]
7667   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7668
7669 ;
7670 ; xorhi3 instruction pattern(s).
7671 ;
7672
7673 (define_insn "*xorhi3"
7674   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7675         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d,    0,0")
7676                 (match_operand:HI 2 "general_operand"      "Os,d,d,NxQH0,Q")))
7677    (clobber (reg:CC CC_REGNUM))]
7678   "s390_logical_operator_ok_p (operands)"
7679   "@
7680    xilf\t%0,%x2
7681    xr\t%0,%2
7682    xrk\t%0,%1,%2
7683    #
7684    #"
7685   [(set_attr "op_type"  "RIL,RR,RRF,SI,SS")
7686    (set_attr "cpu_facility" "*,*,z196,*,*")
7687    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7688
7689 (define_split
7690   [(set (match_operand:HI 0 "s_operand" "")
7691         (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7692    (clobber (reg:CC CC_REGNUM))]
7693   "reload_completed"
7694   [(parallel
7695     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7696      (clobber (reg:CC CC_REGNUM))])]
7697   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7698
7699 ;
7700 ; xorqi3 instruction pattern(s).
7701 ;
7702
7703 (define_insn "*xorqi3"
7704   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7705         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7706                 (match_operand:QI 2 "general_operand"      "Os,d,d,n,n,Q")))
7707    (clobber (reg:CC CC_REGNUM))]
7708   "s390_logical_operator_ok_p (operands)"
7709   "@
7710    xilf\t%0,%b2
7711    xr\t%0,%2
7712    xrk\t%0,%1,%2
7713    xi\t%S0,%b2
7714    xiy\t%S0,%b2
7715    #"
7716   [(set_attr "op_type"  "RIL,RR,RRF,SI,SIY,SS")
7717    (set_attr "cpu_facility" "*,*,z196,*,*,*")
7718    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7719
7720
7721 ;
7722 ; Block exclusive or (XC) patterns.
7723 ;
7724
7725 (define_insn "*xc"
7726   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7727         (xor:BLK (match_dup 0)
7728                  (match_operand:BLK 1 "memory_operand" "Q")))
7729    (use (match_operand 2 "const_int_operand" "n"))
7730    (clobber (reg:CC CC_REGNUM))]
7731   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7732   "xc\t%O0(%2,%R0),%S1"
7733   [(set_attr "op_type" "SS")])
7734
7735 (define_split
7736   [(set (match_operand 0 "memory_operand" "")
7737         (xor (match_dup 0)
7738              (match_operand 1 "memory_operand" "")))
7739    (clobber (reg:CC CC_REGNUM))]
7740   "reload_completed
7741    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7742    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7743   [(parallel
7744     [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7745      (use (match_dup 2))
7746      (clobber (reg:CC CC_REGNUM))])]
7747 {
7748   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7749   operands[0] = adjust_address (operands[0], BLKmode, 0);
7750   operands[1] = adjust_address (operands[1], BLKmode, 0);
7751 })
7752
7753 (define_peephole2
7754   [(parallel
7755     [(set (match_operand:BLK 0 "memory_operand" "")
7756           (xor:BLK (match_dup 0)
7757                    (match_operand:BLK 1 "memory_operand" "")))
7758      (use (match_operand 2 "const_int_operand" ""))
7759      (clobber (reg:CC CC_REGNUM))])
7760    (parallel
7761     [(set (match_operand:BLK 3 "memory_operand" "")
7762           (xor:BLK (match_dup 3)
7763                    (match_operand:BLK 4 "memory_operand" "")))
7764      (use (match_operand 5 "const_int_operand" ""))
7765      (clobber (reg:CC CC_REGNUM))])]
7766   "s390_offset_p (operands[0], operands[3], operands[2])
7767    && s390_offset_p (operands[1], operands[4], operands[2])
7768    && !s390_overlap_p (operands[0], operands[1],
7769                        INTVAL (operands[2]) + INTVAL (operands[5]))
7770    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7771   [(parallel
7772     [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7773      (use (match_dup 8))
7774      (clobber (reg:CC CC_REGNUM))])]
7775   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7776    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7777    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7778
7779 ;
7780 ; Block xor (XC) patterns with src == dest.
7781 ;
7782
7783 (define_insn "*xc_zero"
7784   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7785         (const_int 0))
7786    (use (match_operand 1 "const_int_operand" "n"))
7787    (clobber (reg:CC CC_REGNUM))]
7788   "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7789   "xc\t%O0(%1,%R0),%S0"
7790   [(set_attr "op_type" "SS")
7791    (set_attr "z196prop" "z196_cracked")])
7792
7793 (define_peephole2
7794   [(parallel
7795     [(set (match_operand:BLK 0 "memory_operand" "")
7796           (const_int 0))
7797      (use (match_operand 1 "const_int_operand" ""))
7798      (clobber (reg:CC CC_REGNUM))])
7799    (parallel
7800     [(set (match_operand:BLK 2 "memory_operand" "")
7801           (const_int 0))
7802      (use (match_operand 3 "const_int_operand" ""))
7803      (clobber (reg:CC CC_REGNUM))])]
7804   "s390_offset_p (operands[0], operands[2], operands[1])
7805    && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7806   [(parallel
7807     [(set (match_dup 4) (const_int 0))
7808      (use (match_dup 5))
7809      (clobber (reg:CC CC_REGNUM))])]
7810   "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7811    operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7812
7813
7814 ;;
7815 ;;- Negate instructions.
7816 ;;
7817
7818 ;
7819 ; neg(di|si)2 instruction pattern(s).
7820 ;
7821
7822 (define_expand "neg<mode>2"
7823   [(parallel
7824     [(set (match_operand:DSI 0 "register_operand" "=d")
7825           (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7826      (clobber (reg:CC CC_REGNUM))])]
7827   ""
7828   "")
7829
7830 (define_insn "*negdi2_sign_cc"
7831   [(set (reg CC_REGNUM)
7832         (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7833                            (match_operand:SI 1 "register_operand" "d") 0)
7834                            (const_int 32)) (const_int 32)))
7835                  (const_int 0)))
7836    (set (match_operand:DI 0 "register_operand" "=d")
7837         (neg:DI (sign_extend:DI (match_dup 1))))]
7838   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7839   "lcgfr\t%0,%1"
7840   [(set_attr "op_type"  "RRE")
7841    (set_attr "z10prop" "z10_c")])
7842
7843 (define_insn "*negdi2_sign"
7844   [(set (match_operand:DI 0 "register_operand" "=d")
7845         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7846    (clobber (reg:CC CC_REGNUM))]
7847   "TARGET_ZARCH"
7848   "lcgfr\t%0,%1"
7849   [(set_attr "op_type"  "RRE")
7850    (set_attr "z10prop" "z10_c")])
7851
7852 ; lcr, lcgr
7853 (define_insn "*neg<mode>2_cc"
7854   [(set (reg CC_REGNUM)
7855         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7856                  (const_int 0)))
7857    (set (match_operand:GPR 0 "register_operand" "=d")
7858         (neg:GPR (match_dup 1)))]
7859   "s390_match_ccmode (insn, CCAmode)"
7860   "lc<g>r\t%0,%1"
7861   [(set_attr "op_type"  "RR<E>")
7862    (set_attr "z10prop" "z10_super_c_E1")])
7863
7864 ; lcr, lcgr
7865 (define_insn "*neg<mode>2_cconly"
7866   [(set (reg CC_REGNUM)
7867         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7868                  (const_int 0)))
7869    (clobber (match_scratch:GPR 0 "=d"))]
7870   "s390_match_ccmode (insn, CCAmode)"
7871   "lc<g>r\t%0,%1"
7872   [(set_attr "op_type"  "RR<E>")
7873    (set_attr "z10prop" "z10_super_c_E1")])
7874
7875 ; lcr, lcgr
7876 (define_insn "*neg<mode>2"
7877   [(set (match_operand:GPR 0 "register_operand" "=d")
7878         (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7879    (clobber (reg:CC CC_REGNUM))]
7880   ""
7881   "lc<g>r\t%0,%1"
7882   [(set_attr "op_type"  "RR<E>")
7883    (set_attr "z10prop" "z10_super_c_E1")])
7884
7885 (define_insn "*negdi2_31"
7886   [(set (match_operand:DI 0 "register_operand" "=d")
7887         (neg:DI (match_operand:DI 1 "register_operand" "d")))
7888    (clobber (reg:CC CC_REGNUM))]
7889   "!TARGET_ZARCH"
7890   "#")
7891
7892 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7893
7894 ; Doing the twos complement separately on the SImode parts does an
7895 ; unwanted +1 on the high part which needs to be subtracted afterwards
7896 ; ... unless the +1 on the low part created an overflow.
7897
7898 (define_split
7899   [(set (match_operand:DI 0 "register_operand" "")
7900         (neg:DI (match_operand:DI 1 "register_operand" "")))
7901    (clobber (reg:CC CC_REGNUM))]
7902   "!TARGET_ZARCH
7903    && (REGNO (operands[0]) == REGNO (operands[1])
7904       || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7905    && reload_completed"
7906   [(parallel
7907     [(set (match_dup 2) (neg:SI (match_dup 3)))
7908      (clobber (reg:CC CC_REGNUM))])
7909    (parallel
7910     [(set (reg:CCAP CC_REGNUM)
7911           (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7912      (set (match_dup 4) (neg:SI (match_dup 5)))])
7913    (set (pc)
7914         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7915                       (pc)
7916                       (label_ref (match_dup 6))))
7917    (parallel
7918     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7919      (clobber (reg:CC CC_REGNUM))])
7920    (match_dup 6)]
7921   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7922    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7923    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7924    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7925    operands[6] = gen_label_rtx ();")
7926
7927 ; Like above but first make a copy of the low part of the src operand
7928 ; since it might overlap with the high part of the destination.
7929
7930 (define_split
7931   [(set (match_operand:DI 0 "register_operand" "")
7932         (neg:DI (match_operand:DI 1 "register_operand" "")))
7933    (clobber (reg:CC CC_REGNUM))]
7934   "!TARGET_ZARCH
7935    && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7936    && reload_completed"
7937   [; Make a backup of op5 first
7938    (set (match_dup 4) (match_dup 5))
7939    ; Setting op2 here might clobber op5
7940    (parallel
7941     [(set (match_dup 2) (neg:SI (match_dup 3)))
7942      (clobber (reg:CC CC_REGNUM))])
7943    (parallel
7944     [(set (reg:CCAP CC_REGNUM)
7945           (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7946      (set (match_dup 4) (neg:SI (match_dup 4)))])
7947    (set (pc)
7948         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7949                       (pc)
7950                       (label_ref (match_dup 6))))
7951    (parallel
7952     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7953      (clobber (reg:CC CC_REGNUM))])
7954    (match_dup 6)]
7955   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7956    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7957    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7958    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7959    operands[6] = gen_label_rtx ();")
7960
7961 ;
7962 ; neg(df|sf)2 instruction pattern(s).
7963 ;
7964
7965 (define_expand "neg<mode>2"
7966   [(parallel
7967     [(set (match_operand:BFP 0 "register_operand" "=f")
7968           (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7969      (clobber (reg:CC CC_REGNUM))])]
7970   "TARGET_HARD_FLOAT"
7971   "")
7972
7973 ; lcxbr, lcdbr, lcebr
7974 (define_insn "*neg<mode>2_cc"
7975   [(set (reg CC_REGNUM)
7976         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7977                  (match_operand:BFP 2 "const0_operand" "")))
7978    (set (match_operand:BFP 0 "register_operand" "=f")
7979         (neg:BFP (match_dup 1)))]
7980   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7981   "lc<xde>br\t%0,%1"
7982   [(set_attr "op_type"  "RRE")
7983    (set_attr "type"     "fsimp<mode>")])
7984
7985 ; lcxbr, lcdbr, lcebr
7986 (define_insn "*neg<mode>2_cconly"
7987   [(set (reg CC_REGNUM)
7988         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7989                  (match_operand:BFP 2 "const0_operand" "")))
7990    (clobber (match_scratch:BFP 0 "=f"))]
7991   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7992   "lc<xde>br\t%0,%1"
7993   [(set_attr "op_type"  "RRE")
7994    (set_attr "type"     "fsimp<mode>")])
7995
7996 ; lcdfr
7997 (define_insn "*neg<mode>2_nocc"
7998   [(set (match_operand:FP 0 "register_operand"         "=f")
7999         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8000   "TARGET_DFP"
8001   "lcdfr\t%0,%1"
8002   [(set_attr "op_type"  "RRE")
8003    (set_attr "type"     "fsimp<mode>")])
8004
8005 ; lcxbr, lcdbr, lcebr
8006 ; FIXME: wflcdb does not clobber cc
8007 (define_insn "*neg<mode>2"
8008   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8009         (neg:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8010    (clobber (reg:CC CC_REGNUM))]
8011   "TARGET_HARD_FLOAT"
8012   "@
8013    lc<xde>br\t%0,%1
8014    wflcdb\t%0,%1"
8015   [(set_attr "op_type"      "RRE,VRR")
8016    (set_attr "cpu_facility" "*,vec")
8017    (set_attr "type"         "fsimp<mode>,*")
8018    (set_attr "enabled"      "*,<DFDI>")])
8019
8020
8021 ;;
8022 ;;- Absolute value instructions.
8023 ;;
8024
8025 ;
8026 ; abs(di|si)2 instruction pattern(s).
8027 ;
8028
8029 (define_insn "*absdi2_sign_cc"
8030   [(set (reg CC_REGNUM)
8031         (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8032                            (match_operand:SI 1 "register_operand" "d") 0)
8033                            (const_int 32)) (const_int 32)))
8034                  (const_int 0)))
8035    (set (match_operand:DI 0 "register_operand" "=d")
8036         (abs:DI (sign_extend:DI (match_dup 1))))]
8037   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8038   "lpgfr\t%0,%1"
8039   [(set_attr "op_type"  "RRE")
8040    (set_attr "z10prop" "z10_c")])
8041
8042 (define_insn "*absdi2_sign"
8043   [(set (match_operand:DI 0 "register_operand" "=d")
8044         (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8045    (clobber (reg:CC CC_REGNUM))]
8046   "TARGET_ZARCH"
8047   "lpgfr\t%0,%1"
8048   [(set_attr "op_type"  "RRE")
8049    (set_attr "z10prop" "z10_c")])
8050
8051 ; lpr, lpgr
8052 (define_insn "*abs<mode>2_cc"
8053   [(set (reg CC_REGNUM)
8054         (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8055                  (const_int 0)))
8056    (set (match_operand:GPR 0 "register_operand" "=d")
8057         (abs:GPR (match_dup 1)))]
8058   "s390_match_ccmode (insn, CCAmode)"
8059   "lp<g>r\t%0,%1"
8060   [(set_attr "op_type"  "RR<E>")
8061    (set_attr "z10prop" "z10_c")])
8062
8063 ; lpr, lpgr
8064 (define_insn "*abs<mode>2_cconly"
8065   [(set (reg CC_REGNUM)
8066         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8067                  (const_int 0)))
8068    (clobber (match_scratch:GPR 0 "=d"))]
8069   "s390_match_ccmode (insn, CCAmode)"
8070   "lp<g>r\t%0,%1"
8071   [(set_attr "op_type"  "RR<E>")
8072    (set_attr "z10prop" "z10_c")])
8073
8074 ; lpr, lpgr
8075 (define_insn "abs<mode>2"
8076   [(set (match_operand:GPR 0 "register_operand" "=d")
8077         (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8078    (clobber (reg:CC CC_REGNUM))]
8079   ""
8080   "lp<g>r\t%0,%1"
8081   [(set_attr "op_type"  "RR<E>")
8082    (set_attr "z10prop" "z10_c")])
8083
8084 ;
8085 ; abs(df|sf)2 instruction pattern(s).
8086 ;
8087
8088 (define_expand "abs<mode>2"
8089   [(parallel
8090     [(set (match_operand:BFP 0 "register_operand" "=f")
8091           (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8092      (clobber (reg:CC CC_REGNUM))])]
8093   "TARGET_HARD_FLOAT"
8094   "")
8095
8096 ; lpxbr, lpdbr, lpebr
8097 (define_insn "*abs<mode>2_cc"
8098   [(set (reg CC_REGNUM)
8099         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8100                  (match_operand:BFP 2 "const0_operand" "")))
8101    (set (match_operand:BFP 0 "register_operand" "=f")
8102         (abs:BFP (match_dup 1)))]
8103   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8104   "lp<xde>br\t%0,%1"
8105   [(set_attr "op_type"  "RRE")
8106    (set_attr "type"     "fsimp<mode>")])
8107
8108 ; lpxbr, lpdbr, lpebr
8109 (define_insn "*abs<mode>2_cconly"
8110   [(set (reg CC_REGNUM)
8111         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8112                  (match_operand:BFP 2 "const0_operand" "")))
8113    (clobber (match_scratch:BFP 0 "=f"))]
8114   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8115   "lp<xde>br\t%0,%1"
8116   [(set_attr "op_type"  "RRE")
8117    (set_attr "type"     "fsimp<mode>")])
8118
8119 ; lpdfr
8120 (define_insn "*abs<mode>2_nocc"
8121   [(set (match_operand:FP 0 "register_operand"         "=f")
8122         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8123   "TARGET_DFP"
8124   "lpdfr\t%0,%1"
8125   [(set_attr "op_type"  "RRE")
8126    (set_attr "type"     "fsimp<mode>")])
8127
8128 ; lpxbr, lpdbr, lpebr
8129 ; FIXME: wflpdb does not clobber cc
8130 (define_insn "*abs<mode>2"
8131   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8132         (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8133    (clobber (reg:CC CC_REGNUM))]
8134   "TARGET_HARD_FLOAT"
8135   "@
8136     lp<xde>br\t%0,%1
8137     wflpdb\t%0,%1"
8138   [(set_attr "op_type"      "RRE,VRR")
8139    (set_attr "cpu_facility" "*,vec")
8140    (set_attr "type"         "fsimp<mode>,*")
8141    (set_attr "enabled"      "*,<DFDI>")])
8142
8143
8144 ;;
8145 ;;- Negated absolute value instructions
8146 ;;
8147
8148 ;
8149 ; Integer
8150 ;
8151
8152 (define_insn "*negabsdi2_sign_cc"
8153   [(set (reg CC_REGNUM)
8154         (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8155                            (match_operand:SI 1 "register_operand" "d") 0)
8156                            (const_int 32)) (const_int 32))))
8157                  (const_int 0)))
8158    (set (match_operand:DI 0 "register_operand" "=d")
8159         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8160   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8161   "lngfr\t%0,%1"
8162   [(set_attr "op_type"  "RRE")
8163    (set_attr "z10prop" "z10_c")])
8164
8165 (define_insn "*negabsdi2_sign"
8166   [(set (match_operand:DI 0 "register_operand" "=d")
8167         (neg:DI (abs:DI (sign_extend:DI
8168                           (match_operand:SI 1 "register_operand" "d")))))
8169    (clobber (reg:CC CC_REGNUM))]
8170   "TARGET_ZARCH"
8171   "lngfr\t%0,%1"
8172   [(set_attr "op_type" "RRE")
8173    (set_attr "z10prop" "z10_c")])
8174
8175 ; lnr, lngr
8176 (define_insn "*negabs<mode>2_cc"
8177   [(set (reg CC_REGNUM)
8178         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8179                  (const_int 0)))
8180    (set (match_operand:GPR 0 "register_operand" "=d")
8181         (neg:GPR (abs:GPR (match_dup 1))))]
8182   "s390_match_ccmode (insn, CCAmode)"
8183   "ln<g>r\t%0,%1"
8184   [(set_attr "op_type"  "RR<E>")
8185    (set_attr "z10prop" "z10_c")])
8186
8187 ; lnr, lngr
8188 (define_insn "*negabs<mode>2_cconly"
8189   [(set (reg CC_REGNUM)
8190         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8191                  (const_int 0)))
8192    (clobber (match_scratch:GPR 0 "=d"))]
8193   "s390_match_ccmode (insn, CCAmode)"
8194   "ln<g>r\t%0,%1"
8195   [(set_attr "op_type"  "RR<E>")
8196    (set_attr "z10prop" "z10_c")])
8197
8198 ; lnr, lngr
8199 (define_insn "*negabs<mode>2"
8200   [(set (match_operand:GPR 0 "register_operand" "=d")
8201         (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8202    (clobber (reg:CC CC_REGNUM))]
8203   ""
8204   "ln<g>r\t%0,%1"
8205   [(set_attr "op_type" "RR<E>")
8206    (set_attr "z10prop" "z10_c")])
8207
8208 ;
8209 ; Floating point
8210 ;
8211
8212 ; lnxbr, lndbr, lnebr
8213 (define_insn "*negabs<mode>2_cc"
8214   [(set (reg CC_REGNUM)
8215         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8216                  (match_operand:BFP 2 "const0_operand" "")))
8217    (set (match_operand:BFP 0 "register_operand" "=f")
8218         (neg:BFP (abs:BFP (match_dup 1))))]
8219   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8220   "ln<xde>br\t%0,%1"
8221   [(set_attr "op_type"  "RRE")
8222    (set_attr "type"     "fsimp<mode>")])
8223
8224 ; lnxbr, lndbr, lnebr
8225 (define_insn "*negabs<mode>2_cconly"
8226   [(set (reg CC_REGNUM)
8227         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8228                  (match_operand:BFP 2 "const0_operand" "")))
8229    (clobber (match_scratch:BFP 0 "=f"))]
8230   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8231   "ln<xde>br\t%0,%1"
8232   [(set_attr "op_type"  "RRE")
8233    (set_attr "type"     "fsimp<mode>")])
8234
8235 ; lndfr
8236 (define_insn "*negabs<mode>2_nocc"
8237   [(set (match_operand:FP 0 "register_operand"                  "=f")
8238         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8239   "TARGET_DFP"
8240   "lndfr\t%0,%1"
8241   [(set_attr "op_type"  "RRE")
8242    (set_attr "type"     "fsimp<mode>")])
8243
8244 ; lnxbr, lndbr, lnebr
8245 ; FIXME: wflndb does not clobber cc
8246 (define_insn "*negabs<mode>2"
8247   [(set (match_operand:BFP                   0 "register_operand" "=f,v")
8248         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v"))))
8249    (clobber (reg:CC CC_REGNUM))]
8250   "TARGET_HARD_FLOAT"
8251   "@
8252    ln<xde>br\t%0,%1
8253    wflndb\t%0,%1"
8254   [(set_attr "op_type"      "RRE,VRR")
8255    (set_attr "cpu_facility" "*,vec")
8256    (set_attr "type"         "fsimp<mode>,*")
8257    (set_attr "enabled"      "*,<DFDI>")])
8258
8259 ;;
8260 ;;- Square root instructions.
8261 ;;
8262
8263 ;
8264 ; sqrt(df|sf)2 instruction pattern(s).
8265 ;
8266
8267 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8268 (define_insn "sqrt<mode>2"
8269   [(set (match_operand:BFP           0 "register_operand" "=f,f,v")
8270         (sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,R,v")))]
8271   "TARGET_HARD_FLOAT"
8272   "@
8273    sq<xde>br\t%0,%1
8274    sq<xde>b\t%0,%1
8275    wfsqdb\t%v0,%v1"
8276   [(set_attr "op_type"      "RRE,RXE,VRR")
8277    (set_attr "type"         "fsqrt<mode>")
8278    (set_attr "cpu_facility" "*,*,vec")
8279    (set_attr "enabled"      "*,<DSF>,<DFDI>")])
8280
8281
8282 ;;
8283 ;;- One complement instructions.
8284 ;;
8285
8286 ;
8287 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8288 ;
8289
8290 (define_expand "one_cmpl<mode>2"
8291   [(parallel
8292     [(set (match_operand:INT 0 "register_operand" "")
8293           (xor:INT (match_operand:INT 1 "register_operand" "")
8294                    (const_int -1)))
8295      (clobber (reg:CC CC_REGNUM))])]
8296   ""
8297   "")
8298
8299
8300 ;;
8301 ;; Find leftmost bit instructions.
8302 ;;
8303
8304 (define_expand "clzdi2"
8305   [(set (match_operand:DI 0 "register_operand" "=d")
8306         (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8307   "TARGET_EXTIMM && TARGET_ZARCH"
8308 {
8309   rtx insn, clz_equal;
8310   rtx wide_reg = gen_reg_rtx (TImode);
8311   rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8312
8313   clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8314
8315   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8316
8317   insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8318   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8319
8320   DONE;
8321 })
8322
8323 (define_insn "clztidi2"
8324   [(set (match_operand:TI 0 "register_operand" "=d")
8325         (ior:TI
8326           (ashift:TI
8327             (zero_extend:TI
8328               (xor:DI (match_operand:DI 1 "register_operand" "d")
8329                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8330                                 (subreg:SI (clz:DI (match_dup 1)) 4))))
8331
8332             (const_int 64))
8333           (zero_extend:TI (clz:DI (match_dup 1)))))
8334    (clobber (reg:CC CC_REGNUM))]
8335   "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8336    == (unsigned HOST_WIDE_INT) 1 << 63
8337    && TARGET_EXTIMM && TARGET_ZARCH"
8338   "flogr\t%0,%1"
8339   [(set_attr "op_type"  "RRE")])
8340
8341
8342 ;;
8343 ;;- Rotate instructions.
8344 ;;
8345
8346 ;
8347 ; rotl(di|si)3 instruction pattern(s).
8348 ;
8349
8350 (define_expand "rotl<mode>3"
8351   [(set (match_operand:GPR 0 "register_operand" "")
8352         (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8353                     (match_operand:SI 2 "nonmemory_operand" "")))]
8354   "TARGET_CPU_ZARCH"
8355   "")
8356
8357 ; rll, rllg
8358 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8359   [(set (match_operand:GPR             0 "register_operand"  "=d")
8360         (rotate:GPR (match_operand:GPR 1 "register_operand"   "d")
8361                     (match_operand:SI  2 "nonmemory_operand" "an")))]
8362   "TARGET_CPU_ZARCH"
8363   "rll<g>\t%0,%1,<addr_style_op_ops>"
8364   [(set_attr "op_type"  "RSE")
8365    (set_attr "atype"    "reg")
8366    (set_attr "z10prop"  "z10_super_E1")])
8367
8368
8369 ;;
8370 ;;- Shift instructions.
8371 ;;
8372
8373 ;
8374 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8375 ; Left shifts and logical right shifts
8376
8377 (define_expand "<shift><mode>3"
8378   [(set (match_operand:DSI 0 "register_operand" "")
8379         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8380                    (match_operand:SI 2 "nonmemory_operand" "")))]
8381   ""
8382   "")
8383
8384 ; ESA 64 bit register pair shift with reg or imm shift count
8385 ; sldl, srdl
8386 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8387   [(set (match_operand:DI 0 "register_operand"            "=d")
8388         (SHIFT:DI (match_operand:DI 1 "register_operand"   "0")
8389                   (match_operand:SI 2 "nonmemory_operand" "an")))]
8390   "!TARGET_ZARCH"
8391   "s<lr>dl\t%0,<addr_style_op_ops>"
8392   [(set_attr "op_type"  "RS")
8393    (set_attr "atype"    "reg")
8394    (set_attr "z196prop" "z196_cracked")])
8395
8396
8397 ; 64 bit register shift with reg or imm shift count
8398 ; sll, srl, sllg, srlg, sllk, srlk
8399 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8400   [(set (match_operand:GPR 0 "register_operand"              "=d, d")
8401         (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8402                    (match_operand:SI 2 "nonmemory_operand"   "an,an")))]
8403   ""
8404   "@
8405    s<lr>l<g>\t%0,<1><addr_style_op_ops>
8406    s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8407   [(set_attr "op_type"  "RS<E>,RSY")
8408    (set_attr "atype"    "reg,reg")
8409    (set_attr "cpu_facility" "*,z196")
8410    (set_attr "z10prop"  "z10_super_E1,*")])
8411
8412 ;
8413 ; ashr(di|si)3 instruction pattern(s).
8414 ; Arithmetic right shifts
8415
8416 (define_expand "ashr<mode>3"
8417   [(parallel
8418     [(set (match_operand:DSI 0 "register_operand" "")
8419           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8420                         (match_operand:SI 2 "nonmemory_operand" "")))
8421      (clobber (reg:CC CC_REGNUM))])]
8422   ""
8423   "")
8424
8425 ; FIXME: The number of alternatives is doubled here to match the fix
8426 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8427 ; The right fix should be to support match_scratch in the output
8428 ; pattern of a define_subst.
8429 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8430   [(set (match_operand:DI 0 "register_operand"               "=d, d")
8431         (ashiftrt:DI (match_operand:DI 1 "register_operand"   "0, 0")
8432                      (match_operand:SI 2 "nonmemory_operand" "an,an")))
8433    (clobber (reg:CC CC_REGNUM))]
8434   "!TARGET_ZARCH"
8435   "@
8436    srda\t%0,<addr_style_op_cc_ops>
8437    srda\t%0,<addr_style_op_cc_ops>"
8438   [(set_attr "op_type" "RS")
8439    (set_attr "atype"   "reg")])
8440
8441
8442 ; sra, srag
8443 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8444   [(set (match_operand:GPR 0 "register_operand"                 "=d, d")
8445         (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8446                       (match_operand:SI 2 "nonmemory_operand"   "an,an")))
8447    (clobber (reg:CC CC_REGNUM))]
8448   ""
8449   "@
8450    sra<g>\t%0,<1><addr_style_op_cc_ops>
8451    sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8452   [(set_attr "op_type"  "RS<E>,RSY")
8453    (set_attr "atype"    "reg")
8454    (set_attr "cpu_facility" "*,z196")
8455    (set_attr "z10prop" "z10_super_E1,*")])
8456
8457
8458 ;;
8459 ;; Branch instruction patterns.
8460 ;;
8461
8462 (define_expand "cbranch<mode>4"
8463   [(set (pc)
8464         (if_then_else (match_operator 0 "comparison_operator"
8465                        [(match_operand:GPR 1 "register_operand" "")
8466                         (match_operand:GPR 2 "general_operand" "")])
8467                       (label_ref (match_operand 3 "" ""))
8468                       (pc)))]
8469   ""
8470   "s390_emit_jump (operands[3],
8471     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8472    DONE;")
8473
8474 (define_expand "cbranch<mode>4"
8475   [(set (pc)
8476         (if_then_else (match_operator 0 "comparison_operator"
8477                        [(match_operand:FP 1 "register_operand" "")
8478                         (match_operand:FP 2 "general_operand" "")])
8479                       (label_ref (match_operand 3 "" ""))
8480                       (pc)))]
8481   "TARGET_HARD_FLOAT"
8482   "s390_emit_jump (operands[3],
8483     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8484    DONE;")
8485
8486 (define_expand "cbranchcc4"
8487   [(set (pc)
8488         (if_then_else (match_operator 0 "s390_comparison"
8489                        [(match_operand 1 "cc_reg_operand" "")
8490                         (match_operand 2 "const_int_operand" "")])
8491                       (label_ref (match_operand 3 "" ""))
8492                       (pc)))]
8493   ""
8494   "")
8495
8496
8497 ;;
8498 ;;- Conditional jump instructions.
8499 ;;
8500
8501 (define_insn "*cjump_64"
8502   [(set (pc)
8503         (if_then_else
8504           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8505                                                (match_operand 2 "const_int_operand" "")])
8506           (label_ref (match_operand 0 "" ""))
8507           (pc)))]
8508   "TARGET_CPU_ZARCH"
8509 {
8510   if (get_attr_length (insn) == 4)
8511     return "j%C1\t%l0";
8512   else
8513     return "jg%C1\t%l0";
8514 }
8515   [(set_attr "op_type" "RI")
8516    (set_attr "type"    "branch")
8517    (set (attr "length")
8518         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8519                       (const_int 4) (const_int 6)))])
8520
8521 (define_insn "*cjump_31"
8522   [(set (pc)
8523         (if_then_else
8524           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8525                                                (match_operand 2 "const_int_operand" "")])
8526           (label_ref (match_operand 0 "" ""))
8527           (pc)))]
8528   "!TARGET_CPU_ZARCH"
8529 {
8530   gcc_assert (get_attr_length (insn) == 4);
8531   return "j%C1\t%l0";
8532 }
8533   [(set_attr "op_type" "RI")
8534    (set_attr "type"    "branch")
8535    (set (attr "length")
8536         (if_then_else (not (match_test "flag_pic"))
8537           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8538                         (const_int 4) (const_int 6))
8539           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8540                         (const_int 4) (const_int 8))))])
8541
8542 (define_insn "*cjump_long"
8543   [(set (pc)
8544         (if_then_else
8545           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8546           (match_operand 0 "address_operand" "ZQZR")
8547           (pc)))]
8548   ""
8549 {
8550   if (get_attr_op_type (insn) == OP_TYPE_RR)
8551     return "b%C1r\t%0";
8552   else
8553     return "b%C1\t%a0";
8554 }
8555   [(set (attr "op_type")
8556         (if_then_else (match_operand 0 "register_operand" "")
8557                       (const_string "RR") (const_string "RX")))
8558    (set_attr "type"  "branch")
8559    (set_attr "atype" "agen")])
8560
8561 ;; A conditional return instruction.
8562 (define_insn "*c<code>"
8563   [(set (pc)
8564         (if_then_else
8565           (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8566           (ANY_RETURN)
8567           (pc)))]
8568   "s390_can_use_<code>_insn ()"
8569   "b%C0r\t%%r14"
8570   [(set_attr "op_type" "RR")
8571    (set_attr "type"  "jsr")
8572    (set_attr "atype" "agen")])
8573
8574 ;;
8575 ;;- Negated conditional jump instructions.
8576 ;;
8577
8578 (define_insn "*icjump_64"
8579   [(set (pc)
8580         (if_then_else
8581           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8582           (pc)
8583           (label_ref (match_operand 0 "" ""))))]
8584   "TARGET_CPU_ZARCH"
8585 {
8586   if (get_attr_length (insn) == 4)
8587     return "j%D1\t%l0";
8588   else
8589     return "jg%D1\t%l0";
8590 }
8591   [(set_attr "op_type" "RI")
8592    (set_attr "type"    "branch")
8593    (set (attr "length")
8594         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8595                       (const_int 4) (const_int 6)))])
8596
8597 (define_insn "*icjump_31"
8598   [(set (pc)
8599         (if_then_else
8600           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8601           (pc)
8602           (label_ref (match_operand 0 "" ""))))]
8603   "!TARGET_CPU_ZARCH"
8604 {
8605   gcc_assert (get_attr_length (insn) == 4);
8606   return "j%D1\t%l0";
8607 }
8608   [(set_attr "op_type" "RI")
8609    (set_attr "type"    "branch")
8610    (set (attr "length")
8611         (if_then_else (not (match_test "flag_pic"))
8612           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8613                         (const_int 4) (const_int 6))
8614           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8615                         (const_int 4) (const_int 8))))])
8616
8617 (define_insn "*icjump_long"
8618   [(set (pc)
8619         (if_then_else
8620           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8621           (pc)
8622           (match_operand 0 "address_operand" "ZQZR")))]
8623   ""
8624 {
8625   if (get_attr_op_type (insn) == OP_TYPE_RR)
8626     return "b%D1r\t%0";
8627   else
8628     return "b%D1\t%a0";
8629 }
8630   [(set (attr "op_type")
8631         (if_then_else (match_operand 0 "register_operand" "")
8632                       (const_string "RR") (const_string "RX")))
8633    (set_attr "type"  "branch")
8634    (set_attr "atype" "agen")])
8635
8636 ;;
8637 ;;- Trap instructions.
8638 ;;
8639
8640 (define_insn "trap"
8641   [(trap_if (const_int 1) (const_int 0))]
8642   ""
8643   "j\t.+2"
8644   [(set_attr "op_type" "RI")
8645    (set_attr "type"  "branch")])
8646
8647 (define_expand "ctrap<mode>4"
8648   [(trap_if (match_operator 0 "comparison_operator"
8649              [(match_operand:GPR 1 "register_operand" "")
8650               (match_operand:GPR 2 "general_operand" "")])
8651              (match_operand 3 "const0_operand" ""))]
8652   ""
8653   {
8654     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8655                                   operands[1], operands[2]);
8656     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8657     DONE;
8658   })
8659
8660 (define_expand "ctrap<mode>4"
8661   [(trap_if (match_operator 0 "comparison_operator"
8662              [(match_operand:FP 1 "register_operand" "")
8663               (match_operand:FP 2 "general_operand" "")])
8664              (match_operand 3 "const0_operand" ""))]
8665   ""
8666   {
8667     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8668                                   operands[1], operands[2]);
8669     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8670     DONE;
8671   })
8672
8673 (define_insn "condtrap"
8674   [(trap_if (match_operator 0 "s390_comparison"
8675              [(match_operand 1 "cc_reg_operand" "c")
8676               (const_int 0)])
8677             (const_int 0))]
8678   ""
8679   "j%C0\t.+2";
8680   [(set_attr "op_type" "RI")
8681    (set_attr "type"  "branch")])
8682
8683 ; crt, cgrt, cit, cgit
8684 (define_insn "*cmp_and_trap_signed_int<mode>"
8685   [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8686                [(match_operand:GPR 1 "register_operand"  "d,d")
8687                 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8688             (const_int 0))]
8689   "TARGET_Z10"
8690   "@
8691    c<g>rt%C0\t%1,%2
8692    c<g>it%C0\t%1,%h2"
8693   [(set_attr "op_type" "RRF,RIE")
8694    (set_attr "type"    "branch")
8695    (set_attr "z10prop" "z10_super_c,z10_super")])
8696
8697 ; clrt, clgrt, clfit, clgit, clt, clgt
8698 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8699   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8700                [(match_operand:GPR 1 "register_operand" "d,d, d")
8701                 (match_operand:GPR 2 "general_operand"  "d,D,RT")])
8702             (const_int 0))]
8703   "TARGET_Z10"
8704   "@
8705    cl<g>rt%C0\t%1,%2
8706    cl<gf>it%C0\t%1,%x2
8707    cl<g>t%C0\t%1,%2"
8708   [(set_attr "op_type"      "RRF,RIE,RSY")
8709    (set_attr "type"         "branch")
8710    (set_attr "z10prop"      "z10_super_c,z10_super,*")
8711    (set_attr "cpu_facility" "z10,z10,zEC12")])
8712
8713 ; lat, lgat
8714 (define_insn "*load_and_trap<mode>"
8715   [(trap_if (eq (match_operand:GPR 0 "memory_operand"  "RT")
8716                 (const_int 0))
8717             (const_int 0))
8718    (set (match_operand:GPR 1 "register_operand" "=d")
8719         (match_dup 0))]
8720   "TARGET_ZEC12"
8721   "l<g>at\t%1,%0"
8722   [(set_attr "op_type" "RXY")])
8723
8724
8725 ;;
8726 ;;- Loop instructions.
8727 ;;
8728 ;;  This is all complicated by the fact that since this is a jump insn
8729 ;;  we must handle our own output reloads.
8730
8731 ;; branch on index
8732
8733 ; This splitter will be matched by combine and has to add the 2 moves
8734 ; necessary to load the compare and the increment values into a
8735 ; register pair as needed by brxle.
8736
8737 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8738   [(set (pc)
8739         (if_then_else
8740          (match_operator 6 "s390_brx_operator"
8741             [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8742                        (match_operand:GPR 2 "general_operand"  ""))
8743              (match_operand:GPR 3 "register_operand" "")])
8744          (label_ref (match_operand 0 "" ""))
8745          (pc)))
8746    (set (match_operand:GPR 4 "nonimmediate_operand" "")
8747         (plus:GPR (match_dup 1) (match_dup 2)))
8748    (clobber (match_scratch:GPR 5 ""))]
8749   "TARGET_CPU_ZARCH"
8750   "#"
8751   "!reload_completed && !reload_in_progress"
8752   [(set (match_dup 7) (match_dup 2)) ; the increment
8753    (set (match_dup 8) (match_dup 3)) ; the comparison value
8754    (parallel [(set (pc)
8755                    (if_then_else
8756                     (match_op_dup 6
8757                        [(plus:GPR (match_dup 1) (match_dup 7))
8758                         (match_dup 8)])
8759                     (label_ref (match_dup 0))
8760                     (pc)))
8761               (set (match_dup 4)
8762                    (plus:GPR (match_dup 1) (match_dup 7)))
8763               (clobber (match_dup 5))
8764               (clobber (reg:CC CC_REGNUM))])]
8765   {
8766     rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8767     operands[7] = gen_lowpart (<GPR:MODE>mode,
8768                                gen_highpart (word_mode, dreg));
8769     operands[8] = gen_lowpart (<GPR:MODE>mode,
8770                                gen_lowpart (word_mode, dreg));
8771   })
8772
8773 ; brxlg, brxhg
8774
8775 (define_insn_and_split "*brxg_64bit"
8776   [(set (pc)
8777         (if_then_else
8778           (match_operator 5 "s390_brx_operator"
8779              [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8780                        (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8781               (subreg:DI (match_dup 2) 8)])
8782           (label_ref (match_operand 0 "" ""))
8783           (pc)))
8784    (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8785         (plus:DI (match_dup 1)
8786                  (subreg:DI (match_dup 2) 0)))
8787    (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8788    (clobber (reg:CC CC_REGNUM))]
8789   "TARGET_ZARCH"
8790 {
8791   if (which_alternative != 0)
8792     return "#";
8793   else if (get_attr_length (insn) == 6)
8794     return "brx%E5g\t%1,%2,%l0";
8795   else
8796     return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8797 }
8798   "&& reload_completed
8799    && (!REG_P (operands[3])
8800        || !rtx_equal_p (operands[1], operands[3]))"
8801   [(set (match_dup 4) (match_dup 1))
8802    (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8803               (clobber (reg:CC CC_REGNUM))])
8804    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8805    (set (match_dup 3) (match_dup 4))
8806    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8807                            (label_ref (match_dup 0))
8808                            (pc)))]
8809   ""
8810   [(set_attr "op_type"  "RIE")
8811    (set_attr "type"  "branch")
8812    (set (attr "length")
8813         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8814                       (const_int 6) (const_int 16)))])
8815
8816 ; brxle, brxh
8817
8818 (define_insn_and_split "*brx_64bit"
8819   [(set (pc)
8820         (if_then_else
8821           (match_operator 5 "s390_brx_operator"
8822              [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8823                        (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8824               (subreg:SI (match_dup 2) 12)])
8825           (label_ref (match_operand 0 "" ""))
8826           (pc)))
8827    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8828         (plus:SI (match_dup 1)
8829                  (subreg:SI (match_dup 2) 4)))
8830    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8831    (clobber (reg:CC CC_REGNUM))]
8832   "TARGET_ZARCH"
8833 {
8834   if (which_alternative != 0)
8835     return "#";
8836   else if (get_attr_length (insn) == 6)
8837     return "brx%C5\t%1,%2,%l0";
8838   else
8839     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8840 }
8841   "&& reload_completed
8842    && (!REG_P (operands[3])
8843        || !rtx_equal_p (operands[1], operands[3]))"
8844   [(set (match_dup 4) (match_dup 1))
8845    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8846               (clobber (reg:CC CC_REGNUM))])
8847    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8848    (set (match_dup 3) (match_dup 4))
8849    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8850                            (label_ref (match_dup 0))
8851                            (pc)))]
8852   ""
8853   [(set_attr "op_type"  "RSI")
8854    (set_attr "type"  "branch")
8855    (set (attr "length")
8856         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8857                       (const_int 6) (const_int 14)))])
8858
8859 ; brxle, brxh
8860
8861 (define_insn_and_split "*brx_31bit"
8862   [(set (pc)
8863         (if_then_else
8864           (match_operator 5 "s390_brx_operator"
8865             [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8866                       (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8867              (subreg:SI (match_dup 2) 4)])
8868           (label_ref (match_operand 0 "" ""))
8869           (pc)))
8870    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8871         (plus:SI (match_dup 1)
8872                  (subreg:SI (match_dup 2) 0)))
8873    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8874    (clobber (reg:CC CC_REGNUM))]
8875   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8876 {
8877   if (which_alternative != 0)
8878     return "#";
8879   else if (get_attr_length (insn) == 6)
8880     return "brx%C5\t%1,%2,%l0";
8881   else
8882     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8883 }
8884   "&& reload_completed
8885    && (!REG_P (operands[3])
8886        || !rtx_equal_p (operands[1], operands[3]))"
8887   [(set (match_dup 4) (match_dup 1))
8888    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8889               (clobber (reg:CC CC_REGNUM))])
8890    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8891    (set (match_dup 3) (match_dup 4))
8892    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8893                            (label_ref (match_dup 0))
8894                            (pc)))]
8895   ""
8896   [(set_attr "op_type"  "RSI")
8897    (set_attr "type"  "branch")
8898    (set (attr "length")
8899         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8900                       (const_int 6) (const_int 14)))])
8901
8902
8903 ;; branch on count
8904
8905 (define_expand "doloop_end"
8906   [(use (match_operand 0 "" ""))        ; loop pseudo
8907    (use (match_operand 1 "" ""))]       ; label
8908   ""
8909 {
8910   if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8911     emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8912   else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8913     emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8914   else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8915     emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8916   else
8917     FAIL;
8918
8919   DONE;
8920 })
8921
8922 (define_insn_and_split "doloop_si64"
8923   [(set (pc)
8924         (if_then_else
8925           (ne (match_operand:SI 1 "register_operand" "d,d,d")
8926               (const_int 1))
8927           (label_ref (match_operand 0 "" ""))
8928           (pc)))
8929    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8930         (plus:SI (match_dup 1) (const_int -1)))
8931    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8932    (clobber (reg:CC CC_REGNUM))]
8933   "TARGET_CPU_ZARCH"
8934 {
8935   if (which_alternative != 0)
8936     return "#";
8937   else if (get_attr_length (insn) == 4)
8938     return "brct\t%1,%l0";
8939   else
8940     return "ahi\t%1,-1\;jgne\t%l0";
8941 }
8942   "&& reload_completed
8943    && (! REG_P (operands[2])
8944        || ! rtx_equal_p (operands[1], operands[2]))"
8945   [(set (match_dup 3) (match_dup 1))
8946    (parallel [(set (reg:CCAN CC_REGNUM)
8947                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8948                                  (const_int 0)))
8949               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8950    (set (match_dup 2) (match_dup 3))
8951    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8952                            (label_ref (match_dup 0))
8953                            (pc)))]
8954   ""
8955   [(set_attr "op_type"  "RI")
8956    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8957    ; hurt us in the (rare) case of ahi.
8958    (set_attr "z10prop"  "z10_super_E1")
8959    (set_attr "type"  "branch")
8960    (set (attr "length")
8961         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8962                       (const_int 4) (const_int 10)))])
8963
8964 (define_insn_and_split "doloop_si31"
8965   [(set (pc)
8966         (if_then_else
8967           (ne (match_operand:SI 1 "register_operand" "d,d,d")
8968               (const_int 1))
8969           (label_ref (match_operand 0 "" ""))
8970           (pc)))
8971    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8972         (plus:SI (match_dup 1) (const_int -1)))
8973    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8974    (clobber (reg:CC CC_REGNUM))]
8975   "!TARGET_CPU_ZARCH"
8976 {
8977   if (which_alternative != 0)
8978     return "#";
8979   else if (get_attr_length (insn) == 4)
8980     return "brct\t%1,%l0";
8981   else
8982     gcc_unreachable ();
8983 }
8984   "&& reload_completed
8985    && (! REG_P (operands[2])
8986        || ! rtx_equal_p (operands[1], operands[2]))"
8987   [(set (match_dup 3) (match_dup 1))
8988    (parallel [(set (reg:CCAN CC_REGNUM)
8989                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8990                                  (const_int 0)))
8991               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8992    (set (match_dup 2) (match_dup 3))
8993    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8994                            (label_ref (match_dup 0))
8995                            (pc)))]
8996   ""
8997   [(set_attr "op_type"  "RI")
8998    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8999    ; hurt us in the (rare) case of ahi.
9000    (set_attr "z10prop"  "z10_super_E1")
9001    (set_attr "type"  "branch")
9002    (set (attr "length")
9003         (if_then_else (not (match_test "flag_pic"))
9004           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9005                         (const_int 4) (const_int 6))
9006           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9007                         (const_int 4) (const_int 8))))])
9008
9009 (define_insn "*doloop_si_long"
9010   [(set (pc)
9011         (if_then_else
9012           (ne (match_operand:SI 1 "register_operand" "d")
9013               (const_int 1))
9014           (match_operand 0 "address_operand" "ZQZR")
9015           (pc)))
9016    (set (match_operand:SI 2 "register_operand" "=1")
9017         (plus:SI (match_dup 1) (const_int -1)))
9018    (clobber (match_scratch:SI 3 "=X"))
9019    (clobber (reg:CC CC_REGNUM))]
9020   "!TARGET_CPU_ZARCH"
9021 {
9022   if (get_attr_op_type (insn) == OP_TYPE_RR)
9023     return "bctr\t%1,%0";
9024   else
9025     return "bct\t%1,%a0";
9026 }
9027   [(set (attr "op_type")
9028         (if_then_else (match_operand 0 "register_operand" "")
9029                       (const_string "RR") (const_string "RX")))
9030    (set_attr "type"  "branch")
9031    (set_attr "atype" "agen")
9032    (set_attr "z10prop"  "z10_c")
9033    (set_attr "z196prop" "z196_cracked")])
9034
9035 (define_insn_and_split "doloop_di"
9036   [(set (pc)
9037         (if_then_else
9038           (ne (match_operand:DI 1 "register_operand" "d,d,d")
9039               (const_int 1))
9040           (label_ref (match_operand 0 "" ""))
9041           (pc)))
9042    (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9043         (plus:DI (match_dup 1) (const_int -1)))
9044    (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9045    (clobber (reg:CC CC_REGNUM))]
9046   "TARGET_ZARCH"
9047 {
9048   if (which_alternative != 0)
9049     return "#";
9050   else if (get_attr_length (insn) == 4)
9051     return "brctg\t%1,%l0";
9052   else
9053     return "aghi\t%1,-1\;jgne\t%l0";
9054 }
9055   "&& reload_completed
9056    && (! REG_P (operands[2])
9057        || ! rtx_equal_p (operands[1], operands[2]))"
9058   [(set (match_dup 3) (match_dup 1))
9059    (parallel [(set (reg:CCAN CC_REGNUM)
9060                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9061                                  (const_int 0)))
9062               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9063    (set (match_dup 2) (match_dup 3))
9064    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9065                            (label_ref (match_dup 0))
9066                            (pc)))]
9067   ""
9068   [(set_attr "op_type"  "RI")
9069    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9070    ; hurt us in the (rare) case of ahi.
9071    (set_attr "z10prop"  "z10_super_E1")
9072    (set_attr "type"  "branch")
9073    (set (attr "length")
9074         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9075                       (const_int 4) (const_int 10)))])
9076
9077 ;;
9078 ;;- Unconditional jump instructions.
9079 ;;
9080
9081 ;
9082 ; jump instruction pattern(s).
9083 ;
9084
9085 (define_expand "jump"
9086   [(match_operand 0 "" "")]
9087   ""
9088   "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9089
9090 (define_insn "*jump64"
9091   [(set (pc) (label_ref (match_operand 0 "" "")))]
9092   "TARGET_CPU_ZARCH"
9093 {
9094   if (get_attr_length (insn) == 4)
9095     return "j\t%l0";
9096   else
9097     return "jg\t%l0";
9098 }
9099   [(set_attr "op_type" "RI")
9100    (set_attr "type"  "branch")
9101    (set (attr "length")
9102         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9103                       (const_int 4) (const_int 6)))])
9104
9105 (define_insn "*jump31"
9106   [(set (pc) (label_ref (match_operand 0 "" "")))]
9107   "!TARGET_CPU_ZARCH"
9108 {
9109   gcc_assert (get_attr_length (insn) == 4);
9110   return "j\t%l0";
9111 }
9112   [(set_attr "op_type" "RI")
9113    (set_attr "type"  "branch")
9114    (set (attr "length")
9115         (if_then_else (not (match_test "flag_pic"))
9116           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9117                         (const_int 4) (const_int 6))
9118           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9119                         (const_int 4) (const_int 8))))])
9120
9121 ;
9122 ; indirect-jump instruction pattern(s).
9123 ;
9124
9125 (define_insn "indirect_jump"
9126  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
9127   ""
9128 {
9129   if (get_attr_op_type (insn) == OP_TYPE_RR)
9130     return "br\t%0";
9131   else
9132     return "b\t%a0";
9133 }
9134   [(set (attr "op_type")
9135         (if_then_else (match_operand 0 "register_operand" "")
9136                       (const_string "RR") (const_string "RX")))
9137    (set_attr "type"  "branch")
9138    (set_attr "atype" "agen")])
9139
9140 ;
9141 ; casesi instruction pattern(s).
9142 ;
9143
9144 (define_insn "casesi_jump"
9145  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
9146    (use (label_ref (match_operand 1 "" "")))]
9147   ""
9148 {
9149   if (get_attr_op_type (insn) == OP_TYPE_RR)
9150     return "br\t%0";
9151   else
9152     return "b\t%a0";
9153 }
9154   [(set (attr "op_type")
9155         (if_then_else (match_operand 0 "register_operand" "")
9156                       (const_string "RR") (const_string "RX")))
9157    (set_attr "type"  "branch")
9158    (set_attr "atype" "agen")])
9159
9160 (define_expand "casesi"
9161   [(match_operand:SI 0 "general_operand" "")
9162    (match_operand:SI 1 "general_operand" "")
9163    (match_operand:SI 2 "general_operand" "")
9164    (label_ref (match_operand 3 "" ""))
9165    (label_ref (match_operand 4 "" ""))]
9166   ""
9167 {
9168    rtx index  = gen_reg_rtx (SImode);
9169    rtx base   = gen_reg_rtx (Pmode);
9170    rtx target = gen_reg_rtx (Pmode);
9171
9172    emit_move_insn (index, operands[0]);
9173    emit_insn (gen_subsi3 (index, index, operands[1]));
9174    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9175                             operands[4]);
9176
9177    if (Pmode != SImode)
9178      index = convert_to_mode (Pmode, index, 1);
9179    if (GET_CODE (index) != REG)
9180      index = copy_to_mode_reg (Pmode, index);
9181
9182    if (TARGET_64BIT)
9183        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9184    else
9185        emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9186
9187    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9188
9189    index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9190    emit_move_insn (target, index);
9191
9192    if (flag_pic)
9193      target = gen_rtx_PLUS (Pmode, base, target);
9194    emit_jump_insn (gen_casesi_jump (target, operands[3]));
9195
9196    DONE;
9197 })
9198
9199
9200 ;;
9201 ;;- Jump to subroutine.
9202 ;;
9203 ;;
9204
9205 ;
9206 ; untyped call instruction pattern(s).
9207 ;
9208
9209 ;; Call subroutine returning any type.
9210 (define_expand "untyped_call"
9211   [(parallel [(call (match_operand 0 "" "")
9212                     (const_int 0))
9213               (match_operand 1 "" "")
9214               (match_operand 2 "" "")])]
9215   ""
9216 {
9217   int i;
9218
9219   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9220
9221   for (i = 0; i < XVECLEN (operands[2], 0); i++)
9222     {
9223       rtx set = XVECEXP (operands[2], 0, i);
9224       emit_move_insn (SET_DEST (set), SET_SRC (set));
9225     }
9226
9227   /* The optimizer does not know that the call sets the function value
9228      registers we stored in the result block.  We avoid problems by
9229      claiming that all hard registers are used and clobbered at this
9230      point.  */
9231   emit_insn (gen_blockage ());
9232
9233   DONE;
9234 })
9235
9236 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9237 ;; all of memory.  This blocks insns from being moved across this point.
9238
9239 (define_insn "blockage"
9240   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9241   ""
9242   ""
9243   [(set_attr "type"    "none")
9244    (set_attr "length"  "0")])
9245
9246 ;
9247 ; sibcall patterns
9248 ;
9249
9250 (define_expand "sibcall"
9251   [(call (match_operand 0 "" "")
9252          (match_operand 1 "" ""))]
9253   ""
9254 {
9255   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9256   DONE;
9257 })
9258
9259 (define_insn "*sibcall_br"
9260   [(call (mem:QI (reg SIBCALL_REGNUM))
9261          (match_operand 0 "const_int_operand" "n"))]
9262   "SIBLING_CALL_P (insn)
9263    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9264   "br\t%%r1"
9265   [(set_attr "op_type" "RR")
9266    (set_attr "type"  "branch")
9267    (set_attr "atype" "agen")])
9268
9269 (define_insn "*sibcall_brc"
9270   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9271          (match_operand 1 "const_int_operand" "n"))]
9272   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9273   "j\t%0"
9274   [(set_attr "op_type" "RI")
9275    (set_attr "type"    "branch")])
9276
9277 (define_insn "*sibcall_brcl"
9278   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9279          (match_operand 1 "const_int_operand" "n"))]
9280   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9281   "jg\t%0"
9282   [(set_attr "op_type" "RIL")
9283    (set_attr "type"    "branch")])
9284
9285 ;
9286 ; sibcall_value patterns
9287 ;
9288
9289 (define_expand "sibcall_value"
9290   [(set (match_operand 0 "" "")
9291         (call (match_operand 1 "" "")
9292               (match_operand 2 "" "")))]
9293   ""
9294 {
9295   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9296   DONE;
9297 })
9298
9299 (define_insn "*sibcall_value_br"
9300   [(set (match_operand 0 "" "")
9301         (call (mem:QI (reg SIBCALL_REGNUM))
9302               (match_operand 1 "const_int_operand" "n")))]
9303   "SIBLING_CALL_P (insn)
9304    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9305   "br\t%%r1"
9306   [(set_attr "op_type" "RR")
9307    (set_attr "type"  "branch")
9308    (set_attr "atype" "agen")])
9309
9310 (define_insn "*sibcall_value_brc"
9311   [(set (match_operand 0 "" "")
9312         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9313               (match_operand 2 "const_int_operand" "n")))]
9314   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9315   "j\t%1"
9316   [(set_attr "op_type" "RI")
9317    (set_attr "type"    "branch")])
9318
9319 (define_insn "*sibcall_value_brcl"
9320   [(set (match_operand 0 "" "")
9321         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9322               (match_operand 2 "const_int_operand" "n")))]
9323   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9324   "jg\t%1"
9325   [(set_attr "op_type" "RIL")
9326    (set_attr "type"    "branch")])
9327
9328
9329 ;
9330 ; call instruction pattern(s).
9331 ;
9332
9333 (define_expand "call"
9334   [(call (match_operand 0 "" "")
9335          (match_operand 1 "" ""))
9336    (use (match_operand 2 "" ""))]
9337   ""
9338 {
9339   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9340                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9341   DONE;
9342 })
9343
9344 (define_insn "*bras"
9345   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9346          (match_operand 1 "const_int_operand" "n"))
9347    (clobber (match_operand 2 "register_operand" "=r"))]
9348   "!SIBLING_CALL_P (insn)
9349    && TARGET_SMALL_EXEC
9350    && GET_MODE (operands[2]) == Pmode"
9351   "bras\t%2,%0"
9352   [(set_attr "op_type" "RI")
9353    (set_attr "type"    "jsr")
9354    (set_attr "z196prop" "z196_cracked")])
9355
9356 (define_insn "*brasl"
9357   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9358          (match_operand 1 "const_int_operand" "n"))
9359    (clobber (match_operand 2 "register_operand" "=r"))]
9360   "!SIBLING_CALL_P (insn)
9361    && TARGET_CPU_ZARCH
9362    && GET_MODE (operands[2]) == Pmode"
9363   "brasl\t%2,%0"
9364   [(set_attr "op_type" "RIL")
9365    (set_attr "type"    "jsr")
9366    (set_attr "z196prop" "z196_cracked")])
9367
9368 (define_insn "*basr"
9369   [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9370          (match_operand 1 "const_int_operand" "n"))
9371    (clobber (match_operand 2 "register_operand" "=r"))]
9372   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9373 {
9374   if (get_attr_op_type (insn) == OP_TYPE_RR)
9375     return "basr\t%2,%0";
9376   else
9377     return "bas\t%2,%a0";
9378 }
9379   [(set (attr "op_type")
9380         (if_then_else (match_operand 0 "register_operand" "")
9381                       (const_string "RR") (const_string "RX")))
9382    (set_attr "type"  "jsr")
9383    (set_attr "atype" "agen")
9384    (set_attr "z196prop" "z196_cracked")])
9385
9386 ;
9387 ; call_value instruction pattern(s).
9388 ;
9389
9390 (define_expand "call_value"
9391   [(set (match_operand 0 "" "")
9392         (call (match_operand 1 "" "")
9393               (match_operand 2 "" "")))
9394    (use (match_operand 3 "" ""))]
9395   ""
9396 {
9397   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9398                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9399   DONE;
9400 })
9401
9402 (define_insn "*bras_r"
9403   [(set (match_operand 0 "" "")
9404         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9405               (match_operand:SI 2 "const_int_operand" "n")))
9406    (clobber (match_operand 3 "register_operand" "=r"))]
9407   "!SIBLING_CALL_P (insn)
9408    && TARGET_SMALL_EXEC
9409    && GET_MODE (operands[3]) == Pmode"
9410   "bras\t%3,%1"
9411   [(set_attr "op_type" "RI")
9412    (set_attr "type"    "jsr")
9413    (set_attr "z196prop" "z196_cracked")])
9414
9415 (define_insn "*brasl_r"
9416   [(set (match_operand 0 "" "")
9417         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9418               (match_operand 2 "const_int_operand" "n")))
9419    (clobber (match_operand 3 "register_operand" "=r"))]
9420   "!SIBLING_CALL_P (insn)
9421    && TARGET_CPU_ZARCH
9422    && GET_MODE (operands[3]) == Pmode"
9423   "brasl\t%3,%1"
9424   [(set_attr "op_type" "RIL")
9425    (set_attr "type"    "jsr")
9426    (set_attr "z196prop" "z196_cracked")])
9427
9428 (define_insn "*basr_r"
9429   [(set (match_operand 0 "" "")
9430         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9431               (match_operand 2 "const_int_operand" "n")))
9432    (clobber (match_operand 3 "register_operand" "=r"))]
9433   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9434 {
9435   if (get_attr_op_type (insn) == OP_TYPE_RR)
9436     return "basr\t%3,%1";
9437   else
9438     return "bas\t%3,%a1";
9439 }
9440   [(set (attr "op_type")
9441         (if_then_else (match_operand 1 "register_operand" "")
9442                       (const_string "RR") (const_string "RX")))
9443    (set_attr "type"  "jsr")
9444    (set_attr "atype" "agen")
9445    (set_attr "z196prop" "z196_cracked")])
9446
9447 ;;
9448 ;;- Thread-local storage support.
9449 ;;
9450
9451 (define_expand "get_thread_pointer<mode>"
9452   [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9453   ""
9454   "")
9455
9456 (define_expand "set_thread_pointer<mode>"
9457   [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9458    (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9459   ""
9460   "")
9461
9462 (define_insn "*set_tp"
9463   [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9464   ""
9465   ""
9466   [(set_attr "type" "none")
9467    (set_attr "length" "0")])
9468
9469 (define_insn "*tls_load_64"
9470   [(set (match_operand:DI 0 "register_operand" "=d")
9471         (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9472                     (match_operand:DI 2 "" "")]
9473                    UNSPEC_TLS_LOAD))]
9474   "TARGET_64BIT"
9475   "lg\t%0,%1%J2"
9476   [(set_attr "op_type" "RXE")
9477    (set_attr "z10prop" "z10_fwd_A3")])
9478
9479 (define_insn "*tls_load_31"
9480   [(set (match_operand:SI 0 "register_operand" "=d,d")
9481         (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9482                     (match_operand:SI 2 "" "")]
9483                    UNSPEC_TLS_LOAD))]
9484   "!TARGET_64BIT"
9485   "@
9486    l\t%0,%1%J2
9487    ly\t%0,%1%J2"
9488   [(set_attr "op_type" "RX,RXY")
9489    (set_attr "type" "load")
9490    (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9491
9492 (define_insn "*bras_tls"
9493   [(set (match_operand 0 "" "")
9494         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9495               (match_operand 2 "const_int_operand" "n")))
9496    (clobber (match_operand 3 "register_operand" "=r"))
9497    (use (match_operand 4 "" ""))]
9498   "!SIBLING_CALL_P (insn)
9499    && TARGET_SMALL_EXEC
9500    && GET_MODE (operands[3]) == Pmode"
9501   "bras\t%3,%1%J4"
9502   [(set_attr "op_type" "RI")
9503    (set_attr "type"    "jsr")
9504    (set_attr "z196prop" "z196_cracked")])
9505
9506 (define_insn "*brasl_tls"
9507   [(set (match_operand 0 "" "")
9508         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9509               (match_operand 2 "const_int_operand" "n")))
9510    (clobber (match_operand 3 "register_operand" "=r"))
9511    (use (match_operand 4 "" ""))]
9512   "!SIBLING_CALL_P (insn)
9513    && TARGET_CPU_ZARCH
9514    && GET_MODE (operands[3]) == Pmode"
9515   "brasl\t%3,%1%J4"
9516   [(set_attr "op_type" "RIL")
9517    (set_attr "type"    "jsr")
9518    (set_attr "z196prop" "z196_cracked")])
9519
9520 (define_insn "*basr_tls"
9521   [(set (match_operand 0 "" "")
9522         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9523               (match_operand 2 "const_int_operand" "n")))
9524    (clobber (match_operand 3 "register_operand" "=r"))
9525    (use (match_operand 4 "" ""))]
9526   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9527 {
9528   if (get_attr_op_type (insn) == OP_TYPE_RR)
9529     return "basr\t%3,%1%J4";
9530   else
9531     return "bas\t%3,%a1%J4";
9532 }
9533   [(set (attr "op_type")
9534         (if_then_else (match_operand 1 "register_operand" "")
9535                       (const_string "RR") (const_string "RX")))
9536    (set_attr "type"  "jsr")
9537    (set_attr "atype" "agen")
9538    (set_attr "z196prop" "z196_cracked")])
9539
9540 ;;
9541 ;;- Atomic operations
9542 ;;
9543
9544 ;
9545 ; memory barrier patterns.
9546 ;
9547
9548 (define_expand "mem_signal_fence"
9549   [(match_operand:SI 0 "const_int_operand")]            ;; model
9550   ""
9551 {
9552   /* The s390 memory model is strong enough not to require any
9553      barrier in order to synchronize a thread with itself.  */
9554   DONE;
9555 })
9556
9557 (define_expand "mem_thread_fence"
9558   [(match_operand:SI 0 "const_int_operand")]            ;; model
9559   ""
9560 {
9561   /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9562      enough not to require barriers of any kind.  */
9563   if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9564     {
9565       rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9566       MEM_VOLATILE_P (mem) = 1;
9567       emit_insn (gen_mem_thread_fence_1 (mem));
9568     }
9569   DONE;
9570 })
9571
9572 ; Although bcr is superscalar on Z10, this variant will never
9573 ; become part of an execution group.
9574 ; With z196 we can make use of the fast-BCR-serialization facility.
9575 ; This allows for a slightly faster sync which is sufficient for our
9576 ; purposes.
9577 (define_insn "mem_thread_fence_1"
9578   [(set (match_operand:BLK 0 "" "")
9579         (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9580   ""
9581 {
9582   if (TARGET_Z196)
9583     return "bcr\t14,0";
9584   else
9585     return "bcr\t15,0";
9586 }
9587   [(set_attr "op_type" "RR")
9588    (set_attr "mnemonic" "bcr_flush")
9589    (set_attr "z196prop" "z196_alone")])
9590
9591 ;
9592 ; atomic load/store operations
9593 ;
9594
9595 ; Atomic loads need not examine the memory model at all.
9596 (define_expand "atomic_load<mode>"
9597   [(match_operand:DINT 0 "register_operand")    ;; output
9598    (match_operand:DINT 1 "memory_operand")      ;; memory
9599    (match_operand:SI 2 "const_int_operand")]    ;; model
9600   ""
9601 {
9602   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9603     FAIL;
9604
9605   if (<MODE>mode == TImode)
9606     emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9607   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9608     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9609   else
9610     emit_move_insn (operands[0], operands[1]);
9611   DONE;
9612 })
9613
9614 ; Different from movdi_31 in that we want no splitters.
9615 (define_insn "atomic_loaddi_1"
9616   [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9617         (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9618                    UNSPEC_MOVA))]
9619   "!TARGET_ZARCH"
9620   "@
9621    lm\t%0,%M0,%S1
9622    lmy\t%0,%M0,%S1
9623    ld\t%0,%1
9624    ldy\t%0,%1"
9625   [(set_attr "op_type" "RS,RSY,RS,RSY")
9626    (set_attr "type" "lm,lm,floaddf,floaddf")])
9627
9628 (define_insn "atomic_loadti_1"
9629   [(set (match_operand:TI 0 "register_operand" "=r")
9630         (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9631                    UNSPEC_MOVA))]
9632   "TARGET_ZARCH"
9633   "lpq\t%0,%1"
9634   [(set_attr "op_type" "RXY")
9635    (set_attr "type" "other")])
9636
9637 ; Atomic stores must(?) enforce sequential consistency.
9638 (define_expand "atomic_store<mode>"
9639   [(match_operand:DINT 0 "memory_operand")      ;; memory
9640    (match_operand:DINT 1 "register_operand")    ;; input
9641    (match_operand:SI 2 "const_int_operand")]    ;; model
9642   ""
9643 {
9644   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9645
9646   if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9647     FAIL;
9648
9649   if (<MODE>mode == TImode)
9650     emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9651   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9652     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9653   else
9654     emit_move_insn (operands[0], operands[1]);
9655   if (is_mm_seq_cst (model))
9656     emit_insn (gen_mem_thread_fence (operands[2]));
9657   DONE;
9658 })
9659
9660 ; Different from movdi_31 in that we want no splitters.
9661 (define_insn "atomic_storedi_1"
9662   [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9663         (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9664                    UNSPEC_MOVA))]
9665   "!TARGET_ZARCH"
9666   "@
9667    stm\t%1,%N1,%S0
9668    stmy\t%1,%N1,%S0
9669    std %1,%0
9670    stdy %1,%0"
9671   [(set_attr "op_type" "RS,RSY,RS,RSY")
9672    (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9673
9674 (define_insn "atomic_storeti_1"
9675   [(set (match_operand:TI 0 "memory_operand" "=RT")
9676         (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9677                    UNSPEC_MOVA))]
9678   "TARGET_ZARCH"
9679   "stpq\t%1,%0"
9680   [(set_attr "op_type" "RXY")
9681    (set_attr "type" "other")])
9682
9683 ;
9684 ; compare and swap patterns.
9685 ;
9686
9687 (define_expand "atomic_compare_and_swap<mode>"
9688   [(match_operand:SI 0 "register_operand")      ;; bool success output
9689    (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9690    (match_operand:DGPR 2 "memory_operand")      ;; memory
9691    (match_operand:DGPR 3 "register_operand")    ;; expected intput
9692    (match_operand:DGPR 4 "register_operand")    ;; newval intput
9693    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9694    (match_operand:SI 6 "const_int_operand")     ;; success model
9695    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9696   ""
9697 {
9698   rtx cc, cmp, output = operands[1];
9699
9700   if (!register_operand (output, <MODE>mode))
9701     output = gen_reg_rtx (<MODE>mode);
9702
9703   if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9704     FAIL;
9705
9706   emit_insn (gen_atomic_compare_and_swap<mode>_internal
9707              (output, operands[2], operands[3], operands[4]));
9708
9709   /* We deliberately accept non-register operands in the predicate
9710      to ensure the write back to the output operand happens *before*
9711      the store-flags code below.  This makes it easier for combine
9712      to merge the store-flags code with a potential test-and-branch
9713      pattern following (immediately!) afterwards.  */
9714   if (output != operands[1])
9715     emit_move_insn (operands[1], output);
9716
9717   cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9718   cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9719   emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9720   DONE;
9721 })
9722
9723 (define_expand "atomic_compare_and_swap<mode>"
9724   [(match_operand:SI 0 "register_operand")      ;; bool success output
9725    (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9726    (match_operand:HQI 2 "memory_operand")       ;; memory
9727    (match_operand:HQI 3 "general_operand")      ;; expected intput
9728    (match_operand:HQI 4 "general_operand")      ;; newval intput
9729    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9730    (match_operand:SI 6 "const_int_operand")     ;; success model
9731    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9732   ""
9733 {
9734   s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9735                       operands[3], operands[4], INTVAL (operands[5]));
9736   DONE;
9737 })
9738
9739 (define_expand "atomic_compare_and_swap<mode>_internal"
9740   [(parallel
9741      [(set (match_operand:DGPR 0 "register_operand")
9742            (match_operand:DGPR 1 "memory_operand"))
9743       (set (match_dup 1)
9744            (unspec_volatile:DGPR
9745              [(match_dup 1)
9746               (match_operand:DGPR 2 "register_operand")
9747               (match_operand:DGPR 3 "register_operand")]
9748              UNSPECV_CAS))
9749       (set (reg:CCZ1 CC_REGNUM)
9750            (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9751   "")
9752
9753 ; cdsg, csg
9754 (define_insn "*atomic_compare_and_swap<mode>_1"
9755   [(set (match_operand:TDI 0 "register_operand" "=r")
9756         (match_operand:TDI 1 "memory_operand" "+QS"))
9757    (set (match_dup 1)
9758         (unspec_volatile:TDI
9759           [(match_dup 1)
9760            (match_operand:TDI 2 "register_operand" "0")
9761            (match_operand:TDI 3 "register_operand" "r")]
9762           UNSPECV_CAS))
9763    (set (reg:CCZ1 CC_REGNUM)
9764         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9765   "TARGET_ZARCH"
9766   "c<td>sg\t%0,%3,%S1"
9767   [(set_attr "op_type" "RSY")
9768    (set_attr "type"   "sem")])
9769
9770 ; cds, cdsy
9771 (define_insn "*atomic_compare_and_swapdi_2"
9772   [(set (match_operand:DI 0 "register_operand" "=r,r")
9773         (match_operand:DI 1 "memory_operand" "+Q,S"))
9774    (set (match_dup 1)
9775         (unspec_volatile:DI
9776           [(match_dup 1)
9777            (match_operand:DI 2 "register_operand" "0,0")
9778            (match_operand:DI 3 "register_operand" "r,r")]
9779           UNSPECV_CAS))
9780    (set (reg:CCZ1 CC_REGNUM)
9781         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9782   "!TARGET_ZARCH"
9783   "@
9784    cds\t%0,%3,%S1
9785    cdsy\t%0,%3,%S1"
9786   [(set_attr "op_type" "RS,RSY")
9787    (set_attr "type" "sem")])
9788
9789 ; cs, csy
9790 (define_insn "*atomic_compare_and_swapsi_3"
9791   [(set (match_operand:SI 0 "register_operand" "=r,r")
9792         (match_operand:SI 1 "memory_operand" "+Q,S"))
9793    (set (match_dup 1)
9794         (unspec_volatile:SI
9795           [(match_dup 1)
9796            (match_operand:SI 2 "register_operand" "0,0")
9797            (match_operand:SI 3 "register_operand" "r,r")]
9798           UNSPECV_CAS))
9799    (set (reg:CCZ1 CC_REGNUM)
9800         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9801   ""
9802   "@
9803    cs\t%0,%3,%S1
9804    csy\t%0,%3,%S1"
9805   [(set_attr "op_type" "RS,RSY")
9806    (set_attr "type"   "sem")])
9807
9808 ;
9809 ; Other atomic instruction patterns.
9810 ;
9811
9812 ; z196 load and add, xor, or and and instructions
9813
9814 (define_expand "atomic_fetch_<atomic><mode>"
9815   [(match_operand:GPR 0 "register_operand")             ;; val out
9816    (ATOMIC_Z196:GPR
9817      (match_operand:GPR 1 "memory_operand")             ;; memory
9818      (match_operand:GPR 2 "register_operand"))          ;; val in
9819    (match_operand:SI 3 "const_int_operand")]            ;; model
9820   "TARGET_Z196"
9821 {
9822   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9823     FAIL;
9824
9825   emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9826              (operands[0], operands[1], operands[2]));
9827   DONE;
9828 })
9829
9830 ; lan, lang, lao, laog, lax, laxg, laa, laag
9831 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9832   [(set (match_operand:GPR 0 "register_operand" "=d")
9833         (match_operand:GPR 1 "memory_operand" "+QS"))
9834    (set (match_dup 1)
9835         (unspec_volatile:GPR
9836          [(ATOMIC_Z196:GPR (match_dup 1)
9837                            (match_operand:GPR 2 "general_operand" "d"))]
9838          UNSPECV_ATOMIC_OP))
9839    (clobber (reg:CC CC_REGNUM))]
9840   "TARGET_Z196"
9841   "la<noxa><g>\t%0,%2,%1"
9842   [(set_attr "op_type" "RSY")
9843    (set_attr "type" "sem")])
9844
9845 ;; For SImode and larger, the optabs.c code will do just fine in
9846 ;; expanding a compare-and-swap loop.  For QI/HImode, we can do
9847 ;; better by expanding our own loop.
9848
9849 (define_expand "atomic_<atomic><mode>"
9850   [(ATOMIC:HQI
9851      (match_operand:HQI 0 "memory_operand")             ;; memory
9852      (match_operand:HQI 1 "general_operand"))           ;; val in
9853    (match_operand:SI 2 "const_int_operand")]            ;; model
9854   ""
9855 {
9856   s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9857                        operands[1], false);
9858   DONE;
9859 })
9860
9861 (define_expand "atomic_fetch_<atomic><mode>"
9862   [(match_operand:HQI 0 "register_operand")             ;; val out
9863    (ATOMIC:HQI
9864      (match_operand:HQI 1 "memory_operand")             ;; memory
9865      (match_operand:HQI 2 "general_operand"))           ;; val in
9866    (match_operand:SI 3 "const_int_operand")]            ;; model
9867   ""
9868 {
9869   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9870                       operands[2], false);
9871   DONE;
9872 })
9873
9874 (define_expand "atomic_<atomic>_fetch<mode>"
9875   [(match_operand:HQI 0 "register_operand")             ;; val out
9876    (ATOMIC:HQI
9877      (match_operand:HQI 1 "memory_operand")             ;; memory
9878      (match_operand:HQI 2 "general_operand"))           ;; val in
9879    (match_operand:SI 3 "const_int_operand")]            ;; model
9880   ""
9881 {
9882   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9883                       operands[2], true);
9884   DONE;
9885 })
9886
9887 (define_expand "atomic_exchange<mode>"
9888   [(match_operand:HQI 0 "register_operand")             ;; val out
9889    (match_operand:HQI 1 "memory_operand")               ;; memory
9890    (match_operand:HQI 2 "general_operand")              ;; val in
9891    (match_operand:SI 3 "const_int_operand")]            ;; model
9892   ""
9893 {
9894   s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9895                       operands[2], false);
9896   DONE;
9897 })
9898
9899 ;;
9900 ;;- Miscellaneous instructions.
9901 ;;
9902
9903 ;
9904 ; allocate stack instruction pattern(s).
9905 ;
9906
9907 (define_expand "allocate_stack"
9908   [(match_operand 0 "general_operand" "")
9909    (match_operand 1 "general_operand" "")]
9910  "TARGET_BACKCHAIN"
9911 {
9912   rtx temp = gen_reg_rtx (Pmode);
9913
9914   emit_move_insn (temp, s390_back_chain_rtx ());
9915   anti_adjust_stack (operands[1]);
9916   emit_move_insn (s390_back_chain_rtx (), temp);
9917
9918   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9919   DONE;
9920 })
9921
9922
9923 ;
9924 ; setjmp instruction pattern.
9925 ;
9926
9927 (define_expand "builtin_setjmp_receiver"
9928   [(match_operand 0 "" "")]
9929   "flag_pic"
9930 {
9931   emit_insn (s390_load_got ());
9932   emit_use (pic_offset_table_rtx);
9933   DONE;
9934 })
9935
9936 ;; These patterns say how to save and restore the stack pointer.  We need not
9937 ;; save the stack pointer at function level since we are careful to
9938 ;; preserve the backchain.  At block level, we have to restore the backchain
9939 ;; when we restore the stack pointer.
9940 ;;
9941 ;; For nonlocal gotos, we must save both the stack pointer and its
9942 ;; backchain and restore both.  Note that in the nonlocal case, the
9943 ;; save area is a memory location.
9944
9945 (define_expand "save_stack_function"
9946   [(match_operand 0 "general_operand" "")
9947    (match_operand 1 "general_operand" "")]
9948   ""
9949   "DONE;")
9950
9951 (define_expand "restore_stack_function"
9952   [(match_operand 0 "general_operand" "")
9953    (match_operand 1 "general_operand" "")]
9954   ""
9955   "DONE;")
9956
9957 (define_expand "restore_stack_block"
9958   [(match_operand 0 "register_operand" "")
9959    (match_operand 1 "register_operand" "")]
9960   "TARGET_BACKCHAIN"
9961 {
9962   rtx temp = gen_reg_rtx (Pmode);
9963
9964   emit_move_insn (temp, s390_back_chain_rtx ());
9965   emit_move_insn (operands[0], operands[1]);
9966   emit_move_insn (s390_back_chain_rtx (), temp);
9967
9968   DONE;
9969 })
9970
9971 (define_expand "save_stack_nonlocal"
9972   [(match_operand 0 "memory_operand" "")
9973    (match_operand 1 "register_operand" "")]
9974   ""
9975 {
9976   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9977
9978   /* Copy the backchain to the first word, sp to the second and the
9979      literal pool base to the third.  */
9980
9981   rtx save_bc = adjust_address (operands[0], Pmode, 0);
9982   rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9983   rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9984
9985   if (TARGET_BACKCHAIN)
9986     emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9987
9988   emit_move_insn (save_sp, operands[1]);
9989   emit_move_insn (save_bp, base);
9990
9991   DONE;
9992 })
9993
9994 (define_expand "restore_stack_nonlocal"
9995   [(match_operand 0 "register_operand" "")
9996    (match_operand 1 "memory_operand" "")]
9997   ""
9998 {
9999   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10000   rtx temp = NULL_RTX;
10001
10002   /* Restore the backchain from the first word, sp from the second and the
10003      literal pool base from the third.  */
10004
10005   rtx save_bc = adjust_address (operands[1], Pmode, 0);
10006   rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10007   rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10008
10009   if (TARGET_BACKCHAIN)
10010     temp = force_reg (Pmode, save_bc);
10011
10012   emit_move_insn (base, save_bp);
10013   emit_move_insn (operands[0], save_sp);
10014
10015   if (temp)
10016     emit_move_insn (s390_back_chain_rtx (), temp);
10017
10018   emit_use (base);
10019   DONE;
10020 })
10021
10022 (define_expand "exception_receiver"
10023   [(const_int 0)]
10024   ""
10025 {
10026   s390_set_has_landing_pad_p (true);
10027   DONE;
10028 })
10029
10030 ;
10031 ; nop instruction pattern(s).
10032 ;
10033
10034 (define_insn "nop"
10035   [(const_int 0)]
10036   ""
10037   "lr\t0,0"
10038   [(set_attr "op_type" "RR")
10039    (set_attr "z10prop"  "z10_fr_E1")])
10040
10041 (define_insn "nop1"
10042   [(const_int 1)]
10043   ""
10044   "lr\t1,1"
10045   [(set_attr "op_type" "RR")])
10046
10047 ;;- Undeletable nops (used for hotpatching)
10048
10049 (define_insn "nop_2_byte"
10050   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10051   ""
10052   "nopr\t%%r7"
10053   [(set_attr "op_type" "RR")])
10054
10055 (define_insn "nop_4_byte"
10056   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10057   ""
10058   "nop\t0"
10059   [(set_attr "op_type" "RX")])
10060
10061 (define_insn "nop_6_byte"
10062   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10063   "TARGET_CPU_ZARCH"
10064   "brcl\t0, 0"
10065   [(set_attr "op_type" "RIL")])
10066
10067
10068 ;
10069 ; Special literal pool access instruction pattern(s).
10070 ;
10071
10072 (define_insn "*pool_entry"
10073   [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10074                     UNSPECV_POOL_ENTRY)]
10075   ""
10076 {
10077   machine_mode mode = GET_MODE (PATTERN (insn));
10078   unsigned int align = GET_MODE_BITSIZE (mode);
10079   s390_output_pool_entry (operands[0], mode, align);
10080   return "";
10081 }
10082   [(set (attr "length")
10083         (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10084
10085 (define_insn "pool_align"
10086   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10087                     UNSPECV_POOL_ALIGN)]
10088   ""
10089   ".align\t%0"
10090   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10091
10092 (define_insn "pool_section_start"
10093   [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10094   ""
10095 {
10096   switch_to_section (targetm.asm_out.function_rodata_section
10097                  (current_function_decl));
10098   return "";
10099 }
10100   [(set_attr "length" "0")])
10101
10102 (define_insn "pool_section_end"
10103   [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10104   ""
10105 {
10106   switch_to_section (current_function_section ());
10107   return "";
10108 }
10109   [(set_attr "length" "0")])
10110
10111 (define_insn "main_base_31_small"
10112   [(set (match_operand 0 "register_operand" "=a")
10113         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10114   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10115   "basr\t%0,0"
10116   [(set_attr "op_type" "RR")
10117    (set_attr "type"    "la")
10118    (set_attr "z196prop" "z196_cracked")])
10119
10120 (define_insn "main_base_31_large"
10121   [(set (match_operand 0 "register_operand" "=a")
10122         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10123    (set (pc) (label_ref (match_operand 2 "" "")))]
10124   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10125   "bras\t%0,%2"
10126   [(set_attr "op_type" "RI")
10127    (set_attr "z196prop" "z196_cracked")])
10128
10129 (define_insn "main_base_64"
10130   [(set (match_operand 0 "register_operand" "=a")
10131         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10132   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10133   "larl\t%0,%1"
10134   [(set_attr "op_type" "RIL")
10135    (set_attr "type"    "larl")
10136    (set_attr "z10prop" "z10_fwd_A1")])
10137
10138 (define_insn "main_pool"
10139   [(set (match_operand 0 "register_operand" "=a")
10140         (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10141   "GET_MODE (operands[0]) == Pmode"
10142 {
10143   gcc_unreachable ();
10144 }
10145   [(set (attr "type")
10146         (if_then_else (match_test "TARGET_CPU_ZARCH")
10147                       (const_string "larl") (const_string "la")))])
10148
10149 (define_insn "reload_base_31"
10150   [(set (match_operand 0 "register_operand" "=a")
10151         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10152   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10153   "basr\t%0,0\;la\t%0,%1-.(%0)"
10154   [(set_attr "length" "6")
10155    (set_attr "type" "la")
10156    (set_attr "z196prop" "z196_cracked")])
10157
10158 (define_insn "reload_base_64"
10159   [(set (match_operand 0 "register_operand" "=a")
10160         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10161   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10162   "larl\t%0,%1"
10163   [(set_attr "op_type" "RIL")
10164    (set_attr "type"    "larl")
10165    (set_attr "z10prop" "z10_fwd_A1")])
10166
10167 (define_insn "pool"
10168   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10169   ""
10170 {
10171   gcc_unreachable ();
10172 }
10173   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10174
10175 ;;
10176 ;; Insns related to generating the function prologue and epilogue.
10177 ;;
10178
10179
10180 (define_expand "prologue"
10181   [(use (const_int 0))]
10182   ""
10183   "s390_emit_prologue (); DONE;")
10184
10185 (define_expand "epilogue"
10186   [(use (const_int 1))]
10187   ""
10188   "s390_emit_epilogue (false); DONE;")
10189
10190 (define_expand "sibcall_epilogue"
10191   [(use (const_int 0))]
10192   ""
10193   "s390_emit_epilogue (true); DONE;")
10194
10195 ;; A direct return instruction, without using an epilogue.
10196 (define_insn "<code>"
10197   [(ANY_RETURN)]
10198   "s390_can_use_<code>_insn ()"
10199   "br\t%%r14"
10200   [(set_attr "op_type" "RR")
10201    (set_attr "type"    "jsr")
10202    (set_attr "atype"   "agen")])
10203
10204 (define_insn "*return"
10205   [(return)
10206    (use (match_operand 0 "register_operand" "a"))]
10207   "GET_MODE (operands[0]) == Pmode"
10208   "br\t%0"
10209   [(set_attr "op_type" "RR")
10210    (set_attr "type"    "jsr")
10211    (set_attr "atype"   "agen")])
10212
10213
10214 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10215 ;; pointer. This is used for compatibility.
10216
10217 (define_expand "ptr_extend"
10218   [(set (match_operand:DI 0 "register_operand" "=r")
10219         (match_operand:SI 1 "register_operand" "r"))]
10220   "TARGET_64BIT"
10221 {
10222   emit_insn (gen_anddi3 (operands[0],
10223                          gen_lowpart (DImode, operands[1]),
10224                          GEN_INT (0x7fffffff)));
10225   DONE;
10226 })
10227
10228 ;; Instruction definition to expand eh_return macro to support
10229 ;; swapping in special linkage return addresses.
10230
10231 (define_expand "eh_return"
10232   [(use (match_operand 0 "register_operand" ""))]
10233   "TARGET_TPF"
10234 {
10235   s390_emit_tpf_eh_return (operands[0]);
10236   DONE;
10237 })
10238
10239 ;
10240 ; Stack Protector Patterns
10241 ;
10242
10243 (define_expand "stack_protect_set"
10244   [(set (match_operand 0 "memory_operand" "")
10245         (match_operand 1 "memory_operand" ""))]
10246   ""
10247 {
10248 #ifdef TARGET_THREAD_SSP_OFFSET
10249   operands[1]
10250     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10251                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10252 #endif
10253   if (TARGET_64BIT)
10254     emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10255   else
10256     emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10257
10258   DONE;
10259 })
10260
10261 (define_insn "stack_protect_set<mode>"
10262   [(set (match_operand:DSI 0 "memory_operand" "=Q")
10263         (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10264   ""
10265   "mvc\t%O0(%G0,%R0),%S1"
10266   [(set_attr "op_type" "SS")])
10267
10268 (define_expand "stack_protect_test"
10269   [(set (reg:CC CC_REGNUM)
10270         (compare (match_operand 0 "memory_operand" "")
10271                  (match_operand 1 "memory_operand" "")))
10272    (match_operand 2 "" "")]
10273   ""
10274 {
10275   rtx cc_reg, test;
10276 #ifdef TARGET_THREAD_SSP_OFFSET
10277   operands[1]
10278     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10279                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10280 #endif
10281   if (TARGET_64BIT)
10282     emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10283   else
10284     emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10285
10286   cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10287   test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10288   emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10289   DONE;
10290 })
10291
10292 (define_insn "stack_protect_test<mode>"
10293   [(set (reg:CCZ CC_REGNUM)
10294         (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10295                      (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10296   ""
10297   "clc\t%O0(%G0,%R0),%S1"
10298   [(set_attr "op_type" "SS")])
10299
10300 ; This is used in s390_emit_prologue in order to prevent insns
10301 ; adjusting the stack pointer to be moved over insns writing stack
10302 ; slots using a copy of the stack pointer in a different register.
10303 (define_insn "stack_tie"
10304   [(set (match_operand:BLK 0 "memory_operand" "+m")
10305         (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10306   ""
10307   ""
10308   [(set_attr "length" "0")])
10309
10310
10311 ;
10312 ; Data prefetch patterns
10313 ;
10314
10315 (define_insn "prefetch"
10316   [(prefetch (match_operand 0    "address_operand"   "ZQZRZSZT,X")
10317              (match_operand:SI 1 "const_int_operand" "       n,n")
10318              (match_operand:SI 2 "const_int_operand" "       n,n"))]
10319   "TARGET_Z10"
10320 {
10321   switch (which_alternative)
10322     {
10323       case 0:
10324         return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10325       case 1:
10326         if (larl_operand (operands[0], Pmode))
10327           return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10328       default:
10329
10330         /* This might be reached for symbolic operands with an odd
10331            addend.  We simply omit the prefetch for such rare cases.  */
10332
10333         return "";
10334      }
10335 }
10336   [(set_attr "type" "load,larl")
10337    (set_attr "op_type" "RXY,RIL")
10338    (set_attr "z10prop" "z10_super")
10339    (set_attr "z196prop" "z196_alone")])
10340
10341
10342 ;
10343 ; Byte swap instructions
10344 ;
10345
10346 ; FIXME: There is also mvcin but we cannot use it since src and target
10347 ; may overlap.
10348 (define_insn "bswap<mode>2"
10349   [(set (match_operand:GPR 0            "nonimmediate_operand" "=d, d,RT")
10350         (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))]
10351   "TARGET_CPU_ZARCH"
10352   "@
10353    lrv<g>r\t%0,%1
10354    lrv<g>\t%0,%1
10355    strv<g>\t%1,%0"
10356   [(set_attr "type" "*,load,store")
10357    (set_attr "op_type" "RRE,RXY,RXY")
10358    (set_attr "z10prop" "z10_super")])
10359
10360 (define_insn "bswaphi2"
10361   [(set (match_operand:HI 0           "nonimmediate_operand" "=d, d,RT")
10362         (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))]
10363   "TARGET_CPU_ZARCH"
10364   "@
10365    #
10366    lrvh\t%0,%1
10367    strvh\t%1,%0"
10368   [(set_attr "type" "*,load,store")
10369    (set_attr "op_type" "RRE,RXY,RXY")
10370    (set_attr "z10prop" "z10_super")])
10371
10372 (define_split
10373   [(set (match_operand:HI 0           "register_operand" "")
10374         (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10375   "TARGET_CPU_ZARCH"
10376   [(set (match_dup 2) (bswap:SI (match_dup 3)))
10377    (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10378 {
10379   operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10380   operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10381 })
10382
10383
10384 ;
10385 ; Population count instruction
10386 ;
10387
10388 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10389 ; portions and stores the result in the corresponding bytes in op0.
10390 (define_insn "*popcount<mode>"
10391   [(set (match_operand:INT 0 "register_operand" "=d")
10392         (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10393    (clobber (reg:CC CC_REGNUM))]
10394   "TARGET_Z196"
10395   "popcnt\t%0,%1"
10396   [(set_attr "op_type" "RRE")])
10397
10398 (define_expand "popcountdi2"
10399   [; popcnt op0, op1
10400    (parallel [(set (match_operand:DI 0 "register_operand" "")
10401                    (unspec:DI [(match_operand:DI 1 "register_operand")]
10402                               UNSPEC_POPCNT))
10403               (clobber (reg:CC CC_REGNUM))])
10404    ; sllg op2, op0, 32
10405    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10406    ; agr op0, op2
10407    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10408               (clobber (reg:CC CC_REGNUM))])
10409    ; sllg op2, op0, 16
10410    (set (match_dup 2)
10411         (ashift:DI (match_dup 0) (const_int 16)))
10412    ; agr op0, op2
10413    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10414               (clobber (reg:CC CC_REGNUM))])
10415    ; sllg op2, op0, 8
10416    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10417    ; agr op0, op2
10418    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10419               (clobber (reg:CC CC_REGNUM))])
10420    ; srlg op0, op0, 56
10421    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10422   "TARGET_Z196 && TARGET_64BIT"
10423   "operands[2] = gen_reg_rtx (DImode);")
10424
10425 (define_expand "popcountsi2"
10426   [; popcnt op0, op1
10427    (parallel [(set (match_operand:SI 0 "register_operand" "")
10428                    (unspec:SI [(match_operand:SI 1 "register_operand")]
10429                               UNSPEC_POPCNT))
10430               (clobber (reg:CC CC_REGNUM))])
10431    ; sllk op2, op0, 16
10432    (set (match_dup 2)
10433         (ashift:SI (match_dup 0) (const_int 16)))
10434    ; ar op0, op2
10435    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10436               (clobber (reg:CC CC_REGNUM))])
10437    ; sllk op2, op0, 8
10438    (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10439    ; ar op0, op2
10440    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10441               (clobber (reg:CC CC_REGNUM))])
10442    ; srl op0, op0, 24
10443    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10444   "TARGET_Z196"
10445   "operands[2] = gen_reg_rtx (SImode);")
10446
10447 (define_expand "popcounthi2"
10448   [; popcnt op0, op1
10449    (parallel [(set (match_operand:HI 0 "register_operand" "")
10450                    (unspec:HI [(match_operand:HI 1 "register_operand")]
10451                               UNSPEC_POPCNT))
10452               (clobber (reg:CC CC_REGNUM))])
10453    ; sllk op2, op0, 8
10454    (set (match_dup 2)
10455         (ashift:SI (match_dup 0) (const_int 8)))
10456    ; ar op0, op2
10457    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10458               (clobber (reg:CC CC_REGNUM))])
10459    ; srl op0, op0, 8
10460    (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10461   "TARGET_Z196"
10462   "operands[2] = gen_reg_rtx (SImode);")
10463
10464 (define_expand "popcountqi2"
10465   [; popcnt op0, op1
10466    (parallel [(set (match_operand:QI 0 "register_operand" "")
10467                    (unspec:QI [(match_operand:QI 1 "register_operand")]
10468                               UNSPEC_POPCNT))
10469               (clobber (reg:CC CC_REGNUM))])]
10470   "TARGET_Z196"
10471   "")
10472
10473 ;;
10474 ;;- Copy sign instructions
10475 ;;
10476
10477 (define_insn "copysign<mode>3"
10478   [(set (match_operand:FP 0 "register_operand" "=f")
10479       (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10480                   (match_operand:FP 2 "register_operand" "f")]
10481                   UNSPEC_COPYSIGN))]
10482   "TARGET_Z196"
10483   "cpsdr\t%0,%2,%1"
10484   [(set_attr "op_type"  "RRF")
10485    (set_attr "type"     "fsimp<mode>")])
10486
10487
10488 ;;
10489 ;;- Transactional execution instructions
10490 ;;
10491
10492 ; This splitter helps combine to make use of CC directly when
10493 ; comparing the integer result of a tbegin builtin with a constant.
10494 ; The unspec is already removed by canonicalize_comparison. So this
10495 ; splitters only job is to turn the PARALLEL into separate insns
10496 ; again.  Unfortunately this only works with the very first cc/int
10497 ; compare since combine is not able to deal with data flow across
10498 ; basic block boundaries.
10499
10500 ; It needs to be an insn pattern as well since combine does not apply
10501 ; the splitter directly.  Combine would only use it if it actually
10502 ; would reduce the number of instructions.
10503 (define_insn_and_split "*ccraw_to_int"
10504   [(set (pc)
10505         (if_then_else
10506          (match_operator 0 "s390_eqne_operator"
10507                          [(reg:CCRAW CC_REGNUM)
10508                           (match_operand 1 "const_int_operand" "")])
10509          (label_ref (match_operand 2 "" ""))
10510          (pc)))
10511    (set (match_operand:SI 3 "register_operand" "=d")
10512         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10513   ""
10514   "#"
10515   ""
10516   [(set (match_dup 3)
10517         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10518    (set (pc)
10519         (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10520                       (label_ref (match_dup 2))
10521                       (pc)))]
10522   "")
10523
10524 ; Non-constrained transaction begin
10525
10526 (define_expand "tbegin"
10527   [(match_operand:SI 0 "register_operand" "")
10528    (match_operand:BLK 1 "memory_operand" "")]
10529   "TARGET_HTM"
10530 {
10531   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10532   DONE;
10533 })
10534
10535 (define_expand "tbegin_nofloat"
10536   [(match_operand:SI 0 "register_operand" "")
10537    (match_operand:BLK 1 "memory_operand" "")]
10538   "TARGET_HTM"
10539 {
10540   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10541   DONE;
10542 })
10543
10544 (define_expand "tbegin_retry"
10545   [(match_operand:SI 0 "register_operand" "")
10546    (match_operand:BLK 1 "memory_operand" "")
10547    (match_operand:SI 2 "general_operand" "")]
10548   "TARGET_HTM"
10549 {
10550   s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10551   DONE;
10552 })
10553
10554 (define_expand "tbegin_retry_nofloat"
10555   [(match_operand:SI 0 "register_operand" "")
10556    (match_operand:BLK 1 "memory_operand" "")
10557    (match_operand:SI 2 "general_operand" "")]
10558   "TARGET_HTM"
10559 {
10560   s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10561   DONE;
10562 })
10563
10564 ; Clobber VRs since they don't get restored
10565 (define_insn "tbegin_1_z13"
10566   [(set (reg:CCRAW CC_REGNUM)
10567         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10568                                UNSPECV_TBEGIN))
10569    (set (match_operand:BLK 1 "memory_operand" "=Q")
10570         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10571    (clobber (reg:TI 16)) (clobber (reg:TI 38))
10572    (clobber (reg:TI 17)) (clobber (reg:TI 39))
10573    (clobber (reg:TI 18)) (clobber (reg:TI 40))
10574    (clobber (reg:TI 19)) (clobber (reg:TI 41))
10575    (clobber (reg:TI 20)) (clobber (reg:TI 42))
10576    (clobber (reg:TI 21)) (clobber (reg:TI 43))
10577    (clobber (reg:TI 22)) (clobber (reg:TI 44))
10578    (clobber (reg:TI 23)) (clobber (reg:TI 45))
10579    (clobber (reg:TI 24)) (clobber (reg:TI 46))
10580    (clobber (reg:TI 25)) (clobber (reg:TI 47))
10581    (clobber (reg:TI 26)) (clobber (reg:TI 48))
10582    (clobber (reg:TI 27)) (clobber (reg:TI 49))
10583    (clobber (reg:TI 28)) (clobber (reg:TI 50))
10584    (clobber (reg:TI 29)) (clobber (reg:TI 51))
10585    (clobber (reg:TI 30)) (clobber (reg:TI 52))
10586    (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10587 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10588 ; not supposed to be used for immediates (see genpreds.c).
10589   "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10590   "tbegin\t%1,%x0"
10591   [(set_attr "op_type" "SIL")])
10592
10593 (define_insn "tbegin_1"
10594   [(set (reg:CCRAW CC_REGNUM)
10595         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10596                                UNSPECV_TBEGIN))
10597    (set (match_operand:BLK 1 "memory_operand" "=Q")
10598         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10599    (clobber (reg:DF 16))
10600    (clobber (reg:DF 17))
10601    (clobber (reg:DF 18))
10602    (clobber (reg:DF 19))
10603    (clobber (reg:DF 20))
10604    (clobber (reg:DF 21))
10605    (clobber (reg:DF 22))
10606    (clobber (reg:DF 23))
10607    (clobber (reg:DF 24))
10608    (clobber (reg:DF 25))
10609    (clobber (reg:DF 26))
10610    (clobber (reg:DF 27))
10611    (clobber (reg:DF 28))
10612    (clobber (reg:DF 29))
10613    (clobber (reg:DF 30))
10614    (clobber (reg:DF 31))]
10615 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10616 ; not supposed to be used for immediates (see genpreds.c).
10617   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10618   "tbegin\t%1,%x0"
10619   [(set_attr "op_type" "SIL")])
10620
10621 ; Same as above but without the FPR clobbers
10622 (define_insn "tbegin_nofloat_1"
10623   [(set (reg:CCRAW CC_REGNUM)
10624         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10625                                UNSPECV_TBEGIN))
10626    (set (match_operand:BLK 1 "memory_operand" "=Q")
10627         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10628   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10629   "tbegin\t%1,%x0"
10630   [(set_attr "op_type" "SIL")])
10631
10632
10633 ; Constrained transaction begin
10634
10635 (define_expand "tbeginc"
10636   [(set (reg:CCRAW CC_REGNUM)
10637         (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10638                                UNSPECV_TBEGINC))]
10639   "TARGET_HTM"
10640   "")
10641
10642 (define_insn "*tbeginc_1"
10643   [(set (reg:CCRAW CC_REGNUM)
10644         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10645                                UNSPECV_TBEGINC))]
10646   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10647   "tbeginc\t0,%x0"
10648   [(set_attr "op_type" "SIL")])
10649
10650 ; Transaction end
10651
10652 (define_expand "tend"
10653   [(set (reg:CCRAW CC_REGNUM)
10654         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10655    (set (match_operand:SI 0 "register_operand" "")
10656         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10657   "TARGET_HTM"
10658   "")
10659
10660 (define_insn "*tend_1"
10661   [(set (reg:CCRAW CC_REGNUM)
10662         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10663   "TARGET_HTM"
10664   "tend"
10665   [(set_attr "op_type" "S")])
10666
10667 ; Transaction abort
10668
10669 (define_expand "tabort"
10670   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
10671                     UNSPECV_TABORT)]
10672   "TARGET_HTM && operands != NULL"
10673 {
10674   if (CONST_INT_P (operands[0])
10675       && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10676     {
10677       error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10678              ".  Values in range 0 through 255 are reserved.",
10679              INTVAL (operands[0]));
10680       FAIL;
10681     }
10682 })
10683
10684 (define_insn "*tabort_1"
10685   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
10686                     UNSPECV_TABORT)]
10687   "TARGET_HTM && operands != NULL"
10688   "tabort\t%Y0"
10689   [(set_attr "op_type" "S")])
10690
10691 (define_insn "*tabort_1_plus"
10692   [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand"  "a")
10693                               (match_operand:SI 1 "const_int_operand" "J"))]
10694                     UNSPECV_TABORT)]
10695   "TARGET_HTM && operands != NULL
10696    && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
10697   "tabort\t%1(%0)"
10698   [(set_attr "op_type" "S")])
10699
10700 ; Transaction extract nesting depth
10701
10702 (define_insn "etnd"
10703   [(set (match_operand:SI 0 "register_operand" "=d")
10704         (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10705   "TARGET_HTM"
10706   "etnd\t%0"
10707   [(set_attr "op_type" "RRE")])
10708
10709 ; Non-transactional store
10710
10711 (define_insn "ntstg"
10712   [(set (match_operand:DI 0 "memory_operand" "=RT")
10713         (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10714                             UNSPECV_NTSTG))]
10715   "TARGET_HTM"
10716   "ntstg\t%1,%0"
10717   [(set_attr "op_type" "RXY")])
10718
10719 ; Transaction perform processor assist
10720
10721 (define_expand "tx_assist"
10722   [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10723                      (reg:SI GPR0_REGNUM)
10724                      (const_int 1)]
10725                     UNSPECV_PPA)]
10726   "TARGET_HTM"
10727   "")
10728
10729 (define_insn "*ppa"
10730   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10731                      (match_operand:SI 1 "register_operand" "d")
10732                      (match_operand 2 "const_int_operand" "I")]
10733                     UNSPECV_PPA)]
10734   "TARGET_HTM && INTVAL (operands[2]) < 16"
10735   "ppa\t%0,%1,%2"
10736   [(set_attr "op_type" "RRF")])
10737
10738
10739 ; Set and get floating point control register
10740
10741 (define_insn "sfpc"
10742   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10743                     UNSPECV_SFPC)]
10744   "TARGET_HARD_FLOAT"
10745   "sfpc\t%0")
10746
10747 (define_insn "efpc"
10748   [(set (match_operand:SI 0 "register_operand" "=d")
10749         (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10750   "TARGET_HARD_FLOAT"
10751   "efpc\t%0")
10752
10753
10754 ; Load count to block boundary
10755
10756 (define_insn "lcbb"
10757   [(set (match_operand:SI             0 "register_operand"  "=d")
10758         (unspec:SI [(match_operand    1 "address_operand" "ZQZR")
10759                     (match_operand:SI 2 "immediate_operand"  "C")] UNSPEC_LCBB))
10760    (clobber (reg:CC CC_REGNUM))]
10761   "TARGET_Z13"
10762   "lcbb\t%0,%a1,%b2"
10763   [(set_attr "op_type" "VRX")])
10764
10765 ; Handle -fsplit-stack.
10766
10767 (define_expand "split_stack_prologue"
10768   [(const_int 0)]
10769   ""
10770 {
10771   s390_expand_split_stack_prologue ();
10772   DONE;
10773 })
10774
10775 ;; If there are operand 0 bytes available on the stack, jump to
10776 ;; operand 1.
10777
10778 (define_expand "split_stack_space_check"
10779   [(set (pc) (if_then_else
10780               (ltu (minus (reg 15)
10781                           (match_operand 0 "register_operand"))
10782                    (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
10783               (label_ref (match_operand 1))
10784               (pc)))]
10785   ""
10786 {
10787   /* Offset from thread pointer to __private_ss.  */
10788   int psso = TARGET_64BIT ? 0x38 : 0x20;
10789   rtx tp = s390_get_thread_pointer ();
10790   rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
10791   rtx reg = gen_reg_rtx (Pmode);
10792   rtx cc;
10793   if (TARGET_64BIT)
10794     emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
10795   else
10796     emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
10797   cc = s390_emit_compare (GT, reg, guard);
10798   s390_emit_jump (operands[1], cc);
10799
10800   DONE;
10801 })
10802
10803 ;; __morestack parameter block for split stack prologue.  Parameters are:
10804 ;; parameter block label, label to be called by __morestack, frame size,
10805 ;; stack parameter size.
10806
10807 (define_insn "split_stack_data"
10808   [(unspec_volatile [(match_operand 0 "" "X")
10809                      (match_operand 1 "" "X")
10810                      (match_operand 2 "const_int_operand" "X")
10811                      (match_operand 3 "const_int_operand" "X")]
10812                     UNSPECV_SPLIT_STACK_DATA)]
10813   "TARGET_CPU_ZARCH"
10814 {
10815   switch_to_section (targetm.asm_out.function_rodata_section
10816                  (current_function_decl));
10817
10818   if (TARGET_64BIT)
10819     output_asm_insn (".align\t8", operands);
10820   else
10821     output_asm_insn (".align\t4", operands);
10822   (*targetm.asm_out.internal_label) (asm_out_file, "L",
10823                                      CODE_LABEL_NUMBER (operands[0]));
10824   if (TARGET_64BIT)
10825     {
10826       output_asm_insn (".quad\t%2", operands);
10827       output_asm_insn (".quad\t%3", operands);
10828       output_asm_insn (".quad\t%1-%0", operands);
10829     }
10830   else
10831     {
10832       output_asm_insn (".long\t%2", operands);
10833       output_asm_insn (".long\t%3", operands);
10834       output_asm_insn (".long\t%1-%0", operands);
10835     }
10836
10837   switch_to_section (current_function_section ());
10838   return "";
10839 }
10840   [(set_attr "length" "0")])
10841
10842
10843 ;; A jg with minimal fuss for use in split stack prologue.
10844
10845 (define_expand "split_stack_call"
10846   [(match_operand 0 "bras_sym_operand" "X")
10847    (match_operand 1 "" "")]
10848   "TARGET_CPU_ZARCH"
10849 {
10850   if (TARGET_64BIT)
10851     emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
10852   else
10853     emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
10854   DONE;
10855 })
10856
10857 (define_insn "split_stack_call_<mode>"
10858   [(set (pc) (label_ref (match_operand 1 "" "")))
10859    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
10860                                     (reg:P 1)]
10861                                    UNSPECV_SPLIT_STACK_CALL))]
10862   "TARGET_CPU_ZARCH"
10863   "jg\t%0"
10864   [(set_attr "op_type" "RIL")
10865    (set_attr "type"  "branch")])
10866
10867 ;; Also a conditional one.
10868
10869 (define_expand "split_stack_cond_call"
10870   [(match_operand 0 "bras_sym_operand" "X")
10871    (match_operand 1 "" "")
10872    (match_operand 2 "" "")]
10873   "TARGET_CPU_ZARCH"
10874 {
10875   if (TARGET_64BIT)
10876     emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
10877   else
10878     emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
10879   DONE;
10880 })
10881
10882 (define_insn "split_stack_cond_call_<mode>"
10883   [(set (pc)
10884         (if_then_else
10885           (match_operand 1 "" "")
10886           (label_ref (match_operand 2 "" ""))
10887           (pc)))
10888    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
10889                                     (reg:P 1)]
10890                                    UNSPECV_SPLIT_STACK_CALL))]
10891   "TARGET_CPU_ZARCH"
10892   "jg%C1\t%0"
10893   [(set_attr "op_type" "RIL")
10894    (set_attr "type"  "branch")])