1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
65 ; GOT/PLT and lt-relative accesses
66 (UNSPEC_LTREL_OFFSET 100)
67 (UNSPEC_LTREL_BASE 101)
75 (UNSPEC_RELOAD_BASE 210)
76 (UNSPEC_MAIN_BASE 211)
81 ; TLS relocation specifiers
86 (UNSPEC_GOTNTPOFF 504)
87 (UNSPEC_INDNTPOFF 505)
90 (UNSPEC_TLSLDM_NTPOFF 511)
97 ; Stack Smashing Protector
101 ; Copy sign instructions
102 (UNSPEC_COPYSIGN 800)
106 ;; UNSPEC_VOLATILE usage
114 (UNSPECV_TPF_PROLOGUE 20)
115 (UNSPECV_TPF_EPILOGUE 21)
119 (UNSPECV_POOL_SECTION 201)
120 (UNSPECV_POOL_ALIGN 202)
121 (UNSPECV_POOL_ENTRY 203)
122 (UNSPECV_MAIN_POOL 300)
138 ; Sibling call register.
140 ; Literal pool base register.
142 ; Return address register.
144 ; Condition code register.
146 ; Thread local storage pointer register.
151 ;; Instruction operand type as used in the Principles of Operation.
152 ;; Used to determine defaults for length and other attribute values.
154 (define_attr "op_type"
155 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF"
158 ;; Instruction type attribute used for scheduling.
160 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
161 cs,vs,store,sem,idiv,
162 imulhi,imulsi,imuldi,
163 branch,jsr,fsimptf,fsimpdf,fsimpsf,
164 floadtf,floaddf,floadsf,fstoredf,fstoresf,
165 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
166 ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
167 ftrunctf,ftruncdf,other"
168 (cond [(eq_attr "op_type" "NN") (const_string "other")
169 (eq_attr "op_type" "SS") (const_string "cs")]
170 (const_string "integer")))
172 ;; Another attribute used for scheduling purposes:
173 ;; agen: Instruction uses the address generation unit
174 ;; reg: Instruction does not use the agen unit
176 (define_attr "atype" "agen,reg"
177 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
179 (const_string "agen")))
183 (define_attr "length" ""
184 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
185 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
189 ;; Processor type. This attribute must exactly match the processor_type
190 ;; enumeration in s390.h. The current machine description does not
191 ;; distinguish between g5 and g6, but there are differences between the two
192 ;; CPUs could in theory be modeled.
194 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
195 (const (symbol_ref "s390_tune")))
197 ;; Pipeline description for z900. For lack of anything better,
198 ;; this description is also used for the g5 and g6.
201 ;; Pipeline description for z990, z9-109 and z9-ec.
205 (include "predicates.md")
207 ;; Constraint definitions
208 (include "constraints.md")
215 ;; This mode macro allows floating point patterns to be generated from the
217 (define_mode_macro BFP [TF DF SF])
218 (define_mode_macro DSF [DF SF])
220 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
221 ;; from the same template.
222 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
224 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
225 ;; from the same template.
226 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
227 (define_mode_macro DSI [DI SI])
229 ;; This mode macro allows :P to be used for patterns that operate on
230 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
231 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
232 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
234 ;; This mode macro allows the QI and HI patterns to be defined from
235 ;; the same template.
236 (define_mode_macro HQI [HI QI])
238 ;; This mode macro allows the integer patterns to be defined from the
240 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
242 ;; This macro allows to unify all 'bCOND' expander patterns.
243 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
244 ordered uneq unlt ungt unle unge ltgt])
246 ;; This macro allows to unify all 'sCOND' patterns.
247 (define_code_macro SCOND [ltu gtu leu geu])
249 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
250 ;; the same template.
251 (define_code_macro SHIFT [ashift lshiftrt])
253 ;; These macros allow to combine most atomic operations.
254 (define_code_macro ATOMIC [and ior xor plus minus mult])
255 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
256 (plus "add") (minus "sub") (mult "nand")])
259 ;; In BFP templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode,
260 ;; "ltdbr" in DFmode, and "ltebr" in SFmode.
261 (define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
263 ;; In BFP templates, a string like "m<dee>br" will expand to "mxbr" in TFmode,
264 ;; "mdbr" in DFmode, and "meebr" in SFmode.
265 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
267 ;; In BFP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
268 ;; Likewise for "<RXe>".
269 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
270 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
272 ;; In BFP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
273 ;; This is used to disable the memory alternative in TFmode patterns.
274 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
276 ;; This attribute is used in the operand constraint list
277 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
278 ;; TFmode values are represented by a fp register pair. Since the
279 ;; sign bit instructions only handle single source and target fp registers
280 ;; these instructions can only be used for TFmode values if the source and
281 ;; target operand uses the same fp register.
282 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
284 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
285 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
286 ;; version only operates on one register.
287 (define_mode_attr d0 [(DI "d") (SI "0")])
289 ;; In combination with d0 this allows to combine instructions of which the 31bit
290 ;; version only operates on one register. The DImode version needs an additional
291 ;; register for the assembler output.
292 (define_mode_attr 1 [(DI "%1,") (SI "")])
294 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
295 ;; 'ashift' and "srdl" in 'lshiftrt'.
296 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
298 ;; In SHIFT templates, this attribute holds the correct standard name for the
299 ;; pattern itself and the corresponding function calls.
300 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
302 ;; This attribute handles differences in the instruction 'type' and will result
303 ;; in "RRE" for DImode and "RR" for SImode.
304 (define_mode_attr E [(DI "E") (SI "")])
306 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
307 ;; to result in "RXY" for DImode and "RX" for SImode.
308 (define_mode_attr Y [(DI "Y") (SI "")])
310 ;; This attribute handles differences in the instruction 'type' and will result
311 ;; in "RSE" for TImode and "RS" for DImode.
312 (define_mode_attr TE [(TI "E") (DI "")])
314 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
315 ;; and "lcr" in SImode.
316 (define_mode_attr g [(DI "g") (SI "")])
318 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
319 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
320 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
321 ;; variant for long displacements.
322 (define_mode_attr y [(DI "g") (SI "y")])
324 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
325 ;; and "cds" in DImode.
326 (define_mode_attr tg [(TI "g") (DI "")])
328 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
329 ;; and "cfdbr" in SImode.
330 (define_mode_attr gf [(DI "g") (SI "f")])
332 ;; ICM mask required to load MODE value into the lowest subreg
333 ;; of a SImode register.
334 (define_mode_attr icm_lo [(HI "3") (QI "1")])
336 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
337 ;; HImode and "llgc" in QImode.
338 (define_mode_attr hc [(HI "h") (QI "c")])
340 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
342 (define_mode_attr DBL [(DI "TI") (SI "DI")])
344 ;; Maximum unsigned integer that fits in MODE.
345 (define_mode_attr max_uint [(HI "65535") (QI "255")])
349 ;;- Compare instructions.
352 (define_expand "cmp<mode>"
353 [(set (reg:CC CC_REGNUM)
354 (compare:CC (match_operand:GPR 0 "register_operand" "")
355 (match_operand:GPR 1 "general_operand" "")))]
358 s390_compare_op0 = operands[0];
359 s390_compare_op1 = operands[1];
363 (define_expand "cmp<mode>"
364 [(set (reg:CC CC_REGNUM)
365 (compare:CC (match_operand:BFP 0 "register_operand" "")
366 (match_operand:BFP 1 "general_operand" "")))]
369 s390_compare_op0 = operands[0];
370 s390_compare_op1 = operands[1];
375 ; Test-under-Mask instructions
377 (define_insn "*tmqi_mem"
378 [(set (reg CC_REGNUM)
379 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
380 (match_operand:QI 1 "immediate_operand" "n,n"))
381 (match_operand:QI 2 "immediate_operand" "n,n")))]
382 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
386 [(set_attr "op_type" "SI,SIY")])
388 (define_insn "*tmdi_reg"
389 [(set (reg CC_REGNUM)
390 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
391 (match_operand:DI 1 "immediate_operand"
392 "N0HD0,N1HD0,N2HD0,N3HD0"))
393 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
395 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
396 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
402 [(set_attr "op_type" "RI")])
404 (define_insn "*tmsi_reg"
405 [(set (reg CC_REGNUM)
406 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
407 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
408 (match_operand:SI 2 "immediate_operand" "n,n")))]
409 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
410 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
414 [(set_attr "op_type" "RI")])
416 (define_insn "*tm<mode>_full"
417 [(set (reg CC_REGNUM)
418 (compare (match_operand:HQI 0 "register_operand" "d")
419 (match_operand:HQI 1 "immediate_operand" "n")))]
420 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
422 [(set_attr "op_type" "RI")])
426 ; Load-and-Test instructions
429 ; tst(di|si) instruction pattern(s).
431 (define_insn "*tstdi_sign"
432 [(set (reg CC_REGNUM)
433 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
434 (const_int 32)) (const_int 32))
435 (match_operand:DI 1 "const0_operand" "")))
436 (set (match_operand:DI 2 "register_operand" "=d")
437 (sign_extend:DI (match_dup 0)))]
438 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
440 [(set_attr "op_type" "RRE")])
443 (define_insn "*tst<mode>_extimm"
444 [(set (reg CC_REGNUM)
445 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
446 (match_operand:GPR 1 "const0_operand" "")))
447 (set (match_operand:GPR 2 "register_operand" "=d,d")
449 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
453 [(set_attr "op_type" "RR<E>,RXY")])
456 (define_insn "*tst<mode>_cconly_extimm"
457 [(set (reg CC_REGNUM)
458 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
459 (match_operand:GPR 1 "const0_operand" "")))
460 (clobber (match_scratch:GPR 2 "=X,d"))]
461 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
465 [(set_attr "op_type" "RR<E>,RXY")])
467 (define_insn "*tstdi"
468 [(set (reg CC_REGNUM)
469 (compare (match_operand:DI 0 "register_operand" "d")
470 (match_operand:DI 1 "const0_operand" "")))
471 (set (match_operand:DI 2 "register_operand" "=d")
473 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
475 [(set_attr "op_type" "RRE")])
477 (define_insn "*tstsi"
478 [(set (reg CC_REGNUM)
479 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
480 (match_operand:SI 1 "const0_operand" "")))
481 (set (match_operand:SI 2 "register_operand" "=d,d,d")
483 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
488 [(set_attr "op_type" "RR,RS,RSY")])
490 (define_insn "*tstsi_cconly"
491 [(set (reg CC_REGNUM)
492 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
493 (match_operand:SI 1 "const0_operand" "")))
494 (clobber (match_scratch:SI 2 "=X,d,d"))]
495 "s390_match_ccmode(insn, CCSmode)"
500 [(set_attr "op_type" "RR,RS,RSY")])
502 (define_insn "*tstdi_cconly_31"
503 [(set (reg CC_REGNUM)
504 (compare (match_operand:DI 0 "register_operand" "d")
505 (match_operand:DI 1 "const0_operand" "")))]
506 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
508 [(set_attr "op_type" "RS")
509 (set_attr "atype" "reg")])
512 (define_insn "*tst<mode>_cconly2"
513 [(set (reg CC_REGNUM)
514 (compare (match_operand:GPR 0 "register_operand" "d")
515 (match_operand:GPR 1 "const0_operand" "")))]
516 "s390_match_ccmode(insn, CCSmode)"
518 [(set_attr "op_type" "RR<E>")])
520 ; tst(hi|qi) instruction pattern(s).
522 (define_insn "*tst<mode>CCT"
523 [(set (reg CC_REGNUM)
524 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
525 (match_operand:HQI 1 "const0_operand" "")))
526 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
528 "s390_match_ccmode(insn, CCTmode)"
531 icmy\t%2,<icm_lo>,%S0
533 [(set_attr "op_type" "RS,RSY,RI")])
535 (define_insn "*tsthiCCT_cconly"
536 [(set (reg CC_REGNUM)
537 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
538 (match_operand:HI 1 "const0_operand" "")))
539 (clobber (match_scratch:HI 2 "=d,d,X"))]
540 "s390_match_ccmode(insn, CCTmode)"
545 [(set_attr "op_type" "RS,RSY,RI")])
547 (define_insn "*tstqiCCT_cconly"
548 [(set (reg CC_REGNUM)
549 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
550 (match_operand:QI 1 "const0_operand" "")))]
551 "s390_match_ccmode(insn, CCTmode)"
556 [(set_attr "op_type" "SI,SIY,RI")])
558 (define_insn "*tst<mode>"
559 [(set (reg CC_REGNUM)
560 (compare (match_operand:HQI 0 "s_operand" "Q,S")
561 (match_operand:HQI 1 "const0_operand" "")))
562 (set (match_operand:HQI 2 "register_operand" "=d,d")
564 "s390_match_ccmode(insn, CCSmode)"
567 icmy\t%2,<icm_lo>,%S0"
568 [(set_attr "op_type" "RS,RSY")])
570 (define_insn "*tst<mode>_cconly"
571 [(set (reg CC_REGNUM)
572 (compare (match_operand:HQI 0 "s_operand" "Q,S")
573 (match_operand:HQI 1 "const0_operand" "")))
574 (clobber (match_scratch:HQI 2 "=d,d"))]
575 "s390_match_ccmode(insn, CCSmode)"
578 icmy\t%2,<icm_lo>,%S0"
579 [(set_attr "op_type" "RS,RSY")])
582 ; Compare (equality) instructions
584 (define_insn "*cmpdi_cct"
585 [(set (reg CC_REGNUM)
586 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
587 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
588 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
595 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
597 (define_insn "*cmpsi_cct"
598 [(set (reg CC_REGNUM)
599 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
600 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
601 "s390_match_ccmode (insn, CCTmode)"
609 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
612 ; Compare (signed) instructions
614 (define_insn "*cmpdi_ccs_sign"
615 [(set (reg CC_REGNUM)
616 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
617 (match_operand:DI 0 "register_operand" "d,d")))]
618 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
622 [(set_attr "op_type" "RRE,RXY")])
624 (define_insn "*cmpsi_ccs_sign"
625 [(set (reg CC_REGNUM)
626 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
627 (match_operand:SI 0 "register_operand" "d,d")))]
628 "s390_match_ccmode(insn, CCSRmode)"
632 [(set_attr "op_type" "RX,RXY")])
634 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
635 (define_insn "*cmp<mode>_ccs"
636 [(set (reg CC_REGNUM)
637 (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
638 (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
639 "s390_match_ccmode(insn, CCSmode)"
646 [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
649 ; Compare (unsigned) instructions
651 (define_insn "*cmpdi_ccu_zero"
652 [(set (reg CC_REGNUM)
653 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
654 (match_operand:DI 0 "register_operand" "d,d")))]
655 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
659 [(set_attr "op_type" "RRE,RXY")])
661 (define_insn "*cmpdi_ccu"
662 [(set (reg CC_REGNUM)
663 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
664 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
665 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
672 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
674 (define_insn "*cmpsi_ccu"
675 [(set (reg CC_REGNUM)
676 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
677 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
678 "s390_match_ccmode (insn, CCUmode)"
686 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
688 (define_insn "*cmphi_ccu"
689 [(set (reg CC_REGNUM)
690 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
691 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
692 "s390_match_ccmode (insn, CCUmode)
693 && !register_operand (operands[1], HImode)"
699 [(set_attr "op_type" "RS,RSY,SS,SS")])
701 (define_insn "*cmpqi_ccu"
702 [(set (reg CC_REGNUM)
703 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
704 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
705 "s390_match_ccmode (insn, CCUmode)
706 && !register_operand (operands[1], QImode)"
714 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
717 ; Block compare (CLC) instruction patterns.
720 [(set (reg CC_REGNUM)
721 (compare (match_operand:BLK 0 "memory_operand" "Q")
722 (match_operand:BLK 1 "memory_operand" "Q")))
723 (use (match_operand 2 "const_int_operand" "n"))]
724 "s390_match_ccmode (insn, CCUmode)
725 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
726 "clc\t%O0(%2,%R0),%S1"
727 [(set_attr "op_type" "SS")])
730 [(set (reg CC_REGNUM)
731 (compare (match_operand 0 "memory_operand" "")
732 (match_operand 1 "memory_operand" "")))]
734 && s390_match_ccmode (insn, CCUmode)
735 && GET_MODE (operands[0]) == GET_MODE (operands[1])
736 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
738 [(set (match_dup 0) (match_dup 1))
739 (use (match_dup 2))])]
741 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
742 operands[0] = adjust_address (operands[0], BLKmode, 0);
743 operands[1] = adjust_address (operands[1], BLKmode, 0);
745 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
746 operands[0], operands[1]);
747 operands[0] = SET_DEST (PATTERN (curr_insn));
751 ; (DF|SF) instructions
753 ; ltxbr, ltdbr, ltebr
754 (define_insn "*cmp<mode>_ccs_0"
755 [(set (reg CC_REGNUM)
756 (compare (match_operand:BFP 0 "register_operand" "f")
757 (match_operand:BFP 1 "const0_operand" "")))]
758 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
760 [(set_attr "op_type" "RRE")
761 (set_attr "type" "fsimp<mode>")])
764 (define_insn "*cmp<mode>_ccs_0_ibm"
765 [(set (reg CC_REGNUM)
766 (compare (match_operand:BFP 0 "register_operand" "f")
767 (match_operand:BFP 1 "const0_operand" "")))]
768 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
770 [(set_attr "op_type" "<RRe>")
771 (set_attr "type" "fsimp<mode>")])
773 ; cxbr, cdbr, cebr, cxb, cdb, ceb
774 (define_insn "*cmp<mode>_ccs"
775 [(set (reg CC_REGNUM)
776 (compare (match_operand:BFP 0 "register_operand" "f,f")
777 (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
778 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
782 [(set_attr "op_type" "RRE,RXE")
783 (set_attr "type" "fsimp<mode>")])
785 ; cxr, cdr, cer, cx, cd, ce
786 (define_insn "*cmp<mode>_ccs_ibm"
787 [(set (reg CC_REGNUM)
788 (compare (match_operand:BFP 0 "register_operand" "f,f")
789 (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
790 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
794 [(set_attr "op_type" "<RRe>,<RXe>")
795 (set_attr "type" "fsimp<mode>")])
799 ;;- Move instructions.
803 ; movti instruction pattern(s).
807 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
808 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
816 [(set_attr "op_type" "RSY,RSY,*,*,SS")
817 (set_attr "type" "lm,stm,*,*,*")])
820 [(set (match_operand:TI 0 "nonimmediate_operand" "")
821 (match_operand:TI 1 "general_operand" ""))]
822 "TARGET_64BIT && reload_completed
823 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
824 [(set (match_dup 2) (match_dup 4))
825 (set (match_dup 3) (match_dup 5))]
827 operands[2] = operand_subword (operands[0], 0, 0, TImode);
828 operands[3] = operand_subword (operands[0], 1, 0, TImode);
829 operands[4] = operand_subword (operands[1], 0, 0, TImode);
830 operands[5] = operand_subword (operands[1], 1, 0, TImode);
834 [(set (match_operand:TI 0 "nonimmediate_operand" "")
835 (match_operand:TI 1 "general_operand" ""))]
836 "TARGET_64BIT && reload_completed
837 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
838 [(set (match_dup 2) (match_dup 4))
839 (set (match_dup 3) (match_dup 5))]
841 operands[2] = operand_subword (operands[0], 1, 0, TImode);
842 operands[3] = operand_subword (operands[0], 0, 0, TImode);
843 operands[4] = operand_subword (operands[1], 1, 0, TImode);
844 operands[5] = operand_subword (operands[1], 0, 0, TImode);
848 [(set (match_operand:TI 0 "register_operand" "")
849 (match_operand:TI 1 "memory_operand" ""))]
850 "TARGET_64BIT && reload_completed
851 && !s_operand (operands[1], VOIDmode)"
852 [(set (match_dup 0) (match_dup 1))]
854 rtx addr = operand_subword (operands[0], 1, 0, TImode);
855 s390_load_address (addr, XEXP (operands[1], 0));
856 operands[1] = replace_equiv_address (operands[1], addr);
859 (define_expand "reload_outti"
860 [(parallel [(match_operand:TI 0 "" "")
861 (match_operand:TI 1 "register_operand" "d")
862 (match_operand:DI 2 "register_operand" "=&a")])]
865 gcc_assert (MEM_P (operands[0]));
866 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
867 operands[0] = replace_equiv_address (operands[0], operands[2]);
868 emit_move_insn (operands[0], operands[1]);
873 ; movdi instruction pattern(s).
876 (define_expand "movdi"
877 [(set (match_operand:DI 0 "general_operand" "")
878 (match_operand:DI 1 "general_operand" ""))]
881 /* Handle symbolic constants. */
883 && (SYMBOLIC_CONST (operands[1])
884 || (GET_CODE (operands[1]) == PLUS
885 && XEXP (operands[1], 0) == pic_offset_table_rtx
886 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
887 emit_symbolic_move (operands);
890 (define_insn "*movdi_larl"
891 [(set (match_operand:DI 0 "register_operand" "=d")
892 (match_operand:DI 1 "larl_operand" "X"))]
894 && !FP_REG_P (operands[0])"
896 [(set_attr "op_type" "RIL")
897 (set_attr "type" "larl")])
899 (define_insn "*movdi_64dfp"
900 [(set (match_operand:DI 0 "nonimmediate_operand"
901 "=d,d,d,d,d,d,d,d,f,d,d,d,d,
902 m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
903 (match_operand:DI 1 "general_operand"
904 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,d,m,
905 d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
906 "TARGET_64BIT && TARGET_DFP"
932 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RRE,RXY,RXY,
933 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
934 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,lr,load,store,
935 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
937 (define_insn "*movdi_64extimm"
938 [(set (match_operand:DI 0 "nonimmediate_operand"
939 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
940 (match_operand:DI 1 "general_operand"
941 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
942 "TARGET_64BIT && TARGET_EXTIMM"
966 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
967 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
968 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
969 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
971 (define_insn "*movdi_64"
972 [(set (match_operand:DI 0 "nonimmediate_operand"
973 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
974 (match_operand:DI 1 "general_operand"
975 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
976 "TARGET_64BIT && !TARGET_EXTIMM"
997 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
998 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
999 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
1000 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1003 [(set (match_operand:DI 0 "register_operand" "")
1004 (match_operand:DI 1 "register_operand" ""))]
1005 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1006 [(set (match_dup 2) (match_dup 3))
1007 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1008 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1009 "operands[2] = gen_lowpart (SImode, operands[0]);
1010 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1013 [(set (match_operand:DI 0 "register_operand" "")
1014 (match_operand:DI 1 "register_operand" ""))]
1015 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1016 && dead_or_set_p (insn, operands[1])"
1017 [(set (match_dup 3) (match_dup 2))
1018 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1019 (set (match_dup 4) (match_dup 2))]
1020 "operands[2] = gen_lowpart (SImode, operands[1]);
1021 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1024 [(set (match_operand:DI 0 "register_operand" "")
1025 (match_operand:DI 1 "register_operand" ""))]
1026 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1027 && !dead_or_set_p (insn, operands[1])"
1028 [(set (match_dup 3) (match_dup 2))
1029 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1030 (set (match_dup 4) (match_dup 2))
1031 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1032 "operands[2] = gen_lowpart (SImode, operands[1]);
1033 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1035 (define_insn "*movdi_31"
1036 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1037 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1052 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1053 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1056 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1057 (match_operand:DI 1 "general_operand" ""))]
1058 "!TARGET_64BIT && reload_completed
1059 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1060 [(set (match_dup 2) (match_dup 4))
1061 (set (match_dup 3) (match_dup 5))]
1063 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1064 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1065 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1066 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1070 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1071 (match_operand:DI 1 "general_operand" ""))]
1072 "!TARGET_64BIT && reload_completed
1073 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1074 [(set (match_dup 2) (match_dup 4))
1075 (set (match_dup 3) (match_dup 5))]
1077 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1078 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1079 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1080 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1084 [(set (match_operand:DI 0 "register_operand" "")
1085 (match_operand:DI 1 "memory_operand" ""))]
1086 "!TARGET_64BIT && reload_completed
1087 && !FP_REG_P (operands[0])
1088 && !s_operand (operands[1], VOIDmode)"
1089 [(set (match_dup 0) (match_dup 1))]
1091 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1092 s390_load_address (addr, XEXP (operands[1], 0));
1093 operands[1] = replace_equiv_address (operands[1], addr);
1096 (define_expand "reload_outdi"
1097 [(parallel [(match_operand:DI 0 "" "")
1098 (match_operand:DI 1 "register_operand" "d")
1099 (match_operand:SI 2 "register_operand" "=&a")])]
1102 gcc_assert (MEM_P (operands[0]));
1103 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1104 operands[0] = replace_equiv_address (operands[0], operands[2]);
1105 emit_move_insn (operands[0], operands[1]);
1110 [(set (match_operand:DI 0 "register_operand" "")
1111 (mem:DI (match_operand 1 "address_operand" "")))]
1113 && !FP_REG_P (operands[0])
1114 && GET_CODE (operands[1]) == SYMBOL_REF
1115 && CONSTANT_POOL_ADDRESS_P (operands[1])
1116 && get_pool_mode (operands[1]) == DImode
1117 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1118 [(set (match_dup 0) (match_dup 2))]
1119 "operands[2] = get_pool_constant (operands[1]);")
1121 (define_insn "*la_64"
1122 [(set (match_operand:DI 0 "register_operand" "=d,d")
1123 (match_operand:QI 1 "address_operand" "U,W"))]
1128 [(set_attr "op_type" "RX,RXY")
1129 (set_attr "type" "la")])
1133 [(set (match_operand:DI 0 "register_operand" "")
1134 (match_operand:QI 1 "address_operand" ""))
1135 (clobber (reg:CC CC_REGNUM))])]
1137 && preferred_la_operand_p (operands[1], const0_rtx)"
1138 [(set (match_dup 0) (match_dup 1))]
1142 [(set (match_operand:DI 0 "register_operand" "")
1143 (match_operand:DI 1 "register_operand" ""))
1146 (plus:DI (match_dup 0)
1147 (match_operand:DI 2 "nonmemory_operand" "")))
1148 (clobber (reg:CC CC_REGNUM))])]
1150 && !reg_overlap_mentioned_p (operands[0], operands[2])
1151 && preferred_la_operand_p (operands[1], operands[2])"
1152 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1155 (define_expand "reload_indi"
1156 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1157 (match_operand:DI 1 "s390_plus_operand" "")
1158 (match_operand:DI 2 "register_operand" "=&a")])]
1161 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1166 ; movsi instruction pattern(s).
1169 (define_expand "movsi"
1170 [(set (match_operand:SI 0 "general_operand" "")
1171 (match_operand:SI 1 "general_operand" ""))]
1174 /* Handle symbolic constants. */
1176 && (SYMBOLIC_CONST (operands[1])
1177 || (GET_CODE (operands[1]) == PLUS
1178 && XEXP (operands[1], 0) == pic_offset_table_rtx
1179 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1180 emit_symbolic_move (operands);
1183 (define_insn "*movsi_larl"
1184 [(set (match_operand:SI 0 "register_operand" "=d")
1185 (match_operand:SI 1 "larl_operand" "X"))]
1186 "!TARGET_64BIT && TARGET_CPU_ZARCH
1187 && !FP_REG_P (operands[0])"
1189 [(set_attr "op_type" "RIL")
1190 (set_attr "type" "larl")])
1192 (define_insn "*movsi_zarch"
1193 [(set (match_operand:SI 0 "nonimmediate_operand"
1194 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1195 (match_operand:SI 1 "general_operand"
1196 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1219 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1220 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1221 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1222 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1224 (define_insn "*movsi_esa"
1225 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1226 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1241 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1242 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1245 [(set (match_operand:SI 0 "register_operand" "")
1246 (mem:SI (match_operand 1 "address_operand" "")))]
1247 "!FP_REG_P (operands[0])
1248 && GET_CODE (operands[1]) == SYMBOL_REF
1249 && CONSTANT_POOL_ADDRESS_P (operands[1])
1250 && get_pool_mode (operands[1]) == SImode
1251 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1252 [(set (match_dup 0) (match_dup 2))]
1253 "operands[2] = get_pool_constant (operands[1]);")
1255 (define_insn "*la_31"
1256 [(set (match_operand:SI 0 "register_operand" "=d,d")
1257 (match_operand:QI 1 "address_operand" "U,W"))]
1258 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1262 [(set_attr "op_type" "RX,RXY")
1263 (set_attr "type" "la")])
1267 [(set (match_operand:SI 0 "register_operand" "")
1268 (match_operand:QI 1 "address_operand" ""))
1269 (clobber (reg:CC CC_REGNUM))])]
1271 && preferred_la_operand_p (operands[1], const0_rtx)"
1272 [(set (match_dup 0) (match_dup 1))]
1276 [(set (match_operand:SI 0 "register_operand" "")
1277 (match_operand:SI 1 "register_operand" ""))
1280 (plus:SI (match_dup 0)
1281 (match_operand:SI 2 "nonmemory_operand" "")))
1282 (clobber (reg:CC CC_REGNUM))])]
1284 && !reg_overlap_mentioned_p (operands[0], operands[2])
1285 && preferred_la_operand_p (operands[1], operands[2])"
1286 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1289 (define_insn "*la_31_and"
1290 [(set (match_operand:SI 0 "register_operand" "=d,d")
1291 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1292 (const_int 2147483647)))]
1297 [(set_attr "op_type" "RX,RXY")
1298 (set_attr "type" "la")])
1300 (define_insn_and_split "*la_31_and_cc"
1301 [(set (match_operand:SI 0 "register_operand" "=d")
1302 (and:SI (match_operand:QI 1 "address_operand" "p")
1303 (const_int 2147483647)))
1304 (clobber (reg:CC CC_REGNUM))]
1307 "&& reload_completed"
1309 (and:SI (match_dup 1) (const_int 2147483647)))]
1311 [(set_attr "op_type" "RX")
1312 (set_attr "type" "la")])
1314 (define_insn "force_la_31"
1315 [(set (match_operand:SI 0 "register_operand" "=d,d")
1316 (match_operand:QI 1 "address_operand" "U,W"))
1317 (use (const_int 0))]
1322 [(set_attr "op_type" "RX")
1323 (set_attr "type" "la")])
1325 (define_expand "reload_insi"
1326 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1327 (match_operand:SI 1 "s390_plus_operand" "")
1328 (match_operand:SI 2 "register_operand" "=&a")])]
1331 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1336 ; movhi instruction pattern(s).
1339 (define_expand "movhi"
1340 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1341 (match_operand:HI 1 "general_operand" ""))]
1344 /* Make it explicit that loading a register from memory
1345 always sign-extends (at least) to SImode. */
1346 if (optimize && !no_new_pseudos
1347 && register_operand (operands[0], VOIDmode)
1348 && GET_CODE (operands[1]) == MEM)
1350 rtx tmp = gen_reg_rtx (SImode);
1351 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1352 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1353 operands[1] = gen_lowpart (HImode, tmp);
1357 (define_insn "*movhi"
1358 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1359 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1369 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1370 (set_attr "type" "lr,*,*,*,store,store,*")])
1373 [(set (match_operand:HI 0 "register_operand" "")
1374 (mem:HI (match_operand 1 "address_operand" "")))]
1375 "GET_CODE (operands[1]) == SYMBOL_REF
1376 && CONSTANT_POOL_ADDRESS_P (operands[1])
1377 && get_pool_mode (operands[1]) == HImode
1378 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1379 [(set (match_dup 0) (match_dup 2))]
1380 "operands[2] = get_pool_constant (operands[1]);")
1383 ; movqi instruction pattern(s).
1386 (define_expand "movqi"
1387 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1388 (match_operand:QI 1 "general_operand" ""))]
1391 /* On z/Architecture, zero-extending from memory to register
1392 is just as fast as a QImode load. */
1393 if (TARGET_ZARCH && optimize && !no_new_pseudos
1394 && register_operand (operands[0], VOIDmode)
1395 && GET_CODE (operands[1]) == MEM)
1397 rtx tmp = gen_reg_rtx (word_mode);
1398 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1399 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1400 operands[1] = gen_lowpart (QImode, tmp);
1404 (define_insn "*movqi"
1405 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1406 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1418 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1419 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1422 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1423 (mem:QI (match_operand 1 "address_operand" "")))]
1424 "GET_CODE (operands[1]) == SYMBOL_REF
1425 && CONSTANT_POOL_ADDRESS_P (operands[1])
1426 && get_pool_mode (operands[1]) == QImode
1427 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1428 [(set (match_dup 0) (match_dup 2))]
1429 "operands[2] = get_pool_constant (operands[1]);")
1432 ; movstrictqi instruction pattern(s).
1435 (define_insn "*movstrictqi"
1436 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1437 (match_operand:QI 1 "memory_operand" "R,T"))]
1442 [(set_attr "op_type" "RX,RXY")])
1445 ; movstricthi instruction pattern(s).
1448 (define_insn "*movstricthi"
1449 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1450 (match_operand:HI 1 "memory_operand" "Q,S"))
1451 (clobber (reg:CC CC_REGNUM))]
1456 [(set_attr "op_type" "RS,RSY")])
1459 ; movstrictsi instruction pattern(s).
1462 (define_insn "movstrictsi"
1463 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1464 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1471 [(set_attr "op_type" "RR,RX,RXY,RRE")
1472 (set_attr "type" "lr,load,load,*")])
1475 ; movtf instruction pattern(s).
1478 (define_expand "movtf"
1479 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1480 (match_operand:TF 1 "general_operand" ""))]
1484 (define_insn "*movtf_64"
1485 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,d,QS,d,o,Q")
1486 (match_operand:TF 1 "general_operand" "G,f,o,f,QS,d,dm,d,Q"))]
1498 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
1499 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
1501 (define_insn "*movtf_31"
1502 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
1503 (match_operand:TF 1 "general_operand" "G,f,o,f,Q"))]
1511 [(set_attr "op_type" "RRE,RRE,*,*,*")
1512 (set_attr "type" "fsimptf,fsimptf,*,*,*")])
1514 ; TFmode in GPRs splitters
1517 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1518 (match_operand:TF 1 "general_operand" ""))]
1519 "TARGET_64BIT && reload_completed
1520 && s390_split_ok_p (operands[0], operands[1], TFmode, 0)"
1521 [(set (match_dup 2) (match_dup 4))
1522 (set (match_dup 3) (match_dup 5))]
1524 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
1525 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
1526 operands[4] = operand_subword (operands[1], 0, 0, TFmode);
1527 operands[5] = operand_subword (operands[1], 1, 0, TFmode);
1531 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1532 (match_operand:TF 1 "general_operand" ""))]
1533 "TARGET_64BIT && reload_completed
1534 && s390_split_ok_p (operands[0], operands[1], TFmode, 1)"
1535 [(set (match_dup 2) (match_dup 4))
1536 (set (match_dup 3) (match_dup 5))]
1538 operands[2] = operand_subword (operands[0], 1, 0, TFmode);
1539 operands[3] = operand_subword (operands[0], 0, 0, TFmode);
1540 operands[4] = operand_subword (operands[1], 1, 0, TFmode);
1541 operands[5] = operand_subword (operands[1], 0, 0, TFmode);
1545 [(set (match_operand:TF 0 "register_operand" "")
1546 (match_operand:TF 1 "memory_operand" ""))]
1547 "TARGET_64BIT && reload_completed
1548 && !FP_REG_P (operands[0])
1549 && !s_operand (operands[1], VOIDmode)"
1550 [(set (match_dup 0) (match_dup 1))]
1552 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1553 s390_load_address (addr, XEXP (operands[1], 0));
1554 operands[1] = replace_equiv_address (operands[1], addr);
1557 ; TFmode in BFPs splitters
1560 [(set (match_operand:TF 0 "register_operand" "")
1561 (match_operand:TF 1 "memory_operand" ""))]
1562 "reload_completed && offsettable_memref_p (operands[1])
1563 && FP_REG_P (operands[0])"
1564 [(set (match_dup 2) (match_dup 4))
1565 (set (match_dup 3) (match_dup 5))]
1567 operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0);
1568 operands[3] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8);
1569 operands[4] = adjust_address_nv (operands[1], DFmode, 0);
1570 operands[5] = adjust_address_nv (operands[1], DFmode, 8);
1574 [(set (match_operand:TF 0 "memory_operand" "")
1575 (match_operand:TF 1 "register_operand" ""))]
1576 "reload_completed && offsettable_memref_p (operands[0])
1577 && FP_REG_P (operands[1])"
1578 [(set (match_dup 2) (match_dup 4))
1579 (set (match_dup 3) (match_dup 5))]
1581 operands[2] = adjust_address_nv (operands[0], DFmode, 0);
1582 operands[3] = adjust_address_nv (operands[0], DFmode, 8);
1583 operands[4] = simplify_gen_subreg (DFmode, operands[1], TFmode, 0);
1584 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, 8);
1587 (define_expand "reload_outtf"
1588 [(parallel [(match_operand:TF 0 "" "")
1589 (match_operand:TF 1 "register_operand" "f")
1590 (match_operand:SI 2 "register_operand" "=&a")])]
1593 rtx addr = gen_lowpart (Pmode, operands[2]);
1595 gcc_assert (MEM_P (operands[0]));
1596 s390_load_address (addr, find_replacement (&XEXP (operands[0], 0)));
1597 operands[0] = replace_equiv_address (operands[0], addr);
1598 emit_move_insn (operands[0], operands[1]);
1602 (define_expand "reload_intf"
1603 [(parallel [(match_operand:TF 0 "register_operand" "=f")
1604 (match_operand:TF 1 "" "")
1605 (match_operand:SI 2 "register_operand" "=&a")])]
1608 rtx addr = gen_lowpart (Pmode, operands[2]);
1610 gcc_assert (MEM_P (operands[1]));
1611 s390_load_address (addr, find_replacement (&XEXP (operands[1], 0)));
1612 operands[1] = replace_equiv_address (operands[1], addr);
1613 emit_move_insn (operands[0], operands[1]);
1618 ; movdf instruction pattern(s).
1621 (define_expand "movdf"
1622 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1623 (match_operand:DF 1 "general_operand" ""))]
1627 (define_insn "*movdf_64dfp"
1628 [(set (match_operand:DF 0 "nonimmediate_operand"
1629 "=f,f,f,d,f,f,R,T,d,d,m,?Q")
1630 (match_operand:DF 1 "general_operand"
1631 "G,f,d,f,R,T,f,f,d,m,d,?Q"))]
1632 "TARGET_64BIT && TARGET_DFP"
1646 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1647 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
1648 fstoredf,fstoredf,lr,load,store,*")])
1650 (define_insn "*movdf_64"
1651 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1652 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1665 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1666 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1668 (define_insn "*movdf_31"
1669 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1670 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1686 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1687 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1688 lm,lm,stm,stm,*,*,*")])
1691 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1692 (match_operand:DF 1 "general_operand" ""))]
1693 "!TARGET_64BIT && reload_completed
1694 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1695 [(set (match_dup 2) (match_dup 4))
1696 (set (match_dup 3) (match_dup 5))]
1698 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1699 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1700 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1701 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1705 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1706 (match_operand:DF 1 "general_operand" ""))]
1707 "!TARGET_64BIT && reload_completed
1708 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1709 [(set (match_dup 2) (match_dup 4))
1710 (set (match_dup 3) (match_dup 5))]
1712 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1713 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1714 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1715 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1719 [(set (match_operand:DF 0 "register_operand" "")
1720 (match_operand:DF 1 "memory_operand" ""))]
1721 "!TARGET_64BIT && reload_completed
1722 && !FP_REG_P (operands[0])
1723 && !s_operand (operands[1], VOIDmode)"
1724 [(set (match_dup 0) (match_dup 1))]
1726 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1727 s390_load_address (addr, XEXP (operands[1], 0));
1728 operands[1] = replace_equiv_address (operands[1], addr);
1731 (define_expand "reload_outdf"
1732 [(parallel [(match_operand:DF 0 "" "")
1733 (match_operand:DF 1 "register_operand" "d")
1734 (match_operand:SI 2 "register_operand" "=&a")])]
1737 gcc_assert (MEM_P (operands[0]));
1738 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1739 operands[0] = replace_equiv_address (operands[0], operands[2]);
1740 emit_move_insn (operands[0], operands[1]);
1745 ; movsf instruction pattern(s).
1748 (define_insn "movsf"
1749 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1750 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1765 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1766 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1767 lr,load,load,store,store,*")])
1770 ; movcc instruction pattern
1773 (define_insn "movcc"
1774 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1775 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1785 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1786 (set_attr "type" "lr,*,*,store,store,load,load")])
1789 ; Block move (MVC) patterns.
1793 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1794 (match_operand:BLK 1 "memory_operand" "Q"))
1795 (use (match_operand 2 "const_int_operand" "n"))]
1796 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1797 "mvc\t%O0(%2,%R0),%S1"
1798 [(set_attr "op_type" "SS")])
1801 [(set (match_operand 0 "memory_operand" "")
1802 (match_operand 1 "memory_operand" ""))]
1804 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1805 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1807 [(set (match_dup 0) (match_dup 1))
1808 (use (match_dup 2))])]
1810 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1811 operands[0] = adjust_address (operands[0], BLKmode, 0);
1812 operands[1] = adjust_address (operands[1], BLKmode, 0);
1817 [(set (match_operand:BLK 0 "memory_operand" "")
1818 (match_operand:BLK 1 "memory_operand" ""))
1819 (use (match_operand 2 "const_int_operand" ""))])
1821 [(set (match_operand:BLK 3 "memory_operand" "")
1822 (match_operand:BLK 4 "memory_operand" ""))
1823 (use (match_operand 5 "const_int_operand" ""))])]
1824 "s390_offset_p (operands[0], operands[3], operands[2])
1825 && s390_offset_p (operands[1], operands[4], operands[2])
1826 && !s390_overlap_p (operands[0], operands[1],
1827 INTVAL (operands[2]) + INTVAL (operands[5]))
1828 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1830 [(set (match_dup 6) (match_dup 7))
1831 (use (match_dup 8))])]
1832 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1833 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1834 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1838 ; load_multiple pattern(s).
1840 ; ??? Due to reload problems with replacing registers inside match_parallel
1841 ; we currently support load_multiple/store_multiple only after reload.
1844 (define_expand "load_multiple"
1845 [(match_par_dup 3 [(set (match_operand 0 "" "")
1846 (match_operand 1 "" ""))
1847 (use (match_operand 2 "" ""))])]
1850 enum machine_mode mode;
1856 /* Support only loading a constant number of fixed-point registers from
1857 memory and only bother with this if more than two */
1858 if (GET_CODE (operands[2]) != CONST_INT
1859 || INTVAL (operands[2]) < 2
1860 || INTVAL (operands[2]) > 16
1861 || GET_CODE (operands[1]) != MEM
1862 || GET_CODE (operands[0]) != REG
1863 || REGNO (operands[0]) >= 16)
1866 count = INTVAL (operands[2]);
1867 regno = REGNO (operands[0]);
1868 mode = GET_MODE (operands[0]);
1869 if (mode != SImode && mode != word_mode)
1872 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1875 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1877 from = XEXP (operands[1], 0);
1880 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1881 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1882 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1884 from = XEXP (XEXP (operands[1], 0), 0);
1885 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1892 from = force_reg (Pmode, XEXP (operands[1], 0));
1896 for (i = 0; i < count; i++)
1897 XVECEXP (operands[3], 0, i)
1898 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1899 change_address (operands[1], mode,
1900 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1903 (define_insn "*load_multiple_di"
1904 [(match_parallel 0 "load_multiple_operation"
1905 [(set (match_operand:DI 1 "register_operand" "=r")
1906 (match_operand:DI 2 "s_operand" "QS"))])]
1907 "reload_completed && word_mode == DImode"
1909 int words = XVECLEN (operands[0], 0);
1910 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1911 return "lmg\t%1,%0,%S2";
1913 [(set_attr "op_type" "RSY")
1914 (set_attr "type" "lm")])
1916 (define_insn "*load_multiple_si"
1917 [(match_parallel 0 "load_multiple_operation"
1918 [(set (match_operand:SI 1 "register_operand" "=r,r")
1919 (match_operand:SI 2 "s_operand" "Q,S"))])]
1922 int words = XVECLEN (operands[0], 0);
1923 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1924 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1926 [(set_attr "op_type" "RS,RSY")
1927 (set_attr "type" "lm")])
1930 ; store multiple pattern(s).
1933 (define_expand "store_multiple"
1934 [(match_par_dup 3 [(set (match_operand 0 "" "")
1935 (match_operand 1 "" ""))
1936 (use (match_operand 2 "" ""))])]
1939 enum machine_mode mode;
1945 /* Support only storing a constant number of fixed-point registers to
1946 memory and only bother with this if more than two. */
1947 if (GET_CODE (operands[2]) != CONST_INT
1948 || INTVAL (operands[2]) < 2
1949 || INTVAL (operands[2]) > 16
1950 || GET_CODE (operands[0]) != MEM
1951 || GET_CODE (operands[1]) != REG
1952 || REGNO (operands[1]) >= 16)
1955 count = INTVAL (operands[2]);
1956 regno = REGNO (operands[1]);
1957 mode = GET_MODE (operands[1]);
1958 if (mode != SImode && mode != word_mode)
1961 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1965 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1967 to = XEXP (operands[0], 0);
1970 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1971 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1972 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1974 to = XEXP (XEXP (operands[0], 0), 0);
1975 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1982 to = force_reg (Pmode, XEXP (operands[0], 0));
1986 for (i = 0; i < count; i++)
1987 XVECEXP (operands[3], 0, i)
1988 = gen_rtx_SET (VOIDmode,
1989 change_address (operands[0], mode,
1990 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1991 gen_rtx_REG (mode, regno + i));
1994 (define_insn "*store_multiple_di"
1995 [(match_parallel 0 "store_multiple_operation"
1996 [(set (match_operand:DI 1 "s_operand" "=QS")
1997 (match_operand:DI 2 "register_operand" "r"))])]
1998 "reload_completed && word_mode == DImode"
2000 int words = XVECLEN (operands[0], 0);
2001 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2002 return "stmg\t%2,%0,%S1";
2004 [(set_attr "op_type" "RSY")
2005 (set_attr "type" "stm")])
2008 (define_insn "*store_multiple_si"
2009 [(match_parallel 0 "store_multiple_operation"
2010 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2011 (match_operand:SI 2 "register_operand" "r,r"))])]
2014 int words = XVECLEN (operands[0], 0);
2015 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2016 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2018 [(set_attr "op_type" "RS,RSY")
2019 (set_attr "type" "stm")])
2022 ;; String instructions.
2025 (define_insn "*execute"
2026 [(match_parallel 0 ""
2027 [(unspec [(match_operand 1 "register_operand" "a")
2028 (match_operand:BLK 2 "memory_operand" "R")
2029 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2030 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2031 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2033 [(set_attr "op_type" "RX")
2034 (set_attr "type" "cs")])
2038 ; strlenM instruction pattern(s).
2041 (define_expand "strlen<mode>"
2042 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2045 (unspec:P [(const_int 0)
2046 (match_operand:BLK 1 "memory_operand" "")
2048 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2049 (clobber (scratch:P))
2050 (clobber (reg:CC CC_REGNUM))])
2052 [(set (match_operand:P 0 "register_operand" "")
2053 (minus:P (match_dup 4) (match_dup 5)))
2054 (clobber (reg:CC CC_REGNUM))])]
2057 operands[4] = gen_reg_rtx (Pmode);
2058 operands[5] = gen_reg_rtx (Pmode);
2059 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2060 operands[1] = replace_equiv_address (operands[1], operands[5]);
2063 (define_insn "*strlen<mode>"
2064 [(set (match_operand:P 0 "register_operand" "=a")
2065 (unspec:P [(match_operand:P 2 "general_operand" "0")
2066 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2068 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2069 (clobber (match_scratch:P 1 "=a"))
2070 (clobber (reg:CC CC_REGNUM))]
2072 "srst\t%0,%1\;jo\t.-4"
2073 [(set_attr "length" "8")
2074 (set_attr "type" "vs")])
2077 ; cmpstrM instruction pattern(s).
2080 (define_expand "cmpstrsi"
2081 [(set (reg:SI 0) (const_int 0))
2083 [(clobber (match_operand 3 "" ""))
2084 (clobber (match_dup 4))
2085 (set (reg:CCU CC_REGNUM)
2086 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2087 (match_operand:BLK 2 "memory_operand" "")))
2090 [(set (match_operand:SI 0 "register_operand" "=d")
2091 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
2092 (clobber (reg:CC CC_REGNUM))])]
2095 /* As the result of CMPINT is inverted compared to what we need,
2096 we have to swap the operands. */
2097 rtx op1 = operands[2];
2098 rtx op2 = operands[1];
2099 rtx addr1 = gen_reg_rtx (Pmode);
2100 rtx addr2 = gen_reg_rtx (Pmode);
2102 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2103 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2104 operands[1] = replace_equiv_address_nv (op1, addr1);
2105 operands[2] = replace_equiv_address_nv (op2, addr2);
2106 operands[3] = addr1;
2107 operands[4] = addr2;
2110 (define_insn "*cmpstr<mode>"
2111 [(clobber (match_operand:P 0 "register_operand" "=d"))
2112 (clobber (match_operand:P 1 "register_operand" "=d"))
2113 (set (reg:CCU CC_REGNUM)
2114 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2115 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2118 "clst\t%0,%1\;jo\t.-4"
2119 [(set_attr "length" "8")
2120 (set_attr "type" "vs")])
2123 ; movstr instruction pattern.
2126 (define_expand "movstr"
2127 [(set (reg:SI 0) (const_int 0))
2129 [(clobber (match_dup 3))
2130 (set (match_operand:BLK 1 "memory_operand" "")
2131 (match_operand:BLK 2 "memory_operand" ""))
2132 (set (match_operand 0 "register_operand" "")
2133 (unspec [(match_dup 1)
2135 (reg:SI 0)] UNSPEC_MVST))
2136 (clobber (reg:CC CC_REGNUM))])]
2139 rtx addr1 = gen_reg_rtx (Pmode);
2140 rtx addr2 = gen_reg_rtx (Pmode);
2142 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2143 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2144 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2145 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2146 operands[3] = addr2;
2149 (define_insn "*movstr"
2150 [(clobber (match_operand:P 2 "register_operand" "=d"))
2151 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2152 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2153 (set (match_operand:P 0 "register_operand" "=d")
2154 (unspec [(mem:BLK (match_dup 1))
2155 (mem:BLK (match_dup 3))
2156 (reg:SI 0)] UNSPEC_MVST))
2157 (clobber (reg:CC CC_REGNUM))]
2159 "mvst\t%1,%2\;jo\t.-4"
2160 [(set_attr "length" "8")
2161 (set_attr "type" "vs")])
2165 ; movmemM instruction pattern(s).
2168 (define_expand "movmem<mode>"
2169 [(set (match_operand:BLK 0 "memory_operand" "")
2170 (match_operand:BLK 1 "memory_operand" ""))
2171 (use (match_operand:GPR 2 "general_operand" ""))
2172 (match_operand 3 "" "")]
2174 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2176 ; Move a block that is up to 256 bytes in length.
2177 ; The block length is taken as (operands[2] % 256) + 1.
2179 (define_expand "movmem_short"
2181 [(set (match_operand:BLK 0 "memory_operand" "")
2182 (match_operand:BLK 1 "memory_operand" ""))
2183 (use (match_operand 2 "nonmemory_operand" ""))
2184 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2185 (clobber (match_dup 3))])]
2187 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2189 (define_insn "*movmem_short"
2190 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2191 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2192 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2193 (use (match_operand 3 "immediate_operand" "X,R,X"))
2194 (clobber (match_scratch 4 "=X,X,&a"))]
2195 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2196 && GET_MODE (operands[4]) == Pmode"
2198 [(set_attr "type" "cs")])
2201 [(set (match_operand:BLK 0 "memory_operand" "")
2202 (match_operand:BLK 1 "memory_operand" ""))
2203 (use (match_operand 2 "const_int_operand" ""))
2204 (use (match_operand 3 "immediate_operand" ""))
2205 (clobber (scratch))]
2208 [(set (match_dup 0) (match_dup 1))
2209 (use (match_dup 2))])]
2210 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2213 [(set (match_operand:BLK 0 "memory_operand" "")
2214 (match_operand:BLK 1 "memory_operand" ""))
2215 (use (match_operand 2 "register_operand" ""))
2216 (use (match_operand 3 "memory_operand" ""))
2217 (clobber (scratch))]
2220 [(unspec [(match_dup 2) (match_dup 3)
2221 (const_int 0)] UNSPEC_EXECUTE)
2222 (set (match_dup 0) (match_dup 1))
2223 (use (const_int 1))])]
2227 [(set (match_operand:BLK 0 "memory_operand" "")
2228 (match_operand:BLK 1 "memory_operand" ""))
2229 (use (match_operand 2 "register_operand" ""))
2230 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2231 (clobber (match_operand 3 "register_operand" ""))]
2232 "reload_completed && TARGET_CPU_ZARCH"
2233 [(set (match_dup 3) (label_ref (match_dup 4)))
2235 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2236 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2237 (set (match_dup 0) (match_dup 1))
2238 (use (const_int 1))])]
2239 "operands[4] = gen_label_rtx ();")
2241 ; Move a block of arbitrary length.
2243 (define_expand "movmem_long"
2245 [(clobber (match_dup 2))
2246 (clobber (match_dup 3))
2247 (set (match_operand:BLK 0 "memory_operand" "")
2248 (match_operand:BLK 1 "memory_operand" ""))
2249 (use (match_operand 2 "general_operand" ""))
2251 (clobber (reg:CC CC_REGNUM))])]
2254 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2255 rtx reg0 = gen_reg_rtx (dword_mode);
2256 rtx reg1 = gen_reg_rtx (dword_mode);
2257 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2258 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2259 rtx len0 = gen_lowpart (Pmode, reg0);
2260 rtx len1 = gen_lowpart (Pmode, reg1);
2262 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2263 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2264 emit_move_insn (len0, operands[2]);
2266 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2267 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2268 emit_move_insn (len1, operands[2]);
2270 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2271 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2276 (define_insn "*movmem_long"
2277 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2278 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2279 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2280 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2283 (clobber (reg:CC CC_REGNUM))]
2285 "mvcle\t%0,%1,0\;jo\t.-4"
2286 [(set_attr "length" "8")
2287 (set_attr "type" "vs")])
2290 ; setmemM instruction pattern(s).
2293 (define_expand "setmem<mode>"
2294 [(set (match_operand:BLK 0 "memory_operand" "")
2295 (match_operand:QI 2 "general_operand" ""))
2296 (use (match_operand:GPR 1 "general_operand" ""))
2297 (match_operand 3 "" "")]
2299 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2301 ; Clear a block that is up to 256 bytes in length.
2302 ; The block length is taken as (operands[1] % 256) + 1.
2304 (define_expand "clrmem_short"
2306 [(set (match_operand:BLK 0 "memory_operand" "")
2308 (use (match_operand 1 "nonmemory_operand" ""))
2309 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2310 (clobber (match_dup 2))
2311 (clobber (reg:CC CC_REGNUM))])]
2313 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2315 (define_insn "*clrmem_short"
2316 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2318 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2319 (use (match_operand 2 "immediate_operand" "X,R,X"))
2320 (clobber (match_scratch 3 "=X,X,&a"))
2321 (clobber (reg:CC CC_REGNUM))]
2322 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2323 && GET_MODE (operands[3]) == Pmode"
2325 [(set_attr "type" "cs")])
2328 [(set (match_operand:BLK 0 "memory_operand" "")
2330 (use (match_operand 1 "const_int_operand" ""))
2331 (use (match_operand 2 "immediate_operand" ""))
2333 (clobber (reg:CC CC_REGNUM))]
2336 [(set (match_dup 0) (const_int 0))
2338 (clobber (reg:CC CC_REGNUM))])]
2339 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2342 [(set (match_operand:BLK 0 "memory_operand" "")
2344 (use (match_operand 1 "register_operand" ""))
2345 (use (match_operand 2 "memory_operand" ""))
2347 (clobber (reg:CC CC_REGNUM))]
2350 [(unspec [(match_dup 1) (match_dup 2)
2351 (const_int 0)] UNSPEC_EXECUTE)
2352 (set (match_dup 0) (const_int 0))
2354 (clobber (reg:CC CC_REGNUM))])]
2358 [(set (match_operand:BLK 0 "memory_operand" "")
2360 (use (match_operand 1 "register_operand" ""))
2361 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2362 (clobber (match_operand 2 "register_operand" ""))
2363 (clobber (reg:CC CC_REGNUM))]
2364 "reload_completed && TARGET_CPU_ZARCH"
2365 [(set (match_dup 2) (label_ref (match_dup 3)))
2367 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2368 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2369 (set (match_dup 0) (const_int 0))
2371 (clobber (reg:CC CC_REGNUM))])]
2372 "operands[3] = gen_label_rtx ();")
2374 ; Initialize a block of arbitrary length with (operands[2] % 256).
2376 (define_expand "setmem_long"
2378 [(clobber (match_dup 1))
2379 (set (match_operand:BLK 0 "memory_operand" "")
2380 (match_operand 2 "shift_count_or_setmem_operand" ""))
2381 (use (match_operand 1 "general_operand" ""))
2383 (clobber (reg:CC CC_REGNUM))])]
2386 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2387 rtx reg0 = gen_reg_rtx (dword_mode);
2388 rtx reg1 = gen_reg_rtx (dword_mode);
2389 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2390 rtx len0 = gen_lowpart (Pmode, reg0);
2392 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2393 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2394 emit_move_insn (len0, operands[1]);
2396 emit_move_insn (reg1, const0_rtx);
2398 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2403 (define_insn "*setmem_long"
2404 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2405 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2406 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2408 (use (match_operand:<DBL> 1 "register_operand" "d"))
2409 (clobber (reg:CC CC_REGNUM))]
2411 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2412 [(set_attr "length" "8")
2413 (set_attr "type" "vs")])
2415 (define_insn "*setmem_long_and"
2416 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2417 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2418 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2419 (match_operand 4 "const_int_operand" "n")))
2421 (use (match_operand:<DBL> 1 "register_operand" "d"))
2422 (clobber (reg:CC CC_REGNUM))]
2423 "(INTVAL (operands[4]) & 255) == 255"
2424 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2425 [(set_attr "length" "8")
2426 (set_attr "type" "vs")])
2428 ; cmpmemM instruction pattern(s).
2431 (define_expand "cmpmemsi"
2432 [(set (match_operand:SI 0 "register_operand" "")
2433 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2434 (match_operand:BLK 2 "memory_operand" "") ) )
2435 (use (match_operand:SI 3 "general_operand" ""))
2436 (use (match_operand:SI 4 "" ""))]
2438 "s390_expand_cmpmem (operands[0], operands[1],
2439 operands[2], operands[3]); DONE;")
2441 ; Compare a block that is up to 256 bytes in length.
2442 ; The block length is taken as (operands[2] % 256) + 1.
2444 (define_expand "cmpmem_short"
2446 [(set (reg:CCU CC_REGNUM)
2447 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2448 (match_operand:BLK 1 "memory_operand" "")))
2449 (use (match_operand 2 "nonmemory_operand" ""))
2450 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2451 (clobber (match_dup 3))])]
2453 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2455 (define_insn "*cmpmem_short"
2456 [(set (reg:CCU CC_REGNUM)
2457 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2458 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2459 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2460 (use (match_operand 3 "immediate_operand" "X,R,X"))
2461 (clobber (match_scratch 4 "=X,X,&a"))]
2462 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2463 && GET_MODE (operands[4]) == Pmode"
2465 [(set_attr "type" "cs")])
2468 [(set (reg:CCU CC_REGNUM)
2469 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2470 (match_operand:BLK 1 "memory_operand" "")))
2471 (use (match_operand 2 "const_int_operand" ""))
2472 (use (match_operand 3 "immediate_operand" ""))
2473 (clobber (scratch))]
2476 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2477 (use (match_dup 2))])]
2478 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2481 [(set (reg:CCU CC_REGNUM)
2482 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2483 (match_operand:BLK 1 "memory_operand" "")))
2484 (use (match_operand 2 "register_operand" ""))
2485 (use (match_operand 3 "memory_operand" ""))
2486 (clobber (scratch))]
2489 [(unspec [(match_dup 2) (match_dup 3)
2490 (const_int 0)] UNSPEC_EXECUTE)
2491 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2492 (use (const_int 1))])]
2496 [(set (reg:CCU CC_REGNUM)
2497 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2498 (match_operand:BLK 1 "memory_operand" "")))
2499 (use (match_operand 2 "register_operand" ""))
2500 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2501 (clobber (match_operand 3 "register_operand" ""))]
2502 "reload_completed && TARGET_CPU_ZARCH"
2503 [(set (match_dup 3) (label_ref (match_dup 4)))
2505 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2506 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2507 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2508 (use (const_int 1))])]
2509 "operands[4] = gen_label_rtx ();")
2511 ; Compare a block of arbitrary length.
2513 (define_expand "cmpmem_long"
2515 [(clobber (match_dup 2))
2516 (clobber (match_dup 3))
2517 (set (reg:CCU CC_REGNUM)
2518 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2519 (match_operand:BLK 1 "memory_operand" "")))
2520 (use (match_operand 2 "general_operand" ""))
2521 (use (match_dup 3))])]
2524 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2525 rtx reg0 = gen_reg_rtx (dword_mode);
2526 rtx reg1 = gen_reg_rtx (dword_mode);
2527 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2528 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2529 rtx len0 = gen_lowpart (Pmode, reg0);
2530 rtx len1 = gen_lowpart (Pmode, reg1);
2532 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2533 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2534 emit_move_insn (len0, operands[2]);
2536 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2537 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2538 emit_move_insn (len1, operands[2]);
2540 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2541 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2546 (define_insn "*cmpmem_long"
2547 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2548 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2549 (set (reg:CCU CC_REGNUM)
2550 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2551 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2553 (use (match_dup 3))]
2555 "clcle\t%0,%1,0\;jo\t.-4"
2556 [(set_attr "length" "8")
2557 (set_attr "type" "vs")])
2559 ; Convert CCUmode condition code to integer.
2560 ; Result is zero if EQ, positive if LTU, negative if GTU.
2562 (define_insn_and_split "cmpint"
2563 [(set (match_operand:SI 0 "register_operand" "=d")
2564 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2566 (clobber (reg:CC CC_REGNUM))]
2570 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2572 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2573 (clobber (reg:CC CC_REGNUM))])])
2575 (define_insn_and_split "*cmpint_cc"
2576 [(set (reg CC_REGNUM)
2577 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2580 (set (match_operand:SI 0 "register_operand" "=d")
2581 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2582 "s390_match_ccmode (insn, CCSmode)"
2584 "&& reload_completed"
2585 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2587 [(set (match_dup 2) (match_dup 3))
2588 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2590 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2591 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2592 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2595 (define_insn_and_split "*cmpint_sign"
2596 [(set (match_operand:DI 0 "register_operand" "=d")
2597 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2599 (clobber (reg:CC CC_REGNUM))]
2602 "&& reload_completed"
2603 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2605 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2606 (clobber (reg:CC CC_REGNUM))])])
2608 (define_insn_and_split "*cmpint_sign_cc"
2609 [(set (reg CC_REGNUM)
2610 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2611 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2613 (const_int 32)) (const_int 32))
2615 (set (match_operand:DI 0 "register_operand" "=d")
2616 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2617 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2619 "&& reload_completed"
2620 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2622 [(set (match_dup 2) (match_dup 3))
2623 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2625 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2626 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2627 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2632 ;;- Conversion instructions.
2635 (define_insn "*sethighpartsi"
2636 [(set (match_operand:SI 0 "register_operand" "=d,d")
2637 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2638 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2639 (clobber (reg:CC CC_REGNUM))]
2644 [(set_attr "op_type" "RS,RSY")])
2646 (define_insn "*sethighpartdi_64"
2647 [(set (match_operand:DI 0 "register_operand" "=d")
2648 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2649 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2650 (clobber (reg:CC CC_REGNUM))]
2653 [(set_attr "op_type" "RSY")])
2655 (define_insn "*sethighpartdi_31"
2656 [(set (match_operand:DI 0 "register_operand" "=d,d")
2657 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2658 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2659 (clobber (reg:CC CC_REGNUM))]
2664 [(set_attr "op_type" "RS,RSY")])
2666 (define_insn_and_split "*extzv<mode>"
2667 [(set (match_operand:GPR 0 "register_operand" "=d")
2668 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2669 (match_operand 2 "const_int_operand" "n")
2671 (clobber (reg:CC CC_REGNUM))]
2672 "INTVAL (operands[2]) > 0
2673 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2675 "&& reload_completed"
2677 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2678 (clobber (reg:CC CC_REGNUM))])
2679 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2681 int bitsize = INTVAL (operands[2]);
2682 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2683 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2685 operands[1] = adjust_address (operands[1], BLKmode, 0);
2686 set_mem_size (operands[1], GEN_INT (size));
2687 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2688 operands[3] = GEN_INT (mask);
2691 (define_insn_and_split "*extv<mode>"
2692 [(set (match_operand:GPR 0 "register_operand" "=d")
2693 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2694 (match_operand 2 "const_int_operand" "n")
2696 (clobber (reg:CC CC_REGNUM))]
2697 "INTVAL (operands[2]) > 0
2698 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2700 "&& reload_completed"
2702 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2703 (clobber (reg:CC CC_REGNUM))])
2705 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2706 (clobber (reg:CC CC_REGNUM))])]
2708 int bitsize = INTVAL (operands[2]);
2709 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2710 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2712 operands[1] = adjust_address (operands[1], BLKmode, 0);
2713 set_mem_size (operands[1], GEN_INT (size));
2714 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2715 operands[3] = GEN_INT (mask);
2719 ; insv instruction patterns
2722 (define_expand "insv"
2723 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2724 (match_operand 1 "const_int_operand" "")
2725 (match_operand 2 "const_int_operand" ""))
2726 (match_operand 3 "general_operand" ""))]
2729 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2734 (define_insn "*insv<mode>_mem_reg"
2735 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2736 (match_operand 1 "const_int_operand" "n,n")
2738 (match_operand:P 2 "register_operand" "d,d"))]
2739 "INTVAL (operands[1]) > 0
2740 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2741 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2743 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2745 operands[1] = GEN_INT ((1ul << size) - 1);
2746 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2747 : "stcmy\t%2,%1,%S0";
2749 [(set_attr "op_type" "RS,RSY")])
2751 (define_insn "*insvdi_mem_reghigh"
2752 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2753 (match_operand 1 "const_int_operand" "n")
2755 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2758 && INTVAL (operands[1]) > 0
2759 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2760 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2762 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2764 operands[1] = GEN_INT ((1ul << size) - 1);
2765 return "stcmh\t%2,%1,%S0";
2767 [(set_attr "op_type" "RSY")])
2769 (define_insn "*insv<mode>_reg_imm"
2770 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2772 (match_operand 1 "const_int_operand" "n"))
2773 (match_operand:P 2 "const_int_operand" "n"))]
2775 && INTVAL (operands[1]) >= 0
2776 && INTVAL (operands[1]) < BITS_PER_WORD
2777 && INTVAL (operands[1]) % 16 == 0"
2779 switch (BITS_PER_WORD - INTVAL (operands[1]))
2781 case 64: return "iihh\t%0,%x2"; break;
2782 case 48: return "iihl\t%0,%x2"; break;
2783 case 32: return "iilh\t%0,%x2"; break;
2784 case 16: return "iill\t%0,%x2"; break;
2785 default: gcc_unreachable();
2788 [(set_attr "op_type" "RI")])
2790 (define_insn "*insv<mode>_reg_extimm"
2791 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2793 (match_operand 1 "const_int_operand" "n"))
2794 (match_operand:P 2 "const_int_operand" "n"))]
2796 && INTVAL (operands[1]) >= 0
2797 && INTVAL (operands[1]) < BITS_PER_WORD
2798 && INTVAL (operands[1]) % 32 == 0"
2800 switch (BITS_PER_WORD - INTVAL (operands[1]))
2802 case 64: return "iihf\t%0,%o2"; break;
2803 case 32: return "iilf\t%0,%o2"; break;
2804 default: gcc_unreachable();
2807 [(set_attr "op_type" "RIL")])
2810 ; extendsidi2 instruction pattern(s).
2813 (define_expand "extendsidi2"
2814 [(set (match_operand:DI 0 "register_operand" "")
2815 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2820 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2821 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2822 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2823 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2828 (define_insn "*extendsidi2"
2829 [(set (match_operand:DI 0 "register_operand" "=d,d")
2830 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2835 [(set_attr "op_type" "RRE,RXY")])
2838 ; extend(hi|qi)(si|di)2 instruction pattern(s).
2841 (define_expand "extend<HQI:mode><DSI:mode>2"
2842 [(set (match_operand:DSI 0 "register_operand" "")
2843 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2846 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
2848 rtx tmp = gen_reg_rtx (SImode);
2849 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
2850 emit_insn (gen_extendsidi2 (operands[0], tmp));
2853 else if (!TARGET_EXTIMM)
2855 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
2856 GET_MODE_BITSIZE (<HQI:MODE>mode));
2858 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
2859 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
2860 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
2866 ; extendhidi2 instruction pattern(s).
2869 (define_insn "*extendhidi2_extimm"
2870 [(set (match_operand:DI 0 "register_operand" "=d,d")
2871 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2872 "TARGET_64BIT && TARGET_EXTIMM"
2876 [(set_attr "op_type" "RRE,RXY")])
2878 (define_insn "*extendhidi2"
2879 [(set (match_operand:DI 0 "register_operand" "=d")
2880 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2883 [(set_attr "op_type" "RXY")])
2886 ; extendhisi2 instruction pattern(s).
2889 (define_insn "*extendhisi2_extimm"
2890 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2891 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2897 [(set_attr "op_type" "RRE,RX,RXY")])
2899 (define_insn "*extendhisi2"
2900 [(set (match_operand:SI 0 "register_operand" "=d,d")
2901 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2906 [(set_attr "op_type" "RX,RXY")])
2909 ; extendqi(si|di)2 instruction pattern(s).
2912 ; lbr, lgbr, lb, lgb
2913 (define_insn "*extendqi<mode>2_extimm"
2914 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2915 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2920 [(set_attr "op_type" "RRE,RXY")])
2923 (define_insn "*extendqi<mode>2"
2924 [(set (match_operand:GPR 0 "register_operand" "=d")
2925 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
2926 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
2928 [(set_attr "op_type" "RXY")])
2930 (define_insn_and_split "*extendqi<mode>2_short_displ"
2931 [(set (match_operand:GPR 0 "register_operand" "=d")
2932 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
2933 (clobber (reg:CC CC_REGNUM))]
2934 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
2936 "&& reload_completed"
2938 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2939 (clobber (reg:CC CC_REGNUM))])
2941 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2942 (clobber (reg:CC CC_REGNUM))])]
2944 operands[1] = adjust_address (operands[1], BLKmode, 0);
2945 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2946 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
2947 - GET_MODE_BITSIZE (QImode));
2951 ; zero_extendsidi2 instruction pattern(s).
2954 (define_expand "zero_extendsidi2"
2955 [(set (match_operand:DI 0 "register_operand" "")
2956 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2961 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2962 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2963 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2968 (define_insn "*zero_extendsidi2"
2969 [(set (match_operand:DI 0 "register_operand" "=d,d")
2970 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2975 [(set_attr "op_type" "RRE,RXY")])
2978 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2981 (define_insn "*llgt_sidi"
2982 [(set (match_operand:DI 0 "register_operand" "=d")
2983 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2984 (const_int 2147483647)))]
2987 [(set_attr "op_type" "RXE")])
2989 (define_insn_and_split "*llgt_sidi_split"
2990 [(set (match_operand:DI 0 "register_operand" "=d")
2991 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2992 (const_int 2147483647)))
2993 (clobber (reg:CC CC_REGNUM))]
2996 "&& reload_completed"
2998 (and:DI (subreg:DI (match_dup 1) 0)
2999 (const_int 2147483647)))]
3002 (define_insn "*llgt_sisi"
3003 [(set (match_operand:SI 0 "register_operand" "=d,d")
3004 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
3005 (const_int 2147483647)))]
3010 [(set_attr "op_type" "RRE,RXE")])
3012 (define_insn "*llgt_didi"
3013 [(set (match_operand:DI 0 "register_operand" "=d,d")
3014 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3015 (const_int 2147483647)))]
3020 [(set_attr "op_type" "RRE,RXE")])
3023 [(set (match_operand:GPR 0 "register_operand" "")
3024 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3025 (const_int 2147483647)))
3026 (clobber (reg:CC CC_REGNUM))]
3027 "TARGET_ZARCH && reload_completed"
3029 (and:GPR (match_dup 1)
3030 (const_int 2147483647)))]
3034 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3037 (define_expand "zero_extend<mode>di2"
3038 [(set (match_operand:DI 0 "register_operand" "")
3039 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3044 rtx tmp = gen_reg_rtx (SImode);
3045 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3046 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3049 else if (!TARGET_EXTIMM)
3051 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3052 GET_MODE_BITSIZE(<MODE>mode));
3053 operands[1] = gen_lowpart (DImode, operands[1]);
3054 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3055 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3060 (define_expand "zero_extend<mode>si2"
3061 [(set (match_operand:SI 0 "register_operand" "")
3062 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3067 operands[1] = gen_lowpart (SImode, operands[1]);
3068 emit_insn (gen_andsi3 (operands[0], operands[1],
3069 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3074 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3075 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3076 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3077 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
3082 [(set_attr "op_type" "RRE,RXY")])
3085 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3086 [(set (match_operand:GPR 0 "register_operand" "=d")
3087 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
3088 "TARGET_ZARCH && !TARGET_EXTIMM"
3090 [(set_attr "op_type" "RXY")])
3092 (define_insn_and_split "*zero_extendhisi2_31"
3093 [(set (match_operand:SI 0 "register_operand" "=&d")
3094 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3095 (clobber (reg:CC CC_REGNUM))]
3098 "&& reload_completed"
3099 [(set (match_dup 0) (const_int 0))
3101 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3102 (clobber (reg:CC CC_REGNUM))])]
3103 "operands[2] = gen_lowpart (HImode, operands[0]);")
3105 (define_insn_and_split "*zero_extendqisi2_31"
3106 [(set (match_operand:SI 0 "register_operand" "=&d")
3107 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3110 "&& reload_completed"
3111 [(set (match_dup 0) (const_int 0))
3112 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3113 "operands[2] = gen_lowpart (QImode, operands[0]);")
3116 ; zero_extendqihi2 instruction pattern(s).
3119 (define_expand "zero_extendqihi2"
3120 [(set (match_operand:HI 0 "register_operand" "")
3121 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3122 "TARGET_ZARCH && !TARGET_EXTIMM"
3124 operands[1] = gen_lowpart (HImode, operands[1]);
3125 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3129 (define_insn "*zero_extendqihi2_64"
3130 [(set (match_operand:HI 0 "register_operand" "=d")
3131 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3132 "TARGET_ZARCH && !TARGET_EXTIMM"
3134 [(set_attr "op_type" "RXY")])
3136 (define_insn_and_split "*zero_extendqihi2_31"
3137 [(set (match_operand:HI 0 "register_operand" "=&d")
3138 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3141 "&& reload_completed"
3142 [(set (match_dup 0) (const_int 0))
3143 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3144 "operands[2] = gen_lowpart (QImode, operands[0]);")
3148 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
3151 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3152 [(set (match_operand:GPR 0 "register_operand" "")
3153 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3154 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3156 rtx label1 = gen_label_rtx ();
3157 rtx label2 = gen_label_rtx ();
3158 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3159 REAL_VALUE_TYPE cmp, sub;
3161 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3162 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
3163 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
3165 emit_insn (gen_cmp<BFP:mode> (operands[1],
3166 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
3167 emit_jump_insn (gen_blt (label1));
3168 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3169 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3170 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0], temp,
3174 emit_label (label1);
3175 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0],
3176 operands[1], GEN_INT(5)));
3177 emit_label (label2);
3181 (define_expand "fix_trunc<mode>di2"
3182 [(set (match_operand:DI 0 "register_operand" "")
3183 (fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))]
3184 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3186 operands[1] = force_reg (<MODE>mode, operands[1]);
3187 emit_insn (gen_fix_trunc<mode>di2_ieee (operands[0], operands[1],
3192 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3193 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_ieee"
3194 [(set (match_operand:GPR 0 "register_operand" "=d")
3195 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3196 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3197 (clobber (reg:CC CC_REGNUM))]
3198 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3199 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3200 [(set_attr "op_type" "RRE")
3201 (set_attr "type" "ftoi")])
3204 ; fix_trunctf(si|di)2 instruction pattern(s).
3207 (define_expand "fix_trunctf<mode>2"
3208 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3209 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3210 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3211 (clobber (reg:CC CC_REGNUM))])]
3212 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3216 ; fix_truncdfsi2 instruction pattern(s).
3219 (define_expand "fix_truncdfsi2"
3220 [(set (match_operand:SI 0 "register_operand" "")
3221 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3224 if (TARGET_IBM_FLOAT)
3226 /* This is the algorithm from POP chapter A.5.7.2. */
3228 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3229 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3230 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3232 operands[1] = force_reg (DFmode, operands[1]);
3233 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3234 two31r, two32, temp));
3238 operands[1] = force_reg (DFmode, operands[1]);
3239 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3245 (define_insn "fix_truncdfsi2_ibm"
3246 [(set (match_operand:SI 0 "register_operand" "=d")
3247 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3248 (use (match_operand:DI 2 "immediate_operand" "m"))
3249 (use (match_operand:DI 3 "immediate_operand" "m"))
3250 (use (match_operand:BLK 4 "memory_operand" "m"))
3251 (clobber (reg:CC CC_REGNUM))]
3252 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3254 output_asm_insn ("sd\t%1,%2", operands);
3255 output_asm_insn ("aw\t%1,%3", operands);
3256 output_asm_insn ("std\t%1,%4", operands);
3257 output_asm_insn ("xi\t%N4,128", operands);
3260 [(set_attr "length" "20")])
3263 ; fix_truncsfsi2 instruction pattern(s).
3266 (define_expand "fix_truncsfsi2"
3267 [(set (match_operand:SI 0 "register_operand" "")
3268 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3271 if (TARGET_IBM_FLOAT)
3273 /* Convert to DFmode and then use the POP algorithm. */
3274 rtx temp = gen_reg_rtx (DFmode);
3275 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3276 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3280 operands[1] = force_reg (SFmode, operands[1]);
3281 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3288 ; float(si|di)(tf|df|sf)2 instruction pattern(s).
3291 ; cxgbr, cdgbr, cegbr
3292 (define_insn "floatdi<mode>2"
3293 [(set (match_operand:BFP 0 "register_operand" "=f")
3294 (float:BFP (match_operand:DI 1 "register_operand" "d")))]
3295 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3297 [(set_attr "op_type" "RRE")
3298 (set_attr "type" "itof" )])
3300 ; cxfbr, cdfbr, cefbr
3301 (define_insn "floatsi<mode>2_ieee"
3302 [(set (match_operand:BFP 0 "register_operand" "=f")
3303 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3304 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3306 [(set_attr "op_type" "RRE")
3307 (set_attr "type" "itof" )])
3311 ; floatsi(tf|df)2 instruction pattern(s).
3314 (define_expand "floatsitf2"
3315 [(set (match_operand:TF 0 "register_operand" "")
3316 (float:TF (match_operand:SI 1 "register_operand" "")))]
3317 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3320 (define_expand "floatsidf2"
3321 [(set (match_operand:DF 0 "register_operand" "")
3322 (float:DF (match_operand:SI 1 "register_operand" "")))]
3325 if (TARGET_IBM_FLOAT)
3327 /* This is the algorithm from POP chapter A.5.7.1. */
3329 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3330 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3332 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3337 (define_insn "floatsidf2_ibm"
3338 [(set (match_operand:DF 0 "register_operand" "=f")
3339 (float:DF (match_operand:SI 1 "register_operand" "d")))
3340 (use (match_operand:DI 2 "immediate_operand" "m"))
3341 (use (match_operand:BLK 3 "memory_operand" "m"))
3342 (clobber (reg:CC CC_REGNUM))]
3343 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3345 output_asm_insn ("st\t%1,%N3", operands);
3346 output_asm_insn ("xi\t%N3,128", operands);
3347 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3348 output_asm_insn ("ld\t%0,%3", operands);
3351 [(set_attr "length" "20")])
3354 ; floatsisf2 instruction pattern(s).
3357 (define_expand "floatsisf2"
3358 [(set (match_operand:SF 0 "register_operand" "")
3359 (float:SF (match_operand:SI 1 "register_operand" "")))]
3362 if (TARGET_IBM_FLOAT)
3364 /* Use the POP algorithm to convert to DFmode and then truncate. */
3365 rtx temp = gen_reg_rtx (DFmode);
3366 emit_insn (gen_floatsidf2 (temp, operands[1]));
3367 emit_insn (gen_truncdfsf2 (operands[0], temp));
3373 ; truncdfsf2 instruction pattern(s).
3376 (define_expand "truncdfsf2"
3377 [(set (match_operand:SF 0 "register_operand" "")
3378 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3382 (define_insn "truncdfsf2_ieee"
3383 [(set (match_operand:SF 0 "register_operand" "=f")
3384 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3385 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3387 [(set_attr "op_type" "RRE")
3388 (set_attr "type" "ftruncdf")])
3390 (define_insn "truncdfsf2_ibm"
3391 [(set (match_operand:SF 0 "register_operand" "=f,f")
3392 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3393 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3397 [(set_attr "op_type" "RR,RX")
3398 (set_attr "type" "floadsf")])
3401 ; trunctfdf2 instruction pattern(s).
3404 (define_expand "trunctfdf2"
3406 [(set (match_operand:DF 0 "register_operand" "")
3407 (float_truncate:DF (match_operand:TF 1 "register_operand" "")))
3408 (clobber (match_scratch:TF 2 "=f"))])]
3412 (define_insn "*trunctfdf2_ieee"
3413 [(set (match_operand:DF 0 "register_operand" "=f")
3414 (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3415 (clobber (match_scratch:TF 2 "=f"))]
3416 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3417 "ldxbr\t%2,%1\;ldr\t%0,%2"
3418 [(set_attr "length" "6")
3419 (set_attr "type" "ftrunctf")])
3421 (define_insn "*trunctfdf2_ibm"
3422 [(set (match_operand:DF 0 "register_operand" "=f")
3423 (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3424 (clobber (match_scratch:TF 2 "=f"))]
3425 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3426 "ldxr\t%2,%1\;ldr\t%0,%2"
3427 [(set_attr "length" "4")
3428 (set_attr "type" "ftrunctf")])
3431 ; trunctfsf2 instruction pattern(s).
3434 (define_expand "trunctfsf2"
3436 [(set (match_operand:SF 0 "register_operand" "=f")
3437 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3438 (clobber (match_scratch:TF 2 "=f"))])]
3442 (define_insn "*trunctfsf2_ieee"
3443 [(set (match_operand:SF 0 "register_operand" "=f")
3444 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3445 (clobber (match_scratch:TF 2 "=f"))]
3446 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3447 "lexbr\t%2,%1\;ler\t%0,%2"
3448 [(set_attr "length" "6")
3449 (set_attr "type" "ftrunctf")])
3451 (define_insn "*trunctfsf2_ibm"
3452 [(set (match_operand:SF 0 "register_operand" "=f")
3453 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3454 (clobber (match_scratch:TF 2 "=f"))]
3455 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3456 "lexr\t%2,%1\;ler\t%0,%2"
3457 [(set_attr "length" "6")
3458 (set_attr "type" "ftrunctf")])
3461 ; extendsfdf2 instruction pattern(s).
3464 (define_expand "extendsfdf2"
3465 [(set (match_operand:DF 0 "register_operand" "")
3466 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3469 if (TARGET_IBM_FLOAT)
3471 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3476 (define_insn "extendsfdf2_ieee"
3477 [(set (match_operand:DF 0 "register_operand" "=f,f")
3478 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3479 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3483 [(set_attr "op_type" "RRE,RXE")
3484 (set_attr "type" "fsimpsf, floadsf")])
3486 (define_insn "extendsfdf2_ibm"
3487 [(set (match_operand:DF 0 "register_operand" "=f,f")
3488 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3489 (clobber (reg:CC CC_REGNUM))]
3490 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3492 sdr\t%0,%0\;ler\t%0,%1
3493 sdr\t%0,%0\;le\t%0,%1"
3494 [(set_attr "length" "4,6")
3495 (set_attr "type" "floadsf")])
3498 ; extenddftf2 instruction pattern(s).
3501 (define_expand "extenddftf2"
3502 [(set (match_operand:TF 0 "register_operand" "")
3503 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
3507 (define_insn "*extenddftf2_ieee"
3508 [(set (match_operand:TF 0 "register_operand" "=f,f")
3509 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3510 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3514 [(set_attr "op_type" "RRE,RXE")
3515 (set_attr "type" "fsimptf, floadtf")])
3517 (define_insn "*extenddftf2_ibm"
3518 [(set (match_operand:TF 0 "register_operand" "=f,f")
3519 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3520 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3524 [(set_attr "op_type" "RRE,RXE")
3525 (set_attr "type" "fsimptf, floadtf")])
3528 ; extendsftf2 instruction pattern(s).
3531 (define_expand "extendsftf2"
3532 [(set (match_operand:TF 0 "register_operand" "")
3533 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
3537 (define_insn "*extendsftf2_ieee"
3538 [(set (match_operand:TF 0 "register_operand" "=f,f")
3539 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3540 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3544 [(set_attr "op_type" "RRE,RXE")
3545 (set_attr "type" "fsimptf, floadtf")])
3547 (define_insn "*extendsftf2_ibm"
3548 [(set (match_operand:TF 0 "register_operand" "=f,f")
3549 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3550 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3554 [(set_attr "op_type" "RRE,RXE")
3555 (set_attr "type" "fsimptf, floadtf")])
3559 ;; ARITHMETIC OPERATIONS
3561 ; arithmetic operations set the ConditionCode,
3562 ; because of unpredictable Bits in Register for Halfword and Byte
3563 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3566 ;;- Add instructions.
3570 ; addti3 instruction pattern(s).
3573 (define_insn_and_split "addti3"
3574 [(set (match_operand:TI 0 "register_operand" "=&d")
3575 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3576 (match_operand:TI 2 "general_operand" "do") ) )
3577 (clobber (reg:CC CC_REGNUM))]
3580 "&& reload_completed"
3582 [(set (reg:CCL1 CC_REGNUM)
3583 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3585 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3587 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3588 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3589 (clobber (reg:CC CC_REGNUM))])]
3590 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3591 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3592 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3593 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3594 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3595 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3598 ; adddi3 instruction pattern(s).
3601 (define_expand "adddi3"
3603 [(set (match_operand:DI 0 "register_operand" "")
3604 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3605 (match_operand:DI 2 "general_operand" "")))
3606 (clobber (reg:CC CC_REGNUM))])]
3610 (define_insn "*adddi3_sign"
3611 [(set (match_operand:DI 0 "register_operand" "=d,d")
3612 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3613 (match_operand:DI 1 "register_operand" "0,0")))
3614 (clobber (reg:CC CC_REGNUM))]
3619 [(set_attr "op_type" "RRE,RXY")])
3621 (define_insn "*adddi3_zero_cc"
3622 [(set (reg CC_REGNUM)
3623 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3624 (match_operand:DI 1 "register_operand" "0,0"))
3626 (set (match_operand:DI 0 "register_operand" "=d,d")
3627 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3628 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3632 [(set_attr "op_type" "RRE,RXY")])
3634 (define_insn "*adddi3_zero_cconly"
3635 [(set (reg CC_REGNUM)
3636 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3637 (match_operand:DI 1 "register_operand" "0,0"))
3639 (clobber (match_scratch:DI 0 "=d,d"))]
3640 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3644 [(set_attr "op_type" "RRE,RXY")])
3646 (define_insn "*adddi3_zero"
3647 [(set (match_operand:DI 0 "register_operand" "=d,d")
3648 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3649 (match_operand:DI 1 "register_operand" "0,0")))
3650 (clobber (reg:CC CC_REGNUM))]
3655 [(set_attr "op_type" "RRE,RXY")])
3657 (define_insn_and_split "*adddi3_31z"
3658 [(set (match_operand:DI 0 "register_operand" "=&d")
3659 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3660 (match_operand:DI 2 "general_operand" "do") ) )
3661 (clobber (reg:CC CC_REGNUM))]
3662 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3664 "&& reload_completed"
3666 [(set (reg:CCL1 CC_REGNUM)
3667 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3669 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3671 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3672 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3673 (clobber (reg:CC CC_REGNUM))])]
3674 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3675 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3676 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3677 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3678 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3679 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3681 (define_insn_and_split "*adddi3_31"
3682 [(set (match_operand:DI 0 "register_operand" "=&d")
3683 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3684 (match_operand:DI 2 "general_operand" "do") ) )
3685 (clobber (reg:CC CC_REGNUM))]
3688 "&& reload_completed"
3690 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3691 (clobber (reg:CC CC_REGNUM))])
3693 [(set (reg:CCL1 CC_REGNUM)
3694 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3696 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3698 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3700 (label_ref (match_dup 9))))
3702 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3703 (clobber (reg:CC CC_REGNUM))])
3705 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3706 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3707 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3708 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3709 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3710 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3711 operands[9] = gen_label_rtx ();")
3714 ; addsi3 instruction pattern(s).
3717 (define_expand "addsi3"
3719 [(set (match_operand:SI 0 "register_operand" "")
3720 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3721 (match_operand:SI 2 "general_operand" "")))
3722 (clobber (reg:CC CC_REGNUM))])]
3726 (define_insn "*addsi3_sign"
3727 [(set (match_operand:SI 0 "register_operand" "=d,d")
3728 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3729 (match_operand:SI 1 "register_operand" "0,0")))
3730 (clobber (reg:CC CC_REGNUM))]
3735 [(set_attr "op_type" "RX,RXY")])
3738 ; add(di|si)3 instruction pattern(s).
3741 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag
3742 (define_insn "*add<mode>3"
3743 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
3744 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
3745 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
3746 (clobber (reg:CC CC_REGNUM))]
3755 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
3757 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3758 (define_insn "*add<mode>3_carry1_cc"
3759 [(set (reg CC_REGNUM)
3760 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3761 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3763 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3764 (plus:GPR (match_dup 1) (match_dup 2)))]
3765 "s390_match_ccmode (insn, CCL1mode)"
3772 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3774 ; alr, al, aly, algr, alg
3775 (define_insn "*add<mode>3_carry1_cconly"
3776 [(set (reg CC_REGNUM)
3777 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3778 (match_operand:GPR 2 "general_operand" "d,R,T"))
3780 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3781 "s390_match_ccmode (insn, CCL1mode)"
3786 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3788 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3789 (define_insn "*add<mode>3_carry2_cc"
3790 [(set (reg CC_REGNUM)
3791 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3792 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3794 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3795 (plus:GPR (match_dup 1) (match_dup 2)))]
3796 "s390_match_ccmode (insn, CCL1mode)"
3803 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3805 ; alr, al, aly, algr, alg
3806 (define_insn "*add<mode>3_carry2_cconly"
3807 [(set (reg CC_REGNUM)
3808 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3809 (match_operand:GPR 2 "general_operand" "d,R,T"))
3811 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3812 "s390_match_ccmode (insn, CCL1mode)"
3817 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3819 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3820 (define_insn "*add<mode>3_cc"
3821 [(set (reg CC_REGNUM)
3822 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3823 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3825 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3826 (plus:GPR (match_dup 1) (match_dup 2)))]
3827 "s390_match_ccmode (insn, CCLmode)"
3834 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3836 ; alr, al, aly, algr, alg
3837 (define_insn "*add<mode>3_cconly"
3838 [(set (reg CC_REGNUM)
3839 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3840 (match_operand:GPR 2 "general_operand" "d,R,T"))
3842 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3843 "s390_match_ccmode (insn, CCLmode)"
3848 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3850 ; alr, al, aly, algr, alg
3851 (define_insn "*add<mode>3_cconly2"
3852 [(set (reg CC_REGNUM)
3853 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3854 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
3855 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3856 "s390_match_ccmode(insn, CCLmode)"
3861 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3863 ; ahi, afi, aghi, agfi
3864 (define_insn "*add<mode>3_imm_cc"
3865 [(set (reg CC_REGNUM)
3866 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3867 (match_operand:GPR 2 "const_int_operand" "K,Os"))
3869 (set (match_operand:GPR 0 "register_operand" "=d,d")
3870 (plus:GPR (match_dup 1) (match_dup 2)))]
3871 "s390_match_ccmode (insn, CCAmode)
3872 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3873 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3874 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
3878 [(set_attr "op_type" "RI,RIL")])
3881 ; add(df|sf)3 instruction pattern(s).
3884 (define_expand "add<mode>3"
3886 [(set (match_operand:BFP 0 "register_operand" "=f,f")
3887 (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
3888 (match_operand:BFP 2 "general_operand" "f,<Rf>")))
3889 (clobber (reg:CC CC_REGNUM))])]
3893 ; axbr, adbr, aebr, axb, adb, aeb
3894 (define_insn "*add<mode>3"
3895 [(set (match_operand:BFP 0 "register_operand" "=f,f")
3896 (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
3897 (match_operand:BFP 2 "general_operand" "f,<Rf>")))
3898 (clobber (reg:CC CC_REGNUM))]
3899 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3903 [(set_attr "op_type" "RRE,RXE")
3904 (set_attr "type" "fsimp<mode>")])
3906 ; axbr, adbr, aebr, axb, adb, aeb
3907 (define_insn "*add<mode>3_cc"
3908 [(set (reg CC_REGNUM)
3909 (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
3910 (match_operand:BFP 2 "general_operand" "f,<Rf>"))
3911 (match_operand:BFP 3 "const0_operand" "")))
3912 (set (match_operand:BFP 0 "register_operand" "=f,f")
3913 (plus:BFP (match_dup 1) (match_dup 2)))]
3914 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3918 [(set_attr "op_type" "RRE,RXE")
3919 (set_attr "type" "fsimp<mode>")])
3921 ; axbr, adbr, aebr, axb, adb, aeb
3922 (define_insn "*add<mode>3_cconly"
3923 [(set (reg CC_REGNUM)
3924 (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
3925 (match_operand:BFP 2 "general_operand" "f,<Rf>"))
3926 (match_operand:BFP 3 "const0_operand" "")))
3927 (clobber (match_scratch:BFP 0 "=f,f"))]
3928 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3932 [(set_attr "op_type" "RRE,RXE")
3933 (set_attr "type" "fsimp<mode>")])
3935 ; axr, adr, aer, ax, ad, ae
3936 (define_insn "*add<mode>3_ibm"
3937 [(set (match_operand:BFP 0 "register_operand" "=f,f")
3938 (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
3939 (match_operand:BFP 2 "general_operand" "f,<Rf>")))
3940 (clobber (reg:CC CC_REGNUM))]
3941 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3945 [(set_attr "op_type" "<RRe>,<RXe>")
3946 (set_attr "type" "fsimp<mode>")])
3950 ;;- Subtract instructions.
3954 ; subti3 instruction pattern(s).
3957 (define_insn_and_split "subti3"
3958 [(set (match_operand:TI 0 "register_operand" "=&d")
3959 (minus:TI (match_operand:TI 1 "register_operand" "0")
3960 (match_operand:TI 2 "general_operand" "do") ) )
3961 (clobber (reg:CC CC_REGNUM))]
3964 "&& reload_completed"
3966 [(set (reg:CCL2 CC_REGNUM)
3967 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3969 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3971 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3972 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3973 (clobber (reg:CC CC_REGNUM))])]
3974 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3975 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3976 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3977 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3978 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3979 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3982 ; subdi3 instruction pattern(s).
3985 (define_expand "subdi3"
3987 [(set (match_operand:DI 0 "register_operand" "")
3988 (minus:DI (match_operand:DI 1 "register_operand" "")
3989 (match_operand:DI 2 "general_operand" "")))
3990 (clobber (reg:CC CC_REGNUM))])]
3994 (define_insn "*subdi3_sign"
3995 [(set (match_operand:DI 0 "register_operand" "=d,d")
3996 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3997 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3998 (clobber (reg:CC CC_REGNUM))]
4003 [(set_attr "op_type" "RRE,RXY")])
4005 (define_insn "*subdi3_zero_cc"
4006 [(set (reg CC_REGNUM)
4007 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4008 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4010 (set (match_operand:DI 0 "register_operand" "=d,d")
4011 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4012 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4016 [(set_attr "op_type" "RRE,RXY")])
4018 (define_insn "*subdi3_zero_cconly"
4019 [(set (reg CC_REGNUM)
4020 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4021 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4023 (clobber (match_scratch:DI 0 "=d,d"))]
4024 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4028 [(set_attr "op_type" "RRE,RXY")])
4030 (define_insn "*subdi3_zero"
4031 [(set (match_operand:DI 0 "register_operand" "=d,d")
4032 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4033 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
4034 (clobber (reg:CC CC_REGNUM))]
4039 [(set_attr "op_type" "RRE,RXY")])
4041 (define_insn_and_split "*subdi3_31z"
4042 [(set (match_operand:DI 0 "register_operand" "=&d")
4043 (minus:DI (match_operand:DI 1 "register_operand" "0")
4044 (match_operand:DI 2 "general_operand" "do") ) )
4045 (clobber (reg:CC CC_REGNUM))]
4046 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4048 "&& reload_completed"
4050 [(set (reg:CCL2 CC_REGNUM)
4051 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4053 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4055 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4056 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4057 (clobber (reg:CC CC_REGNUM))])]
4058 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4059 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4060 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4061 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4062 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4063 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4065 (define_insn_and_split "*subdi3_31"
4066 [(set (match_operand:DI 0 "register_operand" "=&d")
4067 (minus:DI (match_operand:DI 1 "register_operand" "0")
4068 (match_operand:DI 2 "general_operand" "do") ) )
4069 (clobber (reg:CC CC_REGNUM))]
4072 "&& reload_completed"
4074 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4075 (clobber (reg:CC CC_REGNUM))])
4077 [(set (reg:CCL2 CC_REGNUM)
4078 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4080 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4082 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4084 (label_ref (match_dup 9))))
4086 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4087 (clobber (reg:CC CC_REGNUM))])
4089 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4090 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4091 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4092 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4093 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4094 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4095 operands[9] = gen_label_rtx ();")
4098 ; subsi3 instruction pattern(s).
4101 (define_expand "subsi3"
4103 [(set (match_operand:SI 0 "register_operand" "")
4104 (minus:SI (match_operand:SI 1 "register_operand" "")
4105 (match_operand:SI 2 "general_operand" "")))
4106 (clobber (reg:CC CC_REGNUM))])]
4110 (define_insn "*subsi3_sign"
4111 [(set (match_operand:SI 0 "register_operand" "=d,d")
4112 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4113 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4114 (clobber (reg:CC CC_REGNUM))]
4119 [(set_attr "op_type" "RX,RXY")])
4122 ; sub(di|si)3 instruction pattern(s).
4125 ; sr, s, sy, sgr, sg
4126 (define_insn "*sub<mode>3"
4127 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4128 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4129 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4130 (clobber (reg:CC CC_REGNUM))]
4136 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4138 ; slr, sl, sly, slgr, slg
4139 (define_insn "*sub<mode>3_borrow_cc"
4140 [(set (reg CC_REGNUM)
4141 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4142 (match_operand:GPR 2 "general_operand" "d,R,T"))
4144 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4145 (minus:GPR (match_dup 1) (match_dup 2)))]
4146 "s390_match_ccmode (insn, CCL2mode)"
4151 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4153 ; slr, sl, sly, slgr, slg
4154 (define_insn "*sub<mode>3_borrow_cconly"
4155 [(set (reg CC_REGNUM)
4156 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4157 (match_operand:GPR 2 "general_operand" "d,R,T"))
4159 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4160 "s390_match_ccmode (insn, CCL2mode)"
4165 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4167 ; slr, sl, sly, slgr, slg
4168 (define_insn "*sub<mode>3_cc"
4169 [(set (reg CC_REGNUM)
4170 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4171 (match_operand:GPR 2 "general_operand" "d,R,T"))
4173 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4174 (minus:GPR (match_dup 1) (match_dup 2)))]
4175 "s390_match_ccmode (insn, CCLmode)"
4180 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4182 ; slr, sl, sly, slgr, slg
4183 (define_insn "*sub<mode>3_cc2"
4184 [(set (reg CC_REGNUM)
4185 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4186 (match_operand:GPR 2 "general_operand" "d,R,T")))
4187 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4188 (minus:GPR (match_dup 1) (match_dup 2)))]
4189 "s390_match_ccmode (insn, CCL3mode)"
4194 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4196 ; slr, sl, sly, slgr, slg
4197 (define_insn "*sub<mode>3_cconly"
4198 [(set (reg CC_REGNUM)
4199 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4200 (match_operand:GPR 2 "general_operand" "d,R,T"))
4202 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4203 "s390_match_ccmode (insn, CCLmode)"
4208 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4210 ; slr, sl, sly, slgr, slg
4211 (define_insn "*sub<mode>3_cconly2"
4212 [(set (reg CC_REGNUM)
4213 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4214 (match_operand:GPR 2 "general_operand" "d,R,T")))
4215 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4216 "s390_match_ccmode (insn, CCL3mode)"
4221 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4224 ; sub(df|sf)3 instruction pattern(s).
4227 (define_expand "sub<mode>3"
4229 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4230 (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
4231 (match_operand:BFP 2 "general_operand" "f,R")))
4232 (clobber (reg:CC CC_REGNUM))])]
4236 ; sxbr, sdbr, sebr, sxb, sdb, seb
4237 (define_insn "*sub<mode>3"
4238 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4239 (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
4240 (match_operand:BFP 2 "general_operand" "f,<Rf>")))
4241 (clobber (reg:CC CC_REGNUM))]
4242 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4246 [(set_attr "op_type" "RRE,RXE")
4247 (set_attr "type" "fsimp<mode>")])
4249 ; sxbr, sdbr, sebr, sxb, sdb, seb
4250 (define_insn "*sub<mode>3_cc"
4251 [(set (reg CC_REGNUM)
4252 (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0")
4253 (match_operand:BFP 2 "general_operand" "f,<Rf>"))
4254 (match_operand:BFP 3 "const0_operand" "")))
4255 (set (match_operand:BFP 0 "register_operand" "=f,f")
4256 (minus:BFP (match_dup 1) (match_dup 2)))]
4257 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4261 [(set_attr "op_type" "RRE,RXE")
4262 (set_attr "type" "fsimp<mode>")])
4264 ; sxbr, sdbr, sebr, sxb, sdb, seb
4265 (define_insn "*sub<mode>3_cconly"
4266 [(set (reg CC_REGNUM)
4267 (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0")
4268 (match_operand:BFP 2 "general_operand" "f,<Rf>"))
4269 (match_operand:BFP 3 "const0_operand" "")))
4270 (clobber (match_scratch:BFP 0 "=f,f"))]
4271 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4275 [(set_attr "op_type" "RRE,RXE")
4276 (set_attr "type" "fsimp<mode>")])
4278 ; sxr, sdr, ser, sx, sd, se
4279 (define_insn "*sub<mode>3_ibm"
4280 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4281 (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
4282 (match_operand:BFP 2 "general_operand" "f,<Rf>")))
4283 (clobber (reg:CC CC_REGNUM))]
4284 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4288 [(set_attr "op_type" "<RRe>,<RXe>")
4289 (set_attr "type" "fsimp<mode>")])
4293 ;;- Conditional add/subtract instructions.
4297 ; add(di|si)cc instruction pattern(s).
4300 ; alcr, alc, alcgr, alcg
4301 (define_insn "*add<mode>3_alc_cc"
4302 [(set (reg CC_REGNUM)
4304 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4305 (match_operand:GPR 2 "general_operand" "d,m"))
4306 (match_operand:GPR 3 "s390_alc_comparison" ""))
4308 (set (match_operand:GPR 0 "register_operand" "=d,d")
4309 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4310 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4314 [(set_attr "op_type" "RRE,RXY")])
4316 ; alcr, alc, alcgr, alcg
4317 (define_insn "*add<mode>3_alc"
4318 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4319 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4320 (match_operand:GPR 2 "general_operand" "d,m"))
4321 (match_operand:GPR 3 "s390_alc_comparison" "")))
4322 (clobber (reg:CC CC_REGNUM))]
4327 [(set_attr "op_type" "RRE,RXY")])
4329 ; slbr, slb, slbgr, slbg
4330 (define_insn "*sub<mode>3_slb_cc"
4331 [(set (reg CC_REGNUM)
4333 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4334 (match_operand:GPR 2 "general_operand" "d,m"))
4335 (match_operand:GPR 3 "s390_slb_comparison" ""))
4337 (set (match_operand:GPR 0 "register_operand" "=d,d")
4338 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4339 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4343 [(set_attr "op_type" "RRE,RXY")])
4345 ; slbr, slb, slbgr, slbg
4346 (define_insn "*sub<mode>3_slb"
4347 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4348 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4349 (match_operand:GPR 2 "general_operand" "d,m"))
4350 (match_operand:GPR 3 "s390_slb_comparison" "")))
4351 (clobber (reg:CC CC_REGNUM))]
4356 [(set_attr "op_type" "RRE,RXY")])
4358 (define_expand "add<mode>cc"
4359 [(match_operand:GPR 0 "register_operand" "")
4360 (match_operand 1 "comparison_operator" "")
4361 (match_operand:GPR 2 "register_operand" "")
4362 (match_operand:GPR 3 "const_int_operand" "")]
4364 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4365 s390_compare_op0, s390_compare_op1,
4366 operands[0], operands[2],
4367 operands[3])) FAIL; DONE;")
4370 ; scond instruction pattern(s).
4373 (define_insn_and_split "*scond<mode>"
4374 [(set (match_operand:GPR 0 "register_operand" "=&d")
4375 (match_operand:GPR 1 "s390_alc_comparison" ""))
4376 (clobber (reg:CC CC_REGNUM))]
4379 "&& reload_completed"
4380 [(set (match_dup 0) (const_int 0))
4382 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4384 (clobber (reg:CC CC_REGNUM))])]
4387 (define_insn_and_split "*scond<mode>_neg"
4388 [(set (match_operand:GPR 0 "register_operand" "=&d")
4389 (match_operand:GPR 1 "s390_slb_comparison" ""))
4390 (clobber (reg:CC CC_REGNUM))]
4393 "&& reload_completed"
4394 [(set (match_dup 0) (const_int 0))
4396 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4398 (clobber (reg:CC CC_REGNUM))])
4400 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4401 (clobber (reg:CC CC_REGNUM))])]
4405 (define_expand "s<code>"
4406 [(set (match_operand:SI 0 "register_operand" "")
4407 (SCOND (match_dup 0)
4410 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4411 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4413 (define_expand "seq"
4415 [(set (match_operand:SI 0 "register_operand" "=d")
4417 (clobber (reg:CC CC_REGNUM))])
4419 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4420 (clobber (reg:CC CC_REGNUM))])]
4423 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4425 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4426 PUT_MODE (operands[1], SImode);
4429 (define_insn_and_split "*sne"
4430 [(set (match_operand:SI 0 "register_operand" "=d")
4431 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4433 (clobber (reg:CC CC_REGNUM))]
4438 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4439 (clobber (reg:CC CC_REGNUM))])])
4443 ;;- Multiply instructions.
4447 ; muldi3 instruction pattern(s).
4450 (define_insn "*muldi3_sign"
4451 [(set (match_operand:DI 0 "register_operand" "=d,d")
4452 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4453 (match_operand:DI 1 "register_operand" "0,0")))]
4458 [(set_attr "op_type" "RRE,RXY")
4459 (set_attr "type" "imuldi")])
4461 (define_insn "muldi3"
4462 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4463 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4464 (match_operand:DI 2 "general_operand" "d,K,m")))]
4470 [(set_attr "op_type" "RRE,RI,RXY")
4471 (set_attr "type" "imuldi")])
4474 ; mulsi3 instruction pattern(s).
4477 (define_insn "*mulsi3_sign"
4478 [(set (match_operand:SI 0 "register_operand" "=d")
4479 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4480 (match_operand:SI 1 "register_operand" "0")))]
4483 [(set_attr "op_type" "RX")
4484 (set_attr "type" "imulhi")])
4486 (define_insn "mulsi3"
4487 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4488 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4489 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4496 [(set_attr "op_type" "RRE,RI,RX,RXY")
4497 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4500 ; mulsidi3 instruction pattern(s).
4503 (define_insn "mulsidi3"
4504 [(set (match_operand:DI 0 "register_operand" "=d,d")
4505 (mult:DI (sign_extend:DI
4506 (match_operand:SI 1 "register_operand" "%0,0"))
4508 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4513 [(set_attr "op_type" "RR,RX")
4514 (set_attr "type" "imulsi")])
4517 ; umulsidi3 instruction pattern(s).
4520 (define_insn "umulsidi3"
4521 [(set (match_operand:DI 0 "register_operand" "=d,d")
4522 (mult:DI (zero_extend:DI
4523 (match_operand:SI 1 "register_operand" "%0,0"))
4525 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4526 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4530 [(set_attr "op_type" "RRE,RXY")
4531 (set_attr "type" "imulsi")])
4534 ; mul(df|sf)3 instruction pattern(s).
4537 (define_expand "mul<mode>3"
4538 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4539 (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
4540 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
4544 ; mxbr mdbr, meebr, mxb, mxb, meeb
4545 (define_insn "*mul<mode>3"
4546 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4547 (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
4548 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
4549 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4553 [(set_attr "op_type" "RRE,RXE")
4554 (set_attr "type" "fmul<mode>")])
4556 ; mxr, mdr, mer, mx, md, me
4557 (define_insn "*mul<mode>3_ibm"
4558 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4559 (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
4560 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
4561 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4565 [(set_attr "op_type" "<RRe>,<RXe>")
4566 (set_attr "type" "fmul<mode>")])
4568 ; maxbr, madbr, maebr, maxb, madb, maeb
4569 (define_insn "*fmadd<mode>"
4570 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4571 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
4572 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4573 (match_operand:DSF 3 "register_operand" "0,0")))]
4574 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4578 [(set_attr "op_type" "RRE,RXE")
4579 (set_attr "type" "fmul<mode>")])
4581 ; msxbr, msdbr, msebr, msxb, msdb, mseb
4582 (define_insn "*fmsub<mode>"
4583 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4584 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
4585 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4586 (match_operand:DSF 3 "register_operand" "0,0")))]
4587 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4591 [(set_attr "op_type" "RRE,RXE")
4592 (set_attr "type" "fmul<mode>")])
4595 ;;- Divide and modulo instructions.
4599 ; divmoddi4 instruction pattern(s).
4602 (define_expand "divmoddi4"
4603 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4604 (div:DI (match_operand:DI 1 "register_operand" "")
4605 (match_operand:DI 2 "general_operand" "")))
4606 (set (match_operand:DI 3 "general_operand" "")
4607 (mod:DI (match_dup 1) (match_dup 2)))])
4608 (clobber (match_dup 4))]
4611 rtx insn, div_equal, mod_equal;
4613 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4614 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4616 operands[4] = gen_reg_rtx(TImode);
4617 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4619 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4620 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4622 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4623 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4628 (define_insn "divmodtidi3"
4629 [(set (match_operand:TI 0 "register_operand" "=d,d")
4633 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4634 (match_operand:DI 2 "general_operand" "d,m")))
4636 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4641 [(set_attr "op_type" "RRE,RXY")
4642 (set_attr "type" "idiv")])
4644 (define_insn "divmodtisi3"
4645 [(set (match_operand:TI 0 "register_operand" "=d,d")
4649 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4651 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4654 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4659 [(set_attr "op_type" "RRE,RXY")
4660 (set_attr "type" "idiv")])
4663 ; udivmoddi4 instruction pattern(s).
4666 (define_expand "udivmoddi4"
4667 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4668 (udiv:DI (match_operand:DI 1 "general_operand" "")
4669 (match_operand:DI 2 "nonimmediate_operand" "")))
4670 (set (match_operand:DI 3 "general_operand" "")
4671 (umod:DI (match_dup 1) (match_dup 2)))])
4672 (clobber (match_dup 4))]
4675 rtx insn, div_equal, mod_equal, equal;
4677 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4678 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4679 equal = gen_rtx_IOR (TImode,
4680 gen_rtx_ASHIFT (TImode,
4681 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4683 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4685 operands[4] = gen_reg_rtx(TImode);
4686 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4687 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4688 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4690 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4691 set_unique_reg_note (insn, REG_EQUAL, equal);
4693 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4694 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4696 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4697 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4702 (define_insn "udivmodtidi3"
4703 [(set (match_operand:TI 0 "register_operand" "=d,d")
4708 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4710 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4714 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4719 [(set_attr "op_type" "RRE,RXY")
4720 (set_attr "type" "idiv")])
4723 ; divmodsi4 instruction pattern(s).
4726 (define_expand "divmodsi4"
4727 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4728 (div:SI (match_operand:SI 1 "general_operand" "")
4729 (match_operand:SI 2 "nonimmediate_operand" "")))
4730 (set (match_operand:SI 3 "general_operand" "")
4731 (mod:SI (match_dup 1) (match_dup 2)))])
4732 (clobber (match_dup 4))]
4735 rtx insn, div_equal, mod_equal, equal;
4737 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4738 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4739 equal = gen_rtx_IOR (DImode,
4740 gen_rtx_ASHIFT (DImode,
4741 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4743 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4745 operands[4] = gen_reg_rtx(DImode);
4746 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4748 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4749 set_unique_reg_note (insn, REG_EQUAL, equal);
4751 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4752 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4754 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4755 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4760 (define_insn "divmoddisi3"
4761 [(set (match_operand:DI 0 "register_operand" "=d,d")
4766 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4768 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4772 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4777 [(set_attr "op_type" "RR,RX")
4778 (set_attr "type" "idiv")])
4781 ; udivsi3 and umodsi3 instruction pattern(s).
4784 (define_expand "udivmodsi4"
4785 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4786 (udiv:SI (match_operand:SI 1 "general_operand" "")
4787 (match_operand:SI 2 "nonimmediate_operand" "")))
4788 (set (match_operand:SI 3 "general_operand" "")
4789 (umod:SI (match_dup 1) (match_dup 2)))])
4790 (clobber (match_dup 4))]
4791 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4793 rtx insn, div_equal, mod_equal, equal;
4795 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4796 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4797 equal = gen_rtx_IOR (DImode,
4798 gen_rtx_ASHIFT (DImode,
4799 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4801 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4803 operands[4] = gen_reg_rtx(DImode);
4804 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4805 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4806 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4808 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4809 set_unique_reg_note (insn, REG_EQUAL, equal);
4811 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4812 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4814 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4815 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4820 (define_insn "udivmoddisi3"
4821 [(set (match_operand:DI 0 "register_operand" "=d,d")
4826 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4828 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4832 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4833 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4837 [(set_attr "op_type" "RRE,RXY")
4838 (set_attr "type" "idiv")])
4840 (define_expand "udivsi3"
4841 [(set (match_operand:SI 0 "register_operand" "=d")
4842 (udiv:SI (match_operand:SI 1 "general_operand" "")
4843 (match_operand:SI 2 "general_operand" "")))
4844 (clobber (match_dup 3))]
4845 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4847 rtx insn, udiv_equal, umod_equal, equal;
4849 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4850 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4851 equal = gen_rtx_IOR (DImode,
4852 gen_rtx_ASHIFT (DImode,
4853 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4855 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4857 operands[3] = gen_reg_rtx (DImode);
4859 if (CONSTANT_P (operands[2]))
4861 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4863 rtx label1 = gen_label_rtx ();
4865 operands[1] = make_safe_from (operands[1], operands[0]);
4866 emit_move_insn (operands[0], const0_rtx);
4867 emit_insn (gen_cmpsi (operands[1], operands[2]));
4868 emit_jump_insn (gen_bltu (label1));
4869 emit_move_insn (operands[0], const1_rtx);
4870 emit_label (label1);
4874 operands[2] = force_reg (SImode, operands[2]);
4875 operands[2] = make_safe_from (operands[2], operands[0]);
4877 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4878 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4880 set_unique_reg_note (insn, REG_EQUAL, equal);
4882 insn = emit_move_insn (operands[0],
4883 gen_lowpart (SImode, operands[3]));
4884 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
4889 rtx label1 = gen_label_rtx ();
4890 rtx label2 = gen_label_rtx ();
4891 rtx label3 = gen_label_rtx ();
4893 operands[1] = force_reg (SImode, operands[1]);
4894 operands[1] = make_safe_from (operands[1], operands[0]);
4895 operands[2] = force_reg (SImode, operands[2]);
4896 operands[2] = make_safe_from (operands[2], operands[0]);
4898 emit_move_insn (operands[0], const0_rtx);
4899 emit_insn (gen_cmpsi (operands[2], operands[1]));
4900 emit_jump_insn (gen_bgtu (label3));
4901 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4902 emit_jump_insn (gen_blt (label2));
4903 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4904 emit_jump_insn (gen_beq (label1));
4905 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4906 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4908 set_unique_reg_note (insn, REG_EQUAL, equal);
4910 insn = emit_move_insn (operands[0],
4911 gen_lowpart (SImode, operands[3]));
4912 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
4915 emit_label (label1);
4916 emit_move_insn (operands[0], operands[1]);
4918 emit_label (label2);
4919 emit_move_insn (operands[0], const1_rtx);
4920 emit_label (label3);
4922 emit_move_insn (operands[0], operands[0]);
4926 (define_expand "umodsi3"
4927 [(set (match_operand:SI 0 "register_operand" "=d")
4928 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4929 (match_operand:SI 2 "nonimmediate_operand" "")))
4930 (clobber (match_dup 3))]
4931 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4933 rtx insn, udiv_equal, umod_equal, equal;
4935 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4936 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4937 equal = gen_rtx_IOR (DImode,
4938 gen_rtx_ASHIFT (DImode,
4939 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4941 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4943 operands[3] = gen_reg_rtx (DImode);
4945 if (CONSTANT_P (operands[2]))
4947 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4949 rtx label1 = gen_label_rtx ();
4951 operands[1] = make_safe_from (operands[1], operands[0]);
4952 emit_move_insn (operands[0], operands[1]);
4953 emit_insn (gen_cmpsi (operands[0], operands[2]));
4954 emit_jump_insn (gen_bltu (label1));
4955 emit_insn (gen_abssi2 (operands[0], operands[2]));
4956 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4957 emit_label (label1);
4961 operands[2] = force_reg (SImode, operands[2]);
4962 operands[2] = make_safe_from (operands[2], operands[0]);
4964 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4965 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4967 set_unique_reg_note (insn, REG_EQUAL, equal);
4969 insn = emit_move_insn (operands[0],
4970 gen_highpart (SImode, operands[3]));
4971 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
4976 rtx label1 = gen_label_rtx ();
4977 rtx label2 = gen_label_rtx ();
4978 rtx label3 = gen_label_rtx ();
4980 operands[1] = force_reg (SImode, operands[1]);
4981 operands[1] = make_safe_from (operands[1], operands[0]);
4982 operands[2] = force_reg (SImode, operands[2]);
4983 operands[2] = make_safe_from (operands[2], operands[0]);
4985 emit_move_insn(operands[0], operands[1]);
4986 emit_insn (gen_cmpsi (operands[2], operands[1]));
4987 emit_jump_insn (gen_bgtu (label3));
4988 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4989 emit_jump_insn (gen_blt (label2));
4990 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4991 emit_jump_insn (gen_beq (label1));
4992 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4993 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4995 set_unique_reg_note (insn, REG_EQUAL, equal);
4997 insn = emit_move_insn (operands[0],
4998 gen_highpart (SImode, operands[3]));
4999 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5002 emit_label (label1);
5003 emit_move_insn (operands[0], const0_rtx);
5005 emit_label (label2);
5006 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5007 emit_label (label3);
5013 ; div(df|sf)3 instruction pattern(s).
5016 (define_expand "div<mode>3"
5017 [(set (match_operand:BFP 0 "register_operand" "=f,f")
5018 (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
5019 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
5023 ; dxbr, ddbr, debr, dxb, ddb, deb
5024 (define_insn "*div<mode>3"
5025 [(set (match_operand:BFP 0 "register_operand" "=f,f")
5026 (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
5027 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
5028 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5032 [(set_attr "op_type" "RRE,RXE")
5033 (set_attr "type" "fdiv<mode>")])
5035 ; dxr, ddr, der, dx, dd, de
5036 (define_insn "*div<mode>3_ibm"
5037 [(set (match_operand:BFP 0 "register_operand" "=f,f")
5038 (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
5039 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
5040 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5044 [(set_attr "op_type" "<RRe>,<RXe>")
5045 (set_attr "type" "fdiv<mode>")])
5049 ;;- And instructions.
5052 (define_expand "and<mode>3"
5053 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5054 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5055 (match_operand:INT 2 "general_operand" "")))
5056 (clobber (reg:CC CC_REGNUM))]
5058 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5061 ; anddi3 instruction pattern(s).
5064 (define_insn "*anddi3_cc"
5065 [(set (reg CC_REGNUM)
5066 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5067 (match_operand:DI 2 "general_operand" "d,m"))
5069 (set (match_operand:DI 0 "register_operand" "=d,d")
5070 (and:DI (match_dup 1) (match_dup 2)))]
5071 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5075 [(set_attr "op_type" "RRE,RXY")])
5077 (define_insn "*anddi3_cconly"
5078 [(set (reg CC_REGNUM)
5079 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5080 (match_operand:DI 2 "general_operand" "d,m"))
5082 (clobber (match_scratch:DI 0 "=d,d"))]
5083 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5084 /* Do not steal TM patterns. */
5085 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5089 [(set_attr "op_type" "RRE,RXY")])
5091 (define_insn "*anddi3_extimm"
5092 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5093 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5094 "%d,o,0,0,0,0,0,0,0,0,0,0")
5095 (match_operand:DI 2 "general_operand"
5096 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5097 (clobber (reg:CC CC_REGNUM))]
5098 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5112 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5114 (define_insn "*anddi3"
5115 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5116 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5117 "%d,o,0,0,0,0,0,0,0,0")
5118 (match_operand:DI 2 "general_operand"
5119 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5120 (clobber (reg:CC CC_REGNUM))]
5121 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5133 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5136 [(set (match_operand:DI 0 "s_operand" "")
5137 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5138 (clobber (reg:CC CC_REGNUM))]
5141 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5142 (clobber (reg:CC CC_REGNUM))])]
5143 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5147 ; andsi3 instruction pattern(s).
5150 (define_insn "*andsi3_cc"
5151 [(set (reg CC_REGNUM)
5152 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5153 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5155 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5156 (and:SI (match_dup 1) (match_dup 2)))]
5157 "s390_match_ccmode(insn, CCTmode)"
5163 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5165 (define_insn "*andsi3_cconly"
5166 [(set (reg CC_REGNUM)
5167 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5168 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5170 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5171 "s390_match_ccmode(insn, CCTmode)
5172 /* Do not steal TM patterns. */
5173 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5179 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5181 (define_insn "*andsi3_zarch"
5182 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5183 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5184 "%d,o,0,0,0,0,0,0,0,0")
5185 (match_operand:SI 2 "general_operand"
5186 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5187 (clobber (reg:CC CC_REGNUM))]
5188 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5200 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5202 (define_insn "*andsi3_esa"
5203 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5204 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5205 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5206 (clobber (reg:CC CC_REGNUM))]
5207 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5213 [(set_attr "op_type" "RR,RX,SI,SS")])
5216 [(set (match_operand:SI 0 "s_operand" "")
5217 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5218 (clobber (reg:CC CC_REGNUM))]
5221 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5222 (clobber (reg:CC CC_REGNUM))])]
5223 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5226 ; andhi3 instruction pattern(s).
5229 (define_insn "*andhi3_zarch"
5230 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5231 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5232 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5233 (clobber (reg:CC CC_REGNUM))]
5234 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5240 [(set_attr "op_type" "RR,RI,SI,SS")])
5242 (define_insn "*andhi3_esa"
5243 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5244 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5245 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5246 (clobber (reg:CC CC_REGNUM))]
5247 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5252 [(set_attr "op_type" "RR,SI,SS")])
5255 [(set (match_operand:HI 0 "s_operand" "")
5256 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5257 (clobber (reg:CC CC_REGNUM))]
5260 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5261 (clobber (reg:CC CC_REGNUM))])]
5262 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5265 ; andqi3 instruction pattern(s).
5268 (define_insn "*andqi3_zarch"
5269 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5270 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5271 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5272 (clobber (reg:CC CC_REGNUM))]
5273 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5280 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5282 (define_insn "*andqi3_esa"
5283 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5284 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5285 (match_operand:QI 2 "general_operand" "d,n,Q")))
5286 (clobber (reg:CC CC_REGNUM))]
5287 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5292 [(set_attr "op_type" "RR,SI,SS")])
5295 ; Block and (NC) patterns.
5299 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5300 (and:BLK (match_dup 0)
5301 (match_operand:BLK 1 "memory_operand" "Q")))
5302 (use (match_operand 2 "const_int_operand" "n"))
5303 (clobber (reg:CC CC_REGNUM))]
5304 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5305 "nc\t%O0(%2,%R0),%S1"
5306 [(set_attr "op_type" "SS")])
5309 [(set (match_operand 0 "memory_operand" "")
5311 (match_operand 1 "memory_operand" "")))
5312 (clobber (reg:CC CC_REGNUM))]
5314 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5315 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5317 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5319 (clobber (reg:CC CC_REGNUM))])]
5321 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5322 operands[0] = adjust_address (operands[0], BLKmode, 0);
5323 operands[1] = adjust_address (operands[1], BLKmode, 0);
5328 [(set (match_operand:BLK 0 "memory_operand" "")
5329 (and:BLK (match_dup 0)
5330 (match_operand:BLK 1 "memory_operand" "")))
5331 (use (match_operand 2 "const_int_operand" ""))
5332 (clobber (reg:CC CC_REGNUM))])
5334 [(set (match_operand:BLK 3 "memory_operand" "")
5335 (and:BLK (match_dup 3)
5336 (match_operand:BLK 4 "memory_operand" "")))
5337 (use (match_operand 5 "const_int_operand" ""))
5338 (clobber (reg:CC CC_REGNUM))])]
5339 "s390_offset_p (operands[0], operands[3], operands[2])
5340 && s390_offset_p (operands[1], operands[4], operands[2])
5341 && !s390_overlap_p (operands[0], operands[1],
5342 INTVAL (operands[2]) + INTVAL (operands[5]))
5343 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5345 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5347 (clobber (reg:CC CC_REGNUM))])]
5348 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5349 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5350 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5354 ;;- Bit set (inclusive or) instructions.
5357 (define_expand "ior<mode>3"
5358 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5359 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5360 (match_operand:INT 2 "general_operand" "")))
5361 (clobber (reg:CC CC_REGNUM))]
5363 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5366 ; iordi3 instruction pattern(s).
5369 (define_insn "*iordi3_cc"
5370 [(set (reg CC_REGNUM)
5371 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5372 (match_operand:DI 2 "general_operand" "d,m"))
5374 (set (match_operand:DI 0 "register_operand" "=d,d")
5375 (ior:DI (match_dup 1) (match_dup 2)))]
5376 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5380 [(set_attr "op_type" "RRE,RXY")])
5382 (define_insn "*iordi3_cconly"
5383 [(set (reg CC_REGNUM)
5384 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5385 (match_operand:DI 2 "general_operand" "d,m"))
5387 (clobber (match_scratch:DI 0 "=d,d"))]
5388 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5392 [(set_attr "op_type" "RRE,RXY")])
5394 (define_insn "*iordi3_extimm"
5395 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5396 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5397 (match_operand:DI 2 "general_operand"
5398 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5399 (clobber (reg:CC CC_REGNUM))]
5400 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5412 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5414 (define_insn "*iordi3"
5415 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5416 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5417 (match_operand:DI 2 "general_operand"
5418 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5419 (clobber (reg:CC CC_REGNUM))]
5420 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5430 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5433 [(set (match_operand:DI 0 "s_operand" "")
5434 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5435 (clobber (reg:CC CC_REGNUM))]
5438 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5439 (clobber (reg:CC CC_REGNUM))])]
5440 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5443 ; iorsi3 instruction pattern(s).
5446 (define_insn "*iorsi3_cc"
5447 [(set (reg CC_REGNUM)
5448 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5449 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5451 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5452 (ior:SI (match_dup 1) (match_dup 2)))]
5453 "s390_match_ccmode(insn, CCTmode)"
5459 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5461 (define_insn "*iorsi3_cconly"
5462 [(set (reg CC_REGNUM)
5463 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5464 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5466 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5467 "s390_match_ccmode(insn, CCTmode)"
5473 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5475 (define_insn "*iorsi3_zarch"
5476 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5477 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5478 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5479 (clobber (reg:CC CC_REGNUM))]
5480 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5490 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5492 (define_insn "*iorsi3_esa"
5493 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5494 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5495 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5496 (clobber (reg:CC CC_REGNUM))]
5497 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5503 [(set_attr "op_type" "RR,RX,SI,SS")])
5506 [(set (match_operand:SI 0 "s_operand" "")
5507 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5508 (clobber (reg:CC CC_REGNUM))]
5511 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5512 (clobber (reg:CC CC_REGNUM))])]
5513 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5516 ; iorhi3 instruction pattern(s).
5519 (define_insn "*iorhi3_zarch"
5520 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5521 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5522 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5523 (clobber (reg:CC CC_REGNUM))]
5524 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5530 [(set_attr "op_type" "RR,RI,SI,SS")])
5532 (define_insn "*iorhi3_esa"
5533 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5534 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5535 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5536 (clobber (reg:CC CC_REGNUM))]
5537 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5542 [(set_attr "op_type" "RR,SI,SS")])
5545 [(set (match_operand:HI 0 "s_operand" "")
5546 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5547 (clobber (reg:CC CC_REGNUM))]
5550 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5551 (clobber (reg:CC CC_REGNUM))])]
5552 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5555 ; iorqi3 instruction pattern(s).
5558 (define_insn "*iorqi3_zarch"
5559 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5560 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5561 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5562 (clobber (reg:CC CC_REGNUM))]
5563 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5570 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5572 (define_insn "*iorqi3_esa"
5573 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5574 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5575 (match_operand:QI 2 "general_operand" "d,n,Q")))
5576 (clobber (reg:CC CC_REGNUM))]
5577 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5582 [(set_attr "op_type" "RR,SI,SS")])
5585 ; Block inclusive or (OC) patterns.
5589 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5590 (ior:BLK (match_dup 0)
5591 (match_operand:BLK 1 "memory_operand" "Q")))
5592 (use (match_operand 2 "const_int_operand" "n"))
5593 (clobber (reg:CC CC_REGNUM))]
5594 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5595 "oc\t%O0(%2,%R0),%S1"
5596 [(set_attr "op_type" "SS")])
5599 [(set (match_operand 0 "memory_operand" "")
5601 (match_operand 1 "memory_operand" "")))
5602 (clobber (reg:CC CC_REGNUM))]
5604 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5605 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5607 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5609 (clobber (reg:CC CC_REGNUM))])]
5611 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5612 operands[0] = adjust_address (operands[0], BLKmode, 0);
5613 operands[1] = adjust_address (operands[1], BLKmode, 0);
5618 [(set (match_operand:BLK 0 "memory_operand" "")
5619 (ior:BLK (match_dup 0)
5620 (match_operand:BLK 1 "memory_operand" "")))
5621 (use (match_operand 2 "const_int_operand" ""))
5622 (clobber (reg:CC CC_REGNUM))])
5624 [(set (match_operand:BLK 3 "memory_operand" "")
5625 (ior:BLK (match_dup 3)
5626 (match_operand:BLK 4 "memory_operand" "")))
5627 (use (match_operand 5 "const_int_operand" ""))
5628 (clobber (reg:CC CC_REGNUM))])]
5629 "s390_offset_p (operands[0], operands[3], operands[2])
5630 && s390_offset_p (operands[1], operands[4], operands[2])
5631 && !s390_overlap_p (operands[0], operands[1],
5632 INTVAL (operands[2]) + INTVAL (operands[5]))
5633 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5635 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5637 (clobber (reg:CC CC_REGNUM))])]
5638 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5639 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5640 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5644 ;;- Xor instructions.
5647 (define_expand "xor<mode>3"
5648 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5649 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5650 (match_operand:INT 2 "general_operand" "")))
5651 (clobber (reg:CC CC_REGNUM))]
5653 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5656 ; xordi3 instruction pattern(s).
5659 (define_insn "*xordi3_cc"
5660 [(set (reg CC_REGNUM)
5661 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5662 (match_operand:DI 2 "general_operand" "d,m"))
5664 (set (match_operand:DI 0 "register_operand" "=d,d")
5665 (xor:DI (match_dup 1) (match_dup 2)))]
5666 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5670 [(set_attr "op_type" "RRE,RXY")])
5672 (define_insn "*xordi3_cconly"
5673 [(set (reg CC_REGNUM)
5674 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5675 (match_operand:DI 2 "general_operand" "d,m"))
5677 (clobber (match_scratch:DI 0 "=d,d"))]
5678 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5682 [(set_attr "op_type" "RRE,RXY")])
5684 (define_insn "*xordi3_extimm"
5685 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5686 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5687 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5688 (clobber (reg:CC CC_REGNUM))]
5689 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5697 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5699 (define_insn "*xordi3"
5700 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5701 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5702 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5703 (clobber (reg:CC CC_REGNUM))]
5704 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5710 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5713 [(set (match_operand:DI 0 "s_operand" "")
5714 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5715 (clobber (reg:CC CC_REGNUM))]
5718 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5719 (clobber (reg:CC CC_REGNUM))])]
5720 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5723 ; xorsi3 instruction pattern(s).
5726 (define_insn "*xorsi3_cc"
5727 [(set (reg CC_REGNUM)
5728 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5729 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5731 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5732 (xor:SI (match_dup 1) (match_dup 2)))]
5733 "s390_match_ccmode(insn, CCTmode)"
5739 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5741 (define_insn "*xorsi3_cconly"
5742 [(set (reg CC_REGNUM)
5743 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5744 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5746 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5747 "s390_match_ccmode(insn, CCTmode)"
5753 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5755 (define_insn "*xorsi3"
5756 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5757 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5758 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5759 (clobber (reg:CC CC_REGNUM))]
5760 "s390_logical_operator_ok_p (operands)"
5768 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5771 [(set (match_operand:SI 0 "s_operand" "")
5772 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5773 (clobber (reg:CC CC_REGNUM))]
5776 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5777 (clobber (reg:CC CC_REGNUM))])]
5778 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5781 ; xorhi3 instruction pattern(s).
5784 (define_insn "*xorhi3"
5785 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5786 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5787 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5788 (clobber (reg:CC CC_REGNUM))]
5789 "s390_logical_operator_ok_p (operands)"
5795 [(set_attr "op_type" "RIL,RR,SI,SS")])
5798 [(set (match_operand:HI 0 "s_operand" "")
5799 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5800 (clobber (reg:CC CC_REGNUM))]
5803 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5804 (clobber (reg:CC CC_REGNUM))])]
5805 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5808 ; xorqi3 instruction pattern(s).
5811 (define_insn "*xorqi3"
5812 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5813 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5814 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5815 (clobber (reg:CC CC_REGNUM))]
5816 "s390_logical_operator_ok_p (operands)"
5823 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5826 ; Block exclusive or (XC) patterns.
5830 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5831 (xor:BLK (match_dup 0)
5832 (match_operand:BLK 1 "memory_operand" "Q")))
5833 (use (match_operand 2 "const_int_operand" "n"))
5834 (clobber (reg:CC CC_REGNUM))]
5835 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5836 "xc\t%O0(%2,%R0),%S1"
5837 [(set_attr "op_type" "SS")])
5840 [(set (match_operand 0 "memory_operand" "")
5842 (match_operand 1 "memory_operand" "")))
5843 (clobber (reg:CC CC_REGNUM))]
5845 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5846 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5848 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5850 (clobber (reg:CC CC_REGNUM))])]
5852 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5853 operands[0] = adjust_address (operands[0], BLKmode, 0);
5854 operands[1] = adjust_address (operands[1], BLKmode, 0);
5859 [(set (match_operand:BLK 0 "memory_operand" "")
5860 (xor:BLK (match_dup 0)
5861 (match_operand:BLK 1 "memory_operand" "")))
5862 (use (match_operand 2 "const_int_operand" ""))
5863 (clobber (reg:CC CC_REGNUM))])
5865 [(set (match_operand:BLK 3 "memory_operand" "")
5866 (xor:BLK (match_dup 3)
5867 (match_operand:BLK 4 "memory_operand" "")))
5868 (use (match_operand 5 "const_int_operand" ""))
5869 (clobber (reg:CC CC_REGNUM))])]
5870 "s390_offset_p (operands[0], operands[3], operands[2])
5871 && s390_offset_p (operands[1], operands[4], operands[2])
5872 && !s390_overlap_p (operands[0], operands[1],
5873 INTVAL (operands[2]) + INTVAL (operands[5]))
5874 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5876 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5878 (clobber (reg:CC CC_REGNUM))])]
5879 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5880 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5881 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5884 ; Block xor (XC) patterns with src == dest.
5887 (define_insn "*xc_zero"
5888 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5890 (use (match_operand 1 "const_int_operand" "n"))
5891 (clobber (reg:CC CC_REGNUM))]
5892 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5893 "xc\t%O0(%1,%R0),%S0"
5894 [(set_attr "op_type" "SS")])
5898 [(set (match_operand:BLK 0 "memory_operand" "")
5900 (use (match_operand 1 "const_int_operand" ""))
5901 (clobber (reg:CC CC_REGNUM))])
5903 [(set (match_operand:BLK 2 "memory_operand" "")
5905 (use (match_operand 3 "const_int_operand" ""))
5906 (clobber (reg:CC CC_REGNUM))])]
5907 "s390_offset_p (operands[0], operands[2], operands[1])
5908 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5910 [(set (match_dup 4) (const_int 0))
5912 (clobber (reg:CC CC_REGNUM))])]
5913 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5914 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5918 ;;- Negate instructions.
5922 ; neg(di|si)2 instruction pattern(s).
5925 (define_expand "neg<mode>2"
5927 [(set (match_operand:DSI 0 "register_operand" "=d")
5928 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5929 (clobber (reg:CC CC_REGNUM))])]
5933 (define_insn "*negdi2_sign_cc"
5934 [(set (reg CC_REGNUM)
5935 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5936 (match_operand:SI 1 "register_operand" "d") 0)
5937 (const_int 32)) (const_int 32)))
5939 (set (match_operand:DI 0 "register_operand" "=d")
5940 (neg:DI (sign_extend:DI (match_dup 1))))]
5941 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5943 [(set_attr "op_type" "RRE")])
5945 (define_insn "*negdi2_sign"
5946 [(set (match_operand:DI 0 "register_operand" "=d")
5947 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5948 (clobber (reg:CC CC_REGNUM))]
5951 [(set_attr "op_type" "RRE")])
5954 (define_insn "*neg<mode>2_cc"
5955 [(set (reg CC_REGNUM)
5956 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5958 (set (match_operand:GPR 0 "register_operand" "=d")
5959 (neg:GPR (match_dup 1)))]
5960 "s390_match_ccmode (insn, CCAmode)"
5962 [(set_attr "op_type" "RR<E>")])
5965 (define_insn "*neg<mode>2_cconly"
5966 [(set (reg CC_REGNUM)
5967 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5969 (clobber (match_scratch:GPR 0 "=d"))]
5970 "s390_match_ccmode (insn, CCAmode)"
5972 [(set_attr "op_type" "RR<E>")])
5975 (define_insn "*neg<mode>2"
5976 [(set (match_operand:GPR 0 "register_operand" "=d")
5977 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5978 (clobber (reg:CC CC_REGNUM))]
5981 [(set_attr "op_type" "RR<E>")])
5983 (define_insn_and_split "*negdi2_31"
5984 [(set (match_operand:DI 0 "register_operand" "=d")
5985 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5986 (clobber (reg:CC CC_REGNUM))]
5989 "&& reload_completed"
5991 [(set (match_dup 2) (neg:SI (match_dup 3)))
5992 (clobber (reg:CC CC_REGNUM))])
5994 [(set (reg:CCAP CC_REGNUM)
5995 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5996 (set (match_dup 4) (neg:SI (match_dup 5)))])
5998 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6000 (label_ref (match_dup 6))))
6002 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6003 (clobber (reg:CC CC_REGNUM))])
6005 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6006 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6007 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6008 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6009 operands[6] = gen_label_rtx ();")
6012 ; neg(df|sf)2 instruction pattern(s).
6015 (define_expand "neg<mode>2"
6017 [(set (match_operand:BFP 0 "register_operand" "=f")
6018 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6019 (clobber (reg:CC CC_REGNUM))])]
6023 ; lcxbr, lcdbr, lcebr
6024 (define_insn "*neg<mode>2_cc"
6025 [(set (reg CC_REGNUM)
6026 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6027 (match_operand:BFP 2 "const0_operand" "")))
6028 (set (match_operand:BFP 0 "register_operand" "=f")
6029 (neg:BFP (match_dup 1)))]
6030 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6032 [(set_attr "op_type" "RRE")
6033 (set_attr "type" "fsimp<mode>")])
6035 ; lcxbr, lcdbr, lcebr
6036 (define_insn "*neg<mode>2_cconly"
6037 [(set (reg CC_REGNUM)
6038 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6039 (match_operand:BFP 2 "const0_operand" "")))
6040 (clobber (match_scratch:BFP 0 "=f"))]
6041 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6043 [(set_attr "op_type" "RRE")
6044 (set_attr "type" "fsimp<mode>")])
6047 (define_insn "*neg<mode>2_nocc"
6048 [(set (match_operand:BFP 0 "register_operand" "=f")
6049 (neg:BFP (match_operand:BFP 1 "register_operand" "<fT0>")))]
6050 "TARGET_HARD_FLOAT && TARGET_DFP"
6052 [(set_attr "op_type" "RRE")
6053 (set_attr "type" "fsimp<mode>")])
6055 ; lcxbr, lcdbr, lcebr
6056 (define_insn "*neg<mode>2"
6057 [(set (match_operand:BFP 0 "register_operand" "=f")
6058 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6059 (clobber (reg:CC CC_REGNUM))]
6060 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6062 [(set_attr "op_type" "RRE")
6063 (set_attr "type" "fsimp<mode>")])
6066 (define_insn "*neg<mode>2_ibm"
6067 [(set (match_operand:BFP 0 "register_operand" "=f")
6068 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6069 (clobber (reg:CC CC_REGNUM))]
6070 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6072 [(set_attr "op_type" "<RRe>")
6073 (set_attr "type" "fsimp<mode>")])
6077 ;;- Absolute value instructions.
6081 ; abs(di|si)2 instruction pattern(s).
6084 (define_insn "*absdi2_sign_cc"
6085 [(set (reg CC_REGNUM)
6086 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6087 (match_operand:SI 1 "register_operand" "d") 0)
6088 (const_int 32)) (const_int 32)))
6090 (set (match_operand:DI 0 "register_operand" "=d")
6091 (abs:DI (sign_extend:DI (match_dup 1))))]
6092 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6094 [(set_attr "op_type" "RRE")])
6096 (define_insn "*absdi2_sign"
6097 [(set (match_operand:DI 0 "register_operand" "=d")
6098 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6099 (clobber (reg:CC CC_REGNUM))]
6102 [(set_attr "op_type" "RRE")])
6105 (define_insn "*abs<mode>2_cc"
6106 [(set (reg CC_REGNUM)
6107 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6109 (set (match_operand:GPR 0 "register_operand" "=d")
6110 (abs:GPR (match_dup 1)))]
6111 "s390_match_ccmode (insn, CCAmode)"
6113 [(set_attr "op_type" "RR<E>")])
6116 (define_insn "*abs<mode>2_cconly"
6117 [(set (reg CC_REGNUM)
6118 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6120 (clobber (match_scratch:GPR 0 "=d"))]
6121 "s390_match_ccmode (insn, CCAmode)"
6123 [(set_attr "op_type" "RR<E>")])
6126 (define_insn "abs<mode>2"
6127 [(set (match_operand:GPR 0 "register_operand" "=d")
6128 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6129 (clobber (reg:CC CC_REGNUM))]
6132 [(set_attr "op_type" "RR<E>")])
6135 ; abs(df|sf)2 instruction pattern(s).
6138 (define_expand "abs<mode>2"
6140 [(set (match_operand:BFP 0 "register_operand" "=f")
6141 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6142 (clobber (reg:CC CC_REGNUM))])]
6146 ; lpxbr, lpdbr, lpebr
6147 (define_insn "*abs<mode>2_cc"
6148 [(set (reg CC_REGNUM)
6149 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6150 (match_operand:BFP 2 "const0_operand" "")))
6151 (set (match_operand:BFP 0 "register_operand" "=f")
6152 (abs:BFP (match_dup 1)))]
6153 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6155 [(set_attr "op_type" "RRE")
6156 (set_attr "type" "fsimp<mode>")])
6158 ; lpxbr, lpdbr, lpebr
6159 (define_insn "*abs<mode>2_cconly"
6160 [(set (reg CC_REGNUM)
6161 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6162 (match_operand:BFP 2 "const0_operand" "")))
6163 (clobber (match_scratch:BFP 0 "=f"))]
6164 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6166 [(set_attr "op_type" "RRE")
6167 (set_attr "type" "fsimp<mode>")])
6170 (define_insn "*abs<mode>2_nocc"
6171 [(set (match_operand:BFP 0 "register_operand" "=f")
6172 (abs:BFP (match_operand:BFP 1 "register_operand" "<fT0>")))]
6173 "TARGET_HARD_FLOAT && TARGET_DFP"
6175 [(set_attr "op_type" "RRE")
6176 (set_attr "type" "fsimp<mode>")])
6178 ; lpxbr, lpdbr, lpebr
6179 (define_insn "*abs<mode>2"
6180 [(set (match_operand:BFP 0 "register_operand" "=f")
6181 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6182 (clobber (reg:CC CC_REGNUM))]
6183 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6185 [(set_attr "op_type" "RRE")
6186 (set_attr "type" "fsimp<mode>")])
6189 (define_insn "*abs<mode>2_ibm"
6190 [(set (match_operand:BFP 0 "register_operand" "=f")
6191 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6192 (clobber (reg:CC CC_REGNUM))]
6193 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6195 [(set_attr "op_type" "<RRe>")
6196 (set_attr "type" "fsimp<mode>")])
6199 ;;- Negated absolute value instructions
6206 (define_insn "*negabsdi2_sign_cc"
6207 [(set (reg CC_REGNUM)
6208 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6209 (match_operand:SI 1 "register_operand" "d") 0)
6210 (const_int 32)) (const_int 32))))
6212 (set (match_operand:DI 0 "register_operand" "=d")
6213 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6214 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6216 [(set_attr "op_type" "RRE")])
6218 (define_insn "*negabsdi2_sign"
6219 [(set (match_operand:DI 0 "register_operand" "=d")
6220 (neg:DI (abs:DI (sign_extend:DI
6221 (match_operand:SI 1 "register_operand" "d")))))
6222 (clobber (reg:CC CC_REGNUM))]
6225 [(set_attr "op_type" "RRE")])
6228 (define_insn "*negabs<mode>2_cc"
6229 [(set (reg CC_REGNUM)
6230 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6232 (set (match_operand:GPR 0 "register_operand" "=d")
6233 (neg:GPR (abs:GPR (match_dup 1))))]
6234 "s390_match_ccmode (insn, CCAmode)"
6236 [(set_attr "op_type" "RR<E>")])
6239 (define_insn "*negabs<mode>2_cconly"
6240 [(set (reg CC_REGNUM)
6241 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6243 (clobber (match_scratch:GPR 0 "=d"))]
6244 "s390_match_ccmode (insn, CCAmode)"
6246 [(set_attr "op_type" "RR<E>")])
6249 (define_insn "*negabs<mode>2"
6250 [(set (match_operand:GPR 0 "register_operand" "=d")
6251 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6252 (clobber (reg:CC CC_REGNUM))]
6255 [(set_attr "op_type" "RR<E>")])
6261 ; lnxbr, lndbr, lnebr
6262 (define_insn "*negabs<mode>2_cc"
6263 [(set (reg CC_REGNUM)
6264 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6265 (match_operand:BFP 2 "const0_operand" "")))
6266 (set (match_operand:BFP 0 "register_operand" "=f")
6267 (neg:BFP (abs:BFP (match_dup 1))))]
6268 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6270 [(set_attr "op_type" "RRE")
6271 (set_attr "type" "fsimp<mode>")])
6273 ; lnxbr, lndbr, lnebr
6274 (define_insn "*negabs<mode>2_cconly"
6275 [(set (reg CC_REGNUM)
6276 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6277 (match_operand:BFP 2 "const0_operand" "")))
6278 (clobber (match_scratch:BFP 0 "=f"))]
6279 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6281 [(set_attr "op_type" "RRE")
6282 (set_attr "type" "fsimp<mode>")])
6285 (define_insn "*negabs<mode>2_nocc"
6286 [(set (match_operand:BFP 0 "register_operand" "=f")
6287 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
6288 "TARGET_HARD_FLOAT && TARGET_DFP"
6290 [(set_attr "op_type" "RRE")
6291 (set_attr "type" "fsimp<mode>")])
6293 ; lnxbr, lndbr, lnebr
6294 (define_insn "*negabs<mode>2"
6295 [(set (match_operand:BFP 0 "register_operand" "=f")
6296 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
6297 (clobber (reg:CC CC_REGNUM))]
6298 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6300 [(set_attr "op_type" "RRE")
6301 (set_attr "type" "fsimp<mode>")])
6304 ;;- Copy sign instructions
6308 (define_insn "copysign<mode>3"
6309 [(set (match_operand:BFP 0 "register_operand" "=f")
6310 (unspec:BFP [(match_operand:BFP 1 "register_operand" "<fT0>")
6311 (match_operand:BFP 2 "register_operand" "f")]
6313 "TARGET_HARD_FLOAT && TARGET_DFP"
6315 [(set_attr "op_type" "RRF")
6316 (set_attr "type" "fsimp<mode>")])
6319 ;;- Square root instructions.
6323 ; sqrt(df|sf)2 instruction pattern(s).
6326 ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
6327 (define_insn "sqrt<mode>2"
6328 [(set (match_operand:BFP 0 "register_operand" "=f,f")
6329 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
6330 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6334 [(set_attr "op_type" "RRE,RXE")
6335 (set_attr "type" "fsqrt<mode>")])
6339 ;;- One complement instructions.
6343 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6346 (define_expand "one_cmpl<mode>2"
6348 [(set (match_operand:INT 0 "register_operand" "")
6349 (xor:INT (match_operand:INT 1 "register_operand" "")
6351 (clobber (reg:CC CC_REGNUM))])]
6357 ;; Find leftmost bit instructions.
6360 (define_expand "clzdi2"
6361 [(set (match_operand:DI 0 "register_operand" "=d")
6362 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6363 "TARGET_EXTIMM && TARGET_64BIT"
6365 rtx insn, clz_equal;
6366 rtx wide_reg = gen_reg_rtx (TImode);
6367 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6369 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6371 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6373 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6374 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
6379 (define_insn "clztidi2"
6380 [(set (match_operand:TI 0 "register_operand" "=d")
6384 (xor:DI (match_operand:DI 1 "register_operand" "d")
6385 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6386 (subreg:SI (clz:DI (match_dup 1)) 4))))
6389 (zero_extend:TI (clz:DI (match_dup 1)))))
6390 (clobber (reg:CC CC_REGNUM))]
6391 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6392 == (unsigned HOST_WIDE_INT) 1 << 63
6393 && TARGET_EXTIMM && TARGET_64BIT"
6395 [(set_attr "op_type" "RRE")])
6399 ;;- Rotate instructions.
6403 ; rotl(di|si)3 instruction pattern(s).
6407 (define_insn "rotl<mode>3"
6408 [(set (match_operand:GPR 0 "register_operand" "=d")
6409 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6410 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6413 [(set_attr "op_type" "RSE")
6414 (set_attr "atype" "reg")])
6417 (define_insn "*rotl<mode>3_and"
6418 [(set (match_operand:GPR 0 "register_operand" "=d")
6419 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6420 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6421 (match_operand:SI 3 "const_int_operand" "n"))))]
6422 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6424 [(set_attr "op_type" "RSE")
6425 (set_attr "atype" "reg")])
6429 ;;- Shift instructions.
6433 ; (ashl|lshr)(di|si)3 instruction pattern(s).
6436 (define_expand "<shift><mode>3"
6437 [(set (match_operand:DSI 0 "register_operand" "")
6438 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
6439 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6444 (define_insn "*<shift>di3_31"
6445 [(set (match_operand:DI 0 "register_operand" "=d")
6446 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6447 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6450 [(set_attr "op_type" "RS")
6451 (set_attr "atype" "reg")])
6453 ; sll, srl, sllg, srlg
6454 (define_insn "*<shift><mode>3"
6455 [(set (match_operand:GPR 0 "register_operand" "=d")
6456 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6457 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6459 "s<lr>l<g>\t%0,<1>%Y2"
6460 [(set_attr "op_type" "RS<E>")
6461 (set_attr "atype" "reg")])
6464 (define_insn "*<shift>di3_31_and"
6465 [(set (match_operand:DI 0 "register_operand" "=d")
6466 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6467 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6468 (match_operand:SI 3 "const_int_operand" "n"))))]
6469 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6471 [(set_attr "op_type" "RS")
6472 (set_attr "atype" "reg")])
6474 ; sll, srl, sllg, srlg
6475 (define_insn "*<shift><mode>3_and"
6476 [(set (match_operand:GPR 0 "register_operand" "=d")
6477 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6478 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6479 (match_operand:SI 3 "const_int_operand" "n"))))]
6480 "(INTVAL (operands[3]) & 63) == 63"
6481 "s<lr>l<g>\t%0,<1>%Y2"
6482 [(set_attr "op_type" "RS<E>")
6483 (set_attr "atype" "reg")])
6486 ; ashr(di|si)3 instruction pattern(s).
6489 (define_expand "ashr<mode>3"
6491 [(set (match_operand:DSI 0 "register_operand" "")
6492 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
6493 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6494 (clobber (reg:CC CC_REGNUM))])]
6498 (define_insn "*ashrdi3_cc_31"
6499 [(set (reg CC_REGNUM)
6500 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6501 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6503 (set (match_operand:DI 0 "register_operand" "=d")
6504 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6505 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6507 [(set_attr "op_type" "RS")
6508 (set_attr "atype" "reg")])
6510 (define_insn "*ashrdi3_cconly_31"
6511 [(set (reg CC_REGNUM)
6512 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6513 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6515 (clobber (match_scratch:DI 0 "=d"))]
6516 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6518 [(set_attr "op_type" "RS")
6519 (set_attr "atype" "reg")])
6521 (define_insn "*ashrdi3_31"
6522 [(set (match_operand:DI 0 "register_operand" "=d")
6523 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6524 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6525 (clobber (reg:CC CC_REGNUM))]
6528 [(set_attr "op_type" "RS")
6529 (set_attr "atype" "reg")])
6532 (define_insn "*ashr<mode>3_cc"
6533 [(set (reg CC_REGNUM)
6534 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6535 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6537 (set (match_operand:GPR 0 "register_operand" "=d")
6538 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
6539 "s390_match_ccmode(insn, CCSmode)"
6541 [(set_attr "op_type" "RS<E>")
6542 (set_attr "atype" "reg")])
6545 (define_insn "*ashr<mode>3_cconly"
6546 [(set (reg CC_REGNUM)
6547 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6548 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6550 (clobber (match_scratch:GPR 0 "=d"))]
6551 "s390_match_ccmode(insn, CCSmode)"
6553 [(set_attr "op_type" "RS<E>")
6554 (set_attr "atype" "reg")])
6557 (define_insn "*ashr<mode>3"
6558 [(set (match_operand:GPR 0 "register_operand" "=d")
6559 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6560 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6561 (clobber (reg:CC CC_REGNUM))]
6564 [(set_attr "op_type" "RS<E>")
6565 (set_attr "atype" "reg")])
6568 ; shift pattern with implicit ANDs
6570 (define_insn "*ashrdi3_cc_31_and"
6571 [(set (reg CC_REGNUM)
6572 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6573 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6574 (match_operand:SI 3 "const_int_operand" "n")))
6576 (set (match_operand:DI 0 "register_operand" "=d")
6577 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6578 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6579 && (INTVAL (operands[3]) & 63) == 63"
6581 [(set_attr "op_type" "RS")
6582 (set_attr "atype" "reg")])
6584 (define_insn "*ashrdi3_cconly_31_and"
6585 [(set (reg CC_REGNUM)
6586 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6587 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6588 (match_operand:SI 3 "const_int_operand" "n")))
6590 (clobber (match_scratch:DI 0 "=d"))]
6591 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6592 && (INTVAL (operands[3]) & 63) == 63"
6594 [(set_attr "op_type" "RS")
6595 (set_attr "atype" "reg")])
6597 (define_insn "*ashrdi3_31_and"
6598 [(set (match_operand:DI 0 "register_operand" "=d")
6599 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6600 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6601 (match_operand:SI 3 "const_int_operand" "n"))))
6602 (clobber (reg:CC CC_REGNUM))]
6603 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6605 [(set_attr "op_type" "RS")
6606 (set_attr "atype" "reg")])
6609 (define_insn "*ashr<mode>3_cc_and"
6610 [(set (reg CC_REGNUM)
6611 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6612 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6613 (match_operand:SI 3 "const_int_operand" "n")))
6615 (set (match_operand:GPR 0 "register_operand" "=d")
6616 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6617 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6619 [(set_attr "op_type" "RS<E>")
6620 (set_attr "atype" "reg")])
6623 (define_insn "*ashr<mode>3_cconly_and"
6624 [(set (reg CC_REGNUM)
6625 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6626 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6627 (match_operand:SI 3 "const_int_operand" "n")))
6629 (clobber (match_scratch:GPR 0 "=d"))]
6630 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6632 [(set_attr "op_type" "RS<E>")
6633 (set_attr "atype" "reg")])
6636 (define_insn "*ashr<mode>3_and"
6637 [(set (match_operand:GPR 0 "register_operand" "=d")
6638 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6639 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6640 (match_operand:SI 3 "const_int_operand" "n"))))
6641 (clobber (reg:CC CC_REGNUM))]
6642 "(INTVAL (operands[3]) & 63) == 63"
6644 [(set_attr "op_type" "RS<E>")
6645 (set_attr "atype" "reg")])
6649 ;; Branch instruction patterns.
6652 (define_expand "b<code>"
6654 (if_then_else (COMPARE (match_operand 0 "" "")
6659 "s390_emit_jump (operands[0],
6660 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6664 ;;- Conditional jump instructions.
6667 (define_insn "*cjump_64"
6670 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6671 (label_ref (match_operand 0 "" ""))
6675 if (get_attr_length (insn) == 4)
6678 return "jg%C1\t%l0";
6680 [(set_attr "op_type" "RI")
6681 (set_attr "type" "branch")
6682 (set (attr "length")
6683 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6684 (const_int 4) (const_int 6)))])
6686 (define_insn "*cjump_31"
6689 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6690 (label_ref (match_operand 0 "" ""))
6694 gcc_assert (get_attr_length (insn) == 4);
6697 [(set_attr "op_type" "RI")
6698 (set_attr "type" "branch")
6699 (set (attr "length")
6700 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6701 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6702 (const_int 4) (const_int 6))
6703 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6704 (const_int 4) (const_int 8))))])
6706 (define_insn "*cjump_long"
6709 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6710 (match_operand 0 "address_operand" "U")
6714 if (get_attr_op_type (insn) == OP_TYPE_RR)
6719 [(set (attr "op_type")
6720 (if_then_else (match_operand 0 "register_operand" "")
6721 (const_string "RR") (const_string "RX")))
6722 (set_attr "type" "branch")
6723 (set_attr "atype" "agen")])
6727 ;;- Negated conditional jump instructions.
6730 (define_insn "*icjump_64"
6733 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6735 (label_ref (match_operand 0 "" ""))))]
6738 if (get_attr_length (insn) == 4)
6741 return "jg%D1\t%l0";
6743 [(set_attr "op_type" "RI")
6744 (set_attr "type" "branch")
6745 (set (attr "length")
6746 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6747 (const_int 4) (const_int 6)))])
6749 (define_insn "*icjump_31"
6752 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6754 (label_ref (match_operand 0 "" ""))))]
6757 gcc_assert (get_attr_length (insn) == 4);
6760 [(set_attr "op_type" "RI")
6761 (set_attr "type" "branch")
6762 (set (attr "length")
6763 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6764 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6765 (const_int 4) (const_int 6))
6766 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6767 (const_int 4) (const_int 8))))])
6769 (define_insn "*icjump_long"
6772 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6774 (match_operand 0 "address_operand" "U")))]
6777 if (get_attr_op_type (insn) == OP_TYPE_RR)
6782 [(set (attr "op_type")
6783 (if_then_else (match_operand 0 "register_operand" "")
6784 (const_string "RR") (const_string "RX")))
6785 (set_attr "type" "branch")
6786 (set_attr "atype" "agen")])
6789 ;;- Trap instructions.
6793 [(trap_if (const_int 1) (const_int 0))]
6796 [(set_attr "op_type" "RI")
6797 (set_attr "type" "branch")])
6799 (define_expand "conditional_trap"
6800 [(trap_if (match_operand 0 "comparison_operator" "")
6801 (match_operand 1 "general_operand" ""))]
6804 if (operands[1] != const0_rtx) FAIL;
6805 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6806 s390_compare_op0, s390_compare_op1);
6809 (define_insn "*trap"
6810 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6814 [(set_attr "op_type" "RI")
6815 (set_attr "type" "branch")])
6818 ;;- Loop instructions.
6820 ;; This is all complicated by the fact that since this is a jump insn
6821 ;; we must handle our own output reloads.
6823 (define_expand "doloop_end"
6824 [(use (match_operand 0 "" "")) ; loop pseudo
6825 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6826 (use (match_operand 2 "" "")) ; max iterations
6827 (use (match_operand 3 "" "")) ; loop level
6828 (use (match_operand 4 "" ""))] ; label
6831 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6832 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6833 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6834 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6835 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6836 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6843 (define_insn_and_split "doloop_si64"
6846 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6848 (label_ref (match_operand 0 "" ""))
6850 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6851 (plus:SI (match_dup 1) (const_int -1)))
6852 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6853 (clobber (reg:CC CC_REGNUM))]
6856 if (which_alternative != 0)
6858 else if (get_attr_length (insn) == 4)
6859 return "brct\t%1,%l0";
6861 return "ahi\t%1,-1\;jgne\t%l0";
6863 "&& reload_completed
6864 && (! REG_P (operands[2])
6865 || ! rtx_equal_p (operands[1], operands[2]))"
6866 [(set (match_dup 3) (match_dup 1))
6867 (parallel [(set (reg:CCAN CC_REGNUM)
6868 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6870 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6871 (set (match_dup 2) (match_dup 3))
6872 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6873 (label_ref (match_dup 0))
6876 [(set_attr "op_type" "RI")
6877 (set_attr "type" "branch")
6878 (set (attr "length")
6879 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6880 (const_int 4) (const_int 10)))])
6882 (define_insn_and_split "doloop_si31"
6885 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6887 (label_ref (match_operand 0 "" ""))
6889 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6890 (plus:SI (match_dup 1) (const_int -1)))
6891 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6892 (clobber (reg:CC CC_REGNUM))]
6895 if (which_alternative != 0)
6897 else if (get_attr_length (insn) == 4)
6898 return "brct\t%1,%l0";
6902 "&& reload_completed
6903 && (! REG_P (operands[2])
6904 || ! rtx_equal_p (operands[1], operands[2]))"
6905 [(set (match_dup 3) (match_dup 1))
6906 (parallel [(set (reg:CCAN CC_REGNUM)
6907 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6909 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6910 (set (match_dup 2) (match_dup 3))
6911 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6912 (label_ref (match_dup 0))
6915 [(set_attr "op_type" "RI")
6916 (set_attr "type" "branch")
6917 (set (attr "length")
6918 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6919 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6920 (const_int 4) (const_int 6))
6921 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6922 (const_int 4) (const_int 8))))])
6924 (define_insn "*doloop_si_long"
6927 (ne (match_operand:SI 1 "register_operand" "d")
6929 (match_operand 0 "address_operand" "U")
6931 (set (match_operand:SI 2 "register_operand" "=1")
6932 (plus:SI (match_dup 1) (const_int -1)))
6933 (clobber (match_scratch:SI 3 "=X"))
6934 (clobber (reg:CC CC_REGNUM))]
6937 if (get_attr_op_type (insn) == OP_TYPE_RR)
6938 return "bctr\t%1,%0";
6940 return "bct\t%1,%a0";
6942 [(set (attr "op_type")
6943 (if_then_else (match_operand 0 "register_operand" "")
6944 (const_string "RR") (const_string "RX")))
6945 (set_attr "type" "branch")
6946 (set_attr "atype" "agen")])
6948 (define_insn_and_split "doloop_di"
6951 (ne (match_operand:DI 1 "register_operand" "d,d,d")
6953 (label_ref (match_operand 0 "" ""))
6955 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
6956 (plus:DI (match_dup 1) (const_int -1)))
6957 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
6958 (clobber (reg:CC CC_REGNUM))]
6961 if (which_alternative != 0)
6963 else if (get_attr_length (insn) == 4)
6964 return "brctg\t%1,%l0";
6966 return "aghi\t%1,-1\;jgne\t%l0";
6968 "&& reload_completed
6969 && (! REG_P (operands[2])
6970 || ! rtx_equal_p (operands[1], operands[2]))"
6971 [(set (match_dup 3) (match_dup 1))
6972 (parallel [(set (reg:CCAN CC_REGNUM)
6973 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6975 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6976 (set (match_dup 2) (match_dup 3))
6977 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6978 (label_ref (match_dup 0))
6981 [(set_attr "op_type" "RI")
6982 (set_attr "type" "branch")
6983 (set (attr "length")
6984 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6985 (const_int 4) (const_int 10)))])
6988 ;;- Unconditional jump instructions.
6992 ; jump instruction pattern(s).
6995 (define_expand "jump"
6996 [(match_operand 0 "" "")]
6998 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7000 (define_insn "*jump64"
7001 [(set (pc) (label_ref (match_operand 0 "" "")))]
7004 if (get_attr_length (insn) == 4)
7009 [(set_attr "op_type" "RI")
7010 (set_attr "type" "branch")
7011 (set (attr "length")
7012 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7013 (const_int 4) (const_int 6)))])
7015 (define_insn "*jump31"
7016 [(set (pc) (label_ref (match_operand 0 "" "")))]
7019 gcc_assert (get_attr_length (insn) == 4);
7022 [(set_attr "op_type" "RI")
7023 (set_attr "type" "branch")
7024 (set (attr "length")
7025 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7026 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7027 (const_int 4) (const_int 6))
7028 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7029 (const_int 4) (const_int 8))))])
7032 ; indirect-jump instruction pattern(s).
7035 (define_insn "indirect_jump"
7036 [(set (pc) (match_operand 0 "address_operand" "U"))]
7039 if (get_attr_op_type (insn) == OP_TYPE_RR)
7044 [(set (attr "op_type")
7045 (if_then_else (match_operand 0 "register_operand" "")
7046 (const_string "RR") (const_string "RX")))
7047 (set_attr "type" "branch")
7048 (set_attr "atype" "agen")])
7051 ; casesi instruction pattern(s).
7054 (define_insn "casesi_jump"
7055 [(set (pc) (match_operand 0 "address_operand" "U"))
7056 (use (label_ref (match_operand 1 "" "")))]
7059 if (get_attr_op_type (insn) == OP_TYPE_RR)
7064 [(set (attr "op_type")
7065 (if_then_else (match_operand 0 "register_operand" "")
7066 (const_string "RR") (const_string "RX")))
7067 (set_attr "type" "branch")
7068 (set_attr "atype" "agen")])
7070 (define_expand "casesi"
7071 [(match_operand:SI 0 "general_operand" "")
7072 (match_operand:SI 1 "general_operand" "")
7073 (match_operand:SI 2 "general_operand" "")
7074 (label_ref (match_operand 3 "" ""))
7075 (label_ref (match_operand 4 "" ""))]
7078 rtx index = gen_reg_rtx (SImode);
7079 rtx base = gen_reg_rtx (Pmode);
7080 rtx target = gen_reg_rtx (Pmode);
7082 emit_move_insn (index, operands[0]);
7083 emit_insn (gen_subsi3 (index, index, operands[1]));
7084 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7087 if (Pmode != SImode)
7088 index = convert_to_mode (Pmode, index, 1);
7089 if (GET_CODE (index) != REG)
7090 index = copy_to_mode_reg (Pmode, index);
7093 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7095 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7097 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7099 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7100 emit_move_insn (target, index);
7103 target = gen_rtx_PLUS (Pmode, base, target);
7104 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7111 ;;- Jump to subroutine.
7116 ; untyped call instruction pattern(s).
7119 ;; Call subroutine returning any type.
7120 (define_expand "untyped_call"
7121 [(parallel [(call (match_operand 0 "" "")
7123 (match_operand 1 "" "")
7124 (match_operand 2 "" "")])]
7129 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7131 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7133 rtx set = XVECEXP (operands[2], 0, i);
7134 emit_move_insn (SET_DEST (set), SET_SRC (set));
7137 /* The optimizer does not know that the call sets the function value
7138 registers we stored in the result block. We avoid problems by
7139 claiming that all hard registers are used and clobbered at this
7141 emit_insn (gen_blockage ());
7146 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7147 ;; all of memory. This blocks insns from being moved across this point.
7149 (define_insn "blockage"
7150 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7153 [(set_attr "type" "none")
7154 (set_attr "length" "0")])
7160 (define_expand "sibcall"
7161 [(call (match_operand 0 "" "")
7162 (match_operand 1 "" ""))]
7165 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7169 (define_insn "*sibcall_br"
7170 [(call (mem:QI (reg SIBCALL_REGNUM))
7171 (match_operand 0 "const_int_operand" "n"))]
7172 "SIBLING_CALL_P (insn)
7173 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7175 [(set_attr "op_type" "RR")
7176 (set_attr "type" "branch")
7177 (set_attr "atype" "agen")])
7179 (define_insn "*sibcall_brc"
7180 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7181 (match_operand 1 "const_int_operand" "n"))]
7182 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7184 [(set_attr "op_type" "RI")
7185 (set_attr "type" "branch")])
7187 (define_insn "*sibcall_brcl"
7188 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7189 (match_operand 1 "const_int_operand" "n"))]
7190 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7192 [(set_attr "op_type" "RIL")
7193 (set_attr "type" "branch")])
7196 ; sibcall_value patterns
7199 (define_expand "sibcall_value"
7200 [(set (match_operand 0 "" "")
7201 (call (match_operand 1 "" "")
7202 (match_operand 2 "" "")))]
7205 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7209 (define_insn "*sibcall_value_br"
7210 [(set (match_operand 0 "" "")
7211 (call (mem:QI (reg SIBCALL_REGNUM))
7212 (match_operand 1 "const_int_operand" "n")))]
7213 "SIBLING_CALL_P (insn)
7214 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7216 [(set_attr "op_type" "RR")
7217 (set_attr "type" "branch")
7218 (set_attr "atype" "agen")])
7220 (define_insn "*sibcall_value_brc"
7221 [(set (match_operand 0 "" "")
7222 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7223 (match_operand 2 "const_int_operand" "n")))]
7224 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7226 [(set_attr "op_type" "RI")
7227 (set_attr "type" "branch")])
7229 (define_insn "*sibcall_value_brcl"
7230 [(set (match_operand 0 "" "")
7231 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7232 (match_operand 2 "const_int_operand" "n")))]
7233 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7235 [(set_attr "op_type" "RIL")
7236 (set_attr "type" "branch")])
7240 ; call instruction pattern(s).
7243 (define_expand "call"
7244 [(call (match_operand 0 "" "")
7245 (match_operand 1 "" ""))
7246 (use (match_operand 2 "" ""))]
7249 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7250 gen_rtx_REG (Pmode, RETURN_REGNUM));
7254 (define_insn "*bras"
7255 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7256 (match_operand 1 "const_int_operand" "n"))
7257 (clobber (match_operand 2 "register_operand" "=r"))]
7258 "!SIBLING_CALL_P (insn)
7259 && TARGET_SMALL_EXEC
7260 && GET_MODE (operands[2]) == Pmode"
7262 [(set_attr "op_type" "RI")
7263 (set_attr "type" "jsr")])
7265 (define_insn "*brasl"
7266 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7267 (match_operand 1 "const_int_operand" "n"))
7268 (clobber (match_operand 2 "register_operand" "=r"))]
7269 "!SIBLING_CALL_P (insn)
7271 && GET_MODE (operands[2]) == Pmode"
7273 [(set_attr "op_type" "RIL")
7274 (set_attr "type" "jsr")])
7276 (define_insn "*basr"
7277 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7278 (match_operand 1 "const_int_operand" "n"))
7279 (clobber (match_operand 2 "register_operand" "=r"))]
7280 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7282 if (get_attr_op_type (insn) == OP_TYPE_RR)
7283 return "basr\t%2,%0";
7285 return "bas\t%2,%a0";
7287 [(set (attr "op_type")
7288 (if_then_else (match_operand 0 "register_operand" "")
7289 (const_string "RR") (const_string "RX")))
7290 (set_attr "type" "jsr")
7291 (set_attr "atype" "agen")])
7294 ; call_value instruction pattern(s).
7297 (define_expand "call_value"
7298 [(set (match_operand 0 "" "")
7299 (call (match_operand 1 "" "")
7300 (match_operand 2 "" "")))
7301 (use (match_operand 3 "" ""))]
7304 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7305 gen_rtx_REG (Pmode, RETURN_REGNUM));
7309 (define_insn "*bras_r"
7310 [(set (match_operand 0 "" "")
7311 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7312 (match_operand:SI 2 "const_int_operand" "n")))
7313 (clobber (match_operand 3 "register_operand" "=r"))]
7314 "!SIBLING_CALL_P (insn)
7315 && TARGET_SMALL_EXEC
7316 && GET_MODE (operands[3]) == Pmode"
7318 [(set_attr "op_type" "RI")
7319 (set_attr "type" "jsr")])
7321 (define_insn "*brasl_r"
7322 [(set (match_operand 0 "" "")
7323 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7324 (match_operand 2 "const_int_operand" "n")))
7325 (clobber (match_operand 3 "register_operand" "=r"))]
7326 "!SIBLING_CALL_P (insn)
7328 && GET_MODE (operands[3]) == Pmode"
7330 [(set_attr "op_type" "RIL")
7331 (set_attr "type" "jsr")])
7333 (define_insn "*basr_r"
7334 [(set (match_operand 0 "" "")
7335 (call (mem:QI (match_operand 1 "address_operand" "U"))
7336 (match_operand 2 "const_int_operand" "n")))
7337 (clobber (match_operand 3 "register_operand" "=r"))]
7338 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7340 if (get_attr_op_type (insn) == OP_TYPE_RR)
7341 return "basr\t%3,%1";
7343 return "bas\t%3,%a1";
7345 [(set (attr "op_type")
7346 (if_then_else (match_operand 1 "register_operand" "")
7347 (const_string "RR") (const_string "RX")))
7348 (set_attr "type" "jsr")
7349 (set_attr "atype" "agen")])
7352 ;;- Thread-local storage support.
7355 (define_expand "get_tp_64"
7356 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7360 (define_expand "get_tp_31"
7361 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7365 (define_expand "set_tp_64"
7366 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7367 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7371 (define_expand "set_tp_31"
7372 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7373 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7377 (define_insn "*set_tp"
7378 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7381 [(set_attr "type" "none")
7382 (set_attr "length" "0")])
7384 (define_insn "*tls_load_64"
7385 [(set (match_operand:DI 0 "register_operand" "=d")
7386 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7387 (match_operand:DI 2 "" "")]
7391 [(set_attr "op_type" "RXE")])
7393 (define_insn "*tls_load_31"
7394 [(set (match_operand:SI 0 "register_operand" "=d,d")
7395 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7396 (match_operand:SI 2 "" "")]
7402 [(set_attr "op_type" "RX,RXY")])
7404 (define_insn "*bras_tls"
7405 [(set (match_operand 0 "" "")
7406 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7407 (match_operand 2 "const_int_operand" "n")))
7408 (clobber (match_operand 3 "register_operand" "=r"))
7409 (use (match_operand 4 "" ""))]
7410 "!SIBLING_CALL_P (insn)
7411 && TARGET_SMALL_EXEC
7412 && GET_MODE (operands[3]) == Pmode"
7414 [(set_attr "op_type" "RI")
7415 (set_attr "type" "jsr")])
7417 (define_insn "*brasl_tls"
7418 [(set (match_operand 0 "" "")
7419 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7420 (match_operand 2 "const_int_operand" "n")))
7421 (clobber (match_operand 3 "register_operand" "=r"))
7422 (use (match_operand 4 "" ""))]
7423 "!SIBLING_CALL_P (insn)
7425 && GET_MODE (operands[3]) == Pmode"
7427 [(set_attr "op_type" "RIL")
7428 (set_attr "type" "jsr")])
7430 (define_insn "*basr_tls"
7431 [(set (match_operand 0 "" "")
7432 (call (mem:QI (match_operand 1 "address_operand" "U"))
7433 (match_operand 2 "const_int_operand" "n")))
7434 (clobber (match_operand 3 "register_operand" "=r"))
7435 (use (match_operand 4 "" ""))]
7436 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7438 if (get_attr_op_type (insn) == OP_TYPE_RR)
7439 return "basr\t%3,%1%J4";
7441 return "bas\t%3,%a1%J4";
7443 [(set (attr "op_type")
7444 (if_then_else (match_operand 1 "register_operand" "")
7445 (const_string "RR") (const_string "RX")))
7446 (set_attr "type" "jsr")
7447 (set_attr "atype" "agen")])
7450 ;;- Atomic operations
7454 ; memory barrier pattern.
7457 (define_expand "memory_barrier"
7458 [(set (mem:BLK (match_dup 0))
7459 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7462 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7463 MEM_VOLATILE_P (operands[0]) = 1;
7466 (define_insn "*memory_barrier"
7467 [(set (match_operand:BLK 0 "" "")
7468 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7471 [(set_attr "op_type" "RR")])
7474 ; compare and swap patterns.
7477 (define_expand "sync_compare_and_swap<mode>"
7479 [(set (match_operand:TDSI 0 "register_operand" "")
7480 (match_operand:TDSI 1 "memory_operand" ""))
7482 (unspec_volatile:TDSI
7484 (match_operand:TDSI 2 "register_operand" "")
7485 (match_operand:TDSI 3 "register_operand" "")]
7487 (set (reg:CCZ1 CC_REGNUM)
7488 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7491 (define_expand "sync_compare_and_swap<mode>"
7493 [(set (match_operand:HQI 0 "register_operand" "")
7494 (match_operand:HQI 1 "memory_operand" ""))
7496 (unspec_volatile:HQI
7498 (match_operand:HQI 2 "general_operand" "")
7499 (match_operand:HQI 3 "general_operand" "")]
7501 (set (reg:CCZ1 CC_REGNUM)
7502 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7504 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7505 operands[2], operands[3]); DONE;")
7507 (define_expand "sync_compare_and_swap_cc<mode>"
7509 [(set (match_operand:TDSI 0 "register_operand" "")
7510 (match_operand:TDSI 1 "memory_operand" ""))
7512 (unspec_volatile:TDSI
7514 (match_operand:TDSI 2 "register_operand" "")
7515 (match_operand:TDSI 3 "register_operand" "")]
7518 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7521 /* Emulate compare. */
7522 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7523 s390_compare_op0 = operands[1];
7524 s390_compare_op1 = operands[2];
7525 s390_compare_emitted = operands[4];
7529 (define_insn "*sync_compare_and_swap<mode>"
7530 [(set (match_operand:DP 0 "register_operand" "=r")
7531 (match_operand:DP 1 "memory_operand" "+Q"))
7535 (match_operand:DP 2 "register_operand" "0")
7536 (match_operand:DP 3 "register_operand" "r")]
7538 (set (reg:CCZ1 CC_REGNUM)
7539 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7541 "cds<tg>\t%0,%3,%S1"
7542 [(set_attr "op_type" "RS<TE>")
7543 (set_attr "type" "sem")])
7546 (define_insn "*sync_compare_and_swap<mode>"
7547 [(set (match_operand:GPR 0 "register_operand" "=r")
7548 (match_operand:GPR 1 "memory_operand" "+Q"))
7550 (unspec_volatile:GPR
7552 (match_operand:GPR 2 "register_operand" "0")
7553 (match_operand:GPR 3 "register_operand" "r")]
7555 (set (reg:CCZ1 CC_REGNUM)
7556 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7559 [(set_attr "op_type" "RS<E>")
7560 (set_attr "type" "sem")])
7564 ; Other atomic instruction patterns.
7567 (define_expand "sync_lock_test_and_set<mode>"
7568 [(match_operand:HQI 0 "register_operand")
7569 (match_operand:HQI 1 "memory_operand")
7570 (match_operand:HQI 2 "general_operand")]
7572 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7573 operands[2], false); DONE;")
7575 (define_expand "sync_<atomic><mode>"
7576 [(set (match_operand:HQI 0 "memory_operand")
7577 (ATOMIC:HQI (match_dup 0)
7578 (match_operand:HQI 1 "general_operand")))]
7580 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7581 operands[1], false); DONE;")
7583 (define_expand "sync_old_<atomic><mode>"
7584 [(set (match_operand:HQI 0 "register_operand")
7585 (match_operand:HQI 1 "memory_operand"))
7587 (ATOMIC:HQI (match_dup 1)
7588 (match_operand:HQI 2 "general_operand")))]
7590 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7591 operands[2], false); DONE;")
7593 (define_expand "sync_new_<atomic><mode>"
7594 [(set (match_operand:HQI 0 "register_operand")
7595 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7596 (match_operand:HQI 2 "general_operand")))
7597 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7599 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7600 operands[2], true); DONE;")
7603 ;;- Miscellaneous instructions.
7607 ; allocate stack instruction pattern(s).
7610 (define_expand "allocate_stack"
7611 [(match_operand 0 "general_operand" "")
7612 (match_operand 1 "general_operand" "")]
7615 rtx temp = gen_reg_rtx (Pmode);
7617 emit_move_insn (temp, s390_back_chain_rtx ());
7618 anti_adjust_stack (operands[1]);
7619 emit_move_insn (s390_back_chain_rtx (), temp);
7621 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7627 ; setjmp instruction pattern.
7630 (define_expand "builtin_setjmp_receiver"
7631 [(match_operand 0 "" "")]
7634 emit_insn (s390_load_got ());
7635 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7639 ;; These patterns say how to save and restore the stack pointer. We need not
7640 ;; save the stack pointer at function level since we are careful to
7641 ;; preserve the backchain. At block level, we have to restore the backchain
7642 ;; when we restore the stack pointer.
7644 ;; For nonlocal gotos, we must save both the stack pointer and its
7645 ;; backchain and restore both. Note that in the nonlocal case, the
7646 ;; save area is a memory location.
7648 (define_expand "save_stack_function"
7649 [(match_operand 0 "general_operand" "")
7650 (match_operand 1 "general_operand" "")]
7654 (define_expand "restore_stack_function"
7655 [(match_operand 0 "general_operand" "")
7656 (match_operand 1 "general_operand" "")]
7660 (define_expand "restore_stack_block"
7661 [(match_operand 0 "register_operand" "")
7662 (match_operand 1 "register_operand" "")]
7665 rtx temp = gen_reg_rtx (Pmode);
7667 emit_move_insn (temp, s390_back_chain_rtx ());
7668 emit_move_insn (operands[0], operands[1]);
7669 emit_move_insn (s390_back_chain_rtx (), temp);
7674 (define_expand "save_stack_nonlocal"
7675 [(match_operand 0 "memory_operand" "")
7676 (match_operand 1 "register_operand" "")]
7679 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7680 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7682 /* Copy the backchain to the first word, sp to the second and the
7683 literal pool base to the third. */
7685 if (TARGET_BACKCHAIN)
7687 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7688 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7691 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7692 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7697 (define_expand "restore_stack_nonlocal"
7698 [(match_operand 0 "register_operand" "")
7699 (match_operand 1 "memory_operand" "")]
7702 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7703 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7704 rtx temp = NULL_RTX;
7706 /* Restore the backchain from the first word, sp from the second and the
7707 literal pool base from the third. */
7709 if (TARGET_BACKCHAIN)
7710 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7712 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7713 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7716 emit_move_insn (s390_back_chain_rtx (), temp);
7718 emit_insn (gen_rtx_USE (VOIDmode, base));
7722 (define_expand "exception_receiver"
7726 s390_set_has_landing_pad_p (true);
7731 ; nop instruction pattern(s).
7738 [(set_attr "op_type" "RR")])
7742 ; Special literal pool access instruction pattern(s).
7745 (define_insn "*pool_entry"
7746 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7747 UNSPECV_POOL_ENTRY)]
7750 enum machine_mode mode = GET_MODE (PATTERN (insn));
7751 unsigned int align = GET_MODE_BITSIZE (mode);
7752 s390_output_pool_entry (operands[0], mode, align);
7755 [(set (attr "length")
7756 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7758 (define_insn "pool_align"
7759 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7760 UNSPECV_POOL_ALIGN)]
7763 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7765 (define_insn "pool_section_start"
7766 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7769 [(set_attr "length" "0")])
7771 (define_insn "pool_section_end"
7772 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7775 [(set_attr "length" "0")])
7777 (define_insn "main_base_31_small"
7778 [(set (match_operand 0 "register_operand" "=a")
7779 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7780 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7782 [(set_attr "op_type" "RR")
7783 (set_attr "type" "la")])
7785 (define_insn "main_base_31_large"
7786 [(set (match_operand 0 "register_operand" "=a")
7787 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7788 (set (pc) (label_ref (match_operand 2 "" "")))]
7789 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7791 [(set_attr "op_type" "RI")])
7793 (define_insn "main_base_64"
7794 [(set (match_operand 0 "register_operand" "=a")
7795 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7796 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7798 [(set_attr "op_type" "RIL")
7799 (set_attr "type" "larl")])
7801 (define_insn "main_pool"
7802 [(set (match_operand 0 "register_operand" "=a")
7803 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7804 "GET_MODE (operands[0]) == Pmode"
7809 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7810 (const_string "larl") (const_string "la")))])
7812 (define_insn "reload_base_31"
7813 [(set (match_operand 0 "register_operand" "=a")
7814 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7815 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7816 "basr\t%0,0\;la\t%0,%1-.(%0)"
7817 [(set_attr "length" "6")
7818 (set_attr "type" "la")])
7820 (define_insn "reload_base_64"
7821 [(set (match_operand 0 "register_operand" "=a")
7822 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7823 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7825 [(set_attr "op_type" "RIL")
7826 (set_attr "type" "larl")])
7829 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7834 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7837 ;; Insns related to generating the function prologue and epilogue.
7841 (define_expand "prologue"
7842 [(use (const_int 0))]
7844 "s390_emit_prologue (); DONE;")
7846 (define_expand "epilogue"
7847 [(use (const_int 1))]
7849 "s390_emit_epilogue (false); DONE;")
7851 (define_expand "sibcall_epilogue"
7852 [(use (const_int 0))]
7854 "s390_emit_epilogue (true); DONE;")
7856 (define_insn "*return"
7858 (use (match_operand 0 "register_operand" "a"))]
7859 "GET_MODE (operands[0]) == Pmode"
7861 [(set_attr "op_type" "RR")
7862 (set_attr "type" "jsr")
7863 (set_attr "atype" "agen")])
7866 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7867 ;; pointer. This is used for compatibility.
7869 (define_expand "ptr_extend"
7870 [(set (match_operand:DI 0 "register_operand" "=r")
7871 (match_operand:SI 1 "register_operand" "r"))]
7874 emit_insn (gen_anddi3 (operands[0],
7875 gen_lowpart (DImode, operands[1]),
7876 GEN_INT (0x7fffffff)));
7880 ;; Instruction definition to expand eh_return macro to support
7881 ;; swapping in special linkage return addresses.
7883 (define_expand "eh_return"
7884 [(use (match_operand 0 "register_operand" ""))]
7887 s390_emit_tpf_eh_return (operands[0]);
7892 ; Stack Protector Patterns
7895 (define_expand "stack_protect_set"
7896 [(set (match_operand 0 "memory_operand" "")
7897 (match_operand 1 "memory_operand" ""))]
7900 #ifdef TARGET_THREAD_SSP_OFFSET
7902 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7903 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7906 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7908 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7913 (define_insn "stack_protect_set<mode>"
7914 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7915 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7917 "mvc\t%O0(%G0,%R0),%S1"
7918 [(set_attr "op_type" "SS")])
7920 (define_expand "stack_protect_test"
7921 [(set (reg:CC CC_REGNUM)
7922 (compare (match_operand 0 "memory_operand" "")
7923 (match_operand 1 "memory_operand" "")))
7924 (match_operand 2 "" "")]
7927 #ifdef TARGET_THREAD_SSP_OFFSET
7929 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7930 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7932 s390_compare_op0 = operands[0];
7933 s390_compare_op1 = operands[1];
7934 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7937 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7939 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7941 emit_jump_insn (gen_beq (operands[2]));
7946 (define_insn "stack_protect_test<mode>"
7947 [(set (reg:CCZ CC_REGNUM)
7948 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7949 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7951 "clc\t%O0(%G0,%R0),%S1"
7952 [(set_attr "op_type" "SS")])