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s390.md ("*adddi3_cc", [...]): Use "nonimmediate_operand" instead of "register_operan...
[gcc.git] / gcc / config / s390 / s390.md
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
21
22 ;;
23 ;; Special constraints for s/390 machine description:
24 ;;
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
32 ;;
33 ;; Special formats used for outputting 390 instructions.
34 ;;
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
41 ;;
42 ;; We have a special constraint for pattern matching.
43 ;;
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
45 ;;
46
47
48 ;; Define an insn type attribute. This is used in function unit delay
49 ;; computations.
50
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
53
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
57
58 (define_attr "atype" "reg,mem"
59 (const_string "reg"))
60
61 ;; Generic pipeline function unit.
62
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
65
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
68
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
71
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
74
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
77
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
80
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
83
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
86
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
89
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
92
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
95
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
98
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
101
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
104
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
107
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
110
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
113
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
116
117 ;; Operand type. Used to default length attribute values
118
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
121 (const_string "RX"))
122
123 ;; Length in bytes.
124
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
141 (const_int 4)))
142
143 ;; Define attributes for `asm' insns.
144
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
147
148 ;;
149 ;; Condition Codes
150 ;;
151 ;
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
157
158 ; CCZ -> CCL / CCZ1
159 ; CCZ1 -> CCA/CCU/CCS/CCT
160 ; CCS -> CCA
161
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
164
165
166 ;;
167 ;;- Compare instructions.
168 ;;
169
170 (define_expand "cmpdi"
171 [(set (reg:CC 33)
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
174 "TARGET_64BIT"
175 "
176 {
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
179 DONE;
180 }")
181
182 (define_expand "cmpsi"
183 [(set (reg:CC 33)
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
186 ""
187 "
188 {
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
191 DONE;
192 }")
193
194 (define_expand "cmpdf"
195 [(set (reg:CC 33)
196 (compare:CC (match_operand:DF 0 "register_operand" "")
197 (match_operand:DF 1 "general_operand" "")))]
198 "TARGET_HARD_FLOAT"
199 "
200 {
201 s390_compare_op0 = operands[0];
202 s390_compare_op1 = operands[1];
203 DONE;
204 }")
205
206 (define_expand "cmpsf"
207 [(set (reg:CC 33)
208 (compare:CC (match_operand:SF 0 "register_operand" "")
209 (match_operand:SF 1 "general_operand" "")))]
210 "TARGET_HARD_FLOAT"
211 "
212 {
213 s390_compare_op0 = operands[0];
214 s390_compare_op1 = operands[1];
215 DONE;
216 }")
217
218
219 ; Test-under-Mask (zero_extract) instructions
220
221 (define_insn "*tmdi_ext"
222 [(set (reg 33)
223 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
224 (match_operand:DI 1 "const_int_operand" "n")
225 (match_operand:DI 2 "const_int_operand" "n"))
226 (const_int 0)))]
227 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
228 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
229 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
230 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
231 == INTVAL (operands[2]) >> 4"
232 "*
233 {
234 int part = INTVAL (operands[2]) >> 4;
235 int block = (1 << INTVAL (operands[1])) - 1;
236 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
237
238 operands[2] = GEN_INT (block << shift);
239
240 switch (part)
241 {
242 case 0: return \"tmhh\\t%0,%x2\";
243 case 1: return \"tmhl\\t%0,%x2\";
244 case 2: return \"tmlh\\t%0,%x2\";
245 case 3: return \"tmll\\t%0,%x2\";
246 default: abort ();
247 }
248 }"
249 [(set_attr "op_type" "RI")])
250
251 (define_insn "*tmsi_ext"
252 [(set (reg 33)
253 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
254 (match_operand:SI 1 "const_int_operand" "n")
255 (match_operand:SI 2 "const_int_operand" "n"))
256 (const_int 0)))]
257 "s390_match_ccmode(insn, CCTmode)
258 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
259 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
260 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
261 == INTVAL (operands[2]) >> 4"
262 "*
263 {
264 int part = INTVAL (operands[2]) >> 4;
265 int block = (1 << INTVAL (operands[1])) - 1;
266 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
267
268 operands[2] = GEN_INT (block << shift);
269
270 switch (part)
271 {
272 case 0: return \"tmh\\t%0,%x2\";
273 case 1: return \"tml\\t%0,%x2\";
274 default: abort ();
275 }
276 }"
277 [(set_attr "op_type" "RI")])
278
279 (define_insn "*tmqi_ext"
280 [(set (reg 33)
281 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
282 (match_operand:SI 1 "const_int_operand" "n")
283 (match_operand:SI 2 "const_int_operand" "n"))
284 (const_int 0)))]
285 "s390_match_ccmode(insn, CCTmode)
286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
288 "*
289 {
290 int block = (1 << INTVAL (operands[1])) - 1;
291 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
292
293 operands[2] = GEN_INT (block << shift);
294 return \"tm\\t%0,%b2\";
295 }"
296 [(set_attr "op_type" "SI")
297 (set_attr "atype" "mem")])
298
299 ; Test-under-Mask instructions
300
301 (define_insn "*tmdi_reg"
302 [(set (reg 33)
303 (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
304 (match_operand:DI 1 "immediate_operand" "n"))
305 (match_operand:DI 2 "immediate_operand" "n")))]
306 "TARGET_64BIT
307 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
308 && s390_single_hi (operands[1], DImode, 0) >= 0"
309 "*
310 {
311 int part = s390_single_hi (operands[1], DImode, 0);
312 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
313
314 switch (part)
315 {
316 case 0: return \"tmhh\\t%0,%x1\";
317 case 1: return \"tmhl\\t%0,%x1\";
318 case 2: return \"tmlh\\t%0,%x1\";
319 case 3: return \"tmll\\t%0,%x1\";
320 default: abort ();
321 }
322 }"
323 [(set_attr "op_type" "RI")])
324
325 (define_insn "*tmsi_reg"
326 [(set (reg 33)
327 (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
328 (match_operand:SI 1 "immediate_operand" "n"))
329 (match_operand:SI 2 "immediate_operand" "n")))]
330 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
331 && s390_single_hi (operands[1], SImode, 0) >= 0"
332 "*
333 {
334 int part = s390_single_hi (operands[1], SImode, 0);
335 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
336
337 switch (part)
338 {
339 case 0: return \"tmh\\t%0,%x1\";
340 case 1: return \"tml\\t%0,%x1\";
341 default: abort ();
342 }
343 }"
344 [(set_attr "op_type" "RI")])
345
346 (define_insn "*tmdi_mem"
347 [(set (reg 33)
348 (compare (and:DI (match_operand:DI 0 "memory_operand" "%Q")
349 (match_operand:DI 1 "immediate_operand" "n"))
350 (match_operand:DI 2 "immediate_operand" "n")))]
351 "TARGET_64BIT
352 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
353 && s390_single_qi (operands[1], DImode, 0) >= 0"
354 "*
355 {
356 int part = s390_single_qi (operands[1], DImode, 0);
357 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
358
359 operands[0] = gen_rtx_MEM (QImode,
360 plus_constant (XEXP (operands[0], 0), part));
361 return \"tm\\t%0,%b1\";
362 }"
363 [(set_attr "op_type" "SI")
364 (set_attr "atype" "mem")])
365
366 (define_insn "*tmsi_mem"
367 [(set (reg 33)
368 (compare (and:SI (match_operand:SI 0 "memory_operand" "%Q")
369 (match_operand:SI 1 "immediate_operand" "n"))
370 (match_operand:SI 2 "immediate_operand" "n")))]
371 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
372 && s390_single_qi (operands[1], SImode, 0) >= 0"
373 "*
374 {
375 int part = s390_single_qi (operands[1], SImode, 0);
376 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
377
378 operands[0] = gen_rtx_MEM (QImode,
379 plus_constant (XEXP (operands[0], 0), part));
380 return \"tm\\t%0,%b1\";
381 }"
382 [(set_attr "op_type" "SI")
383 (set_attr "atype" "mem")])
384
385 (define_insn "*tmhi_mem"
386 [(set (reg 33)
387 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "%Q") 0)
388 (match_operand:SI 1 "immediate_operand" "n"))
389 (match_operand:SI 2 "immediate_operand" "n")))]
390 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
391 && s390_single_qi (operands[1], HImode, 0) >= 0"
392 "*
393 {
394 int part = s390_single_qi (operands[1], HImode, 0);
395 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
396
397 operands[0] = gen_rtx_MEM (QImode,
398 plus_constant (XEXP (operands[0], 0), part));
399 return \"tm\\t%0,%b1\";
400 }"
401 [(set_attr "op_type" "SI")
402 (set_attr "atype" "mem")])
403
404 (define_insn "*tmqi_mem"
405 [(set (reg 33)
406 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "%Q") 0)
407 (match_operand:SI 1 "immediate_operand" "n"))
408 (match_operand:SI 2 "immediate_operand" "n")))]
409 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
410 "tm\\t%0,%b1"
411 [(set_attr "op_type" "SI")
412 (set_attr "atype" "mem")])
413
414 (define_insn "*tmhi_full"
415 [(set (reg 33)
416 (compare (match_operand:HI 0 "register_operand" "d")
417 (match_operand:HI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
419 "tml\\t%0,65535"
420 [(set_attr "op_type" "RX")])
421
422 (define_insn "*tmqi_full"
423 [(set (reg 33)
424 (compare (match_operand:QI 0 "register_operand" "d")
425 (match_operand:QI 1 "immediate_operand" "n")))]
426 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
427 "tml\\t%0,255"
428 [(set_attr "op_type" "RI")])
429
430
431 ; Load-and-Test instructions
432
433 (define_insn "*tstdi_sign"
434 [(set (reg 33)
435 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
436 (const_int 32)) (const_int 32))
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
439 (sign_extend:DI (match_dup 0)))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
441 "ltgfr\\t%2,%0"
442 [(set_attr "op_type" "RRE")])
443
444 (define_insn "*tstdi"
445 [(set (reg 33)
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))
448 (set (match_operand:DI 2 "register_operand" "=d")
449 (match_dup 0))]
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
451 "ltgr\\t%2,%0"
452 [(set_attr "op_type" "RRE")])
453
454 (define_insn "*tstdi_cconly"
455 [(set (reg 33)
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
459 "ltgr\\t%0,%0"
460 [(set_attr "op_type" "RRE")])
461
462 (define_insn "*tstdi_cconly_31"
463 [(set (reg 33)
464 (compare (match_operand:DI 0 "register_operand" "d")
465 (match_operand:DI 1 "const0_operand" "")))]
466 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
467 "srda\\t%0,0"
468 [(set_attr "op_type" "RS")])
469
470 (define_insn "*tstsi"
471 [(set (reg 33)
472 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
473 (match_operand:SI 1 "const0_operand" "")))
474 (set (match_operand:SI 2 "register_operand" "=d,d")
475 (match_dup 0))]
476 "s390_match_ccmode(insn, CCSmode)"
477 "@
478 ltr\\t%2,%0
479 icm\\t%2,15,%0"
480 [(set_attr "op_type" "RR,RS")
481 (set_attr "atype" "reg,mem")])
482
483 (define_insn "*tstsi_cconly"
484 [(set (reg 33)
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
486 (match_operand:SI 1 "const0_operand" "")))
487 (clobber (match_scratch:SI 2 "=X,d"))]
488 "s390_match_ccmode(insn, CCSmode)"
489 "@
490 ltr\\t%0,%0
491 icm\\t%2,15,%0"
492 [(set_attr "op_type" "RR,RS")
493 (set_attr "atype" "reg,mem")])
494
495 (define_insn "*tstsi_cconly2"
496 [(set (reg 33)
497 (compare (match_operand:SI 0 "register_operand" "d")
498 (match_operand:SI 1 "const0_operand" "")))]
499 "s390_match_ccmode(insn, CCSmode)"
500 "ltr\\t%0,%0"
501 [(set_attr "op_type" "RR")])
502
503 (define_insn "*tsthi"
504 [(set (reg 33)
505 (compare (match_operand:HI 0 "s_operand" "Q")
506 (match_operand:HI 1 "const0_operand" "")))
507 (set (match_operand:HI 2 "register_operand" "=d")
508 (match_dup 0))]
509 "s390_match_ccmode(insn, CCSmode)"
510 "icm\\t%2,3,%0"
511 [(set_attr "op_type" "RS")
512 (set_attr "atype" "mem")])
513
514 (define_insn "*tsthi_cconly"
515 [(set (reg 33)
516 (compare (match_operand:HI 0 "s_operand" "Q")
517 (match_operand:HI 1 "const0_operand" "")))
518 (clobber (match_scratch:HI 2 "=d"))]
519 "s390_match_ccmode(insn, CCSmode)"
520 "icm\\t%2,3,%0"
521 [(set_attr "op_type" "RS")
522 (set_attr "atype" "mem")])
523
524 (define_insn "*tstqi"
525 [(set (reg 33)
526 (compare (match_operand:QI 0 "s_operand" "Q")
527 (match_operand:QI 1 "const0_operand" "")))
528 (set (match_operand:QI 2 "register_operand" "=d")
529 (match_dup 0))]
530 "s390_match_ccmode(insn, CCSmode)"
531 "icm\\t%2,1,%0"
532 [(set_attr "op_type" "RS")
533 (set_attr "atype" "mem")])
534
535 (define_insn "*tstqi_cconly"
536 [(set (reg 33)
537 (compare (match_operand:QI 0 "s_operand" "Q")
538 (match_operand:QI 1 "const0_operand" "")))
539 (clobber (match_scratch:QI 2 "=d"))]
540 "s390_match_ccmode(insn, CCSmode)"
541 "icm\\t%2,1,%0"
542 [(set_attr "op_type" "RS")
543 (set_attr "atype" "mem")])
544
545
546 ; Compare (signed) instructions
547
548 (define_insn "*cmpdi_ccs_sign"
549 [(set (reg 33)
550 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
551 (match_operand:DI 0 "register_operand" "d,d")))]
552 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
553 "@
554 cgfr\\t%0,%1
555 cgf\\t%0,%1"
556 [(set_attr "op_type" "RRE,RXE")
557 (set_attr "atype" "reg,mem")])
558
559 (define_insn "*cmpdi_ccs"
560 [(set (reg 33)
561 (compare (match_operand:DI 0 "register_operand" "d,d,d")
562 (match_operand:DI 1 "general_operand" "d,K,m")))]
563 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
564 "@
565 cgr\\t%0,%1
566 cghi\\t%0,%c1
567 cg\\t%0,%1"
568 [(set_attr "op_type" "RRE,RI,RXE")
569 (set_attr "atype" "reg,reg,mem")])
570
571 (define_insn "*cmpsi_ccs_sign"
572 [(set (reg 33)
573 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
574 (match_operand:SI 0 "register_operand" "d")))]
575 "s390_match_ccmode(insn, CCSRmode)"
576 "ch\\t%0,%1"
577 [(set_attr "op_type" "RX")
578 (set_attr "atype" "mem")])
579
580 (define_insn "*cmpsi_ccs"
581 [(set (reg 33)
582 (compare (match_operand:SI 0 "register_operand" "d,d,d")
583 (match_operand:SI 1 "general_operand" "d,K,m")))]
584 "s390_match_ccmode(insn, CCSmode)"
585 "@
586 cr\\t%0,%1
587 chi\\t%0,%c1
588 c\\t%0,%1"
589 [(set_attr "op_type" "RR,RI,RX")
590 (set_attr "atype" "reg,reg,mem")])
591
592
593 ; Compare (unsigned) instructions
594
595 (define_insn "*cmpdi_ccu_zero"
596 [(set (reg 33)
597 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
598 (match_operand:DI 0 "register_operand" "d,d")))]
599 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
600 "@
601 clgfr\\t%0,%1
602 clgf\\t%0,%1"
603 [(set_attr "op_type" "RRE,RXE")
604 (set_attr "atype" "reg,mem")])
605
606 (define_insn "*cmpdi_ccu"
607 [(set (reg 33)
608 (compare (match_operand:DI 0 "register_operand" "d,d")
609 (match_operand:DI 1 "general_operand" "d,m")))]
610 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
611 "@
612 clgr\\t%0,%1
613 clg\\t%0,%1"
614 [(set_attr "op_type" "RRE,RXE")
615 (set_attr "atype" "reg,mem")])
616
617 (define_insn "*cmpsi_ccu"
618 [(set (reg 33)
619 (compare (match_operand:SI 0 "register_operand" "d,d")
620 (match_operand:SI 1 "general_operand" "d,m")))]
621 "s390_match_ccmode(insn, CCUmode)"
622 "@
623 clr\\t%0,%1
624 cl\\t%0,%1"
625 [(set_attr "op_type" "RR,RX")
626 (set_attr "atype" "reg,mem")])
627
628 (define_insn "*cmphi_ccu"
629 [(set (reg 33)
630 (compare (match_operand:HI 0 "register_operand" "d")
631 (match_operand:HI 1 "s_imm_operand" "Q")))]
632 "s390_match_ccmode(insn, CCUmode)"
633 "clm\\t%0,3,%1"
634 [(set_attr "op_type" "RS")
635 (set_attr "atype" "mem")])
636
637 (define_insn "*cmpqi_ccu"
638 [(set (reg 33)
639 (compare (match_operand:QI 0 "register_operand" "d")
640 (match_operand:QI 1 "s_imm_operand" "Q")))]
641 "s390_match_ccmode(insn, CCUmode)"
642 "clm\\t%0,1,%1"
643 [(set_attr "op_type" "RS")
644 (set_attr "atype" "mem")])
645
646 (define_insn "*cli"
647 [(set (reg 33)
648 (compare (match_operand:QI 0 "memory_operand" "Q")
649 (match_operand:QI 1 "immediate_operand" "n")))]
650 "s390_match_ccmode (insn, CCUmode)"
651 "cli\\t%0,%b1"
652 [(set_attr "op_type" "SI")
653 (set_attr "atype" "mem")])
654
655 (define_insn "*cmpdi_ccu_mem"
656 [(set (reg 33)
657 (compare (match_operand:DI 0 "s_operand" "Q")
658 (match_operand:DI 1 "s_imm_operand" "Q")))]
659 "s390_match_ccmode(insn, CCUmode)"
660 "clc\\t%O0(8,%R0),%1"
661 [(set_attr "op_type" "SS")
662 (set_attr "atype" "mem")])
663
664 (define_insn "*cmpsi_ccu_mem"
665 [(set (reg 33)
666 (compare (match_operand:SI 0 "s_operand" "Q")
667 (match_operand:SI 1 "s_imm_operand" "Q")))]
668 "s390_match_ccmode(insn, CCUmode)"
669 "clc\\t%O0(4,%R0),%1"
670 [(set_attr "op_type" "SS")
671 (set_attr "atype" "mem")])
672
673 (define_insn "*cmphi_ccu_mem"
674 [(set (reg 33)
675 (compare (match_operand:HI 0 "s_operand" "Q")
676 (match_operand:HI 1 "s_imm_operand" "Q")))]
677 "s390_match_ccmode(insn, CCUmode)"
678 "clc\\t%O0(2,%R0),%1"
679 [(set_attr "op_type" "SS")
680 (set_attr "atype" "mem")])
681
682 (define_insn "*cmpqi_ccu_mem"
683 [(set (reg 33)
684 (compare (match_operand:QI 0 "s_operand" "Q")
685 (match_operand:QI 1 "s_imm_operand" "Q")))]
686 "s390_match_ccmode(insn, CCUmode)"
687 "clc\\t%O0(1,%R0),%1"
688 [(set_attr "op_type" "SS")
689 (set_attr "atype" "mem")])
690
691
692 ; DF instructions
693
694 (define_insn "*cmpdf_ccs_0"
695 [(set (reg 33)
696 (compare (match_operand:DF 0 "register_operand" "f")
697 (match_operand:DF 1 "const0_operand" "")))]
698 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
699 "ltdbr\\t%0,%0"
700 [(set_attr "op_type" "RRE")])
701
702 (define_insn "*cmpdf_ccs_0_ibm"
703 [(set (reg 33)
704 (compare (match_operand:DF 0 "register_operand" "f")
705 (match_operand:DF 1 "const0_operand" "")))]
706 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
707 "ltdr\\t%0,%0"
708 [(set_attr "op_type" "RR")])
709
710 (define_insn "*cmpdf_ccs"
711 [(set (reg 33)
712 (compare (match_operand:DF 0 "register_operand" "f,f")
713 (match_operand:DF 1 "general_operand" "f,m")))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
715 "@
716 cdbr\\t%0,%1
717 cdb\\t%0,%1"
718 [(set_attr "op_type" "RRE,RXE")
719 (set_attr "atype" "reg,mem")])
720
721 (define_insn "*cmpdf_ccs_ibm"
722 [(set (reg 33)
723 (compare (match_operand:DF 0 "register_operand" "f,f")
724 (match_operand:DF 1 "general_operand" "f,m")))]
725 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
726 "@
727 cdr\\t%0,%1
728 cd\\t%0,%1"
729 [(set_attr "op_type" "RR,RX")
730 (set_attr "atype" "reg,mem")])
731
732
733 ; SF instructions
734
735 (define_insn "*cmpsf_ccs_0"
736 [(set (reg 33)
737 (compare (match_operand:SF 0 "register_operand" "f")
738 (match_operand:SF 1 "const0_operand" "")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
740 "ltebr\\t%0,%0"
741 [(set_attr "op_type" "RRE")])
742
743 (define_insn "*cmpsf_ccs_0_ibm"
744 [(set (reg 33)
745 (compare (match_operand:SF 0 "register_operand" "f")
746 (match_operand:SF 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
748 "lter\\t%0,%0"
749 [(set_attr "op_type" "RR")])
750
751 (define_insn "*cmpsf_ccs"
752 [(set (reg 33)
753 (compare (match_operand:SF 0 "register_operand" "f,f")
754 (match_operand:SF 1 "general_operand" "f,m")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
756 "@
757 cebr\\t%0,%1
758 ceb\\t%0,%1"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "atype" "reg,mem")])
761
762 (define_insn "*cmpsf_ccs"
763 [(set (reg 33)
764 (compare (match_operand:SF 0 "register_operand" "f,f")
765 (match_operand:SF 1 "general_operand" "f,m")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
767 "@
768 cer\\t%0,%1
769 ce\\t%0,%1"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "atype" "reg,mem")])
772
773
774 ;;
775 ;;- Move instructions.
776 ;;
777
778 ;
779 ; movti instruction pattern(s).
780 ;
781
782 (define_insn "movti"
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
784 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
785 "TARGET_64BIT"
786 "@
787 lmg\\t%0,%N0,%1
788 stmg\\t%1,%N1,%0
789 #
790 #
791 mvc\\t%O0(16,%R0),%1"
792 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
793 (set_attr "atype" "mem")])
794
795 (define_split
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && !s_operand (operands[0], VOIDmode)
800 && !s_operand (operands[1], VOIDmode)
801 && (register_operand (operands[0], VOIDmode)
802 || register_operand (operands[1], VOIDmode))
803 && (!register_operand (operands[0], VOIDmode)
804 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
805 operands[1])
806 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
807 operands[1]))"
808 [(set (match_dup 2) (match_dup 4))
809 (set (match_dup 3) (match_dup 5))]
810 "
811 {
812 if (!register_operand (operands[0], VOIDmode)
813 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
814 operands[1]))
815 {
816 operands[2] = operand_subword (operands[0], 0, 0, TImode);
817 operands[3] = operand_subword (operands[0], 1, 0, TImode);
818 operands[4] = operand_subword (operands[1], 0, 0, TImode);
819 operands[5] = operand_subword (operands[1], 1, 0, TImode);
820 }
821 else
822 {
823 operands[2] = operand_subword (operands[0], 1, 0, TImode);
824 operands[3] = operand_subword (operands[0], 0, 0, TImode);
825 operands[4] = operand_subword (operands[1], 1, 0, TImode);
826 operands[5] = operand_subword (operands[1], 0, 0, TImode);
827 }
828 }")
829
830 (define_split
831 [(set (match_operand:TI 0 "register_operand" "")
832 (match_operand:TI 1 "memory_operand" ""))]
833 "TARGET_64BIT && reload_completed
834 && !s_operand (operands[1], VOIDmode)"
835 [(set (match_dup 2) (match_dup 3))
836 (set (match_dup 0) (mem:TI (match_dup 2)))]
837 "operands[2] = operand_subword (operands[0], 1, 0, TImode);
838 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
839
840 ;
841 ; movdi instruction pattern(s).
842 ;
843
844 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
845 ;; move to get the address of the symbolic object from the GOT.
846
847 (define_expand "movdi"
848 [(set (match_operand:DI 0 "general_operand" "")
849 (match_operand:DI 1 "general_operand" ""))]
850 ""
851 "
852 {
853 /* Handle PIC symbolic constants. */
854 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
855 emit_pic_move (operands, DImode);
856
857 /* During and after reload, we need to force constants
858 to the literal pool ourselves, if necessary. */
859 if ((reload_in_progress || reload_completed)
860 && CONSTANT_P (operands[1])
861 && (!legitimate_reload_constant_p (operands[1])
862 || fp_operand (operands[0], VOIDmode)))
863 operands[1] = force_const_mem (DImode, operands[1]);
864 }")
865
866 (define_insn "*movdi_lhi"
867 [(set (match_operand:DI 0 "register_operand" "=d")
868 (match_operand:DI 1 "immediate_operand" "K"))]
869 "TARGET_64BIT
870 && GET_CODE (operands[1]) == CONST_INT
871 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
872 && !fp_operand (operands[0], VOIDmode)"
873 "lghi\\t%0,%h1"
874 [(set_attr "op_type" "RI")
875 (set_attr "atype" "reg")])
876
877 (define_insn "*movdi_lli"
878 [(set (match_operand:DI 0 "register_operand" "=d")
879 (match_operand:DI 1 "immediate_operand" "n"))]
880 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
881 && !fp_operand (operands[0], VOIDmode)"
882 "*
883 {
884 int part = s390_single_hi (operands[1], DImode, 0);
885 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
886
887 switch (part)
888 {
889 case 0: return \"llihh\\t%0,%x1\";
890 case 1: return \"llihl\\t%0,%x1\";
891 case 2: return \"llilh\\t%0,%x1\";
892 case 3: return \"llill\\t%0,%x1\";
893 default: abort ();
894 }
895 }"
896 [(set_attr "op_type" "RI")
897 (set_attr "atype" "reg")])
898
899 (define_insn "*movdi_larl"
900 [(set (match_operand:DI 0 "register_operand" "=d")
901 (match_operand:DI 1 "larl_operand" "X"))]
902 "TARGET_64BIT
903 && !fp_operand (operands[0], VOIDmode)"
904 "larl\\t%0,%1"
905 [(set_attr "op_type" "RIL")
906 (set_attr "atype" "reg")
907 (set_attr "type" "la")])
908
909 (define_insn "*movdi_64"
910 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
911 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
912 "TARGET_64BIT"
913 "@
914 lgr\\t%0,%1
915 lg\\t%0,%1
916 stg\\t%1,%0
917 ldr\\t%0,%1
918 ld\\t%0,%1
919 std\\t%1,%0
920 mvc\\t%O0(8,%R0),%1"
921 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX,SS")
922 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
923
924 (define_insn "*movdi_31"
925 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
926 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
927 "!TARGET_64BIT"
928 "@
929 lm\\t%0,%N0,%1
930 stm\\t%1,%N1,%0
931 #
932 #
933 ldr\\t%0,%1
934 ld\\t%0,%1
935 std\\t%1,%0
936 mvc\\t%O0(8,%R0),%1"
937 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
938 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
939
940 (define_split
941 [(set (match_operand:DI 0 "nonimmediate_operand" "")
942 (match_operand:DI 1 "general_operand" ""))]
943 "!TARGET_64BIT && reload_completed
944 && !fp_operand (operands[0], VOIDmode)
945 && !fp_operand (operands[1], VOIDmode)
946 && !s_operand (operands[0], VOIDmode)
947 && !s_operand (operands[1], VOIDmode)
948 && (register_operand (operands[0], VOIDmode)
949 || register_operand (operands[1], VOIDmode))
950 && (!register_operand (operands[0], VOIDmode)
951 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
952 operands[1])
953 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
954 operands[1]))"
955 [(set (match_dup 2) (match_dup 4))
956 (set (match_dup 3) (match_dup 5))]
957 "
958 {
959 if (!register_operand (operands[0], VOIDmode)
960 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
961 operands[1]))
962 {
963 operands[2] = operand_subword (operands[0], 0, 0, DImode);
964 operands[3] = operand_subword (operands[0], 1, 0, DImode);
965 operands[4] = operand_subword (operands[1], 0, 0, DImode);
966 operands[5] = operand_subword (operands[1], 1, 0, DImode);
967 }
968 else
969 {
970 operands[2] = operand_subword (operands[0], 1, 0, DImode);
971 operands[3] = operand_subword (operands[0], 0, 0, DImode);
972 operands[4] = operand_subword (operands[1], 1, 0, DImode);
973 operands[5] = operand_subword (operands[1], 0, 0, DImode);
974 }
975 }")
976
977 (define_split
978 [(set (match_operand:DI 0 "register_operand" "")
979 (match_operand:DI 1 "memory_operand" ""))]
980 "!TARGET_64BIT && reload_completed
981 && !fp_operand (operands[0], VOIDmode)
982 && !fp_operand (operands[1], VOIDmode)
983 && !s_operand (operands[1], VOIDmode)"
984 [(set (match_dup 2) (match_dup 3))
985 (set (match_dup 0) (mem:DI (match_dup 2)))]
986 "operands[2] = operand_subword (operands[0], 1, 0, DImode);
987 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
988
989 ;
990 ; movsi instruction pattern(s).
991 ;
992
993 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
994 ;; move to get the address of the symbolic object from the GOT.
995
996 (define_expand "movsi"
997 [(set (match_operand:SI 0 "general_operand" "")
998 (match_operand:SI 1 "general_operand" ""))]
999 ""
1000 "
1001 {
1002 /* Handle PIC symbolic constants. */
1003 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1004 emit_pic_move (operands, SImode);
1005
1006 /* expr.c tries to load an effective address using
1007 force_reg. This fails because we don't have a
1008 generic load_address pattern. Convert the move
1009 to a proper arithmetic operation instead, unless
1010 it is guaranteed to be OK. */
1011 if (GET_CODE (operands[1]) == PLUS
1012 && !legitimate_la_operand_p (operands[1]))
1013 {
1014 operands[1] = force_operand (operands[1], operands[0]);
1015 if (operands[1] == operands[0])
1016 DONE;
1017 }
1018
1019 /* During and after reload, we need to force constants
1020 to the literal pool ourselves, if necessary. */
1021 if ((reload_in_progress || reload_completed)
1022 && CONSTANT_P (operands[1])
1023 && (!legitimate_reload_constant_p (operands[1])
1024 || fp_operand (operands[0], VOIDmode)))
1025 operands[1] = force_const_mem (SImode, operands[1]);
1026 }")
1027
1028 (define_insn "*movsi_lhi"
1029 [(set (match_operand:SI 0 "register_operand" "=d")
1030 (match_operand:SI 1 "immediate_operand" "K"))]
1031 "GET_CODE (operands[1]) == CONST_INT
1032 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1033 && !fp_operand (operands[0], VOIDmode)"
1034 "lhi\\t%0,%h1"
1035 [(set_attr "op_type" "RI")])
1036
1037 (define_insn "*movsi_lli"
1038 [(set (match_operand:SI 0 "register_operand" "=d")
1039 (match_operand:SI 1 "immediate_operand" "n"))]
1040 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1041 && !fp_operand (operands[0], VOIDmode)"
1042 "*
1043 {
1044 int part = s390_single_hi (operands[1], SImode, 0);
1045 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1046
1047 switch (part)
1048 {
1049 case 0: return \"llilh\\t%0,%x1\";
1050 case 1: return \"llill\\t%0,%x1\";
1051 default: abort ();
1052 }
1053 }"
1054 [(set_attr "op_type" "RI")])
1055
1056 (define_insn "*movsi"
1057 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1058 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1059 ""
1060 "@
1061 lr\\t%0,%1
1062 l\\t%0,%1
1063 st\\t%1,%0
1064 ler\\t%0,%1
1065 le\\t%0,%1
1066 ste\\t%1,%0
1067 mvc\\t%O0(4,%R0),%1"
1068 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1069 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1070
1071
1072 ;
1073 ; movhi instruction pattern(s).
1074 ;
1075
1076 (define_insn "movhi"
1077 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1078 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1079 ""
1080 "@
1081 lr\\t%0,%1
1082 lhi\\t%0,%h1
1083 lh\\t%0,%1
1084 sth\\t%1,%0
1085 mvc\\t%O0(2,%R0),%1"
1086 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1087 (set_attr "atype" "reg,reg,mem,mem,mem")])
1088
1089
1090 ;
1091 ; movqi instruction pattern(s).
1092 ;
1093
1094 (define_insn "movqi_64"
1095 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1096 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1097 "TARGET_64BIT"
1098 "@
1099 lr\\t%0,%1
1100 lhi\\t%0,%b1
1101 llgc\\t%0,%1
1102 stc\\t%1,%0
1103 mvi\\t%0,%b1
1104 mvc\\t%O0(1,%R0),%1"
1105 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1106 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1107
1108
1109 (define_insn "movqi"
1110 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1111 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1112 ""
1113 "@
1114 lr\\t%0,%1
1115 lhi\\t%0,%b1
1116 ic\\t%0,%1
1117 stc\\t%1,%0
1118 mvi\\t%0,%b1
1119 mvc\\t%O0(1,%R0),%1"
1120 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1121 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1122
1123
1124 ;
1125 ; moveqstrictqi instruction pattern(s).
1126 ;
1127
1128 (define_insn "*movstrictqi"
1129 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1130 (match_operand:QI 1 "memory_operand" "m"))]
1131 ""
1132 "ic\\t%0,%1"
1133 [(set_attr "op_type" "RX")
1134 (set_attr "atype" "mem")])
1135
1136 ;
1137 ; movstricthi instruction pattern(s).
1138 ;
1139
1140 (define_insn "*movstricthi"
1141 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1142 (match_operand:HI 1 "s_imm_operand" "Q"))
1143 (clobber (reg:CC 33))]
1144 ""
1145 "icm\\t%0,3,%1"
1146 [(set_attr "op_type" "RS")
1147 (set_attr "atype" "mem")])
1148
1149
1150 ;
1151 ; movstrictsi instruction pattern(s).
1152 ;
1153
1154 (define_insn "movestrictsi"
1155 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1156 (match_operand:SI 1 "general_operand" "d,m"))]
1157 "TARGET_64BIT"
1158 "@
1159 lr\\t%0,%1
1160 l\\t%0,%1"
1161 [(set_attr "op_type" "RR,RS")
1162 (set_attr "atype" "reg,mem")])
1163
1164
1165 ;
1166 ; movdf instruction pattern(s).
1167 ;
1168
1169 (define_expand "movdf"
1170 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1171 (match_operand:DF 1 "general_operand" ""))]
1172 ""
1173 "
1174 {
1175 /* During and after reload, we need to force constants
1176 to the literal pool ourselves, if necessary. */
1177 if ((reload_in_progress || reload_completed)
1178 && CONSTANT_P (operands[1]))
1179 operands[1] = force_const_mem (DFmode, operands[1]);
1180 }")
1181
1182 (define_insn "*movdf_64"
1183 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1184 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1185 "TARGET_64BIT"
1186 "@
1187 ldr\\t%0,%1
1188 ld\\t%0,%1
1189 std\\t%1,%0
1190 lgr\\t%0,%1
1191 lg\\t%0,%1
1192 stg\\t%1,%0
1193 mvc\\t%O0(8,%R0),%1"
1194 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE,SS")
1195 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1196
1197 (define_insn "*movdf_31"
1198 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1199 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1200 "!TARGET_64BIT"
1201 "@
1202 ldr\\t%0,%1
1203 ld\\t%0,%1
1204 std\\t%1,%0
1205 lm\\t%0,%N0,%1
1206 stm\\t%1,%N1,%0
1207 #
1208 #
1209 mvc\\t%O0(8,%R0),%1"
1210 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1211 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
1212
1213 (define_split
1214 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1215 (match_operand:DF 1 "general_operand" ""))]
1216 "!TARGET_64BIT && reload_completed
1217 && !fp_operand (operands[0], VOIDmode)
1218 && !fp_operand (operands[1], VOIDmode)
1219 && !s_operand (operands[0], VOIDmode)
1220 && !s_operand (operands[1], VOIDmode)
1221 && (register_operand (operands[0], VOIDmode)
1222 || register_operand (operands[1], VOIDmode))
1223 && (!register_operand (operands[0], VOIDmode)
1224 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1225 operands[1])
1226 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1227 operands[1]))"
1228 [(set (match_dup 2) (match_dup 4))
1229 (set (match_dup 3) (match_dup 5))]
1230 "
1231 {
1232 if (!register_operand (operands[0], VOIDmode)
1233 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1234 operands[1]))
1235 {
1236 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1237 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1238 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1239 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1240 }
1241 else
1242 {
1243 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1244 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1245 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1246 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1247 }
1248 }")
1249
1250 (define_split
1251 [(set (match_operand:DF 0 "register_operand" "")
1252 (match_operand:DF 1 "memory_operand" ""))]
1253 "!TARGET_64BIT && reload_completed
1254 && !fp_operand (operands[0], VOIDmode)
1255 && !fp_operand (operands[1], VOIDmode)
1256 && !s_operand (operands[1], VOIDmode)"
1257 [(set (match_dup 2) (match_dup 3))
1258 (set (match_dup 0) (mem:DI (match_dup 2)))]
1259 "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1260 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1261
1262 ;
1263 ; movsf instruction pattern(s).
1264 ;
1265
1266 (define_expand "movsf"
1267 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1268 (match_operand:SF 1 "general_operand" ""))]
1269 ""
1270 "
1271 {
1272 /* During and after reload, we need to force constants
1273 to the literal pool ourselves, if necessary. */
1274 if ((reload_in_progress || reload_completed)
1275 && CONSTANT_P (operands[1]))
1276 operands[1] = force_const_mem (SFmode, operands[1]);
1277 }")
1278
1279 (define_insn "*movsf"
1280 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1281 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1282 ""
1283 "@
1284 ler\\t%0,%1
1285 le\\t%0,%1
1286 ste\\t%1,%0
1287 lr\\t%0,%1
1288 l\\t%0,%1
1289 st\\t%1,%0
1290 mvc\\t%O0(4,%R0),%1"
1291 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1292 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1293
1294 ;
1295 ; load_multiple pattern(s).
1296 ;
1297
1298 (define_expand "load_multiple"
1299 [(match_par_dup 3 [(set (match_operand 0 "" "")
1300 (match_operand 1 "" ""))
1301 (use (match_operand 2 "" ""))])]
1302 ""
1303 "
1304 {
1305 int regno;
1306 int count;
1307 rtx from;
1308 int i, off;
1309
1310 /* Support only loading a constant number of fixed-point registers from
1311 memory and only bother with this if more than two */
1312 if (GET_CODE (operands[2]) != CONST_INT
1313 || INTVAL (operands[2]) < 2
1314 || INTVAL (operands[2]) > 16
1315 || GET_CODE (operands[1]) != MEM
1316 || GET_CODE (operands[0]) != REG
1317 || REGNO (operands[0]) >= 16)
1318 FAIL;
1319
1320 count = INTVAL (operands[2]);
1321 regno = REGNO (operands[0]);
1322
1323 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1324 if (no_new_pseudos)
1325 {
1326 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1327 {
1328 from = XEXP (operands[1], 0);
1329 off = 0;
1330 }
1331 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1332 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1333 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1334 {
1335 from = XEXP (XEXP (operands[1], 0), 0);
1336 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1337 }
1338 else
1339 FAIL;
1340
1341 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1342 FAIL;
1343 }
1344 else
1345 {
1346 from = force_reg (Pmode, XEXP (operands[1], 0));
1347 off = 0;
1348 }
1349
1350 for (i = 0; i < count; i++)
1351 XVECEXP (operands[3], 0, i)
1352 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1353 change_address (operands[1], Pmode,
1354 plus_constant (from,
1355 off + i * UNITS_PER_WORD)));
1356 }")
1357
1358 (define_insn "*load_multiple_di"
1359 [(match_parallel 0 "load_multiple_operation"
1360 [(set (match_operand:DI 1 "register_operand" "=r")
1361 (match_operand:DI 2 "s_operand" "Q"))])]
1362 ""
1363 "*
1364 {
1365 int words = XVECLEN (operands[0], 0);
1366
1367 if (XVECLEN (operands[0], 0) == 1)
1368 return \"lg\\t%1,0(%2)\";
1369
1370 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1371 return \"lmg\\t%1,%0,%2\";
1372 }"
1373 [(set_attr "op_type" "RXE")
1374 (set_attr "atype" "mem")
1375 (set_attr "type" "lm")])
1376
1377 (define_insn "*load_multiple_si"
1378 [(match_parallel 0 "load_multiple_operation"
1379 [(set (match_operand:SI 1 "register_operand" "=r")
1380 (match_operand:SI 2 "s_operand" "Q"))])]
1381 ""
1382 "*
1383 {
1384 int words = XVECLEN (operands[0], 0);
1385
1386 if (XVECLEN (operands[0], 0) == 1)
1387 return \"l\\t%1,0(%2)\";
1388
1389 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1390 return \"lm\\t%1,%0,%2\";
1391 }"
1392 [(set_attr "op_type" "RXE")
1393 (set_attr "atype" "mem")
1394 (set_attr "type" "lm")])
1395
1396 ;
1397 ; store multiple pattern(s).
1398 ;
1399
1400 (define_expand "store_multiple"
1401 [(match_par_dup 3 [(set (match_operand 0 "" "")
1402 (match_operand 1 "" ""))
1403 (use (match_operand 2 "" ""))])]
1404 ""
1405 "
1406 {
1407 int regno;
1408 int count;
1409 rtx to;
1410 int i, off;
1411
1412 /* Support only storing a constant number of fixed-point registers to
1413 memory and only bother with this if more than two. */
1414 if (GET_CODE (operands[2]) != CONST_INT
1415 || INTVAL (operands[2]) < 2
1416 || INTVAL (operands[2]) > 16
1417 || GET_CODE (operands[0]) != MEM
1418 || GET_CODE (operands[1]) != REG
1419 || REGNO (operands[1]) >= 16)
1420 FAIL;
1421
1422 count = INTVAL (operands[2]);
1423 regno = REGNO (operands[1]);
1424
1425 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1426
1427 if (no_new_pseudos)
1428 {
1429 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1430 {
1431 to = XEXP (operands[0], 0);
1432 off = 0;
1433 }
1434 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1435 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1436 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1437 {
1438 to = XEXP (XEXP (operands[0], 0), 0);
1439 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1440 }
1441 else
1442 FAIL;
1443
1444 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1445 FAIL;
1446 }
1447 else
1448 {
1449 to = force_reg (Pmode, XEXP (operands[0], 0));
1450 off = 0;
1451 }
1452
1453 for (i = 0; i < count; i++)
1454 XVECEXP (operands[3], 0, i)
1455 = gen_rtx_SET (VOIDmode,
1456 change_address (operands[0], Pmode,
1457 plus_constant (to,
1458 off + i * UNITS_PER_WORD)),
1459 gen_rtx_REG (Pmode, regno + i));
1460 }")
1461
1462 (define_insn "*store_multiple_di"
1463 [(match_parallel 0 "store_multiple_operation"
1464 [(set (match_operand:DI 1 "s_operand" "=Q")
1465 (match_operand:DI 2 "register_operand" "r"))])]
1466 ""
1467 "*
1468 {
1469 int words = XVECLEN (operands[0], 0);
1470
1471 if (XVECLEN (operands[0], 0) == 1)
1472 return \"stg\\t%1,0(%2)\";
1473
1474 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1475 return \"stmg\\t%2,%0,%1\";
1476 }"
1477 [(set_attr "op_type" "RXE")
1478 (set_attr "atype" "mem")
1479 (set_attr "type" "stm")])
1480
1481
1482 (define_insn "*store_multiple_si"
1483 [(match_parallel 0 "store_multiple_operation"
1484 [(set (match_operand:SI 1 "s_operand" "=Q")
1485 (match_operand:SI 2 "register_operand" "r"))])]
1486 ""
1487 "*
1488 {
1489 int words = XVECLEN (operands[0], 0);
1490
1491 if (XVECLEN (operands[0], 0) == 1)
1492 return \"st\\t%1,0(%2)\";
1493
1494 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1495 return \"stm\\t%2,%0,%1\";
1496 }"
1497 [(set_attr "op_type" "RXE")
1498 (set_attr "atype" "mem")
1499 (set_attr "type" "stm")])
1500
1501 ;;
1502 ;; String instructions.
1503 ;;
1504
1505 ;
1506 ; movstrdi instruction pattern(s).
1507 ;
1508
1509 (define_expand "movstrdi"
1510 [(set (match_operand:BLK 0 "general_operand" "")
1511 (match_operand:BLK 1 "general_operand" ""))
1512 (use (match_operand:DI 2 "general_operand" ""))
1513 (match_operand 3 "" "")]
1514 "TARGET_64BIT"
1515 "
1516 {
1517 rtx addr0, addr1;
1518
1519 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1520 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1521
1522 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1523 {
1524 operands[0] = change_address (operands[0], VOIDmode, addr0);
1525 operands[1] = change_address (operands[1], VOIDmode, addr1);
1526 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1527
1528 emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2]));
1529 DONE;
1530 }
1531 else
1532 {
1533 if (TARGET_MVCLE)
1534 {
1535 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1536 rtx reg0 = gen_reg_rtx (TImode);
1537 rtx reg1 = gen_reg_rtx (TImode);
1538 rtx len = operands[2];
1539
1540 if (! CONSTANT_P (len))
1541 len = force_reg (DImode, len);
1542
1543 /* Load up the address+length pairs. */
1544
1545 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1546 emit_move_insn (gen_lowpart (DImode, reg0), len);
1547
1548 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1549 emit_move_insn (gen_lowpart (DImode, reg1), len);
1550
1551 /* MOVE */
1552 emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1553 DONE;
1554 }
1555 else
1556 {
1557 rtx label1 = gen_label_rtx ();
1558 rtx label2 = gen_label_rtx ();
1559 rtx reg0, reg1, len, blocks;
1560
1561 reg0 = gen_reg_rtx (DImode);
1562 reg1 = gen_reg_rtx (DImode);
1563 len = gen_reg_rtx (DImode);
1564 blocks = gen_reg_rtx (DImode);
1565
1566 emit_move_insn (len, operands[2]);
1567 emit_insn (gen_cmpdi (len, const0_rtx));
1568 emit_jump_insn (gen_beq (label1));
1569 emit_move_insn (reg0, addr0);
1570 emit_move_insn (reg1, addr1);
1571 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1572 emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8)));
1573 emit_insn (gen_cmpdi (blocks, const0_rtx));
1574 emit_jump_insn (gen_beq (label2));
1575 emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1576 emit_label (label2);
1577 operands[0] = change_address (operands[0], VOIDmode, reg0);
1578 operands[1] = change_address (operands[1], VOIDmode, reg1);
1579 emit_insn (gen_movstrdi_short (operands[0], operands[1], len));
1580 emit_label (label1);
1581 DONE;
1582 }
1583 }
1584 }")
1585
1586 ;
1587 ; movstrsi instruction pattern(s).
1588 ;
1589
1590 (define_expand "movstrsi"
1591 [(set (match_operand:BLK 0 "general_operand" "")
1592 (match_operand:BLK 1 "general_operand" ""))
1593 (use (match_operand:SI 2 "general_operand" ""))
1594 (match_operand 3 "" "")]
1595 "!TARGET_64BIT"
1596 "
1597 {
1598 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1599 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1600
1601 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1602 {
1603 operands[0] = change_address (operands[0], VOIDmode, addr0);
1604 operands[1] = change_address (operands[1], VOIDmode, addr1);
1605 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1606
1607 emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2]));
1608 DONE;
1609 }
1610 else
1611 {
1612 if (TARGET_MVCLE)
1613 {
1614 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1615 rtx reg0 = gen_reg_rtx (DImode);
1616 rtx reg1 = gen_reg_rtx (DImode);
1617 rtx len = operands[2];
1618
1619
1620 if (! CONSTANT_P (len))
1621 len = force_reg (SImode, len);
1622
1623 /* Load up the address+length pairs. */
1624
1625 emit_move_insn (gen_highpart (SImode, reg0), addr0);
1626 emit_move_insn (gen_lowpart (SImode, reg0), len);
1627
1628 emit_move_insn (gen_highpart (SImode, reg1), addr1);
1629 emit_move_insn (gen_lowpart (SImode, reg1), len);
1630
1631 /* MOVE */
1632 emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1633 DONE;
1634 }
1635 else
1636 {
1637 rtx label1 = gen_label_rtx ();
1638 rtx label2 = gen_label_rtx ();
1639 rtx reg0, reg1, len, blocks;
1640
1641 reg0 = gen_reg_rtx (SImode);
1642 reg1 = gen_reg_rtx (SImode);
1643 len = gen_reg_rtx (SImode);
1644 blocks = gen_reg_rtx (SImode);
1645
1646 emit_move_insn (len, operands[2]);
1647 emit_insn (gen_cmpsi (len, const0_rtx));
1648 emit_jump_insn (gen_beq (label1));
1649 emit_move_insn (reg0, addr0);
1650 emit_move_insn (reg1, addr1);
1651 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1652 emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8)));
1653 emit_insn (gen_cmpsi (blocks, const0_rtx));
1654 emit_jump_insn (gen_beq (label2));
1655 emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1656 emit_label (label2);
1657 operands[0] = change_address (operands[0], VOIDmode, reg0);
1658 operands[1] = change_address (operands[1], VOIDmode, reg1);
1659 emit_insn (gen_movstrsi_short (operands[0], operands[1], len));
1660 emit_label (label1);
1661 DONE;
1662 }
1663 }
1664 }")
1665
1666 ; Move a block that is up to 256 bytes in length.
1667 ; The block length is taken as (operands[2] % 256) + 1.
1668
1669 (define_insn "movstrdi_short"
1670 [(set (match_operand:BLK 0 "s_operand" "=Q,Q")
1671 (match_operand:BLK 1 "s_operand" "Q,Q"))
1672 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1673 (clobber (match_scratch:DI 3 "=X,&a"))]
1674 "TARGET_64BIT"
1675 "*
1676 {
1677 switch (which_alternative)
1678 {
1679 case 0:
1680 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1681
1682 case 1:
1683 output_asm_insn (\"bras\\t%3,.+10\", operands);
1684 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1685 return \"ex\\t%2,0(%3)\";
1686
1687 default:
1688 abort ();
1689 }
1690 }"
1691 [(set_attr "op_type" "SS,NN")
1692 (set_attr "atype" "mem,mem")
1693 (set_attr "length" "*,14")])
1694
1695 (define_insn "movstrsi_short"
1696 [(set (match_operand:BLK 0 "s_operand" "=Q,Q")
1697 (match_operand:BLK 1 "s_operand" "Q,Q"))
1698 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1699 (clobber (match_scratch:SI 3 "=X,&a"))]
1700 "!TARGET_64BIT"
1701 "*
1702 {
1703 switch (which_alternative)
1704 {
1705 case 0:
1706 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1707
1708 case 1:
1709 output_asm_insn (\"bras\\t%3,.+10\", operands);
1710 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1711 return \"ex\\t%2,0(%3)\";
1712
1713 default:
1714 abort ();
1715 }
1716 }"
1717 [(set_attr "op_type" "SS,NN")
1718 (set_attr "atype" "mem,mem")
1719 (set_attr "length" "*,14")])
1720
1721 ; Move a block that is a multiple of 256 bytes in length
1722
1723 (define_insn "movstrdi_long"
1724 [(set (match_operand:DI 4 "register_operand" "=d")
1725 (const_int 0))
1726 (set (match_operand:DI 0 "register_operand" "=a")
1727 (plus:DI (match_operand:DI 2 "register_operand" "0")
1728 (ashift:DI (match_operand:DI 5 "register_operand" "4")
1729 (const_int 8))))
1730 (set (match_operand:DI 1 "register_operand" "=a")
1731 (plus:DI (match_operand:DI 3 "register_operand" "1")
1732 (ashift:DI (match_dup 5) (const_int 8))))
1733 (set (mem:BLK (match_dup 2))
1734 (mem:BLK (match_dup 3)))
1735 (use (match_dup 5))]
1736 "TARGET_64BIT"
1737 "*
1738 {
1739 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1740 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1741 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1742 return \"brct\\t%4,.-14\";
1743 }"
1744 [(set_attr "op_type" "NN")
1745 (set_attr "atype" "mem")
1746 (set_attr "length" "18")])
1747
1748 (define_insn "movstrsi_long"
1749 [(set (match_operand:SI 4 "register_operand" "=d")
1750 (const_int 0))
1751 (set (match_operand:SI 0 "register_operand" "=a")
1752 (plus:SI (match_operand:SI 2 "register_operand" "0")
1753 (ashift:SI (match_operand:SI 5 "register_operand" "4")
1754 (const_int 8))))
1755 (set (match_operand:SI 1 "register_operand" "=a")
1756 (plus:SI (match_operand:SI 3 "register_operand" "1")
1757 (ashift:SI (match_dup 5) (const_int 8))))
1758 (set (mem:BLK (match_dup 2))
1759 (mem:BLK (match_dup 3)))
1760 (use (match_dup 5))]
1761 "!TARGET_64BIT"
1762 "*
1763 {
1764 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1765 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1766 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1767 return \"brct\\t%4,.-14\";
1768 }"
1769 [(set_attr "op_type" "NN")
1770 (set_attr "atype" "mem")
1771 (set_attr "length" "18")])
1772
1773 ; Move a block that is larger than 255 bytes in length.
1774
1775 (define_insn "movstrdi_64"
1776 [(set (match_operand:TI 0 "register_operand" "=d")
1777 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1778 (lshiftrt:TI (match_dup 2) (const_int 64)))
1779 (const_int 64)))
1780 (set (match_operand:TI 1 "register_operand" "=d")
1781 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1782 (lshiftrt:TI (match_dup 3) (const_int 64)))
1783 (const_int 64)))
1784 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1785 (mem:BLK (subreg:DI (match_dup 3) 0)))
1786 (clobber (reg:CC 33))]
1787 "TARGET_64BIT"
1788 "mvcle\\t%0,%1,0\;jo\\t.-4"
1789 [(set_attr "op_type" "NN")
1790 (set_attr "atype" "mem")
1791 (set_attr "length" "8")])
1792
1793 (define_insn "movstrsi_31"
1794 [(set (match_operand:DI 0 "register_operand" "=d")
1795 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1796 (lshiftrt:DI (match_dup 2) (const_int 32)))
1797 (const_int 32)))
1798 (set (match_operand:DI 1 "register_operand" "=d")
1799 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1800 (lshiftrt:DI (match_dup 3) (const_int 32)))
1801 (const_int 32)))
1802 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1803 (mem:BLK (subreg:SI (match_dup 3) 0)))
1804 (clobber (reg:CC 33))]
1805 "!TARGET_64BIT"
1806 "mvcle\\t%0,%1,0\;jo\\t.-4"
1807 [(set_attr "op_type" "NN")
1808 (set_attr "atype" "mem")
1809 (set_attr "length" "8")])
1810
1811 ;
1812 ; clrstrdi instruction pattern(s).
1813 ;
1814
1815 (define_expand "clrstrdi"
1816 [(set (match_operand:BLK 0 "general_operand" "")
1817 (const_int 0))
1818 (use (match_operand:DI 1 "general_operand" ""))
1819 (match_operand 2 "" "")]
1820 "TARGET_64BIT"
1821 "
1822 {
1823 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1824
1825 operands[0] = change_address (operands[0], VOIDmode, addr);
1826
1827 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1828 {
1829 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1830 DONE;
1831 }
1832 else
1833 {
1834 rtx reg0 = gen_reg_rtx (TImode);
1835 rtx reg1 = gen_reg_rtx (TImode);
1836 rtx len = operands[1];
1837
1838 if (! CONSTANT_P (len))
1839 len = force_reg (DImode, len);
1840
1841 /* Load up the address+length pairs. */
1842
1843 emit_move_insn (gen_highpart (DImode, reg0), addr);
1844 emit_move_insn (gen_lowpart (DImode, reg0), len);
1845
1846 emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1847
1848 /* Clear! */
1849 emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0));
1850 DONE;
1851 }
1852 }")
1853
1854 ;
1855 ; clrstrsi instruction pattern(s).
1856 ;
1857
1858 (define_expand "clrstrsi"
1859 [(set (match_operand:BLK 0 "general_operand" "")
1860 (const_int 0))
1861 (use (match_operand:SI 1 "general_operand" ""))
1862 (match_operand 2 "" "")]
1863 "!TARGET_64BIT"
1864 "
1865 {
1866 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1867
1868 operands[0] = change_address (operands[0], VOIDmode, addr);
1869
1870 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1871 {
1872 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1873 DONE;
1874 }
1875 else
1876 {
1877 rtx reg0 = gen_reg_rtx (DImode);
1878 rtx reg1 = gen_reg_rtx (DImode);
1879 rtx len = operands[1];
1880
1881 if (! CONSTANT_P (len))
1882 len = force_reg (SImode, len);
1883
1884 /* Load up the address+length pairs. */
1885
1886 emit_move_insn (gen_highpart (SImode, reg0), addr);
1887 emit_move_insn (gen_lowpart (SImode, reg0), len);
1888
1889 emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1890
1891 /* CLear! */
1892 emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0));
1893 DONE;
1894 }
1895 }")
1896
1897 ; Clear memory with length less than 256 bytes
1898
1899 (define_insn "clrstrsico"
1900 [(set (match_operand:BLK 0 "s_operand" "=Q")
1901 (const_int 0))
1902 (use (match_operand 1 "immediate_operand" "I"))
1903 (clobber (reg:CC 33))]
1904 ""
1905 "xc\\t%O0(%1,%R0),%0"
1906 [(set_attr "op_type" "RS")
1907 (set_attr "type" "cs")
1908 (set_attr "atype" "mem")])
1909
1910 ; Clear memory with length greater 256 bytes or lenght not constant
1911
1912 (define_insn "clrstrsi_64"
1913 [(set (match_operand:TI 0 "register_operand" "=d")
1914 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1915 (lshiftrt:TI (match_dup 2) (const_int 64)))
1916 (const_int 64)))
1917 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1918 (const_int 0))
1919 (use (match_operand:TI 1 "register_operand" "d"))
1920 (clobber (reg:CC 33))]
1921 "TARGET_64BIT"
1922 "mvcle\\t%0,%1,0\;jo\\t.-4"
1923 [(set_attr "op_type" "NN")
1924 (set_attr "atype" "mem")
1925 (set_attr "type" "vs")
1926 (set_attr "length" "8")])
1927
1928 (define_insn "clrstrsi_31"
1929 [(set (match_operand:DI 0 "register_operand" "=d")
1930 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1931 (lshiftrt:DI (match_dup 2) (const_int 32)))
1932 (const_int 32)))
1933 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1934 (const_int 0))
1935 (use (match_operand:DI 1 "register_operand" "d"))
1936 (clobber (reg:CC 33))]
1937 "!TARGET_64BIT"
1938 "mvcle\\t%0,%1,0\;jo\\t.-4"
1939 [(set_attr "op_type" "NN")
1940 (set_attr "atype" "mem")
1941 (set_attr "type" "vs")
1942 (set_attr "length" "8")])
1943
1944 ;
1945 ; cmpstrdi instruction pattern(s).
1946 ;
1947
1948 (define_expand "cmpstrdi"
1949 [(set (match_operand:DI 0 "register_operand" "")
1950 (compare:DI (match_operand:BLK 1 "general_operand" "")
1951 (match_operand:BLK 2 "general_operand" "") ) )
1952 (use (match_operand:DI 3 "general_operand" ""))
1953 (use (match_operand:DI 4 "" ""))]
1954 "TARGET_64BIT"
1955 "
1956 {
1957 rtx addr0, addr1;
1958
1959 /* for pre/post increment */
1960 operands[1] = protect_from_queue (operands[1], 0);
1961 operands[2] = protect_from_queue (operands[2], 0);
1962 operands[3] = protect_from_queue (operands[3], 0);
1963
1964 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1965 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1966
1967 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1968 {
1969 if (INTVAL (operands[3]) == 0) {
1970 emit_move_insn (operands[0], operands[3]);
1971 DONE;
1972 }
1973
1974 operands[1] = change_address (operands[1], VOIDmode, addr0);
1975 operands[2] = change_address (operands[2], VOIDmode, addr1);
1976
1977 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1978 emit_insn (gen_cmpint_di (operands[0]));
1979 DONE;
1980 }
1981 else
1982 {
1983 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1984 rtx reg0 = gen_reg_rtx (TImode);
1985 rtx reg1 = gen_reg_rtx (TImode);
1986 rtx len = operands[3];
1987
1988 if (! CONSTANT_P (len))
1989 len = force_reg (DImode, len);
1990
1991 /* Load up the address+length pairs. */
1992 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1993 emit_move_insn (gen_lowpart (DImode, reg0), len);
1994
1995 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1996 emit_move_insn (gen_lowpart (DImode, reg1), len);
1997
1998 /* Compare! */
1999 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2000 emit_insn (gen_cmpint_di (operands[0]));
2001 DONE;
2002 }
2003 }")
2004
2005 ;
2006 ; cmpstrsi instruction pattern(s).
2007 ;
2008
2009 (define_expand "cmpstrsi"
2010 [(set (match_operand:SI 0 "register_operand" "")
2011 (compare:SI (match_operand:BLK 1 "general_operand" "")
2012 (match_operand:BLK 2 "general_operand" "") ) )
2013 (use (match_operand:SI 3 "general_operand" ""))
2014 (use (match_operand:SI 4 "" ""))]
2015 ""
2016 "
2017 {
2018 rtx addr0, addr1;
2019
2020 /* for pre/post increment */
2021 operands[1] = protect_from_queue (operands[1], 0);
2022 operands[2] = protect_from_queue (operands[2], 0);
2023 operands[3] = protect_from_queue (operands[3], 0);
2024
2025 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2026 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2027
2028 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2029 {
2030 if (INTVAL (operands[3]) == 0) {
2031 emit_move_insn (operands[0], operands[3]);
2032 DONE;
2033 }
2034
2035 operands[1] = change_address (operands[1], VOIDmode, addr0);
2036 operands[2] = change_address (operands[2], VOIDmode, addr1);
2037
2038 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2039 emit_insn (gen_cmpint_si (operands[0]));
2040 DONE;
2041 }
2042 else
2043 {
2044 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2045 rtx reg0, reg1;
2046 rtx len = operands[3];
2047
2048 if (TARGET_64BIT)
2049 {
2050 reg0 = gen_reg_rtx (TImode);
2051 reg1 = gen_reg_rtx (TImode);
2052 }
2053 else
2054 {
2055 reg0 = gen_reg_rtx (DImode);
2056 reg1 = gen_reg_rtx (DImode);
2057 }
2058
2059 if (! CONSTANT_P (len))
2060 len = force_reg (Pmode, len);
2061
2062 /* Load up the address+length pairs. */
2063 emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2064 emit_move_insn (gen_lowpart (Pmode, reg0), len);
2065
2066 emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2067 emit_move_insn (gen_lowpart (Pmode, reg1), len);
2068
2069 /* Compare! */
2070 if (TARGET_64BIT)
2071 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2072 else
2073 emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2074
2075 emit_insn (gen_cmpint_si (operands[0]));
2076 DONE;
2077 }
2078 }")
2079
2080 ; Compare a block that is less than 256 bytes in length.
2081
2082 (define_insn "cmpstr_const"
2083 [(set (reg:CCS 33)
2084 (compare:CCS (match_operand:BLK 0 "s_operand" "Q")
2085 (match_operand:BLK 1 "s_operand" "Q")))
2086 (use (match_operand 2 "immediate_operand" "I"))]
2087 "(unsigned) INTVAL (operands[2]) < 256"
2088 "clc\\t%O0(%c2,%R0),%1"
2089 [(set_attr "op_type" "SS")
2090 (set_attr "atype" "mem")
2091 (set_attr "type" "cs")])
2092
2093 ; Compare a block that is larger than 255 bytes in length.
2094
2095 (define_insn "cmpstr_64"
2096 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2097 (clobber (match_operand:TI 1 "register_operand" "=d"))
2098 (set (reg:CCS 33)
2099 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2100 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2101 (use (match_dup 2))
2102 (use (match_dup 3))]
2103 "TARGET_64BIT"
2104 "clcl\\t%0,%1"
2105 [(set_attr "op_type" "RR")
2106 (set_attr "atype" "mem")
2107 (set_attr "type" "vs")])
2108
2109 (define_insn "cmpstr_31"
2110 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2111 (clobber (match_operand:DI 1 "register_operand" "=d"))
2112 (set (reg:CCS 33)
2113 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2114 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2115 (use (match_dup 2))
2116 (use (match_dup 3))]
2117 "!TARGET_64BIT"
2118 "clcl\\t%0,%1"
2119 [(set_attr "op_type" "RR")
2120 (set_attr "atype" "mem")
2121 (set_attr "type" "vs")])
2122
2123 ; Convert condition code to integer in range (-1, 0, 1)
2124
2125 (define_insn "cmpint_si"
2126 [(set (match_operand:SI 0 "register_operand" "=d")
2127 (compare:SI (reg:CCS 33) (const_int 0)))]
2128 ""
2129 "*
2130 {
2131 output_asm_insn (\"lhi\\t%0,1\", operands);
2132 output_asm_insn (\"jh\\t.+12\", operands);
2133 output_asm_insn (\"jl\\t.+6\", operands);
2134 output_asm_insn (\"sr\\t%0,%0\", operands);
2135 return \"lcr\\t%0,%0\";
2136 }"
2137 [(set_attr "op_type" "NN")
2138 (set_attr "length" "16")
2139 (set_attr "atype" "reg")
2140 (set_attr "type" "other")])
2141
2142 (define_insn "cmpint_di"
2143 [(set (match_operand:DI 0 "register_operand" "=d")
2144 (compare:DI (reg:CCS 33) (const_int 0)))]
2145 "TARGET_64BIT"
2146 "*
2147 {
2148 output_asm_insn (\"lghi\\t%0,1\", operands);
2149 output_asm_insn (\"jh\\t.+12\", operands);
2150 output_asm_insn (\"jl\\t.+6\", operands);
2151 output_asm_insn (\"sgr\\t%0,%0\", operands);
2152 return \"lcgr\\t%0,%0\";
2153 }"
2154 [(set_attr "op_type" "NN")
2155 (set_attr "length" "22")
2156 (set_attr "atype" "reg")
2157 (set_attr "type" "other")])
2158
2159
2160 ;;
2161 ;;- Conversion instructions.
2162 ;;
2163
2164 (define_insn "*sethighqisi"
2165 [(set (match_operand:SI 0 "register_operand" "=d")
2166 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
2167 (clobber (reg:CC 33))]
2168 ""
2169 "icm\\t%0,8,%1"
2170 [(set_attr "op_type" "RS")
2171 (set_attr "atype" "mem")])
2172
2173 (define_insn "*sethighhisi"
2174 [(set (match_operand:SI 0 "register_operand" "=d")
2175 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
2176 (clobber (reg:CC 33))]
2177 ""
2178 "icm\\t%0,12,%1"
2179 [(set_attr "op_type" "RS")
2180 (set_attr "atype" "mem")])
2181
2182 (define_insn "*sethighqidi_64"
2183 [(set (match_operand:DI 0 "register_operand" "=d")
2184 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2185 (clobber (reg:CC 33))]
2186 "TARGET_64BIT"
2187 "icmh\\t%0,8,%1"
2188 [(set_attr "op_type" "RSE")
2189 (set_attr "atype" "mem")])
2190
2191 (define_insn "*sethighqidi_31"
2192 [(set (match_operand:DI 0 "register_operand" "=d")
2193 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2194 (clobber (reg:CC 33))]
2195 "!TARGET_64BIT"
2196 "icm\\t%0,8,%1"
2197 [(set_attr "op_type" "RS")
2198 (set_attr "atype" "mem")])
2199
2200 (define_split
2201 [(set (match_operand:SI 0 "register_operand" "")
2202 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2203 (match_operand 2 "const_int_operand" "")
2204 (const_int 0)))]
2205 "!TARGET_64BIT && !reload_completed
2206 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2207 [(parallel
2208 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2209 (clobber (reg:CC 33))])
2210 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2211 "
2212 {
2213 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2214 operands[1] = change_address (operands[1], QImode, 0);
2215 }")
2216
2217 (define_split
2218 [(set (match_operand:SI 0 "register_operand" "")
2219 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2220 (match_operand 2 "const_int_operand" "")
2221 (const_int 0)))]
2222 "!TARGET_64BIT && !reload_completed
2223 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2224 [(parallel
2225 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2226 (clobber (reg:CC 33))])
2227 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2228 "
2229 {
2230 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2231 operands[1] = change_address (operands[1], HImode, 0);
2232 }")
2233
2234 ;
2235 ; extendsidi2 instruction pattern(s).
2236 ;
2237
2238 (define_expand "extendsidi2"
2239 [(set (match_operand:DI 0 "register_operand" "")
2240 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2241 ""
2242 "
2243 {
2244 if (!TARGET_64BIT)
2245 {
2246 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2247 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2248 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2249 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2250 DONE;
2251 }
2252 }
2253 ")
2254
2255 (define_insn "*extendsidi2"
2256 [(set (match_operand:DI 0 "register_operand" "=d,d")
2257 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2258 "TARGET_64BIT"
2259 "@
2260 lgfr\\t%0,%1
2261 lgf\\t%0,%1"
2262 [(set_attr "op_type" "RRE,RXE")
2263 (set_attr "atype" "reg,mem")])
2264
2265 ;
2266 ; extendhidi2 instruction pattern(s).
2267 ;
2268
2269 (define_expand "extendhidi2"
2270 [(set (match_operand:DI 0 "register_operand" "")
2271 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2272 ""
2273 "
2274 {
2275 if (!TARGET_64BIT)
2276 {
2277 rtx tmp = gen_reg_rtx (SImode);
2278 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2279 emit_insn (gen_extendsidi2 (operands[0], tmp));
2280 DONE;
2281 }
2282 else
2283 {
2284 operands[1] = gen_lowpart (DImode, operands[1]);
2285 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2286 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2287 DONE;
2288 }
2289 }
2290 ")
2291
2292 (define_insn "*extendhidi2"
2293 [(set (match_operand:DI 0 "register_operand" "=d")
2294 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2295 "TARGET_64BIT"
2296 "lgh\\t%0,%1"
2297 [(set_attr "op_type" "RXE")
2298 (set_attr "atype" "mem")])
2299
2300 ;
2301 ; extendqidi2 instruction pattern(s).
2302 ;
2303
2304 (define_expand "extendqidi2"
2305 [(set (match_operand:DI 0 "register_operand" "")
2306 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2307 ""
2308 "
2309 {
2310 if (!TARGET_64BIT)
2311 {
2312 rtx tmp = gen_reg_rtx (SImode);
2313 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2314 emit_insn (gen_extendsidi2 (operands[0], tmp));
2315 DONE;
2316 }
2317 else
2318 {
2319 operands[1] = gen_lowpart (DImode, operands[1]);
2320 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2321 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2322 DONE;
2323 }
2324 }
2325 ")
2326
2327 (define_split
2328 [(set (match_operand:DI 0 "register_operand" "")
2329 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2330 "TARGET_64BIT && !reload_completed"
2331 [(parallel
2332 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2333 (clobber (reg:CC 33))])
2334 (parallel
2335 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2336 (clobber (reg:CC 33))])]
2337 "")
2338
2339 ;
2340 ; extendhisi2 instruction pattern(s).
2341 ;
2342
2343 (define_expand "extendhisi2"
2344 [(set (match_operand:SI 0 "register_operand" "")
2345 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2346 ""
2347 "
2348 {
2349 operands[1] = gen_lowpart (SImode, operands[1]);
2350 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2351 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2352 DONE;
2353 }
2354 ")
2355
2356 (define_insn "*extendhisi2"
2357 [(set (match_operand:SI 0 "register_operand" "=d")
2358 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2359 ""
2360 "lh\\t%0,%1"
2361 [(set_attr "op_type" "RX")
2362 (set_attr "atype" "mem")])
2363
2364 ;
2365 ; extendqisi2 instruction pattern(s).
2366 ;
2367
2368 (define_expand "extendqisi2"
2369 [(set (match_operand:SI 0 "register_operand" "")
2370 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2371 ""
2372 "
2373 {
2374 operands[1] = gen_lowpart (SImode, operands[1]);
2375 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2376 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2377 DONE;
2378 }
2379 ")
2380
2381 (define_split
2382 [(set (match_operand:SI 0 "register_operand" "")
2383 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2384 "!reload_completed"
2385 [(parallel
2386 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2387 (clobber (reg:CC 33))])
2388 (parallel
2389 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2390 (clobber (reg:CC 33))])]
2391 "")
2392
2393 ;
2394 ; extendqihi2 instruction pattern(s).
2395 ;
2396
2397
2398 ;
2399 ; zero_extendsidi2 instruction pattern(s).
2400 ;
2401
2402 (define_expand "zero_extendsidi2"
2403 [(set (match_operand:DI 0 "register_operand" "")
2404 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2405 ""
2406 "
2407 {
2408 if (!TARGET_64BIT)
2409 {
2410 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2411 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2412 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2413 DONE;
2414 }
2415 }
2416 ")
2417
2418 (define_insn "*zero_extendsidi2"
2419 [(set (match_operand:DI 0 "register_operand" "=d,d")
2420 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2421 "TARGET_64BIT"
2422 "@
2423 llgfr\\t%0,%1
2424 llgf\\t%0,%1"
2425 [(set_attr "op_type" "RRE,RXE")
2426 (set_attr "atype" "reg,mem")])
2427
2428 ;
2429 ; zero_extendhidi2 instruction pattern(s).
2430 ;
2431
2432 (define_expand "zero_extendhidi2"
2433 [(set (match_operand:DI 0 "register_operand" "")
2434 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2435 ""
2436 "
2437 {
2438 if (!TARGET_64BIT)
2439 {
2440 rtx tmp = gen_reg_rtx (SImode);
2441 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2442 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2443 DONE;
2444 }
2445 else
2446 {
2447 operands[1] = gen_lowpart (DImode, operands[1]);
2448 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2449 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2450 DONE;
2451 }
2452 }
2453 ")
2454
2455 (define_insn "*zero_extendhidi2"
2456 [(set (match_operand:DI 0 "register_operand" "=d")
2457 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2458 "TARGET_64BIT"
2459 "llgh\\t%0,%1"
2460 [(set_attr "op_type" "RXE")
2461 (set_attr "atype" "mem")])
2462
2463 ;
2464 ; zero_extendqidi2 instruction pattern(s)
2465 ;
2466
2467 (define_expand "zero_extendqidi2"
2468 [(set (match_operand:DI 0 "register_operand" "")
2469 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2470 ""
2471 "
2472 {
2473 if (!TARGET_64BIT)
2474 {
2475 rtx tmp = gen_reg_rtx (SImode);
2476 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2477 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2478 DONE;
2479 }
2480 else
2481 {
2482 operands[1] = gen_lowpart (DImode, operands[1]);
2483 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2484 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2485 DONE;
2486 }
2487 }
2488 ")
2489
2490 (define_insn "*zero_extendqidi2"
2491 [(set (match_operand:DI 0 "register_operand" "=d")
2492 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2493 "TARGET_64BIT"
2494 "llgc\\t%0,%1"
2495 [(set_attr "op_type" "RXE")
2496 (set_attr "atype" "mem")])
2497
2498 ;
2499 ; zero_extendhisi2 instruction pattern(s).
2500 ;
2501
2502 (define_expand "zero_extendhisi2"
2503 [(set (match_operand:SI 0 "register_operand" "")
2504 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2505 ""
2506 "
2507 {
2508 operands[1] = gen_lowpart (SImode, operands[1]);
2509 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2510 DONE;
2511 }
2512 ")
2513
2514 (define_insn "*zero_extendhisi2_64"
2515 [(set (match_operand:SI 0 "register_operand" "=d")
2516 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2517 "TARGET_64BIT"
2518 "llgh\\t%0,%1"
2519 [(set_attr "op_type" "RXE")
2520 (set_attr "atype" "mem")])
2521
2522 ;
2523 ; zero_extendqisi2 instruction pattern(s).
2524 ;
2525
2526 (define_expand "zero_extendqisi2"
2527 [(set (match_operand:SI 0 "register_operand" "")
2528 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2529 ""
2530 "
2531 {
2532 operands[1] = gen_lowpart (SImode, operands[1]);
2533 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2534 DONE;
2535 }
2536 ")
2537
2538 (define_insn "*zero_extendqisi2_64"
2539 [(set (match_operand:SI 0 "register_operand" "=d")
2540 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2541 "TARGET_64BIT"
2542 "llgc\\t%0,%1"
2543 [(set_attr "op_type" "RXE")
2544 (set_attr "atype" "mem")])
2545
2546 ;
2547 ; zero_extendqihi2 instruction pattern(s).
2548 ;
2549
2550 (define_expand "zero_extendqihi2"
2551 [(set (match_operand:HI 0 "register_operand" "")
2552 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2553 "TARGET_64BIT"
2554 "
2555 {
2556 operands[1] = gen_lowpart (HImode, operands[1]);
2557 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2558 DONE;
2559 }
2560 ")
2561
2562 (define_insn "*zero_extendqihi2_64"
2563 [(set (match_operand:HI 0 "register_operand" "=d")
2564 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2565 (clobber (reg:CC 33))]
2566 "TARGET_64BIT"
2567 "llgc\\t%0,%1"
2568 [(set_attr "op_type" "RXE")
2569 (set_attr "atype" "mem")])
2570
2571 ;
2572 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2573 ;
2574
2575 (define_expand "fixuns_truncdfdi2"
2576 [(set (match_operand:DI 0 "register_operand" "")
2577 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2578 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2579 "
2580 {
2581 rtx label1 = gen_label_rtx ();
2582 rtx label2 = gen_label_rtx ();
2583 rtx temp = gen_reg_rtx (DFmode);
2584 operands[1] = force_reg (DFmode, operands[1]);
2585
2586 emit_insn (gen_cmpdf (operands[1],
2587 CONST_DOUBLE_FROM_REAL_VALUE (
2588 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2589 emit_jump_insn (gen_blt (label1));
2590 emit_insn (gen_subdf3 (temp, operands[1],
2591 CONST_DOUBLE_FROM_REAL_VALUE (
2592 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2593 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2594 emit_jump (label2);
2595
2596 emit_label (label1);
2597 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2598 emit_label (label2);
2599 DONE;
2600 }")
2601
2602 (define_expand "fix_truncdfdi2"
2603 [(set (match_operand:DI 0 "register_operand" "")
2604 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2605 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2606 "
2607 {
2608 operands[1] = force_reg (DFmode, operands[1]);
2609 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2610 DONE;
2611 }")
2612
2613 (define_insn "fix_truncdfdi2_ieee"
2614 [(set (match_operand:DI 0 "register_operand" "=d")
2615 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2616 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2617 (clobber (reg:CC 33))]
2618 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2619 "cgdbr\\t%0,%h2,%1"
2620 [(set_attr "op_type" "RRE")
2621 (set_attr "type" "other")])
2622
2623 ;
2624 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2625 ;
2626
2627 (define_expand "fixuns_truncdfsi2"
2628 [(set (match_operand:SI 0 "register_operand" "")
2629 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2630 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2631 "
2632 {
2633 rtx label1 = gen_label_rtx ();
2634 rtx label2 = gen_label_rtx ();
2635 rtx temp = gen_reg_rtx (DFmode);
2636
2637 operands[1] = force_reg (DFmode,operands[1]);
2638 emit_insn (gen_cmpdf (operands[1],
2639 CONST_DOUBLE_FROM_REAL_VALUE (
2640 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2641 emit_jump_insn (gen_blt (label1));
2642 emit_insn (gen_subdf3 (temp, operands[1],
2643 CONST_DOUBLE_FROM_REAL_VALUE (
2644 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2645 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2646 emit_jump (label2);
2647
2648 emit_label (label1);
2649 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2650 emit_label (label2);
2651 DONE;
2652 }")
2653
2654 (define_expand "fix_truncdfsi2"
2655 [(set (match_operand:SI 0 "register_operand" "")
2656 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2657 "TARGET_HARD_FLOAT"
2658 "
2659 {
2660 if (TARGET_IBM_FLOAT)
2661 {
2662 /* This is the algorithm from POP chapter A.5.7.2. */
2663
2664 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2665 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2666 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2667
2668 operands[1] = force_reg (DFmode, operands[1]);
2669 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2670 two31r, two32, temp));
2671 }
2672 else
2673 {
2674 operands[1] = force_reg (DFmode, operands[1]);
2675 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2676 }
2677
2678 DONE;
2679 }")
2680
2681 (define_insn "fix_truncdfsi2_ieee"
2682 [(set (match_operand:SI 0 "register_operand" "=d")
2683 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2684 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2685 (clobber (reg:CC 33))]
2686 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2687 "cfdbr\\t%0,%h2,%1"
2688 [(set_attr "op_type" "RRE")
2689 (set_attr "type" "other" )])
2690
2691 (define_insn "fix_truncdfsi2_ibm"
2692 [(set (match_operand:SI 0 "register_operand" "=d")
2693 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2694 (use (match_operand:DI 2 "immediate_operand" "m"))
2695 (use (match_operand:DI 3 "immediate_operand" "m"))
2696 (use (match_operand:BLK 4 "memory_operand" "m"))
2697 (clobber (reg:CC 33))]
2698 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2699 "*
2700 {
2701 output_asm_insn (\"sd\\t%1,%2\", operands);
2702 output_asm_insn (\"aw\\t%1,%3\", operands);
2703 output_asm_insn (\"std\\t%1,%4\", operands);
2704 output_asm_insn (\"xi\\t%N4,128\", operands);
2705 return \"l\\t%0,%N4\";
2706 }"
2707 [(set_attr "op_type" "NN")
2708 (set_attr "type" "other")
2709 (set_attr "length" "20")])
2710
2711 ;
2712 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2713 ;
2714
2715 (define_expand "fixuns_truncsfdi2"
2716 [(set (match_operand:DI 0 "register_operand" "")
2717 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2718 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2719 "
2720 {
2721 rtx label1 = gen_label_rtx ();
2722 rtx label2 = gen_label_rtx ();
2723 rtx temp = gen_reg_rtx (SFmode);
2724
2725 operands[1] = force_reg (SFmode, operands[1]);
2726 emit_insn (gen_cmpsf (operands[1],
2727 CONST_DOUBLE_FROM_REAL_VALUE (
2728 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2729 emit_jump_insn (gen_blt (label1));
2730
2731 emit_insn (gen_subsf3 (temp, operands[1],
2732 CONST_DOUBLE_FROM_REAL_VALUE (
2733 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2734 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2735 emit_jump (label2);
2736
2737 emit_label (label1);
2738 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2739 emit_label (label2);
2740 DONE;
2741 }")
2742
2743 (define_expand "fix_truncsfdi2"
2744 [(set (match_operand:DI 0 "register_operand" "")
2745 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2746 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2747 "
2748 {
2749 operands[1] = force_reg (SFmode, operands[1]);
2750 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2751 DONE;
2752 }")
2753
2754 (define_insn "fix_truncsfdi2_ieee"
2755 [(set (match_operand:DI 0 "register_operand" "=d")
2756 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2757 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2758 (clobber (reg:CC 33))]
2759 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2760 "cgebr\\t%0,%h2,%1"
2761 [(set_attr "op_type" "RRE")
2762 (set_attr "type" "other")])
2763
2764 ;
2765 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2766 ;
2767
2768 (define_expand "fixuns_truncsfsi2"
2769 [(set (match_operand:SI 0 "register_operand" "")
2770 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2771 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2772 "
2773 {
2774 rtx label1 = gen_label_rtx ();
2775 rtx label2 = gen_label_rtx ();
2776 rtx temp = gen_reg_rtx (SFmode);
2777
2778 operands[1] = force_reg (SFmode, operands[1]);
2779 emit_insn (gen_cmpsf (operands[1],
2780 CONST_DOUBLE_FROM_REAL_VALUE (
2781 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2782 emit_jump_insn (gen_blt (label1));
2783 emit_insn (gen_subsf3 (temp, operands[1],
2784 CONST_DOUBLE_FROM_REAL_VALUE (
2785 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2786 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2787 emit_jump (label2);
2788
2789 emit_label (label1);
2790 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2791 emit_label (label2);
2792 DONE;
2793 }")
2794
2795 (define_expand "fix_truncsfsi2"
2796 [(set (match_operand:SI 0 "register_operand" "")
2797 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2798 "TARGET_HARD_FLOAT"
2799 "
2800 {
2801 if (TARGET_IBM_FLOAT)
2802 {
2803 /* Convert to DFmode and then use the POP algorithm. */
2804 rtx temp = gen_reg_rtx (DFmode);
2805 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2806 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2807 }
2808 else
2809 {
2810 operands[1] = force_reg (SFmode, operands[1]);
2811 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2812 }
2813
2814 DONE;
2815 }")
2816
2817 (define_insn "fix_truncsfsi2_ieee"
2818 [(set (match_operand:SI 0 "register_operand" "=d")
2819 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2820 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2821 (clobber (reg:CC 33))]
2822 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2823 "cfebr\\t%0,%h2,%1"
2824 [(set_attr "op_type" "RRE")
2825 (set_attr "type" "other")])
2826
2827 ;
2828 ; floatdidf2 instruction pattern(s).
2829 ;
2830
2831 (define_insn "floatdidf2"
2832 [(set (match_operand:DF 0 "register_operand" "=f")
2833 (float:DF (match_operand:DI 1 "register_operand" "d")))
2834 (clobber (reg:CC 33))]
2835 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2836 "cdgbr\\t%0,%1"
2837 [(set_attr "op_type" "RRE")
2838 (set_attr "type" "other" )])
2839
2840 ;
2841 ; floatdisf2 instruction pattern(s).
2842 ;
2843
2844 (define_insn "floatdisf2"
2845 [(set (match_operand:SF 0 "register_operand" "=f")
2846 (float:SF (match_operand:DI 1 "register_operand" "d")))
2847 (clobber (reg:CC 33))]
2848 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2849 "cegbr\\t%0,%1"
2850 [(set_attr "op_type" "RRE")
2851 (set_attr "type" "other" )])
2852
2853 ;
2854 ; floatsidf2 instruction pattern(s).
2855 ;
2856
2857 (define_expand "floatsidf2"
2858 [(parallel
2859 [(set (match_operand:DF 0 "register_operand" "")
2860 (float:DF (match_operand:SI 1 "register_operand" "")))
2861 (clobber (reg:CC 33))])]
2862 "TARGET_HARD_FLOAT"
2863 "
2864 {
2865 if (TARGET_IBM_FLOAT)
2866 {
2867 /* This is the algorithm from POP chapter A.5.7.1. */
2868
2869 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2870 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2871
2872 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2873 DONE;
2874 }
2875 }")
2876
2877 (define_insn "floatsidf2_ieee"
2878 [(set (match_operand:DF 0 "register_operand" "=f")
2879 (float:DF (match_operand:SI 1 "register_operand" "d")))
2880 (clobber (reg:CC 33))]
2881 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2882 "cdfbr\\t%0,%1"
2883 [(set_attr "op_type" "RRE")
2884 (set_attr "type" "other" )])
2885
2886 (define_insn "floatsidf2_ibm"
2887 [(set (match_operand:DF 0 "register_operand" "=f")
2888 (float:DF (match_operand:SI 1 "register_operand" "d")))
2889 (use (match_operand:DI 2 "immediate_operand" "m"))
2890 (use (match_operand:BLK 3 "memory_operand" "m"))
2891 (clobber (reg:CC 33))]
2892 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2893 "*
2894 {
2895 output_asm_insn (\"st\\t%1,%N3\", operands);
2896 output_asm_insn (\"xi\\t%N3,128\", operands);
2897 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2898 output_asm_insn (\"ld\\t%0,%3\", operands);
2899 return \"sd\\t%0,%2\";
2900 }"
2901 [(set_attr "op_type" "NN")
2902 (set_attr "type" "other" )
2903 (set_attr "length" "20")])
2904
2905 ;
2906 ; floatsisf2 instruction pattern(s).
2907 ;
2908
2909 (define_expand "floatsisf2"
2910 [(parallel
2911 [(set (match_operand:SF 0 "register_operand" "")
2912 (float:SF (match_operand:SI 1 "register_operand" "")))
2913 (clobber (reg:CC 33))])]
2914 "TARGET_HARD_FLOAT"
2915 "
2916 {
2917 if (TARGET_IBM_FLOAT)
2918 {
2919 /* Use the POP algorithm to convert to DFmode and then truncate. */
2920 rtx temp = gen_reg_rtx (DFmode);
2921 emit_insn (gen_floatsidf2 (temp, operands[1]));
2922 emit_insn (gen_truncdfsf2 (operands[0], temp));
2923 DONE;
2924 }
2925 }")
2926
2927 (define_insn "floatsisf2_ieee"
2928 [(set (match_operand:SF 0 "register_operand" "=f")
2929 (float:SF (match_operand:SI 1 "register_operand" "d")))
2930 (clobber (reg:CC 33))]
2931 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2932 "cefbr\\t%0,%1"
2933 [(set_attr "op_type" "RRE")
2934 (set_attr "type" "other" )])
2935
2936 ;
2937 ; truncdfsf2 instruction pattern(s).
2938 ;
2939
2940 (define_expand "truncdfsf2"
2941 [(set (match_operand:SF 0 "register_operand" "")
2942 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2943 "TARGET_HARD_FLOAT"
2944 "")
2945
2946 (define_insn "truncdfsf2_ieee"
2947 [(set (match_operand:SF 0 "register_operand" "=f")
2948 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2949 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2950 "ledbr\\t%0,%1"
2951 [(set_attr "op_type" "RRE")])
2952
2953 (define_insn "truncdfsf2_ibm"
2954 [(set (match_operand:SF 0 "register_operand" "=f,f")
2955 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2956 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2957 "@
2958 lrer\\t%0,%1
2959 le\\t%0,%1"
2960 [(set_attr "op_type" "RR,RX")
2961 (set_attr "atype" "reg,mem")])
2962
2963 ;
2964 ; extendsfdf2 instruction pattern(s).
2965 ;
2966
2967 (define_expand "extendsfdf2"
2968 [(set (match_operand:DF 0 "register_operand" "")
2969 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2970 "TARGET_HARD_FLOAT"
2971 "
2972 {
2973 if (TARGET_IBM_FLOAT)
2974 {
2975 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2976 DONE;
2977 }
2978 }")
2979
2980 (define_insn "extendsfdf2_ieee"
2981 [(set (match_operand:DF 0 "register_operand" "=f,f")
2982 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2983 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2984 "@
2985 ldebr\\t%0,%1
2986 ldeb\\t%0,%1"
2987 [(set_attr "op_type" "RRE,RXE")])
2988
2989 (define_insn "extendsfdf2_ibm"
2990 [(set (match_operand:DF 0 "register_operand" "=f,f")
2991 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2992 (clobber (reg:CC 33))]
2993 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2994 "@
2995 sdr\\t%0,%0\;ler\\t%0,%1
2996 sdr\\t%0,%0\;le\\t%0,%1"
2997 [(set_attr "op_type" "RRE,RXE")
2998 (set_attr "atype" "reg,mem")
2999 (set_attr "type" "o2,o2")])
3000
3001
3002 ;;
3003 ;; ARITHMETRIC OPERATIONS
3004 ;;
3005 ; arithmetric operations set the ConditionCode,
3006 ; because of unpredictable Bits in Register for Halfword and Byte
3007 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3008
3009 ;;
3010 ;;- Add instructions.
3011 ;;
3012
3013 ;
3014 ; adddi3 instruction pattern(s).
3015 ;
3016
3017 (define_insn "addaddr_esame"
3018 [(set (match_operand:DI 0 "register_operand" "=a,a")
3019 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3020 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3021 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3022 (REGNO (operands[1]) == BASE_REGISTER)) &&
3023 (GET_CODE (operands[2]) == REG ||
3024 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3025 "@
3026 la\\t%0,%c2(,%1)
3027 la\\t%0,0(%1,%2)"
3028 [(set_attr "op_type" "RX")
3029 (set_attr "atype" "mem")
3030 (set_attr "type" "la")])
3031
3032 (define_insn "*adddi3_sign"
3033 [(set (match_operand:DI 0 "register_operand" "=d,d")
3034 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3035 (match_operand:DI 1 "register_operand" "0,0")))
3036 (clobber (reg:CC 33))]
3037 "TARGET_64BIT"
3038 "@
3039 agfr\\t%0,%2
3040 agf\\t%0,%2"
3041 [(set_attr "op_type" "RRE,RXE")
3042 (set_attr "atype" "reg,mem")])
3043
3044 (define_insn "*adddi3_zero_cc"
3045 [(set (reg 33)
3046 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3047 (match_operand:DI 1 "register_operand" "0,0"))
3048 (const_int 0)))
3049 (set (match_operand:DI 0 "register_operand" "=d,d")
3050 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3051 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3052 "@
3053 algfr\\t%0,%2
3054 algf\\t%0,%2"
3055 [(set_attr "op_type" "RRE,RXE")
3056 (set_attr "atype" "reg,mem")])
3057
3058 (define_insn "*adddi3_zero_cconly"
3059 [(set (reg 33)
3060 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3061 (match_operand:DI 1 "register_operand" "0,0"))
3062 (const_int 0)))
3063 (clobber (match_scratch:DI 0 "=d,d"))]
3064 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3065 "@
3066 algfr\\t%0,%2
3067 algf\\t%0,%2"
3068 [(set_attr "op_type" "RRE,RXE")
3069 (set_attr "atype" "reg,mem")])
3070
3071 (define_insn "*adddi3_zero"
3072 [(set (match_operand:DI 0 "register_operand" "=d,d")
3073 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3074 (match_operand:DI 1 "register_operand" "0,0")))
3075 (clobber (reg:CC 33))]
3076 "TARGET_64BIT"
3077 "@
3078 algfr\\t%0,%2
3079 algf\\t%0,%2"
3080 [(set_attr "op_type" "RRE,RXE")
3081 (set_attr "atype" "reg,mem")])
3082
3083 (define_insn "*adddi3_cc"
3084 [(set (reg 33)
3085 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3086 (match_operand:DI 2 "general_operand" "d,m"))
3087 (const_int 0)))
3088 (set (match_operand:DI 0 "register_operand" "=d,d")
3089 (plus:DI (match_dup 1) (match_dup 2)))]
3090 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3091 "@
3092 algr\\t%0,%2
3093 alg\\t%0,%2"
3094 [(set_attr "op_type" "RRE,RXE")
3095 (set_attr "atype" "reg,mem")])
3096
3097 (define_insn "*adddi3_cconly"
3098 [(set (reg 33)
3099 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3100 (match_operand:DI 2 "general_operand" "d,m"))
3101 (const_int 0)))
3102 (clobber (match_scratch:DI 0 "=d,d"))]
3103 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3104 "@
3105 algr\\t%0,%2
3106 alg\\t%0,%2"
3107 [(set_attr "op_type" "RRE,RXE")
3108 (set_attr "atype" "reg,mem")])
3109
3110 (define_insn "*adddi3_cconly2"
3111 [(set (reg 33)
3112 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3113 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3114 (clobber (match_scratch:DI 0 "=d,d"))]
3115 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3116 "@
3117 algr\\t%0,%2
3118 alg\\t%0,%2"
3119 [(set_attr "op_type" "RRE,RXE")
3120 (set_attr "atype" "reg,mem")])
3121
3122 (define_insn "*adddi3_64"
3123 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3124 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3125 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3126 (clobber (reg:CC 33))]
3127 "TARGET_64BIT"
3128 "@
3129 agr\\t%0,%2
3130 aghi\\t%0,%h2
3131 ag\\t%0,%2"
3132 [(set_attr "op_type" "RRE,RI,RXE")
3133 (set_attr "atype" "reg,reg,mem")])
3134
3135 (define_insn_and_split "*adddi3_31"
3136 [(set (match_operand:DI 0 "register_operand" "=&d")
3137 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3138 (match_operand:DI 2 "general_operand" "dm") ) )
3139 (clobber (reg:CC 33))]
3140 "!TARGET_64BIT"
3141 "#"
3142 "&& reload_completed"
3143 [(parallel
3144 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3145 (clobber (reg:CC 33))])
3146 (parallel
3147 [(set (reg:CCL1 33)
3148 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3149 (match_dup 7)))
3150 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3151 (set (pc)
3152 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3153 (pc)
3154 (label_ref (match_dup 9))))
3155 (parallel
3156 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3157 (clobber (reg:CC 33))])
3158 (match_dup 9)]
3159 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3160 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3161 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3162 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3163 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3164 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3165 operands[9] = gen_label_rtx ();"
3166 [(set_attr "op_type" "NN")
3167 (set_attr "type" "o3")])
3168
3169 (define_expand "adddi3"
3170 [(parallel
3171 [(set (match_operand:DI 0 "register_operand" "")
3172 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3173 (match_operand:DI 2 "general_operand" "")))
3174 (clobber (reg:CC 33))])]
3175 ""
3176 "")
3177
3178 (define_insn "*la_64"
3179 [(set (match_operand:DI 0 "register_operand" "=d")
3180 (match_operand:QI 1 "address_operand" "p"))]
3181 "TARGET_64BIT"
3182 "la\\t%0,%a1"
3183 [(set_attr "op_type" "RX")
3184 (set_attr "atype" "mem")
3185 (set_attr "type" "la")])
3186
3187 (define_expand "reload_indi"
3188 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3189 (match_operand:DI 1 "s390_plus_operand" "")
3190 (match_operand:DI 2 "register_operand" "=&a")])]
3191 "TARGET_64BIT"
3192 "
3193 {
3194 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3195 DONE;
3196 }")
3197
3198
3199 ;
3200 ; addsi3 instruction pattern(s).
3201 ;
3202
3203 (define_insn "*la_ccclobber"
3204 [(set (match_operand:SI 0 "register_operand" "=d")
3205 (match_operand:QI 1 "address_operand" "p"))
3206 (clobber (reg:CC 33))]
3207 "legitimate_la_operand_p (operands[1])"
3208 "la\\t%0,%a1"
3209 [(set_attr "op_type" "RX")
3210 (set_attr "atype" "mem")
3211 (set_attr "type" "la")])
3212
3213 (define_insn "*addsi3_carry1_cc"
3214 [(set (reg 33)
3215 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3216 (match_operand:SI 2 "general_operand" "d,m"))
3217 (match_dup 1)))
3218 (set (match_operand:SI 0 "register_operand" "=d,d")
3219 (plus:SI (match_dup 1) (match_dup 2)))]
3220 "s390_match_ccmode (insn, CCL1mode)"
3221 "@
3222 alr\\t%0,%2
3223 al\\t%0,%2"
3224 [(set_attr "op_type" "RR,RX")
3225 (set_attr "atype" "reg,mem")])
3226
3227 (define_insn "*addsi3_carry1_cconly"
3228 [(set (reg 33)
3229 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3230 (match_operand:SI 2 "general_operand" "d,m"))
3231 (match_dup 1)))
3232 (clobber (match_scratch:SI 0 "=d,d"))]
3233 "s390_match_ccmode (insn, CCL1mode)"
3234 "@
3235 alr\\t%0,%2
3236 al\\t%0,%2"
3237 [(set_attr "op_type" "RR,RX")
3238 (set_attr "atype" "reg,mem")])
3239
3240 (define_insn "*addsi3_carry2_cc"
3241 [(set (reg 33)
3242 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3243 (match_operand:SI 2 "general_operand" "d,m"))
3244 (match_dup 2)))
3245 (set (match_operand:SI 0 "register_operand" "=d,d")
3246 (plus:SI (match_dup 1) (match_dup 2)))]
3247 "s390_match_ccmode (insn, CCL1mode)"
3248 "@
3249 alr\\t%0,%2
3250 al\\t%0,%2"
3251 [(set_attr "op_type" "RR,RX")
3252 (set_attr "atype" "reg,mem")])
3253
3254 (define_insn "*addsi3_carry2_cconly"
3255 [(set (reg 33)
3256 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3257 (match_operand:SI 2 "general_operand" "d,m"))
3258 (match_dup 2)))
3259 (clobber (match_scratch:SI 0 "=d,d"))]
3260 "s390_match_ccmode (insn, CCL1mode)"
3261 "@
3262 alr\\t%0,%2
3263 al\\t%0,%2"
3264 [(set_attr "op_type" "RR,RX")
3265 (set_attr "atype" "reg,mem")])
3266
3267 (define_insn "*addsi3_cc"
3268 [(set (reg 33)
3269 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3270 (match_operand:SI 2 "general_operand" "d,m"))
3271 (const_int 0)))
3272 (set (match_operand:SI 0 "register_operand" "=d,d")
3273 (plus:SI (match_dup 1) (match_dup 2)))]
3274 "s390_match_ccmode (insn, CCLmode)"
3275 "@
3276 alr\\t%0,%2
3277 al\\t%0,%2"
3278 [(set_attr "op_type" "RR,RX")
3279 (set_attr "atype" "reg,mem")])
3280
3281 (define_insn "*addsi3_cconly"
3282 [(set (reg 33)
3283 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3284 (match_operand:SI 2 "general_operand" "d,m"))
3285 (const_int 0)))
3286 (clobber (match_scratch:SI 0 "=d,d"))]
3287 "s390_match_ccmode (insn, CCLmode)"
3288 "@
3289 alr\\t%0,%2
3290 al\\t%0,%2"
3291 [(set_attr "op_type" "RR,RX")
3292 (set_attr "atype" "reg,mem")])
3293
3294 (define_insn "*addsi3_cconly2"
3295 [(set (reg 33)
3296 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3297 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3298 (clobber (match_scratch:SI 0 "=d,d"))]
3299 "s390_match_ccmode(insn, CCLmode)"
3300 "@
3301 alr\\t%0,%2
3302 al\\t%0,%2"
3303 [(set_attr "op_type" "RR,RX")
3304 (set_attr "atype" "reg,mem")])
3305
3306 (define_insn "*addsi3_sign"
3307 [(set (match_operand:SI 0 "register_operand" "=d")
3308 (plus:SI (match_operand:SI 1 "register_operand" "0")
3309 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3310 (clobber (reg:CC 33))]
3311 ""
3312 "ah\\t%0,%2"
3313 [(set_attr "op_type" "RX")
3314 (set_attr "atype" "mem")])
3315
3316 (define_insn "*addsi3_sub"
3317 [(set (match_operand:SI 0 "register_operand" "=d")
3318 (plus:SI (match_operand:SI 1 "register_operand" "0")
3319 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3320 (clobber (reg:CC 33))]
3321 ""
3322 "ah\\t%0,%2"
3323 [(set_attr "op_type" "RX")
3324 (set_attr "atype" "mem")])
3325
3326 (define_insn "addsi3"
3327 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3328 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3329 (match_operand:SI 2 "general_operand" "d,K,m")))
3330 (clobber (reg:CC 33))]
3331 ""
3332 "@
3333 ar\\t%0,%2
3334 ahi\\t%0,%h2
3335 a\\t%0,%2"
3336 [(set_attr "op_type" "RR,RI,RX")
3337 (set_attr "atype" "reg,reg,mem")])
3338
3339 (define_insn "*la_31"
3340 [(set (match_operand:SI 0 "register_operand" "=d")
3341 (match_operand:QI 1 "address_operand" "p"))]
3342 "legitimate_la_operand_p (operands[1])"
3343 "la\\t%0,%a1"
3344 [(set_attr "op_type" "RX")
3345 (set_attr "atype" "mem")
3346 (set_attr "type" "la")])
3347
3348 (define_expand "reload_insi"
3349 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3350 (match_operand:SI 1 "s390_plus_operand" "")
3351 (match_operand:SI 2 "register_operand" "=&a")])]
3352 "!TARGET_64BIT"
3353 "
3354 {
3355 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3356 DONE;
3357 }")
3358
3359
3360 ;
3361 ; adddf3 instruction pattern(s).
3362 ;
3363
3364 (define_expand "adddf3"
3365 [(parallel
3366 [(set (match_operand:DF 0 "register_operand" "=f,f")
3367 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3368 (match_operand:DF 2 "general_operand" "f,m")))
3369 (clobber (reg:CC 33))])]
3370 "TARGET_HARD_FLOAT"
3371 "")
3372
3373 (define_insn "*adddf3"
3374 [(set (match_operand:DF 0 "register_operand" "=f,f")
3375 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3376 (match_operand:DF 2 "general_operand" "f,m")))
3377 (clobber (reg:CC 33))]
3378 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3379 "@
3380 adbr\\t%0,%2
3381 adb\\t%0,%2"
3382 [(set_attr "op_type" "RRE,RXE")
3383 (set_attr "atype" "reg,mem")])
3384
3385 (define_insn "*adddf3_ibm"
3386 [(set (match_operand:DF 0 "register_operand" "=f,f")
3387 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3388 (match_operand:DF 2 "general_operand" "f,m")))
3389 (clobber (reg:CC 33))]
3390 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3391 "@
3392 adr\\t%0,%2
3393 ad\\t%0,%2"
3394 [(set_attr "op_type" "RR,RX")
3395 (set_attr "atype" "reg,mem")])
3396
3397 ;
3398 ; addsf3 instruction pattern(s).
3399 ;
3400
3401 (define_expand "addsf3"
3402 [(parallel
3403 [(set (match_operand:SF 0 "register_operand" "=f,f")
3404 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3405 (match_operand:SF 2 "general_operand" "f,m")))
3406 (clobber (reg:CC 33))])]
3407 "TARGET_HARD_FLOAT"
3408 "")
3409
3410 (define_insn "*addsf3"
3411 [(set (match_operand:SF 0 "register_operand" "=f,f")
3412 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3413 (match_operand:SF 2 "general_operand" "f,m")))
3414 (clobber (reg:CC 33))]
3415 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3416 "@
3417 aebr\\t%0,%2
3418 aeb\\t%0,%2"
3419 [(set_attr "op_type" "RRE,RXE")
3420 (set_attr "atype" "reg,mem")])
3421
3422 (define_insn "*addsf3"
3423 [(set (match_operand:SF 0 "register_operand" "=f,f")
3424 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3425 (match_operand:SF 2 "general_operand" "f,m")))
3426 (clobber (reg:CC 33))]
3427 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3428 "@
3429 aer\\t%0,%2
3430 ae\\t%0,%2"
3431 [(set_attr "op_type" "RR,RX")
3432 (set_attr "atype" "reg,mem")])
3433
3434
3435 ;;
3436 ;;- Subtract instructions.
3437 ;;
3438
3439 ;
3440 ; subdi3 instruction pattern(s).
3441 ;
3442
3443 (define_insn "*subdi3_sign"
3444 [(set (match_operand:DI 0 "register_operand" "=d,d")
3445 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3446 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3447 (clobber (reg:CC 33))]
3448 "TARGET_64BIT"
3449 "@
3450 sgfr\\t%0,%2
3451 sgf\\t%0,%2"
3452 [(set_attr "op_type" "RRE,RXE")
3453 (set_attr "atype" "reg,mem")])
3454
3455 (define_insn "*subdi3_zero_cc"
3456 [(set (reg 33)
3457 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3458 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3459 (const_int 0)))
3460 (set (match_operand:DI 0 "register_operand" "=d,d")
3461 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3462 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3463 "@
3464 slgfr\\t%0,%2
3465 slgf\\t%0,%2"
3466 [(set_attr "op_type" "RRE,RXE")
3467 (set_attr "atype" "reg,mem")])
3468
3469 (define_insn "*subdi3_zero_cconly"
3470 [(set (reg 33)
3471 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3472 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3473 (const_int 0)))
3474 (clobber (match_scratch:DI 0 "=d,d"))]
3475 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3476 "@
3477 slgfr\\t%0,%2
3478 slgf\\t%0,%2"
3479 [(set_attr "op_type" "RRE,RXE")
3480 (set_attr "atype" "reg,mem")])
3481
3482 (define_insn "*subdi3_zero"
3483 [(set (match_operand:DI 0 "register_operand" "=d,d")
3484 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3485 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3486 (clobber (reg:CC 33))]
3487 "TARGET_64BIT"
3488 "@
3489 slgfr\\t%0,%2
3490 slgf\\t%0,%2"
3491 [(set_attr "op_type" "RRE,RXE")
3492 (set_attr "atype" "reg,mem")])
3493
3494 (define_insn "*subdi3_cc"
3495 [(set (reg 33)
3496 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3497 (match_operand:DI 2 "general_operand" "d,m"))
3498 (const_int 0)))
3499 (set (match_operand:DI 0 "register_operand" "=d,d")
3500 (minus:DI (match_dup 1) (match_dup 2)))]
3501 "s390_match_ccmode (insn, CCLmode)"
3502 "@
3503 slgr\\t%0,%2
3504 slg\\t%0,%2"
3505 [(set_attr "op_type" "RRE,RXE")
3506 (set_attr "atype" "reg,mem")])
3507
3508 (define_insn "*subdi3_cconly"
3509 [(set (reg 33)
3510 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3511 (match_operand:DI 2 "general_operand" "d,m"))
3512 (const_int 0)))
3513 (clobber (match_scratch:DI 0 "=d,d"))]
3514 "s390_match_ccmode (insn, CCLmode)"
3515 "@
3516 slgr\\t%0,%2
3517 slg\\t%0,%2"
3518 [(set_attr "op_type" "RRE,RXE")
3519 (set_attr "atype" "reg,mem")])
3520
3521 (define_insn "*subdi3_64"
3522 [(set (match_operand:DI 0 "register_operand" "=d,d")
3523 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3524 (match_operand:DI 2 "general_operand" "d,m") ) )
3525 (clobber (reg:CC 33))]
3526 "TARGET_64BIT"
3527 "@
3528 sgr\\t%0,%2
3529 sg\\t%0,%2"
3530 [(set_attr "op_type" "RRE,RRE")
3531 (set_attr "atype" "reg,mem")])
3532
3533 (define_insn_and_split "*subdi3_31"
3534 [(set (match_operand:DI 0 "register_operand" "=&d")
3535 (minus:DI (match_operand:DI 1 "register_operand" "0")
3536 (match_operand:DI 2 "general_operand" "dm") ) )
3537 (clobber (reg:CC 33))]
3538 "!TARGET_64BIT"
3539 "#"
3540 "&& reload_completed"
3541 [(parallel
3542 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3543 (clobber (reg:CC 33))])
3544 (parallel
3545 [(set (reg:CCL2 33)
3546 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3547 (match_dup 7)))
3548 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3549 (set (pc)
3550 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3551 (pc)
3552 (label_ref (match_dup 9))))
3553 (parallel
3554 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3555 (clobber (reg:CC 33))])
3556 (match_dup 9)]
3557 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3558 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3559 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3560 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3561 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3562 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3563 operands[9] = gen_label_rtx ();"
3564 [(set_attr "op_type" "NN")
3565 (set_attr "type" "o3")])
3566
3567 (define_expand "subdi3"
3568 [(parallel
3569 [(set (match_operand:DI 0 "register_operand" "")
3570 (minus:DI (match_operand:DI 1 "register_operand" "")
3571 (match_operand:DI 2 "general_operand" "")))
3572 (clobber (reg:CC 33))])]
3573 ""
3574 "")
3575
3576 ;
3577 ; subsi3 instruction pattern(s).
3578 ;
3579
3580 (define_insn "*subsi3_borrow_cc"
3581 [(set (reg 33)
3582 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3583 (match_operand:SI 2 "general_operand" "d,m"))
3584 (match_dup 1)))
3585 (set (match_operand:SI 0 "register_operand" "=d,d")
3586 (minus:SI (match_dup 1) (match_dup 2)))]
3587 "s390_match_ccmode(insn, CCL2mode)"
3588 "@
3589 slr\\t%0,%2
3590 sl\\t%0,%2"
3591 [(set_attr "op_type" "RR,RX")
3592 (set_attr "atype" "reg,mem")])
3593
3594 (define_insn "*subsi3_borrow_cconly"
3595 [(set (reg 33)
3596 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3597 (match_operand:SI 2 "general_operand" "d,m"))
3598 (match_dup 1)))
3599 (clobber (match_scratch:SI 0 "=d,d"))]
3600 "s390_match_ccmode(insn, CCL2mode)"
3601 "@
3602 slr\\t%0,%2
3603 sl\\t%0,%2"
3604 [(set_attr "op_type" "RR,RX")
3605 (set_attr "atype" "reg,mem")])
3606
3607 (define_insn "*subsi3_cc"
3608 [(set (reg 33)
3609 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3610 (match_operand:SI 2 "general_operand" "d,m"))
3611 (const_int 0)))
3612 (set (match_operand:SI 0 "register_operand" "=d,d")
3613 (minus:SI (match_dup 1) (match_dup 2)))]
3614 "s390_match_ccmode(insn, CCLmode)"
3615 "@
3616 slr\\t%0,%2
3617 sl\\t%0,%2"
3618 [(set_attr "op_type" "RR,RX")
3619 (set_attr "atype" "reg,mem")])
3620
3621 (define_insn "*subsi3_cconly"
3622 [(set (reg 33)
3623 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3624 (match_operand:SI 2 "general_operand" "d,m"))
3625 (const_int 0)))
3626 (clobber (match_scratch:SI 0 "=d,d"))]
3627 "s390_match_ccmode(insn, CCLmode)"
3628 "@
3629 slr\\t%0,%2
3630 sl\\t%0,%2"
3631 [(set_attr "op_type" "RR,RX")
3632 (set_attr "atype" "reg,mem")])
3633
3634 (define_insn "*subsi3_sign"
3635 [(set (match_operand:SI 0 "register_operand" "=d")
3636 (minus:SI (match_operand:SI 1 "register_operand" "0")
3637 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3638 (clobber (reg:CC 33))]
3639 ""
3640 "sh\\t%0,%2"
3641 [(set_attr "op_type" "RX")
3642 (set_attr "atype" "mem")])
3643
3644 (define_insn "*subsi3_sub"
3645 [(set (match_operand:SI 0 "register_operand" "=d")
3646 (minus:SI (match_operand:SI 1 "register_operand" "0")
3647 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3648 (clobber (reg:CC 33))]
3649 ""
3650 "sh\\t%0,%2"
3651 [(set_attr "op_type" "RX")
3652 (set_attr "atype" "mem")])
3653
3654 (define_insn "subsi3"
3655 [(set (match_operand:SI 0 "register_operand" "=d,d")
3656 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3657 (match_operand:SI 2 "general_operand" "d,m")))
3658 (clobber (reg:CC 33))]
3659 ""
3660 "@
3661 sr\\t%0,%2
3662 s\\t%0,%2"
3663 [(set_attr "op_type" "RR,RX")
3664 (set_attr "atype" "reg,mem")])
3665
3666
3667 ;
3668 ; subdf3 instruction pattern(s).
3669 ;
3670
3671 (define_expand "subdf3"
3672 [(parallel
3673 [(set (match_operand:DF 0 "register_operand" "=f,f")
3674 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3675 (match_operand:DF 2 "general_operand" "f,m")))
3676 (clobber (reg:CC 33))])]
3677 "TARGET_HARD_FLOAT"
3678 "")
3679
3680 (define_insn "*subdf3"
3681 [(set (match_operand:DF 0 "register_operand" "=f,f")
3682 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3683 (match_operand:DF 2 "general_operand" "f,m")))
3684 (clobber (reg:CC 33))]
3685 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3686 "@
3687 sdbr\\t%0,%2
3688 sdb\\t%0,%2"
3689 [(set_attr "op_type" "RRE,RXE")
3690 (set_attr "atype" "reg,mem")])
3691
3692 (define_insn "*subdf3_ibm"
3693 [(set (match_operand:DF 0 "register_operand" "=f,f")
3694 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3695 (match_operand:DF 2 "general_operand" "f,m")))
3696 (clobber (reg:CC 33))]
3697 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3698 "@
3699 sdr\\t%0,%2
3700 sd\\t%0,%2"
3701 [(set_attr "op_type" "RR,RX")
3702 (set_attr "atype" "reg,mem")])
3703
3704 ;
3705 ; subsf3 instruction pattern(s).
3706 ;
3707
3708 (define_expand "subsf3"
3709 [(parallel
3710 [(set (match_operand:SF 0 "register_operand" "=f,f")
3711 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3712 (match_operand:SF 2 "general_operand" "f,m")))
3713 (clobber (reg:CC 33))])]
3714 "TARGET_HARD_FLOAT"
3715 "")
3716
3717 (define_insn "*subsf3"
3718 [(set (match_operand:SF 0 "register_operand" "=f,f")
3719 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3720 (match_operand:SF 2 "general_operand" "f,m")))
3721 (clobber (reg:CC 33))]
3722 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3723 "@
3724 sebr\\t%0,%2
3725 seb\\t%0,%2"
3726 [(set_attr "op_type" "RRE,RXE")
3727 (set_attr "atype" "reg,mem")])
3728
3729 (define_insn "*subsf3_ibm"
3730 [(set (match_operand:SF 0 "register_operand" "=f,f")
3731 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3732 (match_operand:SF 2 "general_operand" "f,m")))
3733 (clobber (reg:CC 33))]
3734 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3735 "@
3736 ser\\t%0,%2
3737 se\\t%0,%2"
3738 [(set_attr "op_type" "RR,RX")
3739 (set_attr "atype" "reg,mem")])
3740
3741
3742 ;;
3743 ;;- Multiply instructions.
3744 ;;
3745
3746 ;
3747 ; muldi3 instruction pattern(s).
3748 ;
3749
3750 (define_insn "*muldi3_sign"
3751 [(set (match_operand:DI 0 "register_operand" "=d,d")
3752 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3753 (match_operand:DI 1 "register_operand" "0,0")))]
3754 "TARGET_64BIT"
3755 "@
3756 msgfr\\t%0,%2
3757 msgf\\t%0,%2"
3758 [(set_attr "op_type" "RRE,RXE")
3759 (set_attr "atype" "reg,mem")
3760 (set_attr "type" "imul")])
3761
3762
3763 (define_insn "muldi3"
3764 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3765 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3766 (match_operand:DI 2 "general_operand" "d,K,m")))]
3767 "TARGET_64BIT"
3768 "@
3769 msgr\\t%0,%2
3770 mghi\\t%0,%h2
3771 msg\\t%0,%2"
3772 [(set_attr "op_type" "RRE,RI,RXE")
3773 (set_attr "atype" "reg,reg,mem")
3774 (set_attr "type" "imul")])
3775
3776 ;
3777 ; mulsi3 instruction pattern(s).
3778 ;
3779
3780 (define_insn "mulsi3"
3781 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3782 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3783 (match_operand:SI 2 "general_operand" "d,K,m")))]
3784 ""
3785 "@
3786 msr\\t%0,%2
3787 mhi\\t%0,%h2
3788 ms\\t%0,%2"
3789 [(set_attr "op_type" "RRE,RI,RX")
3790 (set_attr "atype" "reg,reg,mem")
3791 (set_attr "type" "imul")])
3792
3793 ;
3794 ; mulsidi3 instruction pattern(s).
3795 ;
3796
3797 (define_expand "mulsidi3"
3798 [(set (match_operand:DI 0 "register_operand" "")
3799 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3800 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3801 "!TARGET_64BIT"
3802 "
3803 {
3804 rtx insn;
3805
3806 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3807 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3808
3809 REG_NOTES (insn) =
3810 gen_rtx_EXPR_LIST (REG_EQUAL,
3811 gen_rtx_MULT (DImode,
3812 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3813 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3814 REG_NOTES (insn));
3815 DONE;
3816 }")
3817
3818 (define_insn "mulsi_6432"
3819 [(set (match_operand:DI 0 "register_operand" "=d,d")
3820 (mult:DI (sign_extend:DI
3821 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3822 (sign_extend:DI
3823 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3824 "!TARGET_64BIT"
3825 "@
3826 mr\\t%0,%2
3827 m\\t%0,%2"
3828 [(set_attr "op_type" "RR,RX")
3829 (set_attr "atype" "reg,mem")
3830 (set_attr "type" "imul")])
3831
3832 ;
3833 ; muldf3 instruction pattern(s).
3834 ;
3835
3836 (define_expand "muldf3"
3837 [(parallel
3838 [(set (match_operand:DF 0 "register_operand" "=f,f")
3839 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3840 (match_operand:DF 2 "general_operand" "f,m")))
3841 (clobber (reg:CC 33))])]
3842 "TARGET_HARD_FLOAT"
3843 "")
3844
3845 (define_insn "*muldf3"
3846 [(set (match_operand:DF 0 "register_operand" "=f,f")
3847 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3848 (match_operand:DF 2 "general_operand" "f,m")))
3849 (clobber (reg:CC 33))]
3850 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3851 "@
3852 mdbr\\t%0,%2
3853 mdb\\t%0,%2"
3854 [(set_attr "op_type" "RRE,RXE")
3855 (set_attr "type" "fmul")
3856 (set_attr "atype" "reg,mem")])
3857
3858 (define_insn "*muldf3_ibm"
3859 [(set (match_operand:DF 0 "register_operand" "=f,f")
3860 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3861 (match_operand:DF 2 "general_operand" "f,m")))
3862 (clobber (reg:CC 33))]
3863 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3864 "@
3865 mdr\\t%0,%2
3866 md\\t%0,%2"
3867 [(set_attr "op_type" "RR,RX")
3868 (set_attr "type" "fmul")
3869 (set_attr "atype" "reg,mem")])
3870
3871 ;
3872 ; mulsf3 instruction pattern(s).
3873 ;
3874
3875 (define_expand "mulsf3"
3876 [(parallel
3877 [(set (match_operand:SF 0 "register_operand" "=f,f")
3878 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3879 (match_operand:SF 2 "general_operand" "f,m")))
3880 (clobber (reg:CC 33))])]
3881 "TARGET_HARD_FLOAT"
3882 "")
3883
3884 (define_insn "*mulsf3"
3885 [(set (match_operand:SF 0 "register_operand" "=f,f")
3886 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3887 (match_operand:SF 2 "general_operand" "f,m")))
3888 (clobber (reg:CC 33))]
3889 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3890 "@
3891 meebr\\t%0,%2
3892 meeb\\t%0,%2"
3893 [(set_attr "op_type" "RRE,RXE")
3894 (set_attr "type" "fmul")
3895 (set_attr "atype" "reg,mem")])
3896
3897 (define_insn "*mulsf3_ibm"
3898 [(set (match_operand:SF 0 "register_operand" "=f,f")
3899 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3900 (match_operand:SF 2 "general_operand" "f,m")))
3901 (clobber (reg:CC 33))]
3902 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3903 "@
3904 mer\\t%0,%2
3905 me\\t%0,%2"
3906 [(set_attr "op_type" "RR,RX")
3907 (set_attr "type" "fmul")
3908 (set_attr "atype" "reg,mem")])
3909
3910
3911 ;;
3912 ;;- Divide and modulo instructions.
3913 ;;
3914
3915 ;
3916 ; divmoddi4 instruction pattern(s).
3917 ;
3918
3919 (define_expand "divmoddi4"
3920 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3921 (div:DI (match_operand:DI 1 "general_operand" "")
3922 (match_operand:DI 2 "general_operand" "")))
3923 (set (match_operand:DI 3 "general_operand" "")
3924 (mod:DI (match_dup 1) (match_dup 2)))])
3925 (clobber (match_dup 4))]
3926 "TARGET_64BIT"
3927 "
3928 {
3929 rtx insn, div_equal, mod_equal, equal;
3930
3931 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3932 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3933 equal = gen_rtx_IOR (TImode,
3934 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3935 gen_rtx_ASHIFT (TImode,
3936 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3937 GEN_INT (64)));
3938
3939 operands[4] = gen_reg_rtx(TImode);
3940 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3941 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3942 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3943 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3944 REG_NOTES (insn) =
3945 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3946
3947 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3948 REG_NOTES (insn) =
3949 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3950
3951 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3952 REG_NOTES (insn) =
3953 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3954
3955 DONE;
3956 }")
3957
3958 (define_insn "divmodtidi3"
3959 [(set (match_operand:TI 0 "register_operand" "=d,d")
3960 (ior:TI
3961 (zero_extend:TI
3962 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3963 (match_operand:DI 2 "general_operand" "d,m")))
3964 (ashift:TI
3965 (zero_extend:TI
3966 (mod:DI (truncate:DI (match_dup 1))
3967 (match_dup 2)))
3968 (const_int 64))))]
3969 "TARGET_64BIT"
3970 "@
3971 dsgr\\t%0,%2
3972 dsg\\t%0,%2"
3973 [(set_attr "op_type" "RRE,RXE")
3974 (set_attr "type" "idiv")
3975 (set_attr "atype" "reg,mem")])
3976
3977 (define_insn "divmodtisi3"
3978 [(set (match_operand:TI 0 "register_operand" "=d,d")
3979 (ior:TI
3980 (zero_extend:TI
3981 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3982 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3983 (ashift:TI
3984 (zero_extend:TI
3985 (mod:DI (truncate:DI (match_dup 1))
3986 (sign_extend:DI (match_dup 2))))
3987 (const_int 64))))]
3988 "TARGET_64BIT"
3989 "@
3990 dsgfr\\t%0,%2
3991 dsgf\\t%0,%2"
3992 [(set_attr "op_type" "RRE,RXE")
3993 (set_attr "type" "idiv")
3994 (set_attr "atype" "reg,mem")])
3995
3996 ;
3997 ; udivmoddi4 instruction pattern(s).
3998 ;
3999
4000 (define_expand "udivmoddi4"
4001 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4002 (udiv:DI (match_operand:DI 1 "general_operand" "")
4003 (match_operand:DI 2 "nonimmediate_operand" "")))
4004 (set (match_operand:DI 3 "general_operand" "")
4005 (umod:DI (match_dup 1) (match_dup 2)))])
4006 (clobber (match_dup 4))]
4007 "TARGET_64BIT"
4008 "
4009 {
4010 rtx insn, div_equal, mod_equal, equal;
4011
4012 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4013 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4014 equal = gen_rtx_IOR (TImode,
4015 gen_rtx_ZERO_EXTEND (TImode, div_equal),
4016 gen_rtx_ASHIFT (TImode,
4017 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4018 GEN_INT (64)));
4019
4020 operands[4] = gen_reg_rtx(TImode);
4021 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4022 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4023 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4024 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4025 REG_NOTES (insn) =
4026 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4027
4028 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4029 REG_NOTES (insn) =
4030 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4031
4032 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4033 REG_NOTES (insn) =
4034 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4035
4036 DONE;
4037 }")
4038
4039 (define_insn "udivmodtidi3"
4040 [(set (match_operand:TI 0 "register_operand" "=d,d")
4041 (ior:TI (zero_extend:TI
4042 (truncate:DI
4043 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
4044 (zero_extend:TI
4045 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4046 (ashift:TI
4047 (zero_extend:TI
4048 (truncate:DI
4049 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
4050 (const_int 64))))]
4051 "TARGET_64BIT"
4052 "@
4053 dlgr\\t%0,%2
4054 dlg\\t%0,%2"
4055 [(set_attr "op_type" "RRE,RXE")
4056 (set_attr "type" "idiv")
4057 (set_attr "atype" "reg,mem")])
4058
4059 ;
4060 ; divmodsi4 instruction pattern(s).
4061 ;
4062
4063 (define_expand "divmodsi4"
4064 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4065 (div:SI (match_operand:SI 1 "general_operand" "")
4066 (match_operand:SI 2 "nonimmediate_operand" "")))
4067 (set (match_operand:SI 3 "general_operand" "")
4068 (mod:SI (match_dup 1) (match_dup 2)))])
4069 (clobber (match_dup 4))]
4070 "!TARGET_64BIT"
4071 "
4072 {
4073 rtx insn, div_equal, mod_equal, equal;
4074
4075 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4076 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4077 equal = gen_rtx_IOR (DImode,
4078 gen_rtx_ZERO_EXTEND (DImode, div_equal),
4079 gen_rtx_ASHIFT (DImode,
4080 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4081 GEN_INT (32)));
4082
4083 operands[4] = gen_reg_rtx(DImode);
4084 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4085 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4086 REG_NOTES (insn) =
4087 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4088
4089 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4090 REG_NOTES (insn) =
4091 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4092
4093 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4094 REG_NOTES (insn) =
4095 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4096
4097 DONE;
4098 }")
4099
4100 (define_insn "divmoddisi3"
4101 [(set (match_operand:DI 0 "register_operand" "=d,d")
4102 (ior:DI (zero_extend:DI
4103 (truncate:SI
4104 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4105 (sign_extend:DI
4106 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4107 (ashift:DI
4108 (zero_extend:DI
4109 (truncate:SI
4110 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4111 (const_int 32))))]
4112 "!TARGET_64BIT"
4113 "@
4114 dr\\t%0,%2
4115 d\\t%0,%2"
4116 [(set_attr "op_type" "RR,RX")
4117 (set_attr "type" "idiv")
4118 (set_attr "atype" "reg,mem")])
4119
4120 ;
4121 ; udivsi3 and umodsi3 instruction pattern(s).
4122 ;
4123
4124
4125 (define_expand "udivsi3"
4126 [(set (match_operand:SI 0 "register_operand" "=d")
4127 (udiv:SI (match_operand:SI 1 "general_operand" "")
4128 (match_operand:SI 2 "general_operand" "")))
4129 (clobber (match_dup 3))]
4130 "!TARGET_64BIT"
4131 "
4132 {
4133 rtx insn, udiv_equal, umod_equal, equal;
4134
4135 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4136 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4137 equal = gen_rtx_IOR (DImode,
4138 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4139 gen_rtx_ASHIFT (DImode,
4140 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4141 GEN_INT (32)));
4142
4143 operands[3] = gen_reg_rtx (DImode);
4144
4145 if (CONSTANT_P (operands[2]))
4146 {
4147 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4148 {
4149 rtx label1 = gen_label_rtx ();
4150
4151 operands[1] = make_safe_from (operands[1], operands[0]);
4152 emit_move_insn (operands[0], const0_rtx);
4153 emit_insn (gen_cmpsi (operands[1], operands[2]));
4154 emit_jump_insn (gen_bltu (label1));
4155 emit_move_insn (operands[0], const1_rtx);
4156 emit_label (label1);
4157 }
4158 else
4159 {
4160 operands[2] = force_reg (SImode, operands[2]);
4161 operands[2] = make_safe_from (operands[2], operands[0]);
4162
4163 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4164 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4165 operands[2]));
4166 REG_NOTES (insn) =
4167 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4168
4169 insn = emit_move_insn (operands[0],
4170 gen_lowpart (SImode, operands[3]));
4171 REG_NOTES (insn) =
4172 gen_rtx_EXPR_LIST (REG_EQUAL,
4173 udiv_equal, REG_NOTES (insn));
4174 }
4175 }
4176 else
4177 {
4178 rtx label1 = gen_label_rtx ();
4179 rtx label2 = gen_label_rtx ();
4180 rtx label3 = gen_label_rtx ();
4181
4182 operands[1] = force_reg (SImode, operands[1]);
4183 operands[1] = make_safe_from (operands[1], operands[0]);
4184 operands[2] = force_reg (SImode, operands[2]);
4185 operands[2] = make_safe_from (operands[2], operands[0]);
4186
4187 emit_move_insn (operands[0], const0_rtx);
4188 emit_insn (gen_cmpsi (operands[2], operands[1]));
4189 emit_jump_insn (gen_bgtu (label3));
4190 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4191 emit_jump_insn (gen_blt (label2));
4192 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4193 emit_jump_insn (gen_beq (label1));
4194 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4195 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4196 operands[2]));
4197 REG_NOTES (insn) =
4198 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4199
4200 insn = emit_move_insn (operands[0],
4201 gen_lowpart (SImode, operands[3]));
4202 REG_NOTES (insn) =
4203 gen_rtx_EXPR_LIST (REG_EQUAL,
4204 udiv_equal, REG_NOTES (insn));
4205 emit_jump (label3);
4206 emit_label (label1);
4207 emit_move_insn (operands[0], operands[1]);
4208 emit_jump (label3);
4209 emit_label (label2);
4210 emit_move_insn (operands[0], const1_rtx);
4211 emit_label (label3);
4212 }
4213 emit_move_insn (operands[0], operands[0]);
4214 DONE;
4215 }")
4216
4217 (define_expand "umodsi3"
4218 [(set (match_operand:SI 0 "register_operand" "=d")
4219 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4220 (match_operand:SI 2 "nonimmediate_operand" "")))
4221 (clobber (match_dup 3))]
4222 "!TARGET_64BIT"
4223 "
4224 {
4225 rtx insn, udiv_equal, umod_equal, equal;
4226
4227 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4228 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4229 equal = gen_rtx_IOR (DImode,
4230 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4231 gen_rtx_ASHIFT (DImode,
4232 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4233 GEN_INT (32)));
4234
4235 operands[3] = gen_reg_rtx (DImode);
4236
4237 if (CONSTANT_P (operands[2]))
4238 {
4239 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4240 {
4241 rtx label1 = gen_label_rtx ();
4242
4243 operands[1] = make_safe_from (operands[1], operands[0]);
4244 emit_move_insn (operands[0], operands[1]);
4245 emit_insn (gen_cmpsi (operands[0], operands[2]));
4246 emit_jump_insn (gen_bltu (label1));
4247 emit_insn (gen_abssi2 (operands[0], operands[2]));
4248 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4249 emit_label (label1);
4250 }
4251 else
4252 {
4253 operands[2] = force_reg (SImode, operands[2]);
4254 operands[2] = make_safe_from (operands[2], operands[0]);
4255
4256 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4257 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4258 operands[2]));
4259 REG_NOTES (insn) =
4260 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4261
4262 insn = emit_move_insn (operands[0],
4263 gen_highpart (SImode, operands[3]));
4264 REG_NOTES (insn) =
4265 gen_rtx_EXPR_LIST (REG_EQUAL,
4266 umod_equal, REG_NOTES (insn));
4267 }
4268 }
4269 else
4270 {
4271 rtx label1 = gen_label_rtx ();
4272 rtx label2 = gen_label_rtx ();
4273 rtx label3 = gen_label_rtx ();
4274
4275 operands[1] = force_reg (SImode, operands[1]);
4276 operands[1] = make_safe_from (operands[1], operands[0]);
4277 operands[2] = force_reg (SImode, operands[2]);
4278 operands[2] = make_safe_from (operands[2], operands[0]);
4279
4280 emit_move_insn(operands[0], operands[1]);
4281 emit_insn (gen_cmpsi (operands[2], operands[1]));
4282 emit_jump_insn (gen_bgtu (label3));
4283 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4284 emit_jump_insn (gen_blt (label2));
4285 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4286 emit_jump_insn (gen_beq (label1));
4287 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4288 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4289 operands[2]));
4290 REG_NOTES (insn) =
4291 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4292
4293 insn = emit_move_insn (operands[0],
4294 gen_highpart (SImode, operands[3]));
4295 REG_NOTES (insn) =
4296 gen_rtx_EXPR_LIST (REG_EQUAL,
4297 umod_equal, REG_NOTES (insn));
4298 emit_jump (label3);
4299 emit_label (label1);
4300 emit_move_insn (operands[0], const0_rtx);
4301 emit_jump (label3);
4302 emit_label (label2);
4303 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4304 emit_label (label3);
4305 }
4306 DONE;
4307 }")
4308
4309 ;
4310 ; divdf3 instruction pattern(s).
4311 ;
4312
4313 (define_expand "divdf3"
4314 [(parallel
4315 [(set (match_operand:DF 0 "register_operand" "=f,f")
4316 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4317 (match_operand:DF 2 "general_operand" "f,m")))
4318 (clobber (reg:CC 33))])]
4319 "TARGET_HARD_FLOAT"
4320 "")
4321
4322 (define_insn "*divdf3"
4323 [(set (match_operand:DF 0 "register_operand" "=f,f")
4324 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4325 (match_operand:DF 2 "general_operand" "f,m")))
4326 (clobber (reg:CC 33))]
4327 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4328 "@
4329 ddbr\\t%0,%2
4330 ddb\\t%0,%2"
4331 [(set_attr "op_type" "RRE,RXE")
4332 (set_attr "type" "fdiv")
4333 (set_attr "atype" "reg,mem")])
4334
4335 (define_insn "*divdf3_ibm"
4336 [(set (match_operand:DF 0 "register_operand" "=f,f")
4337 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4338 (match_operand:DF 2 "general_operand" "f,m")))
4339 (clobber (reg:CC 33))]
4340 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4341 "@
4342 ddr\\t%0,%2
4343 dd\\t%0,%2"
4344 [(set_attr "op_type" "RR,RX")
4345 (set_attr "type" "fdiv")
4346 (set_attr "atype" "reg,mem")])
4347
4348 ;
4349 ; divsf3 instruction pattern(s).
4350 ;
4351
4352 (define_expand "divsf3"
4353 [(parallel
4354 [(set (match_operand:SF 0 "register_operand" "=f,f")
4355 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4356 (match_operand:SF 2 "general_operand" "f,m")))
4357 (clobber (reg:CC 33))])]
4358 "TARGET_HARD_FLOAT"
4359 "")
4360
4361 (define_insn "*divsf3"
4362 [(set (match_operand:SF 0 "register_operand" "=f,f")
4363 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4364 (match_operand:SF 2 "general_operand" "f,m")))
4365 (clobber (reg:CC 33))]
4366 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4367 "@
4368 debr\\t%0,%2
4369 deb\\t%0,%2"
4370 [(set_attr "op_type" "RRE,RXE")
4371 (set_attr "type" "fdiv")
4372 (set_attr "atype" "reg,mem")])
4373
4374 (define_insn "*divsf3"
4375 [(set (match_operand:SF 0 "register_operand" "=f,f")
4376 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4377 (match_operand:SF 2 "general_operand" "f,m")))
4378 (clobber (reg:CC 33))]
4379 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4380 "@
4381 der\\t%0,%2
4382 de\\t%0,%2"
4383 [(set_attr "op_type" "RR,RX")
4384 (set_attr "type" "fdiv")
4385 (set_attr "atype" "reg,mem")])
4386
4387
4388 ;;
4389 ;;- And instructions.
4390 ;;
4391
4392 ;
4393 ; anddi3 instruction pattern(s).
4394 ;
4395
4396 (define_insn "*anddi3_cc"
4397 [(set (reg 33)
4398 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4399 (match_operand:DI 2 "general_operand" "d,m"))
4400 (const_int 0)))
4401 (set (match_operand:DI 0 "register_operand" "=d,d")
4402 (and:DI (match_dup 1) (match_dup 2)))]
4403 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4404 "@
4405 ngr\\t%0,%2
4406 ng\\t%0,%2"
4407 [(set_attr "op_type" "RRE,RXE")
4408 (set_attr "atype" "reg,mem")])
4409
4410 (define_insn "*anddi3_cconly"
4411 [(set (reg 33)
4412 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4413 (match_operand:DI 2 "general_operand" "d,m"))
4414 (const_int 0)))
4415 (clobber (match_scratch:DI 0 "=d,d"))]
4416 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4417 "@
4418 ngr\\t%0,%2
4419 ng\\t%0,%2"
4420 [(set_attr "op_type" "RRE,RXE")
4421 (set_attr "atype" "reg,mem")])
4422
4423 (define_insn "*anddi3_ni"
4424 [(set (match_operand:DI 0 "register_operand" "=d")
4425 (and:DI (match_operand:DI 1 "register_operand" "%0")
4426 (match_operand:DI 2 "immediate_operand" "n")))
4427 (clobber (reg:CC 33))]
4428 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4429 "*
4430 {
4431 int part = s390_single_hi (operands[2], DImode, -1);
4432 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4433
4434 switch (part)
4435 {
4436 case 0: return \"nihh\\t%0,%x2\";
4437 case 1: return \"nihl\\t%0,%x2\";
4438 case 2: return \"nilh\\t%0,%x2\";
4439 case 3: return \"nill\\t%0,%x2\";
4440 default: abort ();
4441 }
4442 }"
4443 [(set_attr "op_type" "RI")
4444 (set_attr "atype" "reg")])
4445
4446 (define_insn "anddi3"
4447 [(set (match_operand:DI 0 "register_operand" "=d,d")
4448 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4449 (match_operand:DI 2 "general_operand" "d,m")))
4450 (clobber (reg:CC 33))]
4451 "TARGET_64BIT"
4452 "@
4453 ngr\\t%0,%2
4454 ng\\t%0,%2"
4455 [(set_attr "op_type" "RRE,RXE")
4456 (set_attr "atype" "reg,mem")])
4457
4458 (define_insn "*anddi3_ss"
4459 [(set (match_operand:DI 0 "s_operand" "=Q")
4460 (and:DI (match_dup 0)
4461 (match_operand:DI 1 "s_imm_operand" "Q")))
4462 (clobber (reg:CC 33))]
4463 ""
4464 "nc\\t%O0(8,%R0),%1"
4465 [(set_attr "op_type" "SS")
4466 (set_attr "atype" "mem")])
4467
4468 (define_insn "*anddi3_ss_inv"
4469 [(set (match_operand:DI 0 "s_operand" "=Q")
4470 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4471 (match_dup 0)))
4472 (clobber (reg:CC 33))]
4473 ""
4474 "nc\\t%O0(8,%R0),%1"
4475 [(set_attr "op_type" "SS")
4476 (set_attr "atype" "mem")])
4477
4478 ;
4479 ; andsi3 instruction pattern(s).
4480 ;
4481
4482 (define_insn "*andsi3_cc"
4483 [(set (reg 33)
4484 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4485 (match_operand:SI 2 "general_operand" "d,m"))
4486 (const_int 0)))
4487 (set (match_operand:SI 0 "register_operand" "=d,d")
4488 (and:SI (match_dup 1) (match_dup 2)))]
4489 "s390_match_ccmode(insn, CCTmode)"
4490 "@
4491 nr\\t%0,%2
4492 n\\t%0,%2"
4493 [(set_attr "op_type" "RR,RX")
4494 (set_attr "atype" "reg,mem")])
4495
4496 (define_insn "*andsi3_cconly"
4497 [(set (reg 33)
4498 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4499 (match_operand:SI 2 "general_operand" "d,m"))
4500 (const_int 0)))
4501 (clobber (match_scratch:SI 0 "=d,d"))]
4502 "s390_match_ccmode(insn, CCTmode)"
4503 "@
4504 nr\\t%0,%2
4505 n\\t%0,%2"
4506 [(set_attr "op_type" "RR,RX")
4507 (set_attr "atype" "reg,mem")])
4508
4509 (define_insn "*andsi3_ni"
4510 [(set (match_operand:SI 0 "register_operand" "=d")
4511 (and:SI (match_operand:SI 1 "register_operand" "%0")
4512 (match_operand:SI 2 "immediate_operand" "n")))
4513 (clobber (reg:CC 33))]
4514 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4515 "*
4516 {
4517 int part = s390_single_hi (operands[2], SImode, -1);
4518 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4519
4520 switch (part)
4521 {
4522 case 0: return \"nilh\\t%0,%x2\";
4523 case 1: return \"nill\\t%0,%x2\";
4524 default: abort ();
4525 }
4526 }"
4527 [(set_attr "op_type" "RI")
4528 (set_attr "atype" "reg")])
4529
4530 (define_insn "andsi3"
4531 [(set (match_operand:SI 0 "register_operand" "=d,d")
4532 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4533 (match_operand:SI 2 "general_operand" "d,m")))
4534 (clobber (reg:CC 33))]
4535 ""
4536 "@
4537 nr\\t%0,%2
4538 n\\t%0,%2"
4539 [(set_attr "op_type" "RR,RX")
4540 (set_attr "atype" "reg,mem")])
4541
4542 (define_insn "*andsi3_ss"
4543 [(set (match_operand:SI 0 "s_operand" "=Q")
4544 (and:SI (match_dup 0)
4545 (match_operand:SI 1 "s_imm_operand" "Q")))
4546 (clobber (reg:CC 33))]
4547 ""
4548 "nc\\t%O0(4,%R0),%1"
4549 [(set_attr "op_type" "SS")
4550 (set_attr "atype" "mem")])
4551
4552 (define_insn "*andsi3_ss_inv"
4553 [(set (match_operand:SI 0 "s_operand" "=Q")
4554 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4555 (match_dup 0)))
4556 (clobber (reg:CC 33))]
4557 ""
4558 "nc\\t%O0(4,%R0),%1"
4559 [(set_attr "op_type" "SS")
4560 (set_attr "atype" "mem")])
4561
4562 ;
4563 ; andhi3 instruction pattern(s).
4564 ;
4565
4566 (define_insn "*andhi3_ni"
4567 [(set (match_operand:HI 0 "register_operand" "=d,d")
4568 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4569 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4570 (clobber (reg:CC 33))]
4571 "TARGET_64BIT"
4572 "@
4573 nr\\t%0,%2
4574 nill\\t%0,%x2"
4575 [(set_attr "op_type" "RR,RI")
4576 (set_attr "atype" "reg")])
4577
4578 (define_insn "andhi3"
4579 [(set (match_operand:HI 0 "register_operand" "=d")
4580 (and:HI (match_operand:HI 1 "register_operand" "%0")
4581 (match_operand:HI 2 "nonmemory_operand" "d")))
4582 (clobber (reg:CC 33))]
4583 ""
4584 "nr\\t%0,%2"
4585 [(set_attr "op_type" "RR")
4586 (set_attr "atype" "reg")])
4587
4588 (define_insn "*andhi3_ss"
4589 [(set (match_operand:HI 0 "s_operand" "=Q")
4590 (and:HI (match_dup 0)
4591 (match_operand:HI 1 "s_imm_operand" "Q")))
4592 (clobber (reg:CC 33))]
4593 ""
4594 "nc\\t%O0(2,%R0),%1"
4595 [(set_attr "op_type" "SS")
4596 (set_attr "atype" "mem")])
4597
4598 (define_insn "*andhi3_ss_inv"
4599 [(set (match_operand:HI 0 "s_operand" "=Q")
4600 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4601 (match_dup 0)))
4602 (clobber (reg:CC 33))]
4603 ""
4604 "nc\\t%O0(2,%R0),%1"
4605 [(set_attr "op_type" "SS")
4606 (set_attr "atype" "mem")])
4607
4608 ;
4609 ; andqi3 instruction pattern(s).
4610 ;
4611
4612 (define_insn "*andqi3_ni"
4613 [(set (match_operand:QI 0 "register_operand" "=d,d")
4614 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4615 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4616 (clobber (reg:CC 33))]
4617 "TARGET_64BIT"
4618 "@
4619 nr\\t%0,%2
4620 nill\\t%0,%b2"
4621 [(set_attr "op_type" "RR,RI")
4622 (set_attr "atype" "reg")])
4623
4624 (define_insn "andqi3"
4625 [(set (match_operand:QI 0 "register_operand" "=d")
4626 (and:QI (match_operand:QI 1 "register_operand" "%0")
4627 (match_operand:QI 2 "nonmemory_operand" "d")))
4628 (clobber (reg:CC 33))]
4629 ""
4630 "nr\\t%0,%2"
4631 [(set_attr "op_type" "RR")
4632 (set_attr "atype" "reg")])
4633
4634 (define_insn "*andqi3_ss"
4635 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4636 (and:QI (match_dup 0)
4637 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4638 (clobber (reg:CC 33))]
4639 ""
4640 "@
4641 ni\\t%0,%b1
4642 nc\\t%O0(1,%R0),%1"
4643 [(set_attr "op_type" "SI,SS")
4644 (set_attr "atype" "mem")])
4645
4646 (define_insn "*andqi3_ss_inv"
4647 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4648 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4649 (match_dup 0)))
4650 (clobber (reg:CC 33))]
4651 ""
4652 "@
4653 ni\\t%0,%b1
4654 nc\\t%O0(1,%R0),%1"
4655 [(set_attr "op_type" "SI,SS")
4656 (set_attr "atype" "mem")])
4657
4658
4659 ;;
4660 ;;- Bit set (inclusive or) instructions.
4661 ;;
4662
4663 ;
4664 ; iordi3 instruction pattern(s).
4665 ;
4666
4667 (define_insn "*iordi3_cc"
4668 [(set (reg 33)
4669 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4670 (match_operand:DI 2 "general_operand" "d,m"))
4671 (const_int 0)))
4672 (set (match_operand:DI 0 "register_operand" "=d,d")
4673 (ior:DI (match_dup 1) (match_dup 2)))]
4674 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4675 "@
4676 ogr\\t%0,%2
4677 og\\t%0,%2"
4678 [(set_attr "op_type" "RRE,RXE")
4679 (set_attr "atype" "reg,mem")])
4680
4681 (define_insn "*iordi3_cconly"
4682 [(set (reg 33)
4683 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4684 (match_operand:DI 2 "general_operand" "d,m"))
4685 (const_int 0)))
4686 (clobber (match_scratch:DI 0 "=d,d"))]
4687 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4688 "@
4689 ogr\\t%0,%2
4690 og\\t%0,%2"
4691 [(set_attr "op_type" "RRE,RXE")
4692 (set_attr "atype" "reg,mem")])
4693
4694 (define_insn "*iordi3_oi"
4695 [(set (match_operand:DI 0 "register_operand" "=d")
4696 (ior:DI (match_operand:DI 1 "register_operand" "%0")
4697 (match_operand:DI 2 "immediate_operand" "n")))
4698 (clobber (reg:CC 33))]
4699 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4700 "*
4701 {
4702 int part = s390_single_hi (operands[2], DImode, 0);
4703 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4704
4705 switch (part)
4706 {
4707 case 0: return \"oihh\\t%0,%x2\";
4708 case 1: return \"oihl\\t%0,%x2\";
4709 case 2: return \"oilh\\t%0,%x2\";
4710 case 3: return \"oill\\t%0,%x2\";
4711 default: abort ();
4712 }
4713 }"
4714 [(set_attr "op_type" "RI")
4715 (set_attr "atype" "reg")])
4716
4717 (define_insn "iordi3"
4718 [(set (match_operand:DI 0 "register_operand" "=d,d")
4719 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4720 (match_operand:DI 2 "general_operand" "d,m")))
4721 (clobber (reg:CC 33))]
4722 "TARGET_64BIT"
4723 "@
4724 ogr\\t%0,%2
4725 og\\t%0,%2"
4726 [(set_attr "op_type" "RRE,RXE")
4727 (set_attr "atype" "reg,mem")])
4728
4729 (define_insn "*iordi3_ss"
4730 [(set (match_operand:DI 0 "s_operand" "=Q")
4731 (ior:DI (match_dup 0)
4732 (match_operand:DI 1 "s_imm_operand" "Q")))
4733 (clobber (reg:CC 33))]
4734 ""
4735 "oc\\t%O0(8,%R0),%1"
4736 [(set_attr "op_type" "SS")
4737 (set_attr "atype" "mem")])
4738
4739 (define_insn "*iordi3_ss_inv"
4740 [(set (match_operand:DI 0 "s_operand" "=Q")
4741 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4742 (match_dup 0)))
4743 (clobber (reg:CC 33))]
4744 ""
4745 "oc\\t%O0(8,%R0),%1"
4746 [(set_attr "op_type" "SS")
4747 (set_attr "atype" "mem")])
4748
4749 ;
4750 ; iorsi3 instruction pattern(s).
4751 ;
4752
4753 (define_insn "*iorsi3_cc"
4754 [(set (reg 33)
4755 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4756 (match_operand:SI 2 "general_operand" "d,m"))
4757 (const_int 0)))
4758 (set (match_operand:SI 0 "register_operand" "=d,d")
4759 (ior:SI (match_dup 1) (match_dup 2)))]
4760 "s390_match_ccmode(insn, CCTmode)"
4761 "@
4762 or\\t%0,%2
4763 o\\t%0,%2"
4764 [(set_attr "op_type" "RR,RX")
4765 (set_attr "atype" "reg,mem")])
4766
4767 (define_insn "*iorsi3_cconly"
4768 [(set (reg 33)
4769 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4770 (match_operand:SI 2 "general_operand" "d,m"))
4771 (const_int 0)))
4772 (clobber (match_scratch:SI 0 "=d,d"))]
4773 "s390_match_ccmode(insn, CCTmode)"
4774 "@
4775 or\\t%0,%2
4776 o\\t%0,%2"
4777 [(set_attr "op_type" "RR,RX")
4778 (set_attr "atype" "reg,mem")])
4779
4780 (define_insn "*iorsi3_oi"
4781 [(set (match_operand:SI 0 "register_operand" "=d")
4782 (ior:SI (match_operand:SI 1 "register_operand" "%0")
4783 (match_operand:SI 2 "immediate_operand" "n")))
4784 (clobber (reg:CC 33))]
4785 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4786 "*
4787 {
4788 int part = s390_single_hi (operands[2], SImode, 0);
4789 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4790
4791 switch (part)
4792 {
4793 case 0: return \"oilh\\t%0,%x2\";
4794 case 1: return \"oill\\t%0,%x2\";
4795 default: abort ();
4796 }
4797 }"
4798 [(set_attr "op_type" "RI")
4799 (set_attr "atype" "reg")])
4800
4801 (define_insn "iorsi3"
4802 [(set (match_operand:SI 0 "register_operand" "=d,d")
4803 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4804 (match_operand:SI 2 "general_operand" "d,m")))
4805 (clobber (reg:CC 33))]
4806 ""
4807 "@
4808 or\\t%0,%2
4809 o\\t%0,%2"
4810 [(set_attr "op_type" "RR,RX")
4811 (set_attr "atype" "reg,mem")])
4812
4813 (define_insn "*iorsi3_ss"
4814 [(set (match_operand:SI 0 "s_operand" "=Q")
4815 (ior:SI (match_dup 0)
4816 (match_operand:SI 1 "s_imm_operand" "Q")))
4817 (clobber (reg:CC 33))]
4818 ""
4819 "oc\\t%O0(4,%R0),%1"
4820 [(set_attr "op_type" "SS")
4821 (set_attr "atype" "mem")])
4822
4823 (define_insn "*iorsi3_ss_inv"
4824 [(set (match_operand:SI 0 "s_operand" "=Q")
4825 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4826 (match_dup 0)))
4827 (clobber (reg:CC 33))]
4828 ""
4829 "oc\\t%O0(4,%R0),%1"
4830 [(set_attr "op_type" "SS")
4831 (set_attr "atype" "mem")])
4832
4833 ;
4834 ; iorhi3 instruction pattern(s).
4835 ;
4836
4837 (define_insn "*iorhi3_oi"
4838 [(set (match_operand:HI 0 "register_operand" "=d,d")
4839 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4840 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4841 (clobber (reg:CC 33))]
4842 "TARGET_64BIT"
4843 "@
4844 or\\t%0,%2
4845 oill\\t%0,%x2"
4846 [(set_attr "op_type" "RR,RI")
4847 (set_attr "atype" "reg")])
4848
4849 (define_insn "iorhi3"
4850 [(set (match_operand:HI 0 "register_operand" "=d")
4851 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4852 (match_operand:HI 2 "nonmemory_operand" "d")))
4853 (clobber (reg:CC 33))]
4854 ""
4855 "or\\t%0,%2"
4856 [(set_attr "op_type" "RR")
4857 (set_attr "atype" "reg")])
4858
4859 (define_insn "*iorhi3_ss"
4860 [(set (match_operand:HI 0 "s_operand" "=Q")
4861 (ior:HI (match_dup 0)
4862 (match_operand:HI 1 "s_imm_operand" "Q")))
4863 (clobber (reg:CC 33))]
4864 ""
4865 "oc\\t%O0(2,%R0),%1"
4866 [(set_attr "op_type" "SS")
4867 (set_attr "atype" "mem")])
4868
4869 (define_insn "*iorhi3_ss_inv"
4870 [(set (match_operand:HI 0 "s_operand" "=Q")
4871 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4872 (match_dup 0)))
4873 (clobber (reg:CC 33))]
4874 ""
4875 "oc\\t%O0(2,%R0),%1"
4876 [(set_attr "op_type" "SS")
4877 (set_attr "atype" "mem")])
4878
4879 ;
4880 ; iorqi3 instruction pattern(s).
4881 ;
4882
4883 (define_insn "*iorqi3_oi"
4884 [(set (match_operand:QI 0 "register_operand" "=d,d")
4885 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4886 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4887 (clobber (reg:CC 33))]
4888 "TARGET_64BIT"
4889 "@
4890 or\\t%0,%2
4891 oill\\t%0,%b2"
4892 [(set_attr "op_type" "RR,RI")
4893 (set_attr "atype" "reg")])
4894
4895 (define_insn "iorqi3"
4896 [(set (match_operand:QI 0 "register_operand" "=d")
4897 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4898 (match_operand:QI 2 "nonmemory_operand" "d")))
4899 (clobber (reg:CC 33))]
4900 ""
4901 "or\\t%0,%2"
4902 [(set_attr "op_type" "RR")
4903 (set_attr "atype" "reg")])
4904
4905 (define_insn "*iorqi3_ss"
4906 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4907 (ior:QI (match_dup 0)
4908 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4909 (clobber (reg:CC 33))]
4910 ""
4911 "@
4912 oi\\t%0,%b1
4913 oc\\t%O0(1,%R0),%1"
4914 [(set_attr "op_type" "SI,SS")
4915 (set_attr "atype" "reg,mem")])
4916
4917 (define_insn "*iorqi3_ss_inv"
4918 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4919 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4920 (match_dup 0)))
4921 (clobber (reg:CC 33))]
4922 ""
4923 "@
4924 oi\\t%0,%b1
4925 oc\\t%O0(1,%R0),%1"
4926 [(set_attr "op_type" "SI,SS")
4927 (set_attr "atype" "reg,mem")])
4928
4929
4930 ;;
4931 ;;- Xor instructions.
4932 ;;
4933
4934 ;
4935 ; xordi3 instruction pattern(s).
4936 ;
4937
4938 (define_insn "*xordi3_cc"
4939 [(set (reg 33)
4940 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4941 (match_operand:DI 2 "general_operand" "d,m"))
4942 (const_int 0)))
4943 (set (match_operand:DI 0 "register_operand" "=d,d")
4944 (xor:DI (match_dup 1) (match_dup 2)))]
4945 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4946 "@
4947 xgr\\t%0,%2
4948 xg\\t%0,%2"
4949 [(set_attr "op_type" "RRE,RXE")
4950 (set_attr "atype" "reg,mem")])
4951
4952 (define_insn "*xordi3_cconly"
4953 [(set (reg 33)
4954 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4955 (match_operand:DI 2 "general_operand" "d,m"))
4956 (const_int 0)))
4957 (clobber (match_scratch:DI 0 "=d,d"))]
4958 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4959 "@
4960 xgr\\t%0,%2
4961 xr\\t%0,%2"
4962 [(set_attr "op_type" "RRE,RXE")
4963 (set_attr "atype" "reg,mem")])
4964
4965 (define_insn "xordi3"
4966 [(set (match_operand:DI 0 "register_operand" "=d,d")
4967 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4968 (match_operand:DI 2 "general_operand" "d,m")))
4969 (clobber (reg:CC 33))]
4970 "TARGET_64BIT"
4971 "@
4972 xgr\\t%0,%2
4973 xg\\t%0,%2"
4974 [(set_attr "op_type" "RRE,RXE")
4975 (set_attr "atype" "reg,mem")])
4976
4977 (define_insn "*xordi3_ss"
4978 [(set (match_operand:DI 0 "s_operand" "=Q")
4979 (xor:DI (match_dup 0)
4980 (match_operand:DI 1 "s_imm_operand" "Q")))
4981 (clobber (reg:CC 33))]
4982 ""
4983 "xc\\t%O0(8,%R0),%1"
4984 [(set_attr "op_type" "SS")
4985 (set_attr "atype" "mem")])
4986
4987 (define_insn "*xordi3_ss_inv"
4988 [(set (match_operand:DI 0 "s_operand" "=Q")
4989 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4990 (match_dup 0)))
4991 (clobber (reg:CC 33))]
4992 ""
4993 "xc\\t%O0(8,%R0),%1"
4994 [(set_attr "op_type" "SS")
4995 (set_attr "atype" "mem")])
4996
4997 ;
4998 ; xorsi3 instruction pattern(s).
4999 ;
5000
5001 (define_insn "*xorsi3_cc"
5002 [(set (reg 33)
5003 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5004 (match_operand:SI 2 "general_operand" "d,m"))
5005 (const_int 0)))
5006 (set (match_operand:SI 0 "register_operand" "=d,d")
5007 (xor:SI (match_dup 1) (match_dup 2)))]
5008 "s390_match_ccmode(insn, CCTmode)"
5009 "@
5010 xr\\t%0,%2
5011 x\\t%0,%2"
5012 [(set_attr "op_type" "RR,RX")
5013 (set_attr "atype" "reg,mem")])
5014
5015 (define_insn "*xorsi3_cconly"
5016 [(set (reg 33)
5017 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5018 (match_operand:SI 2 "general_operand" "d,m"))
5019 (const_int 0)))
5020 (clobber (match_scratch:SI 0 "=d,d"))]
5021 "s390_match_ccmode(insn, CCTmode)"
5022 "@
5023 xr\\t%0,%2
5024 x\\t%0,%2"
5025 [(set_attr "op_type" "RR,RX")
5026 (set_attr "atype" "reg,mem")])
5027
5028 (define_insn "xorsi3"
5029 [(set (match_operand:SI 0 "register_operand" "=d,d")
5030 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5031 (match_operand:SI 2 "general_operand" "d,m")))
5032 (clobber (reg:CC 33))]
5033 ""
5034 "@
5035 xr\\t%0,%2
5036 x\\t%0,%2"
5037 [(set_attr "op_type" "RR,RX")
5038 (set_attr "atype" "reg,mem")])
5039
5040 (define_insn "*xorsi3_ss"
5041 [(set (match_operand:SI 0 "s_operand" "=Q")
5042 (xor:SI (match_dup 0)
5043 (match_operand:SI 1 "s_imm_operand" "Q")))
5044 (clobber (reg:CC 33))]
5045 ""
5046 "xc\\t%O0(4,%R0),%1"
5047 [(set_attr "op_type" "SS")
5048 (set_attr "atype" "mem")])
5049
5050 (define_insn "*xorsi3_ss_inv"
5051 [(set (match_operand:SI 0 "s_operand" "=Q")
5052 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
5053 (match_dup 0)))
5054 (clobber (reg:CC 33))]
5055 ""
5056 "xc\\t%O0(4,%R0),%1"
5057 [(set_attr "op_type" "SS")
5058 (set_attr "atype" "mem")])
5059
5060 ;
5061 ; xorhi3 instruction pattern(s).
5062 ;
5063
5064 (define_insn "xorhi3"
5065 [(set (match_operand:HI 0 "register_operand" "=d")
5066 (xor:HI (match_operand:HI 1 "register_operand" "%0")
5067 (match_operand:HI 2 "nonmemory_operand" "d")))
5068 (clobber (reg:CC 33))]
5069 ""
5070 "xr\\t%0,%2"
5071 [(set_attr "op_type" "RR")
5072 (set_attr "atype" "reg")])
5073
5074 (define_insn "*xorhi3_ss"
5075 [(set (match_operand:HI 0 "s_operand" "=Q")
5076 (xor:HI (match_dup 0)
5077 (match_operand:HI 1 "s_imm_operand" "Q")))
5078 (clobber (reg:CC 33))]
5079 ""
5080 "xc\\t%O0(2,%R0),%1"
5081 [(set_attr "op_type" "SS")
5082 (set_attr "atype" "mem")])
5083
5084 (define_insn "*xorhi3_ss_inv"
5085 [(set (match_operand:HI 0 "s_operand" "=Q")
5086 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
5087 (match_dup 0)))
5088 (clobber (reg:CC 33))]
5089 ""
5090 "xc\\t%O0(2,%R0),%1"
5091 [(set_attr "op_type" "SS")
5092 (set_attr "atype" "mem")])
5093
5094 ;
5095 ; xorqi3 instruction pattern(s).
5096 ;
5097
5098 (define_insn "xorqi3"
5099 [(set (match_operand:QI 0 "register_operand" "=d")
5100 (xor:QI (match_operand:QI 1 "register_operand" "%0")
5101 (match_operand:QI 2 "nonmemory_operand" "d")))
5102 (clobber (reg:CC 33))]
5103 ""
5104 "xr\\t%0,%2"
5105 [(set_attr "op_type" "RR")
5106 (set_attr "atype" "reg")])
5107
5108 (define_insn "*xorqi3_ss"
5109 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5110 (xor:QI (match_dup 0)
5111 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5112 (clobber (reg:CC 33))]
5113 ""
5114 "@
5115 xi\\t%0,%b1
5116 xc\\t%O0(1,%R0),%1"
5117 [(set_attr "op_type" "SI,SS")
5118 (set_attr "atype" "mem")])
5119
5120 (define_insn "*xorqi3_ss_inv"
5121 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5122 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5123 (match_dup 0)))
5124 (clobber (reg:CC 33))]
5125 ""
5126 "@
5127 xi\\t%0,%b1
5128 xc\\t%O0(1,%R0),%1"
5129 [(set_attr "op_type" "SI,SS")
5130 (set_attr "atype" "mem")])
5131
5132
5133 ;;
5134 ;;- Negate instructions.
5135 ;;
5136
5137 ;
5138 ; negdi2 instruction pattern(s).
5139 ;
5140
5141 (define_expand "negdi2"
5142 [(parallel
5143 [(set (match_operand:DI 0 "register_operand" "=d")
5144 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5145 (clobber (reg:CC 33))])]
5146 ""
5147 "")
5148
5149 (define_insn "*negdi2_64"
5150 [(set (match_operand:DI 0 "register_operand" "=d")
5151 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5152 (clobber (reg:CC 33))]
5153 "TARGET_64BIT"
5154 "lcgr\\t%0,%1"
5155 [(set_attr "op_type" "RR")])
5156
5157 (define_insn "*negdi2_31"
5158 [(set (match_operand:DI 0 "register_operand" "=d")
5159 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5160 (clobber (reg:CC 33))]
5161 "!TARGET_64BIT"
5162 "*
5163 {
5164 rtx xop[1];
5165 xop[0] = gen_label_rtx ();
5166 output_asm_insn (\"lcr\\t%0,%1\", operands);
5167 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5168 output_asm_insn (\"je\\t%l0\", xop);
5169 output_asm_insn (\"bctr\\t%0,0\", operands);
5170 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5171 CODE_LABEL_NUMBER (xop[0]));
5172 return \"\";
5173 }"
5174 [(set_attr "op_type" "NN")
5175 (set_attr "type" "other")
5176 (set_attr "length" "10")])
5177
5178 ;
5179 ; negsi2 instruction pattern(s).
5180 ;
5181
5182 (define_insn "negsi2"
5183 [(set (match_operand:SI 0 "register_operand" "=d")
5184 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5185 (clobber (reg:CC 33))]
5186 ""
5187 "lcr\\t%0,%1"
5188 [(set_attr "op_type" "RR")])
5189
5190 ;
5191 ; negdf2 instruction pattern(s).
5192 ;
5193
5194 (define_expand "negdf2"
5195 [(parallel
5196 [(set (match_operand:DF 0 "register_operand" "=f")
5197 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5198 (clobber (reg:CC 33))])]
5199 "TARGET_HARD_FLOAT"
5200 "")
5201
5202 (define_insn "*negdf2"
5203 [(set (match_operand:DF 0 "register_operand" "=f")
5204 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5205 (clobber (reg:CC 33))]
5206 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5207 "lcdbr\\t%0,%1"
5208 [(set_attr "op_type" "RRE")])
5209
5210 (define_insn "*negdf2_ibm"
5211 [(set (match_operand:DF 0 "register_operand" "=f")
5212 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5213 (clobber (reg:CC 33))]
5214 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5215 "lcdr\\t%0,%1"
5216 [(set_attr "op_type" "RR")])
5217
5218 ;
5219 ; negsf2 instruction pattern(s).
5220 ;
5221
5222 (define_expand "negsf2"
5223 [(parallel
5224 [(set (match_operand:SF 0 "register_operand" "=f")
5225 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5226 (clobber (reg:CC 33))])]
5227 "TARGET_HARD_FLOAT"
5228 "")
5229
5230 (define_insn "*negsf2"
5231 [(set (match_operand:SF 0 "register_operand" "=f")
5232 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5233 (clobber (reg:CC 33))]
5234 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5235 "lcebr\\t%0,%1"
5236 [(set_attr "op_type" "RRE")])
5237
5238 (define_insn "*negsf2"
5239 [(set (match_operand:SF 0 "register_operand" "=f")
5240 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5241 (clobber (reg:CC 33))]
5242 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5243 "lcer\\t%0,%1"
5244 [(set_attr "op_type" "RR")])
5245
5246
5247 ;;
5248 ;;- Absolute value instructions.
5249 ;;
5250
5251 ;
5252 ; absdi2 instruction pattern(s).
5253 ;
5254
5255 (define_insn "absdi2"
5256 [(set (match_operand:DI 0 "register_operand" "=d")
5257 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5258 (clobber (reg:CC 33))]
5259 "TARGET_64BIT"
5260 "lpgr\\t%0,%1"
5261 [(set_attr "op_type" "RRE")])
5262
5263 ;
5264 ; abssi2 instruction pattern(s).
5265 ;
5266
5267 (define_insn "abssi2"
5268 [(set (match_operand:SI 0 "register_operand" "=d")
5269 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5270 (clobber (reg:CC 33))]
5271 ""
5272 "lpr\\t%0,%1"
5273 [(set_attr "op_type" "RR")])
5274
5275 ;
5276 ; absdf2 instruction pattern(s).
5277 ;
5278
5279 (define_expand "absdf2"
5280 [(parallel
5281 [(set (match_operand:DF 0 "register_operand" "=f")
5282 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5283 (clobber (reg:CC 33))])]
5284 "TARGET_HARD_FLOAT"
5285 "")
5286
5287 (define_insn "*absdf2"
5288 [(set (match_operand:DF 0 "register_operand" "=f")
5289 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5290 (clobber (reg:CC 33))]
5291 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5292 "lpdbr\\t%0,%1"
5293 [(set_attr "op_type" "RRE")])
5294
5295 (define_insn "*absdf2_ibm"
5296 [(set (match_operand:DF 0 "register_operand" "=f")
5297 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5298 (clobber (reg:CC 33))]
5299 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5300 "lpdr\\t%0,%1"
5301 [(set_attr "op_type" "RR")])
5302
5303 ;
5304 ; abssf2 instruction pattern(s).
5305 ;
5306
5307 (define_expand "abssf2"
5308 [(parallel
5309 [(set (match_operand:SF 0 "register_operand" "=f")
5310 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5311 (clobber (reg:CC 33))])]
5312 "TARGET_HARD_FLOAT"
5313 "")
5314
5315 (define_insn "*abssf2"
5316 [(set (match_operand:SF 0 "register_operand" "=f")
5317 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5318 (clobber (reg:CC 33))]
5319 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5320 "lpebr\\t%0,%1"
5321 [(set_attr "op_type" "RRE")])
5322
5323 (define_insn "*abssf2_ibm"
5324 [(set (match_operand:SF 0 "register_operand" "=f")
5325 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5326 (clobber (reg:CC 33))]
5327 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5328 "lper\\t%0,%1"
5329 [(set_attr "op_type" "RR")])
5330
5331 ;;
5332 ;;- Square root instructions.
5333 ;;
5334
5335 ;
5336 ; sqrtdf2 instruction pattern(s).
5337 ;
5338
5339 (define_insn "sqrtdf2"
5340 [(set (match_operand:DF 0 "register_operand" "=f,f")
5341 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5342 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5343 "@
5344 sqdbr\\t%0,%1
5345 sqdb\\t%0,%1"
5346 [(set_attr "op_type" "RRE,RSE")])
5347
5348 ;
5349 ; sqrtsf2 instruction pattern(s).
5350 ;
5351
5352 (define_insn "sqrtsf2"
5353 [(set (match_operand:SF 0 "register_operand" "=f,f")
5354 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5355 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5356 "@
5357 sqebr\\t%0,%1
5358 sqeb\\t%0,%1"
5359 [(set_attr "op_type" "RRE,RSE")])
5360
5361 ;;
5362 ;;- One complement instructions.
5363 ;;
5364
5365 ;
5366 ; one_cmpldi2 instruction pattern(s).
5367 ;
5368
5369 (define_expand "one_cmpldi2"
5370 [(parallel
5371 [(set (match_operand:DI 0 "register_operand" "")
5372 (xor:DI (match_operand:DI 1 "register_operand" "")
5373 (const_int -1)))
5374 (clobber (reg:CC 33))])]
5375 "TARGET_64BIT"
5376 "")
5377
5378 ;
5379 ; one_cmplsi2 instruction pattern(s).
5380 ;
5381
5382 (define_expand "one_cmplsi2"
5383 [(parallel
5384 [(set (match_operand:SI 0 "register_operand" "")
5385 (xor:SI (match_operand:SI 1 "register_operand" "")
5386 (const_int -1)))
5387 (clobber (reg:CC 33))])]
5388 ""
5389 "")
5390
5391 ;
5392 ; one_cmplhi2 instruction pattern(s).
5393 ;
5394
5395 (define_expand "one_cmplhi2"
5396 [(parallel
5397 [(set (match_operand:HI 0 "register_operand" "")
5398 (xor:HI (match_operand:HI 1 "register_operand" "")
5399 (const_int -1)))
5400 (clobber (reg:CC 33))])]
5401 ""
5402 "")
5403
5404 ;
5405 ; one_cmplqi2 instruction pattern(s).
5406 ;
5407
5408 (define_expand "one_cmplqi2"
5409 [(parallel
5410 [(set (match_operand:QI 0 "register_operand" "")
5411 (xor:QI (match_operand:QI 1 "register_operand" "")
5412 (const_int -1)))
5413 (clobber (reg:CC 33))])]
5414 ""
5415 "")
5416
5417
5418 ;;
5419 ;;- Rotate instructions.
5420 ;;
5421
5422 ;
5423 ; rotldi3 instruction pattern(s).
5424 ;
5425
5426 (define_insn "rotldi3"
5427 [(set (match_operand:DI 0 "register_operand" "=d,d")
5428 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5429 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5430 "TARGET_64BIT"
5431 "@
5432 rllg\\t%0,%1,%c2
5433 rllg\\t%0,%1,0(%2)"
5434 [(set_attr "op_type" "RSE")])
5435
5436 ;
5437 ; rotlsi3 instruction pattern(s).
5438 ;
5439
5440 (define_insn "rotlsi3"
5441 [(set (match_operand:SI 0 "register_operand" "=d,d")
5442 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5443 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5444 "TARGET_64BIT"
5445 "@
5446 rll\\t%0,%1,%c2
5447 rll\\t%0,%1,0(%2)"
5448 [(set_attr "op_type" "RSE")])
5449
5450
5451 ;;
5452 ;;- Arithmetic shift instructions.
5453 ;;
5454
5455 ;
5456 ; ashldi3 instruction pattern(s).
5457 ;
5458
5459 (define_expand "ashldi3"
5460 [(set (match_operand:DI 0 "register_operand" "")
5461 (ashift:DI (match_operand:DI 1 "register_operand" "")
5462 (match_operand:SI 2 "nonmemory_operand" "")))]
5463 ""
5464 "")
5465
5466 (define_insn "*ashldi3_31"
5467 [(set (match_operand:DI 0 "register_operand" "=d,d")
5468 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5469 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5470 "!TARGET_64BIT"
5471 "@
5472 sldl\\t%0,%c2
5473 sldl\\t%0,0(%2)"
5474 [(set_attr "op_type" "RS")])
5475
5476 (define_insn "*ashldi3_64"
5477 [(set (match_operand:DI 0 "register_operand" "=d,d")
5478 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5479 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5480 "TARGET_64BIT"
5481 "@
5482 sllg\\t%0,%1,%2
5483 sllg\\t%0,%1,0(%2)"
5484 [(set_attr "op_type" "RSE")])
5485
5486 ;
5487 ; ashrdi3 instruction pattern(s).
5488 ;
5489
5490 (define_expand "ashrdi3"
5491 [(parallel
5492 [(set (match_operand:DI 0 "register_operand" "")
5493 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5494 (match_operand:SI 2 "nonmemory_operand" "")))
5495 (clobber (reg:CC 33))])]
5496 ""
5497 "")
5498
5499 (define_insn "*ashrdi3_cc_31"
5500 [(set (reg 33)
5501 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5502 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5503 (const_int 0)))
5504 (set (match_operand:DI 0 "register_operand" "=d,d")
5505 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5506 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5507 "@
5508 srda\\t%0,%c2
5509 srda\\t%0,0(%2)"
5510 [(set_attr "op_type" "RS")])
5511
5512 (define_insn "*ashrdi3_cconly_31"
5513 [(set (reg 33)
5514 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5515 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5516 (const_int 0)))
5517 (clobber (match_scratch:DI 0 "=d,d"))]
5518 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5519 "@
5520 srda\\t%0,%c2
5521 srda\\t%0,0(%2)"
5522 [(set_attr "op_type" "RS")])
5523
5524 (define_insn "*ashrdi3_31"
5525 [(set (match_operand:DI 0 "register_operand" "=d,d")
5526 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5527 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5528 (clobber (reg:CC 33))]
5529 "!TARGET_64BIT"
5530 "@
5531 srda\\t%0,%c2
5532 srda\\t%0,0(%2)"
5533 [(set_attr "op_type" "RS")])
5534
5535 (define_insn "*ashrdi3_cc_64"
5536 [(set (reg 33)
5537 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5538 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5539 (const_int 0)))
5540 (set (match_operand:DI 0 "register_operand" "=d,d")
5541 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5542 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5543 "@
5544 srag\\t%0,%1,%c2
5545 srag\\t%0,%1,0(%2)"
5546 [(set_attr "op_type" "RSE")])
5547
5548 (define_insn "*ashrdi3_cconly_64"
5549 [(set (reg 33)
5550 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5551 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5552 (const_int 0)))
5553 (clobber (match_scratch:DI 0 "=d,d"))]
5554 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5555 "@
5556 srag\\t%0,%1,%c2
5557 srag\\t%0,%1,0(%2)"
5558 [(set_attr "op_type" "RSE")])
5559
5560 (define_insn "*ashrdi3_64"
5561 [(set (match_operand:DI 0 "register_operand" "=d,d")
5562 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5563 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5564 (clobber (reg:CC 33))]
5565 "TARGET_64BIT"
5566 "@
5567 srag\\t%0,%1,%c2
5568 srag\\t%0,%1,0(%2)"
5569 [(set_attr "op_type" "RSE")])
5570
5571 ;
5572 ; ashlsi3 instruction pattern(s).
5573 ;
5574
5575 (define_insn "ashlsi3"
5576 [(set (match_operand:SI 0 "register_operand" "=d,d")
5577 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5578 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5579 ""
5580 "@
5581 sll\\t%0,%c2
5582 sll\\t%0,0(%2)"
5583 [(set_attr "op_type" "RS")])
5584
5585 ;
5586 ; ashrsi3 instruction pattern(s).
5587 ;
5588
5589 (define_insn "*ashrsi3_cc"
5590 [(set (reg 33)
5591 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5592 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5593 (const_int 0)))
5594 (set (match_operand:SI 0 "register_operand" "=d,d")
5595 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5596 "s390_match_ccmode(insn, CCSmode)"
5597 "@
5598 sra\\t%0,%c2
5599 sra\\t%0,0(%2)"
5600 [(set_attr "op_type" "RS")])
5601
5602 (define_insn "*ashrsi3_cconly"
5603 [(set (reg 33)
5604 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5605 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5606 (const_int 0)))
5607 (clobber (match_scratch:SI 0 "=d,d"))]
5608 "s390_match_ccmode(insn, CCSmode)"
5609 "@
5610 sra\\t%0,%c2
5611 sra\\t%0,0(%2)"
5612 [(set_attr "op_type" "RS")])
5613
5614 (define_insn "ashrsi3"
5615 [(set (match_operand:SI 0 "register_operand" "=d,d")
5616 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5617 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5618 (clobber (reg:CC 33))]
5619 ""
5620 "@
5621 sra\\t%0,%c2
5622 sra\\t%0,0(%2)"
5623 [(set_attr "op_type" "RS")])
5624
5625
5626 ;;
5627 ;;- logical shift instructions.
5628 ;;
5629
5630 ;
5631 ; lshrdi3 instruction pattern(s).
5632 ;
5633
5634 (define_expand "lshrdi3"
5635 [(set (match_operand:DI 0 "register_operand" "")
5636 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5637 (match_operand:SI 2 "nonmemory_operand" "")))]
5638 ""
5639 "")
5640
5641 (define_insn "*lshrdi3_31"
5642 [(set (match_operand:DI 0 "register_operand" "=d,d")
5643 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5644 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5645 "!TARGET_64BIT"
5646 "@
5647 srdl\\t%0,%c2
5648 srdl\\t%0,0(%2)"
5649 [(set_attr "op_type" "RS,RS")])
5650
5651 (define_insn "*lshrdi3_64"
5652 [(set (match_operand:DI 0 "register_operand" "=d,d")
5653 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5654 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5655 "TARGET_64BIT"
5656 "@
5657 srlg\\t%0,%1,%c2
5658 srlg\\t%0,%1,0(%2)"
5659 [(set_attr "op_type" "RS,RS")])
5660
5661 ;
5662 ; lshrsi3 instruction pattern(s).
5663 ;
5664
5665 (define_insn "lshrsi3"
5666 [(set (match_operand:SI 0 "register_operand" "=d,d")
5667 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5668 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5669 ""
5670 "@
5671 srl\\t%0,%c2
5672 srl\\t%0,0(%2)"
5673 [(set_attr "op_type" "RS")])
5674
5675
5676 ;;
5677 ;; Branch instruction patterns.
5678 ;;
5679
5680 (define_expand "beq"
5681 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5682 (set (pc)
5683 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5684 (label_ref (match_operand 0 "" ""))
5685 (pc)))]
5686 ""
5687 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5688
5689 (define_expand "bne"
5690 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5691 (set (pc)
5692 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5693 (label_ref (match_operand 0 "" ""))
5694 (pc)))]
5695 ""
5696 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5697
5698 (define_expand "bgt"
5699 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5700 (set (pc)
5701 (if_then_else (gt (reg:CCS 33) (const_int 0))
5702 (label_ref (match_operand 0 "" ""))
5703 (pc)))]
5704 ""
5705 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5706
5707 (define_expand "bgtu"
5708 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5709 (set (pc)
5710 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5711 (label_ref (match_operand 0 "" ""))
5712 (pc)))]
5713 ""
5714 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5715
5716 (define_expand "blt"
5717 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5718 (set (pc)
5719 (if_then_else (lt (reg:CCS 33) (const_int 0))
5720 (label_ref (match_operand 0 "" ""))
5721 (pc)))]
5722 ""
5723 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5724
5725 (define_expand "bltu"
5726 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5727 (set (pc)
5728 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5729 (label_ref (match_operand 0 "" ""))
5730 (pc)))]
5731 ""
5732 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5733
5734 (define_expand "bge"
5735 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5736 (set (pc)
5737 (if_then_else (ge (reg:CCS 33) (const_int 0))
5738 (label_ref (match_operand 0 "" ""))
5739 (pc)))]
5740 ""
5741 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5742
5743 (define_expand "bgeu"
5744 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5745 (set (pc)
5746 (if_then_else (geu (reg:CCU 33) (const_int 0))
5747 (label_ref (match_operand 0 "" ""))
5748 (pc)))]
5749 ""
5750 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5751
5752 (define_expand "ble"
5753 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5754 (set (pc)
5755 (if_then_else (le (reg:CCS 33) (const_int 0))
5756 (label_ref (match_operand 0 "" ""))
5757 (pc)))]
5758 ""
5759 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5760
5761 (define_expand "bleu"
5762 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5763 (set (pc)
5764 (if_then_else (leu (reg:CCU 33) (const_int 0))
5765 (label_ref (match_operand 0 "" ""))
5766 (pc)))]
5767 ""
5768 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5769
5770 (define_expand "bunordered"
5771 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5772 (set (pc)
5773 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5774 (label_ref (match_operand 0 "" ""))
5775 (pc)))]
5776 ""
5777 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5778
5779 (define_expand "bordered"
5780 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5781 (set (pc)
5782 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5783 (label_ref (match_operand 0 "" ""))
5784 (pc)))]
5785 ""
5786 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5787
5788 (define_expand "buneq"
5789 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5790 (set (pc)
5791 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5792 (label_ref (match_operand 0 "" ""))
5793 (pc)))]
5794 ""
5795 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5796
5797 (define_expand "bungt"
5798 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5799 (set (pc)
5800 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5801 (label_ref (match_operand 0 "" ""))
5802 (pc)))]
5803 ""
5804 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5805
5806 (define_expand "bunlt"
5807 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5808 (set (pc)
5809 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5810 (label_ref (match_operand 0 "" ""))
5811 (pc)))]
5812 ""
5813 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5814
5815 (define_expand "bunge"
5816 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5817 (set (pc)
5818 (if_then_else (unge (reg:CCS 33) (const_int 0))
5819 (label_ref (match_operand 0 "" ""))
5820 (pc)))]
5821 ""
5822 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5823
5824 (define_expand "bunle"
5825 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5826 (set (pc)
5827 (if_then_else (unle (reg:CCS 33) (const_int 0))
5828 (label_ref (match_operand 0 "" ""))
5829 (pc)))]
5830 ""
5831 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5832
5833 (define_expand "bltgt"
5834 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5835 (set (pc)
5836 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5837 (label_ref (match_operand 0 "" ""))
5838 (pc)))]
5839 ""
5840 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5841
5842
5843 ;;
5844 ;;- Conditional jump instructions.
5845 ;;
5846
5847 (define_insn "cjump"
5848 [(set (pc)
5849 (if_then_else
5850 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5851 (label_ref (match_operand 0 "" ""))
5852 (pc)))]
5853 ""
5854 "*
5855 {
5856 if (get_attr_length (insn) == 4)
5857 return \"j%C1\\t%l0\";
5858 else if (TARGET_64BIT)
5859 return \"jg%C1\\t%l0\";
5860 else
5861 abort ();
5862 }"
5863 [(set_attr "op_type" "RI")
5864 (set (attr "length")
5865 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5866 (const_int 4)
5867 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5868 (const_int 6)
5869 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5870 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5871 (const_int 12) (const_int 14))
5872 (eq (symbol_ref "flag_pic") (const_int 0))
5873 (const_int 6)] (const_int 8)))])
5874
5875 (define_insn "*cjump_long"
5876 [(set (pc)
5877 (if_then_else
5878 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5879 (match_operand 0 "address_operand" "p")
5880 (pc)))]
5881 ""
5882 "*
5883 {
5884 if (get_attr_op_type (insn) == OP_TYPE_RR)
5885 return \"b%C1r\\t%0\";
5886 else
5887 return \"b%C1\\t%a0\";
5888 }"
5889 [(set (attr "op_type")
5890 (if_then_else (match_operand 0 "register_operand" "")
5891 (const_string "RR") (const_string "RX")))
5892 (set_attr "atype" "mem")])
5893
5894
5895 ;;
5896 ;;- Negated conditional jump instructions.
5897 ;;
5898
5899 (define_insn "icjump"
5900 [(set (pc)
5901 (if_then_else
5902 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5903 (pc)
5904 (label_ref (match_operand 0 "" ""))))]
5905 ""
5906 "*
5907 {
5908 if (get_attr_length (insn) == 4)
5909 return \"j%D1\\t%l0\";
5910 else if (TARGET_64BIT)
5911 return \"jg%D1\\t%l0\";
5912 else
5913 abort ();
5914 }"
5915 [(set_attr "op_type" "RI")
5916 (set (attr "length")
5917 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5918 (const_int 4)
5919 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5920 (const_int 6)
5921 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5922 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5923 (const_int 12) (const_int 14))
5924 (eq (symbol_ref "flag_pic") (const_int 0))
5925 (const_int 6)] (const_int 8)))])
5926
5927 (define_insn "*icjump_long"
5928 [(set (pc)
5929 (if_then_else
5930 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5931 (pc)
5932 (match_operand 0 "address_operand" "p")))]
5933 ""
5934 "*
5935 {
5936 if (get_attr_op_type (insn) == OP_TYPE_RR)
5937 return \"b%D1r\\t%0\";
5938 else
5939 return \"b%D1\\t%a0\";
5940 }"
5941 [(set (attr "op_type")
5942 (if_then_else (match_operand 0 "register_operand" "")
5943 (const_string "RR") (const_string "RX")))
5944 (set_attr "atype" "mem")])
5945
5946
5947 ;;
5948 ;;- Subtract one and jump if not zero.
5949 ;;
5950
5951 ;(define_expand "decrement_and_branch_on_count"
5952 ; [(use (match_operand 0 "register_operand" ""))
5953 ; (use (label_ref (match_operand 1 "" "")))]
5954 ; ""
5955 ; "
5956 ;{
5957 ;/* if (TARGET_64BIT)
5958 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5959 ; else */
5960 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5961 ; DONE;
5962 ;}")
5963 ;
5964 ;(define_insn "brctsi"
5965 ; [(set (pc)
5966 ; (if_then_else
5967 ; (ne (match_operand:SI 0 "register_operand" "+a")
5968 ; (const_int 1))
5969 ; (label_ref (match_operand 1 "" ""))
5970 ; (pc)))
5971 ; (set (match_dup 0)
5972 ; (plus:SI (match_dup 0) (const_int -1)))]
5973 ; ""
5974 ; "brct\\t%0,%l1"
5975 ; [(set_attr "op_type" "RI")
5976 ; (set_attr "type" "branch")]
5977 ;)
5978 ;
5979 ;(define_insn "ibrctsi"
5980 ; [(set (pc)
5981 ; (if_then_else
5982 ; (eq (match_operand:SI 0 "register_operand" "+a")
5983 ; (const_int 1))
5984 ; (pc)
5985 ; (label_ref (match_operand 1 "" ""))))
5986 ; (set (match_dup 0)
5987 ; (plus:SI (match_dup 0) (const_int -1)))]
5988 ; ""
5989 ; "brct\\t%0,%l1"
5990 ; [(set_attr "op_type" "RI")
5991 ; (set_attr "type" "branch")]
5992 ;)
5993
5994
5995 ;;
5996 ;;- Unconditional jump instructions.
5997 ;;
5998
5999 ;
6000 ; jump instruction pattern(s).
6001 ;
6002
6003 (define_insn "jump"
6004 [(set (pc) (label_ref (match_operand 0 "" "")))]
6005 ""
6006 "*
6007 {
6008 if (get_attr_length (insn) == 4)
6009 return \"j\\t%l0\";
6010 else if (TARGET_64BIT)
6011 return \"jg\\t%l0\";
6012 else
6013 abort ();
6014 }"
6015 [(set_attr "op_type" "RI")
6016 (set (attr "length")
6017 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6018 (const_int 4)
6019 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6020 (const_int 6)
6021 (eq (symbol_ref "flag_pic") (const_int 0))
6022 (const_int 6)] (const_int 8)))])
6023
6024 ;
6025 ; indirect-jump instruction pattern(s).
6026 ;
6027
6028 (define_insn "indirect_jump"
6029 [(set (pc) (match_operand 0 "address_operand" "p"))]
6030 ""
6031 "*
6032 {
6033 if (get_attr_op_type (insn) == OP_TYPE_RR)
6034 return \"br\\t%0\";
6035 else
6036 return \"b\\t%a0\";
6037 }"
6038 [(set (attr "op_type")
6039 (if_then_else (match_operand 0 "register_operand" "")
6040 (const_string "RR") (const_string "RX")))
6041 (set_attr "atype" "mem")])
6042
6043 ;
6044 ; casesi instruction pattern(s).
6045 ;
6046
6047 (define_insn "casesi_jump"
6048 [(set (pc) (match_operand 0 "address_operand" "p"))
6049 (use (label_ref (match_operand 1 "" "")))]
6050 ""
6051 "*
6052 {
6053 if (get_attr_op_type (insn) == OP_TYPE_RR)
6054 return \"br\\t%0\";
6055 else
6056 return \"b\\t%a0\";
6057 }"
6058 [(set (attr "op_type")
6059 (if_then_else (match_operand 0 "register_operand" "")
6060 (const_string "RR") (const_string "RX")))
6061 (set_attr "atype" "mem")])
6062
6063 (define_expand "casesi"
6064 [(match_operand:SI 0 "general_operand" "")
6065 (match_operand:SI 1 "general_operand" "")
6066 (match_operand:SI 2 "general_operand" "")
6067 (label_ref (match_operand 3 "" ""))
6068 (label_ref (match_operand 4 "" ""))]
6069 ""
6070 "
6071 {
6072 rtx index = gen_reg_rtx (SImode);
6073 rtx base = gen_reg_rtx (Pmode);
6074 rtx target = gen_reg_rtx (Pmode);
6075
6076 emit_move_insn (index, operands[0]);
6077 emit_insn (gen_subsi3 (index, index, operands[1]));
6078 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6079 operands[4]);
6080
6081 if (Pmode != SImode)
6082 index = convert_to_mode (Pmode, index, 1);
6083 if (GET_CODE (index) != REG)
6084 index = copy_to_mode_reg (Pmode, index);
6085
6086 if (TARGET_64BIT)
6087 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6088 else
6089 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6090
6091 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6092
6093 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6094 emit_move_insn (target, index);
6095
6096 if (flag_pic)
6097 target = gen_rtx_PLUS (Pmode, base, target);
6098 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6099
6100 DONE;
6101 }")
6102
6103
6104 ;;
6105 ;;- Jump to subroutine.
6106 ;;
6107 ;;
6108
6109 ;
6110 ; untyped call instruction pattern(s).
6111 ;
6112
6113 ;; Call subroutine returning any type.
6114 (define_expand "untyped_call"
6115 [(parallel [(call (match_operand 0 "" "")
6116 (const_int 0))
6117 (match_operand 1 "" "")
6118 (match_operand 2 "" "")])]
6119 ""
6120 "
6121 {
6122 int i;
6123
6124 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6125
6126 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6127 {
6128 rtx set = XVECEXP (operands[2], 0, i);
6129 emit_move_insn (SET_DEST (set), SET_SRC (set));
6130 }
6131
6132 /* The optimizer does not know that the call sets the function value
6133 registers we stored in the result block. We avoid problems by
6134 claiming that all hard registers are used and clobbered at this
6135 point. */
6136 emit_insn (gen_blockage ());
6137
6138 DONE;
6139 }")
6140
6141 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6142 ;; all of memory. This blocks insns from being moved across this point.
6143
6144 (define_insn "blockage"
6145 [(unspec_volatile [(const_int 0)] 0)]
6146 ""
6147 ""
6148 [(set_attr "type" "none")])
6149
6150
6151
6152 ;
6153 ; call instruction pattern(s).
6154 ;
6155
6156 (define_expand "call"
6157 [(call (match_operand 0 "" "")
6158 (match_operand 1 "" ""))
6159 (use (match_operand 2 "" ""))]
6160 ""
6161 "
6162 {
6163 int plt_call = 0;
6164 rtx insn;
6165
6166 /* Direct function calls need special treatment. */
6167 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6168 {
6169 rtx sym = XEXP (operands[0], 0);
6170
6171 /* When calling a global routine in PIC mode, we must
6172 replace the symbol itself with the PLT stub. */
6173 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6174 {
6175 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6176 sym = gen_rtx_CONST (Pmode, sym);
6177
6178 plt_call = 1;
6179 }
6180
6181 /* Unless we can use the bras(l) insn, force the
6182 routine address into a register. */
6183 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6184 {
6185 rtx target = gen_reg_rtx (Pmode);
6186 emit_move_insn (target, sym);
6187 sym = target;
6188 }
6189
6190 operands[0] = gen_rtx_MEM (QImode, sym);
6191 }
6192
6193 /* Emit insn. */
6194 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6195 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6196
6197 /* In 31-bit, we must load the GOT register even if the
6198 compiler doesn't know about it, because the PLT glue
6199 code uses it. In 64-bit, this is not necessary. */
6200 if (plt_call && !TARGET_64BIT)
6201 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6202
6203 DONE;
6204 }")
6205
6206 (define_expand "call_exp"
6207 [(parallel [(call (match_operand 0 "" "")
6208 (match_operand 1 "" ""))
6209 (clobber (match_operand 2 "" ""))])]
6210 ""
6211 "")
6212
6213 (define_insn "brasl"
6214 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6215 (match_operand:SI 1 "const_int_operand" "n"))
6216 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6217 "TARGET_64BIT"
6218 "brasl\\t%2,%0"
6219 [(set_attr "op_type" "RIL")
6220 (set_attr "type" "jsr")])
6221
6222 (define_insn "bras"
6223 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6224 (match_operand:SI 1 "const_int_operand" "n"))
6225 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6226 "TARGET_SMALL_EXEC"
6227 "bras\\t%2,%0"
6228 [(set_attr "op_type" "RI")
6229 (set_attr "type" "jsr")])
6230
6231 (define_insn "basr_64"
6232 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6233 (match_operand:SI 1 "const_int_operand" "n"))
6234 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6235 "TARGET_64BIT"
6236 "basr\\t%2,%0"
6237 [(set_attr "op_type" "RR")
6238 (set_attr "type" "jsr")
6239 (set_attr "atype" "mem")])
6240
6241 (define_insn "basr_31"
6242 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6243 (match_operand:SI 1 "const_int_operand" "n"))
6244 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6245 "!TARGET_64BIT"
6246 "basr\\t%2,%0"
6247 [(set_attr "op_type" "RR")
6248 (set_attr "type" "jsr")
6249 (set_attr "atype" "mem")])
6250
6251 (define_insn "bas_64"
6252 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6253 (match_operand:SI 1 "const_int_operand" "n"))
6254 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6255 "TARGET_64BIT"
6256 "bas\\t%2,%a0"
6257 [(set_attr "op_type" "RX")
6258 (set_attr "type" "jsr")
6259 (set_attr "atype" "mem")])
6260
6261 (define_insn "bas_31"
6262 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6263 (match_operand:SI 1 "const_int_operand" "n"))
6264 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6265 "!TARGET_64BIT"
6266 "bas\\t%2,%a0"
6267 [(set_attr "op_type" "RX")
6268 (set_attr "type" "jsr")
6269 (set_attr "atype" "mem")])
6270
6271
6272 ;
6273 ; call_value instruction pattern(s).
6274 ;
6275
6276 (define_expand "call_value"
6277 [(set (match_operand 0 "" "")
6278 (call (match_operand 1 "" "")
6279 (match_operand 2 "" "")))
6280 (use (match_operand 3 "" ""))]
6281 ""
6282 "
6283 {
6284 int plt_call = 0;
6285 rtx insn;
6286
6287 /* Direct function calls need special treatment. */
6288 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6289 {
6290 rtx sym = XEXP (operands[1], 0);
6291
6292 /* When calling a global routine in PIC mode, we must
6293 replace the symbol itself with the PLT stub. */
6294 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6295 {
6296 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6297 sym = gen_rtx_CONST (Pmode, sym);
6298
6299 plt_call = 1;
6300 }
6301
6302 /* Unless we can use the bras(l) insn, force the
6303 routine address into a register. */
6304 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6305 {
6306 rtx target = gen_reg_rtx (Pmode);
6307 emit_move_insn (target, sym);
6308 sym = target;
6309 }
6310
6311 operands[1] = gen_rtx_MEM (QImode, sym);
6312 }
6313
6314 /* Emit insn. */
6315 insn = emit_call_insn (
6316 gen_call_value_exp (operands[0], operands[1], operands[2],
6317 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6318
6319 /* In 31-bit, we must load the GOT register even if the
6320 compiler doesn't know about it, because the PLT glue
6321 code uses it. In 64-bit, this is not necessary. */
6322 if (plt_call && !TARGET_64BIT)
6323 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6324
6325 DONE;
6326 }")
6327
6328 (define_expand "call_value_exp"
6329 [(parallel [(set (match_operand 0 "" "")
6330 (call (match_operand 1 "" "")
6331 (match_operand 2 "" "")))
6332 (clobber (match_operand 3 "" ""))])]
6333 ""
6334 "")
6335
6336 (define_insn "brasl_r"
6337 [(set (match_operand 0 "register_operand" "=df")
6338 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6339 (match_operand:SI 2 "const_int_operand" "n")))
6340 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6341 "TARGET_64BIT"
6342 "brasl\\t%3,%1"
6343 [(set_attr "op_type" "RIL")
6344 (set_attr "type" "jsr")])
6345
6346 (define_insn "bras_r"
6347 [(set (match_operand 0 "register_operand" "=df")
6348 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6349 (match_operand:SI 2 "const_int_operand" "n")))
6350 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6351 "TARGET_SMALL_EXEC"
6352 "bras\\t%3,%1"
6353 [(set_attr "op_type" "RI")
6354 (set_attr "type" "jsr")])
6355
6356 (define_insn "basr_r_64"
6357 [(set (match_operand 0 "register_operand" "=df")
6358 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6359 (match_operand:SI 2 "const_int_operand" "n")))
6360 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6361 "TARGET_64BIT"
6362 "basr\\t%3,%1"
6363 [(set_attr "op_type" "RR")
6364 (set_attr "type" "jsr")])
6365
6366 (define_insn "basr_r_31"
6367 [(set (match_operand 0 "register_operand" "=df")
6368 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6369 (match_operand:SI 2 "const_int_operand" "n")))
6370 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6371 "!TARGET_64BIT"
6372 "basr\\t%3,%1"
6373 [(set_attr "op_type" "RR")
6374 (set_attr "type" "jsr")
6375 (set_attr "atype" "mem")])
6376
6377 (define_insn "bas_r_64"
6378 [(set (match_operand 0 "register_operand" "=df")
6379 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6380 (match_operand:SI 2 "const_int_operand" "n")))
6381 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6382 "TARGET_64BIT"
6383 "bas\\t%3,%a1"
6384 [(set_attr "op_type" "RX")
6385 (set_attr "type" "jsr")
6386 (set_attr "atype" "mem")])
6387
6388 (define_insn "bas_r_31"
6389 [(set (match_operand 0 "register_operand" "=df")
6390 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6391 (match_operand:SI 2 "const_int_operand" "n")))
6392 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6393 "!TARGET_64BIT"
6394 "bas\\t%3,%a1"
6395 [(set_attr "op_type" "RX")
6396 (set_attr "type" "jsr")
6397 (set_attr "atype" "mem")])
6398
6399
6400 ;;
6401 ;;- Miscellaneous instructions.
6402 ;;
6403
6404 ;
6405 ; allocate stack instruction pattern(s).
6406 ;
6407
6408 (define_expand "allocate_stack"
6409 [(set (reg 15)
6410 (plus (reg 15) (match_operand 1 "general_operand" "")))
6411 (set (match_operand 0 "general_operand" "")
6412 (reg 15))]
6413 ""
6414 "
6415 {
6416 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6417 rtx chain = gen_rtx (MEM, Pmode, stack);
6418 rtx temp = gen_reg_rtx (Pmode);
6419
6420 emit_move_insn (temp, chain);
6421
6422 if (TARGET_64BIT)
6423 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6424 else
6425 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6426
6427 emit_move_insn (chain, temp);
6428
6429 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6430 DONE;
6431 }")
6432
6433
6434 ;
6435 ; setjmp/longjmp instruction pattern(s).
6436 ;
6437
6438 (define_expand "builtin_setjmp_setup"
6439 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6440 ""
6441 "
6442 {
6443 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6444 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6445
6446 emit_move_insn (base, basereg);
6447 DONE;
6448 }")
6449
6450 (define_expand "builtin_setjmp_receiver"
6451 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6452 "flag_pic"
6453 "
6454 {
6455 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6456 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6457 SYMBOL_REF_FLAG (got) = 1;
6458
6459 emit_move_insn (gotreg, got);
6460 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6461 DONE;
6462 }")
6463
6464 (define_expand "builtin_longjmp"
6465 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6466 ""
6467 "
6468 {
6469 /* The elements of the buffer are, in order: */
6470 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6471 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6472 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6473 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6474 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6475 rtx jmp = gen_rtx_REG (Pmode, 14);
6476
6477 emit_move_insn (jmp, lab);
6478 emit_move_insn (basereg, base);
6479 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6480 emit_move_insn (hard_frame_pointer_rtx, fp);
6481
6482 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6483 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6484 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6485 emit_indirect_jump (jmp);
6486 DONE;
6487 }")
6488
6489
6490 ;; These patterns say how to save and restore the stack pointer. We need not
6491 ;; save the stack pointer at function level since we are careful to
6492 ;; preserve the backchain. At block level, we have to restore the backchain
6493 ;; when we restore the stack pointer.
6494 ;;
6495 ;; For nonlocal gotos, we must save both the stack pointer and its
6496 ;; backchain and restore both. Note that in the nonlocal case, the
6497 ;; save area is a memory location.
6498
6499 (define_expand "save_stack_function"
6500 [(match_operand 0 "general_operand" "")
6501 (match_operand 1 "general_operand" "")]
6502 ""
6503 "DONE;")
6504
6505 (define_expand "restore_stack_function"
6506 [(match_operand 0 "general_operand" "")
6507 (match_operand 1 "general_operand" "")]
6508 ""
6509 "DONE;")
6510
6511 (define_expand "restore_stack_block"
6512 [(use (match_operand 0 "register_operand" ""))
6513 (set (match_dup 2) (match_dup 3))
6514 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6515 (set (match_dup 3) (match_dup 2))]
6516 ""
6517 "
6518 {
6519 operands[2] = gen_reg_rtx (Pmode);
6520 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6521 }")
6522
6523 (define_expand "save_stack_nonlocal"
6524 [(match_operand 0 "memory_operand" "")
6525 (match_operand 1 "register_operand" "")]
6526 ""
6527 "
6528 {
6529 rtx temp = gen_reg_rtx (Pmode);
6530
6531 /* Copy the backchain to the first word, sp to the second. */
6532 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6533 emit_move_insn (operand_subword (operands[0], 0, 0,
6534 TARGET_64BIT ? TImode : DImode),
6535 temp);
6536 emit_move_insn (operand_subword (operands[0], 1, 0,
6537 TARGET_64BIT ? TImode : DImode),
6538 operands[1]);
6539 DONE;
6540 }")
6541
6542 (define_expand "restore_stack_nonlocal"
6543 [(match_operand 0 "register_operand" "")
6544 (match_operand 1 "memory_operand" "")]
6545 ""
6546 "
6547 {
6548 rtx temp = gen_reg_rtx (Pmode);
6549
6550 /* Restore the backchain from the first word, sp from the second. */
6551 emit_move_insn (temp,
6552 operand_subword (operands[1], 0, 0,
6553 TARGET_64BIT ? TImode : DImode));
6554 emit_move_insn (operands[0],
6555 operand_subword (operands[1], 1, 0,
6556 TARGET_64BIT ? TImode : DImode));
6557 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6558 DONE;
6559 }")
6560
6561
6562 ;
6563 ; nop instruction pattern(s).
6564 ;
6565
6566 (define_insn "nop"
6567 [(const_int 0)]
6568 ""
6569 "lr\\t0,0"
6570 [(set_attr "op_type" "RR")])
6571
6572
6573 ;
6574 ; Special literal pool access instruction pattern(s).
6575 ;
6576
6577 (define_insn "consttable_qi"
6578 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6579 ""
6580 "*
6581 {
6582 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6583 return \"\";
6584 }"
6585 [(set_attr "op_type" "NN")
6586 (set_attr "length" "1")])
6587
6588 (define_insn "consttable_hi"
6589 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6590 ""
6591 "*
6592 {
6593 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6594 return \"\";
6595 }"
6596 [(set_attr "op_type" "NN")
6597 (set_attr "length" "2")])
6598
6599 (define_insn "consttable_si"
6600 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6601 ""
6602 "*
6603 {
6604 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6605 return \".long\\t%0\";
6606
6607 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6608 return \"\";
6609 }"
6610 [(set_attr "op_type" "NN")
6611 (set_attr "length" "4")])
6612
6613 (define_insn "consttable_di"
6614 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6615 ""
6616 "*
6617 {
6618 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6619 return \"\";
6620 }"
6621 [(set_attr "op_type" "NN")
6622 (set_attr "length" "8")])
6623
6624 (define_insn "consttable_sf"
6625 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6626 ""
6627 "*
6628 {
6629 REAL_VALUE_TYPE r;
6630
6631 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6632 abort ();
6633
6634 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6635 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6636 return \"\";
6637 }"
6638 [(set_attr "op_type" "NN")
6639 (set_attr "length" "4")])
6640
6641 (define_insn "consttable_df"
6642 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6643 ""
6644 "*
6645 {
6646 REAL_VALUE_TYPE r;
6647
6648 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6649 abort ();
6650
6651 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6652 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6653 return \"\";
6654 }"
6655 [(set_attr "op_type" "NN")
6656 (set_attr "length" "8")])
6657
6658 (define_insn "pool_start_31"
6659 [(unspec_volatile [(const_int 0)] 206)]
6660 "!TARGET_64BIT"
6661 ".align\\t4"
6662 [(set_attr "op_type" "NN")
6663 (set_attr "length" "2")])
6664
6665 (define_insn "pool_end_31"
6666 [(unspec_volatile [(const_int 0)] 207)]
6667 "!TARGET_64BIT"
6668 ".align\\t2"
6669 [(set_attr "op_type" "NN")
6670 (set_attr "length" "2")])
6671
6672 (define_insn "pool_start_64"
6673 [(unspec_volatile [(const_int 0)] 206)]
6674 "TARGET_64BIT"
6675 ".section\\t.rodata\;.align\\t8"
6676 [(set_attr "op_type" "NN")
6677 (set_attr "length" "0")])
6678
6679 (define_insn "pool_end_64"
6680 [(unspec_volatile [(const_int 0)] 207)]
6681 "TARGET_64BIT"
6682 ".previous"
6683 [(set_attr "op_type" "NN")
6684 (set_attr "length" "0")])
6685
6686 (define_insn "reload_base"
6687 [(set (match_operand:SI 0 "register_operand" "=a")
6688 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6689 "!TARGET_64BIT"
6690 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6691 [(set_attr "op_type" "NN")
6692 (set_attr "type" "la")
6693 (set_attr "length" "6")])
6694
6695 (define_insn "reload_base2"
6696 [(set (match_operand:SI 0 "register_operand" "=a")
6697 (unspec:SI [(label_ref (match_operand 1 "" ""))] 211))]
6698 "!TARGET_64BIT"
6699 "la\\t%0,%1-.(%0)"
6700 [(set_attr "op_type" "NN")
6701 (set_attr "type" "la")
6702 (set_attr "length" "4")])
6703
6704
6705 ;;
6706 ;; Insns related to generating the function prologue and epilogue.
6707 ;;
6708
6709
6710 (define_expand "prologue"
6711 [(use (const_int 0))]
6712 ""
6713 "
6714 {
6715 s390_emit_prologue ();
6716 DONE;
6717 }")
6718
6719 (define_expand "epilogue"
6720 [(use (const_int 1))]
6721 ""
6722 "
6723 {
6724 s390_emit_epilogue ();
6725 DONE;
6726 }")
6727
6728
6729 (define_insn "*return_si"
6730 [(return)
6731 (use (match_operand:SI 0 "register_operand" "a"))]
6732 "!TARGET_64BIT"
6733 "br\\t%0"
6734 [(set_attr "op_type" "RR")
6735 (set_attr "type" "jsr")
6736 (set_attr "atype" "mem")])
6737
6738 (define_insn "*return_di"
6739 [(return)
6740 (use (match_operand:DI 0 "register_operand" "a"))]
6741 "TARGET_64BIT"
6742 "br\\t%0"
6743 [(set_attr "op_type" "RR")
6744 (set_attr "type" "jsr")
6745 (set_attr "atype" "mem")])
6746
6747
6748 (define_insn "lit"
6749 [(set (reg 13) (pc))
6750 (unspec_volatile [(const_int 0)] 200)]
6751 ""
6752 "*
6753 {
6754 s390_output_constant_pool (asm_out_file);
6755 return \"\";
6756 }"
6757 [(set_attr "op_type" "NN")
6758 (set_attr "type" "integer")])
6759
6760
6761 ;;
6762 ;; Peephole optimization patterns.
6763 ;;
6764
6765 (define_peephole
6766 [(set (match_operand:SI 0 "memory_operand" "m")
6767 (match_operand:SI 1 "register_operand" "d"))
6768 (set (match_dup 1)
6769 (match_dup 0))]
6770 ""
6771 "st\\t%1,%0")
6772
6773 (define_peephole
6774 [(set (match_operand:SI 0 "memory_operand" "m")
6775 (match_operand:SI 1 "register_operand" "d"))
6776 (set (match_dup 0)
6777 (match_dup 1))]
6778 ""
6779 "st\\t%1,%0")
6780
6781 (define_peephole
6782 [(set (match_operand:SI 0 "register_operand" "")
6783 (match_operand:SI 1 "register_operand" ""))
6784 (parallel
6785 [(set (match_dup 0)
6786 (plus:SI (match_dup 0)
6787 (match_operand:SI 2 "immediate_operand" "")))
6788 (clobber (reg:CC 33))])]
6789 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6790 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6791 REGNO (operands[0]) == BASE_REGISTER ||
6792 REGNO (operands[1]) == BASE_REGISTER) &&
6793 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6794 "la\\t%0,%c2(%1)")
6795
6796 ;
6797 ; peepholes for fast char instructions
6798 ;
6799
6800 ;(define_peephole
6801 ; [(set (match_operand:QI 0 "register_operand" "d")
6802 ; (match_operand:QI 1 "s_operand" "Q"))
6803 ; (set (match_operand:SI 2 "register_operand" "0")
6804 ; (zero_extend:SI (match_dup 0)))]
6805 ; "REGNO(operands[0]) == REGNO(operands[2])"
6806 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6807
6808 ;(define_peephole
6809 ; [(set (match_operand:QI 0 "register_operand" "d")
6810 ; (match_operand:QI 1 "s_operand" "Q"))
6811 ; (set (match_operand:SI 2 "register_operand" "0")
6812 ; (sign_extend:SI (match_dup 0)))]
6813 ; "REGNO(operands[0]) == REGNO(operands[2])"
6814 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6815
6816 (define_peephole
6817 [(set (match_operand:QI 0 "register_operand" "d")
6818 (match_operand:QI 1 "immediate_operand" "J"))
6819 (set (match_operand:SI 2 "register_operand" "0" )
6820 (sign_extend:SI (match_dup 0) ) )]
6821 "REGNO(operands[0]) == REGNO(operands[2])"
6822 "lhi\\t%0,%h1")
6823
6824 ;
6825 ; peepholes for fast short instructions
6826 ;
6827
6828 ;(define_peephole
6829 ; [(set (match_operand:HI 0 "register_operand" "d")
6830 ; (match_operand:HI 1 "s_operand" "Q"))
6831 ; (set (match_operand:SI 2 "register_operand" "0" )
6832 ; (zero_extend:SI (match_dup 0)))]
6833 ; "REGNO(operands[0]) == REGNO(operands[2])"
6834 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6835
6836 (define_peephole
6837 [(set (match_operand:HI 0 "register_operand" "d")
6838 (match_operand:HI 1 "memory_operand" "m"))
6839 (set (match_operand:SI 2 "register_operand" "0" )
6840 (sign_extend:SI (match_dup 0)))]
6841 "REGNO(operands[0]) == REGNO(operands[2])"
6842 "lh\\t%0,%1")
6843
6844 (define_peephole
6845 [(set (match_operand:HI 0 "register_operand" "d")
6846 (match_operand:HI 1 "immediate_operand" "K"))
6847 (set (match_operand:SI 2 "register_operand" "0" )
6848 (sign_extend:SI (match_dup 0) ) )]
6849 "REGNO(operands[0]) == REGNO(operands[2])"
6850 "lhi\\t%0,%h1")
6851
6852 ;
6853 ; peepholes for divide instructions
6854 ;
6855
6856 (define_peephole
6857 [(set (match_operand:DI 0 "register_operand" "d")
6858 (match_operand:DI 1 "memory_operand" "m"))
6859 (set (match_dup 0)
6860 (lshiftrt:DI (match_dup 0)
6861 (match_operand:SI 2 "immediate_operand" "J")))
6862 (set (match_dup 0)
6863 (div:SI (match_dup 0)
6864 (match_operand:SI 3 "nonimmediate_operand" "g")))
6865 (set (match_dup 1)
6866 (match_dup 0))]
6867 ""
6868 "*
6869 {
6870 output_asm_insn (\"l\\t%0,%1\", operands);
6871 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6872
6873 if (REG_P (operands[3]))
6874 output_asm_insn (\"dr\\t%0,%3\", operands);
6875 else
6876 output_asm_insn (\"d\\t%0,%3\", operands);
6877
6878 return \"st\\t%N0,%N1\";
6879 }")
6880
6881 (define_peephole
6882 [(set (match_operand:DI 0 "register_operand" "d")
6883 (match_operand:DI 1 "memory_operand" "m"))
6884 (set (match_dup 0)
6885 (lshiftrt:DI (match_dup 0)
6886 (match_operand:SI 2 "immediate_operand" "J")))
6887 (set (match_dup 0)
6888 (mod:SI (match_dup 0)
6889 (match_operand:SI 3 "nonimmediate_operand" "g")))
6890 (set (match_dup 1)
6891 (match_dup 0))]
6892 ""
6893 "*
6894 {
6895 output_asm_insn (\"l\\t%0,%1\", operands);
6896 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6897
6898 if (REG_P (operands[3]))
6899 output_asm_insn (\"dr\\t%0,%3\", operands);
6900 else
6901 output_asm_insn (\"d\\t%0,%3\", operands);
6902
6903 return \"st\\t%0,%1\";
6904 }")
6905