projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
s390.c: (legitimize_la_operand): Remove, replace by ...
[gcc.git] / gcc / config / s390 / s390.md
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
21
22 ;;
23 ;; Special constraints for s/390 machine description:
24 ;;
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
32 ;;
33 ;; Special formats used for outputting 390 instructions.
34 ;;
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
41 ;;
42 ;; We have a special constraint for pattern matching.
43 ;;
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
45 ;;
46
47
48 ;; Define an insn type attribute. This is used in function unit delay
49 ;; computations.
50
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
53
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
57
58 (define_attr "atype" "reg,mem"
59 (const_string "reg"))
60
61 ;; Generic pipeline function unit.
62
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
65
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
68
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
71
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
74
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
77
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
80
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
83
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
86
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
89
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
92
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
95
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
98
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
101
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
104
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
107
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
110
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
113
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
116
117 ;; Operand type. Used to default length attribute values
118
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
121 (const_string "RX"))
122
123 ;; Length in bytes.
124
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
141 (const_int 4)))
142
143 ;; Define attributes for `asm' insns.
144
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
147
148 ;;
149 ;; Condition Codes
150 ;;
151 ;
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
157
158 ; CCZ -> CCL / CCZ1
159 ; CCZ1 -> CCA/CCU/CCS/CCT
160 ; CCS -> CCA
161
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
164
165
166 ;;
167 ;;- Compare instructions.
168 ;;
169
170 (define_expand "cmpdi"
171 [(set (reg:CC 33)
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
174 "TARGET_64BIT"
175 "
176 {
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
179 DONE;
180 }")
181
182 (define_expand "cmpsi"
183 [(set (reg:CC 33)
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
186 ""
187 "
188 {
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
191 DONE;
192 }")
193
194 (define_expand "cmpdf"
195 [(set (reg:CC 33)
196 (compare:CC (match_operand:DF 0 "register_operand" "")
197 (match_operand:DF 1 "general_operand" "")))]
198 "TARGET_HARD_FLOAT"
199 "
200 {
201 s390_compare_op0 = operands[0];
202 s390_compare_op1 = operands[1];
203 DONE;
204 }")
205
206 (define_expand "cmpsf"
207 [(set (reg:CC 33)
208 (compare:CC (match_operand:SF 0 "register_operand" "")
209 (match_operand:SF 1 "general_operand" "")))]
210 "TARGET_HARD_FLOAT"
211 "
212 {
213 s390_compare_op0 = operands[0];
214 s390_compare_op1 = operands[1];
215 DONE;
216 }")
217
218
219 ; Test-under-Mask (zero_extract) instructions
220
221 (define_insn "*tmdi_ext"
222 [(set (reg 33)
223 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
224 (match_operand:DI 1 "const_int_operand" "n")
225 (match_operand:DI 2 "const_int_operand" "n"))
226 (const_int 0)))]
227 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
228 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
229 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
230 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
231 == INTVAL (operands[2]) >> 4"
232 "*
233 {
234 int part = INTVAL (operands[2]) >> 4;
235 int block = (1 << INTVAL (operands[1])) - 1;
236 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
237
238 operands[2] = GEN_INT (block << shift);
239
240 switch (part)
241 {
242 case 0: return \"tmhh\\t%0,%x2\";
243 case 1: return \"tmhl\\t%0,%x2\";
244 case 2: return \"tmlh\\t%0,%x2\";
245 case 3: return \"tmll\\t%0,%x2\";
246 default: abort ();
247 }
248 }"
249 [(set_attr "op_type" "RI")])
250
251 (define_insn "*tmsi_ext"
252 [(set (reg 33)
253 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
254 (match_operand:SI 1 "const_int_operand" "n")
255 (match_operand:SI 2 "const_int_operand" "n"))
256 (const_int 0)))]
257 "s390_match_ccmode(insn, CCTmode)
258 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
259 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
260 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
261 == INTVAL (operands[2]) >> 4"
262 "*
263 {
264 int part = INTVAL (operands[2]) >> 4;
265 int block = (1 << INTVAL (operands[1])) - 1;
266 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
267
268 operands[2] = GEN_INT (block << shift);
269
270 switch (part)
271 {
272 case 0: return \"tmh\\t%0,%x2\";
273 case 1: return \"tml\\t%0,%x2\";
274 default: abort ();
275 }
276 }"
277 [(set_attr "op_type" "RI")])
278
279 (define_insn "*tmqi_ext"
280 [(set (reg 33)
281 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
282 (match_operand:SI 1 "const_int_operand" "n")
283 (match_operand:SI 2 "const_int_operand" "n"))
284 (const_int 0)))]
285 "s390_match_ccmode(insn, CCTmode)
286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
288 "*
289 {
290 int block = (1 << INTVAL (operands[1])) - 1;
291 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
292
293 operands[2] = GEN_INT (block << shift);
294 return \"tm\\t%0,%b2\";
295 }"
296 [(set_attr "op_type" "SI")
297 (set_attr "atype" "mem")])
298
299 ; Test-under-Mask instructions
300
301 (define_insn "*tmdi_mem"
302 [(set (reg 33)
303 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
304 (match_operand:DI 1 "immediate_operand" "n"))
305 (match_operand:DI 2 "immediate_operand" "n")))]
306 "TARGET_64BIT
307 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
308 && s390_single_qi (operands[1], DImode, 0) >= 0"
309 "*
310 {
311 int part = s390_single_qi (operands[1], DImode, 0);
312 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
313
314 operands[0] = gen_rtx_MEM (QImode,
315 plus_constant (XEXP (operands[0], 0), part));
316 return \"tm\\t%0,%b1\";
317 }"
318 [(set_attr "op_type" "SI")
319 (set_attr "atype" "mem")])
320
321 (define_insn "*tmsi_mem"
322 [(set (reg 33)
323 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
324 (match_operand:SI 1 "immediate_operand" "n"))
325 (match_operand:SI 2 "immediate_operand" "n")))]
326 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
327 && s390_single_qi (operands[1], SImode, 0) >= 0"
328 "*
329 {
330 int part = s390_single_qi (operands[1], SImode, 0);
331 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
332
333 operands[0] = gen_rtx_MEM (QImode,
334 plus_constant (XEXP (operands[0], 0), part));
335 return \"tm\\t%0,%b1\";
336 }"
337 [(set_attr "op_type" "SI")
338 (set_attr "atype" "mem")])
339
340 (define_insn "*tmhi_mem"
341 [(set (reg 33)
342 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
343 (match_operand:SI 1 "immediate_operand" "n"))
344 (match_operand:SI 2 "immediate_operand" "n")))]
345 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
346 && s390_single_qi (operands[1], HImode, 0) >= 0"
347 "*
348 {
349 int part = s390_single_qi (operands[1], HImode, 0);
350 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
351
352 operands[0] = gen_rtx_MEM (QImode,
353 plus_constant (XEXP (operands[0], 0), part));
354 return \"tm\\t%0,%b1\";
355 }"
356 [(set_attr "op_type" "SI")
357 (set_attr "atype" "mem")])
358
359 (define_insn "*tmqi_mem"
360 [(set (reg 33)
361 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
362 (match_operand:SI 1 "immediate_operand" "n"))
363 (match_operand:SI 2 "immediate_operand" "n")))]
364 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
365 "tm\\t%0,%b1"
366 [(set_attr "op_type" "SI")
367 (set_attr "atype" "mem")])
368
369 (define_insn "*tmdi_reg"
370 [(set (reg 33)
371 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
372 (match_operand:DI 1 "immediate_operand" "n"))
373 (match_operand:DI 2 "immediate_operand" "n")))]
374 "TARGET_64BIT
375 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
376 && s390_single_hi (operands[1], DImode, 0) >= 0"
377 "*
378 {
379 int part = s390_single_hi (operands[1], DImode, 0);
380 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
381
382 switch (part)
383 {
384 case 0: return \"tmhh\\t%0,%x1\";
385 case 1: return \"tmhl\\t%0,%x1\";
386 case 2: return \"tmlh\\t%0,%x1\";
387 case 3: return \"tmll\\t%0,%x1\";
388 default: abort ();
389 }
390 }"
391 [(set_attr "op_type" "RI")])
392
393 (define_insn "*tmsi_reg"
394 [(set (reg 33)
395 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
396 (match_operand:SI 1 "immediate_operand" "n"))
397 (match_operand:SI 2 "immediate_operand" "n")))]
398 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
399 && s390_single_hi (operands[1], SImode, 0) >= 0"
400 "*
401 {
402 int part = s390_single_hi (operands[1], SImode, 0);
403 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
404
405 switch (part)
406 {
407 case 0: return \"tmh\\t%0,%x1\";
408 case 1: return \"tml\\t%0,%x1\";
409 default: abort ();
410 }
411 }"
412 [(set_attr "op_type" "RI")])
413
414 (define_insn "*tmhi_full"
415 [(set (reg 33)
416 (compare (match_operand:HI 0 "register_operand" "d")
417 (match_operand:HI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
419 "tml\\t%0,65535"
420 [(set_attr "op_type" "RX")])
421
422 (define_insn "*tmqi_full"
423 [(set (reg 33)
424 (compare (match_operand:QI 0 "register_operand" "d")
425 (match_operand:QI 1 "immediate_operand" "n")))]
426 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
427 "tml\\t%0,255"
428 [(set_attr "op_type" "RI")])
429
430
431 ; Load-and-Test instructions
432
433 (define_insn "*tstdi_sign"
434 [(set (reg 33)
435 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
436 (const_int 32)) (const_int 32))
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
439 (sign_extend:DI (match_dup 0)))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
441 "ltgfr\\t%2,%0"
442 [(set_attr "op_type" "RRE")])
443
444 (define_insn "*tstdi"
445 [(set (reg 33)
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))
448 (set (match_operand:DI 2 "register_operand" "=d")
449 (match_dup 0))]
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
451 "ltgr\\t%2,%0"
452 [(set_attr "op_type" "RRE")])
453
454 (define_insn "*tstdi_cconly"
455 [(set (reg 33)
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
459 "ltgr\\t%0,%0"
460 [(set_attr "op_type" "RRE")])
461
462 (define_insn "*tstdi_cconly_31"
463 [(set (reg 33)
464 (compare (match_operand:DI 0 "register_operand" "d")
465 (match_operand:DI 1 "const0_operand" "")))]
466 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
467 "srda\\t%0,0"
468 [(set_attr "op_type" "RS")])
469
470 (define_insn "*tstsi"
471 [(set (reg 33)
472 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
473 (match_operand:SI 1 "const0_operand" "")))
474 (set (match_operand:SI 2 "register_operand" "=d,d")
475 (match_dup 0))]
476 "s390_match_ccmode(insn, CCSmode)"
477 "@
478 ltr\\t%2,%0
479 icm\\t%2,15,%0"
480 [(set_attr "op_type" "RR,RS")
481 (set_attr "atype" "reg,mem")])
482
483 (define_insn "*tstsi_cconly"
484 [(set (reg 33)
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
486 (match_operand:SI 1 "const0_operand" "")))
487 (clobber (match_scratch:SI 2 "=X,d"))]
488 "s390_match_ccmode(insn, CCSmode)"
489 "@
490 ltr\\t%0,%0
491 icm\\t%2,15,%0"
492 [(set_attr "op_type" "RR,RS")
493 (set_attr "atype" "reg,mem")])
494
495 (define_insn "*tstsi_cconly2"
496 [(set (reg 33)
497 (compare (match_operand:SI 0 "register_operand" "d")
498 (match_operand:SI 1 "const0_operand" "")))]
499 "s390_match_ccmode(insn, CCSmode)"
500 "ltr\\t%0,%0"
501 [(set_attr "op_type" "RR")])
502
503 (define_insn "*tsthi"
504 [(set (reg 33)
505 (compare (match_operand:HI 0 "s_operand" "Q")
506 (match_operand:HI 1 "const0_operand" "")))
507 (set (match_operand:HI 2 "register_operand" "=d")
508 (match_dup 0))]
509 "s390_match_ccmode(insn, CCSmode)"
510 "icm\\t%2,3,%0"
511 [(set_attr "op_type" "RS")
512 (set_attr "atype" "mem")])
513
514 (define_insn "*tsthi_cconly"
515 [(set (reg 33)
516 (compare (match_operand:HI 0 "s_operand" "Q")
517 (match_operand:HI 1 "const0_operand" "")))
518 (clobber (match_scratch:HI 2 "=d"))]
519 "s390_match_ccmode(insn, CCSmode)"
520 "icm\\t%2,3,%0"
521 [(set_attr "op_type" "RS")
522 (set_attr "atype" "mem")])
523
524 (define_insn "*tstqi"
525 [(set (reg 33)
526 (compare (match_operand:QI 0 "s_operand" "Q")
527 (match_operand:QI 1 "const0_operand" "")))
528 (set (match_operand:QI 2 "register_operand" "=d")
529 (match_dup 0))]
530 "s390_match_ccmode(insn, CCSmode)"
531 "icm\\t%2,1,%0"
532 [(set_attr "op_type" "RS")
533 (set_attr "atype" "mem")])
534
535 (define_insn "*tstqi_cconly"
536 [(set (reg 33)
537 (compare (match_operand:QI 0 "s_operand" "Q")
538 (match_operand:QI 1 "const0_operand" "")))
539 (clobber (match_scratch:QI 2 "=d"))]
540 "s390_match_ccmode(insn, CCSmode)"
541 "icm\\t%2,1,%0"
542 [(set_attr "op_type" "RS")
543 (set_attr "atype" "mem")])
544
545
546 ; Compare (signed) instructions
547
548 (define_insn "*cmpdi_ccs_sign"
549 [(set (reg 33)
550 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
551 (match_operand:DI 0 "register_operand" "d,d")))]
552 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
553 "@
554 cgfr\\t%0,%1
555 cgf\\t%0,%1"
556 [(set_attr "op_type" "RRE,RXE")
557 (set_attr "atype" "reg,mem")])
558
559 (define_insn "*cmpdi_ccs"
560 [(set (reg 33)
561 (compare (match_operand:DI 0 "register_operand" "d,d,d")
562 (match_operand:DI 1 "general_operand" "d,K,m")))]
563 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
564 "@
565 cgr\\t%0,%1
566 cghi\\t%0,%c1
567 cg\\t%0,%1"
568 [(set_attr "op_type" "RRE,RI,RXE")
569 (set_attr "atype" "reg,reg,mem")])
570
571 (define_insn "*cmpsi_ccs_sign"
572 [(set (reg 33)
573 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
574 (match_operand:SI 0 "register_operand" "d")))]
575 "s390_match_ccmode(insn, CCSRmode)"
576 "ch\\t%0,%1"
577 [(set_attr "op_type" "RX")
578 (set_attr "atype" "mem")])
579
580 (define_insn "*cmpsi_ccs"
581 [(set (reg 33)
582 (compare (match_operand:SI 0 "register_operand" "d,d,d")
583 (match_operand:SI 1 "general_operand" "d,K,m")))]
584 "s390_match_ccmode(insn, CCSmode)"
585 "@
586 cr\\t%0,%1
587 chi\\t%0,%c1
588 c\\t%0,%1"
589 [(set_attr "op_type" "RR,RI,RX")
590 (set_attr "atype" "reg,reg,mem")])
591
592
593 ; Compare (unsigned) instructions
594
595 (define_insn "*cmpdi_ccu_zero"
596 [(set (reg 33)
597 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
598 (match_operand:DI 0 "register_operand" "d,d")))]
599 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
600 "@
601 clgfr\\t%0,%1
602 clgf\\t%0,%1"
603 [(set_attr "op_type" "RRE,RXE")
604 (set_attr "atype" "reg,mem")])
605
606 (define_insn "*cmpdi_ccu"
607 [(set (reg 33)
608 (compare (match_operand:DI 0 "register_operand" "d,d")
609 (match_operand:DI 1 "general_operand" "d,m")))]
610 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
611 "@
612 clgr\\t%0,%1
613 clg\\t%0,%1"
614 [(set_attr "op_type" "RRE,RXE")
615 (set_attr "atype" "reg,mem")])
616
617 (define_insn "*cmpsi_ccu"
618 [(set (reg 33)
619 (compare (match_operand:SI 0 "register_operand" "d,d")
620 (match_operand:SI 1 "general_operand" "d,m")))]
621 "s390_match_ccmode(insn, CCUmode)"
622 "@
623 clr\\t%0,%1
624 cl\\t%0,%1"
625 [(set_attr "op_type" "RR,RX")
626 (set_attr "atype" "reg,mem")])
627
628 (define_insn "*cmphi_ccu"
629 [(set (reg 33)
630 (compare (match_operand:HI 0 "register_operand" "d")
631 (match_operand:HI 1 "s_imm_operand" "Q")))]
632 "s390_match_ccmode(insn, CCUmode)"
633 "clm\\t%0,3,%1"
634 [(set_attr "op_type" "RS")
635 (set_attr "atype" "mem")])
636
637 (define_insn "*cmpqi_ccu"
638 [(set (reg 33)
639 (compare (match_operand:QI 0 "register_operand" "d")
640 (match_operand:QI 1 "s_imm_operand" "Q")))]
641 "s390_match_ccmode(insn, CCUmode)"
642 "clm\\t%0,1,%1"
643 [(set_attr "op_type" "RS")
644 (set_attr "atype" "mem")])
645
646 (define_insn "*cli"
647 [(set (reg 33)
648 (compare (match_operand:QI 0 "memory_operand" "Q")
649 (match_operand:QI 1 "immediate_operand" "n")))]
650 "s390_match_ccmode (insn, CCUmode)"
651 "cli\\t%0,%b1"
652 [(set_attr "op_type" "SI")
653 (set_attr "atype" "mem")])
654
655 (define_insn "*cmpdi_ccu_mem"
656 [(set (reg 33)
657 (compare (match_operand:DI 0 "s_operand" "Q")
658 (match_operand:DI 1 "s_imm_operand" "Q")))]
659 "s390_match_ccmode(insn, CCUmode)"
660 "clc\\t%O0(8,%R0),%1"
661 [(set_attr "op_type" "SS")
662 (set_attr "atype" "mem")])
663
664 (define_insn "*cmpsi_ccu_mem"
665 [(set (reg 33)
666 (compare (match_operand:SI 0 "s_operand" "Q")
667 (match_operand:SI 1 "s_imm_operand" "Q")))]
668 "s390_match_ccmode(insn, CCUmode)"
669 "clc\\t%O0(4,%R0),%1"
670 [(set_attr "op_type" "SS")
671 (set_attr "atype" "mem")])
672
673 (define_insn "*cmphi_ccu_mem"
674 [(set (reg 33)
675 (compare (match_operand:HI 0 "s_operand" "Q")
676 (match_operand:HI 1 "s_imm_operand" "Q")))]
677 "s390_match_ccmode(insn, CCUmode)"
678 "clc\\t%O0(2,%R0),%1"
679 [(set_attr "op_type" "SS")
680 (set_attr "atype" "mem")])
681
682 (define_insn "*cmpqi_ccu_mem"
683 [(set (reg 33)
684 (compare (match_operand:QI 0 "s_operand" "Q")
685 (match_operand:QI 1 "s_imm_operand" "Q")))]
686 "s390_match_ccmode(insn, CCUmode)"
687 "clc\\t%O0(1,%R0),%1"
688 [(set_attr "op_type" "SS")
689 (set_attr "atype" "mem")])
690
691
692 ; DF instructions
693
694 (define_insn "*cmpdf_ccs_0"
695 [(set (reg 33)
696 (compare (match_operand:DF 0 "register_operand" "f")
697 (match_operand:DF 1 "const0_operand" "")))]
698 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
699 "ltdbr\\t%0,%0"
700 [(set_attr "op_type" "RRE")])
701
702 (define_insn "*cmpdf_ccs_0_ibm"
703 [(set (reg 33)
704 (compare (match_operand:DF 0 "register_operand" "f")
705 (match_operand:DF 1 "const0_operand" "")))]
706 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
707 "ltdr\\t%0,%0"
708 [(set_attr "op_type" "RR")])
709
710 (define_insn "*cmpdf_ccs"
711 [(set (reg 33)
712 (compare (match_operand:DF 0 "register_operand" "f,f")
713 (match_operand:DF 1 "general_operand" "f,m")))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
715 "@
716 cdbr\\t%0,%1
717 cdb\\t%0,%1"
718 [(set_attr "op_type" "RRE,RXE")
719 (set_attr "atype" "reg,mem")])
720
721 (define_insn "*cmpdf_ccs_ibm"
722 [(set (reg 33)
723 (compare (match_operand:DF 0 "register_operand" "f,f")
724 (match_operand:DF 1 "general_operand" "f,m")))]
725 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
726 "@
727 cdr\\t%0,%1
728 cd\\t%0,%1"
729 [(set_attr "op_type" "RR,RX")
730 (set_attr "atype" "reg,mem")])
731
732
733 ; SF instructions
734
735 (define_insn "*cmpsf_ccs_0"
736 [(set (reg 33)
737 (compare (match_operand:SF 0 "register_operand" "f")
738 (match_operand:SF 1 "const0_operand" "")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
740 "ltebr\\t%0,%0"
741 [(set_attr "op_type" "RRE")])
742
743 (define_insn "*cmpsf_ccs_0_ibm"
744 [(set (reg 33)
745 (compare (match_operand:SF 0 "register_operand" "f")
746 (match_operand:SF 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
748 "lter\\t%0,%0"
749 [(set_attr "op_type" "RR")])
750
751 (define_insn "*cmpsf_ccs"
752 [(set (reg 33)
753 (compare (match_operand:SF 0 "register_operand" "f,f")
754 (match_operand:SF 1 "general_operand" "f,m")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
756 "@
757 cebr\\t%0,%1
758 ceb\\t%0,%1"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "atype" "reg,mem")])
761
762 (define_insn "*cmpsf_ccs"
763 [(set (reg 33)
764 (compare (match_operand:SF 0 "register_operand" "f,f")
765 (match_operand:SF 1 "general_operand" "f,m")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
767 "@
768 cer\\t%0,%1
769 ce\\t%0,%1"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "atype" "reg,mem")])
772
773
774 ;;
775 ;;- Move instructions.
776 ;;
777
778 ;
779 ; movti instruction pattern(s).
780 ;
781
782 (define_insn "movti"
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
784 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
785 "TARGET_64BIT"
786 "@
787 lmg\\t%0,%N0,%1
788 stmg\\t%1,%N1,%0
789 #
790 #
791 mvc\\t%O0(16,%R0),%1"
792 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
793 (set_attr "atype" "mem")])
794
795 (define_split
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && !s_operand (operands[0], VOIDmode)
800 && !s_operand (operands[1], VOIDmode)
801 && (register_operand (operands[0], VOIDmode)
802 || register_operand (operands[1], VOIDmode))
803 && (!register_operand (operands[0], VOIDmode)
804 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
805 operands[1])
806 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
807 operands[1]))"
808 [(set (match_dup 2) (match_dup 4))
809 (set (match_dup 3) (match_dup 5))]
810 "
811 {
812 if (!register_operand (operands[0], VOIDmode)
813 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
814 operands[1]))
815 {
816 operands[2] = operand_subword (operands[0], 0, 0, TImode);
817 operands[3] = operand_subword (operands[0], 1, 0, TImode);
818 operands[4] = operand_subword (operands[1], 0, 0, TImode);
819 operands[5] = operand_subword (operands[1], 1, 0, TImode);
820 }
821 else
822 {
823 operands[2] = operand_subword (operands[0], 1, 0, TImode);
824 operands[3] = operand_subword (operands[0], 0, 0, TImode);
825 operands[4] = operand_subword (operands[1], 1, 0, TImode);
826 operands[5] = operand_subword (operands[1], 0, 0, TImode);
827 }
828 }")
829
830 (define_split
831 [(set (match_operand:TI 0 "register_operand" "")
832 (match_operand:TI 1 "memory_operand" ""))]
833 "TARGET_64BIT && reload_completed
834 && !s_operand (operands[1], VOIDmode)"
835 [(set (match_dup 0) (match_dup 1))]
836 "
837 {
838 rtx addr = operand_subword (operands[0], 1, 0, TImode);
839 s390_load_address (addr, XEXP (operands[1], 0));
840 operands[1] = replace_equiv_address (operands[1], addr);
841 }")
842
843 ;
844 ; movdi instruction pattern(s).
845 ;
846
847 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
848 ;; move to get the address of the symbolic object from the GOT.
849
850 (define_expand "movdi"
851 [(set (match_operand:DI 0 "general_operand" "")
852 (match_operand:DI 1 "general_operand" ""))]
853 ""
854 "
855 {
856 /* Handle PIC symbolic constants. */
857 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
858 emit_pic_move (operands, DImode);
859
860 /* During and after reload, we need to force constants
861 to the literal pool ourselves, if necessary. */
862 if ((reload_in_progress || reload_completed)
863 && CONSTANT_P (operands[1])
864 && (!legitimate_reload_constant_p (operands[1])
865 || fp_operand (operands[0], VOIDmode)))
866 operands[1] = force_const_mem (DImode, operands[1]);
867 }")
868
869 (define_insn "*movdi_lhi"
870 [(set (match_operand:DI 0 "register_operand" "=d")
871 (match_operand:DI 1 "immediate_operand" "K"))]
872 "TARGET_64BIT
873 && GET_CODE (operands[1]) == CONST_INT
874 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
875 && !fp_operand (operands[0], VOIDmode)"
876 "lghi\\t%0,%h1"
877 [(set_attr "op_type" "RI")
878 (set_attr "atype" "reg")])
879
880 (define_insn "*movdi_lli"
881 [(set (match_operand:DI 0 "register_operand" "=d")
882 (match_operand:DI 1 "immediate_operand" "n"))]
883 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
884 && !fp_operand (operands[0], VOIDmode)"
885 "*
886 {
887 int part = s390_single_hi (operands[1], DImode, 0);
888 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
889
890 switch (part)
891 {
892 case 0: return \"llihh\\t%0,%x1\";
893 case 1: return \"llihl\\t%0,%x1\";
894 case 2: return \"llilh\\t%0,%x1\";
895 case 3: return \"llill\\t%0,%x1\";
896 default: abort ();
897 }
898 }"
899 [(set_attr "op_type" "RI")
900 (set_attr "atype" "reg")])
901
902 (define_insn "*movdi_larl"
903 [(set (match_operand:DI 0 "register_operand" "=d")
904 (match_operand:DI 1 "larl_operand" "X"))]
905 "TARGET_64BIT
906 && !fp_operand (operands[0], VOIDmode)"
907 "larl\\t%0,%1"
908 [(set_attr "op_type" "RIL")
909 (set_attr "atype" "reg")
910 (set_attr "type" "la")])
911
912 (define_insn "*movdi_64"
913 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
914 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
915 "TARGET_64BIT"
916 "@
917 lgr\\t%0,%1
918 lg\\t%0,%1
919 stg\\t%1,%0
920 ldr\\t%0,%1
921 ld\\t%0,%1
922 std\\t%1,%0
923 mvc\\t%O0(8,%R0),%1"
924 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX,SS")
925 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
926
927 (define_insn "*movdi_31"
928 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
929 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
930 "!TARGET_64BIT"
931 "@
932 lm\\t%0,%N0,%1
933 stm\\t%1,%N1,%0
934 #
935 #
936 ldr\\t%0,%1
937 ld\\t%0,%1
938 std\\t%1,%0
939 mvc\\t%O0(8,%R0),%1"
940 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
941 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
942
943 (define_split
944 [(set (match_operand:DI 0 "nonimmediate_operand" "")
945 (match_operand:DI 1 "general_operand" ""))]
946 "!TARGET_64BIT && reload_completed
947 && !fp_operand (operands[0], VOIDmode)
948 && !fp_operand (operands[1], VOIDmode)
949 && !s_operand (operands[0], VOIDmode)
950 && !s_operand (operands[1], VOIDmode)
951 && (register_operand (operands[0], VOIDmode)
952 || register_operand (operands[1], VOIDmode))
953 && (!register_operand (operands[0], VOIDmode)
954 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
955 operands[1])
956 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
957 operands[1]))"
958 [(set (match_dup 2) (match_dup 4))
959 (set (match_dup 3) (match_dup 5))]
960 "
961 {
962 if (!register_operand (operands[0], VOIDmode)
963 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
964 operands[1]))
965 {
966 operands[2] = operand_subword (operands[0], 0, 0, DImode);
967 operands[3] = operand_subword (operands[0], 1, 0, DImode);
968 operands[4] = operand_subword (operands[1], 0, 0, DImode);
969 operands[5] = operand_subword (operands[1], 1, 0, DImode);
970 }
971 else
972 {
973 operands[2] = operand_subword (operands[0], 1, 0, DImode);
974 operands[3] = operand_subword (operands[0], 0, 0, DImode);
975 operands[4] = operand_subword (operands[1], 1, 0, DImode);
976 operands[5] = operand_subword (operands[1], 0, 0, DImode);
977 }
978 }")
979
980 (define_split
981 [(set (match_operand:DI 0 "register_operand" "")
982 (match_operand:DI 1 "memory_operand" ""))]
983 "!TARGET_64BIT && reload_completed
984 && !fp_operand (operands[0], VOIDmode)
985 && !fp_operand (operands[1], VOIDmode)
986 && !s_operand (operands[1], VOIDmode)"
987 [(set (match_dup 0) (match_dup 1))]
988 "
989 {
990 rtx addr = operand_subword (operands[0], 1, 0, DImode);
991 s390_load_address (addr, XEXP (operands[1], 0));
992 operands[1] = replace_equiv_address (operands[1], addr);
993 }")
994
995 ;
996 ; movsi instruction pattern(s).
997 ;
998
999 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1000 ;; move to get the address of the symbolic object from the GOT.
1001
1002 (define_expand "movsi"
1003 [(set (match_operand:SI 0 "general_operand" "")
1004 (match_operand:SI 1 "general_operand" ""))]
1005 ""
1006 "
1007 {
1008 /* Handle PIC symbolic constants. */
1009 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1010 emit_pic_move (operands, SImode);
1011
1012 /* expr.c tries to load an effective address using
1013 force_reg. This fails because we don't have a
1014 generic load_address pattern. Convert the move
1015 to a proper arithmetic operation instead, unless
1016 it is guaranteed to be OK. */
1017 if (GET_CODE (operands[1]) == PLUS
1018 && !legitimate_la_operand_p (operands[1]))
1019 {
1020 operands[1] = force_operand (operands[1], operands[0]);
1021 if (operands[1] == operands[0])
1022 DONE;
1023 }
1024
1025 /* During and after reload, we need to force constants
1026 to the literal pool ourselves, if necessary. */
1027 if ((reload_in_progress || reload_completed)
1028 && CONSTANT_P (operands[1])
1029 && (!legitimate_reload_constant_p (operands[1])
1030 || fp_operand (operands[0], VOIDmode)))
1031 operands[1] = force_const_mem (SImode, operands[1]);
1032 }")
1033
1034 (define_insn "*movsi_lhi"
1035 [(set (match_operand:SI 0 "register_operand" "=d")
1036 (match_operand:SI 1 "immediate_operand" "K"))]
1037 "GET_CODE (operands[1]) == CONST_INT
1038 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1039 && !fp_operand (operands[0], VOIDmode)"
1040 "lhi\\t%0,%h1"
1041 [(set_attr "op_type" "RI")])
1042
1043 (define_insn "*movsi_lli"
1044 [(set (match_operand:SI 0 "register_operand" "=d")
1045 (match_operand:SI 1 "immediate_operand" "n"))]
1046 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1047 && !fp_operand (operands[0], VOIDmode)"
1048 "*
1049 {
1050 int part = s390_single_hi (operands[1], SImode, 0);
1051 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1052
1053 switch (part)
1054 {
1055 case 0: return \"llilh\\t%0,%x1\";
1056 case 1: return \"llill\\t%0,%x1\";
1057 default: abort ();
1058 }
1059 }"
1060 [(set_attr "op_type" "RI")])
1061
1062 (define_insn "*movsi"
1063 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1064 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1065 ""
1066 "@
1067 lr\\t%0,%1
1068 l\\t%0,%1
1069 st\\t%1,%0
1070 ler\\t%0,%1
1071 le\\t%0,%1
1072 ste\\t%1,%0
1073 mvc\\t%O0(4,%R0),%1"
1074 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1075 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1076
1077
1078 ;
1079 ; movhi instruction pattern(s).
1080 ;
1081
1082 (define_insn "movhi"
1083 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1084 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1085 ""
1086 "@
1087 lr\\t%0,%1
1088 lhi\\t%0,%h1
1089 lh\\t%0,%1
1090 sth\\t%1,%0
1091 mvc\\t%O0(2,%R0),%1"
1092 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1093 (set_attr "atype" "reg,reg,mem,mem,mem")])
1094
1095
1096 ;
1097 ; movqi instruction pattern(s).
1098 ;
1099
1100 (define_insn "movqi_64"
1101 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1102 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1103 "TARGET_64BIT"
1104 "@
1105 lr\\t%0,%1
1106 lhi\\t%0,%b1
1107 llgc\\t%0,%1
1108 stc\\t%1,%0
1109 mvi\\t%0,%b1
1110 mvc\\t%O0(1,%R0),%1"
1111 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1112 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1113
1114
1115 (define_insn "movqi"
1116 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1117 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1118 ""
1119 "@
1120 lr\\t%0,%1
1121 lhi\\t%0,%b1
1122 ic\\t%0,%1
1123 stc\\t%1,%0
1124 mvi\\t%0,%b1
1125 mvc\\t%O0(1,%R0),%1"
1126 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1127 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1128
1129
1130 ;
1131 ; movstrictqi instruction pattern(s).
1132 ;
1133
1134 (define_insn "*movstrictqi"
1135 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1136 (match_operand:QI 1 "memory_operand" "m"))]
1137 ""
1138 "ic\\t%0,%1"
1139 [(set_attr "op_type" "RX")
1140 (set_attr "atype" "mem")])
1141
1142 ;
1143 ; movstricthi instruction pattern(s).
1144 ;
1145
1146 (define_insn "*movstricthi"
1147 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1148 (match_operand:HI 1 "s_imm_operand" "Q"))
1149 (clobber (reg:CC 33))]
1150 ""
1151 "icm\\t%0,3,%1"
1152 [(set_attr "op_type" "RS")
1153 (set_attr "atype" "mem")])
1154
1155
1156 ;
1157 ; movstrictsi instruction pattern(s).
1158 ;
1159
1160 (define_insn "movstrictsi"
1161 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1162 (match_operand:SI 1 "general_operand" "d,m"))]
1163 "TARGET_64BIT"
1164 "@
1165 lr\\t%0,%1
1166 l\\t%0,%1"
1167 [(set_attr "op_type" "RR,RS")
1168 (set_attr "atype" "reg,mem")])
1169
1170
1171 ;
1172 ; movdf instruction pattern(s).
1173 ;
1174
1175 (define_expand "movdf"
1176 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1177 (match_operand:DF 1 "general_operand" ""))]
1178 ""
1179 "
1180 {
1181 /* During and after reload, we need to force constants
1182 to the literal pool ourselves, if necessary. */
1183 if ((reload_in_progress || reload_completed)
1184 && CONSTANT_P (operands[1]))
1185 operands[1] = force_const_mem (DFmode, operands[1]);
1186 }")
1187
1188 (define_insn "*movdf_64"
1189 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1190 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1191 "TARGET_64BIT"
1192 "@
1193 ldr\\t%0,%1
1194 ld\\t%0,%1
1195 std\\t%1,%0
1196 lgr\\t%0,%1
1197 lg\\t%0,%1
1198 stg\\t%1,%0
1199 mvc\\t%O0(8,%R0),%1"
1200 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE,SS")
1201 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1202
1203 (define_insn "*movdf_31"
1204 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1205 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1206 "!TARGET_64BIT"
1207 "@
1208 ldr\\t%0,%1
1209 ld\\t%0,%1
1210 std\\t%1,%0
1211 lm\\t%0,%N0,%1
1212 stm\\t%1,%N1,%0
1213 #
1214 #
1215 mvc\\t%O0(8,%R0),%1"
1216 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1217 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
1218
1219 (define_split
1220 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1221 (match_operand:DF 1 "general_operand" ""))]
1222 "!TARGET_64BIT && reload_completed
1223 && !fp_operand (operands[0], VOIDmode)
1224 && !fp_operand (operands[1], VOIDmode)
1225 && !s_operand (operands[0], VOIDmode)
1226 && !s_operand (operands[1], VOIDmode)
1227 && (register_operand (operands[0], VOIDmode)
1228 || register_operand (operands[1], VOIDmode))
1229 && (!register_operand (operands[0], VOIDmode)
1230 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1231 operands[1])
1232 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1233 operands[1]))"
1234 [(set (match_dup 2) (match_dup 4))
1235 (set (match_dup 3) (match_dup 5))]
1236 "
1237 {
1238 if (!register_operand (operands[0], VOIDmode)
1239 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1240 operands[1]))
1241 {
1242 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1243 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1244 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1245 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1246 }
1247 else
1248 {
1249 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1250 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1251 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1252 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1253 }
1254 }")
1255
1256 (define_split
1257 [(set (match_operand:DF 0 "register_operand" "")
1258 (match_operand:DF 1 "memory_operand" ""))]
1259 "!TARGET_64BIT && reload_completed
1260 && !fp_operand (operands[0], VOIDmode)
1261 && !fp_operand (operands[1], VOIDmode)
1262 && !s_operand (operands[1], VOIDmode)"
1263 [(set (match_dup 0) (match_dup 1))]
1264 "
1265 {
1266 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1267 s390_load_address (addr, XEXP (operands[1], 0));
1268 operands[1] = replace_equiv_address (operands[1], addr);
1269 }")
1270
1271 ;
1272 ; movsf instruction pattern(s).
1273 ;
1274
1275 (define_expand "movsf"
1276 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1277 (match_operand:SF 1 "general_operand" ""))]
1278 ""
1279 "
1280 {
1281 /* During and after reload, we need to force constants
1282 to the literal pool ourselves, if necessary. */
1283 if ((reload_in_progress || reload_completed)
1284 && CONSTANT_P (operands[1]))
1285 operands[1] = force_const_mem (SFmode, operands[1]);
1286 }")
1287
1288 (define_insn "*movsf"
1289 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1290 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1291 ""
1292 "@
1293 ler\\t%0,%1
1294 le\\t%0,%1
1295 ste\\t%1,%0
1296 lr\\t%0,%1
1297 l\\t%0,%1
1298 st\\t%1,%0
1299 mvc\\t%O0(4,%R0),%1"
1300 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1301 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1302
1303 ;
1304 ; load_multiple pattern(s).
1305 ;
1306
1307 (define_expand "load_multiple"
1308 [(match_par_dup 3 [(set (match_operand 0 "" "")
1309 (match_operand 1 "" ""))
1310 (use (match_operand 2 "" ""))])]
1311 ""
1312 "
1313 {
1314 int regno;
1315 int count;
1316 rtx from;
1317 int i, off;
1318
1319 /* Support only loading a constant number of fixed-point registers from
1320 memory and only bother with this if more than two */
1321 if (GET_CODE (operands[2]) != CONST_INT
1322 || INTVAL (operands[2]) < 2
1323 || INTVAL (operands[2]) > 16
1324 || GET_CODE (operands[1]) != MEM
1325 || GET_CODE (operands[0]) != REG
1326 || REGNO (operands[0]) >= 16)
1327 FAIL;
1328
1329 count = INTVAL (operands[2]);
1330 regno = REGNO (operands[0]);
1331
1332 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1333 if (no_new_pseudos)
1334 {
1335 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1336 {
1337 from = XEXP (operands[1], 0);
1338 off = 0;
1339 }
1340 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1341 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1342 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1343 {
1344 from = XEXP (XEXP (operands[1], 0), 0);
1345 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1346 }
1347 else
1348 FAIL;
1349
1350 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1351 FAIL;
1352 }
1353 else
1354 {
1355 from = force_reg (Pmode, XEXP (operands[1], 0));
1356 off = 0;
1357 }
1358
1359 for (i = 0; i < count; i++)
1360 XVECEXP (operands[3], 0, i)
1361 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1362 change_address (operands[1], Pmode,
1363 plus_constant (from,
1364 off + i * UNITS_PER_WORD)));
1365 }")
1366
1367 (define_insn "*load_multiple_di"
1368 [(match_parallel 0 "load_multiple_operation"
1369 [(set (match_operand:DI 1 "register_operand" "=r")
1370 (match_operand:DI 2 "s_operand" "Q"))])]
1371 ""
1372 "*
1373 {
1374 int words = XVECLEN (operands[0], 0);
1375
1376 if (XVECLEN (operands[0], 0) == 1)
1377 return \"lg\\t%1,0(%2)\";
1378
1379 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1380 return \"lmg\\t%1,%0,%2\";
1381 }"
1382 [(set_attr "op_type" "RXE")
1383 (set_attr "atype" "mem")
1384 (set_attr "type" "lm")])
1385
1386 (define_insn "*load_multiple_si"
1387 [(match_parallel 0 "load_multiple_operation"
1388 [(set (match_operand:SI 1 "register_operand" "=r")
1389 (match_operand:SI 2 "s_operand" "Q"))])]
1390 ""
1391 "*
1392 {
1393 int words = XVECLEN (operands[0], 0);
1394
1395 if (XVECLEN (operands[0], 0) == 1)
1396 return \"l\\t%1,0(%2)\";
1397
1398 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1399 return \"lm\\t%1,%0,%2\";
1400 }"
1401 [(set_attr "op_type" "RXE")
1402 (set_attr "atype" "mem")
1403 (set_attr "type" "lm")])
1404
1405 ;
1406 ; store multiple pattern(s).
1407 ;
1408
1409 (define_expand "store_multiple"
1410 [(match_par_dup 3 [(set (match_operand 0 "" "")
1411 (match_operand 1 "" ""))
1412 (use (match_operand 2 "" ""))])]
1413 ""
1414 "
1415 {
1416 int regno;
1417 int count;
1418 rtx to;
1419 int i, off;
1420
1421 /* Support only storing a constant number of fixed-point registers to
1422 memory and only bother with this if more than two. */
1423 if (GET_CODE (operands[2]) != CONST_INT
1424 || INTVAL (operands[2]) < 2
1425 || INTVAL (operands[2]) > 16
1426 || GET_CODE (operands[0]) != MEM
1427 || GET_CODE (operands[1]) != REG
1428 || REGNO (operands[1]) >= 16)
1429 FAIL;
1430
1431 count = INTVAL (operands[2]);
1432 regno = REGNO (operands[1]);
1433
1434 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1435
1436 if (no_new_pseudos)
1437 {
1438 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1439 {
1440 to = XEXP (operands[0], 0);
1441 off = 0;
1442 }
1443 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1444 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1445 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1446 {
1447 to = XEXP (XEXP (operands[0], 0), 0);
1448 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1449 }
1450 else
1451 FAIL;
1452
1453 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1454 FAIL;
1455 }
1456 else
1457 {
1458 to = force_reg (Pmode, XEXP (operands[0], 0));
1459 off = 0;
1460 }
1461
1462 for (i = 0; i < count; i++)
1463 XVECEXP (operands[3], 0, i)
1464 = gen_rtx_SET (VOIDmode,
1465 change_address (operands[0], Pmode,
1466 plus_constant (to,
1467 off + i * UNITS_PER_WORD)),
1468 gen_rtx_REG (Pmode, regno + i));
1469 }")
1470
1471 (define_insn "*store_multiple_di"
1472 [(match_parallel 0 "store_multiple_operation"
1473 [(set (match_operand:DI 1 "s_operand" "=Q")
1474 (match_operand:DI 2 "register_operand" "r"))])]
1475 ""
1476 "*
1477 {
1478 int words = XVECLEN (operands[0], 0);
1479
1480 if (XVECLEN (operands[0], 0) == 1)
1481 return \"stg\\t%1,0(%2)\";
1482
1483 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1484 return \"stmg\\t%2,%0,%1\";
1485 }"
1486 [(set_attr "op_type" "RXE")
1487 (set_attr "atype" "mem")
1488 (set_attr "type" "stm")])
1489
1490
1491 (define_insn "*store_multiple_si"
1492 [(match_parallel 0 "store_multiple_operation"
1493 [(set (match_operand:SI 1 "s_operand" "=Q")
1494 (match_operand:SI 2 "register_operand" "r"))])]
1495 ""
1496 "*
1497 {
1498 int words = XVECLEN (operands[0], 0);
1499
1500 if (XVECLEN (operands[0], 0) == 1)
1501 return \"st\\t%1,0(%2)\";
1502
1503 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1504 return \"stm\\t%2,%0,%1\";
1505 }"
1506 [(set_attr "op_type" "RXE")
1507 (set_attr "atype" "mem")
1508 (set_attr "type" "stm")])
1509
1510 ;;
1511 ;; String instructions.
1512 ;;
1513
1514 ;
1515 ; movstrM instruction pattern(s).
1516 ;
1517
1518 (define_expand "movstrdi"
1519 [(set (match_operand:BLK 0 "memory_operand" "")
1520 (match_operand:BLK 1 "memory_operand" ""))
1521 (use (match_operand:DI 2 "general_operand" ""))
1522 (match_operand 3 "" "")]
1523 "TARGET_64BIT"
1524 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1525
1526 (define_expand "movstrsi"
1527 [(set (match_operand:BLK 0 "memory_operand" "")
1528 (match_operand:BLK 1 "memory_operand" ""))
1529 (use (match_operand:SI 2 "general_operand" ""))
1530 (match_operand 3 "" "")]
1531 ""
1532 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1533
1534 ; Move a block that is up to 256 bytes in length.
1535 ; The block length is taken as (operands[2] % 256) + 1.
1536
1537 (define_insn "movstr_short_64"
1538 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1539 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1540 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1541 (clobber (match_scratch:DI 3 "=X,&a"))]
1542 "TARGET_64BIT"
1543 "*
1544 {
1545 switch (which_alternative)
1546 {
1547 case 0:
1548 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1549
1550 case 1:
1551 output_asm_insn (\"bras\\t%3,.+10\", operands);
1552 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1553 return \"ex\\t%2,0(%3)\";
1554
1555 default:
1556 abort ();
1557 }
1558 }"
1559 [(set_attr "op_type" "SS,NN")
1560 (set_attr "type" "cs,cs")
1561 (set_attr "atype" "mem,mem")
1562 (set_attr "length" "*,14")])
1563
1564 (define_insn "movstr_short_31"
1565 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1566 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1567 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1568 (clobber (match_scratch:SI 3 "=X,&a"))]
1569 "!TARGET_64BIT"
1570 "*
1571 {
1572 switch (which_alternative)
1573 {
1574 case 0:
1575 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1576
1577 case 1:
1578 output_asm_insn (\"bras\\t%3,.+10\", operands);
1579 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1580 return \"ex\\t%2,0(%3)\";
1581
1582 default:
1583 abort ();
1584 }
1585 }"
1586 [(set_attr "op_type" "SS,NN")
1587 (set_attr "type" "cs,cs")
1588 (set_attr "atype" "mem,mem")
1589 (set_attr "length" "*,14")])
1590
1591 ; Move a block of arbitrary length.
1592
1593 (define_insn "movstr_long_64"
1594 [(set (match_operand:TI 0 "register_operand" "=d")
1595 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1596 (lshiftrt:TI (match_dup 2) (const_int 64)))
1597 (const_int 64)))
1598 (set (match_operand:TI 1 "register_operand" "=d")
1599 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1600 (lshiftrt:TI (match_dup 3) (const_int 64)))
1601 (const_int 64)))
1602 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1603 (mem:BLK (subreg:DI (match_dup 3) 0)))
1604 (clobber (reg:CC 33))]
1605 "TARGET_64BIT"
1606 "mvcle\\t%0,%1,0\;jo\\t.-4"
1607 [(set_attr "op_type" "NN")
1608 (set_attr "type" "vs")
1609 (set_attr "atype" "mem")
1610 (set_attr "length" "8")])
1611
1612 (define_insn "movstr_long_31"
1613 [(set (match_operand:DI 0 "register_operand" "=d")
1614 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1615 (lshiftrt:DI (match_dup 2) (const_int 32)))
1616 (const_int 32)))
1617 (set (match_operand:DI 1 "register_operand" "=d")
1618 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1619 (lshiftrt:DI (match_dup 3) (const_int 32)))
1620 (const_int 32)))
1621 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1622 (mem:BLK (subreg:SI (match_dup 3) 0)))
1623 (clobber (reg:CC 33))]
1624 "!TARGET_64BIT"
1625 "mvcle\\t%0,%1,0\;jo\\t.-4"
1626 [(set_attr "op_type" "NN")
1627 (set_attr "type" "vs")
1628 (set_attr "atype" "mem")
1629 (set_attr "length" "8")])
1630
1631 ;
1632 ; clrstrM instruction pattern(s).
1633 ;
1634
1635 (define_expand "clrstrdi"
1636 [(set (match_operand:BLK 0 "memory_operand" "")
1637 (const_int 0))
1638 (use (match_operand:DI 1 "general_operand" ""))
1639 (match_operand 2 "" "")]
1640 "TARGET_64BIT"
1641 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1642
1643 (define_expand "clrstrsi"
1644 [(set (match_operand:BLK 0 "memory_operand" "")
1645 (const_int 0))
1646 (use (match_operand:SI 1 "general_operand" ""))
1647 (match_operand 2 "" "")]
1648 ""
1649 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1650
1651 ; Clear a block that is up to 256 bytes in length.
1652 ; The block length is taken as (operands[2] % 256) + 1.
1653
1654 (define_insn "clrstr_short_64"
1655 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1656 (const_int 0))
1657 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1658 (clobber (match_scratch:DI 2 "=X,&a"))
1659 (clobber (reg:CC 33))]
1660 "TARGET_64BIT"
1661 "*
1662 {
1663 switch (which_alternative)
1664 {
1665 case 0:
1666 return \"xc\\t%O0(%b1+1,%R0),%0\";
1667
1668 case 1:
1669 output_asm_insn (\"bras\\t%2,.+10\", operands);
1670 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1671 return \"ex\\t%1,0(%2)\";
1672
1673 default:
1674 abort ();
1675 }
1676 }"
1677 [(set_attr "op_type" "SS,NN")
1678 (set_attr "type" "cs,cs")
1679 (set_attr "atype" "mem,mem")
1680 (set_attr "length" "*,14")])
1681
1682 (define_insn "clrstr_short_31"
1683 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1684 (const_int 0))
1685 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1686 (clobber (match_scratch:SI 2 "=X,&a"))
1687 (clobber (reg:CC 33))]
1688 "!TARGET_64BIT"
1689 "*
1690 {
1691 switch (which_alternative)
1692 {
1693 case 0:
1694 return \"xc\\t%O0(%b1+1,%R0),%0\";
1695
1696 case 1:
1697 output_asm_insn (\"bras\\t%2,.+10\", operands);
1698 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1699 return \"ex\\t%1,0(%2)\";
1700
1701 default:
1702 abort ();
1703 }
1704 }"
1705 [(set_attr "op_type" "SS,NN")
1706 (set_attr "type" "cs,cs")
1707 (set_attr "atype" "mem,mem")
1708 (set_attr "length" "*,14")])
1709
1710 ; Clear a block of arbitrary length.
1711
1712 (define_insn "clrstr_long_64"
1713 [(set (match_operand:TI 0 "register_operand" "=d")
1714 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1715 (lshiftrt:TI (match_dup 2) (const_int 64)))
1716 (const_int 64)))
1717 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1718 (const_int 0))
1719 (use (match_operand:TI 1 "register_operand" "d"))
1720 (clobber (reg:CC 33))]
1721 "TARGET_64BIT"
1722 "mvcle\\t%0,%1,0\;jo\\t.-4"
1723 [(set_attr "op_type" "NN")
1724 (set_attr "atype" "mem")
1725 (set_attr "type" "vs")
1726 (set_attr "length" "8")])
1727
1728 (define_insn "clrstr_long_31"
1729 [(set (match_operand:DI 0 "register_operand" "=d")
1730 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1731 (lshiftrt:DI (match_dup 2) (const_int 32)))
1732 (const_int 32)))
1733 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1734 (const_int 0))
1735 (use (match_operand:DI 1 "register_operand" "d"))
1736 (clobber (reg:CC 33))]
1737 "!TARGET_64BIT"
1738 "mvcle\\t%0,%1,0\;jo\\t.-4"
1739 [(set_attr "op_type" "NN")
1740 (set_attr "atype" "mem")
1741 (set_attr "type" "vs")
1742 (set_attr "length" "8")])
1743
1744 ;
1745 ; cmpstrM instruction pattern(s).
1746 ;
1747
1748 (define_expand "cmpstrdi"
1749 [(set (match_operand:DI 0 "register_operand" "")
1750 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1751 (match_operand:BLK 2 "memory_operand" "") ) )
1752 (use (match_operand:DI 3 "general_operand" ""))
1753 (use (match_operand:DI 4 "" ""))]
1754 "TARGET_64BIT"
1755 "s390_expand_cmpstr (operands[0], operands[1],
1756 operands[2], operands[3]); DONE;")
1757
1758 (define_expand "cmpstrsi"
1759 [(set (match_operand:SI 0 "register_operand" "")
1760 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1761 (match_operand:BLK 2 "memory_operand" "") ) )
1762 (use (match_operand:SI 3 "general_operand" ""))
1763 (use (match_operand:SI 4 "" ""))]
1764 ""
1765 "s390_expand_cmpstr (operands[0], operands[1],
1766 operands[2], operands[3]); DONE;")
1767
1768 ; Compare a block that is up to 256 bytes in length.
1769 ; The block length is taken as (operands[2] % 256) + 1.
1770
1771 (define_insn "cmpstr_short_64"
1772 [(set (reg:CCS 33)
1773 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1774 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1775 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1776 (clobber (match_scratch:DI 3 "=X,&a"))]
1777 "TARGET_64BIT"
1778 "*
1779 {
1780 switch (which_alternative)
1781 {
1782 case 0:
1783 return \"clc\\t%O0(%b2+1,%R0),%1\";
1784
1785 case 1:
1786 output_asm_insn (\"bras\\t%3,.+10\", operands);
1787 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1788 return \"ex\\t%2,0(%3)\";
1789
1790 default:
1791 abort ();
1792 }
1793 }"
1794 [(set_attr "op_type" "SS,NN")
1795 (set_attr "type" "cs,cs")
1796 (set_attr "atype" "mem,mem")
1797 (set_attr "length" "*,14")])
1798
1799 (define_insn "cmpstr_short_31"
1800 [(set (reg:CCS 33)
1801 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1802 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1803 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1804 (clobber (match_scratch:SI 3 "=X,&a"))]
1805 "!TARGET_64BIT"
1806 "*
1807 {
1808 switch (which_alternative)
1809 {
1810 case 0:
1811 return \"clc\\t%O0(%b2+1,%R0),%1\";
1812
1813 case 1:
1814 output_asm_insn (\"bras\\t%3,.+10\", operands);
1815 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1816 return \"ex\\t%2,0(%3)\";
1817
1818 default:
1819 abort ();
1820 }
1821 }"
1822 [(set_attr "op_type" "SS,NN")
1823 (set_attr "type" "cs,cs")
1824 (set_attr "atype" "mem,mem")
1825 (set_attr "length" "*,14")])
1826
1827 ; Compare a block of arbitrary length.
1828
1829 (define_insn "cmpstr_long_64"
1830 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1831 (clobber (match_operand:TI 1 "register_operand" "=d"))
1832 (set (reg:CCS 33)
1833 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1834 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1835 (use (match_dup 2))
1836 (use (match_dup 3))]
1837 "TARGET_64BIT"
1838 "clcl\\t%0,%1"
1839 [(set_attr "op_type" "RR")
1840 (set_attr "atype" "mem")
1841 (set_attr "type" "vs")])
1842
1843 (define_insn "cmpstr_long_31"
1844 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1845 (clobber (match_operand:DI 1 "register_operand" "=d"))
1846 (set (reg:CCS 33)
1847 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1848 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1849 (use (match_dup 2))
1850 (use (match_dup 3))]
1851 "!TARGET_64BIT"
1852 "clcl\\t%0,%1"
1853 [(set_attr "op_type" "RR")
1854 (set_attr "atype" "mem")
1855 (set_attr "type" "vs")])
1856
1857 ; Convert condition code to integer in range (-1, 0, 1)
1858
1859 (define_insn "cmpint_si"
1860 [(set (match_operand:SI 0 "register_operand" "=d")
1861 (compare:SI (reg:CCS 33) (const_int 0)))]
1862 ""
1863 "*
1864 {
1865 output_asm_insn (\"lhi\\t%0,1\", operands);
1866 output_asm_insn (\"jh\\t.+12\", operands);
1867 output_asm_insn (\"jl\\t.+6\", operands);
1868 output_asm_insn (\"sr\\t%0,%0\", operands);
1869 return \"lcr\\t%0,%0\";
1870 }"
1871 [(set_attr "op_type" "NN")
1872 (set_attr "length" "16")
1873 (set_attr "atype" "reg")
1874 (set_attr "type" "other")])
1875
1876 (define_insn "cmpint_di"
1877 [(set (match_operand:DI 0 "register_operand" "=d")
1878 (compare:DI (reg:CCS 33) (const_int 0)))]
1879 "TARGET_64BIT"
1880 "*
1881 {
1882 output_asm_insn (\"lghi\\t%0,1\", operands);
1883 output_asm_insn (\"jh\\t.+12\", operands);
1884 output_asm_insn (\"jl\\t.+6\", operands);
1885 output_asm_insn (\"sgr\\t%0,%0\", operands);
1886 return \"lcgr\\t%0,%0\";
1887 }"
1888 [(set_attr "op_type" "NN")
1889 (set_attr "length" "22")
1890 (set_attr "atype" "reg")
1891 (set_attr "type" "other")])
1892
1893
1894 ;;
1895 ;;- Conversion instructions.
1896 ;;
1897
1898 (define_insn "*sethighqisi"
1899 [(set (match_operand:SI 0 "register_operand" "=d")
1900 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
1901 (clobber (reg:CC 33))]
1902 ""
1903 "icm\\t%0,8,%1"
1904 [(set_attr "op_type" "RS")
1905 (set_attr "atype" "mem")])
1906
1907 (define_insn "*sethighhisi"
1908 [(set (match_operand:SI 0 "register_operand" "=d")
1909 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
1910 (clobber (reg:CC 33))]
1911 ""
1912 "icm\\t%0,12,%1"
1913 [(set_attr "op_type" "RS")
1914 (set_attr "atype" "mem")])
1915
1916 (define_insn "*sethighqidi_64"
1917 [(set (match_operand:DI 0 "register_operand" "=d")
1918 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1919 (clobber (reg:CC 33))]
1920 "TARGET_64BIT"
1921 "icmh\\t%0,8,%1"
1922 [(set_attr "op_type" "RSE")
1923 (set_attr "atype" "mem")])
1924
1925 (define_insn "*sethighqidi_31"
1926 [(set (match_operand:DI 0 "register_operand" "=d")
1927 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1928 (clobber (reg:CC 33))]
1929 "!TARGET_64BIT"
1930 "icm\\t%0,8,%1"
1931 [(set_attr "op_type" "RS")
1932 (set_attr "atype" "mem")])
1933
1934 (define_split
1935 [(set (match_operand:SI 0 "register_operand" "")
1936 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
1937 (match_operand 2 "const_int_operand" "")
1938 (const_int 0)))]
1939 "!TARGET_64BIT && !reload_completed
1940 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
1941 [(parallel
1942 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1943 (clobber (reg:CC 33))])
1944 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1945 "
1946 {
1947 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1948 operands[1] = change_address (operands[1], QImode, 0);
1949 }")
1950
1951 (define_split
1952 [(set (match_operand:SI 0 "register_operand" "")
1953 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
1954 (match_operand 2 "const_int_operand" "")
1955 (const_int 0)))]
1956 "!TARGET_64BIT && !reload_completed
1957 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
1958 [(parallel
1959 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1960 (clobber (reg:CC 33))])
1961 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1962 "
1963 {
1964 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1965 operands[1] = change_address (operands[1], HImode, 0);
1966 }")
1967
1968 ;
1969 ; extendsidi2 instruction pattern(s).
1970 ;
1971
1972 (define_expand "extendsidi2"
1973 [(set (match_operand:DI 0 "register_operand" "")
1974 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
1975 ""
1976 "
1977 {
1978 if (!TARGET_64BIT)
1979 {
1980 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
1981 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
1982 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
1983 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
1984 DONE;
1985 }
1986 }
1987 ")
1988
1989 (define_insn "*extendsidi2"
1990 [(set (match_operand:DI 0 "register_operand" "=d,d")
1991 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
1992 "TARGET_64BIT"
1993 "@
1994 lgfr\\t%0,%1
1995 lgf\\t%0,%1"
1996 [(set_attr "op_type" "RRE,RXE")
1997 (set_attr "atype" "reg,mem")])
1998
1999 ;
2000 ; extendhidi2 instruction pattern(s).
2001 ;
2002
2003 (define_expand "extendhidi2"
2004 [(set (match_operand:DI 0 "register_operand" "")
2005 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2006 ""
2007 "
2008 {
2009 if (!TARGET_64BIT)
2010 {
2011 rtx tmp = gen_reg_rtx (SImode);
2012 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2013 emit_insn (gen_extendsidi2 (operands[0], tmp));
2014 DONE;
2015 }
2016 else
2017 {
2018 operands[1] = gen_lowpart (DImode, operands[1]);
2019 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2020 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2021 DONE;
2022 }
2023 }
2024 ")
2025
2026 (define_insn "*extendhidi2"
2027 [(set (match_operand:DI 0 "register_operand" "=d")
2028 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2029 "TARGET_64BIT"
2030 "lgh\\t%0,%1"
2031 [(set_attr "op_type" "RXE")
2032 (set_attr "atype" "mem")])
2033
2034 ;
2035 ; extendqidi2 instruction pattern(s).
2036 ;
2037
2038 (define_expand "extendqidi2"
2039 [(set (match_operand:DI 0 "register_operand" "")
2040 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2041 ""
2042 "
2043 {
2044 if (!TARGET_64BIT)
2045 {
2046 rtx tmp = gen_reg_rtx (SImode);
2047 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2048 emit_insn (gen_extendsidi2 (operands[0], tmp));
2049 DONE;
2050 }
2051 else
2052 {
2053 operands[1] = gen_lowpart (DImode, operands[1]);
2054 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2055 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2056 DONE;
2057 }
2058 }
2059 ")
2060
2061 (define_split
2062 [(set (match_operand:DI 0 "register_operand" "")
2063 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2064 "TARGET_64BIT && !reload_completed"
2065 [(parallel
2066 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2067 (clobber (reg:CC 33))])
2068 (parallel
2069 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2070 (clobber (reg:CC 33))])]
2071 "")
2072
2073 ;
2074 ; extendhisi2 instruction pattern(s).
2075 ;
2076
2077 (define_expand "extendhisi2"
2078 [(set (match_operand:SI 0 "register_operand" "")
2079 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2080 ""
2081 "
2082 {
2083 operands[1] = gen_lowpart (SImode, operands[1]);
2084 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2085 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2086 DONE;
2087 }
2088 ")
2089
2090 (define_insn "*extendhisi2"
2091 [(set (match_operand:SI 0 "register_operand" "=d")
2092 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2093 ""
2094 "lh\\t%0,%1"
2095 [(set_attr "op_type" "RX")
2096 (set_attr "atype" "mem")])
2097
2098 ;
2099 ; extendqisi2 instruction pattern(s).
2100 ;
2101
2102 (define_expand "extendqisi2"
2103 [(set (match_operand:SI 0 "register_operand" "")
2104 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2105 ""
2106 "
2107 {
2108 operands[1] = gen_lowpart (SImode, operands[1]);
2109 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2110 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2111 DONE;
2112 }
2113 ")
2114
2115 (define_split
2116 [(set (match_operand:SI 0 "register_operand" "")
2117 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2118 "!reload_completed"
2119 [(parallel
2120 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2121 (clobber (reg:CC 33))])
2122 (parallel
2123 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2124 (clobber (reg:CC 33))])]
2125 "")
2126
2127 ;
2128 ; extendqihi2 instruction pattern(s).
2129 ;
2130
2131
2132 ;
2133 ; zero_extendsidi2 instruction pattern(s).
2134 ;
2135
2136 (define_expand "zero_extendsidi2"
2137 [(set (match_operand:DI 0 "register_operand" "")
2138 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2139 ""
2140 "
2141 {
2142 if (!TARGET_64BIT)
2143 {
2144 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2145 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2146 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2147 DONE;
2148 }
2149 }
2150 ")
2151
2152 (define_insn "*zero_extendsidi2"
2153 [(set (match_operand:DI 0 "register_operand" "=d,d")
2154 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2155 "TARGET_64BIT"
2156 "@
2157 llgfr\\t%0,%1
2158 llgf\\t%0,%1"
2159 [(set_attr "op_type" "RRE,RXE")
2160 (set_attr "atype" "reg,mem")])
2161
2162 ;
2163 ; zero_extendhidi2 instruction pattern(s).
2164 ;
2165
2166 (define_expand "zero_extendhidi2"
2167 [(set (match_operand:DI 0 "register_operand" "")
2168 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2169 ""
2170 "
2171 {
2172 if (!TARGET_64BIT)
2173 {
2174 rtx tmp = gen_reg_rtx (SImode);
2175 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2176 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2177 DONE;
2178 }
2179 else
2180 {
2181 operands[1] = gen_lowpart (DImode, operands[1]);
2182 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2183 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2184 DONE;
2185 }
2186 }
2187 ")
2188
2189 (define_insn "*zero_extendhidi2"
2190 [(set (match_operand:DI 0 "register_operand" "=d")
2191 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2192 "TARGET_64BIT"
2193 "llgh\\t%0,%1"
2194 [(set_attr "op_type" "RXE")
2195 (set_attr "atype" "mem")])
2196
2197 ;
2198 ; zero_extendqidi2 instruction pattern(s)
2199 ;
2200
2201 (define_expand "zero_extendqidi2"
2202 [(set (match_operand:DI 0 "register_operand" "")
2203 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2204 ""
2205 "
2206 {
2207 if (!TARGET_64BIT)
2208 {
2209 rtx tmp = gen_reg_rtx (SImode);
2210 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2211 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2212 DONE;
2213 }
2214 else
2215 {
2216 operands[1] = gen_lowpart (DImode, operands[1]);
2217 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2218 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2219 DONE;
2220 }
2221 }
2222 ")
2223
2224 (define_insn "*zero_extendqidi2"
2225 [(set (match_operand:DI 0 "register_operand" "=d")
2226 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2227 "TARGET_64BIT"
2228 "llgc\\t%0,%1"
2229 [(set_attr "op_type" "RXE")
2230 (set_attr "atype" "mem")])
2231
2232 ;
2233 ; zero_extendhisi2 instruction pattern(s).
2234 ;
2235
2236 (define_expand "zero_extendhisi2"
2237 [(set (match_operand:SI 0 "register_operand" "")
2238 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2239 ""
2240 "
2241 {
2242 operands[1] = gen_lowpart (SImode, operands[1]);
2243 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2244 DONE;
2245 }
2246 ")
2247
2248 (define_insn "*zero_extendhisi2_64"
2249 [(set (match_operand:SI 0 "register_operand" "=d")
2250 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2251 "TARGET_64BIT"
2252 "llgh\\t%0,%1"
2253 [(set_attr "op_type" "RXE")
2254 (set_attr "atype" "mem")])
2255
2256 ;
2257 ; zero_extendqisi2 instruction pattern(s).
2258 ;
2259
2260 (define_expand "zero_extendqisi2"
2261 [(set (match_operand:SI 0 "register_operand" "")
2262 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2263 ""
2264 "
2265 {
2266 operands[1] = gen_lowpart (SImode, operands[1]);
2267 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2268 DONE;
2269 }
2270 ")
2271
2272 (define_insn "*zero_extendqisi2_64"
2273 [(set (match_operand:SI 0 "register_operand" "=d")
2274 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2275 "TARGET_64BIT"
2276 "llgc\\t%0,%1"
2277 [(set_attr "op_type" "RXE")
2278 (set_attr "atype" "mem")])
2279
2280 ;
2281 ; zero_extendqihi2 instruction pattern(s).
2282 ;
2283
2284 (define_expand "zero_extendqihi2"
2285 [(set (match_operand:HI 0 "register_operand" "")
2286 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2287 "TARGET_64BIT"
2288 "
2289 {
2290 operands[1] = gen_lowpart (HImode, operands[1]);
2291 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2292 DONE;
2293 }
2294 ")
2295
2296 (define_insn "*zero_extendqihi2_64"
2297 [(set (match_operand:HI 0 "register_operand" "=d")
2298 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2299 (clobber (reg:CC 33))]
2300 "TARGET_64BIT"
2301 "llgc\\t%0,%1"
2302 [(set_attr "op_type" "RXE")
2303 (set_attr "atype" "mem")])
2304
2305 ;
2306 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2307 ;
2308
2309 (define_expand "fixuns_truncdfdi2"
2310 [(set (match_operand:DI 0 "register_operand" "")
2311 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2312 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2313 "
2314 {
2315 rtx label1 = gen_label_rtx ();
2316 rtx label2 = gen_label_rtx ();
2317 rtx temp = gen_reg_rtx (DFmode);
2318 operands[1] = force_reg (DFmode, operands[1]);
2319
2320 emit_insn (gen_cmpdf (operands[1],
2321 CONST_DOUBLE_FROM_REAL_VALUE (
2322 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2323 emit_jump_insn (gen_blt (label1));
2324 emit_insn (gen_subdf3 (temp, operands[1],
2325 CONST_DOUBLE_FROM_REAL_VALUE (
2326 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2327 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2328 emit_jump (label2);
2329
2330 emit_label (label1);
2331 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2332 emit_label (label2);
2333 DONE;
2334 }")
2335
2336 (define_expand "fix_truncdfdi2"
2337 [(set (match_operand:DI 0 "register_operand" "")
2338 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2339 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2340 "
2341 {
2342 operands[1] = force_reg (DFmode, operands[1]);
2343 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2344 DONE;
2345 }")
2346
2347 (define_insn "fix_truncdfdi2_ieee"
2348 [(set (match_operand:DI 0 "register_operand" "=d")
2349 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2350 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2351 (clobber (reg:CC 33))]
2352 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2353 "cgdbr\\t%0,%h2,%1"
2354 [(set_attr "op_type" "RRE")
2355 (set_attr "type" "other")])
2356
2357 ;
2358 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2359 ;
2360
2361 (define_expand "fixuns_truncdfsi2"
2362 [(set (match_operand:SI 0 "register_operand" "")
2363 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2364 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2365 "
2366 {
2367 rtx label1 = gen_label_rtx ();
2368 rtx label2 = gen_label_rtx ();
2369 rtx temp = gen_reg_rtx (DFmode);
2370
2371 operands[1] = force_reg (DFmode,operands[1]);
2372 emit_insn (gen_cmpdf (operands[1],
2373 CONST_DOUBLE_FROM_REAL_VALUE (
2374 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2375 emit_jump_insn (gen_blt (label1));
2376 emit_insn (gen_subdf3 (temp, operands[1],
2377 CONST_DOUBLE_FROM_REAL_VALUE (
2378 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2379 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2380 emit_jump (label2);
2381
2382 emit_label (label1);
2383 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2384 emit_label (label2);
2385 DONE;
2386 }")
2387
2388 (define_expand "fix_truncdfsi2"
2389 [(set (match_operand:SI 0 "register_operand" "")
2390 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2391 "TARGET_HARD_FLOAT"
2392 "
2393 {
2394 if (TARGET_IBM_FLOAT)
2395 {
2396 /* This is the algorithm from POP chapter A.5.7.2. */
2397
2398 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2399 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2400 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2401
2402 operands[1] = force_reg (DFmode, operands[1]);
2403 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2404 two31r, two32, temp));
2405 }
2406 else
2407 {
2408 operands[1] = force_reg (DFmode, operands[1]);
2409 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2410 }
2411
2412 DONE;
2413 }")
2414
2415 (define_insn "fix_truncdfsi2_ieee"
2416 [(set (match_operand:SI 0 "register_operand" "=d")
2417 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2418 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2419 (clobber (reg:CC 33))]
2420 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2421 "cfdbr\\t%0,%h2,%1"
2422 [(set_attr "op_type" "RRE")
2423 (set_attr "type" "other" )])
2424
2425 (define_insn "fix_truncdfsi2_ibm"
2426 [(set (match_operand:SI 0 "register_operand" "=d")
2427 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2428 (use (match_operand:DI 2 "immediate_operand" "m"))
2429 (use (match_operand:DI 3 "immediate_operand" "m"))
2430 (use (match_operand:BLK 4 "memory_operand" "m"))
2431 (clobber (reg:CC 33))]
2432 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2433 "*
2434 {
2435 output_asm_insn (\"sd\\t%1,%2\", operands);
2436 output_asm_insn (\"aw\\t%1,%3\", operands);
2437 output_asm_insn (\"std\\t%1,%4\", operands);
2438 output_asm_insn (\"xi\\t%N4,128\", operands);
2439 return \"l\\t%0,%N4\";
2440 }"
2441 [(set_attr "op_type" "NN")
2442 (set_attr "type" "other")
2443 (set_attr "length" "20")])
2444
2445 ;
2446 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2447 ;
2448
2449 (define_expand "fixuns_truncsfdi2"
2450 [(set (match_operand:DI 0 "register_operand" "")
2451 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2452 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2453 "
2454 {
2455 rtx label1 = gen_label_rtx ();
2456 rtx label2 = gen_label_rtx ();
2457 rtx temp = gen_reg_rtx (SFmode);
2458
2459 operands[1] = force_reg (SFmode, operands[1]);
2460 emit_insn (gen_cmpsf (operands[1],
2461 CONST_DOUBLE_FROM_REAL_VALUE (
2462 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2463 emit_jump_insn (gen_blt (label1));
2464
2465 emit_insn (gen_subsf3 (temp, operands[1],
2466 CONST_DOUBLE_FROM_REAL_VALUE (
2467 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2468 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2469 emit_jump (label2);
2470
2471 emit_label (label1);
2472 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2473 emit_label (label2);
2474 DONE;
2475 }")
2476
2477 (define_expand "fix_truncsfdi2"
2478 [(set (match_operand:DI 0 "register_operand" "")
2479 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2480 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2481 "
2482 {
2483 operands[1] = force_reg (SFmode, operands[1]);
2484 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2485 DONE;
2486 }")
2487
2488 (define_insn "fix_truncsfdi2_ieee"
2489 [(set (match_operand:DI 0 "register_operand" "=d")
2490 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2491 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2492 (clobber (reg:CC 33))]
2493 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2494 "cgebr\\t%0,%h2,%1"
2495 [(set_attr "op_type" "RRE")
2496 (set_attr "type" "other")])
2497
2498 ;
2499 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2500 ;
2501
2502 (define_expand "fixuns_truncsfsi2"
2503 [(set (match_operand:SI 0 "register_operand" "")
2504 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2505 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2506 "
2507 {
2508 rtx label1 = gen_label_rtx ();
2509 rtx label2 = gen_label_rtx ();
2510 rtx temp = gen_reg_rtx (SFmode);
2511
2512 operands[1] = force_reg (SFmode, operands[1]);
2513 emit_insn (gen_cmpsf (operands[1],
2514 CONST_DOUBLE_FROM_REAL_VALUE (
2515 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2516 emit_jump_insn (gen_blt (label1));
2517 emit_insn (gen_subsf3 (temp, operands[1],
2518 CONST_DOUBLE_FROM_REAL_VALUE (
2519 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2520 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2521 emit_jump (label2);
2522
2523 emit_label (label1);
2524 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2525 emit_label (label2);
2526 DONE;
2527 }")
2528
2529 (define_expand "fix_truncsfsi2"
2530 [(set (match_operand:SI 0 "register_operand" "")
2531 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2532 "TARGET_HARD_FLOAT"
2533 "
2534 {
2535 if (TARGET_IBM_FLOAT)
2536 {
2537 /* Convert to DFmode and then use the POP algorithm. */
2538 rtx temp = gen_reg_rtx (DFmode);
2539 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2540 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2541 }
2542 else
2543 {
2544 operands[1] = force_reg (SFmode, operands[1]);
2545 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2546 }
2547
2548 DONE;
2549 }")
2550
2551 (define_insn "fix_truncsfsi2_ieee"
2552 [(set (match_operand:SI 0 "register_operand" "=d")
2553 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2554 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2555 (clobber (reg:CC 33))]
2556 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2557 "cfebr\\t%0,%h2,%1"
2558 [(set_attr "op_type" "RRE")
2559 (set_attr "type" "other")])
2560
2561 ;
2562 ; floatdidf2 instruction pattern(s).
2563 ;
2564
2565 (define_insn "floatdidf2"
2566 [(set (match_operand:DF 0 "register_operand" "=f")
2567 (float:DF (match_operand:DI 1 "register_operand" "d")))
2568 (clobber (reg:CC 33))]
2569 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2570 "cdgbr\\t%0,%1"
2571 [(set_attr "op_type" "RRE")
2572 (set_attr "type" "other" )])
2573
2574 ;
2575 ; floatdisf2 instruction pattern(s).
2576 ;
2577
2578 (define_insn "floatdisf2"
2579 [(set (match_operand:SF 0 "register_operand" "=f")
2580 (float:SF (match_operand:DI 1 "register_operand" "d")))
2581 (clobber (reg:CC 33))]
2582 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2583 "cegbr\\t%0,%1"
2584 [(set_attr "op_type" "RRE")
2585 (set_attr "type" "other" )])
2586
2587 ;
2588 ; floatsidf2 instruction pattern(s).
2589 ;
2590
2591 (define_expand "floatsidf2"
2592 [(parallel
2593 [(set (match_operand:DF 0 "register_operand" "")
2594 (float:DF (match_operand:SI 1 "register_operand" "")))
2595 (clobber (reg:CC 33))])]
2596 "TARGET_HARD_FLOAT"
2597 "
2598 {
2599 if (TARGET_IBM_FLOAT)
2600 {
2601 /* This is the algorithm from POP chapter A.5.7.1. */
2602
2603 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2604 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2605
2606 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2607 DONE;
2608 }
2609 }")
2610
2611 (define_insn "floatsidf2_ieee"
2612 [(set (match_operand:DF 0 "register_operand" "=f")
2613 (float:DF (match_operand:SI 1 "register_operand" "d")))
2614 (clobber (reg:CC 33))]
2615 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2616 "cdfbr\\t%0,%1"
2617 [(set_attr "op_type" "RRE")
2618 (set_attr "type" "other" )])
2619
2620 (define_insn "floatsidf2_ibm"
2621 [(set (match_operand:DF 0 "register_operand" "=f")
2622 (float:DF (match_operand:SI 1 "register_operand" "d")))
2623 (use (match_operand:DI 2 "immediate_operand" "m"))
2624 (use (match_operand:BLK 3 "memory_operand" "m"))
2625 (clobber (reg:CC 33))]
2626 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2627 "*
2628 {
2629 output_asm_insn (\"st\\t%1,%N3\", operands);
2630 output_asm_insn (\"xi\\t%N3,128\", operands);
2631 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2632 output_asm_insn (\"ld\\t%0,%3\", operands);
2633 return \"sd\\t%0,%2\";
2634 }"
2635 [(set_attr "op_type" "NN")
2636 (set_attr "type" "other" )
2637 (set_attr "length" "20")])
2638
2639 ;
2640 ; floatsisf2 instruction pattern(s).
2641 ;
2642
2643 (define_expand "floatsisf2"
2644 [(parallel
2645 [(set (match_operand:SF 0 "register_operand" "")
2646 (float:SF (match_operand:SI 1 "register_operand" "")))
2647 (clobber (reg:CC 33))])]
2648 "TARGET_HARD_FLOAT"
2649 "
2650 {
2651 if (TARGET_IBM_FLOAT)
2652 {
2653 /* Use the POP algorithm to convert to DFmode and then truncate. */
2654 rtx temp = gen_reg_rtx (DFmode);
2655 emit_insn (gen_floatsidf2 (temp, operands[1]));
2656 emit_insn (gen_truncdfsf2 (operands[0], temp));
2657 DONE;
2658 }
2659 }")
2660
2661 (define_insn "floatsisf2_ieee"
2662 [(set (match_operand:SF 0 "register_operand" "=f")
2663 (float:SF (match_operand:SI 1 "register_operand" "d")))
2664 (clobber (reg:CC 33))]
2665 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2666 "cefbr\\t%0,%1"
2667 [(set_attr "op_type" "RRE")
2668 (set_attr "type" "other" )])
2669
2670 ;
2671 ; truncdfsf2 instruction pattern(s).
2672 ;
2673
2674 (define_expand "truncdfsf2"
2675 [(set (match_operand:SF 0 "register_operand" "")
2676 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2677 "TARGET_HARD_FLOAT"
2678 "")
2679
2680 (define_insn "truncdfsf2_ieee"
2681 [(set (match_operand:SF 0 "register_operand" "=f")
2682 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2683 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2684 "ledbr\\t%0,%1"
2685 [(set_attr "op_type" "RRE")])
2686
2687 (define_insn "truncdfsf2_ibm"
2688 [(set (match_operand:SF 0 "register_operand" "=f,f")
2689 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2690 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2691 "@
2692 lrer\\t%0,%1
2693 le\\t%0,%1"
2694 [(set_attr "op_type" "RR,RX")
2695 (set_attr "atype" "reg,mem")])
2696
2697 ;
2698 ; extendsfdf2 instruction pattern(s).
2699 ;
2700
2701 (define_expand "extendsfdf2"
2702 [(set (match_operand:DF 0 "register_operand" "")
2703 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2704 "TARGET_HARD_FLOAT"
2705 "
2706 {
2707 if (TARGET_IBM_FLOAT)
2708 {
2709 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2710 DONE;
2711 }
2712 }")
2713
2714 (define_insn "extendsfdf2_ieee"
2715 [(set (match_operand:DF 0 "register_operand" "=f,f")
2716 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2717 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2718 "@
2719 ldebr\\t%0,%1
2720 ldeb\\t%0,%1"
2721 [(set_attr "op_type" "RRE,RXE")])
2722
2723 (define_insn "extendsfdf2_ibm"
2724 [(set (match_operand:DF 0 "register_operand" "=f,f")
2725 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2726 (clobber (reg:CC 33))]
2727 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2728 "@
2729 sdr\\t%0,%0\;ler\\t%0,%1
2730 sdr\\t%0,%0\;le\\t%0,%1"
2731 [(set_attr "op_type" "RRE,RXE")
2732 (set_attr "atype" "reg,mem")
2733 (set_attr "type" "o2,o2")])
2734
2735
2736 ;;
2737 ;; ARITHMETRIC OPERATIONS
2738 ;;
2739 ; arithmetric operations set the ConditionCode,
2740 ; because of unpredictable Bits in Register for Halfword and Byte
2741 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2742
2743 ;;
2744 ;;- Add instructions.
2745 ;;
2746
2747 ;
2748 ; adddi3 instruction pattern(s).
2749 ;
2750
2751 (define_insn "addaddr_esame"
2752 [(set (match_operand:DI 0 "register_operand" "=a,a")
2753 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
2754 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
2755 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
2756 (REGNO (operands[1]) == BASE_REGISTER)) &&
2757 (GET_CODE (operands[2]) == REG ||
2758 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
2759 "@
2760 la\\t%0,%c2(,%1)
2761 la\\t%0,0(%1,%2)"
2762 [(set_attr "op_type" "RX")
2763 (set_attr "atype" "mem")
2764 (set_attr "type" "la")])
2765
2766 (define_insn "*adddi3_sign"
2767 [(set (match_operand:DI 0 "register_operand" "=d,d")
2768 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2769 (match_operand:DI 1 "register_operand" "0,0")))
2770 (clobber (reg:CC 33))]
2771 "TARGET_64BIT"
2772 "@
2773 agfr\\t%0,%2
2774 agf\\t%0,%2"
2775 [(set_attr "op_type" "RRE,RXE")
2776 (set_attr "atype" "reg,mem")])
2777
2778 (define_insn "*adddi3_zero_cc"
2779 [(set (reg 33)
2780 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2781 (match_operand:DI 1 "register_operand" "0,0"))
2782 (const_int 0)))
2783 (set (match_operand:DI 0 "register_operand" "=d,d")
2784 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2785 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2786 "@
2787 algfr\\t%0,%2
2788 algf\\t%0,%2"
2789 [(set_attr "op_type" "RRE,RXE")
2790 (set_attr "atype" "reg,mem")])
2791
2792 (define_insn "*adddi3_zero_cconly"
2793 [(set (reg 33)
2794 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2795 (match_operand:DI 1 "register_operand" "0,0"))
2796 (const_int 0)))
2797 (clobber (match_scratch:DI 0 "=d,d"))]
2798 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2799 "@
2800 algfr\\t%0,%2
2801 algf\\t%0,%2"
2802 [(set_attr "op_type" "RRE,RXE")
2803 (set_attr "atype" "reg,mem")])
2804
2805 (define_insn "*adddi3_zero"
2806 [(set (match_operand:DI 0 "register_operand" "=d,d")
2807 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2808 (match_operand:DI 1 "register_operand" "0,0")))
2809 (clobber (reg:CC 33))]
2810 "TARGET_64BIT"
2811 "@
2812 algfr\\t%0,%2
2813 algf\\t%0,%2"
2814 [(set_attr "op_type" "RRE,RXE")
2815 (set_attr "atype" "reg,mem")])
2816
2817 (define_insn "*adddi3_imm_cc"
2818 [(set (reg 33)
2819 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2820 (match_operand:DI 2 "const_int_operand" "K"))
2821 (const_int 0)))
2822 (set (match_operand:DI 0 "register_operand" "=d")
2823 (plus:DI (match_dup 1) (match_dup 2)))]
2824 "TARGET_64BIT
2825 && s390_match_ccmode (insn, CCAmode)
2826 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2827 "aghi\\t%0,%h2"
2828 [(set_attr "op_type" "RI")
2829 (set_attr "atype" "reg")])
2830
2831 (define_insn "*adddi3_cc"
2832 [(set (reg 33)
2833 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2834 (match_operand:DI 2 "general_operand" "d,m"))
2835 (const_int 0)))
2836 (set (match_operand:DI 0 "register_operand" "=d,d")
2837 (plus:DI (match_dup 1) (match_dup 2)))]
2838 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2839 "@
2840 algr\\t%0,%2
2841 alg\\t%0,%2"
2842 [(set_attr "op_type" "RRE,RXE")
2843 (set_attr "atype" "reg,mem")])
2844
2845 (define_insn "*adddi3_cconly"
2846 [(set (reg 33)
2847 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2848 (match_operand:DI 2 "general_operand" "d,m"))
2849 (const_int 0)))
2850 (clobber (match_scratch:DI 0 "=d,d"))]
2851 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2852 "@
2853 algr\\t%0,%2
2854 alg\\t%0,%2"
2855 [(set_attr "op_type" "RRE,RXE")
2856 (set_attr "atype" "reg,mem")])
2857
2858 (define_insn "*adddi3_cconly2"
2859 [(set (reg 33)
2860 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2861 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
2862 (clobber (match_scratch:DI 0 "=d,d"))]
2863 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
2864 "@
2865 algr\\t%0,%2
2866 alg\\t%0,%2"
2867 [(set_attr "op_type" "RRE,RXE")
2868 (set_attr "atype" "reg,mem")])
2869
2870 (define_insn "*adddi3_64"
2871 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2872 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
2873 (match_operand:DI 2 "general_operand" "d,K,m") ) )
2874 (clobber (reg:CC 33))]
2875 "TARGET_64BIT"
2876 "@
2877 agr\\t%0,%2
2878 aghi\\t%0,%h2
2879 ag\\t%0,%2"
2880 [(set_attr "op_type" "RRE,RI,RXE")
2881 (set_attr "atype" "reg,reg,mem")])
2882
2883 (define_insn_and_split "*adddi3_31"
2884 [(set (match_operand:DI 0 "register_operand" "=&d")
2885 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
2886 (match_operand:DI 2 "general_operand" "dm") ) )
2887 (clobber (reg:CC 33))]
2888 "!TARGET_64BIT"
2889 "#"
2890 "&& reload_completed"
2891 [(parallel
2892 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
2893 (clobber (reg:CC 33))])
2894 (parallel
2895 [(set (reg:CCL1 33)
2896 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
2897 (match_dup 7)))
2898 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
2899 (set (pc)
2900 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
2901 (pc)
2902 (label_ref (match_dup 9))))
2903 (parallel
2904 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
2905 (clobber (reg:CC 33))])
2906 (match_dup 9)]
2907 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
2908 operands[4] = operand_subword (operands[1], 0, 1, DImode);
2909 operands[5] = operand_subword (operands[2], 0, 1, DImode);
2910 operands[6] = operand_subword (operands[0], 1, 1, DImode);
2911 operands[7] = operand_subword (operands[1], 1, 1, DImode);
2912 operands[8] = operand_subword (operands[2], 1, 1, DImode);
2913 operands[9] = gen_label_rtx ();"
2914 [(set_attr "op_type" "NN")
2915 (set_attr "type" "o3")])
2916
2917 (define_expand "adddi3"
2918 [(parallel
2919 [(set (match_operand:DI 0 "register_operand" "")
2920 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
2921 (match_operand:DI 2 "general_operand" "")))
2922 (clobber (reg:CC 33))])]
2923 ""
2924 "")
2925
2926 (define_insn "*la_64"
2927 [(set (match_operand:DI 0 "register_operand" "=d")
2928 (match_operand:QI 1 "address_operand" "p"))]
2929 "TARGET_64BIT"
2930 "la\\t%0,%a1"
2931 [(set_attr "op_type" "RX")
2932 (set_attr "atype" "mem")
2933 (set_attr "type" "la")])
2934
2935 (define_expand "reload_indi"
2936 [(parallel [(match_operand:DI 0 "register_operand" "=a")
2937 (match_operand:DI 1 "s390_plus_operand" "")
2938 (match_operand:DI 2 "register_operand" "=&a")])]
2939 "TARGET_64BIT"
2940 "
2941 {
2942 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
2943 DONE;
2944 }")
2945
2946
2947 ;
2948 ; addsi3 instruction pattern(s).
2949 ;
2950
2951 (define_insn "*la_ccclobber"
2952 [(set (match_operand:SI 0 "register_operand" "=d")
2953 (match_operand:QI 1 "address_operand" "p"))
2954 (clobber (reg:CC 33))]
2955 "legitimate_la_operand_p (operands[1])"
2956 "la\\t%0,%a1"
2957 [(set_attr "op_type" "RX")
2958 (set_attr "atype" "mem")
2959 (set_attr "type" "la")])
2960
2961 (define_insn "*addsi3_imm_cc"
2962 [(set (reg 33)
2963 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
2964 (match_operand:SI 2 "const_int_operand" "K"))
2965 (const_int 0)))
2966 (set (match_operand:SI 0 "register_operand" "=d")
2967 (plus:SI (match_dup 1) (match_dup 2)))]
2968 "s390_match_ccmode (insn, CCAmode)
2969 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2970 "ahi\\t%0,%h2"
2971 [(set_attr "op_type" "RI")
2972 (set_attr "atype" "reg")])
2973
2974 (define_insn "*addsi3_carry1_cc"
2975 [(set (reg 33)
2976 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
2977 (match_operand:SI 2 "general_operand" "d,m"))
2978 (match_dup 1)))
2979 (set (match_operand:SI 0 "register_operand" "=d,d")
2980 (plus:SI (match_dup 1) (match_dup 2)))]
2981 "s390_match_ccmode (insn, CCL1mode)"
2982 "@
2983 alr\\t%0,%2
2984 al\\t%0,%2"
2985 [(set_attr "op_type" "RR,RX")
2986 (set_attr "atype" "reg,mem")])
2987
2988 (define_insn "*addsi3_carry1_cconly"
2989 [(set (reg 33)
2990 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
2991 (match_operand:SI 2 "general_operand" "d,m"))
2992 (match_dup 1)))
2993 (clobber (match_scratch:SI 0 "=d,d"))]
2994 "s390_match_ccmode (insn, CCL1mode)"
2995 "@
2996 alr\\t%0,%2
2997 al\\t%0,%2"
2998 [(set_attr "op_type" "RR,RX")
2999 (set_attr "atype" "reg,mem")])
3000
3001 (define_insn "*addsi3_carry2_cc"
3002 [(set (reg 33)
3003 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3004 (match_operand:SI 2 "general_operand" "d,m"))
3005 (match_dup 2)))
3006 (set (match_operand:SI 0 "register_operand" "=d,d")
3007 (plus:SI (match_dup 1) (match_dup 2)))]
3008 "s390_match_ccmode (insn, CCL1mode)"
3009 "@
3010 alr\\t%0,%2
3011 al\\t%0,%2"
3012 [(set_attr "op_type" "RR,RX")
3013 (set_attr "atype" "reg,mem")])
3014
3015 (define_insn "*addsi3_carry2_cconly"
3016 [(set (reg 33)
3017 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3018 (match_operand:SI 2 "general_operand" "d,m"))
3019 (match_dup 2)))
3020 (clobber (match_scratch:SI 0 "=d,d"))]
3021 "s390_match_ccmode (insn, CCL1mode)"
3022 "@
3023 alr\\t%0,%2
3024 al\\t%0,%2"
3025 [(set_attr "op_type" "RR,RX")
3026 (set_attr "atype" "reg,mem")])
3027
3028 (define_insn "*addsi3_cc"
3029 [(set (reg 33)
3030 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3031 (match_operand:SI 2 "general_operand" "d,m"))
3032 (const_int 0)))
3033 (set (match_operand:SI 0 "register_operand" "=d,d")
3034 (plus:SI (match_dup 1) (match_dup 2)))]
3035 "s390_match_ccmode (insn, CCLmode)"
3036 "@
3037 alr\\t%0,%2
3038 al\\t%0,%2"
3039 [(set_attr "op_type" "RR,RX")
3040 (set_attr "atype" "reg,mem")])
3041
3042 (define_insn "*addsi3_cconly"
3043 [(set (reg 33)
3044 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3045 (match_operand:SI 2 "general_operand" "d,m"))
3046 (const_int 0)))
3047 (clobber (match_scratch:SI 0 "=d,d"))]
3048 "s390_match_ccmode (insn, CCLmode)"
3049 "@
3050 alr\\t%0,%2
3051 al\\t%0,%2"
3052 [(set_attr "op_type" "RR,RX")
3053 (set_attr "atype" "reg,mem")])
3054
3055 (define_insn "*addsi3_cconly2"
3056 [(set (reg 33)
3057 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3058 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3059 (clobber (match_scratch:SI 0 "=d,d"))]
3060 "s390_match_ccmode(insn, CCLmode)"
3061 "@
3062 alr\\t%0,%2
3063 al\\t%0,%2"
3064 [(set_attr "op_type" "RR,RX")
3065 (set_attr "atype" "reg,mem")])
3066
3067 (define_insn "*addsi3_sign"
3068 [(set (match_operand:SI 0 "register_operand" "=d")
3069 (plus:SI (match_operand:SI 1 "register_operand" "0")
3070 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3071 (clobber (reg:CC 33))]
3072 ""
3073 "ah\\t%0,%2"
3074 [(set_attr "op_type" "RX")
3075 (set_attr "atype" "mem")])
3076
3077 (define_insn "*addsi3_sub"
3078 [(set (match_operand:SI 0 "register_operand" "=d")
3079 (plus:SI (match_operand:SI 1 "register_operand" "0")
3080 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3081 (clobber (reg:CC 33))]
3082 ""
3083 "ah\\t%0,%2"
3084 [(set_attr "op_type" "RX")
3085 (set_attr "atype" "mem")])
3086
3087 (define_insn "addsi3"
3088 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3089 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3090 (match_operand:SI 2 "general_operand" "d,K,m")))
3091 (clobber (reg:CC 33))]
3092 ""
3093 "@
3094 ar\\t%0,%2
3095 ahi\\t%0,%h2
3096 a\\t%0,%2"
3097 [(set_attr "op_type" "RR,RI,RX")
3098 (set_attr "atype" "reg,reg,mem")])
3099
3100 (define_insn "*la_31"
3101 [(set (match_operand:SI 0 "register_operand" "=d")
3102 (match_operand:QI 1 "address_operand" "p"))]
3103 "legitimate_la_operand_p (operands[1])"
3104 "la\\t%0,%a1"
3105 [(set_attr "op_type" "RX")
3106 (set_attr "atype" "mem")
3107 (set_attr "type" "la")])
3108
3109 (define_insn "force_la_31"
3110 [(set (match_operand:SI 0 "register_operand" "=d")
3111 (match_operand:QI 1 "address_operand" "p"))
3112 (use (const_int 0))]
3113 "!TARGET_64BIT"
3114 "la\\t%0,%a1"
3115 [(set_attr "op_type" "RX")
3116 (set_attr "atype" "mem")
3117 (set_attr "type" "la")])
3118
3119 (define_expand "reload_insi"
3120 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3121 (match_operand:SI 1 "s390_plus_operand" "")
3122 (match_operand:SI 2 "register_operand" "=&a")])]
3123 "!TARGET_64BIT"
3124 "
3125 {
3126 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3127 DONE;
3128 }")
3129
3130
3131 ;
3132 ; adddf3 instruction pattern(s).
3133 ;
3134
3135 (define_expand "adddf3"
3136 [(parallel
3137 [(set (match_operand:DF 0 "register_operand" "=f,f")
3138 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3139 (match_operand:DF 2 "general_operand" "f,m")))
3140 (clobber (reg:CC 33))])]
3141 "TARGET_HARD_FLOAT"
3142 "")
3143
3144 (define_insn "*adddf3"
3145 [(set (match_operand:DF 0 "register_operand" "=f,f")
3146 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3147 (match_operand:DF 2 "general_operand" "f,m")))
3148 (clobber (reg:CC 33))]
3149 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3150 "@
3151 adbr\\t%0,%2
3152 adb\\t%0,%2"
3153 [(set_attr "op_type" "RRE,RXE")
3154 (set_attr "atype" "reg,mem")])
3155
3156 (define_insn "*adddf3_ibm"
3157 [(set (match_operand:DF 0 "register_operand" "=f,f")
3158 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3159 (match_operand:DF 2 "general_operand" "f,m")))
3160 (clobber (reg:CC 33))]
3161 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3162 "@
3163 adr\\t%0,%2
3164 ad\\t%0,%2"
3165 [(set_attr "op_type" "RR,RX")
3166 (set_attr "atype" "reg,mem")])
3167
3168 ;
3169 ; addsf3 instruction pattern(s).
3170 ;
3171
3172 (define_expand "addsf3"
3173 [(parallel
3174 [(set (match_operand:SF 0 "register_operand" "=f,f")
3175 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3176 (match_operand:SF 2 "general_operand" "f,m")))
3177 (clobber (reg:CC 33))])]
3178 "TARGET_HARD_FLOAT"
3179 "")
3180
3181 (define_insn "*addsf3"
3182 [(set (match_operand:SF 0 "register_operand" "=f,f")
3183 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3184 (match_operand:SF 2 "general_operand" "f,m")))
3185 (clobber (reg:CC 33))]
3186 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3187 "@
3188 aebr\\t%0,%2
3189 aeb\\t%0,%2"
3190 [(set_attr "op_type" "RRE,RXE")
3191 (set_attr "atype" "reg,mem")])
3192
3193 (define_insn "*addsf3"
3194 [(set (match_operand:SF 0 "register_operand" "=f,f")
3195 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3196 (match_operand:SF 2 "general_operand" "f,m")))
3197 (clobber (reg:CC 33))]
3198 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3199 "@
3200 aer\\t%0,%2
3201 ae\\t%0,%2"
3202 [(set_attr "op_type" "RR,RX")
3203 (set_attr "atype" "reg,mem")])
3204
3205
3206 ;;
3207 ;;- Subtract instructions.
3208 ;;
3209
3210 ;
3211 ; subdi3 instruction pattern(s).
3212 ;
3213
3214 (define_insn "*subdi3_sign"
3215 [(set (match_operand:DI 0 "register_operand" "=d,d")
3216 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3217 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3218 (clobber (reg:CC 33))]
3219 "TARGET_64BIT"
3220 "@
3221 sgfr\\t%0,%2
3222 sgf\\t%0,%2"
3223 [(set_attr "op_type" "RRE,RXE")
3224 (set_attr "atype" "reg,mem")])
3225
3226 (define_insn "*subdi3_zero_cc"
3227 [(set (reg 33)
3228 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3229 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3230 (const_int 0)))
3231 (set (match_operand:DI 0 "register_operand" "=d,d")
3232 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3233 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3234 "@
3235 slgfr\\t%0,%2
3236 slgf\\t%0,%2"
3237 [(set_attr "op_type" "RRE,RXE")
3238 (set_attr "atype" "reg,mem")])
3239
3240 (define_insn "*subdi3_zero_cconly"
3241 [(set (reg 33)
3242 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3243 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3244 (const_int 0)))
3245 (clobber (match_scratch:DI 0 "=d,d"))]
3246 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3247 "@
3248 slgfr\\t%0,%2
3249 slgf\\t%0,%2"
3250 [(set_attr "op_type" "RRE,RXE")
3251 (set_attr "atype" "reg,mem")])
3252
3253 (define_insn "*subdi3_zero"
3254 [(set (match_operand:DI 0 "register_operand" "=d,d")
3255 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3256 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3257 (clobber (reg:CC 33))]
3258 "TARGET_64BIT"
3259 "@
3260 slgfr\\t%0,%2
3261 slgf\\t%0,%2"
3262 [(set_attr "op_type" "RRE,RXE")
3263 (set_attr "atype" "reg,mem")])
3264
3265 (define_insn "*subdi3_cc"
3266 [(set (reg 33)
3267 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3268 (match_operand:DI 2 "general_operand" "d,m"))
3269 (const_int 0)))
3270 (set (match_operand:DI 0 "register_operand" "=d,d")
3271 (minus:DI (match_dup 1) (match_dup 2)))]
3272 "s390_match_ccmode (insn, CCLmode)"
3273 "@
3274 slgr\\t%0,%2
3275 slg\\t%0,%2"
3276 [(set_attr "op_type" "RRE,RXE")
3277 (set_attr "atype" "reg,mem")])
3278
3279 (define_insn "*subdi3_cconly"
3280 [(set (reg 33)
3281 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3282 (match_operand:DI 2 "general_operand" "d,m"))
3283 (const_int 0)))
3284 (clobber (match_scratch:DI 0 "=d,d"))]
3285 "s390_match_ccmode (insn, CCLmode)"
3286 "@
3287 slgr\\t%0,%2
3288 slg\\t%0,%2"
3289 [(set_attr "op_type" "RRE,RXE")
3290 (set_attr "atype" "reg,mem")])
3291
3292 (define_insn "*subdi3_64"
3293 [(set (match_operand:DI 0 "register_operand" "=d,d")
3294 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3295 (match_operand:DI 2 "general_operand" "d,m") ) )
3296 (clobber (reg:CC 33))]
3297 "TARGET_64BIT"
3298 "@
3299 sgr\\t%0,%2
3300 sg\\t%0,%2"
3301 [(set_attr "op_type" "RRE,RRE")
3302 (set_attr "atype" "reg,mem")])
3303
3304 (define_insn_and_split "*subdi3_31"
3305 [(set (match_operand:DI 0 "register_operand" "=&d")
3306 (minus:DI (match_operand:DI 1 "register_operand" "0")
3307 (match_operand:DI 2 "general_operand" "dm") ) )
3308 (clobber (reg:CC 33))]
3309 "!TARGET_64BIT"
3310 "#"
3311 "&& reload_completed"
3312 [(parallel
3313 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3314 (clobber (reg:CC 33))])
3315 (parallel
3316 [(set (reg:CCL2 33)
3317 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3318 (match_dup 7)))
3319 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3320 (set (pc)
3321 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3322 (pc)
3323 (label_ref (match_dup 9))))
3324 (parallel
3325 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3326 (clobber (reg:CC 33))])
3327 (match_dup 9)]
3328 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3329 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3330 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3331 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3332 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3333 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3334 operands[9] = gen_label_rtx ();"
3335 [(set_attr "op_type" "NN")
3336 (set_attr "type" "o3")])
3337
3338 (define_expand "subdi3"
3339 [(parallel
3340 [(set (match_operand:DI 0 "register_operand" "")
3341 (minus:DI (match_operand:DI 1 "register_operand" "")
3342 (match_operand:DI 2 "general_operand" "")))
3343 (clobber (reg:CC 33))])]
3344 ""
3345 "")
3346
3347 ;
3348 ; subsi3 instruction pattern(s).
3349 ;
3350
3351 (define_insn "*subsi3_borrow_cc"
3352 [(set (reg 33)
3353 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3354 (match_operand:SI 2 "general_operand" "d,m"))
3355 (match_dup 1)))
3356 (set (match_operand:SI 0 "register_operand" "=d,d")
3357 (minus:SI (match_dup 1) (match_dup 2)))]
3358 "s390_match_ccmode(insn, CCL2mode)"
3359 "@
3360 slr\\t%0,%2
3361 sl\\t%0,%2"
3362 [(set_attr "op_type" "RR,RX")
3363 (set_attr "atype" "reg,mem")])
3364
3365 (define_insn "*subsi3_borrow_cconly"
3366 [(set (reg 33)
3367 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3368 (match_operand:SI 2 "general_operand" "d,m"))
3369 (match_dup 1)))
3370 (clobber (match_scratch:SI 0 "=d,d"))]
3371 "s390_match_ccmode(insn, CCL2mode)"
3372 "@
3373 slr\\t%0,%2
3374 sl\\t%0,%2"
3375 [(set_attr "op_type" "RR,RX")
3376 (set_attr "atype" "reg,mem")])
3377
3378 (define_insn "*subsi3_cc"
3379 [(set (reg 33)
3380 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3381 (match_operand:SI 2 "general_operand" "d,m"))
3382 (const_int 0)))
3383 (set (match_operand:SI 0 "register_operand" "=d,d")
3384 (minus:SI (match_dup 1) (match_dup 2)))]
3385 "s390_match_ccmode(insn, CCLmode)"
3386 "@
3387 slr\\t%0,%2
3388 sl\\t%0,%2"
3389 [(set_attr "op_type" "RR,RX")
3390 (set_attr "atype" "reg,mem")])
3391
3392 (define_insn "*subsi3_cconly"
3393 [(set (reg 33)
3394 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3395 (match_operand:SI 2 "general_operand" "d,m"))
3396 (const_int 0)))
3397 (clobber (match_scratch:SI 0 "=d,d"))]
3398 "s390_match_ccmode(insn, CCLmode)"
3399 "@
3400 slr\\t%0,%2
3401 sl\\t%0,%2"
3402 [(set_attr "op_type" "RR,RX")
3403 (set_attr "atype" "reg,mem")])
3404
3405 (define_insn "*subsi3_sign"
3406 [(set (match_operand:SI 0 "register_operand" "=d")
3407 (minus:SI (match_operand:SI 1 "register_operand" "0")
3408 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3409 (clobber (reg:CC 33))]
3410 ""
3411 "sh\\t%0,%2"
3412 [(set_attr "op_type" "RX")
3413 (set_attr "atype" "mem")])
3414
3415 (define_insn "*subsi3_sub"
3416 [(set (match_operand:SI 0 "register_operand" "=d")
3417 (minus:SI (match_operand:SI 1 "register_operand" "0")
3418 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3419 (clobber (reg:CC 33))]
3420 ""
3421 "sh\\t%0,%2"
3422 [(set_attr "op_type" "RX")
3423 (set_attr "atype" "mem")])
3424
3425 (define_insn "subsi3"
3426 [(set (match_operand:SI 0 "register_operand" "=d,d")
3427 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3428 (match_operand:SI 2 "general_operand" "d,m")))
3429 (clobber (reg:CC 33))]
3430 ""
3431 "@
3432 sr\\t%0,%2
3433 s\\t%0,%2"
3434 [(set_attr "op_type" "RR,RX")
3435 (set_attr "atype" "reg,mem")])
3436
3437
3438 ;
3439 ; subdf3 instruction pattern(s).
3440 ;
3441
3442 (define_expand "subdf3"
3443 [(parallel
3444 [(set (match_operand:DF 0 "register_operand" "=f,f")
3445 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3446 (match_operand:DF 2 "general_operand" "f,m")))
3447 (clobber (reg:CC 33))])]
3448 "TARGET_HARD_FLOAT"
3449 "")
3450
3451 (define_insn "*subdf3"
3452 [(set (match_operand:DF 0 "register_operand" "=f,f")
3453 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3454 (match_operand:DF 2 "general_operand" "f,m")))
3455 (clobber (reg:CC 33))]
3456 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3457 "@
3458 sdbr\\t%0,%2
3459 sdb\\t%0,%2"
3460 [(set_attr "op_type" "RRE,RXE")
3461 (set_attr "atype" "reg,mem")])
3462
3463 (define_insn "*subdf3_ibm"
3464 [(set (match_operand:DF 0 "register_operand" "=f,f")
3465 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3466 (match_operand:DF 2 "general_operand" "f,m")))
3467 (clobber (reg:CC 33))]
3468 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3469 "@
3470 sdr\\t%0,%2
3471 sd\\t%0,%2"
3472 [(set_attr "op_type" "RR,RX")
3473 (set_attr "atype" "reg,mem")])
3474
3475 ;
3476 ; subsf3 instruction pattern(s).
3477 ;
3478
3479 (define_expand "subsf3"
3480 [(parallel
3481 [(set (match_operand:SF 0 "register_operand" "=f,f")
3482 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3483 (match_operand:SF 2 "general_operand" "f,m")))
3484 (clobber (reg:CC 33))])]
3485 "TARGET_HARD_FLOAT"
3486 "")
3487
3488 (define_insn "*subsf3"
3489 [(set (match_operand:SF 0 "register_operand" "=f,f")
3490 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3491 (match_operand:SF 2 "general_operand" "f,m")))
3492 (clobber (reg:CC 33))]
3493 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3494 "@
3495 sebr\\t%0,%2
3496 seb\\t%0,%2"
3497 [(set_attr "op_type" "RRE,RXE")
3498 (set_attr "atype" "reg,mem")])
3499
3500 (define_insn "*subsf3_ibm"
3501 [(set (match_operand:SF 0 "register_operand" "=f,f")
3502 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3503 (match_operand:SF 2 "general_operand" "f,m")))
3504 (clobber (reg:CC 33))]
3505 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3506 "@
3507 ser\\t%0,%2
3508 se\\t%0,%2"
3509 [(set_attr "op_type" "RR,RX")
3510 (set_attr "atype" "reg,mem")])
3511
3512
3513 ;;
3514 ;;- Multiply instructions.
3515 ;;
3516
3517 ;
3518 ; muldi3 instruction pattern(s).
3519 ;
3520
3521 (define_insn "*muldi3_sign"
3522 [(set (match_operand:DI 0 "register_operand" "=d,d")
3523 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3524 (match_operand:DI 1 "register_operand" "0,0")))]
3525 "TARGET_64BIT"
3526 "@
3527 msgfr\\t%0,%2
3528 msgf\\t%0,%2"
3529 [(set_attr "op_type" "RRE,RXE")
3530 (set_attr "atype" "reg,mem")
3531 (set_attr "type" "imul")])
3532
3533
3534 (define_insn "muldi3"
3535 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3536 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3537 (match_operand:DI 2 "general_operand" "d,K,m")))]
3538 "TARGET_64BIT"
3539 "@
3540 msgr\\t%0,%2
3541 mghi\\t%0,%h2
3542 msg\\t%0,%2"
3543 [(set_attr "op_type" "RRE,RI,RXE")
3544 (set_attr "atype" "reg,reg,mem")
3545 (set_attr "type" "imul")])
3546
3547 ;
3548 ; mulsi3 instruction pattern(s).
3549 ;
3550
3551 (define_insn "mulsi3"
3552 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3553 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3554 (match_operand:SI 2 "general_operand" "d,K,m")))]
3555 ""
3556 "@
3557 msr\\t%0,%2
3558 mhi\\t%0,%h2
3559 ms\\t%0,%2"
3560 [(set_attr "op_type" "RRE,RI,RX")
3561 (set_attr "atype" "reg,reg,mem")
3562 (set_attr "type" "imul")])
3563
3564 ;
3565 ; mulsidi3 instruction pattern(s).
3566 ;
3567
3568 (define_expand "mulsidi3"
3569 [(set (match_operand:DI 0 "register_operand" "")
3570 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3571 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3572 "!TARGET_64BIT"
3573 "
3574 {
3575 rtx insn;
3576
3577 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3578 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3579
3580 REG_NOTES (insn) =
3581 gen_rtx_EXPR_LIST (REG_EQUAL,
3582 gen_rtx_MULT (DImode,
3583 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3584 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3585 REG_NOTES (insn));
3586 DONE;
3587 }")
3588
3589 (define_insn "mulsi_6432"
3590 [(set (match_operand:DI 0 "register_operand" "=d,d")
3591 (mult:DI (sign_extend:DI
3592 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3593 (sign_extend:DI
3594 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3595 "!TARGET_64BIT"
3596 "@
3597 mr\\t%0,%2
3598 m\\t%0,%2"
3599 [(set_attr "op_type" "RR,RX")
3600 (set_attr "atype" "reg,mem")
3601 (set_attr "type" "imul")])
3602
3603 ;
3604 ; muldf3 instruction pattern(s).
3605 ;
3606
3607 (define_expand "muldf3"
3608 [(parallel
3609 [(set (match_operand:DF 0 "register_operand" "=f,f")
3610 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3611 (match_operand:DF 2 "general_operand" "f,m")))
3612 (clobber (reg:CC 33))])]
3613 "TARGET_HARD_FLOAT"
3614 "")
3615
3616 (define_insn "*muldf3"
3617 [(set (match_operand:DF 0 "register_operand" "=f,f")
3618 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3619 (match_operand:DF 2 "general_operand" "f,m")))
3620 (clobber (reg:CC 33))]
3621 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3622 "@
3623 mdbr\\t%0,%2
3624 mdb\\t%0,%2"
3625 [(set_attr "op_type" "RRE,RXE")
3626 (set_attr "type" "fmul")
3627 (set_attr "atype" "reg,mem")])
3628
3629 (define_insn "*muldf3_ibm"
3630 [(set (match_operand:DF 0 "register_operand" "=f,f")
3631 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3632 (match_operand:DF 2 "general_operand" "f,m")))
3633 (clobber (reg:CC 33))]
3634 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3635 "@
3636 mdr\\t%0,%2
3637 md\\t%0,%2"
3638 [(set_attr "op_type" "RR,RX")
3639 (set_attr "type" "fmul")
3640 (set_attr "atype" "reg,mem")])
3641
3642 ;
3643 ; mulsf3 instruction pattern(s).
3644 ;
3645
3646 (define_expand "mulsf3"
3647 [(parallel
3648 [(set (match_operand:SF 0 "register_operand" "=f,f")
3649 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3650 (match_operand:SF 2 "general_operand" "f,m")))
3651 (clobber (reg:CC 33))])]
3652 "TARGET_HARD_FLOAT"
3653 "")
3654
3655 (define_insn "*mulsf3"
3656 [(set (match_operand:SF 0 "register_operand" "=f,f")
3657 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3658 (match_operand:SF 2 "general_operand" "f,m")))
3659 (clobber (reg:CC 33))]
3660 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3661 "@
3662 meebr\\t%0,%2
3663 meeb\\t%0,%2"
3664 [(set_attr "op_type" "RRE,RXE")
3665 (set_attr "type" "fmul")
3666 (set_attr "atype" "reg,mem")])
3667
3668 (define_insn "*mulsf3_ibm"
3669 [(set (match_operand:SF 0 "register_operand" "=f,f")
3670 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3671 (match_operand:SF 2 "general_operand" "f,m")))
3672 (clobber (reg:CC 33))]
3673 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3674 "@
3675 mer\\t%0,%2
3676 me\\t%0,%2"
3677 [(set_attr "op_type" "RR,RX")
3678 (set_attr "type" "fmul")
3679 (set_attr "atype" "reg,mem")])
3680
3681
3682 ;;
3683 ;;- Divide and modulo instructions.
3684 ;;
3685
3686 ;
3687 ; divmoddi4 instruction pattern(s).
3688 ;
3689
3690 (define_expand "divmoddi4"
3691 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3692 (div:DI (match_operand:DI 1 "general_operand" "")
3693 (match_operand:DI 2 "general_operand" "")))
3694 (set (match_operand:DI 3 "general_operand" "")
3695 (mod:DI (match_dup 1) (match_dup 2)))])
3696 (clobber (match_dup 4))]
3697 "TARGET_64BIT"
3698 "
3699 {
3700 rtx insn, div_equal, mod_equal, equal;
3701
3702 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3703 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3704 equal = gen_rtx_IOR (TImode,
3705 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3706 gen_rtx_ASHIFT (TImode,
3707 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3708 GEN_INT (64)));
3709
3710 operands[4] = gen_reg_rtx(TImode);
3711 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3712 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3713 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3714 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3715 REG_NOTES (insn) =
3716 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3717
3718 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3719 REG_NOTES (insn) =
3720 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3721
3722 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3723 REG_NOTES (insn) =
3724 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3725
3726 DONE;
3727 }")
3728
3729 (define_insn "divmodtidi3"
3730 [(set (match_operand:TI 0 "register_operand" "=d,d")
3731 (ior:TI
3732 (zero_extend:TI
3733 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3734 (match_operand:DI 2 "general_operand" "d,m")))
3735 (ashift:TI
3736 (zero_extend:TI
3737 (mod:DI (truncate:DI (match_dup 1))
3738 (match_dup 2)))
3739 (const_int 64))))]
3740 "TARGET_64BIT"
3741 "@
3742 dsgr\\t%0,%2
3743 dsg\\t%0,%2"
3744 [(set_attr "op_type" "RRE,RXE")
3745 (set_attr "type" "idiv")
3746 (set_attr "atype" "reg,mem")])
3747
3748 (define_insn "divmodtisi3"
3749 [(set (match_operand:TI 0 "register_operand" "=d,d")
3750 (ior:TI
3751 (zero_extend:TI
3752 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3753 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3754 (ashift:TI
3755 (zero_extend:TI
3756 (mod:DI (truncate:DI (match_dup 1))
3757 (sign_extend:DI (match_dup 2))))
3758 (const_int 64))))]
3759 "TARGET_64BIT"
3760 "@
3761 dsgfr\\t%0,%2
3762 dsgf\\t%0,%2"
3763 [(set_attr "op_type" "RRE,RXE")
3764 (set_attr "type" "idiv")
3765 (set_attr "atype" "reg,mem")])
3766
3767 ;
3768 ; udivmoddi4 instruction pattern(s).
3769 ;
3770
3771 (define_expand "udivmoddi4"
3772 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3773 (udiv:DI (match_operand:DI 1 "general_operand" "")
3774 (match_operand:DI 2 "nonimmediate_operand" "")))
3775 (set (match_operand:DI 3 "general_operand" "")
3776 (umod:DI (match_dup 1) (match_dup 2)))])
3777 (clobber (match_dup 4))]
3778 "TARGET_64BIT"
3779 "
3780 {
3781 rtx insn, div_equal, mod_equal, equal;
3782
3783 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3784 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3785 equal = gen_rtx_IOR (TImode,
3786 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3787 gen_rtx_ASHIFT (TImode,
3788 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3789 GEN_INT (64)));
3790
3791 operands[4] = gen_reg_rtx(TImode);
3792 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3793 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3794 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3795 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3796 REG_NOTES (insn) =
3797 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3798
3799 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3800 REG_NOTES (insn) =
3801 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3802
3803 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3804 REG_NOTES (insn) =
3805 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3806
3807 DONE;
3808 }")
3809
3810 (define_insn "udivmodtidi3"
3811 [(set (match_operand:TI 0 "register_operand" "=d,d")
3812 (ior:TI (zero_extend:TI
3813 (truncate:DI
3814 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3815 (zero_extend:TI
3816 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3817 (ashift:TI
3818 (zero_extend:TI
3819 (truncate:DI
3820 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3821 (const_int 64))))]
3822 "TARGET_64BIT"
3823 "@
3824 dlgr\\t%0,%2
3825 dlg\\t%0,%2"
3826 [(set_attr "op_type" "RRE,RXE")
3827 (set_attr "type" "idiv")
3828 (set_attr "atype" "reg,mem")])
3829
3830 ;
3831 ; divmodsi4 instruction pattern(s).
3832 ;
3833
3834 (define_expand "divmodsi4"
3835 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3836 (div:SI (match_operand:SI 1 "general_operand" "")
3837 (match_operand:SI 2 "nonimmediate_operand" "")))
3838 (set (match_operand:SI 3 "general_operand" "")
3839 (mod:SI (match_dup 1) (match_dup 2)))])
3840 (clobber (match_dup 4))]
3841 "!TARGET_64BIT"
3842 "
3843 {
3844 rtx insn, div_equal, mod_equal, equal;
3845
3846 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3847 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3848 equal = gen_rtx_IOR (DImode,
3849 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3850 gen_rtx_ASHIFT (DImode,
3851 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3852 GEN_INT (32)));
3853
3854 operands[4] = gen_reg_rtx(DImode);
3855 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3856 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3857 REG_NOTES (insn) =
3858 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3859
3860 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3861 REG_NOTES (insn) =
3862 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3863
3864 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3865 REG_NOTES (insn) =
3866 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3867
3868 DONE;
3869 }")
3870
3871 (define_insn "divmoddisi3"
3872 [(set (match_operand:DI 0 "register_operand" "=d,d")
3873 (ior:DI (zero_extend:DI
3874 (truncate:SI
3875 (div:DI (match_operand:DI 1 "register_operand" "0,0")
3876 (sign_extend:DI
3877 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3878 (ashift:DI
3879 (zero_extend:DI
3880 (truncate:SI
3881 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
3882 (const_int 32))))]
3883 "!TARGET_64BIT"
3884 "@
3885 dr\\t%0,%2
3886 d\\t%0,%2"
3887 [(set_attr "op_type" "RR,RX")
3888 (set_attr "type" "idiv")
3889 (set_attr "atype" "reg,mem")])
3890
3891 ;
3892 ; udivsi3 and umodsi3 instruction pattern(s).
3893 ;
3894
3895
3896 (define_expand "udivsi3"
3897 [(set (match_operand:SI 0 "register_operand" "=d")
3898 (udiv:SI (match_operand:SI 1 "general_operand" "")
3899 (match_operand:SI 2 "general_operand" "")))
3900 (clobber (match_dup 3))]
3901 "!TARGET_64BIT"
3902 "
3903 {
3904 rtx insn, udiv_equal, umod_equal, equal;
3905
3906 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3907 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
3908 equal = gen_rtx_IOR (DImode,
3909 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
3910 gen_rtx_ASHIFT (DImode,
3911 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
3912 GEN_INT (32)));
3913
3914 operands[3] = gen_reg_rtx (DImode);
3915
3916 if (CONSTANT_P (operands[2]))
3917 {
3918 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3919 {
3920 rtx label1 = gen_label_rtx ();
3921
3922 operands[1] = make_safe_from (operands[1], operands[0]);
3923 emit_move_insn (operands[0], const0_rtx);
3924 emit_insn (gen_cmpsi (operands[1], operands[2]));
3925 emit_jump_insn (gen_bltu (label1));
3926 emit_move_insn (operands[0], const1_rtx);
3927 emit_label (label1);
3928 }
3929 else
3930 {
3931 operands[2] = force_reg (SImode, operands[2]);
3932 operands[2] = make_safe_from (operands[2], operands[0]);
3933
3934 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
3935 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
3936 operands[2]));
3937 REG_NOTES (insn) =
3938 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3939
3940 insn = emit_move_insn (operands[0],
3941 gen_lowpart (SImode, operands[3]));
3942 REG_NOTES (insn) =
3943 gen_rtx_EXPR_LIST (REG_EQUAL,
3944 udiv_equal, REG_NOTES (insn));
3945 }
3946 }
3947 else
3948 {
3949 rtx label1 = gen_label_rtx ();
3950 rtx label2 = gen_label_rtx ();
3951 rtx label3 = gen_label_rtx ();
3952
3953 operands[1] = force_reg (SImode, operands[1]);
3954 operands[1] = make_safe_from (operands[1], operands[0]);
3955 operands[2] = force_reg (SImode, operands[2]);
3956 operands[2] = make_safe_from (operands[2], operands[0]);
3957
3958 emit_move_insn (operands[0], const0_rtx);
3959 emit_insn (gen_cmpsi (operands[2], operands[1]));
3960 emit_jump_insn (gen_bgtu (label3));
3961 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3962 emit_jump_insn (gen_blt (label2));
3963 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3964 emit_jump_insn (gen_beq (label1));
3965 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
3966 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
3967 operands[2]));
3968 REG_NOTES (insn) =
3969 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3970
3971 insn = emit_move_insn (operands[0],
3972 gen_lowpart (SImode, operands[3]));
3973 REG_NOTES (insn) =
3974 gen_rtx_EXPR_LIST (REG_EQUAL,
3975 udiv_equal, REG_NOTES (insn));
3976 emit_jump (label3);
3977 emit_label (label1);
3978 emit_move_insn (operands[0], operands[1]);
3979 emit_jump (label3);
3980 emit_label (label2);
3981 emit_move_insn (operands[0], const1_rtx);
3982 emit_label (label3);
3983 }
3984 emit_move_insn (operands[0], operands[0]);
3985 DONE;
3986 }")
3987
3988 (define_expand "umodsi3"
3989 [(set (match_operand:SI 0 "register_operand" "=d")
3990 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
3991 (match_operand:SI 2 "nonimmediate_operand" "")))
3992 (clobber (match_dup 3))]
3993 "!TARGET_64BIT"
3994 "
3995 {
3996 rtx insn, udiv_equal, umod_equal, equal;
3997
3998 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3999 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4000 equal = gen_rtx_IOR (DImode,
4001 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4002 gen_rtx_ASHIFT (DImode,
4003 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4004 GEN_INT (32)));
4005
4006 operands[3] = gen_reg_rtx (DImode);
4007
4008 if (CONSTANT_P (operands[2]))
4009 {
4010 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4011 {
4012 rtx label1 = gen_label_rtx ();
4013
4014 operands[1] = make_safe_from (operands[1], operands[0]);
4015 emit_move_insn (operands[0], operands[1]);
4016 emit_insn (gen_cmpsi (operands[0], operands[2]));
4017 emit_jump_insn (gen_bltu (label1));
4018 emit_insn (gen_abssi2 (operands[0], operands[2]));
4019 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4020 emit_label (label1);
4021 }
4022 else
4023 {
4024 operands[2] = force_reg (SImode, operands[2]);
4025 operands[2] = make_safe_from (operands[2], operands[0]);
4026
4027 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4028 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4029 operands[2]));
4030 REG_NOTES (insn) =
4031 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4032
4033 insn = emit_move_insn (operands[0],
4034 gen_highpart (SImode, operands[3]));
4035 REG_NOTES (insn) =
4036 gen_rtx_EXPR_LIST (REG_EQUAL,
4037 umod_equal, REG_NOTES (insn));
4038 }
4039 }
4040 else
4041 {
4042 rtx label1 = gen_label_rtx ();
4043 rtx label2 = gen_label_rtx ();
4044 rtx label3 = gen_label_rtx ();
4045
4046 operands[1] = force_reg (SImode, operands[1]);
4047 operands[1] = make_safe_from (operands[1], operands[0]);
4048 operands[2] = force_reg (SImode, operands[2]);
4049 operands[2] = make_safe_from (operands[2], operands[0]);
4050
4051 emit_move_insn(operands[0], operands[1]);
4052 emit_insn (gen_cmpsi (operands[2], operands[1]));
4053 emit_jump_insn (gen_bgtu (label3));
4054 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4055 emit_jump_insn (gen_blt (label2));
4056 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4057 emit_jump_insn (gen_beq (label1));
4058 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4059 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4060 operands[2]));
4061 REG_NOTES (insn) =
4062 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4063
4064 insn = emit_move_insn (operands[0],
4065 gen_highpart (SImode, operands[3]));
4066 REG_NOTES (insn) =
4067 gen_rtx_EXPR_LIST (REG_EQUAL,
4068 umod_equal, REG_NOTES (insn));
4069 emit_jump (label3);
4070 emit_label (label1);
4071 emit_move_insn (operands[0], const0_rtx);
4072 emit_jump (label3);
4073 emit_label (label2);
4074 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4075 emit_label (label3);
4076 }
4077 DONE;
4078 }")
4079
4080 ;
4081 ; divdf3 instruction pattern(s).
4082 ;
4083
4084 (define_expand "divdf3"
4085 [(parallel
4086 [(set (match_operand:DF 0 "register_operand" "=f,f")
4087 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4088 (match_operand:DF 2 "general_operand" "f,m")))
4089 (clobber (reg:CC 33))])]
4090 "TARGET_HARD_FLOAT"
4091 "")
4092
4093 (define_insn "*divdf3"
4094 [(set (match_operand:DF 0 "register_operand" "=f,f")
4095 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4096 (match_operand:DF 2 "general_operand" "f,m")))
4097 (clobber (reg:CC 33))]
4098 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4099 "@
4100 ddbr\\t%0,%2
4101 ddb\\t%0,%2"
4102 [(set_attr "op_type" "RRE,RXE")
4103 (set_attr "type" "fdiv")
4104 (set_attr "atype" "reg,mem")])
4105
4106 (define_insn "*divdf3_ibm"
4107 [(set (match_operand:DF 0 "register_operand" "=f,f")
4108 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4109 (match_operand:DF 2 "general_operand" "f,m")))
4110 (clobber (reg:CC 33))]
4111 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4112 "@
4113 ddr\\t%0,%2
4114 dd\\t%0,%2"
4115 [(set_attr "op_type" "RR,RX")
4116 (set_attr "type" "fdiv")
4117 (set_attr "atype" "reg,mem")])
4118
4119 ;
4120 ; divsf3 instruction pattern(s).
4121 ;
4122
4123 (define_expand "divsf3"
4124 [(parallel
4125 [(set (match_operand:SF 0 "register_operand" "=f,f")
4126 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4127 (match_operand:SF 2 "general_operand" "f,m")))
4128 (clobber (reg:CC 33))])]
4129 "TARGET_HARD_FLOAT"
4130 "")
4131
4132 (define_insn "*divsf3"
4133 [(set (match_operand:SF 0 "register_operand" "=f,f")
4134 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4135 (match_operand:SF 2 "general_operand" "f,m")))
4136 (clobber (reg:CC 33))]
4137 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4138 "@
4139 debr\\t%0,%2
4140 deb\\t%0,%2"
4141 [(set_attr "op_type" "RRE,RXE")
4142 (set_attr "type" "fdiv")
4143 (set_attr "atype" "reg,mem")])
4144
4145 (define_insn "*divsf3"
4146 [(set (match_operand:SF 0 "register_operand" "=f,f")
4147 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4148 (match_operand:SF 2 "general_operand" "f,m")))
4149 (clobber (reg:CC 33))]
4150 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4151 "@
4152 der\\t%0,%2
4153 de\\t%0,%2"
4154 [(set_attr "op_type" "RR,RX")
4155 (set_attr "type" "fdiv")
4156 (set_attr "atype" "reg,mem")])
4157
4158
4159 ;;
4160 ;;- And instructions.
4161 ;;
4162
4163 ;
4164 ; anddi3 instruction pattern(s).
4165 ;
4166
4167 (define_insn "*anddi3_cc"
4168 [(set (reg 33)
4169 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4170 (match_operand:DI 2 "general_operand" "d,m"))
4171 (const_int 0)))
4172 (set (match_operand:DI 0 "register_operand" "=d,d")
4173 (and:DI (match_dup 1) (match_dup 2)))]
4174 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4175 "@
4176 ngr\\t%0,%2
4177 ng\\t%0,%2"
4178 [(set_attr "op_type" "RRE,RXE")
4179 (set_attr "atype" "reg,mem")])
4180
4181 (define_insn "*anddi3_cconly"
4182 [(set (reg 33)
4183 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4184 (match_operand:DI 2 "general_operand" "d,m"))
4185 (const_int 0)))
4186 (clobber (match_scratch:DI 0 "=d,d"))]
4187 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4188 "@
4189 ngr\\t%0,%2
4190 ng\\t%0,%2"
4191 [(set_attr "op_type" "RRE,RXE")
4192 (set_attr "atype" "reg,mem")])
4193
4194 (define_insn "*anddi3_ni"
4195 [(set (match_operand:DI 0 "register_operand" "=d")
4196 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4197 (match_operand:DI 2 "immediate_operand" "n")))
4198 (clobber (reg:CC 33))]
4199 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4200 "*
4201 {
4202 int part = s390_single_hi (operands[2], DImode, -1);
4203 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4204
4205 switch (part)
4206 {
4207 case 0: return \"nihh\\t%0,%x2\";
4208 case 1: return \"nihl\\t%0,%x2\";
4209 case 2: return \"nilh\\t%0,%x2\";
4210 case 3: return \"nill\\t%0,%x2\";
4211 default: abort ();
4212 }
4213 }"
4214 [(set_attr "op_type" "RI")
4215 (set_attr "atype" "reg")])
4216
4217 (define_insn "anddi3"
4218 [(set (match_operand:DI 0 "register_operand" "=d,d")
4219 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4220 (match_operand:DI 2 "general_operand" "d,m")))
4221 (clobber (reg:CC 33))]
4222 "TARGET_64BIT"
4223 "@
4224 ngr\\t%0,%2
4225 ng\\t%0,%2"
4226 [(set_attr "op_type" "RRE,RXE")
4227 (set_attr "atype" "reg,mem")])
4228
4229 (define_insn "*anddi3_ss"
4230 [(set (match_operand:DI 0 "s_operand" "=Q")
4231 (and:DI (match_dup 0)
4232 (match_operand:DI 1 "s_imm_operand" "Q")))
4233 (clobber (reg:CC 33))]
4234 ""
4235 "nc\\t%O0(8,%R0),%1"
4236 [(set_attr "op_type" "SS")
4237 (set_attr "atype" "mem")])
4238
4239 (define_insn "*anddi3_ss_inv"
4240 [(set (match_operand:DI 0 "s_operand" "=Q")
4241 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4242 (match_dup 0)))
4243 (clobber (reg:CC 33))]
4244 ""
4245 "nc\\t%O0(8,%R0),%1"
4246 [(set_attr "op_type" "SS")
4247 (set_attr "atype" "mem")])
4248
4249 ;
4250 ; andsi3 instruction pattern(s).
4251 ;
4252
4253 (define_insn "*andsi3_cc"
4254 [(set (reg 33)
4255 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4256 (match_operand:SI 2 "general_operand" "d,m"))
4257 (const_int 0)))
4258 (set (match_operand:SI 0 "register_operand" "=d,d")
4259 (and:SI (match_dup 1) (match_dup 2)))]
4260 "s390_match_ccmode(insn, CCTmode)"
4261 "@
4262 nr\\t%0,%2
4263 n\\t%0,%2"
4264 [(set_attr "op_type" "RR,RX")
4265 (set_attr "atype" "reg,mem")])
4266
4267 (define_insn "*andsi3_cconly"
4268 [(set (reg 33)
4269 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4270 (match_operand:SI 2 "general_operand" "d,m"))
4271 (const_int 0)))
4272 (clobber (match_scratch:SI 0 "=d,d"))]
4273 "s390_match_ccmode(insn, CCTmode)"
4274 "@
4275 nr\\t%0,%2
4276 n\\t%0,%2"
4277 [(set_attr "op_type" "RR,RX")
4278 (set_attr "atype" "reg,mem")])
4279
4280 (define_insn "*andsi3_ni"
4281 [(set (match_operand:SI 0 "register_operand" "=d")
4282 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4283 (match_operand:SI 2 "immediate_operand" "n")))
4284 (clobber (reg:CC 33))]
4285 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4286 "*
4287 {
4288 int part = s390_single_hi (operands[2], SImode, -1);
4289 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4290
4291 switch (part)
4292 {
4293 case 0: return \"nilh\\t%0,%x2\";
4294 case 1: return \"nill\\t%0,%x2\";
4295 default: abort ();
4296 }
4297 }"
4298 [(set_attr "op_type" "RI")
4299 (set_attr "atype" "reg")])
4300
4301 (define_insn "andsi3"
4302 [(set (match_operand:SI 0 "register_operand" "=d,d")
4303 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4304 (match_operand:SI 2 "general_operand" "d,m")))
4305 (clobber (reg:CC 33))]
4306 ""
4307 "@
4308 nr\\t%0,%2
4309 n\\t%0,%2"
4310 [(set_attr "op_type" "RR,RX")
4311 (set_attr "atype" "reg,mem")])
4312
4313 (define_insn "*andsi3_ss"
4314 [(set (match_operand:SI 0 "s_operand" "=Q")
4315 (and:SI (match_dup 0)
4316 (match_operand:SI 1 "s_imm_operand" "Q")))
4317 (clobber (reg:CC 33))]
4318 ""
4319 "nc\\t%O0(4,%R0),%1"
4320 [(set_attr "op_type" "SS")
4321 (set_attr "atype" "mem")])
4322
4323 (define_insn "*andsi3_ss_inv"
4324 [(set (match_operand:SI 0 "s_operand" "=Q")
4325 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4326 (match_dup 0)))
4327 (clobber (reg:CC 33))]
4328 ""
4329 "nc\\t%O0(4,%R0),%1"
4330 [(set_attr "op_type" "SS")
4331 (set_attr "atype" "mem")])
4332
4333 ;
4334 ; andhi3 instruction pattern(s).
4335 ;
4336
4337 (define_insn "*andhi3_ni"
4338 [(set (match_operand:HI 0 "register_operand" "=d,d")
4339 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4340 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4341 (clobber (reg:CC 33))]
4342 "TARGET_64BIT"
4343 "@
4344 nr\\t%0,%2
4345 nill\\t%0,%x2"
4346 [(set_attr "op_type" "RR,RI")
4347 (set_attr "atype" "reg")])
4348
4349 (define_insn "andhi3"
4350 [(set (match_operand:HI 0 "register_operand" "=d")
4351 (and:HI (match_operand:HI 1 "register_operand" "%0")
4352 (match_operand:HI 2 "nonmemory_operand" "d")))
4353 (clobber (reg:CC 33))]
4354 ""
4355 "nr\\t%0,%2"
4356 [(set_attr "op_type" "RR")
4357 (set_attr "atype" "reg")])
4358
4359 (define_insn "*andhi3_ss"
4360 [(set (match_operand:HI 0 "s_operand" "=Q")
4361 (and:HI (match_dup 0)
4362 (match_operand:HI 1 "s_imm_operand" "Q")))
4363 (clobber (reg:CC 33))]
4364 ""
4365 "nc\\t%O0(2,%R0),%1"
4366 [(set_attr "op_type" "SS")
4367 (set_attr "atype" "mem")])
4368
4369 (define_insn "*andhi3_ss_inv"
4370 [(set (match_operand:HI 0 "s_operand" "=Q")
4371 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4372 (match_dup 0)))
4373 (clobber (reg:CC 33))]
4374 ""
4375 "nc\\t%O0(2,%R0),%1"
4376 [(set_attr "op_type" "SS")
4377 (set_attr "atype" "mem")])
4378
4379 ;
4380 ; andqi3 instruction pattern(s).
4381 ;
4382
4383 (define_insn "*andqi3_ni"
4384 [(set (match_operand:QI 0 "register_operand" "=d,d")
4385 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4386 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4387 (clobber (reg:CC 33))]
4388 "TARGET_64BIT"
4389 "@
4390 nr\\t%0,%2
4391 nill\\t%0,%b2"
4392 [(set_attr "op_type" "RR,RI")
4393 (set_attr "atype" "reg")])
4394
4395 (define_insn "andqi3"
4396 [(set (match_operand:QI 0 "register_operand" "=d")
4397 (and:QI (match_operand:QI 1 "register_operand" "%0")
4398 (match_operand:QI 2 "nonmemory_operand" "d")))
4399 (clobber (reg:CC 33))]
4400 ""
4401 "nr\\t%0,%2"
4402 [(set_attr "op_type" "RR")
4403 (set_attr "atype" "reg")])
4404
4405 (define_insn "*andqi3_ss"
4406 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4407 (and:QI (match_dup 0)
4408 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4409 (clobber (reg:CC 33))]
4410 ""
4411 "@
4412 ni\\t%0,%b1
4413 nc\\t%O0(1,%R0),%1"
4414 [(set_attr "op_type" "SI,SS")
4415 (set_attr "atype" "mem")])
4416
4417 (define_insn "*andqi3_ss_inv"
4418 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4419 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4420 (match_dup 0)))
4421 (clobber (reg:CC 33))]
4422 ""
4423 "@
4424 ni\\t%0,%b1
4425 nc\\t%O0(1,%R0),%1"
4426 [(set_attr "op_type" "SI,SS")
4427 (set_attr "atype" "mem")])
4428
4429
4430 ;;
4431 ;;- Bit set (inclusive or) instructions.
4432 ;;
4433
4434 ;
4435 ; iordi3 instruction pattern(s).
4436 ;
4437
4438 (define_insn "*iordi3_cc"
4439 [(set (reg 33)
4440 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4441 (match_operand:DI 2 "general_operand" "d,m"))
4442 (const_int 0)))
4443 (set (match_operand:DI 0 "register_operand" "=d,d")
4444 (ior:DI (match_dup 1) (match_dup 2)))]
4445 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4446 "@
4447 ogr\\t%0,%2
4448 og\\t%0,%2"
4449 [(set_attr "op_type" "RRE,RXE")
4450 (set_attr "atype" "reg,mem")])
4451
4452 (define_insn "*iordi3_cconly"
4453 [(set (reg 33)
4454 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4455 (match_operand:DI 2 "general_operand" "d,m"))
4456 (const_int 0)))
4457 (clobber (match_scratch:DI 0 "=d,d"))]
4458 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4459 "@
4460 ogr\\t%0,%2
4461 og\\t%0,%2"
4462 [(set_attr "op_type" "RRE,RXE")
4463 (set_attr "atype" "reg,mem")])
4464
4465 (define_insn "*iordi3_oi"
4466 [(set (match_operand:DI 0 "register_operand" "=d")
4467 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4468 (match_operand:DI 2 "immediate_operand" "n")))
4469 (clobber (reg:CC 33))]
4470 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4471 "*
4472 {
4473 int part = s390_single_hi (operands[2], DImode, 0);
4474 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4475
4476 switch (part)
4477 {
4478 case 0: return \"oihh\\t%0,%x2\";
4479 case 1: return \"oihl\\t%0,%x2\";
4480 case 2: return \"oilh\\t%0,%x2\";
4481 case 3: return \"oill\\t%0,%x2\";
4482 default: abort ();
4483 }
4484 }"
4485 [(set_attr "op_type" "RI")
4486 (set_attr "atype" "reg")])
4487
4488 (define_insn "iordi3"
4489 [(set (match_operand:DI 0 "register_operand" "=d,d")
4490 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4491 (match_operand:DI 2 "general_operand" "d,m")))
4492 (clobber (reg:CC 33))]
4493 "TARGET_64BIT"
4494 "@
4495 ogr\\t%0,%2
4496 og\\t%0,%2"
4497 [(set_attr "op_type" "RRE,RXE")
4498 (set_attr "atype" "reg,mem")])
4499
4500 (define_insn "*iordi3_ss"
4501 [(set (match_operand:DI 0 "s_operand" "=Q")
4502 (ior:DI (match_dup 0)
4503 (match_operand:DI 1 "s_imm_operand" "Q")))
4504 (clobber (reg:CC 33))]
4505 ""
4506 "oc\\t%O0(8,%R0),%1"
4507 [(set_attr "op_type" "SS")
4508 (set_attr "atype" "mem")])
4509
4510 (define_insn "*iordi3_ss_inv"
4511 [(set (match_operand:DI 0 "s_operand" "=Q")
4512 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4513 (match_dup 0)))
4514 (clobber (reg:CC 33))]
4515 ""
4516 "oc\\t%O0(8,%R0),%1"
4517 [(set_attr "op_type" "SS")
4518 (set_attr "atype" "mem")])
4519
4520 ;
4521 ; iorsi3 instruction pattern(s).
4522 ;
4523
4524 (define_insn "*iorsi3_cc"
4525 [(set (reg 33)
4526 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4527 (match_operand:SI 2 "general_operand" "d,m"))
4528 (const_int 0)))
4529 (set (match_operand:SI 0 "register_operand" "=d,d")
4530 (ior:SI (match_dup 1) (match_dup 2)))]
4531 "s390_match_ccmode(insn, CCTmode)"
4532 "@
4533 or\\t%0,%2
4534 o\\t%0,%2"
4535 [(set_attr "op_type" "RR,RX")
4536 (set_attr "atype" "reg,mem")])
4537
4538 (define_insn "*iorsi3_cconly"
4539 [(set (reg 33)
4540 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4541 (match_operand:SI 2 "general_operand" "d,m"))
4542 (const_int 0)))
4543 (clobber (match_scratch:SI 0 "=d,d"))]
4544 "s390_match_ccmode(insn, CCTmode)"
4545 "@
4546 or\\t%0,%2
4547 o\\t%0,%2"
4548 [(set_attr "op_type" "RR,RX")
4549 (set_attr "atype" "reg,mem")])
4550
4551 (define_insn "*iorsi3_oi"
4552 [(set (match_operand:SI 0 "register_operand" "=d")
4553 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4554 (match_operand:SI 2 "immediate_operand" "n")))
4555 (clobber (reg:CC 33))]
4556 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4557 "*
4558 {
4559 int part = s390_single_hi (operands[2], SImode, 0);
4560 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4561
4562 switch (part)
4563 {
4564 case 0: return \"oilh\\t%0,%x2\";
4565 case 1: return \"oill\\t%0,%x2\";
4566 default: abort ();
4567 }
4568 }"
4569 [(set_attr "op_type" "RI")
4570 (set_attr "atype" "reg")])
4571
4572 (define_insn "iorsi3"
4573 [(set (match_operand:SI 0 "register_operand" "=d,d")
4574 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4575 (match_operand:SI 2 "general_operand" "d,m")))
4576 (clobber (reg:CC 33))]
4577 ""
4578 "@
4579 or\\t%0,%2
4580 o\\t%0,%2"
4581 [(set_attr "op_type" "RR,RX")
4582 (set_attr "atype" "reg,mem")])
4583
4584 (define_insn "*iorsi3_ss"
4585 [(set (match_operand:SI 0 "s_operand" "=Q")
4586 (ior:SI (match_dup 0)
4587 (match_operand:SI 1 "s_imm_operand" "Q")))
4588 (clobber (reg:CC 33))]
4589 ""
4590 "oc\\t%O0(4,%R0),%1"
4591 [(set_attr "op_type" "SS")
4592 (set_attr "atype" "mem")])
4593
4594 (define_insn "*iorsi3_ss_inv"
4595 [(set (match_operand:SI 0 "s_operand" "=Q")
4596 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4597 (match_dup 0)))
4598 (clobber (reg:CC 33))]
4599 ""
4600 "oc\\t%O0(4,%R0),%1"
4601 [(set_attr "op_type" "SS")
4602 (set_attr "atype" "mem")])
4603
4604 ;
4605 ; iorhi3 instruction pattern(s).
4606 ;
4607
4608 (define_insn "*iorhi3_oi"
4609 [(set (match_operand:HI 0 "register_operand" "=d,d")
4610 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4611 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4612 (clobber (reg:CC 33))]
4613 "TARGET_64BIT"
4614 "@
4615 or\\t%0,%2
4616 oill\\t%0,%x2"
4617 [(set_attr "op_type" "RR,RI")
4618 (set_attr "atype" "reg")])
4619
4620 (define_insn "iorhi3"
4621 [(set (match_operand:HI 0 "register_operand" "=d")
4622 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4623 (match_operand:HI 2 "nonmemory_operand" "d")))
4624 (clobber (reg:CC 33))]
4625 ""
4626 "or\\t%0,%2"
4627 [(set_attr "op_type" "RR")
4628 (set_attr "atype" "reg")])
4629
4630 (define_insn "*iorhi3_ss"
4631 [(set (match_operand:HI 0 "s_operand" "=Q")
4632 (ior:HI (match_dup 0)
4633 (match_operand:HI 1 "s_imm_operand" "Q")))
4634 (clobber (reg:CC 33))]
4635 ""
4636 "oc\\t%O0(2,%R0),%1"
4637 [(set_attr "op_type" "SS")
4638 (set_attr "atype" "mem")])
4639
4640 (define_insn "*iorhi3_ss_inv"
4641 [(set (match_operand:HI 0 "s_operand" "=Q")
4642 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4643 (match_dup 0)))
4644 (clobber (reg:CC 33))]
4645 ""
4646 "oc\\t%O0(2,%R0),%1"
4647 [(set_attr "op_type" "SS")
4648 (set_attr "atype" "mem")])
4649
4650 ;
4651 ; iorqi3 instruction pattern(s).
4652 ;
4653
4654 (define_insn "*iorqi3_oi"
4655 [(set (match_operand:QI 0 "register_operand" "=d,d")
4656 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4657 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4658 (clobber (reg:CC 33))]
4659 "TARGET_64BIT"
4660 "@
4661 or\\t%0,%2
4662 oill\\t%0,%b2"
4663 [(set_attr "op_type" "RR,RI")
4664 (set_attr "atype" "reg")])
4665
4666 (define_insn "iorqi3"
4667 [(set (match_operand:QI 0 "register_operand" "=d")
4668 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4669 (match_operand:QI 2 "nonmemory_operand" "d")))
4670 (clobber (reg:CC 33))]
4671 ""
4672 "or\\t%0,%2"
4673 [(set_attr "op_type" "RR")
4674 (set_attr "atype" "reg")])
4675
4676 (define_insn "*iorqi3_ss"
4677 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4678 (ior:QI (match_dup 0)
4679 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4680 (clobber (reg:CC 33))]
4681 ""
4682 "@
4683 oi\\t%0,%b1
4684 oc\\t%O0(1,%R0),%1"
4685 [(set_attr "op_type" "SI,SS")
4686 (set_attr "atype" "reg,mem")])
4687
4688 (define_insn "*iorqi3_ss_inv"
4689 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4690 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4691 (match_dup 0)))
4692 (clobber (reg:CC 33))]
4693 ""
4694 "@
4695 oi\\t%0,%b1
4696 oc\\t%O0(1,%R0),%1"
4697 [(set_attr "op_type" "SI,SS")
4698 (set_attr "atype" "reg,mem")])
4699
4700
4701 ;;
4702 ;;- Xor instructions.
4703 ;;
4704
4705 ;
4706 ; xordi3 instruction pattern(s).
4707 ;
4708
4709 (define_insn "*xordi3_cc"
4710 [(set (reg 33)
4711 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4712 (match_operand:DI 2 "general_operand" "d,m"))
4713 (const_int 0)))
4714 (set (match_operand:DI 0 "register_operand" "=d,d")
4715 (xor:DI (match_dup 1) (match_dup 2)))]
4716 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4717 "@
4718 xgr\\t%0,%2
4719 xg\\t%0,%2"
4720 [(set_attr "op_type" "RRE,RXE")
4721 (set_attr "atype" "reg,mem")])
4722
4723 (define_insn "*xordi3_cconly"
4724 [(set (reg 33)
4725 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4726 (match_operand:DI 2 "general_operand" "d,m"))
4727 (const_int 0)))
4728 (clobber (match_scratch:DI 0 "=d,d"))]
4729 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4730 "@
4731 xgr\\t%0,%2
4732 xr\\t%0,%2"
4733 [(set_attr "op_type" "RRE,RXE")
4734 (set_attr "atype" "reg,mem")])
4735
4736 (define_insn "xordi3"
4737 [(set (match_operand:DI 0 "register_operand" "=d,d")
4738 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4739 (match_operand:DI 2 "general_operand" "d,m")))
4740 (clobber (reg:CC 33))]
4741 "TARGET_64BIT"
4742 "@
4743 xgr\\t%0,%2
4744 xg\\t%0,%2"
4745 [(set_attr "op_type" "RRE,RXE")
4746 (set_attr "atype" "reg,mem")])
4747
4748 (define_insn "*xordi3_ss"
4749 [(set (match_operand:DI 0 "s_operand" "=Q")
4750 (xor:DI (match_dup 0)
4751 (match_operand:DI 1 "s_imm_operand" "Q")))
4752 (clobber (reg:CC 33))]
4753 ""
4754 "xc\\t%O0(8,%R0),%1"
4755 [(set_attr "op_type" "SS")
4756 (set_attr "atype" "mem")])
4757
4758 (define_insn "*xordi3_ss_inv"
4759 [(set (match_operand:DI 0 "s_operand" "=Q")
4760 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4761 (match_dup 0)))
4762 (clobber (reg:CC 33))]
4763 ""
4764 "xc\\t%O0(8,%R0),%1"
4765 [(set_attr "op_type" "SS")
4766 (set_attr "atype" "mem")])
4767
4768 ;
4769 ; xorsi3 instruction pattern(s).
4770 ;
4771
4772 (define_insn "*xorsi3_cc"
4773 [(set (reg 33)
4774 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4775 (match_operand:SI 2 "general_operand" "d,m"))
4776 (const_int 0)))
4777 (set (match_operand:SI 0 "register_operand" "=d,d")
4778 (xor:SI (match_dup 1) (match_dup 2)))]
4779 "s390_match_ccmode(insn, CCTmode)"
4780 "@
4781 xr\\t%0,%2
4782 x\\t%0,%2"
4783 [(set_attr "op_type" "RR,RX")
4784 (set_attr "atype" "reg,mem")])
4785
4786 (define_insn "*xorsi3_cconly"
4787 [(set (reg 33)
4788 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4789 (match_operand:SI 2 "general_operand" "d,m"))
4790 (const_int 0)))
4791 (clobber (match_scratch:SI 0 "=d,d"))]
4792 "s390_match_ccmode(insn, CCTmode)"
4793 "@
4794 xr\\t%0,%2
4795 x\\t%0,%2"
4796 [(set_attr "op_type" "RR,RX")
4797 (set_attr "atype" "reg,mem")])
4798
4799 (define_insn "xorsi3"
4800 [(set (match_operand:SI 0 "register_operand" "=d,d")
4801 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4802 (match_operand:SI 2 "general_operand" "d,m")))
4803 (clobber (reg:CC 33))]
4804 ""
4805 "@
4806 xr\\t%0,%2
4807 x\\t%0,%2"
4808 [(set_attr "op_type" "RR,RX")
4809 (set_attr "atype" "reg,mem")])
4810
4811 (define_insn "*xorsi3_ss"
4812 [(set (match_operand:SI 0 "s_operand" "=Q")
4813 (xor:SI (match_dup 0)
4814 (match_operand:SI 1 "s_imm_operand" "Q")))
4815 (clobber (reg:CC 33))]
4816 ""
4817 "xc\\t%O0(4,%R0),%1"
4818 [(set_attr "op_type" "SS")
4819 (set_attr "atype" "mem")])
4820
4821 (define_insn "*xorsi3_ss_inv"
4822 [(set (match_operand:SI 0 "s_operand" "=Q")
4823 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4824 (match_dup 0)))
4825 (clobber (reg:CC 33))]
4826 ""
4827 "xc\\t%O0(4,%R0),%1"
4828 [(set_attr "op_type" "SS")
4829 (set_attr "atype" "mem")])
4830
4831 ;
4832 ; xorhi3 instruction pattern(s).
4833 ;
4834
4835 (define_insn "xorhi3"
4836 [(set (match_operand:HI 0 "register_operand" "=d")
4837 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4838 (match_operand:HI 2 "nonmemory_operand" "d")))
4839 (clobber (reg:CC 33))]
4840 ""
4841 "xr\\t%0,%2"
4842 [(set_attr "op_type" "RR")
4843 (set_attr "atype" "reg")])
4844
4845 (define_insn "*xorhi3_ss"
4846 [(set (match_operand:HI 0 "s_operand" "=Q")
4847 (xor:HI (match_dup 0)
4848 (match_operand:HI 1 "s_imm_operand" "Q")))
4849 (clobber (reg:CC 33))]
4850 ""
4851 "xc\\t%O0(2,%R0),%1"
4852 [(set_attr "op_type" "SS")
4853 (set_attr "atype" "mem")])
4854
4855 (define_insn "*xorhi3_ss_inv"
4856 [(set (match_operand:HI 0 "s_operand" "=Q")
4857 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4858 (match_dup 0)))
4859 (clobber (reg:CC 33))]
4860 ""
4861 "xc\\t%O0(2,%R0),%1"
4862 [(set_attr "op_type" "SS")
4863 (set_attr "atype" "mem")])
4864
4865 ;
4866 ; xorqi3 instruction pattern(s).
4867 ;
4868
4869 (define_insn "xorqi3"
4870 [(set (match_operand:QI 0 "register_operand" "=d")
4871 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4872 (match_operand:QI 2 "nonmemory_operand" "d")))
4873 (clobber (reg:CC 33))]
4874 ""
4875 "xr\\t%0,%2"
4876 [(set_attr "op_type" "RR")
4877 (set_attr "atype" "reg")])
4878
4879 (define_insn "*xorqi3_ss"
4880 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4881 (xor:QI (match_dup 0)
4882 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4883 (clobber (reg:CC 33))]
4884 ""
4885 "@
4886 xi\\t%0,%b1
4887 xc\\t%O0(1,%R0),%1"
4888 [(set_attr "op_type" "SI,SS")
4889 (set_attr "atype" "mem")])
4890
4891 (define_insn "*xorqi3_ss_inv"
4892 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4893 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4894 (match_dup 0)))
4895 (clobber (reg:CC 33))]
4896 ""
4897 "@
4898 xi\\t%0,%b1
4899 xc\\t%O0(1,%R0),%1"
4900 [(set_attr "op_type" "SI,SS")
4901 (set_attr "atype" "mem")])
4902
4903
4904 ;;
4905 ;;- Negate instructions.
4906 ;;
4907
4908 ;
4909 ; negdi2 instruction pattern(s).
4910 ;
4911
4912 (define_expand "negdi2"
4913 [(parallel
4914 [(set (match_operand:DI 0 "register_operand" "=d")
4915 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4916 (clobber (reg:CC 33))])]
4917 ""
4918 "")
4919
4920 (define_insn "*negdi2_64"
4921 [(set (match_operand:DI 0 "register_operand" "=d")
4922 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4923 (clobber (reg:CC 33))]
4924 "TARGET_64BIT"
4925 "lcgr\\t%0,%1"
4926 [(set_attr "op_type" "RR")])
4927
4928 (define_insn "*negdi2_31"
4929 [(set (match_operand:DI 0 "register_operand" "=d")
4930 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4931 (clobber (reg:CC 33))]
4932 "!TARGET_64BIT"
4933 "*
4934 {
4935 rtx xop[1];
4936 xop[0] = gen_label_rtx ();
4937 output_asm_insn (\"lcr\\t%0,%1\", operands);
4938 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
4939 output_asm_insn (\"je\\t%l0\", xop);
4940 output_asm_insn (\"bctr\\t%0,0\", operands);
4941 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4942 CODE_LABEL_NUMBER (xop[0]));
4943 return \"\";
4944 }"
4945 [(set_attr "op_type" "NN")
4946 (set_attr "type" "other")
4947 (set_attr "length" "10")])
4948
4949 ;
4950 ; negsi2 instruction pattern(s).
4951 ;
4952
4953 (define_insn "negsi2"
4954 [(set (match_operand:SI 0 "register_operand" "=d")
4955 (neg:SI (match_operand:SI 1 "register_operand" "d")))
4956 (clobber (reg:CC 33))]
4957 ""
4958 "lcr\\t%0,%1"
4959 [(set_attr "op_type" "RR")])
4960
4961 ;
4962 ; negdf2 instruction pattern(s).
4963 ;
4964
4965 (define_expand "negdf2"
4966 [(parallel
4967 [(set (match_operand:DF 0 "register_operand" "=f")
4968 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4969 (clobber (reg:CC 33))])]
4970 "TARGET_HARD_FLOAT"
4971 "")
4972
4973 (define_insn "*negdf2"
4974 [(set (match_operand:DF 0 "register_operand" "=f")
4975 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4976 (clobber (reg:CC 33))]
4977 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4978 "lcdbr\\t%0,%1"
4979 [(set_attr "op_type" "RRE")])
4980
4981 (define_insn "*negdf2_ibm"
4982 [(set (match_operand:DF 0 "register_operand" "=f")
4983 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4984 (clobber (reg:CC 33))]
4985 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4986 "lcdr\\t%0,%1"
4987 [(set_attr "op_type" "RR")])
4988
4989 ;
4990 ; negsf2 instruction pattern(s).
4991 ;
4992
4993 (define_expand "negsf2"
4994 [(parallel
4995 [(set (match_operand:SF 0 "register_operand" "=f")
4996 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4997 (clobber (reg:CC 33))])]
4998 "TARGET_HARD_FLOAT"
4999 "")
5000
5001 (define_insn "*negsf2"
5002 [(set (match_operand:SF 0 "register_operand" "=f")
5003 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5004 (clobber (reg:CC 33))]
5005 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5006 "lcebr\\t%0,%1"
5007 [(set_attr "op_type" "RRE")])
5008
5009 (define_insn "*negsf2"
5010 [(set (match_operand:SF 0 "register_operand" "=f")
5011 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5012 (clobber (reg:CC 33))]
5013 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5014 "lcer\\t%0,%1"
5015 [(set_attr "op_type" "RR")])
5016
5017
5018 ;;
5019 ;;- Absolute value instructions.
5020 ;;
5021
5022 ;
5023 ; absdi2 instruction pattern(s).
5024 ;
5025
5026 (define_insn "absdi2"
5027 [(set (match_operand:DI 0 "register_operand" "=d")
5028 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5029 (clobber (reg:CC 33))]
5030 "TARGET_64BIT"
5031 "lpgr\\t%0,%1"
5032 [(set_attr "op_type" "RRE")])
5033
5034 ;
5035 ; abssi2 instruction pattern(s).
5036 ;
5037
5038 (define_insn "abssi2"
5039 [(set (match_operand:SI 0 "register_operand" "=d")
5040 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5041 (clobber (reg:CC 33))]
5042 ""
5043 "lpr\\t%0,%1"
5044 [(set_attr "op_type" "RR")])
5045
5046 ;
5047 ; absdf2 instruction pattern(s).
5048 ;
5049
5050 (define_expand "absdf2"
5051 [(parallel
5052 [(set (match_operand:DF 0 "register_operand" "=f")
5053 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5054 (clobber (reg:CC 33))])]
5055 "TARGET_HARD_FLOAT"
5056 "")
5057
5058 (define_insn "*absdf2"
5059 [(set (match_operand:DF 0 "register_operand" "=f")
5060 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5061 (clobber (reg:CC 33))]
5062 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5063 "lpdbr\\t%0,%1"
5064 [(set_attr "op_type" "RRE")])
5065
5066 (define_insn "*absdf2_ibm"
5067 [(set (match_operand:DF 0 "register_operand" "=f")
5068 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5069 (clobber (reg:CC 33))]
5070 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5071 "lpdr\\t%0,%1"
5072 [(set_attr "op_type" "RR")])
5073
5074 ;
5075 ; abssf2 instruction pattern(s).
5076 ;
5077
5078 (define_expand "abssf2"
5079 [(parallel
5080 [(set (match_operand:SF 0 "register_operand" "=f")
5081 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5082 (clobber (reg:CC 33))])]
5083 "TARGET_HARD_FLOAT"
5084 "")
5085
5086 (define_insn "*abssf2"
5087 [(set (match_operand:SF 0 "register_operand" "=f")
5088 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5089 (clobber (reg:CC 33))]
5090 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5091 "lpebr\\t%0,%1"
5092 [(set_attr "op_type" "RRE")])
5093
5094 (define_insn "*abssf2_ibm"
5095 [(set (match_operand:SF 0 "register_operand" "=f")
5096 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5097 (clobber (reg:CC 33))]
5098 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5099 "lper\\t%0,%1"
5100 [(set_attr "op_type" "RR")])
5101
5102 ;;
5103 ;;- Square root instructions.
5104 ;;
5105
5106 ;
5107 ; sqrtdf2 instruction pattern(s).
5108 ;
5109
5110 (define_insn "sqrtdf2"
5111 [(set (match_operand:DF 0 "register_operand" "=f,f")
5112 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5113 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5114 "@
5115 sqdbr\\t%0,%1
5116 sqdb\\t%0,%1"
5117 [(set_attr "op_type" "RRE,RSE")])
5118
5119 ;
5120 ; sqrtsf2 instruction pattern(s).
5121 ;
5122
5123 (define_insn "sqrtsf2"
5124 [(set (match_operand:SF 0 "register_operand" "=f,f")
5125 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5126 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5127 "@
5128 sqebr\\t%0,%1
5129 sqeb\\t%0,%1"
5130 [(set_attr "op_type" "RRE,RSE")])
5131
5132 ;;
5133 ;;- One complement instructions.
5134 ;;
5135
5136 ;
5137 ; one_cmpldi2 instruction pattern(s).
5138 ;
5139
5140 (define_expand "one_cmpldi2"
5141 [(parallel
5142 [(set (match_operand:DI 0 "register_operand" "")
5143 (xor:DI (match_operand:DI 1 "register_operand" "")
5144 (const_int -1)))
5145 (clobber (reg:CC 33))])]
5146 "TARGET_64BIT"
5147 "")
5148
5149 ;
5150 ; one_cmplsi2 instruction pattern(s).
5151 ;
5152
5153 (define_expand "one_cmplsi2"
5154 [(parallel
5155 [(set (match_operand:SI 0 "register_operand" "")
5156 (xor:SI (match_operand:SI 1 "register_operand" "")
5157 (const_int -1)))
5158 (clobber (reg:CC 33))])]
5159 ""
5160 "")
5161
5162 ;
5163 ; one_cmplhi2 instruction pattern(s).
5164 ;
5165
5166 (define_expand "one_cmplhi2"
5167 [(parallel
5168 [(set (match_operand:HI 0 "register_operand" "")
5169 (xor:HI (match_operand:HI 1 "register_operand" "")
5170 (const_int -1)))
5171 (clobber (reg:CC 33))])]
5172 ""
5173 "")
5174
5175 ;
5176 ; one_cmplqi2 instruction pattern(s).
5177 ;
5178
5179 (define_expand "one_cmplqi2"
5180 [(parallel
5181 [(set (match_operand:QI 0 "register_operand" "")
5182 (xor:QI (match_operand:QI 1 "register_operand" "")
5183 (const_int -1)))
5184 (clobber (reg:CC 33))])]
5185 ""
5186 "")
5187
5188
5189 ;;
5190 ;;- Rotate instructions.
5191 ;;
5192
5193 ;
5194 ; rotldi3 instruction pattern(s).
5195 ;
5196
5197 (define_insn "rotldi3"
5198 [(set (match_operand:DI 0 "register_operand" "=d,d")
5199 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5200 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5201 "TARGET_64BIT"
5202 "@
5203 rllg\\t%0,%1,%c2
5204 rllg\\t%0,%1,0(%2)"
5205 [(set_attr "op_type" "RSE")])
5206
5207 ;
5208 ; rotlsi3 instruction pattern(s).
5209 ;
5210
5211 (define_insn "rotlsi3"
5212 [(set (match_operand:SI 0 "register_operand" "=d,d")
5213 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5214 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5215 "TARGET_64BIT"
5216 "@
5217 rll\\t%0,%1,%c2
5218 rll\\t%0,%1,0(%2)"
5219 [(set_attr "op_type" "RSE")])
5220
5221
5222 ;;
5223 ;;- Arithmetic shift instructions.
5224 ;;
5225
5226 ;
5227 ; ashldi3 instruction pattern(s).
5228 ;
5229
5230 (define_expand "ashldi3"
5231 [(set (match_operand:DI 0 "register_operand" "")
5232 (ashift:DI (match_operand:DI 1 "register_operand" "")
5233 (match_operand:SI 2 "nonmemory_operand" "")))]
5234 ""
5235 "")
5236
5237 (define_insn "*ashldi3_31"
5238 [(set (match_operand:DI 0 "register_operand" "=d,d")
5239 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5240 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5241 "!TARGET_64BIT"
5242 "@
5243 sldl\\t%0,%c2
5244 sldl\\t%0,0(%2)"
5245 [(set_attr "op_type" "RS")])
5246
5247 (define_insn "*ashldi3_64"
5248 [(set (match_operand:DI 0 "register_operand" "=d,d")
5249 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5250 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5251 "TARGET_64BIT"
5252 "@
5253 sllg\\t%0,%1,%2
5254 sllg\\t%0,%1,0(%2)"
5255 [(set_attr "op_type" "RSE")])
5256
5257 ;
5258 ; ashrdi3 instruction pattern(s).
5259 ;
5260
5261 (define_expand "ashrdi3"
5262 [(parallel
5263 [(set (match_operand:DI 0 "register_operand" "")
5264 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5265 (match_operand:SI 2 "nonmemory_operand" "")))
5266 (clobber (reg:CC 33))])]
5267 ""
5268 "")
5269
5270 (define_insn "*ashrdi3_cc_31"
5271 [(set (reg 33)
5272 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5273 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5274 (const_int 0)))
5275 (set (match_operand:DI 0 "register_operand" "=d,d")
5276 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5277 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5278 "@
5279 srda\\t%0,%c2
5280 srda\\t%0,0(%2)"
5281 [(set_attr "op_type" "RS")])
5282
5283 (define_insn "*ashrdi3_cconly_31"
5284 [(set (reg 33)
5285 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5286 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5287 (const_int 0)))
5288 (clobber (match_scratch:DI 0 "=d,d"))]
5289 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5290 "@
5291 srda\\t%0,%c2
5292 srda\\t%0,0(%2)"
5293 [(set_attr "op_type" "RS")])
5294
5295 (define_insn "*ashrdi3_31"
5296 [(set (match_operand:DI 0 "register_operand" "=d,d")
5297 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5298 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5299 (clobber (reg:CC 33))]
5300 "!TARGET_64BIT"
5301 "@
5302 srda\\t%0,%c2
5303 srda\\t%0,0(%2)"
5304 [(set_attr "op_type" "RS")])
5305
5306 (define_insn "*ashrdi3_cc_64"
5307 [(set (reg 33)
5308 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5309 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5310 (const_int 0)))
5311 (set (match_operand:DI 0 "register_operand" "=d,d")
5312 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5313 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5314 "@
5315 srag\\t%0,%1,%c2
5316 srag\\t%0,%1,0(%2)"
5317 [(set_attr "op_type" "RSE")])
5318
5319 (define_insn "*ashrdi3_cconly_64"
5320 [(set (reg 33)
5321 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5322 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5323 (const_int 0)))
5324 (clobber (match_scratch:DI 0 "=d,d"))]
5325 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5326 "@
5327 srag\\t%0,%1,%c2
5328 srag\\t%0,%1,0(%2)"
5329 [(set_attr "op_type" "RSE")])
5330
5331 (define_insn "*ashrdi3_64"
5332 [(set (match_operand:DI 0 "register_operand" "=d,d")
5333 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5334 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5335 (clobber (reg:CC 33))]
5336 "TARGET_64BIT"
5337 "@
5338 srag\\t%0,%1,%c2
5339 srag\\t%0,%1,0(%2)"
5340 [(set_attr "op_type" "RSE")])
5341
5342 ;
5343 ; ashlsi3 instruction pattern(s).
5344 ;
5345
5346 (define_insn "ashlsi3"
5347 [(set (match_operand:SI 0 "register_operand" "=d,d")
5348 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5349 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5350 ""
5351 "@
5352 sll\\t%0,%c2
5353 sll\\t%0,0(%2)"
5354 [(set_attr "op_type" "RS")])
5355
5356 ;
5357 ; ashrsi3 instruction pattern(s).
5358 ;
5359
5360 (define_insn "*ashrsi3_cc"
5361 [(set (reg 33)
5362 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5363 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5364 (const_int 0)))
5365 (set (match_operand:SI 0 "register_operand" "=d,d")
5366 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5367 "s390_match_ccmode(insn, CCSmode)"
5368 "@
5369 sra\\t%0,%c2
5370 sra\\t%0,0(%2)"
5371 [(set_attr "op_type" "RS")])
5372
5373 (define_insn "*ashrsi3_cconly"
5374 [(set (reg 33)
5375 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5376 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5377 (const_int 0)))
5378 (clobber (match_scratch:SI 0 "=d,d"))]
5379 "s390_match_ccmode(insn, CCSmode)"
5380 "@
5381 sra\\t%0,%c2
5382 sra\\t%0,0(%2)"
5383 [(set_attr "op_type" "RS")])
5384
5385 (define_insn "ashrsi3"
5386 [(set (match_operand:SI 0 "register_operand" "=d,d")
5387 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5388 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5389 (clobber (reg:CC 33))]
5390 ""
5391 "@
5392 sra\\t%0,%c2
5393 sra\\t%0,0(%2)"
5394 [(set_attr "op_type" "RS")])
5395
5396
5397 ;;
5398 ;;- logical shift instructions.
5399 ;;
5400
5401 ;
5402 ; lshrdi3 instruction pattern(s).
5403 ;
5404
5405 (define_expand "lshrdi3"
5406 [(set (match_operand:DI 0 "register_operand" "")
5407 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5408 (match_operand:SI 2 "nonmemory_operand" "")))]
5409 ""
5410 "")
5411
5412 (define_insn "*lshrdi3_31"
5413 [(set (match_operand:DI 0 "register_operand" "=d,d")
5414 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5415 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5416 "!TARGET_64BIT"
5417 "@
5418 srdl\\t%0,%c2
5419 srdl\\t%0,0(%2)"
5420 [(set_attr "op_type" "RS,RS")])
5421
5422 (define_insn "*lshrdi3_64"
5423 [(set (match_operand:DI 0 "register_operand" "=d,d")
5424 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5425 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5426 "TARGET_64BIT"
5427 "@
5428 srlg\\t%0,%1,%c2
5429 srlg\\t%0,%1,0(%2)"
5430 [(set_attr "op_type" "RS,RS")])
5431
5432 ;
5433 ; lshrsi3 instruction pattern(s).
5434 ;
5435
5436 (define_insn "lshrsi3"
5437 [(set (match_operand:SI 0 "register_operand" "=d,d")
5438 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5439 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5440 ""
5441 "@
5442 srl\\t%0,%c2
5443 srl\\t%0,0(%2)"
5444 [(set_attr "op_type" "RS")])
5445
5446
5447 ;;
5448 ;; Branch instruction patterns.
5449 ;;
5450
5451 (define_expand "beq"
5452 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5453 (set (pc)
5454 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5455 (label_ref (match_operand 0 "" ""))
5456 (pc)))]
5457 ""
5458 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5459
5460 (define_expand "bne"
5461 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5462 (set (pc)
5463 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5464 (label_ref (match_operand 0 "" ""))
5465 (pc)))]
5466 ""
5467 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5468
5469 (define_expand "bgt"
5470 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5471 (set (pc)
5472 (if_then_else (gt (reg:CCS 33) (const_int 0))
5473 (label_ref (match_operand 0 "" ""))
5474 (pc)))]
5475 ""
5476 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5477
5478 (define_expand "bgtu"
5479 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5480 (set (pc)
5481 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5482 (label_ref (match_operand 0 "" ""))
5483 (pc)))]
5484 ""
5485 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5486
5487 (define_expand "blt"
5488 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5489 (set (pc)
5490 (if_then_else (lt (reg:CCS 33) (const_int 0))
5491 (label_ref (match_operand 0 "" ""))
5492 (pc)))]
5493 ""
5494 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5495
5496 (define_expand "bltu"
5497 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5498 (set (pc)
5499 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5500 (label_ref (match_operand 0 "" ""))
5501 (pc)))]
5502 ""
5503 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5504
5505 (define_expand "bge"
5506 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5507 (set (pc)
5508 (if_then_else (ge (reg:CCS 33) (const_int 0))
5509 (label_ref (match_operand 0 "" ""))
5510 (pc)))]
5511 ""
5512 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5513
5514 (define_expand "bgeu"
5515 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5516 (set (pc)
5517 (if_then_else (geu (reg:CCU 33) (const_int 0))
5518 (label_ref (match_operand 0 "" ""))
5519 (pc)))]
5520 ""
5521 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5522
5523 (define_expand "ble"
5524 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5525 (set (pc)
5526 (if_then_else (le (reg:CCS 33) (const_int 0))
5527 (label_ref (match_operand 0 "" ""))
5528 (pc)))]
5529 ""
5530 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5531
5532 (define_expand "bleu"
5533 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5534 (set (pc)
5535 (if_then_else (leu (reg:CCU 33) (const_int 0))
5536 (label_ref (match_operand 0 "" ""))
5537 (pc)))]
5538 ""
5539 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5540
5541 (define_expand "bunordered"
5542 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5543 (set (pc)
5544 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5545 (label_ref (match_operand 0 "" ""))
5546 (pc)))]
5547 ""
5548 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5549
5550 (define_expand "bordered"
5551 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5552 (set (pc)
5553 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5554 (label_ref (match_operand 0 "" ""))
5555 (pc)))]
5556 ""
5557 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5558
5559 (define_expand "buneq"
5560 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5561 (set (pc)
5562 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5563 (label_ref (match_operand 0 "" ""))
5564 (pc)))]
5565 ""
5566 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5567
5568 (define_expand "bungt"
5569 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5570 (set (pc)
5571 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5572 (label_ref (match_operand 0 "" ""))
5573 (pc)))]
5574 ""
5575 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5576
5577 (define_expand "bunlt"
5578 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5579 (set (pc)
5580 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5581 (label_ref (match_operand 0 "" ""))
5582 (pc)))]
5583 ""
5584 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5585
5586 (define_expand "bunge"
5587 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5588 (set (pc)
5589 (if_then_else (unge (reg:CCS 33) (const_int 0))
5590 (label_ref (match_operand 0 "" ""))
5591 (pc)))]
5592 ""
5593 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5594
5595 (define_expand "bunle"
5596 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5597 (set (pc)
5598 (if_then_else (unle (reg:CCS 33) (const_int 0))
5599 (label_ref (match_operand 0 "" ""))
5600 (pc)))]
5601 ""
5602 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5603
5604 (define_expand "bltgt"
5605 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5606 (set (pc)
5607 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5608 (label_ref (match_operand 0 "" ""))
5609 (pc)))]
5610 ""
5611 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5612
5613
5614 ;;
5615 ;;- Conditional jump instructions.
5616 ;;
5617
5618 (define_insn "cjump"
5619 [(set (pc)
5620 (if_then_else
5621 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5622 (label_ref (match_operand 0 "" ""))
5623 (pc)))]
5624 ""
5625 "*
5626 {
5627 if (get_attr_length (insn) == 4)
5628 return \"j%C1\\t%l0\";
5629 else if (TARGET_64BIT)
5630 return \"jg%C1\\t%l0\";
5631 else
5632 abort ();
5633 }"
5634 [(set_attr "op_type" "RI")
5635 (set (attr "length")
5636 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5637 (const_int 4)
5638 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5639 (const_int 6)
5640 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5641 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5642 (const_int 12) (const_int 14))
5643 (eq (symbol_ref "flag_pic") (const_int 0))
5644 (const_int 6)] (const_int 8)))])
5645
5646 (define_insn "*cjump_long"
5647 [(set (pc)
5648 (if_then_else
5649 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5650 (match_operand 0 "address_operand" "p")
5651 (pc)))]
5652 ""
5653 "*
5654 {
5655 if (get_attr_op_type (insn) == OP_TYPE_RR)
5656 return \"b%C1r\\t%0\";
5657 else
5658 return \"b%C1\\t%a0\";
5659 }"
5660 [(set (attr "op_type")
5661 (if_then_else (match_operand 0 "register_operand" "")
5662 (const_string "RR") (const_string "RX")))
5663 (set_attr "atype" "mem")])
5664
5665
5666 ;;
5667 ;;- Negated conditional jump instructions.
5668 ;;
5669
5670 (define_insn "icjump"
5671 [(set (pc)
5672 (if_then_else
5673 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5674 (pc)
5675 (label_ref (match_operand 0 "" ""))))]
5676 ""
5677 "*
5678 {
5679 if (get_attr_length (insn) == 4)
5680 return \"j%D1\\t%l0\";
5681 else if (TARGET_64BIT)
5682 return \"jg%D1\\t%l0\";
5683 else
5684 abort ();
5685 }"
5686 [(set_attr "op_type" "RI")
5687 (set (attr "length")
5688 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5689 (const_int 4)
5690 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5691 (const_int 6)
5692 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5693 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5694 (const_int 12) (const_int 14))
5695 (eq (symbol_ref "flag_pic") (const_int 0))
5696 (const_int 6)] (const_int 8)))])
5697
5698 (define_insn "*icjump_long"
5699 [(set (pc)
5700 (if_then_else
5701 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5702 (pc)
5703 (match_operand 0 "address_operand" "p")))]
5704 ""
5705 "*
5706 {
5707 if (get_attr_op_type (insn) == OP_TYPE_RR)
5708 return \"b%D1r\\t%0\";
5709 else
5710 return \"b%D1\\t%a0\";
5711 }"
5712 [(set (attr "op_type")
5713 (if_then_else (match_operand 0 "register_operand" "")
5714 (const_string "RR") (const_string "RX")))
5715 (set_attr "atype" "mem")])
5716
5717 ;;
5718 ;;- Trap instructions.
5719 ;;
5720
5721 (define_insn "trap"
5722 [(trap_if (const_int 1) (const_int 0))]
5723 ""
5724 "j\\t.+2"
5725 [(set_attr "op_type" "RX")])
5726
5727 (define_expand "conditional_trap"
5728 [(set (match_dup 2) (match_dup 3))
5729 (trap_if (match_operator 0 "comparison_operator"
5730 [(match_dup 2) (const_int 0)])
5731 (match_operand:SI 1 "general_operand" ""))]
5732 ""
5733 "
5734 {
5735 enum machine_mode ccmode;
5736
5737 if (operands[1] != const0_rtx) FAIL;
5738
5739 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5740 s390_compare_op0, s390_compare_op1);
5741 operands[2] = gen_rtx_REG (ccmode, 33);
5742 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5743 }")
5744
5745 (define_insn "*trap"
5746 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5747 (const_int 0))]
5748 ""
5749 "j%C0\\t.+2";
5750 [(set_attr "op_type" "RX")])
5751
5752 ;;
5753 ;;- Loop instructions.
5754 ;;
5755 ;; This is all complicated by the fact that since this is a jump insn
5756 ;; we must handle our own output reloads.
5757
5758 (define_expand "doloop_end"
5759 [(use (match_operand 0 "" "")) ; loop pseudo
5760 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5761 (use (match_operand 2 "" "")) ; max iterations
5762 (use (match_operand 3 "" "")) ; loop level
5763 (use (match_operand 4 "" ""))] ; label
5764 ""
5765 "
5766 {
5767 if (GET_MODE (operands[0]) == SImode)
5768 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5769 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5770 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5771 else
5772 FAIL;
5773
5774 DONE;
5775 }")
5776
5777 (define_insn "doloop_si"
5778 [(set (pc)
5779 (if_then_else
5780 (ne (match_operand:SI 1 "register_operand" "d,d")
5781 (const_int 1))
5782 (label_ref (match_operand 0 "" ""))
5783 (pc)))
5784 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5785 (plus:SI (match_dup 1) (const_int -1)))
5786 (clobber (match_scratch:SI 3 "=X,&d"))
5787 (clobber (reg:CC 33))]
5788 ""
5789 "*
5790 {
5791 if (which_alternative != 0)
5792 return \"#\";
5793 else if (get_attr_length (insn) == 4)
5794 return \"brct\\t%1,%l0\";
5795 else
5796 abort ();
5797 }"
5798 [(set_attr "op_type" "RI")
5799 (set (attr "length")
5800 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5801 (const_int 4)
5802 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5803 (const_int 10)
5804 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5805 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5806 (const_int 12) (const_int 14))
5807 (eq (symbol_ref "flag_pic") (const_int 0))
5808 (const_int 6)] (const_int 8)))])
5809
5810 (define_insn "*doloop_si_long"
5811 [(set (pc)
5812 (if_then_else
5813 (ne (match_operand:SI 1 "register_operand" "d,d")
5814 (const_int 1))
5815 (match_operand 0 "address_operand" "p,p")
5816 (pc)))
5817 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5818 (plus:SI (match_dup 1) (const_int -1)))
5819 (clobber (match_scratch:SI 3 "=X,&d"))
5820 (clobber (reg:CC 33))]
5821 ""
5822 "*
5823 {
5824 if (get_attr_op_type (insn) == OP_TYPE_RR)
5825 return \"bctr\\t%0\";
5826 else
5827 return \"bct\\t%a0\";
5828 }"
5829 [(set (attr "op_type")
5830 (if_then_else (match_operand 0 "register_operand" "")
5831 (const_string "RR") (const_string "RX")))
5832 (set_attr "atype" "mem")])
5833
5834 (define_split
5835 [(set (pc)
5836 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5837 (const_int 1))
5838 (match_operand 0 "" "")
5839 (pc)))
5840 (set (match_operand:SI 2 "nonimmediate_operand" "")
5841 (plus:SI (match_dup 1) (const_int -1)))
5842 (clobber (match_scratch:SI 3 ""))
5843 (clobber (reg:CC 33))]
5844 "reload_completed
5845 && (! REG_P (operands[2])
5846 || ! rtx_equal_p (operands[1], operands[2]))"
5847 [(set (match_dup 3) (match_dup 1))
5848 (parallel [(set (reg:CCAN 33)
5849 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5850 (const_int 0)))
5851 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5852 (set (match_dup 2) (match_dup 3))
5853 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5854 (match_dup 0)
5855 (pc)))]
5856 "")
5857
5858 (define_insn "doloop_di"
5859 [(set (pc)
5860 (if_then_else
5861 (ne (match_operand:DI 1 "register_operand" "d,d")
5862 (const_int 1))
5863 (label_ref (match_operand 0 "" ""))
5864 (pc)))
5865 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
5866 (plus:DI (match_dup 1) (const_int -1)))
5867 (clobber (match_scratch:DI 3 "=X,&d"))
5868 (clobber (reg:CC 33))]
5869 "TARGET_64BIT"
5870 "*
5871 {
5872 if (which_alternative != 0)
5873 return \"#\";
5874 else if (get_attr_length (insn) == 4)
5875 return \"brctg\\t%1,%l0\";
5876 else
5877 abort ();
5878 }"
5879 [(set_attr "op_type" "RI")
5880 (set (attr "length")
5881 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5882 (const_int 4) (const_int 12)))])
5883
5884 (define_insn "*doloop_di_long"
5885 [(set (pc)
5886 (if_then_else
5887 (ne (match_operand:DI 1 "register_operand" "d,d")
5888 (const_int 1))
5889 (match_operand 0 "address_operand" "p,p")
5890 (pc)))
5891 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
5892 (plus:DI (match_dup 1) (const_int -1)))
5893 (clobber (match_scratch:DI 3 "=X,&d"))
5894 (clobber (reg:CC 33))]
5895 ""
5896 "*
5897 {
5898 if (get_attr_op_type (insn) == OP_TYPE_RRE)
5899 return \"bctgr\\t%0\";
5900 else
5901 return \"bctg\\t%a0\";
5902 }"
5903 [(set (attr "op_type")
5904 (if_then_else (match_operand 0 "register_operand" "")
5905 (const_string "RRE") (const_string "RXE")))
5906 (set_attr "atype" "mem")])
5907
5908 (define_split
5909 [(set (pc)
5910 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
5911 (const_int 1))
5912 (match_operand 0 "" "")
5913 (pc)))
5914 (set (match_operand:DI 2 "nonimmediate_operand" "")
5915 (plus:DI (match_dup 1) (const_int -1)))
5916 (clobber (match_scratch:DI 3 ""))
5917 (clobber (reg:CC 33))]
5918 "reload_completed
5919 && (! REG_P (operands[2])
5920 || ! rtx_equal_p (operands[1], operands[2]))"
5921 [(set (match_dup 3) (match_dup 1))
5922 (parallel [(set (reg:CCAN 33)
5923 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
5924 (const_int 0)))
5925 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
5926 (set (match_dup 2) (match_dup 3))
5927 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5928 (match_dup 0)
5929 (pc)))]
5930 "")
5931
5932 ;;
5933 ;;- Unconditional jump instructions.
5934 ;;
5935
5936 ;
5937 ; jump instruction pattern(s).
5938 ;
5939
5940 (define_insn "jump"
5941 [(set (pc) (label_ref (match_operand 0 "" "")))]
5942 ""
5943 "*
5944 {
5945 if (get_attr_length (insn) == 4)
5946 return \"j\\t%l0\";
5947 else if (TARGET_64BIT)
5948 return \"jg\\t%l0\";
5949 else
5950 abort ();
5951 }"
5952 [(set_attr "op_type" "RI")
5953 (set (attr "length")
5954 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5955 (const_int 4)
5956 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5957 (const_int 6)
5958 (eq (symbol_ref "flag_pic") (const_int 0))
5959 (const_int 6)] (const_int 8)))])
5960
5961 ;
5962 ; indirect-jump instruction pattern(s).
5963 ;
5964
5965 (define_insn "indirect_jump"
5966 [(set (pc) (match_operand 0 "address_operand" "p"))]
5967 ""
5968 "*
5969 {
5970 if (get_attr_op_type (insn) == OP_TYPE_RR)
5971 return \"br\\t%0\";
5972 else
5973 return \"b\\t%a0\";
5974 }"
5975 [(set (attr "op_type")
5976 (if_then_else (match_operand 0 "register_operand" "")
5977 (const_string "RR") (const_string "RX")))
5978 (set_attr "atype" "mem")])
5979
5980 ;
5981 ; casesi instruction pattern(s).
5982 ;
5983
5984 (define_insn "casesi_jump"
5985 [(set (pc) (match_operand 0 "address_operand" "p"))
5986 (use (label_ref (match_operand 1 "" "")))]
5987 ""
5988 "*
5989 {
5990 if (get_attr_op_type (insn) == OP_TYPE_RR)
5991 return \"br\\t%0\";
5992 else
5993 return \"b\\t%a0\";
5994 }"
5995 [(set (attr "op_type")
5996 (if_then_else (match_operand 0 "register_operand" "")
5997 (const_string "RR") (const_string "RX")))
5998 (set_attr "atype" "mem")])
5999
6000 (define_expand "casesi"
6001 [(match_operand:SI 0 "general_operand" "")
6002 (match_operand:SI 1 "general_operand" "")
6003 (match_operand:SI 2 "general_operand" "")
6004 (label_ref (match_operand 3 "" ""))
6005 (label_ref (match_operand 4 "" ""))]
6006 ""
6007 "
6008 {
6009 rtx index = gen_reg_rtx (SImode);
6010 rtx base = gen_reg_rtx (Pmode);
6011 rtx target = gen_reg_rtx (Pmode);
6012
6013 emit_move_insn (index, operands[0]);
6014 emit_insn (gen_subsi3 (index, index, operands[1]));
6015 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6016 operands[4]);
6017
6018 if (Pmode != SImode)
6019 index = convert_to_mode (Pmode, index, 1);
6020 if (GET_CODE (index) != REG)
6021 index = copy_to_mode_reg (Pmode, index);
6022
6023 if (TARGET_64BIT)
6024 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6025 else
6026 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6027
6028 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6029
6030 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6031 emit_move_insn (target, index);
6032
6033 if (flag_pic)
6034 target = gen_rtx_PLUS (Pmode, base, target);
6035 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6036
6037 DONE;
6038 }")
6039
6040
6041 ;;
6042 ;;- Jump to subroutine.
6043 ;;
6044 ;;
6045
6046 ;
6047 ; untyped call instruction pattern(s).
6048 ;
6049
6050 ;; Call subroutine returning any type.
6051 (define_expand "untyped_call"
6052 [(parallel [(call (match_operand 0 "" "")
6053 (const_int 0))
6054 (match_operand 1 "" "")
6055 (match_operand 2 "" "")])]
6056 ""
6057 "
6058 {
6059 int i;
6060
6061 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6062
6063 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6064 {
6065 rtx set = XVECEXP (operands[2], 0, i);
6066 emit_move_insn (SET_DEST (set), SET_SRC (set));
6067 }
6068
6069 /* The optimizer does not know that the call sets the function value
6070 registers we stored in the result block. We avoid problems by
6071 claiming that all hard registers are used and clobbered at this
6072 point. */
6073 emit_insn (gen_blockage ());
6074
6075 DONE;
6076 }")
6077
6078 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6079 ;; all of memory. This blocks insns from being moved across this point.
6080
6081 (define_insn "blockage"
6082 [(unspec_volatile [(const_int 0)] 0)]
6083 ""
6084 ""
6085 [(set_attr "type" "none")])
6086
6087
6088
6089 ;
6090 ; call instruction pattern(s).
6091 ;
6092
6093 (define_expand "call"
6094 [(call (match_operand 0 "" "")
6095 (match_operand 1 "" ""))
6096 (use (match_operand 2 "" ""))]
6097 ""
6098 "
6099 {
6100 int plt_call = 0;
6101 rtx insn;
6102
6103 /* Direct function calls need special treatment. */
6104 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6105 {
6106 rtx sym = XEXP (operands[0], 0);
6107
6108 /* When calling a global routine in PIC mode, we must
6109 replace the symbol itself with the PLT stub. */
6110 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6111 {
6112 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6113 sym = gen_rtx_CONST (Pmode, sym);
6114
6115 plt_call = 1;
6116 }
6117
6118 /* Unless we can use the bras(l) insn, force the
6119 routine address into a register. */
6120 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6121 {
6122 rtx target = gen_reg_rtx (Pmode);
6123 emit_move_insn (target, sym);
6124 sym = target;
6125 }
6126
6127 operands[0] = gen_rtx_MEM (QImode, sym);
6128 }
6129
6130 /* Emit insn. */
6131 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6132 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6133
6134 /* In 31-bit, we must load the GOT register even if the
6135 compiler doesn't know about it, because the PLT glue
6136 code uses it. In 64-bit, this is not necessary. */
6137 if (plt_call && !TARGET_64BIT)
6138 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6139
6140 DONE;
6141 }")
6142
6143 (define_expand "call_exp"
6144 [(parallel [(call (match_operand 0 "" "")
6145 (match_operand 1 "" ""))
6146 (clobber (match_operand 2 "" ""))])]
6147 ""
6148 "")
6149
6150 (define_insn "brasl"
6151 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6152 (match_operand:SI 1 "const_int_operand" "n"))
6153 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6154 "TARGET_64BIT"
6155 "brasl\\t%2,%0"
6156 [(set_attr "op_type" "RIL")
6157 (set_attr "type" "jsr")])
6158
6159 (define_insn "bras"
6160 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6161 (match_operand:SI 1 "const_int_operand" "n"))
6162 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6163 "TARGET_SMALL_EXEC"
6164 "bras\\t%2,%0"
6165 [(set_attr "op_type" "RI")
6166 (set_attr "type" "jsr")])
6167
6168 (define_insn "basr_64"
6169 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6170 (match_operand:SI 1 "const_int_operand" "n"))
6171 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6172 "TARGET_64BIT"
6173 "basr\\t%2,%0"
6174 [(set_attr "op_type" "RR")
6175 (set_attr "type" "jsr")
6176 (set_attr "atype" "mem")])
6177
6178 (define_insn "basr_31"
6179 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6180 (match_operand:SI 1 "const_int_operand" "n"))
6181 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6182 "!TARGET_64BIT"
6183 "basr\\t%2,%0"
6184 [(set_attr "op_type" "RR")
6185 (set_attr "type" "jsr")
6186 (set_attr "atype" "mem")])
6187
6188 (define_insn "bas_64"
6189 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6190 (match_operand:SI 1 "const_int_operand" "n"))
6191 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6192 "TARGET_64BIT"
6193 "bas\\t%2,%a0"
6194 [(set_attr "op_type" "RX")
6195 (set_attr "type" "jsr")
6196 (set_attr "atype" "mem")])
6197
6198 (define_insn "bas_31"
6199 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6200 (match_operand:SI 1 "const_int_operand" "n"))
6201 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6202 "!TARGET_64BIT"
6203 "bas\\t%2,%a0"
6204 [(set_attr "op_type" "RX")
6205 (set_attr "type" "jsr")
6206 (set_attr "atype" "mem")])
6207
6208
6209 ;
6210 ; call_value instruction pattern(s).
6211 ;
6212
6213 (define_expand "call_value"
6214 [(set (match_operand 0 "" "")
6215 (call (match_operand 1 "" "")
6216 (match_operand 2 "" "")))
6217 (use (match_operand 3 "" ""))]
6218 ""
6219 "
6220 {
6221 int plt_call = 0;
6222 rtx insn;
6223
6224 /* Direct function calls need special treatment. */
6225 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6226 {
6227 rtx sym = XEXP (operands[1], 0);
6228
6229 /* When calling a global routine in PIC mode, we must
6230 replace the symbol itself with the PLT stub. */
6231 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6232 {
6233 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6234 sym = gen_rtx_CONST (Pmode, sym);
6235
6236 plt_call = 1;
6237 }
6238
6239 /* Unless we can use the bras(l) insn, force the
6240 routine address into a register. */
6241 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6242 {
6243 rtx target = gen_reg_rtx (Pmode);
6244 emit_move_insn (target, sym);
6245 sym = target;
6246 }
6247
6248 operands[1] = gen_rtx_MEM (QImode, sym);
6249 }
6250
6251 /* Emit insn. */
6252 insn = emit_call_insn (
6253 gen_call_value_exp (operands[0], operands[1], operands[2],
6254 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6255
6256 /* In 31-bit, we must load the GOT register even if the
6257 compiler doesn't know about it, because the PLT glue
6258 code uses it. In 64-bit, this is not necessary. */
6259 if (plt_call && !TARGET_64BIT)
6260 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6261
6262 DONE;
6263 }")
6264
6265 (define_expand "call_value_exp"
6266 [(parallel [(set (match_operand 0 "" "")
6267 (call (match_operand 1 "" "")
6268 (match_operand 2 "" "")))
6269 (clobber (match_operand 3 "" ""))])]
6270 ""
6271 "")
6272
6273 (define_insn "brasl_r"
6274 [(set (match_operand 0 "register_operand" "=df")
6275 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6276 (match_operand:SI 2 "const_int_operand" "n")))
6277 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6278 "TARGET_64BIT"
6279 "brasl\\t%3,%1"
6280 [(set_attr "op_type" "RIL")
6281 (set_attr "type" "jsr")])
6282
6283 (define_insn "bras_r"
6284 [(set (match_operand 0 "register_operand" "=df")
6285 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6286 (match_operand:SI 2 "const_int_operand" "n")))
6287 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6288 "TARGET_SMALL_EXEC"
6289 "bras\\t%3,%1"
6290 [(set_attr "op_type" "RI")
6291 (set_attr "type" "jsr")])
6292
6293 (define_insn "basr_r_64"
6294 [(set (match_operand 0 "register_operand" "=df")
6295 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6296 (match_operand:SI 2 "const_int_operand" "n")))
6297 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6298 "TARGET_64BIT"
6299 "basr\\t%3,%1"
6300 [(set_attr "op_type" "RR")
6301 (set_attr "type" "jsr")])
6302
6303 (define_insn "basr_r_31"
6304 [(set (match_operand 0 "register_operand" "=df")
6305 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6306 (match_operand:SI 2 "const_int_operand" "n")))
6307 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6308 "!TARGET_64BIT"
6309 "basr\\t%3,%1"
6310 [(set_attr "op_type" "RR")
6311 (set_attr "type" "jsr")
6312 (set_attr "atype" "mem")])
6313
6314 (define_insn "bas_r_64"
6315 [(set (match_operand 0 "register_operand" "=df")
6316 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6317 (match_operand:SI 2 "const_int_operand" "n")))
6318 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6319 "TARGET_64BIT"
6320 "bas\\t%3,%a1"
6321 [(set_attr "op_type" "RX")
6322 (set_attr "type" "jsr")
6323 (set_attr "atype" "mem")])
6324
6325 (define_insn "bas_r_31"
6326 [(set (match_operand 0 "register_operand" "=df")
6327 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6328 (match_operand:SI 2 "const_int_operand" "n")))
6329 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6330 "!TARGET_64BIT"
6331 "bas\\t%3,%a1"
6332 [(set_attr "op_type" "RX")
6333 (set_attr "type" "jsr")
6334 (set_attr "atype" "mem")])
6335
6336
6337 ;;
6338 ;;- Miscellaneous instructions.
6339 ;;
6340
6341 ;
6342 ; allocate stack instruction pattern(s).
6343 ;
6344
6345 (define_expand "allocate_stack"
6346 [(set (reg 15)
6347 (plus (reg 15) (match_operand 1 "general_operand" "")))
6348 (set (match_operand 0 "general_operand" "")
6349 (reg 15))]
6350 ""
6351 "
6352 {
6353 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6354 rtx chain = gen_rtx (MEM, Pmode, stack);
6355 rtx temp = gen_reg_rtx (Pmode);
6356
6357 emit_move_insn (temp, chain);
6358
6359 if (TARGET_64BIT)
6360 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6361 else
6362 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6363
6364 emit_move_insn (chain, temp);
6365
6366 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6367 DONE;
6368 }")
6369
6370
6371 ;
6372 ; setjmp/longjmp instruction pattern(s).
6373 ;
6374
6375 (define_expand "builtin_setjmp_setup"
6376 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6377 ""
6378 "
6379 {
6380 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6381 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6382
6383 emit_move_insn (base, basereg);
6384 DONE;
6385 }")
6386
6387 (define_expand "builtin_setjmp_receiver"
6388 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6389 "flag_pic"
6390 "
6391 {
6392 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6393 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6394 SYMBOL_REF_FLAG (got) = 1;
6395
6396 emit_move_insn (gotreg, got);
6397 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6398 DONE;
6399 }")
6400
6401 (define_expand "builtin_longjmp"
6402 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6403 ""
6404 "
6405 {
6406 /* The elements of the buffer are, in order: */
6407 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6408 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6409 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6410 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6411 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6412 rtx jmp = gen_rtx_REG (Pmode, 14);
6413
6414 emit_move_insn (jmp, lab);
6415 emit_move_insn (basereg, base);
6416 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6417 emit_move_insn (hard_frame_pointer_rtx, fp);
6418
6419 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6420 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6421 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6422 emit_indirect_jump (jmp);
6423 DONE;
6424 }")
6425
6426
6427 ;; These patterns say how to save and restore the stack pointer. We need not
6428 ;; save the stack pointer at function level since we are careful to
6429 ;; preserve the backchain. At block level, we have to restore the backchain
6430 ;; when we restore the stack pointer.
6431 ;;
6432 ;; For nonlocal gotos, we must save both the stack pointer and its
6433 ;; backchain and restore both. Note that in the nonlocal case, the
6434 ;; save area is a memory location.
6435
6436 (define_expand "save_stack_function"
6437 [(match_operand 0 "general_operand" "")
6438 (match_operand 1 "general_operand" "")]
6439 ""
6440 "DONE;")
6441
6442 (define_expand "restore_stack_function"
6443 [(match_operand 0 "general_operand" "")
6444 (match_operand 1 "general_operand" "")]
6445 ""
6446 "DONE;")
6447
6448 (define_expand "restore_stack_block"
6449 [(use (match_operand 0 "register_operand" ""))
6450 (set (match_dup 2) (match_dup 3))
6451 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6452 (set (match_dup 3) (match_dup 2))]
6453 ""
6454 "
6455 {
6456 operands[2] = gen_reg_rtx (Pmode);
6457 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6458 }")
6459
6460 (define_expand "save_stack_nonlocal"
6461 [(match_operand 0 "memory_operand" "")
6462 (match_operand 1 "register_operand" "")]
6463 ""
6464 "
6465 {
6466 rtx temp = gen_reg_rtx (Pmode);
6467
6468 /* Copy the backchain to the first word, sp to the second. */
6469 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6470 emit_move_insn (operand_subword (operands[0], 0, 0,
6471 TARGET_64BIT ? TImode : DImode),
6472 temp);
6473 emit_move_insn (operand_subword (operands[0], 1, 0,
6474 TARGET_64BIT ? TImode : DImode),
6475 operands[1]);
6476 DONE;
6477 }")
6478
6479 (define_expand "restore_stack_nonlocal"
6480 [(match_operand 0 "register_operand" "")
6481 (match_operand 1 "memory_operand" "")]
6482 ""
6483 "
6484 {
6485 rtx temp = gen_reg_rtx (Pmode);
6486
6487 /* Restore the backchain from the first word, sp from the second. */
6488 emit_move_insn (temp,
6489 operand_subword (operands[1], 0, 0,
6490 TARGET_64BIT ? TImode : DImode));
6491 emit_move_insn (operands[0],
6492 operand_subword (operands[1], 1, 0,
6493 TARGET_64BIT ? TImode : DImode));
6494 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6495 DONE;
6496 }")
6497
6498
6499 ;
6500 ; nop instruction pattern(s).
6501 ;
6502
6503 (define_insn "nop"
6504 [(const_int 0)]
6505 ""
6506 "lr\\t0,0"
6507 [(set_attr "op_type" "RR")])
6508
6509
6510 ;
6511 ; Special literal pool access instruction pattern(s).
6512 ;
6513
6514 (define_insn "consttable_qi"
6515 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6516 ""
6517 "*
6518 {
6519 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6520 return \"\";
6521 }"
6522 [(set_attr "op_type" "NN")
6523 (set_attr "length" "1")])
6524
6525 (define_insn "consttable_hi"
6526 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6527 ""
6528 "*
6529 {
6530 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6531 return \"\";
6532 }"
6533 [(set_attr "op_type" "NN")
6534 (set_attr "length" "2")])
6535
6536 (define_insn "consttable_si"
6537 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6538 ""
6539 "*
6540 {
6541 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6542 return \".long\\t%0\";
6543
6544 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6545 return \"\";
6546 }"
6547 [(set_attr "op_type" "NN")
6548 (set_attr "length" "4")])
6549
6550 (define_insn "consttable_di"
6551 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6552 ""
6553 "*
6554 {
6555 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6556 return \"\";
6557 }"
6558 [(set_attr "op_type" "NN")
6559 (set_attr "length" "8")])
6560
6561 (define_insn "consttable_sf"
6562 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6563 ""
6564 "*
6565 {
6566 REAL_VALUE_TYPE r;
6567
6568 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6569 abort ();
6570
6571 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6572 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6573 return \"\";
6574 }"
6575 [(set_attr "op_type" "NN")
6576 (set_attr "length" "4")])
6577
6578 (define_insn "consttable_df"
6579 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6580 ""
6581 "*
6582 {
6583 REAL_VALUE_TYPE r;
6584
6585 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6586 abort ();
6587
6588 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6589 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6590 return \"\";
6591 }"
6592 [(set_attr "op_type" "NN")
6593 (set_attr "length" "8")])
6594
6595 (define_insn "pool_start_31"
6596 [(unspec_volatile [(const_int 0)] 206)]
6597 "!TARGET_64BIT"
6598 ".align\\t4"
6599 [(set_attr "op_type" "NN")
6600 (set_attr "length" "2")])
6601
6602 (define_insn "pool_end_31"
6603 [(unspec_volatile [(const_int 0)] 207)]
6604 "!TARGET_64BIT"
6605 ".align\\t2"
6606 [(set_attr "op_type" "NN")
6607 (set_attr "length" "2")])
6608
6609 (define_insn "pool_start_64"
6610 [(unspec_volatile [(const_int 0)] 206)]
6611 "TARGET_64BIT"
6612 ".section\\t.rodata\;.align\\t8"
6613 [(set_attr "op_type" "NN")
6614 (set_attr "length" "0")])
6615
6616 (define_insn "pool_end_64"
6617 [(unspec_volatile [(const_int 0)] 207)]
6618 "TARGET_64BIT"
6619 ".previous"
6620 [(set_attr "op_type" "NN")
6621 (set_attr "length" "0")])
6622
6623 (define_insn "reload_base"
6624 [(set (match_operand:SI 0 "register_operand" "=a")
6625 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6626 "!TARGET_64BIT"
6627 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6628 [(set_attr "op_type" "NN")
6629 (set_attr "type" "la")
6630 (set_attr "length" "6")])
6631
6632 (define_insn "reload_base2"
6633 [(set (match_operand:SI 0 "register_operand" "=a")
6634 (unspec:SI [(label_ref (match_operand 1 "" ""))] 211))]
6635 "!TARGET_64BIT"
6636 "la\\t%0,%1-.(%0)"
6637 [(set_attr "op_type" "NN")
6638 (set_attr "type" "la")
6639 (set_attr "length" "4")])
6640
6641
6642 ;;
6643 ;; Insns related to generating the function prologue and epilogue.
6644 ;;
6645
6646
6647 (define_expand "prologue"
6648 [(use (const_int 0))]
6649 ""
6650 "
6651 {
6652 s390_emit_prologue ();
6653 DONE;
6654 }")
6655
6656 (define_expand "epilogue"
6657 [(use (const_int 1))]
6658 ""
6659 "
6660 {
6661 s390_emit_epilogue ();
6662 DONE;
6663 }")
6664
6665
6666 (define_insn "*return_si"
6667 [(return)
6668 (use (match_operand:SI 0 "register_operand" "a"))]
6669 "!TARGET_64BIT"
6670 "br\\t%0"
6671 [(set_attr "op_type" "RR")
6672 (set_attr "type" "jsr")
6673 (set_attr "atype" "mem")])
6674
6675 (define_insn "*return_di"
6676 [(return)
6677 (use (match_operand:DI 0 "register_operand" "a"))]
6678 "TARGET_64BIT"
6679 "br\\t%0"
6680 [(set_attr "op_type" "RR")
6681 (set_attr "type" "jsr")
6682 (set_attr "atype" "mem")])
6683
6684
6685 (define_insn "lit"
6686 [(set (reg 13) (pc))
6687 (unspec_volatile [(const_int 0)] 200)]
6688 ""
6689 "*
6690 {
6691 s390_output_constant_pool (asm_out_file);
6692 return \"\";
6693 }"
6694 [(set_attr "op_type" "NN")
6695 (set_attr "type" "integer")])
6696
6697
6698 ;;
6699 ;; Peephole optimization patterns.
6700 ;;
6701
6702 (define_peephole
6703 [(set (match_operand:SI 0 "memory_operand" "m")
6704 (match_operand:SI 1 "register_operand" "d"))
6705 (set (match_dup 1)
6706 (match_dup 0))]
6707 ""
6708 "st\\t%1,%0")
6709
6710 (define_peephole
6711 [(set (match_operand:SI 0 "memory_operand" "m")
6712 (match_operand:SI 1 "register_operand" "d"))
6713 (set (match_dup 0)
6714 (match_dup 1))]
6715 ""
6716 "st\\t%1,%0")
6717
6718 (define_peephole
6719 [(set (match_operand:SI 0 "register_operand" "")
6720 (match_operand:SI 1 "register_operand" ""))
6721 (parallel
6722 [(set (match_dup 0)
6723 (plus:SI (match_dup 0)
6724 (match_operand:SI 2 "immediate_operand" "")))
6725 (clobber (reg:CC 33))])]
6726 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6727 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6728 REGNO (operands[0]) == BASE_REGISTER ||
6729 REGNO (operands[1]) == BASE_REGISTER) &&
6730 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6731 "la\\t%0,%c2(%1)")
6732
6733 ;
6734 ; peepholes for fast char instructions
6735 ;
6736
6737 ;(define_peephole
6738 ; [(set (match_operand:QI 0 "register_operand" "d")
6739 ; (match_operand:QI 1 "s_operand" "Q"))
6740 ; (set (match_operand:SI 2 "register_operand" "0")
6741 ; (zero_extend:SI (match_dup 0)))]
6742 ; "REGNO(operands[0]) == REGNO(operands[2])"
6743 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6744
6745 ;(define_peephole
6746 ; [(set (match_operand:QI 0 "register_operand" "d")
6747 ; (match_operand:QI 1 "s_operand" "Q"))
6748 ; (set (match_operand:SI 2 "register_operand" "0")
6749 ; (sign_extend:SI (match_dup 0)))]
6750 ; "REGNO(operands[0]) == REGNO(operands[2])"
6751 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6752
6753 (define_peephole
6754 [(set (match_operand:QI 0 "register_operand" "d")
6755 (match_operand:QI 1 "immediate_operand" "J"))
6756 (set (match_operand:SI 2 "register_operand" "0" )
6757 (sign_extend:SI (match_dup 0) ) )]
6758 "REGNO(operands[0]) == REGNO(operands[2])"
6759 "lhi\\t%0,%h1")
6760
6761 ;
6762 ; peepholes for fast short instructions
6763 ;
6764
6765 ;(define_peephole
6766 ; [(set (match_operand:HI 0 "register_operand" "d")
6767 ; (match_operand:HI 1 "s_operand" "Q"))
6768 ; (set (match_operand:SI 2 "register_operand" "0" )
6769 ; (zero_extend:SI (match_dup 0)))]
6770 ; "REGNO(operands[0]) == REGNO(operands[2])"
6771 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6772
6773 (define_peephole
6774 [(set (match_operand:HI 0 "register_operand" "d")
6775 (match_operand:HI 1 "memory_operand" "m"))
6776 (set (match_operand:SI 2 "register_operand" "0" )
6777 (sign_extend:SI (match_dup 0)))]
6778 "REGNO(operands[0]) == REGNO(operands[2])"
6779 "lh\\t%0,%1")
6780
6781 (define_peephole
6782 [(set (match_operand:HI 0 "register_operand" "d")
6783 (match_operand:HI 1 "immediate_operand" "K"))
6784 (set (match_operand:SI 2 "register_operand" "0" )
6785 (sign_extend:SI (match_dup 0) ) )]
6786 "REGNO(operands[0]) == REGNO(operands[2])"
6787 "lhi\\t%0,%h1")
6788
6789 ;
6790 ; peepholes for divide instructions
6791 ;
6792
6793 (define_peephole
6794 [(set (match_operand:DI 0 "register_operand" "d")
6795 (match_operand:DI 1 "memory_operand" "m"))
6796 (set (match_dup 0)
6797 (lshiftrt:DI (match_dup 0)
6798 (match_operand:SI 2 "immediate_operand" "J")))
6799 (set (match_dup 0)
6800 (div:SI (match_dup 0)
6801 (match_operand:SI 3 "nonimmediate_operand" "g")))
6802 (set (match_dup 1)
6803 (match_dup 0))]
6804 ""
6805 "*
6806 {
6807 output_asm_insn (\"l\\t%0,%1\", operands);
6808 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6809
6810 if (REG_P (operands[3]))
6811 output_asm_insn (\"dr\\t%0,%3\", operands);
6812 else
6813 output_asm_insn (\"d\\t%0,%3\", operands);
6814
6815 return \"st\\t%N0,%N1\";
6816 }")
6817
6818 (define_peephole
6819 [(set (match_operand:DI 0 "register_operand" "d")
6820 (match_operand:DI 1 "memory_operand" "m"))
6821 (set (match_dup 0)
6822 (lshiftrt:DI (match_dup 0)
6823 (match_operand:SI 2 "immediate_operand" "J")))
6824 (set (match_dup 0)
6825 (mod:SI (match_dup 0)
6826 (match_operand:SI 3 "nonimmediate_operand" "g")))
6827 (set (match_dup 1)
6828 (match_dup 0))]
6829 ""
6830 "*
6831 {
6832 output_asm_insn (\"l\\t%0,%1\", operands);
6833 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6834
6835 if (REG_P (operands[3]))
6836 output_asm_insn (\"dr\\t%0,%3\", operands);
6837 else
6838 output_asm_insn (\"d\\t%0,%3\", operands);
6839
6840 return \"st\\t%0,%1\";
6841 }")
6842