1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2016 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; The right hand side of an setmem
76 ; GOT/PLT and lt-relative accesses
97 ; TLS relocation specifiers
113 ; Stack Smashing Protector
117 ; Split stack support
120 ; Test Data Class (TDC)
132 UNSPEC_FPINT_NEARBYINT
141 UNSPEC_VEC_SMULT_EVEN
142 UNSPEC_VEC_UMULT_EVEN
156 UNSPEC_VEC_INSERT_AND_ZERO
157 UNSPEC_VEC_LOAD_BNDRY
162 UNSPEC_VEC_PACK_SATURATE
163 UNSPEC_VEC_PACK_SATURATE_CC
164 UNSPEC_VEC_PACK_SATURATE_GENCC
165 UNSPEC_VEC_PACK_UNSIGNED_SATURATE
166 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
178 UNSPEC_VEC_ADDEC_U128
183 UNSPEC_VEC_GFMSUM_128
184 UNSPEC_VEC_GFMSUM_ACCUM
185 UNSPEC_VEC_GFMSUM_ACCUM_128
202 UNSPEC_VEC_SUBEC_U128
236 ;; UNSPEC_VOLATILE usage
239 (define_c_enum "unspecv" [
261 ; Hotpatching (unremovable NOPs)
266 ; Transactional Execution support
276 ; Set and get floating point control register
280 ; Split stack support
281 UNSPECV_SPLIT_STACK_CALL
282 UNSPECV_SPLIT_STACK_DATA
289 ; Registers with special meaning
293 ; Sibling call register.
295 ; Literal pool base register.
297 ; Return address register.
299 ; Stack pointer register.
301 ; Condition code register.
303 ; Thread local storage pointer register.
307 ; Hardware register names
311 ; General purpose registers
316 ; Floating point registers.
340 ; Rounding modes for binary floating point numbers
343 (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
344 (BFP_RND_PREP_FOR_SHORT_PREC 3)
345 (BFP_RND_NEAREST_TIE_TO_EVEN 4)
347 (BFP_RND_TOWARD_INF 6)
348 (BFP_RND_TOWARD_MINF 7)])
350 ; Rounding modes for decimal floating point numbers
351 ; 1-7 were introduced with the floating point extension facility
352 ; available with z196
353 ; With these rounding modes (1-7) a quantum exception might occur
354 ; which is suppressed for the other modes.
357 (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
358 (DFP_RND_CURRENT_QUANTEXC 2)
359 (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3)
360 (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4)
361 (DFP_RND_TOWARD_0_QUANTEXC 5)
362 (DFP_RND_TOWARD_INF_QUANTEXC 6)
363 (DFP_RND_TOWARD_MINF_QUANTEXC 7)
364 (DFP_RND_NEAREST_TIE_TO_EVEN 8)
366 (DFP_RND_TOWARD_INF 10)
367 (DFP_RND_TOWARD_MINF 11)
368 (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12)
369 (DFP_RND_NEAREST_TIE_TO_0 13)
370 (DFP_RND_AWAY_FROM_0 14)
371 (DFP_RND_PREP_FOR_SHORT_PREC 15)])
374 ;; PFPO GPR0 argument format
379 ; PFPO operation type
380 (PFPO_CONVERT 0x1000000)
382 (PFPO_OP_TYPE_SF 0x5)
383 (PFPO_OP_TYPE_DF 0x6)
384 (PFPO_OP_TYPE_TF 0x7)
385 (PFPO_OP_TYPE_SD 0x8)
386 (PFPO_OP_TYPE_DD 0x9)
387 (PFPO_OP_TYPE_TD 0xa)
388 ; Bitposition of operand types
389 (PFPO_OP0_TYPE_SHIFT 16)
390 (PFPO_OP1_TYPE_SHIFT 8)
393 ; Immediate operands for tbegin and tbeginc
394 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
395 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
397 ;; Instruction operand type as used in the Principles of Operation.
398 ;; Used to determine defaults for length and other attribute values.
400 (define_attr "op_type"
401 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
404 ;; Instruction type attribute used for scheduling.
406 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
407 cs,vs,store,sem,idiv,
408 imulhi,imulsi,imuldi,
409 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
410 floadtf,floaddf,floadsf,fstoredf,fstoresf,
411 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
412 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
414 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
415 itoftf, itofdf, itofsf, itofdd, itoftd,
416 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
417 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
419 (cond [(eq_attr "op_type" "NN") (const_string "other")
420 (eq_attr "op_type" "SS") (const_string "cs")]
421 (const_string "integer")))
423 ;; Another attribute used for scheduling purposes:
424 ;; agen: Instruction uses the address generation unit
425 ;; reg: Instruction does not use the agen unit
427 (define_attr "atype" "agen,reg"
428 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
430 (const_string "agen")))
432 ;; Properties concerning Z10 execution grouping and value forwarding.
433 ;; z10_super: instruction is superscalar.
434 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
435 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
436 ;; target register. It can forward this value to a second instruction that reads
437 ;; the same register if that second instruction is issued in the same group.
438 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
439 ;; instruction in the S pipe writes to the register, then the T instruction
440 ;; can immediately read the new value.
441 ;; z10_fr: union of Z10_fwd and z10_rec.
442 ;; z10_c: second operand of instruction is a register and read with complemented bits.
444 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
447 (define_attr "z10prop" "none,
448 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
449 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
451 z10_fr, z10_fr_A3, z10_fr_E1,
453 (const_string "none"))
455 ;; Properties concerning Z196 decoding
456 ;; z196_alone: must group alone
457 ;; z196_end: ends a group
458 ;; z196_cracked: instruction is cracked or expanded
459 (define_attr "z196prop" "none,
460 z196_alone, z196_ends,
462 (const_string "none"))
464 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
468 (define_attr "length" ""
469 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
470 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
474 ;; Processor type. This attribute must exactly match the processor_type
475 ;; enumeration in s390.h. The current machine description does not
476 ;; distinguish between g5 and g6, but there are differences between the two
477 ;; CPUs could in theory be modeled.
479 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
480 (const (symbol_ref "s390_tune_attr")))
482 (define_attr "cpu_facility"
483 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec,z13"
484 (const_string "standard"))
486 (define_attr "enabled" ""
487 (cond [(eq_attr "cpu_facility" "standard")
490 (and (eq_attr "cpu_facility" "ieee")
491 (match_test "TARGET_CPU_IEEE_FLOAT"))
494 (and (eq_attr "cpu_facility" "zarch")
495 (match_test "TARGET_ZARCH"))
498 (and (eq_attr "cpu_facility" "longdisp")
499 (match_test "TARGET_LONG_DISPLACEMENT"))
502 (and (eq_attr "cpu_facility" "extimm")
503 (match_test "TARGET_EXTIMM"))
506 (and (eq_attr "cpu_facility" "dfp")
507 (match_test "TARGET_DFP"))
510 (and (eq_attr "cpu_facility" "cpu_zarch")
511 (match_test "TARGET_CPU_ZARCH"))
514 (and (eq_attr "cpu_facility" "z10")
515 (match_test "TARGET_Z10"))
518 (and (eq_attr "cpu_facility" "z196")
519 (match_test "TARGET_Z196"))
522 (and (eq_attr "cpu_facility" "zEC12")
523 (match_test "TARGET_ZEC12"))
526 (and (eq_attr "cpu_facility" "vec")
527 (match_test "TARGET_VX"))
530 (and (eq_attr "cpu_facility" "z13")
531 (match_test "TARGET_Z13"))
536 ;; Pipeline description for z900. For lack of anything better,
537 ;; this description is also used for the g5 and g6.
540 ;; Pipeline description for z990, z9-109 and z9-ec.
543 ;; Pipeline description for z10
546 ;; Pipeline description for z196
549 ;; Pipeline description for zEC12
552 ;; Pipeline description for z13
556 (include "predicates.md")
558 ;; Constraint definitions
559 (include "constraints.md")
566 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
568 ;; These mode iterators allow floating point patterns to be generated from the
570 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
571 (SD "TARGET_HARD_DFP")])
572 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
573 (define_mode_iterator BFP [TF DF SF])
574 (define_mode_iterator DFP [TD DD])
575 (define_mode_iterator DFP_ALL [TD DD SD])
576 (define_mode_iterator DSF [DF SF])
577 (define_mode_iterator SD_SF [SF SD])
578 (define_mode_iterator DD_DF [DF DD])
579 (define_mode_iterator TD_TF [TF TD])
581 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
582 ;; from the same template.
583 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
584 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
585 (define_mode_iterator DSI [DI SI])
586 (define_mode_iterator TDI [TI DI])
588 ;; These mode iterators allow :P to be used for patterns that operate on
589 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
590 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
592 ;; These macros refer to the actual word_mode of the configuration.
593 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
594 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
595 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
597 ;; Used by the umul pattern to express modes having half the size.
598 (define_mode_attr DWH [(TI "DI") (DI "SI")])
599 (define_mode_attr dwh [(TI "di") (DI "si")])
601 ;; This mode iterator allows the QI and HI patterns to be defined from
602 ;; the same template.
603 (define_mode_iterator HQI [HI QI])
605 ;; This mode iterator allows the integer patterns to be defined from the
607 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
608 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
609 (define_mode_iterator SINT [SI HI QI])
611 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
612 ;; the same template.
613 (define_code_iterator SHIFT [ashift lshiftrt])
615 ;; This iterator allows r[ox]sbg to be defined with the same template
616 (define_code_iterator IXOR [ior xor])
618 ;; This iterator is used to expand the patterns for the nearest
619 ;; integer functions.
620 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
621 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
622 UNSPEC_FPINT_NEARBYINT])
623 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
624 (UNSPEC_FPINT_BTRUNC "btrunc")
625 (UNSPEC_FPINT_ROUND "round")
626 (UNSPEC_FPINT_CEIL "ceil")
627 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
628 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
629 (UNSPEC_FPINT_BTRUNC "5")
630 (UNSPEC_FPINT_ROUND "1")
631 (UNSPEC_FPINT_CEIL "6")
632 (UNSPEC_FPINT_NEARBYINT "0")])
634 ;; This iterator and attribute allow to combine most atomic operations.
635 (define_code_iterator ATOMIC [and ior xor plus minus mult])
636 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
637 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
638 (plus "add") (minus "sub") (mult "nand")])
639 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
641 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
642 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
643 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
645 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
646 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
648 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
650 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
651 ;; Likewise for "<RXe>".
652 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
653 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
655 ;; The decimal floating point variants of add, sub, div and mul support 3
656 ;; fp register operands. The following attributes allow to merge the bfp and
657 ;; dfp variants in a single insn definition.
659 ;; These mode attributes are supposed to be used in the `enabled' insn
660 ;; attribute to disable certain alternatives for certain modes.
661 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
662 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
663 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
664 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
665 (TD "0") (DD "0") (DD "0")
666 (TI "0") (DI "*") (SI "0")])
668 ;; This attribute is used in the operand constraint list
669 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
670 ;; TFmode values are represented by a fp register pair. Since the
671 ;; sign bit instructions only handle single source and target fp registers
672 ;; these instructions can only be used for TFmode values if the source and
673 ;; target operand uses the same fp register.
674 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
676 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
677 ;; within instruction mnemonics.
678 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
680 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
681 ;; modes and to an empty string for bfp modes.
682 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
684 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
685 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
686 ;; version only operates on one register.
687 (define_mode_attr d0 [(DI "d") (SI "0")])
689 ;; In combination with d0 this allows to combine instructions of which the 31bit
690 ;; version only operates on one register. The DImode version needs an additional
691 ;; register for the assembler output.
692 (define_mode_attr 1 [(DI "%1,") (SI "")])
694 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
695 ;; 'ashift' and "srdl" in 'lshiftrt'.
696 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
698 ;; In SHIFT templates, this attribute holds the correct standard name for the
699 ;; pattern itself and the corresponding function calls.
700 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
702 ;; This attribute handles differences in the instruction 'type' and will result
703 ;; in "RRE" for DImode and "RR" for SImode.
704 (define_mode_attr E [(DI "E") (SI "")])
706 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
707 ;; to result in "RXY" for DImode and "RX" for SImode.
708 (define_mode_attr Y [(DI "Y") (SI "")])
710 ;; This attribute handles differences in the instruction 'type' and will result
711 ;; in "RSE" for TImode and "RS" for DImode.
712 (define_mode_attr TE [(TI "E") (DI "")])
714 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
715 ;; and "lcr" in SImode.
716 (define_mode_attr g [(DI "g") (SI "")])
718 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
719 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
720 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
721 ;; variant for long displacements.
722 (define_mode_attr y [(DI "g") (SI "y")])
724 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
725 ;; and "cds" in DImode.
726 (define_mode_attr tg [(TI "g") (DI "")])
728 ;; In TDI templates, a string like "c<d>sg".
729 (define_mode_attr td [(TI "d") (DI "")])
731 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
732 ;; and "cfdbr" in SImode.
733 (define_mode_attr gf [(DI "g") (SI "f")])
735 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
736 ;; and sllk for SI. This way it is possible to merge the new z196 SI
737 ;; 3 operands shift instructions into the existing patterns.
738 (define_mode_attr gk [(DI "g") (SI "k")])
740 ;; ICM mask required to load MODE value into the lowest subreg
741 ;; of a SImode register.
742 (define_mode_attr icm_lo [(HI "3") (QI "1")])
744 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
745 ;; HImode and "llgc" in QImode.
746 (define_mode_attr hc [(HI "h") (QI "c")])
748 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
750 (define_mode_attr DBL [(DI "TI") (SI "DI")])
752 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
753 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
754 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
756 ;; Maximum unsigned integer that fits in MODE.
757 (define_mode_attr max_uint [(HI "65535") (QI "255")])
759 ;; Start and end field computations for RISBG et al.
760 (define_mode_attr bfstart [(DI "s") (SI "t")])
761 (define_mode_attr bfend [(DI "e") (SI "f")])
763 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
764 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
766 (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
767 (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
769 ;; In place of GET_MODE_SIZE (<MODE>mode)
770 (define_mode_attr modesize [(DI "8") (SI "4")])
772 ;; Allow return and simple_return to be defined from a single template.
773 (define_code_iterator ANY_RETURN [return simple_return])
777 ; Condition code modes generated by vector fp comparisons. These will
778 ; be used also in single element mode.
779 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
780 ; Used with VFCMP to expand part of the mnemonic
781 ; For fp we have a mismatch: eq in the insn name - e in asm
782 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
783 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
785 ;; Subst pattern definitions
788 (include "vector.md")
791 ;;- Compare instructions.
794 ; Test-under-Mask instructions
796 (define_insn "*tmqi_mem"
797 [(set (reg CC_REGNUM)
798 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
799 (match_operand:QI 1 "immediate_operand" "n,n"))
800 (match_operand:QI 2 "immediate_operand" "n,n")))]
801 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
805 [(set_attr "op_type" "SI,SIY")
806 (set_attr "cpu_facility" "*,longdisp")
807 (set_attr "z10prop" "z10_super,z10_super")])
809 (define_insn "*tmdi_reg"
810 [(set (reg CC_REGNUM)
811 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
812 (match_operand:DI 1 "immediate_operand"
813 "N0HD0,N1HD0,N2HD0,N3HD0"))
814 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
816 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
817 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
823 [(set_attr "op_type" "RI")
824 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
826 (define_insn "*tmsi_reg"
827 [(set (reg CC_REGNUM)
828 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
829 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
830 (match_operand:SI 2 "immediate_operand" "n,n")))]
831 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
832 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
836 [(set_attr "op_type" "RI")
837 (set_attr "z10prop" "z10_super,z10_super")])
839 (define_insn "*tm<mode>_full"
840 [(set (reg CC_REGNUM)
841 (compare (match_operand:HQI 0 "register_operand" "d")
842 (match_operand:HQI 1 "immediate_operand" "n")))]
843 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
845 [(set_attr "op_type" "RI")
846 (set_attr "z10prop" "z10_super")])
850 ; Load-and-Test instructions
853 ; tst(di|si) instruction pattern(s).
855 (define_insn "*tstdi_sign"
856 [(set (reg CC_REGNUM)
860 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
861 (const_int 32)) (const_int 32))
862 (match_operand:DI 1 "const0_operand" "")))
863 (set (match_operand:DI 2 "register_operand" "=d,d")
864 (sign_extend:DI (match_dup 0)))]
865 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
868 [(set_attr "op_type" "RRE,RXY")
869 (set_attr "cpu_facility" "*,z10")
870 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
873 (define_insn "*tst<mode>_extimm"
874 [(set (reg CC_REGNUM)
875 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
876 (match_operand:GPR 1 "const0_operand" "")))
877 (set (match_operand:GPR 2 "register_operand" "=d,d")
879 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
883 [(set_attr "op_type" "RR<E>,RXY")
884 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
887 (define_insn "*tst<mode>_cconly_extimm"
888 [(set (reg CC_REGNUM)
889 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
890 (match_operand:GPR 1 "const0_operand" "")))
891 (clobber (match_scratch:GPR 2 "=X,d"))]
892 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
896 [(set_attr "op_type" "RR<E>,RXY")
897 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
899 (define_insn "*tstdi"
900 [(set (reg CC_REGNUM)
901 (compare (match_operand:DI 0 "register_operand" "d")
902 (match_operand:DI 1 "const0_operand" "")))
903 (set (match_operand:DI 2 "register_operand" "=d")
905 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
907 [(set_attr "op_type" "RRE")
908 (set_attr "z10prop" "z10_fr_E1")])
910 (define_insn "*tstsi"
911 [(set (reg CC_REGNUM)
912 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
913 (match_operand:SI 1 "const0_operand" "")))
914 (set (match_operand:SI 2 "register_operand" "=d,d,d")
916 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
921 [(set_attr "op_type" "RR,RS,RSY")
922 (set_attr "cpu_facility" "*,*,longdisp")
923 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
925 (define_insn "*tstsi_cconly"
926 [(set (reg CC_REGNUM)
927 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
928 (match_operand:SI 1 "const0_operand" "")))
929 (clobber (match_scratch:SI 2 "=X,d,d"))]
930 "s390_match_ccmode(insn, CCSmode)"
935 [(set_attr "op_type" "RR,RS,RSY")
936 (set_attr "cpu_facility" "*,*,longdisp")
937 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
939 (define_insn "*tstdi_cconly_31"
940 [(set (reg CC_REGNUM)
941 (compare (match_operand:DI 0 "register_operand" "d")
942 (match_operand:DI 1 "const0_operand" "")))]
943 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
945 [(set_attr "op_type" "RS")
946 (set_attr "atype" "reg")])
949 (define_insn "*tst<mode>_cconly2"
950 [(set (reg CC_REGNUM)
951 (compare (match_operand:GPR 0 "register_operand" "d")
952 (match_operand:GPR 1 "const0_operand" "")))]
953 "s390_match_ccmode(insn, CCSmode)"
955 [(set_attr "op_type" "RR<E>")
956 (set_attr "z10prop" "z10_fr_E1")])
958 ; tst(hi|qi) instruction pattern(s).
960 (define_insn "*tst<mode>CCT"
961 [(set (reg CC_REGNUM)
962 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
963 (match_operand:HQI 1 "const0_operand" "")))
964 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
966 "s390_match_ccmode(insn, CCTmode)"
969 icmy\t%2,<icm_lo>,%S0
971 [(set_attr "op_type" "RS,RSY,RI")
972 (set_attr "cpu_facility" "*,longdisp,*")
973 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
975 (define_insn "*tsthiCCT_cconly"
976 [(set (reg CC_REGNUM)
977 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
978 (match_operand:HI 1 "const0_operand" "")))
979 (clobber (match_scratch:HI 2 "=d,d,X"))]
980 "s390_match_ccmode(insn, CCTmode)"
985 [(set_attr "op_type" "RS,RSY,RI")
986 (set_attr "cpu_facility" "*,longdisp,*")
987 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
989 (define_insn "*tstqiCCT_cconly"
990 [(set (reg CC_REGNUM)
991 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
992 (match_operand:QI 1 "const0_operand" "")))]
993 "s390_match_ccmode(insn, CCTmode)"
998 [(set_attr "op_type" "SI,SIY,RI")
999 (set_attr "cpu_facility" "*,longdisp,*")
1000 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
1002 (define_insn "*tst<mode>"
1003 [(set (reg CC_REGNUM)
1004 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1005 (match_operand:HQI 1 "const0_operand" "")))
1006 (set (match_operand:HQI 2 "register_operand" "=d,d")
1008 "s390_match_ccmode(insn, CCSmode)"
1010 icm\t%2,<icm_lo>,%S0
1011 icmy\t%2,<icm_lo>,%S0"
1012 [(set_attr "op_type" "RS,RSY")
1013 (set_attr "cpu_facility" "*,longdisp")
1014 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1016 (define_insn "*tst<mode>_cconly"
1017 [(set (reg CC_REGNUM)
1018 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1019 (match_operand:HQI 1 "const0_operand" "")))
1020 (clobber (match_scratch:HQI 2 "=d,d"))]
1021 "s390_match_ccmode(insn, CCSmode)"
1023 icm\t%2,<icm_lo>,%S0
1024 icmy\t%2,<icm_lo>,%S0"
1025 [(set_attr "op_type" "RS,RSY")
1026 (set_attr "cpu_facility" "*,longdisp")
1027 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1030 ; Compare (equality) instructions
1032 (define_insn "*cmpdi_cct"
1033 [(set (reg CC_REGNUM)
1034 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
1035 (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
1036 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
1043 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
1044 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
1046 (define_insn "*cmpsi_cct"
1047 [(set (reg CC_REGNUM)
1048 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1049 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1050 "s390_match_ccmode (insn, CCTmode)"
1058 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1059 (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
1060 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1062 ; Compare (signed) instructions
1064 (define_insn "*cmpdi_ccs_sign"
1065 [(set (reg CC_REGNUM)
1066 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1068 (match_operand:DI 0 "register_operand" "d, d,d")))]
1069 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1074 [(set_attr "op_type" "RRE,RXY,RIL")
1075 (set_attr "z10prop" "z10_c,*,*")
1076 (set_attr "type" "*,*,larl")])
1080 (define_insn "*cmpsi_ccs_sign"
1081 [(set (reg CC_REGNUM)
1082 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1083 (match_operand:SI 0 "register_operand" "d,d,d")))]
1084 "s390_match_ccmode(insn, CCSRmode)"
1089 [(set_attr "op_type" "RX,RXY,RIL")
1090 (set_attr "cpu_facility" "*,longdisp,z10")
1091 (set_attr "type" "*,*,larl")
1092 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1094 (define_insn "*cmphi_ccs_z10"
1095 [(set (reg CC_REGNUM)
1096 (compare (match_operand:HI 0 "s_operand" "Q")
1097 (match_operand:HI 1 "immediate_operand" "K")))]
1098 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1100 [(set_attr "op_type" "SIL")
1101 (set_attr "z196prop" "z196_cracked")])
1103 (define_insn "*cmpdi_ccs_signhi_rl"
1104 [(set (reg CC_REGNUM)
1105 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
1106 (match_operand:GPR 0 "register_operand" "d,d")))]
1107 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1111 [(set_attr "op_type" "RXY,RIL")
1112 (set_attr "type" "*,larl")])
1114 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1115 (define_insn "*cmp<mode>_ccs"
1116 [(set (reg CC_REGNUM)
1117 (compare (match_operand:GPR 0 "nonimmediate_operand"
1119 (match_operand:GPR 1 "general_operand"
1120 "d,K,K,Os,R,T,b")))]
1121 "s390_match_ccmode(insn, CCSmode)"
1130 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1131 (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
1132 (set_attr "type" "*,*,*,*,*,*,larl")
1133 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1136 ; Compare (unsigned) instructions
1138 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1139 [(set (reg CC_REGNUM)
1140 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1141 "larl_operand" "X")))
1142 (match_operand:SI 0 "register_operand" "d")))]
1143 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1145 [(set_attr "op_type" "RIL")
1146 (set_attr "type" "larl")
1147 (set_attr "z10prop" "z10_super")])
1150 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1151 [(set (reg CC_REGNUM)
1152 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1153 "larl_operand" "X")))
1154 (match_operand:GPR 0 "register_operand" "d")))]
1155 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1157 [(set_attr "op_type" "RIL")
1158 (set_attr "type" "larl")
1159 (set_attr "z10prop" "z10_super")])
1161 (define_insn "*cmpdi_ccu_zero"
1162 [(set (reg CC_REGNUM)
1163 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1165 (match_operand:DI 0 "register_operand" "d,d,d")))]
1166 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1171 [(set_attr "op_type" "RRE,RXY,RIL")
1172 (set_attr "cpu_facility" "*,*,z10")
1173 (set_attr "type" "*,*,larl")
1174 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1176 (define_insn "*cmpdi_ccu"
1177 [(set (reg CC_REGNUM)
1178 (compare (match_operand:DI 0 "nonimmediate_operand"
1180 (match_operand:DI 1 "general_operand"
1181 "d,Op,b,D,T,BQ,Q")))]
1182 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1191 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1192 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1193 (set_attr "type" "*,*,larl,*,*,*,*")
1194 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1196 (define_insn "*cmpsi_ccu"
1197 [(set (reg CC_REGNUM)
1198 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1199 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1200 "s390_match_ccmode (insn, CCUmode)"
1210 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1211 (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
1212 (set_attr "type" "*,*,larl,*,*,*,*,*")
1213 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1215 (define_insn "*cmphi_ccu"
1216 [(set (reg CC_REGNUM)
1217 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1218 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1219 "s390_match_ccmode (insn, CCUmode)
1220 && !register_operand (operands[1], HImode)"
1227 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1228 (set_attr "cpu_facility" "*,longdisp,z10,*,*")
1229 (set_attr "z10prop" "*,*,z10_super,*,*")])
1231 (define_insn "*cmpqi_ccu"
1232 [(set (reg CC_REGNUM)
1233 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1234 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1235 "s390_match_ccmode (insn, CCUmode)
1236 && !register_operand (operands[1], QImode)"
1244 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1245 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
1246 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1249 ; Block compare (CLC) instruction patterns.
1252 [(set (reg CC_REGNUM)
1253 (compare (match_operand:BLK 0 "memory_operand" "Q")
1254 (match_operand:BLK 1 "memory_operand" "Q")))
1255 (use (match_operand 2 "const_int_operand" "n"))]
1256 "s390_match_ccmode (insn, CCUmode)
1257 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1258 "clc\t%O0(%2,%R0),%S1"
1259 [(set_attr "op_type" "SS")])
1262 [(set (reg CC_REGNUM)
1263 (compare (match_operand 0 "memory_operand" "")
1264 (match_operand 1 "memory_operand" "")))]
1266 && s390_match_ccmode (insn, CCUmode)
1267 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1268 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1270 [(set (match_dup 0) (match_dup 1))
1271 (use (match_dup 2))])]
1273 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1274 operands[0] = adjust_address (operands[0], BLKmode, 0);
1275 operands[1] = adjust_address (operands[1], BLKmode, 0);
1277 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1278 operands[0], operands[1]);
1279 operands[0] = SET_DEST (PATTERN (curr_insn));
1283 ; (TF|DF|SF|TD|DD|SD) instructions
1285 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1286 (define_insn "*cmp<mode>_ccs_0"
1287 [(set (reg CC_REGNUM)
1288 (compare (match_operand:FP 0 "register_operand" "f")
1289 (match_operand:FP 1 "const0_operand" "")))]
1290 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1291 "lt<xde><bt>r\t%0,%0"
1292 [(set_attr "op_type" "RRE")
1293 (set_attr "type" "fsimp<mode>")])
1295 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1296 (define_insn "*cmp<mode>_ccs"
1297 [(set (reg CC_REGNUM)
1298 (compare (match_operand:FP 0 "register_operand" "f,f")
1299 (match_operand:FP 1 "general_operand" "f,R")))]
1300 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1304 [(set_attr "op_type" "RRE,RXE")
1305 (set_attr "type" "fsimp<mode>")
1306 (set_attr "enabled" "*,<DSF>")])
1308 ; wfcedbs, wfchdbs, wfchedbs
1309 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1310 [(set (reg:VFCMP CC_REGNUM)
1311 (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1312 (match_operand:DF 1 "register_operand" "v")))
1313 (clobber (match_scratch:V2DI 2 "=v"))]
1314 "TARGET_VX && TARGET_HARD_FLOAT"
1315 "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1316 [(set_attr "op_type" "VRR")])
1318 ; Compare and Branch instructions
1320 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1321 ; The following instructions do a complementary access of their second
1322 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1323 (define_insn "*cmp_and_br_signed_<mode>"
1325 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1326 [(match_operand:GPR 1 "register_operand" "d,d")
1327 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1328 (label_ref (match_operand 3 "" ""))
1330 (clobber (reg:CC CC_REGNUM))]
1331 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1333 if (get_attr_length (insn) == 6)
1334 return which_alternative ?
1335 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1337 return which_alternative ?
1338 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1340 [(set_attr "op_type" "RIE")
1341 (set_attr "type" "branch")
1342 (set_attr "z10prop" "z10_super_c,z10_super")
1343 (set (attr "length")
1344 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1345 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1346 ; 10 byte for cgr/jg
1348 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1349 ; The following instructions do a complementary access of their second
1350 ; operand (z10 only): clrj, clgrj, clr, clgr
1351 (define_insn "*cmp_and_br_unsigned_<mode>"
1353 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1354 [(match_operand:GPR 1 "register_operand" "d,d")
1355 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1356 (label_ref (match_operand 3 "" ""))
1358 (clobber (reg:CC CC_REGNUM))]
1359 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1361 if (get_attr_length (insn) == 6)
1362 return which_alternative ?
1363 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1365 return which_alternative ?
1366 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1368 [(set_attr "op_type" "RIE")
1369 (set_attr "type" "branch")
1370 (set_attr "z10prop" "z10_super_c,z10_super")
1371 (set (attr "length")
1372 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1373 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1374 ; 10 byte for clgr/jg
1376 ; And now the same two patterns as above but with a negated CC mask.
1378 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1379 ; The following instructions do a complementary access of their second
1380 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1381 (define_insn "*icmp_and_br_signed_<mode>"
1383 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1384 [(match_operand:GPR 1 "register_operand" "d,d")
1385 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1387 (label_ref (match_operand 3 "" ""))))
1388 (clobber (reg:CC CC_REGNUM))]
1389 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1391 if (get_attr_length (insn) == 6)
1392 return which_alternative ?
1393 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1395 return which_alternative ?
1396 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1398 [(set_attr "op_type" "RIE")
1399 (set_attr "type" "branch")
1400 (set_attr "z10prop" "z10_super_c,z10_super")
1401 (set (attr "length")
1402 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1403 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1404 ; 10 byte for cgr/jg
1406 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1407 ; The following instructions do a complementary access of their second
1408 ; operand (z10 only): clrj, clgrj, clr, clgr
1409 (define_insn "*icmp_and_br_unsigned_<mode>"
1411 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1412 [(match_operand:GPR 1 "register_operand" "d,d")
1413 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1415 (label_ref (match_operand 3 "" ""))))
1416 (clobber (reg:CC CC_REGNUM))]
1417 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1419 if (get_attr_length (insn) == 6)
1420 return which_alternative ?
1421 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1423 return which_alternative ?
1424 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1426 [(set_attr "op_type" "RIE")
1427 (set_attr "type" "branch")
1428 (set_attr "z10prop" "z10_super_c,z10_super")
1429 (set (attr "length")
1430 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1431 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1432 ; 10 byte for clgr/jg
1435 ;;- Move instructions.
1439 ; movti instruction pattern(s).
1442 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1443 ; for TImode (use double-int for the calculations)
1444 (define_insn "movti"
1445 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o")
1446 (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))]
1460 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1461 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1462 (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1465 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1466 (match_operand:TI 1 "general_operand" ""))]
1467 "TARGET_ZARCH && reload_completed
1468 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1469 [(set (match_dup 2) (match_dup 4))
1470 (set (match_dup 3) (match_dup 5))]
1472 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1473 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1474 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1475 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1479 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1480 (match_operand:TI 1 "general_operand" ""))]
1481 "TARGET_ZARCH && reload_completed
1482 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1483 [(set (match_dup 2) (match_dup 4))
1484 (set (match_dup 3) (match_dup 5))]
1486 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1487 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1488 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1489 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1492 ; Use part of the TImode target reg to perform the address
1493 ; calculation. If the TImode value is supposed to be copied into a VR
1494 ; this splitter is not necessary.
1496 [(set (match_operand:TI 0 "register_operand" "")
1497 (match_operand:TI 1 "memory_operand" ""))]
1498 "TARGET_ZARCH && reload_completed
1499 && !VECTOR_REG_P (operands[0])
1500 && !s_operand (operands[1], VOIDmode)"
1501 [(set (match_dup 0) (match_dup 1))]
1503 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1504 addr = gen_lowpart (Pmode, addr);
1505 s390_load_address (addr, XEXP (operands[1], 0));
1506 operands[1] = replace_equiv_address (operands[1], addr);
1510 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1511 ; For the higher order bits we do simply a DImode move while the
1512 ; second part is done via vec extract. Both will end up as vlgvg.
1514 [(set (match_operand:TI 0 "register_operand" "")
1515 (match_operand:TI 1 "register_operand" ""))]
1516 "TARGET_VX && reload_completed
1517 && GENERAL_REG_P (operands[0])
1518 && VECTOR_REG_P (operands[1])"
1519 [(set (match_dup 2) (match_dup 4))
1520 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1521 UNSPEC_VEC_EXTRACT))]
1523 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1524 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1525 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1526 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1530 ; Patterns used for secondary reloads
1533 ; z10 provides move instructions accepting larl memory operands.
1534 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1535 ; These patterns are also used for unaligned SI and DI accesses.
1537 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1538 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1539 (match_operand:ALL 1 "register_operand" "=d")
1540 (match_operand:P 2 "register_operand" "=&a")])]
1543 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1547 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1548 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1549 (match_operand:ALL 1 "memory_operand" "")
1550 (match_operand:P 2 "register_operand" "=a")])]
1553 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1557 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1558 [(parallel [(match_operand:P 0 "register_operand" "=d")
1559 (match_operand:P 1 "larl_operand" "")
1560 (match_operand:P 2 "register_operand" "=a")])]
1563 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1567 ; Handles loading a PLUS (load address) expression
1569 (define_expand "reload<mode>_plus"
1570 [(parallel [(match_operand:P 0 "register_operand" "=a")
1571 (match_operand:P 1 "s390_plus_operand" "")
1572 (match_operand:P 2 "register_operand" "=&a")])]
1575 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1579 ; Not all the indirect memory access instructions support the full
1580 ; format (long disp + index + base). So whenever a move from/to such
1581 ; an address is required and the instruction cannot deal with it we do
1582 ; a load address into a scratch register first and use this as the new
1584 ; This in particular is used for:
1585 ; - non-offsetable memory accesses for multiword moves
1586 ; - full vector reg moves with long displacements
1588 (define_expand "reload<mode>_la_in"
1589 [(parallel [(match_operand 0 "register_operand" "")
1590 (match_operand 1 "" "")
1591 (match_operand:P 2 "register_operand" "=&a")])]
1594 gcc_assert (MEM_P (operands[1]));
1595 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1596 operands[1] = replace_equiv_address (operands[1], operands[2]);
1597 emit_move_insn (operands[0], operands[1]);
1601 (define_expand "reload<mode>_la_out"
1602 [(parallel [(match_operand 0 "" "")
1603 (match_operand 1 "register_operand" "")
1604 (match_operand:P 2 "register_operand" "=&a")])]
1607 gcc_assert (MEM_P (operands[0]));
1608 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1609 operands[0] = replace_equiv_address (operands[0], operands[2]);
1610 emit_move_insn (operands[0], operands[1]);
1614 (define_expand "reload<mode>_PIC_addr"
1615 [(parallel [(match_operand 0 "register_operand" "=d")
1616 (match_operand 1 "larl_operand" "")
1617 (match_operand:P 2 "register_operand" "=a")])]
1620 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1621 emit_move_insn (operands[0], new_rtx);
1625 ; movdi instruction pattern(s).
1628 (define_expand "movdi"
1629 [(set (match_operand:DI 0 "general_operand" "")
1630 (match_operand:DI 1 "general_operand" ""))]
1633 /* Handle symbolic constants. */
1635 && (SYMBOLIC_CONST (operands[1])
1636 || (GET_CODE (operands[1]) == PLUS
1637 && XEXP (operands[1], 0) == pic_offset_table_rtx
1638 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1639 emit_symbolic_move (operands);
1642 (define_insn "*movdi_larl"
1643 [(set (match_operand:DI 0 "register_operand" "=d")
1644 (match_operand:DI 1 "larl_operand" "X"))]
1646 && !FP_REG_P (operands[0])"
1648 [(set_attr "op_type" "RIL")
1649 (set_attr "type" "larl")
1650 (set_attr "z10prop" "z10_super_A1")])
1652 (define_insn "*movdi_64"
1653 [(set (match_operand:DI 0 "nonimmediate_operand"
1654 "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
1655 (match_operand:DI 1 "general_operand"
1656 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
1691 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1692 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1693 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1694 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1696 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1697 z10,*,*,*,*,*,longdisp,*,longdisp,
1698 z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1699 (set_attr "z10prop" "z10_fwd_A1,
1728 [(set (match_operand:DI 0 "register_operand" "")
1729 (match_operand:DI 1 "register_operand" ""))]
1730 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1731 [(set (match_dup 2) (match_dup 3))
1732 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1733 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1734 "operands[2] = gen_lowpart (SImode, operands[0]);
1735 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1738 [(set (match_operand:DI 0 "register_operand" "")
1739 (match_operand:DI 1 "register_operand" ""))]
1740 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1741 && dead_or_set_p (insn, operands[1])"
1742 [(set (match_dup 3) (match_dup 2))
1743 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1744 (set (match_dup 4) (match_dup 2))]
1745 "operands[2] = gen_lowpart (SImode, operands[1]);
1746 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1749 [(set (match_operand:DI 0 "register_operand" "")
1750 (match_operand:DI 1 "register_operand" ""))]
1751 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1752 && !dead_or_set_p (insn, operands[1])"
1753 [(set (match_dup 3) (match_dup 2))
1754 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1755 (set (match_dup 4) (match_dup 2))
1756 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1757 "operands[2] = gen_lowpart (SImode, operands[1]);
1758 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1760 (define_insn "*movdi_31"
1761 [(set (match_operand:DI 0 "nonimmediate_operand"
1762 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1763 (match_operand:DI 1 "general_operand"
1764 " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
1779 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1780 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1781 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
1783 ; For a load from a symbol ref we can use one of the target registers
1784 ; together with larl to load the address.
1786 [(set (match_operand:DI 0 "register_operand" "")
1787 (match_operand:DI 1 "memory_operand" ""))]
1788 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1789 && larl_operand (XEXP (operands[1], 0), SImode)"
1790 [(set (match_dup 2) (match_dup 3))
1791 (set (match_dup 0) (match_dup 1))]
1793 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1794 operands[3] = XEXP (operands[1], 0);
1795 operands[1] = replace_equiv_address (operands[1], operands[2]);
1799 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1800 (match_operand:DI 1 "general_operand" ""))]
1801 "!TARGET_ZARCH && reload_completed
1802 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1803 [(set (match_dup 2) (match_dup 4))
1804 (set (match_dup 3) (match_dup 5))]
1806 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1807 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1808 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1809 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1813 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1814 (match_operand:DI 1 "general_operand" ""))]
1815 "!TARGET_ZARCH && reload_completed
1816 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1817 [(set (match_dup 2) (match_dup 4))
1818 (set (match_dup 3) (match_dup 5))]
1820 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1821 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1822 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1823 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1827 [(set (match_operand:DI 0 "register_operand" "")
1828 (match_operand:DI 1 "memory_operand" ""))]
1829 "!TARGET_ZARCH && reload_completed
1830 && !FP_REG_P (operands[0])
1831 && !s_operand (operands[1], VOIDmode)"
1832 [(set (match_dup 0) (match_dup 1))]
1834 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1835 s390_load_address (addr, XEXP (operands[1], 0));
1836 operands[1] = replace_equiv_address (operands[1], addr);
1840 [(set (match_operand:DI 0 "register_operand" "")
1841 (mem:DI (match_operand 1 "address_operand" "")))]
1843 && !FP_REG_P (operands[0])
1844 && GET_CODE (operands[1]) == SYMBOL_REF
1845 && CONSTANT_POOL_ADDRESS_P (operands[1])
1846 && get_pool_mode (operands[1]) == DImode
1847 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1848 [(set (match_dup 0) (match_dup 2))]
1849 "operands[2] = get_pool_constant (operands[1]);")
1851 (define_insn "*la_64"
1852 [(set (match_operand:DI 0 "register_operand" "=d,d")
1853 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
1858 [(set_attr "op_type" "RX,RXY")
1859 (set_attr "type" "la")
1860 (set_attr "cpu_facility" "*,longdisp")
1861 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1865 [(set (match_operand:DI 0 "register_operand" "")
1866 (match_operand:QI 1 "address_operand" ""))
1867 (clobber (reg:CC CC_REGNUM))])]
1869 && preferred_la_operand_p (operands[1], const0_rtx)"
1870 [(set (match_dup 0) (match_dup 1))]
1874 [(set (match_operand:DI 0 "register_operand" "")
1875 (match_operand:DI 1 "register_operand" ""))
1878 (plus:DI (match_dup 0)
1879 (match_operand:DI 2 "nonmemory_operand" "")))
1880 (clobber (reg:CC CC_REGNUM))])]
1882 && !reg_overlap_mentioned_p (operands[0], operands[2])
1883 && preferred_la_operand_p (operands[1], operands[2])"
1884 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1888 ; movsi instruction pattern(s).
1891 (define_expand "movsi"
1892 [(set (match_operand:SI 0 "general_operand" "")
1893 (match_operand:SI 1 "general_operand" ""))]
1896 /* Handle symbolic constants. */
1898 && (SYMBOLIC_CONST (operands[1])
1899 || (GET_CODE (operands[1]) == PLUS
1900 && XEXP (operands[1], 0) == pic_offset_table_rtx
1901 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1902 emit_symbolic_move (operands);
1905 (define_insn "*movsi_larl"
1906 [(set (match_operand:SI 0 "register_operand" "=d")
1907 (match_operand:SI 1 "larl_operand" "X"))]
1908 "!TARGET_64BIT && TARGET_CPU_ZARCH
1909 && !FP_REG_P (operands[0])"
1911 [(set_attr "op_type" "RIL")
1912 (set_attr "type" "larl")
1913 (set_attr "z10prop" "z10_fwd_A1")])
1915 (define_insn "*movsi_zarch"
1916 [(set (match_operand:SI 0 "nonimmediate_operand"
1917 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
1918 (match_operand:SI 1 "general_operand"
1919 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
1952 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1953 RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1954 (set_attr "type" "*,
1978 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1979 vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1980 (set_attr "z10prop" "z10_fwd_A1,
2005 (define_insn "*movsi_esa"
2006 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
2007 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
2023 [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
2024 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
2025 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
2027 (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
2031 [(set (match_operand:SI 0 "register_operand" "")
2032 (mem:SI (match_operand 1 "address_operand" "")))]
2033 "!FP_REG_P (operands[0])
2034 && GET_CODE (operands[1]) == SYMBOL_REF
2035 && CONSTANT_POOL_ADDRESS_P (operands[1])
2036 && get_pool_mode (operands[1]) == SImode
2037 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
2038 [(set (match_dup 0) (match_dup 2))]
2039 "operands[2] = get_pool_constant (operands[1]);")
2041 (define_insn "*la_31"
2042 [(set (match_operand:SI 0 "register_operand" "=d,d")
2043 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
2044 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
2048 [(set_attr "op_type" "RX,RXY")
2049 (set_attr "type" "la")
2050 (set_attr "cpu_facility" "*,longdisp")
2051 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2055 [(set (match_operand:SI 0 "register_operand" "")
2056 (match_operand:QI 1 "address_operand" ""))
2057 (clobber (reg:CC CC_REGNUM))])]
2059 && preferred_la_operand_p (operands[1], const0_rtx)"
2060 [(set (match_dup 0) (match_dup 1))]
2064 [(set (match_operand:SI 0 "register_operand" "")
2065 (match_operand:SI 1 "register_operand" ""))
2068 (plus:SI (match_dup 0)
2069 (match_operand:SI 2 "nonmemory_operand" "")))
2070 (clobber (reg:CC CC_REGNUM))])]
2072 && !reg_overlap_mentioned_p (operands[0], operands[2])
2073 && preferred_la_operand_p (operands[1], operands[2])"
2074 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2077 (define_insn "*la_31_and"
2078 [(set (match_operand:SI 0 "register_operand" "=d,d")
2079 (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
2080 (const_int 2147483647)))]
2085 [(set_attr "op_type" "RX,RXY")
2086 (set_attr "type" "la")
2087 (set_attr "cpu_facility" "*,longdisp")
2088 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2090 (define_insn_and_split "*la_31_and_cc"
2091 [(set (match_operand:SI 0 "register_operand" "=d")
2092 (and:SI (match_operand:QI 1 "address_operand" "p")
2093 (const_int 2147483647)))
2094 (clobber (reg:CC CC_REGNUM))]
2097 "&& reload_completed"
2099 (and:SI (match_dup 1) (const_int 2147483647)))]
2101 [(set_attr "op_type" "RX")
2102 (set_attr "type" "la")])
2104 (define_insn "force_la_31"
2105 [(set (match_operand:SI 0 "register_operand" "=d,d")
2106 (match_operand:QI 1 "address_operand" "ZR,ZT"))
2107 (use (const_int 0))]
2112 [(set_attr "op_type" "RX")
2113 (set_attr "type" "la")
2114 (set_attr "cpu_facility" "*,longdisp")
2115 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2118 ; movhi instruction pattern(s).
2121 (define_expand "movhi"
2122 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2123 (match_operand:HI 1 "general_operand" ""))]
2126 /* Make it explicit that loading a register from memory
2127 always sign-extends (at least) to SImode. */
2128 if (optimize && can_create_pseudo_p ()
2129 && register_operand (operands[0], VOIDmode)
2130 && GET_CODE (operands[1]) == MEM)
2132 rtx tmp = gen_reg_rtx (SImode);
2133 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2134 emit_insn (gen_rtx_SET (tmp, ext));
2135 operands[1] = gen_lowpart (HImode, tmp);
2139 (define_insn "*movhi"
2140 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
2141 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
2159 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2160 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2161 (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vec,vec,vec,vec,vec,vec")
2162 (set_attr "z10prop" "z10_fr_E1,
2170 z10_super,*,*,*,*,*,*")])
2173 [(set (match_operand:HI 0 "register_operand" "")
2174 (mem:HI (match_operand 1 "address_operand" "")))]
2175 "GET_CODE (operands[1]) == SYMBOL_REF
2176 && CONSTANT_POOL_ADDRESS_P (operands[1])
2177 && get_pool_mode (operands[1]) == HImode
2178 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2179 [(set (match_dup 0) (match_dup 2))]
2180 "operands[2] = get_pool_constant (operands[1]);")
2183 ; movqi instruction pattern(s).
2186 (define_expand "movqi"
2187 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2188 (match_operand:QI 1 "general_operand" ""))]
2191 /* On z/Architecture, zero-extending from memory to register
2192 is just as fast as a QImode load. */
2193 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2194 && register_operand (operands[0], VOIDmode)
2195 && GET_CODE (operands[1]) == MEM)
2197 rtx tmp = gen_reg_rtx (DImode);
2198 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2199 emit_insn (gen_rtx_SET (tmp, ext));
2200 operands[1] = gen_lowpart (QImode, tmp);
2204 (define_insn "*movqi"
2205 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
2206 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
2224 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2225 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2226 (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vec,vec,vec,vec,vec,vec")
2227 (set_attr "z10prop" "z10_fr_E1,
2238 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2239 (mem:QI (match_operand 1 "address_operand" "")))]
2240 "GET_CODE (operands[1]) == SYMBOL_REF
2241 && CONSTANT_POOL_ADDRESS_P (operands[1])
2242 && get_pool_mode (operands[1]) == QImode
2243 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2244 [(set (match_dup 0) (match_dup 2))]
2245 "operands[2] = get_pool_constant (operands[1]);")
2248 ; movstrictqi instruction pattern(s).
2251 (define_insn "*movstrictqi"
2252 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2253 (match_operand:QI 1 "memory_operand" "R,T"))]
2258 [(set_attr "op_type" "RX,RXY")
2259 (set_attr "cpu_facility" "*,longdisp")
2260 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2263 ; movstricthi instruction pattern(s).
2266 (define_insn "*movstricthi"
2267 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2268 (match_operand:HI 1 "memory_operand" "Q,S"))
2269 (clobber (reg:CC CC_REGNUM))]
2274 [(set_attr "op_type" "RS,RSY")
2275 (set_attr "cpu_facility" "*,longdisp")
2276 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2279 ; movstrictsi instruction pattern(s).
2282 (define_insn "movstrictsi"
2283 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2284 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2291 [(set_attr "op_type" "RR,RX,RXY,RRE")
2292 (set_attr "type" "lr,load,load,*")
2293 (set_attr "cpu_facility" "*,*,longdisp,*")
2294 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2297 ; mov(tf|td) instruction pattern(s).
2300 (define_expand "mov<mode>"
2301 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2302 (match_operand:TD_TF 1 "general_operand" ""))]
2306 (define_insn "*mov<mode>_64"
2307 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
2308 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
2319 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2320 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2321 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2323 (define_insn "*mov<mode>_31"
2324 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2325 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2332 [(set_attr "op_type" "RRE,RRE,*,*")
2333 (set_attr "type" "fsimptf,fsimptf,*,*")
2334 (set_attr "cpu_facility" "z196,*,*,*")])
2336 ; TFmode in GPRs splitters
2339 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2340 (match_operand:TD_TF 1 "general_operand" ""))]
2341 "TARGET_ZARCH && reload_completed
2342 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2343 [(set (match_dup 2) (match_dup 4))
2344 (set (match_dup 3) (match_dup 5))]
2346 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2347 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2348 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2349 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2353 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2354 (match_operand:TD_TF 1 "general_operand" ""))]
2355 "TARGET_ZARCH && reload_completed
2356 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2357 [(set (match_dup 2) (match_dup 4))
2358 (set (match_dup 3) (match_dup 5))]
2360 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2361 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2362 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2363 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2367 [(set (match_operand:TD_TF 0 "register_operand" "")
2368 (match_operand:TD_TF 1 "memory_operand" ""))]
2369 "TARGET_ZARCH && reload_completed
2370 && GENERAL_REG_P (operands[0])
2371 && !s_operand (operands[1], VOIDmode)"
2372 [(set (match_dup 0) (match_dup 1))]
2374 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2375 addr = gen_lowpart (Pmode, addr);
2376 s390_load_address (addr, XEXP (operands[1], 0));
2377 operands[1] = replace_equiv_address (operands[1], addr);
2380 ; TFmode in BFPs splitters
2383 [(set (match_operand:TD_TF 0 "register_operand" "")
2384 (match_operand:TD_TF 1 "memory_operand" ""))]
2385 "reload_completed && offsettable_memref_p (operands[1])
2386 && FP_REG_P (operands[0])"
2387 [(set (match_dup 2) (match_dup 4))
2388 (set (match_dup 3) (match_dup 5))]
2390 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2392 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2394 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2395 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2399 [(set (match_operand:TD_TF 0 "memory_operand" "")
2400 (match_operand:TD_TF 1 "register_operand" ""))]
2401 "reload_completed && offsettable_memref_p (operands[0])
2402 && FP_REG_P (operands[1])"
2403 [(set (match_dup 2) (match_dup 4))
2404 (set (match_dup 3) (match_dup 5))]
2406 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2407 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2408 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2410 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2415 ; mov(df|dd) instruction pattern(s).
2418 (define_expand "mov<mode>"
2419 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2420 (match_operand:DD_DF 1 "general_operand" ""))]
2424 (define_insn "*mov<mode>_64dfp"
2425 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2426 "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,d,v,R")
2427 (match_operand:DD_DF 1 "general_operand"
2428 " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,d,v,R,v"))]
2450 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2451 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2452 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2453 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2454 (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2456 (define_insn "*mov<mode>_64"
2457 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R")
2458 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d,v,R,v"))]
2476 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2477 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2478 fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2479 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2480 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec")])
2482 (define_insn "*mov<mode>_31"
2483 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2484 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2485 (match_operand:DD_DF 1 "general_operand"
2486 " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
2501 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2502 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2503 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2504 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
2507 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2508 (match_operand:DD_DF 1 "general_operand" ""))]
2509 "!TARGET_ZARCH && reload_completed
2510 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2511 [(set (match_dup 2) (match_dup 4))
2512 (set (match_dup 3) (match_dup 5))]
2514 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2515 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2516 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2517 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2521 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2522 (match_operand:DD_DF 1 "general_operand" ""))]
2523 "!TARGET_ZARCH && reload_completed
2524 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2525 [(set (match_dup 2) (match_dup 4))
2526 (set (match_dup 3) (match_dup 5))]
2528 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2529 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2530 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2531 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2535 [(set (match_operand:DD_DF 0 "register_operand" "")
2536 (match_operand:DD_DF 1 "memory_operand" ""))]
2537 "!TARGET_ZARCH && reload_completed
2538 && !FP_REG_P (operands[0])
2539 && !s_operand (operands[1], VOIDmode)"
2540 [(set (match_dup 0) (match_dup 1))]
2542 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2543 s390_load_address (addr, XEXP (operands[1], 0));
2544 operands[1] = replace_equiv_address (operands[1], addr);
2548 ; mov(sf|sd) instruction pattern(s).
2551 (define_insn "mov<mode>"
2552 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2553 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
2554 (match_operand:SD_SF 1 "general_operand"
2555 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
2580 [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2581 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2582 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2583 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2584 (set_attr "cpu_facility" "z196,vec,*,vec,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vec,vec,vec,vec,vec,vec")])
2587 ; movcc instruction pattern
2590 (define_insn "movcc"
2591 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2592 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2602 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2603 (set_attr "type" "lr,*,*,load,load,store,store")
2604 (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
2605 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2606 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2609 ; Block move (MVC) patterns.
2613 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2614 (match_operand:BLK 1 "memory_operand" "Q"))
2615 (use (match_operand 2 "const_int_operand" "n"))]
2616 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2617 "mvc\t%O0(%2,%R0),%S1"
2618 [(set_attr "op_type" "SS")])
2620 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2621 ; order to have it implemented with mvc.
2624 [(set (match_operand:QI 0 "memory_operand" "")
2625 (match_operand:QI 1 "memory_operand" ""))]
2628 [(set (match_dup 0) (match_dup 1))
2629 (use (const_int 1))])]
2631 operands[0] = adjust_address (operands[0], BLKmode, 0);
2632 operands[1] = adjust_address (operands[1], BLKmode, 0);
2638 [(set (match_operand:BLK 0 "memory_operand" "")
2639 (match_operand:BLK 1 "memory_operand" ""))
2640 (use (match_operand 2 "const_int_operand" ""))])
2642 [(set (match_operand:BLK 3 "memory_operand" "")
2643 (match_operand:BLK 4 "memory_operand" ""))
2644 (use (match_operand 5 "const_int_operand" ""))])]
2645 "s390_offset_p (operands[0], operands[3], operands[2])
2646 && s390_offset_p (operands[1], operands[4], operands[2])
2647 && !s390_overlap_p (operands[0], operands[1],
2648 INTVAL (operands[2]) + INTVAL (operands[5]))
2649 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2651 [(set (match_dup 6) (match_dup 7))
2652 (use (match_dup 8))])]
2653 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2654 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2655 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2659 ; load_multiple pattern(s).
2661 ; ??? Due to reload problems with replacing registers inside match_parallel
2662 ; we currently support load_multiple/store_multiple only after reload.
2665 (define_expand "load_multiple"
2666 [(match_par_dup 3 [(set (match_operand 0 "" "")
2667 (match_operand 1 "" ""))
2668 (use (match_operand 2 "" ""))])]
2677 /* Support only loading a constant number of fixed-point registers from
2678 memory and only bother with this if more than two */
2679 if (GET_CODE (operands[2]) != CONST_INT
2680 || INTVAL (operands[2]) < 2
2681 || INTVAL (operands[2]) > 16
2682 || GET_CODE (operands[1]) != MEM
2683 || GET_CODE (operands[0]) != REG
2684 || REGNO (operands[0]) >= 16)
2687 count = INTVAL (operands[2]);
2688 regno = REGNO (operands[0]);
2689 mode = GET_MODE (operands[0]);
2690 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2693 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2694 if (!can_create_pseudo_p ())
2696 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2698 from = XEXP (operands[1], 0);
2701 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2702 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2703 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2705 from = XEXP (XEXP (operands[1], 0), 0);
2706 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2713 from = force_reg (Pmode, XEXP (operands[1], 0));
2717 for (i = 0; i < count; i++)
2718 XVECEXP (operands[3], 0, i)
2719 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2720 change_address (operands[1], mode,
2721 plus_constant (Pmode, from,
2722 off + i * GET_MODE_SIZE (mode))));
2725 (define_insn "*load_multiple_di"
2726 [(match_parallel 0 "load_multiple_operation"
2727 [(set (match_operand:DI 1 "register_operand" "=r")
2728 (match_operand:DI 2 "s_operand" "S"))])]
2729 "reload_completed && TARGET_ZARCH"
2731 int words = XVECLEN (operands[0], 0);
2732 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2733 return "lmg\t%1,%0,%S2";
2735 [(set_attr "op_type" "RSY")
2736 (set_attr "type" "lm")])
2738 (define_insn "*load_multiple_si"
2739 [(match_parallel 0 "load_multiple_operation"
2740 [(set (match_operand:SI 1 "register_operand" "=r,r")
2741 (match_operand:SI 2 "s_operand" "Q,S"))])]
2744 int words = XVECLEN (operands[0], 0);
2745 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2746 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2748 [(set_attr "op_type" "RS,RSY")
2749 (set_attr "cpu_facility" "*,longdisp")
2750 (set_attr "type" "lm")])
2753 ; store multiple pattern(s).
2756 (define_expand "store_multiple"
2757 [(match_par_dup 3 [(set (match_operand 0 "" "")
2758 (match_operand 1 "" ""))
2759 (use (match_operand 2 "" ""))])]
2768 /* Support only storing a constant number of fixed-point registers to
2769 memory and only bother with this if more than two. */
2770 if (GET_CODE (operands[2]) != CONST_INT
2771 || INTVAL (operands[2]) < 2
2772 || INTVAL (operands[2]) > 16
2773 || GET_CODE (operands[0]) != MEM
2774 || GET_CODE (operands[1]) != REG
2775 || REGNO (operands[1]) >= 16)
2778 count = INTVAL (operands[2]);
2779 regno = REGNO (operands[1]);
2780 mode = GET_MODE (operands[1]);
2781 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2784 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2786 if (!can_create_pseudo_p ())
2788 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2790 to = XEXP (operands[0], 0);
2793 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2794 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2795 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2797 to = XEXP (XEXP (operands[0], 0), 0);
2798 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2805 to = force_reg (Pmode, XEXP (operands[0], 0));
2809 for (i = 0; i < count; i++)
2810 XVECEXP (operands[3], 0, i)
2811 = gen_rtx_SET (change_address (operands[0], mode,
2812 plus_constant (Pmode, to,
2813 off + i * GET_MODE_SIZE (mode))),
2814 gen_rtx_REG (mode, regno + i));
2817 (define_insn "*store_multiple_di"
2818 [(match_parallel 0 "store_multiple_operation"
2819 [(set (match_operand:DI 1 "s_operand" "=S")
2820 (match_operand:DI 2 "register_operand" "r"))])]
2821 "reload_completed && TARGET_ZARCH"
2823 int words = XVECLEN (operands[0], 0);
2824 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2825 return "stmg\t%2,%0,%S1";
2827 [(set_attr "op_type" "RSY")
2828 (set_attr "type" "stm")])
2831 (define_insn "*store_multiple_si"
2832 [(match_parallel 0 "store_multiple_operation"
2833 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2834 (match_operand:SI 2 "register_operand" "r,r"))])]
2837 int words = XVECLEN (operands[0], 0);
2838 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2839 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2841 [(set_attr "op_type" "RS,RSY")
2842 (set_attr "cpu_facility" "*,longdisp")
2843 (set_attr "type" "stm")])
2846 ;; String instructions.
2849 (define_insn "*execute_rl"
2850 [(match_parallel 0 "execute_operation"
2851 [(unspec [(match_operand 1 "register_operand" "a")
2852 (match_operand 2 "" "")
2853 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2854 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2855 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2857 [(set_attr "op_type" "RIL")
2858 (set_attr "type" "cs")])
2860 (define_insn "*execute"
2861 [(match_parallel 0 "execute_operation"
2862 [(unspec [(match_operand 1 "register_operand" "a")
2863 (match_operand:BLK 2 "memory_operand" "R")
2864 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2865 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2866 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2868 [(set_attr "op_type" "RX")
2869 (set_attr "type" "cs")])
2873 ; strlenM instruction pattern(s).
2876 (define_expand "strlen<mode>"
2877 [(match_operand:P 0 "register_operand" "") ; result
2878 (match_operand:BLK 1 "memory_operand" "") ; input string
2879 (match_operand:SI 2 "immediate_operand" "") ; search character
2880 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2883 if (!TARGET_VX || operands[2] != const0_rtx)
2884 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2885 operands[2], operands[3]));
2887 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2892 (define_expand "strlen_srst<mode>"
2893 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2896 (unspec:P [(const_int 0)
2897 (match_operand:BLK 1 "memory_operand" "")
2899 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2900 (clobber (scratch:P))
2901 (clobber (reg:CC CC_REGNUM))])
2903 [(set (match_operand:P 0 "register_operand" "")
2904 (minus:P (match_dup 4) (match_dup 5)))
2905 (clobber (reg:CC CC_REGNUM))])]
2908 operands[4] = gen_reg_rtx (Pmode);
2909 operands[5] = gen_reg_rtx (Pmode);
2910 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2911 operands[1] = replace_equiv_address (operands[1], operands[5]);
2914 (define_insn "*strlen<mode>"
2915 [(set (match_operand:P 0 "register_operand" "=a")
2916 (unspec:P [(match_operand:P 2 "general_operand" "0")
2917 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2919 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2920 (clobber (match_scratch:P 1 "=a"))
2921 (clobber (reg:CC CC_REGNUM))]
2923 "srst\t%0,%1\;jo\t.-4"
2924 [(set_attr "length" "8")
2925 (set_attr "type" "vs")])
2928 ; cmpstrM instruction pattern(s).
2931 (define_expand "cmpstrsi"
2932 [(set (reg:SI 0) (const_int 0))
2934 [(clobber (match_operand 3 "" ""))
2935 (clobber (match_dup 4))
2936 (set (reg:CCU CC_REGNUM)
2937 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2938 (match_operand:BLK 2 "memory_operand" "")))
2941 [(set (match_operand:SI 0 "register_operand" "=d")
2942 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2943 (clobber (reg:CC CC_REGNUM))])]
2946 /* As the result of CMPINT is inverted compared to what we need,
2947 we have to swap the operands. */
2948 rtx op1 = operands[2];
2949 rtx op2 = operands[1];
2950 rtx addr1 = gen_reg_rtx (Pmode);
2951 rtx addr2 = gen_reg_rtx (Pmode);
2953 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2954 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2955 operands[1] = replace_equiv_address_nv (op1, addr1);
2956 operands[2] = replace_equiv_address_nv (op2, addr2);
2957 operands[3] = addr1;
2958 operands[4] = addr2;
2961 (define_insn "*cmpstr<mode>"
2962 [(clobber (match_operand:P 0 "register_operand" "=d"))
2963 (clobber (match_operand:P 1 "register_operand" "=d"))
2964 (set (reg:CCU CC_REGNUM)
2965 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2966 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2969 "clst\t%0,%1\;jo\t.-4"
2970 [(set_attr "length" "8")
2971 (set_attr "type" "vs")])
2974 ; movstr instruction pattern.
2977 (define_expand "movstr"
2978 [(match_operand 0 "register_operand" "")
2979 (match_operand 1 "memory_operand" "")
2980 (match_operand 2 "memory_operand" "")]
2984 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2986 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2990 (define_expand "movstr<P:mode>"
2991 [(set (reg:SI 0) (const_int 0))
2993 [(clobber (match_dup 3))
2994 (set (match_operand:BLK 1 "memory_operand" "")
2995 (match_operand:BLK 2 "memory_operand" ""))
2996 (set (match_operand:P 0 "register_operand" "")
2997 (unspec:P [(match_dup 1)
2999 (reg:SI 0)] UNSPEC_MVST))
3000 (clobber (reg:CC CC_REGNUM))])]
3005 if (TARGET_VX && optimize_function_for_speed_p (cfun))
3007 s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
3011 addr1 = gen_reg_rtx (Pmode);
3012 addr2 = gen_reg_rtx (Pmode);
3014 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3015 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
3016 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3017 operands[2] = replace_equiv_address_nv (operands[2], addr2);
3018 operands[3] = addr2;
3021 (define_insn "*movstr"
3022 [(clobber (match_operand:P 2 "register_operand" "=d"))
3023 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
3024 (mem:BLK (match_operand:P 3 "register_operand" "2")))
3025 (set (match_operand:P 0 "register_operand" "=d")
3026 (unspec:P [(mem:BLK (match_dup 1))
3027 (mem:BLK (match_dup 3))
3028 (reg:SI 0)] UNSPEC_MVST))
3029 (clobber (reg:CC CC_REGNUM))]
3031 "mvst\t%1,%2\;jo\t.-4"
3032 [(set_attr "length" "8")
3033 (set_attr "type" "vs")])
3037 ; movmemM instruction pattern(s).
3040 (define_expand "movmem<mode>"
3041 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
3042 (match_operand:BLK 1 "memory_operand" "")) ; source
3043 (use (match_operand:GPR 2 "general_operand" "")) ; count
3044 (match_operand 3 "" "")]
3047 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
3053 ; Move a block that is up to 256 bytes in length.
3054 ; The block length is taken as (operands[2] % 256) + 1.
3056 (define_expand "movmem_short"
3058 [(set (match_operand:BLK 0 "memory_operand" "")
3059 (match_operand:BLK 1 "memory_operand" ""))
3060 (use (match_operand 2 "nonmemory_operand" ""))
3061 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3062 (clobber (match_dup 3))])]
3064 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3066 (define_insn "*movmem_short"
3067 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3068 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3069 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3070 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3071 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3072 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3074 [(set_attr "type" "cs")
3075 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3078 [(set (match_operand:BLK 0 "memory_operand" "")
3079 (match_operand:BLK 1 "memory_operand" ""))
3080 (use (match_operand 2 "const_int_operand" ""))
3081 (use (match_operand 3 "immediate_operand" ""))
3082 (clobber (scratch))]
3085 [(set (match_dup 0) (match_dup 1))
3086 (use (match_dup 2))])]
3087 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3090 [(set (match_operand:BLK 0 "memory_operand" "")
3091 (match_operand:BLK 1 "memory_operand" ""))
3092 (use (match_operand 2 "register_operand" ""))
3093 (use (match_operand 3 "memory_operand" ""))
3094 (clobber (scratch))]
3097 [(unspec [(match_dup 2) (match_dup 3)
3098 (const_int 0)] UNSPEC_EXECUTE)
3099 (set (match_dup 0) (match_dup 1))
3100 (use (const_int 1))])]
3104 [(set (match_operand:BLK 0 "memory_operand" "")
3105 (match_operand:BLK 1 "memory_operand" ""))
3106 (use (match_operand 2 "register_operand" ""))
3107 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3108 (clobber (scratch))]
3109 "TARGET_Z10 && reload_completed"
3111 [(unspec [(match_dup 2) (const_int 0)
3112 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3113 (set (match_dup 0) (match_dup 1))
3114 (use (const_int 1))])]
3115 "operands[3] = gen_label_rtx ();")
3118 [(set (match_operand:BLK 0 "memory_operand" "")
3119 (match_operand:BLK 1 "memory_operand" ""))
3120 (use (match_operand 2 "register_operand" ""))
3121 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3122 (clobber (match_operand 3 "register_operand" ""))]
3123 "reload_completed && TARGET_CPU_ZARCH"
3124 [(set (match_dup 3) (label_ref (match_dup 4)))
3126 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3127 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3128 (set (match_dup 0) (match_dup 1))
3129 (use (const_int 1))])]
3130 "operands[4] = gen_label_rtx ();")
3132 ; Move a block of arbitrary length.
3134 (define_expand "movmem_long"
3136 [(clobber (match_dup 2))
3137 (clobber (match_dup 3))
3138 (set (match_operand:BLK 0 "memory_operand" "")
3139 (match_operand:BLK 1 "memory_operand" ""))
3140 (use (match_operand 2 "general_operand" ""))
3142 (clobber (reg:CC CC_REGNUM))])]
3145 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3146 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3147 rtx reg0 = gen_reg_rtx (dreg_mode);
3148 rtx reg1 = gen_reg_rtx (dreg_mode);
3149 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3150 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3151 rtx len0 = gen_lowpart (Pmode, reg0);
3152 rtx len1 = gen_lowpart (Pmode, reg1);
3154 emit_clobber (reg0);
3155 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3156 emit_move_insn (len0, operands[2]);
3158 emit_clobber (reg1);
3159 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3160 emit_move_insn (len1, operands[2]);
3162 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3163 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3168 (define_insn "*movmem_long"
3169 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3170 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3171 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3172 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3175 (clobber (reg:CC CC_REGNUM))]
3176 "TARGET_64BIT || !TARGET_ZARCH"
3177 "mvcle\t%0,%1,0\;jo\t.-4"
3178 [(set_attr "length" "8")
3179 (set_attr "type" "vs")])
3181 (define_insn "*movmem_long_31z"
3182 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3183 (clobber (match_operand:TI 1 "register_operand" "=d"))
3184 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3185 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3188 (clobber (reg:CC CC_REGNUM))]
3189 "!TARGET_64BIT && TARGET_ZARCH"
3190 "mvcle\t%0,%1,0\;jo\t.-4"
3191 [(set_attr "length" "8")
3192 (set_attr "type" "vs")])
3199 (define_expand "signbit<mode>2"
3200 [(set (reg:CCZ CC_REGNUM)
3201 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3204 (set (match_operand:SI 0 "register_operand" "=d")
3205 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3208 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3211 (define_expand "isinf<mode>2"
3212 [(set (reg:CCZ CC_REGNUM)
3213 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3216 (set (match_operand:SI 0 "register_operand" "=d")
3217 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3220 operands[2] = GEN_INT (S390_TDC_INFINITY);
3223 ; This extracts CC into a GPR properly shifted. The actual IPM
3224 ; instruction will be issued by reload. The constraint of operand 1
3225 ; forces reload to use a GPR. So reload will issue a movcc insn for
3226 ; copying CC into a GPR first.
3227 (define_insn_and_split "*cc_to_int"
3228 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3229 (unspec:SI [(match_operand 1 "register_operand" "0")]
3234 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3236 ; This insn is used to generate all variants of the Test Data Class
3237 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3238 ; is the register to be tested and the second one is the bit mask
3239 ; specifying the required test(s).
3241 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3242 (define_insn "*TDC_insn_<mode>"
3243 [(set (reg:CCZ CC_REGNUM)
3244 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3245 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3247 "t<_d>c<xde><bt>\t%0,%1"
3248 [(set_attr "op_type" "RXE")
3249 (set_attr "type" "fsimp<mode>")])
3254 ; setmemM instruction pattern(s).
3257 (define_expand "setmem<mode>"
3258 [(set (match_operand:BLK 0 "memory_operand" "")
3259 (match_operand:QI 2 "general_operand" ""))
3260 (use (match_operand:GPR 1 "general_operand" ""))
3261 (match_operand 3 "" "")]
3263 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3265 ; Clear a block that is up to 256 bytes in length.
3266 ; The block length is taken as (operands[1] % 256) + 1.
3268 (define_expand "clrmem_short"
3270 [(set (match_operand:BLK 0 "memory_operand" "")
3272 (use (match_operand 1 "nonmemory_operand" ""))
3273 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3274 (clobber (match_dup 2))
3275 (clobber (reg:CC CC_REGNUM))])]
3277 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3279 (define_insn "*clrmem_short"
3280 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3282 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3283 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3284 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3285 (clobber (reg:CC CC_REGNUM))]
3286 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3288 [(set_attr "type" "cs")
3289 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3292 [(set (match_operand:BLK 0 "memory_operand" "")
3294 (use (match_operand 1 "const_int_operand" ""))
3295 (use (match_operand 2 "immediate_operand" ""))
3297 (clobber (reg:CC CC_REGNUM))]
3300 [(set (match_dup 0) (const_int 0))
3302 (clobber (reg:CC CC_REGNUM))])]
3303 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3306 [(set (match_operand:BLK 0 "memory_operand" "")
3308 (use (match_operand 1 "register_operand" ""))
3309 (use (match_operand 2 "memory_operand" ""))
3311 (clobber (reg:CC CC_REGNUM))]
3314 [(unspec [(match_dup 1) (match_dup 2)
3315 (const_int 0)] UNSPEC_EXECUTE)
3316 (set (match_dup 0) (const_int 0))
3318 (clobber (reg:CC CC_REGNUM))])]
3322 [(set (match_operand:BLK 0 "memory_operand" "")
3324 (use (match_operand 1 "register_operand" ""))
3325 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3327 (clobber (reg:CC CC_REGNUM))]
3328 "TARGET_Z10 && reload_completed"
3330 [(unspec [(match_dup 1) (const_int 0)
3331 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3332 (set (match_dup 0) (const_int 0))
3334 (clobber (reg:CC CC_REGNUM))])]
3335 "operands[3] = gen_label_rtx ();")
3338 [(set (match_operand:BLK 0 "memory_operand" "")
3340 (use (match_operand 1 "register_operand" ""))
3341 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3342 (clobber (match_operand 2 "register_operand" ""))
3343 (clobber (reg:CC CC_REGNUM))]
3344 "reload_completed && TARGET_CPU_ZARCH"
3345 [(set (match_dup 2) (label_ref (match_dup 3)))
3347 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3348 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3349 (set (match_dup 0) (const_int 0))
3351 (clobber (reg:CC CC_REGNUM))])]
3352 "operands[3] = gen_label_rtx ();")
3354 ; Initialize a block of arbitrary length with (operands[2] % 256).
3356 (define_expand "setmem_long_<P:mode>"
3358 [(clobber (match_dup 1))
3359 (set (match_operand:BLK 0 "memory_operand" "")
3360 (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
3361 (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3363 (clobber (reg:CC CC_REGNUM))])]
3366 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3367 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3368 rtx reg0 = gen_reg_rtx (dreg_mode);
3369 rtx reg1 = gen_reg_rtx (dreg_mode);
3370 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3371 rtx len0 = gen_lowpart (Pmode, reg0);
3373 emit_clobber (reg0);
3374 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3375 emit_move_insn (len0, operands[1]);
3377 emit_move_insn (reg1, const0_rtx);
3379 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3382 operands[4] = gen_lowpart (Pmode, operands[1]);
3385 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3387 (define_insn "*setmem_long"
3388 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3389 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3390 (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
3391 (subreg:P (match_dup 3) <modesize>)]
3392 UNSPEC_REPLICATE_BYTE))
3393 (use (match_operand:<DBL> 1 "register_operand" "d"))
3394 (clobber (reg:CC CC_REGNUM))]
3395 "TARGET_64BIT || !TARGET_ZARCH"
3396 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3397 [(set_attr "length" "8")
3398 (set_attr "type" "vs")])
3400 (define_insn "*setmem_long_and"
3401 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3402 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3404 (match_operand:P 2 "setmem_operand" "Y")
3405 (match_operand:P 4 "const_int_operand" "n"))
3406 (subreg:P (match_dup 3) <modesize>)]
3407 UNSPEC_REPLICATE_BYTE))
3408 (use (match_operand:<DBL> 1 "register_operand" "d"))
3409 (clobber (reg:CC CC_REGNUM))]
3410 "(TARGET_64BIT || !TARGET_ZARCH) &&
3411 (INTVAL (operands[4]) & 255) == 255"
3412 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3413 [(set_attr "length" "8")
3414 (set_attr "type" "vs")])
3416 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3417 ; of the SImode subregs.
3419 (define_insn "*setmem_long_31z"
3420 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3421 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3422 (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
3423 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3424 (use (match_operand:TI 1 "register_operand" "d"))
3425 (clobber (reg:CC CC_REGNUM))]
3426 "!TARGET_64BIT && TARGET_ZARCH"
3427 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3428 [(set_attr "length" "8")
3429 (set_attr "type" "vs")])
3431 (define_insn "*setmem_long_and_31z"
3432 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3433 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3434 (unspec:BLK [(and:SI
3435 (match_operand:SI 2 "setmem_operand" "Y")
3436 (match_operand:SI 4 "const_int_operand" "n"))
3437 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3438 (use (match_operand:TI 1 "register_operand" "d"))
3439 (clobber (reg:CC CC_REGNUM))]
3440 "(!TARGET_64BIT && TARGET_ZARCH) &&
3441 (INTVAL (operands[4]) & 255) == 255"
3442 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3443 [(set_attr "length" "8")
3444 (set_attr "type" "vs")])
3447 ; cmpmemM instruction pattern(s).
3450 (define_expand "cmpmemsi"
3451 [(set (match_operand:SI 0 "register_operand" "")
3452 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3453 (match_operand:BLK 2 "memory_operand" "") ) )
3454 (use (match_operand:SI 3 "general_operand" ""))
3455 (use (match_operand:SI 4 "" ""))]
3458 if (s390_expand_cmpmem (operands[0], operands[1],
3459 operands[2], operands[3]))
3465 ; Compare a block that is up to 256 bytes in length.
3466 ; The block length is taken as (operands[2] % 256) + 1.
3468 (define_expand "cmpmem_short"
3470 [(set (reg:CCU CC_REGNUM)
3471 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3472 (match_operand:BLK 1 "memory_operand" "")))
3473 (use (match_operand 2 "nonmemory_operand" ""))
3474 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3475 (clobber (match_dup 3))])]
3477 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3479 (define_insn "*cmpmem_short"
3480 [(set (reg:CCU CC_REGNUM)
3481 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3482 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3483 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3484 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3485 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3486 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3488 [(set_attr "type" "cs")
3489 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3492 [(set (reg:CCU CC_REGNUM)
3493 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3494 (match_operand:BLK 1 "memory_operand" "")))
3495 (use (match_operand 2 "const_int_operand" ""))
3496 (use (match_operand 3 "immediate_operand" ""))
3497 (clobber (scratch))]
3500 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3501 (use (match_dup 2))])]
3502 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3505 [(set (reg:CCU CC_REGNUM)
3506 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3507 (match_operand:BLK 1 "memory_operand" "")))
3508 (use (match_operand 2 "register_operand" ""))
3509 (use (match_operand 3 "memory_operand" ""))
3510 (clobber (scratch))]
3513 [(unspec [(match_dup 2) (match_dup 3)
3514 (const_int 0)] UNSPEC_EXECUTE)
3515 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3516 (use (const_int 1))])]
3520 [(set (reg:CCU CC_REGNUM)
3521 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3522 (match_operand:BLK 1 "memory_operand" "")))
3523 (use (match_operand 2 "register_operand" ""))
3524 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3525 (clobber (scratch))]
3526 "TARGET_Z10 && reload_completed"
3528 [(unspec [(match_dup 2) (const_int 0)
3529 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3530 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3531 (use (const_int 1))])]
3532 "operands[4] = gen_label_rtx ();")
3535 [(set (reg:CCU CC_REGNUM)
3536 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3537 (match_operand:BLK 1 "memory_operand" "")))
3538 (use (match_operand 2 "register_operand" ""))
3539 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3540 (clobber (match_operand 3 "register_operand" ""))]
3541 "reload_completed && TARGET_CPU_ZARCH"
3542 [(set (match_dup 3) (label_ref (match_dup 4)))
3544 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3545 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3546 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3547 (use (const_int 1))])]
3548 "operands[4] = gen_label_rtx ();")
3550 ; Compare a block of arbitrary length.
3552 (define_expand "cmpmem_long"
3554 [(clobber (match_dup 2))
3555 (clobber (match_dup 3))
3556 (set (reg:CCU CC_REGNUM)
3557 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3558 (match_operand:BLK 1 "memory_operand" "")))
3559 (use (match_operand 2 "general_operand" ""))
3560 (use (match_dup 3))])]
3563 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3564 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3565 rtx reg0 = gen_reg_rtx (dreg_mode);
3566 rtx reg1 = gen_reg_rtx (dreg_mode);
3567 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3568 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3569 rtx len0 = gen_lowpart (Pmode, reg0);
3570 rtx len1 = gen_lowpart (Pmode, reg1);
3572 emit_clobber (reg0);
3573 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3574 emit_move_insn (len0, operands[2]);
3576 emit_clobber (reg1);
3577 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3578 emit_move_insn (len1, operands[2]);
3580 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3581 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3586 (define_insn "*cmpmem_long"
3587 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3588 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3589 (set (reg:CCU CC_REGNUM)
3590 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3591 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3593 (use (match_dup 3))]
3594 "TARGET_64BIT || !TARGET_ZARCH"
3595 "clcle\t%0,%1,0\;jo\t.-4"
3596 [(set_attr "length" "8")
3597 (set_attr "type" "vs")])
3599 (define_insn "*cmpmem_long_31z"
3600 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3601 (clobber (match_operand:TI 1 "register_operand" "=d"))
3602 (set (reg:CCU CC_REGNUM)
3603 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3604 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3606 (use (match_dup 3))]
3607 "!TARGET_64BIT && TARGET_ZARCH"
3608 "clcle\t%0,%1,0\;jo\t.-4"
3609 [(set_attr "op_type" "NN")
3610 (set_attr "type" "vs")
3611 (set_attr "length" "8")])
3613 ; Convert CCUmode condition code to integer.
3614 ; Result is zero if EQ, positive if LTU, negative if GTU.
3616 (define_insn_and_split "cmpint"
3617 [(set (match_operand:SI 0 "register_operand" "=d")
3618 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3619 UNSPEC_STRCMPCC_TO_INT))
3620 (clobber (reg:CC CC_REGNUM))]
3624 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3626 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3627 (clobber (reg:CC CC_REGNUM))])])
3629 (define_insn_and_split "*cmpint_cc"
3630 [(set (reg CC_REGNUM)
3631 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3632 UNSPEC_STRCMPCC_TO_INT)
3634 (set (match_operand:SI 0 "register_operand" "=d")
3635 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3636 "s390_match_ccmode (insn, CCSmode)"
3638 "&& reload_completed"
3639 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3641 [(set (match_dup 2) (match_dup 3))
3642 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3644 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3645 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3646 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3649 (define_insn_and_split "*cmpint_sign"
3650 [(set (match_operand:DI 0 "register_operand" "=d")
3651 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3652 UNSPEC_STRCMPCC_TO_INT)))
3653 (clobber (reg:CC CC_REGNUM))]
3656 "&& reload_completed"
3657 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3659 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3660 (clobber (reg:CC CC_REGNUM))])])
3662 (define_insn_and_split "*cmpint_sign_cc"
3663 [(set (reg CC_REGNUM)
3664 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3665 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3666 UNSPEC_STRCMPCC_TO_INT) 0)
3667 (const_int 32)) (const_int 32))
3669 (set (match_operand:DI 0 "register_operand" "=d")
3670 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3671 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3673 "&& reload_completed"
3674 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3676 [(set (match_dup 2) (match_dup 3))
3677 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3679 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3680 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3681 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3686 ;;- Conversion instructions.
3689 (define_insn "*sethighpartsi"
3690 [(set (match_operand:SI 0 "register_operand" "=d,d")
3691 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3692 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3693 (clobber (reg:CC CC_REGNUM))]
3698 [(set_attr "op_type" "RS,RSY")
3699 (set_attr "cpu_facility" "*,longdisp")
3700 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3702 (define_insn "*sethighpartdi_64"
3703 [(set (match_operand:DI 0 "register_operand" "=d")
3704 (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
3705 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3706 (clobber (reg:CC CC_REGNUM))]
3709 [(set_attr "op_type" "RSY")
3710 (set_attr "z10prop" "z10_super")])
3712 (define_insn "*sethighpartdi_31"
3713 [(set (match_operand:DI 0 "register_operand" "=d,d")
3714 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3715 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3716 (clobber (reg:CC CC_REGNUM))]
3721 [(set_attr "op_type" "RS,RSY")
3722 (set_attr "cpu_facility" "*,longdisp")
3723 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3726 ; extv instruction patterns
3729 ; FIXME: This expander needs to be converted from DI to GPR as well
3730 ; after resolving some issues with it.
3732 (define_expand "extzv"
3734 [(set (match_operand:DI 0 "register_operand" "=d")
3736 (match_operand:DI 1 "register_operand" "d")
3737 (match_operand 2 "const_int_operand" "") ; size
3738 (match_operand 3 "const_int_operand" ""))) ; start
3739 (clobber (reg:CC CC_REGNUM))])]
3742 /* Starting with zEC12 there is risbgn not clobbering CC. */
3745 emit_move_insn (operands[0],
3746 gen_rtx_ZERO_EXTRACT (DImode,
3754 (define_insn "*extzv<mode><clobbercc_or_nocc>"
3755 [(set (match_operand:GPR 0 "register_operand" "=d")
3757 (match_operand:GPR 1 "register_operand" "d")
3758 (match_operand 2 "const_int_operand" "") ; size
3759 (match_operand 3 "const_int_operand" ""))) ; start
3761 "<z10_or_zEC12_cond>"
3762 "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
3763 [(set_attr "op_type" "RIE")
3764 (set_attr "z10prop" "z10_super_E1")])
3766 ; 64 bit: (a & -16) | ((b >> 8) & 15)
3767 (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt"
3768 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3769 (match_operand 1 "const_int_operand" "") ; size
3770 (match_operand 2 "const_int_operand" "")) ; start
3771 (lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
3772 (match_operand:DI 4 "nonzero_shift_count_operand" "")))]
3773 "<z10_or_zEC12_cond>
3774 && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
3775 "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
3776 [(set_attr "op_type" "RIE")
3777 (set_attr "z10prop" "z10_super_E1")])
3779 ; 32 bit: (a & -16) | ((b >> 8) & 15)
3780 (define_insn "*<risbg_n>_ior_and_sr_ze"
3781 [(set (match_operand:SI 0 "register_operand" "=d")
3783 (match_operand:SI 1 "register_operand" "0")
3784 (match_operand:SI 2 "const_int_operand" ""))
3787 (match_operand:DI 3 "register_operand" "d")
3788 (match_operand 4 "const_int_operand" "") ; size
3789 (match_operand 5 "const_int_operand" "")) ; start
3791 "<z10_or_zEC12_cond>
3792 && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
3793 "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
3794 [(set_attr "op_type" "RIE")
3795 (set_attr "z10prop" "z10_super_E1")])
3797 ; ((int)foo >> 10) & 1;
3798 (define_insn "*extract1bitdi<clobbercc_or_nocc>"
3799 [(set (match_operand:DI 0 "register_operand" "=d")
3800 (ne:DI (zero_extract:DI
3801 (match_operand:DI 1 "register_operand" "d")
3802 (const_int 1) ; size
3803 (match_operand 2 "const_int_operand" "")) ; start
3805 "<z10_or_zEC12_cond>"
3806 "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
3807 [(set_attr "op_type" "RIE")
3808 (set_attr "z10prop" "z10_super_E1")])
3810 (define_insn "*<risbg_n>_and_subregdi_rotr"
3811 [(set (match_operand:DI 0 "register_operand" "=d")
3813 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3814 (match_operand:SINT 2 "const_int_operand" "")) 0)
3815 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3816 "<z10_or_zEC12_cond>
3817 && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
3818 "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
3819 [(set_attr "op_type" "RIE")
3820 (set_attr "z10prop" "z10_super_E1")])
3822 (define_insn "*<risbg_n>_and_subregdi_rotl"
3823 [(set (match_operand:DI 0 "register_operand" "=d")
3825 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3826 (match_operand:SINT 2 "const_int_operand" "")) 0)
3827 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3828 "<z10_or_zEC12_cond>
3829 && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
3830 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3831 [(set_attr "op_type" "RIE")
3832 (set_attr "z10prop" "z10_super_E1")])
3834 (define_insn "*<risbg_n>_di_and_rot"
3835 [(set (match_operand:DI 0 "register_operand" "=d")
3836 (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d")
3837 (match_operand:DI 2 "const_int_operand" ""))
3838 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3839 "<z10_or_zEC12_cond>"
3840 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3841 [(set_attr "op_type" "RIE")
3842 (set_attr "z10prop" "z10_super_E1")])
3844 (define_insn_and_split "*pre_z10_extzv<mode>"
3845 [(set (match_operand:GPR 0 "register_operand" "=d")
3846 (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
3847 (match_operand 2 "nonzero_shift_count_operand" "")
3849 (clobber (reg:CC CC_REGNUM))]
3852 "&& reload_completed"
3854 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3855 (clobber (reg:CC CC_REGNUM))])
3856 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3858 int bitsize = INTVAL (operands[2]);
3859 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3860 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3862 operands[1] = adjust_address (operands[1], BLKmode, 0);
3863 set_mem_size (operands[1], size);
3864 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3865 operands[3] = GEN_INT (mask);
3868 (define_insn_and_split "*pre_z10_extv<mode>"
3869 [(set (match_operand:GPR 0 "register_operand" "=d")
3870 (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
3871 (match_operand 2 "nonzero_shift_count_operand" "")
3873 (clobber (reg:CC CC_REGNUM))]
3876 "&& reload_completed"
3878 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3879 (clobber (reg:CC CC_REGNUM))])
3881 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3882 (clobber (reg:CC CC_REGNUM))])]
3884 int bitsize = INTVAL (operands[2]);
3885 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3886 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3888 operands[1] = adjust_address (operands[1], BLKmode, 0);
3889 set_mem_size (operands[1], size);
3890 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3891 operands[3] = GEN_INT (mask);
3895 ; insv instruction patterns
3898 (define_expand "insv"
3899 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3900 (match_operand 1 "const_int_operand" "")
3901 (match_operand 2 "const_int_operand" ""))
3902 (match_operand 3 "general_operand" ""))]
3905 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3911 ; The normal RTL expansion will never generate a zero_extract where
3912 ; the location operand isn't word mode. However, we do this in the
3913 ; back-end when generating atomic operations. See s390_two_part_insv.
3914 (define_insn "*insv<mode><clobbercc_or_nocc>"
3915 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3916 (match_operand 1 "const_int_operand" "I") ; size
3917 (match_operand 2 "const_int_operand" "I")) ; pos
3918 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3919 "<z10_or_zEC12_cond>
3920 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3921 "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
3922 [(set_attr "op_type" "RIE")
3923 (set_attr "z10prop" "z10_super_E1")])
3925 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3926 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3927 (define_insn "*insv<mode><clobbercc_or_nocc>_noshift"
3928 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d")
3929 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0")
3930 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3931 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d")
3932 (match_operand:GPR 4 "const_int_operand" ""))))]
3933 "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3935 <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0
3936 <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0"
3937 [(set_attr "op_type" "RIE")
3938 (set_attr "z10prop" "z10_super_E1")])
3940 (define_insn "*insv_z10_noshift_cc"
3941 [(set (reg CC_REGNUM)
3944 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
3945 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3946 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
3947 (match_operand:DI 4 "const_int_operand" "")))
3949 (set (match_operand:DI 0 "nonimmediate_operand" "=d,d")
3950 (ior:DI (and:DI (match_dup 1) (match_dup 2))
3951 (and:DI (match_dup 3) (match_dup 4))))]
3952 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
3953 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3955 risbg\t%0,%1,%s2,%e2,0
3956 risbg\t%0,%3,%s4,%e4,0"
3957 [(set_attr "op_type" "RIE")
3958 (set_attr "z10prop" "z10_super_E1")])
3960 (define_insn "*insv_z10_noshift_cconly"
3965 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
3966 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3967 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
3968 (match_operand:DI 4 "const_int_operand" "")))
3970 (clobber (match_scratch:DI 0 "=d,d"))]
3971 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
3972 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3974 risbg\t%0,%1,%s2,%e2,0
3975 risbg\t%0,%3,%s4,%e4,0"
3976 [(set_attr "op_type" "RIE")
3977 (set_attr "z10prop" "z10_super_E1")])
3979 ; Implement appending Y on the left of S bits of X
3980 ; x = (y << s) | (x & ((1 << s) - 1))
3981 (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft"
3982 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3983 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3984 (match_operand:GPR 2 "immediate_operand" ""))
3985 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3986 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3987 "<z10_or_zEC12_cond>
3988 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3989 "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
3990 [(set_attr "op_type" "RIE")
3991 (set_attr "z10prop" "z10_super_E1")])
3993 ; a = ((i32)a & -16777216) | (((ui32)b) >> 8)
3994 (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt"
3995 [(set (match_operand:GPR 0 "register_operand" "=d")
3997 (match_operand:GPR 1 "register_operand" "0")
3998 (match_operand:GPR 2 "const_int_operand" ""))
4000 (match_operand:GPR 3 "register_operand" "d")
4001 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4002 "<z10_or_zEC12_cond> && UINTVAL (operands[2])
4003 == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
4004 "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
4005 [(set_attr "op_type" "RIE")
4006 (set_attr "z10prop" "z10_super_E1")])
4008 ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536);
4009 (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt"
4010 [(set (match_operand:SI 0 "register_operand" "=d")
4012 (match_operand:SI 1 "register_operand" "0")
4013 (match_operand:SI 2 "const_int_operand" ""))
4016 (match_operand:DI 3 "register_operand" "d")
4017 (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
4018 "<z10_or_zEC12_cond>
4019 && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
4020 "<risbg_n>\t%0,%3,%4,63,64-%4"
4021 [(set_attr "op_type" "RIE")
4022 (set_attr "z10prop" "z10_super_E1")])
4024 ; (ui32)(((ui64)x) >> 12) & -4
4025 (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"
4026 [(set (match_operand:SI 0 "register_operand" "=d")
4028 (subreg:SI (lshiftrt:DI
4029 (match_operand:DI 1 "register_operand" "d")
4030 (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4)
4031 (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))]
4032 "<z10_or_zEC12_cond>"
4033 "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2"
4034 [(set_attr "op_type" "RIE")
4035 (set_attr "z10prop" "z10_super_E1")])
4037 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
4038 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
4039 ; -> z = y >> d; z = risbg;
4042 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4043 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4044 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4045 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4046 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4047 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4049 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4051 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4052 (ashift:GPR (match_dup 3) (match_dup 4))))]
4054 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4055 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4057 if (!can_create_pseudo_p ())
4059 operands[6] = gen_reg_rtx (<MODE>mode);
4062 operands[6] = operands[0];
4067 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4068 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4069 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4070 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4071 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
4072 (clobber (reg:CC CC_REGNUM))])]
4073 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4075 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4078 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4079 (ashift:GPR (match_dup 3) (match_dup 4))))
4080 (clobber (reg:CC CC_REGNUM))])]
4082 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4083 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4085 if (!can_create_pseudo_p ())
4087 operands[6] = gen_reg_rtx (<MODE>mode);
4090 operands[6] = operands[0];
4093 (define_insn "*r<noxa>sbg_<mode>_noshift"
4094 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4096 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
4097 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4098 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4099 (clobber (reg:CC CC_REGNUM))]
4101 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
4102 [(set_attr "op_type" "RIE")])
4104 (define_insn "*r<noxa>sbg_di_rotl"
4105 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4109 (match_operand:DI 1 "nonimmediate_operand" "d")
4110 (match_operand:DI 3 "const_int_operand" ""))
4111 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4112 (match_operand:DI 4 "nonimmediate_operand" "0")))
4113 (clobber (reg:CC CC_REGNUM))]
4115 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
4116 [(set_attr "op_type" "RIE")])
4118 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
4119 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4123 (match_operand:GPR 1 "nonimmediate_operand" "d")
4124 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4125 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4126 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4127 (clobber (reg:CC CC_REGNUM))]
4129 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
4130 INTVAL (operands[2]))"
4131 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
4132 [(set_attr "op_type" "RIE")])
4134 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
4135 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4139 (match_operand:GPR 1 "nonimmediate_operand" "d")
4140 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4141 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4142 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4143 (clobber (reg:CC CC_REGNUM))]
4145 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
4146 INTVAL (operands[2]))"
4147 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
4148 [(set_attr "op_type" "RIE")])
4150 ;; unsigned {int,long} a, b
4151 ;; a = a | (b << const_int)
4152 ;; a = a ^ (b << const_int)
4153 (define_insn "*r<noxa>sbg_<mode>_sll"
4154 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4157 (match_operand:GPR 1 "nonimmediate_operand" "d")
4158 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4159 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4160 (clobber (reg:CC CC_REGNUM))]
4162 "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
4163 [(set_attr "op_type" "RIE")])
4165 ;; unsigned {int,long} a, b
4166 ;; a = a | (b >> const_int)
4167 ;; a = a ^ (b >> const_int)
4168 (define_insn "*r<noxa>sbg_<mode>_srl"
4169 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4172 (match_operand:GPR 1 "nonimmediate_operand" "d")
4173 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4174 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4175 (clobber (reg:CC CC_REGNUM))]
4177 "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
4178 [(set_attr "op_type" "RIE")])
4180 ;; These two are generated by combine for s.bf &= val.
4181 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
4182 ;; shifts and ands, which results in some truly awful patterns
4183 ;; including subregs of operations. Rather unnecessisarily, IMO.
4186 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4187 ;; (const_int 24 [0x18])
4188 ;; (const_int 0 [0]))
4189 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
4190 ;; (const_int 40 [0x28])) 4)
4191 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
4193 ;; we should instead generate
4195 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4196 ;; (const_int 24 [0x18])
4197 ;; (const_int 0 [0]))
4198 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
4199 ;; (const_int 40 [0x28]))
4200 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
4202 ;; by noticing that we can push down the outer paradoxical subreg
4203 ;; into the operation.
4205 (define_insn "*insv_rnsbg_noshift"
4206 [(set (zero_extract:DI
4207 (match_operand:DI 0 "nonimmediate_operand" "+d")
4208 (match_operand 1 "const_int_operand" "")
4209 (match_operand 2 "const_int_operand" ""))
4212 (match_operand:DI 3 "nonimmediate_operand" "d")))
4213 (clobber (reg:CC CC_REGNUM))]
4215 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4216 "rnsbg\t%0,%3,%2,63,0"
4217 [(set_attr "op_type" "RIE")])
4219 (define_insn "*insv_rnsbg_srl"
4220 [(set (zero_extract:DI
4221 (match_operand:DI 0 "nonimmediate_operand" "+d")
4222 (match_operand 1 "const_int_operand" "")
4223 (match_operand 2 "const_int_operand" ""))
4227 (match_operand 3 "const_int_operand" ""))
4228 (match_operand:DI 4 "nonimmediate_operand" "d")))
4229 (clobber (reg:CC CC_REGNUM))]
4231 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4232 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4233 [(set_attr "op_type" "RIE")])
4235 (define_insn "*insv<mode>_mem_reg"
4236 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4237 (match_operand 1 "const_int_operand" "n,n")
4239 (match_operand:W 2 "register_operand" "d,d"))]
4240 "INTVAL (operands[1]) > 0
4241 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4242 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4244 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4246 operands[1] = GEN_INT ((1ul << size) - 1);
4247 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4248 : "stcmy\t%2,%1,%S0";
4250 [(set_attr "op_type" "RS,RSY")
4251 (set_attr "cpu_facility" "*,longdisp")
4252 (set_attr "z10prop" "z10_super,z10_super")])
4254 (define_insn "*insvdi_mem_reghigh"
4255 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
4256 (match_operand 1 "const_int_operand" "n")
4258 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4261 && INTVAL (operands[1]) > 0
4262 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4263 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4265 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4267 operands[1] = GEN_INT ((1ul << size) - 1);
4268 return "stcmh\t%2,%1,%S0";
4270 [(set_attr "op_type" "RSY")
4271 (set_attr "z10prop" "z10_super")])
4273 (define_insn "*insvdi_reg_imm"
4274 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4276 (match_operand 1 "const_int_operand" "n"))
4277 (match_operand:DI 2 "const_int_operand" "n"))]
4279 && INTVAL (operands[1]) >= 0
4280 && INTVAL (operands[1]) < BITS_PER_WORD
4281 && INTVAL (operands[1]) % 16 == 0"
4283 switch (BITS_PER_WORD - INTVAL (operands[1]))
4285 case 64: return "iihh\t%0,%x2"; break;
4286 case 48: return "iihl\t%0,%x2"; break;
4287 case 32: return "iilh\t%0,%x2"; break;
4288 case 16: return "iill\t%0,%x2"; break;
4289 default: gcc_unreachable();
4292 [(set_attr "op_type" "RI")
4293 (set_attr "z10prop" "z10_super_E1")])
4295 ; Update the left-most 32 bit of a DI.
4296 (define_insn "*insv_h_di_reg_extimm"
4297 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4300 (match_operand:DI 1 "const_int_operand" "n"))]
4303 [(set_attr "op_type" "RIL")
4304 (set_attr "z10prop" "z10_fwd_E1")])
4306 ; Update the right-most 32 bit of a DI.
4307 (define_insn "*insv_l_di_reg_extimm"
4308 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4311 (match_operand:DI 1 "const_int_operand" "n"))]
4314 [(set_attr "op_type" "RIL")
4315 (set_attr "z10prop" "z10_fwd_A1")])
4318 ; extendsidi2 instruction pattern(s).
4321 (define_expand "extendsidi2"
4322 [(set (match_operand:DI 0 "register_operand" "")
4323 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4328 emit_clobber (operands[0]);
4329 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4330 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4331 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4336 (define_insn "*extendsidi2"
4337 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4338 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4344 [(set_attr "op_type" "RRE,RXY,RIL")
4345 (set_attr "type" "*,*,larl")
4346 (set_attr "cpu_facility" "*,*,z10")
4347 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4350 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4353 (define_expand "extend<HQI:mode><DSI:mode>2"
4354 [(set (match_operand:DSI 0 "register_operand" "")
4355 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4358 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4360 rtx tmp = gen_reg_rtx (SImode);
4361 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4362 emit_insn (gen_extendsidi2 (operands[0], tmp));
4365 else if (!TARGET_EXTIMM)
4367 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4369 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4370 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4371 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4377 ; extendhidi2 instruction pattern(s).
4380 (define_insn "*extendhidi2_extimm"
4381 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4382 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
4383 "TARGET_ZARCH && TARGET_EXTIMM"
4388 [(set_attr "op_type" "RRE,RXY,RIL")
4389 (set_attr "type" "*,*,larl")
4390 (set_attr "cpu_facility" "extimm,extimm,z10")
4391 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4393 (define_insn "*extendhidi2"
4394 [(set (match_operand:DI 0 "register_operand" "=d")
4395 (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
4398 [(set_attr "op_type" "RXY")
4399 (set_attr "z10prop" "z10_super_E1")])
4402 ; extendhisi2 instruction pattern(s).
4405 (define_insn "*extendhisi2_extimm"
4406 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4407 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4414 [(set_attr "op_type" "RRE,RX,RXY,RIL")
4415 (set_attr "type" "*,*,*,larl")
4416 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4417 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4419 (define_insn "*extendhisi2"
4420 [(set (match_operand:SI 0 "register_operand" "=d,d")
4421 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4426 [(set_attr "op_type" "RX,RXY")
4427 (set_attr "cpu_facility" "*,longdisp")
4428 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4431 ; extendqi(si|di)2 instruction pattern(s).
4434 ; lbr, lgbr, lb, lgb
4435 (define_insn "*extendqi<mode>2_extimm"
4436 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4437 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
4442 [(set_attr "op_type" "RRE,RXY")
4443 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4446 (define_insn "*extendqi<mode>2"
4447 [(set (match_operand:GPR 0 "register_operand" "=d")
4448 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
4449 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4451 [(set_attr "op_type" "RXY")
4452 (set_attr "z10prop" "z10_super_E1")])
4454 (define_insn_and_split "*extendqi<mode>2_short_displ"
4455 [(set (match_operand:GPR 0 "register_operand" "=d")
4456 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4457 (clobber (reg:CC CC_REGNUM))]
4458 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4460 "&& reload_completed"
4462 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4463 (clobber (reg:CC CC_REGNUM))])
4465 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4466 (clobber (reg:CC CC_REGNUM))])]
4468 operands[1] = adjust_address (operands[1], BLKmode, 0);
4469 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4470 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4474 ; zero_extendsidi2 instruction pattern(s).
4477 (define_expand "zero_extendsidi2"
4478 [(set (match_operand:DI 0 "register_operand" "")
4479 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4484 emit_clobber (operands[0]);
4485 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4486 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4491 (define_insn "*zero_extendsidi2"
4492 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4493 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4499 [(set_attr "op_type" "RRE,RXY,RIL")
4500 (set_attr "type" "*,*,larl")
4501 (set_attr "cpu_facility" "*,*,z10")
4502 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4505 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4508 (define_insn "*llgt_sidi"
4509 [(set (match_operand:DI 0 "register_operand" "=d")
4510 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4511 (const_int 2147483647)))]
4514 [(set_attr "op_type" "RXE")
4515 (set_attr "z10prop" "z10_super_E1")])
4517 (define_insn_and_split "*llgt_sidi_split"
4518 [(set (match_operand:DI 0 "register_operand" "=d")
4519 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4520 (const_int 2147483647)))
4521 (clobber (reg:CC CC_REGNUM))]
4524 "&& reload_completed"
4526 (and:DI (subreg:DI (match_dup 1) 0)
4527 (const_int 2147483647)))]
4530 (define_insn "*llgt_sisi"
4531 [(set (match_operand:SI 0 "register_operand" "=d,d")
4532 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
4533 (const_int 2147483647)))]
4538 [(set_attr "op_type" "RRE,RXE")
4539 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4541 (define_insn "*llgt_didi"
4542 [(set (match_operand:DI 0 "register_operand" "=d,d")
4543 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4544 (const_int 2147483647)))]
4549 [(set_attr "op_type" "RRE,RXE")
4550 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4553 [(set (match_operand:DSI 0 "register_operand" "")
4554 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4555 (const_int 2147483647)))
4556 (clobber (reg:CC CC_REGNUM))]
4557 "TARGET_ZARCH && reload_completed"
4559 (and:DSI (match_dup 1)
4560 (const_int 2147483647)))]
4564 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4567 (define_expand "zero_extend<mode>di2"
4568 [(set (match_operand:DI 0 "register_operand" "")
4569 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4574 rtx tmp = gen_reg_rtx (SImode);
4575 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4576 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4579 else if (!TARGET_EXTIMM)
4581 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4582 operands[1] = gen_lowpart (DImode, operands[1]);
4583 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4584 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4589 (define_expand "zero_extend<mode>si2"
4590 [(set (match_operand:SI 0 "register_operand" "")
4591 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4596 operands[1] = gen_lowpart (SImode, operands[1]);
4597 emit_insn (gen_andsi3 (operands[0], operands[1],
4598 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4604 (define_insn "*zero_extendhi<mode>2_z10"
4605 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4606 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
4612 [(set_attr "op_type" "RXY,RRE,RIL")
4613 (set_attr "type" "*,*,larl")
4614 (set_attr "cpu_facility" "*,*,z10")
4615 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4617 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4618 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4619 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4620 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
4625 [(set_attr "op_type" "RRE,RXY")
4626 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4629 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4630 [(set (match_operand:GPR 0 "register_operand" "=d")
4631 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
4632 "TARGET_ZARCH && !TARGET_EXTIMM"
4634 [(set_attr "op_type" "RXY")
4635 (set_attr "z10prop" "z10_fwd_A3")])
4637 (define_insn_and_split "*zero_extendhisi2_31"
4638 [(set (match_operand:SI 0 "register_operand" "=&d")
4639 (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
4640 (clobber (reg:CC CC_REGNUM))]
4643 "&& reload_completed"
4644 [(set (match_dup 0) (const_int 0))
4646 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4647 (clobber (reg:CC CC_REGNUM))])]
4648 "operands[2] = gen_lowpart (HImode, operands[0]);")
4650 (define_insn_and_split "*zero_extendqisi2_31"
4651 [(set (match_operand:SI 0 "register_operand" "=&d")
4652 (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
4655 "&& reload_completed"
4656 [(set (match_dup 0) (const_int 0))
4657 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4658 "operands[2] = gen_lowpart (QImode, operands[0]);")
4661 ; zero_extendqihi2 instruction pattern(s).
4664 (define_expand "zero_extendqihi2"
4665 [(set (match_operand:HI 0 "register_operand" "")
4666 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4667 "TARGET_ZARCH && !TARGET_EXTIMM"
4669 operands[1] = gen_lowpart (HImode, operands[1]);
4670 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4674 (define_insn "*zero_extendqihi2_64"
4675 [(set (match_operand:HI 0 "register_operand" "=d")
4676 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4677 "TARGET_ZARCH && !TARGET_EXTIMM"
4679 [(set_attr "op_type" "RXY")
4680 (set_attr "z10prop" "z10_fwd_A3")])
4682 (define_insn_and_split "*zero_extendqihi2_31"
4683 [(set (match_operand:HI 0 "register_operand" "=&d")
4684 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4687 "&& reload_completed"
4688 [(set (match_dup 0) (const_int 0))
4689 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4690 "operands[2] = gen_lowpart (QImode, operands[0]);")
4693 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4696 (define_expand "fixuns_truncdddi2"
4698 [(set (match_operand:DI 0 "register_operand" "")
4699 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4700 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4701 (clobber (reg:CC CC_REGNUM))])]
4707 rtx_code_label *label1 = gen_label_rtx ();
4708 rtx_code_label *label2 = gen_label_rtx ();
4709 rtx temp = gen_reg_rtx (TDmode);
4710 REAL_VALUE_TYPE cmp, sub;
4712 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4713 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4715 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4716 solution is doing the check and the subtraction in TD mode and using a
4717 TD -> DI convert afterwards. */
4718 emit_insn (gen_extendddtd2 (temp, operands[1]));
4719 temp = force_reg (TDmode, temp);
4720 emit_cmp_and_jump_insns (temp,
4721 const_double_from_real_value (cmp, TDmode),
4722 LT, NULL_RTX, VOIDmode, 0, label1);
4723 emit_insn (gen_subtd3 (temp, temp,
4724 const_double_from_real_value (sub, TDmode)));
4725 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4726 GEN_INT (DFP_RND_TOWARD_MINF)));
4729 emit_label (label1);
4730 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
4731 GEN_INT (DFP_RND_TOWARD_0)));
4732 emit_label (label2);
4737 (define_expand "fixuns_trunctddi2"
4739 [(set (match_operand:DI 0 "register_operand" "")
4740 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4741 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4742 (clobber (reg:CC CC_REGNUM))])]
4748 rtx_code_label *label1 = gen_label_rtx ();
4749 rtx_code_label *label2 = gen_label_rtx ();
4750 rtx temp = gen_reg_rtx (TDmode);
4751 REAL_VALUE_TYPE cmp, sub;
4753 operands[1] = force_reg (TDmode, operands[1]);
4754 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4755 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4757 emit_cmp_and_jump_insns (operands[1],
4758 const_double_from_real_value (cmp, TDmode),
4759 LT, NULL_RTX, VOIDmode, 0, label1);
4760 emit_insn (gen_subtd3 (temp, operands[1],
4761 const_double_from_real_value (sub, TDmode)));
4762 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4763 GEN_INT (DFP_RND_TOWARD_MINF)));
4766 emit_label (label1);
4767 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
4768 GEN_INT (DFP_RND_TOWARD_0)));
4769 emit_label (label2);
4775 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4776 ; instruction pattern(s).
4779 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4781 [(set (match_operand:GPR 0 "register_operand" "")
4782 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4783 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4784 (clobber (reg:CC CC_REGNUM))])]
4789 rtx_code_label *label1 = gen_label_rtx ();
4790 rtx_code_label *label2 = gen_label_rtx ();
4791 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4792 REAL_VALUE_TYPE cmp, sub;
4794 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4795 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4796 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4798 emit_cmp_and_jump_insns (operands[1],
4799 const_double_from_real_value (cmp, <BFP:MODE>mode),
4800 LT, NULL_RTX, VOIDmode, 0, label1);
4801 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4802 const_double_from_real_value (sub, <BFP:MODE>mode)));
4803 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4804 GEN_INT (BFP_RND_TOWARD_MINF)));
4807 emit_label (label1);
4808 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4809 operands[1], GEN_INT (BFP_RND_TOWARD_0)));
4810 emit_label (label2);
4815 ; fixuns_trunc(td|dd)si2 expander
4816 (define_expand "fixuns_trunc<mode>si2"
4818 [(set (match_operand:SI 0 "register_operand" "")
4819 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4820 (unspec:SI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4821 (clobber (reg:CC CC_REGNUM))])]
4822 "TARGET_Z196 && TARGET_HARD_DFP"
4825 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4827 (define_insn "*fixuns_truncdfdi2_z13"
4828 [(set (match_operand:DI 0 "register_operand" "=d,v")
4829 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4830 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4831 (clobber (reg:CC CC_REGNUM))]
4832 "TARGET_VX && TARGET_HARD_FLOAT"
4835 wclgdb\t%v0,%v1,0,%h2"
4836 [(set_attr "op_type" "RRF,VRR")
4837 (set_attr "type" "ftoi")])
4839 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4840 ; clfdtr, clfxtr, clgdtr, clgxtr
4841 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4842 [(set (match_operand:GPR 0 "register_operand" "=d")
4843 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4844 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4845 (clobber (reg:CC CC_REGNUM))]
4846 "TARGET_Z196 && TARGET_HARD_FLOAT
4847 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4848 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4849 [(set_attr "op_type" "RRF")
4850 (set_attr "type" "ftoi")])
4852 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4853 [(set (match_operand:GPR 0 "register_operand" "")
4854 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4857 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4858 GEN_INT (BFP_RND_TOWARD_0)));
4862 (define_insn "*fix_truncdfdi2_bfp_z13"
4863 [(set (match_operand:DI 0 "register_operand" "=d,v")
4864 (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4865 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4866 (clobber (reg:CC CC_REGNUM))]
4867 "TARGET_VX && TARGET_HARD_FLOAT"
4870 wcgdb\t%v0,%v1,0,%h2"
4871 [(set_attr "op_type" "RRE,VRR")
4872 (set_attr "type" "ftoi")])
4874 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4875 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4876 [(set (match_operand:GPR 0 "register_operand" "=d")
4877 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4878 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4879 (clobber (reg:CC CC_REGNUM))]
4881 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4882 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4883 [(set_attr "op_type" "RRE")
4884 (set_attr "type" "ftoi")])
4886 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4888 [(set (match_operand:GPR 0 "register_operand" "=d")
4889 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4890 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4891 (clobber (reg:CC CC_REGNUM))])]
4892 "TARGET_HARD_FLOAT")
4894 ; fix_trunc(td|dd)di2 instruction pattern(s).
4897 (define_expand "fix_trunc<mode>di2"
4898 [(set (match_operand:DI 0 "register_operand" "")
4899 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4900 "TARGET_ZARCH && TARGET_HARD_DFP"
4902 operands[1] = force_reg (<MODE>mode, operands[1]);
4903 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4904 GEN_INT (DFP_RND_TOWARD_0)));
4909 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4910 [(set (match_operand:DI 0 "register_operand" "=d")
4911 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4912 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4913 (clobber (reg:CC CC_REGNUM))]
4914 "TARGET_ZARCH && TARGET_HARD_DFP"
4915 "cg<DFP:xde>tr\t%0,%h2,%1"
4916 [(set_attr "op_type" "RRF")
4917 (set_attr "type" "ftoidfp")])
4921 ; fix_trunctf(si|di)2 instruction pattern(s).
4924 (define_expand "fix_trunctf<mode>2"
4925 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4926 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4927 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4928 (clobber (reg:CC CC_REGNUM))])]
4934 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4937 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4938 (define_insn "floatdi<mode>2"
4939 [(set (match_operand:FP 0 "register_operand" "=f,v")
4940 (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
4941 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4945 [(set_attr "op_type" "RRE,VRR")
4946 (set_attr "type" "itof<mode>" )
4947 (set_attr "cpu_facility" "*,vec")
4948 (set_attr "enabled" "*,<DFDI>")])
4950 ; cxfbr, cdfbr, cefbr
4951 (define_insn "floatsi<mode>2"
4952 [(set (match_operand:BFP 0 "register_operand" "=f")
4953 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4956 [(set_attr "op_type" "RRE")
4957 (set_attr "type" "itof<mode>" )])
4960 (define_insn "floatsi<mode>2"
4961 [(set (match_operand:DFP 0 "register_operand" "=f")
4962 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4963 "TARGET_Z196 && TARGET_HARD_FLOAT"
4964 "c<xde>ftr\t%0,0,%1,0"
4965 [(set_attr "op_type" "RRE")
4966 (set_attr "type" "itof<mode>" )])
4969 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4972 (define_insn "*floatunsdidf2_z13"
4973 [(set (match_operand:DF 0 "register_operand" "=f,v")
4974 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
4975 "TARGET_VX && TARGET_HARD_FLOAT"
4978 wcdlgb\t%v0,%v1,0,0"
4979 [(set_attr "op_type" "RRE,VRR")
4980 (set_attr "type" "itofdf")])
4982 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4983 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4984 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4985 [(set (match_operand:FP 0 "register_operand" "=f")
4986 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4987 "TARGET_Z196 && TARGET_HARD_FLOAT
4988 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4989 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4990 [(set_attr "op_type" "RRE")
4991 (set_attr "type" "itof<FP:mode>")])
4993 (define_expand "floatuns<GPR:mode><FP:mode>2"
4994 [(set (match_operand:FP 0 "register_operand" "")
4995 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4996 "TARGET_Z196 && TARGET_HARD_FLOAT")
4999 ; truncdfsf2 instruction pattern(s).
5002 (define_insn "truncdfsf2"
5003 [(set (match_operand:SF 0 "register_operand" "=f,v")
5004 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
5008 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
5009 ; According to BFP rounding mode
5010 [(set_attr "op_type" "RRE,VRR")
5011 (set_attr "type" "ftruncdf")
5012 (set_attr "cpu_facility" "*,vec")])
5015 ; trunctf(df|sf)2 instruction pattern(s).
5019 (define_insn "trunctf<mode>2"
5020 [(set (match_operand:DSF 0 "register_operand" "=f")
5021 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
5022 (clobber (match_scratch:TF 2 "=f"))]
5024 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
5025 [(set_attr "length" "6")
5026 (set_attr "type" "ftrunctf")])
5029 ; trunctddd2 and truncddsd2 instruction pattern(s).
5033 (define_expand "trunctddd2"
5035 [(set (match_operand:DD 0 "register_operand" "")
5036 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5037 (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
5038 (clobber (scratch:TD))])]
5041 (define_insn "*trunctddd2"
5042 [(set (match_operand:DD 0 "register_operand" "=f")
5043 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
5044 (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
5045 (clobber (match_scratch:TD 3 "=f"))]
5047 "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
5048 [(set_attr "length" "6")
5049 (set_attr "type" "ftruncdd")])
5051 (define_insn "truncddsd2"
5052 [(set (match_operand:SD 0 "register_operand" "=f")
5053 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
5056 [(set_attr "op_type" "RRF")
5057 (set_attr "type" "ftruncsd")])
5059 (define_expand "trunctdsd2"
5062 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5063 (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
5064 (clobber (match_scratch:TD 2 ""))])
5065 (set (match_operand:SD 0 "register_operand" "")
5066 (float_truncate:SD (match_dup 3)))]
5069 operands[3] = gen_reg_rtx (DDmode);
5073 ; extend(sf|df)(df|tf)2 instruction pattern(s).
5076 (define_insn "*extendsfdf2_z13"
5077 [(set (match_operand:DF 0 "register_operand" "=f,f,v")
5078 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
5079 "TARGET_VX && TARGET_HARD_FLOAT"
5084 [(set_attr "op_type" "RRE,RXE,VRR")
5085 (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
5087 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
5088 (define_insn "*extend<DSF:mode><BFP:mode>2"
5089 [(set (match_operand:BFP 0 "register_operand" "=f,f")
5090 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
5092 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
5093 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
5095 l<BFP:xde><DSF:xde>br\t%0,%1
5096 l<BFP:xde><DSF:xde>b\t%0,%1"
5097 [(set_attr "op_type" "RRE,RXE")
5098 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
5100 (define_expand "extend<DSF:mode><BFP:mode>2"
5101 [(set (match_operand:BFP 0 "register_operand" "")
5102 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
5104 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
5107 ; extendddtd2 and extendsddd2 instruction pattern(s).
5110 (define_insn "extendddtd2"
5111 [(set (match_operand:TD 0 "register_operand" "=f")
5112 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
5115 [(set_attr "op_type" "RRF")
5116 (set_attr "type" "fsimptf")])
5118 (define_insn "extendsddd2"
5119 [(set (match_operand:DD 0 "register_operand" "=f")
5120 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
5123 [(set_attr "op_type" "RRF")
5124 (set_attr "type" "fsimptf")])
5126 (define_expand "extendsdtd2"
5128 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
5129 (set (match_operand:TD 0 "register_operand" "")
5130 (float_extend:TD (match_dup 2)))]
5133 operands[2] = gen_reg_rtx (DDmode);
5136 ; Binary Floating Point - load fp integer
5138 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
5139 ; For all of them the inexact exceptions are suppressed.
5141 ; fiebra, fidbra, fixbra
5142 (define_insn "<FPINT:fpint_name><BFP:mode>2"
5143 [(set (match_operand:BFP 0 "register_operand" "=f")
5144 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5147 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
5148 [(set_attr "op_type" "RRF")
5149 (set_attr "type" "fsimp<BFP:mode>")])
5151 ; rint is supposed to raise an inexact exception so we can use the
5152 ; older instructions.
5154 ; fiebr, fidbr, fixbr
5155 (define_insn "rint<BFP:mode>2"
5156 [(set (match_operand:BFP 0 "register_operand" "=f")
5157 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5158 UNSPEC_FPINT_RINT))]
5160 "fi<BFP:xde>br\t%0,0,%1"
5161 [(set_attr "op_type" "RRF")
5162 (set_attr "type" "fsimp<BFP:mode>")])
5165 ; Decimal Floating Point - load fp integer
5168 (define_insn "<FPINT:fpint_name><DFP:mode>2"
5169 [(set (match_operand:DFP 0 "register_operand" "=f")
5170 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5173 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
5174 [(set_attr "op_type" "RRF")
5175 (set_attr "type" "fsimp<DFP:mode>")])
5178 (define_insn "rint<DFP:mode>2"
5179 [(set (match_operand:DFP 0 "register_operand" "=f")
5180 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5181 UNSPEC_FPINT_RINT))]
5183 "fi<DFP:xde>tr\t%0,0,%1,0"
5184 [(set_attr "op_type" "RRF")
5185 (set_attr "type" "fsimp<DFP:mode>")])
5188 ; Binary <-> Decimal floating point trunc patterns
5191 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
5192 [(set (reg:DFP_ALL FPR0_REGNUM)
5193 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5194 (use (reg:SI GPR0_REGNUM))
5195 (clobber (reg:CC CC_REGNUM))
5196 (clobber (reg:SI GPR1_REGNUM))]
5200 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
5201 [(set (reg:BFP FPR0_REGNUM)
5202 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5203 (use (reg:SI GPR0_REGNUM))
5204 (clobber (reg:CC CC_REGNUM))
5205 (clobber (reg:SI GPR1_REGNUM))]
5209 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
5210 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5211 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5213 [(set (reg:DFP_ALL FPR0_REGNUM)
5214 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5215 (use (reg:SI GPR0_REGNUM))
5216 (clobber (reg:CC CC_REGNUM))
5217 (clobber (reg:SI GPR1_REGNUM))])
5218 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5219 (reg:DFP_ALL FPR0_REGNUM))]
5221 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5223 HOST_WIDE_INT flags;
5225 flags = (PFPO_CONVERT |
5226 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5227 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5229 operands[2] = GEN_INT (flags);
5232 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5233 [(set (reg:DFP_ALL FPR4_REGNUM)
5234 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5235 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5237 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5238 (use (reg:SI GPR0_REGNUM))
5239 (clobber (reg:CC CC_REGNUM))
5240 (clobber (reg:SI GPR1_REGNUM))])
5241 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5243 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5245 HOST_WIDE_INT flags;
5247 flags = (PFPO_CONVERT |
5248 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5249 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5251 operands[2] = GEN_INT (flags);
5255 ; Binary <-> Decimal floating point extend patterns
5258 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5259 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5260 (use (reg:SI GPR0_REGNUM))
5261 (clobber (reg:CC CC_REGNUM))
5262 (clobber (reg:SI GPR1_REGNUM))]
5266 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5267 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5268 (use (reg:SI GPR0_REGNUM))
5269 (clobber (reg:CC CC_REGNUM))
5270 (clobber (reg:SI GPR1_REGNUM))]
5274 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5275 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5276 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5278 [(set (reg:DFP_ALL FPR0_REGNUM)
5279 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5280 (use (reg:SI GPR0_REGNUM))
5281 (clobber (reg:CC CC_REGNUM))
5282 (clobber (reg:SI GPR1_REGNUM))])
5283 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5284 (reg:DFP_ALL FPR0_REGNUM))]
5286 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5288 HOST_WIDE_INT flags;
5290 flags = (PFPO_CONVERT |
5291 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5292 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5294 operands[2] = GEN_INT (flags);
5297 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5298 [(set (reg:DFP_ALL FPR4_REGNUM)
5299 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5300 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5302 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5303 (use (reg:SI GPR0_REGNUM))
5304 (clobber (reg:CC CC_REGNUM))
5305 (clobber (reg:SI GPR1_REGNUM))])
5306 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5308 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5310 HOST_WIDE_INT flags;
5312 flags = (PFPO_CONVERT |
5313 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5314 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5316 operands[2] = GEN_INT (flags);
5321 ;; ARITHMETIC OPERATIONS
5323 ; arithmetic operations set the ConditionCode,
5324 ; because of unpredictable Bits in Register for Halfword and Byte
5325 ; the ConditionCode can be set wrong in operations for Halfword and Byte
5328 ;;- Add instructions.
5332 ; addti3 instruction pattern(s).
5335 (define_expand "addti3"
5337 [(set (match_operand:TI 0 "register_operand" "")
5338 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5339 (match_operand:TI 2 "general_operand" "") ) )
5340 (clobber (reg:CC CC_REGNUM))])]
5343 /* For z13 we have vaq which doesn't set CC. */
5346 emit_insn (gen_rtx_SET (operands[0],
5347 gen_rtx_PLUS (TImode,
5348 copy_to_mode_reg (TImode, operands[1]),
5349 copy_to_mode_reg (TImode, operands[2]))));
5354 (define_insn_and_split "*addti3"
5355 [(set (match_operand:TI 0 "register_operand" "=&d")
5356 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5357 (match_operand:TI 2 "general_operand" "do") ) )
5358 (clobber (reg:CC CC_REGNUM))]
5361 "&& reload_completed"
5363 [(set (reg:CCL1 CC_REGNUM)
5364 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5366 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5368 [(set (match_dup 3) (plus:DI
5369 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5370 (match_dup 4)) (match_dup 5)))
5371 (clobber (reg:CC CC_REGNUM))])]
5372 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5373 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5374 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5375 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5376 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5377 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5378 [(set_attr "op_type" "*")
5379 (set_attr "cpu_facility" "*")])
5382 ; adddi3 instruction pattern(s).
5385 (define_expand "adddi3"
5387 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5388 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5389 (match_operand:DI 2 "general_operand" "")))
5390 (clobber (reg:CC CC_REGNUM))])]
5394 (define_insn "*adddi3_sign"
5395 [(set (match_operand:DI 0 "register_operand" "=d,d")
5396 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5397 (match_operand:DI 1 "register_operand" "0,0")))
5398 (clobber (reg:CC CC_REGNUM))]
5403 [(set_attr "op_type" "RRE,RXY")
5404 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5406 (define_insn "*adddi3_zero_cc"
5407 [(set (reg CC_REGNUM)
5408 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5409 (match_operand:DI 1 "register_operand" "0,0"))
5411 (set (match_operand:DI 0 "register_operand" "=d,d")
5412 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5413 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5417 [(set_attr "op_type" "RRE,RXY")
5418 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5420 (define_insn "*adddi3_zero_cconly"
5421 [(set (reg CC_REGNUM)
5422 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5423 (match_operand:DI 1 "register_operand" "0,0"))
5425 (clobber (match_scratch:DI 0 "=d,d"))]
5426 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5430 [(set_attr "op_type" "RRE,RXY")
5431 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5433 (define_insn "*adddi3_zero"
5434 [(set (match_operand:DI 0 "register_operand" "=d,d")
5435 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5436 (match_operand:DI 1 "register_operand" "0,0")))
5437 (clobber (reg:CC CC_REGNUM))]
5442 [(set_attr "op_type" "RRE,RXY")
5443 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5445 (define_insn_and_split "*adddi3_31z"
5446 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5447 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5448 (match_operand:DI 2 "general_operand" "do") ) )
5449 (clobber (reg:CC CC_REGNUM))]
5450 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5452 "&& reload_completed"
5454 [(set (reg:CCL1 CC_REGNUM)
5455 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5457 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5459 [(set (match_dup 3) (plus:SI
5460 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5461 (match_dup 4)) (match_dup 5)))
5462 (clobber (reg:CC CC_REGNUM))])]
5463 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5464 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5465 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5466 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5467 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5468 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5470 (define_insn_and_split "*adddi3_31"
5471 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5472 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5473 (match_operand:DI 2 "general_operand" "do") ) )
5474 (clobber (reg:CC CC_REGNUM))]
5477 "&& reload_completed"
5479 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5480 (clobber (reg:CC CC_REGNUM))])
5482 [(set (reg:CCL1 CC_REGNUM)
5483 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5485 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5487 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5489 (label_ref (match_dup 9))))
5491 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5492 (clobber (reg:CC CC_REGNUM))])
5494 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5495 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5496 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5497 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5498 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5499 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5500 operands[9] = gen_label_rtx ();")
5503 ; addsi3 instruction pattern(s).
5506 (define_expand "addsi3"
5508 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5509 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5510 (match_operand:SI 2 "general_operand" "")))
5511 (clobber (reg:CC CC_REGNUM))])]
5515 (define_insn "*addsi3_sign"
5516 [(set (match_operand:SI 0 "register_operand" "=d,d")
5517 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5518 (match_operand:SI 1 "register_operand" "0,0")))
5519 (clobber (reg:CC CC_REGNUM))]
5524 [(set_attr "op_type" "RX,RXY")
5525 (set_attr "cpu_facility" "*,longdisp")
5526 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5529 ; add(di|si)3 instruction pattern(s).
5532 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5533 (define_insn "*add<mode>3"
5534 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
5535 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
5536 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
5537 (clobber (reg:CC CC_REGNUM))]
5549 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5550 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
5551 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5552 z10_super_E1,z10_super_E1,z10_super_E1")])
5554 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5555 (define_insn "*add<mode>3_carry1_cc"
5556 [(set (reg CC_REGNUM)
5557 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5558 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5560 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5561 (plus:GPR (match_dup 1) (match_dup 2)))]
5562 "s390_match_ccmode (insn, CCL1mode)"
5568 al<g>hsik\t%0,%1,%h2
5572 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5573 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5574 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5575 z10_super_E1,z10_super_E1,z10_super_E1")])
5577 ; alr, al, aly, algr, alg, alrk, algrk
5578 (define_insn "*add<mode>3_carry1_cconly"
5579 [(set (reg CC_REGNUM)
5580 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5581 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5583 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5584 "s390_match_ccmode (insn, CCL1mode)"
5590 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5591 (set_attr "cpu_facility" "*,z196,*,longdisp")
5592 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5594 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5595 (define_insn "*add<mode>3_carry2_cc"
5596 [(set (reg CC_REGNUM)
5597 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5598 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5600 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5601 (plus:GPR (match_dup 1) (match_dup 2)))]
5602 "s390_match_ccmode (insn, CCL1mode)"
5608 al<g>hsik\t%0,%1,%h2
5612 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5613 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5614 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5615 z10_super_E1,z10_super_E1,z10_super_E1")])
5617 ; alr, al, aly, algr, alg, alrk, algrk
5618 (define_insn "*add<mode>3_carry2_cconly"
5619 [(set (reg CC_REGNUM)
5620 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5621 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5623 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5624 "s390_match_ccmode (insn, CCL1mode)"
5630 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5631 (set_attr "cpu_facility" "*,z196,*,longdisp")
5632 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5634 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5635 (define_insn "*add<mode>3_cc"
5636 [(set (reg CC_REGNUM)
5637 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5638 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5640 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5641 (plus:GPR (match_dup 1) (match_dup 2)))]
5642 "s390_match_ccmode (insn, CCLmode)"
5648 al<g>hsik\t%0,%1,%h2
5652 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5653 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5654 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5655 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5657 ; alr, al, aly, algr, alg, alrk, algrk
5658 (define_insn "*add<mode>3_cconly"
5659 [(set (reg CC_REGNUM)
5660 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5661 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5663 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5664 "s390_match_ccmode (insn, CCLmode)"
5670 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5671 (set_attr "cpu_facility" "*,z196,*,longdisp")
5672 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5674 ; alr, al, aly, algr, alg, alrk, algrk
5675 (define_insn "*add<mode>3_cconly2"
5676 [(set (reg CC_REGNUM)
5677 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5678 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5679 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5680 "s390_match_ccmode(insn, CCLmode)"
5686 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5687 (set_attr "cpu_facility" "*,z196,*,longdisp")
5688 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5690 ; ahi, afi, aghi, agfi, asi, agsi
5691 (define_insn "*add<mode>3_imm_cc"
5692 [(set (reg CC_REGNUM)
5693 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5694 (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
5696 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
5697 (plus:GPR (match_dup 1) (match_dup 2)))]
5698 "s390_match_ccmode (insn, CCAmode)
5699 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5700 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5701 /* Avoid INT32_MIN on 32 bit. */
5702 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5708 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5709 (set_attr "cpu_facility" "*,z196,extimm,z10")
5710 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5713 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5716 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5717 ; FIXME: wfadb does not clobber cc
5718 (define_insn "add<mode>3"
5719 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
5720 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5721 (match_operand:FP 2 "general_operand" "f,f,R,v")))
5722 (clobber (reg:CC CC_REGNUM))]
5729 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
5730 (set_attr "type" "fsimp<mode>")
5731 (set_attr "cpu_facility" "*,*,*,vec")
5732 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5734 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5735 (define_insn "*add<mode>3_cc"
5736 [(set (reg CC_REGNUM)
5737 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5738 (match_operand:FP 2 "general_operand" "f,f,R"))
5739 (match_operand:FP 3 "const0_operand" "")))
5740 (set (match_operand:FP 0 "register_operand" "=f,f,f")
5741 (plus:FP (match_dup 1) (match_dup 2)))]
5742 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5747 [(set_attr "op_type" "RRF,RRE,RXE")
5748 (set_attr "type" "fsimp<mode>")
5749 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5751 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5752 (define_insn "*add<mode>3_cconly"
5753 [(set (reg CC_REGNUM)
5754 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5755 (match_operand:FP 2 "general_operand" "f,f,R"))
5756 (match_operand:FP 3 "const0_operand" "")))
5757 (clobber (match_scratch:FP 0 "=f,f,f"))]
5758 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5763 [(set_attr "op_type" "RRF,RRE,RXE")
5764 (set_attr "type" "fsimp<mode>")
5765 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5768 ; Pointer add instruction patterns
5771 ; This will match "*la_64"
5772 (define_expand "addptrdi3"
5773 [(set (match_operand:DI 0 "register_operand" "")
5774 (plus:DI (match_operand:DI 1 "register_operand" "")
5775 (match_operand:DI 2 "nonmemory_operand" "")))]
5778 if (GET_CODE (operands[2]) == CONST_INT)
5780 HOST_WIDE_INT c = INTVAL (operands[2]);
5782 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5783 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5785 operands[2] = force_const_mem (DImode, operands[2]);
5786 operands[2] = force_reg (DImode, operands[2]);
5788 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5789 operands[2] = force_reg (DImode, operands[2]);
5793 ; For 31 bit we have to prevent the generated pattern from matching
5794 ; normal ADDs since la only does a 31 bit add. This is supposed to
5795 ; match "force_la_31".
5796 (define_expand "addptrsi3"
5798 [(set (match_operand:SI 0 "register_operand" "")
5799 (plus:SI (match_operand:SI 1 "register_operand" "")
5800 (match_operand:SI 2 "nonmemory_operand" "")))
5801 (use (const_int 0))])]
5804 if (GET_CODE (operands[2]) == CONST_INT)
5806 HOST_WIDE_INT c = INTVAL (operands[2]);
5808 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5809 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5811 operands[2] = force_const_mem (SImode, operands[2]);
5812 operands[2] = force_reg (SImode, operands[2]);
5814 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5815 operands[2] = force_reg (SImode, operands[2]);
5820 ;;- Subtract instructions.
5824 ; subti3 instruction pattern(s).
5827 (define_expand "subti3"
5829 [(set (match_operand:TI 0 "register_operand" "")
5830 (minus:TI (match_operand:TI 1 "register_operand" "")
5831 (match_operand:TI 2 "general_operand" "") ) )
5832 (clobber (reg:CC CC_REGNUM))])]
5835 /* For z13 we have vsq which doesn't set CC. */
5838 emit_insn (gen_rtx_SET (operands[0],
5839 gen_rtx_MINUS (TImode,
5841 copy_to_mode_reg (TImode, operands[2]))));
5846 (define_insn_and_split "*subti3"
5847 [(set (match_operand:TI 0 "register_operand" "=&d")
5848 (minus:TI (match_operand:TI 1 "register_operand" "0")
5849 (match_operand:TI 2 "general_operand" "do") ) )
5850 (clobber (reg:CC CC_REGNUM))]
5853 "&& reload_completed"
5855 [(set (reg:CCL2 CC_REGNUM)
5856 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5858 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5860 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5861 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5862 (clobber (reg:CC CC_REGNUM))])]
5863 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5864 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5865 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5866 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5867 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5868 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5869 [(set_attr "op_type" "*")
5870 (set_attr "cpu_facility" "*")])
5873 ; subdi3 instruction pattern(s).
5876 (define_expand "subdi3"
5878 [(set (match_operand:DI 0 "register_operand" "")
5879 (minus:DI (match_operand:DI 1 "register_operand" "")
5880 (match_operand:DI 2 "general_operand" "")))
5881 (clobber (reg:CC CC_REGNUM))])]
5885 (define_insn "*subdi3_sign"
5886 [(set (match_operand:DI 0 "register_operand" "=d,d")
5887 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5888 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5889 (clobber (reg:CC CC_REGNUM))]
5894 [(set_attr "op_type" "RRE,RXY")
5895 (set_attr "z10prop" "z10_c,*")
5896 (set_attr "z196prop" "z196_cracked")])
5898 (define_insn "*subdi3_zero_cc"
5899 [(set (reg CC_REGNUM)
5900 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5901 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5903 (set (match_operand:DI 0 "register_operand" "=d,d")
5904 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5905 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5909 [(set_attr "op_type" "RRE,RXY")
5910 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5912 (define_insn "*subdi3_zero_cconly"
5913 [(set (reg CC_REGNUM)
5914 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5915 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5917 (clobber (match_scratch:DI 0 "=d,d"))]
5918 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5922 [(set_attr "op_type" "RRE,RXY")
5923 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5925 (define_insn "*subdi3_zero"
5926 [(set (match_operand:DI 0 "register_operand" "=d,d")
5927 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5928 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5929 (clobber (reg:CC CC_REGNUM))]
5934 [(set_attr "op_type" "RRE,RXY")
5935 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5937 (define_insn_and_split "*subdi3_31z"
5938 [(set (match_operand:DI 0 "register_operand" "=&d")
5939 (minus:DI (match_operand:DI 1 "register_operand" "0")
5940 (match_operand:DI 2 "general_operand" "do") ) )
5941 (clobber (reg:CC CC_REGNUM))]
5942 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5944 "&& reload_completed"
5946 [(set (reg:CCL2 CC_REGNUM)
5947 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5949 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5951 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5952 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5953 (clobber (reg:CC CC_REGNUM))])]
5954 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5955 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5956 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5957 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5958 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5959 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5961 (define_insn_and_split "*subdi3_31"
5962 [(set (match_operand:DI 0 "register_operand" "=&d")
5963 (minus:DI (match_operand:DI 1 "register_operand" "0")
5964 (match_operand:DI 2 "general_operand" "do") ) )
5965 (clobber (reg:CC CC_REGNUM))]
5968 "&& reload_completed"
5970 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5971 (clobber (reg:CC CC_REGNUM))])
5973 [(set (reg:CCL2 CC_REGNUM)
5974 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5976 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5978 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5980 (label_ref (match_dup 9))))
5982 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5983 (clobber (reg:CC CC_REGNUM))])
5985 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5986 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5987 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5988 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5989 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5990 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5991 operands[9] = gen_label_rtx ();")
5994 ; subsi3 instruction pattern(s).
5997 (define_expand "subsi3"
5999 [(set (match_operand:SI 0 "register_operand" "")
6000 (minus:SI (match_operand:SI 1 "register_operand" "")
6001 (match_operand:SI 2 "general_operand" "")))
6002 (clobber (reg:CC CC_REGNUM))])]
6006 (define_insn "*subsi3_sign"
6007 [(set (match_operand:SI 0 "register_operand" "=d,d")
6008 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6009 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
6010 (clobber (reg:CC CC_REGNUM))]
6015 [(set_attr "op_type" "RX,RXY")
6016 (set_attr "cpu_facility" "*,longdisp")
6017 (set_attr "z196prop" "z196_cracked,z196_cracked")])
6020 ; sub(di|si)3 instruction pattern(s).
6023 ; sr, s, sy, sgr, sg, srk, sgrk
6024 (define_insn "*sub<mode>3"
6025 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6026 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6027 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
6028 (clobber (reg:CC CC_REGNUM))]
6035 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6036 (set_attr "cpu_facility" "*,z196,*,longdisp")
6037 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6039 ; slr, sl, sly, slgr, slg, slrk, slgrk
6040 (define_insn "*sub<mode>3_borrow_cc"
6041 [(set (reg CC_REGNUM)
6042 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6043 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6045 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6046 (minus:GPR (match_dup 1) (match_dup 2)))]
6047 "s390_match_ccmode (insn, CCL2mode)"
6053 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6054 (set_attr "cpu_facility" "*,z196,*,longdisp")
6055 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6057 ; slr, sl, sly, slgr, slg, slrk, slgrk
6058 (define_insn "*sub<mode>3_borrow_cconly"
6059 [(set (reg CC_REGNUM)
6060 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6061 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6063 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6064 "s390_match_ccmode (insn, CCL2mode)"
6070 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6071 (set_attr "cpu_facility" "*,z196,*,longdisp")
6072 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6074 ; slr, sl, sly, slgr, slg, slrk, slgrk
6075 (define_insn "*sub<mode>3_cc"
6076 [(set (reg CC_REGNUM)
6077 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6078 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6080 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6081 (minus:GPR (match_dup 1) (match_dup 2)))]
6082 "s390_match_ccmode (insn, CCLmode)"
6088 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6089 (set_attr "cpu_facility" "*,z196,*,longdisp")
6090 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6092 ; slr, sl, sly, slgr, slg, slrk, slgrk
6093 (define_insn "*sub<mode>3_cc2"
6094 [(set (reg CC_REGNUM)
6095 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6096 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6097 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6098 (minus:GPR (match_dup 1) (match_dup 2)))]
6099 "s390_match_ccmode (insn, CCL3mode)"
6105 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6106 (set_attr "cpu_facility" "*,z196,*,longdisp")
6107 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6109 ; slr, sl, sly, slgr, slg, slrk, slgrk
6110 (define_insn "*sub<mode>3_cconly"
6111 [(set (reg CC_REGNUM)
6112 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6113 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6115 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6116 "s390_match_ccmode (insn, CCLmode)"
6122 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6123 (set_attr "cpu_facility" "*,z196,*,longdisp")
6124 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6127 ; slr, sl, sly, slgr, slg, slrk, slgrk
6128 (define_insn "*sub<mode>3_cconly2"
6129 [(set (reg CC_REGNUM)
6130 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6131 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6132 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6133 "s390_match_ccmode (insn, CCL3mode)"
6139 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6140 (set_attr "cpu_facility" "*,z196,*,longdisp")
6141 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6145 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
6148 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6149 (define_insn "sub<mode>3"
6150 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6151 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
6152 (match_operand:FP 2 "general_operand" "f,f,R,v")))
6153 (clobber (reg:CC CC_REGNUM))]
6160 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6161 (set_attr "type" "fsimp<mode>")
6162 (set_attr "cpu_facility" "*,*,*,vec")
6163 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6165 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6166 (define_insn "*sub<mode>3_cc"
6167 [(set (reg CC_REGNUM)
6168 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6169 (match_operand:FP 2 "general_operand" "f,f,R"))
6170 (match_operand:FP 3 "const0_operand" "")))
6171 (set (match_operand:FP 0 "register_operand" "=f,f,f")
6172 (minus:FP (match_dup 1) (match_dup 2)))]
6173 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6178 [(set_attr "op_type" "RRF,RRE,RXE")
6179 (set_attr "type" "fsimp<mode>")
6180 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6182 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6183 (define_insn "*sub<mode>3_cconly"
6184 [(set (reg CC_REGNUM)
6185 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6186 (match_operand:FP 2 "general_operand" "f,f,R"))
6187 (match_operand:FP 3 "const0_operand" "")))
6188 (clobber (match_scratch:FP 0 "=f,f,f"))]
6189 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6194 [(set_attr "op_type" "RRF,RRE,RXE")
6195 (set_attr "type" "fsimp<mode>")
6196 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6200 ;;- Conditional add/subtract instructions.
6204 ; add(di|si)cc instruction pattern(s).
6207 ; the following 4 patterns are used when the result of an add with
6208 ; carry is checked for an overflow condition
6210 ; op1 + op2 + c < op1
6212 ; alcr, alc, alcgr, alcg
6213 (define_insn "*add<mode>3_alc_carry1_cc"
6214 [(set (reg CC_REGNUM)
6216 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6217 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6218 (match_operand:GPR 2 "general_operand" "d,T"))
6220 (set (match_operand:GPR 0 "register_operand" "=d,d")
6221 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6222 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6226 [(set_attr "op_type" "RRE,RXY")
6227 (set_attr "z196prop" "z196_alone,z196_alone")])
6229 ; alcr, alc, alcgr, alcg
6230 (define_insn "*add<mode>3_alc_carry1_cconly"
6231 [(set (reg CC_REGNUM)
6233 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6234 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6235 (match_operand:GPR 2 "general_operand" "d,T"))
6237 (clobber (match_scratch:GPR 0 "=d,d"))]
6238 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6242 [(set_attr "op_type" "RRE,RXY")
6243 (set_attr "z196prop" "z196_alone,z196_alone")])
6245 ; op1 + op2 + c < op2
6247 ; alcr, alc, alcgr, alcg
6248 (define_insn "*add<mode>3_alc_carry2_cc"
6249 [(set (reg CC_REGNUM)
6251 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6252 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6253 (match_operand:GPR 2 "general_operand" "d,T"))
6255 (set (match_operand:GPR 0 "register_operand" "=d,d")
6256 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6257 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6261 [(set_attr "op_type" "RRE,RXY")])
6263 ; alcr, alc, alcgr, alcg
6264 (define_insn "*add<mode>3_alc_carry2_cconly"
6265 [(set (reg CC_REGNUM)
6267 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6268 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6269 (match_operand:GPR 2 "general_operand" "d,T"))
6271 (clobber (match_scratch:GPR 0 "=d,d"))]
6272 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6276 [(set_attr "op_type" "RRE,RXY")])
6278 ; alcr, alc, alcgr, alcg
6279 (define_insn "*add<mode>3_alc_cc"
6280 [(set (reg CC_REGNUM)
6282 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6283 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6284 (match_operand:GPR 2 "general_operand" "d,T"))
6286 (set (match_operand:GPR 0 "register_operand" "=d,d")
6287 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6288 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6292 [(set_attr "op_type" "RRE,RXY")])
6294 ; alcr, alc, alcgr, alcg
6295 (define_insn "*add<mode>3_alc"
6296 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6297 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6298 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6299 (match_operand:GPR 2 "general_operand" "d,T")))
6300 (clobber (reg:CC CC_REGNUM))]
6305 [(set_attr "op_type" "RRE,RXY")])
6307 ; slbr, slb, slbgr, slbg
6308 (define_insn "*sub<mode>3_slb_cc"
6309 [(set (reg CC_REGNUM)
6311 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6312 (match_operand:GPR 2 "general_operand" "d,T"))
6313 (match_operand:GPR 3 "s390_slb_comparison" ""))
6315 (set (match_operand:GPR 0 "register_operand" "=d,d")
6316 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6317 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6321 [(set_attr "op_type" "RRE,RXY")
6322 (set_attr "z10prop" "z10_c,*")])
6324 ; slbr, slb, slbgr, slbg
6325 (define_insn "*sub<mode>3_slb"
6326 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6327 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6328 (match_operand:GPR 2 "general_operand" "d,T"))
6329 (match_operand:GPR 3 "s390_slb_comparison" "")))
6330 (clobber (reg:CC CC_REGNUM))]
6335 [(set_attr "op_type" "RRE,RXY")
6336 (set_attr "z10prop" "z10_c,*")])
6338 (define_expand "add<mode>cc"
6339 [(match_operand:GPR 0 "register_operand" "")
6340 (match_operand 1 "comparison_operator" "")
6341 (match_operand:GPR 2 "register_operand" "")
6342 (match_operand:GPR 3 "const_int_operand" "")]
6344 "if (!s390_expand_addcc (GET_CODE (operands[1]),
6345 XEXP (operands[1], 0), XEXP (operands[1], 1),
6346 operands[0], operands[2],
6347 operands[3])) FAIL; DONE;")
6350 ; scond instruction pattern(s).
6353 (define_insn_and_split "*scond<mode>"
6354 [(set (match_operand:GPR 0 "register_operand" "=&d")
6355 (match_operand:GPR 1 "s390_alc_comparison" ""))
6356 (clobber (reg:CC CC_REGNUM))]
6359 "&& reload_completed"
6360 [(set (match_dup 0) (const_int 0))
6362 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6364 (clobber (reg:CC CC_REGNUM))])]
6367 (define_insn_and_split "*scond<mode>_neg"
6368 [(set (match_operand:GPR 0 "register_operand" "=&d")
6369 (match_operand:GPR 1 "s390_slb_comparison" ""))
6370 (clobber (reg:CC CC_REGNUM))]
6373 "&& reload_completed"
6374 [(set (match_dup 0) (const_int 0))
6376 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6378 (clobber (reg:CC CC_REGNUM))])
6380 [(set (match_dup 0) (neg:GPR (match_dup 0)))
6381 (clobber (reg:CC CC_REGNUM))])]
6385 (define_expand "cstore<mode>4"
6386 [(set (match_operand:SI 0 "register_operand" "")
6387 (match_operator:SI 1 "s390_scond_operator"
6388 [(match_operand:GPR 2 "register_operand" "")
6389 (match_operand:GPR 3 "general_operand" "")]))]
6391 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6392 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6394 (define_expand "cstorecc4"
6396 [(set (match_operand:SI 0 "register_operand" "")
6397 (match_operator:SI 1 "s390_eqne_operator"
6398 [(match_operand:CCZ1 2 "register_operand")
6399 (match_operand 3 "const0_operand")]))
6400 (clobber (reg:CC CC_REGNUM))])]
6402 "emit_insn (gen_sne (operands[0], operands[2]));
6403 if (GET_CODE (operands[1]) == EQ)
6404 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6407 (define_insn_and_split "sne"
6408 [(set (match_operand:SI 0 "register_operand" "=d")
6409 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6411 (clobber (reg:CC CC_REGNUM))]
6416 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6417 (clobber (reg:CC CC_REGNUM))])])
6421 ;; - Conditional move instructions (introduced with z196)
6424 (define_expand "mov<mode>cc"
6425 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6426 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6427 (match_operand:GPR 2 "nonimmediate_operand" "")
6428 (match_operand:GPR 3 "nonimmediate_operand" "")))]
6431 /* Emit the comparison insn in case we do not already have a comparison result. */
6432 if (!s390_comparison (operands[1], VOIDmode))
6433 operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6434 XEXP (operands[1], 0),
6435 XEXP (operands[1], 1));
6438 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
6439 (define_insn_and_split "*mov<mode>cc"
6440 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S,&d")
6442 (match_operator 1 "s390_comparison"
6443 [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c")
6444 (match_operand 5 "const_int_operand" "")])
6445 (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
6446 (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
6458 "&& reload_completed
6459 && MEM_P (operands[3]) && MEM_P (operands[4])"
6462 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6467 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6471 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
6472 (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
6475 ;;- Multiply instructions.
6479 ; muldi3 instruction pattern(s).
6482 (define_insn "*muldi3_sign"
6483 [(set (match_operand:DI 0 "register_operand" "=d,d")
6484 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
6485 (match_operand:DI 1 "register_operand" "0,0")))]
6490 [(set_attr "op_type" "RRE,RXY")
6491 (set_attr "type" "imuldi")])
6493 (define_insn "muldi3"
6494 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6495 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6496 (match_operand:DI 2 "general_operand" "d,K,T,Os")))]
6503 [(set_attr "op_type" "RRE,RI,RXY,RIL")
6504 (set_attr "type" "imuldi")
6505 (set_attr "cpu_facility" "*,*,*,z10")])
6508 ; mulsi3 instruction pattern(s).
6511 (define_insn "*mulsi3_sign"
6512 [(set (match_operand:SI 0 "register_operand" "=d,d")
6513 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6514 (match_operand:SI 1 "register_operand" "0,0")))]
6519 [(set_attr "op_type" "RX,RXY")
6520 (set_attr "type" "imulhi")
6521 (set_attr "cpu_facility" "*,z10")])
6523 (define_insn "mulsi3"
6524 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6525 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6526 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6534 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
6535 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
6536 (set_attr "cpu_facility" "*,*,*,longdisp,z10")])
6539 ; mulsidi3 instruction pattern(s).
6542 (define_insn "mulsidi3"
6543 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6544 (mult:DI (sign_extend:DI
6545 (match_operand:SI 1 "register_operand" "%0,0,0"))
6547 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6553 [(set_attr "op_type" "RR,RX,RXY")
6554 (set_attr "type" "imulsi")
6555 (set_attr "cpu_facility" "*,*,z10")])
6558 ; umul instruction pattern(s).
6561 ; mlr, ml, mlgr, mlg
6562 (define_insn "umul<dwh><mode>3"
6563 [(set (match_operand:DW 0 "register_operand" "=d,d")
6564 (mult:DW (zero_extend:DW
6565 (match_operand:<DWH> 1 "register_operand" "%0,0"))
6567 (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
6572 [(set_attr "op_type" "RRE,RXY")
6573 (set_attr "type" "imul<dwh>")])
6576 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6579 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6580 (define_insn "mul<mode>3"
6581 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6582 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6583 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
6590 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6591 (set_attr "type" "fmul<mode>")
6592 (set_attr "cpu_facility" "*,*,*,vec")
6593 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6595 ; madbr, maebr, maxb, madb, maeb
6596 (define_insn "fma<mode>4"
6597 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6598 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6599 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6600 (match_operand:DSF 3 "register_operand" "0,0,v")))]
6605 wfmadb\t%v0,%v1,%v2,%v3"
6606 [(set_attr "op_type" "RRE,RXE,VRR")
6607 (set_attr "type" "fmadd<mode>")
6608 (set_attr "cpu_facility" "*,*,vec")
6609 (set_attr "enabled" "*,*,<DFDI>")])
6611 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6612 (define_insn "fms<mode>4"
6613 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6614 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6615 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6616 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))]
6621 wfmsdb\t%v0,%v1,%v2,%v3"
6622 [(set_attr "op_type" "RRE,RXE,VRR")
6623 (set_attr "type" "fmadd<mode>")
6624 (set_attr "cpu_facility" "*,*,vec")
6625 (set_attr "enabled" "*,*,<DFDI>")])
6628 ;;- Divide and modulo instructions.
6632 ; divmoddi4 instruction pattern(s).
6635 (define_expand "divmoddi4"
6636 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6637 (div:DI (match_operand:DI 1 "register_operand" "")
6638 (match_operand:DI 2 "general_operand" "")))
6639 (set (match_operand:DI 3 "general_operand" "")
6640 (mod:DI (match_dup 1) (match_dup 2)))])
6641 (clobber (match_dup 4))]
6644 rtx insn, div_equal, mod_equal;
6646 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6647 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6649 operands[4] = gen_reg_rtx(TImode);
6650 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6652 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6653 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6655 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6656 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6661 (define_insn "divmodtidi3"
6662 [(set (match_operand:TI 0 "register_operand" "=d,d")
6666 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6667 (match_operand:DI 2 "general_operand" "d,T")))
6669 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6674 [(set_attr "op_type" "RRE,RXY")
6675 (set_attr "type" "idiv")])
6677 (define_insn "divmodtisi3"
6678 [(set (match_operand:TI 0 "register_operand" "=d,d")
6682 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6684 (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
6687 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6692 [(set_attr "op_type" "RRE,RXY")
6693 (set_attr "type" "idiv")])
6696 ; udivmoddi4 instruction pattern(s).
6699 (define_expand "udivmoddi4"
6700 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6701 (udiv:DI (match_operand:DI 1 "general_operand" "")
6702 (match_operand:DI 2 "nonimmediate_operand" "")))
6703 (set (match_operand:DI 3 "general_operand" "")
6704 (umod:DI (match_dup 1) (match_dup 2)))])
6705 (clobber (match_dup 4))]
6708 rtx insn, div_equal, mod_equal, equal;
6710 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6711 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6712 equal = gen_rtx_IOR (TImode,
6713 gen_rtx_ASHIFT (TImode,
6714 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6716 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6718 operands[4] = gen_reg_rtx(TImode);
6719 emit_clobber (operands[4]);
6720 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6721 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6723 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6724 set_unique_reg_note (insn, REG_EQUAL, equal);
6726 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6727 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6729 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6730 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6735 (define_insn "udivmodtidi3"
6736 [(set (match_operand:TI 0 "register_operand" "=d,d")
6741 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6743 (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
6747 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6752 [(set_attr "op_type" "RRE,RXY")
6753 (set_attr "type" "idiv")])
6756 ; divmodsi4 instruction pattern(s).
6759 (define_expand "divmodsi4"
6760 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6761 (div:SI (match_operand:SI 1 "general_operand" "")
6762 (match_operand:SI 2 "nonimmediate_operand" "")))
6763 (set (match_operand:SI 3 "general_operand" "")
6764 (mod:SI (match_dup 1) (match_dup 2)))])
6765 (clobber (match_dup 4))]
6768 rtx insn, div_equal, mod_equal, equal;
6770 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6771 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6772 equal = gen_rtx_IOR (DImode,
6773 gen_rtx_ASHIFT (DImode,
6774 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6776 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6778 operands[4] = gen_reg_rtx(DImode);
6779 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6781 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6782 set_unique_reg_note (insn, REG_EQUAL, equal);
6784 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6785 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6787 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6788 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6793 (define_insn "divmoddisi3"
6794 [(set (match_operand:DI 0 "register_operand" "=d,d")
6799 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6801 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6805 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6810 [(set_attr "op_type" "RR,RX")
6811 (set_attr "type" "idiv")])
6814 ; udivsi3 and umodsi3 instruction pattern(s).
6817 (define_expand "udivmodsi4"
6818 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6819 (udiv:SI (match_operand:SI 1 "general_operand" "")
6820 (match_operand:SI 2 "nonimmediate_operand" "")))
6821 (set (match_operand:SI 3 "general_operand" "")
6822 (umod:SI (match_dup 1) (match_dup 2)))])
6823 (clobber (match_dup 4))]
6824 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6826 rtx insn, div_equal, mod_equal, equal;
6828 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6829 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6830 equal = gen_rtx_IOR (DImode,
6831 gen_rtx_ASHIFT (DImode,
6832 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6834 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6836 operands[4] = gen_reg_rtx(DImode);
6837 emit_clobber (operands[4]);
6838 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6839 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6841 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6842 set_unique_reg_note (insn, REG_EQUAL, equal);
6844 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6845 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6847 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6848 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6853 (define_insn "udivmoddisi3"
6854 [(set (match_operand:DI 0 "register_operand" "=d,d")
6859 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6861 (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
6865 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6866 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6870 [(set_attr "op_type" "RRE,RXY")
6871 (set_attr "type" "idiv")])
6873 (define_expand "udivsi3"
6874 [(set (match_operand:SI 0 "register_operand" "=d")
6875 (udiv:SI (match_operand:SI 1 "general_operand" "")
6876 (match_operand:SI 2 "general_operand" "")))
6877 (clobber (match_dup 3))]
6878 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6880 rtx insn, udiv_equal, umod_equal, equal;
6882 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6883 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6884 equal = gen_rtx_IOR (DImode,
6885 gen_rtx_ASHIFT (DImode,
6886 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6888 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6890 operands[3] = gen_reg_rtx (DImode);
6892 if (CONSTANT_P (operands[2]))
6894 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6896 rtx_code_label *label1 = gen_label_rtx ();
6898 operands[1] = make_safe_from (operands[1], operands[0]);
6899 emit_move_insn (operands[0], const0_rtx);
6900 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6902 emit_move_insn (operands[0], const1_rtx);
6903 emit_label (label1);
6907 operands[2] = force_reg (SImode, operands[2]);
6908 operands[2] = make_safe_from (operands[2], operands[0]);
6910 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6911 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6913 set_unique_reg_note (insn, REG_EQUAL, equal);
6915 insn = emit_move_insn (operands[0],
6916 gen_lowpart (SImode, operands[3]));
6917 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6922 rtx_code_label *label1 = gen_label_rtx ();
6923 rtx_code_label *label2 = gen_label_rtx ();
6924 rtx_code_label *label3 = gen_label_rtx ();
6926 operands[1] = force_reg (SImode, operands[1]);
6927 operands[1] = make_safe_from (operands[1], operands[0]);
6928 operands[2] = force_reg (SImode, operands[2]);
6929 operands[2] = make_safe_from (operands[2], operands[0]);
6931 emit_move_insn (operands[0], const0_rtx);
6932 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6934 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6936 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6938 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6939 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6941 set_unique_reg_note (insn, REG_EQUAL, equal);
6943 insn = emit_move_insn (operands[0],
6944 gen_lowpart (SImode, operands[3]));
6945 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6948 emit_label (label1);
6949 emit_move_insn (operands[0], operands[1]);
6951 emit_label (label2);
6952 emit_move_insn (operands[0], const1_rtx);
6953 emit_label (label3);
6955 emit_move_insn (operands[0], operands[0]);
6959 (define_expand "umodsi3"
6960 [(set (match_operand:SI 0 "register_operand" "=d")
6961 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6962 (match_operand:SI 2 "nonimmediate_operand" "")))
6963 (clobber (match_dup 3))]
6964 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6966 rtx insn, udiv_equal, umod_equal, equal;
6968 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6969 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6970 equal = gen_rtx_IOR (DImode,
6971 gen_rtx_ASHIFT (DImode,
6972 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6974 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6976 operands[3] = gen_reg_rtx (DImode);
6978 if (CONSTANT_P (operands[2]))
6980 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6982 rtx_code_label *label1 = gen_label_rtx ();
6984 operands[1] = make_safe_from (operands[1], operands[0]);
6985 emit_move_insn (operands[0], operands[1]);
6986 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6988 emit_insn (gen_abssi2 (operands[0], operands[2]));
6989 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6990 emit_label (label1);
6994 operands[2] = force_reg (SImode, operands[2]);
6995 operands[2] = make_safe_from (operands[2], operands[0]);
6997 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6998 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7000 set_unique_reg_note (insn, REG_EQUAL, equal);
7002 insn = emit_move_insn (operands[0],
7003 gen_highpart (SImode, operands[3]));
7004 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7009 rtx_code_label *label1 = gen_label_rtx ();
7010 rtx_code_label *label2 = gen_label_rtx ();
7011 rtx_code_label *label3 = gen_label_rtx ();
7013 operands[1] = force_reg (SImode, operands[1]);
7014 operands[1] = make_safe_from (operands[1], operands[0]);
7015 operands[2] = force_reg (SImode, operands[2]);
7016 operands[2] = make_safe_from (operands[2], operands[0]);
7018 emit_move_insn(operands[0], operands[1]);
7019 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
7021 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
7023 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
7025 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7026 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7028 set_unique_reg_note (insn, REG_EQUAL, equal);
7030 insn = emit_move_insn (operands[0],
7031 gen_highpart (SImode, operands[3]));
7032 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7035 emit_label (label1);
7036 emit_move_insn (operands[0], const0_rtx);
7038 emit_label (label2);
7039 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
7040 emit_label (label3);
7046 ; div(df|sf)3 instruction pattern(s).
7049 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
7050 (define_insn "div<mode>3"
7051 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
7052 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
7053 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
7060 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
7061 (set_attr "type" "fdiv<mode>")
7062 (set_attr "cpu_facility" "*,*,*,vec")
7063 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
7067 ;;- And instructions.
7070 (define_expand "and<mode>3"
7071 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7072 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
7073 (match_operand:INT 2 "general_operand" "")))
7074 (clobber (reg:CC CC_REGNUM))]
7076 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
7079 ; anddi3 instruction pattern(s).
7082 (define_insn "*anddi3_cc"
7083 [(set (reg CC_REGNUM)
7085 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7086 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7088 (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
7089 (and:DI (match_dup 1) (match_dup 2)))]
7090 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
7095 risbg\t%0,%1,%s2,128+%e2,0"
7096 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7097 (set_attr "cpu_facility" "*,z196,*,z10")
7098 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7100 (define_insn "*anddi3_cconly"
7101 [(set (reg CC_REGNUM)
7103 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7104 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7106 (clobber (match_scratch:DI 0 "=d,d,d, d"))]
7108 && s390_match_ccmode(insn, CCTmode)
7109 /* Do not steal TM patterns. */
7110 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
7115 risbg\t%0,%1,%s2,128+%e2,0"
7116 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7117 (set_attr "cpu_facility" "*,z196,*,z10")
7118 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7120 (define_insn "*anddi3"
7121 [(set (match_operand:DI 0 "nonimmediate_operand"
7122 "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
7124 (match_operand:DI 1 "nonimmediate_operand"
7125 "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
7126 (match_operand:DI 2 "general_operand"
7127 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q")))
7128 (clobber (reg:CC CC_REGNUM))]
7129 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7142 risbg\t%0,%1,%s2,128+%e2,0
7145 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7146 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
7147 (set_attr "z10prop" "*,
7163 [(set (match_operand:DI 0 "s_operand" "")
7164 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7165 (clobber (reg:CC CC_REGNUM))]
7168 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7169 (clobber (reg:CC CC_REGNUM))])]
7170 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7172 ;; These two are what combine generates for (ashift (zero_extract)).
7173 (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>"
7174 [(set (match_operand:GPR 0 "register_operand" "=d")
7175 (and:GPR (lshiftrt:GPR
7176 (match_operand:GPR 1 "register_operand" "d")
7177 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7178 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))]
7179 "<z10_or_zEC12_cond>
7180 /* Note that even for the SImode pattern, the rotate is always DImode. */
7181 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
7182 INTVAL (operands[3]))"
7183 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
7184 [(set_attr "op_type" "RIE")
7185 (set_attr "z10prop" "z10_super_E1")])
7187 (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>"
7188 [(set (match_operand:GPR 0 "register_operand" "=d")
7189 (and:GPR (ashift:GPR
7190 (match_operand:GPR 1 "register_operand" "d")
7191 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7192 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))]
7193 "<z10_or_zEC12_cond>
7194 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
7195 INTVAL (operands[3]))"
7196 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
7197 [(set_attr "op_type" "RIE")
7198 (set_attr "z10prop" "z10_super_E1")])
7202 ; andsi3 instruction pattern(s).
7205 (define_insn "*andsi3_cc"
7206 [(set (reg CC_REGNUM)
7209 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7210 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7212 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
7213 (and:SI (match_dup 1) (match_dup 2)))]
7214 "s390_match_ccmode(insn, CCTmode)"
7221 risbg\t%0,%1,%t2,128+%f2,0"
7222 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7223 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7224 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7225 z10_super_E1,z10_super_E1,z10_super_E1")])
7227 (define_insn "*andsi3_cconly"
7228 [(set (reg CC_REGNUM)
7231 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7232 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7234 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
7235 "s390_match_ccmode(insn, CCTmode)
7236 /* Do not steal TM patterns. */
7237 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7244 risbg\t%0,%1,%t2,128+%f2,0"
7245 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7246 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7247 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7248 z10_super_E1,z10_super_E1,z10_super_E1")])
7250 (define_insn "*andsi3_zarch"
7251 [(set (match_operand:SI 0 "nonimmediate_operand"
7252 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
7253 (and:SI (match_operand:SI 1 "nonimmediate_operand"
7254 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
7255 (match_operand:SI 2 "general_operand"
7256 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q")))
7257 (clobber (reg:CC CC_REGNUM))]
7258 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7269 risbg\t%0,%1,%t2,128+%f2,0
7272 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7273 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
7274 (set_attr "z10prop" "*,
7287 (define_insn "*andsi3_esa"
7288 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
7289 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
7290 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
7291 (clobber (reg:CC CC_REGNUM))]
7292 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7298 [(set_attr "op_type" "RR,RX,SI,SS")
7299 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7303 [(set (match_operand:SI 0 "s_operand" "")
7304 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7305 (clobber (reg:CC CC_REGNUM))]
7308 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7309 (clobber (reg:CC CC_REGNUM))])]
7310 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7313 ; andhi3 instruction pattern(s).
7316 (define_insn "*andhi3_zarch"
7317 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7318 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7319 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
7320 (clobber (reg:CC CC_REGNUM))]
7321 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7328 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7329 (set_attr "cpu_facility" "*,z196,*,*,*")
7330 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7333 (define_insn "*andhi3_esa"
7334 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7335 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7336 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7337 (clobber (reg:CC CC_REGNUM))]
7338 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7343 [(set_attr "op_type" "RR,SI,SS")
7344 (set_attr "z10prop" "z10_super_E1,*,*")
7348 [(set (match_operand:HI 0 "s_operand" "")
7349 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7350 (clobber (reg:CC CC_REGNUM))]
7353 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7354 (clobber (reg:CC CC_REGNUM))])]
7355 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7358 ; andqi3 instruction pattern(s).
7361 (define_insn "*andqi3_zarch"
7362 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7363 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7364 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7365 (clobber (reg:CC CC_REGNUM))]
7366 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7374 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7375 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7376 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7378 (define_insn "*andqi3_esa"
7379 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7380 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7381 (match_operand:QI 2 "general_operand" "d,n,Q")))
7382 (clobber (reg:CC CC_REGNUM))]
7383 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7388 [(set_attr "op_type" "RR,SI,SS")
7389 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7392 ; And with complement
7394 ; c = ~b & a = (b & a) ^ a
7396 (define_insn_and_split "*andc_split_<mode>"
7397 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
7398 (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
7399 (match_operand:GPR 2 "general_operand" "")))
7400 (clobber (reg:CC CC_REGNUM))]
7401 "! reload_completed && s390_logical_operator_ok_p (operands)"
7406 [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
7407 (clobber (reg:CC CC_REGNUM))])
7409 [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
7410 (clobber (reg:CC CC_REGNUM))])]
7412 if (reg_overlap_mentioned_p (operands[0], operands[2]))
7413 operands[3] = gen_reg_rtx (<MODE>mode);
7415 operands[3] = operands[0];
7419 ; Block and (NC) patterns.
7423 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7424 (and:BLK (match_dup 0)
7425 (match_operand:BLK 1 "memory_operand" "Q")))
7426 (use (match_operand 2 "const_int_operand" "n"))
7427 (clobber (reg:CC CC_REGNUM))]
7428 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7429 "nc\t%O0(%2,%R0),%S1"
7430 [(set_attr "op_type" "SS")
7431 (set_attr "z196prop" "z196_cracked")])
7434 [(set (match_operand 0 "memory_operand" "")
7436 (match_operand 1 "memory_operand" "")))
7437 (clobber (reg:CC CC_REGNUM))]
7439 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7440 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7442 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7444 (clobber (reg:CC CC_REGNUM))])]
7446 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7447 operands[0] = adjust_address (operands[0], BLKmode, 0);
7448 operands[1] = adjust_address (operands[1], BLKmode, 0);
7453 [(set (match_operand:BLK 0 "memory_operand" "")
7454 (and:BLK (match_dup 0)
7455 (match_operand:BLK 1 "memory_operand" "")))
7456 (use (match_operand 2 "const_int_operand" ""))
7457 (clobber (reg:CC CC_REGNUM))])
7459 [(set (match_operand:BLK 3 "memory_operand" "")
7460 (and:BLK (match_dup 3)
7461 (match_operand:BLK 4 "memory_operand" "")))
7462 (use (match_operand 5 "const_int_operand" ""))
7463 (clobber (reg:CC CC_REGNUM))])]
7464 "s390_offset_p (operands[0], operands[3], operands[2])
7465 && s390_offset_p (operands[1], operands[4], operands[2])
7466 && !s390_overlap_p (operands[0], operands[1],
7467 INTVAL (operands[2]) + INTVAL (operands[5]))
7468 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7470 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7472 (clobber (reg:CC CC_REGNUM))])]
7473 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7474 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7475 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7479 ;;- Bit set (inclusive or) instructions.
7482 (define_expand "ior<mode>3"
7483 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7484 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7485 (match_operand:INT 2 "general_operand" "")))
7486 (clobber (reg:CC CC_REGNUM))]
7488 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7491 ; iordi3 instruction pattern(s).
7494 (define_insn "*iordi3_cc"
7495 [(set (reg CC_REGNUM)
7496 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7497 (match_operand:DI 2 "general_operand" " d,d,T"))
7499 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7500 (ior:DI (match_dup 1) (match_dup 2)))]
7501 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7506 [(set_attr "op_type" "RRE,RRF,RXY")
7507 (set_attr "cpu_facility" "*,z196,*")
7508 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7510 (define_insn "*iordi3_cconly"
7511 [(set (reg CC_REGNUM)
7512 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7513 (match_operand:DI 2 "general_operand" " d,d,T"))
7515 (clobber (match_scratch:DI 0 "=d,d,d"))]
7516 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7521 [(set_attr "op_type" "RRE,RRF,RXY")
7522 (set_attr "cpu_facility" "*,z196,*")
7523 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7525 (define_insn "*iordi3"
7526 [(set (match_operand:DI 0 "nonimmediate_operand"
7527 "=d, d, d, d, d, d,d,d,d, AQ,Q")
7528 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7529 " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
7530 (match_operand:DI 2 "general_operand"
7531 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7532 (clobber (reg:CC CC_REGNUM))]
7533 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7546 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7547 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7548 (set_attr "z10prop" "z10_super_E1,
7561 [(set (match_operand:DI 0 "s_operand" "")
7562 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7563 (clobber (reg:CC CC_REGNUM))]
7566 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7567 (clobber (reg:CC CC_REGNUM))])]
7568 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7571 ; iorsi3 instruction pattern(s).
7574 (define_insn "*iorsi3_cc"
7575 [(set (reg CC_REGNUM)
7576 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7577 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7579 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7580 (ior:SI (match_dup 1) (match_dup 2)))]
7581 "s390_match_ccmode(insn, CCTmode)"
7588 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7589 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7590 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7592 (define_insn "*iorsi3_cconly"
7593 [(set (reg CC_REGNUM)
7594 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7595 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7597 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7598 "s390_match_ccmode(insn, CCTmode)"
7605 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7606 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7607 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7609 (define_insn "*iorsi3_zarch"
7610 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
7611 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
7612 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7613 (clobber (reg:CC CC_REGNUM))]
7614 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7625 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7626 (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
7627 (set_attr "z10prop" "z10_super_E1,
7637 (define_insn "*iorsi3_esa"
7638 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7639 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7640 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7641 (clobber (reg:CC CC_REGNUM))]
7642 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7648 [(set_attr "op_type" "RR,RX,SI,SS")
7649 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7652 [(set (match_operand:SI 0 "s_operand" "")
7653 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7654 (clobber (reg:CC CC_REGNUM))]
7657 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7658 (clobber (reg:CC CC_REGNUM))])]
7659 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7662 ; iorhi3 instruction pattern(s).
7665 (define_insn "*iorhi3_zarch"
7666 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7667 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7668 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7669 (clobber (reg:CC CC_REGNUM))]
7670 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7677 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7678 (set_attr "cpu_facility" "*,z196,*,*,*")
7679 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7681 (define_insn "*iorhi3_esa"
7682 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7683 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7684 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7685 (clobber (reg:CC CC_REGNUM))]
7686 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7691 [(set_attr "op_type" "RR,SI,SS")
7692 (set_attr "z10prop" "z10_super_E1,*,*")])
7695 [(set (match_operand:HI 0 "s_operand" "")
7696 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7697 (clobber (reg:CC CC_REGNUM))]
7700 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7701 (clobber (reg:CC CC_REGNUM))])]
7702 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7705 ; iorqi3 instruction pattern(s).
7708 (define_insn "*iorqi3_zarch"
7709 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7710 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7711 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7712 (clobber (reg:CC CC_REGNUM))]
7713 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7721 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7722 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7723 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7724 z10_super,z10_super,*")])
7726 (define_insn "*iorqi3_esa"
7727 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7728 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7729 (match_operand:QI 2 "general_operand" "d,n,Q")))
7730 (clobber (reg:CC CC_REGNUM))]
7731 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7736 [(set_attr "op_type" "RR,SI,SS")
7737 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7740 ; Block inclusive or (OC) patterns.
7744 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7745 (ior:BLK (match_dup 0)
7746 (match_operand:BLK 1 "memory_operand" "Q")))
7747 (use (match_operand 2 "const_int_operand" "n"))
7748 (clobber (reg:CC CC_REGNUM))]
7749 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7750 "oc\t%O0(%2,%R0),%S1"
7751 [(set_attr "op_type" "SS")
7752 (set_attr "z196prop" "z196_cracked")])
7755 [(set (match_operand 0 "memory_operand" "")
7757 (match_operand 1 "memory_operand" "")))
7758 (clobber (reg:CC CC_REGNUM))]
7760 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7761 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7763 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7765 (clobber (reg:CC CC_REGNUM))])]
7767 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7768 operands[0] = adjust_address (operands[0], BLKmode, 0);
7769 operands[1] = adjust_address (operands[1], BLKmode, 0);
7774 [(set (match_operand:BLK 0 "memory_operand" "")
7775 (ior:BLK (match_dup 0)
7776 (match_operand:BLK 1 "memory_operand" "")))
7777 (use (match_operand 2 "const_int_operand" ""))
7778 (clobber (reg:CC CC_REGNUM))])
7780 [(set (match_operand:BLK 3 "memory_operand" "")
7781 (ior:BLK (match_dup 3)
7782 (match_operand:BLK 4 "memory_operand" "")))
7783 (use (match_operand 5 "const_int_operand" ""))
7784 (clobber (reg:CC CC_REGNUM))])]
7785 "s390_offset_p (operands[0], operands[3], operands[2])
7786 && s390_offset_p (operands[1], operands[4], operands[2])
7787 && !s390_overlap_p (operands[0], operands[1],
7788 INTVAL (operands[2]) + INTVAL (operands[5]))
7789 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7791 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7793 (clobber (reg:CC CC_REGNUM))])]
7794 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7795 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7796 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7800 ;;- Xor instructions.
7803 (define_expand "xor<mode>3"
7804 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7805 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7806 (match_operand:INT 2 "general_operand" "")))
7807 (clobber (reg:CC CC_REGNUM))]
7809 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7811 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7812 ; simplifications. So its better to have something matching.
7814 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7815 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7818 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7819 (clobber (reg:CC CC_REGNUM))])]
7821 operands[2] = constm1_rtx;
7822 if (!s390_logical_operator_ok_p (operands))
7827 ; xordi3 instruction pattern(s).
7830 (define_insn "*xordi3_cc"
7831 [(set (reg CC_REGNUM)
7832 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7833 (match_operand:DI 2 "general_operand" " d,d,T"))
7835 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7836 (xor:DI (match_dup 1) (match_dup 2)))]
7837 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7842 [(set_attr "op_type" "RRE,RRF,RXY")
7843 (set_attr "cpu_facility" "*,z196,*")
7844 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7846 (define_insn "*xordi3_cconly"
7847 [(set (reg CC_REGNUM)
7848 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7849 (match_operand:DI 2 "general_operand" " d,d,T"))
7851 (clobber (match_scratch:DI 0 "=d,d,d"))]
7852 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7857 [(set_attr "op_type" "RRE,RRF,RXY")
7858 (set_attr "cpu_facility" "*,z196,*")
7859 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7861 (define_insn "*xordi3"
7862 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
7863 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
7864 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7865 (clobber (reg:CC CC_REGNUM))]
7866 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7875 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7876 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7877 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7878 *,z10_super_E1,*,*")])
7881 [(set (match_operand:DI 0 "s_operand" "")
7882 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7883 (clobber (reg:CC CC_REGNUM))]
7886 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7887 (clobber (reg:CC CC_REGNUM))])]
7888 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7891 ; xorsi3 instruction pattern(s).
7894 (define_insn "*xorsi3_cc"
7895 [(set (reg CC_REGNUM)
7896 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7897 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7899 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7900 (xor:SI (match_dup 1) (match_dup 2)))]
7901 "s390_match_ccmode(insn, CCTmode)"
7908 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7909 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7910 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7911 z10_super_E1,z10_super_E1")])
7913 (define_insn "*xorsi3_cconly"
7914 [(set (reg CC_REGNUM)
7915 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7916 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7918 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7919 "s390_match_ccmode(insn, CCTmode)"
7926 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7927 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7928 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7929 z10_super_E1,z10_super_E1")])
7931 (define_insn "*xorsi3"
7932 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7933 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7934 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7935 (clobber (reg:CC CC_REGNUM))]
7936 "s390_logical_operator_ok_p (operands)"
7945 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7946 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
7947 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7948 z10_super_E1,z10_super_E1,*,*")])
7951 [(set (match_operand:SI 0 "s_operand" "")
7952 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7953 (clobber (reg:CC CC_REGNUM))]
7956 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7957 (clobber (reg:CC CC_REGNUM))])]
7958 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7961 ; xorhi3 instruction pattern(s).
7964 (define_insn "*xorhi3"
7965 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7966 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7967 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7968 (clobber (reg:CC CC_REGNUM))]
7969 "s390_logical_operator_ok_p (operands)"
7976 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7977 (set_attr "cpu_facility" "*,*,z196,*,*")
7978 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7981 [(set (match_operand:HI 0 "s_operand" "")
7982 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7983 (clobber (reg:CC CC_REGNUM))]
7986 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7987 (clobber (reg:CC CC_REGNUM))])]
7988 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7991 ; xorqi3 instruction pattern(s).
7994 (define_insn "*xorqi3"
7995 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7996 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7997 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7998 (clobber (reg:CC CC_REGNUM))]
7999 "s390_logical_operator_ok_p (operands)"
8007 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
8008 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
8009 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
8013 ; Block exclusive or (XC) patterns.
8017 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8018 (xor:BLK (match_dup 0)
8019 (match_operand:BLK 1 "memory_operand" "Q")))
8020 (use (match_operand 2 "const_int_operand" "n"))
8021 (clobber (reg:CC CC_REGNUM))]
8022 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
8023 "xc\t%O0(%2,%R0),%S1"
8024 [(set_attr "op_type" "SS")])
8027 [(set (match_operand 0 "memory_operand" "")
8029 (match_operand 1 "memory_operand" "")))
8030 (clobber (reg:CC CC_REGNUM))]
8032 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8033 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
8035 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
8037 (clobber (reg:CC CC_REGNUM))])]
8039 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
8040 operands[0] = adjust_address (operands[0], BLKmode, 0);
8041 operands[1] = adjust_address (operands[1], BLKmode, 0);
8046 [(set (match_operand:BLK 0 "memory_operand" "")
8047 (xor:BLK (match_dup 0)
8048 (match_operand:BLK 1 "memory_operand" "")))
8049 (use (match_operand 2 "const_int_operand" ""))
8050 (clobber (reg:CC CC_REGNUM))])
8052 [(set (match_operand:BLK 3 "memory_operand" "")
8053 (xor:BLK (match_dup 3)
8054 (match_operand:BLK 4 "memory_operand" "")))
8055 (use (match_operand 5 "const_int_operand" ""))
8056 (clobber (reg:CC CC_REGNUM))])]
8057 "s390_offset_p (operands[0], operands[3], operands[2])
8058 && s390_offset_p (operands[1], operands[4], operands[2])
8059 && !s390_overlap_p (operands[0], operands[1],
8060 INTVAL (operands[2]) + INTVAL (operands[5]))
8061 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
8063 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
8065 (clobber (reg:CC CC_REGNUM))])]
8066 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8067 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
8068 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
8071 ; Block xor (XC) patterns with src == dest.
8074 (define_insn "*xc_zero"
8075 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8077 (use (match_operand 1 "const_int_operand" "n"))
8078 (clobber (reg:CC CC_REGNUM))]
8079 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
8080 "xc\t%O0(%1,%R0),%S0"
8081 [(set_attr "op_type" "SS")
8082 (set_attr "z196prop" "z196_cracked")])
8086 [(set (match_operand:BLK 0 "memory_operand" "")
8088 (use (match_operand 1 "const_int_operand" ""))
8089 (clobber (reg:CC CC_REGNUM))])
8091 [(set (match_operand:BLK 2 "memory_operand" "")
8093 (use (match_operand 3 "const_int_operand" ""))
8094 (clobber (reg:CC CC_REGNUM))])]
8095 "s390_offset_p (operands[0], operands[2], operands[1])
8096 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
8098 [(set (match_dup 4) (const_int 0))
8100 (clobber (reg:CC CC_REGNUM))])]
8101 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8102 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
8106 ;;- Negate instructions.
8110 ; neg(di|si)2 instruction pattern(s).
8113 (define_expand "neg<mode>2"
8115 [(set (match_operand:DSI 0 "register_operand" "=d")
8116 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
8117 (clobber (reg:CC CC_REGNUM))])]
8121 (define_insn "*negdi2_sign_cc"
8122 [(set (reg CC_REGNUM)
8123 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
8124 (match_operand:SI 1 "register_operand" "d") 0)
8125 (const_int 32)) (const_int 32)))
8127 (set (match_operand:DI 0 "register_operand" "=d")
8128 (neg:DI (sign_extend:DI (match_dup 1))))]
8129 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8131 [(set_attr "op_type" "RRE")
8132 (set_attr "z10prop" "z10_c")])
8134 (define_insn "*negdi2_sign"
8135 [(set (match_operand:DI 0 "register_operand" "=d")
8136 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8137 (clobber (reg:CC CC_REGNUM))]
8140 [(set_attr "op_type" "RRE")
8141 (set_attr "z10prop" "z10_c")])
8144 (define_insn "*neg<mode>2_cc"
8145 [(set (reg CC_REGNUM)
8146 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8148 (set (match_operand:GPR 0 "register_operand" "=d")
8149 (neg:GPR (match_dup 1)))]
8150 "s390_match_ccmode (insn, CCAmode)"
8152 [(set_attr "op_type" "RR<E>")
8153 (set_attr "z10prop" "z10_super_c_E1")])
8156 (define_insn "*neg<mode>2_cconly"
8157 [(set (reg CC_REGNUM)
8158 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8160 (clobber (match_scratch:GPR 0 "=d"))]
8161 "s390_match_ccmode (insn, CCAmode)"
8163 [(set_attr "op_type" "RR<E>")
8164 (set_attr "z10prop" "z10_super_c_E1")])
8167 (define_insn "*neg<mode>2"
8168 [(set (match_operand:GPR 0 "register_operand" "=d")
8169 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
8170 (clobber (reg:CC CC_REGNUM))]
8173 [(set_attr "op_type" "RR<E>")
8174 (set_attr "z10prop" "z10_super_c_E1")])
8176 (define_insn "*negdi2_31"
8177 [(set (match_operand:DI 0 "register_operand" "=d")
8178 (neg:DI (match_operand:DI 1 "register_operand" "d")))
8179 (clobber (reg:CC CC_REGNUM))]
8183 ; Split a DImode NEG on 31bit into 2 SImode NEGs
8185 ; Doing the twos complement separately on the SImode parts does an
8186 ; unwanted +1 on the high part which needs to be subtracted afterwards
8187 ; ... unless the +1 on the low part created an overflow.
8190 [(set (match_operand:DI 0 "register_operand" "")
8191 (neg:DI (match_operand:DI 1 "register_operand" "")))
8192 (clobber (reg:CC CC_REGNUM))]
8194 && (REGNO (operands[0]) == REGNO (operands[1])
8195 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
8196 && reload_completed"
8198 [(set (match_dup 2) (neg:SI (match_dup 3)))
8199 (clobber (reg:CC CC_REGNUM))])
8201 [(set (reg:CCAP CC_REGNUM)
8202 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
8203 (set (match_dup 4) (neg:SI (match_dup 5)))])
8205 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8207 (label_ref (match_dup 6))))
8209 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8210 (clobber (reg:CC CC_REGNUM))])
8212 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8213 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8214 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8215 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8216 operands[6] = gen_label_rtx ();")
8218 ; Like above but first make a copy of the low part of the src operand
8219 ; since it might overlap with the high part of the destination.
8222 [(set (match_operand:DI 0 "register_operand" "")
8223 (neg:DI (match_operand:DI 1 "register_operand" "")))
8224 (clobber (reg:CC CC_REGNUM))]
8226 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
8227 && reload_completed"
8228 [; Make a backup of op5 first
8229 (set (match_dup 4) (match_dup 5))
8230 ; Setting op2 here might clobber op5
8232 [(set (match_dup 2) (neg:SI (match_dup 3)))
8233 (clobber (reg:CC CC_REGNUM))])
8235 [(set (reg:CCAP CC_REGNUM)
8236 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
8237 (set (match_dup 4) (neg:SI (match_dup 4)))])
8239 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8241 (label_ref (match_dup 6))))
8243 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8244 (clobber (reg:CC CC_REGNUM))])
8246 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8247 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8248 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8249 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8250 operands[6] = gen_label_rtx ();")
8253 ; neg(df|sf)2 instruction pattern(s).
8256 (define_expand "neg<mode>2"
8258 [(set (match_operand:BFP 0 "register_operand" "=f")
8259 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
8260 (clobber (reg:CC CC_REGNUM))])]
8264 ; lcxbr, lcdbr, lcebr
8265 (define_insn "*neg<mode>2_cc"
8266 [(set (reg CC_REGNUM)
8267 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8268 (match_operand:BFP 2 "const0_operand" "")))
8269 (set (match_operand:BFP 0 "register_operand" "=f")
8270 (neg:BFP (match_dup 1)))]
8271 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8273 [(set_attr "op_type" "RRE")
8274 (set_attr "type" "fsimp<mode>")])
8276 ; lcxbr, lcdbr, lcebr
8277 (define_insn "*neg<mode>2_cconly"
8278 [(set (reg CC_REGNUM)
8279 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8280 (match_operand:BFP 2 "const0_operand" "")))
8281 (clobber (match_scratch:BFP 0 "=f"))]
8282 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8284 [(set_attr "op_type" "RRE")
8285 (set_attr "type" "fsimp<mode>")])
8288 (define_insn "*neg<mode>2_nocc"
8289 [(set (match_operand:FP 0 "register_operand" "=f")
8290 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8293 [(set_attr "op_type" "RRE")
8294 (set_attr "type" "fsimp<mode>")])
8296 ; lcxbr, lcdbr, lcebr
8297 ; FIXME: wflcdb does not clobber cc
8298 (define_insn "*neg<mode>2"
8299 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8300 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8301 (clobber (reg:CC CC_REGNUM))]
8306 [(set_attr "op_type" "RRE,VRR")
8307 (set_attr "cpu_facility" "*,vec")
8308 (set_attr "type" "fsimp<mode>,*")
8309 (set_attr "enabled" "*,<DFDI>")])
8313 ;;- Absolute value instructions.
8317 ; abs(di|si)2 instruction pattern(s).
8320 (define_insn "*absdi2_sign_cc"
8321 [(set (reg CC_REGNUM)
8322 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8323 (match_operand:SI 1 "register_operand" "d") 0)
8324 (const_int 32)) (const_int 32)))
8326 (set (match_operand:DI 0 "register_operand" "=d")
8327 (abs:DI (sign_extend:DI (match_dup 1))))]
8328 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8330 [(set_attr "op_type" "RRE")
8331 (set_attr "z10prop" "z10_c")])
8333 (define_insn "*absdi2_sign"
8334 [(set (match_operand:DI 0 "register_operand" "=d")
8335 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8336 (clobber (reg:CC CC_REGNUM))]
8339 [(set_attr "op_type" "RRE")
8340 (set_attr "z10prop" "z10_c")])
8343 (define_insn "*abs<mode>2_cc"
8344 [(set (reg CC_REGNUM)
8345 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8347 (set (match_operand:GPR 0 "register_operand" "=d")
8348 (abs:GPR (match_dup 1)))]
8349 "s390_match_ccmode (insn, CCAmode)"
8351 [(set_attr "op_type" "RR<E>")
8352 (set_attr "z10prop" "z10_c")])
8355 (define_insn "*abs<mode>2_cconly"
8356 [(set (reg CC_REGNUM)
8357 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8359 (clobber (match_scratch:GPR 0 "=d"))]
8360 "s390_match_ccmode (insn, CCAmode)"
8362 [(set_attr "op_type" "RR<E>")
8363 (set_attr "z10prop" "z10_c")])
8366 (define_insn "abs<mode>2"
8367 [(set (match_operand:GPR 0 "register_operand" "=d")
8368 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8369 (clobber (reg:CC CC_REGNUM))]
8372 [(set_attr "op_type" "RR<E>")
8373 (set_attr "z10prop" "z10_c")])
8376 ; abs(df|sf)2 instruction pattern(s).
8379 (define_expand "abs<mode>2"
8381 [(set (match_operand:BFP 0 "register_operand" "=f")
8382 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8383 (clobber (reg:CC CC_REGNUM))])]
8387 ; lpxbr, lpdbr, lpebr
8388 (define_insn "*abs<mode>2_cc"
8389 [(set (reg CC_REGNUM)
8390 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8391 (match_operand:BFP 2 "const0_operand" "")))
8392 (set (match_operand:BFP 0 "register_operand" "=f")
8393 (abs:BFP (match_dup 1)))]
8394 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8396 [(set_attr "op_type" "RRE")
8397 (set_attr "type" "fsimp<mode>")])
8399 ; lpxbr, lpdbr, lpebr
8400 (define_insn "*abs<mode>2_cconly"
8401 [(set (reg CC_REGNUM)
8402 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8403 (match_operand:BFP 2 "const0_operand" "")))
8404 (clobber (match_scratch:BFP 0 "=f"))]
8405 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8407 [(set_attr "op_type" "RRE")
8408 (set_attr "type" "fsimp<mode>")])
8411 (define_insn "*abs<mode>2_nocc"
8412 [(set (match_operand:FP 0 "register_operand" "=f")
8413 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8416 [(set_attr "op_type" "RRE")
8417 (set_attr "type" "fsimp<mode>")])
8419 ; lpxbr, lpdbr, lpebr
8420 ; FIXME: wflpdb does not clobber cc
8421 (define_insn "*abs<mode>2"
8422 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8423 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8424 (clobber (reg:CC CC_REGNUM))]
8429 [(set_attr "op_type" "RRE,VRR")
8430 (set_attr "cpu_facility" "*,vec")
8431 (set_attr "type" "fsimp<mode>,*")
8432 (set_attr "enabled" "*,<DFDI>")])
8436 ;;- Negated absolute value instructions
8443 (define_insn "*negabsdi2_sign_cc"
8444 [(set (reg CC_REGNUM)
8445 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8446 (match_operand:SI 1 "register_operand" "d") 0)
8447 (const_int 32)) (const_int 32))))
8449 (set (match_operand:DI 0 "register_operand" "=d")
8450 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8451 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8453 [(set_attr "op_type" "RRE")
8454 (set_attr "z10prop" "z10_c")])
8456 (define_insn "*negabsdi2_sign"
8457 [(set (match_operand:DI 0 "register_operand" "=d")
8458 (neg:DI (abs:DI (sign_extend:DI
8459 (match_operand:SI 1 "register_operand" "d")))))
8460 (clobber (reg:CC CC_REGNUM))]
8463 [(set_attr "op_type" "RRE")
8464 (set_attr "z10prop" "z10_c")])
8467 (define_insn "*negabs<mode>2_cc"
8468 [(set (reg CC_REGNUM)
8469 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8471 (set (match_operand:GPR 0 "register_operand" "=d")
8472 (neg:GPR (abs:GPR (match_dup 1))))]
8473 "s390_match_ccmode (insn, CCAmode)"
8475 [(set_attr "op_type" "RR<E>")
8476 (set_attr "z10prop" "z10_c")])
8479 (define_insn "*negabs<mode>2_cconly"
8480 [(set (reg CC_REGNUM)
8481 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8483 (clobber (match_scratch:GPR 0 "=d"))]
8484 "s390_match_ccmode (insn, CCAmode)"
8486 [(set_attr "op_type" "RR<E>")
8487 (set_attr "z10prop" "z10_c")])
8490 (define_insn "*negabs<mode>2"
8491 [(set (match_operand:GPR 0 "register_operand" "=d")
8492 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8493 (clobber (reg:CC CC_REGNUM))]
8496 [(set_attr "op_type" "RR<E>")
8497 (set_attr "z10prop" "z10_c")])
8503 ; lnxbr, lndbr, lnebr
8504 (define_insn "*negabs<mode>2_cc"
8505 [(set (reg CC_REGNUM)
8506 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8507 (match_operand:BFP 2 "const0_operand" "")))
8508 (set (match_operand:BFP 0 "register_operand" "=f")
8509 (neg:BFP (abs:BFP (match_dup 1))))]
8510 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8512 [(set_attr "op_type" "RRE")
8513 (set_attr "type" "fsimp<mode>")])
8515 ; lnxbr, lndbr, lnebr
8516 (define_insn "*negabs<mode>2_cconly"
8517 [(set (reg CC_REGNUM)
8518 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8519 (match_operand:BFP 2 "const0_operand" "")))
8520 (clobber (match_scratch:BFP 0 "=f"))]
8521 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8523 [(set_attr "op_type" "RRE")
8524 (set_attr "type" "fsimp<mode>")])
8527 (define_insn "*negabs<mode>2_nocc"
8528 [(set (match_operand:FP 0 "register_operand" "=f")
8529 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8532 [(set_attr "op_type" "RRE")
8533 (set_attr "type" "fsimp<mode>")])
8535 ; lnxbr, lndbr, lnebr
8536 ; FIXME: wflndb does not clobber cc
8537 (define_insn "*negabs<mode>2"
8538 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8539 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
8540 (clobber (reg:CC CC_REGNUM))]
8545 [(set_attr "op_type" "RRE,VRR")
8546 (set_attr "cpu_facility" "*,vec")
8547 (set_attr "type" "fsimp<mode>,*")
8548 (set_attr "enabled" "*,<DFDI>")])
8551 ;;- Square root instructions.
8555 ; sqrt(df|sf)2 instruction pattern(s).
8558 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8559 (define_insn "sqrt<mode>2"
8560 [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
8561 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
8567 [(set_attr "op_type" "RRE,RXE,VRR")
8568 (set_attr "type" "fsqrt<mode>")
8569 (set_attr "cpu_facility" "*,*,vec")
8570 (set_attr "enabled" "*,<DSF>,<DFDI>")])
8574 ;;- One complement instructions.
8578 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8581 (define_expand "one_cmpl<mode>2"
8583 [(set (match_operand:INT 0 "register_operand" "")
8584 (xor:INT (match_operand:INT 1 "register_operand" "")
8586 (clobber (reg:CC CC_REGNUM))])]
8592 ;; Find leftmost bit instructions.
8595 (define_expand "clzdi2"
8596 [(set (match_operand:DI 0 "register_operand" "=d")
8597 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8598 "TARGET_EXTIMM && TARGET_ZARCH"
8600 rtx insn, clz_equal;
8601 rtx wide_reg = gen_reg_rtx (TImode);
8602 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8604 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8606 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8608 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8609 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8614 (define_insn "clztidi2"
8615 [(set (match_operand:TI 0 "register_operand" "=d")
8619 (xor:DI (match_operand:DI 1 "register_operand" "d")
8620 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8621 (subreg:SI (clz:DI (match_dup 1)) 4))))
8624 (zero_extend:TI (clz:DI (match_dup 1)))))
8625 (clobber (reg:CC CC_REGNUM))]
8626 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8627 == (unsigned HOST_WIDE_INT) 1 << 63
8628 && TARGET_EXTIMM && TARGET_ZARCH"
8630 [(set_attr "op_type" "RRE")])
8634 ;;- Rotate instructions.
8638 ; rotl(di|si)3 instruction pattern(s).
8641 (define_expand "rotl<mode>3"
8642 [(set (match_operand:GPR 0 "register_operand" "")
8643 (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8644 (match_operand:SI 2 "nonmemory_operand" "")))]
8649 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8650 [(set (match_operand:GPR 0 "register_operand" "=d")
8651 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8652 (match_operand:SI 2 "nonmemory_operand" "an")))]
8654 "rll<g>\t%0,%1,<addr_style_op_ops>"
8655 [(set_attr "op_type" "RSE")
8656 (set_attr "atype" "reg")
8657 (set_attr "z10prop" "z10_super_E1")])
8661 ;;- Shift instructions.
8665 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8666 ; Left shifts and logical right shifts
8668 (define_expand "<shift><mode>3"
8669 [(set (match_operand:DSI 0 "register_operand" "")
8670 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8671 (match_operand:SI 2 "nonmemory_operand" "")))]
8675 ; ESA 64 bit register pair shift with reg or imm shift count
8677 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8678 [(set (match_operand:DI 0 "register_operand" "=d")
8679 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8680 (match_operand:SI 2 "nonmemory_operand" "an")))]
8682 "s<lr>dl\t%0,<addr_style_op_ops>"
8683 [(set_attr "op_type" "RS")
8684 (set_attr "atype" "reg")
8685 (set_attr "z196prop" "z196_cracked")])
8688 ; 64 bit register shift with reg or imm shift count
8689 ; sll, srl, sllg, srlg, sllk, srlk
8690 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8691 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8692 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8693 (match_operand:SI 2 "nonmemory_operand" "an,an")))]
8696 s<lr>l<g>\t%0,<1><addr_style_op_ops>
8697 s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8698 [(set_attr "op_type" "RS<E>,RSY")
8699 (set_attr "atype" "reg,reg")
8700 (set_attr "cpu_facility" "*,z196")
8701 (set_attr "z10prop" "z10_super_E1,*")])
8704 ; ashr(di|si)3 instruction pattern(s).
8705 ; Arithmetic right shifts
8707 (define_expand "ashr<mode>3"
8709 [(set (match_operand:DSI 0 "register_operand" "")
8710 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8711 (match_operand:SI 2 "nonmemory_operand" "")))
8712 (clobber (reg:CC CC_REGNUM))])]
8716 ; FIXME: The number of alternatives is doubled here to match the fix
8717 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8718 ; The right fix should be to support match_scratch in the output
8719 ; pattern of a define_subst.
8720 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8721 [(set (match_operand:DI 0 "register_operand" "=d, d")
8722 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0")
8723 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8724 (clobber (reg:CC CC_REGNUM))]
8727 srda\t%0,<addr_style_op_cc_ops>
8728 srda\t%0,<addr_style_op_cc_ops>"
8729 [(set_attr "op_type" "RS")
8730 (set_attr "atype" "reg")])
8734 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8735 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8736 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8737 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8738 (clobber (reg:CC CC_REGNUM))]
8741 sra<g>\t%0,<1><addr_style_op_cc_ops>
8742 sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8743 [(set_attr "op_type" "RS<E>,RSY")
8744 (set_attr "atype" "reg")
8745 (set_attr "cpu_facility" "*,z196")
8746 (set_attr "z10prop" "z10_super_E1,*")])
8750 ;; Branch instruction patterns.
8753 (define_expand "cbranch<mode>4"
8755 (if_then_else (match_operator 0 "comparison_operator"
8756 [(match_operand:GPR 1 "register_operand" "")
8757 (match_operand:GPR 2 "general_operand" "")])
8758 (label_ref (match_operand 3 "" ""))
8761 "s390_emit_jump (operands[3],
8762 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8765 (define_expand "cbranch<mode>4"
8767 (if_then_else (match_operator 0 "comparison_operator"
8768 [(match_operand:FP 1 "register_operand" "")
8769 (match_operand:FP 2 "general_operand" "")])
8770 (label_ref (match_operand 3 "" ""))
8773 "s390_emit_jump (operands[3],
8774 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8777 (define_expand "cbranchcc4"
8779 (if_then_else (match_operator 0 "s390_comparison"
8780 [(match_operand 1 "cc_reg_operand" "")
8781 (match_operand 2 "const_int_operand" "")])
8782 (label_ref (match_operand 3 "" ""))
8789 ;;- Conditional jump instructions.
8792 (define_insn "*cjump_64"
8795 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8796 (match_operand 2 "const_int_operand" "")])
8797 (label_ref (match_operand 0 "" ""))
8801 if (get_attr_length (insn) == 4)
8804 return "jg%C1\t%l0";
8806 [(set_attr "op_type" "RI")
8807 (set_attr "type" "branch")
8808 (set (attr "length")
8809 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8810 (const_int 4) (const_int 6)))])
8812 (define_insn "*cjump_31"
8815 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8816 (match_operand 2 "const_int_operand" "")])
8817 (label_ref (match_operand 0 "" ""))
8821 gcc_assert (get_attr_length (insn) == 4);
8824 [(set_attr "op_type" "RI")
8825 (set_attr "type" "branch")
8826 (set (attr "length")
8827 (if_then_else (not (match_test "flag_pic"))
8828 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8829 (const_int 4) (const_int 6))
8830 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8831 (const_int 4) (const_int 8))))])
8833 (define_insn "*cjump_long"
8836 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8837 (match_operand 0 "address_operand" "ZQZR")
8841 if (get_attr_op_type (insn) == OP_TYPE_RR)
8846 [(set (attr "op_type")
8847 (if_then_else (match_operand 0 "register_operand" "")
8848 (const_string "RR") (const_string "RX")))
8849 (set_attr "type" "branch")
8850 (set_attr "atype" "agen")])
8852 ;; A conditional return instruction.
8853 (define_insn "*c<code>"
8856 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8859 "s390_can_use_<code>_insn ()"
8861 [(set_attr "op_type" "RR")
8862 (set_attr "type" "jsr")
8863 (set_attr "atype" "agen")])
8866 ;;- Negated conditional jump instructions.
8869 (define_insn "*icjump_64"
8872 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8874 (label_ref (match_operand 0 "" ""))))]
8877 if (get_attr_length (insn) == 4)
8880 return "jg%D1\t%l0";
8882 [(set_attr "op_type" "RI")
8883 (set_attr "type" "branch")
8884 (set (attr "length")
8885 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8886 (const_int 4) (const_int 6)))])
8888 (define_insn "*icjump_31"
8891 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8893 (label_ref (match_operand 0 "" ""))))]
8896 gcc_assert (get_attr_length (insn) == 4);
8899 [(set_attr "op_type" "RI")
8900 (set_attr "type" "branch")
8901 (set (attr "length")
8902 (if_then_else (not (match_test "flag_pic"))
8903 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8904 (const_int 4) (const_int 6))
8905 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8906 (const_int 4) (const_int 8))))])
8908 (define_insn "*icjump_long"
8911 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8913 (match_operand 0 "address_operand" "ZQZR")))]
8916 if (get_attr_op_type (insn) == OP_TYPE_RR)
8921 [(set (attr "op_type")
8922 (if_then_else (match_operand 0 "register_operand" "")
8923 (const_string "RR") (const_string "RX")))
8924 (set_attr "type" "branch")
8925 (set_attr "atype" "agen")])
8928 ;;- Trap instructions.
8932 [(trap_if (const_int 1) (const_int 0))]
8935 [(set_attr "op_type" "RI")
8936 (set_attr "type" "branch")])
8938 (define_expand "ctrap<mode>4"
8939 [(trap_if (match_operator 0 "comparison_operator"
8940 [(match_operand:GPR 1 "register_operand" "")
8941 (match_operand:GPR 2 "general_operand" "")])
8942 (match_operand 3 "const0_operand" ""))]
8945 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8946 operands[1], operands[2]);
8947 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8951 (define_expand "ctrap<mode>4"
8952 [(trap_if (match_operator 0 "comparison_operator"
8953 [(match_operand:FP 1 "register_operand" "")
8954 (match_operand:FP 2 "general_operand" "")])
8955 (match_operand 3 "const0_operand" ""))]
8958 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8959 operands[1], operands[2]);
8960 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8964 (define_insn "condtrap"
8965 [(trap_if (match_operator 0 "s390_comparison"
8966 [(match_operand 1 "cc_reg_operand" "c")
8971 [(set_attr "op_type" "RI")
8972 (set_attr "type" "branch")])
8974 ; crt, cgrt, cit, cgit
8975 (define_insn "*cmp_and_trap_signed_int<mode>"
8976 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8977 [(match_operand:GPR 1 "register_operand" "d,d")
8978 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8984 [(set_attr "op_type" "RRF,RIE")
8985 (set_attr "type" "branch")
8986 (set_attr "z10prop" "z10_super_c,z10_super")])
8988 ; clrt, clgrt, clfit, clgit, clt, clgt
8989 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8990 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8991 [(match_operand:GPR 1 "register_operand" "d,d,d")
8992 (match_operand:GPR 2 "general_operand" "d,D,T")])
8999 [(set_attr "op_type" "RRF,RIE,RSY")
9000 (set_attr "type" "branch")
9001 (set_attr "z10prop" "z10_super_c,z10_super,*")
9002 (set_attr "cpu_facility" "z10,z10,zEC12")])
9005 (define_insn "*load_and_trap<mode>"
9006 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
9009 (set (match_operand:GPR 1 "register_operand" "=d")
9013 [(set_attr "op_type" "RXY")])
9017 ;;- Loop instructions.
9019 ;; This is all complicated by the fact that since this is a jump insn
9020 ;; we must handle our own output reloads.
9024 ; This splitter will be matched by combine and has to add the 2 moves
9025 ; necessary to load the compare and the increment values into a
9026 ; register pair as needed by brxle.
9028 (define_insn_and_split "*brx_stage1_<GPR:mode>"
9031 (match_operator 6 "s390_brx_operator"
9032 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
9033 (match_operand:GPR 2 "general_operand" ""))
9034 (match_operand:GPR 3 "register_operand" "")])
9035 (label_ref (match_operand 0 "" ""))
9037 (set (match_operand:GPR 4 "nonimmediate_operand" "")
9038 (plus:GPR (match_dup 1) (match_dup 2)))
9039 (clobber (match_scratch:GPR 5 ""))]
9042 "!reload_completed && !reload_in_progress"
9043 [(set (match_dup 7) (match_dup 2)) ; the increment
9044 (set (match_dup 8) (match_dup 3)) ; the comparison value
9045 (parallel [(set (pc)
9048 [(plus:GPR (match_dup 1) (match_dup 7))
9050 (label_ref (match_dup 0))
9053 (plus:GPR (match_dup 1) (match_dup 7)))
9054 (clobber (match_dup 5))
9055 (clobber (reg:CC CC_REGNUM))])]
9057 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
9058 operands[7] = gen_lowpart (<GPR:MODE>mode,
9059 gen_highpart (word_mode, dreg));
9060 operands[8] = gen_lowpart (<GPR:MODE>mode,
9061 gen_lowpart (word_mode, dreg));
9066 (define_insn_and_split "*brxg_64bit"
9069 (match_operator 5 "s390_brx_operator"
9070 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
9071 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
9072 (subreg:DI (match_dup 2) 8)])
9073 (label_ref (match_operand 0 "" ""))
9075 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
9076 (plus:DI (match_dup 1)
9077 (subreg:DI (match_dup 2) 0)))
9078 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
9079 (clobber (reg:CC CC_REGNUM))]
9082 if (which_alternative != 0)
9084 else if (get_attr_length (insn) == 6)
9085 return "brx%E5g\t%1,%2,%l0";
9087 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
9089 "&& reload_completed
9090 && (!REG_P (operands[3])
9091 || !rtx_equal_p (operands[1], operands[3]))"
9092 [(set (match_dup 4) (match_dup 1))
9093 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
9094 (clobber (reg:CC CC_REGNUM))])
9095 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
9096 (set (match_dup 3) (match_dup 4))
9097 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9098 (label_ref (match_dup 0))
9101 [(set_attr "op_type" "RIE")
9102 (set_attr "type" "branch")
9103 (set (attr "length")
9104 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9105 (const_int 6) (const_int 16)))])
9109 (define_insn_and_split "*brx_64bit"
9112 (match_operator 5 "s390_brx_operator"
9113 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9114 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
9115 (subreg:SI (match_dup 2) 12)])
9116 (label_ref (match_operand 0 "" ""))
9118 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9119 (plus:SI (match_dup 1)
9120 (subreg:SI (match_dup 2) 4)))
9121 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9122 (clobber (reg:CC CC_REGNUM))]
9125 if (which_alternative != 0)
9127 else if (get_attr_length (insn) == 6)
9128 return "brx%C5\t%1,%2,%l0";
9130 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9132 "&& reload_completed
9133 && (!REG_P (operands[3])
9134 || !rtx_equal_p (operands[1], operands[3]))"
9135 [(set (match_dup 4) (match_dup 1))
9136 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9137 (clobber (reg:CC CC_REGNUM))])
9138 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9139 (set (match_dup 3) (match_dup 4))
9140 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9141 (label_ref (match_dup 0))
9144 [(set_attr "op_type" "RSI")
9145 (set_attr "type" "branch")
9146 (set (attr "length")
9147 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9148 (const_int 6) (const_int 14)))])
9152 (define_insn_and_split "*brx_31bit"
9155 (match_operator 5 "s390_brx_operator"
9156 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9157 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9158 (subreg:SI (match_dup 2) 4)])
9159 (label_ref (match_operand 0 "" ""))
9161 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9162 (plus:SI (match_dup 1)
9163 (subreg:SI (match_dup 2) 0)))
9164 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9165 (clobber (reg:CC CC_REGNUM))]
9166 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9168 if (which_alternative != 0)
9170 else if (get_attr_length (insn) == 6)
9171 return "brx%C5\t%1,%2,%l0";
9173 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9175 "&& reload_completed
9176 && (!REG_P (operands[3])
9177 || !rtx_equal_p (operands[1], operands[3]))"
9178 [(set (match_dup 4) (match_dup 1))
9179 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9180 (clobber (reg:CC CC_REGNUM))])
9181 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9182 (set (match_dup 3) (match_dup 4))
9183 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9184 (label_ref (match_dup 0))
9187 [(set_attr "op_type" "RSI")
9188 (set_attr "type" "branch")
9189 (set (attr "length")
9190 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9191 (const_int 6) (const_int 14)))])
9196 (define_expand "doloop_end"
9197 [(use (match_operand 0 "" "")) ; loop pseudo
9198 (use (match_operand 1 "" ""))] ; label
9201 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9202 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9203 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9204 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9205 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9206 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9213 (define_insn_and_split "doloop_si64"
9216 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9218 (label_ref (match_operand 0 "" ""))
9220 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9221 (plus:SI (match_dup 1) (const_int -1)))
9222 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9223 (clobber (reg:CC CC_REGNUM))]
9226 if (which_alternative != 0)
9228 else if (get_attr_length (insn) == 4)
9229 return "brct\t%1,%l0";
9231 return "ahi\t%1,-1\;jgne\t%l0";
9233 "&& reload_completed
9234 && (! REG_P (operands[2])
9235 || ! rtx_equal_p (operands[1], operands[2]))"
9236 [(set (match_dup 3) (match_dup 1))
9237 (parallel [(set (reg:CCAN CC_REGNUM)
9238 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9240 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9241 (set (match_dup 2) (match_dup 3))
9242 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9243 (label_ref (match_dup 0))
9246 [(set_attr "op_type" "RI")
9247 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9248 ; hurt us in the (rare) case of ahi.
9249 (set_attr "z10prop" "z10_super_E1")
9250 (set_attr "type" "branch")
9251 (set (attr "length")
9252 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9253 (const_int 4) (const_int 10)))])
9255 (define_insn_and_split "doloop_si31"
9258 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9260 (label_ref (match_operand 0 "" ""))
9262 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9263 (plus:SI (match_dup 1) (const_int -1)))
9264 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9265 (clobber (reg:CC CC_REGNUM))]
9268 if (which_alternative != 0)
9270 else if (get_attr_length (insn) == 4)
9271 return "brct\t%1,%l0";
9275 "&& reload_completed
9276 && (! REG_P (operands[2])
9277 || ! rtx_equal_p (operands[1], operands[2]))"
9278 [(set (match_dup 3) (match_dup 1))
9279 (parallel [(set (reg:CCAN CC_REGNUM)
9280 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9282 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9283 (set (match_dup 2) (match_dup 3))
9284 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9285 (label_ref (match_dup 0))
9288 [(set_attr "op_type" "RI")
9289 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9290 ; hurt us in the (rare) case of ahi.
9291 (set_attr "z10prop" "z10_super_E1")
9292 (set_attr "type" "branch")
9293 (set (attr "length")
9294 (if_then_else (not (match_test "flag_pic"))
9295 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9296 (const_int 4) (const_int 6))
9297 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9298 (const_int 4) (const_int 8))))])
9300 (define_insn "*doloop_si_long"
9303 (ne (match_operand:SI 1 "register_operand" "d")
9305 (match_operand 0 "address_operand" "ZR")
9307 (set (match_operand:SI 2 "register_operand" "=1")
9308 (plus:SI (match_dup 1) (const_int -1)))
9309 (clobber (match_scratch:SI 3 "=X"))
9310 (clobber (reg:CC CC_REGNUM))]
9313 if (get_attr_op_type (insn) == OP_TYPE_RR)
9314 return "bctr\t%1,%0";
9316 return "bct\t%1,%a0";
9318 [(set (attr "op_type")
9319 (if_then_else (match_operand 0 "register_operand" "")
9320 (const_string "RR") (const_string "RX")))
9321 (set_attr "type" "branch")
9322 (set_attr "atype" "agen")
9323 (set_attr "z10prop" "z10_c")
9324 (set_attr "z196prop" "z196_cracked")])
9326 (define_insn_and_split "doloop_di"
9329 (ne (match_operand:DI 1 "register_operand" "d,d,d")
9331 (label_ref (match_operand 0 "" ""))
9333 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9334 (plus:DI (match_dup 1) (const_int -1)))
9335 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9336 (clobber (reg:CC CC_REGNUM))]
9339 if (which_alternative != 0)
9341 else if (get_attr_length (insn) == 4)
9342 return "brctg\t%1,%l0";
9344 return "aghi\t%1,-1\;jgne\t%l0";
9346 "&& reload_completed
9347 && (! REG_P (operands[2])
9348 || ! rtx_equal_p (operands[1], operands[2]))"
9349 [(set (match_dup 3) (match_dup 1))
9350 (parallel [(set (reg:CCAN CC_REGNUM)
9351 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9353 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9354 (set (match_dup 2) (match_dup 3))
9355 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9356 (label_ref (match_dup 0))
9359 [(set_attr "op_type" "RI")
9360 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9361 ; hurt us in the (rare) case of ahi.
9362 (set_attr "z10prop" "z10_super_E1")
9363 (set_attr "type" "branch")
9364 (set (attr "length")
9365 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9366 (const_int 4) (const_int 10)))])
9369 ;;- Unconditional jump instructions.
9373 ; jump instruction pattern(s).
9376 (define_expand "jump"
9377 [(match_operand 0 "" "")]
9379 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9381 (define_insn "*jump64"
9382 [(set (pc) (label_ref (match_operand 0 "" "")))]
9385 if (get_attr_length (insn) == 4)
9390 [(set_attr "op_type" "RI")
9391 (set_attr "type" "branch")
9392 (set (attr "length")
9393 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9394 (const_int 4) (const_int 6)))])
9396 (define_insn "*jump31"
9397 [(set (pc) (label_ref (match_operand 0 "" "")))]
9400 gcc_assert (get_attr_length (insn) == 4);
9403 [(set_attr "op_type" "RI")
9404 (set_attr "type" "branch")
9405 (set (attr "length")
9406 (if_then_else (not (match_test "flag_pic"))
9407 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9408 (const_int 4) (const_int 6))
9409 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9410 (const_int 4) (const_int 8))))])
9413 ; indirect-jump instruction pattern(s).
9416 (define_insn "indirect_jump"
9417 [(set (pc) (match_operand 0 "address_operand" "ZR"))]
9420 if (get_attr_op_type (insn) == OP_TYPE_RR)
9425 [(set (attr "op_type")
9426 (if_then_else (match_operand 0 "register_operand" "")
9427 (const_string "RR") (const_string "RX")))
9428 (set_attr "type" "branch")
9429 (set_attr "atype" "agen")])
9432 ; casesi instruction pattern(s).
9435 (define_insn "casesi_jump"
9436 [(set (pc) (match_operand 0 "address_operand" "ZR"))
9437 (use (label_ref (match_operand 1 "" "")))]
9440 if (get_attr_op_type (insn) == OP_TYPE_RR)
9445 [(set (attr "op_type")
9446 (if_then_else (match_operand 0 "register_operand" "")
9447 (const_string "RR") (const_string "RX")))
9448 (set_attr "type" "branch")
9449 (set_attr "atype" "agen")])
9451 (define_expand "casesi"
9452 [(match_operand:SI 0 "general_operand" "")
9453 (match_operand:SI 1 "general_operand" "")
9454 (match_operand:SI 2 "general_operand" "")
9455 (label_ref (match_operand 3 "" ""))
9456 (label_ref (match_operand 4 "" ""))]
9459 rtx index = gen_reg_rtx (SImode);
9460 rtx base = gen_reg_rtx (Pmode);
9461 rtx target = gen_reg_rtx (Pmode);
9463 emit_move_insn (index, operands[0]);
9464 emit_insn (gen_subsi3 (index, index, operands[1]));
9465 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9468 if (Pmode != SImode)
9469 index = convert_to_mode (Pmode, index, 1);
9470 if (GET_CODE (index) != REG)
9471 index = copy_to_mode_reg (Pmode, index);
9474 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9476 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9478 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9480 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9481 emit_move_insn (target, index);
9484 target = gen_rtx_PLUS (Pmode, base, target);
9485 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9492 ;;- Jump to subroutine.
9497 ; untyped call instruction pattern(s).
9500 ;; Call subroutine returning any type.
9501 (define_expand "untyped_call"
9502 [(parallel [(call (match_operand 0 "" "")
9504 (match_operand 1 "" "")
9505 (match_operand 2 "" "")])]
9510 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9512 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9514 rtx set = XVECEXP (operands[2], 0, i);
9515 emit_move_insn (SET_DEST (set), SET_SRC (set));
9518 /* The optimizer does not know that the call sets the function value
9519 registers we stored in the result block. We avoid problems by
9520 claiming that all hard registers are used and clobbered at this
9522 emit_insn (gen_blockage ());
9527 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9528 ;; all of memory. This blocks insns from being moved across this point.
9530 (define_insn "blockage"
9531 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9534 [(set_attr "type" "none")
9535 (set_attr "length" "0")])
9541 (define_expand "sibcall"
9542 [(call (match_operand 0 "" "")
9543 (match_operand 1 "" ""))]
9546 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9550 (define_insn "*sibcall_br"
9551 [(call (mem:QI (reg SIBCALL_REGNUM))
9552 (match_operand 0 "const_int_operand" "n"))]
9553 "SIBLING_CALL_P (insn)
9554 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9556 [(set_attr "op_type" "RR")
9557 (set_attr "type" "branch")
9558 (set_attr "atype" "agen")])
9560 (define_insn "*sibcall_brc"
9561 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9562 (match_operand 1 "const_int_operand" "n"))]
9563 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9565 [(set_attr "op_type" "RI")
9566 (set_attr "type" "branch")])
9568 (define_insn "*sibcall_brcl"
9569 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9570 (match_operand 1 "const_int_operand" "n"))]
9571 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9573 [(set_attr "op_type" "RIL")
9574 (set_attr "type" "branch")])
9577 ; sibcall_value patterns
9580 (define_expand "sibcall_value"
9581 [(set (match_operand 0 "" "")
9582 (call (match_operand 1 "" "")
9583 (match_operand 2 "" "")))]
9586 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9590 (define_insn "*sibcall_value_br"
9591 [(set (match_operand 0 "" "")
9592 (call (mem:QI (reg SIBCALL_REGNUM))
9593 (match_operand 1 "const_int_operand" "n")))]
9594 "SIBLING_CALL_P (insn)
9595 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9597 [(set_attr "op_type" "RR")
9598 (set_attr "type" "branch")
9599 (set_attr "atype" "agen")])
9601 (define_insn "*sibcall_value_brc"
9602 [(set (match_operand 0 "" "")
9603 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9604 (match_operand 2 "const_int_operand" "n")))]
9605 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9607 [(set_attr "op_type" "RI")
9608 (set_attr "type" "branch")])
9610 (define_insn "*sibcall_value_brcl"
9611 [(set (match_operand 0 "" "")
9612 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9613 (match_operand 2 "const_int_operand" "n")))]
9614 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9616 [(set_attr "op_type" "RIL")
9617 (set_attr "type" "branch")])
9621 ; call instruction pattern(s).
9624 (define_expand "call"
9625 [(call (match_operand 0 "" "")
9626 (match_operand 1 "" ""))
9627 (use (match_operand 2 "" ""))]
9630 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9631 gen_rtx_REG (Pmode, RETURN_REGNUM));
9635 (define_insn "*bras"
9636 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9637 (match_operand 1 "const_int_operand" "n"))
9638 (clobber (match_operand 2 "register_operand" "=r"))]
9639 "!SIBLING_CALL_P (insn)
9640 && TARGET_SMALL_EXEC
9641 && GET_MODE (operands[2]) == Pmode"
9643 [(set_attr "op_type" "RI")
9644 (set_attr "type" "jsr")
9645 (set_attr "z196prop" "z196_cracked")])
9647 (define_insn "*brasl"
9648 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9649 (match_operand 1 "const_int_operand" "n"))
9650 (clobber (match_operand 2 "register_operand" "=r"))]
9651 "!SIBLING_CALL_P (insn)
9653 && GET_MODE (operands[2]) == Pmode"
9655 [(set_attr "op_type" "RIL")
9656 (set_attr "type" "jsr")
9657 (set_attr "z196prop" "z196_cracked")])
9659 (define_insn "*basr"
9660 [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
9661 (match_operand 1 "const_int_operand" "n"))
9662 (clobber (match_operand 2 "register_operand" "=r"))]
9663 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9665 if (get_attr_op_type (insn) == OP_TYPE_RR)
9666 return "basr\t%2,%0";
9668 return "bas\t%2,%a0";
9670 [(set (attr "op_type")
9671 (if_then_else (match_operand 0 "register_operand" "")
9672 (const_string "RR") (const_string "RX")))
9673 (set_attr "type" "jsr")
9674 (set_attr "atype" "agen")
9675 (set_attr "z196prop" "z196_cracked")])
9678 ; call_value instruction pattern(s).
9681 (define_expand "call_value"
9682 [(set (match_operand 0 "" "")
9683 (call (match_operand 1 "" "")
9684 (match_operand 2 "" "")))
9685 (use (match_operand 3 "" ""))]
9688 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9689 gen_rtx_REG (Pmode, RETURN_REGNUM));
9693 (define_insn "*bras_r"
9694 [(set (match_operand 0 "" "")
9695 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9696 (match_operand:SI 2 "const_int_operand" "n")))
9697 (clobber (match_operand 3 "register_operand" "=r"))]
9698 "!SIBLING_CALL_P (insn)
9699 && TARGET_SMALL_EXEC
9700 && GET_MODE (operands[3]) == Pmode"
9702 [(set_attr "op_type" "RI")
9703 (set_attr "type" "jsr")
9704 (set_attr "z196prop" "z196_cracked")])
9706 (define_insn "*brasl_r"
9707 [(set (match_operand 0 "" "")
9708 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9709 (match_operand 2 "const_int_operand" "n")))
9710 (clobber (match_operand 3 "register_operand" "=r"))]
9711 "!SIBLING_CALL_P (insn)
9713 && GET_MODE (operands[3]) == Pmode"
9715 [(set_attr "op_type" "RIL")
9716 (set_attr "type" "jsr")
9717 (set_attr "z196prop" "z196_cracked")])
9719 (define_insn "*basr_r"
9720 [(set (match_operand 0 "" "")
9721 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9722 (match_operand 2 "const_int_operand" "n")))
9723 (clobber (match_operand 3 "register_operand" "=r"))]
9724 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9726 if (get_attr_op_type (insn) == OP_TYPE_RR)
9727 return "basr\t%3,%1";
9729 return "bas\t%3,%a1";
9731 [(set (attr "op_type")
9732 (if_then_else (match_operand 1 "register_operand" "")
9733 (const_string "RR") (const_string "RX")))
9734 (set_attr "type" "jsr")
9735 (set_attr "atype" "agen")
9736 (set_attr "z196prop" "z196_cracked")])
9739 ;;- Thread-local storage support.
9742 (define_expand "get_thread_pointer<mode>"
9743 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9747 (define_expand "set_thread_pointer<mode>"
9748 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9749 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9753 (define_insn "*set_tp"
9754 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9757 [(set_attr "type" "none")
9758 (set_attr "length" "0")])
9760 (define_insn "*tls_load_64"
9761 [(set (match_operand:DI 0 "register_operand" "=d")
9762 (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
9763 (match_operand:DI 2 "" "")]
9767 [(set_attr "op_type" "RXE")
9768 (set_attr "z10prop" "z10_fwd_A3")])
9770 (define_insn "*tls_load_31"
9771 [(set (match_operand:SI 0 "register_operand" "=d,d")
9772 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9773 (match_operand:SI 2 "" "")]
9779 [(set_attr "op_type" "RX,RXY")
9780 (set_attr "type" "load")
9781 (set_attr "cpu_facility" "*,longdisp")
9782 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9784 (define_insn "*bras_tls"
9785 [(set (match_operand 0 "" "")
9786 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9787 (match_operand 2 "const_int_operand" "n")))
9788 (clobber (match_operand 3 "register_operand" "=r"))
9789 (use (match_operand 4 "" ""))]
9790 "!SIBLING_CALL_P (insn)
9791 && TARGET_SMALL_EXEC
9792 && GET_MODE (operands[3]) == Pmode"
9794 [(set_attr "op_type" "RI")
9795 (set_attr "type" "jsr")
9796 (set_attr "z196prop" "z196_cracked")])
9798 (define_insn "*brasl_tls"
9799 [(set (match_operand 0 "" "")
9800 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9801 (match_operand 2 "const_int_operand" "n")))
9802 (clobber (match_operand 3 "register_operand" "=r"))
9803 (use (match_operand 4 "" ""))]
9804 "!SIBLING_CALL_P (insn)
9806 && GET_MODE (operands[3]) == Pmode"
9808 [(set_attr "op_type" "RIL")
9809 (set_attr "type" "jsr")
9810 (set_attr "z196prop" "z196_cracked")])
9812 (define_insn "*basr_tls"
9813 [(set (match_operand 0 "" "")
9814 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9815 (match_operand 2 "const_int_operand" "n")))
9816 (clobber (match_operand 3 "register_operand" "=r"))
9817 (use (match_operand 4 "" ""))]
9818 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9820 if (get_attr_op_type (insn) == OP_TYPE_RR)
9821 return "basr\t%3,%1%J4";
9823 return "bas\t%3,%a1%J4";
9825 [(set (attr "op_type")
9826 (if_then_else (match_operand 1 "register_operand" "")
9827 (const_string "RR") (const_string "RX")))
9828 (set_attr "type" "jsr")
9829 (set_attr "atype" "agen")
9830 (set_attr "z196prop" "z196_cracked")])
9833 ;;- Atomic operations
9837 ; memory barrier patterns.
9840 (define_expand "mem_signal_fence"
9841 [(match_operand:SI 0 "const_int_operand")] ;; model
9844 /* The s390 memory model is strong enough not to require any
9845 barrier in order to synchronize a thread with itself. */
9849 (define_expand "mem_thread_fence"
9850 [(match_operand:SI 0 "const_int_operand")] ;; model
9853 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9854 enough not to require barriers of any kind. */
9855 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9857 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9858 MEM_VOLATILE_P (mem) = 1;
9859 emit_insn (gen_mem_thread_fence_1 (mem));
9864 ; Although bcr is superscalar on Z10, this variant will never
9865 ; become part of an execution group.
9866 ; With z196 we can make use of the fast-BCR-serialization facility.
9867 ; This allows for a slightly faster sync which is sufficient for our
9869 (define_insn "mem_thread_fence_1"
9870 [(set (match_operand:BLK 0 "" "")
9871 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9879 [(set_attr "op_type" "RR")
9880 (set_attr "mnemonic" "bcr_flush")
9881 (set_attr "z196prop" "z196_alone")])
9884 ; atomic load/store operations
9887 ; Atomic loads need not examine the memory model at all.
9888 (define_expand "atomic_load<mode>"
9889 [(match_operand:DINT 0 "register_operand") ;; output
9890 (match_operand:DINT 1 "memory_operand") ;; memory
9891 (match_operand:SI 2 "const_int_operand")] ;; model
9894 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9897 if (<MODE>mode == TImode)
9898 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9899 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9900 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9902 emit_move_insn (operands[0], operands[1]);
9906 ; Different from movdi_31 in that we want no splitters.
9907 (define_insn "atomic_loaddi_1"
9908 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9909 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9917 [(set_attr "op_type" "RS,RSY,RS,RSY")
9918 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
9919 (set_attr "type" "lm,lm,floaddf,floaddf")])
9921 (define_insn "atomic_loadti_1"
9922 [(set (match_operand:TI 0 "register_operand" "=r")
9923 (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
9927 [(set_attr "op_type" "RXY")
9928 (set_attr "type" "other")])
9930 ; Atomic stores must(?) enforce sequential consistency.
9931 (define_expand "atomic_store<mode>"
9932 [(match_operand:DINT 0 "memory_operand") ;; memory
9933 (match_operand:DINT 1 "register_operand") ;; input
9934 (match_operand:SI 2 "const_int_operand")] ;; model
9937 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9939 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9942 if (<MODE>mode == TImode)
9943 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9944 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9945 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9947 emit_move_insn (operands[0], operands[1]);
9948 if (is_mm_seq_cst (model))
9949 emit_insn (gen_mem_thread_fence (operands[2]));
9953 ; Different from movdi_31 in that we want no splitters.
9954 (define_insn "atomic_storedi_1"
9955 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9956 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9964 [(set_attr "op_type" "RS,RSY,RS,RSY")
9965 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
9966 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9968 (define_insn "atomic_storeti_1"
9969 [(set (match_operand:TI 0 "memory_operand" "=T")
9970 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9974 [(set_attr "op_type" "RXY")
9975 (set_attr "type" "other")])
9978 ; compare and swap patterns.
9981 (define_expand "atomic_compare_and_swap<mode>"
9982 [(match_operand:SI 0 "register_operand") ;; bool success output
9983 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9984 (match_operand:DGPR 2 "memory_operand") ;; memory
9985 (match_operand:DGPR 3 "register_operand") ;; expected intput
9986 (match_operand:DGPR 4 "register_operand") ;; newval intput
9987 (match_operand:SI 5 "const_int_operand") ;; is_weak
9988 (match_operand:SI 6 "const_int_operand") ;; success model
9989 (match_operand:SI 7 "const_int_operand")] ;; failure model
9992 rtx cc, cmp, output = operands[1];
9994 if (!register_operand (output, <MODE>mode))
9995 output = gen_reg_rtx (<MODE>mode);
9997 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
10000 emit_insn (gen_atomic_compare_and_swap<mode>_internal
10001 (output, operands[2], operands[3], operands[4]));
10003 /* We deliberately accept non-register operands in the predicate
10004 to ensure the write back to the output operand happens *before*
10005 the store-flags code below. This makes it easier for combine
10006 to merge the store-flags code with a potential test-and-branch
10007 pattern following (immediately!) afterwards. */
10008 if (output != operands[1])
10009 emit_move_insn (operands[1], output);
10011 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
10012 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
10013 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
10017 (define_expand "atomic_compare_and_swap<mode>"
10018 [(match_operand:SI 0 "register_operand") ;; bool success output
10019 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
10020 (match_operand:HQI 2 "memory_operand") ;; memory
10021 (match_operand:HQI 3 "general_operand") ;; expected intput
10022 (match_operand:HQI 4 "general_operand") ;; newval intput
10023 (match_operand:SI 5 "const_int_operand") ;; is_weak
10024 (match_operand:SI 6 "const_int_operand") ;; success model
10025 (match_operand:SI 7 "const_int_operand")] ;; failure model
10028 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
10029 operands[3], operands[4], INTVAL (operands[5]));
10033 (define_expand "atomic_compare_and_swap<mode>_internal"
10035 [(set (match_operand:DGPR 0 "register_operand")
10036 (match_operand:DGPR 1 "memory_operand"))
10038 (unspec_volatile:DGPR
10040 (match_operand:DGPR 2 "register_operand")
10041 (match_operand:DGPR 3 "register_operand")]
10043 (set (reg:CCZ1 CC_REGNUM)
10044 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
10048 (define_insn "*atomic_compare_and_swap<mode>_1"
10049 [(set (match_operand:TDI 0 "register_operand" "=r")
10050 (match_operand:TDI 1 "memory_operand" "+S"))
10052 (unspec_volatile:TDI
10054 (match_operand:TDI 2 "register_operand" "0")
10055 (match_operand:TDI 3 "register_operand" "r")]
10057 (set (reg:CCZ1 CC_REGNUM)
10058 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10060 "c<td>sg\t%0,%3,%S1"
10061 [(set_attr "op_type" "RSY")
10062 (set_attr "type" "sem")])
10065 (define_insn "*atomic_compare_and_swapdi_2"
10066 [(set (match_operand:DI 0 "register_operand" "=r,r")
10067 (match_operand:DI 1 "memory_operand" "+Q,S"))
10069 (unspec_volatile:DI
10071 (match_operand:DI 2 "register_operand" "0,0")
10072 (match_operand:DI 3 "register_operand" "r,r")]
10074 (set (reg:CCZ1 CC_REGNUM)
10075 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10080 [(set_attr "op_type" "RS,RSY")
10081 (set_attr "cpu_facility" "*,longdisp")
10082 (set_attr "type" "sem")])
10085 (define_insn "*atomic_compare_and_swapsi_3"
10086 [(set (match_operand:SI 0 "register_operand" "=r,r")
10087 (match_operand:SI 1 "memory_operand" "+Q,S"))
10089 (unspec_volatile:SI
10091 (match_operand:SI 2 "register_operand" "0,0")
10092 (match_operand:SI 3 "register_operand" "r,r")]
10094 (set (reg:CCZ1 CC_REGNUM)
10095 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
10100 [(set_attr "op_type" "RS,RSY")
10101 (set_attr "cpu_facility" "*,longdisp")
10102 (set_attr "type" "sem")])
10105 ; Other atomic instruction patterns.
10108 ; z196 load and add, xor, or and and instructions
10110 (define_expand "atomic_fetch_<atomic><mode>"
10111 [(match_operand:GPR 0 "register_operand") ;; val out
10113 (match_operand:GPR 1 "memory_operand") ;; memory
10114 (match_operand:GPR 2 "register_operand")) ;; val in
10115 (match_operand:SI 3 "const_int_operand")] ;; model
10118 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10121 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
10122 (operands[0], operands[1], operands[2]));
10126 ; lan, lang, lao, laog, lax, laxg, laa, laag
10127 (define_insn "atomic_fetch_<atomic><mode>_iaf"
10128 [(set (match_operand:GPR 0 "register_operand" "=d")
10129 (match_operand:GPR 1 "memory_operand" "+S"))
10131 (unspec_volatile:GPR
10132 [(ATOMIC_Z196:GPR (match_dup 1)
10133 (match_operand:GPR 2 "general_operand" "d"))]
10134 UNSPECV_ATOMIC_OP))
10135 (clobber (reg:CC CC_REGNUM))]
10137 "la<noxa><g>\t%0,%2,%1"
10138 [(set_attr "op_type" "RSY")
10139 (set_attr "type" "sem")])
10141 ;; For SImode and larger, the optabs.c code will do just fine in
10142 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
10143 ;; better by expanding our own loop.
10145 (define_expand "atomic_<atomic><mode>"
10147 (match_operand:HQI 0 "memory_operand") ;; memory
10148 (match_operand:HQI 1 "general_operand")) ;; val in
10149 (match_operand:SI 2 "const_int_operand")] ;; model
10152 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10153 operands[1], false);
10157 (define_expand "atomic_fetch_<atomic><mode>"
10158 [(match_operand:HQI 0 "register_operand") ;; val out
10160 (match_operand:HQI 1 "memory_operand") ;; memory
10161 (match_operand:HQI 2 "general_operand")) ;; val in
10162 (match_operand:SI 3 "const_int_operand")] ;; model
10165 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10166 operands[2], false);
10170 (define_expand "atomic_<atomic>_fetch<mode>"
10171 [(match_operand:HQI 0 "register_operand") ;; val out
10173 (match_operand:HQI 1 "memory_operand") ;; memory
10174 (match_operand:HQI 2 "general_operand")) ;; val in
10175 (match_operand:SI 3 "const_int_operand")] ;; model
10178 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10179 operands[2], true);
10183 (define_expand "atomic_exchange<mode>"
10184 [(match_operand:HQI 0 "register_operand") ;; val out
10185 (match_operand:HQI 1 "memory_operand") ;; memory
10186 (match_operand:HQI 2 "general_operand") ;; val in
10187 (match_operand:SI 3 "const_int_operand")] ;; model
10190 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10191 operands[2], false);
10196 ;;- Miscellaneous instructions.
10200 ; allocate stack instruction pattern(s).
10203 (define_expand "allocate_stack"
10204 [(match_operand 0 "general_operand" "")
10205 (match_operand 1 "general_operand" "")]
10208 rtx temp = gen_reg_rtx (Pmode);
10210 emit_move_insn (temp, s390_back_chain_rtx ());
10211 anti_adjust_stack (operands[1]);
10212 emit_move_insn (s390_back_chain_rtx (), temp);
10214 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10220 ; setjmp instruction pattern.
10223 (define_expand "builtin_setjmp_receiver"
10224 [(match_operand 0 "" "")]
10227 emit_insn (s390_load_got ());
10228 emit_use (pic_offset_table_rtx);
10232 ;; These patterns say how to save and restore the stack pointer. We need not
10233 ;; save the stack pointer at function level since we are careful to
10234 ;; preserve the backchain. At block level, we have to restore the backchain
10235 ;; when we restore the stack pointer.
10237 ;; For nonlocal gotos, we must save both the stack pointer and its
10238 ;; backchain and restore both. Note that in the nonlocal case, the
10239 ;; save area is a memory location.
10241 (define_expand "save_stack_function"
10242 [(match_operand 0 "general_operand" "")
10243 (match_operand 1 "general_operand" "")]
10247 (define_expand "restore_stack_function"
10248 [(match_operand 0 "general_operand" "")
10249 (match_operand 1 "general_operand" "")]
10253 (define_expand "restore_stack_block"
10254 [(match_operand 0 "register_operand" "")
10255 (match_operand 1 "register_operand" "")]
10258 rtx temp = gen_reg_rtx (Pmode);
10260 emit_move_insn (temp, s390_back_chain_rtx ());
10261 emit_move_insn (operands[0], operands[1]);
10262 emit_move_insn (s390_back_chain_rtx (), temp);
10267 (define_expand "save_stack_nonlocal"
10268 [(match_operand 0 "memory_operand" "")
10269 (match_operand 1 "register_operand" "")]
10272 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10274 /* Copy the backchain to the first word, sp to the second and the
10275 literal pool base to the third. */
10277 rtx save_bc = adjust_address (operands[0], Pmode, 0);
10278 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10279 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10281 if (TARGET_BACKCHAIN)
10282 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10284 emit_move_insn (save_sp, operands[1]);
10285 emit_move_insn (save_bp, base);
10290 (define_expand "restore_stack_nonlocal"
10291 [(match_operand 0 "register_operand" "")
10292 (match_operand 1 "memory_operand" "")]
10295 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10296 rtx temp = NULL_RTX;
10298 /* Restore the backchain from the first word, sp from the second and the
10299 literal pool base from the third. */
10301 rtx save_bc = adjust_address (operands[1], Pmode, 0);
10302 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10303 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10305 if (TARGET_BACKCHAIN)
10306 temp = force_reg (Pmode, save_bc);
10308 emit_move_insn (base, save_bp);
10309 emit_move_insn (operands[0], save_sp);
10312 emit_move_insn (s390_back_chain_rtx (), temp);
10318 (define_expand "exception_receiver"
10322 s390_set_has_landing_pad_p (true);
10327 ; nop instruction pattern(s).
10334 [(set_attr "op_type" "RR")
10335 (set_attr "z10prop" "z10_fr_E1")])
10337 (define_insn "nop1"
10341 [(set_attr "op_type" "RR")])
10343 ;;- Undeletable nops (used for hotpatching)
10345 (define_insn "nop_2_byte"
10346 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10349 [(set_attr "op_type" "RR")])
10351 (define_insn "nop_4_byte"
10352 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10355 [(set_attr "op_type" "RX")])
10357 (define_insn "nop_6_byte"
10358 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10361 [(set_attr "op_type" "RIL")])
10365 ; Special literal pool access instruction pattern(s).
10368 (define_insn "*pool_entry"
10369 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10370 UNSPECV_POOL_ENTRY)]
10373 machine_mode mode = GET_MODE (PATTERN (insn));
10374 unsigned int align = GET_MODE_BITSIZE (mode);
10375 s390_output_pool_entry (operands[0], mode, align);
10378 [(set (attr "length")
10379 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10381 (define_insn "pool_align"
10382 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10383 UNSPECV_POOL_ALIGN)]
10386 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10388 (define_insn "pool_section_start"
10389 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10392 switch_to_section (targetm.asm_out.function_rodata_section
10393 (current_function_decl));
10396 [(set_attr "length" "0")])
10398 (define_insn "pool_section_end"
10399 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10402 switch_to_section (current_function_section ());
10405 [(set_attr "length" "0")])
10407 (define_insn "main_base_31_small"
10408 [(set (match_operand 0 "register_operand" "=a")
10409 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10410 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10412 [(set_attr "op_type" "RR")
10413 (set_attr "type" "la")
10414 (set_attr "z196prop" "z196_cracked")])
10416 (define_insn "main_base_31_large"
10417 [(set (match_operand 0 "register_operand" "=a")
10418 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10419 (set (pc) (label_ref (match_operand 2 "" "")))]
10420 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10422 [(set_attr "op_type" "RI")
10423 (set_attr "z196prop" "z196_cracked")])
10425 (define_insn "main_base_64"
10426 [(set (match_operand 0 "register_operand" "=a")
10427 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10428 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10430 [(set_attr "op_type" "RIL")
10431 (set_attr "type" "larl")
10432 (set_attr "z10prop" "z10_fwd_A1")])
10434 (define_insn "main_pool"
10435 [(set (match_operand 0 "register_operand" "=a")
10436 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10437 "GET_MODE (operands[0]) == Pmode"
10439 gcc_unreachable ();
10441 [(set (attr "type")
10442 (if_then_else (match_test "TARGET_CPU_ZARCH")
10443 (const_string "larl") (const_string "la")))])
10445 (define_insn "reload_base_31"
10446 [(set (match_operand 0 "register_operand" "=a")
10447 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10448 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10449 "basr\t%0,0\;la\t%0,%1-.(%0)"
10450 [(set_attr "length" "6")
10451 (set_attr "type" "la")
10452 (set_attr "z196prop" "z196_cracked")])
10454 (define_insn "reload_base_64"
10455 [(set (match_operand 0 "register_operand" "=a")
10456 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10457 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10459 [(set_attr "op_type" "RIL")
10460 (set_attr "type" "larl")
10461 (set_attr "z10prop" "z10_fwd_A1")])
10463 (define_insn "pool"
10464 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10467 gcc_unreachable ();
10469 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10472 ;; Insns related to generating the function prologue and epilogue.
10476 (define_expand "prologue"
10477 [(use (const_int 0))]
10479 "s390_emit_prologue (); DONE;")
10481 (define_expand "epilogue"
10482 [(use (const_int 1))]
10484 "s390_emit_epilogue (false); DONE;")
10486 (define_expand "sibcall_epilogue"
10487 [(use (const_int 0))]
10489 "s390_emit_epilogue (true); DONE;")
10491 ;; A direct return instruction, without using an epilogue.
10492 (define_insn "<code>"
10494 "s390_can_use_<code>_insn ()"
10496 [(set_attr "op_type" "RR")
10497 (set_attr "type" "jsr")
10498 (set_attr "atype" "agen")])
10500 (define_insn "*return"
10502 (use (match_operand 0 "register_operand" "a"))]
10503 "GET_MODE (operands[0]) == Pmode"
10505 [(set_attr "op_type" "RR")
10506 (set_attr "type" "jsr")
10507 (set_attr "atype" "agen")])
10510 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10511 ;; pointer. This is used for compatibility.
10513 (define_expand "ptr_extend"
10514 [(set (match_operand:DI 0 "register_operand" "=r")
10515 (match_operand:SI 1 "register_operand" "r"))]
10518 emit_insn (gen_anddi3 (operands[0],
10519 gen_lowpart (DImode, operands[1]),
10520 GEN_INT (0x7fffffff)));
10524 ;; Instruction definition to expand eh_return macro to support
10525 ;; swapping in special linkage return addresses.
10527 (define_expand "eh_return"
10528 [(use (match_operand 0 "register_operand" ""))]
10531 s390_emit_tpf_eh_return (operands[0]);
10536 ; Stack Protector Patterns
10539 (define_expand "stack_protect_set"
10540 [(set (match_operand 0 "memory_operand" "")
10541 (match_operand 1 "memory_operand" ""))]
10544 #ifdef TARGET_THREAD_SSP_OFFSET
10546 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10547 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10550 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10552 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10557 (define_insn "stack_protect_set<mode>"
10558 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10559 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10561 "mvc\t%O0(%G0,%R0),%S1"
10562 [(set_attr "op_type" "SS")])
10564 (define_expand "stack_protect_test"
10565 [(set (reg:CC CC_REGNUM)
10566 (compare (match_operand 0 "memory_operand" "")
10567 (match_operand 1 "memory_operand" "")))
10568 (match_operand 2 "" "")]
10572 #ifdef TARGET_THREAD_SSP_OFFSET
10574 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10575 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10578 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10580 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10582 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10583 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10584 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10588 (define_insn "stack_protect_test<mode>"
10589 [(set (reg:CCZ CC_REGNUM)
10590 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10591 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10593 "clc\t%O0(%G0,%R0),%S1"
10594 [(set_attr "op_type" "SS")])
10596 ; This is used in s390_emit_prologue in order to prevent insns
10597 ; adjusting the stack pointer to be moved over insns writing stack
10598 ; slots using a copy of the stack pointer in a different register.
10599 (define_insn "stack_tie"
10600 [(set (match_operand:BLK 0 "memory_operand" "+m")
10601 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10604 [(set_attr "length" "0")])
10607 (define_insn "stack_restore_from_fpr"
10608 [(set (reg:DI STACK_REGNUM)
10609 (match_operand:DI 0 "register_operand" "f"))
10610 (clobber (mem:BLK (scratch)))]
10613 [(set_attr "op_type" "RRE")])
10616 ; Data prefetch patterns
10619 (define_insn "prefetch"
10620 [(prefetch (match_operand 0 "address_operand" "ZT,X")
10621 (match_operand:SI 1 "const_int_operand" " n,n")
10622 (match_operand:SI 2 "const_int_operand" " n,n"))]
10625 switch (which_alternative)
10628 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10630 if (larl_operand (operands[0], Pmode))
10631 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10635 /* This might be reached for symbolic operands with an odd
10636 addend. We simply omit the prefetch for such rare cases. */
10641 [(set_attr "type" "load,larl")
10642 (set_attr "op_type" "RXY,RIL")
10643 (set_attr "z10prop" "z10_super")
10644 (set_attr "z196prop" "z196_alone")])
10648 ; Byte swap instructions
10651 ; FIXME: There is also mvcin but we cannot use it since src and target
10653 (define_insn "bswap<mode>2"
10654 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
10655 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
10661 [(set_attr "type" "*,load,store")
10662 (set_attr "op_type" "RRE,RXY,RXY")
10663 (set_attr "z10prop" "z10_super")])
10665 (define_insn "bswaphi2"
10666 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
10667 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
10673 [(set_attr "type" "*,load,store")
10674 (set_attr "op_type" "RRE,RXY,RXY")
10675 (set_attr "z10prop" "z10_super")])
10678 [(set (match_operand:HI 0 "register_operand" "")
10679 (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10681 [(set (match_dup 2) (bswap:SI (match_dup 3)))
10682 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10684 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10685 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10690 ; Population count instruction
10693 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10694 ; portions and stores the result in the corresponding bytes in op0.
10695 (define_insn "*popcount<mode>"
10696 [(set (match_operand:INT 0 "register_operand" "=d")
10697 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10698 (clobber (reg:CC CC_REGNUM))]
10701 [(set_attr "op_type" "RRE")])
10703 (define_expand "popcountdi2"
10705 (parallel [(set (match_operand:DI 0 "register_operand" "")
10706 (unspec:DI [(match_operand:DI 1 "register_operand")]
10708 (clobber (reg:CC CC_REGNUM))])
10709 ; sllg op2, op0, 32
10710 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10712 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10713 (clobber (reg:CC CC_REGNUM))])
10714 ; sllg op2, op0, 16
10716 (ashift:DI (match_dup 0) (const_int 16)))
10718 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10719 (clobber (reg:CC CC_REGNUM))])
10721 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10723 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10724 (clobber (reg:CC CC_REGNUM))])
10725 ; srlg op0, op0, 56
10726 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10727 "TARGET_Z196 && TARGET_64BIT"
10728 "operands[2] = gen_reg_rtx (DImode);")
10730 (define_expand "popcountsi2"
10732 (parallel [(set (match_operand:SI 0 "register_operand" "")
10733 (unspec:SI [(match_operand:SI 1 "register_operand")]
10735 (clobber (reg:CC CC_REGNUM))])
10736 ; sllk op2, op0, 16
10738 (ashift:SI (match_dup 0) (const_int 16)))
10740 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10741 (clobber (reg:CC CC_REGNUM))])
10743 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10745 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10746 (clobber (reg:CC CC_REGNUM))])
10748 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10750 "operands[2] = gen_reg_rtx (SImode);")
10752 (define_expand "popcounthi2"
10754 (parallel [(set (match_operand:HI 0 "register_operand" "")
10755 (unspec:HI [(match_operand:HI 1 "register_operand")]
10757 (clobber (reg:CC CC_REGNUM))])
10760 (ashift:SI (match_dup 0) (const_int 8)))
10762 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10763 (clobber (reg:CC CC_REGNUM))])
10765 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10767 "operands[2] = gen_reg_rtx (SImode);")
10769 (define_expand "popcountqi2"
10771 (parallel [(set (match_operand:QI 0 "register_operand" "")
10772 (unspec:QI [(match_operand:QI 1 "register_operand")]
10774 (clobber (reg:CC CC_REGNUM))])]
10779 ;;- Copy sign instructions
10782 (define_insn "copysign<mode>3"
10783 [(set (match_operand:FP 0 "register_operand" "=f")
10784 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10785 (match_operand:FP 2 "register_operand" "f")]
10789 [(set_attr "op_type" "RRF")
10790 (set_attr "type" "fsimp<mode>")])
10794 ;;- Transactional execution instructions
10797 ; This splitter helps combine to make use of CC directly when
10798 ; comparing the integer result of a tbegin builtin with a constant.
10799 ; The unspec is already removed by canonicalize_comparison. So this
10800 ; splitters only job is to turn the PARALLEL into separate insns
10801 ; again. Unfortunately this only works with the very first cc/int
10802 ; compare since combine is not able to deal with data flow across
10803 ; basic block boundaries.
10805 ; It needs to be an insn pattern as well since combine does not apply
10806 ; the splitter directly. Combine would only use it if it actually
10807 ; would reduce the number of instructions.
10808 (define_insn_and_split "*ccraw_to_int"
10811 (match_operator 0 "s390_eqne_operator"
10812 [(reg:CCRAW CC_REGNUM)
10813 (match_operand 1 "const_int_operand" "")])
10814 (label_ref (match_operand 2 "" ""))
10816 (set (match_operand:SI 3 "register_operand" "=d")
10817 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10821 [(set (match_dup 3)
10822 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10824 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10825 (label_ref (match_dup 2))
10829 ; Non-constrained transaction begin
10831 (define_expand "tbegin"
10832 [(match_operand:SI 0 "register_operand" "")
10833 (match_operand:BLK 1 "memory_operand" "")]
10836 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10840 (define_expand "tbegin_nofloat"
10841 [(match_operand:SI 0 "register_operand" "")
10842 (match_operand:BLK 1 "memory_operand" "")]
10845 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10849 (define_expand "tbegin_retry"
10850 [(match_operand:SI 0 "register_operand" "")
10851 (match_operand:BLK 1 "memory_operand" "")
10852 (match_operand:SI 2 "general_operand" "")]
10855 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10859 (define_expand "tbegin_retry_nofloat"
10860 [(match_operand:SI 0 "register_operand" "")
10861 (match_operand:BLK 1 "memory_operand" "")
10862 (match_operand:SI 2 "general_operand" "")]
10865 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10869 ; Clobber VRs since they don't get restored
10870 (define_insn "tbegin_1_z13"
10871 [(set (reg:CCRAW CC_REGNUM)
10872 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10874 (set (match_operand:BLK 1 "memory_operand" "=Q")
10875 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10876 (clobber (reg:TI 16)) (clobber (reg:TI 38))
10877 (clobber (reg:TI 17)) (clobber (reg:TI 39))
10878 (clobber (reg:TI 18)) (clobber (reg:TI 40))
10879 (clobber (reg:TI 19)) (clobber (reg:TI 41))
10880 (clobber (reg:TI 20)) (clobber (reg:TI 42))
10881 (clobber (reg:TI 21)) (clobber (reg:TI 43))
10882 (clobber (reg:TI 22)) (clobber (reg:TI 44))
10883 (clobber (reg:TI 23)) (clobber (reg:TI 45))
10884 (clobber (reg:TI 24)) (clobber (reg:TI 46))
10885 (clobber (reg:TI 25)) (clobber (reg:TI 47))
10886 (clobber (reg:TI 26)) (clobber (reg:TI 48))
10887 (clobber (reg:TI 27)) (clobber (reg:TI 49))
10888 (clobber (reg:TI 28)) (clobber (reg:TI 50))
10889 (clobber (reg:TI 29)) (clobber (reg:TI 51))
10890 (clobber (reg:TI 30)) (clobber (reg:TI 52))
10891 (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10892 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10893 ; not supposed to be used for immediates (see genpreds.c).
10894 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10896 [(set_attr "op_type" "SIL")])
10898 (define_insn "tbegin_1"
10899 [(set (reg:CCRAW CC_REGNUM)
10900 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10902 (set (match_operand:BLK 1 "memory_operand" "=Q")
10903 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10904 (clobber (reg:DF 16))
10905 (clobber (reg:DF 17))
10906 (clobber (reg:DF 18))
10907 (clobber (reg:DF 19))
10908 (clobber (reg:DF 20))
10909 (clobber (reg:DF 21))
10910 (clobber (reg:DF 22))
10911 (clobber (reg:DF 23))
10912 (clobber (reg:DF 24))
10913 (clobber (reg:DF 25))
10914 (clobber (reg:DF 26))
10915 (clobber (reg:DF 27))
10916 (clobber (reg:DF 28))
10917 (clobber (reg:DF 29))
10918 (clobber (reg:DF 30))
10919 (clobber (reg:DF 31))]
10920 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10921 ; not supposed to be used for immediates (see genpreds.c).
10922 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10924 [(set_attr "op_type" "SIL")])
10926 ; Same as above but without the FPR clobbers
10927 (define_insn "tbegin_nofloat_1"
10928 [(set (reg:CCRAW CC_REGNUM)
10929 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10931 (set (match_operand:BLK 1 "memory_operand" "=Q")
10932 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10933 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10935 [(set_attr "op_type" "SIL")])
10938 ; Constrained transaction begin
10940 (define_expand "tbeginc"
10941 [(set (reg:CCRAW CC_REGNUM)
10942 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10947 (define_insn "*tbeginc_1"
10948 [(set (reg:CCRAW CC_REGNUM)
10949 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10951 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10953 [(set_attr "op_type" "SIL")])
10957 (define_expand "tend"
10958 [(set (reg:CCRAW CC_REGNUM)
10959 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10960 (set (match_operand:SI 0 "register_operand" "")
10961 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10965 (define_insn "*tend_1"
10966 [(set (reg:CCRAW CC_REGNUM)
10967 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10970 [(set_attr "op_type" "S")])
10972 ; Transaction abort
10974 (define_expand "tabort"
10975 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
10977 "TARGET_HTM && operands != NULL"
10979 if (CONST_INT_P (operands[0])
10980 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10982 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10983 ". Values in range 0 through 255 are reserved.",
10984 INTVAL (operands[0]));
10989 (define_insn "*tabort_1"
10990 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
10992 "TARGET_HTM && operands != NULL"
10994 [(set_attr "op_type" "S")])
10996 (define_insn "*tabort_1_plus"
10997 [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a")
10998 (match_operand:SI 1 "const_int_operand" "J"))]
11000 "TARGET_HTM && operands != NULL
11001 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
11003 [(set_attr "op_type" "S")])
11005 ; Transaction extract nesting depth
11007 (define_insn "etnd"
11008 [(set (match_operand:SI 0 "register_operand" "=d")
11009 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
11012 [(set_attr "op_type" "RRE")])
11014 ; Non-transactional store
11016 (define_insn "ntstg"
11017 [(set (match_operand:DI 0 "memory_operand" "=T")
11018 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
11022 [(set_attr "op_type" "RXY")])
11024 ; Transaction perform processor assist
11026 (define_expand "tx_assist"
11027 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
11028 (reg:SI GPR0_REGNUM)
11034 (define_insn "*ppa"
11035 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
11036 (match_operand:SI 1 "register_operand" "d")
11037 (match_operand 2 "const_int_operand" "I")]
11039 "TARGET_HTM && INTVAL (operands[2]) < 16"
11041 [(set_attr "op_type" "RRF")])
11044 ; Set and get floating point control register
11046 (define_insn "sfpc"
11047 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
11049 "TARGET_HARD_FLOAT"
11052 (define_insn "efpc"
11053 [(set (match_operand:SI 0 "register_operand" "=d")
11054 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
11055 "TARGET_HARD_FLOAT"
11059 ; Load count to block boundary
11061 (define_insn "lcbb"
11062 [(set (match_operand:SI 0 "register_operand" "=d")
11063 (unspec:SI [(match_operand 1 "address_operand" "ZR")
11064 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
11065 (clobber (reg:CC CC_REGNUM))]
11068 [(set_attr "op_type" "VRX")])
11070 ; Handle -fsplit-stack.
11072 (define_expand "split_stack_prologue"
11076 s390_expand_split_stack_prologue ();
11080 ;; If there are operand 0 bytes available on the stack, jump to
11083 (define_expand "split_stack_space_check"
11084 [(set (pc) (if_then_else
11085 (ltu (minus (reg 15)
11086 (match_operand 0 "register_operand"))
11087 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
11088 (label_ref (match_operand 1))
11092 /* Offset from thread pointer to __private_ss. */
11093 int psso = TARGET_64BIT ? 0x38 : 0x20;
11094 rtx tp = s390_get_thread_pointer ();
11095 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
11096 rtx reg = gen_reg_rtx (Pmode);
11099 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
11101 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
11102 cc = s390_emit_compare (GT, reg, guard);
11103 s390_emit_jump (operands[1], cc);
11108 ;; __morestack parameter block for split stack prologue. Parameters are:
11109 ;; parameter block label, label to be called by __morestack, frame size,
11110 ;; stack parameter size.
11112 (define_insn "split_stack_data"
11113 [(unspec_volatile [(match_operand 0 "" "X")
11114 (match_operand 1 "" "X")
11115 (match_operand 2 "const_int_operand" "X")
11116 (match_operand 3 "const_int_operand" "X")]
11117 UNSPECV_SPLIT_STACK_DATA)]
11120 switch_to_section (targetm.asm_out.function_rodata_section
11121 (current_function_decl));
11124 output_asm_insn (".align\t8", operands);
11126 output_asm_insn (".align\t4", operands);
11127 (*targetm.asm_out.internal_label) (asm_out_file, "L",
11128 CODE_LABEL_NUMBER (operands[0]));
11131 output_asm_insn (".quad\t%2", operands);
11132 output_asm_insn (".quad\t%3", operands);
11133 output_asm_insn (".quad\t%1-%0", operands);
11137 output_asm_insn (".long\t%2", operands);
11138 output_asm_insn (".long\t%3", operands);
11139 output_asm_insn (".long\t%1-%0", operands);
11142 switch_to_section (current_function_section ());
11145 [(set_attr "length" "0")])
11148 ;; A jg with minimal fuss for use in split stack prologue.
11150 (define_expand "split_stack_call"
11151 [(match_operand 0 "bras_sym_operand" "X")
11152 (match_operand 1 "" "")]
11156 emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11158 emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11162 (define_insn "split_stack_call_<mode>"
11163 [(set (pc) (label_ref (match_operand 1 "" "")))
11164 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11166 UNSPECV_SPLIT_STACK_CALL))]
11169 [(set_attr "op_type" "RIL")
11170 (set_attr "type" "branch")])
11172 ;; Also a conditional one.
11174 (define_expand "split_stack_cond_call"
11175 [(match_operand 0 "bras_sym_operand" "X")
11176 (match_operand 1 "" "")
11177 (match_operand 2 "" "")]
11181 emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11183 emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11187 (define_insn "split_stack_cond_call_<mode>"
11190 (match_operand 1 "" "")
11191 (label_ref (match_operand 2 "" ""))
11193 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11195 UNSPECV_SPLIT_STACK_CALL))]
11198 [(set_attr "op_type" "RIL")
11199 (set_attr "type" "branch")])