1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; GOT/PLT and lt-relative accesses
94 ; TLS relocation specifiers
110 ; Stack Smashing Protector
114 ; Test Data Class (TDC)
123 ;; UNSPEC_VOLATILE usage
126 (define_c_enum "unspecv" [
148 ; Transactional Execution support
162 ; Registers with special meaning
166 ; Sibling call register.
168 ; Literal pool base register.
170 ; Return address register.
172 ; Condition code register.
174 ; Thread local storage pointer register.
178 ; Hardware register names
182 ; General purpose registers
184 ; Floating point registers.
204 ;; PFPO GPR0 argument format
209 ; PFPO operation type
210 (PFPO_CONVERT 0x1000000)
212 (PFPO_OP_TYPE_SF 0x5)
213 (PFPO_OP_TYPE_DF 0x6)
214 (PFPO_OP_TYPE_TF 0x7)
215 (PFPO_OP_TYPE_SD 0x8)
216 (PFPO_OP_TYPE_DD 0x9)
217 (PFPO_OP_TYPE_TD 0xa)
218 ; Bitposition of operand types
219 (PFPO_OP0_TYPE_SHIFT 16)
220 (PFPO_OP1_TYPE_SHIFT 8)
223 ; Immediate operands for tbegin and tbeginc
224 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
225 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
227 ;; Instruction operand type as used in the Principles of Operation.
228 ;; Used to determine defaults for length and other attribute values.
230 (define_attr "op_type"
231 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
234 ;; Instruction type attribute used for scheduling.
236 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
237 cs,vs,store,sem,idiv,
238 imulhi,imulsi,imuldi,
239 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
240 floadtf,floaddf,floadsf,fstoredf,fstoresf,
241 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
242 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
244 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
245 itoftf, itofdf, itofsf, itofdd, itoftd,
246 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
247 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
249 (cond [(eq_attr "op_type" "NN") (const_string "other")
250 (eq_attr "op_type" "SS") (const_string "cs")]
251 (const_string "integer")))
253 ;; Another attribute used for scheduling purposes:
254 ;; agen: Instruction uses the address generation unit
255 ;; reg: Instruction does not use the agen unit
257 (define_attr "atype" "agen,reg"
258 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
260 (const_string "agen")))
262 ;; Properties concerning Z10 execution grouping and value forwarding.
263 ;; z10_super: instruction is superscalar.
264 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
265 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
266 ;; target register. It can forward this value to a second instruction that reads
267 ;; the same register if that second instruction is issued in the same group.
268 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
269 ;; instruction in the S pipe writes to the register, then the T instruction
270 ;; can immediately read the new value.
271 ;; z10_fr: union of Z10_fwd and z10_rec.
272 ;; z10_c: second operand of instruction is a register and read with complemented bits.
274 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
277 (define_attr "z10prop" "none,
278 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
279 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
281 z10_fr, z10_fr_A3, z10_fr_E1,
283 (const_string "none"))
285 ;; Properties concerning Z196 decoding
286 ;; z196_alone: must group alone
287 ;; z196_end: ends a group
288 ;; z196_cracked: instruction is cracked or expanded
289 (define_attr "z196prop" "none,
290 z196_alone, z196_ends,
292 (const_string "none"))
294 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
298 (define_attr "length" ""
299 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
300 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
304 ;; Processor type. This attribute must exactly match the processor_type
305 ;; enumeration in s390.h. The current machine description does not
306 ;; distinguish between g5 and g6, but there are differences between the two
307 ;; CPUs could in theory be modeled.
309 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
310 (const (symbol_ref "s390_tune_attr")))
312 (define_attr "cpu_facility"
313 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12"
314 (const_string "standard"))
316 (define_attr "enabled" ""
317 (cond [(eq_attr "cpu_facility" "standard")
320 (and (eq_attr "cpu_facility" "ieee")
321 (match_test "TARGET_CPU_IEEE_FLOAT"))
324 (and (eq_attr "cpu_facility" "zarch")
325 (match_test "TARGET_ZARCH"))
328 (and (eq_attr "cpu_facility" "longdisp")
329 (match_test "TARGET_LONG_DISPLACEMENT"))
332 (and (eq_attr "cpu_facility" "extimm")
333 (match_test "TARGET_EXTIMM"))
336 (and (eq_attr "cpu_facility" "dfp")
337 (match_test "TARGET_DFP"))
340 (and (eq_attr "cpu_facility" "cpu_zarch")
341 (match_test "TARGET_CPU_ZARCH"))
344 (and (eq_attr "cpu_facility" "z10")
345 (match_test "TARGET_Z10"))
348 (and (eq_attr "cpu_facility" "z196")
349 (match_test "TARGET_Z196"))
352 (and (eq_attr "cpu_facility" "zEC12")
353 (match_test "TARGET_ZEC12"))
357 ;; Pipeline description for z900. For lack of anything better,
358 ;; this description is also used for the g5 and g6.
361 ;; Pipeline description for z990, z9-109 and z9-ec.
364 ;; Pipeline description for z10
367 ;; Pipeline description for z196
370 ;; Pipeline description for zEC12
374 (include "predicates.md")
376 ;; Constraint definitions
377 (include "constraints.md")
384 ;; These mode iterators allow floating point patterns to be generated from the
386 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
387 (SD "TARGET_HARD_DFP")])
388 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
389 (define_mode_iterator FPALL [TF DF SF TD DD SD])
390 (define_mode_iterator BFP [TF DF SF])
391 (define_mode_iterator DFP [TD DD])
392 (define_mode_iterator DFP_ALL [TD DD SD])
393 (define_mode_iterator DSF [DF SF])
394 (define_mode_iterator SD_SF [SF SD])
395 (define_mode_iterator DD_DF [DF DD])
396 (define_mode_iterator TD_TF [TF TD])
398 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
399 ;; from the same template.
400 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
401 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
402 (define_mode_iterator DSI [DI SI])
403 (define_mode_iterator TDI [TI DI])
405 ;; These mode iterators allow :P to be used for patterns that operate on
406 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
407 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
409 ;; These macros refer to the actual word_mode of the configuration.
410 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
411 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
412 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
414 ;; Used by the umul pattern to express modes having half the size.
415 (define_mode_attr DWH [(TI "DI") (DI "SI")])
416 (define_mode_attr dwh [(TI "di") (DI "si")])
418 ;; This mode iterator allows the QI and HI patterns to be defined from
419 ;; the same template.
420 (define_mode_iterator HQI [HI QI])
422 ;; This mode iterator allows the integer patterns to be defined from the
424 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
425 (define_mode_iterator INTALL [TI DI SI HI QI])
426 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
428 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
429 ;; the same template.
430 (define_code_iterator SHIFT [ashift lshiftrt])
432 ;; This iterator allow r[ox]sbg to be defined with the same template
433 (define_code_iterator IXOR [ior xor])
435 ;; This iterator and attribute allow to combine most atomic operations.
436 (define_code_iterator ATOMIC [and ior xor plus minus mult])
437 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
438 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
439 (plus "add") (minus "sub") (mult "nand")])
440 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
442 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
443 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
444 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
446 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
447 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
449 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
451 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
452 ;; Likewise for "<RXe>".
453 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
454 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
456 ;; The decimal floating point variants of add, sub, div and mul support 3
457 ;; fp register operands. The following attributes allow to merge the bfp and
458 ;; dfp variants in a single insn definition.
460 ;; This attribute is used to set op_type accordingly.
461 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
462 (DD "RRR") (SD "RRR")])
464 ;; This attribute is used in the operand constraint list in order to have the
465 ;; first and the second operand match for bfp modes.
466 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
468 ;; This attribute is used in the operand list of the instruction to have an
469 ;; additional operand for the dfp instructions.
470 (define_mode_attr op1 [(TF "") (DF "") (SF "")
471 (TD "%1,") (DD "%1,") (SD "%1,")])
474 ;; This attribute is used in the operand constraint list
475 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
476 ;; TFmode values are represented by a fp register pair. Since the
477 ;; sign bit instructions only handle single source and target fp registers
478 ;; these instructions can only be used for TFmode values if the source and
479 ;; target operand uses the same fp register.
480 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
482 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
483 ;; This is used to disable the memory alternative in TFmode patterns.
484 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
486 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
487 ;; within instruction mnemonics.
488 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
490 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
491 ;; modes and to an empty string for bfp modes.
492 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
494 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
495 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
496 ;; version only operates on one register.
497 (define_mode_attr d0 [(DI "d") (SI "0")])
499 ;; In combination with d0 this allows to combine instructions of which the 31bit
500 ;; version only operates on one register. The DImode version needs an additional
501 ;; register for the assembler output.
502 (define_mode_attr 1 [(DI "%1,") (SI "")])
504 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
505 ;; 'ashift' and "srdl" in 'lshiftrt'.
506 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
508 ;; In SHIFT templates, this attribute holds the correct standard name for the
509 ;; pattern itself and the corresponding function calls.
510 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
512 ;; This attribute handles differences in the instruction 'type' and will result
513 ;; in "RRE" for DImode and "RR" for SImode.
514 (define_mode_attr E [(DI "E") (SI "")])
516 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
517 ;; to result in "RXY" for DImode and "RX" for SImode.
518 (define_mode_attr Y [(DI "Y") (SI "")])
520 ;; This attribute handles differences in the instruction 'type' and will result
521 ;; in "RSE" for TImode and "RS" for DImode.
522 (define_mode_attr TE [(TI "E") (DI "")])
524 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
525 ;; and "lcr" in SImode.
526 (define_mode_attr g [(DI "g") (SI "")])
528 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
529 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
530 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
531 ;; variant for long displacements.
532 (define_mode_attr y [(DI "g") (SI "y")])
534 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
535 ;; and "cds" in DImode.
536 (define_mode_attr tg [(TI "g") (DI "")])
538 ;; In TDI templates, a string like "c<d>sg".
539 (define_mode_attr td [(TI "d") (DI "")])
541 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
542 ;; and "cfdbr" in SImode.
543 (define_mode_attr gf [(DI "g") (SI "f")])
545 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
546 ;; and sllk for SI. This way it is possible to merge the new z196 SI
547 ;; 3 operands shift instructions into the existing patterns.
548 (define_mode_attr gk [(DI "g") (SI "k")])
550 ;; ICM mask required to load MODE value into the lowest subreg
551 ;; of a SImode register.
552 (define_mode_attr icm_lo [(HI "3") (QI "1")])
554 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
555 ;; HImode and "llgc" in QImode.
556 (define_mode_attr hc [(HI "h") (QI "c")])
558 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
560 (define_mode_attr DBL [(DI "TI") (SI "DI")])
562 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
563 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
564 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
566 ;; Maximum unsigned integer that fits in MODE.
567 (define_mode_attr max_uint [(HI "65535") (QI "255")])
569 ;; Start and end field computations for RISBG et al.
570 (define_mode_attr bfstart [(DI "s") (SI "t")])
571 (define_mode_attr bfend [(DI "e") (SI "f")])
573 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
574 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
577 ;;- Compare instructions.
580 ; Test-under-Mask instructions
582 (define_insn "*tmqi_mem"
583 [(set (reg CC_REGNUM)
584 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
585 (match_operand:QI 1 "immediate_operand" "n,n"))
586 (match_operand:QI 2 "immediate_operand" "n,n")))]
587 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
591 [(set_attr "op_type" "SI,SIY")
592 (set_attr "z10prop" "z10_super,z10_super")])
594 (define_insn "*tmdi_reg"
595 [(set (reg CC_REGNUM)
596 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
597 (match_operand:DI 1 "immediate_operand"
598 "N0HD0,N1HD0,N2HD0,N3HD0"))
599 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
601 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
602 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
608 [(set_attr "op_type" "RI")
609 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
611 (define_insn "*tmsi_reg"
612 [(set (reg CC_REGNUM)
613 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
614 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
615 (match_operand:SI 2 "immediate_operand" "n,n")))]
616 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
617 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
621 [(set_attr "op_type" "RI")
622 (set_attr "z10prop" "z10_super,z10_super")])
624 (define_insn "*tm<mode>_full"
625 [(set (reg CC_REGNUM)
626 (compare (match_operand:HQI 0 "register_operand" "d")
627 (match_operand:HQI 1 "immediate_operand" "n")))]
628 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
630 [(set_attr "op_type" "RI")
631 (set_attr "z10prop" "z10_super")])
635 ; Load-and-Test instructions
638 ; tst(di|si) instruction pattern(s).
640 (define_insn "*tstdi_sign"
641 [(set (reg CC_REGNUM)
645 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
646 (const_int 32)) (const_int 32))
647 (match_operand:DI 1 "const0_operand" "")))
648 (set (match_operand:DI 2 "register_operand" "=d,d")
649 (sign_extend:DI (match_dup 0)))]
650 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
653 [(set_attr "op_type" "RRE,RXY")
654 (set_attr "cpu_facility" "*,z10")
655 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
658 (define_insn "*tst<mode>_extimm"
659 [(set (reg CC_REGNUM)
660 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
661 (match_operand:GPR 1 "const0_operand" "")))
662 (set (match_operand:GPR 2 "register_operand" "=d,d")
664 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
668 [(set_attr "op_type" "RR<E>,RXY")
669 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
672 (define_insn "*tst<mode>_cconly_extimm"
673 [(set (reg CC_REGNUM)
674 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
675 (match_operand:GPR 1 "const0_operand" "")))
676 (clobber (match_scratch:GPR 2 "=X,d"))]
677 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
681 [(set_attr "op_type" "RR<E>,RXY")
682 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
684 (define_insn "*tstdi"
685 [(set (reg CC_REGNUM)
686 (compare (match_operand:DI 0 "register_operand" "d")
687 (match_operand:DI 1 "const0_operand" "")))
688 (set (match_operand:DI 2 "register_operand" "=d")
690 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
692 [(set_attr "op_type" "RRE")
693 (set_attr "z10prop" "z10_fr_E1")])
695 (define_insn "*tstsi"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
698 (match_operand:SI 1 "const0_operand" "")))
699 (set (match_operand:SI 2 "register_operand" "=d,d,d")
701 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
706 [(set_attr "op_type" "RR,RS,RSY")
707 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
709 (define_insn "*tstsi_cconly"
710 [(set (reg CC_REGNUM)
711 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
712 (match_operand:SI 1 "const0_operand" "")))
713 (clobber (match_scratch:SI 2 "=X,d,d"))]
714 "s390_match_ccmode(insn, CCSmode)"
719 [(set_attr "op_type" "RR,RS,RSY")
720 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
722 (define_insn "*tstdi_cconly_31"
723 [(set (reg CC_REGNUM)
724 (compare (match_operand:DI 0 "register_operand" "d")
725 (match_operand:DI 1 "const0_operand" "")))]
726 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
728 [(set_attr "op_type" "RS")
729 (set_attr "atype" "reg")])
732 (define_insn "*tst<mode>_cconly2"
733 [(set (reg CC_REGNUM)
734 (compare (match_operand:GPR 0 "register_operand" "d")
735 (match_operand:GPR 1 "const0_operand" "")))]
736 "s390_match_ccmode(insn, CCSmode)"
738 [(set_attr "op_type" "RR<E>")
739 (set_attr "z10prop" "z10_fr_E1")])
741 ; tst(hi|qi) instruction pattern(s).
743 (define_insn "*tst<mode>CCT"
744 [(set (reg CC_REGNUM)
745 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
746 (match_operand:HQI 1 "const0_operand" "")))
747 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
749 "s390_match_ccmode(insn, CCTmode)"
752 icmy\t%2,<icm_lo>,%S0
754 [(set_attr "op_type" "RS,RSY,RI")
755 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
757 (define_insn "*tsthiCCT_cconly"
758 [(set (reg CC_REGNUM)
759 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
760 (match_operand:HI 1 "const0_operand" "")))
761 (clobber (match_scratch:HI 2 "=d,d,X"))]
762 "s390_match_ccmode(insn, CCTmode)"
767 [(set_attr "op_type" "RS,RSY,RI")
768 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
770 (define_insn "*tstqiCCT_cconly"
771 [(set (reg CC_REGNUM)
772 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
773 (match_operand:QI 1 "const0_operand" "")))]
774 "s390_match_ccmode(insn, CCTmode)"
779 [(set_attr "op_type" "SI,SIY,RI")
780 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
782 (define_insn "*tst<mode>"
783 [(set (reg CC_REGNUM)
784 (compare (match_operand:HQI 0 "s_operand" "Q,S")
785 (match_operand:HQI 1 "const0_operand" "")))
786 (set (match_operand:HQI 2 "register_operand" "=d,d")
788 "s390_match_ccmode(insn, CCSmode)"
791 icmy\t%2,<icm_lo>,%S0"
792 [(set_attr "op_type" "RS,RSY")
793 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
795 (define_insn "*tst<mode>_cconly"
796 [(set (reg CC_REGNUM)
797 (compare (match_operand:HQI 0 "s_operand" "Q,S")
798 (match_operand:HQI 1 "const0_operand" "")))
799 (clobber (match_scratch:HQI 2 "=d,d"))]
800 "s390_match_ccmode(insn, CCSmode)"
803 icmy\t%2,<icm_lo>,%S0"
804 [(set_attr "op_type" "RS,RSY")
805 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
808 ; Compare (equality) instructions
810 (define_insn "*cmpdi_cct"
811 [(set (reg CC_REGNUM)
812 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
813 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
814 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
821 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
822 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
824 (define_insn "*cmpsi_cct"
825 [(set (reg CC_REGNUM)
826 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
827 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
828 "s390_match_ccmode (insn, CCTmode)"
836 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
837 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
839 ; Compare (signed) instructions
841 (define_insn "*cmpdi_ccs_sign"
842 [(set (reg CC_REGNUM)
843 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
845 (match_operand:DI 0 "register_operand" "d, d,d")))]
846 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
851 [(set_attr "op_type" "RRE,RXY,RIL")
852 (set_attr "z10prop" "z10_c,*,*")
853 (set_attr "type" "*,*,larl")])
857 (define_insn "*cmpsi_ccs_sign"
858 [(set (reg CC_REGNUM)
859 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
860 (match_operand:SI 0 "register_operand" "d,d,d")))]
861 "s390_match_ccmode(insn, CCSRmode)"
866 [(set_attr "op_type" "RX,RXY,RIL")
867 (set_attr "cpu_facility" "*,*,z10")
868 (set_attr "type" "*,*,larl")
869 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
871 (define_insn "*cmphi_ccs_z10"
872 [(set (reg CC_REGNUM)
873 (compare (match_operand:HI 0 "s_operand" "Q")
874 (match_operand:HI 1 "immediate_operand" "K")))]
875 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
877 [(set_attr "op_type" "SIL")
878 (set_attr "z196prop" "z196_cracked")])
880 (define_insn "*cmpdi_ccs_signhi_rl"
881 [(set (reg CC_REGNUM)
882 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
883 (match_operand:GPR 0 "register_operand" "d,d")))]
884 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
888 [(set_attr "op_type" "RXY,RIL")
889 (set_attr "type" "*,larl")])
891 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
892 (define_insn "*cmp<mode>_ccs"
893 [(set (reg CC_REGNUM)
894 (compare (match_operand:GPR 0 "nonimmediate_operand"
896 (match_operand:GPR 1 "general_operand"
898 "s390_match_ccmode(insn, CCSmode)"
907 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
908 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
909 (set_attr "type" "*,*,*,*,*,*,larl")
910 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
913 ; Compare (unsigned) instructions
915 (define_insn "*cmpsi_ccu_zerohi_rlsi"
916 [(set (reg CC_REGNUM)
917 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
918 "larl_operand" "X")))
919 (match_operand:SI 0 "register_operand" "d")))]
920 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
922 [(set_attr "op_type" "RIL")
923 (set_attr "type" "larl")
924 (set_attr "z10prop" "z10_super")])
927 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
928 [(set (reg CC_REGNUM)
929 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
930 "larl_operand" "X")))
931 (match_operand:GPR 0 "register_operand" "d")))]
932 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
934 [(set_attr "op_type" "RIL")
935 (set_attr "type" "larl")
936 (set_attr "z10prop" "z10_super")])
938 (define_insn "*cmpdi_ccu_zero"
939 [(set (reg CC_REGNUM)
940 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
942 (match_operand:DI 0 "register_operand" "d, d,d")))]
943 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
948 [(set_attr "op_type" "RRE,RXY,RIL")
949 (set_attr "cpu_facility" "*,*,z10")
950 (set_attr "type" "*,*,larl")
951 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
953 (define_insn "*cmpdi_ccu"
954 [(set (reg CC_REGNUM)
955 (compare (match_operand:DI 0 "nonimmediate_operand"
957 (match_operand:DI 1 "general_operand"
958 "d,Op,b,D,RT,BQ,Q")))]
959 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
968 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
969 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
970 (set_attr "type" "*,*,larl,*,*,*,*")
971 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
973 (define_insn "*cmpsi_ccu"
974 [(set (reg CC_REGNUM)
975 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
976 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
977 "s390_match_ccmode (insn, CCUmode)"
987 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
988 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
989 (set_attr "type" "*,*,larl,*,*,*,*,*")
990 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
992 (define_insn "*cmphi_ccu"
993 [(set (reg CC_REGNUM)
994 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
995 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
996 "s390_match_ccmode (insn, CCUmode)
997 && !register_operand (operands[1], HImode)"
1004 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1005 (set_attr "cpu_facility" "*,*,z10,*,*")
1006 (set_attr "z10prop" "*,*,z10_super,*,*")])
1008 (define_insn "*cmpqi_ccu"
1009 [(set (reg CC_REGNUM)
1010 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1011 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1012 "s390_match_ccmode (insn, CCUmode)
1013 && !register_operand (operands[1], QImode)"
1021 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1022 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1025 ; Block compare (CLC) instruction patterns.
1028 [(set (reg CC_REGNUM)
1029 (compare (match_operand:BLK 0 "memory_operand" "Q")
1030 (match_operand:BLK 1 "memory_operand" "Q")))
1031 (use (match_operand 2 "const_int_operand" "n"))]
1032 "s390_match_ccmode (insn, CCUmode)
1033 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1034 "clc\t%O0(%2,%R0),%S1"
1035 [(set_attr "op_type" "SS")])
1038 [(set (reg CC_REGNUM)
1039 (compare (match_operand 0 "memory_operand" "")
1040 (match_operand 1 "memory_operand" "")))]
1042 && s390_match_ccmode (insn, CCUmode)
1043 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1044 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1046 [(set (match_dup 0) (match_dup 1))
1047 (use (match_dup 2))])]
1049 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1050 operands[0] = adjust_address (operands[0], BLKmode, 0);
1051 operands[1] = adjust_address (operands[1], BLKmode, 0);
1053 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1054 operands[0], operands[1]);
1055 operands[0] = SET_DEST (PATTERN (curr_insn));
1059 ; (TF|DF|SF|TD|DD|SD) instructions
1061 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1062 (define_insn "*cmp<mode>_ccs_0"
1063 [(set (reg CC_REGNUM)
1064 (compare (match_operand:FP 0 "register_operand" "f")
1065 (match_operand:FP 1 "const0_operand" "")))]
1066 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1067 "lt<xde><bt>r\t%0,%0"
1068 [(set_attr "op_type" "RRE")
1069 (set_attr "type" "fsimp<mode>")])
1071 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1072 (define_insn "*cmp<mode>_ccs"
1073 [(set (reg CC_REGNUM)
1074 (compare (match_operand:FP 0 "register_operand" "f,f")
1075 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1076 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1080 [(set_attr "op_type" "RRE,RXE")
1081 (set_attr "type" "fsimp<mode>")])
1084 ; Compare and Branch instructions
1086 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1087 ; The following instructions do a complementary access of their second
1088 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1089 (define_insn "*cmp_and_br_signed_<mode>"
1091 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1092 [(match_operand:GPR 1 "register_operand" "d,d")
1093 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1094 (label_ref (match_operand 3 "" ""))
1096 (clobber (reg:CC CC_REGNUM))]
1097 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1099 if (get_attr_length (insn) == 6)
1100 return which_alternative ?
1101 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1103 return which_alternative ?
1104 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1106 [(set_attr "op_type" "RIE")
1107 (set_attr "type" "branch")
1108 (set_attr "z10prop" "z10_super_c,z10_super")
1109 (set (attr "length")
1110 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1111 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1112 ; 10 byte for cgr/jg
1114 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1115 ; The following instructions do a complementary access of their second
1116 ; operand (z10 only): clrj, clgrj, clr, clgr
1117 (define_insn "*cmp_and_br_unsigned_<mode>"
1119 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1120 [(match_operand:GPR 1 "register_operand" "d,d")
1121 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1122 (label_ref (match_operand 3 "" ""))
1124 (clobber (reg:CC CC_REGNUM))]
1125 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1127 if (get_attr_length (insn) == 6)
1128 return which_alternative ?
1129 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1131 return which_alternative ?
1132 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1134 [(set_attr "op_type" "RIE")
1135 (set_attr "type" "branch")
1136 (set_attr "z10prop" "z10_super_c,z10_super")
1137 (set (attr "length")
1138 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1139 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1140 ; 10 byte for clgr/jg
1142 ; And now the same two patterns as above but with a negated CC mask.
1144 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1145 ; The following instructions do a complementary access of their second
1146 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1147 (define_insn "*icmp_and_br_signed_<mode>"
1149 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1150 [(match_operand:GPR 1 "register_operand" "d,d")
1151 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1153 (label_ref (match_operand 3 "" ""))))
1154 (clobber (reg:CC CC_REGNUM))]
1155 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1157 if (get_attr_length (insn) == 6)
1158 return which_alternative ?
1159 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1161 return which_alternative ?
1162 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1164 [(set_attr "op_type" "RIE")
1165 (set_attr "type" "branch")
1166 (set_attr "z10prop" "z10_super_c,z10_super")
1167 (set (attr "length")
1168 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1169 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1170 ; 10 byte for cgr/jg
1172 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1173 ; The following instructions do a complementary access of their second
1174 ; operand (z10 only): clrj, clgrj, clr, clgr
1175 (define_insn "*icmp_and_br_unsigned_<mode>"
1177 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1178 [(match_operand:GPR 1 "register_operand" "d,d")
1179 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1181 (label_ref (match_operand 3 "" ""))))
1182 (clobber (reg:CC CC_REGNUM))]
1183 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1185 if (get_attr_length (insn) == 6)
1186 return which_alternative ?
1187 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1189 return which_alternative ?
1190 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1192 [(set_attr "op_type" "RIE")
1193 (set_attr "type" "branch")
1194 (set_attr "z10prop" "z10_super_c,z10_super")
1195 (set (attr "length")
1196 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1197 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1198 ; 10 byte for clgr/jg
1201 ;;- Move instructions.
1205 ; movti instruction pattern(s).
1208 (define_insn "movti"
1209 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1210 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1217 [(set_attr "op_type" "RSY,RSY,*,*")
1218 (set_attr "type" "lm,stm,*,*")])
1221 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1222 (match_operand:TI 1 "general_operand" ""))]
1223 "TARGET_ZARCH && reload_completed
1224 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1225 [(set (match_dup 2) (match_dup 4))
1226 (set (match_dup 3) (match_dup 5))]
1228 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1229 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1230 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1231 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1235 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1236 (match_operand:TI 1 "general_operand" ""))]
1237 "TARGET_ZARCH && reload_completed
1238 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1239 [(set (match_dup 2) (match_dup 4))
1240 (set (match_dup 3) (match_dup 5))]
1242 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1243 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1244 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1245 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1249 [(set (match_operand:TI 0 "register_operand" "")
1250 (match_operand:TI 1 "memory_operand" ""))]
1251 "TARGET_ZARCH && reload_completed
1252 && !s_operand (operands[1], VOIDmode)"
1253 [(set (match_dup 0) (match_dup 1))]
1255 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1256 addr = gen_lowpart (Pmode, addr);
1257 s390_load_address (addr, XEXP (operands[1], 0));
1258 operands[1] = replace_equiv_address (operands[1], addr);
1263 ; Patterns used for secondary reloads
1266 ; z10 provides move instructions accepting larl memory operands.
1267 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1268 ; These patterns are also used for unaligned SI and DI accesses.
1270 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1271 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1272 (match_operand:INTALL 1 "register_operand" "=d")
1273 (match_operand:P 2 "register_operand" "=&a")])]
1276 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1280 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1281 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1282 (match_operand:INTALL 1 "memory_operand" "")
1283 (match_operand:P 2 "register_operand" "=a")])]
1286 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1290 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1291 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1292 (match_operand:FPALL 1 "register_operand" "=d")
1293 (match_operand:P 2 "register_operand" "=&a")])]
1296 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1300 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1301 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1302 (match_operand:FPALL 1 "memory_operand" "")
1303 (match_operand:P 2 "register_operand" "=a")])]
1306 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1310 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1311 [(parallel [(match_operand:P 0 "register_operand" "=d")
1312 (match_operand:P 1 "larl_operand" "")
1313 (match_operand:P 2 "register_operand" "=a")])]
1316 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1320 ; Handles loading a PLUS (load address) expression
1322 (define_expand "reload<mode>_plus"
1323 [(parallel [(match_operand:P 0 "register_operand" "=a")
1324 (match_operand:P 1 "s390_plus_operand" "")
1325 (match_operand:P 2 "register_operand" "=&a")])]
1328 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1332 ; Handles assessing a non-offsetable memory address
1334 (define_expand "reload<mode>_nonoffmem_in"
1335 [(parallel [(match_operand 0 "register_operand" "")
1336 (match_operand 1 "" "")
1337 (match_operand:P 2 "register_operand" "=&a")])]
1340 gcc_assert (MEM_P (operands[1]));
1341 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1342 operands[1] = replace_equiv_address (operands[1], operands[2]);
1343 emit_move_insn (operands[0], operands[1]);
1347 (define_expand "reload<mode>_nonoffmem_out"
1348 [(parallel [(match_operand 0 "" "")
1349 (match_operand 1 "register_operand" "")
1350 (match_operand:P 2 "register_operand" "=&a")])]
1353 gcc_assert (MEM_P (operands[0]));
1354 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1355 operands[0] = replace_equiv_address (operands[0], operands[2]);
1356 emit_move_insn (operands[0], operands[1]);
1360 (define_expand "reload<mode>_PIC_addr"
1361 [(parallel [(match_operand 0 "register_operand" "=d")
1362 (match_operand 1 "larl_operand" "")
1363 (match_operand:P 2 "register_operand" "=a")])]
1366 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1367 emit_move_insn (operands[0], new_rtx);
1371 ; movdi instruction pattern(s).
1374 (define_expand "movdi"
1375 [(set (match_operand:DI 0 "general_operand" "")
1376 (match_operand:DI 1 "general_operand" ""))]
1379 /* Handle symbolic constants. */
1381 && (SYMBOLIC_CONST (operands[1])
1382 || (GET_CODE (operands[1]) == PLUS
1383 && XEXP (operands[1], 0) == pic_offset_table_rtx
1384 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1385 emit_symbolic_move (operands);
1388 (define_insn "*movdi_larl"
1389 [(set (match_operand:DI 0 "register_operand" "=d")
1390 (match_operand:DI 1 "larl_operand" "X"))]
1392 && !FP_REG_P (operands[0])"
1394 [(set_attr "op_type" "RIL")
1395 (set_attr "type" "larl")
1396 (set_attr "z10prop" "z10_super_A1")])
1398 (define_insn "*movdi_64"
1399 [(set (match_operand:DI 0 "nonimmediate_operand"
1400 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1401 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1402 (match_operand:DI 1 "general_operand"
1403 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1404 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1433 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1434 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1435 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1436 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1438 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1439 z10,*,*,*,*,*,longdisp,*,longdisp,
1441 (set_attr "z10prop" "z10_fwd_A1,
1470 [(set (match_operand:DI 0 "register_operand" "")
1471 (match_operand:DI 1 "register_operand" ""))]
1472 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1473 [(set (match_dup 2) (match_dup 3))
1474 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1475 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1476 "operands[2] = gen_lowpart (SImode, operands[0]);
1477 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1480 [(set (match_operand:DI 0 "register_operand" "")
1481 (match_operand:DI 1 "register_operand" ""))]
1482 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1483 && dead_or_set_p (insn, operands[1])"
1484 [(set (match_dup 3) (match_dup 2))
1485 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1486 (set (match_dup 4) (match_dup 2))]
1487 "operands[2] = gen_lowpart (SImode, operands[1]);
1488 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1491 [(set (match_operand:DI 0 "register_operand" "")
1492 (match_operand:DI 1 "register_operand" ""))]
1493 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1494 && !dead_or_set_p (insn, operands[1])"
1495 [(set (match_dup 3) (match_dup 2))
1496 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1497 (set (match_dup 4) (match_dup 2))
1498 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1499 "operands[2] = gen_lowpart (SImode, operands[1]);
1500 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1502 (define_insn "*movdi_31"
1503 [(set (match_operand:DI 0 "nonimmediate_operand"
1504 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1505 (match_operand:DI 1 "general_operand"
1506 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1521 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1522 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1523 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1525 ; For a load from a symbol ref we can use one of the target registers
1526 ; together with larl to load the address.
1528 [(set (match_operand:DI 0 "register_operand" "")
1529 (match_operand:DI 1 "memory_operand" ""))]
1530 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1531 && larl_operand (XEXP (operands[1], 0), SImode)"
1532 [(set (match_dup 2) (match_dup 3))
1533 (set (match_dup 0) (match_dup 1))]
1535 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1536 operands[3] = XEXP (operands[1], 0);
1537 operands[1] = replace_equiv_address (operands[1], operands[2]);
1541 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1542 (match_operand:DI 1 "general_operand" ""))]
1543 "!TARGET_ZARCH && reload_completed
1544 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1545 [(set (match_dup 2) (match_dup 4))
1546 (set (match_dup 3) (match_dup 5))]
1548 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1549 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1550 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1551 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1555 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1556 (match_operand:DI 1 "general_operand" ""))]
1557 "!TARGET_ZARCH && reload_completed
1558 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1559 [(set (match_dup 2) (match_dup 4))
1560 (set (match_dup 3) (match_dup 5))]
1562 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1563 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1564 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1565 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1569 [(set (match_operand:DI 0 "register_operand" "")
1570 (match_operand:DI 1 "memory_operand" ""))]
1571 "!TARGET_ZARCH && reload_completed
1572 && !FP_REG_P (operands[0])
1573 && !s_operand (operands[1], VOIDmode)"
1574 [(set (match_dup 0) (match_dup 1))]
1576 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1577 s390_load_address (addr, XEXP (operands[1], 0));
1578 operands[1] = replace_equiv_address (operands[1], addr);
1582 [(set (match_operand:DI 0 "register_operand" "")
1583 (mem:DI (match_operand 1 "address_operand" "")))]
1585 && !FP_REG_P (operands[0])
1586 && GET_CODE (operands[1]) == SYMBOL_REF
1587 && CONSTANT_POOL_ADDRESS_P (operands[1])
1588 && get_pool_mode (operands[1]) == DImode
1589 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1590 [(set (match_dup 0) (match_dup 2))]
1591 "operands[2] = get_pool_constant (operands[1]);")
1593 (define_insn "*la_64"
1594 [(set (match_operand:DI 0 "register_operand" "=d,d")
1595 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1600 [(set_attr "op_type" "RX,RXY")
1601 (set_attr "type" "la")
1602 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1606 [(set (match_operand:DI 0 "register_operand" "")
1607 (match_operand:QI 1 "address_operand" ""))
1608 (clobber (reg:CC CC_REGNUM))])]
1610 && preferred_la_operand_p (operands[1], const0_rtx)"
1611 [(set (match_dup 0) (match_dup 1))]
1615 [(set (match_operand:DI 0 "register_operand" "")
1616 (match_operand:DI 1 "register_operand" ""))
1619 (plus:DI (match_dup 0)
1620 (match_operand:DI 2 "nonmemory_operand" "")))
1621 (clobber (reg:CC CC_REGNUM))])]
1623 && !reg_overlap_mentioned_p (operands[0], operands[2])
1624 && preferred_la_operand_p (operands[1], operands[2])"
1625 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1629 ; movsi instruction pattern(s).
1632 (define_expand "movsi"
1633 [(set (match_operand:SI 0 "general_operand" "")
1634 (match_operand:SI 1 "general_operand" ""))]
1637 /* Handle symbolic constants. */
1639 && (SYMBOLIC_CONST (operands[1])
1640 || (GET_CODE (operands[1]) == PLUS
1641 && XEXP (operands[1], 0) == pic_offset_table_rtx
1642 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1643 emit_symbolic_move (operands);
1646 (define_insn "*movsi_larl"
1647 [(set (match_operand:SI 0 "register_operand" "=d")
1648 (match_operand:SI 1 "larl_operand" "X"))]
1649 "!TARGET_64BIT && TARGET_CPU_ZARCH
1650 && !FP_REG_P (operands[0])"
1652 [(set_attr "op_type" "RIL")
1653 (set_attr "type" "larl")
1654 (set_attr "z10prop" "z10_fwd_A1")])
1656 (define_insn "*movsi_zarch"
1657 [(set (match_operand:SI 0 "nonimmediate_operand"
1658 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1659 (match_operand:SI 1 "general_operand"
1660 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1685 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1686 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1687 (set_attr "type" "*,
1709 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1710 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1711 (set_attr "z10prop" "z10_fwd_A1,
1734 (define_insn "*movsi_esa"
1735 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1736 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1750 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1751 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1752 (set_attr "z10prop" "z10_fwd_A1,
1766 [(set (match_operand:SI 0 "register_operand" "")
1767 (mem:SI (match_operand 1 "address_operand" "")))]
1768 "!FP_REG_P (operands[0])
1769 && GET_CODE (operands[1]) == SYMBOL_REF
1770 && CONSTANT_POOL_ADDRESS_P (operands[1])
1771 && get_pool_mode (operands[1]) == SImode
1772 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1773 [(set (match_dup 0) (match_dup 2))]
1774 "operands[2] = get_pool_constant (operands[1]);")
1776 (define_insn "*la_31"
1777 [(set (match_operand:SI 0 "register_operand" "=d,d")
1778 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1779 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1783 [(set_attr "op_type" "RX,RXY")
1784 (set_attr "type" "la")
1785 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1789 [(set (match_operand:SI 0 "register_operand" "")
1790 (match_operand:QI 1 "address_operand" ""))
1791 (clobber (reg:CC CC_REGNUM))])]
1793 && preferred_la_operand_p (operands[1], const0_rtx)"
1794 [(set (match_dup 0) (match_dup 1))]
1798 [(set (match_operand:SI 0 "register_operand" "")
1799 (match_operand:SI 1 "register_operand" ""))
1802 (plus:SI (match_dup 0)
1803 (match_operand:SI 2 "nonmemory_operand" "")))
1804 (clobber (reg:CC CC_REGNUM))])]
1806 && !reg_overlap_mentioned_p (operands[0], operands[2])
1807 && preferred_la_operand_p (operands[1], operands[2])"
1808 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1811 (define_insn "*la_31_and"
1812 [(set (match_operand:SI 0 "register_operand" "=d,d")
1813 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1814 (const_int 2147483647)))]
1819 [(set_attr "op_type" "RX,RXY")
1820 (set_attr "type" "la")
1821 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1823 (define_insn_and_split "*la_31_and_cc"
1824 [(set (match_operand:SI 0 "register_operand" "=d")
1825 (and:SI (match_operand:QI 1 "address_operand" "p")
1826 (const_int 2147483647)))
1827 (clobber (reg:CC CC_REGNUM))]
1830 "&& reload_completed"
1832 (and:SI (match_dup 1) (const_int 2147483647)))]
1834 [(set_attr "op_type" "RX")
1835 (set_attr "type" "la")])
1837 (define_insn "force_la_31"
1838 [(set (match_operand:SI 0 "register_operand" "=d,d")
1839 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1840 (use (const_int 0))]
1845 [(set_attr "op_type" "RX")
1846 (set_attr "type" "la")
1847 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1850 ; movhi instruction pattern(s).
1853 (define_expand "movhi"
1854 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1855 (match_operand:HI 1 "general_operand" ""))]
1858 /* Make it explicit that loading a register from memory
1859 always sign-extends (at least) to SImode. */
1860 if (optimize && can_create_pseudo_p ()
1861 && register_operand (operands[0], VOIDmode)
1862 && GET_CODE (operands[1]) == MEM)
1864 rtx tmp = gen_reg_rtx (SImode);
1865 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1866 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1867 operands[1] = gen_lowpart (HImode, tmp);
1871 (define_insn "*movhi"
1872 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1873 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1885 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1886 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1887 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1888 (set_attr "z10prop" "z10_fr_E1,
1899 [(set (match_operand:HI 0 "register_operand" "")
1900 (mem:HI (match_operand 1 "address_operand" "")))]
1901 "GET_CODE (operands[1]) == SYMBOL_REF
1902 && CONSTANT_POOL_ADDRESS_P (operands[1])
1903 && get_pool_mode (operands[1]) == HImode
1904 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1905 [(set (match_dup 0) (match_dup 2))]
1906 "operands[2] = get_pool_constant (operands[1]);")
1909 ; movqi instruction pattern(s).
1912 (define_expand "movqi"
1913 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1914 (match_operand:QI 1 "general_operand" ""))]
1917 /* On z/Architecture, zero-extending from memory to register
1918 is just as fast as a QImode load. */
1919 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1920 && register_operand (operands[0], VOIDmode)
1921 && GET_CODE (operands[1]) == MEM)
1923 rtx tmp = gen_reg_rtx (DImode);
1924 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1925 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1926 operands[1] = gen_lowpart (QImode, tmp);
1930 (define_insn "*movqi"
1931 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1932 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1944 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1945 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1946 (set_attr "z10prop" "z10_fr_E1,
1957 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1958 (mem:QI (match_operand 1 "address_operand" "")))]
1959 "GET_CODE (operands[1]) == SYMBOL_REF
1960 && CONSTANT_POOL_ADDRESS_P (operands[1])
1961 && get_pool_mode (operands[1]) == QImode
1962 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1963 [(set (match_dup 0) (match_dup 2))]
1964 "operands[2] = get_pool_constant (operands[1]);")
1967 ; movstrictqi instruction pattern(s).
1970 (define_insn "*movstrictqi"
1971 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1972 (match_operand:QI 1 "memory_operand" "R,T"))]
1977 [(set_attr "op_type" "RX,RXY")
1978 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1981 ; movstricthi instruction pattern(s).
1984 (define_insn "*movstricthi"
1985 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1986 (match_operand:HI 1 "memory_operand" "Q,S"))
1987 (clobber (reg:CC CC_REGNUM))]
1992 [(set_attr "op_type" "RS,RSY")
1993 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1996 ; movstrictsi instruction pattern(s).
1999 (define_insn "movstrictsi"
2000 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2001 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2008 [(set_attr "op_type" "RR,RX,RXY,RRE")
2009 (set_attr "type" "lr,load,load,*")
2010 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2013 ; mov(tf|td) instruction pattern(s).
2016 (define_expand "mov<mode>"
2017 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2018 (match_operand:TD_TF 1 "general_operand" ""))]
2022 (define_insn "*mov<mode>_64"
2023 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2024 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2035 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2036 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2037 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2039 (define_insn "*mov<mode>_31"
2040 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2041 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2048 [(set_attr "op_type" "RRE,RRE,*,*")
2049 (set_attr "type" "fsimptf,fsimptf,*,*")
2050 (set_attr "cpu_facility" "z196,*,*,*")])
2052 ; TFmode in GPRs splitters
2055 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2056 (match_operand:TD_TF 1 "general_operand" ""))]
2057 "TARGET_ZARCH && reload_completed
2058 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2059 [(set (match_dup 2) (match_dup 4))
2060 (set (match_dup 3) (match_dup 5))]
2062 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2063 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2064 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2065 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2069 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2070 (match_operand:TD_TF 1 "general_operand" ""))]
2071 "TARGET_ZARCH && reload_completed
2072 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2073 [(set (match_dup 2) (match_dup 4))
2074 (set (match_dup 3) (match_dup 5))]
2076 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2077 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2078 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2079 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2083 [(set (match_operand:TD_TF 0 "register_operand" "")
2084 (match_operand:TD_TF 1 "memory_operand" ""))]
2085 "TARGET_ZARCH && reload_completed
2086 && !FP_REG_P (operands[0])
2087 && !s_operand (operands[1], VOIDmode)"
2088 [(set (match_dup 0) (match_dup 1))]
2090 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2091 addr = gen_lowpart (Pmode, addr);
2092 s390_load_address (addr, XEXP (operands[1], 0));
2093 operands[1] = replace_equiv_address (operands[1], addr);
2096 ; TFmode in BFPs splitters
2099 [(set (match_operand:TD_TF 0 "register_operand" "")
2100 (match_operand:TD_TF 1 "memory_operand" ""))]
2101 "reload_completed && offsettable_memref_p (operands[1])
2102 && FP_REG_P (operands[0])"
2103 [(set (match_dup 2) (match_dup 4))
2104 (set (match_dup 3) (match_dup 5))]
2106 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2108 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2110 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2111 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2115 [(set (match_operand:TD_TF 0 "memory_operand" "")
2116 (match_operand:TD_TF 1 "register_operand" ""))]
2117 "reload_completed && offsettable_memref_p (operands[0])
2118 && FP_REG_P (operands[1])"
2119 [(set (match_dup 2) (match_dup 4))
2120 (set (match_dup 3) (match_dup 5))]
2122 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2123 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2124 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2126 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2131 ; mov(df|dd) instruction pattern(s).
2134 (define_expand "mov<mode>"
2135 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2136 (match_operand:DD_DF 1 "general_operand" ""))]
2140 (define_insn "*mov<mode>_64dfp"
2141 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2142 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2143 (match_operand:DD_DF 1 "general_operand"
2144 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2159 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2160 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2161 fstoredf,fstoredf,*,lr,load,store")
2162 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2163 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2165 (define_insn "*mov<mode>_64"
2166 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2167 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2180 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2181 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2182 fstore<mode>,fstore<mode>,*,lr,load,store")
2183 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2184 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2186 (define_insn "*mov<mode>_31"
2187 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2188 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2189 (match_operand:DD_DF 1 "general_operand"
2190 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2205 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2206 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2207 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2208 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2211 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2212 (match_operand:DD_DF 1 "general_operand" ""))]
2213 "!TARGET_ZARCH && reload_completed
2214 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2215 [(set (match_dup 2) (match_dup 4))
2216 (set (match_dup 3) (match_dup 5))]
2218 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2219 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2220 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2221 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2225 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2226 (match_operand:DD_DF 1 "general_operand" ""))]
2227 "!TARGET_ZARCH && reload_completed
2228 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2229 [(set (match_dup 2) (match_dup 4))
2230 (set (match_dup 3) (match_dup 5))]
2232 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2233 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2234 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2235 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2239 [(set (match_operand:DD_DF 0 "register_operand" "")
2240 (match_operand:DD_DF 1 "memory_operand" ""))]
2241 "!TARGET_ZARCH && reload_completed
2242 && !FP_REG_P (operands[0])
2243 && !s_operand (operands[1], VOIDmode)"
2244 [(set (match_dup 0) (match_dup 1))]
2246 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2247 s390_load_address (addr, XEXP (operands[1], 0));
2248 operands[1] = replace_equiv_address (operands[1], addr);
2252 ; mov(sf|sd) instruction pattern(s).
2255 (define_insn "mov<mode>"
2256 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2257 "=f,f,f,f,R,T,d,d,d,d,R,T")
2258 (match_operand:SD_SF 1 "general_operand"
2259 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2274 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2275 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2276 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2277 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2278 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2281 ; movcc instruction pattern
2284 (define_insn "movcc"
2285 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2286 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2296 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2297 (set_attr "type" "lr,*,*,load,load,store,store")
2298 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2299 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2302 ; Block move (MVC) patterns.
2306 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2307 (match_operand:BLK 1 "memory_operand" "Q"))
2308 (use (match_operand 2 "const_int_operand" "n"))]
2309 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2310 "mvc\t%O0(%2,%R0),%S1"
2311 [(set_attr "op_type" "SS")])
2313 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2314 ; order to have it implemented with mvc.
2317 [(set (match_operand:QI 0 "memory_operand" "")
2318 (match_operand:QI 1 "memory_operand" ""))]
2321 [(set (match_dup 0) (match_dup 1))
2322 (use (const_int 1))])]
2324 operands[0] = adjust_address (operands[0], BLKmode, 0);
2325 operands[1] = adjust_address (operands[1], BLKmode, 0);
2331 [(set (match_operand:BLK 0 "memory_operand" "")
2332 (match_operand:BLK 1 "memory_operand" ""))
2333 (use (match_operand 2 "const_int_operand" ""))])
2335 [(set (match_operand:BLK 3 "memory_operand" "")
2336 (match_operand:BLK 4 "memory_operand" ""))
2337 (use (match_operand 5 "const_int_operand" ""))])]
2338 "s390_offset_p (operands[0], operands[3], operands[2])
2339 && s390_offset_p (operands[1], operands[4], operands[2])
2340 && !s390_overlap_p (operands[0], operands[1],
2341 INTVAL (operands[2]) + INTVAL (operands[5]))
2342 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2344 [(set (match_dup 6) (match_dup 7))
2345 (use (match_dup 8))])]
2346 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2347 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2348 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2352 ; load_multiple pattern(s).
2354 ; ??? Due to reload problems with replacing registers inside match_parallel
2355 ; we currently support load_multiple/store_multiple only after reload.
2358 (define_expand "load_multiple"
2359 [(match_par_dup 3 [(set (match_operand 0 "" "")
2360 (match_operand 1 "" ""))
2361 (use (match_operand 2 "" ""))])]
2364 enum machine_mode mode;
2370 /* Support only loading a constant number of fixed-point registers from
2371 memory and only bother with this if more than two */
2372 if (GET_CODE (operands[2]) != CONST_INT
2373 || INTVAL (operands[2]) < 2
2374 || INTVAL (operands[2]) > 16
2375 || GET_CODE (operands[1]) != MEM
2376 || GET_CODE (operands[0]) != REG
2377 || REGNO (operands[0]) >= 16)
2380 count = INTVAL (operands[2]);
2381 regno = REGNO (operands[0]);
2382 mode = GET_MODE (operands[0]);
2383 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2386 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2387 if (!can_create_pseudo_p ())
2389 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2391 from = XEXP (operands[1], 0);
2394 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2395 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2396 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2398 from = XEXP (XEXP (operands[1], 0), 0);
2399 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2406 from = force_reg (Pmode, XEXP (operands[1], 0));
2410 for (i = 0; i < count; i++)
2411 XVECEXP (operands[3], 0, i)
2412 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2413 change_address (operands[1], mode,
2414 plus_constant (Pmode, from,
2415 off + i * GET_MODE_SIZE (mode))));
2418 (define_insn "*load_multiple_di"
2419 [(match_parallel 0 "load_multiple_operation"
2420 [(set (match_operand:DI 1 "register_operand" "=r")
2421 (match_operand:DI 2 "s_operand" "QS"))])]
2422 "reload_completed && TARGET_ZARCH"
2424 int words = XVECLEN (operands[0], 0);
2425 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2426 return "lmg\t%1,%0,%S2";
2428 [(set_attr "op_type" "RSY")
2429 (set_attr "type" "lm")])
2431 (define_insn "*load_multiple_si"
2432 [(match_parallel 0 "load_multiple_operation"
2433 [(set (match_operand:SI 1 "register_operand" "=r,r")
2434 (match_operand:SI 2 "s_operand" "Q,S"))])]
2437 int words = XVECLEN (operands[0], 0);
2438 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2439 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2441 [(set_attr "op_type" "RS,RSY")
2442 (set_attr "type" "lm")])
2445 ; store multiple pattern(s).
2448 (define_expand "store_multiple"
2449 [(match_par_dup 3 [(set (match_operand 0 "" "")
2450 (match_operand 1 "" ""))
2451 (use (match_operand 2 "" ""))])]
2454 enum machine_mode mode;
2460 /* Support only storing a constant number of fixed-point registers to
2461 memory and only bother with this if more than two. */
2462 if (GET_CODE (operands[2]) != CONST_INT
2463 || INTVAL (operands[2]) < 2
2464 || INTVAL (operands[2]) > 16
2465 || GET_CODE (operands[0]) != MEM
2466 || GET_CODE (operands[1]) != REG
2467 || REGNO (operands[1]) >= 16)
2470 count = INTVAL (operands[2]);
2471 regno = REGNO (operands[1]);
2472 mode = GET_MODE (operands[1]);
2473 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2476 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2478 if (!can_create_pseudo_p ())
2480 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2482 to = XEXP (operands[0], 0);
2485 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2486 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2487 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2489 to = XEXP (XEXP (operands[0], 0), 0);
2490 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2497 to = force_reg (Pmode, XEXP (operands[0], 0));
2501 for (i = 0; i < count; i++)
2502 XVECEXP (operands[3], 0, i)
2503 = gen_rtx_SET (VOIDmode,
2504 change_address (operands[0], mode,
2505 plus_constant (Pmode, to,
2506 off + i * GET_MODE_SIZE (mode))),
2507 gen_rtx_REG (mode, regno + i));
2510 (define_insn "*store_multiple_di"
2511 [(match_parallel 0 "store_multiple_operation"
2512 [(set (match_operand:DI 1 "s_operand" "=QS")
2513 (match_operand:DI 2 "register_operand" "r"))])]
2514 "reload_completed && TARGET_ZARCH"
2516 int words = XVECLEN (operands[0], 0);
2517 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2518 return "stmg\t%2,%0,%S1";
2520 [(set_attr "op_type" "RSY")
2521 (set_attr "type" "stm")])
2524 (define_insn "*store_multiple_si"
2525 [(match_parallel 0 "store_multiple_operation"
2526 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2527 (match_operand:SI 2 "register_operand" "r,r"))])]
2530 int words = XVECLEN (operands[0], 0);
2531 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2532 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2534 [(set_attr "op_type" "RS,RSY")
2535 (set_attr "type" "stm")])
2538 ;; String instructions.
2541 (define_insn "*execute_rl"
2542 [(match_parallel 0 "execute_operation"
2543 [(unspec [(match_operand 1 "register_operand" "a")
2544 (match_operand 2 "" "")
2545 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2546 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2547 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2549 [(set_attr "op_type" "RIL")
2550 (set_attr "type" "cs")])
2552 (define_insn "*execute"
2553 [(match_parallel 0 "execute_operation"
2554 [(unspec [(match_operand 1 "register_operand" "a")
2555 (match_operand:BLK 2 "memory_operand" "R")
2556 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2557 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2558 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2560 [(set_attr "op_type" "RX")
2561 (set_attr "type" "cs")])
2565 ; strlenM instruction pattern(s).
2568 (define_expand "strlen<mode>"
2569 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2572 (unspec:P [(const_int 0)
2573 (match_operand:BLK 1 "memory_operand" "")
2575 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2576 (clobber (scratch:P))
2577 (clobber (reg:CC CC_REGNUM))])
2579 [(set (match_operand:P 0 "register_operand" "")
2580 (minus:P (match_dup 4) (match_dup 5)))
2581 (clobber (reg:CC CC_REGNUM))])]
2584 operands[4] = gen_reg_rtx (Pmode);
2585 operands[5] = gen_reg_rtx (Pmode);
2586 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2587 operands[1] = replace_equiv_address (operands[1], operands[5]);
2590 (define_insn "*strlen<mode>"
2591 [(set (match_operand:P 0 "register_operand" "=a")
2592 (unspec:P [(match_operand:P 2 "general_operand" "0")
2593 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2595 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2596 (clobber (match_scratch:P 1 "=a"))
2597 (clobber (reg:CC CC_REGNUM))]
2599 "srst\t%0,%1\;jo\t.-4"
2600 [(set_attr "length" "8")
2601 (set_attr "type" "vs")])
2604 ; cmpstrM instruction pattern(s).
2607 (define_expand "cmpstrsi"
2608 [(set (reg:SI 0) (const_int 0))
2610 [(clobber (match_operand 3 "" ""))
2611 (clobber (match_dup 4))
2612 (set (reg:CCU CC_REGNUM)
2613 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2614 (match_operand:BLK 2 "memory_operand" "")))
2617 [(set (match_operand:SI 0 "register_operand" "=d")
2618 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2619 (clobber (reg:CC CC_REGNUM))])]
2622 /* As the result of CMPINT is inverted compared to what we need,
2623 we have to swap the operands. */
2624 rtx op1 = operands[2];
2625 rtx op2 = operands[1];
2626 rtx addr1 = gen_reg_rtx (Pmode);
2627 rtx addr2 = gen_reg_rtx (Pmode);
2629 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2630 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2631 operands[1] = replace_equiv_address_nv (op1, addr1);
2632 operands[2] = replace_equiv_address_nv (op2, addr2);
2633 operands[3] = addr1;
2634 operands[4] = addr2;
2637 (define_insn "*cmpstr<mode>"
2638 [(clobber (match_operand:P 0 "register_operand" "=d"))
2639 (clobber (match_operand:P 1 "register_operand" "=d"))
2640 (set (reg:CCU CC_REGNUM)
2641 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2642 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2645 "clst\t%0,%1\;jo\t.-4"
2646 [(set_attr "length" "8")
2647 (set_attr "type" "vs")])
2650 ; movstr instruction pattern.
2653 (define_expand "movstr"
2654 [(set (reg:SI 0) (const_int 0))
2656 [(clobber (match_dup 3))
2657 (set (match_operand:BLK 1 "memory_operand" "")
2658 (match_operand:BLK 2 "memory_operand" ""))
2659 (set (match_operand 0 "register_operand" "")
2660 (unspec [(match_dup 1)
2662 (reg:SI 0)] UNSPEC_MVST))
2663 (clobber (reg:CC CC_REGNUM))])]
2666 rtx addr1 = gen_reg_rtx (Pmode);
2667 rtx addr2 = gen_reg_rtx (Pmode);
2669 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2670 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2671 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2672 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2673 operands[3] = addr2;
2676 (define_insn "*movstr"
2677 [(clobber (match_operand:P 2 "register_operand" "=d"))
2678 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2679 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2680 (set (match_operand:P 0 "register_operand" "=d")
2681 (unspec [(mem:BLK (match_dup 1))
2682 (mem:BLK (match_dup 3))
2683 (reg:SI 0)] UNSPEC_MVST))
2684 (clobber (reg:CC CC_REGNUM))]
2686 "mvst\t%1,%2\;jo\t.-4"
2687 [(set_attr "length" "8")
2688 (set_attr "type" "vs")])
2692 ; movmemM instruction pattern(s).
2695 (define_expand "movmem<mode>"
2696 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2697 (match_operand:BLK 1 "memory_operand" "")) ; source
2698 (use (match_operand:GPR 2 "general_operand" "")) ; count
2699 (match_operand 3 "" "")]
2702 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2708 ; Move a block that is up to 256 bytes in length.
2709 ; The block length is taken as (operands[2] % 256) + 1.
2711 (define_expand "movmem_short"
2713 [(set (match_operand:BLK 0 "memory_operand" "")
2714 (match_operand:BLK 1 "memory_operand" ""))
2715 (use (match_operand 2 "nonmemory_operand" ""))
2716 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2717 (clobber (match_dup 3))])]
2719 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2721 (define_insn "*movmem_short"
2722 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2723 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2724 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2725 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2726 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2727 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2729 [(set_attr "type" "cs")
2730 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2733 [(set (match_operand:BLK 0 "memory_operand" "")
2734 (match_operand:BLK 1 "memory_operand" ""))
2735 (use (match_operand 2 "const_int_operand" ""))
2736 (use (match_operand 3 "immediate_operand" ""))
2737 (clobber (scratch))]
2740 [(set (match_dup 0) (match_dup 1))
2741 (use (match_dup 2))])]
2742 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2745 [(set (match_operand:BLK 0 "memory_operand" "")
2746 (match_operand:BLK 1 "memory_operand" ""))
2747 (use (match_operand 2 "register_operand" ""))
2748 (use (match_operand 3 "memory_operand" ""))
2749 (clobber (scratch))]
2752 [(unspec [(match_dup 2) (match_dup 3)
2753 (const_int 0)] UNSPEC_EXECUTE)
2754 (set (match_dup 0) (match_dup 1))
2755 (use (const_int 1))])]
2759 [(set (match_operand:BLK 0 "memory_operand" "")
2760 (match_operand:BLK 1 "memory_operand" ""))
2761 (use (match_operand 2 "register_operand" ""))
2762 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2763 (clobber (scratch))]
2764 "TARGET_Z10 && reload_completed"
2766 [(unspec [(match_dup 2) (const_int 0)
2767 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2768 (set (match_dup 0) (match_dup 1))
2769 (use (const_int 1))])]
2770 "operands[3] = gen_label_rtx ();")
2773 [(set (match_operand:BLK 0 "memory_operand" "")
2774 (match_operand:BLK 1 "memory_operand" ""))
2775 (use (match_operand 2 "register_operand" ""))
2776 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2777 (clobber (match_operand 3 "register_operand" ""))]
2778 "reload_completed && TARGET_CPU_ZARCH"
2779 [(set (match_dup 3) (label_ref (match_dup 4)))
2781 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2782 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2783 (set (match_dup 0) (match_dup 1))
2784 (use (const_int 1))])]
2785 "operands[4] = gen_label_rtx ();")
2787 ; Move a block of arbitrary length.
2789 (define_expand "movmem_long"
2791 [(clobber (match_dup 2))
2792 (clobber (match_dup 3))
2793 (set (match_operand:BLK 0 "memory_operand" "")
2794 (match_operand:BLK 1 "memory_operand" ""))
2795 (use (match_operand 2 "general_operand" ""))
2797 (clobber (reg:CC CC_REGNUM))])]
2800 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2801 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2802 rtx reg0 = gen_reg_rtx (dreg_mode);
2803 rtx reg1 = gen_reg_rtx (dreg_mode);
2804 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2805 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2806 rtx len0 = gen_lowpart (Pmode, reg0);
2807 rtx len1 = gen_lowpart (Pmode, reg1);
2809 emit_clobber (reg0);
2810 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2811 emit_move_insn (len0, operands[2]);
2813 emit_clobber (reg1);
2814 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2815 emit_move_insn (len1, operands[2]);
2817 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2818 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2823 (define_insn "*movmem_long"
2824 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2825 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2826 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2827 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2830 (clobber (reg:CC CC_REGNUM))]
2831 "TARGET_64BIT || !TARGET_ZARCH"
2832 "mvcle\t%0,%1,0\;jo\t.-4"
2833 [(set_attr "length" "8")
2834 (set_attr "type" "vs")])
2836 (define_insn "*movmem_long_31z"
2837 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2838 (clobber (match_operand:TI 1 "register_operand" "=d"))
2839 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2840 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2843 (clobber (reg:CC CC_REGNUM))]
2844 "!TARGET_64BIT && TARGET_ZARCH"
2845 "mvcle\t%0,%1,0\;jo\t.-4"
2846 [(set_attr "length" "8")
2847 (set_attr "type" "vs")])
2854 (define_expand "signbit<mode>2"
2855 [(set (reg:CCZ CC_REGNUM)
2856 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2859 (set (match_operand:SI 0 "register_operand" "=d")
2860 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2863 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2866 (define_expand "isinf<mode>2"
2867 [(set (reg:CCZ CC_REGNUM)
2868 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2871 (set (match_operand:SI 0 "register_operand" "=d")
2872 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2875 operands[2] = GEN_INT (S390_TDC_INFINITY);
2878 (define_insn_and_split "*cc_to_int"
2879 [(set (match_operand:SI 0 "register_operand" "=d")
2880 (unspec:SI [(match_operand 1 "register_operand" "0")]
2885 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2887 ; This insn is used to generate all variants of the Test Data Class
2888 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2889 ; is the register to be tested and the second one is the bit mask
2890 ; specifying the required test(s).
2892 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2893 (define_insn "*TDC_insn_<mode>"
2894 [(set (reg:CCZ CC_REGNUM)
2895 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2896 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2898 "t<_d>c<xde><bt>\t%0,%1"
2899 [(set_attr "op_type" "RXE")
2900 (set_attr "type" "fsimp<mode>")])
2905 ; setmemM instruction pattern(s).
2908 (define_expand "setmem<mode>"
2909 [(set (match_operand:BLK 0 "memory_operand" "")
2910 (match_operand:QI 2 "general_operand" ""))
2911 (use (match_operand:GPR 1 "general_operand" ""))
2912 (match_operand 3 "" "")]
2914 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2916 ; Clear a block that is up to 256 bytes in length.
2917 ; The block length is taken as (operands[1] % 256) + 1.
2919 (define_expand "clrmem_short"
2921 [(set (match_operand:BLK 0 "memory_operand" "")
2923 (use (match_operand 1 "nonmemory_operand" ""))
2924 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2925 (clobber (match_dup 2))
2926 (clobber (reg:CC CC_REGNUM))])]
2928 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2930 (define_insn "*clrmem_short"
2931 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2933 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2934 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2935 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2936 (clobber (reg:CC CC_REGNUM))]
2937 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2939 [(set_attr "type" "cs")
2940 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2943 [(set (match_operand:BLK 0 "memory_operand" "")
2945 (use (match_operand 1 "const_int_operand" ""))
2946 (use (match_operand 2 "immediate_operand" ""))
2948 (clobber (reg:CC CC_REGNUM))]
2951 [(set (match_dup 0) (const_int 0))
2953 (clobber (reg:CC CC_REGNUM))])]
2954 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2957 [(set (match_operand:BLK 0 "memory_operand" "")
2959 (use (match_operand 1 "register_operand" ""))
2960 (use (match_operand 2 "memory_operand" ""))
2962 (clobber (reg:CC CC_REGNUM))]
2965 [(unspec [(match_dup 1) (match_dup 2)
2966 (const_int 0)] UNSPEC_EXECUTE)
2967 (set (match_dup 0) (const_int 0))
2969 (clobber (reg:CC CC_REGNUM))])]
2973 [(set (match_operand:BLK 0 "memory_operand" "")
2975 (use (match_operand 1 "register_operand" ""))
2976 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2978 (clobber (reg:CC CC_REGNUM))]
2979 "TARGET_Z10 && reload_completed"
2981 [(unspec [(match_dup 1) (const_int 0)
2982 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2983 (set (match_dup 0) (const_int 0))
2985 (clobber (reg:CC CC_REGNUM))])]
2986 "operands[3] = gen_label_rtx ();")
2989 [(set (match_operand:BLK 0 "memory_operand" "")
2991 (use (match_operand 1 "register_operand" ""))
2992 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2993 (clobber (match_operand 2 "register_operand" ""))
2994 (clobber (reg:CC CC_REGNUM))]
2995 "reload_completed && TARGET_CPU_ZARCH"
2996 [(set (match_dup 2) (label_ref (match_dup 3)))
2998 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2999 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3000 (set (match_dup 0) (const_int 0))
3002 (clobber (reg:CC CC_REGNUM))])]
3003 "operands[3] = gen_label_rtx ();")
3005 ; Initialize a block of arbitrary length with (operands[2] % 256).
3007 (define_expand "setmem_long"
3009 [(clobber (match_dup 1))
3010 (set (match_operand:BLK 0 "memory_operand" "")
3011 (match_operand 2 "shift_count_or_setmem_operand" ""))
3012 (use (match_operand 1 "general_operand" ""))
3014 (clobber (reg:CC CC_REGNUM))])]
3017 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3018 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3019 rtx reg0 = gen_reg_rtx (dreg_mode);
3020 rtx reg1 = gen_reg_rtx (dreg_mode);
3021 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3022 rtx len0 = gen_lowpart (Pmode, reg0);
3024 emit_clobber (reg0);
3025 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3026 emit_move_insn (len0, operands[1]);
3028 emit_move_insn (reg1, const0_rtx);
3030 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3035 (define_insn "*setmem_long"
3036 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3037 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3038 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3040 (use (match_operand:<DBL> 1 "register_operand" "d"))
3041 (clobber (reg:CC CC_REGNUM))]
3042 "TARGET_64BIT || !TARGET_ZARCH"
3043 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3044 [(set_attr "length" "8")
3045 (set_attr "type" "vs")])
3047 (define_insn "*setmem_long_and"
3048 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3049 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3050 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3051 (match_operand 4 "const_int_operand" "n")))
3053 (use (match_operand:<DBL> 1 "register_operand" "d"))
3054 (clobber (reg:CC CC_REGNUM))]
3055 "(TARGET_64BIT || !TARGET_ZARCH) &&
3056 (INTVAL (operands[4]) & 255) == 255"
3057 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3058 [(set_attr "length" "8")
3059 (set_attr "type" "vs")])
3061 (define_insn "*setmem_long_31z"
3062 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3063 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3064 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3066 (use (match_operand:TI 1 "register_operand" "d"))
3067 (clobber (reg:CC CC_REGNUM))]
3068 "!TARGET_64BIT && TARGET_ZARCH"
3069 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3070 [(set_attr "length" "8")
3071 (set_attr "type" "vs")])
3074 ; cmpmemM instruction pattern(s).
3077 (define_expand "cmpmemsi"
3078 [(set (match_operand:SI 0 "register_operand" "")
3079 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3080 (match_operand:BLK 2 "memory_operand" "") ) )
3081 (use (match_operand:SI 3 "general_operand" ""))
3082 (use (match_operand:SI 4 "" ""))]
3085 if (s390_expand_cmpmem (operands[0], operands[1],
3086 operands[2], operands[3]))
3092 ; Compare a block that is up to 256 bytes in length.
3093 ; The block length is taken as (operands[2] % 256) + 1.
3095 (define_expand "cmpmem_short"
3097 [(set (reg:CCU CC_REGNUM)
3098 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3099 (match_operand:BLK 1 "memory_operand" "")))
3100 (use (match_operand 2 "nonmemory_operand" ""))
3101 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3102 (clobber (match_dup 3))])]
3104 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3106 (define_insn "*cmpmem_short"
3107 [(set (reg:CCU CC_REGNUM)
3108 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3109 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3110 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3111 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3112 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3113 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3115 [(set_attr "type" "cs")
3116 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3119 [(set (reg:CCU CC_REGNUM)
3120 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3121 (match_operand:BLK 1 "memory_operand" "")))
3122 (use (match_operand 2 "const_int_operand" ""))
3123 (use (match_operand 3 "immediate_operand" ""))
3124 (clobber (scratch))]
3127 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3128 (use (match_dup 2))])]
3129 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3132 [(set (reg:CCU CC_REGNUM)
3133 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3134 (match_operand:BLK 1 "memory_operand" "")))
3135 (use (match_operand 2 "register_operand" ""))
3136 (use (match_operand 3 "memory_operand" ""))
3137 (clobber (scratch))]
3140 [(unspec [(match_dup 2) (match_dup 3)
3141 (const_int 0)] UNSPEC_EXECUTE)
3142 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3143 (use (const_int 1))])]
3147 [(set (reg:CCU CC_REGNUM)
3148 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3149 (match_operand:BLK 1 "memory_operand" "")))
3150 (use (match_operand 2 "register_operand" ""))
3151 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3152 (clobber (scratch))]
3153 "TARGET_Z10 && reload_completed"
3155 [(unspec [(match_dup 2) (const_int 0)
3156 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3157 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3158 (use (const_int 1))])]
3159 "operands[4] = gen_label_rtx ();")
3162 [(set (reg:CCU CC_REGNUM)
3163 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3164 (match_operand:BLK 1 "memory_operand" "")))
3165 (use (match_operand 2 "register_operand" ""))
3166 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3167 (clobber (match_operand 3 "register_operand" ""))]
3168 "reload_completed && TARGET_CPU_ZARCH"
3169 [(set (match_dup 3) (label_ref (match_dup 4)))
3171 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3172 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3173 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3174 (use (const_int 1))])]
3175 "operands[4] = gen_label_rtx ();")
3177 ; Compare a block of arbitrary length.
3179 (define_expand "cmpmem_long"
3181 [(clobber (match_dup 2))
3182 (clobber (match_dup 3))
3183 (set (reg:CCU CC_REGNUM)
3184 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3185 (match_operand:BLK 1 "memory_operand" "")))
3186 (use (match_operand 2 "general_operand" ""))
3187 (use (match_dup 3))])]
3190 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3191 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3192 rtx reg0 = gen_reg_rtx (dreg_mode);
3193 rtx reg1 = gen_reg_rtx (dreg_mode);
3194 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3195 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3196 rtx len0 = gen_lowpart (Pmode, reg0);
3197 rtx len1 = gen_lowpart (Pmode, reg1);
3199 emit_clobber (reg0);
3200 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3201 emit_move_insn (len0, operands[2]);
3203 emit_clobber (reg1);
3204 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3205 emit_move_insn (len1, operands[2]);
3207 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3208 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3213 (define_insn "*cmpmem_long"
3214 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3215 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3216 (set (reg:CCU CC_REGNUM)
3217 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3218 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3220 (use (match_dup 3))]
3221 "TARGET_64BIT || !TARGET_ZARCH"
3222 "clcle\t%0,%1,0\;jo\t.-4"
3223 [(set_attr "length" "8")
3224 (set_attr "type" "vs")])
3226 (define_insn "*cmpmem_long_31z"
3227 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3228 (clobber (match_operand:TI 1 "register_operand" "=d"))
3229 (set (reg:CCU CC_REGNUM)
3230 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3231 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3233 (use (match_dup 3))]
3234 "!TARGET_64BIT && TARGET_ZARCH"
3235 "clcle\t%0,%1,0\;jo\t.-4"
3236 [(set_attr "op_type" "NN")
3237 (set_attr "type" "vs")
3238 (set_attr "length" "8")])
3240 ; Convert CCUmode condition code to integer.
3241 ; Result is zero if EQ, positive if LTU, negative if GTU.
3243 (define_insn_and_split "cmpint"
3244 [(set (match_operand:SI 0 "register_operand" "=d")
3245 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3246 UNSPEC_STRCMPCC_TO_INT))
3247 (clobber (reg:CC CC_REGNUM))]
3251 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3253 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3254 (clobber (reg:CC CC_REGNUM))])])
3256 (define_insn_and_split "*cmpint_cc"
3257 [(set (reg CC_REGNUM)
3258 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3259 UNSPEC_STRCMPCC_TO_INT)
3261 (set (match_operand:SI 0 "register_operand" "=d")
3262 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3263 "s390_match_ccmode (insn, CCSmode)"
3265 "&& reload_completed"
3266 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3268 [(set (match_dup 2) (match_dup 3))
3269 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3271 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3272 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3273 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3276 (define_insn_and_split "*cmpint_sign"
3277 [(set (match_operand:DI 0 "register_operand" "=d")
3278 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3279 UNSPEC_STRCMPCC_TO_INT)))
3280 (clobber (reg:CC CC_REGNUM))]
3283 "&& reload_completed"
3284 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3286 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3287 (clobber (reg:CC CC_REGNUM))])])
3289 (define_insn_and_split "*cmpint_sign_cc"
3290 [(set (reg CC_REGNUM)
3291 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3292 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3293 UNSPEC_STRCMPCC_TO_INT) 0)
3294 (const_int 32)) (const_int 32))
3296 (set (match_operand:DI 0 "register_operand" "=d")
3297 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3298 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3300 "&& reload_completed"
3301 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3303 [(set (match_dup 2) (match_dup 3))
3304 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3306 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3307 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3308 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3313 ;;- Conversion instructions.
3316 (define_insn "*sethighpartsi"
3317 [(set (match_operand:SI 0 "register_operand" "=d,d")
3318 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3319 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3320 (clobber (reg:CC CC_REGNUM))]
3325 [(set_attr "op_type" "RS,RSY")
3326 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3328 (define_insn "*sethighpartdi_64"
3329 [(set (match_operand:DI 0 "register_operand" "=d")
3330 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3331 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3332 (clobber (reg:CC CC_REGNUM))]
3335 [(set_attr "op_type" "RSY")
3336 (set_attr "z10prop" "z10_super")])
3338 (define_insn "*sethighpartdi_31"
3339 [(set (match_operand:DI 0 "register_operand" "=d,d")
3340 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3341 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3342 (clobber (reg:CC CC_REGNUM))]
3347 [(set_attr "op_type" "RS,RSY")
3348 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3351 ; extv instruction patterns
3354 ; FIXME: This expander needs to be converted from DI to GPR as well
3355 ; after resolving some issues with it.
3357 (define_expand "extzv"
3359 [(set (match_operand:DI 0 "register_operand" "=d")
3361 (match_operand:DI 1 "register_operand" "d")
3362 (match_operand 2 "const_int_operand" "") ; size
3363 (match_operand 3 "const_int_operand" ""))) ; start
3364 (clobber (reg:CC CC_REGNUM))])]
3367 /* Starting with zEC12 there is risbgn not clobbering CC. */
3370 emit_move_insn (operands[0],
3371 gen_rtx_ZERO_EXTRACT (DImode,
3379 (define_insn "*extzv<mode>_zEC12"
3380 [(set (match_operand:GPR 0 "register_operand" "=d")
3382 (match_operand:GPR 1 "register_operand" "d")
3383 (match_operand 2 "const_int_operand" "") ; size
3384 (match_operand 3 "const_int_operand" "")))] ; start]
3386 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3387 [(set_attr "op_type" "RIE")])
3389 (define_insn "*extzv<mode>_z10"
3390 [(set (match_operand:GPR 0 "register_operand" "=d")
3392 (match_operand:GPR 1 "register_operand" "d")
3393 (match_operand 2 "const_int_operand" "") ; size
3394 (match_operand 3 "const_int_operand" ""))) ; start
3395 (clobber (reg:CC CC_REGNUM))]
3397 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3398 [(set_attr "op_type" "RIE")
3399 (set_attr "z10prop" "z10_super_E1")])
3401 (define_insn_and_split "*pre_z10_extzv<mode>"
3402 [(set (match_operand:GPR 0 "register_operand" "=d")
3403 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3404 (match_operand 2 "nonzero_shift_count_operand" "")
3406 (clobber (reg:CC CC_REGNUM))]
3409 "&& reload_completed"
3411 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3412 (clobber (reg:CC CC_REGNUM))])
3413 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3415 int bitsize = INTVAL (operands[2]);
3416 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3417 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3419 operands[1] = adjust_address (operands[1], BLKmode, 0);
3420 set_mem_size (operands[1], size);
3421 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3422 operands[3] = GEN_INT (mask);
3425 (define_insn_and_split "*pre_z10_extv<mode>"
3426 [(set (match_operand:GPR 0 "register_operand" "=d")
3427 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3428 (match_operand 2 "nonzero_shift_count_operand" "")
3430 (clobber (reg:CC CC_REGNUM))]
3433 "&& reload_completed"
3435 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3436 (clobber (reg:CC CC_REGNUM))])
3438 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3439 (clobber (reg:CC CC_REGNUM))])]
3441 int bitsize = INTVAL (operands[2]);
3442 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3443 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3445 operands[1] = adjust_address (operands[1], BLKmode, 0);
3446 set_mem_size (operands[1], size);
3447 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3448 operands[3] = GEN_INT (mask);
3452 ; insv instruction patterns
3455 (define_expand "insv"
3456 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3457 (match_operand 1 "const_int_operand" "")
3458 (match_operand 2 "const_int_operand" ""))
3459 (match_operand 3 "general_operand" ""))]
3462 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3468 ; The normal RTL expansion will never generate a zero_extract where
3469 ; the location operand isn't word mode. However, we do this in the
3470 ; back-end when generating atomic operations. See s390_two_part_insv.
3471 (define_insn "*insv<mode>_zEC12"
3472 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3473 (match_operand 1 "const_int_operand" "I") ; size
3474 (match_operand 2 "const_int_operand" "I")) ; pos
3475 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3477 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3478 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3479 [(set_attr "op_type" "RIE")])
3481 (define_insn "*insv<mode>_z10"
3482 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3483 (match_operand 1 "const_int_operand" "I") ; size
3484 (match_operand 2 "const_int_operand" "I")) ; pos
3485 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3486 (clobber (reg:CC CC_REGNUM))]
3488 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3489 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3490 [(set_attr "op_type" "RIE")
3491 (set_attr "z10prop" "z10_super_E1")])
3493 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3494 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3495 (define_insn "*insv<mode>_zEC12_noshift"
3496 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3497 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3498 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3499 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3500 (match_operand:GPR 4 "const_int_operand" ""))))]
3501 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3502 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3503 [(set_attr "op_type" "RIE")])
3505 (define_insn "*insv<mode>_z10_noshift"
3506 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3507 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3508 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3509 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3510 (match_operand:GPR 4 "const_int_operand" ""))))
3511 (clobber (reg:CC CC_REGNUM))]
3512 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3513 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3514 [(set_attr "op_type" "RIE")
3515 (set_attr "z10prop" "z10_super_E1")])
3517 (define_insn "*r<noxa>sbg_<mode>_noshift"
3518 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3520 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3521 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3522 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3523 (clobber (reg:CC CC_REGNUM))]
3525 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3526 [(set_attr "op_type" "RIE")])
3528 (define_insn "*r<noxa>sbg_di_rotl"
3529 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3533 (match_operand:DI 1 "nonimmediate_operand" "d")
3534 (match_operand:DI 3 "const_int_operand" ""))
3535 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3536 (match_operand:DI 4 "nonimmediate_operand" "0")))
3537 (clobber (reg:CC CC_REGNUM))]
3539 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3540 [(set_attr "op_type" "RIE")])
3542 (define_insn "*r<noxa>sbg_<mode>_srl"
3543 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3547 (match_operand:GPR 1 "nonimmediate_operand" "d")
3548 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3549 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3550 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3551 (clobber (reg:CC CC_REGNUM))]
3553 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3554 INTVAL (operands[2]))"
3555 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3556 [(set_attr "op_type" "RIE")])
3558 (define_insn "*r<noxa>sbg_<mode>_sll"
3559 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3563 (match_operand:GPR 1 "nonimmediate_operand" "d")
3564 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3565 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3566 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3567 (clobber (reg:CC CC_REGNUM))]
3569 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3570 INTVAL (operands[2]))"
3571 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3572 [(set_attr "op_type" "RIE")])
3574 ;; These two are generated by combine for s.bf &= val.
3575 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3576 ;; shifts and ands, which results in some truly awful patterns
3577 ;; including subregs of operations. Rather unnecessisarily, IMO.
3580 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3581 ;; (const_int 24 [0x18])
3582 ;; (const_int 0 [0]))
3583 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3584 ;; (const_int 40 [0x28])) 4)
3585 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3587 ;; we should instead generate
3589 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3590 ;; (const_int 24 [0x18])
3591 ;; (const_int 0 [0]))
3592 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3593 ;; (const_int 40 [0x28]))
3594 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3596 ;; by noticing that we can push down the outer paradoxical subreg
3597 ;; into the operation.
3599 (define_insn "*insv_rnsbg_noshift"
3600 [(set (zero_extract:DI
3601 (match_operand:DI 0 "nonimmediate_operand" "+d")
3602 (match_operand 1 "const_int_operand" "")
3603 (match_operand 2 "const_int_operand" ""))
3606 (match_operand:DI 3 "nonimmediate_operand" "d")))
3607 (clobber (reg:CC CC_REGNUM))]
3609 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3610 "rnsbg\t%0,%3,%2,63,0"
3611 [(set_attr "op_type" "RIE")])
3613 (define_insn "*insv_rnsbg_srl"
3614 [(set (zero_extract:DI
3615 (match_operand:DI 0 "nonimmediate_operand" "+d")
3616 (match_operand 1 "const_int_operand" "")
3617 (match_operand 2 "const_int_operand" ""))
3621 (match_operand 3 "const_int_operand" ""))
3622 (match_operand:DI 4 "nonimmediate_operand" "d")))
3623 (clobber (reg:CC CC_REGNUM))]
3625 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3626 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3627 [(set_attr "op_type" "RIE")])
3629 (define_insn "*insv<mode>_mem_reg"
3630 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3631 (match_operand 1 "const_int_operand" "n,n")
3633 (match_operand:W 2 "register_operand" "d,d"))]
3634 "INTVAL (operands[1]) > 0
3635 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3636 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3638 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3640 operands[1] = GEN_INT ((1ul << size) - 1);
3641 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3642 : "stcmy\t%2,%1,%S0";
3644 [(set_attr "op_type" "RS,RSY")
3645 (set_attr "z10prop" "z10_super,z10_super")])
3647 (define_insn "*insvdi_mem_reghigh"
3648 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3649 (match_operand 1 "const_int_operand" "n")
3651 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3654 && INTVAL (operands[1]) > 0
3655 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3656 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3658 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3660 operands[1] = GEN_INT ((1ul << size) - 1);
3661 return "stcmh\t%2,%1,%S0";
3663 [(set_attr "op_type" "RSY")
3664 (set_attr "z10prop" "z10_super")])
3666 (define_insn "*insvdi_reg_imm"
3667 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3669 (match_operand 1 "const_int_operand" "n"))
3670 (match_operand:DI 2 "const_int_operand" "n"))]
3672 && INTVAL (operands[1]) >= 0
3673 && INTVAL (operands[1]) < BITS_PER_WORD
3674 && INTVAL (operands[1]) % 16 == 0"
3676 switch (BITS_PER_WORD - INTVAL (operands[1]))
3678 case 64: return "iihh\t%0,%x2"; break;
3679 case 48: return "iihl\t%0,%x2"; break;
3680 case 32: return "iilh\t%0,%x2"; break;
3681 case 16: return "iill\t%0,%x2"; break;
3682 default: gcc_unreachable();
3685 [(set_attr "op_type" "RI")
3686 (set_attr "z10prop" "z10_super_E1")])
3688 ; Update the left-most 32 bit of a DI.
3689 (define_insn "*insv_h_di_reg_extimm"
3690 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3693 (match_operand:DI 1 "const_int_operand" "n"))]
3696 [(set_attr "op_type" "RIL")
3697 (set_attr "z10prop" "z10_fwd_E1")])
3699 ; Update the right-most 32 bit of a DI.
3700 (define_insn "*insv_l_di_reg_extimm"
3701 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3704 (match_operand:DI 1 "const_int_operand" "n"))]
3707 [(set_attr "op_type" "RIL")
3708 (set_attr "z10prop" "z10_fwd_A1")])
3711 ; extendsidi2 instruction pattern(s).
3714 (define_expand "extendsidi2"
3715 [(set (match_operand:DI 0 "register_operand" "")
3716 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3721 emit_clobber (operands[0]);
3722 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3723 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3724 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3729 (define_insn "*extendsidi2"
3730 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3731 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3737 [(set_attr "op_type" "RRE,RXY,RIL")
3738 (set_attr "type" "*,*,larl")
3739 (set_attr "cpu_facility" "*,*,z10")
3740 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3743 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3746 (define_expand "extend<HQI:mode><DSI:mode>2"
3747 [(set (match_operand:DSI 0 "register_operand" "")
3748 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3751 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3753 rtx tmp = gen_reg_rtx (SImode);
3754 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3755 emit_insn (gen_extendsidi2 (operands[0], tmp));
3758 else if (!TARGET_EXTIMM)
3760 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3762 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3763 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3764 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3770 ; extendhidi2 instruction pattern(s).
3773 (define_insn "*extendhidi2_extimm"
3774 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3775 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3776 "TARGET_ZARCH && TARGET_EXTIMM"
3781 [(set_attr "op_type" "RRE,RXY,RIL")
3782 (set_attr "type" "*,*,larl")
3783 (set_attr "cpu_facility" "extimm,extimm,z10")
3784 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3786 (define_insn "*extendhidi2"
3787 [(set (match_operand:DI 0 "register_operand" "=d")
3788 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3791 [(set_attr "op_type" "RXY")
3792 (set_attr "z10prop" "z10_super_E1")])
3795 ; extendhisi2 instruction pattern(s).
3798 (define_insn "*extendhisi2_extimm"
3799 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3800 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3807 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3808 (set_attr "type" "*,*,*,larl")
3809 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3810 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3812 (define_insn "*extendhisi2"
3813 [(set (match_operand:SI 0 "register_operand" "=d,d")
3814 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3819 [(set_attr "op_type" "RX,RXY")
3820 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3823 ; extendqi(si|di)2 instruction pattern(s).
3826 ; lbr, lgbr, lb, lgb
3827 (define_insn "*extendqi<mode>2_extimm"
3828 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3829 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3834 [(set_attr "op_type" "RRE,RXY")
3835 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3838 (define_insn "*extendqi<mode>2"
3839 [(set (match_operand:GPR 0 "register_operand" "=d")
3840 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3841 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3843 [(set_attr "op_type" "RXY")
3844 (set_attr "z10prop" "z10_super_E1")])
3846 (define_insn_and_split "*extendqi<mode>2_short_displ"
3847 [(set (match_operand:GPR 0 "register_operand" "=d")
3848 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3849 (clobber (reg:CC CC_REGNUM))]
3850 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3852 "&& reload_completed"
3854 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3855 (clobber (reg:CC CC_REGNUM))])
3857 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3858 (clobber (reg:CC CC_REGNUM))])]
3860 operands[1] = adjust_address (operands[1], BLKmode, 0);
3861 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3862 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3866 ; zero_extendsidi2 instruction pattern(s).
3869 (define_expand "zero_extendsidi2"
3870 [(set (match_operand:DI 0 "register_operand" "")
3871 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3876 emit_clobber (operands[0]);
3877 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3878 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3883 (define_insn "*zero_extendsidi2"
3884 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3885 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3891 [(set_attr "op_type" "RRE,RXY,RIL")
3892 (set_attr "type" "*,*,larl")
3893 (set_attr "cpu_facility" "*,*,z10")
3894 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3897 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3900 (define_insn "*llgt_sidi"
3901 [(set (match_operand:DI 0 "register_operand" "=d")
3902 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3903 (const_int 2147483647)))]
3906 [(set_attr "op_type" "RXE")
3907 (set_attr "z10prop" "z10_super_E1")])
3909 (define_insn_and_split "*llgt_sidi_split"
3910 [(set (match_operand:DI 0 "register_operand" "=d")
3911 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3912 (const_int 2147483647)))
3913 (clobber (reg:CC CC_REGNUM))]
3916 "&& reload_completed"
3918 (and:DI (subreg:DI (match_dup 1) 0)
3919 (const_int 2147483647)))]
3922 (define_insn "*llgt_sisi"
3923 [(set (match_operand:SI 0 "register_operand" "=d,d")
3924 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3925 (const_int 2147483647)))]
3930 [(set_attr "op_type" "RRE,RXE")
3931 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3933 (define_insn "*llgt_didi"
3934 [(set (match_operand:DI 0 "register_operand" "=d,d")
3935 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3936 (const_int 2147483647)))]
3941 [(set_attr "op_type" "RRE,RXE")
3942 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3945 [(set (match_operand:DSI 0 "register_operand" "")
3946 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3947 (const_int 2147483647)))
3948 (clobber (reg:CC CC_REGNUM))]
3949 "TARGET_ZARCH && reload_completed"
3951 (and:DSI (match_dup 1)
3952 (const_int 2147483647)))]
3956 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3959 (define_expand "zero_extend<mode>di2"
3960 [(set (match_operand:DI 0 "register_operand" "")
3961 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3966 rtx tmp = gen_reg_rtx (SImode);
3967 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3968 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3971 else if (!TARGET_EXTIMM)
3973 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
3974 operands[1] = gen_lowpart (DImode, operands[1]);
3975 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3976 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3981 (define_expand "zero_extend<mode>si2"
3982 [(set (match_operand:SI 0 "register_operand" "")
3983 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3988 operands[1] = gen_lowpart (SImode, operands[1]);
3989 emit_insn (gen_andsi3 (operands[0], operands[1],
3990 GEN_INT ((1 << <HQI:bitsize>) - 1)));
3996 (define_insn "*zero_extendhi<mode>2_z10"
3997 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3998 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4004 [(set_attr "op_type" "RXY,RRE,RIL")
4005 (set_attr "type" "*,*,larl")
4006 (set_attr "cpu_facility" "*,*,z10")
4007 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4009 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4010 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4011 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4012 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4017 [(set_attr "op_type" "RRE,RXY")
4018 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4021 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4022 [(set (match_operand:GPR 0 "register_operand" "=d")
4023 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4024 "TARGET_ZARCH && !TARGET_EXTIMM"
4026 [(set_attr "op_type" "RXY")
4027 (set_attr "z10prop" "z10_fwd_A3")])
4029 (define_insn_and_split "*zero_extendhisi2_31"
4030 [(set (match_operand:SI 0 "register_operand" "=&d")
4031 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4032 (clobber (reg:CC CC_REGNUM))]
4035 "&& reload_completed"
4036 [(set (match_dup 0) (const_int 0))
4038 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4039 (clobber (reg:CC CC_REGNUM))])]
4040 "operands[2] = gen_lowpart (HImode, operands[0]);")
4042 (define_insn_and_split "*zero_extendqisi2_31"
4043 [(set (match_operand:SI 0 "register_operand" "=&d")
4044 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4047 "&& reload_completed"
4048 [(set (match_dup 0) (const_int 0))
4049 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4050 "operands[2] = gen_lowpart (QImode, operands[0]);")
4053 ; zero_extendqihi2 instruction pattern(s).
4056 (define_expand "zero_extendqihi2"
4057 [(set (match_operand:HI 0 "register_operand" "")
4058 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4059 "TARGET_ZARCH && !TARGET_EXTIMM"
4061 operands[1] = gen_lowpart (HImode, operands[1]);
4062 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4066 (define_insn "*zero_extendqihi2_64"
4067 [(set (match_operand:HI 0 "register_operand" "=d")
4068 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4069 "TARGET_ZARCH && !TARGET_EXTIMM"
4071 [(set_attr "op_type" "RXY")
4072 (set_attr "z10prop" "z10_fwd_A3")])
4074 (define_insn_and_split "*zero_extendqihi2_31"
4075 [(set (match_operand:HI 0 "register_operand" "=&d")
4076 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4079 "&& reload_completed"
4080 [(set (match_dup 0) (const_int 0))
4081 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4082 "operands[2] = gen_lowpart (QImode, operands[0]);")
4085 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4088 (define_expand "fixuns_truncdddi2"
4090 [(set (match_operand:DI 0 "register_operand" "")
4091 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4092 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4093 (clobber (reg:CC CC_REGNUM))])]
4099 rtx label1 = gen_label_rtx ();
4100 rtx label2 = gen_label_rtx ();
4101 rtx temp = gen_reg_rtx (TDmode);
4102 REAL_VALUE_TYPE cmp, sub;
4104 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4105 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4107 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4108 solution is doing the check and the subtraction in TD mode and using a
4109 TD -> DI convert afterwards. */
4110 emit_insn (gen_extendddtd2 (temp, operands[1]));
4111 temp = force_reg (TDmode, temp);
4112 emit_cmp_and_jump_insns (temp,
4113 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4114 LT, NULL_RTX, VOIDmode, 0, label1);
4115 emit_insn (gen_subtd3 (temp, temp,
4116 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4117 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4120 emit_label (label1);
4121 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4122 emit_label (label2);
4127 (define_expand "fixuns_trunctddi2"
4129 [(set (match_operand:DI 0 "register_operand" "")
4130 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4131 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4132 (clobber (reg:CC CC_REGNUM))])]
4138 rtx label1 = gen_label_rtx ();
4139 rtx label2 = gen_label_rtx ();
4140 rtx temp = gen_reg_rtx (TDmode);
4141 REAL_VALUE_TYPE cmp, sub;
4143 operands[1] = force_reg (TDmode, operands[1]);
4144 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4145 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4147 emit_cmp_and_jump_insns (operands[1],
4148 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4149 LT, NULL_RTX, VOIDmode, 0, label1);
4150 emit_insn (gen_subtd3 (temp, operands[1],
4151 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4152 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4155 emit_label (label1);
4156 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4157 emit_label (label2);
4163 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4164 ; instruction pattern(s).
4167 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4169 [(set (match_operand:GPR 0 "register_operand" "")
4170 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4171 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4172 (clobber (reg:CC CC_REGNUM))])]
4177 rtx label1 = gen_label_rtx ();
4178 rtx label2 = gen_label_rtx ();
4179 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4180 REAL_VALUE_TYPE cmp, sub;
4182 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4183 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4184 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4186 emit_cmp_and_jump_insns (operands[1],
4187 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4188 LT, NULL_RTX, VOIDmode, 0, label1);
4189 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4190 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4191 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4195 emit_label (label1);
4196 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4197 operands[1], GEN_INT (5)));
4198 emit_label (label2);
4203 ; fixuns_trunc(td|dd)si2 expander
4204 (define_expand "fixuns_trunc<mode>si2"
4206 [(set (match_operand:SI 0 "register_operand" "")
4207 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4208 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4209 (clobber (reg:CC CC_REGNUM))])]
4210 "TARGET_Z196 && TARGET_HARD_DFP"
4213 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4215 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4216 ; clfdtr, clfxtr, clgdtr, clgxtr
4217 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4218 [(set (match_operand:GPR 0 "register_operand" "=r")
4219 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4220 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4221 (clobber (reg:CC CC_REGNUM))]
4223 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4224 [(set_attr "op_type" "RRF")
4225 (set_attr "type" "ftoi")])
4227 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4228 [(set (match_operand:GPR 0 "register_operand" "")
4229 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4232 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4237 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4238 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4239 [(set (match_operand:GPR 0 "register_operand" "=d")
4240 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4241 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4242 (clobber (reg:CC CC_REGNUM))]
4244 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4245 [(set_attr "op_type" "RRE")
4246 (set_attr "type" "ftoi")])
4250 ; fix_trunc(td|dd)di2 instruction pattern(s).
4253 (define_expand "fix_trunc<mode>di2"
4254 [(set (match_operand:DI 0 "register_operand" "")
4255 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4256 "TARGET_ZARCH && TARGET_HARD_DFP"
4258 operands[1] = force_reg (<MODE>mode, operands[1]);
4259 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4265 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4266 [(set (match_operand:DI 0 "register_operand" "=d")
4267 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4268 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4269 (clobber (reg:CC CC_REGNUM))]
4270 "TARGET_ZARCH && TARGET_HARD_DFP"
4271 "cg<DFP:xde>tr\t%0,%h2,%1"
4272 [(set_attr "op_type" "RRF")
4273 (set_attr "type" "ftoidfp")])
4277 ; fix_trunctf(si|di)2 instruction pattern(s).
4280 (define_expand "fix_trunctf<mode>2"
4281 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4282 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4283 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4284 (clobber (reg:CC CC_REGNUM))])]
4290 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4293 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4294 (define_insn "floatdi<mode>2"
4295 [(set (match_operand:FP 0 "register_operand" "=f")
4296 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4297 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4298 "c<xde>g<bt>r\t%0,%1"
4299 [(set_attr "op_type" "RRE")
4300 (set_attr "type" "itof<mode>" )])
4302 ; cxfbr, cdfbr, cefbr
4303 (define_insn "floatsi<mode>2"
4304 [(set (match_operand:BFP 0 "register_operand" "=f")
4305 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4308 [(set_attr "op_type" "RRE")
4309 (set_attr "type" "itof<mode>" )])
4312 (define_insn "floatsi<mode>2"
4313 [(set (match_operand:DFP 0 "register_operand" "=f")
4314 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4315 "TARGET_Z196 && TARGET_HARD_FLOAT"
4316 "c<xde>ftr\t%0,0,%1,0"
4317 [(set_attr "op_type" "RRE")
4318 (set_attr "type" "itof<mode>" )])
4321 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4324 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4325 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4326 (define_insn "floatuns<GPR:mode><FP:mode>2"
4327 [(set (match_operand:FP 0 "register_operand" "=f")
4328 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4329 "TARGET_Z196 && TARGET_HARD_FLOAT"
4330 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4331 [(set_attr "op_type" "RRE")
4332 (set_attr "type" "itof<FP:mode>" )])
4335 ; truncdfsf2 instruction pattern(s).
4338 (define_insn "truncdfsf2"
4339 [(set (match_operand:SF 0 "register_operand" "=f")
4340 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4343 [(set_attr "op_type" "RRE")
4344 (set_attr "type" "ftruncdf")])
4347 ; trunctf(df|sf)2 instruction pattern(s).
4351 (define_insn "trunctf<mode>2"
4352 [(set (match_operand:DSF 0 "register_operand" "=f")
4353 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4354 (clobber (match_scratch:TF 2 "=f"))]
4356 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4357 [(set_attr "length" "6")
4358 (set_attr "type" "ftrunctf")])
4361 ; trunctddd2 and truncddsd2 instruction pattern(s).
4364 (define_insn "trunctddd2"
4365 [(set (match_operand:DD 0 "register_operand" "=f")
4366 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4367 (clobber (match_scratch:TD 2 "=f"))]
4369 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4370 [(set_attr "length" "6")
4371 (set_attr "type" "ftruncdd")])
4373 (define_insn "truncddsd2"
4374 [(set (match_operand:SD 0 "register_operand" "=f")
4375 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4378 [(set_attr "op_type" "RRF")
4379 (set_attr "type" "ftruncsd")])
4382 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4385 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4386 (define_insn "extend<DSF:mode><BFP:mode>2"
4387 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4388 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4390 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4392 l<BFP:xde><DSF:xde>br\t%0,%1
4393 l<BFP:xde><DSF:xde>b\t%0,%1"
4394 [(set_attr "op_type" "RRE,RXE")
4395 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4398 ; extendddtd2 and extendsddd2 instruction pattern(s).
4401 (define_insn "extendddtd2"
4402 [(set (match_operand:TD 0 "register_operand" "=f")
4403 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4406 [(set_attr "op_type" "RRF")
4407 (set_attr "type" "fsimptf")])
4409 (define_insn "extendsddd2"
4410 [(set (match_operand:DD 0 "register_operand" "=f")
4411 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4414 [(set_attr "op_type" "RRF")
4415 (set_attr "type" "fsimptf")])
4417 ; Binary <-> Decimal floating point trunc patterns
4420 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4421 [(set (reg:DFP_ALL FPR0_REGNUM)
4422 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4423 (use (reg:SI GPR0_REGNUM))
4424 (clobber (reg:CC CC_REGNUM))]
4428 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4429 [(set (reg:BFP FPR0_REGNUM)
4430 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4431 (use (reg:SI GPR0_REGNUM))
4432 (clobber (reg:CC CC_REGNUM))]
4436 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4437 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4438 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4440 [(set (reg:DFP_ALL FPR0_REGNUM)
4441 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4442 (use (reg:SI GPR0_REGNUM))
4443 (clobber (reg:CC CC_REGNUM))])
4444 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4445 (reg:DFP_ALL FPR0_REGNUM))]
4447 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4449 HOST_WIDE_INT flags;
4451 flags = (PFPO_CONVERT |
4452 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4453 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4455 operands[2] = GEN_INT (flags);
4458 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4459 [(set (reg:DFP_ALL FPR4_REGNUM)
4460 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4461 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4463 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4464 (use (reg:SI GPR0_REGNUM))
4465 (clobber (reg:CC CC_REGNUM))])
4466 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4468 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4470 HOST_WIDE_INT flags;
4472 flags = (PFPO_CONVERT |
4473 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4474 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4476 operands[2] = GEN_INT (flags);
4480 ; Binary <-> Decimal floating point extend patterns
4483 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4484 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4485 (use (reg:SI GPR0_REGNUM))
4486 (clobber (reg:CC CC_REGNUM))]
4490 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4491 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4492 (use (reg:SI GPR0_REGNUM))
4493 (clobber (reg:CC CC_REGNUM))]
4497 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4498 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4499 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4501 [(set (reg:DFP_ALL FPR0_REGNUM)
4502 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4503 (use (reg:SI GPR0_REGNUM))
4504 (clobber (reg:CC CC_REGNUM))])
4505 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4506 (reg:DFP_ALL FPR0_REGNUM))]
4508 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4510 HOST_WIDE_INT flags;
4512 flags = (PFPO_CONVERT |
4513 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4514 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4516 operands[2] = GEN_INT (flags);
4519 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4520 [(set (reg:DFP_ALL FPR4_REGNUM)
4521 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4522 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4524 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4525 (use (reg:SI GPR0_REGNUM))
4526 (clobber (reg:CC CC_REGNUM))])
4527 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4529 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4531 HOST_WIDE_INT flags;
4533 flags = (PFPO_CONVERT |
4534 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4535 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4537 operands[2] = GEN_INT (flags);
4542 ;; ARITHMETIC OPERATIONS
4544 ; arithmetic operations set the ConditionCode,
4545 ; because of unpredictable Bits in Register for Halfword and Byte
4546 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4549 ;;- Add instructions.
4553 ; addti3 instruction pattern(s).
4556 (define_insn_and_split "addti3"
4557 [(set (match_operand:TI 0 "register_operand" "=&d")
4558 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4559 (match_operand:TI 2 "general_operand" "do") ) )
4560 (clobber (reg:CC CC_REGNUM))]
4563 "&& reload_completed"
4565 [(set (reg:CCL1 CC_REGNUM)
4566 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4568 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4570 [(set (match_dup 3) (plus:DI
4571 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4572 (match_dup 4)) (match_dup 5)))
4573 (clobber (reg:CC CC_REGNUM))])]
4574 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4575 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4576 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4577 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4578 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4579 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4582 ; adddi3 instruction pattern(s).
4585 (define_expand "adddi3"
4587 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4588 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4589 (match_operand:DI 2 "general_operand" "")))
4590 (clobber (reg:CC CC_REGNUM))])]
4594 (define_insn "*adddi3_sign"
4595 [(set (match_operand:DI 0 "register_operand" "=d,d")
4596 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4597 (match_operand:DI 1 "register_operand" "0,0")))
4598 (clobber (reg:CC CC_REGNUM))]
4603 [(set_attr "op_type" "RRE,RXY")
4604 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4606 (define_insn "*adddi3_zero_cc"
4607 [(set (reg CC_REGNUM)
4608 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4609 (match_operand:DI 1 "register_operand" "0,0"))
4611 (set (match_operand:DI 0 "register_operand" "=d,d")
4612 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4613 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4617 [(set_attr "op_type" "RRE,RXY")
4618 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4620 (define_insn "*adddi3_zero_cconly"
4621 [(set (reg CC_REGNUM)
4622 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4623 (match_operand:DI 1 "register_operand" "0,0"))
4625 (clobber (match_scratch:DI 0 "=d,d"))]
4626 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4630 [(set_attr "op_type" "RRE,RXY")
4631 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4633 (define_insn "*adddi3_zero"
4634 [(set (match_operand:DI 0 "register_operand" "=d,d")
4635 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4636 (match_operand:DI 1 "register_operand" "0,0")))
4637 (clobber (reg:CC CC_REGNUM))]
4642 [(set_attr "op_type" "RRE,RXY")
4643 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4645 (define_insn_and_split "*adddi3_31z"
4646 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4647 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4648 (match_operand:DI 2 "general_operand" "do") ) )
4649 (clobber (reg:CC CC_REGNUM))]
4650 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4652 "&& reload_completed"
4654 [(set (reg:CCL1 CC_REGNUM)
4655 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4657 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4659 [(set (match_dup 3) (plus:SI
4660 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4661 (match_dup 4)) (match_dup 5)))
4662 (clobber (reg:CC CC_REGNUM))])]
4663 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4664 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4665 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4666 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4667 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4668 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4670 (define_insn_and_split "*adddi3_31"
4671 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4672 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4673 (match_operand:DI 2 "general_operand" "do") ) )
4674 (clobber (reg:CC CC_REGNUM))]
4677 "&& reload_completed"
4679 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4680 (clobber (reg:CC CC_REGNUM))])
4682 [(set (reg:CCL1 CC_REGNUM)
4683 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4685 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4687 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4689 (label_ref (match_dup 9))))
4691 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4692 (clobber (reg:CC CC_REGNUM))])
4694 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4695 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4696 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4697 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4698 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4699 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4700 operands[9] = gen_label_rtx ();")
4703 ; addsi3 instruction pattern(s).
4706 (define_expand "addsi3"
4708 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4709 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4710 (match_operand:SI 2 "general_operand" "")))
4711 (clobber (reg:CC CC_REGNUM))])]
4715 (define_insn "*addsi3_sign"
4716 [(set (match_operand:SI 0 "register_operand" "=d,d")
4717 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4718 (match_operand:SI 1 "register_operand" "0,0")))
4719 (clobber (reg:CC CC_REGNUM))]
4724 [(set_attr "op_type" "RX,RXY")
4725 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4728 ; add(di|si)3 instruction pattern(s).
4731 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4732 (define_insn "*add<mode>3"
4733 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4734 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4735 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4736 (clobber (reg:CC CC_REGNUM))]
4748 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4749 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4750 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4751 z10_super_E1,z10_super_E1,z10_super_E1")])
4753 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4754 (define_insn "*add<mode>3_carry1_cc"
4755 [(set (reg CC_REGNUM)
4756 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4757 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4759 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4760 (plus:GPR (match_dup 1) (match_dup 2)))]
4761 "s390_match_ccmode (insn, CCL1mode)"
4767 al<g>hsik\t%0,%1,%h2
4771 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4772 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4773 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4774 z10_super_E1,z10_super_E1,z10_super_E1")])
4776 ; alr, al, aly, algr, alg, alrk, algrk
4777 (define_insn "*add<mode>3_carry1_cconly"
4778 [(set (reg CC_REGNUM)
4779 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4780 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4782 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4783 "s390_match_ccmode (insn, CCL1mode)"
4789 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4790 (set_attr "cpu_facility" "*,z196,*,*")
4791 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4793 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4794 (define_insn "*add<mode>3_carry2_cc"
4795 [(set (reg CC_REGNUM)
4796 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4797 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4799 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4800 (plus:GPR (match_dup 1) (match_dup 2)))]
4801 "s390_match_ccmode (insn, CCL1mode)"
4807 al<g>hsik\t%0,%1,%h2
4811 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4812 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4813 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4814 z10_super_E1,z10_super_E1,z10_super_E1")])
4816 ; alr, al, aly, algr, alg, alrk, algrk
4817 (define_insn "*add<mode>3_carry2_cconly"
4818 [(set (reg CC_REGNUM)
4819 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4820 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4822 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4823 "s390_match_ccmode (insn, CCL1mode)"
4829 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4830 (set_attr "cpu_facility" "*,z196,*,*")
4831 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4833 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4834 (define_insn "*add<mode>3_cc"
4835 [(set (reg CC_REGNUM)
4836 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4837 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4839 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4840 (plus:GPR (match_dup 1) (match_dup 2)))]
4841 "s390_match_ccmode (insn, CCLmode)"
4847 al<g>hsik\t%0,%1,%h2
4851 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4852 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4853 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4854 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4856 ; alr, al, aly, algr, alg, alrk, algrk
4857 (define_insn "*add<mode>3_cconly"
4858 [(set (reg CC_REGNUM)
4859 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4860 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4862 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4863 "s390_match_ccmode (insn, CCLmode)"
4869 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4870 (set_attr "cpu_facility" "*,z196,*,*")
4871 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4873 ; alr, al, aly, algr, alg, alrk, algrk
4874 (define_insn "*add<mode>3_cconly2"
4875 [(set (reg CC_REGNUM)
4876 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4877 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4878 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4879 "s390_match_ccmode(insn, CCLmode)"
4885 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4886 (set_attr "cpu_facility" "*,z196,*,*")
4887 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4889 ; ahi, afi, aghi, agfi, asi, agsi
4890 (define_insn "*add<mode>3_imm_cc"
4891 [(set (reg CC_REGNUM)
4892 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4893 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4895 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4896 (plus:GPR (match_dup 1) (match_dup 2)))]
4897 "s390_match_ccmode (insn, CCAmode)
4898 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4899 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4900 /* Avoid INT32_MIN on 32 bit. */
4901 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4907 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4908 (set_attr "cpu_facility" "*,z196,extimm,z10")
4909 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4912 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4915 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4916 (define_insn "add<mode>3"
4917 [(set (match_operand:FP 0 "register_operand" "=f, f")
4918 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4919 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4920 (clobber (reg:CC CC_REGNUM))]
4923 a<xde><bt>r\t%0,<op1>%2
4925 [(set_attr "op_type" "<RRer>,RXE")
4926 (set_attr "type" "fsimp<mode>")])
4928 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4929 (define_insn "*add<mode>3_cc"
4930 [(set (reg CC_REGNUM)
4931 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4932 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4933 (match_operand:FP 3 "const0_operand" "")))
4934 (set (match_operand:FP 0 "register_operand" "=f,f")
4935 (plus:FP (match_dup 1) (match_dup 2)))]
4936 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4938 a<xde><bt>r\t%0,<op1>%2
4940 [(set_attr "op_type" "<RRer>,RXE")
4941 (set_attr "type" "fsimp<mode>")])
4943 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4944 (define_insn "*add<mode>3_cconly"
4945 [(set (reg CC_REGNUM)
4946 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4947 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4948 (match_operand:FP 3 "const0_operand" "")))
4949 (clobber (match_scratch:FP 0 "=f,f"))]
4950 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4952 a<xde><bt>r\t%0,<op1>%2
4954 [(set_attr "op_type" "<RRer>,RXE")
4955 (set_attr "type" "fsimp<mode>")])
4959 ;;- Subtract instructions.
4963 ; subti3 instruction pattern(s).
4966 (define_insn_and_split "subti3"
4967 [(set (match_operand:TI 0 "register_operand" "=&d")
4968 (minus:TI (match_operand:TI 1 "register_operand" "0")
4969 (match_operand:TI 2 "general_operand" "do") ) )
4970 (clobber (reg:CC CC_REGNUM))]
4973 "&& reload_completed"
4975 [(set (reg:CCL2 CC_REGNUM)
4976 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4978 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4980 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4981 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4982 (clobber (reg:CC CC_REGNUM))])]
4983 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4984 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4985 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4986 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4987 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4988 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4991 ; subdi3 instruction pattern(s).
4994 (define_expand "subdi3"
4996 [(set (match_operand:DI 0 "register_operand" "")
4997 (minus:DI (match_operand:DI 1 "register_operand" "")
4998 (match_operand:DI 2 "general_operand" "")))
4999 (clobber (reg:CC CC_REGNUM))])]
5003 (define_insn "*subdi3_sign"
5004 [(set (match_operand:DI 0 "register_operand" "=d,d")
5005 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5006 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5007 (clobber (reg:CC CC_REGNUM))]
5012 [(set_attr "op_type" "RRE,RXY")
5013 (set_attr "z10prop" "z10_c,*")
5014 (set_attr "z196prop" "z196_cracked")])
5016 (define_insn "*subdi3_zero_cc"
5017 [(set (reg CC_REGNUM)
5018 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5019 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5021 (set (match_operand:DI 0 "register_operand" "=d,d")
5022 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5023 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5027 [(set_attr "op_type" "RRE,RXY")
5028 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5030 (define_insn "*subdi3_zero_cconly"
5031 [(set (reg CC_REGNUM)
5032 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5033 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5035 (clobber (match_scratch:DI 0 "=d,d"))]
5036 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5040 [(set_attr "op_type" "RRE,RXY")
5041 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5043 (define_insn "*subdi3_zero"
5044 [(set (match_operand:DI 0 "register_operand" "=d,d")
5045 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5046 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5047 (clobber (reg:CC CC_REGNUM))]
5052 [(set_attr "op_type" "RRE,RXY")
5053 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5055 (define_insn_and_split "*subdi3_31z"
5056 [(set (match_operand:DI 0 "register_operand" "=&d")
5057 (minus:DI (match_operand:DI 1 "register_operand" "0")
5058 (match_operand:DI 2 "general_operand" "do") ) )
5059 (clobber (reg:CC CC_REGNUM))]
5060 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5062 "&& reload_completed"
5064 [(set (reg:CCL2 CC_REGNUM)
5065 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5067 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5069 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5070 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5071 (clobber (reg:CC CC_REGNUM))])]
5072 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5073 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5074 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5075 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5076 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5077 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5079 (define_insn_and_split "*subdi3_31"
5080 [(set (match_operand:DI 0 "register_operand" "=&d")
5081 (minus:DI (match_operand:DI 1 "register_operand" "0")
5082 (match_operand:DI 2 "general_operand" "do") ) )
5083 (clobber (reg:CC CC_REGNUM))]
5086 "&& reload_completed"
5088 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5089 (clobber (reg:CC CC_REGNUM))])
5091 [(set (reg:CCL2 CC_REGNUM)
5092 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5094 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5096 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5098 (label_ref (match_dup 9))))
5100 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5101 (clobber (reg:CC CC_REGNUM))])
5103 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5104 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5105 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5106 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5107 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5108 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5109 operands[9] = gen_label_rtx ();")
5112 ; subsi3 instruction pattern(s).
5115 (define_expand "subsi3"
5117 [(set (match_operand:SI 0 "register_operand" "")
5118 (minus:SI (match_operand:SI 1 "register_operand" "")
5119 (match_operand:SI 2 "general_operand" "")))
5120 (clobber (reg:CC CC_REGNUM))])]
5124 (define_insn "*subsi3_sign"
5125 [(set (match_operand:SI 0 "register_operand" "=d,d")
5126 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5127 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5128 (clobber (reg:CC CC_REGNUM))]
5133 [(set_attr "op_type" "RX,RXY")
5134 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5137 ; sub(di|si)3 instruction pattern(s).
5140 ; sr, s, sy, sgr, sg, srk, sgrk
5141 (define_insn "*sub<mode>3"
5142 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5143 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5144 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5145 (clobber (reg:CC CC_REGNUM))]
5152 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5153 (set_attr "cpu_facility" "*,z196,*,*")
5154 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5156 ; slr, sl, sly, slgr, slg, slrk, slgrk
5157 (define_insn "*sub<mode>3_borrow_cc"
5158 [(set (reg CC_REGNUM)
5159 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5160 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5162 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5163 (minus:GPR (match_dup 1) (match_dup 2)))]
5164 "s390_match_ccmode (insn, CCL2mode)"
5170 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5171 (set_attr "cpu_facility" "*,z196,*,*")
5172 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5174 ; slr, sl, sly, slgr, slg, slrk, slgrk
5175 (define_insn "*sub<mode>3_borrow_cconly"
5176 [(set (reg CC_REGNUM)
5177 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5178 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5180 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5181 "s390_match_ccmode (insn, CCL2mode)"
5187 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5188 (set_attr "cpu_facility" "*,z196,*,*")
5189 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5191 ; slr, sl, sly, slgr, slg, slrk, slgrk
5192 (define_insn "*sub<mode>3_cc"
5193 [(set (reg CC_REGNUM)
5194 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5195 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5197 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5198 (minus:GPR (match_dup 1) (match_dup 2)))]
5199 "s390_match_ccmode (insn, CCLmode)"
5205 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5206 (set_attr "cpu_facility" "*,z196,*,*")
5207 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5209 ; slr, sl, sly, slgr, slg, slrk, slgrk
5210 (define_insn "*sub<mode>3_cc2"
5211 [(set (reg CC_REGNUM)
5212 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5213 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5214 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5215 (minus:GPR (match_dup 1) (match_dup 2)))]
5216 "s390_match_ccmode (insn, CCL3mode)"
5222 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5223 (set_attr "cpu_facility" "*,z196,*,*")
5224 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5226 ; slr, sl, sly, slgr, slg, slrk, slgrk
5227 (define_insn "*sub<mode>3_cconly"
5228 [(set (reg CC_REGNUM)
5229 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5230 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5232 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5233 "s390_match_ccmode (insn, CCLmode)"
5239 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5240 (set_attr "cpu_facility" "*,z196,*,*")
5241 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5244 ; slr, sl, sly, slgr, slg, slrk, slgrk
5245 (define_insn "*sub<mode>3_cconly2"
5246 [(set (reg CC_REGNUM)
5247 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5248 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5249 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5250 "s390_match_ccmode (insn, CCL3mode)"
5256 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5257 (set_attr "cpu_facility" "*,z196,*,*")
5258 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5262 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5265 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5266 (define_insn "sub<mode>3"
5267 [(set (match_operand:FP 0 "register_operand" "=f, f")
5268 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5269 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5270 (clobber (reg:CC CC_REGNUM))]
5273 s<xde><bt>r\t%0,<op1>%2
5275 [(set_attr "op_type" "<RRer>,RXE")
5276 (set_attr "type" "fsimp<mode>")])
5278 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5279 (define_insn "*sub<mode>3_cc"
5280 [(set (reg CC_REGNUM)
5281 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5282 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5283 (match_operand:FP 3 "const0_operand" "")))
5284 (set (match_operand:FP 0 "register_operand" "=f,f")
5285 (minus:FP (match_dup 1) (match_dup 2)))]
5286 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5288 s<xde><bt>r\t%0,<op1>%2
5290 [(set_attr "op_type" "<RRer>,RXE")
5291 (set_attr "type" "fsimp<mode>")])
5293 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5294 (define_insn "*sub<mode>3_cconly"
5295 [(set (reg CC_REGNUM)
5296 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5297 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5298 (match_operand:FP 3 "const0_operand" "")))
5299 (clobber (match_scratch:FP 0 "=f,f"))]
5300 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5302 s<xde><bt>r\t%0,<op1>%2
5304 [(set_attr "op_type" "<RRer>,RXE")
5305 (set_attr "type" "fsimp<mode>")])
5309 ;;- Conditional add/subtract instructions.
5313 ; add(di|si)cc instruction pattern(s).
5316 ; the following 4 patterns are used when the result of an add with
5317 ; carry is checked for an overflow condition
5319 ; op1 + op2 + c < op1
5321 ; alcr, alc, alcgr, alcg
5322 (define_insn "*add<mode>3_alc_carry1_cc"
5323 [(set (reg CC_REGNUM)
5325 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5326 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5327 (match_operand:GPR 2 "general_operand" "d,RT"))
5329 (set (match_operand:GPR 0 "register_operand" "=d,d")
5330 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5331 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5335 [(set_attr "op_type" "RRE,RXY")
5336 (set_attr "z196prop" "z196_alone,z196_alone")])
5338 ; alcr, alc, alcgr, alcg
5339 (define_insn "*add<mode>3_alc_carry1_cconly"
5340 [(set (reg CC_REGNUM)
5342 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5343 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5344 (match_operand:GPR 2 "general_operand" "d,RT"))
5346 (clobber (match_scratch:GPR 0 "=d,d"))]
5347 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5351 [(set_attr "op_type" "RRE,RXY")
5352 (set_attr "z196prop" "z196_alone,z196_alone")])
5354 ; op1 + op2 + c < op2
5356 ; alcr, alc, alcgr, alcg
5357 (define_insn "*add<mode>3_alc_carry2_cc"
5358 [(set (reg CC_REGNUM)
5360 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5361 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5362 (match_operand:GPR 2 "general_operand" "d,RT"))
5364 (set (match_operand:GPR 0 "register_operand" "=d,d")
5365 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5366 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5370 [(set_attr "op_type" "RRE,RXY")])
5372 ; alcr, alc, alcgr, alcg
5373 (define_insn "*add<mode>3_alc_carry2_cconly"
5374 [(set (reg CC_REGNUM)
5376 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5377 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5378 (match_operand:GPR 2 "general_operand" "d,RT"))
5380 (clobber (match_scratch:GPR 0 "=d,d"))]
5381 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5385 [(set_attr "op_type" "RRE,RXY")])
5387 ; alcr, alc, alcgr, alcg
5388 (define_insn "*add<mode>3_alc_cc"
5389 [(set (reg CC_REGNUM)
5391 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5392 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5393 (match_operand:GPR 2 "general_operand" "d,RT"))
5395 (set (match_operand:GPR 0 "register_operand" "=d,d")
5396 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5397 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5401 [(set_attr "op_type" "RRE,RXY")])
5403 ; alcr, alc, alcgr, alcg
5404 (define_insn "*add<mode>3_alc"
5405 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5406 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5407 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5408 (match_operand:GPR 2 "general_operand" "d,RT")))
5409 (clobber (reg:CC CC_REGNUM))]
5414 [(set_attr "op_type" "RRE,RXY")])
5416 ; slbr, slb, slbgr, slbg
5417 (define_insn "*sub<mode>3_slb_cc"
5418 [(set (reg CC_REGNUM)
5420 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5421 (match_operand:GPR 2 "general_operand" "d,RT"))
5422 (match_operand:GPR 3 "s390_slb_comparison" ""))
5424 (set (match_operand:GPR 0 "register_operand" "=d,d")
5425 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5426 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5430 [(set_attr "op_type" "RRE,RXY")
5431 (set_attr "z10prop" "z10_c,*")])
5433 ; slbr, slb, slbgr, slbg
5434 (define_insn "*sub<mode>3_slb"
5435 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5436 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5437 (match_operand:GPR 2 "general_operand" "d,RT"))
5438 (match_operand:GPR 3 "s390_slb_comparison" "")))
5439 (clobber (reg:CC CC_REGNUM))]
5444 [(set_attr "op_type" "RRE,RXY")
5445 (set_attr "z10prop" "z10_c,*")])
5447 (define_expand "add<mode>cc"
5448 [(match_operand:GPR 0 "register_operand" "")
5449 (match_operand 1 "comparison_operator" "")
5450 (match_operand:GPR 2 "register_operand" "")
5451 (match_operand:GPR 3 "const_int_operand" "")]
5453 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5454 XEXP (operands[1], 0), XEXP (operands[1], 1),
5455 operands[0], operands[2],
5456 operands[3])) FAIL; DONE;")
5459 ; scond instruction pattern(s).
5462 (define_insn_and_split "*scond<mode>"
5463 [(set (match_operand:GPR 0 "register_operand" "=&d")
5464 (match_operand:GPR 1 "s390_alc_comparison" ""))
5465 (clobber (reg:CC CC_REGNUM))]
5468 "&& reload_completed"
5469 [(set (match_dup 0) (const_int 0))
5471 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5473 (clobber (reg:CC CC_REGNUM))])]
5476 (define_insn_and_split "*scond<mode>_neg"
5477 [(set (match_operand:GPR 0 "register_operand" "=&d")
5478 (match_operand:GPR 1 "s390_slb_comparison" ""))
5479 (clobber (reg:CC CC_REGNUM))]
5482 "&& reload_completed"
5483 [(set (match_dup 0) (const_int 0))
5485 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5487 (clobber (reg:CC CC_REGNUM))])
5489 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5490 (clobber (reg:CC CC_REGNUM))])]
5494 (define_expand "cstore<mode>4"
5495 [(set (match_operand:SI 0 "register_operand" "")
5496 (match_operator:SI 1 "s390_scond_operator"
5497 [(match_operand:GPR 2 "register_operand" "")
5498 (match_operand:GPR 3 "general_operand" "")]))]
5500 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5501 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5503 (define_expand "cstorecc4"
5505 [(set (match_operand:SI 0 "register_operand" "")
5506 (match_operator:SI 1 "s390_eqne_operator"
5507 [(match_operand:CCZ1 2 "register_operand")
5508 (match_operand 3 "const0_operand")]))
5509 (clobber (reg:CC CC_REGNUM))])]
5511 "emit_insn (gen_sne (operands[0], operands[2]));
5512 if (GET_CODE (operands[1]) == EQ)
5513 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5516 (define_insn_and_split "sne"
5517 [(set (match_operand:SI 0 "register_operand" "=d")
5518 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5520 (clobber (reg:CC CC_REGNUM))]
5525 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5526 (clobber (reg:CC CC_REGNUM))])])
5530 ;; - Conditional move instructions (introduced with z196)
5533 (define_expand "mov<mode>cc"
5534 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5535 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5536 (match_operand:GPR 2 "nonimmediate_operand" "")
5537 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5539 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5540 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5542 ; locr, loc, stoc, locgr, locg, stocg
5543 (define_insn_and_split "*mov<mode>cc"
5544 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5546 (match_operator 1 "s390_comparison"
5547 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5548 (match_operand 5 "const_int_operand" "")])
5549 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5550 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5560 "&& reload_completed
5561 && MEM_P (operands[3]) && MEM_P (operands[4])"
5564 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5569 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5573 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5576 ;;- Multiply instructions.
5580 ; muldi3 instruction pattern(s).
5583 (define_insn "*muldi3_sign"
5584 [(set (match_operand:DI 0 "register_operand" "=d,d")
5585 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5586 (match_operand:DI 1 "register_operand" "0,0")))]
5591 [(set_attr "op_type" "RRE,RXY")
5592 (set_attr "type" "imuldi")])
5594 (define_insn "muldi3"
5595 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5596 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5597 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5604 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5605 (set_attr "type" "imuldi")
5606 (set_attr "cpu_facility" "*,*,*,z10")])
5609 ; mulsi3 instruction pattern(s).
5612 (define_insn "*mulsi3_sign"
5613 [(set (match_operand:SI 0 "register_operand" "=d,d")
5614 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5615 (match_operand:SI 1 "register_operand" "0,0")))]
5620 [(set_attr "op_type" "RX,RXY")
5621 (set_attr "type" "imulhi")
5622 (set_attr "cpu_facility" "*,z10")])
5624 (define_insn "mulsi3"
5625 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5626 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5627 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5635 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5636 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5637 (set_attr "cpu_facility" "*,*,*,*,z10")])
5640 ; mulsidi3 instruction pattern(s).
5643 (define_insn "mulsidi3"
5644 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5645 (mult:DI (sign_extend:DI
5646 (match_operand:SI 1 "register_operand" "%0,0,0"))
5648 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5654 [(set_attr "op_type" "RR,RX,RXY")
5655 (set_attr "type" "imulsi")
5656 (set_attr "cpu_facility" "*,*,z10")])
5659 ; umul instruction pattern(s).
5662 ; mlr, ml, mlgr, mlg
5663 (define_insn "umul<dwh><mode>3"
5664 [(set (match_operand:DW 0 "register_operand" "=d, d")
5665 (mult:DW (zero_extend:DW
5666 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5668 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5673 [(set_attr "op_type" "RRE,RXY")
5674 (set_attr "type" "imul<dwh>")])
5677 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5680 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5681 (define_insn "mul<mode>3"
5682 [(set (match_operand:FP 0 "register_operand" "=f,f")
5683 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5684 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5687 m<xdee><bt>r\t%0,<op1>%2
5689 [(set_attr "op_type" "<RRer>,RXE")
5690 (set_attr "type" "fmul<mode>")])
5692 ; madbr, maebr, maxb, madb, maeb
5693 (define_insn "fma<mode>4"
5694 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5695 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5696 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5697 (match_operand:DSF 3 "register_operand" "0,0")))]
5702 [(set_attr "op_type" "RRE,RXE")
5703 (set_attr "type" "fmadd<mode>")])
5705 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5706 (define_insn "fms<mode>4"
5707 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5708 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5709 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5710 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5715 [(set_attr "op_type" "RRE,RXE")
5716 (set_attr "type" "fmadd<mode>")])
5719 ;;- Divide and modulo instructions.
5723 ; divmoddi4 instruction pattern(s).
5726 (define_expand "divmoddi4"
5727 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5728 (div:DI (match_operand:DI 1 "register_operand" "")
5729 (match_operand:DI 2 "general_operand" "")))
5730 (set (match_operand:DI 3 "general_operand" "")
5731 (mod:DI (match_dup 1) (match_dup 2)))])
5732 (clobber (match_dup 4))]
5735 rtx insn, div_equal, mod_equal;
5737 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5738 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5740 operands[4] = gen_reg_rtx(TImode);
5741 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5743 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5744 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5746 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5747 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5752 (define_insn "divmodtidi3"
5753 [(set (match_operand:TI 0 "register_operand" "=d,d")
5757 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5758 (match_operand:DI 2 "general_operand" "d,RT")))
5760 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5765 [(set_attr "op_type" "RRE,RXY")
5766 (set_attr "type" "idiv")])
5768 (define_insn "divmodtisi3"
5769 [(set (match_operand:TI 0 "register_operand" "=d,d")
5773 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5775 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5778 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5783 [(set_attr "op_type" "RRE,RXY")
5784 (set_attr "type" "idiv")])
5787 ; udivmoddi4 instruction pattern(s).
5790 (define_expand "udivmoddi4"
5791 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5792 (udiv:DI (match_operand:DI 1 "general_operand" "")
5793 (match_operand:DI 2 "nonimmediate_operand" "")))
5794 (set (match_operand:DI 3 "general_operand" "")
5795 (umod:DI (match_dup 1) (match_dup 2)))])
5796 (clobber (match_dup 4))]
5799 rtx insn, div_equal, mod_equal, equal;
5801 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5802 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5803 equal = gen_rtx_IOR (TImode,
5804 gen_rtx_ASHIFT (TImode,
5805 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5807 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5809 operands[4] = gen_reg_rtx(TImode);
5810 emit_clobber (operands[4]);
5811 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5812 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5814 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5815 set_unique_reg_note (insn, REG_EQUAL, equal);
5817 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5818 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5820 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5821 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5826 (define_insn "udivmodtidi3"
5827 [(set (match_operand:TI 0 "register_operand" "=d,d")
5832 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5834 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5838 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5843 [(set_attr "op_type" "RRE,RXY")
5844 (set_attr "type" "idiv")])
5847 ; divmodsi4 instruction pattern(s).
5850 (define_expand "divmodsi4"
5851 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5852 (div:SI (match_operand:SI 1 "general_operand" "")
5853 (match_operand:SI 2 "nonimmediate_operand" "")))
5854 (set (match_operand:SI 3 "general_operand" "")
5855 (mod:SI (match_dup 1) (match_dup 2)))])
5856 (clobber (match_dup 4))]
5859 rtx insn, div_equal, mod_equal, equal;
5861 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5862 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5863 equal = gen_rtx_IOR (DImode,
5864 gen_rtx_ASHIFT (DImode,
5865 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5867 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5869 operands[4] = gen_reg_rtx(DImode);
5870 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5872 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5873 set_unique_reg_note (insn, REG_EQUAL, equal);
5875 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5876 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5878 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5879 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5884 (define_insn "divmoddisi3"
5885 [(set (match_operand:DI 0 "register_operand" "=d,d")
5890 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5892 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5896 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5901 [(set_attr "op_type" "RR,RX")
5902 (set_attr "type" "idiv")])
5905 ; udivsi3 and umodsi3 instruction pattern(s).
5908 (define_expand "udivmodsi4"
5909 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5910 (udiv:SI (match_operand:SI 1 "general_operand" "")
5911 (match_operand:SI 2 "nonimmediate_operand" "")))
5912 (set (match_operand:SI 3 "general_operand" "")
5913 (umod:SI (match_dup 1) (match_dup 2)))])
5914 (clobber (match_dup 4))]
5915 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5917 rtx insn, div_equal, mod_equal, equal;
5919 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5920 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5921 equal = gen_rtx_IOR (DImode,
5922 gen_rtx_ASHIFT (DImode,
5923 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5925 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5927 operands[4] = gen_reg_rtx(DImode);
5928 emit_clobber (operands[4]);
5929 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5930 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5932 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5933 set_unique_reg_note (insn, REG_EQUAL, equal);
5935 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5936 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5938 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5939 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5944 (define_insn "udivmoddisi3"
5945 [(set (match_operand:DI 0 "register_operand" "=d,d")
5950 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5952 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5956 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5957 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5961 [(set_attr "op_type" "RRE,RXY")
5962 (set_attr "type" "idiv")])
5964 (define_expand "udivsi3"
5965 [(set (match_operand:SI 0 "register_operand" "=d")
5966 (udiv:SI (match_operand:SI 1 "general_operand" "")
5967 (match_operand:SI 2 "general_operand" "")))
5968 (clobber (match_dup 3))]
5969 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5971 rtx insn, udiv_equal, umod_equal, equal;
5973 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5974 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5975 equal = gen_rtx_IOR (DImode,
5976 gen_rtx_ASHIFT (DImode,
5977 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5979 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5981 operands[3] = gen_reg_rtx (DImode);
5983 if (CONSTANT_P (operands[2]))
5985 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5987 rtx label1 = gen_label_rtx ();
5989 operands[1] = make_safe_from (operands[1], operands[0]);
5990 emit_move_insn (operands[0], const0_rtx);
5991 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5993 emit_move_insn (operands[0], const1_rtx);
5994 emit_label (label1);
5998 operands[2] = force_reg (SImode, operands[2]);
5999 operands[2] = make_safe_from (operands[2], operands[0]);
6001 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6002 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6004 set_unique_reg_note (insn, REG_EQUAL, equal);
6006 insn = emit_move_insn (operands[0],
6007 gen_lowpart (SImode, operands[3]));
6008 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6013 rtx label1 = gen_label_rtx ();
6014 rtx label2 = gen_label_rtx ();
6015 rtx label3 = gen_label_rtx ();
6017 operands[1] = force_reg (SImode, operands[1]);
6018 operands[1] = make_safe_from (operands[1], operands[0]);
6019 operands[2] = force_reg (SImode, operands[2]);
6020 operands[2] = make_safe_from (operands[2], operands[0]);
6022 emit_move_insn (operands[0], const0_rtx);
6023 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6025 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6027 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6029 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6030 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6032 set_unique_reg_note (insn, REG_EQUAL, equal);
6034 insn = emit_move_insn (operands[0],
6035 gen_lowpart (SImode, operands[3]));
6036 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6039 emit_label (label1);
6040 emit_move_insn (operands[0], operands[1]);
6042 emit_label (label2);
6043 emit_move_insn (operands[0], const1_rtx);
6044 emit_label (label3);
6046 emit_move_insn (operands[0], operands[0]);
6050 (define_expand "umodsi3"
6051 [(set (match_operand:SI 0 "register_operand" "=d")
6052 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6053 (match_operand:SI 2 "nonimmediate_operand" "")))
6054 (clobber (match_dup 3))]
6055 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6057 rtx insn, udiv_equal, umod_equal, equal;
6059 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6060 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6061 equal = gen_rtx_IOR (DImode,
6062 gen_rtx_ASHIFT (DImode,
6063 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6065 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6067 operands[3] = gen_reg_rtx (DImode);
6069 if (CONSTANT_P (operands[2]))
6071 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6073 rtx label1 = gen_label_rtx ();
6075 operands[1] = make_safe_from (operands[1], operands[0]);
6076 emit_move_insn (operands[0], operands[1]);
6077 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6079 emit_insn (gen_abssi2 (operands[0], operands[2]));
6080 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6081 emit_label (label1);
6085 operands[2] = force_reg (SImode, operands[2]);
6086 operands[2] = make_safe_from (operands[2], operands[0]);
6088 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6089 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6091 set_unique_reg_note (insn, REG_EQUAL, equal);
6093 insn = emit_move_insn (operands[0],
6094 gen_highpart (SImode, operands[3]));
6095 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6100 rtx label1 = gen_label_rtx ();
6101 rtx label2 = gen_label_rtx ();
6102 rtx label3 = gen_label_rtx ();
6104 operands[1] = force_reg (SImode, operands[1]);
6105 operands[1] = make_safe_from (operands[1], operands[0]);
6106 operands[2] = force_reg (SImode, operands[2]);
6107 operands[2] = make_safe_from (operands[2], operands[0]);
6109 emit_move_insn(operands[0], operands[1]);
6110 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6112 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6114 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6116 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6117 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6119 set_unique_reg_note (insn, REG_EQUAL, equal);
6121 insn = emit_move_insn (operands[0],
6122 gen_highpart (SImode, operands[3]));
6123 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6126 emit_label (label1);
6127 emit_move_insn (operands[0], const0_rtx);
6129 emit_label (label2);
6130 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6131 emit_label (label3);
6137 ; div(df|sf)3 instruction pattern(s).
6140 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6141 (define_insn "div<mode>3"
6142 [(set (match_operand:FP 0 "register_operand" "=f,f")
6143 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6144 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6147 d<xde><bt>r\t%0,<op1>%2
6149 [(set_attr "op_type" "<RRer>,RXE")
6150 (set_attr "type" "fdiv<mode>")])
6154 ;;- And instructions.
6157 (define_expand "and<mode>3"
6158 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6159 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6160 (match_operand:INT 2 "general_operand" "")))
6161 (clobber (reg:CC CC_REGNUM))]
6163 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6166 ; anddi3 instruction pattern(s).
6169 (define_insn "*anddi3_cc"
6170 [(set (reg CC_REGNUM)
6172 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6173 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6175 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6176 (and:DI (match_dup 1) (match_dup 2)))]
6177 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6182 risbg\t%0,%1,%s2,128+%e2,0"
6183 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6184 (set_attr "cpu_facility" "*,z196,*,z10")
6185 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6187 (define_insn "*anddi3_cconly"
6188 [(set (reg CC_REGNUM)
6190 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6191 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6193 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6195 && s390_match_ccmode(insn, CCTmode)
6196 /* Do not steal TM patterns. */
6197 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6202 risbg\t%0,%1,%s2,128+%e2,0"
6203 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6204 (set_attr "cpu_facility" "*,z196,*,z10")
6205 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6207 (define_insn "*anddi3"
6208 [(set (match_operand:DI 0 "nonimmediate_operand"
6209 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6211 (match_operand:DI 1 "nonimmediate_operand"
6212 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6213 (match_operand:DI 2 "general_operand"
6214 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6215 (clobber (reg:CC CC_REGNUM))]
6216 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6229 risbg\t%0,%1,%s2,128+%e2,0
6232 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6233 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6234 (set_attr "z10prop" "*,
6250 [(set (match_operand:DI 0 "s_operand" "")
6251 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6252 (clobber (reg:CC CC_REGNUM))]
6255 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6256 (clobber (reg:CC CC_REGNUM))])]
6257 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6259 ;; These two are what combine generates for (ashift (zero_extract)).
6260 (define_insn "*extzv_<mode>_srl"
6261 [(set (match_operand:GPR 0 "register_operand" "=d")
6262 (and:GPR (lshiftrt:GPR
6263 (match_operand:GPR 1 "register_operand" "d")
6264 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6265 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6266 (clobber (reg:CC CC_REGNUM))]
6268 /* Note that even for the SImode pattern, the rotate is always DImode. */
6269 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6270 INTVAL (operands[3]))"
6271 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6272 [(set_attr "op_type" "RIE")
6273 (set_attr "z10prop" "z10_super_E1")])
6275 (define_insn "*extzv_<mode>_sll"
6276 [(set (match_operand:GPR 0 "register_operand" "=d")
6277 (and:GPR (ashift:GPR
6278 (match_operand:GPR 1 "register_operand" "d")
6279 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6280 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6281 (clobber (reg:CC CC_REGNUM))]
6283 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6284 INTVAL (operands[3]))"
6285 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6286 [(set_attr "op_type" "RIE")
6287 (set_attr "z10prop" "z10_super_E1")])
6291 ; andsi3 instruction pattern(s).
6294 (define_insn "*andsi3_cc"
6295 [(set (reg CC_REGNUM)
6298 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6299 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6301 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6302 (and:SI (match_dup 1) (match_dup 2)))]
6303 "s390_match_ccmode(insn, CCTmode)"
6310 risbg\t%0,%1,%t2,128+%f2,0"
6311 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6312 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6313 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6314 z10_super_E1,z10_super_E1,z10_super_E1")])
6316 (define_insn "*andsi3_cconly"
6317 [(set (reg CC_REGNUM)
6320 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6321 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6323 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6324 "s390_match_ccmode(insn, CCTmode)
6325 /* Do not steal TM patterns. */
6326 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6333 risbg\t%0,%1,%t2,128+%f2,0"
6334 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6335 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6336 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6337 z10_super_E1,z10_super_E1,z10_super_E1")])
6339 (define_insn "*andsi3_zarch"
6340 [(set (match_operand:SI 0 "nonimmediate_operand"
6341 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6342 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6343 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6344 (match_operand:SI 2 "general_operand"
6345 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6346 (clobber (reg:CC CC_REGNUM))]
6347 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6358 risbg\t%0,%1,%t2,128+%f2,0
6361 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6362 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6363 (set_attr "z10prop" "*,
6376 (define_insn "*andsi3_esa"
6377 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6378 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6379 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6380 (clobber (reg:CC CC_REGNUM))]
6381 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6387 [(set_attr "op_type" "RR,RX,SI,SS")
6388 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6392 [(set (match_operand:SI 0 "s_operand" "")
6393 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6394 (clobber (reg:CC CC_REGNUM))]
6397 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6398 (clobber (reg:CC CC_REGNUM))])]
6399 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6402 ; andhi3 instruction pattern(s).
6405 (define_insn "*andhi3_zarch"
6406 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6407 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6408 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6409 (clobber (reg:CC CC_REGNUM))]
6410 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6417 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6418 (set_attr "cpu_facility" "*,z196,*,*,*")
6419 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6422 (define_insn "*andhi3_esa"
6423 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6424 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6425 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6426 (clobber (reg:CC CC_REGNUM))]
6427 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6432 [(set_attr "op_type" "RR,SI,SS")
6433 (set_attr "z10prop" "z10_super_E1,*,*")
6437 [(set (match_operand:HI 0 "s_operand" "")
6438 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6439 (clobber (reg:CC CC_REGNUM))]
6442 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6443 (clobber (reg:CC CC_REGNUM))])]
6444 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6447 ; andqi3 instruction pattern(s).
6450 (define_insn "*andqi3_zarch"
6451 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6452 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6453 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6454 (clobber (reg:CC CC_REGNUM))]
6455 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6463 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6464 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6465 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6467 (define_insn "*andqi3_esa"
6468 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6469 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6470 (match_operand:QI 2 "general_operand" "d,n,Q")))
6471 (clobber (reg:CC CC_REGNUM))]
6472 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6477 [(set_attr "op_type" "RR,SI,SS")
6478 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6481 ; Block and (NC) patterns.
6485 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6486 (and:BLK (match_dup 0)
6487 (match_operand:BLK 1 "memory_operand" "Q")))
6488 (use (match_operand 2 "const_int_operand" "n"))
6489 (clobber (reg:CC CC_REGNUM))]
6490 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6491 "nc\t%O0(%2,%R0),%S1"
6492 [(set_attr "op_type" "SS")
6493 (set_attr "z196prop" "z196_cracked")])
6496 [(set (match_operand 0 "memory_operand" "")
6498 (match_operand 1 "memory_operand" "")))
6499 (clobber (reg:CC CC_REGNUM))]
6501 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6502 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6504 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6506 (clobber (reg:CC CC_REGNUM))])]
6508 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6509 operands[0] = adjust_address (operands[0], BLKmode, 0);
6510 operands[1] = adjust_address (operands[1], BLKmode, 0);
6515 [(set (match_operand:BLK 0 "memory_operand" "")
6516 (and:BLK (match_dup 0)
6517 (match_operand:BLK 1 "memory_operand" "")))
6518 (use (match_operand 2 "const_int_operand" ""))
6519 (clobber (reg:CC CC_REGNUM))])
6521 [(set (match_operand:BLK 3 "memory_operand" "")
6522 (and:BLK (match_dup 3)
6523 (match_operand:BLK 4 "memory_operand" "")))
6524 (use (match_operand 5 "const_int_operand" ""))
6525 (clobber (reg:CC CC_REGNUM))])]
6526 "s390_offset_p (operands[0], operands[3], operands[2])
6527 && s390_offset_p (operands[1], operands[4], operands[2])
6528 && !s390_overlap_p (operands[0], operands[1],
6529 INTVAL (operands[2]) + INTVAL (operands[5]))
6530 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6532 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6534 (clobber (reg:CC CC_REGNUM))])]
6535 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6536 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6537 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6541 ;;- Bit set (inclusive or) instructions.
6544 (define_expand "ior<mode>3"
6545 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6546 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6547 (match_operand:INT 2 "general_operand" "")))
6548 (clobber (reg:CC CC_REGNUM))]
6550 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6553 ; iordi3 instruction pattern(s).
6556 (define_insn "*iordi3_cc"
6557 [(set (reg CC_REGNUM)
6558 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6559 (match_operand:DI 2 "general_operand" " d,d,RT"))
6561 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6562 (ior:DI (match_dup 1) (match_dup 2)))]
6563 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6568 [(set_attr "op_type" "RRE,RRF,RXY")
6569 (set_attr "cpu_facility" "*,z196,*")
6570 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6572 (define_insn "*iordi3_cconly"
6573 [(set (reg CC_REGNUM)
6574 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6575 (match_operand:DI 2 "general_operand" " d,d,RT"))
6577 (clobber (match_scratch:DI 0 "=d,d,d"))]
6578 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6583 [(set_attr "op_type" "RRE,RRF,RXY")
6584 (set_attr "cpu_facility" "*,z196,*")
6585 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6587 (define_insn "*iordi3"
6588 [(set (match_operand:DI 0 "nonimmediate_operand"
6589 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6590 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6591 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6592 (match_operand:DI 2 "general_operand"
6593 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6594 (clobber (reg:CC CC_REGNUM))]
6595 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6608 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6609 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6610 (set_attr "z10prop" "z10_super_E1,
6623 [(set (match_operand:DI 0 "s_operand" "")
6624 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6625 (clobber (reg:CC CC_REGNUM))]
6628 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6629 (clobber (reg:CC CC_REGNUM))])]
6630 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6633 ; iorsi3 instruction pattern(s).
6636 (define_insn "*iorsi3_cc"
6637 [(set (reg CC_REGNUM)
6638 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6639 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6641 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6642 (ior:SI (match_dup 1) (match_dup 2)))]
6643 "s390_match_ccmode(insn, CCTmode)"
6650 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6651 (set_attr "cpu_facility" "*,*,z196,*,*")
6652 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6654 (define_insn "*iorsi3_cconly"
6655 [(set (reg CC_REGNUM)
6656 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6657 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6659 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6660 "s390_match_ccmode(insn, CCTmode)"
6667 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6668 (set_attr "cpu_facility" "*,*,z196,*,*")
6669 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6671 (define_insn "*iorsi3_zarch"
6672 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6673 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6674 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6675 (clobber (reg:CC CC_REGNUM))]
6676 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6687 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6688 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6689 (set_attr "z10prop" "z10_super_E1,
6699 (define_insn "*iorsi3_esa"
6700 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6701 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6702 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6703 (clobber (reg:CC CC_REGNUM))]
6704 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6710 [(set_attr "op_type" "RR,RX,SI,SS")
6711 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6714 [(set (match_operand:SI 0 "s_operand" "")
6715 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6716 (clobber (reg:CC CC_REGNUM))]
6719 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6720 (clobber (reg:CC CC_REGNUM))])]
6721 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6724 ; iorhi3 instruction pattern(s).
6727 (define_insn "*iorhi3_zarch"
6728 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6729 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6730 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6731 (clobber (reg:CC CC_REGNUM))]
6732 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6739 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6740 (set_attr "cpu_facility" "*,z196,*,*,*")
6741 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6743 (define_insn "*iorhi3_esa"
6744 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6745 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6746 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6747 (clobber (reg:CC CC_REGNUM))]
6748 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6753 [(set_attr "op_type" "RR,SI,SS")
6754 (set_attr "z10prop" "z10_super_E1,*,*")])
6757 [(set (match_operand:HI 0 "s_operand" "")
6758 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6759 (clobber (reg:CC CC_REGNUM))]
6762 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6763 (clobber (reg:CC CC_REGNUM))])]
6764 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6767 ; iorqi3 instruction pattern(s).
6770 (define_insn "*iorqi3_zarch"
6771 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6772 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6773 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6774 (clobber (reg:CC CC_REGNUM))]
6775 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6783 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6784 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6785 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6786 z10_super,z10_super,*")])
6788 (define_insn "*iorqi3_esa"
6789 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6790 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6791 (match_operand:QI 2 "general_operand" "d,n,Q")))
6792 (clobber (reg:CC CC_REGNUM))]
6793 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6798 [(set_attr "op_type" "RR,SI,SS")
6799 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6802 ; Block inclusive or (OC) patterns.
6806 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6807 (ior:BLK (match_dup 0)
6808 (match_operand:BLK 1 "memory_operand" "Q")))
6809 (use (match_operand 2 "const_int_operand" "n"))
6810 (clobber (reg:CC CC_REGNUM))]
6811 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6812 "oc\t%O0(%2,%R0),%S1"
6813 [(set_attr "op_type" "SS")
6814 (set_attr "z196prop" "z196_cracked")])
6817 [(set (match_operand 0 "memory_operand" "")
6819 (match_operand 1 "memory_operand" "")))
6820 (clobber (reg:CC CC_REGNUM))]
6822 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6823 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6825 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6827 (clobber (reg:CC CC_REGNUM))])]
6829 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6830 operands[0] = adjust_address (operands[0], BLKmode, 0);
6831 operands[1] = adjust_address (operands[1], BLKmode, 0);
6836 [(set (match_operand:BLK 0 "memory_operand" "")
6837 (ior:BLK (match_dup 0)
6838 (match_operand:BLK 1 "memory_operand" "")))
6839 (use (match_operand 2 "const_int_operand" ""))
6840 (clobber (reg:CC CC_REGNUM))])
6842 [(set (match_operand:BLK 3 "memory_operand" "")
6843 (ior:BLK (match_dup 3)
6844 (match_operand:BLK 4 "memory_operand" "")))
6845 (use (match_operand 5 "const_int_operand" ""))
6846 (clobber (reg:CC CC_REGNUM))])]
6847 "s390_offset_p (operands[0], operands[3], operands[2])
6848 && s390_offset_p (operands[1], operands[4], operands[2])
6849 && !s390_overlap_p (operands[0], operands[1],
6850 INTVAL (operands[2]) + INTVAL (operands[5]))
6851 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6853 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6855 (clobber (reg:CC CC_REGNUM))])]
6856 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6857 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6858 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6862 ;;- Xor instructions.
6865 (define_expand "xor<mode>3"
6866 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6867 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6868 (match_operand:INT 2 "general_operand" "")))
6869 (clobber (reg:CC CC_REGNUM))]
6871 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6874 ; xordi3 instruction pattern(s).
6877 (define_insn "*xordi3_cc"
6878 [(set (reg CC_REGNUM)
6879 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6880 (match_operand:DI 2 "general_operand" " d,d,RT"))
6882 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6883 (xor:DI (match_dup 1) (match_dup 2)))]
6884 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6889 [(set_attr "op_type" "RRE,RRF,RXY")
6890 (set_attr "cpu_facility" "*,z196,*")
6891 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6893 (define_insn "*xordi3_cconly"
6894 [(set (reg CC_REGNUM)
6895 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6896 (match_operand:DI 2 "general_operand" " d,d,RT"))
6898 (clobber (match_scratch:DI 0 "=d,d, d"))]
6899 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6904 [(set_attr "op_type" "RRE,RRF,RXY")
6905 (set_attr "cpu_facility" "*,z196,*")
6906 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6908 (define_insn "*xordi3"
6909 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6910 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6911 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6912 (clobber (reg:CC CC_REGNUM))]
6913 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6922 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6923 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6924 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6925 *,z10_super_E1,*,*")])
6928 [(set (match_operand:DI 0 "s_operand" "")
6929 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6930 (clobber (reg:CC CC_REGNUM))]
6933 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6934 (clobber (reg:CC CC_REGNUM))])]
6935 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6938 ; xorsi3 instruction pattern(s).
6941 (define_insn "*xorsi3_cc"
6942 [(set (reg CC_REGNUM)
6943 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6944 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6946 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6947 (xor:SI (match_dup 1) (match_dup 2)))]
6948 "s390_match_ccmode(insn, CCTmode)"
6955 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6956 (set_attr "cpu_facility" "*,*,z196,*,*")
6957 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6958 z10_super_E1,z10_super_E1")])
6960 (define_insn "*xorsi3_cconly"
6961 [(set (reg CC_REGNUM)
6962 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6963 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6965 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6966 "s390_match_ccmode(insn, CCTmode)"
6973 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6974 (set_attr "cpu_facility" "*,*,z196,*,*")
6975 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6976 z10_super_E1,z10_super_E1")])
6978 (define_insn "*xorsi3"
6979 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6980 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6981 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6982 (clobber (reg:CC CC_REGNUM))]
6983 "s390_logical_operator_ok_p (operands)"
6992 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6993 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6994 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6995 z10_super_E1,z10_super_E1,*,*")])
6998 [(set (match_operand:SI 0 "s_operand" "")
6999 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7000 (clobber (reg:CC CC_REGNUM))]
7003 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7004 (clobber (reg:CC CC_REGNUM))])]
7005 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7008 ; xorhi3 instruction pattern(s).
7011 (define_insn "*xorhi3"
7012 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7013 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7014 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7015 (clobber (reg:CC CC_REGNUM))]
7016 "s390_logical_operator_ok_p (operands)"
7023 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7024 (set_attr "cpu_facility" "*,*,z196,*,*")
7025 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7028 [(set (match_operand:HI 0 "s_operand" "")
7029 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7030 (clobber (reg:CC CC_REGNUM))]
7033 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7034 (clobber (reg:CC CC_REGNUM))])]
7035 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7038 ; xorqi3 instruction pattern(s).
7041 (define_insn "*xorqi3"
7042 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7043 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7044 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7045 (clobber (reg:CC CC_REGNUM))]
7046 "s390_logical_operator_ok_p (operands)"
7054 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7055 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7056 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7060 ; Block exclusive or (XC) patterns.
7064 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7065 (xor:BLK (match_dup 0)
7066 (match_operand:BLK 1 "memory_operand" "Q")))
7067 (use (match_operand 2 "const_int_operand" "n"))
7068 (clobber (reg:CC CC_REGNUM))]
7069 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7070 "xc\t%O0(%2,%R0),%S1"
7071 [(set_attr "op_type" "SS")])
7074 [(set (match_operand 0 "memory_operand" "")
7076 (match_operand 1 "memory_operand" "")))
7077 (clobber (reg:CC CC_REGNUM))]
7079 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7080 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7082 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7084 (clobber (reg:CC CC_REGNUM))])]
7086 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7087 operands[0] = adjust_address (operands[0], BLKmode, 0);
7088 operands[1] = adjust_address (operands[1], BLKmode, 0);
7093 [(set (match_operand:BLK 0 "memory_operand" "")
7094 (xor:BLK (match_dup 0)
7095 (match_operand:BLK 1 "memory_operand" "")))
7096 (use (match_operand 2 "const_int_operand" ""))
7097 (clobber (reg:CC CC_REGNUM))])
7099 [(set (match_operand:BLK 3 "memory_operand" "")
7100 (xor:BLK (match_dup 3)
7101 (match_operand:BLK 4 "memory_operand" "")))
7102 (use (match_operand 5 "const_int_operand" ""))
7103 (clobber (reg:CC CC_REGNUM))])]
7104 "s390_offset_p (operands[0], operands[3], operands[2])
7105 && s390_offset_p (operands[1], operands[4], operands[2])
7106 && !s390_overlap_p (operands[0], operands[1],
7107 INTVAL (operands[2]) + INTVAL (operands[5]))
7108 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7110 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7112 (clobber (reg:CC CC_REGNUM))])]
7113 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7114 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7115 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7118 ; Block xor (XC) patterns with src == dest.
7121 (define_insn "*xc_zero"
7122 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7124 (use (match_operand 1 "const_int_operand" "n"))
7125 (clobber (reg:CC CC_REGNUM))]
7126 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7127 "xc\t%O0(%1,%R0),%S0"
7128 [(set_attr "op_type" "SS")
7129 (set_attr "z196prop" "z196_cracked")])
7133 [(set (match_operand:BLK 0 "memory_operand" "")
7135 (use (match_operand 1 "const_int_operand" ""))
7136 (clobber (reg:CC CC_REGNUM))])
7138 [(set (match_operand:BLK 2 "memory_operand" "")
7140 (use (match_operand 3 "const_int_operand" ""))
7141 (clobber (reg:CC CC_REGNUM))])]
7142 "s390_offset_p (operands[0], operands[2], operands[1])
7143 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7145 [(set (match_dup 4) (const_int 0))
7147 (clobber (reg:CC CC_REGNUM))])]
7148 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7149 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7153 ;;- Negate instructions.
7157 ; neg(di|si)2 instruction pattern(s).
7160 (define_expand "neg<mode>2"
7162 [(set (match_operand:DSI 0 "register_operand" "=d")
7163 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7164 (clobber (reg:CC CC_REGNUM))])]
7168 (define_insn "*negdi2_sign_cc"
7169 [(set (reg CC_REGNUM)
7170 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7171 (match_operand:SI 1 "register_operand" "d") 0)
7172 (const_int 32)) (const_int 32)))
7174 (set (match_operand:DI 0 "register_operand" "=d")
7175 (neg:DI (sign_extend:DI (match_dup 1))))]
7176 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7178 [(set_attr "op_type" "RRE")
7179 (set_attr "z10prop" "z10_c")])
7181 (define_insn "*negdi2_sign"
7182 [(set (match_operand:DI 0 "register_operand" "=d")
7183 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7184 (clobber (reg:CC CC_REGNUM))]
7187 [(set_attr "op_type" "RRE")
7188 (set_attr "z10prop" "z10_c")])
7191 (define_insn "*neg<mode>2_cc"
7192 [(set (reg CC_REGNUM)
7193 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7195 (set (match_operand:GPR 0 "register_operand" "=d")
7196 (neg:GPR (match_dup 1)))]
7197 "s390_match_ccmode (insn, CCAmode)"
7199 [(set_attr "op_type" "RR<E>")
7200 (set_attr "z10prop" "z10_super_c_E1")])
7203 (define_insn "*neg<mode>2_cconly"
7204 [(set (reg CC_REGNUM)
7205 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7207 (clobber (match_scratch:GPR 0 "=d"))]
7208 "s390_match_ccmode (insn, CCAmode)"
7210 [(set_attr "op_type" "RR<E>")
7211 (set_attr "z10prop" "z10_super_c_E1")])
7214 (define_insn "*neg<mode>2"
7215 [(set (match_operand:GPR 0 "register_operand" "=d")
7216 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7217 (clobber (reg:CC CC_REGNUM))]
7220 [(set_attr "op_type" "RR<E>")
7221 (set_attr "z10prop" "z10_super_c_E1")])
7223 (define_insn_and_split "*negdi2_31"
7224 [(set (match_operand:DI 0 "register_operand" "=d")
7225 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7226 (clobber (reg:CC CC_REGNUM))]
7229 "&& reload_completed"
7231 [(set (match_dup 2) (neg:SI (match_dup 3)))
7232 (clobber (reg:CC CC_REGNUM))])
7234 [(set (reg:CCAP CC_REGNUM)
7235 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7236 (set (match_dup 4) (neg:SI (match_dup 5)))])
7238 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7240 (label_ref (match_dup 6))))
7242 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7243 (clobber (reg:CC CC_REGNUM))])
7245 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7246 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7247 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7248 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7249 operands[6] = gen_label_rtx ();")
7252 ; neg(df|sf)2 instruction pattern(s).
7255 (define_expand "neg<mode>2"
7257 [(set (match_operand:BFP 0 "register_operand" "=f")
7258 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7259 (clobber (reg:CC CC_REGNUM))])]
7263 ; lcxbr, lcdbr, lcebr
7264 (define_insn "*neg<mode>2_cc"
7265 [(set (reg CC_REGNUM)
7266 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7267 (match_operand:BFP 2 "const0_operand" "")))
7268 (set (match_operand:BFP 0 "register_operand" "=f")
7269 (neg:BFP (match_dup 1)))]
7270 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7272 [(set_attr "op_type" "RRE")
7273 (set_attr "type" "fsimp<mode>")])
7275 ; lcxbr, lcdbr, lcebr
7276 (define_insn "*neg<mode>2_cconly"
7277 [(set (reg CC_REGNUM)
7278 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7279 (match_operand:BFP 2 "const0_operand" "")))
7280 (clobber (match_scratch:BFP 0 "=f"))]
7281 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7283 [(set_attr "op_type" "RRE")
7284 (set_attr "type" "fsimp<mode>")])
7287 (define_insn "*neg<mode>2_nocc"
7288 [(set (match_operand:FP 0 "register_operand" "=f")
7289 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7292 [(set_attr "op_type" "RRE")
7293 (set_attr "type" "fsimp<mode>")])
7295 ; lcxbr, lcdbr, lcebr
7296 (define_insn "*neg<mode>2"
7297 [(set (match_operand:BFP 0 "register_operand" "=f")
7298 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7299 (clobber (reg:CC CC_REGNUM))]
7302 [(set_attr "op_type" "RRE")
7303 (set_attr "type" "fsimp<mode>")])
7307 ;;- Absolute value instructions.
7311 ; abs(di|si)2 instruction pattern(s).
7314 (define_insn "*absdi2_sign_cc"
7315 [(set (reg CC_REGNUM)
7316 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7317 (match_operand:SI 1 "register_operand" "d") 0)
7318 (const_int 32)) (const_int 32)))
7320 (set (match_operand:DI 0 "register_operand" "=d")
7321 (abs:DI (sign_extend:DI (match_dup 1))))]
7322 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7324 [(set_attr "op_type" "RRE")
7325 (set_attr "z10prop" "z10_c")])
7327 (define_insn "*absdi2_sign"
7328 [(set (match_operand:DI 0 "register_operand" "=d")
7329 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7330 (clobber (reg:CC CC_REGNUM))]
7333 [(set_attr "op_type" "RRE")
7334 (set_attr "z10prop" "z10_c")])
7337 (define_insn "*abs<mode>2_cc"
7338 [(set (reg CC_REGNUM)
7339 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7341 (set (match_operand:GPR 0 "register_operand" "=d")
7342 (abs:GPR (match_dup 1)))]
7343 "s390_match_ccmode (insn, CCAmode)"
7345 [(set_attr "op_type" "RR<E>")
7346 (set_attr "z10prop" "z10_c")])
7349 (define_insn "*abs<mode>2_cconly"
7350 [(set (reg CC_REGNUM)
7351 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7353 (clobber (match_scratch:GPR 0 "=d"))]
7354 "s390_match_ccmode (insn, CCAmode)"
7356 [(set_attr "op_type" "RR<E>")
7357 (set_attr "z10prop" "z10_c")])
7360 (define_insn "abs<mode>2"
7361 [(set (match_operand:GPR 0 "register_operand" "=d")
7362 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7363 (clobber (reg:CC CC_REGNUM))]
7366 [(set_attr "op_type" "RR<E>")
7367 (set_attr "z10prop" "z10_c")])
7370 ; abs(df|sf)2 instruction pattern(s).
7373 (define_expand "abs<mode>2"
7375 [(set (match_operand:BFP 0 "register_operand" "=f")
7376 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7377 (clobber (reg:CC CC_REGNUM))])]
7381 ; lpxbr, lpdbr, lpebr
7382 (define_insn "*abs<mode>2_cc"
7383 [(set (reg CC_REGNUM)
7384 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7385 (match_operand:BFP 2 "const0_operand" "")))
7386 (set (match_operand:BFP 0 "register_operand" "=f")
7387 (abs:BFP (match_dup 1)))]
7388 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7390 [(set_attr "op_type" "RRE")
7391 (set_attr "type" "fsimp<mode>")])
7393 ; lpxbr, lpdbr, lpebr
7394 (define_insn "*abs<mode>2_cconly"
7395 [(set (reg CC_REGNUM)
7396 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7397 (match_operand:BFP 2 "const0_operand" "")))
7398 (clobber (match_scratch:BFP 0 "=f"))]
7399 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7401 [(set_attr "op_type" "RRE")
7402 (set_attr "type" "fsimp<mode>")])
7405 (define_insn "*abs<mode>2_nocc"
7406 [(set (match_operand:FP 0 "register_operand" "=f")
7407 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7410 [(set_attr "op_type" "RRE")
7411 (set_attr "type" "fsimp<mode>")])
7413 ; lpxbr, lpdbr, lpebr
7414 (define_insn "*abs<mode>2"
7415 [(set (match_operand:BFP 0 "register_operand" "=f")
7416 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7417 (clobber (reg:CC CC_REGNUM))]
7420 [(set_attr "op_type" "RRE")
7421 (set_attr "type" "fsimp<mode>")])
7425 ;;- Negated absolute value instructions
7432 (define_insn "*negabsdi2_sign_cc"
7433 [(set (reg CC_REGNUM)
7434 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7435 (match_operand:SI 1 "register_operand" "d") 0)
7436 (const_int 32)) (const_int 32))))
7438 (set (match_operand:DI 0 "register_operand" "=d")
7439 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7440 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7442 [(set_attr "op_type" "RRE")
7443 (set_attr "z10prop" "z10_c")])
7445 (define_insn "*negabsdi2_sign"
7446 [(set (match_operand:DI 0 "register_operand" "=d")
7447 (neg:DI (abs:DI (sign_extend:DI
7448 (match_operand:SI 1 "register_operand" "d")))))
7449 (clobber (reg:CC CC_REGNUM))]
7452 [(set_attr "op_type" "RRE")
7453 (set_attr "z10prop" "z10_c")])
7456 (define_insn "*negabs<mode>2_cc"
7457 [(set (reg CC_REGNUM)
7458 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7460 (set (match_operand:GPR 0 "register_operand" "=d")
7461 (neg:GPR (abs:GPR (match_dup 1))))]
7462 "s390_match_ccmode (insn, CCAmode)"
7464 [(set_attr "op_type" "RR<E>")
7465 (set_attr "z10prop" "z10_c")])
7468 (define_insn "*negabs<mode>2_cconly"
7469 [(set (reg CC_REGNUM)
7470 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7472 (clobber (match_scratch:GPR 0 "=d"))]
7473 "s390_match_ccmode (insn, CCAmode)"
7475 [(set_attr "op_type" "RR<E>")
7476 (set_attr "z10prop" "z10_c")])
7479 (define_insn "*negabs<mode>2"
7480 [(set (match_operand:GPR 0 "register_operand" "=d")
7481 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7482 (clobber (reg:CC CC_REGNUM))]
7485 [(set_attr "op_type" "RR<E>")
7486 (set_attr "z10prop" "z10_c")])
7492 ; lnxbr, lndbr, lnebr
7493 (define_insn "*negabs<mode>2_cc"
7494 [(set (reg CC_REGNUM)
7495 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7496 (match_operand:BFP 2 "const0_operand" "")))
7497 (set (match_operand:BFP 0 "register_operand" "=f")
7498 (neg:BFP (abs:BFP (match_dup 1))))]
7499 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7501 [(set_attr "op_type" "RRE")
7502 (set_attr "type" "fsimp<mode>")])
7504 ; lnxbr, lndbr, lnebr
7505 (define_insn "*negabs<mode>2_cconly"
7506 [(set (reg CC_REGNUM)
7507 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7508 (match_operand:BFP 2 "const0_operand" "")))
7509 (clobber (match_scratch:BFP 0 "=f"))]
7510 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7512 [(set_attr "op_type" "RRE")
7513 (set_attr "type" "fsimp<mode>")])
7516 (define_insn "*negabs<mode>2_nocc"
7517 [(set (match_operand:FP 0 "register_operand" "=f")
7518 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7521 [(set_attr "op_type" "RRE")
7522 (set_attr "type" "fsimp<mode>")])
7524 ; lnxbr, lndbr, lnebr
7525 (define_insn "*negabs<mode>2"
7526 [(set (match_operand:BFP 0 "register_operand" "=f")
7527 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7528 (clobber (reg:CC CC_REGNUM))]
7531 [(set_attr "op_type" "RRE")
7532 (set_attr "type" "fsimp<mode>")])
7535 ;;- Square root instructions.
7539 ; sqrt(df|sf)2 instruction pattern(s).
7542 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7543 (define_insn "sqrt<mode>2"
7544 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7545 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7550 [(set_attr "op_type" "RRE,RXE")
7551 (set_attr "type" "fsqrt<mode>")])
7555 ;;- One complement instructions.
7559 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7562 (define_expand "one_cmpl<mode>2"
7564 [(set (match_operand:INT 0 "register_operand" "")
7565 (xor:INT (match_operand:INT 1 "register_operand" "")
7567 (clobber (reg:CC CC_REGNUM))])]
7573 ;; Find leftmost bit instructions.
7576 (define_expand "clzdi2"
7577 [(set (match_operand:DI 0 "register_operand" "=d")
7578 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7579 "TARGET_EXTIMM && TARGET_ZARCH"
7581 rtx insn, clz_equal;
7582 rtx wide_reg = gen_reg_rtx (TImode);
7583 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7585 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7587 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7589 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7590 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7595 (define_insn "clztidi2"
7596 [(set (match_operand:TI 0 "register_operand" "=d")
7600 (xor:DI (match_operand:DI 1 "register_operand" "d")
7601 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7602 (subreg:SI (clz:DI (match_dup 1)) 4))))
7605 (zero_extend:TI (clz:DI (match_dup 1)))))
7606 (clobber (reg:CC CC_REGNUM))]
7607 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7608 == (unsigned HOST_WIDE_INT) 1 << 63
7609 && TARGET_EXTIMM && TARGET_ZARCH"
7611 [(set_attr "op_type" "RRE")])
7615 ;;- Rotate instructions.
7619 ; rotl(di|si)3 instruction pattern(s).
7623 (define_insn "rotl<mode>3"
7624 [(set (match_operand:GPR 0 "register_operand" "=d")
7625 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7626 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7629 [(set_attr "op_type" "RSE")
7630 (set_attr "atype" "reg")
7631 (set_attr "z10prop" "z10_super_E1")])
7634 (define_insn "*rotl<mode>3_and"
7635 [(set (match_operand:GPR 0 "register_operand" "=d")
7636 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7637 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7638 (match_operand:SI 3 "const_int_operand" "n"))))]
7639 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7641 [(set_attr "op_type" "RSE")
7642 (set_attr "atype" "reg")
7643 (set_attr "z10prop" "z10_super_E1")])
7647 ;;- Shift instructions.
7651 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7652 ; Left shifts and logical right shifts
7654 (define_expand "<shift><mode>3"
7655 [(set (match_operand:DSI 0 "register_operand" "")
7656 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7657 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7662 (define_insn "*<shift>di3_31"
7663 [(set (match_operand:DI 0 "register_operand" "=d")
7664 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7665 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7668 [(set_attr "op_type" "RS")
7669 (set_attr "atype" "reg")
7670 (set_attr "z196prop" "z196_cracked")])
7672 ; sll, srl, sllg, srlg, sllk, srlk
7673 (define_insn "*<shift><mode>3"
7674 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7675 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7676 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7679 s<lr>l<g>\t%0,<1>%Y2
7680 s<lr>l<gk>\t%0,%1,%Y2"
7681 [(set_attr "op_type" "RS<E>,RSY")
7682 (set_attr "atype" "reg,reg")
7683 (set_attr "cpu_facility" "*,z196")
7684 (set_attr "z10prop" "z10_super_E1,*")])
7687 (define_insn "*<shift>di3_31_and"
7688 [(set (match_operand:DI 0 "register_operand" "=d")
7689 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7690 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7691 (match_operand:SI 3 "const_int_operand" "n"))))]
7692 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7694 [(set_attr "op_type" "RS")
7695 (set_attr "atype" "reg")])
7697 ; sll, srl, sllg, srlg, sllk, srlk
7698 (define_insn "*<shift><mode>3_and"
7699 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7700 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7701 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7702 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7703 "(INTVAL (operands[3]) & 63) == 63"
7705 s<lr>l<g>\t%0,<1>%Y2
7706 s<lr>l<gk>\t%0,%1,%Y2"
7707 [(set_attr "op_type" "RS<E>,RSY")
7708 (set_attr "atype" "reg,reg")
7709 (set_attr "cpu_facility" "*,z196")
7710 (set_attr "z10prop" "z10_super_E1,*")])
7713 ; ashr(di|si)3 instruction pattern(s).
7714 ; Arithmetic right shifts
7716 (define_expand "ashr<mode>3"
7718 [(set (match_operand:DSI 0 "register_operand" "")
7719 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7720 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7721 (clobber (reg:CC CC_REGNUM))])]
7725 (define_insn "*ashrdi3_cc_31"
7726 [(set (reg CC_REGNUM)
7727 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7728 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7730 (set (match_operand:DI 0 "register_operand" "=d")
7731 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7732 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7734 [(set_attr "op_type" "RS")
7735 (set_attr "atype" "reg")])
7737 (define_insn "*ashrdi3_cconly_31"
7738 [(set (reg CC_REGNUM)
7739 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7740 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7742 (clobber (match_scratch:DI 0 "=d"))]
7743 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7745 [(set_attr "op_type" "RS")
7746 (set_attr "atype" "reg")])
7748 (define_insn "*ashrdi3_31"
7749 [(set (match_operand:DI 0 "register_operand" "=d")
7750 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7751 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7752 (clobber (reg:CC CC_REGNUM))]
7755 [(set_attr "op_type" "RS")
7756 (set_attr "atype" "reg")])
7759 (define_insn "*ashr<mode>3_cc"
7760 [(set (reg CC_REGNUM)
7761 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7762 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7764 (set (match_operand:GPR 0 "register_operand" "=d,d")
7765 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7766 "s390_match_ccmode(insn, CCSmode)"
7770 [(set_attr "op_type" "RS<E>,RSY")
7771 (set_attr "atype" "reg,reg")
7772 (set_attr "cpu_facility" "*,z196")
7773 (set_attr "z10prop" "z10_super_E1,*")])
7776 (define_insn "*ashr<mode>3_cconly"
7777 [(set (reg CC_REGNUM)
7778 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7779 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7781 (clobber (match_scratch:GPR 0 "=d,d"))]
7782 "s390_match_ccmode(insn, CCSmode)"
7786 [(set_attr "op_type" "RS<E>,RSY")
7787 (set_attr "atype" "reg,reg")
7788 (set_attr "cpu_facility" "*,z196")
7789 (set_attr "z10prop" "z10_super_E1,*")])
7792 (define_insn "*ashr<mode>3"
7793 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7794 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7795 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7796 (clobber (reg:CC CC_REGNUM))]
7801 [(set_attr "op_type" "RS<E>,RSY")
7802 (set_attr "atype" "reg,reg")
7803 (set_attr "cpu_facility" "*,z196")
7804 (set_attr "z10prop" "z10_super_E1,*")])
7807 ; shift pattern with implicit ANDs
7809 (define_insn "*ashrdi3_cc_31_and"
7810 [(set (reg CC_REGNUM)
7811 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7812 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7813 (match_operand:SI 3 "const_int_operand" "n")))
7815 (set (match_operand:DI 0 "register_operand" "=d")
7816 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7817 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7818 && (INTVAL (operands[3]) & 63) == 63"
7820 [(set_attr "op_type" "RS")
7821 (set_attr "atype" "reg")])
7823 (define_insn "*ashrdi3_cconly_31_and"
7824 [(set (reg CC_REGNUM)
7825 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7826 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7827 (match_operand:SI 3 "const_int_operand" "n")))
7829 (clobber (match_scratch:DI 0 "=d"))]
7830 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7831 && (INTVAL (operands[3]) & 63) == 63"
7833 [(set_attr "op_type" "RS")
7834 (set_attr "atype" "reg")])
7836 (define_insn "*ashrdi3_31_and"
7837 [(set (match_operand:DI 0 "register_operand" "=d")
7838 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7839 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7840 (match_operand:SI 3 "const_int_operand" "n"))))
7841 (clobber (reg:CC CC_REGNUM))]
7842 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7844 [(set_attr "op_type" "RS")
7845 (set_attr "atype" "reg")])
7848 (define_insn "*ashr<mode>3_cc_and"
7849 [(set (reg CC_REGNUM)
7850 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7851 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7852 (match_operand:SI 3 "const_int_operand" "n,n")))
7854 (set (match_operand:GPR 0 "register_operand" "=d,d")
7855 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7856 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7860 [(set_attr "op_type" "RS<E>,RSY")
7861 (set_attr "atype" "reg,reg")
7862 (set_attr "cpu_facility" "*,z196")
7863 (set_attr "z10prop" "z10_super_E1,*")])
7866 (define_insn "*ashr<mode>3_cconly_and"
7867 [(set (reg CC_REGNUM)
7868 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7869 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7870 (match_operand:SI 3 "const_int_operand" "n,n")))
7872 (clobber (match_scratch:GPR 0 "=d,d"))]
7873 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7877 [(set_attr "op_type" "RS<E>,RSY")
7878 (set_attr "atype" "reg,reg")
7879 (set_attr "cpu_facility" "*,z196")
7880 (set_attr "z10prop" "z10_super_E1,*")])
7883 (define_insn "*ashr<mode>3_and"
7884 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7885 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7886 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7887 (match_operand:SI 3 "const_int_operand" "n,n"))))
7888 (clobber (reg:CC CC_REGNUM))]
7889 "(INTVAL (operands[3]) & 63) == 63"
7893 [(set_attr "op_type" "RS<E>,RSY")
7894 (set_attr "atype" "reg,reg")
7895 (set_attr "cpu_facility" "*,z196")
7896 (set_attr "z10prop" "z10_super_E1,*")])
7900 ;; Branch instruction patterns.
7903 (define_expand "cbranch<mode>4"
7905 (if_then_else (match_operator 0 "comparison_operator"
7906 [(match_operand:GPR 1 "register_operand" "")
7907 (match_operand:GPR 2 "general_operand" "")])
7908 (label_ref (match_operand 3 "" ""))
7911 "s390_emit_jump (operands[3],
7912 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7915 (define_expand "cbranch<mode>4"
7917 (if_then_else (match_operator 0 "comparison_operator"
7918 [(match_operand:FP 1 "register_operand" "")
7919 (match_operand:FP 2 "general_operand" "")])
7920 (label_ref (match_operand 3 "" ""))
7923 "s390_emit_jump (operands[3],
7924 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7927 (define_expand "cbranchcc4"
7929 (if_then_else (match_operator 0 "s390_eqne_operator"
7930 [(match_operand 1 "cc_reg_operand" "")
7931 (match_operand 2 "const0_operand" "")])
7932 (label_ref (match_operand 3 "" ""))
7935 "s390_emit_jump (operands[3],
7936 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7942 ;;- Conditional jump instructions.
7945 (define_insn "*cjump_64"
7948 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
7949 (match_operand 2 "const_int_operand" "")])
7950 (label_ref (match_operand 0 "" ""))
7954 if (get_attr_length (insn) == 4)
7957 return "jg%C1\t%l0";
7959 [(set_attr "op_type" "RI")
7960 (set_attr "type" "branch")
7961 (set (attr "length")
7962 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7963 (const_int 4) (const_int 6)))])
7965 (define_insn "*cjump_31"
7968 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
7969 (match_operand 2 "const_int_operand" "")])
7970 (label_ref (match_operand 0 "" ""))
7974 gcc_assert (get_attr_length (insn) == 4);
7977 [(set_attr "op_type" "RI")
7978 (set_attr "type" "branch")
7979 (set (attr "length")
7980 (if_then_else (not (match_test "flag_pic"))
7981 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7982 (const_int 4) (const_int 6))
7983 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7984 (const_int 4) (const_int 8))))])
7986 (define_insn "*cjump_long"
7989 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7990 (match_operand 0 "address_operand" "ZQZR")
7994 if (get_attr_op_type (insn) == OP_TYPE_RR)
7999 [(set (attr "op_type")
8000 (if_then_else (match_operand 0 "register_operand" "")
8001 (const_string "RR") (const_string "RX")))
8002 (set_attr "type" "branch")
8003 (set_attr "atype" "agen")])
8007 ;;- Negated conditional jump instructions.
8010 (define_insn "*icjump_64"
8013 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8015 (label_ref (match_operand 0 "" ""))))]
8018 if (get_attr_length (insn) == 4)
8021 return "jg%D1\t%l0";
8023 [(set_attr "op_type" "RI")
8024 (set_attr "type" "branch")
8025 (set (attr "length")
8026 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8027 (const_int 4) (const_int 6)))])
8029 (define_insn "*icjump_31"
8032 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8034 (label_ref (match_operand 0 "" ""))))]
8037 gcc_assert (get_attr_length (insn) == 4);
8040 [(set_attr "op_type" "RI")
8041 (set_attr "type" "branch")
8042 (set (attr "length")
8043 (if_then_else (not (match_test "flag_pic"))
8044 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8045 (const_int 4) (const_int 6))
8046 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8047 (const_int 4) (const_int 8))))])
8049 (define_insn "*icjump_long"
8052 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8054 (match_operand 0 "address_operand" "ZQZR")))]
8057 if (get_attr_op_type (insn) == OP_TYPE_RR)
8062 [(set (attr "op_type")
8063 (if_then_else (match_operand 0 "register_operand" "")
8064 (const_string "RR") (const_string "RX")))
8065 (set_attr "type" "branch")
8066 (set_attr "atype" "agen")])
8069 ;;- Trap instructions.
8073 [(trap_if (const_int 1) (const_int 0))]
8076 [(set_attr "op_type" "RI")
8077 (set_attr "type" "branch")])
8079 (define_expand "ctrap<mode>4"
8080 [(trap_if (match_operator 0 "comparison_operator"
8081 [(match_operand:GPR 1 "register_operand" "")
8082 (match_operand:GPR 2 "general_operand" "")])
8083 (match_operand 3 "const0_operand" ""))]
8086 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8087 operands[1], operands[2]);
8088 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8092 (define_expand "ctrap<mode>4"
8093 [(trap_if (match_operator 0 "comparison_operator"
8094 [(match_operand:FP 1 "register_operand" "")
8095 (match_operand:FP 2 "general_operand" "")])
8096 (match_operand 3 "const0_operand" ""))]
8099 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8100 operands[1], operands[2]);
8101 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8105 (define_insn "condtrap"
8106 [(trap_if (match_operator 0 "s390_comparison"
8107 [(match_operand 1 "cc_reg_operand" "c")
8112 [(set_attr "op_type" "RI")
8113 (set_attr "type" "branch")])
8115 ; crt, cgrt, cit, cgit
8116 (define_insn "*cmp_and_trap_signed_int<mode>"
8117 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8118 [(match_operand:GPR 1 "register_operand" "d,d")
8119 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8125 [(set_attr "op_type" "RRF,RIE")
8126 (set_attr "type" "branch")
8127 (set_attr "z10prop" "z10_super_c,z10_super")])
8129 ; clrt, clgrt, clfit, clgit, clt, clgt
8130 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8131 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8132 [(match_operand:GPR 1 "register_operand" "d,d, d")
8133 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8140 [(set_attr "op_type" "RRF,RIE,RSY")
8141 (set_attr "type" "branch")
8142 (set_attr "z10prop" "z10_super_c,z10_super,*")
8143 (set_attr "cpu_facility" "z10,z10,zEC12")])
8146 (define_insn "*load_and_trap<mode>"
8147 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8150 (set (match_operand:GPR 1 "register_operand" "=d")
8154 [(set_attr "op_type" "RXY")])
8158 ;;- Loop instructions.
8160 ;; This is all complicated by the fact that since this is a jump insn
8161 ;; we must handle our own output reloads.
8165 ; This splitter will be matched by combine and has to add the 2 moves
8166 ; necessary to load the compare and the increment values into a
8167 ; register pair as needed by brxle.
8169 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8172 (match_operator 6 "s390_brx_operator"
8173 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8174 (match_operand:GPR 2 "general_operand" ""))
8175 (match_operand:GPR 3 "register_operand" "")])
8176 (label_ref (match_operand 0 "" ""))
8178 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8179 (plus:GPR (match_dup 1) (match_dup 2)))
8180 (clobber (match_scratch:GPR 5 ""))]
8183 "!reload_completed && !reload_in_progress"
8184 [(set (match_dup 7) (match_dup 2)) ; the increment
8185 (set (match_dup 8) (match_dup 3)) ; the comparison value
8186 (parallel [(set (pc)
8189 [(plus:GPR (match_dup 1) (match_dup 7))
8191 (label_ref (match_dup 0))
8194 (plus:GPR (match_dup 1) (match_dup 7)))
8195 (clobber (match_dup 5))
8196 (clobber (reg:CC CC_REGNUM))])]
8198 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8199 operands[7] = gen_lowpart (<GPR:MODE>mode,
8200 gen_highpart (word_mode, dreg));
8201 operands[8] = gen_lowpart (<GPR:MODE>mode,
8202 gen_lowpart (word_mode, dreg));
8207 (define_insn_and_split "*brxg_64bit"
8210 (match_operator 5 "s390_brx_operator"
8211 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8212 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8213 (subreg:DI (match_dup 2) 8)])
8214 (label_ref (match_operand 0 "" ""))
8216 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8217 (plus:DI (match_dup 1)
8218 (subreg:DI (match_dup 2) 0)))
8219 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8220 (clobber (reg:CC CC_REGNUM))]
8223 if (which_alternative != 0)
8225 else if (get_attr_length (insn) == 6)
8226 return "brx%E5g\t%1,%2,%l0";
8228 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8230 "&& reload_completed
8231 && (!REG_P (operands[3])
8232 || !rtx_equal_p (operands[1], operands[3]))"
8233 [(set (match_dup 4) (match_dup 1))
8234 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8235 (clobber (reg:CC CC_REGNUM))])
8236 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8237 (set (match_dup 3) (match_dup 4))
8238 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8239 (label_ref (match_dup 0))
8242 [(set_attr "op_type" "RIE")
8243 (set_attr "type" "branch")
8244 (set (attr "length")
8245 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8246 (const_int 6) (const_int 16)))])
8250 (define_insn_and_split "*brx_64bit"
8253 (match_operator 5 "s390_brx_operator"
8254 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8255 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8256 (subreg:SI (match_dup 2) 12)])
8257 (label_ref (match_operand 0 "" ""))
8259 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8260 (plus:SI (match_dup 1)
8261 (subreg:SI (match_dup 2) 4)))
8262 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8263 (clobber (reg:CC CC_REGNUM))]
8266 if (which_alternative != 0)
8268 else if (get_attr_length (insn) == 6)
8269 return "brx%C5\t%1,%2,%l0";
8271 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8273 "&& reload_completed
8274 && (!REG_P (operands[3])
8275 || !rtx_equal_p (operands[1], operands[3]))"
8276 [(set (match_dup 4) (match_dup 1))
8277 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8278 (clobber (reg:CC CC_REGNUM))])
8279 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8280 (set (match_dup 3) (match_dup 4))
8281 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8282 (label_ref (match_dup 0))
8285 [(set_attr "op_type" "RSI")
8286 (set_attr "type" "branch")
8287 (set (attr "length")
8288 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8289 (const_int 6) (const_int 14)))])
8293 (define_insn_and_split "*brx_31bit"
8296 (match_operator 5 "s390_brx_operator"
8297 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8298 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8299 (subreg:SI (match_dup 2) 4)])
8300 (label_ref (match_operand 0 "" ""))
8302 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8303 (plus:SI (match_dup 1)
8304 (subreg:SI (match_dup 2) 0)))
8305 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8306 (clobber (reg:CC CC_REGNUM))]
8307 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8309 if (which_alternative != 0)
8311 else if (get_attr_length (insn) == 6)
8312 return "brx%C5\t%1,%2,%l0";
8314 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8316 "&& reload_completed
8317 && (!REG_P (operands[3])
8318 || !rtx_equal_p (operands[1], operands[3]))"
8319 [(set (match_dup 4) (match_dup 1))
8320 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8321 (clobber (reg:CC CC_REGNUM))])
8322 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8323 (set (match_dup 3) (match_dup 4))
8324 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8325 (label_ref (match_dup 0))
8328 [(set_attr "op_type" "RSI")
8329 (set_attr "type" "branch")
8330 (set (attr "length")
8331 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8332 (const_int 6) (const_int 14)))])
8337 (define_expand "doloop_end"
8338 [(use (match_operand 0 "" "")) ; loop pseudo
8339 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8340 (use (match_operand 2 "" "")) ; max iterations
8341 (use (match_operand 3 "" "")) ; loop level
8342 (use (match_operand 4 "" "")) ; label
8343 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8346 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8347 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8348 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8349 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8350 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8351 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8358 (define_insn_and_split "doloop_si64"
8361 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8363 (label_ref (match_operand 0 "" ""))
8365 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8366 (plus:SI (match_dup 1) (const_int -1)))
8367 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8368 (clobber (reg:CC CC_REGNUM))]
8371 if (which_alternative != 0)
8373 else if (get_attr_length (insn) == 4)
8374 return "brct\t%1,%l0";
8376 return "ahi\t%1,-1\;jgne\t%l0";
8378 "&& reload_completed
8379 && (! REG_P (operands[2])
8380 || ! rtx_equal_p (operands[1], operands[2]))"
8381 [(set (match_dup 3) (match_dup 1))
8382 (parallel [(set (reg:CCAN CC_REGNUM)
8383 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8385 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8386 (set (match_dup 2) (match_dup 3))
8387 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8388 (label_ref (match_dup 0))
8391 [(set_attr "op_type" "RI")
8392 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8393 ; hurt us in the (rare) case of ahi.
8394 (set_attr "z10prop" "z10_super_E1")
8395 (set_attr "type" "branch")
8396 (set (attr "length")
8397 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8398 (const_int 4) (const_int 10)))])
8400 (define_insn_and_split "doloop_si31"
8403 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8405 (label_ref (match_operand 0 "" ""))
8407 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8408 (plus:SI (match_dup 1) (const_int -1)))
8409 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8410 (clobber (reg:CC CC_REGNUM))]
8413 if (which_alternative != 0)
8415 else if (get_attr_length (insn) == 4)
8416 return "brct\t%1,%l0";
8420 "&& reload_completed
8421 && (! REG_P (operands[2])
8422 || ! rtx_equal_p (operands[1], operands[2]))"
8423 [(set (match_dup 3) (match_dup 1))
8424 (parallel [(set (reg:CCAN CC_REGNUM)
8425 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8427 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8428 (set (match_dup 2) (match_dup 3))
8429 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8430 (label_ref (match_dup 0))
8433 [(set_attr "op_type" "RI")
8434 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8435 ; hurt us in the (rare) case of ahi.
8436 (set_attr "z10prop" "z10_super_E1")
8437 (set_attr "type" "branch")
8438 (set (attr "length")
8439 (if_then_else (not (match_test "flag_pic"))
8440 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8441 (const_int 4) (const_int 6))
8442 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8443 (const_int 4) (const_int 8))))])
8445 (define_insn "*doloop_si_long"
8448 (ne (match_operand:SI 1 "register_operand" "d")
8450 (match_operand 0 "address_operand" "ZQZR")
8452 (set (match_operand:SI 2 "register_operand" "=1")
8453 (plus:SI (match_dup 1) (const_int -1)))
8454 (clobber (match_scratch:SI 3 "=X"))
8455 (clobber (reg:CC CC_REGNUM))]
8458 if (get_attr_op_type (insn) == OP_TYPE_RR)
8459 return "bctr\t%1,%0";
8461 return "bct\t%1,%a0";
8463 [(set (attr "op_type")
8464 (if_then_else (match_operand 0 "register_operand" "")
8465 (const_string "RR") (const_string "RX")))
8466 (set_attr "type" "branch")
8467 (set_attr "atype" "agen")
8468 (set_attr "z10prop" "z10_c")
8469 (set_attr "z196prop" "z196_cracked")])
8471 (define_insn_and_split "doloop_di"
8474 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8476 (label_ref (match_operand 0 "" ""))
8478 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8479 (plus:DI (match_dup 1) (const_int -1)))
8480 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8481 (clobber (reg:CC CC_REGNUM))]
8484 if (which_alternative != 0)
8486 else if (get_attr_length (insn) == 4)
8487 return "brctg\t%1,%l0";
8489 return "aghi\t%1,-1\;jgne\t%l0";
8491 "&& reload_completed
8492 && (! REG_P (operands[2])
8493 || ! rtx_equal_p (operands[1], operands[2]))"
8494 [(set (match_dup 3) (match_dup 1))
8495 (parallel [(set (reg:CCAN CC_REGNUM)
8496 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8498 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8499 (set (match_dup 2) (match_dup 3))
8500 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8501 (label_ref (match_dup 0))
8504 [(set_attr "op_type" "RI")
8505 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8506 ; hurt us in the (rare) case of ahi.
8507 (set_attr "z10prop" "z10_super_E1")
8508 (set_attr "type" "branch")
8509 (set (attr "length")
8510 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8511 (const_int 4) (const_int 10)))])
8514 ;;- Unconditional jump instructions.
8518 ; jump instruction pattern(s).
8521 (define_expand "jump"
8522 [(match_operand 0 "" "")]
8524 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8526 (define_insn "*jump64"
8527 [(set (pc) (label_ref (match_operand 0 "" "")))]
8530 if (get_attr_length (insn) == 4)
8535 [(set_attr "op_type" "RI")
8536 (set_attr "type" "branch")
8537 (set (attr "length")
8538 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8539 (const_int 4) (const_int 6)))])
8541 (define_insn "*jump31"
8542 [(set (pc) (label_ref (match_operand 0 "" "")))]
8545 gcc_assert (get_attr_length (insn) == 4);
8548 [(set_attr "op_type" "RI")
8549 (set_attr "type" "branch")
8550 (set (attr "length")
8551 (if_then_else (not (match_test "flag_pic"))
8552 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8553 (const_int 4) (const_int 6))
8554 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8555 (const_int 4) (const_int 8))))])
8558 ; indirect-jump instruction pattern(s).
8561 (define_insn "indirect_jump"
8562 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8565 if (get_attr_op_type (insn) == OP_TYPE_RR)
8570 [(set (attr "op_type")
8571 (if_then_else (match_operand 0 "register_operand" "")
8572 (const_string "RR") (const_string "RX")))
8573 (set_attr "type" "branch")
8574 (set_attr "atype" "agen")])
8577 ; casesi instruction pattern(s).
8580 (define_insn "casesi_jump"
8581 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8582 (use (label_ref (match_operand 1 "" "")))]
8585 if (get_attr_op_type (insn) == OP_TYPE_RR)
8590 [(set (attr "op_type")
8591 (if_then_else (match_operand 0 "register_operand" "")
8592 (const_string "RR") (const_string "RX")))
8593 (set_attr "type" "branch")
8594 (set_attr "atype" "agen")])
8596 (define_expand "casesi"
8597 [(match_operand:SI 0 "general_operand" "")
8598 (match_operand:SI 1 "general_operand" "")
8599 (match_operand:SI 2 "general_operand" "")
8600 (label_ref (match_operand 3 "" ""))
8601 (label_ref (match_operand 4 "" ""))]
8604 rtx index = gen_reg_rtx (SImode);
8605 rtx base = gen_reg_rtx (Pmode);
8606 rtx target = gen_reg_rtx (Pmode);
8608 emit_move_insn (index, operands[0]);
8609 emit_insn (gen_subsi3 (index, index, operands[1]));
8610 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8613 if (Pmode != SImode)
8614 index = convert_to_mode (Pmode, index, 1);
8615 if (GET_CODE (index) != REG)
8616 index = copy_to_mode_reg (Pmode, index);
8619 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8621 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8623 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8625 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8626 emit_move_insn (target, index);
8629 target = gen_rtx_PLUS (Pmode, base, target);
8630 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8637 ;;- Jump to subroutine.
8642 ; untyped call instruction pattern(s).
8645 ;; Call subroutine returning any type.
8646 (define_expand "untyped_call"
8647 [(parallel [(call (match_operand 0 "" "")
8649 (match_operand 1 "" "")
8650 (match_operand 2 "" "")])]
8655 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8657 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8659 rtx set = XVECEXP (operands[2], 0, i);
8660 emit_move_insn (SET_DEST (set), SET_SRC (set));
8663 /* The optimizer does not know that the call sets the function value
8664 registers we stored in the result block. We avoid problems by
8665 claiming that all hard registers are used and clobbered at this
8667 emit_insn (gen_blockage ());
8672 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8673 ;; all of memory. This blocks insns from being moved across this point.
8675 (define_insn "blockage"
8676 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8679 [(set_attr "type" "none")
8680 (set_attr "length" "0")])
8686 (define_expand "sibcall"
8687 [(call (match_operand 0 "" "")
8688 (match_operand 1 "" ""))]
8691 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8695 (define_insn "*sibcall_br"
8696 [(call (mem:QI (reg SIBCALL_REGNUM))
8697 (match_operand 0 "const_int_operand" "n"))]
8698 "SIBLING_CALL_P (insn)
8699 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8701 [(set_attr "op_type" "RR")
8702 (set_attr "type" "branch")
8703 (set_attr "atype" "agen")])
8705 (define_insn "*sibcall_brc"
8706 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8707 (match_operand 1 "const_int_operand" "n"))]
8708 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8710 [(set_attr "op_type" "RI")
8711 (set_attr "type" "branch")])
8713 (define_insn "*sibcall_brcl"
8714 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8715 (match_operand 1 "const_int_operand" "n"))]
8716 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8718 [(set_attr "op_type" "RIL")
8719 (set_attr "type" "branch")])
8722 ; sibcall_value patterns
8725 (define_expand "sibcall_value"
8726 [(set (match_operand 0 "" "")
8727 (call (match_operand 1 "" "")
8728 (match_operand 2 "" "")))]
8731 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8735 (define_insn "*sibcall_value_br"
8736 [(set (match_operand 0 "" "")
8737 (call (mem:QI (reg SIBCALL_REGNUM))
8738 (match_operand 1 "const_int_operand" "n")))]
8739 "SIBLING_CALL_P (insn)
8740 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8742 [(set_attr "op_type" "RR")
8743 (set_attr "type" "branch")
8744 (set_attr "atype" "agen")])
8746 (define_insn "*sibcall_value_brc"
8747 [(set (match_operand 0 "" "")
8748 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8749 (match_operand 2 "const_int_operand" "n")))]
8750 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8752 [(set_attr "op_type" "RI")
8753 (set_attr "type" "branch")])
8755 (define_insn "*sibcall_value_brcl"
8756 [(set (match_operand 0 "" "")
8757 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8758 (match_operand 2 "const_int_operand" "n")))]
8759 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8761 [(set_attr "op_type" "RIL")
8762 (set_attr "type" "branch")])
8766 ; call instruction pattern(s).
8769 (define_expand "call"
8770 [(call (match_operand 0 "" "")
8771 (match_operand 1 "" ""))
8772 (use (match_operand 2 "" ""))]
8775 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8776 gen_rtx_REG (Pmode, RETURN_REGNUM));
8780 (define_insn "*bras"
8781 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8782 (match_operand 1 "const_int_operand" "n"))
8783 (clobber (match_operand 2 "register_operand" "=r"))]
8784 "!SIBLING_CALL_P (insn)
8785 && TARGET_SMALL_EXEC
8786 && GET_MODE (operands[2]) == Pmode"
8788 [(set_attr "op_type" "RI")
8789 (set_attr "type" "jsr")
8790 (set_attr "z196prop" "z196_cracked")])
8792 (define_insn "*brasl"
8793 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8794 (match_operand 1 "const_int_operand" "n"))
8795 (clobber (match_operand 2 "register_operand" "=r"))]
8796 "!SIBLING_CALL_P (insn)
8798 && GET_MODE (operands[2]) == Pmode"
8800 [(set_attr "op_type" "RIL")
8801 (set_attr "type" "jsr")
8802 (set_attr "z196prop" "z196_cracked")])
8804 (define_insn "*basr"
8805 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8806 (match_operand 1 "const_int_operand" "n"))
8807 (clobber (match_operand 2 "register_operand" "=r"))]
8808 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8810 if (get_attr_op_type (insn) == OP_TYPE_RR)
8811 return "basr\t%2,%0";
8813 return "bas\t%2,%a0";
8815 [(set (attr "op_type")
8816 (if_then_else (match_operand 0 "register_operand" "")
8817 (const_string "RR") (const_string "RX")))
8818 (set_attr "type" "jsr")
8819 (set_attr "atype" "agen")
8820 (set_attr "z196prop" "z196_cracked")])
8823 ; call_value instruction pattern(s).
8826 (define_expand "call_value"
8827 [(set (match_operand 0 "" "")
8828 (call (match_operand 1 "" "")
8829 (match_operand 2 "" "")))
8830 (use (match_operand 3 "" ""))]
8833 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8834 gen_rtx_REG (Pmode, RETURN_REGNUM));
8838 (define_insn "*bras_r"
8839 [(set (match_operand 0 "" "")
8840 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8841 (match_operand:SI 2 "const_int_operand" "n")))
8842 (clobber (match_operand 3 "register_operand" "=r"))]
8843 "!SIBLING_CALL_P (insn)
8844 && TARGET_SMALL_EXEC
8845 && GET_MODE (operands[3]) == Pmode"
8847 [(set_attr "op_type" "RI")
8848 (set_attr "type" "jsr")
8849 (set_attr "z196prop" "z196_cracked")])
8851 (define_insn "*brasl_r"
8852 [(set (match_operand 0 "" "")
8853 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8854 (match_operand 2 "const_int_operand" "n")))
8855 (clobber (match_operand 3 "register_operand" "=r"))]
8856 "!SIBLING_CALL_P (insn)
8858 && GET_MODE (operands[3]) == Pmode"
8860 [(set_attr "op_type" "RIL")
8861 (set_attr "type" "jsr")
8862 (set_attr "z196prop" "z196_cracked")])
8864 (define_insn "*basr_r"
8865 [(set (match_operand 0 "" "")
8866 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8867 (match_operand 2 "const_int_operand" "n")))
8868 (clobber (match_operand 3 "register_operand" "=r"))]
8869 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8871 if (get_attr_op_type (insn) == OP_TYPE_RR)
8872 return "basr\t%3,%1";
8874 return "bas\t%3,%a1";
8876 [(set (attr "op_type")
8877 (if_then_else (match_operand 1 "register_operand" "")
8878 (const_string "RR") (const_string "RX")))
8879 (set_attr "type" "jsr")
8880 (set_attr "atype" "agen")
8881 (set_attr "z196prop" "z196_cracked")])
8884 ;;- Thread-local storage support.
8887 (define_expand "get_thread_pointer<mode>"
8888 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8892 (define_expand "set_thread_pointer<mode>"
8893 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8894 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8898 (define_insn "*set_tp"
8899 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8902 [(set_attr "type" "none")
8903 (set_attr "length" "0")])
8905 (define_insn "*tls_load_64"
8906 [(set (match_operand:DI 0 "register_operand" "=d")
8907 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8908 (match_operand:DI 2 "" "")]
8912 [(set_attr "op_type" "RXE")
8913 (set_attr "z10prop" "z10_fwd_A3")])
8915 (define_insn "*tls_load_31"
8916 [(set (match_operand:SI 0 "register_operand" "=d,d")
8917 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8918 (match_operand:SI 2 "" "")]
8924 [(set_attr "op_type" "RX,RXY")
8925 (set_attr "type" "load")
8926 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8928 (define_insn "*bras_tls"
8929 [(set (match_operand 0 "" "")
8930 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8931 (match_operand 2 "const_int_operand" "n")))
8932 (clobber (match_operand 3 "register_operand" "=r"))
8933 (use (match_operand 4 "" ""))]
8934 "!SIBLING_CALL_P (insn)
8935 && TARGET_SMALL_EXEC
8936 && GET_MODE (operands[3]) == Pmode"
8938 [(set_attr "op_type" "RI")
8939 (set_attr "type" "jsr")
8940 (set_attr "z196prop" "z196_cracked")])
8942 (define_insn "*brasl_tls"
8943 [(set (match_operand 0 "" "")
8944 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8945 (match_operand 2 "const_int_operand" "n")))
8946 (clobber (match_operand 3 "register_operand" "=r"))
8947 (use (match_operand 4 "" ""))]
8948 "!SIBLING_CALL_P (insn)
8950 && GET_MODE (operands[3]) == Pmode"
8952 [(set_attr "op_type" "RIL")
8953 (set_attr "type" "jsr")
8954 (set_attr "z196prop" "z196_cracked")])
8956 (define_insn "*basr_tls"
8957 [(set (match_operand 0 "" "")
8958 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8959 (match_operand 2 "const_int_operand" "n")))
8960 (clobber (match_operand 3 "register_operand" "=r"))
8961 (use (match_operand 4 "" ""))]
8962 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8964 if (get_attr_op_type (insn) == OP_TYPE_RR)
8965 return "basr\t%3,%1%J4";
8967 return "bas\t%3,%a1%J4";
8969 [(set (attr "op_type")
8970 (if_then_else (match_operand 1 "register_operand" "")
8971 (const_string "RR") (const_string "RX")))
8972 (set_attr "type" "jsr")
8973 (set_attr "atype" "agen")
8974 (set_attr "z196prop" "z196_cracked")])
8977 ;;- Atomic operations
8981 ; memory barrier patterns.
8984 (define_expand "mem_signal_fence"
8985 [(match_operand:SI 0 "const_int_operand")] ;; model
8988 /* The s390 memory model is strong enough not to require any
8989 barrier in order to synchronize a thread with itself. */
8993 (define_expand "mem_thread_fence"
8994 [(match_operand:SI 0 "const_int_operand")] ;; model
8997 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8998 enough not to require barriers of any kind. */
8999 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
9001 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9002 MEM_VOLATILE_P (mem) = 1;
9003 emit_insn (gen_mem_thread_fence_1 (mem));
9008 ; Although bcr is superscalar on Z10, this variant will never
9009 ; become part of an execution group.
9010 ; With z196 we can make use of the fast-BCR-serialization facility.
9011 ; This allows for a slightly faster sync which is sufficient for our
9013 (define_insn "mem_thread_fence_1"
9014 [(set (match_operand:BLK 0 "" "")
9015 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9023 [(set_attr "op_type" "RR")
9024 (set_attr "mnemonic" "bcr_flush")
9025 (set_attr "z196prop" "z196_alone")])
9028 ; atomic load/store operations
9031 ; Atomic loads need not examine the memory model at all.
9032 (define_expand "atomic_load<mode>"
9033 [(match_operand:DINT 0 "register_operand") ;; output
9034 (match_operand:DINT 1 "memory_operand") ;; memory
9035 (match_operand:SI 2 "const_int_operand")] ;; model
9038 if (<MODE>mode == TImode)
9039 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9040 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9041 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9043 emit_move_insn (operands[0], operands[1]);
9047 ; Different from movdi_31 in that we want no splitters.
9048 (define_insn "atomic_loaddi_1"
9049 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9050 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9058 [(set_attr "op_type" "RS,RSY,RS,RSY")
9059 (set_attr "type" "lm,lm,floaddf,floaddf")])
9061 (define_insn "atomic_loadti_1"
9062 [(set (match_operand:TI 0 "register_operand" "=r")
9063 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9067 [(set_attr "op_type" "RXY")
9068 (set_attr "type" "other")])
9070 ; Atomic stores must(?) enforce sequential consistency.
9071 (define_expand "atomic_store<mode>"
9072 [(match_operand:DINT 0 "memory_operand") ;; memory
9073 (match_operand:DINT 1 "register_operand") ;; input
9074 (match_operand:SI 2 "const_int_operand")] ;; model
9077 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9079 if (<MODE>mode == TImode)
9080 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9081 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9082 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9084 emit_move_insn (operands[0], operands[1]);
9085 if (model == MEMMODEL_SEQ_CST)
9086 emit_insn (gen_mem_thread_fence (operands[2]));
9090 ; Different from movdi_31 in that we want no splitters.
9091 (define_insn "atomic_storedi_1"
9092 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9093 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9101 [(set_attr "op_type" "RS,RSY,RS,RSY")
9102 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9104 (define_insn "atomic_storeti_1"
9105 [(set (match_operand:TI 0 "memory_operand" "=RT")
9106 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9110 [(set_attr "op_type" "RXY")
9111 (set_attr "type" "other")])
9114 ; compare and swap patterns.
9117 (define_expand "atomic_compare_and_swap<mode>"
9118 [(match_operand:SI 0 "register_operand") ;; bool success output
9119 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9120 (match_operand:DGPR 2 "memory_operand") ;; memory
9121 (match_operand:DGPR 3 "register_operand") ;; expected intput
9122 (match_operand:DGPR 4 "register_operand") ;; newval intput
9123 (match_operand:SI 5 "const_int_operand") ;; is_weak
9124 (match_operand:SI 6 "const_int_operand") ;; success model
9125 (match_operand:SI 7 "const_int_operand")] ;; failure model
9128 rtx cc, cmp, output = operands[1];
9130 if (!register_operand (output, <MODE>mode))
9131 output = gen_reg_rtx (<MODE>mode);
9133 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9134 (output, operands[2], operands[3], operands[4]));
9136 /* We deliberately accept non-register operands in the predicate
9137 to ensure the write back to the output operand happens *before*
9138 the store-flags code below. This makes it easier for combine
9139 to merge the store-flags code with a potential test-and-branch
9140 pattern following (immediately!) afterwards. */
9141 if (output != operands[1])
9142 emit_move_insn (operands[1], output);
9144 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9145 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9146 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9150 (define_expand "atomic_compare_and_swap<mode>"
9151 [(match_operand:SI 0 "register_operand") ;; bool success output
9152 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9153 (match_operand:HQI 2 "memory_operand") ;; memory
9154 (match_operand:HQI 3 "general_operand") ;; expected intput
9155 (match_operand:HQI 4 "general_operand") ;; newval intput
9156 (match_operand:SI 5 "const_int_operand") ;; is_weak
9157 (match_operand:SI 6 "const_int_operand") ;; success model
9158 (match_operand:SI 7 "const_int_operand")] ;; failure model
9161 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9162 operands[3], operands[4], INTVAL (operands[5]));
9166 (define_expand "atomic_compare_and_swap<mode>_internal"
9168 [(set (match_operand:DGPR 0 "register_operand")
9169 (match_operand:DGPR 1 "memory_operand"))
9171 (unspec_volatile:DGPR
9173 (match_operand:DGPR 2 "register_operand")
9174 (match_operand:DGPR 3 "register_operand")]
9176 (set (reg:CCZ1 CC_REGNUM)
9177 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9181 (define_insn "*atomic_compare_and_swap<mode>_1"
9182 [(set (match_operand:TDI 0 "register_operand" "=r")
9183 (match_operand:TDI 1 "memory_operand" "+QS"))
9185 (unspec_volatile:TDI
9187 (match_operand:TDI 2 "register_operand" "0")
9188 (match_operand:TDI 3 "register_operand" "r")]
9190 (set (reg:CCZ1 CC_REGNUM)
9191 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9193 "c<td>sg\t%0,%3,%S1"
9194 [(set_attr "op_type" "RSY")
9195 (set_attr "type" "sem")])
9198 (define_insn "*atomic_compare_and_swapdi_2"
9199 [(set (match_operand:DI 0 "register_operand" "=r,r")
9200 (match_operand:DI 1 "memory_operand" "+Q,S"))
9204 (match_operand:DI 2 "register_operand" "0,0")
9205 (match_operand:DI 3 "register_operand" "r,r")]
9207 (set (reg:CCZ1 CC_REGNUM)
9208 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9213 [(set_attr "op_type" "RS,RSY")
9214 (set_attr "type" "sem")])
9217 (define_insn "*atomic_compare_and_swapsi_3"
9218 [(set (match_operand:SI 0 "register_operand" "=r,r")
9219 (match_operand:SI 1 "memory_operand" "+Q,S"))
9223 (match_operand:SI 2 "register_operand" "0,0")
9224 (match_operand:SI 3 "register_operand" "r,r")]
9226 (set (reg:CCZ1 CC_REGNUM)
9227 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9232 [(set_attr "op_type" "RS,RSY")
9233 (set_attr "type" "sem")])
9236 ; Other atomic instruction patterns.
9239 ; z196 load and add, xor, or and and instructions
9241 (define_expand "atomic_fetch_<atomic><mode>"
9242 [(match_operand:GPR 0 "register_operand") ;; val out
9244 (match_operand:GPR 1 "memory_operand") ;; memory
9245 (match_operand:GPR 2 "register_operand")) ;; val in
9246 (match_operand:SI 3 "const_int_operand")] ;; model
9249 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9250 (operands[0], operands[1], operands[2]));
9254 ; lan, lang, lao, laog, lax, laxg, laa, laag
9255 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9256 [(set (match_operand:GPR 0 "register_operand" "=d")
9257 (match_operand:GPR 1 "memory_operand" "+QS"))
9259 (unspec_volatile:GPR
9260 [(ATOMIC_Z196:GPR (match_dup 1)
9261 (match_operand:GPR 2 "general_operand" "d"))]
9263 (clobber (reg:CC CC_REGNUM))]
9265 "la<noxa><g>\t%0,%2,%1"
9266 [(set_attr "op_type" "RSY")
9267 (set_attr "type" "sem")])
9269 ;; For SImode and larger, the optabs.c code will do just fine in
9270 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9271 ;; better by expanding our own loop.
9273 (define_expand "atomic_<atomic><mode>"
9275 (match_operand:HQI 0 "memory_operand") ;; memory
9276 (match_operand:HQI 1 "general_operand")) ;; val in
9277 (match_operand:SI 2 "const_int_operand")] ;; model
9280 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9281 operands[1], false);
9285 (define_expand "atomic_fetch_<atomic><mode>"
9286 [(match_operand:HQI 0 "register_operand") ;; val out
9288 (match_operand:HQI 1 "memory_operand") ;; memory
9289 (match_operand:HQI 2 "general_operand")) ;; val in
9290 (match_operand:SI 3 "const_int_operand")] ;; model
9293 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9294 operands[2], false);
9298 (define_expand "atomic_<atomic>_fetch<mode>"
9299 [(match_operand:HQI 0 "register_operand") ;; val out
9301 (match_operand:HQI 1 "memory_operand") ;; memory
9302 (match_operand:HQI 2 "general_operand")) ;; val in
9303 (match_operand:SI 3 "const_int_operand")] ;; model
9306 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9311 (define_expand "atomic_exchange<mode>"
9312 [(match_operand:HQI 0 "register_operand") ;; val out
9313 (match_operand:HQI 1 "memory_operand") ;; memory
9314 (match_operand:HQI 2 "general_operand") ;; val in
9315 (match_operand:SI 3 "const_int_operand")] ;; model
9318 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9319 operands[2], false);
9324 ;;- Miscellaneous instructions.
9328 ; allocate stack instruction pattern(s).
9331 (define_expand "allocate_stack"
9332 [(match_operand 0 "general_operand" "")
9333 (match_operand 1 "general_operand" "")]
9336 rtx temp = gen_reg_rtx (Pmode);
9338 emit_move_insn (temp, s390_back_chain_rtx ());
9339 anti_adjust_stack (operands[1]);
9340 emit_move_insn (s390_back_chain_rtx (), temp);
9342 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9348 ; setjmp instruction pattern.
9351 (define_expand "builtin_setjmp_receiver"
9352 [(match_operand 0 "" "")]
9355 emit_insn (s390_load_got ());
9356 emit_use (pic_offset_table_rtx);
9360 ;; These patterns say how to save and restore the stack pointer. We need not
9361 ;; save the stack pointer at function level since we are careful to
9362 ;; preserve the backchain. At block level, we have to restore the backchain
9363 ;; when we restore the stack pointer.
9365 ;; For nonlocal gotos, we must save both the stack pointer and its
9366 ;; backchain and restore both. Note that in the nonlocal case, the
9367 ;; save area is a memory location.
9369 (define_expand "save_stack_function"
9370 [(match_operand 0 "general_operand" "")
9371 (match_operand 1 "general_operand" "")]
9375 (define_expand "restore_stack_function"
9376 [(match_operand 0 "general_operand" "")
9377 (match_operand 1 "general_operand" "")]
9381 (define_expand "restore_stack_block"
9382 [(match_operand 0 "register_operand" "")
9383 (match_operand 1 "register_operand" "")]
9386 rtx temp = gen_reg_rtx (Pmode);
9388 emit_move_insn (temp, s390_back_chain_rtx ());
9389 emit_move_insn (operands[0], operands[1]);
9390 emit_move_insn (s390_back_chain_rtx (), temp);
9395 (define_expand "save_stack_nonlocal"
9396 [(match_operand 0 "memory_operand" "")
9397 (match_operand 1 "register_operand" "")]
9400 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9402 /* Copy the backchain to the first word, sp to the second and the
9403 literal pool base to the third. */
9405 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9406 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9407 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9409 if (TARGET_BACKCHAIN)
9410 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9412 emit_move_insn (save_sp, operands[1]);
9413 emit_move_insn (save_bp, base);
9418 (define_expand "restore_stack_nonlocal"
9419 [(match_operand 0 "register_operand" "")
9420 (match_operand 1 "memory_operand" "")]
9423 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9424 rtx temp = NULL_RTX;
9426 /* Restore the backchain from the first word, sp from the second and the
9427 literal pool base from the third. */
9429 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9430 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9431 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9433 if (TARGET_BACKCHAIN)
9434 temp = force_reg (Pmode, save_bc);
9436 emit_move_insn (base, save_bp);
9437 emit_move_insn (operands[0], save_sp);
9440 emit_move_insn (s390_back_chain_rtx (), temp);
9446 (define_expand "exception_receiver"
9450 s390_set_has_landing_pad_p (true);
9455 ; nop instruction pattern(s).
9462 [(set_attr "op_type" "RR")
9463 (set_attr "z10prop" "z10_fr_E1")])
9469 [(set_attr "op_type" "RR")])
9473 ; Special literal pool access instruction pattern(s).
9476 (define_insn "*pool_entry"
9477 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9478 UNSPECV_POOL_ENTRY)]
9481 enum machine_mode mode = GET_MODE (PATTERN (insn));
9482 unsigned int align = GET_MODE_BITSIZE (mode);
9483 s390_output_pool_entry (operands[0], mode, align);
9486 [(set (attr "length")
9487 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9489 (define_insn "pool_align"
9490 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9491 UNSPECV_POOL_ALIGN)]
9494 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9496 (define_insn "pool_section_start"
9497 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9500 [(set_attr "length" "0")])
9502 (define_insn "pool_section_end"
9503 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9506 [(set_attr "length" "0")])
9508 (define_insn "main_base_31_small"
9509 [(set (match_operand 0 "register_operand" "=a")
9510 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9511 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9513 [(set_attr "op_type" "RR")
9514 (set_attr "type" "la")
9515 (set_attr "z196prop" "z196_cracked")])
9517 (define_insn "main_base_31_large"
9518 [(set (match_operand 0 "register_operand" "=a")
9519 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9520 (set (pc) (label_ref (match_operand 2 "" "")))]
9521 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9523 [(set_attr "op_type" "RI")
9524 (set_attr "z196prop" "z196_cracked")])
9526 (define_insn "main_base_64"
9527 [(set (match_operand 0 "register_operand" "=a")
9528 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9529 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9531 [(set_attr "op_type" "RIL")
9532 (set_attr "type" "larl")
9533 (set_attr "z10prop" "z10_fwd_A1")])
9535 (define_insn "main_pool"
9536 [(set (match_operand 0 "register_operand" "=a")
9537 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9538 "GET_MODE (operands[0]) == Pmode"
9543 (if_then_else (match_test "TARGET_CPU_ZARCH")
9544 (const_string "larl") (const_string "la")))])
9546 (define_insn "reload_base_31"
9547 [(set (match_operand 0 "register_operand" "=a")
9548 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9549 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9550 "basr\t%0,0\;la\t%0,%1-.(%0)"
9551 [(set_attr "length" "6")
9552 (set_attr "type" "la")
9553 (set_attr "z196prop" "z196_cracked")])
9555 (define_insn "reload_base_64"
9556 [(set (match_operand 0 "register_operand" "=a")
9557 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9558 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9560 [(set_attr "op_type" "RIL")
9561 (set_attr "type" "larl")
9562 (set_attr "z10prop" "z10_fwd_A1")])
9565 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9570 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9573 ;; Insns related to generating the function prologue and epilogue.
9577 (define_expand "prologue"
9578 [(use (const_int 0))]
9580 "s390_emit_prologue (); DONE;")
9582 (define_expand "epilogue"
9583 [(use (const_int 1))]
9585 "s390_emit_epilogue (false); DONE;")
9587 (define_expand "sibcall_epilogue"
9588 [(use (const_int 0))]
9590 "s390_emit_epilogue (true); DONE;")
9592 (define_insn "*return"
9594 (use (match_operand 0 "register_operand" "a"))]
9595 "GET_MODE (operands[0]) == Pmode"
9597 [(set_attr "op_type" "RR")
9598 (set_attr "type" "jsr")
9599 (set_attr "atype" "agen")])
9602 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9603 ;; pointer. This is used for compatibility.
9605 (define_expand "ptr_extend"
9606 [(set (match_operand:DI 0 "register_operand" "=r")
9607 (match_operand:SI 1 "register_operand" "r"))]
9610 emit_insn (gen_anddi3 (operands[0],
9611 gen_lowpart (DImode, operands[1]),
9612 GEN_INT (0x7fffffff)));
9616 ;; Instruction definition to expand eh_return macro to support
9617 ;; swapping in special linkage return addresses.
9619 (define_expand "eh_return"
9620 [(use (match_operand 0 "register_operand" ""))]
9623 s390_emit_tpf_eh_return (operands[0]);
9628 ; Stack Protector Patterns
9631 (define_expand "stack_protect_set"
9632 [(set (match_operand 0 "memory_operand" "")
9633 (match_operand 1 "memory_operand" ""))]
9636 #ifdef TARGET_THREAD_SSP_OFFSET
9638 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9639 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9642 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9644 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9649 (define_insn "stack_protect_set<mode>"
9650 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9651 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9653 "mvc\t%O0(%G0,%R0),%S1"
9654 [(set_attr "op_type" "SS")])
9656 (define_expand "stack_protect_test"
9657 [(set (reg:CC CC_REGNUM)
9658 (compare (match_operand 0 "memory_operand" "")
9659 (match_operand 1 "memory_operand" "")))
9660 (match_operand 2 "" "")]
9664 #ifdef TARGET_THREAD_SSP_OFFSET
9666 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9667 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9670 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9672 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9674 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9675 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9676 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9680 (define_insn "stack_protect_test<mode>"
9681 [(set (reg:CCZ CC_REGNUM)
9682 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9683 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9685 "clc\t%O0(%G0,%R0),%S1"
9686 [(set_attr "op_type" "SS")])
9688 ; This is used in s390_emit_prologue in order to prevent insns
9689 ; adjusting the stack pointer to be moved over insns writing stack
9690 ; slots using a copy of the stack pointer in a different register.
9691 (define_insn "stack_tie"
9692 [(set (match_operand:BLK 0 "memory_operand" "+m")
9693 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9696 [(set_attr "length" "0")])
9700 ; Data prefetch patterns
9703 (define_insn "prefetch"
9704 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9705 (match_operand:SI 1 "const_int_operand" " n,n")
9706 (match_operand:SI 2 "const_int_operand" " n,n"))]
9709 switch (which_alternative)
9712 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9714 if (larl_operand (operands[0], Pmode))
9715 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9718 /* This might be reached for symbolic operands with an odd
9719 addend. We simply omit the prefetch for such rare cases. */
9724 [(set_attr "type" "load,larl")
9725 (set_attr "op_type" "RXY,RIL")
9726 (set_attr "z10prop" "z10_super")
9727 (set_attr "z196prop" "z196_alone")])
9731 ; Byte swap instructions
9734 (define_insn "bswap<mode>2"
9735 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9736 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9741 [(set_attr "type" "*,load")
9742 (set_attr "op_type" "RRE,RXY")
9743 (set_attr "z10prop" "z10_super")])
9747 ; Population count instruction
9750 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9751 ; portions and stores the result in the corresponding bytes in op0.
9752 (define_insn "*popcount<mode>"
9753 [(set (match_operand:INT 0 "register_operand" "=d")
9754 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9755 (clobber (reg:CC CC_REGNUM))]
9758 [(set_attr "op_type" "RRE")])
9760 (define_expand "popcountdi2"
9762 (parallel [(set (match_operand:DI 0 "register_operand" "")
9763 (unspec:DI [(match_operand:DI 1 "register_operand")]
9765 (clobber (reg:CC CC_REGNUM))])
9767 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9769 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9770 (clobber (reg:CC CC_REGNUM))])
9773 (ashift:DI (match_dup 0) (const_int 16)))
9775 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9776 (clobber (reg:CC CC_REGNUM))])
9778 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9780 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9781 (clobber (reg:CC CC_REGNUM))])
9783 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9784 "TARGET_Z196 && TARGET_64BIT"
9785 "operands[2] = gen_reg_rtx (DImode);")
9787 (define_expand "popcountsi2"
9789 (parallel [(set (match_operand:SI 0 "register_operand" "")
9790 (unspec:SI [(match_operand:SI 1 "register_operand")]
9792 (clobber (reg:CC CC_REGNUM))])
9795 (ashift:SI (match_dup 0) (const_int 16)))
9797 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9798 (clobber (reg:CC CC_REGNUM))])
9800 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9802 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9803 (clobber (reg:CC CC_REGNUM))])
9805 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9807 "operands[2] = gen_reg_rtx (SImode);")
9809 (define_expand "popcounthi2"
9811 (parallel [(set (match_operand:HI 0 "register_operand" "")
9812 (unspec:HI [(match_operand:HI 1 "register_operand")]
9814 (clobber (reg:CC CC_REGNUM))])
9817 (ashift:SI (match_dup 0) (const_int 8)))
9819 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9820 (clobber (reg:CC CC_REGNUM))])
9822 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9824 "operands[2] = gen_reg_rtx (SImode);")
9826 (define_expand "popcountqi2"
9828 (parallel [(set (match_operand:QI 0 "register_operand" "")
9829 (unspec:QI [(match_operand:QI 1 "register_operand")]
9831 (clobber (reg:CC CC_REGNUM))])]
9836 ;;- Copy sign instructions
9839 (define_insn "copysign<mode>3"
9840 [(set (match_operand:FP 0 "register_operand" "=f")
9841 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9842 (match_operand:FP 2 "register_operand" "f")]
9846 [(set_attr "op_type" "RRF")
9847 (set_attr "type" "fsimp<mode>")])
9851 ;;- Transactional execution instructions
9854 ; This splitter helps combine to make use of CC directly when
9855 ; comparing the integer result of a tbegin builtin with a constant.
9856 ; The unspec is already removed by canonicalize_comparison. So this
9857 ; splitters only job is to turn the PARALLEL into separate insns
9858 ; again. Unfortunately this only works with the very first cc/int
9859 ; compare since combine is not able to deal with data flow across
9860 ; basic block boundaries.
9862 ; It needs to be an insn pattern as well since combine does not apply
9863 ; the splitter directly. Combine would only use it if it actually
9864 ; would reduce the number of instructions.
9865 (define_insn_and_split "*ccraw_to_int"
9868 (match_operator 0 "s390_eqne_operator"
9869 [(reg:CCRAW CC_REGNUM)
9870 (match_operand 1 "const_int_operand" "")])
9871 (label_ref (match_operand 2 "" ""))
9873 (set (match_operand:SI 3 "register_operand" "=d")
9874 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
9879 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
9881 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
9882 (label_ref (match_dup 2))
9886 ; Non-constrained transaction begin
9888 (define_expand "tbegin"
9889 [(match_operand:SI 0 "register_operand" "=d")
9890 (match_operand:BLK 1 "memory_operand" "=Q")]
9893 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
9897 (define_expand "tbegin_nofloat"
9898 [(match_operand:SI 0 "register_operand" "=d")
9899 (match_operand:BLK 1 "memory_operand" "=Q")]
9902 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
9906 (define_expand "tbegin_retry"
9907 [(match_operand:SI 0 "register_operand" "=d")
9908 (match_operand:BLK 1 "memory_operand" "=Q")
9909 (match_operand 2 "const_int_operand")]
9912 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
9916 (define_expand "tbegin_retry_nofloat"
9917 [(match_operand:SI 0 "register_operand" "=d")
9918 (match_operand:BLK 1 "memory_operand" "=Q")
9919 (match_operand 2 "const_int_operand")]
9922 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
9926 (define_insn "tbegin_1"
9927 [(set (reg:CCRAW CC_REGNUM)
9928 (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")
9929 (match_operand 1 "const_int_operand" " D")]
9931 (clobber (reg:DF 16))
9932 (clobber (reg:DF 17))
9933 (clobber (reg:DF 18))
9934 (clobber (reg:DF 19))
9935 (clobber (reg:DF 20))
9936 (clobber (reg:DF 21))
9937 (clobber (reg:DF 22))
9938 (clobber (reg:DF 23))
9939 (clobber (reg:DF 24))
9940 (clobber (reg:DF 25))
9941 (clobber (reg:DF 26))
9942 (clobber (reg:DF 27))
9943 (clobber (reg:DF 28))
9944 (clobber (reg:DF 29))
9945 (clobber (reg:DF 30))
9946 (clobber (reg:DF 31))]
9947 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
9948 ; not supposed to be used for immediates (see genpreds.c).
9949 "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
9951 [(set_attr "op_type" "SIL")])
9953 ; Same as above but without the FPR clobbers
9954 (define_insn "tbegin_nofloat_1"
9955 [(set (reg:CCRAW CC_REGNUM)
9956 (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q")
9957 (match_operand 1 "const_int_operand" " D")]
9959 "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff"
9961 [(set_attr "op_type" "SIL")])
9964 ; Constrained transaction begin
9966 (define_expand "tbeginc"
9967 [(set (reg:CCRAW CC_REGNUM)
9968 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
9973 (define_insn "*tbeginc_1"
9974 [(set (reg:CCRAW CC_REGNUM)
9975 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
9977 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
9979 [(set_attr "op_type" "SIL")])
9983 (define_expand "tend"
9984 [(set (reg:CCRAW CC_REGNUM)
9985 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
9986 (set (match_operand:SI 0 "register_operand" "=d")
9987 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
9991 (define_insn "*tend_1"
9992 [(set (reg:CCRAW CC_REGNUM)
9993 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
9996 [(set_attr "op_type" "S")])
10000 (define_expand "tabort"
10001 [(unspec_volatile [(match_operand 0 "shift_count_or_setmem_operand" "")]
10003 "TARGET_HTM && operands != NULL"
10005 if (CONST_INT_P (operands[0])
10006 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10008 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10009 ". Values in range 0 through 255 are reserved.",
10010 INTVAL (operands[0]));
10015 (define_insn "*tabort_1"
10016 [(unspec_volatile [(match_operand 0 "shift_count_or_setmem_operand" "")]
10018 "TARGET_HTM && operands != NULL"
10020 [(set_attr "op_type" "S")])
10022 ; Transaction extract nesting depth
10024 (define_insn "etnd"
10025 [(set (match_operand:SI 0 "register_operand" "=d")
10026 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10029 [(set_attr "op_type" "RRE")])
10031 ; Non-transactional store
10033 (define_insn "ntstg"
10034 [(set (match_operand:DI 0 "memory_operand" "=RT")
10035 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10039 [(set_attr "op_type" "RXY")])
10041 ; Transaction perform processor assist
10043 (define_expand "tx_assist"
10044 [(set (match_dup 1) (const_int 0))
10045 (unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10051 operands[1] = gen_reg_rtx (SImode);
10054 (define_insn "*ppa"
10055 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10056 (match_operand:SI 1 "register_operand" "d")
10057 (match_operand 2 "const_int_operand" "I")]
10059 "TARGET_HTM && INTVAL (operands[2]) < 16"
10061 [(set_attr "op_type" "RRF")])