1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
48 ;; Define an insn type attribute. This is used in function unit delay
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
58 (define_attr "atype" "reg,mem"
61 ;; Generic pipeline function unit.
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
117 ;; Operand type. Used to default length attribute values
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
143 ;; Define attributes for `asm' insns.
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
159 ; CCZ1 -> CCA/CCU/CCS/CCT
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
167 ;;- Compare instructions.
170 (define_expand "cmpdi"
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
182 (define_expand "cmpsi"
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
194 (define_expand "cmpdf"
196 (compare:CC (match_operand:DF 0 "register_operand" "")
197 (match_operand:DF 1 "general_operand" "")))]
201 s390_compare_op0 = operands[0];
202 s390_compare_op1 = operands[1];
206 (define_expand "cmpsf"
208 (compare:CC (match_operand:SF 0 "register_operand" "")
209 (match_operand:SF 1 "general_operand" "")))]
213 s390_compare_op0 = operands[0];
214 s390_compare_op1 = operands[1];
219 ; Test-under-Mask (zero_extract) instructions
221 (define_insn "*tmdi_ext"
223 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
224 (match_operand:DI 1 "const_int_operand" "n")
225 (match_operand:DI 2 "const_int_operand" "n"))
227 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
228 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
229 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
230 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
231 == INTVAL (operands[2]) >> 4"
234 int part = INTVAL (operands[2]) >> 4;
235 int block = (1 << INTVAL (operands[1])) - 1;
236 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
238 operands[2] = GEN_INT (block << shift);
242 case 0: return \"tmhh\\t%0,%x2\";
243 case 1: return \"tmhl\\t%0,%x2\";
244 case 2: return \"tmlh\\t%0,%x2\";
245 case 3: return \"tmll\\t%0,%x2\";
249 [(set_attr "op_type" "RI")])
251 (define_insn "*tmsi_ext"
253 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
254 (match_operand:SI 1 "const_int_operand" "n")
255 (match_operand:SI 2 "const_int_operand" "n"))
257 "s390_match_ccmode(insn, CCTmode)
258 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
259 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
260 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
261 == INTVAL (operands[2]) >> 4"
264 int part = INTVAL (operands[2]) >> 4;
265 int block = (1 << INTVAL (operands[1])) - 1;
266 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
268 operands[2] = GEN_INT (block << shift);
272 case 0: return \"tmh\\t%0,%x2\";
273 case 1: return \"tml\\t%0,%x2\";
277 [(set_attr "op_type" "RI")])
279 (define_insn "*tmqi_ext"
281 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
282 (match_operand:SI 1 "const_int_operand" "n")
283 (match_operand:SI 2 "const_int_operand" "n"))
285 "s390_match_ccmode(insn, CCTmode)
286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
290 int block = (1 << INTVAL (operands[1])) - 1;
291 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
293 operands[2] = GEN_INT (block << shift);
294 return \"tm\\t%0,%b2\";
296 [(set_attr "op_type" "SI")
297 (set_attr "atype" "mem")])
299 ; Test-under-Mask instructions
301 (define_insn "*tmdi_mem"
303 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
304 (match_operand:DI 1 "immediate_operand" "n"))
305 (match_operand:DI 2 "immediate_operand" "n")))]
307 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
308 && s390_single_qi (operands[1], DImode, 0) >= 0"
311 int part = s390_single_qi (operands[1], DImode, 0);
312 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
314 operands[0] = gen_rtx_MEM (QImode,
315 plus_constant (XEXP (operands[0], 0), part));
316 return \"tm\\t%0,%b1\";
318 [(set_attr "op_type" "SI")
319 (set_attr "atype" "mem")])
321 (define_insn "*tmsi_mem"
323 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
324 (match_operand:SI 1 "immediate_operand" "n"))
325 (match_operand:SI 2 "immediate_operand" "n")))]
326 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
327 && s390_single_qi (operands[1], SImode, 0) >= 0"
330 int part = s390_single_qi (operands[1], SImode, 0);
331 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
333 operands[0] = gen_rtx_MEM (QImode,
334 plus_constant (XEXP (operands[0], 0), part));
335 return \"tm\\t%0,%b1\";
337 [(set_attr "op_type" "SI")
338 (set_attr "atype" "mem")])
340 (define_insn "*tmhi_mem"
342 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
343 (match_operand:SI 1 "immediate_operand" "n"))
344 (match_operand:SI 2 "immediate_operand" "n")))]
345 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
346 && s390_single_qi (operands[1], HImode, 0) >= 0"
349 int part = s390_single_qi (operands[1], HImode, 0);
350 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
352 operands[0] = gen_rtx_MEM (QImode,
353 plus_constant (XEXP (operands[0], 0), part));
354 return \"tm\\t%0,%b1\";
356 [(set_attr "op_type" "SI")
357 (set_attr "atype" "mem")])
359 (define_insn "*tmqi_mem"
361 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
362 (match_operand:SI 1 "immediate_operand" "n"))
363 (match_operand:SI 2 "immediate_operand" "n")))]
364 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
366 [(set_attr "op_type" "SI")
367 (set_attr "atype" "mem")])
369 (define_insn "*tmdi_reg"
371 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
372 (match_operand:DI 1 "immediate_operand" "n"))
373 (match_operand:DI 2 "immediate_operand" "n")))]
375 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
376 && s390_single_hi (operands[1], DImode, 0) >= 0"
379 int part = s390_single_hi (operands[1], DImode, 0);
380 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
384 case 0: return \"tmhh\\t%0,%x1\";
385 case 1: return \"tmhl\\t%0,%x1\";
386 case 2: return \"tmlh\\t%0,%x1\";
387 case 3: return \"tmll\\t%0,%x1\";
391 [(set_attr "op_type" "RI")])
393 (define_insn "*tmsi_reg"
395 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
396 (match_operand:SI 1 "immediate_operand" "n"))
397 (match_operand:SI 2 "immediate_operand" "n")))]
398 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
399 && s390_single_hi (operands[1], SImode, 0) >= 0"
402 int part = s390_single_hi (operands[1], SImode, 0);
403 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
407 case 0: return \"tmh\\t%0,%x1\";
408 case 1: return \"tml\\t%0,%x1\";
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tmhi_full"
416 (compare (match_operand:HI 0 "register_operand" "d")
417 (match_operand:HI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
420 [(set_attr "op_type" "RX")])
422 (define_insn "*tmqi_full"
424 (compare (match_operand:QI 0 "register_operand" "d")
425 (match_operand:QI 1 "immediate_operand" "n")))]
426 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
428 [(set_attr "op_type" "RI")])
431 ; Load-and-Test instructions
433 (define_insn "*tstdi_sign"
435 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
436 (const_int 32)) (const_int 32))
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
439 (sign_extend:DI (match_dup 0)))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
442 [(set_attr "op_type" "RRE")])
444 (define_insn "*tstdi"
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))
448 (set (match_operand:DI 2 "register_operand" "=d")
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
452 [(set_attr "op_type" "RRE")])
454 (define_insn "*tstdi_cconly"
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
460 [(set_attr "op_type" "RRE")])
462 (define_insn "*tstdi_cconly_31"
464 (compare (match_operand:DI 0 "register_operand" "d")
465 (match_operand:DI 1 "const0_operand" "")))]
466 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
468 [(set_attr "op_type" "RS")])
470 (define_insn "*tstsi"
472 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
473 (match_operand:SI 1 "const0_operand" "")))
474 (set (match_operand:SI 2 "register_operand" "=d,d")
476 "s390_match_ccmode(insn, CCSmode)"
480 [(set_attr "op_type" "RR,RS")
481 (set_attr "atype" "reg,mem")])
483 (define_insn "*tstsi_cconly"
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
486 (match_operand:SI 1 "const0_operand" "")))
487 (clobber (match_scratch:SI 2 "=X,d"))]
488 "s390_match_ccmode(insn, CCSmode)"
492 [(set_attr "op_type" "RR,RS")
493 (set_attr "atype" "reg,mem")])
495 (define_insn "*tstsi_cconly2"
497 (compare (match_operand:SI 0 "register_operand" "d")
498 (match_operand:SI 1 "const0_operand" "")))]
499 "s390_match_ccmode(insn, CCSmode)"
501 [(set_attr "op_type" "RR")])
503 (define_insn "*tsthi"
505 (compare (match_operand:HI 0 "s_operand" "Q")
506 (match_operand:HI 1 "const0_operand" "")))
507 (set (match_operand:HI 2 "register_operand" "=d")
509 "s390_match_ccmode(insn, CCSmode)"
511 [(set_attr "op_type" "RS")
512 (set_attr "atype" "mem")])
514 (define_insn "*tsthi_cconly"
516 (compare (match_operand:HI 0 "s_operand" "Q")
517 (match_operand:HI 1 "const0_operand" "")))
518 (clobber (match_scratch:HI 2 "=d"))]
519 "s390_match_ccmode(insn, CCSmode)"
521 [(set_attr "op_type" "RS")
522 (set_attr "atype" "mem")])
524 (define_insn "*tstqi"
526 (compare (match_operand:QI 0 "s_operand" "Q")
527 (match_operand:QI 1 "const0_operand" "")))
528 (set (match_operand:QI 2 "register_operand" "=d")
530 "s390_match_ccmode(insn, CCSmode)"
532 [(set_attr "op_type" "RS")
533 (set_attr "atype" "mem")])
535 (define_insn "*tstqi_cconly"
537 (compare (match_operand:QI 0 "s_operand" "Q")
538 (match_operand:QI 1 "const0_operand" "")))
539 (clobber (match_scratch:QI 2 "=d"))]
540 "s390_match_ccmode(insn, CCSmode)"
542 [(set_attr "op_type" "RS")
543 (set_attr "atype" "mem")])
546 ; Compare (signed) instructions
548 (define_insn "*cmpdi_ccs_sign"
550 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
551 (match_operand:DI 0 "register_operand" "d,d")))]
552 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
556 [(set_attr "op_type" "RRE,RXE")
557 (set_attr "atype" "reg,mem")])
559 (define_insn "*cmpdi_ccs"
561 (compare (match_operand:DI 0 "register_operand" "d,d,d")
562 (match_operand:DI 1 "general_operand" "d,K,m")))]
563 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
568 [(set_attr "op_type" "RRE,RI,RXE")
569 (set_attr "atype" "reg,reg,mem")])
571 (define_insn "*cmpsi_ccs_sign"
573 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
574 (match_operand:SI 0 "register_operand" "d")))]
575 "s390_match_ccmode(insn, CCSRmode)"
577 [(set_attr "op_type" "RX")
578 (set_attr "atype" "mem")])
580 (define_insn "*cmpsi_ccs"
582 (compare (match_operand:SI 0 "register_operand" "d,d,d")
583 (match_operand:SI 1 "general_operand" "d,K,m")))]
584 "s390_match_ccmode(insn, CCSmode)"
589 [(set_attr "op_type" "RR,RI,RX")
590 (set_attr "atype" "reg,reg,mem")])
593 ; Compare (unsigned) instructions
595 (define_insn "*cmpdi_ccu_zero"
597 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
598 (match_operand:DI 0 "register_operand" "d,d")))]
599 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
603 [(set_attr "op_type" "RRE,RXE")
604 (set_attr "atype" "reg,mem")])
606 (define_insn "*cmpdi_ccu"
608 (compare (match_operand:DI 0 "register_operand" "d,d")
609 (match_operand:DI 1 "general_operand" "d,m")))]
610 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
614 [(set_attr "op_type" "RRE,RXE")
615 (set_attr "atype" "reg,mem")])
617 (define_insn "*cmpsi_ccu"
619 (compare (match_operand:SI 0 "register_operand" "d,d")
620 (match_operand:SI 1 "general_operand" "d,m")))]
621 "s390_match_ccmode(insn, CCUmode)"
625 [(set_attr "op_type" "RR,RX")
626 (set_attr "atype" "reg,mem")])
628 (define_insn "*cmphi_ccu"
630 (compare (match_operand:HI 0 "register_operand" "d")
631 (match_operand:HI 1 "s_imm_operand" "Q")))]
632 "s390_match_ccmode(insn, CCUmode)"
634 [(set_attr "op_type" "RS")
635 (set_attr "atype" "mem")])
637 (define_insn "*cmpqi_ccu"
639 (compare (match_operand:QI 0 "register_operand" "d")
640 (match_operand:QI 1 "s_imm_operand" "Q")))]
641 "s390_match_ccmode(insn, CCUmode)"
643 [(set_attr "op_type" "RS")
644 (set_attr "atype" "mem")])
648 (compare (match_operand:QI 0 "memory_operand" "Q")
649 (match_operand:QI 1 "immediate_operand" "n")))]
650 "s390_match_ccmode (insn, CCUmode)"
652 [(set_attr "op_type" "SI")
653 (set_attr "atype" "mem")])
655 (define_insn "*cmpdi_ccu_mem"
657 (compare (match_operand:DI 0 "s_operand" "Q")
658 (match_operand:DI 1 "s_imm_operand" "Q")))]
659 "s390_match_ccmode(insn, CCUmode)"
660 "clc\\t%O0(8,%R0),%1"
661 [(set_attr "op_type" "SS")
662 (set_attr "atype" "mem")])
664 (define_insn "*cmpsi_ccu_mem"
666 (compare (match_operand:SI 0 "s_operand" "Q")
667 (match_operand:SI 1 "s_imm_operand" "Q")))]
668 "s390_match_ccmode(insn, CCUmode)"
669 "clc\\t%O0(4,%R0),%1"
670 [(set_attr "op_type" "SS")
671 (set_attr "atype" "mem")])
673 (define_insn "*cmphi_ccu_mem"
675 (compare (match_operand:HI 0 "s_operand" "Q")
676 (match_operand:HI 1 "s_imm_operand" "Q")))]
677 "s390_match_ccmode(insn, CCUmode)"
678 "clc\\t%O0(2,%R0),%1"
679 [(set_attr "op_type" "SS")
680 (set_attr "atype" "mem")])
682 (define_insn "*cmpqi_ccu_mem"
684 (compare (match_operand:QI 0 "s_operand" "Q")
685 (match_operand:QI 1 "s_imm_operand" "Q")))]
686 "s390_match_ccmode(insn, CCUmode)"
687 "clc\\t%O0(1,%R0),%1"
688 [(set_attr "op_type" "SS")
689 (set_attr "atype" "mem")])
694 (define_insn "*cmpdf_ccs_0"
696 (compare (match_operand:DF 0 "register_operand" "f")
697 (match_operand:DF 1 "const0_operand" "")))]
698 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
700 [(set_attr "op_type" "RRE")])
702 (define_insn "*cmpdf_ccs_0_ibm"
704 (compare (match_operand:DF 0 "register_operand" "f")
705 (match_operand:DF 1 "const0_operand" "")))]
706 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
708 [(set_attr "op_type" "RR")])
710 (define_insn "*cmpdf_ccs"
712 (compare (match_operand:DF 0 "register_operand" "f,f")
713 (match_operand:DF 1 "general_operand" "f,m")))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
718 [(set_attr "op_type" "RRE,RXE")
719 (set_attr "atype" "reg,mem")])
721 (define_insn "*cmpdf_ccs_ibm"
723 (compare (match_operand:DF 0 "register_operand" "f,f")
724 (match_operand:DF 1 "general_operand" "f,m")))]
725 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
729 [(set_attr "op_type" "RR,RX")
730 (set_attr "atype" "reg,mem")])
735 (define_insn "*cmpsf_ccs_0"
737 (compare (match_operand:SF 0 "register_operand" "f")
738 (match_operand:SF 1 "const0_operand" "")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
741 [(set_attr "op_type" "RRE")])
743 (define_insn "*cmpsf_ccs_0_ibm"
745 (compare (match_operand:SF 0 "register_operand" "f")
746 (match_operand:SF 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
749 [(set_attr "op_type" "RR")])
751 (define_insn "*cmpsf_ccs"
753 (compare (match_operand:SF 0 "register_operand" "f,f")
754 (match_operand:SF 1 "general_operand" "f,m")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "atype" "reg,mem")])
762 (define_insn "*cmpsf_ccs"
764 (compare (match_operand:SF 0 "register_operand" "f,f")
765 (match_operand:SF 1 "general_operand" "f,m")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "atype" "reg,mem")])
775 ;;- Move instructions.
779 ; movti instruction pattern(s).
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
784 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
791 mvc\\t%O0(16,%R0),%1"
792 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
793 (set_attr "atype" "mem")])
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && !s_operand (operands[0], VOIDmode)
800 && !s_operand (operands[1], VOIDmode)
801 && (register_operand (operands[0], VOIDmode)
802 || register_operand (operands[1], VOIDmode))
803 && (!register_operand (operands[0], VOIDmode)
804 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
806 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
808 [(set (match_dup 2) (match_dup 4))
809 (set (match_dup 3) (match_dup 5))]
812 if (!register_operand (operands[0], VOIDmode)
813 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
816 operands[2] = operand_subword (operands[0], 0, 0, TImode);
817 operands[3] = operand_subword (operands[0], 1, 0, TImode);
818 operands[4] = operand_subword (operands[1], 0, 0, TImode);
819 operands[5] = operand_subword (operands[1], 1, 0, TImode);
823 operands[2] = operand_subword (operands[0], 1, 0, TImode);
824 operands[3] = operand_subword (operands[0], 0, 0, TImode);
825 operands[4] = operand_subword (operands[1], 1, 0, TImode);
826 operands[5] = operand_subword (operands[1], 0, 0, TImode);
831 [(set (match_operand:TI 0 "register_operand" "")
832 (match_operand:TI 1 "memory_operand" ""))]
833 "TARGET_64BIT && reload_completed
834 && !s_operand (operands[1], VOIDmode)"
835 [(set (match_dup 0) (match_dup 1))]
838 rtx addr = operand_subword (operands[0], 1, 0, TImode);
839 s390_load_address (addr, XEXP (operands[1], 0));
840 operands[1] = replace_equiv_address (operands[1], addr);
844 ; movdi instruction pattern(s).
847 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
848 ;; move to get the address of the symbolic object from the GOT.
850 (define_expand "movdi"
851 [(set (match_operand:DI 0 "general_operand" "")
852 (match_operand:DI 1 "general_operand" ""))]
856 /* Handle PIC symbolic constants. */
857 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
858 emit_pic_move (operands, DImode);
860 /* During and after reload, we need to force constants
861 to the literal pool ourselves, if necessary. */
862 if ((reload_in_progress || reload_completed)
863 && CONSTANT_P (operands[1])
864 && (!legitimate_reload_constant_p (operands[1])
865 || fp_operand (operands[0], VOIDmode)))
866 operands[1] = force_const_mem (DImode, operands[1]);
869 (define_insn "*movdi_lhi"
870 [(set (match_operand:DI 0 "register_operand" "=d")
871 (match_operand:DI 1 "immediate_operand" "K"))]
873 && GET_CODE (operands[1]) == CONST_INT
874 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
875 && !fp_operand (operands[0], VOIDmode)"
877 [(set_attr "op_type" "RI")
878 (set_attr "atype" "reg")])
880 (define_insn "*movdi_lli"
881 [(set (match_operand:DI 0 "register_operand" "=d")
882 (match_operand:DI 1 "immediate_operand" "n"))]
883 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
884 && !fp_operand (operands[0], VOIDmode)"
887 int part = s390_single_hi (operands[1], DImode, 0);
888 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
892 case 0: return \"llihh\\t%0,%x1\";
893 case 1: return \"llihl\\t%0,%x1\";
894 case 2: return \"llilh\\t%0,%x1\";
895 case 3: return \"llill\\t%0,%x1\";
899 [(set_attr "op_type" "RI")
900 (set_attr "atype" "reg")])
902 (define_insn "*movdi_larl"
903 [(set (match_operand:DI 0 "register_operand" "=d")
904 (match_operand:DI 1 "larl_operand" "X"))]
906 && !fp_operand (operands[0], VOIDmode)"
908 [(set_attr "op_type" "RIL")
909 (set_attr "atype" "reg")
910 (set_attr "type" "la")])
912 (define_insn "*movdi_64"
913 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
914 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
924 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX,SS")
925 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
927 (define_insn "*movdi_31"
928 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
929 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
940 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
941 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
944 [(set (match_operand:DI 0 "nonimmediate_operand" "")
945 (match_operand:DI 1 "general_operand" ""))]
946 "!TARGET_64BIT && reload_completed
947 && !fp_operand (operands[0], VOIDmode)
948 && !fp_operand (operands[1], VOIDmode)
949 && !s_operand (operands[0], VOIDmode)
950 && !s_operand (operands[1], VOIDmode)
951 && (register_operand (operands[0], VOIDmode)
952 || register_operand (operands[1], VOIDmode))
953 && (!register_operand (operands[0], VOIDmode)
954 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
956 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
958 [(set (match_dup 2) (match_dup 4))
959 (set (match_dup 3) (match_dup 5))]
962 if (!register_operand (operands[0], VOIDmode)
963 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
966 operands[2] = operand_subword (operands[0], 0, 0, DImode);
967 operands[3] = operand_subword (operands[0], 1, 0, DImode);
968 operands[4] = operand_subword (operands[1], 0, 0, DImode);
969 operands[5] = operand_subword (operands[1], 1, 0, DImode);
973 operands[2] = operand_subword (operands[0], 1, 0, DImode);
974 operands[3] = operand_subword (operands[0], 0, 0, DImode);
975 operands[4] = operand_subword (operands[1], 1, 0, DImode);
976 operands[5] = operand_subword (operands[1], 0, 0, DImode);
981 [(set (match_operand:DI 0 "register_operand" "")
982 (match_operand:DI 1 "memory_operand" ""))]
983 "!TARGET_64BIT && reload_completed
984 && !fp_operand (operands[0], VOIDmode)
985 && !fp_operand (operands[1], VOIDmode)
986 && !s_operand (operands[1], VOIDmode)"
987 [(set (match_dup 0) (match_dup 1))]
990 rtx addr = operand_subword (operands[0], 1, 0, DImode);
991 s390_load_address (addr, XEXP (operands[1], 0));
992 operands[1] = replace_equiv_address (operands[1], addr);
996 ; movsi instruction pattern(s).
999 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1000 ;; move to get the address of the symbolic object from the GOT.
1002 (define_expand "movsi"
1003 [(set (match_operand:SI 0 "general_operand" "")
1004 (match_operand:SI 1 "general_operand" ""))]
1008 /* Handle PIC symbolic constants. */
1009 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1010 emit_pic_move (operands, SImode);
1012 /* expr.c tries to load an effective address using
1013 force_reg. This fails because we don't have a
1014 generic load_address pattern. Convert the move
1015 to a proper arithmetic operation instead, unless
1016 it is guaranteed to be OK. */
1017 if (GET_CODE (operands[1]) == PLUS
1018 && !legitimate_la_operand_p (operands[1]))
1020 operands[1] = force_operand (operands[1], operands[0]);
1021 if (operands[1] == operands[0])
1025 /* During and after reload, we need to force constants
1026 to the literal pool ourselves, if necessary. */
1027 if ((reload_in_progress || reload_completed)
1028 && CONSTANT_P (operands[1])
1029 && (!legitimate_reload_constant_p (operands[1])
1030 || fp_operand (operands[0], VOIDmode)))
1031 operands[1] = force_const_mem (SImode, operands[1]);
1034 (define_insn "*movsi_lhi"
1035 [(set (match_operand:SI 0 "register_operand" "=d")
1036 (match_operand:SI 1 "immediate_operand" "K"))]
1037 "GET_CODE (operands[1]) == CONST_INT
1038 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1039 && !fp_operand (operands[0], VOIDmode)"
1041 [(set_attr "op_type" "RI")])
1043 (define_insn "*movsi_lli"
1044 [(set (match_operand:SI 0 "register_operand" "=d")
1045 (match_operand:SI 1 "immediate_operand" "n"))]
1046 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1047 && !fp_operand (operands[0], VOIDmode)"
1050 int part = s390_single_hi (operands[1], SImode, 0);
1051 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1055 case 0: return \"llilh\\t%0,%x1\";
1056 case 1: return \"llill\\t%0,%x1\";
1060 [(set_attr "op_type" "RI")])
1062 (define_insn "*movsi"
1063 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1064 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1073 mvc\\t%O0(4,%R0),%1"
1074 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1075 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1079 ; movhi instruction pattern(s).
1082 (define_insn "movhi"
1083 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1084 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1091 mvc\\t%O0(2,%R0),%1"
1092 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1093 (set_attr "atype" "reg,reg,mem,mem,mem")])
1097 ; movqi instruction pattern(s).
1100 (define_insn "movqi_64"
1101 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1102 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1110 mvc\\t%O0(1,%R0),%1"
1111 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1112 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1115 (define_insn "movqi"
1116 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1117 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1125 mvc\\t%O0(1,%R0),%1"
1126 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1127 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1131 ; movstrictqi instruction pattern(s).
1134 (define_insn "*movstrictqi"
1135 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1136 (match_operand:QI 1 "memory_operand" "m"))]
1139 [(set_attr "op_type" "RX")
1140 (set_attr "atype" "mem")])
1143 ; movstricthi instruction pattern(s).
1146 (define_insn "*movstricthi"
1147 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1148 (match_operand:HI 1 "s_imm_operand" "Q"))
1149 (clobber (reg:CC 33))]
1152 [(set_attr "op_type" "RS")
1153 (set_attr "atype" "mem")])
1157 ; movstrictsi instruction pattern(s).
1160 (define_insn "movstrictsi"
1161 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1162 (match_operand:SI 1 "general_operand" "d,m"))]
1167 [(set_attr "op_type" "RR,RS")
1168 (set_attr "atype" "reg,mem")])
1172 ; movdf instruction pattern(s).
1175 (define_expand "movdf"
1176 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1177 (match_operand:DF 1 "general_operand" ""))]
1181 /* During and after reload, we need to force constants
1182 to the literal pool ourselves, if necessary. */
1183 if ((reload_in_progress || reload_completed)
1184 && CONSTANT_P (operands[1]))
1185 operands[1] = force_const_mem (DFmode, operands[1]);
1188 (define_insn "*movdf_64"
1189 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1190 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1199 mvc\\t%O0(8,%R0),%1"
1200 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE,SS")
1201 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1203 (define_insn "*movdf_31"
1204 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1205 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1215 mvc\\t%O0(8,%R0),%1"
1216 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1217 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
1220 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1221 (match_operand:DF 1 "general_operand" ""))]
1222 "!TARGET_64BIT && reload_completed
1223 && !fp_operand (operands[0], VOIDmode)
1224 && !fp_operand (operands[1], VOIDmode)
1225 && !s_operand (operands[0], VOIDmode)
1226 && !s_operand (operands[1], VOIDmode)
1227 && (register_operand (operands[0], VOIDmode)
1228 || register_operand (operands[1], VOIDmode))
1229 && (!register_operand (operands[0], VOIDmode)
1230 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1232 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1234 [(set (match_dup 2) (match_dup 4))
1235 (set (match_dup 3) (match_dup 5))]
1238 if (!register_operand (operands[0], VOIDmode)
1239 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1242 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1243 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1244 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1245 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1249 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1250 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1251 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1252 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1257 [(set (match_operand:DF 0 "register_operand" "")
1258 (match_operand:DF 1 "memory_operand" ""))]
1259 "!TARGET_64BIT && reload_completed
1260 && !fp_operand (operands[0], VOIDmode)
1261 && !fp_operand (operands[1], VOIDmode)
1262 && !s_operand (operands[1], VOIDmode)"
1263 [(set (match_dup 0) (match_dup 1))]
1266 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1267 s390_load_address (addr, XEXP (operands[1], 0));
1268 operands[1] = replace_equiv_address (operands[1], addr);
1272 ; movsf instruction pattern(s).
1275 (define_expand "movsf"
1276 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1277 (match_operand:SF 1 "general_operand" ""))]
1281 /* During and after reload, we need to force constants
1282 to the literal pool ourselves, if necessary. */
1283 if ((reload_in_progress || reload_completed)
1284 && CONSTANT_P (operands[1]))
1285 operands[1] = force_const_mem (SFmode, operands[1]);
1288 (define_insn "*movsf"
1289 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1290 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1299 mvc\\t%O0(4,%R0),%1"
1300 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1301 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1304 ; load_multiple pattern(s).
1307 (define_expand "load_multiple"
1308 [(match_par_dup 3 [(set (match_operand 0 "" "")
1309 (match_operand 1 "" ""))
1310 (use (match_operand 2 "" ""))])]
1319 /* Support only loading a constant number of fixed-point registers from
1320 memory and only bother with this if more than two */
1321 if (GET_CODE (operands[2]) != CONST_INT
1322 || INTVAL (operands[2]) < 2
1323 || INTVAL (operands[2]) > 16
1324 || GET_CODE (operands[1]) != MEM
1325 || GET_CODE (operands[0]) != REG
1326 || REGNO (operands[0]) >= 16)
1329 count = INTVAL (operands[2]);
1330 regno = REGNO (operands[0]);
1332 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1335 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1337 from = XEXP (operands[1], 0);
1340 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1341 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1342 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1344 from = XEXP (XEXP (operands[1], 0), 0);
1345 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1350 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1355 from = force_reg (Pmode, XEXP (operands[1], 0));
1359 for (i = 0; i < count; i++)
1360 XVECEXP (operands[3], 0, i)
1361 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1362 change_address (operands[1], Pmode,
1363 plus_constant (from,
1364 off + i * UNITS_PER_WORD)));
1367 (define_insn "*load_multiple_di"
1368 [(match_parallel 0 "load_multiple_operation"
1369 [(set (match_operand:DI 1 "register_operand" "=r")
1370 (match_operand:DI 2 "s_operand" "Q"))])]
1374 int words = XVECLEN (operands[0], 0);
1376 if (XVECLEN (operands[0], 0) == 1)
1377 return \"lg\\t%1,0(%2)\";
1379 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1380 return \"lmg\\t%1,%0,%2\";
1382 [(set_attr "op_type" "RXE")
1383 (set_attr "atype" "mem")
1384 (set_attr "type" "lm")])
1386 (define_insn "*load_multiple_si"
1387 [(match_parallel 0 "load_multiple_operation"
1388 [(set (match_operand:SI 1 "register_operand" "=r")
1389 (match_operand:SI 2 "s_operand" "Q"))])]
1393 int words = XVECLEN (operands[0], 0);
1395 if (XVECLEN (operands[0], 0) == 1)
1396 return \"l\\t%1,0(%2)\";
1398 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1399 return \"lm\\t%1,%0,%2\";
1401 [(set_attr "op_type" "RXE")
1402 (set_attr "atype" "mem")
1403 (set_attr "type" "lm")])
1406 ; store multiple pattern(s).
1409 (define_expand "store_multiple"
1410 [(match_par_dup 3 [(set (match_operand 0 "" "")
1411 (match_operand 1 "" ""))
1412 (use (match_operand 2 "" ""))])]
1421 /* Support only storing a constant number of fixed-point registers to
1422 memory and only bother with this if more than two. */
1423 if (GET_CODE (operands[2]) != CONST_INT
1424 || INTVAL (operands[2]) < 2
1425 || INTVAL (operands[2]) > 16
1426 || GET_CODE (operands[0]) != MEM
1427 || GET_CODE (operands[1]) != REG
1428 || REGNO (operands[1]) >= 16)
1431 count = INTVAL (operands[2]);
1432 regno = REGNO (operands[1]);
1434 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1438 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1440 to = XEXP (operands[0], 0);
1443 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1444 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1445 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1447 to = XEXP (XEXP (operands[0], 0), 0);
1448 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1453 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1458 to = force_reg (Pmode, XEXP (operands[0], 0));
1462 for (i = 0; i < count; i++)
1463 XVECEXP (operands[3], 0, i)
1464 = gen_rtx_SET (VOIDmode,
1465 change_address (operands[0], Pmode,
1467 off + i * UNITS_PER_WORD)),
1468 gen_rtx_REG (Pmode, regno + i));
1471 (define_insn "*store_multiple_di"
1472 [(match_parallel 0 "store_multiple_operation"
1473 [(set (match_operand:DI 1 "s_operand" "=Q")
1474 (match_operand:DI 2 "register_operand" "r"))])]
1478 int words = XVECLEN (operands[0], 0);
1480 if (XVECLEN (operands[0], 0) == 1)
1481 return \"stg\\t%1,0(%2)\";
1483 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1484 return \"stmg\\t%2,%0,%1\";
1486 [(set_attr "op_type" "RXE")
1487 (set_attr "atype" "mem")
1488 (set_attr "type" "stm")])
1491 (define_insn "*store_multiple_si"
1492 [(match_parallel 0 "store_multiple_operation"
1493 [(set (match_operand:SI 1 "s_operand" "=Q")
1494 (match_operand:SI 2 "register_operand" "r"))])]
1498 int words = XVECLEN (operands[0], 0);
1500 if (XVECLEN (operands[0], 0) == 1)
1501 return \"st\\t%1,0(%2)\";
1503 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1504 return \"stm\\t%2,%0,%1\";
1506 [(set_attr "op_type" "RXE")
1507 (set_attr "atype" "mem")
1508 (set_attr "type" "stm")])
1511 ;; String instructions.
1515 ; movstrM instruction pattern(s).
1518 (define_expand "movstrdi"
1519 [(set (match_operand:BLK 0 "memory_operand" "")
1520 (match_operand:BLK 1 "memory_operand" ""))
1521 (use (match_operand:DI 2 "general_operand" ""))
1522 (match_operand 3 "" "")]
1524 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1526 (define_expand "movstrsi"
1527 [(set (match_operand:BLK 0 "memory_operand" "")
1528 (match_operand:BLK 1 "memory_operand" ""))
1529 (use (match_operand:SI 2 "general_operand" ""))
1530 (match_operand 3 "" "")]
1532 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1534 ; Move a block that is up to 256 bytes in length.
1535 ; The block length is taken as (operands[2] % 256) + 1.
1537 (define_insn "movstr_short_64"
1538 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1539 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1540 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1541 (clobber (match_scratch:DI 3 "=X,&a"))]
1545 switch (which_alternative)
1548 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1551 output_asm_insn (\"bras\\t%3,.+10\", operands);
1552 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1553 return \"ex\\t%2,0(%3)\";
1559 [(set_attr "op_type" "SS,NN")
1560 (set_attr "type" "cs,cs")
1561 (set_attr "atype" "mem,mem")
1562 (set_attr "length" "*,14")])
1564 (define_insn "movstr_short_31"
1565 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1566 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1567 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1568 (clobber (match_scratch:SI 3 "=X,&a"))]
1572 switch (which_alternative)
1575 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1578 output_asm_insn (\"bras\\t%3,.+10\", operands);
1579 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1580 return \"ex\\t%2,0(%3)\";
1586 [(set_attr "op_type" "SS,NN")
1587 (set_attr "type" "cs,cs")
1588 (set_attr "atype" "mem,mem")
1589 (set_attr "length" "*,14")])
1591 ; Move a block of arbitrary length.
1593 (define_insn "movstr_long_64"
1594 [(set (match_operand:TI 0 "register_operand" "=d")
1595 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1596 (lshiftrt:TI (match_dup 2) (const_int 64)))
1598 (set (match_operand:TI 1 "register_operand" "=d")
1599 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1600 (lshiftrt:TI (match_dup 3) (const_int 64)))
1602 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1603 (mem:BLK (subreg:DI (match_dup 3) 0)))
1604 (clobber (reg:CC 33))]
1606 "mvcle\\t%0,%1,0\;jo\\t.-4"
1607 [(set_attr "op_type" "NN")
1608 (set_attr "type" "vs")
1609 (set_attr "atype" "mem")
1610 (set_attr "length" "8")])
1612 (define_insn "movstr_long_31"
1613 [(set (match_operand:DI 0 "register_operand" "=d")
1614 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1615 (lshiftrt:DI (match_dup 2) (const_int 32)))
1617 (set (match_operand:DI 1 "register_operand" "=d")
1618 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1619 (lshiftrt:DI (match_dup 3) (const_int 32)))
1621 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1622 (mem:BLK (subreg:SI (match_dup 3) 0)))
1623 (clobber (reg:CC 33))]
1625 "mvcle\\t%0,%1,0\;jo\\t.-4"
1626 [(set_attr "op_type" "NN")
1627 (set_attr "type" "vs")
1628 (set_attr "atype" "mem")
1629 (set_attr "length" "8")])
1632 ; clrstrM instruction pattern(s).
1635 (define_expand "clrstrdi"
1636 [(set (match_operand:BLK 0 "memory_operand" "")
1638 (use (match_operand:DI 1 "general_operand" ""))
1639 (match_operand 2 "" "")]
1641 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1643 (define_expand "clrstrsi"
1644 [(set (match_operand:BLK 0 "memory_operand" "")
1646 (use (match_operand:SI 1 "general_operand" ""))
1647 (match_operand 2 "" "")]
1649 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1651 ; Clear a block that is up to 256 bytes in length.
1652 ; The block length is taken as (operands[2] % 256) + 1.
1654 (define_insn "clrstr_short_64"
1655 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1657 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1658 (clobber (match_scratch:DI 2 "=X,&a"))
1659 (clobber (reg:CC 33))]
1663 switch (which_alternative)
1666 return \"xc\\t%O0(%b1+1,%R0),%0\";
1669 output_asm_insn (\"bras\\t%2,.+10\", operands);
1670 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1671 return \"ex\\t%1,0(%2)\";
1677 [(set_attr "op_type" "SS,NN")
1678 (set_attr "type" "cs,cs")
1679 (set_attr "atype" "mem,mem")
1680 (set_attr "length" "*,14")])
1682 (define_insn "clrstr_short_31"
1683 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1685 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1686 (clobber (match_scratch:SI 2 "=X,&a"))
1687 (clobber (reg:CC 33))]
1691 switch (which_alternative)
1694 return \"xc\\t%O0(%b1+1,%R0),%0\";
1697 output_asm_insn (\"bras\\t%2,.+10\", operands);
1698 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1699 return \"ex\\t%1,0(%2)\";
1705 [(set_attr "op_type" "SS,NN")
1706 (set_attr "type" "cs,cs")
1707 (set_attr "atype" "mem,mem")
1708 (set_attr "length" "*,14")])
1710 ; Clear a block of arbitrary length.
1712 (define_insn "clrstr_long_64"
1713 [(set (match_operand:TI 0 "register_operand" "=d")
1714 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1715 (lshiftrt:TI (match_dup 2) (const_int 64)))
1717 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1719 (use (match_operand:TI 1 "register_operand" "d"))
1720 (clobber (reg:CC 33))]
1722 "mvcle\\t%0,%1,0\;jo\\t.-4"
1723 [(set_attr "op_type" "NN")
1724 (set_attr "atype" "mem")
1725 (set_attr "type" "vs")
1726 (set_attr "length" "8")])
1728 (define_insn "clrstr_long_31"
1729 [(set (match_operand:DI 0 "register_operand" "=d")
1730 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1731 (lshiftrt:DI (match_dup 2) (const_int 32)))
1733 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1735 (use (match_operand:DI 1 "register_operand" "d"))
1736 (clobber (reg:CC 33))]
1738 "mvcle\\t%0,%1,0\;jo\\t.-4"
1739 [(set_attr "op_type" "NN")
1740 (set_attr "atype" "mem")
1741 (set_attr "type" "vs")
1742 (set_attr "length" "8")])
1745 ; cmpstrM instruction pattern(s).
1748 (define_expand "cmpstrdi"
1749 [(set (match_operand:DI 0 "register_operand" "")
1750 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1751 (match_operand:BLK 2 "memory_operand" "") ) )
1752 (use (match_operand:DI 3 "general_operand" ""))
1753 (use (match_operand:DI 4 "" ""))]
1755 "s390_expand_cmpstr (operands[0], operands[1],
1756 operands[2], operands[3]); DONE;")
1758 (define_expand "cmpstrsi"
1759 [(set (match_operand:SI 0 "register_operand" "")
1760 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1761 (match_operand:BLK 2 "memory_operand" "") ) )
1762 (use (match_operand:SI 3 "general_operand" ""))
1763 (use (match_operand:SI 4 "" ""))]
1765 "s390_expand_cmpstr (operands[0], operands[1],
1766 operands[2], operands[3]); DONE;")
1768 ; Compare a block that is up to 256 bytes in length.
1769 ; The block length is taken as (operands[2] % 256) + 1.
1771 (define_insn "cmpstr_short_64"
1773 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1774 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1775 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1776 (clobber (match_scratch:DI 3 "=X,&a"))]
1780 switch (which_alternative)
1783 return \"clc\\t%O0(%b2+1,%R0),%1\";
1786 output_asm_insn (\"bras\\t%3,.+10\", operands);
1787 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1788 return \"ex\\t%2,0(%3)\";
1794 [(set_attr "op_type" "SS,NN")
1795 (set_attr "type" "cs,cs")
1796 (set_attr "atype" "mem,mem")
1797 (set_attr "length" "*,14")])
1799 (define_insn "cmpstr_short_31"
1801 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1802 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1803 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1804 (clobber (match_scratch:SI 3 "=X,&a"))]
1808 switch (which_alternative)
1811 return \"clc\\t%O0(%b2+1,%R0),%1\";
1814 output_asm_insn (\"bras\\t%3,.+10\", operands);
1815 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1816 return \"ex\\t%2,0(%3)\";
1822 [(set_attr "op_type" "SS,NN")
1823 (set_attr "type" "cs,cs")
1824 (set_attr "atype" "mem,mem")
1825 (set_attr "length" "*,14")])
1827 ; Compare a block of arbitrary length.
1829 (define_insn "cmpstr_long_64"
1830 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1831 (clobber (match_operand:TI 1 "register_operand" "=d"))
1833 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1834 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1836 (use (match_dup 3))]
1839 [(set_attr "op_type" "RR")
1840 (set_attr "atype" "mem")
1841 (set_attr "type" "vs")])
1843 (define_insn "cmpstr_long_31"
1844 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1845 (clobber (match_operand:DI 1 "register_operand" "=d"))
1847 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1848 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1850 (use (match_dup 3))]
1853 [(set_attr "op_type" "RR")
1854 (set_attr "atype" "mem")
1855 (set_attr "type" "vs")])
1857 ; Convert condition code to integer in range (-1, 0, 1)
1859 (define_insn "cmpint_si"
1860 [(set (match_operand:SI 0 "register_operand" "=d")
1861 (compare:SI (reg:CCS 33) (const_int 0)))]
1865 output_asm_insn (\"lhi\\t%0,1\", operands);
1866 output_asm_insn (\"jh\\t.+12\", operands);
1867 output_asm_insn (\"jl\\t.+6\", operands);
1868 output_asm_insn (\"sr\\t%0,%0\", operands);
1869 return \"lcr\\t%0,%0\";
1871 [(set_attr "op_type" "NN")
1872 (set_attr "length" "16")
1873 (set_attr "atype" "reg")
1874 (set_attr "type" "other")])
1876 (define_insn "cmpint_di"
1877 [(set (match_operand:DI 0 "register_operand" "=d")
1878 (compare:DI (reg:CCS 33) (const_int 0)))]
1882 output_asm_insn (\"lghi\\t%0,1\", operands);
1883 output_asm_insn (\"jh\\t.+12\", operands);
1884 output_asm_insn (\"jl\\t.+6\", operands);
1885 output_asm_insn (\"sgr\\t%0,%0\", operands);
1886 return \"lcgr\\t%0,%0\";
1888 [(set_attr "op_type" "NN")
1889 (set_attr "length" "22")
1890 (set_attr "atype" "reg")
1891 (set_attr "type" "other")])
1895 ;;- Conversion instructions.
1898 (define_insn "*sethighqisi"
1899 [(set (match_operand:SI 0 "register_operand" "=d")
1900 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
1901 (clobber (reg:CC 33))]
1904 [(set_attr "op_type" "RS")
1905 (set_attr "atype" "mem")])
1907 (define_insn "*sethighhisi"
1908 [(set (match_operand:SI 0 "register_operand" "=d")
1909 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
1910 (clobber (reg:CC 33))]
1913 [(set_attr "op_type" "RS")
1914 (set_attr "atype" "mem")])
1916 (define_insn "*sethighqidi_64"
1917 [(set (match_operand:DI 0 "register_operand" "=d")
1918 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1919 (clobber (reg:CC 33))]
1922 [(set_attr "op_type" "RSE")
1923 (set_attr "atype" "mem")])
1925 (define_insn "*sethighqidi_31"
1926 [(set (match_operand:DI 0 "register_operand" "=d")
1927 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1928 (clobber (reg:CC 33))]
1931 [(set_attr "op_type" "RS")
1932 (set_attr "atype" "mem")])
1934 (define_insn_and_split "*extractqi"
1935 [(set (match_operand:SI 0 "register_operand" "=d")
1936 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
1937 (match_operand 2 "const_int_operand" "n")
1939 (clobber (reg:CC 33))]
1941 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
1943 "&& reload_completed"
1945 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1946 (clobber (reg:CC 33))])
1947 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1950 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1951 operands[1] = change_address (operands[1], QImode, 0);
1953 [(set_attr "type" "o2")
1954 (set_attr "atype" "mem")])
1956 (define_insn_and_split "*extracthi"
1957 [(set (match_operand:SI 0 "register_operand" "=d")
1958 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
1959 (match_operand 2 "const_int_operand" "n")
1961 (clobber (reg:CC 33))]
1963 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
1965 "&& reload_completed"
1967 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1968 (clobber (reg:CC 33))])
1969 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1972 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1973 operands[1] = change_address (operands[1], HImode, 0);
1975 [(set_attr "type" "o2")
1976 (set_attr "atype" "mem")])
1979 ; extendsidi2 instruction pattern(s).
1982 (define_expand "extendsidi2"
1983 [(set (match_operand:DI 0 "register_operand" "")
1984 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
1990 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
1991 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
1992 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
1993 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
1999 (define_insn "*extendsidi2"
2000 [(set (match_operand:DI 0 "register_operand" "=d,d")
2001 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2006 [(set_attr "op_type" "RRE,RXE")
2007 (set_attr "atype" "reg,mem")])
2010 ; extendhidi2 instruction pattern(s).
2013 (define_expand "extendhidi2"
2014 [(set (match_operand:DI 0 "register_operand" "")
2015 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2021 rtx tmp = gen_reg_rtx (SImode);
2022 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2023 emit_insn (gen_extendsidi2 (operands[0], tmp));
2028 operands[1] = gen_lowpart (DImode, operands[1]);
2029 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2030 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2036 (define_insn "*extendhidi2"
2037 [(set (match_operand:DI 0 "register_operand" "=d")
2038 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2041 [(set_attr "op_type" "RXE")
2042 (set_attr "atype" "mem")])
2045 ; extendqidi2 instruction pattern(s).
2048 (define_expand "extendqidi2"
2049 [(set (match_operand:DI 0 "register_operand" "")
2050 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2056 rtx tmp = gen_reg_rtx (SImode);
2057 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2058 emit_insn (gen_extendsidi2 (operands[0], tmp));
2063 operands[1] = gen_lowpart (DImode, operands[1]);
2064 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2065 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2072 [(set (match_operand:DI 0 "register_operand" "")
2073 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2074 "TARGET_64BIT && !reload_completed"
2076 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2077 (clobber (reg:CC 33))])
2079 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2080 (clobber (reg:CC 33))])]
2084 ; extendhisi2 instruction pattern(s).
2087 (define_expand "extendhisi2"
2088 [(set (match_operand:SI 0 "register_operand" "")
2089 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2093 operands[1] = gen_lowpart (SImode, operands[1]);
2094 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2095 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2100 (define_insn "*extendhisi2"
2101 [(set (match_operand:SI 0 "register_operand" "=d")
2102 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2105 [(set_attr "op_type" "RX")
2106 (set_attr "atype" "mem")])
2109 ; extendqisi2 instruction pattern(s).
2112 (define_expand "extendqisi2"
2113 [(set (match_operand:SI 0 "register_operand" "")
2114 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2118 operands[1] = gen_lowpart (SImode, operands[1]);
2119 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2120 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2126 [(set (match_operand:SI 0 "register_operand" "")
2127 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2130 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2131 (clobber (reg:CC 33))])
2133 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2134 (clobber (reg:CC 33))])]
2138 ; extendqihi2 instruction pattern(s).
2143 ; zero_extendsidi2 instruction pattern(s).
2146 (define_expand "zero_extendsidi2"
2147 [(set (match_operand:DI 0 "register_operand" "")
2148 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2154 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2155 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2156 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2162 (define_insn "*zero_extendsidi2"
2163 [(set (match_operand:DI 0 "register_operand" "=d,d")
2164 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2169 [(set_attr "op_type" "RRE,RXE")
2170 (set_attr "atype" "reg,mem")])
2173 ; zero_extendhidi2 instruction pattern(s).
2176 (define_expand "zero_extendhidi2"
2177 [(set (match_operand:DI 0 "register_operand" "")
2178 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2184 rtx tmp = gen_reg_rtx (SImode);
2185 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2186 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2191 operands[1] = gen_lowpart (DImode, operands[1]);
2192 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2193 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2199 (define_insn "*zero_extendhidi2"
2200 [(set (match_operand:DI 0 "register_operand" "=d")
2201 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2204 [(set_attr "op_type" "RXE")
2205 (set_attr "atype" "mem")])
2208 ; zero_extendqidi2 instruction pattern(s)
2211 (define_expand "zero_extendqidi2"
2212 [(set (match_operand:DI 0 "register_operand" "")
2213 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2219 rtx tmp = gen_reg_rtx (SImode);
2220 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2221 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2226 operands[1] = gen_lowpart (DImode, operands[1]);
2227 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2228 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2234 (define_insn "*zero_extendqidi2"
2235 [(set (match_operand:DI 0 "register_operand" "=d")
2236 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2239 [(set_attr "op_type" "RXE")
2240 (set_attr "atype" "mem")])
2243 ; zero_extendhisi2 instruction pattern(s).
2246 (define_expand "zero_extendhisi2"
2247 [(set (match_operand:SI 0 "register_operand" "")
2248 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2252 operands[1] = gen_lowpart (SImode, operands[1]);
2253 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2258 (define_insn "*zero_extendhisi2_64"
2259 [(set (match_operand:SI 0 "register_operand" "=d")
2260 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2263 [(set_attr "op_type" "RXE")
2264 (set_attr "atype" "mem")])
2266 (define_insn_and_split "*zero_extendhisi2_31"
2267 [(set (match_operand:SI 0 "register_operand" "=&d")
2268 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2269 (clobber (reg:CC 33))]
2272 "&& reload_completed"
2273 [(set (match_dup 0) (const_int 0))
2275 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2276 (clobber (reg:CC 33))])]
2277 "operands[2] = gen_lowpart (HImode, operands[0]);"
2278 [(set_attr "type" "o2")
2279 (set_attr "atype" "mem")])
2282 ; zero_extendqisi2 instruction pattern(s).
2285 (define_expand "zero_extendqisi2"
2286 [(set (match_operand:SI 0 "register_operand" "")
2287 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2291 operands[1] = gen_lowpart (SImode, operands[1]);
2292 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2297 (define_insn "*zero_extendqisi2_64"
2298 [(set (match_operand:SI 0 "register_operand" "=d")
2299 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2302 [(set_attr "op_type" "RXE")
2303 (set_attr "atype" "mem")])
2305 (define_insn_and_split "*zero_extendqisi2_31"
2306 [(set (match_operand:SI 0 "register_operand" "=&d")
2307 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2310 "&& reload_completed"
2311 [(set (match_dup 0) (const_int 0))
2312 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2313 "operands[2] = gen_lowpart (QImode, operands[0]);"
2314 [(set_attr "type" "o2")
2315 (set_attr "atype" "mem")])
2318 ; zero_extendqihi2 instruction pattern(s).
2321 (define_expand "zero_extendqihi2"
2322 [(set (match_operand:HI 0 "register_operand" "")
2323 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2327 operands[1] = gen_lowpart (HImode, operands[1]);
2328 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2333 (define_insn "*zero_extendqihi2_64"
2334 [(set (match_operand:HI 0 "register_operand" "=d")
2335 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2338 [(set_attr "op_type" "RXE")
2339 (set_attr "atype" "mem")])
2341 (define_insn_and_split "*zero_extendqihi2_31"
2342 [(set (match_operand:HI 0 "register_operand" "=&d")
2343 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2346 "&& reload_completed"
2347 [(set (match_dup 0) (const_int 0))
2348 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2349 "operands[2] = gen_lowpart (QImode, operands[0]);"
2350 [(set_attr "type" "o2")
2351 (set_attr "atype" "mem")])
2355 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2358 (define_expand "fixuns_truncdfdi2"
2359 [(set (match_operand:DI 0 "register_operand" "")
2360 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2361 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2364 rtx label1 = gen_label_rtx ();
2365 rtx label2 = gen_label_rtx ();
2366 rtx temp = gen_reg_rtx (DFmode);
2367 operands[1] = force_reg (DFmode, operands[1]);
2369 emit_insn (gen_cmpdf (operands[1],
2370 CONST_DOUBLE_FROM_REAL_VALUE (
2371 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2372 emit_jump_insn (gen_blt (label1));
2373 emit_insn (gen_subdf3 (temp, operands[1],
2374 CONST_DOUBLE_FROM_REAL_VALUE (
2375 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2376 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2379 emit_label (label1);
2380 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2381 emit_label (label2);
2385 (define_expand "fix_truncdfdi2"
2386 [(set (match_operand:DI 0 "register_operand" "")
2387 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2388 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2391 operands[1] = force_reg (DFmode, operands[1]);
2392 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2396 (define_insn "fix_truncdfdi2_ieee"
2397 [(set (match_operand:DI 0 "register_operand" "=d")
2398 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2399 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2400 (clobber (reg:CC 33))]
2401 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2403 [(set_attr "op_type" "RRE")
2404 (set_attr "type" "other")])
2407 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2410 (define_expand "fixuns_truncdfsi2"
2411 [(set (match_operand:SI 0 "register_operand" "")
2412 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2413 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2416 rtx label1 = gen_label_rtx ();
2417 rtx label2 = gen_label_rtx ();
2418 rtx temp = gen_reg_rtx (DFmode);
2420 operands[1] = force_reg (DFmode,operands[1]);
2421 emit_insn (gen_cmpdf (operands[1],
2422 CONST_DOUBLE_FROM_REAL_VALUE (
2423 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2424 emit_jump_insn (gen_blt (label1));
2425 emit_insn (gen_subdf3 (temp, operands[1],
2426 CONST_DOUBLE_FROM_REAL_VALUE (
2427 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2428 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2431 emit_label (label1);
2432 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2433 emit_label (label2);
2437 (define_expand "fix_truncdfsi2"
2438 [(set (match_operand:SI 0 "register_operand" "")
2439 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2443 if (TARGET_IBM_FLOAT)
2445 /* This is the algorithm from POP chapter A.5.7.2. */
2447 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2448 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2449 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2451 operands[1] = force_reg (DFmode, operands[1]);
2452 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2453 two31r, two32, temp));
2457 operands[1] = force_reg (DFmode, operands[1]);
2458 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2464 (define_insn "fix_truncdfsi2_ieee"
2465 [(set (match_operand:SI 0 "register_operand" "=d")
2466 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2467 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2468 (clobber (reg:CC 33))]
2469 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2471 [(set_attr "op_type" "RRE")
2472 (set_attr "type" "other" )])
2474 (define_insn "fix_truncdfsi2_ibm"
2475 [(set (match_operand:SI 0 "register_operand" "=d")
2476 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2477 (use (match_operand:DI 2 "immediate_operand" "m"))
2478 (use (match_operand:DI 3 "immediate_operand" "m"))
2479 (use (match_operand:BLK 4 "memory_operand" "m"))
2480 (clobber (reg:CC 33))]
2481 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2484 output_asm_insn (\"sd\\t%1,%2\", operands);
2485 output_asm_insn (\"aw\\t%1,%3\", operands);
2486 output_asm_insn (\"std\\t%1,%4\", operands);
2487 output_asm_insn (\"xi\\t%N4,128\", operands);
2488 return \"l\\t%0,%N4\";
2490 [(set_attr "op_type" "NN")
2491 (set_attr "type" "other")
2492 (set_attr "length" "20")])
2495 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2498 (define_expand "fixuns_truncsfdi2"
2499 [(set (match_operand:DI 0 "register_operand" "")
2500 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2501 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2504 rtx label1 = gen_label_rtx ();
2505 rtx label2 = gen_label_rtx ();
2506 rtx temp = gen_reg_rtx (SFmode);
2508 operands[1] = force_reg (SFmode, operands[1]);
2509 emit_insn (gen_cmpsf (operands[1],
2510 CONST_DOUBLE_FROM_REAL_VALUE (
2511 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2512 emit_jump_insn (gen_blt (label1));
2514 emit_insn (gen_subsf3 (temp, operands[1],
2515 CONST_DOUBLE_FROM_REAL_VALUE (
2516 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2517 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2520 emit_label (label1);
2521 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2522 emit_label (label2);
2526 (define_expand "fix_truncsfdi2"
2527 [(set (match_operand:DI 0 "register_operand" "")
2528 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2529 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2532 operands[1] = force_reg (SFmode, operands[1]);
2533 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2537 (define_insn "fix_truncsfdi2_ieee"
2538 [(set (match_operand:DI 0 "register_operand" "=d")
2539 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2540 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2541 (clobber (reg:CC 33))]
2542 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2544 [(set_attr "op_type" "RRE")
2545 (set_attr "type" "other")])
2548 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2551 (define_expand "fixuns_truncsfsi2"
2552 [(set (match_operand:SI 0 "register_operand" "")
2553 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2554 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2557 rtx label1 = gen_label_rtx ();
2558 rtx label2 = gen_label_rtx ();
2559 rtx temp = gen_reg_rtx (SFmode);
2561 operands[1] = force_reg (SFmode, operands[1]);
2562 emit_insn (gen_cmpsf (operands[1],
2563 CONST_DOUBLE_FROM_REAL_VALUE (
2564 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2565 emit_jump_insn (gen_blt (label1));
2566 emit_insn (gen_subsf3 (temp, operands[1],
2567 CONST_DOUBLE_FROM_REAL_VALUE (
2568 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2569 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2572 emit_label (label1);
2573 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2574 emit_label (label2);
2578 (define_expand "fix_truncsfsi2"
2579 [(set (match_operand:SI 0 "register_operand" "")
2580 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2584 if (TARGET_IBM_FLOAT)
2586 /* Convert to DFmode and then use the POP algorithm. */
2587 rtx temp = gen_reg_rtx (DFmode);
2588 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2589 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2593 operands[1] = force_reg (SFmode, operands[1]);
2594 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2600 (define_insn "fix_truncsfsi2_ieee"
2601 [(set (match_operand:SI 0 "register_operand" "=d")
2602 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2603 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2604 (clobber (reg:CC 33))]
2605 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2607 [(set_attr "op_type" "RRE")
2608 (set_attr "type" "other")])
2611 ; floatdidf2 instruction pattern(s).
2614 (define_insn "floatdidf2"
2615 [(set (match_operand:DF 0 "register_operand" "=f")
2616 (float:DF (match_operand:DI 1 "register_operand" "d")))
2617 (clobber (reg:CC 33))]
2618 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2620 [(set_attr "op_type" "RRE")
2621 (set_attr "type" "other" )])
2624 ; floatdisf2 instruction pattern(s).
2627 (define_insn "floatdisf2"
2628 [(set (match_operand:SF 0 "register_operand" "=f")
2629 (float:SF (match_operand:DI 1 "register_operand" "d")))
2630 (clobber (reg:CC 33))]
2631 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2633 [(set_attr "op_type" "RRE")
2634 (set_attr "type" "other" )])
2637 ; floatsidf2 instruction pattern(s).
2640 (define_expand "floatsidf2"
2642 [(set (match_operand:DF 0 "register_operand" "")
2643 (float:DF (match_operand:SI 1 "register_operand" "")))
2644 (clobber (reg:CC 33))])]
2648 if (TARGET_IBM_FLOAT)
2650 /* This is the algorithm from POP chapter A.5.7.1. */
2652 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2653 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2655 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2660 (define_insn "floatsidf2_ieee"
2661 [(set (match_operand:DF 0 "register_operand" "=f")
2662 (float:DF (match_operand:SI 1 "register_operand" "d")))
2663 (clobber (reg:CC 33))]
2664 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2666 [(set_attr "op_type" "RRE")
2667 (set_attr "type" "other" )])
2669 (define_insn "floatsidf2_ibm"
2670 [(set (match_operand:DF 0 "register_operand" "=f")
2671 (float:DF (match_operand:SI 1 "register_operand" "d")))
2672 (use (match_operand:DI 2 "immediate_operand" "m"))
2673 (use (match_operand:BLK 3 "memory_operand" "m"))
2674 (clobber (reg:CC 33))]
2675 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2678 output_asm_insn (\"st\\t%1,%N3\", operands);
2679 output_asm_insn (\"xi\\t%N3,128\", operands);
2680 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2681 output_asm_insn (\"ld\\t%0,%3\", operands);
2682 return \"sd\\t%0,%2\";
2684 [(set_attr "op_type" "NN")
2685 (set_attr "type" "other" )
2686 (set_attr "length" "20")])
2689 ; floatsisf2 instruction pattern(s).
2692 (define_expand "floatsisf2"
2694 [(set (match_operand:SF 0 "register_operand" "")
2695 (float:SF (match_operand:SI 1 "register_operand" "")))
2696 (clobber (reg:CC 33))])]
2700 if (TARGET_IBM_FLOAT)
2702 /* Use the POP algorithm to convert to DFmode and then truncate. */
2703 rtx temp = gen_reg_rtx (DFmode);
2704 emit_insn (gen_floatsidf2 (temp, operands[1]));
2705 emit_insn (gen_truncdfsf2 (operands[0], temp));
2710 (define_insn "floatsisf2_ieee"
2711 [(set (match_operand:SF 0 "register_operand" "=f")
2712 (float:SF (match_operand:SI 1 "register_operand" "d")))
2713 (clobber (reg:CC 33))]
2714 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2716 [(set_attr "op_type" "RRE")
2717 (set_attr "type" "other" )])
2720 ; truncdfsf2 instruction pattern(s).
2723 (define_expand "truncdfsf2"
2724 [(set (match_operand:SF 0 "register_operand" "")
2725 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2729 (define_insn "truncdfsf2_ieee"
2730 [(set (match_operand:SF 0 "register_operand" "=f")
2731 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2732 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2734 [(set_attr "op_type" "RRE")])
2736 (define_insn "truncdfsf2_ibm"
2737 [(set (match_operand:SF 0 "register_operand" "=f,f")
2738 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2739 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2743 [(set_attr "op_type" "RR,RX")
2744 (set_attr "atype" "reg,mem")])
2747 ; extendsfdf2 instruction pattern(s).
2750 (define_expand "extendsfdf2"
2751 [(set (match_operand:DF 0 "register_operand" "")
2752 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2756 if (TARGET_IBM_FLOAT)
2758 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2763 (define_insn "extendsfdf2_ieee"
2764 [(set (match_operand:DF 0 "register_operand" "=f,f")
2765 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2766 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2770 [(set_attr "op_type" "RRE,RXE")])
2772 (define_insn "extendsfdf2_ibm"
2773 [(set (match_operand:DF 0 "register_operand" "=f,f")
2774 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2775 (clobber (reg:CC 33))]
2776 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2778 sdr\\t%0,%0\;ler\\t%0,%1
2779 sdr\\t%0,%0\;le\\t%0,%1"
2780 [(set_attr "op_type" "RRE,RXE")
2781 (set_attr "atype" "reg,mem")
2782 (set_attr "type" "o2,o2")])
2786 ;; ARITHMETRIC OPERATIONS
2788 ; arithmetric operations set the ConditionCode,
2789 ; because of unpredictable Bits in Register for Halfword and Byte
2790 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2793 ;;- Add instructions.
2797 ; adddi3 instruction pattern(s).
2800 (define_insn "*la_64_cc"
2801 [(set (match_operand:DI 0 "register_operand" "=d")
2802 (match_operand:QI 1 "address_operand" "p"))
2803 (clobber (reg:CC 33))]
2805 && preferred_la_operand_p (operands[1], 1)"
2807 [(set_attr "op_type" "RX")
2808 (set_attr "atype" "mem")
2809 (set_attr "type" "la")])
2812 [(set (match_operand:DI 0 "register_operand" "")
2813 (match_operand:QI 1 "address_operand" ""))
2814 (clobber (reg:CC 33))]
2815 "TARGET_64BIT && reload_completed
2816 && preferred_la_operand_p (operands[1], 0)"
2817 [(set (match_dup 0) (match_dup 1))])
2819 (define_insn "*adddi3_sign"
2820 [(set (match_operand:DI 0 "register_operand" "=d,d")
2821 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2822 (match_operand:DI 1 "register_operand" "0,0")))
2823 (clobber (reg:CC 33))]
2828 [(set_attr "op_type" "RRE,RXE")
2829 (set_attr "atype" "reg,mem")])
2831 (define_insn "*adddi3_zero_cc"
2833 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2834 (match_operand:DI 1 "register_operand" "0,0"))
2836 (set (match_operand:DI 0 "register_operand" "=d,d")
2837 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2838 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2842 [(set_attr "op_type" "RRE,RXE")
2843 (set_attr "atype" "reg,mem")])
2845 (define_insn "*adddi3_zero_cconly"
2847 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2848 (match_operand:DI 1 "register_operand" "0,0"))
2850 (clobber (match_scratch:DI 0 "=d,d"))]
2851 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2855 [(set_attr "op_type" "RRE,RXE")
2856 (set_attr "atype" "reg,mem")])
2858 (define_insn "*adddi3_zero"
2859 [(set (match_operand:DI 0 "register_operand" "=d,d")
2860 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2861 (match_operand:DI 1 "register_operand" "0,0")))
2862 (clobber (reg:CC 33))]
2867 [(set_attr "op_type" "RRE,RXE")
2868 (set_attr "atype" "reg,mem")])
2870 (define_insn "*adddi3_imm_cc"
2872 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2873 (match_operand:DI 2 "const_int_operand" "K"))
2875 (set (match_operand:DI 0 "register_operand" "=d")
2876 (plus:DI (match_dup 1) (match_dup 2)))]
2878 && s390_match_ccmode (insn, CCAmode)
2879 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2881 [(set_attr "op_type" "RI")
2882 (set_attr "atype" "reg")])
2884 (define_insn "*adddi3_cc"
2886 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2887 (match_operand:DI 2 "general_operand" "d,m"))
2889 (set (match_operand:DI 0 "register_operand" "=d,d")
2890 (plus:DI (match_dup 1) (match_dup 2)))]
2891 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2895 [(set_attr "op_type" "RRE,RXE")
2896 (set_attr "atype" "reg,mem")])
2898 (define_insn "*adddi3_cconly"
2900 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2901 (match_operand:DI 2 "general_operand" "d,m"))
2903 (clobber (match_scratch:DI 0 "=d,d"))]
2904 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2908 [(set_attr "op_type" "RRE,RXE")
2909 (set_attr "atype" "reg,mem")])
2911 (define_insn "*adddi3_cconly2"
2913 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2914 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
2915 (clobber (match_scratch:DI 0 "=d,d"))]
2916 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
2920 [(set_attr "op_type" "RRE,RXE")
2921 (set_attr "atype" "reg,mem")])
2923 (define_insn "*adddi3_64"
2924 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2925 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
2926 (match_operand:DI 2 "general_operand" "d,K,m") ) )
2927 (clobber (reg:CC 33))]
2933 [(set_attr "op_type" "RRE,RI,RXE")
2934 (set_attr "atype" "reg,reg,mem")])
2936 (define_insn_and_split "*adddi3_31"
2937 [(set (match_operand:DI 0 "register_operand" "=&d")
2938 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
2939 (match_operand:DI 2 "general_operand" "dm") ) )
2940 (clobber (reg:CC 33))]
2943 "&& reload_completed"
2945 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
2946 (clobber (reg:CC 33))])
2949 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
2951 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
2953 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
2955 (label_ref (match_dup 9))))
2957 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
2958 (clobber (reg:CC 33))])
2960 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
2961 operands[4] = operand_subword (operands[1], 0, 1, DImode);
2962 operands[5] = operand_subword (operands[2], 0, 1, DImode);
2963 operands[6] = operand_subword (operands[0], 1, 1, DImode);
2964 operands[7] = operand_subword (operands[1], 1, 1, DImode);
2965 operands[8] = operand_subword (operands[2], 1, 1, DImode);
2966 operands[9] = gen_label_rtx ();"
2967 [(set_attr "op_type" "NN")
2968 (set_attr "type" "o3")])
2970 (define_expand "adddi3"
2972 [(set (match_operand:DI 0 "register_operand" "")
2973 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
2974 (match_operand:DI 2 "general_operand" "")))
2975 (clobber (reg:CC 33))])]
2979 (define_insn "*la_64"
2980 [(set (match_operand:DI 0 "register_operand" "=d")
2981 (match_operand:QI 1 "address_operand" "p"))]
2984 [(set_attr "op_type" "RX")
2985 (set_attr "atype" "mem")
2986 (set_attr "type" "la")])
2988 (define_expand "reload_indi"
2989 [(parallel [(match_operand:DI 0 "register_operand" "=a")
2990 (match_operand:DI 1 "s390_plus_operand" "")
2991 (match_operand:DI 2 "register_operand" "=&a")])]
2995 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3001 ; addsi3 instruction pattern(s).
3004 (define_insn "*la_31_cc"
3005 [(set (match_operand:SI 0 "register_operand" "=d")
3006 (match_operand:QI 1 "address_operand" "p"))
3007 (clobber (reg:CC 33))]
3009 && preferred_la_operand_p (operands[1], 1)"
3011 [(set_attr "op_type" "RX")
3012 (set_attr "atype" "mem")
3013 (set_attr "type" "la")])
3016 [(set (match_operand:SI 0 "register_operand" "")
3017 (match_operand:QI 1 "address_operand" ""))
3018 (clobber (reg:CC 33))]
3019 "!TARGET_64BIT && reload_completed
3020 && preferred_la_operand_p (operands[1], 0)"
3021 [(set (match_dup 0) (match_dup 1))])
3023 (define_insn "*addsi3_imm_cc"
3025 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3026 (match_operand:SI 2 "const_int_operand" "K"))
3028 (set (match_operand:SI 0 "register_operand" "=d")
3029 (plus:SI (match_dup 1) (match_dup 2)))]
3030 "s390_match_ccmode (insn, CCAmode)
3031 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3033 [(set_attr "op_type" "RI")
3034 (set_attr "atype" "reg")])
3036 (define_insn "*addsi3_carry1_cc"
3038 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3039 (match_operand:SI 2 "general_operand" "d,m"))
3041 (set (match_operand:SI 0 "register_operand" "=d,d")
3042 (plus:SI (match_dup 1) (match_dup 2)))]
3043 "s390_match_ccmode (insn, CCL1mode)"
3047 [(set_attr "op_type" "RR,RX")
3048 (set_attr "atype" "reg,mem")])
3050 (define_insn "*addsi3_carry1_cconly"
3052 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3053 (match_operand:SI 2 "general_operand" "d,m"))
3055 (clobber (match_scratch:SI 0 "=d,d"))]
3056 "s390_match_ccmode (insn, CCL1mode)"
3060 [(set_attr "op_type" "RR,RX")
3061 (set_attr "atype" "reg,mem")])
3063 (define_insn "*addsi3_carry2_cc"
3065 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3066 (match_operand:SI 2 "general_operand" "d,m"))
3068 (set (match_operand:SI 0 "register_operand" "=d,d")
3069 (plus:SI (match_dup 1) (match_dup 2)))]
3070 "s390_match_ccmode (insn, CCL1mode)"
3074 [(set_attr "op_type" "RR,RX")
3075 (set_attr "atype" "reg,mem")])
3077 (define_insn "*addsi3_carry2_cconly"
3079 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3080 (match_operand:SI 2 "general_operand" "d,m"))
3082 (clobber (match_scratch:SI 0 "=d,d"))]
3083 "s390_match_ccmode (insn, CCL1mode)"
3087 [(set_attr "op_type" "RR,RX")
3088 (set_attr "atype" "reg,mem")])
3090 (define_insn "*addsi3_cc"
3092 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3093 (match_operand:SI 2 "general_operand" "d,m"))
3095 (set (match_operand:SI 0 "register_operand" "=d,d")
3096 (plus:SI (match_dup 1) (match_dup 2)))]
3097 "s390_match_ccmode (insn, CCLmode)"
3101 [(set_attr "op_type" "RR,RX")
3102 (set_attr "atype" "reg,mem")])
3104 (define_insn "*addsi3_cconly"
3106 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3107 (match_operand:SI 2 "general_operand" "d,m"))
3109 (clobber (match_scratch:SI 0 "=d,d"))]
3110 "s390_match_ccmode (insn, CCLmode)"
3114 [(set_attr "op_type" "RR,RX")
3115 (set_attr "atype" "reg,mem")])
3117 (define_insn "*addsi3_cconly2"
3119 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3120 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3121 (clobber (match_scratch:SI 0 "=d,d"))]
3122 "s390_match_ccmode(insn, CCLmode)"
3126 [(set_attr "op_type" "RR,RX")
3127 (set_attr "atype" "reg,mem")])
3129 (define_insn "*addsi3_sign"
3130 [(set (match_operand:SI 0 "register_operand" "=d")
3131 (plus:SI (match_operand:SI 1 "register_operand" "0")
3132 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3133 (clobber (reg:CC 33))]
3136 [(set_attr "op_type" "RX")
3137 (set_attr "atype" "mem")])
3139 (define_insn "*addsi3_sub"
3140 [(set (match_operand:SI 0 "register_operand" "=d")
3141 (plus:SI (match_operand:SI 1 "register_operand" "0")
3142 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3143 (clobber (reg:CC 33))]
3146 [(set_attr "op_type" "RX")
3147 (set_attr "atype" "mem")])
3149 (define_insn "addsi3"
3150 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3151 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3152 (match_operand:SI 2 "general_operand" "d,K,m")))
3153 (clobber (reg:CC 33))]
3159 [(set_attr "op_type" "RR,RI,RX")
3160 (set_attr "atype" "reg,reg,mem")])
3162 (define_insn "*la_31"
3163 [(set (match_operand:SI 0 "register_operand" "=d")
3164 (match_operand:QI 1 "address_operand" "p"))]
3165 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3167 [(set_attr "op_type" "RX")
3168 (set_attr "atype" "mem")
3169 (set_attr "type" "la")])
3171 (define_insn "*la_31_and"
3172 [(set (match_operand:SI 0 "register_operand" "=d")
3173 (and:SI (match_operand:QI 1 "address_operand" "p")
3174 (const_int 2147483647)))]
3177 [(set_attr "op_type" "RX")
3178 (set_attr "atype" "mem")
3179 (set_attr "type" "la")])
3181 (define_insn_and_split "*la_31_and_cc"
3182 [(set (match_operand:SI 0 "register_operand" "=d")
3183 (and:SI (match_operand:QI 1 "address_operand" "p")
3184 (const_int 2147483647)))
3185 (clobber (reg:CC 33))]
3188 "&& reload_completed"
3190 (and:SI (match_dup 1) (const_int 2147483647)))]
3192 [(set_attr "op_type" "RX")
3193 (set_attr "atype" "mem")
3194 (set_attr "type" "la")])
3196 (define_insn "force_la_31"
3197 [(set (match_operand:SI 0 "register_operand" "=d")
3198 (match_operand:QI 1 "address_operand" "p"))
3199 (use (const_int 0))]
3202 [(set_attr "op_type" "RX")
3203 (set_attr "atype" "mem")
3204 (set_attr "type" "la")])
3206 (define_expand "reload_insi"
3207 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3208 (match_operand:SI 1 "s390_plus_operand" "")
3209 (match_operand:SI 2 "register_operand" "=&a")])]
3213 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3219 ; adddf3 instruction pattern(s).
3222 (define_expand "adddf3"
3224 [(set (match_operand:DF 0 "register_operand" "=f,f")
3225 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3226 (match_operand:DF 2 "general_operand" "f,m")))
3227 (clobber (reg:CC 33))])]
3231 (define_insn "*adddf3"
3232 [(set (match_operand:DF 0 "register_operand" "=f,f")
3233 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3234 (match_operand:DF 2 "general_operand" "f,m")))
3235 (clobber (reg:CC 33))]
3236 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3240 [(set_attr "op_type" "RRE,RXE")
3241 (set_attr "atype" "reg,mem")])
3243 (define_insn "*adddf3_ibm"
3244 [(set (match_operand:DF 0 "register_operand" "=f,f")
3245 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3246 (match_operand:DF 2 "general_operand" "f,m")))
3247 (clobber (reg:CC 33))]
3248 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3252 [(set_attr "op_type" "RR,RX")
3253 (set_attr "atype" "reg,mem")])
3256 ; addsf3 instruction pattern(s).
3259 (define_expand "addsf3"
3261 [(set (match_operand:SF 0 "register_operand" "=f,f")
3262 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3263 (match_operand:SF 2 "general_operand" "f,m")))
3264 (clobber (reg:CC 33))])]
3268 (define_insn "*addsf3"
3269 [(set (match_operand:SF 0 "register_operand" "=f,f")
3270 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3271 (match_operand:SF 2 "general_operand" "f,m")))
3272 (clobber (reg:CC 33))]
3273 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3277 [(set_attr "op_type" "RRE,RXE")
3278 (set_attr "atype" "reg,mem")])
3280 (define_insn "*addsf3"
3281 [(set (match_operand:SF 0 "register_operand" "=f,f")
3282 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3283 (match_operand:SF 2 "general_operand" "f,m")))
3284 (clobber (reg:CC 33))]
3285 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3289 [(set_attr "op_type" "RR,RX")
3290 (set_attr "atype" "reg,mem")])
3294 ;;- Subtract instructions.
3298 ; subdi3 instruction pattern(s).
3301 (define_insn "*subdi3_sign"
3302 [(set (match_operand:DI 0 "register_operand" "=d,d")
3303 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3304 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3305 (clobber (reg:CC 33))]
3310 [(set_attr "op_type" "RRE,RXE")
3311 (set_attr "atype" "reg,mem")])
3313 (define_insn "*subdi3_zero_cc"
3315 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3316 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3318 (set (match_operand:DI 0 "register_operand" "=d,d")
3319 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3320 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3324 [(set_attr "op_type" "RRE,RXE")
3325 (set_attr "atype" "reg,mem")])
3327 (define_insn "*subdi3_zero_cconly"
3329 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3330 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3332 (clobber (match_scratch:DI 0 "=d,d"))]
3333 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3337 [(set_attr "op_type" "RRE,RXE")
3338 (set_attr "atype" "reg,mem")])
3340 (define_insn "*subdi3_zero"
3341 [(set (match_operand:DI 0 "register_operand" "=d,d")
3342 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3343 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3344 (clobber (reg:CC 33))]
3349 [(set_attr "op_type" "RRE,RXE")
3350 (set_attr "atype" "reg,mem")])
3352 (define_insn "*subdi3_cc"
3354 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3355 (match_operand:DI 2 "general_operand" "d,m"))
3357 (set (match_operand:DI 0 "register_operand" "=d,d")
3358 (minus:DI (match_dup 1) (match_dup 2)))]
3359 "s390_match_ccmode (insn, CCLmode)"
3363 [(set_attr "op_type" "RRE,RXE")
3364 (set_attr "atype" "reg,mem")])
3366 (define_insn "*subdi3_cconly"
3368 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3369 (match_operand:DI 2 "general_operand" "d,m"))
3371 (clobber (match_scratch:DI 0 "=d,d"))]
3372 "s390_match_ccmode (insn, CCLmode)"
3376 [(set_attr "op_type" "RRE,RXE")
3377 (set_attr "atype" "reg,mem")])
3379 (define_insn "*subdi3_64"
3380 [(set (match_operand:DI 0 "register_operand" "=d,d")
3381 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3382 (match_operand:DI 2 "general_operand" "d,m") ) )
3383 (clobber (reg:CC 33))]
3388 [(set_attr "op_type" "RRE,RRE")
3389 (set_attr "atype" "reg,mem")])
3391 (define_insn_and_split "*subdi3_31"
3392 [(set (match_operand:DI 0 "register_operand" "=&d")
3393 (minus:DI (match_operand:DI 1 "register_operand" "0")
3394 (match_operand:DI 2 "general_operand" "dm") ) )
3395 (clobber (reg:CC 33))]
3398 "&& reload_completed"
3400 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3401 (clobber (reg:CC 33))])
3404 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3406 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3408 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3410 (label_ref (match_dup 9))))
3412 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3413 (clobber (reg:CC 33))])
3415 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3416 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3417 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3418 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3419 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3420 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3421 operands[9] = gen_label_rtx ();"
3422 [(set_attr "op_type" "NN")
3423 (set_attr "type" "o3")])
3425 (define_expand "subdi3"
3427 [(set (match_operand:DI 0 "register_operand" "")
3428 (minus:DI (match_operand:DI 1 "register_operand" "")
3429 (match_operand:DI 2 "general_operand" "")))
3430 (clobber (reg:CC 33))])]
3435 ; subsi3 instruction pattern(s).
3438 (define_insn "*subsi3_borrow_cc"
3440 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3441 (match_operand:SI 2 "general_operand" "d,m"))
3443 (set (match_operand:SI 0 "register_operand" "=d,d")
3444 (minus:SI (match_dup 1) (match_dup 2)))]
3445 "s390_match_ccmode(insn, CCL2mode)"
3449 [(set_attr "op_type" "RR,RX")
3450 (set_attr "atype" "reg,mem")])
3452 (define_insn "*subsi3_borrow_cconly"
3454 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3455 (match_operand:SI 2 "general_operand" "d,m"))
3457 (clobber (match_scratch:SI 0 "=d,d"))]
3458 "s390_match_ccmode(insn, CCL2mode)"
3462 [(set_attr "op_type" "RR,RX")
3463 (set_attr "atype" "reg,mem")])
3465 (define_insn "*subsi3_cc"
3467 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3468 (match_operand:SI 2 "general_operand" "d,m"))
3470 (set (match_operand:SI 0 "register_operand" "=d,d")
3471 (minus:SI (match_dup 1) (match_dup 2)))]
3472 "s390_match_ccmode(insn, CCLmode)"
3476 [(set_attr "op_type" "RR,RX")
3477 (set_attr "atype" "reg,mem")])
3479 (define_insn "*subsi3_cconly"
3481 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3482 (match_operand:SI 2 "general_operand" "d,m"))
3484 (clobber (match_scratch:SI 0 "=d,d"))]
3485 "s390_match_ccmode(insn, CCLmode)"
3489 [(set_attr "op_type" "RR,RX")
3490 (set_attr "atype" "reg,mem")])
3492 (define_insn "*subsi3_sign"
3493 [(set (match_operand:SI 0 "register_operand" "=d")
3494 (minus:SI (match_operand:SI 1 "register_operand" "0")
3495 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3496 (clobber (reg:CC 33))]
3499 [(set_attr "op_type" "RX")
3500 (set_attr "atype" "mem")])
3502 (define_insn "*subsi3_sub"
3503 [(set (match_operand:SI 0 "register_operand" "=d")
3504 (minus:SI (match_operand:SI 1 "register_operand" "0")
3505 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3506 (clobber (reg:CC 33))]
3509 [(set_attr "op_type" "RX")
3510 (set_attr "atype" "mem")])
3512 (define_insn "subsi3"
3513 [(set (match_operand:SI 0 "register_operand" "=d,d")
3514 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3515 (match_operand:SI 2 "general_operand" "d,m")))
3516 (clobber (reg:CC 33))]
3521 [(set_attr "op_type" "RR,RX")
3522 (set_attr "atype" "reg,mem")])
3526 ; subdf3 instruction pattern(s).
3529 (define_expand "subdf3"
3531 [(set (match_operand:DF 0 "register_operand" "=f,f")
3532 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3533 (match_operand:DF 2 "general_operand" "f,m")))
3534 (clobber (reg:CC 33))])]
3538 (define_insn "*subdf3"
3539 [(set (match_operand:DF 0 "register_operand" "=f,f")
3540 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3541 (match_operand:DF 2 "general_operand" "f,m")))
3542 (clobber (reg:CC 33))]
3543 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3547 [(set_attr "op_type" "RRE,RXE")
3548 (set_attr "atype" "reg,mem")])
3550 (define_insn "*subdf3_ibm"
3551 [(set (match_operand:DF 0 "register_operand" "=f,f")
3552 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3553 (match_operand:DF 2 "general_operand" "f,m")))
3554 (clobber (reg:CC 33))]
3555 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3559 [(set_attr "op_type" "RR,RX")
3560 (set_attr "atype" "reg,mem")])
3563 ; subsf3 instruction pattern(s).
3566 (define_expand "subsf3"
3568 [(set (match_operand:SF 0 "register_operand" "=f,f")
3569 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3570 (match_operand:SF 2 "general_operand" "f,m")))
3571 (clobber (reg:CC 33))])]
3575 (define_insn "*subsf3"
3576 [(set (match_operand:SF 0 "register_operand" "=f,f")
3577 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3578 (match_operand:SF 2 "general_operand" "f,m")))
3579 (clobber (reg:CC 33))]
3580 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3584 [(set_attr "op_type" "RRE,RXE")
3585 (set_attr "atype" "reg,mem")])
3587 (define_insn "*subsf3_ibm"
3588 [(set (match_operand:SF 0 "register_operand" "=f,f")
3589 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3590 (match_operand:SF 2 "general_operand" "f,m")))
3591 (clobber (reg:CC 33))]
3592 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3596 [(set_attr "op_type" "RR,RX")
3597 (set_attr "atype" "reg,mem")])
3601 ;;- Multiply instructions.
3605 ; muldi3 instruction pattern(s).
3608 (define_insn "*muldi3_sign"
3609 [(set (match_operand:DI 0 "register_operand" "=d,d")
3610 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3611 (match_operand:DI 1 "register_operand" "0,0")))]
3616 [(set_attr "op_type" "RRE,RXE")
3617 (set_attr "atype" "reg,mem")
3618 (set_attr "type" "imul")])
3621 (define_insn "muldi3"
3622 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3623 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3624 (match_operand:DI 2 "general_operand" "d,K,m")))]
3630 [(set_attr "op_type" "RRE,RI,RXE")
3631 (set_attr "atype" "reg,reg,mem")
3632 (set_attr "type" "imul")])
3635 ; mulsi3 instruction pattern(s).
3638 (define_insn "mulsi3"
3639 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3640 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3641 (match_operand:SI 2 "general_operand" "d,K,m")))]
3647 [(set_attr "op_type" "RRE,RI,RX")
3648 (set_attr "atype" "reg,reg,mem")
3649 (set_attr "type" "imul")])
3652 ; mulsidi3 instruction pattern(s).
3655 (define_expand "mulsidi3"
3656 [(set (match_operand:DI 0 "register_operand" "")
3657 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3658 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3664 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3665 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3668 gen_rtx_EXPR_LIST (REG_EQUAL,
3669 gen_rtx_MULT (DImode,
3670 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3671 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3676 (define_insn "mulsi_6432"
3677 [(set (match_operand:DI 0 "register_operand" "=d,d")
3678 (mult:DI (sign_extend:DI
3679 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3681 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3686 [(set_attr "op_type" "RR,RX")
3687 (set_attr "atype" "reg,mem")
3688 (set_attr "type" "imul")])
3691 ; muldf3 instruction pattern(s).
3694 (define_expand "muldf3"
3696 [(set (match_operand:DF 0 "register_operand" "=f,f")
3697 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3698 (match_operand:DF 2 "general_operand" "f,m")))
3699 (clobber (reg:CC 33))])]
3703 (define_insn "*muldf3"
3704 [(set (match_operand:DF 0 "register_operand" "=f,f")
3705 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3706 (match_operand:DF 2 "general_operand" "f,m")))
3707 (clobber (reg:CC 33))]
3708 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3712 [(set_attr "op_type" "RRE,RXE")
3713 (set_attr "type" "fmul")
3714 (set_attr "atype" "reg,mem")])
3716 (define_insn "*muldf3_ibm"
3717 [(set (match_operand:DF 0 "register_operand" "=f,f")
3718 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3719 (match_operand:DF 2 "general_operand" "f,m")))
3720 (clobber (reg:CC 33))]
3721 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3725 [(set_attr "op_type" "RR,RX")
3726 (set_attr "type" "fmul")
3727 (set_attr "atype" "reg,mem")])
3730 ; mulsf3 instruction pattern(s).
3733 (define_expand "mulsf3"
3735 [(set (match_operand:SF 0 "register_operand" "=f,f")
3736 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3737 (match_operand:SF 2 "general_operand" "f,m")))
3738 (clobber (reg:CC 33))])]
3742 (define_insn "*mulsf3"
3743 [(set (match_operand:SF 0 "register_operand" "=f,f")
3744 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3745 (match_operand:SF 2 "general_operand" "f,m")))
3746 (clobber (reg:CC 33))]
3747 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3751 [(set_attr "op_type" "RRE,RXE")
3752 (set_attr "type" "fmul")
3753 (set_attr "atype" "reg,mem")])
3755 (define_insn "*mulsf3_ibm"
3756 [(set (match_operand:SF 0 "register_operand" "=f,f")
3757 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3758 (match_operand:SF 2 "general_operand" "f,m")))
3759 (clobber (reg:CC 33))]
3760 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3764 [(set_attr "op_type" "RR,RX")
3765 (set_attr "type" "fmul")
3766 (set_attr "atype" "reg,mem")])
3770 ;;- Divide and modulo instructions.
3774 ; divmoddi4 instruction pattern(s).
3777 (define_expand "divmoddi4"
3778 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3779 (div:DI (match_operand:DI 1 "general_operand" "")
3780 (match_operand:DI 2 "general_operand" "")))
3781 (set (match_operand:DI 3 "general_operand" "")
3782 (mod:DI (match_dup 1) (match_dup 2)))])
3783 (clobber (match_dup 4))]
3787 rtx insn, div_equal, mod_equal, equal;
3789 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3790 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3791 equal = gen_rtx_IOR (TImode,
3792 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3793 gen_rtx_ASHIFT (TImode,
3794 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3797 operands[4] = gen_reg_rtx(TImode);
3798 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3799 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3800 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3801 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3803 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3805 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3807 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3809 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3811 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3816 (define_insn "divmodtidi3"
3817 [(set (match_operand:TI 0 "register_operand" "=d,d")
3820 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3821 (match_operand:DI 2 "general_operand" "d,m")))
3824 (mod:DI (truncate:DI (match_dup 1))
3831 [(set_attr "op_type" "RRE,RXE")
3832 (set_attr "type" "idiv")
3833 (set_attr "atype" "reg,mem")])
3835 (define_insn "divmodtisi3"
3836 [(set (match_operand:TI 0 "register_operand" "=d,d")
3839 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3840 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3843 (mod:DI (truncate:DI (match_dup 1))
3844 (sign_extend:DI (match_dup 2))))
3850 [(set_attr "op_type" "RRE,RXE")
3851 (set_attr "type" "idiv")
3852 (set_attr "atype" "reg,mem")])
3855 ; udivmoddi4 instruction pattern(s).
3858 (define_expand "udivmoddi4"
3859 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3860 (udiv:DI (match_operand:DI 1 "general_operand" "")
3861 (match_operand:DI 2 "nonimmediate_operand" "")))
3862 (set (match_operand:DI 3 "general_operand" "")
3863 (umod:DI (match_dup 1) (match_dup 2)))])
3864 (clobber (match_dup 4))]
3868 rtx insn, div_equal, mod_equal, equal;
3870 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3871 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3872 equal = gen_rtx_IOR (TImode,
3873 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3874 gen_rtx_ASHIFT (TImode,
3875 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3878 operands[4] = gen_reg_rtx(TImode);
3879 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3880 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3881 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3882 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3884 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3886 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3888 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3890 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3892 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3897 (define_insn "udivmodtidi3"
3898 [(set (match_operand:TI 0 "register_operand" "=d,d")
3899 (ior:TI (zero_extend:TI
3901 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3903 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3907 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3913 [(set_attr "op_type" "RRE,RXE")
3914 (set_attr "type" "idiv")
3915 (set_attr "atype" "reg,mem")])
3918 ; divmodsi4 instruction pattern(s).
3921 (define_expand "divmodsi4"
3922 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3923 (div:SI (match_operand:SI 1 "general_operand" "")
3924 (match_operand:SI 2 "nonimmediate_operand" "")))
3925 (set (match_operand:SI 3 "general_operand" "")
3926 (mod:SI (match_dup 1) (match_dup 2)))])
3927 (clobber (match_dup 4))]
3931 rtx insn, div_equal, mod_equal, equal;
3933 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3934 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3935 equal = gen_rtx_IOR (DImode,
3936 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3937 gen_rtx_ASHIFT (DImode,
3938 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3941 operands[4] = gen_reg_rtx(DImode);
3942 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3943 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3945 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3947 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3949 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3951 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3953 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3958 (define_insn "divmoddisi3"
3959 [(set (match_operand:DI 0 "register_operand" "=d,d")
3960 (ior:DI (zero_extend:DI
3962 (div:DI (match_operand:DI 1 "register_operand" "0,0")
3964 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3968 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
3974 [(set_attr "op_type" "RR,RX")
3975 (set_attr "type" "idiv")
3976 (set_attr "atype" "reg,mem")])
3979 ; udivsi3 and umodsi3 instruction pattern(s).
3983 (define_expand "udivsi3"
3984 [(set (match_operand:SI 0 "register_operand" "=d")
3985 (udiv:SI (match_operand:SI 1 "general_operand" "")
3986 (match_operand:SI 2 "general_operand" "")))
3987 (clobber (match_dup 3))]
3991 rtx insn, udiv_equal, umod_equal, equal;
3993 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3994 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
3995 equal = gen_rtx_IOR (DImode,
3996 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
3997 gen_rtx_ASHIFT (DImode,
3998 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4001 operands[3] = gen_reg_rtx (DImode);
4003 if (CONSTANT_P (operands[2]))
4005 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4007 rtx label1 = gen_label_rtx ();
4009 operands[1] = make_safe_from (operands[1], operands[0]);
4010 emit_move_insn (operands[0], const0_rtx);
4011 emit_insn (gen_cmpsi (operands[1], operands[2]));
4012 emit_jump_insn (gen_bltu (label1));
4013 emit_move_insn (operands[0], const1_rtx);
4014 emit_label (label1);
4018 operands[2] = force_reg (SImode, operands[2]);
4019 operands[2] = make_safe_from (operands[2], operands[0]);
4021 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4022 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4025 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4027 insn = emit_move_insn (operands[0],
4028 gen_lowpart (SImode, operands[3]));
4030 gen_rtx_EXPR_LIST (REG_EQUAL,
4031 udiv_equal, REG_NOTES (insn));
4036 rtx label1 = gen_label_rtx ();
4037 rtx label2 = gen_label_rtx ();
4038 rtx label3 = gen_label_rtx ();
4040 operands[1] = force_reg (SImode, operands[1]);
4041 operands[1] = make_safe_from (operands[1], operands[0]);
4042 operands[2] = force_reg (SImode, operands[2]);
4043 operands[2] = make_safe_from (operands[2], operands[0]);
4045 emit_move_insn (operands[0], const0_rtx);
4046 emit_insn (gen_cmpsi (operands[2], operands[1]));
4047 emit_jump_insn (gen_bgtu (label3));
4048 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4049 emit_jump_insn (gen_blt (label2));
4050 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4051 emit_jump_insn (gen_beq (label1));
4052 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4053 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4056 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4058 insn = emit_move_insn (operands[0],
4059 gen_lowpart (SImode, operands[3]));
4061 gen_rtx_EXPR_LIST (REG_EQUAL,
4062 udiv_equal, REG_NOTES (insn));
4064 emit_label (label1);
4065 emit_move_insn (operands[0], operands[1]);
4067 emit_label (label2);
4068 emit_move_insn (operands[0], const1_rtx);
4069 emit_label (label3);
4071 emit_move_insn (operands[0], operands[0]);
4075 (define_expand "umodsi3"
4076 [(set (match_operand:SI 0 "register_operand" "=d")
4077 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4078 (match_operand:SI 2 "nonimmediate_operand" "")))
4079 (clobber (match_dup 3))]
4083 rtx insn, udiv_equal, umod_equal, equal;
4085 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4086 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4087 equal = gen_rtx_IOR (DImode,
4088 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4089 gen_rtx_ASHIFT (DImode,
4090 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4093 operands[3] = gen_reg_rtx (DImode);
4095 if (CONSTANT_P (operands[2]))
4097 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4099 rtx label1 = gen_label_rtx ();
4101 operands[1] = make_safe_from (operands[1], operands[0]);
4102 emit_move_insn (operands[0], operands[1]);
4103 emit_insn (gen_cmpsi (operands[0], operands[2]));
4104 emit_jump_insn (gen_bltu (label1));
4105 emit_insn (gen_abssi2 (operands[0], operands[2]));
4106 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4107 emit_label (label1);
4111 operands[2] = force_reg (SImode, operands[2]);
4112 operands[2] = make_safe_from (operands[2], operands[0]);
4114 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4115 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4118 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4120 insn = emit_move_insn (operands[0],
4121 gen_highpart (SImode, operands[3]));
4123 gen_rtx_EXPR_LIST (REG_EQUAL,
4124 umod_equal, REG_NOTES (insn));
4129 rtx label1 = gen_label_rtx ();
4130 rtx label2 = gen_label_rtx ();
4131 rtx label3 = gen_label_rtx ();
4133 operands[1] = force_reg (SImode, operands[1]);
4134 operands[1] = make_safe_from (operands[1], operands[0]);
4135 operands[2] = force_reg (SImode, operands[2]);
4136 operands[2] = make_safe_from (operands[2], operands[0]);
4138 emit_move_insn(operands[0], operands[1]);
4139 emit_insn (gen_cmpsi (operands[2], operands[1]));
4140 emit_jump_insn (gen_bgtu (label3));
4141 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4142 emit_jump_insn (gen_blt (label2));
4143 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4144 emit_jump_insn (gen_beq (label1));
4145 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4146 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4149 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4151 insn = emit_move_insn (operands[0],
4152 gen_highpart (SImode, operands[3]));
4154 gen_rtx_EXPR_LIST (REG_EQUAL,
4155 umod_equal, REG_NOTES (insn));
4157 emit_label (label1);
4158 emit_move_insn (operands[0], const0_rtx);
4160 emit_label (label2);
4161 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4162 emit_label (label3);
4168 ; divdf3 instruction pattern(s).
4171 (define_expand "divdf3"
4173 [(set (match_operand:DF 0 "register_operand" "=f,f")
4174 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4175 (match_operand:DF 2 "general_operand" "f,m")))
4176 (clobber (reg:CC 33))])]
4180 (define_insn "*divdf3"
4181 [(set (match_operand:DF 0 "register_operand" "=f,f")
4182 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4183 (match_operand:DF 2 "general_operand" "f,m")))
4184 (clobber (reg:CC 33))]
4185 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4189 [(set_attr "op_type" "RRE,RXE")
4190 (set_attr "type" "fdiv")
4191 (set_attr "atype" "reg,mem")])
4193 (define_insn "*divdf3_ibm"
4194 [(set (match_operand:DF 0 "register_operand" "=f,f")
4195 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4196 (match_operand:DF 2 "general_operand" "f,m")))
4197 (clobber (reg:CC 33))]
4198 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4202 [(set_attr "op_type" "RR,RX")
4203 (set_attr "type" "fdiv")
4204 (set_attr "atype" "reg,mem")])
4207 ; divsf3 instruction pattern(s).
4210 (define_expand "divsf3"
4212 [(set (match_operand:SF 0 "register_operand" "=f,f")
4213 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4214 (match_operand:SF 2 "general_operand" "f,m")))
4215 (clobber (reg:CC 33))])]
4219 (define_insn "*divsf3"
4220 [(set (match_operand:SF 0 "register_operand" "=f,f")
4221 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4222 (match_operand:SF 2 "general_operand" "f,m")))
4223 (clobber (reg:CC 33))]
4224 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4228 [(set_attr "op_type" "RRE,RXE")
4229 (set_attr "type" "fdiv")
4230 (set_attr "atype" "reg,mem")])
4232 (define_insn "*divsf3"
4233 [(set (match_operand:SF 0 "register_operand" "=f,f")
4234 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4235 (match_operand:SF 2 "general_operand" "f,m")))
4236 (clobber (reg:CC 33))]
4237 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4241 [(set_attr "op_type" "RR,RX")
4242 (set_attr "type" "fdiv")
4243 (set_attr "atype" "reg,mem")])
4247 ;;- And instructions.
4251 ; anddi3 instruction pattern(s).
4254 (define_insn "*anddi3_cc"
4256 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4257 (match_operand:DI 2 "general_operand" "d,m"))
4259 (set (match_operand:DI 0 "register_operand" "=d,d")
4260 (and:DI (match_dup 1) (match_dup 2)))]
4261 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4265 [(set_attr "op_type" "RRE,RXE")
4266 (set_attr "atype" "reg,mem")])
4268 (define_insn "*anddi3_cconly"
4270 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4271 (match_operand:DI 2 "general_operand" "d,m"))
4273 (clobber (match_scratch:DI 0 "=d,d"))]
4274 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4278 [(set_attr "op_type" "RRE,RXE")
4279 (set_attr "atype" "reg,mem")])
4281 (define_insn "*anddi3_ni"
4282 [(set (match_operand:DI 0 "register_operand" "=d")
4283 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4284 (match_operand:DI 2 "immediate_operand" "n")))
4285 (clobber (reg:CC 33))]
4286 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4289 int part = s390_single_hi (operands[2], DImode, -1);
4290 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4294 case 0: return \"nihh\\t%0,%x2\";
4295 case 1: return \"nihl\\t%0,%x2\";
4296 case 2: return \"nilh\\t%0,%x2\";
4297 case 3: return \"nill\\t%0,%x2\";
4301 [(set_attr "op_type" "RI")
4302 (set_attr "atype" "reg")])
4304 (define_insn "anddi3"
4305 [(set (match_operand:DI 0 "register_operand" "=d,d")
4306 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4307 (match_operand:DI 2 "general_operand" "d,m")))
4308 (clobber (reg:CC 33))]
4313 [(set_attr "op_type" "RRE,RXE")
4314 (set_attr "atype" "reg,mem")])
4316 (define_insn "*anddi3_ss"
4317 [(set (match_operand:DI 0 "s_operand" "=Q")
4318 (and:DI (match_dup 0)
4319 (match_operand:DI 1 "s_imm_operand" "Q")))
4320 (clobber (reg:CC 33))]
4322 "nc\\t%O0(8,%R0),%1"
4323 [(set_attr "op_type" "SS")
4324 (set_attr "atype" "mem")])
4326 (define_insn "*anddi3_ss_inv"
4327 [(set (match_operand:DI 0 "s_operand" "=Q")
4328 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4330 (clobber (reg:CC 33))]
4332 "nc\\t%O0(8,%R0),%1"
4333 [(set_attr "op_type" "SS")
4334 (set_attr "atype" "mem")])
4337 ; andsi3 instruction pattern(s).
4340 (define_insn "*andsi3_cc"
4342 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4343 (match_operand:SI 2 "general_operand" "d,m"))
4345 (set (match_operand:SI 0 "register_operand" "=d,d")
4346 (and:SI (match_dup 1) (match_dup 2)))]
4347 "s390_match_ccmode(insn, CCTmode)"
4351 [(set_attr "op_type" "RR,RX")
4352 (set_attr "atype" "reg,mem")])
4354 (define_insn "*andsi3_cconly"
4356 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4357 (match_operand:SI 2 "general_operand" "d,m"))
4359 (clobber (match_scratch:SI 0 "=d,d"))]
4360 "s390_match_ccmode(insn, CCTmode)"
4364 [(set_attr "op_type" "RR,RX")
4365 (set_attr "atype" "reg,mem")])
4367 (define_insn "*andsi3_ni"
4368 [(set (match_operand:SI 0 "register_operand" "=d")
4369 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4370 (match_operand:SI 2 "immediate_operand" "n")))
4371 (clobber (reg:CC 33))]
4372 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4375 int part = s390_single_hi (operands[2], SImode, -1);
4376 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4380 case 0: return \"nilh\\t%0,%x2\";
4381 case 1: return \"nill\\t%0,%x2\";
4385 [(set_attr "op_type" "RI")
4386 (set_attr "atype" "reg")])
4388 (define_insn "andsi3"
4389 [(set (match_operand:SI 0 "register_operand" "=d,d")
4390 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4391 (match_operand:SI 2 "general_operand" "d,m")))
4392 (clobber (reg:CC 33))]
4397 [(set_attr "op_type" "RR,RX")
4398 (set_attr "atype" "reg,mem")])
4400 (define_insn "*andsi3_ss"
4401 [(set (match_operand:SI 0 "s_operand" "=Q")
4402 (and:SI (match_dup 0)
4403 (match_operand:SI 1 "s_imm_operand" "Q")))
4404 (clobber (reg:CC 33))]
4406 "nc\\t%O0(4,%R0),%1"
4407 [(set_attr "op_type" "SS")
4408 (set_attr "atype" "mem")])
4410 (define_insn "*andsi3_ss_inv"
4411 [(set (match_operand:SI 0 "s_operand" "=Q")
4412 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4414 (clobber (reg:CC 33))]
4416 "nc\\t%O0(4,%R0),%1"
4417 [(set_attr "op_type" "SS")
4418 (set_attr "atype" "mem")])
4421 ; andhi3 instruction pattern(s).
4424 (define_insn "*andhi3_ni"
4425 [(set (match_operand:HI 0 "register_operand" "=d,d")
4426 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4427 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4428 (clobber (reg:CC 33))]
4433 [(set_attr "op_type" "RR,RI")
4434 (set_attr "atype" "reg")])
4436 (define_insn "andhi3"
4437 [(set (match_operand:HI 0 "register_operand" "=d")
4438 (and:HI (match_operand:HI 1 "register_operand" "%0")
4439 (match_operand:HI 2 "nonmemory_operand" "d")))
4440 (clobber (reg:CC 33))]
4443 [(set_attr "op_type" "RR")
4444 (set_attr "atype" "reg")])
4446 (define_insn "*andhi3_ss"
4447 [(set (match_operand:HI 0 "s_operand" "=Q")
4448 (and:HI (match_dup 0)
4449 (match_operand:HI 1 "s_imm_operand" "Q")))
4450 (clobber (reg:CC 33))]
4452 "nc\\t%O0(2,%R0),%1"
4453 [(set_attr "op_type" "SS")
4454 (set_attr "atype" "mem")])
4456 (define_insn "*andhi3_ss_inv"
4457 [(set (match_operand:HI 0 "s_operand" "=Q")
4458 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4460 (clobber (reg:CC 33))]
4462 "nc\\t%O0(2,%R0),%1"
4463 [(set_attr "op_type" "SS")
4464 (set_attr "atype" "mem")])
4467 ; andqi3 instruction pattern(s).
4470 (define_insn "*andqi3_ni"
4471 [(set (match_operand:QI 0 "register_operand" "=d,d")
4472 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4473 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4474 (clobber (reg:CC 33))]
4479 [(set_attr "op_type" "RR,RI")
4480 (set_attr "atype" "reg")])
4482 (define_insn "andqi3"
4483 [(set (match_operand:QI 0 "register_operand" "=d")
4484 (and:QI (match_operand:QI 1 "register_operand" "%0")
4485 (match_operand:QI 2 "nonmemory_operand" "d")))
4486 (clobber (reg:CC 33))]
4489 [(set_attr "op_type" "RR")
4490 (set_attr "atype" "reg")])
4492 (define_insn "*andqi3_ss"
4493 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4494 (and:QI (match_dup 0)
4495 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4496 (clobber (reg:CC 33))]
4501 [(set_attr "op_type" "SI,SS")
4502 (set_attr "atype" "mem")])
4504 (define_insn "*andqi3_ss_inv"
4505 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4506 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4508 (clobber (reg:CC 33))]
4513 [(set_attr "op_type" "SI,SS")
4514 (set_attr "atype" "mem")])
4518 ;;- Bit set (inclusive or) instructions.
4522 ; iordi3 instruction pattern(s).
4525 (define_insn "*iordi3_cc"
4527 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4528 (match_operand:DI 2 "general_operand" "d,m"))
4530 (set (match_operand:DI 0 "register_operand" "=d,d")
4531 (ior:DI (match_dup 1) (match_dup 2)))]
4532 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4536 [(set_attr "op_type" "RRE,RXE")
4537 (set_attr "atype" "reg,mem")])
4539 (define_insn "*iordi3_cconly"
4541 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4542 (match_operand:DI 2 "general_operand" "d,m"))
4544 (clobber (match_scratch:DI 0 "=d,d"))]
4545 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4549 [(set_attr "op_type" "RRE,RXE")
4550 (set_attr "atype" "reg,mem")])
4552 (define_insn "*iordi3_oi"
4553 [(set (match_operand:DI 0 "register_operand" "=d")
4554 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4555 (match_operand:DI 2 "immediate_operand" "n")))
4556 (clobber (reg:CC 33))]
4557 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4560 int part = s390_single_hi (operands[2], DImode, 0);
4561 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4565 case 0: return \"oihh\\t%0,%x2\";
4566 case 1: return \"oihl\\t%0,%x2\";
4567 case 2: return \"oilh\\t%0,%x2\";
4568 case 3: return \"oill\\t%0,%x2\";
4572 [(set_attr "op_type" "RI")
4573 (set_attr "atype" "reg")])
4575 (define_insn "iordi3"
4576 [(set (match_operand:DI 0 "register_operand" "=d,d")
4577 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4578 (match_operand:DI 2 "general_operand" "d,m")))
4579 (clobber (reg:CC 33))]
4584 [(set_attr "op_type" "RRE,RXE")
4585 (set_attr "atype" "reg,mem")])
4587 (define_insn "*iordi3_ss"
4588 [(set (match_operand:DI 0 "s_operand" "=Q")
4589 (ior:DI (match_dup 0)
4590 (match_operand:DI 1 "s_imm_operand" "Q")))
4591 (clobber (reg:CC 33))]
4593 "oc\\t%O0(8,%R0),%1"
4594 [(set_attr "op_type" "SS")
4595 (set_attr "atype" "mem")])
4597 (define_insn "*iordi3_ss_inv"
4598 [(set (match_operand:DI 0 "s_operand" "=Q")
4599 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4601 (clobber (reg:CC 33))]
4603 "oc\\t%O0(8,%R0),%1"
4604 [(set_attr "op_type" "SS")
4605 (set_attr "atype" "mem")])
4608 ; iorsi3 instruction pattern(s).
4611 (define_insn "*iorsi3_cc"
4613 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4614 (match_operand:SI 2 "general_operand" "d,m"))
4616 (set (match_operand:SI 0 "register_operand" "=d,d")
4617 (ior:SI (match_dup 1) (match_dup 2)))]
4618 "s390_match_ccmode(insn, CCTmode)"
4622 [(set_attr "op_type" "RR,RX")
4623 (set_attr "atype" "reg,mem")])
4625 (define_insn "*iorsi3_cconly"
4627 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4628 (match_operand:SI 2 "general_operand" "d,m"))
4630 (clobber (match_scratch:SI 0 "=d,d"))]
4631 "s390_match_ccmode(insn, CCTmode)"
4635 [(set_attr "op_type" "RR,RX")
4636 (set_attr "atype" "reg,mem")])
4638 (define_insn "*iorsi3_oi"
4639 [(set (match_operand:SI 0 "register_operand" "=d")
4640 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4641 (match_operand:SI 2 "immediate_operand" "n")))
4642 (clobber (reg:CC 33))]
4643 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4646 int part = s390_single_hi (operands[2], SImode, 0);
4647 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4651 case 0: return \"oilh\\t%0,%x2\";
4652 case 1: return \"oill\\t%0,%x2\";
4656 [(set_attr "op_type" "RI")
4657 (set_attr "atype" "reg")])
4659 (define_insn "iorsi3"
4660 [(set (match_operand:SI 0 "register_operand" "=d,d")
4661 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4662 (match_operand:SI 2 "general_operand" "d,m")))
4663 (clobber (reg:CC 33))]
4668 [(set_attr "op_type" "RR,RX")
4669 (set_attr "atype" "reg,mem")])
4671 (define_insn "*iorsi3_ss"
4672 [(set (match_operand:SI 0 "s_operand" "=Q")
4673 (ior:SI (match_dup 0)
4674 (match_operand:SI 1 "s_imm_operand" "Q")))
4675 (clobber (reg:CC 33))]
4677 "oc\\t%O0(4,%R0),%1"
4678 [(set_attr "op_type" "SS")
4679 (set_attr "atype" "mem")])
4681 (define_insn "*iorsi3_ss_inv"
4682 [(set (match_operand:SI 0 "s_operand" "=Q")
4683 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4685 (clobber (reg:CC 33))]
4687 "oc\\t%O0(4,%R0),%1"
4688 [(set_attr "op_type" "SS")
4689 (set_attr "atype" "mem")])
4692 ; iorhi3 instruction pattern(s).
4695 (define_insn "*iorhi3_oi"
4696 [(set (match_operand:HI 0 "register_operand" "=d,d")
4697 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4698 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4699 (clobber (reg:CC 33))]
4704 [(set_attr "op_type" "RR,RI")
4705 (set_attr "atype" "reg")])
4707 (define_insn "iorhi3"
4708 [(set (match_operand:HI 0 "register_operand" "=d")
4709 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4710 (match_operand:HI 2 "nonmemory_operand" "d")))
4711 (clobber (reg:CC 33))]
4714 [(set_attr "op_type" "RR")
4715 (set_attr "atype" "reg")])
4717 (define_insn "*iorhi3_ss"
4718 [(set (match_operand:HI 0 "s_operand" "=Q")
4719 (ior:HI (match_dup 0)
4720 (match_operand:HI 1 "s_imm_operand" "Q")))
4721 (clobber (reg:CC 33))]
4723 "oc\\t%O0(2,%R0),%1"
4724 [(set_attr "op_type" "SS")
4725 (set_attr "atype" "mem")])
4727 (define_insn "*iorhi3_ss_inv"
4728 [(set (match_operand:HI 0 "s_operand" "=Q")
4729 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4731 (clobber (reg:CC 33))]
4733 "oc\\t%O0(2,%R0),%1"
4734 [(set_attr "op_type" "SS")
4735 (set_attr "atype" "mem")])
4738 ; iorqi3 instruction pattern(s).
4741 (define_insn "*iorqi3_oi"
4742 [(set (match_operand:QI 0 "register_operand" "=d,d")
4743 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4744 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4745 (clobber (reg:CC 33))]
4750 [(set_attr "op_type" "RR,RI")
4751 (set_attr "atype" "reg")])
4753 (define_insn "iorqi3"
4754 [(set (match_operand:QI 0 "register_operand" "=d")
4755 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4756 (match_operand:QI 2 "nonmemory_operand" "d")))
4757 (clobber (reg:CC 33))]
4760 [(set_attr "op_type" "RR")
4761 (set_attr "atype" "reg")])
4763 (define_insn "*iorqi3_ss"
4764 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4765 (ior:QI (match_dup 0)
4766 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4767 (clobber (reg:CC 33))]
4772 [(set_attr "op_type" "SI,SS")
4773 (set_attr "atype" "reg,mem")])
4775 (define_insn "*iorqi3_ss_inv"
4776 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4777 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4779 (clobber (reg:CC 33))]
4784 [(set_attr "op_type" "SI,SS")
4785 (set_attr "atype" "reg,mem")])
4789 ;;- Xor instructions.
4793 ; xordi3 instruction pattern(s).
4796 (define_insn "*xordi3_cc"
4798 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4799 (match_operand:DI 2 "general_operand" "d,m"))
4801 (set (match_operand:DI 0 "register_operand" "=d,d")
4802 (xor:DI (match_dup 1) (match_dup 2)))]
4803 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4807 [(set_attr "op_type" "RRE,RXE")
4808 (set_attr "atype" "reg,mem")])
4810 (define_insn "*xordi3_cconly"
4812 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4813 (match_operand:DI 2 "general_operand" "d,m"))
4815 (clobber (match_scratch:DI 0 "=d,d"))]
4816 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4820 [(set_attr "op_type" "RRE,RXE")
4821 (set_attr "atype" "reg,mem")])
4823 (define_insn "xordi3"
4824 [(set (match_operand:DI 0 "register_operand" "=d,d")
4825 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4826 (match_operand:DI 2 "general_operand" "d,m")))
4827 (clobber (reg:CC 33))]
4832 [(set_attr "op_type" "RRE,RXE")
4833 (set_attr "atype" "reg,mem")])
4835 (define_insn "*xordi3_ss"
4836 [(set (match_operand:DI 0 "s_operand" "=Q")
4837 (xor:DI (match_dup 0)
4838 (match_operand:DI 1 "s_imm_operand" "Q")))
4839 (clobber (reg:CC 33))]
4841 "xc\\t%O0(8,%R0),%1"
4842 [(set_attr "op_type" "SS")
4843 (set_attr "atype" "mem")])
4845 (define_insn "*xordi3_ss_inv"
4846 [(set (match_operand:DI 0 "s_operand" "=Q")
4847 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4849 (clobber (reg:CC 33))]
4851 "xc\\t%O0(8,%R0),%1"
4852 [(set_attr "op_type" "SS")
4853 (set_attr "atype" "mem")])
4856 ; xorsi3 instruction pattern(s).
4859 (define_insn "*xorsi3_cc"
4861 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4862 (match_operand:SI 2 "general_operand" "d,m"))
4864 (set (match_operand:SI 0 "register_operand" "=d,d")
4865 (xor:SI (match_dup 1) (match_dup 2)))]
4866 "s390_match_ccmode(insn, CCTmode)"
4870 [(set_attr "op_type" "RR,RX")
4871 (set_attr "atype" "reg,mem")])
4873 (define_insn "*xorsi3_cconly"
4875 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4876 (match_operand:SI 2 "general_operand" "d,m"))
4878 (clobber (match_scratch:SI 0 "=d,d"))]
4879 "s390_match_ccmode(insn, CCTmode)"
4883 [(set_attr "op_type" "RR,RX")
4884 (set_attr "atype" "reg,mem")])
4886 (define_insn "xorsi3"
4887 [(set (match_operand:SI 0 "register_operand" "=d,d")
4888 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4889 (match_operand:SI 2 "general_operand" "d,m")))
4890 (clobber (reg:CC 33))]
4895 [(set_attr "op_type" "RR,RX")
4896 (set_attr "atype" "reg,mem")])
4898 (define_insn "*xorsi3_ss"
4899 [(set (match_operand:SI 0 "s_operand" "=Q")
4900 (xor:SI (match_dup 0)
4901 (match_operand:SI 1 "s_imm_operand" "Q")))
4902 (clobber (reg:CC 33))]
4904 "xc\\t%O0(4,%R0),%1"
4905 [(set_attr "op_type" "SS")
4906 (set_attr "atype" "mem")])
4908 (define_insn "*xorsi3_ss_inv"
4909 [(set (match_operand:SI 0 "s_operand" "=Q")
4910 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4912 (clobber (reg:CC 33))]
4914 "xc\\t%O0(4,%R0),%1"
4915 [(set_attr "op_type" "SS")
4916 (set_attr "atype" "mem")])
4919 ; xorhi3 instruction pattern(s).
4922 (define_insn "xorhi3"
4923 [(set (match_operand:HI 0 "register_operand" "=d")
4924 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4925 (match_operand:HI 2 "nonmemory_operand" "d")))
4926 (clobber (reg:CC 33))]
4929 [(set_attr "op_type" "RR")
4930 (set_attr "atype" "reg")])
4932 (define_insn "*xorhi3_ss"
4933 [(set (match_operand:HI 0 "s_operand" "=Q")
4934 (xor:HI (match_dup 0)
4935 (match_operand:HI 1 "s_imm_operand" "Q")))
4936 (clobber (reg:CC 33))]
4938 "xc\\t%O0(2,%R0),%1"
4939 [(set_attr "op_type" "SS")
4940 (set_attr "atype" "mem")])
4942 (define_insn "*xorhi3_ss_inv"
4943 [(set (match_operand:HI 0 "s_operand" "=Q")
4944 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4946 (clobber (reg:CC 33))]
4948 "xc\\t%O0(2,%R0),%1"
4949 [(set_attr "op_type" "SS")
4950 (set_attr "atype" "mem")])
4953 ; xorqi3 instruction pattern(s).
4956 (define_insn "xorqi3"
4957 [(set (match_operand:QI 0 "register_operand" "=d")
4958 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4959 (match_operand:QI 2 "nonmemory_operand" "d")))
4960 (clobber (reg:CC 33))]
4963 [(set_attr "op_type" "RR")
4964 (set_attr "atype" "reg")])
4966 (define_insn "*xorqi3_ss"
4967 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4968 (xor:QI (match_dup 0)
4969 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4970 (clobber (reg:CC 33))]
4975 [(set_attr "op_type" "SI,SS")
4976 (set_attr "atype" "mem")])
4978 (define_insn "*xorqi3_ss_inv"
4979 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4980 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4982 (clobber (reg:CC 33))]
4987 [(set_attr "op_type" "SI,SS")
4988 (set_attr "atype" "mem")])
4992 ;;- Negate instructions.
4996 ; negdi2 instruction pattern(s).
4999 (define_expand "negdi2"
5001 [(set (match_operand:DI 0 "register_operand" "=d")
5002 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5003 (clobber (reg:CC 33))])]
5007 (define_insn "*negdi2_64"
5008 [(set (match_operand:DI 0 "register_operand" "=d")
5009 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5010 (clobber (reg:CC 33))]
5013 [(set_attr "op_type" "RR")])
5015 (define_insn "*negdi2_31"
5016 [(set (match_operand:DI 0 "register_operand" "=d")
5017 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5018 (clobber (reg:CC 33))]
5023 xop[0] = gen_label_rtx ();
5024 output_asm_insn (\"lcr\\t%0,%1\", operands);
5025 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5026 output_asm_insn (\"je\\t%l0\", xop);
5027 output_asm_insn (\"bctr\\t%0,0\", operands);
5028 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5029 CODE_LABEL_NUMBER (xop[0]));
5032 [(set_attr "op_type" "NN")
5033 (set_attr "type" "other")
5034 (set_attr "length" "10")])
5037 ; negsi2 instruction pattern(s).
5040 (define_insn "negsi2"
5041 [(set (match_operand:SI 0 "register_operand" "=d")
5042 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5043 (clobber (reg:CC 33))]
5046 [(set_attr "op_type" "RR")])
5049 ; negdf2 instruction pattern(s).
5052 (define_expand "negdf2"
5054 [(set (match_operand:DF 0 "register_operand" "=f")
5055 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5056 (clobber (reg:CC 33))])]
5060 (define_insn "*negdf2"
5061 [(set (match_operand:DF 0 "register_operand" "=f")
5062 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5063 (clobber (reg:CC 33))]
5064 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5066 [(set_attr "op_type" "RRE")])
5068 (define_insn "*negdf2_ibm"
5069 [(set (match_operand:DF 0 "register_operand" "=f")
5070 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5071 (clobber (reg:CC 33))]
5072 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5074 [(set_attr "op_type" "RR")])
5077 ; negsf2 instruction pattern(s).
5080 (define_expand "negsf2"
5082 [(set (match_operand:SF 0 "register_operand" "=f")
5083 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5084 (clobber (reg:CC 33))])]
5088 (define_insn "*negsf2"
5089 [(set (match_operand:SF 0 "register_operand" "=f")
5090 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5091 (clobber (reg:CC 33))]
5092 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5094 [(set_attr "op_type" "RRE")])
5096 (define_insn "*negsf2"
5097 [(set (match_operand:SF 0 "register_operand" "=f")
5098 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5099 (clobber (reg:CC 33))]
5100 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5102 [(set_attr "op_type" "RR")])
5106 ;;- Absolute value instructions.
5110 ; absdi2 instruction pattern(s).
5113 (define_insn "absdi2"
5114 [(set (match_operand:DI 0 "register_operand" "=d")
5115 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5116 (clobber (reg:CC 33))]
5119 [(set_attr "op_type" "RRE")])
5122 ; abssi2 instruction pattern(s).
5125 (define_insn "abssi2"
5126 [(set (match_operand:SI 0 "register_operand" "=d")
5127 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5128 (clobber (reg:CC 33))]
5131 [(set_attr "op_type" "RR")])
5134 ; absdf2 instruction pattern(s).
5137 (define_expand "absdf2"
5139 [(set (match_operand:DF 0 "register_operand" "=f")
5140 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5141 (clobber (reg:CC 33))])]
5145 (define_insn "*absdf2"
5146 [(set (match_operand:DF 0 "register_operand" "=f")
5147 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5148 (clobber (reg:CC 33))]
5149 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5151 [(set_attr "op_type" "RRE")])
5153 (define_insn "*absdf2_ibm"
5154 [(set (match_operand:DF 0 "register_operand" "=f")
5155 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5156 (clobber (reg:CC 33))]
5157 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5159 [(set_attr "op_type" "RR")])
5162 ; abssf2 instruction pattern(s).
5165 (define_expand "abssf2"
5167 [(set (match_operand:SF 0 "register_operand" "=f")
5168 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5169 (clobber (reg:CC 33))])]
5173 (define_insn "*abssf2"
5174 [(set (match_operand:SF 0 "register_operand" "=f")
5175 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5176 (clobber (reg:CC 33))]
5177 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5179 [(set_attr "op_type" "RRE")])
5181 (define_insn "*abssf2_ibm"
5182 [(set (match_operand:SF 0 "register_operand" "=f")
5183 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5184 (clobber (reg:CC 33))]
5185 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5187 [(set_attr "op_type" "RR")])
5190 ;;- Square root instructions.
5194 ; sqrtdf2 instruction pattern(s).
5197 (define_insn "sqrtdf2"
5198 [(set (match_operand:DF 0 "register_operand" "=f,f")
5199 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5200 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5204 [(set_attr "op_type" "RRE,RSE")])
5207 ; sqrtsf2 instruction pattern(s).
5210 (define_insn "sqrtsf2"
5211 [(set (match_operand:SF 0 "register_operand" "=f,f")
5212 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5213 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5217 [(set_attr "op_type" "RRE,RSE")])
5220 ;;- One complement instructions.
5224 ; one_cmpldi2 instruction pattern(s).
5227 (define_expand "one_cmpldi2"
5229 [(set (match_operand:DI 0 "register_operand" "")
5230 (xor:DI (match_operand:DI 1 "register_operand" "")
5232 (clobber (reg:CC 33))])]
5237 ; one_cmplsi2 instruction pattern(s).
5240 (define_expand "one_cmplsi2"
5242 [(set (match_operand:SI 0 "register_operand" "")
5243 (xor:SI (match_operand:SI 1 "register_operand" "")
5245 (clobber (reg:CC 33))])]
5250 ; one_cmplhi2 instruction pattern(s).
5253 (define_expand "one_cmplhi2"
5255 [(set (match_operand:HI 0 "register_operand" "")
5256 (xor:HI (match_operand:HI 1 "register_operand" "")
5258 (clobber (reg:CC 33))])]
5263 ; one_cmplqi2 instruction pattern(s).
5266 (define_expand "one_cmplqi2"
5268 [(set (match_operand:QI 0 "register_operand" "")
5269 (xor:QI (match_operand:QI 1 "register_operand" "")
5271 (clobber (reg:CC 33))])]
5277 ;;- Rotate instructions.
5281 ; rotldi3 instruction pattern(s).
5284 (define_insn "rotldi3"
5285 [(set (match_operand:DI 0 "register_operand" "=d,d")
5286 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5287 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5292 [(set_attr "op_type" "RSE")])
5295 ; rotlsi3 instruction pattern(s).
5298 (define_insn "rotlsi3"
5299 [(set (match_operand:SI 0 "register_operand" "=d,d")
5300 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5301 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5306 [(set_attr "op_type" "RSE")])
5310 ;;- Arithmetic shift instructions.
5314 ; ashldi3 instruction pattern(s).
5317 (define_expand "ashldi3"
5318 [(set (match_operand:DI 0 "register_operand" "")
5319 (ashift:DI (match_operand:DI 1 "register_operand" "")
5320 (match_operand:SI 2 "nonmemory_operand" "")))]
5324 (define_insn "*ashldi3_31"
5325 [(set (match_operand:DI 0 "register_operand" "=d,d")
5326 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5327 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5332 [(set_attr "op_type" "RS")])
5334 (define_insn "*ashldi3_64"
5335 [(set (match_operand:DI 0 "register_operand" "=d,d")
5336 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5337 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5342 [(set_attr "op_type" "RSE")])
5345 ; ashrdi3 instruction pattern(s).
5348 (define_expand "ashrdi3"
5350 [(set (match_operand:DI 0 "register_operand" "")
5351 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5352 (match_operand:SI 2 "nonmemory_operand" "")))
5353 (clobber (reg:CC 33))])]
5357 (define_insn "*ashrdi3_cc_31"
5359 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5360 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5362 (set (match_operand:DI 0 "register_operand" "=d,d")
5363 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5364 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5368 [(set_attr "op_type" "RS")])
5370 (define_insn "*ashrdi3_cconly_31"
5372 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5373 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5375 (clobber (match_scratch:DI 0 "=d,d"))]
5376 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5380 [(set_attr "op_type" "RS")])
5382 (define_insn "*ashrdi3_31"
5383 [(set (match_operand:DI 0 "register_operand" "=d,d")
5384 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5385 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5386 (clobber (reg:CC 33))]
5391 [(set_attr "op_type" "RS")])
5393 (define_insn "*ashrdi3_cc_64"
5395 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5396 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5398 (set (match_operand:DI 0 "register_operand" "=d,d")
5399 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5400 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5404 [(set_attr "op_type" "RSE")])
5406 (define_insn "*ashrdi3_cconly_64"
5408 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5409 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5411 (clobber (match_scratch:DI 0 "=d,d"))]
5412 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5416 [(set_attr "op_type" "RSE")])
5418 (define_insn "*ashrdi3_64"
5419 [(set (match_operand:DI 0 "register_operand" "=d,d")
5420 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5421 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5422 (clobber (reg:CC 33))]
5427 [(set_attr "op_type" "RSE")])
5430 ; ashlsi3 instruction pattern(s).
5433 (define_insn "ashlsi3"
5434 [(set (match_operand:SI 0 "register_operand" "=d,d")
5435 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5436 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5441 [(set_attr "op_type" "RS")])
5444 ; ashrsi3 instruction pattern(s).
5447 (define_insn "*ashrsi3_cc"
5449 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5450 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5452 (set (match_operand:SI 0 "register_operand" "=d,d")
5453 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5454 "s390_match_ccmode(insn, CCSmode)"
5458 [(set_attr "op_type" "RS")])
5460 (define_insn "*ashrsi3_cconly"
5462 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5463 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5465 (clobber (match_scratch:SI 0 "=d,d"))]
5466 "s390_match_ccmode(insn, CCSmode)"
5470 [(set_attr "op_type" "RS")])
5472 (define_insn "ashrsi3"
5473 [(set (match_operand:SI 0 "register_operand" "=d,d")
5474 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5475 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5476 (clobber (reg:CC 33))]
5481 [(set_attr "op_type" "RS")])
5485 ;;- logical shift instructions.
5489 ; lshrdi3 instruction pattern(s).
5492 (define_expand "lshrdi3"
5493 [(set (match_operand:DI 0 "register_operand" "")
5494 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5495 (match_operand:SI 2 "nonmemory_operand" "")))]
5499 (define_insn "*lshrdi3_31"
5500 [(set (match_operand:DI 0 "register_operand" "=d,d")
5501 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5502 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5507 [(set_attr "op_type" "RS,RS")])
5509 (define_insn "*lshrdi3_64"
5510 [(set (match_operand:DI 0 "register_operand" "=d,d")
5511 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5512 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5517 [(set_attr "op_type" "RS,RS")])
5520 ; lshrsi3 instruction pattern(s).
5523 (define_insn "lshrsi3"
5524 [(set (match_operand:SI 0 "register_operand" "=d,d")
5525 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5526 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5531 [(set_attr "op_type" "RS")])
5535 ;; Branch instruction patterns.
5538 (define_expand "beq"
5539 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5541 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5542 (label_ref (match_operand 0 "" ""))
5545 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5547 (define_expand "bne"
5548 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5550 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5551 (label_ref (match_operand 0 "" ""))
5554 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5556 (define_expand "bgt"
5557 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5559 (if_then_else (gt (reg:CCS 33) (const_int 0))
5560 (label_ref (match_operand 0 "" ""))
5563 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5565 (define_expand "bgtu"
5566 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5568 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5569 (label_ref (match_operand 0 "" ""))
5572 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5574 (define_expand "blt"
5575 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5577 (if_then_else (lt (reg:CCS 33) (const_int 0))
5578 (label_ref (match_operand 0 "" ""))
5581 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5583 (define_expand "bltu"
5584 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5586 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5587 (label_ref (match_operand 0 "" ""))
5590 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5592 (define_expand "bge"
5593 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5595 (if_then_else (ge (reg:CCS 33) (const_int 0))
5596 (label_ref (match_operand 0 "" ""))
5599 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5601 (define_expand "bgeu"
5602 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5604 (if_then_else (geu (reg:CCU 33) (const_int 0))
5605 (label_ref (match_operand 0 "" ""))
5608 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5610 (define_expand "ble"
5611 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5613 (if_then_else (le (reg:CCS 33) (const_int 0))
5614 (label_ref (match_operand 0 "" ""))
5617 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5619 (define_expand "bleu"
5620 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5622 (if_then_else (leu (reg:CCU 33) (const_int 0))
5623 (label_ref (match_operand 0 "" ""))
5626 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5628 (define_expand "bunordered"
5629 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5631 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5632 (label_ref (match_operand 0 "" ""))
5635 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5637 (define_expand "bordered"
5638 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5640 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5641 (label_ref (match_operand 0 "" ""))
5644 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5646 (define_expand "buneq"
5647 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5649 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5650 (label_ref (match_operand 0 "" ""))
5653 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5655 (define_expand "bungt"
5656 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5658 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5659 (label_ref (match_operand 0 "" ""))
5662 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5664 (define_expand "bunlt"
5665 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5667 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5668 (label_ref (match_operand 0 "" ""))
5671 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5673 (define_expand "bunge"
5674 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5676 (if_then_else (unge (reg:CCS 33) (const_int 0))
5677 (label_ref (match_operand 0 "" ""))
5680 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5682 (define_expand "bunle"
5683 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5685 (if_then_else (unle (reg:CCS 33) (const_int 0))
5686 (label_ref (match_operand 0 "" ""))
5689 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5691 (define_expand "bltgt"
5692 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5694 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5695 (label_ref (match_operand 0 "" ""))
5698 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5702 ;;- Conditional jump instructions.
5705 (define_insn "cjump"
5708 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5709 (label_ref (match_operand 0 "" ""))
5714 if (get_attr_length (insn) == 4)
5715 return \"j%C1\\t%l0\";
5716 else if (TARGET_64BIT)
5717 return \"jg%C1\\t%l0\";
5721 [(set_attr "op_type" "RI")
5722 (set (attr "length")
5723 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5725 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5727 (eq (symbol_ref "flag_pic") (const_int 0))
5728 (const_int 6)] (const_int 8)))])
5730 (define_insn "*cjump_long"
5733 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5734 (match_operand 0 "address_operand" "p")
5739 if (get_attr_op_type (insn) == OP_TYPE_RR)
5740 return \"b%C1r\\t%0\";
5742 return \"b%C1\\t%a0\";
5744 [(set (attr "op_type")
5745 (if_then_else (match_operand 0 "register_operand" "")
5746 (const_string "RR") (const_string "RX")))
5747 (set_attr "atype" "mem")])
5751 ;;- Negated conditional jump instructions.
5754 (define_insn "icjump"
5757 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5759 (label_ref (match_operand 0 "" ""))))]
5763 if (get_attr_length (insn) == 4)
5764 return \"j%D1\\t%l0\";
5765 else if (TARGET_64BIT)
5766 return \"jg%D1\\t%l0\";
5770 [(set_attr "op_type" "RI")
5771 (set (attr "length")
5772 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5774 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5776 (eq (symbol_ref "flag_pic") (const_int 0))
5777 (const_int 6)] (const_int 8)))])
5779 (define_insn "*icjump_long"
5782 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5784 (match_operand 0 "address_operand" "p")))]
5788 if (get_attr_op_type (insn) == OP_TYPE_RR)
5789 return \"b%D1r\\t%0\";
5791 return \"b%D1\\t%a0\";
5793 [(set (attr "op_type")
5794 (if_then_else (match_operand 0 "register_operand" "")
5795 (const_string "RR") (const_string "RX")))
5796 (set_attr "atype" "mem")])
5799 ;;- Trap instructions.
5803 [(trap_if (const_int 1) (const_int 0))]
5806 [(set_attr "op_type" "RX")])
5808 (define_expand "conditional_trap"
5809 [(set (match_dup 2) (match_dup 3))
5810 (trap_if (match_operator 0 "comparison_operator"
5811 [(match_dup 2) (const_int 0)])
5812 (match_operand:SI 1 "general_operand" ""))]
5816 enum machine_mode ccmode;
5818 if (operands[1] != const0_rtx) FAIL;
5820 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5821 s390_compare_op0, s390_compare_op1);
5822 operands[2] = gen_rtx_REG (ccmode, 33);
5823 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5826 (define_insn "*trap"
5827 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5831 [(set_attr "op_type" "RX")])
5834 ;;- Loop instructions.
5836 ;; This is all complicated by the fact that since this is a jump insn
5837 ;; we must handle our own output reloads.
5839 (define_expand "doloop_end"
5840 [(use (match_operand 0 "" "")) ; loop pseudo
5841 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5842 (use (match_operand 2 "" "")) ; max iterations
5843 (use (match_operand 3 "" "")) ; loop level
5844 (use (match_operand 4 "" ""))] ; label
5848 if (GET_MODE (operands[0]) == SImode)
5849 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5850 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5851 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5858 (define_insn "doloop_si"
5861 (ne (match_operand:SI 1 "register_operand" "d,d")
5863 (label_ref (match_operand 0 "" ""))
5865 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5866 (plus:SI (match_dup 1) (const_int -1)))
5867 (clobber (match_scratch:SI 3 "=X,&d"))
5868 (clobber (reg:CC 33))]
5872 if (which_alternative != 0)
5874 else if (get_attr_length (insn) == 4)
5875 return \"brct\\t%1,%l0\";
5879 [(set_attr "op_type" "RI")
5880 (set (attr "length")
5881 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5883 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5885 (eq (symbol_ref "flag_pic") (const_int 0))
5886 (const_int 6)] (const_int 8)))])
5888 (define_insn "*doloop_si_long"
5891 (ne (match_operand:SI 1 "register_operand" "d,d")
5893 (match_operand 0 "address_operand" "p,p")
5895 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5896 (plus:SI (match_dup 1) (const_int -1)))
5897 (clobber (match_scratch:SI 3 "=X,&d"))
5898 (clobber (reg:CC 33))]
5902 if (get_attr_op_type (insn) == OP_TYPE_RR)
5903 return \"bctr\\t%1,%0\";
5905 return \"bct\\t%1,%a0\";
5907 [(set (attr "op_type")
5908 (if_then_else (match_operand 0 "register_operand" "")
5909 (const_string "RR") (const_string "RX")))
5910 (set_attr "atype" "mem")])
5914 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5916 (match_operand 0 "" "")
5918 (set (match_operand:SI 2 "nonimmediate_operand" "")
5919 (plus:SI (match_dup 1) (const_int -1)))
5920 (clobber (match_scratch:SI 3 ""))
5921 (clobber (reg:CC 33))]
5923 && (! REG_P (operands[2])
5924 || ! rtx_equal_p (operands[1], operands[2]))"
5925 [(set (match_dup 3) (match_dup 1))
5926 (parallel [(set (reg:CCAN 33)
5927 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5929 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5930 (set (match_dup 2) (match_dup 3))
5931 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5936 (define_insn "doloop_di"
5939 (ne (match_operand:DI 1 "register_operand" "d,d")
5941 (label_ref (match_operand 0 "" ""))
5943 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
5944 (plus:DI (match_dup 1) (const_int -1)))
5945 (clobber (match_scratch:DI 3 "=X,&d"))
5946 (clobber (reg:CC 33))]
5950 if (which_alternative != 0)
5952 else if (get_attr_length (insn) == 4)
5953 return \"brctg\\t%1,%l0\";
5957 [(set_attr "op_type" "RI")
5958 (set (attr "length")
5959 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5960 (const_int 4) (const_int 12)))])
5962 (define_insn "*doloop_di_long"
5965 (ne (match_operand:DI 1 "register_operand" "d,d")
5967 (match_operand 0 "address_operand" "p,p")
5969 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
5970 (plus:DI (match_dup 1) (const_int -1)))
5971 (clobber (match_scratch:DI 3 "=X,&d"))
5972 (clobber (reg:CC 33))]
5976 if (get_attr_op_type (insn) == OP_TYPE_RRE)
5977 return \"bctgr\\t%1,%0\";
5979 return \"bctg\\t%1,%a0\";
5981 [(set (attr "op_type")
5982 (if_then_else (match_operand 0 "register_operand" "")
5983 (const_string "RRE") (const_string "RXE")))
5984 (set_attr "atype" "mem")])
5988 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
5990 (match_operand 0 "" "")
5992 (set (match_operand:DI 2 "nonimmediate_operand" "")
5993 (plus:DI (match_dup 1) (const_int -1)))
5994 (clobber (match_scratch:DI 3 ""))
5995 (clobber (reg:CC 33))]
5997 && (! REG_P (operands[2])
5998 || ! rtx_equal_p (operands[1], operands[2]))"
5999 [(set (match_dup 3) (match_dup 1))
6000 (parallel [(set (reg:CCAN 33)
6001 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6003 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6004 (set (match_dup 2) (match_dup 3))
6005 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6011 ;;- Unconditional jump instructions.
6015 ; jump instruction pattern(s).
6019 [(set (pc) (label_ref (match_operand 0 "" "")))]
6023 if (get_attr_length (insn) == 4)
6025 else if (TARGET_64BIT)
6026 return \"jg\\t%l0\";
6030 [(set_attr "op_type" "RI")
6031 (set (attr "length")
6032 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6034 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6036 (eq (symbol_ref "flag_pic") (const_int 0))
6037 (const_int 6)] (const_int 8)))])
6040 ; indirect-jump instruction pattern(s).
6043 (define_insn "indirect_jump"
6044 [(set (pc) (match_operand 0 "address_operand" "p"))]
6048 if (get_attr_op_type (insn) == OP_TYPE_RR)
6053 [(set (attr "op_type")
6054 (if_then_else (match_operand 0 "register_operand" "")
6055 (const_string "RR") (const_string "RX")))
6056 (set_attr "atype" "mem")])
6059 ; casesi instruction pattern(s).
6062 (define_insn "casesi_jump"
6063 [(set (pc) (match_operand 0 "address_operand" "p"))
6064 (use (label_ref (match_operand 1 "" "")))]
6068 if (get_attr_op_type (insn) == OP_TYPE_RR)
6073 [(set (attr "op_type")
6074 (if_then_else (match_operand 0 "register_operand" "")
6075 (const_string "RR") (const_string "RX")))
6076 (set_attr "atype" "mem")])
6078 (define_expand "casesi"
6079 [(match_operand:SI 0 "general_operand" "")
6080 (match_operand:SI 1 "general_operand" "")
6081 (match_operand:SI 2 "general_operand" "")
6082 (label_ref (match_operand 3 "" ""))
6083 (label_ref (match_operand 4 "" ""))]
6087 rtx index = gen_reg_rtx (SImode);
6088 rtx base = gen_reg_rtx (Pmode);
6089 rtx target = gen_reg_rtx (Pmode);
6091 emit_move_insn (index, operands[0]);
6092 emit_insn (gen_subsi3 (index, index, operands[1]));
6093 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6096 if (Pmode != SImode)
6097 index = convert_to_mode (Pmode, index, 1);
6098 if (GET_CODE (index) != REG)
6099 index = copy_to_mode_reg (Pmode, index);
6102 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6104 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6106 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6108 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6109 emit_move_insn (target, index);
6112 target = gen_rtx_PLUS (Pmode, base, target);
6113 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6120 ;;- Jump to subroutine.
6125 ; untyped call instruction pattern(s).
6128 ;; Call subroutine returning any type.
6129 (define_expand "untyped_call"
6130 [(parallel [(call (match_operand 0 "" "")
6132 (match_operand 1 "" "")
6133 (match_operand 2 "" "")])]
6139 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6141 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6143 rtx set = XVECEXP (operands[2], 0, i);
6144 emit_move_insn (SET_DEST (set), SET_SRC (set));
6147 /* The optimizer does not know that the call sets the function value
6148 registers we stored in the result block. We avoid problems by
6149 claiming that all hard registers are used and clobbered at this
6151 emit_insn (gen_blockage ());
6156 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6157 ;; all of memory. This blocks insns from being moved across this point.
6159 (define_insn "blockage"
6160 [(unspec_volatile [(const_int 0)] 0)]
6163 [(set_attr "type" "none")])
6168 ; call instruction pattern(s).
6171 (define_expand "call"
6172 [(call (match_operand 0 "" "")
6173 (match_operand 1 "" ""))
6174 (use (match_operand 2 "" ""))]
6181 /* Direct function calls need special treatment. */
6182 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6184 rtx sym = XEXP (operands[0], 0);
6186 /* When calling a global routine in PIC mode, we must
6187 replace the symbol itself with the PLT stub. */
6188 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6190 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6191 sym = gen_rtx_CONST (Pmode, sym);
6196 /* Unless we can use the bras(l) insn, force the
6197 routine address into a register. */
6198 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6200 rtx target = gen_reg_rtx (Pmode);
6201 emit_move_insn (target, sym);
6205 operands[0] = gen_rtx_MEM (QImode, sym);
6209 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6210 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6212 /* In 31-bit, we must load the GOT register even if the
6213 compiler doesn't know about it, because the PLT glue
6214 code uses it. In 64-bit, this is not necessary. */
6215 if (plt_call && !TARGET_64BIT)
6216 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6221 (define_expand "call_exp"
6222 [(parallel [(call (match_operand 0 "" "")
6223 (match_operand 1 "" ""))
6224 (clobber (match_operand 2 "" ""))])]
6228 (define_insn "brasl"
6229 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6230 (match_operand:SI 1 "const_int_operand" "n"))
6231 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6234 [(set_attr "op_type" "RIL")
6235 (set_attr "type" "jsr")])
6238 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6239 (match_operand:SI 1 "const_int_operand" "n"))
6240 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6243 [(set_attr "op_type" "RI")
6244 (set_attr "type" "jsr")])
6246 (define_insn "basr_64"
6247 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6248 (match_operand:SI 1 "const_int_operand" "n"))
6249 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6252 [(set_attr "op_type" "RR")
6253 (set_attr "type" "jsr")
6254 (set_attr "atype" "mem")])
6256 (define_insn "basr_31"
6257 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6258 (match_operand:SI 1 "const_int_operand" "n"))
6259 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6262 [(set_attr "op_type" "RR")
6263 (set_attr "type" "jsr")
6264 (set_attr "atype" "mem")])
6266 (define_insn "bas_64"
6267 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6268 (match_operand:SI 1 "const_int_operand" "n"))
6269 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6272 [(set_attr "op_type" "RX")
6273 (set_attr "type" "jsr")
6274 (set_attr "atype" "mem")])
6276 (define_insn "bas_31"
6277 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6278 (match_operand:SI 1 "const_int_operand" "n"))
6279 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6282 [(set_attr "op_type" "RX")
6283 (set_attr "type" "jsr")
6284 (set_attr "atype" "mem")])
6288 ; call_value instruction pattern(s).
6291 (define_expand "call_value"
6292 [(set (match_operand 0 "" "")
6293 (call (match_operand 1 "" "")
6294 (match_operand 2 "" "")))
6295 (use (match_operand 3 "" ""))]
6302 /* Direct function calls need special treatment. */
6303 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6305 rtx sym = XEXP (operands[1], 0);
6307 /* When calling a global routine in PIC mode, we must
6308 replace the symbol itself with the PLT stub. */
6309 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6311 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6312 sym = gen_rtx_CONST (Pmode, sym);
6317 /* Unless we can use the bras(l) insn, force the
6318 routine address into a register. */
6319 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6321 rtx target = gen_reg_rtx (Pmode);
6322 emit_move_insn (target, sym);
6326 operands[1] = gen_rtx_MEM (QImode, sym);
6330 insn = emit_call_insn (
6331 gen_call_value_exp (operands[0], operands[1], operands[2],
6332 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6334 /* In 31-bit, we must load the GOT register even if the
6335 compiler doesn't know about it, because the PLT glue
6336 code uses it. In 64-bit, this is not necessary. */
6337 if (plt_call && !TARGET_64BIT)
6338 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6343 (define_expand "call_value_exp"
6344 [(parallel [(set (match_operand 0 "" "")
6345 (call (match_operand 1 "" "")
6346 (match_operand 2 "" "")))
6347 (clobber (match_operand 3 "" ""))])]
6351 (define_insn "brasl_r"
6352 [(set (match_operand 0 "register_operand" "=df")
6353 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6354 (match_operand:SI 2 "const_int_operand" "n")))
6355 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6358 [(set_attr "op_type" "RIL")
6359 (set_attr "type" "jsr")])
6361 (define_insn "bras_r"
6362 [(set (match_operand 0 "register_operand" "=df")
6363 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6364 (match_operand:SI 2 "const_int_operand" "n")))
6365 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6368 [(set_attr "op_type" "RI")
6369 (set_attr "type" "jsr")])
6371 (define_insn "basr_r_64"
6372 [(set (match_operand 0 "register_operand" "=df")
6373 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6374 (match_operand:SI 2 "const_int_operand" "n")))
6375 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6378 [(set_attr "op_type" "RR")
6379 (set_attr "type" "jsr")])
6381 (define_insn "basr_r_31"
6382 [(set (match_operand 0 "register_operand" "=df")
6383 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6384 (match_operand:SI 2 "const_int_operand" "n")))
6385 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6388 [(set_attr "op_type" "RR")
6389 (set_attr "type" "jsr")
6390 (set_attr "atype" "mem")])
6392 (define_insn "bas_r_64"
6393 [(set (match_operand 0 "register_operand" "=df")
6394 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6395 (match_operand:SI 2 "const_int_operand" "n")))
6396 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6399 [(set_attr "op_type" "RX")
6400 (set_attr "type" "jsr")
6401 (set_attr "atype" "mem")])
6403 (define_insn "bas_r_31"
6404 [(set (match_operand 0 "register_operand" "=df")
6405 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6406 (match_operand:SI 2 "const_int_operand" "n")))
6407 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6410 [(set_attr "op_type" "RX")
6411 (set_attr "type" "jsr")
6412 (set_attr "atype" "mem")])
6416 ;;- Miscellaneous instructions.
6420 ; allocate stack instruction pattern(s).
6423 (define_expand "allocate_stack"
6425 (plus (reg 15) (match_operand 1 "general_operand" "")))
6426 (set (match_operand 0 "general_operand" "")
6431 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6432 rtx chain = gen_rtx (MEM, Pmode, stack);
6433 rtx temp = gen_reg_rtx (Pmode);
6435 emit_move_insn (temp, chain);
6438 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6440 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6442 emit_move_insn (chain, temp);
6444 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6450 ; setjmp/longjmp instruction pattern(s).
6453 (define_expand "builtin_setjmp_setup"
6454 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6458 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6459 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6461 emit_move_insn (base, basereg);
6465 (define_expand "builtin_setjmp_receiver"
6466 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6470 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6471 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6472 SYMBOL_REF_FLAG (got) = 1;
6474 emit_move_insn (gotreg, got);
6475 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6479 (define_expand "builtin_longjmp"
6480 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6484 /* The elements of the buffer are, in order: */
6485 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6486 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6487 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6488 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6489 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6490 rtx jmp = gen_rtx_REG (Pmode, 14);
6492 emit_move_insn (jmp, lab);
6493 emit_move_insn (basereg, base);
6494 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6495 emit_move_insn (hard_frame_pointer_rtx, fp);
6497 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6498 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6499 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6500 emit_indirect_jump (jmp);
6505 ;; These patterns say how to save and restore the stack pointer. We need not
6506 ;; save the stack pointer at function level since we are careful to
6507 ;; preserve the backchain. At block level, we have to restore the backchain
6508 ;; when we restore the stack pointer.
6510 ;; For nonlocal gotos, we must save both the stack pointer and its
6511 ;; backchain and restore both. Note that in the nonlocal case, the
6512 ;; save area is a memory location.
6514 (define_expand "save_stack_function"
6515 [(match_operand 0 "general_operand" "")
6516 (match_operand 1 "general_operand" "")]
6520 (define_expand "restore_stack_function"
6521 [(match_operand 0 "general_operand" "")
6522 (match_operand 1 "general_operand" "")]
6526 (define_expand "restore_stack_block"
6527 [(use (match_operand 0 "register_operand" ""))
6528 (set (match_dup 2) (match_dup 3))
6529 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6530 (set (match_dup 3) (match_dup 2))]
6534 operands[2] = gen_reg_rtx (Pmode);
6535 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6538 (define_expand "save_stack_nonlocal"
6539 [(match_operand 0 "memory_operand" "")
6540 (match_operand 1 "register_operand" "")]
6544 rtx temp = gen_reg_rtx (Pmode);
6546 /* Copy the backchain to the first word, sp to the second. */
6547 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6548 emit_move_insn (operand_subword (operands[0], 0, 0,
6549 TARGET_64BIT ? TImode : DImode),
6551 emit_move_insn (operand_subword (operands[0], 1, 0,
6552 TARGET_64BIT ? TImode : DImode),
6557 (define_expand "restore_stack_nonlocal"
6558 [(match_operand 0 "register_operand" "")
6559 (match_operand 1 "memory_operand" "")]
6563 rtx temp = gen_reg_rtx (Pmode);
6565 /* Restore the backchain from the first word, sp from the second. */
6566 emit_move_insn (temp,
6567 operand_subword (operands[1], 0, 0,
6568 TARGET_64BIT ? TImode : DImode));
6569 emit_move_insn (operands[0],
6570 operand_subword (operands[1], 1, 0,
6571 TARGET_64BIT ? TImode : DImode));
6572 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6578 ; nop instruction pattern(s).
6585 [(set_attr "op_type" "RR")])
6589 ; Special literal pool access instruction pattern(s).
6592 (define_insn "consttable_qi"
6593 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6597 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6600 [(set_attr "op_type" "NN")
6601 (set_attr "length" "1")])
6603 (define_insn "consttable_hi"
6604 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6608 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6611 [(set_attr "op_type" "NN")
6612 (set_attr "length" "2")])
6614 (define_insn "consttable_si"
6615 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6619 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6620 return \".long\\t%0\";
6622 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6625 [(set_attr "op_type" "NN")
6626 (set_attr "length" "4")])
6628 (define_insn "consttable_di"
6629 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6633 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6636 [(set_attr "op_type" "NN")
6637 (set_attr "length" "8")])
6639 (define_insn "consttable_sf"
6640 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6646 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6649 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6650 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6653 [(set_attr "op_type" "NN")
6654 (set_attr "length" "4")])
6656 (define_insn "consttable_df"
6657 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6663 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6666 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6667 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6670 [(set_attr "op_type" "NN")
6671 (set_attr "length" "8")])
6673 (define_insn "pool_start_31"
6674 [(unspec_volatile [(const_int 0)] 206)]
6677 [(set_attr "op_type" "NN")
6678 (set_attr "length" "2")])
6680 (define_insn "pool_end_31"
6681 [(unspec_volatile [(const_int 0)] 207)]
6684 [(set_attr "op_type" "NN")
6685 (set_attr "length" "2")])
6687 (define_insn "pool_start_64"
6688 [(unspec_volatile [(const_int 0)] 206)]
6690 ".section\\t.rodata\;.align\\t8"
6691 [(set_attr "op_type" "NN")
6692 (set_attr "length" "0")])
6694 (define_insn "pool_end_64"
6695 [(unspec_volatile [(const_int 0)] 207)]
6698 [(set_attr "op_type" "NN")
6699 (set_attr "length" "0")])
6701 (define_insn "reload_base_31"
6702 [(set (match_operand:SI 0 "register_operand" "=a")
6703 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6705 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6706 [(set_attr "op_type" "NN")
6707 (set_attr "type" "la")
6708 (set_attr "length" "6")])
6710 (define_insn "reload_base_64"
6711 [(set (match_operand:DI 0 "register_operand" "=a")
6712 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
6715 [(set_attr "op_type" "RIL")
6716 (set_attr "type" "la")])
6718 (define_insn "reload_anchor"
6719 [(set (match_operand:SI 0 "register_operand" "=a")
6720 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
6722 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
6723 [(set_attr "op_type" "NN")
6724 (set_attr "type" "la")
6725 (set_attr "length" "8")])
6728 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
6731 [(set_attr "op_type" "NN")
6732 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6735 ;; Insns related to generating the function prologue and epilogue.
6739 (define_expand "prologue"
6740 [(use (const_int 0))]
6744 s390_emit_prologue ();
6748 (define_expand "epilogue"
6749 [(use (const_int 1))]
6753 s390_emit_epilogue ();
6758 (define_insn "*return_si"
6760 (use (match_operand:SI 0 "register_operand" "a"))]
6763 [(set_attr "op_type" "RR")
6764 (set_attr "type" "jsr")
6765 (set_attr "atype" "mem")])
6767 (define_insn "*return_di"
6769 (use (match_operand:DI 0 "register_operand" "a"))]
6772 [(set_attr "op_type" "RR")
6773 (set_attr "type" "jsr")
6774 (set_attr "atype" "mem")])
6778 [(set (reg 13) (pc))
6779 (unspec_volatile [(const_int 0)] 200)]
6783 s390_output_constant_pool (asm_out_file);
6786 [(set_attr "op_type" "NN")
6787 (set_attr "type" "integer")])
6791 ;; Peephole optimization patterns.
6795 [(set (match_operand:SI 0 "memory_operand" "m")
6796 (match_operand:SI 1 "register_operand" "d"))
6803 [(set (match_operand:SI 0 "memory_operand" "m")
6804 (match_operand:SI 1 "register_operand" "d"))
6811 [(set (match_operand:SI 0 "register_operand" "")
6812 (match_operand:SI 1 "register_operand" ""))
6815 (plus:SI (match_dup 0)
6816 (match_operand:SI 2 "immediate_operand" "")))
6817 (clobber (reg:CC 33))])]
6818 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6819 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6820 REGNO (operands[0]) == BASE_REGISTER ||
6821 REGNO (operands[1]) == BASE_REGISTER) &&
6822 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6826 ; peepholes for fast char instructions
6830 ; [(set (match_operand:QI 0 "register_operand" "d")
6831 ; (match_operand:QI 1 "s_operand" "Q"))
6832 ; (set (match_operand:SI 2 "register_operand" "0")
6833 ; (zero_extend:SI (match_dup 0)))]
6834 ; "REGNO(operands[0]) == REGNO(operands[2])"
6835 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6838 ; [(set (match_operand:QI 0 "register_operand" "d")
6839 ; (match_operand:QI 1 "s_operand" "Q"))
6840 ; (set (match_operand:SI 2 "register_operand" "0")
6841 ; (sign_extend:SI (match_dup 0)))]
6842 ; "REGNO(operands[0]) == REGNO(operands[2])"
6843 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6846 [(set (match_operand:QI 0 "register_operand" "d")
6847 (match_operand:QI 1 "immediate_operand" "J"))
6848 (set (match_operand:SI 2 "register_operand" "0" )
6849 (sign_extend:SI (match_dup 0) ) )]
6850 "REGNO(operands[0]) == REGNO(operands[2])"
6854 ; peepholes for fast short instructions
6858 ; [(set (match_operand:HI 0 "register_operand" "d")
6859 ; (match_operand:HI 1 "s_operand" "Q"))
6860 ; (set (match_operand:SI 2 "register_operand" "0" )
6861 ; (zero_extend:SI (match_dup 0)))]
6862 ; "REGNO(operands[0]) == REGNO(operands[2])"
6863 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6866 [(set (match_operand:HI 0 "register_operand" "d")
6867 (match_operand:HI 1 "memory_operand" "m"))
6868 (set (match_operand:SI 2 "register_operand" "0" )
6869 (sign_extend:SI (match_dup 0)))]
6870 "REGNO(operands[0]) == REGNO(operands[2])"
6874 [(set (match_operand:HI 0 "register_operand" "d")
6875 (match_operand:HI 1 "immediate_operand" "K"))
6876 (set (match_operand:SI 2 "register_operand" "0" )
6877 (sign_extend:SI (match_dup 0) ) )]
6878 "REGNO(operands[0]) == REGNO(operands[2])"
6882 ; peepholes for divide instructions
6886 [(set (match_operand:DI 0 "register_operand" "d")
6887 (match_operand:DI 1 "memory_operand" "m"))
6889 (lshiftrt:DI (match_dup 0)
6890 (match_operand:SI 2 "immediate_operand" "J")))
6892 (div:SI (match_dup 0)
6893 (match_operand:SI 3 "nonimmediate_operand" "g")))
6899 output_asm_insn (\"l\\t%0,%1\", operands);
6900 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6902 if (REG_P (operands[3]))
6903 output_asm_insn (\"dr\\t%0,%3\", operands);
6905 output_asm_insn (\"d\\t%0,%3\", operands);
6907 return \"st\\t%N0,%N1\";
6911 [(set (match_operand:DI 0 "register_operand" "d")
6912 (match_operand:DI 1 "memory_operand" "m"))
6914 (lshiftrt:DI (match_dup 0)
6915 (match_operand:SI 2 "immediate_operand" "J")))
6917 (mod:SI (match_dup 0)
6918 (match_operand:SI 3 "nonimmediate_operand" "g")))
6924 output_asm_insn (\"l\\t%0,%1\", operands);
6925 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6927 if (REG_P (operands[3]))
6928 output_asm_insn (\"dr\\t%0,%3\", operands);
6930 output_asm_insn (\"d\\t%0,%3\", operands);
6932 return \"st\\t%0,%1\";