gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999-2015 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com) and
   5 ;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify it under
  10 ;; the terms of the GNU General Public License as published by the Free
  11 ;; Software Foundation; either version 3, or (at your option) any later
  12 ;; version.
  13
  14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 ;; for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;;
  24 ;; See constraints.md for a description of constraints specific to s390.
  25 ;;
  26
  27 ;; Special formats used for outputting 390 instructions.
  28 ;;
  29 ;;     %C: print opcode suffix for branch condition.
  30 ;;     %D: print opcode suffix for inverse branch condition.
  31 ;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
  32 ;;     %G: print the size of the operand in bytes.
  33 ;;     %O: print only the displacement of a memory reference.
  34 ;;     %R: print only the base register of a memory reference.
  35 ;;     %S: print S-type memory reference (base+displacement).
  36 ;;     %N: print the second word of a DImode operand.
  37 ;;     %M: print the second word of a TImode operand.
  38 ;;     %Y: print shift count operand.
  39 ;;
  40 ;;     %b: print integer X as if it's an unsigned byte.
  41 ;;     %c: print integer X as if it's an signed byte.
  42 ;;     %x: print integer X as if it's an unsigned halfword.
  43 ;;     %h: print integer X as if it's a signed halfword.
  44 ;;     %i: print the first nonzero HImode part of X.
  45 ;;     %j: print the first HImode part unequal to -1 of X.
  46 ;;     %k: print the first nonzero SImode part of X.
  47 ;;     %m: print the first SImode part unequal to -1 of X.
  48 ;;     %o: print integer X as if it's an unsigned 32bit word.
  49 ;;
  50 ;; We have a special constraint for pattern matching.
  51 ;;
  52 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  53 ;;
  54
  55 ;;
  56 ;; UNSPEC usage
  57 ;;
  58
  59 (define_c_enum "unspec" [
  60    ; Miscellaneous
  61    UNSPEC_ROUND
  62    UNSPEC_ICM
  63    UNSPEC_TIE
  64
  65    ; Convert CC into a str comparison result and copy it into an
  66    ; integer register
  67    ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
  68    UNSPEC_STRCMPCC_TO_INT
  69
  70    ; Copy CC as is into the lower 2 bits of an integer register
  71    UNSPEC_CC_TO_INT
  72
  73    ; GOT/PLT and lt-relative accesses
  74    UNSPEC_LTREL_OFFSET
  75    UNSPEC_LTREL_BASE
  76    UNSPEC_POOL_OFFSET
  77    UNSPEC_GOTENT
  78    UNSPEC_GOT
  79    UNSPEC_GOTOFF
  80    UNSPEC_PLT
  81    UNSPEC_PLTOFF
  82
  83    ; Literal pool
  84    UNSPEC_RELOAD_BASE
  85    UNSPEC_MAIN_BASE
  86    UNSPEC_LTREF
  87    UNSPEC_INSN
  88    UNSPEC_EXECUTE
  89
  90    ; Atomic Support
  91    UNSPEC_MB
  92    UNSPEC_MOVA
  93
  94    ; TLS relocation specifiers
  95    UNSPEC_TLSGD
  96    UNSPEC_TLSLDM
  97    UNSPEC_NTPOFF
  98    UNSPEC_DTPOFF
  99    UNSPEC_GOTNTPOFF
 100    UNSPEC_INDNTPOFF
 101
 102    ; TLS support
 103    UNSPEC_TLSLDM_NTPOFF
 104    UNSPEC_TLS_LOAD
 105
 106    ; String Functions
 107    UNSPEC_SRST
 108    UNSPEC_MVST
 109
 110    ; Stack Smashing Protector
 111    UNSPEC_SP_SET
 112    UNSPEC_SP_TEST
 113
 114    ; Test Data Class (TDC)
 115    UNSPEC_TDC_INSN
 116
 117    ; Population Count
 118    UNSPEC_POPCNT
 119    UNSPEC_COPYSIGN
 120
 121    ; Load FP Integer
 122    UNSPEC_FPINT_FLOOR
 123    UNSPEC_FPINT_BTRUNC
 124    UNSPEC_FPINT_ROUND
 125    UNSPEC_FPINT_CEIL
 126    UNSPEC_FPINT_NEARBYINT
 127    UNSPEC_FPINT_RINT
 128
 129    UNSPEC_LCBB
 130
 131    ; Vector
 132    UNSPEC_VEC_SMULT_HI
 133    UNSPEC_VEC_UMULT_HI
 134    UNSPEC_VEC_SMULT_LO
 135    UNSPEC_VEC_SMULT_EVEN
 136    UNSPEC_VEC_UMULT_EVEN
 137    UNSPEC_VEC_SMULT_ODD
 138    UNSPEC_VEC_UMULT_ODD
 139
 140    UNSPEC_VEC_VMAL
 141    UNSPEC_VEC_VMAH
 142    UNSPEC_VEC_VMALH
 143    UNSPEC_VEC_VMAE
 144    UNSPEC_VEC_VMALE
 145    UNSPEC_VEC_VMAO
 146    UNSPEC_VEC_VMALO
 147
 148    UNSPEC_VEC_GATHER
 149    UNSPEC_VEC_EXTRACT
 150    UNSPEC_VEC_INSERT_AND_ZERO
 151    UNSPEC_VEC_LOAD_BNDRY
 152    UNSPEC_VEC_LOAD_LEN
 153    UNSPEC_VEC_MERGEH
 154    UNSPEC_VEC_MERGEL
 155    UNSPEC_VEC_PACK
 156    UNSPEC_VEC_PACK_SATURATE
 157    UNSPEC_VEC_PACK_SATURATE_CC
 158    UNSPEC_VEC_PACK_SATURATE_GENCC
 159    UNSPEC_VEC_PACK_UNSIGNED_SATURATE
 160    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
 161    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
 162    UNSPEC_VEC_PERM
 163    UNSPEC_VEC_PERMI
 164    UNSPEC_VEC_EXTEND
 165    UNSPEC_VEC_STORE_LEN
 166    UNSPEC_VEC_UNPACKH
 167    UNSPEC_VEC_UNPACKH_L
 168    UNSPEC_VEC_UNPACKL
 169    UNSPEC_VEC_UNPACKL_L
 170    UNSPEC_VEC_ADDC
 171    UNSPEC_VEC_ADDC_U128
 172    UNSPEC_VEC_ADDE_U128
 173    UNSPEC_VEC_ADDEC_U128
 174    UNSPEC_VEC_AVG
 175    UNSPEC_VEC_AVGU
 176    UNSPEC_VEC_CHECKSUM
 177    UNSPEC_VEC_GFMSUM
 178    UNSPEC_VEC_GFMSUM_128
 179    UNSPEC_VEC_GFMSUM_ACCUM
 180    UNSPEC_VEC_GFMSUM_ACCUM_128
 181    UNSPEC_VEC_SET
 182
 183    UNSPEC_VEC_VSUMG
 184    UNSPEC_VEC_VSUMQ
 185    UNSPEC_VEC_VSUM
 186    UNSPEC_VEC_RL_MASK
 187    UNSPEC_VEC_SLL
 188    UNSPEC_VEC_SLB
 189    UNSPEC_VEC_SLDB
 190    UNSPEC_VEC_SRAL
 191    UNSPEC_VEC_SRAB
 192    UNSPEC_VEC_SRL
 193    UNSPEC_VEC_SRLB
 194
 195    UNSPEC_VEC_SUB_U128
 196    UNSPEC_VEC_SUBC
 197    UNSPEC_VEC_SUBC_U128
 198    UNSPEC_VEC_SUBE_U128
 199    UNSPEC_VEC_SUBEC_U128
 200
 201    UNSPEC_VEC_TEST_MASK
 202
 203    UNSPEC_VEC_VFAE
 204    UNSPEC_VEC_VFAECC
 205
 206    UNSPEC_VEC_VFEE
 207    UNSPEC_VEC_VFEECC
 208    UNSPEC_VEC_VFENE
 209    UNSPEC_VEC_VFENECC
 210
 211    UNSPEC_VEC_VISTR
 212    UNSPEC_VEC_VISTRCC
 213
 214    UNSPEC_VEC_VSTRC
 215    UNSPEC_VEC_VSTRCCC
 216
 217    UNSPEC_VEC_VCDGB
 218    UNSPEC_VEC_VCDLGB
 219
 220    UNSPEC_VEC_VCGDB
 221    UNSPEC_VEC_VCLGDB
 222
 223    UNSPEC_VEC_VFIDB
 224
 225    UNSPEC_VEC_VLDEB
 226    UNSPEC_VEC_VLEDB
 227
 228    UNSPEC_VEC_VFTCIDB
 229    UNSPEC_VEC_VFTCIDBCC
 230 ])
 231
 232 ;;
 233 ;; UNSPEC_VOLATILE usage
 234 ;;
 235
 236 (define_c_enum "unspecv" [
 237    ; Blockage
 238    UNSPECV_BLOCKAGE
 239
 240    ; TPF Support
 241    UNSPECV_TPF_PROLOGUE
 242    UNSPECV_TPF_EPILOGUE
 243
 244    ; Literal pool
 245    UNSPECV_POOL
 246    UNSPECV_POOL_SECTION
 247    UNSPECV_POOL_ALIGN
 248    UNSPECV_POOL_ENTRY
 249    UNSPECV_MAIN_POOL
 250
 251    ; TLS support
 252    UNSPECV_SET_TP
 253
 254    ; Atomic Support
 255    UNSPECV_CAS
 256    UNSPECV_ATOMIC_OP
 257
 258    ; Hotpatching (unremovable NOPs)
 259    UNSPECV_NOP_2_BYTE
 260    UNSPECV_NOP_4_BYTE
 261    UNSPECV_NOP_6_BYTE
 262
 263    ; Transactional Execution support
 264    UNSPECV_TBEGIN
 265    UNSPECV_TBEGIN_TDB
 266    UNSPECV_TBEGINC
 267    UNSPECV_TEND
 268    UNSPECV_TABORT
 269    UNSPECV_ETND
 270    UNSPECV_NTSTG
 271    UNSPECV_PPA
 272
 273    ; Set and get floating point control register
 274    UNSPECV_SFPC
 275    UNSPECV_EFPC
 276   ])
 277
 278 ;;
 279 ;; Registers
 280 ;;
 281
 282 ; Registers with special meaning
 283
 284 (define_constants
 285   [
 286    ; Sibling call register.
 287    (SIBCALL_REGNUM               1)
 288    ; Literal pool base register.
 289    (BASE_REGNUM                 13)
 290    ; Return address register.
 291    (RETURN_REGNUM               14)
 292    ; Condition code register.
 293    (CC_REGNUM                   33)
 294    ; Thread local storage pointer register.
 295    (TP_REGNUM                   36)
 296   ])
 297
 298 ; Hardware register names
 299
 300 (define_constants
 301   [
 302    ; General purpose registers
 303    (GPR0_REGNUM                  0)
 304    (GPR1_REGNUM                  1)
 305    ; Floating point registers.
 306    (FPR0_REGNUM                 16)
 307    (FPR1_REGNUM                 20)
 308    (FPR2_REGNUM                 17)
 309    (FPR3_REGNUM                 21)
 310    (FPR4_REGNUM                 18)
 311    (FPR5_REGNUM                 22)
 312    (FPR6_REGNUM                 19)
 313    (FPR7_REGNUM                 23)
 314    (FPR8_REGNUM                 24)
 315    (FPR9_REGNUM                 28)
 316    (FPR10_REGNUM                25)
 317    (FPR11_REGNUM                29)
 318    (FPR12_REGNUM                26)
 319    (FPR13_REGNUM                30)
 320    (FPR14_REGNUM                27)
 321    (FPR15_REGNUM                31)
 322    (VR0_REGNUM                  16)
 323    (VR16_REGNUM                 38)
 324    (VR23_REGNUM                 45)
 325    (VR24_REGNUM                 46)
 326    (VR31_REGNUM                 53)
 327   ])
 328
 329 ;;
 330 ;; PFPO GPR0 argument format
 331 ;;
 332
 333 (define_constants
 334   [
 335    ; PFPO operation type
 336    (PFPO_CONVERT          0x1000000)
 337    ; PFPO operand types
 338    (PFPO_OP_TYPE_SF             0x5)
 339    (PFPO_OP_TYPE_DF             0x6)
 340    (PFPO_OP_TYPE_TF             0x7)
 341    (PFPO_OP_TYPE_SD             0x8)
 342    (PFPO_OP_TYPE_DD             0x9)
 343    (PFPO_OP_TYPE_TD             0xa)
 344    ; Bitposition of operand types
 345    (PFPO_OP0_TYPE_SHIFT          16)
 346    (PFPO_OP1_TYPE_SHIFT           8)
 347   ])
 348
 349 ; Immediate operands for tbegin and tbeginc
 350 (define_constants [(TBEGIN_MASK  65292)]) ; 0xff0c
 351 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
 352
 353 ;; Instruction operand type as used in the Principles of Operation.
 354 ;; Used to determine defaults for length and other attribute values.
 355
 356 (define_attr "op_type"
 357   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
 358   (const_string "NN"))
 359
 360 ;; Instruction type attribute used for scheduling.
 361
 362 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 363                      cs,vs,store,sem,idiv,
 364                      imulhi,imulsi,imuldi,
 365                      branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 366                      floadtf,floaddf,floadsf,fstoredf,fstoresf,
 367                      fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 368                      ftoi,fsqrttf,fsqrtdf,fsqrtsf,
 369                      fmadddf,fmaddsf,
 370                      ftrunctf,ftruncdf, ftruncsd, ftruncdd,
 371                      itoftf, itofdf, itofsf, itofdd, itoftd,
 372                      fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
 373                      fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
 374                      ftoidfp, other"
 375   (cond [(eq_attr "op_type" "NN")  (const_string "other")
 376          (eq_attr "op_type" "SS")  (const_string "cs")]
 377     (const_string "integer")))
 378
 379 ;; Another attribute used for scheduling purposes:
 380 ;;   agen: Instruction uses the address generation unit
 381 ;;   reg: Instruction does not use the agen unit
 382
 383 (define_attr "atype" "agen,reg"
 384   (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
 385                 (const_string "reg")
 386                 (const_string "agen")))
 387
 388 ;; Properties concerning Z10 execution grouping and value forwarding.
 389 ;; z10_super: instruction is superscalar.
 390 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
 391 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
 392 ;;   target register.  It can forward this value to a second instruction that reads
 393 ;;   the same register if that second instruction is issued in the same group.
 394 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
 395 ;;   instruction in the S pipe writes to the register, then the T instruction
 396 ;;   can immediately read the new value.
 397 ;; z10_fr: union of Z10_fwd and z10_rec.
 398 ;; z10_c: second operand of instruction is a register and read with complemented bits.
 399 ;;
 400 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
 401
 402
 403 (define_attr "z10prop" "none,
 404                         z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
 405                         z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
 406                         z10_rec,
 407                         z10_fr, z10_fr_A3, z10_fr_E1,
 408                         z10_c"
 409              (const_string "none"))
 410
 411 ;; Properties concerning Z196 decoding
 412 ;; z196_alone: must group alone
 413 ;; z196_end: ends a group
 414 ;; z196_cracked: instruction is cracked or expanded
 415 (define_attr "z196prop" "none,
 416                          z196_alone, z196_ends,
 417                          z196_cracked"
 418              (const_string "none"))
 419
 420 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
 421
 422 ;; Length in bytes.
 423
 424 (define_attr "length" ""
 425   (cond [(eq_attr "op_type" "E,RR")                           (const_int 2)
 426          (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR")  (const_int 4)]
 427     (const_int 6)))
 428
 429
 430 ;; Processor type.  This attribute must exactly match the processor_type
 431 ;; enumeration in s390.h.  The current machine description does not
 432 ;; distinguish between g5 and g6, but there are differences between the two
 433 ;; CPUs could in theory be modeled.
 434
 435 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
 436   (const (symbol_ref "s390_tune_attr")))
 437
 438 (define_attr "cpu_facility"
 439   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
 440   (const_string "standard"))
 441
 442 (define_attr "enabled" ""
 443   (cond [(eq_attr "cpu_facility" "standard")
 444          (const_int 1)
 445
 446          (and (eq_attr "cpu_facility" "ieee")
 447               (match_test "TARGET_CPU_IEEE_FLOAT"))
 448          (const_int 1)
 449
 450          (and (eq_attr "cpu_facility" "zarch")
 451               (match_test "TARGET_ZARCH"))
 452          (const_int 1)
 453
 454          (and (eq_attr "cpu_facility" "longdisp")
 455               (match_test "TARGET_LONG_DISPLACEMENT"))
 456          (const_int 1)
 457
 458          (and (eq_attr "cpu_facility" "extimm")
 459               (match_test "TARGET_EXTIMM"))
 460          (const_int 1)
 461
 462          (and (eq_attr "cpu_facility" "dfp")
 463               (match_test "TARGET_DFP"))
 464          (const_int 1)
 465
 466          (and (eq_attr "cpu_facility" "cpu_zarch")
 467               (match_test "TARGET_CPU_ZARCH"))
 468          (const_int 1)
 469
 470          (and (eq_attr "cpu_facility" "z10")
 471               (match_test "TARGET_Z10"))
 472          (const_int 1)
 473
 474          (and (eq_attr "cpu_facility" "z196")
 475               (match_test "TARGET_Z196"))
 476          (const_int 1)
 477
 478          (and (eq_attr "cpu_facility" "zEC12")
 479               (match_test "TARGET_ZEC12"))
 480          (const_int 1)
 481
 482          (and (eq_attr "cpu_facility" "vec")
 483               (match_test "TARGET_VX"))
 484          (const_int 1)]
 485         (const_int 0)))
 486
 487 ;; Pipeline description for z900.  For lack of anything better,
 488 ;; this description is also used for the g5 and g6.
 489 (include "2064.md")
 490
 491 ;; Pipeline description for z990, z9-109 and z9-ec.
 492 (include "2084.md")
 493
 494 ;; Pipeline description for z10
 495 (include "2097.md")
 496
 497 ;; Pipeline description for z196
 498 (include "2817.md")
 499
 500 ;; Pipeline description for zEC12
 501 (include "2827.md")
 502
 503 ;; Predicates
 504 (include "predicates.md")
 505
 506 ;; Constraint definitions
 507 (include "constraints.md")
 508
 509 ;; Other includes
 510 (include "tpf.md")
 511
 512 ;; Iterators
 513
 514 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
 515
 516 ;; These mode iterators allow floating point patterns to be generated from the
 517 ;; same template.
 518 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
 519                               (SD "TARGET_HARD_DFP")])
 520 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
 521 (define_mode_iterator BFP [TF DF SF])
 522 (define_mode_iterator DFP [TD DD])
 523 (define_mode_iterator DFP_ALL [TD DD SD])
 524 (define_mode_iterator DSF [DF SF])
 525 (define_mode_iterator SD_SF [SF SD])
 526 (define_mode_iterator DD_DF [DF DD])
 527 (define_mode_iterator TD_TF [TF TD])
 528
 529 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 530 ;; from the same template.
 531 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
 532 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
 533 (define_mode_iterator DSI [DI SI])
 534 (define_mode_iterator TDI [TI DI])
 535
 536 ;; These mode iterators allow :P to be used for patterns that operate on
 537 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 538 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 539
 540 ;; These macros refer to the actual word_mode of the configuration.
 541 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
 542 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
 543 (define_mode_iterator W  [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
 544
 545 ;; Used by the umul pattern to express modes having half the size.
 546 (define_mode_attr DWH [(TI "DI") (DI "SI")])
 547 (define_mode_attr dwh [(TI "di") (DI "si")])
 548
 549 ;; This mode iterator allows the QI and HI patterns to be defined from
 550 ;; the same template.
 551 (define_mode_iterator HQI [HI QI])
 552
 553 ;; This mode iterator allows the integer patterns to be defined from the
 554 ;; same template.
 555 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
 556 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
 557
 558 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 559 ;; the same template.
 560 (define_code_iterator SHIFT [ashift lshiftrt])
 561
 562 ;; This iterator allows r[ox]sbg to be defined with the same template
 563 (define_code_iterator IXOR [ior xor])
 564
 565 ;; This iterator is used to expand the patterns for the nearest
 566 ;; integer functions.
 567 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
 568                             UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
 569                             UNSPEC_FPINT_NEARBYINT])
 570 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
 571                              (UNSPEC_FPINT_BTRUNC "btrunc")
 572                              (UNSPEC_FPINT_ROUND "round")
 573                              (UNSPEC_FPINT_CEIL "ceil")
 574                              (UNSPEC_FPINT_NEARBYINT "nearbyint")])
 575 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
 576                                      (UNSPEC_FPINT_BTRUNC "5")
 577                                      (UNSPEC_FPINT_ROUND "1")
 578                                      (UNSPEC_FPINT_CEIL "6")
 579                                      (UNSPEC_FPINT_NEARBYINT "0")])
 580
 581 ;; This iterator and attribute allow to combine most atomic operations.
 582 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 583 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
 584 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
 585                           (plus "add") (minus "sub") (mult "nand")])
 586 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
 587
 588 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
 589 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
 590 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
 591
 592 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
 593 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
 594 ;; SDmode.
 595 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
 596
 597 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 598 ;; Likewise for "<RXe>".
 599 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 600 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 601
 602 ;; The decimal floating point variants of add, sub, div and mul support 3
 603 ;; fp register operands.  The following attributes allow to merge the bfp and
 604 ;; dfp variants in a single insn definition.
 605
 606 ;; This attribute is used to set op_type accordingly.
 607 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
 608                         (DD "RRR") (SD "RRR")])
 609
 610 ;; This attribute is used in the operand constraint list in order to have the
 611 ;; first and the second operand match for bfp modes.
 612 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
 613
 614 ;; This attribute is used to merge the scalar vector instructions into
 615 ;; the FP patterns.  For non-supported modes (all but DF) it expands
 616 ;; to constraints which are supposed to be matched by an earlier
 617 ;; variant.
 618 (define_mode_attr v0      [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")])
 619 (define_mode_attr vf      [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")])
 620 (define_mode_attr vd      [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")])
 621
 622 ;; This attribute is used in the operand list of the instruction to have an
 623 ;; additional operand for the dfp instructions.
 624 (define_mode_attr op1 [(TF "") (DF "") (SF "")
 625                        (TD "%1,") (DD "%1,") (SD "%1,")])
 626
 627
 628 ;; This attribute is used in the operand constraint list
 629 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
 630 ;; TFmode values are represented by a fp register pair.  Since the
 631 ;; sign bit instructions only handle single source and target fp registers
 632 ;; these instructions can only be used for TFmode values if the source and
 633 ;; target operand uses the same fp register.
 634 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 635
 636 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
 637 ;; This is used to disable the memory alternative in TFmode patterns.
 638 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
 639
 640 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 641 ;; within instruction mnemonics.
 642 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 643
 644 ;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
 645 ;; modes and to an empty string for bfp modes.
 646 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 647
 648 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 649 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
 650 ;; version only operates on one register.
 651 (define_mode_attr d0 [(DI "d") (SI "0")])
 652
 653 ;; In combination with d0 this allows to combine instructions of which the 31bit
 654 ;; version only operates on one register. The DImode version needs an additional
 655 ;; register for the assembler output.
 656 (define_mode_attr 1 [(DI "%1,") (SI "")])
 657
 658 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 659 ;; 'ashift' and "srdl" in 'lshiftrt'.
 660 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 661
 662 ;; In SHIFT templates, this attribute holds the correct standard name for the
 663 ;; pattern itself and the corresponding function calls.
 664 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 665
 666 ;; This attribute handles differences in the instruction 'type' and will result
 667 ;; in "RRE" for DImode and "RR" for SImode.
 668 (define_mode_attr E [(DI "E") (SI "")])
 669
 670 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
 671 ;; to result in "RXY" for DImode and "RX" for SImode.
 672 (define_mode_attr Y [(DI "Y") (SI "")])
 673
 674 ;; This attribute handles differences in the instruction 'type' and will result
 675 ;; in "RSE" for TImode and "RS" for DImode.
 676 (define_mode_attr TE [(TI "E") (DI "")])
 677
 678 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
 679 ;; and "lcr" in SImode.
 680 (define_mode_attr g [(DI "g") (SI "")])
 681
 682 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
 683 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
 684 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
 685 ;; variant for long displacements.
 686 (define_mode_attr y [(DI "g") (SI "y")])
 687
 688 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
 689 ;; and "cds" in DImode.
 690 (define_mode_attr tg [(TI "g") (DI "")])
 691
 692 ;; In TDI templates, a string like "c<d>sg".
 693 (define_mode_attr td [(TI "d") (DI "")])
 694
 695 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
 696 ;; and "cfdbr" in SImode.
 697 (define_mode_attr gf [(DI "g") (SI "f")])
 698
 699 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
 700 ;; and sllk for SI.  This way it is possible to merge the new z196 SI
 701 ;; 3 operands shift instructions into the existing patterns.
 702 (define_mode_attr gk [(DI "g") (SI "k")])
 703
 704 ;; ICM mask required to load MODE value into the lowest subreg
 705 ;; of a SImode register.
 706 (define_mode_attr icm_lo [(HI "3") (QI "1")])
 707
 708 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
 709 ;; HImode and "llgc" in QImode.
 710 (define_mode_attr hc [(HI "h") (QI "c")])
 711
 712 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
 713 ;; in SImode.
 714 (define_mode_attr DBL [(DI "TI") (SI "DI")])
 715
 716 ;; This attribute expands to DF for TFmode and to DD for TDmode .  It is
 717 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
 718 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
 719
 720 ;; Maximum unsigned integer that fits in MODE.
 721 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 722
 723 ;; Start and end field computations for RISBG et al.
 724 (define_mode_attr bfstart [(DI "s") (SI "t")])
 725 (define_mode_attr bfend   [(DI "e") (SI "f")])
 726
 727 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 728 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
 729
 730 ;; Allow return and simple_return to be defined from a single template.
 731 (define_code_iterator ANY_RETURN [return simple_return])
 732
 733
 734
 735 ; Condition code modes generated by vector fp comparisons.  These will
 736 ; be used also in single element mode.
 737 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
 738 ; Used with VFCMP to expand part of the mnemonic
 739 ; For fp we have a mismatch: eq in the insn name - e in asm
 740 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 741 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
 742
 743
 744 (include "vector.md")
 745
 746 ;;
 747 ;;- Compare instructions.
 748 ;;
 749
 750 ; Test-under-Mask instructions
 751
 752 (define_insn "*tmqi_mem"
 753   [(set (reg CC_REGNUM)
 754         (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
 755                          (match_operand:QI 1 "immediate_operand" "n,n"))
 756                  (match_operand:QI 2 "immediate_operand" "n,n")))]
 757   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
 758   "@
 759    tm\t%S0,%b1
 760    tmy\t%S0,%b1"
 761   [(set_attr "op_type" "SI,SIY")
 762    (set_attr "z10prop" "z10_super,z10_super")])
 763
 764 (define_insn "*tmdi_reg"
 765   [(set (reg CC_REGNUM)
 766         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
 767                          (match_operand:DI 1 "immediate_operand"
 768                                              "N0HD0,N1HD0,N2HD0,N3HD0"))
 769                  (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
 770   "TARGET_ZARCH
 771    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 772    && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
 773   "@
 774    tmhh\t%0,%i1
 775    tmhl\t%0,%i1
 776    tmlh\t%0,%i1
 777    tmll\t%0,%i1"
 778   [(set_attr "op_type" "RI")
 779    (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 780
 781 (define_insn "*tmsi_reg"
 782   [(set (reg CC_REGNUM)
 783         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
 784                          (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
 785                  (match_operand:SI 2 "immediate_operand" "n,n")))]
 786   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 787    && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
 788   "@
 789    tmh\t%0,%i1
 790    tml\t%0,%i1"
 791   [(set_attr "op_type" "RI")
 792    (set_attr "z10prop" "z10_super,z10_super")])
 793
 794 (define_insn "*tm<mode>_full"
 795   [(set (reg CC_REGNUM)
 796         (compare (match_operand:HQI 0 "register_operand" "d")
 797                  (match_operand:HQI 1 "immediate_operand" "n")))]
 798   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
 799   "tml\t%0,<max_uint>"
 800   [(set_attr "op_type" "RI")
 801    (set_attr "z10prop" "z10_super")])
 802
 803
 804 ;
 805 ; Load-and-Test instructions
 806 ;
 807
 808 ; tst(di|si) instruction pattern(s).
 809
 810 (define_insn "*tstdi_sign"
 811   [(set (reg CC_REGNUM)
 812         (compare
 813           (ashiftrt:DI
 814             (ashift:DI
 815               (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
 816               (const_int 32)) (const_int 32))
 817           (match_operand:DI 1 "const0_operand" "")))
 818    (set (match_operand:DI 2 "register_operand" "=d,d")
 819         (sign_extend:DI (match_dup 0)))]
 820   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
 821   "ltgfr\t%2,%0
 822    ltgf\t%2,%0"
 823   [(set_attr "op_type"      "RRE,RXY")
 824    (set_attr "cpu_facility" "*,z10")
 825    (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 826
 827 ; ltr, lt, ltgr, ltg
 828 (define_insn "*tst<mode>_extimm"
 829   [(set (reg CC_REGNUM)
 830         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 831                  (match_operand:GPR 1 "const0_operand" "")))
 832    (set (match_operand:GPR 2 "register_operand" "=d,d")
 833         (match_dup 0))]
 834   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 835   "@
 836    lt<g>r\t%2,%0
 837    lt<g>\t%2,%0"
 838   [(set_attr "op_type" "RR<E>,RXY")
 839    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 840
 841 ; ltr, lt, ltgr, ltg
 842 (define_insn "*tst<mode>_cconly_extimm"
 843   [(set (reg CC_REGNUM)
 844         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 845                  (match_operand:GPR 1 "const0_operand" "")))
 846    (clobber (match_scratch:GPR 2 "=X,d"))]
 847   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 848   "@
 849    lt<g>r\t%0,%0
 850    lt<g>\t%2,%0"
 851   [(set_attr "op_type" "RR<E>,RXY")
 852    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 853
 854 (define_insn "*tstdi"
 855   [(set (reg CC_REGNUM)
 856         (compare (match_operand:DI 0 "register_operand" "d")
 857                  (match_operand:DI 1 "const0_operand" "")))
 858    (set (match_operand:DI 2 "register_operand" "=d")
 859         (match_dup 0))]
 860   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
 861   "ltgr\t%2,%0"
 862   [(set_attr "op_type" "RRE")
 863    (set_attr "z10prop" "z10_fr_E1")])
 864
 865 (define_insn "*tstsi"
 866   [(set (reg CC_REGNUM)
 867         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 868                  (match_operand:SI 1 "const0_operand" "")))
 869    (set (match_operand:SI 2 "register_operand" "=d,d,d")
 870         (match_dup 0))]
 871   "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
 872   "@
 873    ltr\t%2,%0
 874    icm\t%2,15,%S0
 875    icmy\t%2,15,%S0"
 876   [(set_attr "op_type" "RR,RS,RSY")
 877    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 878
 879 (define_insn "*tstsi_cconly"
 880   [(set (reg CC_REGNUM)
 881         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 882                  (match_operand:SI 1 "const0_operand" "")))
 883    (clobber (match_scratch:SI 2 "=X,d,d"))]
 884   "s390_match_ccmode(insn, CCSmode)"
 885   "@
 886    ltr\t%0,%0
 887    icm\t%2,15,%S0
 888    icmy\t%2,15,%S0"
 889   [(set_attr "op_type" "RR,RS,RSY")
 890    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 891
 892 (define_insn "*tstdi_cconly_31"
 893   [(set (reg CC_REGNUM)
 894         (compare (match_operand:DI 0 "register_operand" "d")
 895                  (match_operand:DI 1 "const0_operand" "")))]
 896   "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
 897   "srda\t%0,0"
 898   [(set_attr "op_type" "RS")
 899    (set_attr "atype"   "reg")])
 900
 901 ; ltr, ltgr
 902 (define_insn "*tst<mode>_cconly2"
 903   [(set (reg CC_REGNUM)
 904         (compare (match_operand:GPR 0 "register_operand" "d")
 905                  (match_operand:GPR 1 "const0_operand" "")))]
 906   "s390_match_ccmode(insn, CCSmode)"
 907   "lt<g>r\t%0,%0"
 908   [(set_attr "op_type" "RR<E>")
 909    (set_attr "z10prop" "z10_fr_E1")])
 910
 911 ; tst(hi|qi) instruction pattern(s).
 912
 913 (define_insn "*tst<mode>CCT"
 914   [(set (reg CC_REGNUM)
 915         (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
 916                  (match_operand:HQI 1 "const0_operand" "")))
 917    (set (match_operand:HQI 2 "register_operand" "=d,d,0")
 918         (match_dup 0))]
 919   "s390_match_ccmode(insn, CCTmode)"
 920   "@
 921    icm\t%2,<icm_lo>,%S0
 922    icmy\t%2,<icm_lo>,%S0
 923    tml\t%0,<max_uint>"
 924   [(set_attr "op_type" "RS,RSY,RI")
 925    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 926
 927 (define_insn "*tsthiCCT_cconly"
 928   [(set (reg CC_REGNUM)
 929         (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
 930                  (match_operand:HI 1 "const0_operand" "")))
 931    (clobber (match_scratch:HI 2 "=d,d,X"))]
 932   "s390_match_ccmode(insn, CCTmode)"
 933   "@
 934    icm\t%2,3,%S0
 935    icmy\t%2,3,%S0
 936    tml\t%0,65535"
 937   [(set_attr "op_type" "RS,RSY,RI")
 938    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 939
 940 (define_insn "*tstqiCCT_cconly"
 941   [(set (reg CC_REGNUM)
 942         (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
 943                  (match_operand:QI 1 "const0_operand" "")))]
 944   "s390_match_ccmode(insn, CCTmode)"
 945   "@
 946    cli\t%S0,0
 947    cliy\t%S0,0
 948    tml\t%0,255"
 949   [(set_attr "op_type" "SI,SIY,RI")
 950    (set_attr "z10prop" "z10_super,z10_super,z10_super")])
 951
 952 (define_insn "*tst<mode>"
 953   [(set (reg CC_REGNUM)
 954         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 955                  (match_operand:HQI 1 "const0_operand" "")))
 956    (set (match_operand:HQI 2 "register_operand" "=d,d")
 957         (match_dup 0))]
 958   "s390_match_ccmode(insn, CCSmode)"
 959   "@
 960    icm\t%2,<icm_lo>,%S0
 961    icmy\t%2,<icm_lo>,%S0"
 962   [(set_attr "op_type" "RS,RSY")
 963    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 964
 965 (define_insn "*tst<mode>_cconly"
 966   [(set (reg CC_REGNUM)
 967         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 968                  (match_operand:HQI 1 "const0_operand" "")))
 969    (clobber (match_scratch:HQI 2 "=d,d"))]
 970   "s390_match_ccmode(insn, CCSmode)"
 971   "@
 972    icm\t%2,<icm_lo>,%S0
 973    icmy\t%2,<icm_lo>,%S0"
 974   [(set_attr "op_type" "RS,RSY")
 975    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 976
 977
 978 ; Compare (equality) instructions
 979
 980 (define_insn "*cmpdi_cct"
 981   [(set (reg CC_REGNUM)
 982         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
 983                  (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
 984   "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
 985   "@
 986    cgr\t%0,%1
 987    cghi\t%0,%h1
 988    cgfi\t%0,%1
 989    cg\t%0,%1
 990    #"
 991   [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
 992    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
 993
 994 (define_insn "*cmpsi_cct"
 995   [(set (reg CC_REGNUM)
 996         (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
 997                  (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
 998   "s390_match_ccmode (insn, CCTmode)"
 999   "@
1000    cr\t%0,%1
1001    chi\t%0,%h1
1002    cfi\t%0,%1
1003    c\t%0,%1
1004    cy\t%0,%1
1005    #"
1006   [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1007    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1008
1009 ; Compare (signed) instructions
1010
1011 (define_insn "*cmpdi_ccs_sign"
1012   [(set (reg CC_REGNUM)
1013         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1014                                                      "d,RT,b"))
1015                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1016   "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1017   "@
1018    cgfr\t%0,%1
1019    cgf\t%0,%1
1020    cgfrl\t%0,%1"
1021   [(set_attr "op_type"      "RRE,RXY,RIL")
1022    (set_attr "z10prop" "z10_c,*,*")
1023    (set_attr "type"         "*,*,larl")])
1024
1025
1026
1027 (define_insn "*cmpsi_ccs_sign"
1028   [(set (reg CC_REGNUM)
1029         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1030                  (match_operand:SI 0 "register_operand" "d,d,d")))]
1031   "s390_match_ccmode(insn, CCSRmode)"
1032   "@
1033    ch\t%0,%1
1034    chy\t%0,%1
1035    chrl\t%0,%1"
1036   [(set_attr "op_type"      "RX,RXY,RIL")
1037    (set_attr "cpu_facility" "*,*,z10")
1038    (set_attr "type"         "*,*,larl")
1039    (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1040
1041 (define_insn "*cmphi_ccs_z10"
1042   [(set (reg CC_REGNUM)
1043         (compare (match_operand:HI 0 "s_operand"         "Q")
1044                  (match_operand:HI 1 "immediate_operand" "K")))]
1045   "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1046   "chhsi\t%0,%1"
1047   [(set_attr "op_type" "SIL")
1048    (set_attr "z196prop" "z196_cracked")])
1049
1050 (define_insn "*cmpdi_ccs_signhi_rl"
1051   [(set (reg CC_REGNUM)
1052         (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
1053                  (match_operand:GPR 0 "register_operand"  "d,d")))]
1054   "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1055   "@
1056    cgh\t%0,%1
1057    cghrl\t%0,%1"
1058   [(set_attr "op_type" "RXY,RIL")
1059    (set_attr "type"    "*,larl")])
1060
1061 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1062 (define_insn "*cmp<mode>_ccs"
1063   [(set (reg CC_REGNUM)
1064         (compare (match_operand:GPR 0 "nonimmediate_operand"
1065                                       "d,d,Q, d,d,d,d")
1066                  (match_operand:GPR 1 "general_operand"
1067                                       "d,K,K,Os,R,T,b")))]
1068   "s390_match_ccmode(insn, CCSmode)"
1069   "@
1070    c<g>r\t%0,%1
1071    c<g>hi\t%0,%h1
1072    c<g>hsi\t%0,%h1
1073    c<g>fi\t%0,%1
1074    c<g>\t%0,%1
1075    c<y>\t%0,%1
1076    c<g>rl\t%0,%1"
1077   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1078    (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
1079    (set_attr "type" "*,*,*,*,*,*,larl")
1080    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1081
1082
1083 ; Compare (unsigned) instructions
1084
1085 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1086   [(set (reg CC_REGNUM)
1087         (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1088                                           "larl_operand" "X")))
1089                  (match_operand:SI 0 "register_operand" "d")))]
1090   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1091   "clhrl\t%0,%1"
1092   [(set_attr "op_type" "RIL")
1093    (set_attr "type"    "larl")
1094    (set_attr "z10prop" "z10_super")])
1095
1096 ; clhrl, clghrl
1097 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1098   [(set (reg CC_REGNUM)
1099         (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1100                                           "larl_operand" "X")))
1101                  (match_operand:GPR 0 "register_operand" "d")))]
1102   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1103   "cl<g>hrl\t%0,%1"
1104   [(set_attr "op_type" "RIL")
1105    (set_attr "type"    "larl")
1106    (set_attr "z10prop" "z10_super")])
1107
1108 (define_insn "*cmpdi_ccu_zero"
1109   [(set (reg CC_REGNUM)
1110         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1111                                                         "d,RT,b"))
1112                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1113   "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1114   "@
1115    clgfr\t%0,%1
1116    clgf\t%0,%1
1117    clgfrl\t%0,%1"
1118   [(set_attr "op_type"      "RRE,RXY,RIL")
1119    (set_attr "cpu_facility" "*,*,z10")
1120    (set_attr "type"         "*,*,larl")
1121    (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1122
1123 (define_insn "*cmpdi_ccu"
1124   [(set (reg CC_REGNUM)
1125         (compare (match_operand:DI 0 "nonimmediate_operand"
1126                                      "d, d,d,Q, d, Q,BQ")
1127                  (match_operand:DI 1 "general_operand"
1128                                      "d,Op,b,D,RT,BQ,Q")))]
1129   "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1130   "@
1131    clgr\t%0,%1
1132    clgfi\t%0,%1
1133    clgrl\t%0,%1
1134    clghsi\t%0,%x1
1135    clg\t%0,%1
1136    #
1137    #"
1138   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1139    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1140    (set_attr "type"         "*,*,larl,*,*,*,*")
1141    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1142
1143 (define_insn "*cmpsi_ccu"
1144   [(set (reg CC_REGNUM)
1145         (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1146                  (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
1147   "s390_match_ccmode (insn, CCUmode)"
1148   "@
1149    clr\t%0,%1
1150    clfi\t%0,%o1
1151    clrl\t%0,%1
1152    clfhsi\t%0,%x1
1153    cl\t%0,%1
1154    cly\t%0,%1
1155    #
1156    #"
1157   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1158    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1159    (set_attr "type"         "*,*,larl,*,*,*,*,*")
1160    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1161
1162 (define_insn "*cmphi_ccu"
1163   [(set (reg CC_REGNUM)
1164         (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1165                  (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
1166   "s390_match_ccmode (insn, CCUmode)
1167    && !register_operand (operands[1], HImode)"
1168   "@
1169    clm\t%0,3,%S1
1170    clmy\t%0,3,%S1
1171    clhhsi\t%0,%1
1172    #
1173    #"
1174   [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1175    (set_attr "cpu_facility" "*,*,z10,*,*")
1176    (set_attr "z10prop" "*,*,z10_super,*,*")])
1177
1178 (define_insn "*cmpqi_ccu"
1179   [(set (reg CC_REGNUM)
1180         (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1181                  (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1182   "s390_match_ccmode (insn, CCUmode)
1183    && !register_operand (operands[1], QImode)"
1184   "@
1185    clm\t%0,1,%S1
1186    clmy\t%0,1,%S1
1187    cli\t%S0,%b1
1188    cliy\t%S0,%b1
1189    #
1190    #"
1191   [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1192    (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1193
1194
1195 ; Block compare (CLC) instruction patterns.
1196
1197 (define_insn "*clc"
1198   [(set (reg CC_REGNUM)
1199         (compare (match_operand:BLK 0 "memory_operand" "Q")
1200                  (match_operand:BLK 1 "memory_operand" "Q")))
1201    (use (match_operand 2 "const_int_operand" "n"))]
1202   "s390_match_ccmode (insn, CCUmode)
1203    && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1204   "clc\t%O0(%2,%R0),%S1"
1205   [(set_attr "op_type" "SS")])
1206
1207 (define_split
1208   [(set (reg CC_REGNUM)
1209         (compare (match_operand 0 "memory_operand" "")
1210                  (match_operand 1 "memory_operand" "")))]
1211   "reload_completed
1212    && s390_match_ccmode (insn, CCUmode)
1213    && GET_MODE (operands[0]) == GET_MODE (operands[1])
1214    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1215   [(parallel
1216     [(set (match_dup 0) (match_dup 1))
1217      (use (match_dup 2))])]
1218 {
1219   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1220   operands[0] = adjust_address (operands[0], BLKmode, 0);
1221   operands[1] = adjust_address (operands[1], BLKmode, 0);
1222
1223   operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1224                                  operands[0], operands[1]);
1225   operands[0] = SET_DEST (PATTERN (curr_insn));
1226 })
1227
1228
1229 ; (TF|DF|SF|TD|DD|SD) instructions
1230
1231 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1232 (define_insn "*cmp<mode>_ccs_0"
1233   [(set (reg CC_REGNUM)
1234         (compare (match_operand:FP 0 "register_operand" "f")
1235                  (match_operand:FP 1 "const0_operand"   "")))]
1236   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1237   "lt<xde><bt>r\t%0,%0"
1238    [(set_attr "op_type" "RRE")
1239     (set_attr "type"  "fsimp<mode>")])
1240
1241 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1242 (define_insn "*cmp<mode>_ccs"
1243   [(set (reg CC_REGNUM)
1244         (compare (match_operand:FP 0 "register_operand" "f,f")
1245                  (match_operand:FP 1 "general_operand"  "f,<Rf>")))]
1246   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1247   "@
1248    c<xde><bt>r\t%0,%1
1249    c<xde>b\t%0,%1"
1250    [(set_attr "op_type" "RRE,RXE")
1251     (set_attr "type"  "fsimp<mode>")])
1252
1253 ; wfcedbs, wfchdbs, wfchedbs
1254 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1255   [(set (reg:VFCMP CC_REGNUM)
1256         (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1257                        (match_operand:DF 1 "register_operand" "v")))
1258    (clobber (match_scratch:V2DI 2 "=v"))]
1259   "TARGET_Z13 && TARGET_HARD_FLOAT"
1260   "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1261   [(set_attr "op_type" "VRR")])
1262
1263 ; Compare and Branch instructions
1264
1265 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1266 ; The following instructions do a complementary access of their second
1267 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1268 (define_insn "*cmp_and_br_signed_<mode>"
1269   [(set (pc)
1270         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1271                         [(match_operand:GPR 1 "register_operand"  "d,d")
1272                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1273                       (label_ref (match_operand 3 "" ""))
1274                       (pc)))
1275    (clobber (reg:CC CC_REGNUM))]
1276   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1277 {
1278   if (get_attr_length (insn) == 6)
1279     return which_alternative ?
1280       "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1281   else
1282     return which_alternative ?
1283       "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1284 }
1285   [(set_attr "op_type" "RIE")
1286    (set_attr "type"    "branch")
1287    (set_attr "z10prop" "z10_super_c,z10_super")
1288    (set (attr "length")
1289         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1290                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1291                                                        ; 10 byte for cgr/jg
1292
1293 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1294 ; The following instructions do a complementary access of their second
1295 ; operand (z10 only): clrj, clgrj, clr, clgr
1296 (define_insn "*cmp_and_br_unsigned_<mode>"
1297   [(set (pc)
1298         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1299                         [(match_operand:GPR 1 "register_operand"  "d,d")
1300                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1301                       (label_ref (match_operand 3 "" ""))
1302                       (pc)))
1303    (clobber (reg:CC CC_REGNUM))]
1304   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1305 {
1306   if (get_attr_length (insn) == 6)
1307     return which_alternative ?
1308       "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1309   else
1310     return which_alternative ?
1311       "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1312 }
1313   [(set_attr "op_type" "RIE")
1314    (set_attr "type"    "branch")
1315    (set_attr "z10prop" "z10_super_c,z10_super")
1316    (set (attr "length")
1317         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1318                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1319                                                        ; 10 byte for clgr/jg
1320
1321 ; And now the same two patterns as above but with a negated CC mask.
1322
1323 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1324 ; The following instructions do a complementary access of their second
1325 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1326 (define_insn "*icmp_and_br_signed_<mode>"
1327   [(set (pc)
1328         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1329                         [(match_operand:GPR 1 "register_operand"  "d,d")
1330                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1331                       (pc)
1332                       (label_ref (match_operand 3 "" ""))))
1333    (clobber (reg:CC CC_REGNUM))]
1334   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1335 {
1336   if (get_attr_length (insn) == 6)
1337     return which_alternative ?
1338       "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1339   else
1340     return which_alternative ?
1341       "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1342 }
1343   [(set_attr "op_type" "RIE")
1344    (set_attr "type"    "branch")
1345    (set_attr "z10prop" "z10_super_c,z10_super")
1346    (set (attr "length")
1347         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1348                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1349                                                        ; 10 byte for cgr/jg
1350
1351 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1352 ; The following instructions do a complementary access of their second
1353 ; operand (z10 only): clrj, clgrj, clr, clgr
1354 (define_insn "*icmp_and_br_unsigned_<mode>"
1355   [(set (pc)
1356         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1357                         [(match_operand:GPR 1 "register_operand"  "d,d")
1358                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1359                       (pc)
1360                       (label_ref (match_operand 3 "" ""))))
1361    (clobber (reg:CC CC_REGNUM))]
1362   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1363 {
1364   if (get_attr_length (insn) == 6)
1365     return which_alternative ?
1366       "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1367   else
1368     return which_alternative ?
1369       "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1370 }
1371   [(set_attr "op_type" "RIE")
1372    (set_attr "type"    "branch")
1373    (set_attr "z10prop" "z10_super_c,z10_super")
1374    (set (attr "length")
1375         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1376                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1377                                                        ; 10 byte for clgr/jg
1378
1379 ;;
1380 ;;- Move instructions.
1381 ;;
1382
1383 ;
1384 ; movti instruction pattern(s).
1385 ;
1386
1387 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1388 ; for TImode (use double-int for the calculations)
1389 (define_insn "movti"
1390   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v,  v,  v,v,d, v,QR,   d,o")
1391         (match_operand:TI 1 "general_operand"      "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1392   "TARGET_ZARCH"
1393   "@
1394    lmg\t%0,%N0,%S1
1395    stmg\t%1,%N1,%S0
1396    vlr\t%v0,%v1
1397    vzero\t%v0
1398    vone\t%v0
1399    vlvgp\t%v0,%1,%N1
1400    #
1401    vl\t%v0,%1
1402    vst\t%v1,%0
1403    #
1404    #"
1405   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1406    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1407    (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1408
1409 (define_split
1410   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1411         (match_operand:TI 1 "general_operand" ""))]
1412   "TARGET_ZARCH && reload_completed
1413    && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1414   [(set (match_dup 2) (match_dup 4))
1415    (set (match_dup 3) (match_dup 5))]
1416 {
1417   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1418   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1419   operands[4] = operand_subword (operands[1], 0, 0, TImode);
1420   operands[5] = operand_subword (operands[1], 1, 0, TImode);
1421 })
1422
1423 (define_split
1424   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1425         (match_operand:TI 1 "general_operand" ""))]
1426   "TARGET_ZARCH && reload_completed
1427    && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1428   [(set (match_dup 2) (match_dup 4))
1429    (set (match_dup 3) (match_dup 5))]
1430 {
1431   operands[2] = operand_subword (operands[0], 1, 0, TImode);
1432   operands[3] = operand_subword (operands[0], 0, 0, TImode);
1433   operands[4] = operand_subword (operands[1], 1, 0, TImode);
1434   operands[5] = operand_subword (operands[1], 0, 0, TImode);
1435 })
1436
1437 ; Use part of the TImode target reg to perform the address
1438 ; calculation.  If the TImode value is supposed to be copied into a VR
1439 ; this splitter is not necessary.
1440 (define_split
1441   [(set (match_operand:TI 0 "register_operand" "")
1442         (match_operand:TI 1 "memory_operand" ""))]
1443   "TARGET_ZARCH && reload_completed
1444    && !VECTOR_REG_P (operands[0])
1445    && !s_operand (operands[1], VOIDmode)"
1446   [(set (match_dup 0) (match_dup 1))]
1447 {
1448   rtx addr = operand_subword (operands[0], 1, 0, TImode);
1449   addr = gen_lowpart (Pmode, addr);
1450   s390_load_address (addr, XEXP (operands[1], 0));
1451   operands[1] = replace_equiv_address (operands[1], addr);
1452 })
1453
1454
1455 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1456 ; For the higher order bits we do simply a DImode move while the
1457 ; second part is done via vec extract.  Both will end up as vlgvg.
1458 (define_split
1459   [(set (match_operand:TI 0 "register_operand" "")
1460         (match_operand:TI 1 "register_operand" ""))]
1461   "TARGET_VX && reload_completed
1462    && GENERAL_REG_P (operands[0])
1463    && VECTOR_REG_P (operands[1])"
1464   [(set (match_dup 2) (match_dup 4))
1465    (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1466                                  UNSPEC_VEC_EXTRACT))]
1467 {
1468   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1469   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1470   operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1471   operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1472 })
1473
1474 ;
1475 ; Patterns used for secondary reloads
1476 ;
1477
1478 ; z10 provides move instructions accepting larl memory operands.
1479 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1480 ; These patterns are also used for unaligned SI and DI accesses.
1481
1482 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1483   [(parallel [(match_operand:ALL 0 "memory_operand"   "")
1484               (match_operand:ALL 1 "register_operand" "=d")
1485               (match_operand:P   2 "register_operand" "=&a")])]
1486   "TARGET_Z10"
1487 {
1488   s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1489   DONE;
1490 })
1491
1492 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1493   [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1494               (match_operand:ALL 1 "memory_operand"   "")
1495               (match_operand:P   2 "register_operand" "=a")])]
1496   "TARGET_Z10"
1497 {
1498   s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1499   DONE;
1500 })
1501
1502 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1503   [(parallel [(match_operand:P 0 "register_operand" "=d")
1504               (match_operand:P 1 "larl_operand"     "")
1505               (match_operand:P 2 "register_operand" "=a")])]
1506   "TARGET_Z10"
1507 {
1508   s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1509   DONE;
1510 })
1511
1512 ; Handles loading a PLUS (load address) expression
1513
1514 (define_expand "reload<mode>_plus"
1515   [(parallel [(match_operand:P 0 "register_operand"  "=a")
1516               (match_operand:P 1 "s390_plus_operand" "")
1517               (match_operand:P 2 "register_operand"  "=&a")])]
1518   ""
1519 {
1520   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1521   DONE;
1522 })
1523
1524 ; Not all the indirect memory access instructions support the full
1525 ; format (long disp + index + base).  So whenever a move from/to such
1526 ; an address is required and the instruction cannot deal with it we do
1527 ; a load address into a scratch register first and use this as the new
1528 ; base register.
1529 ; This in particular is used for:
1530 ; - non-offsetable memory accesses for multiword moves
1531 ; - full vector reg moves with long displacements
1532
1533 (define_expand "reload<mode>_la_in"
1534   [(parallel [(match_operand 0   "register_operand" "")
1535               (match_operand 1   "" "")
1536               (match_operand:P 2 "register_operand" "=&a")])]
1537   ""
1538 {
1539   gcc_assert (MEM_P (operands[1]));
1540   s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1541   operands[1] = replace_equiv_address (operands[1], operands[2]);
1542   emit_move_insn (operands[0], operands[1]);
1543   DONE;
1544 })
1545
1546 (define_expand "reload<mode>_la_out"
1547   [(parallel [(match_operand   0 "" "")
1548               (match_operand   1 "register_operand" "")
1549               (match_operand:P 2 "register_operand" "=&a")])]
1550   ""
1551 {
1552   gcc_assert (MEM_P (operands[0]));
1553   s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1554   operands[0] = replace_equiv_address (operands[0], operands[2]);
1555   emit_move_insn (operands[0], operands[1]);
1556   DONE;
1557 })
1558
1559 (define_expand "reload<mode>_PIC_addr"
1560   [(parallel [(match_operand   0 "register_operand" "=d")
1561               (match_operand   1 "larl_operand"     "")
1562               (match_operand:P 2 "register_operand" "=a")])]
1563   ""
1564 {
1565   rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1566   emit_move_insn (operands[0], new_rtx);
1567 })
1568
1569 ;
1570 ; movdi instruction pattern(s).
1571 ;
1572
1573 (define_expand "movdi"
1574   [(set (match_operand:DI 0 "general_operand" "")
1575         (match_operand:DI 1 "general_operand" ""))]
1576   ""
1577 {
1578   /* Handle symbolic constants.  */
1579   if (TARGET_64BIT
1580       && (SYMBOLIC_CONST (operands[1])
1581           || (GET_CODE (operands[1]) == PLUS
1582               && XEXP (operands[1], 0) == pic_offset_table_rtx
1583               && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1584     emit_symbolic_move (operands);
1585 })
1586
1587 (define_insn "*movdi_larl"
1588   [(set (match_operand:DI 0 "register_operand" "=d")
1589         (match_operand:DI 1 "larl_operand" "X"))]
1590   "TARGET_64BIT
1591    && !FP_REG_P (operands[0])"
1592   "larl\t%0,%1"
1593    [(set_attr "op_type" "RIL")
1594     (set_attr "type"    "larl")
1595     (set_attr "z10prop" "z10_super_A1")])
1596
1597 (define_insn "*movdi_64"
1598   [(set (match_operand:DI 0 "nonimmediate_operand"
1599          "=d,    d,    d,    d,    d, d,    d,    d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1600         (match_operand:DI 1 "general_operand"
1601          " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f,  R,  T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1602   "TARGET_ZARCH"
1603   "@
1604    lghi\t%0,%h1
1605    llihh\t%0,%i1
1606    llihl\t%0,%i1
1607    llilh\t%0,%i1
1608    llill\t%0,%i1
1609    lgfi\t%0,%1
1610    llihf\t%0,%k1
1611    llilf\t%0,%k1
1612    ldgr\t%0,%1
1613    lgdr\t%0,%1
1614    lay\t%0,%a1
1615    lgrl\t%0,%1
1616    lgr\t%0,%1
1617    lg\t%0,%1
1618    stg\t%1,%0
1619    ldr\t%0,%1
1620    ld\t%0,%1
1621    ldy\t%0,%1
1622    std\t%1,%0
1623    stdy\t%1,%0
1624    stgrl\t%1,%0
1625    mvghi\t%0,%1
1626    #
1627    #
1628    stam\t%1,%N1,%S0
1629    lam\t%0,%N0,%S1
1630    vleig\t%v0,%h1,0
1631    vlr\t%v0,%v1
1632    vlvgg\t%v0,%1,0
1633    vlgvg\t%0,%v1,0
1634    vleg\t%v0,%1,0
1635    vsteg\t%v1,%0,0"
1636   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1637                         RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1638    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1639                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1640                      *,*,*,*,*,*,*")
1641    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1642                              z10,*,*,*,*,*,longdisp,*,longdisp,
1643                              z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1644    (set_attr "z10prop" "z10_fwd_A1,
1645                         z10_fwd_E1,
1646                         z10_fwd_E1,
1647                         z10_fwd_E1,
1648                         z10_fwd_E1,
1649                         z10_fwd_A1,
1650                         z10_fwd_E1,
1651                         z10_fwd_E1,
1652                         *,
1653                         *,
1654                         z10_fwd_A1,
1655                         z10_fwd_A3,
1656                         z10_fr_E1,
1657                         z10_fwd_A3,
1658                         z10_rec,
1659                         *,
1660                         *,
1661                         *,
1662                         *,
1663                         *,
1664                         z10_rec,
1665                         z10_super,
1666                         *,
1667                         *,
1668                         *,
1669                         *,*,*,*,*,*,*")
1670 ])
1671
1672 (define_split
1673   [(set (match_operand:DI 0 "register_operand" "")
1674         (match_operand:DI 1 "register_operand" ""))]
1675   "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1676   [(set (match_dup 2) (match_dup 3))
1677    (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1678    (set (strict_low_part (match_dup 2)) (match_dup 4))]
1679   "operands[2] = gen_lowpart (SImode, operands[0]);
1680    s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1681
1682 (define_split
1683   [(set (match_operand:DI 0 "register_operand" "")
1684         (match_operand:DI 1 "register_operand" ""))]
1685   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1686    && dead_or_set_p (insn, operands[1])"
1687   [(set (match_dup 3) (match_dup 2))
1688    (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1689    (set (match_dup 4) (match_dup 2))]
1690   "operands[2] = gen_lowpart (SImode, operands[1]);
1691    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1692
1693 (define_split
1694   [(set (match_operand:DI 0 "register_operand" "")
1695         (match_operand:DI 1 "register_operand" ""))]
1696   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1697    && !dead_or_set_p (insn, operands[1])"
1698   [(set (match_dup 3) (match_dup 2))
1699    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1700    (set (match_dup 4) (match_dup 2))
1701    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1702   "operands[2] = gen_lowpart (SImode, operands[1]);
1703    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1704
1705 (define_insn "*movdi_31"
1706   [(set (match_operand:DI 0 "nonimmediate_operand"
1707                             "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,d")
1708         (match_operand:DI 1 "general_operand"
1709                             " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,b"))]
1710   "!TARGET_ZARCH"
1711   "@
1712    lm\t%0,%N0,%S1
1713    lmy\t%0,%N0,%S1
1714    stm\t%1,%N1,%S0
1715    stmy\t%1,%N1,%S0
1716    #
1717    #
1718    ldr\t%0,%1
1719    ld\t%0,%1
1720    ldy\t%0,%1
1721    std\t%1,%0
1722    stdy\t%1,%0
1723    #"
1724   [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1725    (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1726    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1727
1728 ; For a load from a symbol ref we can use one of the target registers
1729 ; together with larl to load the address.
1730 (define_split
1731   [(set (match_operand:DI 0 "register_operand" "")
1732         (match_operand:DI 1 "memory_operand" ""))]
1733   "!TARGET_ZARCH && reload_completed && TARGET_Z10
1734    && larl_operand (XEXP (operands[1], 0), SImode)"
1735   [(set (match_dup 2) (match_dup 3))
1736    (set (match_dup 0) (match_dup 1))]
1737 {
1738   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1739   operands[3] = XEXP (operands[1], 0);
1740   operands[1] = replace_equiv_address (operands[1], operands[2]);
1741 })
1742
1743 (define_split
1744   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1745         (match_operand:DI 1 "general_operand" ""))]
1746   "!TARGET_ZARCH && reload_completed
1747    && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1748   [(set (match_dup 2) (match_dup 4))
1749    (set (match_dup 3) (match_dup 5))]
1750 {
1751   operands[2] = operand_subword (operands[0], 0, 0, DImode);
1752   operands[3] = operand_subword (operands[0], 1, 0, DImode);
1753   operands[4] = operand_subword (operands[1], 0, 0, DImode);
1754   operands[5] = operand_subword (operands[1], 1, 0, DImode);
1755 })
1756
1757 (define_split
1758   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1759         (match_operand:DI 1 "general_operand" ""))]
1760   "!TARGET_ZARCH && reload_completed
1761    && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1762   [(set (match_dup 2) (match_dup 4))
1763    (set (match_dup 3) (match_dup 5))]
1764 {
1765   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1766   operands[3] = operand_subword (operands[0], 0, 0, DImode);
1767   operands[4] = operand_subword (operands[1], 1, 0, DImode);
1768   operands[5] = operand_subword (operands[1], 0, 0, DImode);
1769 })
1770
1771 (define_split
1772   [(set (match_operand:DI 0 "register_operand" "")
1773         (match_operand:DI 1 "memory_operand" ""))]
1774   "!TARGET_ZARCH && reload_completed
1775    && !FP_REG_P (operands[0])
1776    && !s_operand (operands[1], VOIDmode)"
1777   [(set (match_dup 0) (match_dup 1))]
1778 {
1779   rtx addr = operand_subword (operands[0], 1, 0, DImode);
1780   s390_load_address (addr, XEXP (operands[1], 0));
1781   operands[1] = replace_equiv_address (operands[1], addr);
1782 })
1783
1784 (define_peephole2
1785   [(set (match_operand:DI 0 "register_operand" "")
1786         (mem:DI (match_operand 1 "address_operand" "")))]
1787   "TARGET_ZARCH
1788    && !FP_REG_P (operands[0])
1789    && GET_CODE (operands[1]) == SYMBOL_REF
1790    && CONSTANT_POOL_ADDRESS_P (operands[1])
1791    && get_pool_mode (operands[1]) == DImode
1792    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1793   [(set (match_dup 0) (match_dup 2))]
1794   "operands[2] = get_pool_constant (operands[1]);")
1795
1796 (define_insn "*la_64"
1797   [(set (match_operand:DI 0 "register_operand" "=d,d")
1798         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1799   "TARGET_64BIT"
1800   "@
1801    la\t%0,%a1
1802    lay\t%0,%a1"
1803   [(set_attr "op_type" "RX,RXY")
1804    (set_attr "type"    "la")
1805    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1806
1807 (define_peephole2
1808   [(parallel
1809     [(set (match_operand:DI 0 "register_operand" "")
1810           (match_operand:QI 1 "address_operand" ""))
1811      (clobber (reg:CC CC_REGNUM))])]
1812   "TARGET_64BIT
1813    && preferred_la_operand_p (operands[1], const0_rtx)"
1814   [(set (match_dup 0) (match_dup 1))]
1815   "")
1816
1817 (define_peephole2
1818   [(set (match_operand:DI 0 "register_operand" "")
1819         (match_operand:DI 1 "register_operand" ""))
1820    (parallel
1821     [(set (match_dup 0)
1822           (plus:DI (match_dup 0)
1823                    (match_operand:DI 2 "nonmemory_operand" "")))
1824      (clobber (reg:CC CC_REGNUM))])]
1825   "TARGET_64BIT
1826    && !reg_overlap_mentioned_p (operands[0], operands[2])
1827    && preferred_la_operand_p (operands[1], operands[2])"
1828   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1829   "")
1830
1831 ;
1832 ; movsi instruction pattern(s).
1833 ;
1834
1835 (define_expand "movsi"
1836   [(set (match_operand:SI 0 "general_operand" "")
1837         (match_operand:SI 1 "general_operand" ""))]
1838   ""
1839 {
1840   /* Handle symbolic constants.  */
1841   if (!TARGET_64BIT
1842       && (SYMBOLIC_CONST (operands[1])
1843           || (GET_CODE (operands[1]) == PLUS
1844               && XEXP (operands[1], 0) == pic_offset_table_rtx
1845               && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1846     emit_symbolic_move (operands);
1847 })
1848
1849 (define_insn "*movsi_larl"
1850   [(set (match_operand:SI 0 "register_operand" "=d")
1851         (match_operand:SI 1 "larl_operand" "X"))]
1852   "!TARGET_64BIT && TARGET_CPU_ZARCH
1853    && !FP_REG_P (operands[0])"
1854   "larl\t%0,%1"
1855    [(set_attr "op_type" "RIL")
1856     (set_attr "type"    "larl")
1857     (set_attr "z10prop" "z10_fwd_A1")])
1858
1859 (define_insn "*movsi_zarch"
1860   [(set (match_operand:SI 0 "nonimmediate_operand"
1861          "=d,    d,    d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1862         (match_operand:SI 1 "general_operand"
1863          " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f,  R,  R,  T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1864   "TARGET_ZARCH"
1865   "@
1866    lhi\t%0,%h1
1867    llilh\t%0,%i1
1868    llill\t%0,%i1
1869    iilf\t%0,%o1
1870    lay\t%0,%a1
1871    lrl\t%0,%1
1872    lr\t%0,%1
1873    l\t%0,%1
1874    ly\t%0,%1
1875    st\t%1,%0
1876    sty\t%1,%0
1877    lder\t%0,%1
1878    ler\t%0,%1
1879    lde\t%0,%1
1880    le\t%0,%1
1881    ley\t%0,%1
1882    ste\t%1,%0
1883    stey\t%1,%0
1884    ear\t%0,%1
1885    sar\t%0,%1
1886    stam\t%1,%1,%S0
1887    strl\t%1,%0
1888    mvhi\t%0,%1
1889    lam\t%0,%0,%S1
1890    vleif\t%v0,%h1,0
1891    vlr\t%v0,%v1
1892    vlvgf\t%v0,%1,0
1893    vlgvf\t%0,%v1,0
1894    vlef\t%v0,%1,0
1895    vstef\t%v1,%0,0"
1896   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1897                         RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1898    (set_attr "type" "*,
1899                      *,
1900                      *,
1901                      *,
1902                      la,
1903                      larl,
1904                      lr,
1905                      load,
1906                      load,
1907                      store,
1908                      store,
1909                      floadsf,
1910                      floadsf,
1911                      floadsf,
1912                      floadsf,
1913                      floadsf,
1914                      fstoresf,
1915                      fstoresf,
1916                      *,
1917                      *,
1918                      *,
1919                      larl,
1920                      *,
1921                      *,*,*,*,*,*,*")
1922    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1923                              vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1924    (set_attr "z10prop" "z10_fwd_A1,
1925                         z10_fwd_E1,
1926                         z10_fwd_E1,
1927                         z10_fwd_A1,
1928                         z10_fwd_A1,
1929                         z10_fwd_A3,
1930                         z10_fr_E1,
1931                         z10_fwd_A3,
1932                         z10_fwd_A3,
1933                         z10_rec,
1934                         z10_rec,
1935                         *,
1936                         *,
1937                         *,
1938                         *,
1939                         *,
1940                         *,
1941                         *,
1942                         z10_super_E1,
1943                         z10_super,
1944                         *,
1945                         z10_rec,
1946                         z10_super,
1947                         *,*,*,*,*,*,*")])
1948
1949 (define_insn "*movsi_esa"
1950   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1951         (match_operand:SI 1 "general_operand"       "K,d,R,d, *f, *f,  R,  R,*f,t,d,t,Q"))]
1952   "!TARGET_ZARCH"
1953   "@
1954    lhi\t%0,%h1
1955    lr\t%0,%1
1956    l\t%0,%1
1957    st\t%1,%0
1958    lder\t%0,%1
1959    ler\t%0,%1
1960    lde\t%0,%1
1961    le\t%0,%1
1962    ste\t%1,%0
1963    ear\t%0,%1
1964    sar\t%0,%1
1965    stam\t%1,%1,%S0
1966    lam\t%0,%0,%S1"
1967   [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1968    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1969    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1970                         z10_super,*,*")
1971    (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1972 ])
1973
1974 (define_peephole2
1975   [(set (match_operand:SI 0 "register_operand" "")
1976         (mem:SI (match_operand 1 "address_operand" "")))]
1977   "!FP_REG_P (operands[0])
1978    && GET_CODE (operands[1]) == SYMBOL_REF
1979    && CONSTANT_POOL_ADDRESS_P (operands[1])
1980    && get_pool_mode (operands[1]) == SImode
1981    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1982   [(set (match_dup 0) (match_dup 2))]
1983   "operands[2] = get_pool_constant (operands[1]);")
1984
1985 (define_insn "*la_31"
1986   [(set (match_operand:SI 0 "register_operand" "=d,d")
1987         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1988   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1989   "@
1990    la\t%0,%a1
1991    lay\t%0,%a1"
1992   [(set_attr "op_type"  "RX,RXY")
1993    (set_attr "type"     "la")
1994    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1995
1996 (define_peephole2
1997   [(parallel
1998     [(set (match_operand:SI 0 "register_operand" "")
1999           (match_operand:QI 1 "address_operand" ""))
2000      (clobber (reg:CC CC_REGNUM))])]
2001   "!TARGET_64BIT
2002    && preferred_la_operand_p (operands[1], const0_rtx)"
2003   [(set (match_dup 0) (match_dup 1))]
2004   "")
2005
2006 (define_peephole2
2007   [(set (match_operand:SI 0 "register_operand" "")
2008         (match_operand:SI 1 "register_operand" ""))
2009    (parallel
2010     [(set (match_dup 0)
2011           (plus:SI (match_dup 0)
2012                    (match_operand:SI 2 "nonmemory_operand" "")))
2013      (clobber (reg:CC CC_REGNUM))])]
2014   "!TARGET_64BIT
2015    && !reg_overlap_mentioned_p (operands[0], operands[2])
2016    && preferred_la_operand_p (operands[1], operands[2])"
2017   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2018   "")
2019
2020 (define_insn "*la_31_and"
2021   [(set (match_operand:SI 0 "register_operand" "=d,d")
2022         (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
2023                 (const_int 2147483647)))]
2024   "!TARGET_64BIT"
2025   "@
2026    la\t%0,%a1
2027    lay\t%0,%a1"
2028   [(set_attr "op_type"  "RX,RXY")
2029    (set_attr "type"     "la")
2030    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2031
2032 (define_insn_and_split "*la_31_and_cc"
2033   [(set (match_operand:SI 0 "register_operand" "=d")
2034         (and:SI (match_operand:QI 1 "address_operand" "p")
2035                 (const_int 2147483647)))
2036    (clobber (reg:CC CC_REGNUM))]
2037   "!TARGET_64BIT"
2038   "#"
2039   "&& reload_completed"
2040   [(set (match_dup 0)
2041         (and:SI (match_dup 1) (const_int 2147483647)))]
2042   ""
2043   [(set_attr "op_type"  "RX")
2044    (set_attr "type"     "la")])
2045
2046 (define_insn "force_la_31"
2047   [(set (match_operand:SI 0 "register_operand" "=d,d")
2048         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
2049    (use (const_int 0))]
2050   "!TARGET_64BIT"
2051   "@
2052    la\t%0,%a1
2053    lay\t%0,%a1"
2054   [(set_attr "op_type"  "RX")
2055    (set_attr "type"     "la")
2056    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2057
2058 ;
2059 ; movhi instruction pattern(s).
2060 ;
2061
2062 (define_expand "movhi"
2063   [(set (match_operand:HI 0 "nonimmediate_operand" "")
2064         (match_operand:HI 1 "general_operand" ""))]
2065   ""
2066 {
2067   /* Make it explicit that loading a register from memory
2068      always sign-extends (at least) to SImode.  */
2069   if (optimize && can_create_pseudo_p ()
2070       && register_operand (operands[0], VOIDmode)
2071       && GET_CODE (operands[1]) == MEM)
2072     {
2073       rtx tmp = gen_reg_rtx (SImode);
2074       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2075       emit_insn (gen_rtx_SET (tmp, ext));
2076       operands[1] = gen_lowpart (HImode, tmp);
2077     }
2078 })
2079
2080 (define_insn "*movhi"
2081   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
2082         (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
2083   ""
2084   "@
2085    lr\t%0,%1
2086    lhi\t%0,%h1
2087    lh\t%0,%1
2088    lhy\t%0,%1
2089    lhrl\t%0,%1
2090    sth\t%1,%0
2091    sthy\t%1,%0
2092    sthrl\t%1,%0
2093    mvhhi\t%0,%1
2094    vleih\t%v0,%h1,0
2095    vlr\t%v0,%v1
2096    vlvgh\t%v0,%1,0
2097    vlgvh\t%0,%v1,0
2098    vleh\t%v0,%1,0
2099    vsteh\t%v1,%0,0"
2100   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2101    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2102    (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
2103    (set_attr "z10prop" "z10_fr_E1,
2104                        z10_fwd_A1,
2105                        z10_super_E1,
2106                        z10_super_E1,
2107                        z10_super_E1,
2108                        z10_rec,
2109                        z10_rec,
2110                        z10_rec,
2111                        z10_super,*,*,*,*,*,*")])
2112
2113 (define_peephole2
2114   [(set (match_operand:HI 0 "register_operand" "")
2115         (mem:HI (match_operand 1 "address_operand" "")))]
2116   "GET_CODE (operands[1]) == SYMBOL_REF
2117    && CONSTANT_POOL_ADDRESS_P (operands[1])
2118    && get_pool_mode (operands[1]) == HImode
2119    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2120   [(set (match_dup 0) (match_dup 2))]
2121   "operands[2] = get_pool_constant (operands[1]);")
2122
2123 ;
2124 ; movqi instruction pattern(s).
2125 ;
2126
2127 (define_expand "movqi"
2128   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2129         (match_operand:QI 1 "general_operand" ""))]
2130   ""
2131 {
2132   /* On z/Architecture, zero-extending from memory to register
2133      is just as fast as a QImode load.  */
2134   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2135       && register_operand (operands[0], VOIDmode)
2136       && GET_CODE (operands[1]) == MEM)
2137     {
2138       rtx tmp = gen_reg_rtx (DImode);
2139       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2140       emit_insn (gen_rtx_SET (tmp, ext));
2141       operands[1] = gen_lowpart (QImode, tmp);
2142     }
2143 })
2144
2145 (define_insn "*movqi"
2146   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2147         (match_operand:QI 1 "general_operand"      " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2148   ""
2149   "@
2150    lr\t%0,%1
2151    lhi\t%0,%b1
2152    ic\t%0,%1
2153    icy\t%0,%1
2154    stc\t%1,%0
2155    stcy\t%1,%0
2156    mvi\t%S0,%b1
2157    mviy\t%S0,%b1
2158    #
2159    vleib\t%v0,%b1,0
2160    vlr\t%v0,%v1
2161    vlvgb\t%v0,%1,0
2162    vlgvb\t%0,%v1,0
2163    vleb\t%v0,%1,0
2164    vsteb\t%v1,%0,0"
2165   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2166    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2167    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2168    (set_attr "z10prop" "z10_fr_E1,
2169                         z10_fwd_A1,
2170                         z10_super_E1,
2171                         z10_super_E1,
2172                         z10_rec,
2173                         z10_rec,
2174                         z10_super,
2175                         z10_super,
2176                         *,*,*,*,*,*,*")])
2177
2178 (define_peephole2
2179   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2180         (mem:QI (match_operand 1 "address_operand" "")))]
2181   "GET_CODE (operands[1]) == SYMBOL_REF
2182    && CONSTANT_POOL_ADDRESS_P (operands[1])
2183    && get_pool_mode (operands[1]) == QImode
2184    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2185   [(set (match_dup 0) (match_dup 2))]
2186   "operands[2] = get_pool_constant (operands[1]);")
2187
2188 ;
2189 ; movstrictqi instruction pattern(s).
2190 ;
2191
2192 (define_insn "*movstrictqi"
2193   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2194                          (match_operand:QI 1 "memory_operand" "R,T"))]
2195   ""
2196   "@
2197    ic\t%0,%1
2198    icy\t%0,%1"
2199   [(set_attr "op_type"  "RX,RXY")
2200    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2201
2202 ;
2203 ; movstricthi instruction pattern(s).
2204 ;
2205
2206 (define_insn "*movstricthi"
2207   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2208                          (match_operand:HI 1 "memory_operand" "Q,S"))
2209    (clobber (reg:CC CC_REGNUM))]
2210   ""
2211   "@
2212    icm\t%0,3,%S1
2213    icmy\t%0,3,%S1"
2214   [(set_attr "op_type" "RS,RSY")
2215    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2216
2217 ;
2218 ; movstrictsi instruction pattern(s).
2219 ;
2220
2221 (define_insn "movstrictsi"
2222   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2223                          (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2224   "TARGET_ZARCH"
2225   "@
2226    lr\t%0,%1
2227    l\t%0,%1
2228    ly\t%0,%1
2229    ear\t%0,%1"
2230   [(set_attr "op_type" "RR,RX,RXY,RRE")
2231    (set_attr "type" "lr,load,load,*")
2232    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2233
2234 ;
2235 ; mov(tf|td) instruction pattern(s).
2236 ;
2237
2238 (define_expand "mov<mode>"
2239   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2240         (match_operand:TD_TF 1 "general_operand"      ""))]
2241   ""
2242   "")
2243
2244 (define_insn "*mov<mode>_64"
2245   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS,  d,o")
2246         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d"))]
2247   "TARGET_ZARCH"
2248   "@
2249    lzxr\t%0
2250    lxr\t%0,%1
2251    #
2252    #
2253    lmg\t%0,%N0,%S1
2254    stmg\t%1,%N1,%S0
2255    #
2256    #"
2257   [(set_attr "op_type"      "RRE,RRE,*,*,RSY,RSY,*,*")
2258    (set_attr "type"         "fsimptf,fsimptf,*,*,lm,stm,*,*")
2259    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2260
2261 (define_insn "*mov<mode>_31"
2262   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2263         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
2264   "!TARGET_ZARCH"
2265   "@
2266    lzxr\t%0
2267    lxr\t%0,%1
2268    #
2269    #"
2270   [(set_attr "op_type"      "RRE,RRE,*,*")
2271    (set_attr "type"         "fsimptf,fsimptf,*,*")
2272    (set_attr "cpu_facility" "z196,*,*,*")])
2273
2274 ; TFmode in GPRs splitters
2275
2276 (define_split
2277   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2278         (match_operand:TD_TF 1 "general_operand"      ""))]
2279   "TARGET_ZARCH && reload_completed
2280    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2281   [(set (match_dup 2) (match_dup 4))
2282    (set (match_dup 3) (match_dup 5))]
2283 {
2284   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2285   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2286   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2287   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2288 })
2289
2290 (define_split
2291   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2292         (match_operand:TD_TF 1 "general_operand"      ""))]
2293   "TARGET_ZARCH && reload_completed
2294    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2295   [(set (match_dup 2) (match_dup 4))
2296    (set (match_dup 3) (match_dup 5))]
2297 {
2298   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2299   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2300   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2301   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2302 })
2303
2304 (define_split
2305   [(set (match_operand:TD_TF 0 "register_operand" "")
2306         (match_operand:TD_TF 1 "memory_operand"   ""))]
2307   "TARGET_ZARCH && reload_completed
2308    && GENERAL_REG_P (operands[0])
2309    && !s_operand (operands[1], VOIDmode)"
2310   [(set (match_dup 0) (match_dup 1))]
2311 {
2312   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2313   addr = gen_lowpart (Pmode, addr);
2314   s390_load_address (addr, XEXP (operands[1], 0));
2315   operands[1] = replace_equiv_address (operands[1], addr);
2316 })
2317
2318 ; TFmode in BFPs splitters
2319
2320 (define_split
2321   [(set (match_operand:TD_TF 0 "register_operand" "")
2322         (match_operand:TD_TF 1 "memory_operand" ""))]
2323   "reload_completed && offsettable_memref_p (operands[1])
2324    && FP_REG_P (operands[0])"
2325   [(set (match_dup 2) (match_dup 4))
2326    (set (match_dup 3) (match_dup 5))]
2327 {
2328   operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2329                                      <MODE>mode, 0);
2330   operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2331                                      <MODE>mode, 8);
2332   operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2333   operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2334 })
2335
2336 (define_split
2337   [(set (match_operand:TD_TF 0 "memory_operand" "")
2338         (match_operand:TD_TF 1 "register_operand" ""))]
2339   "reload_completed && offsettable_memref_p (operands[0])
2340    && FP_REG_P (operands[1])"
2341   [(set (match_dup 2) (match_dup 4))
2342    (set (match_dup 3) (match_dup 5))]
2343 {
2344   operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2345   operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2346   operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2347                                      <MODE>mode, 0);
2348   operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2349                                      <MODE>mode, 8);
2350 })
2351
2352 ;
2353 ; mov(df|dd) instruction pattern(s).
2354 ;
2355
2356 (define_expand "mov<mode>"
2357   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2358         (match_operand:DD_DF 1 "general_operand"  ""))]
2359   ""
2360   "")
2361
2362 (define_insn "*mov<mode>_64dfp"
2363   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2364                                "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2365         (match_operand:DD_DF 1 "general_operand"
2366                                " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2367   "TARGET_DFP"
2368   "@
2369    lzdr\t%0
2370    ldr\t%0,%1
2371    ldgr\t%0,%1
2372    lgdr\t%0,%1
2373    ld\t%0,%1
2374    ldy\t%0,%1
2375    std\t%1,%0
2376    stdy\t%1,%0
2377    lghi\t%0,0
2378    lgr\t%0,%1
2379    lgrl\t%0,%1
2380    lg\t%0,%1
2381    stgrl\t%1,%0
2382    stg\t%1,%0
2383    vlr\t%v0,%v1
2384    vlvgg\t%v0,%1,0
2385    vlgvg\t%0,%v1,0
2386    vleg\t%0,%1,0
2387    vsteg\t%1,%0,0"
2388   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2389    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2390                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2391    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2392    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2393
2394 (define_insn "*mov<mode>_64"
2395   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2396         (match_operand:DD_DF 1 "general_operand"      " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2397   "TARGET_ZARCH"
2398   "@
2399    lzdr\t%0
2400    ldr\t%0,%1
2401    ld\t%0,%1
2402    ldy\t%0,%1
2403    std\t%1,%0
2404    stdy\t%1,%0
2405    lghi\t%0,0
2406    lgr\t%0,%1
2407    lgrl\t%0,%1
2408    lg\t%0,%1
2409    stgrl\t%1,%0
2410    stg\t%1,%0
2411    vlr\t%v0,%v1
2412    vleg\t%v0,%1,0
2413    vsteg\t%v1,%0,0"
2414   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2415    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2416                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2417    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2418    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2419
2420 (define_insn "*mov<mode>_31"
2421   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2422                                "=f,f,f,f,R,T,d,d,Q,S,   d,o")
2423         (match_operand:DD_DF 1 "general_operand"
2424                                " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2425   "!TARGET_ZARCH"
2426   "@
2427    lzdr\t%0
2428    ldr\t%0,%1
2429    ld\t%0,%1
2430    ldy\t%0,%1
2431    std\t%1,%0
2432    stdy\t%1,%0
2433    lm\t%0,%N0,%S1
2434    lmy\t%0,%N0,%S1
2435    stm\t%1,%N1,%S0
2436    stmy\t%1,%N1,%S0
2437    #
2438    #"
2439   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2440    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2441                         fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2442    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2443
2444 (define_split
2445   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2446         (match_operand:DD_DF 1 "general_operand" ""))]
2447   "!TARGET_ZARCH && reload_completed
2448    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2449   [(set (match_dup 2) (match_dup 4))
2450    (set (match_dup 3) (match_dup 5))]
2451 {
2452   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2453   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2454   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2455   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2456 })
2457
2458 (define_split
2459   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2460         (match_operand:DD_DF 1 "general_operand" ""))]
2461   "!TARGET_ZARCH && reload_completed
2462    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2463   [(set (match_dup 2) (match_dup 4))
2464    (set (match_dup 3) (match_dup 5))]
2465 {
2466   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2467   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2468   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2469   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2470 })
2471
2472 (define_split
2473   [(set (match_operand:DD_DF 0 "register_operand" "")
2474         (match_operand:DD_DF 1 "memory_operand" ""))]
2475   "!TARGET_ZARCH && reload_completed
2476    && !FP_REG_P (operands[0])
2477    && !s_operand (operands[1], VOIDmode)"
2478   [(set (match_dup 0) (match_dup 1))]
2479 {
2480   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2481   s390_load_address (addr, XEXP (operands[1], 0));
2482   operands[1] = replace_equiv_address (operands[1], addr);
2483 })
2484
2485 ;
2486 ; mov(sf|sd) instruction pattern(s).
2487 ;
2488
2489 (define_insn "mov<mode>"
2490   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2491                                "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2492         (match_operand:SD_SF 1 "general_operand"
2493                                " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2494   ""
2495   "@
2496    lzer\t%0
2497    lder\t%0,%1
2498    ler\t%0,%1
2499    lde\t%0,%1
2500    le\t%0,%1
2501    ley\t%0,%1
2502    ste\t%1,%0
2503    stey\t%1,%0
2504    lhi\t%0,0
2505    lr\t%0,%1
2506    lrl\t%0,%1
2507    l\t%0,%1
2508    ly\t%0,%1
2509    strl\t%1,%0
2510    st\t%1,%0
2511    sty\t%1,%0
2512    vlr\t%v0,%v1
2513    vleif\t%v0,0
2514    vlvgf\t%v0,%1,0
2515    vlgvf\t%0,%v1,0
2516    vleg\t%0,%1,0
2517    vsteg\t%1,%0,0"
2518   [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2519    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2520                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2521    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2522    (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2523
2524 ;
2525 ; movcc instruction pattern
2526 ;
2527
2528 (define_insn "movcc"
2529   [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2530         (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2531   ""
2532   "@
2533    lr\t%0,%1
2534    tmh\t%1,12288
2535    ipm\t%0
2536    l\t%0,%1
2537    ly\t%0,%1
2538    st\t%1,%0
2539    sty\t%1,%0"
2540   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2541    (set_attr "type" "lr,*,*,load,load,store,store")
2542    (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2543    (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2544
2545 ;
2546 ; Block move (MVC) patterns.
2547 ;
2548
2549 (define_insn "*mvc"
2550   [(set (match_operand:BLK 0 "memory_operand" "=Q")
2551         (match_operand:BLK 1 "memory_operand" "Q"))
2552    (use (match_operand 2 "const_int_operand" "n"))]
2553   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2554   "mvc\t%O0(%2,%R0),%S1"
2555   [(set_attr "op_type" "SS")])
2556
2557 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2558 ; order to have it implemented with mvc.
2559
2560 (define_split
2561   [(set (match_operand:QI 0 "memory_operand" "")
2562         (match_operand:QI 1 "memory_operand" ""))]
2563   "reload_completed"
2564   [(parallel
2565     [(set (match_dup 0) (match_dup 1))
2566      (use (const_int 1))])]
2567 {
2568   operands[0] = adjust_address (operands[0], BLKmode, 0);
2569   operands[1] = adjust_address (operands[1], BLKmode, 0);
2570 })
2571
2572
2573 (define_peephole2
2574   [(parallel
2575     [(set (match_operand:BLK 0 "memory_operand" "")
2576           (match_operand:BLK 1 "memory_operand" ""))
2577      (use (match_operand 2 "const_int_operand" ""))])
2578    (parallel
2579     [(set (match_operand:BLK 3 "memory_operand" "")
2580           (match_operand:BLK 4 "memory_operand" ""))
2581      (use (match_operand 5 "const_int_operand" ""))])]
2582   "s390_offset_p (operands[0], operands[3], operands[2])
2583    && s390_offset_p (operands[1], operands[4], operands[2])
2584    && !s390_overlap_p (operands[0], operands[1],
2585                        INTVAL (operands[2]) + INTVAL (operands[5]))
2586    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2587   [(parallel
2588     [(set (match_dup 6) (match_dup 7))
2589      (use (match_dup 8))])]
2590   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2591    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2592    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2593
2594
2595 ;
2596 ; load_multiple pattern(s).
2597 ;
2598 ; ??? Due to reload problems with replacing registers inside match_parallel
2599 ; we currently support load_multiple/store_multiple only after reload.
2600 ;
2601
2602 (define_expand "load_multiple"
2603   [(match_par_dup 3 [(set (match_operand 0 "" "")
2604                           (match_operand 1 "" ""))
2605                      (use (match_operand 2 "" ""))])]
2606   "reload_completed"
2607 {
2608   machine_mode mode;
2609   int regno;
2610   int count;
2611   rtx from;
2612   int i, off;
2613
2614   /* Support only loading a constant number of fixed-point registers from
2615      memory and only bother with this if more than two */
2616   if (GET_CODE (operands[2]) != CONST_INT
2617       || INTVAL (operands[2]) < 2
2618       || INTVAL (operands[2]) > 16
2619       || GET_CODE (operands[1]) != MEM
2620       || GET_CODE (operands[0]) != REG
2621       || REGNO (operands[0]) >= 16)
2622     FAIL;
2623
2624   count = INTVAL (operands[2]);
2625   regno = REGNO (operands[0]);
2626   mode = GET_MODE (operands[0]);
2627   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2628     FAIL;
2629
2630   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2631   if (!can_create_pseudo_p ())
2632     {
2633       if (GET_CODE (XEXP (operands[1], 0)) == REG)
2634         {
2635           from = XEXP (operands[1], 0);
2636           off = 0;
2637         }
2638       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2639                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2640                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2641         {
2642           from = XEXP (XEXP (operands[1], 0), 0);
2643           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2644         }
2645       else
2646         FAIL;
2647     }
2648   else
2649     {
2650       from = force_reg (Pmode, XEXP (operands[1], 0));
2651       off = 0;
2652     }
2653
2654   for (i = 0; i < count; i++)
2655     XVECEXP (operands[3], 0, i)
2656       = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2657                      change_address (operands[1], mode,
2658                        plus_constant (Pmode, from,
2659                                       off + i * GET_MODE_SIZE (mode))));
2660 })
2661
2662 (define_insn "*load_multiple_di"
2663   [(match_parallel 0 "load_multiple_operation"
2664                    [(set (match_operand:DI 1 "register_operand" "=r")
2665                          (match_operand:DI 2 "s_operand" "QS"))])]
2666   "reload_completed && TARGET_ZARCH"
2667 {
2668   int words = XVECLEN (operands[0], 0);
2669   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2670   return "lmg\t%1,%0,%S2";
2671 }
2672    [(set_attr "op_type" "RSY")
2673     (set_attr "type"    "lm")])
2674
2675 (define_insn "*load_multiple_si"
2676   [(match_parallel 0 "load_multiple_operation"
2677                    [(set (match_operand:SI 1 "register_operand" "=r,r")
2678                          (match_operand:SI 2 "s_operand" "Q,S"))])]
2679   "reload_completed"
2680 {
2681   int words = XVECLEN (operands[0], 0);
2682   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2683   return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2684 }
2685    [(set_attr "op_type" "RS,RSY")
2686     (set_attr "type"    "lm")])
2687
2688 ;
2689 ; store multiple pattern(s).
2690 ;
2691
2692 (define_expand "store_multiple"
2693   [(match_par_dup 3 [(set (match_operand 0 "" "")
2694                           (match_operand 1 "" ""))
2695                      (use (match_operand 2 "" ""))])]
2696   "reload_completed"
2697 {
2698   machine_mode mode;
2699   int regno;
2700   int count;
2701   rtx to;
2702   int i, off;
2703
2704   /* Support only storing a constant number of fixed-point registers to
2705      memory and only bother with this if more than two.  */
2706   if (GET_CODE (operands[2]) != CONST_INT
2707       || INTVAL (operands[2]) < 2
2708       || INTVAL (operands[2]) > 16
2709       || GET_CODE (operands[0]) != MEM
2710       || GET_CODE (operands[1]) != REG
2711       || REGNO (operands[1]) >= 16)
2712     FAIL;
2713
2714   count = INTVAL (operands[2]);
2715   regno = REGNO (operands[1]);
2716   mode = GET_MODE (operands[1]);
2717   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2718     FAIL;
2719
2720   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2721
2722   if (!can_create_pseudo_p ())
2723     {
2724       if (GET_CODE (XEXP (operands[0], 0)) == REG)
2725         {
2726           to = XEXP (operands[0], 0);
2727           off = 0;
2728         }
2729       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2730                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2731                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2732         {
2733           to = XEXP (XEXP (operands[0], 0), 0);
2734           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2735         }
2736       else
2737         FAIL;
2738     }
2739   else
2740     {
2741       to = force_reg (Pmode, XEXP (operands[0], 0));
2742       off = 0;
2743     }
2744
2745   for (i = 0; i < count; i++)
2746     XVECEXP (operands[3], 0, i)
2747       = gen_rtx_SET (change_address (operands[0], mode,
2748                        plus_constant (Pmode, to,
2749                                       off + i * GET_MODE_SIZE (mode))),
2750                      gen_rtx_REG (mode, regno + i));
2751 })
2752
2753 (define_insn "*store_multiple_di"
2754   [(match_parallel 0 "store_multiple_operation"
2755                    [(set (match_operand:DI 1 "s_operand" "=QS")
2756                          (match_operand:DI 2 "register_operand" "r"))])]
2757   "reload_completed && TARGET_ZARCH"
2758 {
2759   int words = XVECLEN (operands[0], 0);
2760   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2761   return "stmg\t%2,%0,%S1";
2762 }
2763    [(set_attr "op_type" "RSY")
2764     (set_attr "type"    "stm")])
2765
2766
2767 (define_insn "*store_multiple_si"
2768   [(match_parallel 0 "store_multiple_operation"
2769                    [(set (match_operand:SI 1 "s_operand" "=Q,S")
2770                          (match_operand:SI 2 "register_operand" "r,r"))])]
2771   "reload_completed"
2772 {
2773   int words = XVECLEN (operands[0], 0);
2774   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2775   return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2776 }
2777    [(set_attr "op_type" "RS,RSY")
2778     (set_attr "type"    "stm")])
2779
2780 ;;
2781 ;; String instructions.
2782 ;;
2783
2784 (define_insn "*execute_rl"
2785   [(match_parallel 0 "execute_operation"
2786     [(unspec [(match_operand 1    "register_operand" "a")
2787               (match_operand 2    "" "")
2788               (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2789   "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2790    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2791   "exrl\t%1,%3"
2792   [(set_attr "op_type" "RIL")
2793    (set_attr "type"    "cs")])
2794
2795 (define_insn "*execute"
2796   [(match_parallel 0 "execute_operation"
2797     [(unspec [(match_operand 1 "register_operand" "a")
2798               (match_operand:BLK 2 "memory_operand" "R")
2799               (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2800   "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2801    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2802   "ex\t%1,%2"
2803   [(set_attr "op_type" "RX")
2804    (set_attr "type" "cs")])
2805
2806
2807 ;
2808 ; strlenM instruction pattern(s).
2809 ;
2810
2811 (define_expand "strlen<mode>"
2812   [(match_operand:P   0 "register_operand" "")  ; result
2813    (match_operand:BLK 1 "memory_operand" "")    ; input string
2814    (match_operand:SI  2 "immediate_operand" "") ; search character
2815    (match_operand:SI  3 "immediate_operand" "")] ; known alignment
2816   ""
2817 {
2818   if (!TARGET_VX || operands[2] != const0_rtx)
2819     emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2820                                       operands[2], operands[3]));
2821   else
2822     s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2823
2824   DONE;
2825 })
2826
2827 (define_expand "strlen_srst<mode>"
2828   [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2829    (parallel
2830     [(set (match_dup 4)
2831           (unspec:P [(const_int 0)
2832                       (match_operand:BLK 1 "memory_operand" "")
2833                       (reg:SI 0)
2834                       (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2835      (clobber (scratch:P))
2836      (clobber (reg:CC CC_REGNUM))])
2837    (parallel
2838     [(set (match_operand:P 0 "register_operand" "")
2839           (minus:P (match_dup 4) (match_dup 5)))
2840      (clobber (reg:CC CC_REGNUM))])]
2841   ""
2842 {
2843   operands[4] = gen_reg_rtx (Pmode);
2844   operands[5] = gen_reg_rtx (Pmode);
2845   emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2846   operands[1] = replace_equiv_address (operands[1], operands[5]);
2847 })
2848
2849 (define_insn "*strlen<mode>"
2850   [(set (match_operand:P 0 "register_operand" "=a")
2851         (unspec:P [(match_operand:P 2 "general_operand" "0")
2852                     (mem:BLK (match_operand:P 3 "register_operand" "1"))
2853                     (reg:SI 0)
2854                     (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2855    (clobber (match_scratch:P 1 "=a"))
2856    (clobber (reg:CC CC_REGNUM))]
2857   ""
2858   "srst\t%0,%1\;jo\t.-4"
2859   [(set_attr "length" "8")
2860    (set_attr "type" "vs")])
2861
2862 ;
2863 ; cmpstrM instruction pattern(s).
2864 ;
2865
2866 (define_expand "cmpstrsi"
2867   [(set (reg:SI 0) (const_int 0))
2868    (parallel
2869     [(clobber (match_operand 3 "" ""))
2870      (clobber (match_dup 4))
2871      (set (reg:CCU CC_REGNUM)
2872           (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2873                        (match_operand:BLK 2 "memory_operand" "")))
2874      (use (reg:SI 0))])
2875    (parallel
2876     [(set (match_operand:SI 0 "register_operand" "=d")
2877           (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2878      (clobber (reg:CC CC_REGNUM))])]
2879   ""
2880 {
2881   /* As the result of CMPINT is inverted compared to what we need,
2882      we have to swap the operands.  */
2883   rtx op1 = operands[2];
2884   rtx op2 = operands[1];
2885   rtx addr1 = gen_reg_rtx (Pmode);
2886   rtx addr2 = gen_reg_rtx (Pmode);
2887
2888   emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2889   emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2890   operands[1] = replace_equiv_address_nv (op1, addr1);
2891   operands[2] = replace_equiv_address_nv (op2, addr2);
2892   operands[3] = addr1;
2893   operands[4] = addr2;
2894 })
2895
2896 (define_insn "*cmpstr<mode>"
2897   [(clobber (match_operand:P 0 "register_operand" "=d"))
2898    (clobber (match_operand:P 1 "register_operand" "=d"))
2899    (set (reg:CCU CC_REGNUM)
2900         (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2901                      (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2902    (use (reg:SI 0))]
2903   ""
2904   "clst\t%0,%1\;jo\t.-4"
2905   [(set_attr "length" "8")
2906    (set_attr "type" "vs")])
2907
2908 ;
2909 ; movstr instruction pattern.
2910 ;
2911
2912 (define_expand "movstr"
2913   [(set (reg:SI 0) (const_int 0))
2914    (parallel
2915     [(clobber (match_dup 3))
2916      (set (match_operand:BLK 1 "memory_operand" "")
2917           (match_operand:BLK 2 "memory_operand" ""))
2918      (set (match_operand 0 "register_operand" "")
2919           (unspec [(match_dup 1)
2920                    (match_dup 2)
2921                    (reg:SI 0)] UNSPEC_MVST))
2922      (clobber (reg:CC CC_REGNUM))])]
2923   ""
2924 {
2925   rtx addr1 = gen_reg_rtx (Pmode);
2926   rtx addr2 = gen_reg_rtx (Pmode);
2927
2928   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2929   emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2930   operands[1] = replace_equiv_address_nv (operands[1], addr1);
2931   operands[2] = replace_equiv_address_nv (operands[2], addr2);
2932   operands[3] = addr2;
2933 })
2934
2935 (define_insn "*movstr"
2936   [(clobber (match_operand:P 2 "register_operand" "=d"))
2937    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2938         (mem:BLK (match_operand:P 3 "register_operand" "2")))
2939    (set (match_operand:P 0 "register_operand" "=d")
2940         (unspec [(mem:BLK (match_dup 1))
2941                  (mem:BLK (match_dup 3))
2942                  (reg:SI 0)] UNSPEC_MVST))
2943    (clobber (reg:CC CC_REGNUM))]
2944   ""
2945   "mvst\t%1,%2\;jo\t.-4"
2946   [(set_attr "length" "8")
2947    (set_attr "type" "vs")])
2948
2949
2950 ;
2951 ; movmemM instruction pattern(s).
2952 ;
2953
2954 (define_expand "movmem<mode>"
2955   [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
2956         (match_operand:BLK 1 "memory_operand" ""))  ; source
2957    (use (match_operand:GPR 2 "general_operand" "")) ; count
2958    (match_operand 3 "" "")]
2959   ""
2960 {
2961   if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2962     DONE;
2963   else
2964     FAIL;
2965 })
2966
2967 ; Move a block that is up to 256 bytes in length.
2968 ; The block length is taken as (operands[2] % 256) + 1.
2969
2970 (define_expand "movmem_short"
2971   [(parallel
2972     [(set (match_operand:BLK 0 "memory_operand" "")
2973           (match_operand:BLK 1 "memory_operand" ""))
2974      (use (match_operand 2 "nonmemory_operand" ""))
2975      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2976      (clobber (match_dup 3))])]
2977   ""
2978   "operands[3] = gen_rtx_SCRATCH (Pmode);")
2979
2980 (define_insn "*movmem_short"
2981   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2982         (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2983    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2984    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2985    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2986   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2987   "#"
2988   [(set_attr "type"         "cs")
2989    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2990
2991 (define_split
2992   [(set (match_operand:BLK 0 "memory_operand" "")
2993         (match_operand:BLK 1 "memory_operand" ""))
2994    (use (match_operand 2 "const_int_operand" ""))
2995    (use (match_operand 3 "immediate_operand" ""))
2996    (clobber (scratch))]
2997   "reload_completed"
2998   [(parallel
2999     [(set (match_dup 0) (match_dup 1))
3000      (use (match_dup 2))])]
3001   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3002
3003 (define_split
3004   [(set (match_operand:BLK 0 "memory_operand" "")
3005         (match_operand:BLK 1 "memory_operand" ""))
3006    (use (match_operand 2 "register_operand" ""))
3007    (use (match_operand 3 "memory_operand" ""))
3008    (clobber (scratch))]
3009   "reload_completed"
3010   [(parallel
3011     [(unspec [(match_dup 2) (match_dup 3)
3012               (const_int 0)] UNSPEC_EXECUTE)
3013      (set (match_dup 0) (match_dup 1))
3014      (use (const_int 1))])]
3015   "")
3016
3017 (define_split
3018   [(set (match_operand:BLK 0 "memory_operand" "")
3019         (match_operand:BLK 1 "memory_operand" ""))
3020    (use (match_operand 2 "register_operand" ""))
3021    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3022    (clobber (scratch))]
3023   "TARGET_Z10 && reload_completed"
3024   [(parallel
3025     [(unspec [(match_dup 2) (const_int 0)
3026               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3027      (set (match_dup 0) (match_dup 1))
3028      (use (const_int 1))])]
3029   "operands[3] = gen_label_rtx ();")
3030
3031 (define_split
3032   [(set (match_operand:BLK 0 "memory_operand" "")
3033         (match_operand:BLK 1 "memory_operand" ""))
3034    (use (match_operand 2 "register_operand" ""))
3035    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3036    (clobber (match_operand 3 "register_operand" ""))]
3037   "reload_completed && TARGET_CPU_ZARCH"
3038   [(set (match_dup 3) (label_ref (match_dup 4)))
3039    (parallel
3040     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3041               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3042      (set (match_dup 0) (match_dup 1))
3043      (use (const_int 1))])]
3044   "operands[4] = gen_label_rtx ();")
3045
3046 ; Move a block of arbitrary length.
3047
3048 (define_expand "movmem_long"
3049   [(parallel
3050     [(clobber (match_dup 2))
3051      (clobber (match_dup 3))
3052      (set (match_operand:BLK 0 "memory_operand" "")
3053           (match_operand:BLK 1 "memory_operand" ""))
3054      (use (match_operand 2 "general_operand" ""))
3055      (use (match_dup 3))
3056      (clobber (reg:CC CC_REGNUM))])]
3057   ""
3058 {
3059   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3060   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3061   rtx reg0 = gen_reg_rtx (dreg_mode);
3062   rtx reg1 = gen_reg_rtx (dreg_mode);
3063   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3064   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3065   rtx len0 = gen_lowpart (Pmode, reg0);
3066   rtx len1 = gen_lowpart (Pmode, reg1);
3067
3068   emit_clobber (reg0);
3069   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3070   emit_move_insn (len0, operands[2]);
3071
3072   emit_clobber (reg1);
3073   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3074   emit_move_insn (len1, operands[2]);
3075
3076   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3077   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3078   operands[2] = reg0;
3079   operands[3] = reg1;
3080 })
3081
3082 (define_insn "*movmem_long"
3083   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3084    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3085    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3086         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3087    (use (match_dup 2))
3088    (use (match_dup 3))
3089    (clobber (reg:CC CC_REGNUM))]
3090   "TARGET_64BIT || !TARGET_ZARCH"
3091   "mvcle\t%0,%1,0\;jo\t.-4"
3092   [(set_attr "length" "8")
3093    (set_attr "type" "vs")])
3094
3095 (define_insn "*movmem_long_31z"
3096   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3097    (clobber (match_operand:TI 1 "register_operand" "=d"))
3098    (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3099         (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3100    (use (match_dup 2))
3101    (use (match_dup 3))
3102    (clobber (reg:CC CC_REGNUM))]
3103   "!TARGET_64BIT && TARGET_ZARCH"
3104   "mvcle\t%0,%1,0\;jo\t.-4"
3105   [(set_attr "length" "8")
3106    (set_attr "type" "vs")])
3107
3108
3109 ;
3110 ; Test data class.
3111 ;
3112
3113 (define_expand "signbit<mode>2"
3114   [(set (reg:CCZ CC_REGNUM)
3115         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3116                      (match_dup 2)]
3117                      UNSPEC_TDC_INSN))
3118    (set (match_operand:SI 0 "register_operand" "=d")
3119         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3120   "TARGET_HARD_FLOAT"
3121 {
3122   operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3123 })
3124
3125 (define_expand "isinf<mode>2"
3126   [(set (reg:CCZ CC_REGNUM)
3127         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3128                      (match_dup 2)]
3129                      UNSPEC_TDC_INSN))
3130    (set (match_operand:SI 0 "register_operand" "=d")
3131         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3132   "TARGET_HARD_FLOAT"
3133 {
3134   operands[2] = GEN_INT (S390_TDC_INFINITY);
3135 })
3136
3137 ; This extracts CC into a GPR properly shifted.  The actual IPM
3138 ; instruction will be issued by reload.  The constraint of operand 1
3139 ; forces reload to use a GPR.  So reload will issue a movcc insn for
3140 ; copying CC into a GPR first.
3141 (define_insn_and_split "*cc_to_int"
3142   [(set (match_operand:SI 0 "nonimmediate_operand"     "=d")
3143         (unspec:SI [(match_operand 1 "register_operand" "0")]
3144                    UNSPEC_CC_TO_INT))]
3145   "operands != NULL"
3146   "#"
3147   "reload_completed"
3148   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3149
3150 ; This insn is used to generate all variants of the Test Data Class
3151 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
3152 ; is the register to be tested and the second one is the bit mask
3153 ; specifying the required test(s).
3154 ;
3155 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3156 (define_insn "*TDC_insn_<mode>"
3157   [(set (reg:CCZ CC_REGNUM)
3158         (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3159                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3160   "TARGET_HARD_FLOAT"
3161   "t<_d>c<xde><bt>\t%0,%1"
3162    [(set_attr "op_type" "RXE")
3163     (set_attr "type"  "fsimp<mode>")])
3164
3165
3166
3167 ;
3168 ; setmemM instruction pattern(s).
3169 ;
3170
3171 (define_expand "setmem<mode>"
3172   [(set (match_operand:BLK 0 "memory_operand" "")
3173         (match_operand:QI 2 "general_operand" ""))
3174    (use (match_operand:GPR 1 "general_operand" ""))
3175    (match_operand 3 "" "")]
3176   ""
3177   "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3178
3179 ; Clear a block that is up to 256 bytes in length.
3180 ; The block length is taken as (operands[1] % 256) + 1.
3181
3182 (define_expand "clrmem_short"
3183   [(parallel
3184     [(set (match_operand:BLK 0 "memory_operand" "")
3185           (const_int 0))
3186      (use (match_operand 1 "nonmemory_operand" ""))
3187      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3188      (clobber (match_dup 2))
3189      (clobber (reg:CC CC_REGNUM))])]
3190   ""
3191   "operands[2] = gen_rtx_SCRATCH (Pmode);")
3192
3193 (define_insn "*clrmem_short"
3194   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3195         (const_int 0))
3196    (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3197    (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3198    (clobber (match_scratch:P 3 "=X,X,X,&a"))
3199    (clobber (reg:CC CC_REGNUM))]
3200   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3201   "#"
3202   [(set_attr "type" "cs")
3203    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3204
3205 (define_split
3206   [(set (match_operand:BLK 0 "memory_operand" "")
3207         (const_int 0))
3208    (use (match_operand 1 "const_int_operand" ""))
3209    (use (match_operand 2 "immediate_operand" ""))
3210    (clobber (scratch))
3211    (clobber (reg:CC CC_REGNUM))]
3212   "reload_completed"
3213   [(parallel
3214     [(set (match_dup 0) (const_int 0))
3215      (use (match_dup 1))
3216      (clobber (reg:CC CC_REGNUM))])]
3217   "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3218
3219 (define_split
3220   [(set (match_operand:BLK 0 "memory_operand" "")
3221         (const_int 0))
3222    (use (match_operand 1 "register_operand" ""))
3223    (use (match_operand 2 "memory_operand" ""))
3224    (clobber (scratch))
3225    (clobber (reg:CC CC_REGNUM))]
3226   "reload_completed"
3227   [(parallel
3228     [(unspec [(match_dup 1) (match_dup 2)
3229               (const_int 0)] UNSPEC_EXECUTE)
3230      (set (match_dup 0) (const_int 0))
3231      (use (const_int 1))
3232      (clobber (reg:CC CC_REGNUM))])]
3233   "")
3234
3235 (define_split
3236   [(set (match_operand:BLK 0 "memory_operand" "")
3237         (const_int 0))
3238    (use (match_operand 1 "register_operand" ""))
3239    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3240    (clobber (scratch))
3241    (clobber (reg:CC CC_REGNUM))]
3242   "TARGET_Z10 && reload_completed"
3243   [(parallel
3244     [(unspec [(match_dup 1) (const_int 0)
3245               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3246      (set (match_dup 0) (const_int 0))
3247      (use (const_int 1))
3248      (clobber (reg:CC CC_REGNUM))])]
3249   "operands[3] = gen_label_rtx ();")
3250
3251 (define_split
3252   [(set (match_operand:BLK 0 "memory_operand" "")
3253         (const_int 0))
3254    (use (match_operand 1 "register_operand" ""))
3255    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3256    (clobber (match_operand 2 "register_operand" ""))
3257    (clobber (reg:CC CC_REGNUM))]
3258   "reload_completed && TARGET_CPU_ZARCH"
3259   [(set (match_dup 2) (label_ref (match_dup 3)))
3260    (parallel
3261     [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3262               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3263      (set (match_dup 0) (const_int 0))
3264      (use (const_int 1))
3265      (clobber (reg:CC CC_REGNUM))])]
3266   "operands[3] = gen_label_rtx ();")
3267
3268 ; Initialize a block of arbitrary length with (operands[2] % 256).
3269
3270 (define_expand "setmem_long"
3271   [(parallel
3272     [(clobber (match_dup 1))
3273      (set (match_operand:BLK 0 "memory_operand" "")
3274           (match_operand 2 "shift_count_or_setmem_operand" ""))
3275      (use (match_operand 1 "general_operand" ""))
3276      (use (match_dup 3))
3277      (clobber (reg:CC CC_REGNUM))])]
3278   ""
3279 {
3280   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3281   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3282   rtx reg0 = gen_reg_rtx (dreg_mode);
3283   rtx reg1 = gen_reg_rtx (dreg_mode);
3284   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3285   rtx len0 = gen_lowpart (Pmode, reg0);
3286
3287   emit_clobber (reg0);
3288   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3289   emit_move_insn (len0, operands[1]);
3290
3291   emit_move_insn (reg1, const0_rtx);
3292
3293   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3294   operands[1] = reg0;
3295   operands[3] = reg1;
3296 })
3297
3298 (define_insn "*setmem_long"
3299   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3300    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3301         (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3302    (use (match_dup 3))
3303    (use (match_operand:<DBL> 1 "register_operand" "d"))
3304    (clobber (reg:CC CC_REGNUM))]
3305   "TARGET_64BIT || !TARGET_ZARCH"
3306   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3307   [(set_attr "length" "8")
3308    (set_attr "type" "vs")])
3309
3310 (define_insn "*setmem_long_and"
3311   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3312    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3313         (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3314              (match_operand 4 "const_int_operand"             "n")))
3315    (use (match_dup 3))
3316    (use (match_operand:<DBL> 1 "register_operand" "d"))
3317    (clobber (reg:CC CC_REGNUM))]
3318   "(TARGET_64BIT || !TARGET_ZARCH) &&
3319    (INTVAL (operands[4]) & 255) == 255"
3320   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3321   [(set_attr "length" "8")
3322    (set_attr "type" "vs")])
3323
3324 (define_insn "*setmem_long_31z"
3325   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3326    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3327         (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3328    (use (match_dup 3))
3329    (use (match_operand:TI 1 "register_operand" "d"))
3330    (clobber (reg:CC CC_REGNUM))]
3331   "!TARGET_64BIT && TARGET_ZARCH"
3332   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3333   [(set_attr "length" "8")
3334    (set_attr "type" "vs")])
3335
3336 ;
3337 ; cmpmemM instruction pattern(s).
3338 ;
3339
3340 (define_expand "cmpmemsi"
3341   [(set (match_operand:SI 0 "register_operand" "")
3342         (compare:SI (match_operand:BLK 1 "memory_operand" "")
3343                     (match_operand:BLK 2 "memory_operand" "") ) )
3344    (use (match_operand:SI 3 "general_operand" ""))
3345    (use (match_operand:SI 4 "" ""))]
3346   ""
3347 {
3348   if (s390_expand_cmpmem (operands[0], operands[1],
3349                           operands[2], operands[3]))
3350     DONE;
3351   else
3352     FAIL;
3353 })
3354
3355 ; Compare a block that is up to 256 bytes in length.
3356 ; The block length is taken as (operands[2] % 256) + 1.
3357
3358 (define_expand "cmpmem_short"
3359   [(parallel
3360     [(set (reg:CCU CC_REGNUM)
3361           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3362                        (match_operand:BLK 1 "memory_operand" "")))
3363      (use (match_operand 2 "nonmemory_operand" ""))
3364      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3365      (clobber (match_dup 3))])]
3366   ""
3367   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3368
3369 (define_insn "*cmpmem_short"
3370   [(set (reg:CCU CC_REGNUM)
3371         (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3372                      (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3373    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3374    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3375    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3376   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3377   "#"
3378   [(set_attr "type" "cs")
3379    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3380
3381 (define_split
3382   [(set (reg:CCU CC_REGNUM)
3383         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3384                      (match_operand:BLK 1 "memory_operand" "")))
3385    (use (match_operand 2 "const_int_operand" ""))
3386    (use (match_operand 3 "immediate_operand" ""))
3387    (clobber (scratch))]
3388   "reload_completed"
3389   [(parallel
3390     [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3391      (use (match_dup 2))])]
3392   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3393
3394 (define_split
3395   [(set (reg:CCU CC_REGNUM)
3396         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3397                      (match_operand:BLK 1 "memory_operand" "")))
3398    (use (match_operand 2 "register_operand" ""))
3399    (use (match_operand 3 "memory_operand" ""))
3400    (clobber (scratch))]
3401   "reload_completed"
3402   [(parallel
3403     [(unspec [(match_dup 2) (match_dup 3)
3404               (const_int 0)] UNSPEC_EXECUTE)
3405      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3406      (use (const_int 1))])]
3407   "")
3408
3409 (define_split
3410   [(set (reg:CCU CC_REGNUM)
3411         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3412                      (match_operand:BLK 1 "memory_operand" "")))
3413    (use (match_operand 2 "register_operand" ""))
3414    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3415    (clobber (scratch))]
3416   "TARGET_Z10 && reload_completed"
3417   [(parallel
3418     [(unspec [(match_dup 2) (const_int 0)
3419               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3420      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3421      (use (const_int 1))])]
3422   "operands[4] = gen_label_rtx ();")
3423
3424 (define_split
3425   [(set (reg:CCU CC_REGNUM)
3426         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3427                      (match_operand:BLK 1 "memory_operand" "")))
3428    (use (match_operand 2 "register_operand" ""))
3429    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3430    (clobber (match_operand 3 "register_operand" ""))]
3431   "reload_completed && TARGET_CPU_ZARCH"
3432   [(set (match_dup 3) (label_ref (match_dup 4)))
3433    (parallel
3434     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3435               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3436      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3437      (use (const_int 1))])]
3438   "operands[4] = gen_label_rtx ();")
3439
3440 ; Compare a block of arbitrary length.
3441
3442 (define_expand "cmpmem_long"
3443   [(parallel
3444     [(clobber (match_dup 2))
3445      (clobber (match_dup 3))
3446      (set (reg:CCU CC_REGNUM)
3447           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3448                        (match_operand:BLK 1 "memory_operand" "")))
3449      (use (match_operand 2 "general_operand" ""))
3450      (use (match_dup 3))])]
3451   ""
3452 {
3453   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3454   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3455   rtx reg0 = gen_reg_rtx (dreg_mode);
3456   rtx reg1 = gen_reg_rtx (dreg_mode);
3457   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3458   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3459   rtx len0 = gen_lowpart (Pmode, reg0);
3460   rtx len1 = gen_lowpart (Pmode, reg1);
3461
3462   emit_clobber (reg0);
3463   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3464   emit_move_insn (len0, operands[2]);
3465
3466   emit_clobber (reg1);
3467   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3468   emit_move_insn (len1, operands[2]);
3469
3470   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3471   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3472   operands[2] = reg0;
3473   operands[3] = reg1;
3474 })
3475
3476 (define_insn "*cmpmem_long"
3477   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3478    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3479    (set (reg:CCU CC_REGNUM)
3480         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3481                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3482    (use (match_dup 2))
3483    (use (match_dup 3))]
3484   "TARGET_64BIT || !TARGET_ZARCH"
3485   "clcle\t%0,%1,0\;jo\t.-4"
3486   [(set_attr "length" "8")
3487    (set_attr "type" "vs")])
3488
3489 (define_insn "*cmpmem_long_31z"
3490   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3491    (clobber (match_operand:TI 1 "register_operand" "=d"))
3492    (set (reg:CCU CC_REGNUM)
3493         (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3494                      (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3495    (use (match_dup 2))
3496    (use (match_dup 3))]
3497   "!TARGET_64BIT && TARGET_ZARCH"
3498   "clcle\t%0,%1,0\;jo\t.-4"
3499   [(set_attr "op_type" "NN")
3500    (set_attr "type"    "vs")
3501    (set_attr "length"  "8")])
3502
3503 ; Convert CCUmode condition code to integer.
3504 ; Result is zero if EQ, positive if LTU, negative if GTU.
3505
3506 (define_insn_and_split "cmpint"
3507   [(set (match_operand:SI 0 "register_operand" "=d")
3508         (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3509                    UNSPEC_STRCMPCC_TO_INT))
3510    (clobber (reg:CC CC_REGNUM))]
3511   ""
3512   "#"
3513   "reload_completed"
3514   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3515    (parallel
3516     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3517      (clobber (reg:CC CC_REGNUM))])])
3518
3519 (define_insn_and_split "*cmpint_cc"
3520   [(set (reg CC_REGNUM)
3521         (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3522                             UNSPEC_STRCMPCC_TO_INT)
3523                  (const_int 0)))
3524    (set (match_operand:SI 0 "register_operand" "=d")
3525         (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3526   "s390_match_ccmode (insn, CCSmode)"
3527   "#"
3528   "&& reload_completed"
3529   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3530    (parallel
3531     [(set (match_dup 2) (match_dup 3))
3532      (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3533 {
3534   rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3535   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3536   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3537 })
3538
3539 (define_insn_and_split "*cmpint_sign"
3540   [(set (match_operand:DI 0 "register_operand" "=d")
3541         (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3542                                    UNSPEC_STRCMPCC_TO_INT)))
3543    (clobber (reg:CC CC_REGNUM))]
3544   "TARGET_ZARCH"
3545   "#"
3546   "&& reload_completed"
3547   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3548    (parallel
3549     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3550      (clobber (reg:CC CC_REGNUM))])])
3551
3552 (define_insn_and_split "*cmpint_sign_cc"
3553   [(set (reg CC_REGNUM)
3554         (compare (ashiftrt:DI (ashift:DI (subreg:DI
3555                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3556                               UNSPEC_STRCMPCC_TO_INT) 0)
3557                    (const_int 32)) (const_int 32))
3558                  (const_int 0)))
3559    (set (match_operand:DI 0 "register_operand" "=d")
3560         (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3561   "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3562   "#"
3563   "&& reload_completed"
3564   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3565    (parallel
3566     [(set (match_dup 2) (match_dup 3))
3567      (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3568 {
3569   rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3570   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3571   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3572 })
3573
3574
3575 ;;
3576 ;;- Conversion instructions.
3577 ;;
3578
3579 (define_insn "*sethighpartsi"
3580   [(set (match_operand:SI 0 "register_operand" "=d,d")
3581         (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3582                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3583    (clobber (reg:CC CC_REGNUM))]
3584   ""
3585   "@
3586    icm\t%0,%2,%S1
3587    icmy\t%0,%2,%S1"
3588   [(set_attr "op_type" "RS,RSY")
3589    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3590
3591 (define_insn "*sethighpartdi_64"
3592   [(set (match_operand:DI 0 "register_operand" "=d")
3593         (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3594                     (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3595    (clobber (reg:CC CC_REGNUM))]
3596   "TARGET_ZARCH"
3597   "icmh\t%0,%2,%S1"
3598   [(set_attr "op_type" "RSY")
3599    (set_attr "z10prop" "z10_super")])
3600
3601 (define_insn "*sethighpartdi_31"
3602   [(set (match_operand:DI 0 "register_operand" "=d,d")
3603         (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3604                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3605    (clobber (reg:CC CC_REGNUM))]
3606   "!TARGET_ZARCH"
3607   "@
3608    icm\t%0,%2,%S1
3609    icmy\t%0,%2,%S1"
3610   [(set_attr "op_type" "RS,RSY")
3611    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3612
3613 ;
3614 ; extv instruction patterns
3615 ;
3616
3617 ; FIXME: This expander needs to be converted from DI to GPR as well
3618 ; after resolving some issues with it.
3619
3620 (define_expand "extzv"
3621   [(parallel
3622     [(set (match_operand:DI 0 "register_operand" "=d")
3623         (zero_extract:DI
3624          (match_operand:DI 1 "register_operand" "d")
3625          (match_operand 2 "const_int_operand" "")   ; size
3626          (match_operand 3 "const_int_operand" ""))) ; start
3627      (clobber (reg:CC CC_REGNUM))])]
3628   "TARGET_Z10"
3629 {
3630   /* Starting with zEC12 there is risbgn not clobbering CC.  */
3631   if (TARGET_ZEC12)
3632     {
3633       emit_move_insn (operands[0],
3634                     gen_rtx_ZERO_EXTRACT (DImode,
3635                                           operands[1],
3636                                           operands[2],
3637                                           operands[3]));
3638       DONE;
3639     }
3640 })
3641
3642 (define_insn "*extzv<mode>_zEC12"
3643   [(set (match_operand:GPR 0 "register_operand" "=d")
3644       (zero_extract:GPR
3645         (match_operand:GPR 1 "register_operand" "d")
3646         (match_operand 2 "const_int_operand" "")   ; size
3647         (match_operand 3 "const_int_operand" "")))] ; start]
3648   "TARGET_ZEC12"
3649   "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3650   [(set_attr "op_type" "RIE")])
3651
3652 (define_insn "*extzv<mode>_z10"
3653   [(set (match_operand:GPR 0 "register_operand" "=d")
3654       (zero_extract:GPR
3655        (match_operand:GPR 1 "register_operand" "d")
3656        (match_operand 2 "const_int_operand" "")   ; size
3657        (match_operand 3 "const_int_operand" ""))) ; start
3658    (clobber (reg:CC CC_REGNUM))]
3659   "TARGET_Z10"
3660   "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3661   [(set_attr "op_type" "RIE")
3662    (set_attr "z10prop" "z10_super_E1")])
3663
3664 (define_insn_and_split "*pre_z10_extzv<mode>"
3665   [(set (match_operand:GPR 0 "register_operand" "=d")
3666         (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3667                           (match_operand 2 "nonzero_shift_count_operand" "")
3668                           (const_int 0)))
3669    (clobber (reg:CC CC_REGNUM))]
3670   "!TARGET_Z10"
3671   "#"
3672   "&& reload_completed"
3673   [(parallel
3674     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3675      (clobber (reg:CC CC_REGNUM))])
3676    (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3677 {
3678   int bitsize = INTVAL (operands[2]);
3679   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3680   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3681
3682   operands[1] = adjust_address (operands[1], BLKmode, 0);
3683   set_mem_size (operands[1], size);
3684   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3685   operands[3] = GEN_INT (mask);
3686 })
3687
3688 (define_insn_and_split "*pre_z10_extv<mode>"
3689   [(set (match_operand:GPR 0 "register_operand" "=d")
3690         (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3691                           (match_operand 2 "nonzero_shift_count_operand" "")
3692                           (const_int 0)))
3693    (clobber (reg:CC CC_REGNUM))]
3694   ""
3695   "#"
3696   "&& reload_completed"
3697   [(parallel
3698     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3699      (clobber (reg:CC CC_REGNUM))])
3700    (parallel
3701     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3702      (clobber (reg:CC CC_REGNUM))])]
3703 {
3704   int bitsize = INTVAL (operands[2]);
3705   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3706   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3707
3708   operands[1] = adjust_address (operands[1], BLKmode, 0);
3709   set_mem_size (operands[1], size);
3710   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3711   operands[3] = GEN_INT (mask);
3712 })
3713
3714 ;
3715 ; insv instruction patterns
3716 ;
3717
3718 (define_expand "insv"
3719   [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3720                       (match_operand 1 "const_int_operand" "")
3721                       (match_operand 2 "const_int_operand" ""))
3722         (match_operand 3 "general_operand" ""))]
3723   ""
3724 {
3725   if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3726     DONE;
3727   FAIL;
3728 })
3729
3730
3731 ; The normal RTL expansion will never generate a zero_extract where
3732 ; the location operand isn't word mode.  However, we do this in the
3733 ; back-end when generating atomic operations. See s390_two_part_insv.
3734 (define_insn "*insv<mode>_zEC12"
3735   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3736                           (match_operand 1 "const_int_operand"    "I")  ; size
3737                           (match_operand 2 "const_int_operand"    "I")) ; pos
3738         (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3739   "TARGET_ZEC12
3740    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3741   "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3742   [(set_attr "op_type" "RIE")])
3743
3744 (define_insn "*insv<mode>_z10"
3745   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3746                           (match_operand 1 "const_int_operand"    "I")  ; size
3747                           (match_operand 2 "const_int_operand"    "I")) ; pos
3748         (match_operand:GPR 3 "nonimmediate_operand" "d"))
3749    (clobber (reg:CC CC_REGNUM))]
3750   "TARGET_Z10
3751    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3752   "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3753   [(set_attr "op_type" "RIE")
3754    (set_attr "z10prop" "z10_super_E1")])
3755
3756 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3757 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3758 (define_insn "*insv<mode>_zEC12_noshift"
3759   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3760         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3761                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3762                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3763                           (match_operand:GPR 4 "const_int_operand" ""))))]
3764   "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3765   "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3766   [(set_attr "op_type" "RIE")])
3767
3768 (define_insn "*insv<mode>_z10_noshift"
3769   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3770         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3771                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3772                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3773                           (match_operand:GPR 4 "const_int_operand" ""))))
3774    (clobber (reg:CC CC_REGNUM))]
3775   "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3776   "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3777   [(set_attr "op_type" "RIE")
3778    (set_attr "z10prop" "z10_super_E1")])
3779
3780 ; Implement appending Y on the left of S bits of X
3781 ; x = (y << s) | (x & ((1 << s) - 1))
3782 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3783   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3784         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3785                           (match_operand:GPR 2 "immediate_operand" ""))
3786                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3787                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3788   "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3789   "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3790   [(set_attr "op_type" "RIE")
3791    (set_attr "z10prop" "z10_super_E1")])
3792
3793 (define_insn "*insv<mode>_z10_appendbitsleft"
3794   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3795         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3796                           (match_operand:GPR 2 "immediate_operand" ""))
3797                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3798                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3799    (clobber (reg:CC CC_REGNUM))]
3800   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3801   "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3802   [(set_attr "op_type" "RIE")
3803    (set_attr "z10prop" "z10_super_E1")])
3804
3805 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3806 ;  -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3807 ;  -> z = y >> d; z = risbg;
3808
3809 (define_split
3810   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3811         (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3812                                (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3813                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3814                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3815   "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3816   [(set (match_dup 0)
3817         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3818    (set (match_dup 0)
3819         (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3820                  (ashift:GPR (match_dup 3) (match_dup 4))))]
3821 {
3822   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3823 })
3824
3825 (define_split
3826   [(parallel
3827     [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3828           (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3829                                  (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3830                    (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3831                                (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3832      (clobber (reg:CC CC_REGNUM))])]
3833   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3834   [(set (match_dup 0)
3835         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3836    (parallel
3837     [(set (match_dup 0)
3838           (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3839                    (ashift:GPR (match_dup 3) (match_dup 4))))
3840      (clobber (reg:CC CC_REGNUM))])]
3841 {
3842   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3843 })
3844
3845 (define_insn "*r<noxa>sbg_<mode>_noshift"
3846   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3847         (IXOR:GPR
3848           (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3849                    (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3850           (match_operand:GPR 3 "nonimmediate_operand" "0")))
3851    (clobber (reg:CC CC_REGNUM))]
3852   "TARGET_Z10"
3853   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3854   [(set_attr "op_type" "RIE")])
3855
3856 (define_insn "*r<noxa>sbg_di_rotl"
3857   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3858         (IXOR:DI
3859           (and:DI
3860             (rotate:DI
3861               (match_operand:DI 1 "nonimmediate_operand" "d")
3862               (match_operand:DI 3 "const_int_operand" ""))
3863             (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3864           (match_operand:DI 4 "nonimmediate_operand" "0")))
3865    (clobber (reg:CC CC_REGNUM))]
3866   "TARGET_Z10"
3867   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3868   [(set_attr "op_type" "RIE")])
3869
3870 (define_insn "*r<noxa>sbg_<mode>_srl"
3871   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3872         (IXOR:GPR
3873           (and:GPR
3874             (lshiftrt:GPR
3875               (match_operand:GPR 1 "nonimmediate_operand" "d")
3876               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3877             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3878           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3879    (clobber (reg:CC CC_REGNUM))]
3880   "TARGET_Z10
3881    && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3882                            INTVAL (operands[2]))"
3883   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3884   [(set_attr "op_type" "RIE")])
3885
3886 (define_insn "*r<noxa>sbg_<mode>_sll"
3887   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3888         (IXOR:GPR
3889           (and:GPR
3890             (ashift:GPR
3891               (match_operand:GPR 1 "nonimmediate_operand" "d")
3892               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3893             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3894           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3895    (clobber (reg:CC CC_REGNUM))]
3896   "TARGET_Z10
3897    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3898                            INTVAL (operands[2]))"
3899   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3900   [(set_attr "op_type" "RIE")])
3901
3902 ;; These two are generated by combine for s.bf &= val.
3903 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3904 ;; shifts and ands, which results in some truly awful patterns
3905 ;; including subregs of operations.  Rather unnecessisarily, IMO.
3906 ;; Instead of
3907 ;;
3908 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3909 ;;        (const_int 24 [0x18])
3910 ;;        (const_int 0 [0]))
3911 ;;    (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3912 ;;                    (const_int 40 [0x28])) 4)
3913 ;;            (reg:SI 4 %r4 [ y+4 ])) 0))
3914 ;;
3915 ;; we should instead generate
3916 ;;
3917 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3918 ;;        (const_int 24 [0x18])
3919 ;;        (const_int 0 [0]))
3920 ;;    (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3921 ;;                    (const_int 40 [0x28]))
3922 ;;            (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3923 ;;
3924 ;; by noticing that we can push down the outer paradoxical subreg
3925 ;; into the operation.
3926
3927 (define_insn "*insv_rnsbg_noshift"
3928   [(set (zero_extract:DI
3929           (match_operand:DI 0 "nonimmediate_operand" "+d")
3930           (match_operand 1 "const_int_operand" "")
3931           (match_operand 2 "const_int_operand" ""))
3932         (and:DI
3933           (match_dup 0)
3934           (match_operand:DI 3 "nonimmediate_operand" "d")))
3935    (clobber (reg:CC CC_REGNUM))]
3936   "TARGET_Z10
3937    && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3938   "rnsbg\t%0,%3,%2,63,0"
3939   [(set_attr "op_type" "RIE")])
3940
3941 (define_insn "*insv_rnsbg_srl"
3942   [(set (zero_extract:DI
3943           (match_operand:DI 0 "nonimmediate_operand" "+d")
3944           (match_operand 1 "const_int_operand" "")
3945           (match_operand 2 "const_int_operand" ""))
3946         (and:DI
3947           (lshiftrt:DI
3948             (match_dup 0)
3949             (match_operand 3 "const_int_operand" ""))
3950           (match_operand:DI 4 "nonimmediate_operand" "d")))
3951    (clobber (reg:CC CC_REGNUM))]
3952   "TARGET_Z10
3953    && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3954   "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3955   [(set_attr "op_type" "RIE")])
3956
3957 (define_insn "*insv<mode>_mem_reg"
3958   [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3959                         (match_operand 1 "const_int_operand" "n,n")
3960                         (const_int 0))
3961         (match_operand:W 2 "register_operand" "d,d"))]
3962   "INTVAL (operands[1]) > 0
3963    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3964    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3965 {
3966     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3967
3968     operands[1] = GEN_INT ((1ul << size) - 1);
3969     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3970                                     : "stcmy\t%2,%1,%S0";
3971 }
3972   [(set_attr "op_type" "RS,RSY")
3973    (set_attr "z10prop" "z10_super,z10_super")])
3974
3975 (define_insn "*insvdi_mem_reghigh"
3976   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3977                          (match_operand 1 "const_int_operand" "n")
3978                          (const_int 0))
3979         (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3980                      (const_int 32)))]
3981   "TARGET_ZARCH
3982    && INTVAL (operands[1]) > 0
3983    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3984    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3985 {
3986     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3987
3988     operands[1] = GEN_INT ((1ul << size) - 1);
3989     return "stcmh\t%2,%1,%S0";
3990 }
3991 [(set_attr "op_type" "RSY")
3992  (set_attr "z10prop" "z10_super")])
3993
3994 (define_insn "*insvdi_reg_imm"
3995   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3996                          (const_int 16)
3997                          (match_operand 1 "const_int_operand" "n"))
3998         (match_operand:DI 2 "const_int_operand" "n"))]
3999   "TARGET_ZARCH
4000    && INTVAL (operands[1]) >= 0
4001    && INTVAL (operands[1]) < BITS_PER_WORD
4002    && INTVAL (operands[1]) % 16 == 0"
4003 {
4004   switch (BITS_PER_WORD - INTVAL (operands[1]))
4005     {
4006       case 64: return "iihh\t%0,%x2"; break;
4007       case 48: return "iihl\t%0,%x2"; break;
4008       case 32: return "iilh\t%0,%x2"; break;
4009       case 16: return "iill\t%0,%x2"; break;
4010       default: gcc_unreachable();
4011     }
4012 }
4013   [(set_attr "op_type" "RI")
4014    (set_attr "z10prop" "z10_super_E1")])
4015
4016 ; Update the left-most 32 bit of a DI.
4017 (define_insn "*insv_h_di_reg_extimm"
4018   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4019                          (const_int 32)
4020                          (const_int 0))
4021         (match_operand:DI 1 "const_int_operand" "n"))]
4022   "TARGET_EXTIMM"
4023   "iihf\t%0,%o1"
4024   [(set_attr "op_type" "RIL")
4025    (set_attr "z10prop" "z10_fwd_E1")])
4026
4027 ; Update the right-most 32 bit of a DI.
4028 (define_insn "*insv_l_di_reg_extimm"
4029   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4030                          (const_int 32)
4031                          (const_int 32))
4032         (match_operand:DI 1 "const_int_operand" "n"))]
4033   "TARGET_EXTIMM"
4034   "iilf\t%0,%o1"
4035   [(set_attr "op_type" "RIL")
4036    (set_attr "z10prop" "z10_fwd_A1")])
4037
4038 ;
4039 ; extendsidi2 instruction pattern(s).
4040 ;
4041
4042 (define_expand "extendsidi2"
4043   [(set (match_operand:DI 0 "register_operand" "")
4044         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4045   ""
4046 {
4047   if (!TARGET_ZARCH)
4048     {
4049       emit_clobber (operands[0]);
4050       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4051       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4052       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4053       DONE;
4054     }
4055 })
4056
4057 (define_insn "*extendsidi2"
4058   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4059         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4060   "TARGET_ZARCH"
4061   "@
4062    lgfr\t%0,%1
4063    lgf\t%0,%1
4064    lgfrl\t%0,%1"
4065   [(set_attr "op_type"      "RRE,RXY,RIL")
4066    (set_attr "type"         "*,*,larl")
4067    (set_attr "cpu_facility" "*,*,z10")
4068    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4069
4070 ;
4071 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4072 ;
4073
4074 (define_expand "extend<HQI:mode><DSI:mode>2"
4075   [(set (match_operand:DSI 0 "register_operand" "")
4076         (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4077   ""
4078 {
4079   if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4080     {
4081       rtx tmp = gen_reg_rtx (SImode);
4082       emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4083       emit_insn (gen_extendsidi2 (operands[0], tmp));
4084       DONE;
4085     }
4086   else if (!TARGET_EXTIMM)
4087     {
4088       rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4089
4090       operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4091       emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4092       emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4093       DONE;
4094     }
4095 })
4096
4097 ;
4098 ; extendhidi2 instruction pattern(s).
4099 ;
4100
4101 (define_insn "*extendhidi2_extimm"
4102   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4103         (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
4104   "TARGET_ZARCH && TARGET_EXTIMM"
4105   "@
4106    lghr\t%0,%1
4107    lgh\t%0,%1
4108    lghrl\t%0,%1"
4109   [(set_attr "op_type"      "RRE,RXY,RIL")
4110    (set_attr "type"         "*,*,larl")
4111    (set_attr "cpu_facility" "extimm,extimm,z10")
4112    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4113
4114 (define_insn "*extendhidi2"
4115   [(set (match_operand:DI 0 "register_operand" "=d")
4116         (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
4117   "TARGET_ZARCH"
4118   "lgh\t%0,%1"
4119   [(set_attr "op_type" "RXY")
4120    (set_attr "z10prop" "z10_super_E1")])
4121
4122 ;
4123 ; extendhisi2 instruction pattern(s).
4124 ;
4125
4126 (define_insn "*extendhisi2_extimm"
4127   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4128         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4129   "TARGET_EXTIMM"
4130   "@
4131    lhr\t%0,%1
4132    lh\t%0,%1
4133    lhy\t%0,%1
4134    lhrl\t%0,%1"
4135   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
4136    (set_attr "type"         "*,*,*,larl")
4137    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4138    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4139
4140 (define_insn "*extendhisi2"
4141   [(set (match_operand:SI 0 "register_operand" "=d,d")
4142         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4143   "!TARGET_EXTIMM"
4144   "@
4145    lh\t%0,%1
4146    lhy\t%0,%1"
4147   [(set_attr "op_type" "RX,RXY")
4148    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4149
4150 ;
4151 ; extendqi(si|di)2 instruction pattern(s).
4152 ;
4153
4154 ; lbr, lgbr, lb, lgb
4155 (define_insn "*extendqi<mode>2_extimm"
4156   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4157         (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
4158   "TARGET_EXTIMM"
4159   "@
4160    l<g>br\t%0,%1
4161    l<g>b\t%0,%1"
4162   [(set_attr "op_type" "RRE,RXY")
4163    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4164
4165 ; lb, lgb
4166 (define_insn "*extendqi<mode>2"
4167   [(set (match_operand:GPR 0 "register_operand" "=d")
4168         (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
4169   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4170   "l<g>b\t%0,%1"
4171   [(set_attr "op_type" "RXY")
4172    (set_attr "z10prop" "z10_super_E1")])
4173
4174 (define_insn_and_split "*extendqi<mode>2_short_displ"
4175   [(set (match_operand:GPR 0 "register_operand" "=d")
4176         (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4177    (clobber (reg:CC CC_REGNUM))]
4178   "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4179   "#"
4180   "&& reload_completed"
4181   [(parallel
4182     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4183      (clobber (reg:CC CC_REGNUM))])
4184    (parallel
4185     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4186      (clobber (reg:CC CC_REGNUM))])]
4187 {
4188   operands[1] = adjust_address (operands[1], BLKmode, 0);
4189   set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4190   operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4191 })
4192
4193 ;
4194 ; zero_extendsidi2 instruction pattern(s).
4195 ;
4196
4197 (define_expand "zero_extendsidi2"
4198   [(set (match_operand:DI 0 "register_operand" "")
4199         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4200   ""
4201 {
4202   if (!TARGET_ZARCH)
4203     {
4204       emit_clobber (operands[0]);
4205       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4206       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4207       DONE;
4208     }
4209 })
4210
4211 (define_insn "*zero_extendsidi2"
4212   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4213         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4214   "TARGET_ZARCH"
4215   "@
4216    llgfr\t%0,%1
4217    llgf\t%0,%1
4218    llgfrl\t%0,%1"
4219   [(set_attr "op_type"      "RRE,RXY,RIL")
4220    (set_attr "type"         "*,*,larl")
4221    (set_attr "cpu_facility" "*,*,z10")
4222    (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4223
4224 ;
4225 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4226 ;
4227
4228 (define_insn "*llgt_sidi"
4229   [(set (match_operand:DI 0 "register_operand" "=d")
4230         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4231                 (const_int 2147483647)))]
4232   "TARGET_ZARCH"
4233   "llgt\t%0,%1"
4234   [(set_attr "op_type"  "RXE")
4235    (set_attr "z10prop" "z10_super_E1")])
4236
4237 (define_insn_and_split "*llgt_sidi_split"
4238   [(set (match_operand:DI 0 "register_operand" "=d")
4239         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4240                 (const_int 2147483647)))
4241    (clobber (reg:CC CC_REGNUM))]
4242   "TARGET_ZARCH"
4243   "#"
4244   "&& reload_completed"
4245   [(set (match_dup 0)
4246         (and:DI (subreg:DI (match_dup 1) 0)
4247                 (const_int 2147483647)))]
4248   "")
4249
4250 (define_insn "*llgt_sisi"
4251   [(set (match_operand:SI 0 "register_operand" "=d,d")
4252         (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4253                 (const_int 2147483647)))]
4254   "TARGET_ZARCH"
4255   "@
4256    llgtr\t%0,%1
4257    llgt\t%0,%1"
4258   [(set_attr "op_type"  "RRE,RXE")
4259    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4260
4261 (define_insn "*llgt_didi"
4262   [(set (match_operand:DI 0 "register_operand" "=d,d")
4263         (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4264                 (const_int 2147483647)))]
4265   "TARGET_ZARCH"
4266   "@
4267    llgtr\t%0,%1
4268    llgt\t%0,%N1"
4269   [(set_attr "op_type"  "RRE,RXE")
4270    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4271
4272 (define_split
4273   [(set (match_operand:DSI 0 "register_operand" "")
4274         (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4275                  (const_int 2147483647)))
4276    (clobber (reg:CC CC_REGNUM))]
4277   "TARGET_ZARCH && reload_completed"
4278   [(set (match_dup 0)
4279         (and:DSI (match_dup 1)
4280                  (const_int 2147483647)))]
4281   "")
4282
4283 ;
4284 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4285 ;
4286
4287 (define_expand "zero_extend<mode>di2"
4288   [(set (match_operand:DI 0 "register_operand" "")
4289         (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4290   ""
4291 {
4292   if (!TARGET_ZARCH)
4293     {
4294       rtx tmp = gen_reg_rtx (SImode);
4295       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4296       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4297       DONE;
4298     }
4299   else if (!TARGET_EXTIMM)
4300     {
4301       rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4302       operands[1] = gen_lowpart (DImode, operands[1]);
4303       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4304       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4305       DONE;
4306     }
4307 })
4308
4309 (define_expand "zero_extend<mode>si2"
4310   [(set (match_operand:SI 0 "register_operand" "")
4311         (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4312   ""
4313 {
4314   if (!TARGET_EXTIMM)
4315     {
4316       operands[1] = gen_lowpart (SImode, operands[1]);
4317       emit_insn (gen_andsi3 (operands[0], operands[1],
4318                              GEN_INT ((1 << <HQI:bitsize>) - 1)));
4319       DONE;
4320     }
4321 })
4322
4323 ; llhrl, llghrl
4324 (define_insn "*zero_extendhi<mode>2_z10"
4325   [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4326         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4327   "TARGET_Z10"
4328   "@
4329    ll<g>hr\t%0,%1
4330    ll<g>h\t%0,%1
4331    ll<g>hrl\t%0,%1"
4332   [(set_attr "op_type"      "RXY,RRE,RIL")
4333    (set_attr "type"         "*,*,larl")
4334    (set_attr "cpu_facility" "*,*,z10")
4335    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4336
4337 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4338 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4339   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4340         (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4341   "TARGET_EXTIMM"
4342   "@
4343    ll<g><hc>r\t%0,%1
4344    ll<g><hc>\t%0,%1"
4345   [(set_attr "op_type" "RRE,RXY")
4346    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4347
4348 ; llgh, llgc
4349 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4350   [(set (match_operand:GPR 0 "register_operand" "=d")
4351         (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4352   "TARGET_ZARCH && !TARGET_EXTIMM"
4353   "llg<hc>\t%0,%1"
4354   [(set_attr "op_type" "RXY")
4355    (set_attr "z10prop" "z10_fwd_A3")])
4356
4357 (define_insn_and_split "*zero_extendhisi2_31"
4358   [(set (match_operand:SI 0 "register_operand" "=&d")
4359         (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4360    (clobber (reg:CC CC_REGNUM))]
4361   "!TARGET_ZARCH"
4362   "#"
4363   "&& reload_completed"
4364   [(set (match_dup 0) (const_int 0))
4365    (parallel
4366     [(set (strict_low_part (match_dup 2)) (match_dup 1))
4367      (clobber (reg:CC CC_REGNUM))])]
4368   "operands[2] = gen_lowpart (HImode, operands[0]);")
4369
4370 (define_insn_and_split "*zero_extendqisi2_31"
4371   [(set (match_operand:SI 0 "register_operand" "=&d")
4372         (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4373   "!TARGET_ZARCH"
4374   "#"
4375   "&& reload_completed"
4376   [(set (match_dup 0) (const_int 0))
4377    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4378   "operands[2] = gen_lowpart (QImode, operands[0]);")
4379
4380 ;
4381 ; zero_extendqihi2 instruction pattern(s).
4382 ;
4383
4384 (define_expand "zero_extendqihi2"
4385   [(set (match_operand:HI 0 "register_operand" "")
4386         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4387   "TARGET_ZARCH && !TARGET_EXTIMM"
4388 {
4389   operands[1] = gen_lowpart (HImode, operands[1]);
4390   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4391   DONE;
4392 })
4393
4394 (define_insn "*zero_extendqihi2_64"
4395   [(set (match_operand:HI 0 "register_operand" "=d")
4396         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4397   "TARGET_ZARCH && !TARGET_EXTIMM"
4398   "llgc\t%0,%1"
4399   [(set_attr "op_type" "RXY")
4400    (set_attr "z10prop" "z10_fwd_A3")])
4401
4402 (define_insn_and_split "*zero_extendqihi2_31"
4403   [(set (match_operand:HI 0 "register_operand" "=&d")
4404         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4405   "!TARGET_ZARCH"
4406   "#"
4407   "&& reload_completed"
4408   [(set (match_dup 0) (const_int 0))
4409    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4410   "operands[2] = gen_lowpart (QImode, operands[0]);")
4411
4412 ;
4413 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4414 ;
4415
4416 (define_expand "fixuns_truncdddi2"
4417   [(parallel
4418     [(set (match_operand:DI 0 "register_operand" "")
4419           (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4420      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4421      (clobber (reg:CC CC_REGNUM))])]
4422
4423   "TARGET_HARD_DFP"
4424 {
4425   if (!TARGET_Z196)
4426     {
4427       rtx_code_label *label1 = gen_label_rtx ();
4428       rtx_code_label *label2 = gen_label_rtx ();
4429       rtx temp = gen_reg_rtx (TDmode);
4430       REAL_VALUE_TYPE cmp, sub;
4431
4432       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4433       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4434
4435       /* 2^63 can't be represented as 64bit DFP number with full precision.  The
4436          solution is doing the check and the subtraction in TD mode and using a
4437          TD -> DI convert afterwards.  */
4438       emit_insn (gen_extendddtd2 (temp, operands[1]));
4439       temp = force_reg (TDmode, temp);
4440       emit_cmp_and_jump_insns (temp,
4441             const_double_from_real_value (cmp, TDmode),
4442             LT, NULL_RTX, VOIDmode, 0, label1);
4443       emit_insn (gen_subtd3 (temp, temp,
4444             const_double_from_real_value (sub, TDmode)));
4445       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4446       emit_jump (label2);
4447
4448       emit_label (label1);
4449       emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4450       emit_label (label2);
4451       DONE;
4452     }
4453 })
4454
4455 (define_expand "fixuns_trunctddi2"
4456   [(parallel
4457     [(set (match_operand:DI 0 "register_operand" "")
4458           (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4459      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4460      (clobber (reg:CC CC_REGNUM))])]
4461
4462   "TARGET_HARD_DFP"
4463 {
4464   if (!TARGET_Z196)
4465     {
4466       rtx_code_label *label1 = gen_label_rtx ();
4467       rtx_code_label *label2 = gen_label_rtx ();
4468       rtx temp = gen_reg_rtx (TDmode);
4469       REAL_VALUE_TYPE cmp, sub;
4470
4471       operands[1] = force_reg (TDmode, operands[1]);
4472       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4473       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4474
4475       emit_cmp_and_jump_insns (operands[1],
4476             const_double_from_real_value (cmp, TDmode),
4477             LT, NULL_RTX, VOIDmode, 0, label1);
4478       emit_insn (gen_subtd3 (temp, operands[1],
4479             const_double_from_real_value (sub, TDmode)));
4480       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4481       emit_jump (label2);
4482
4483       emit_label (label1);
4484       emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4485       emit_label (label2);
4486       DONE;
4487     }
4488 })
4489
4490 ;
4491 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4492 ; instruction pattern(s).
4493 ;
4494
4495 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4496   [(parallel
4497     [(set (match_operand:GPR 0 "register_operand" "")
4498           (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4499      (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4500      (clobber (reg:CC CC_REGNUM))])]
4501   "TARGET_HARD_FLOAT"
4502 {
4503   if (!TARGET_Z196)
4504     {
4505       rtx_code_label *label1 = gen_label_rtx ();
4506       rtx_code_label *label2 = gen_label_rtx ();
4507       rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4508       REAL_VALUE_TYPE cmp, sub;
4509
4510       operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4511       real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4512       real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4513
4514       emit_cmp_and_jump_insns (operands[1],
4515             const_double_from_real_value (cmp, <BFP:MODE>mode),
4516             LT, NULL_RTX, VOIDmode, 0, label1);
4517       emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4518             const_double_from_real_value (sub, <BFP:MODE>mode)));
4519       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4520             GEN_INT (7)));
4521       emit_jump (label2);
4522
4523       emit_label (label1);
4524       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4525             operands[1], GEN_INT (5)));
4526       emit_label (label2);
4527       DONE;
4528     }
4529 })
4530
4531 ; fixuns_trunc(td|dd)si2 expander
4532 (define_expand "fixuns_trunc<mode>si2"
4533   [(parallel
4534     [(set (match_operand:SI 0 "register_operand" "")
4535           (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4536      (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4537      (clobber (reg:CC CC_REGNUM))])]
4538   "TARGET_Z196 && TARGET_HARD_DFP"
4539   "")
4540
4541 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4542
4543 (define_insn "*fixuns_truncdfdi2_z13"
4544   [(set (match_operand:DI                  0 "register_operand" "=d,v")
4545         (unsigned_fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4546    (unspec:DI [(match_operand:DI           2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4547    (clobber (reg:CC CC_REGNUM))]
4548    "TARGET_Z13 && TARGET_HARD_FLOAT"
4549    "@
4550     clgdbr\t%0,%h2,%1,0
4551     wclgdb\t%v0,%v1,0,%h2"
4552    [(set_attr "op_type" "RRF,VRR")
4553     (set_attr "type"    "ftoi")])
4554
4555 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4556 ;         clfdtr, clfxtr,         clgdtr, clgxtr
4557 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4558   [(set (match_operand:GPR                  0 "register_operand" "=d")
4559         (unsigned_fix:GPR (match_operand:FP 1 "register_operand"  "f")))
4560    (unspec:GPR [(match_operand:GPR          2 "immediate_operand" "K")] UNSPEC_ROUND)
4561    (clobber (reg:CC CC_REGNUM))]
4562    "TARGET_Z196 && TARGET_HARD_FLOAT
4563     && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4564    "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4565    [(set_attr "op_type" "RRF")
4566     (set_attr "type"    "ftoi")])
4567
4568 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4569   [(set (match_operand:GPR 0 "register_operand" "")
4570         (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4571   "TARGET_HARD_FLOAT"
4572 {
4573   emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4574              GEN_INT (5)));
4575   DONE;
4576 })
4577
4578 (define_insn "*fix_truncdfdi2_bfp_z13"
4579   [(set (match_operand:DI         0 "register_operand" "=d,v")
4580         (fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4581    (unspec:DI [(match_operand:DI  2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4582    (clobber (reg:CC CC_REGNUM))]
4583   "TARGET_Z13 && TARGET_HARD_FLOAT"
4584   "@
4585    cgdbr\t%0,%h2,%1
4586    wcgdb\t%v0,%v1,0,%h2"
4587   [(set_attr "op_type" "RRE,VRR")
4588    (set_attr "type"    "ftoi")])
4589
4590 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4591 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4592   [(set (match_operand:GPR          0 "register_operand" "=d")
4593         (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4594    (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4595    (clobber (reg:CC CC_REGNUM))]
4596   "TARGET_HARD_FLOAT
4597     && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4598   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4599   [(set_attr "op_type" "RRE")
4600    (set_attr "type"    "ftoi")])
4601
4602 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4603   [(parallel
4604     [(set (match_operand:GPR          0 "register_operand" "=d")
4605           (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4606      (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4607      (clobber (reg:CC CC_REGNUM))])]
4608   "TARGET_HARD_FLOAT")
4609 ;
4610 ; fix_trunc(td|dd)di2 instruction pattern(s).
4611 ;
4612
4613 (define_expand "fix_trunc<mode>di2"
4614   [(set (match_operand:DI 0 "register_operand" "")
4615         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4616   "TARGET_ZARCH && TARGET_HARD_DFP"
4617 {
4618   operands[1] = force_reg (<MODE>mode, operands[1]);
4619   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4620       GEN_INT (9)));
4621   DONE;
4622 })
4623
4624 ; cgxtr, cgdtr
4625 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4626   [(set (match_operand:DI 0 "register_operand" "=d")
4627         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4628    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4629    (clobber (reg:CC CC_REGNUM))]
4630   "TARGET_ZARCH && TARGET_HARD_DFP"
4631   "cg<DFP:xde>tr\t%0,%h2,%1"
4632   [(set_attr "op_type" "RRF")
4633    (set_attr "type"    "ftoidfp")])
4634
4635
4636 ;
4637 ; fix_trunctf(si|di)2 instruction pattern(s).
4638 ;
4639
4640 (define_expand "fix_trunctf<mode>2"
4641   [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4642                    (fix:GPR (match_operand:TF 1 "register_operand" "")))
4643               (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4644               (clobber (reg:CC CC_REGNUM))])]
4645   "TARGET_HARD_FLOAT"
4646   "")
4647
4648
4649 ;
4650 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4651 ;
4652
4653 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4654 (define_insn "floatdi<mode>2"
4655   [(set (match_operand:FP           0 "register_operand" "=f,<vf>")
4656         (float:FP (match_operand:DI 1 "register_operand"  "d,<vd>")))]
4657   "TARGET_ZARCH && TARGET_HARD_FLOAT"
4658   "@
4659    c<xde>g<bt>r\t%0,%1
4660    wcdgb\t%v0,%v1,0,0"
4661   [(set_attr "op_type"      "RRE,VRR")
4662    (set_attr "type"         "itof<mode>" )
4663    (set_attr "cpu_facility" "*,vec")])
4664
4665 ; cxfbr, cdfbr, cefbr
4666 (define_insn "floatsi<mode>2"
4667   [(set (match_operand:BFP 0 "register_operand" "=f")
4668         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4669   "TARGET_HARD_FLOAT"
4670   "c<xde>fbr\t%0,%1"
4671   [(set_attr "op_type" "RRE")
4672    (set_attr "type"   "itof<mode>" )])
4673
4674 ; cxftr, cdftr
4675 (define_insn "floatsi<mode>2"
4676   [(set (match_operand:DFP 0 "register_operand" "=f")
4677         (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4678   "TARGET_Z196 && TARGET_HARD_FLOAT"
4679   "c<xde>ftr\t%0,0,%1,0"
4680   [(set_attr "op_type" "RRE")
4681    (set_attr "type"   "itof<mode>" )])
4682
4683 ;
4684 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4685 ;
4686
4687 (define_insn "*floatunsdidf2_z13"
4688   [(set (match_operand:DF                    0 "register_operand" "=f,v")
4689         (unsigned_float:DF (match_operand:DI 1 "register_operand"  "d,v")))]
4690   "TARGET_Z13 && TARGET_HARD_FLOAT"
4691   "@
4692    cdlgbr\t%0,0,%1,0
4693    wcdlgb\t%v0,%v1,0,0"
4694   [(set_attr "op_type" "RRE,VRR")
4695    (set_attr "type"    "itofdf")])
4696
4697 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4698 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4699 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4700   [(set (match_operand:FP                     0 "register_operand" "=f")
4701         (unsigned_float:FP (match_operand:GPR 1 "register_operand"  "d")))]
4702   "TARGET_Z196 && TARGET_HARD_FLOAT
4703    && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4704   "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4705   [(set_attr "op_type" "RRE")
4706    (set_attr "type"    "itof<FP:mode>")])
4707
4708 (define_expand "floatuns<GPR:mode><FP:mode>2"
4709   [(set (match_operand:FP                     0 "register_operand" "")
4710         (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4711   "TARGET_Z196 && TARGET_HARD_FLOAT")
4712
4713 ;
4714 ; truncdfsf2 instruction pattern(s).
4715 ;
4716
4717 (define_insn "truncdfsf2"
4718   [(set (match_operand:SF                    0 "register_operand" "=f,v")
4719         (float_truncate:SF (match_operand:DF 1 "register_operand"  "f,v")))]
4720   "TARGET_HARD_FLOAT"
4721   "@
4722    ledbr\t%0,%1
4723    wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4724                        ; According to BFP rounding mode
4725   [(set_attr "op_type"      "RRE,VRR")
4726    (set_attr "type"         "ftruncdf")
4727    (set_attr "cpu_facility" "*,vec")])
4728
4729 ;
4730 ; trunctf(df|sf)2 instruction pattern(s).
4731 ;
4732
4733 ; ldxbr, lexbr
4734 (define_insn "trunctf<mode>2"
4735   [(set (match_operand:DSF 0 "register_operand" "=f")
4736         (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4737    (clobber (match_scratch:TF 2 "=f"))]
4738   "TARGET_HARD_FLOAT"
4739   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4740   [(set_attr "length" "6")
4741    (set_attr "type"   "ftrunctf")])
4742
4743 ;
4744 ; trunctddd2 and truncddsd2 instruction pattern(s).
4745 ;
4746
4747 (define_insn "trunctddd2"
4748   [(set (match_operand:DD 0 "register_operand" "=f")
4749         (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4750    (clobber (match_scratch:TD 2 "=f"))]
4751   "TARGET_HARD_DFP"
4752   "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4753   [(set_attr "length"  "6")
4754    (set_attr "type"    "ftruncdd")])
4755
4756 (define_insn "truncddsd2"
4757   [(set (match_operand:SD 0 "register_operand" "=f")
4758         (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4759   "TARGET_HARD_DFP"
4760   "ledtr\t%0,0,%1,0"
4761   [(set_attr "op_type" "RRF")
4762    (set_attr "type"    "ftruncsd")])
4763
4764 (define_expand "trunctdsd2"
4765   [(parallel
4766     [(set (match_dup 3)
4767           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4768      (clobber (match_scratch:TD 2 ""))])
4769    (set (match_operand:SD 0 "register_operand" "")
4770         (float_truncate:SD (match_dup 3)))]
4771   "TARGET_HARD_DFP"
4772 {
4773   operands[3] = gen_reg_rtx (DDmode);
4774 })
4775
4776 ;
4777 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4778 ;
4779
4780 (define_insn "*extendsfdf2_z13"
4781   [(set (match_operand:DF                  0 "register_operand"     "=f,f,v")
4782         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R,v")))]
4783   "TARGET_Z13 && TARGET_HARD_FLOAT"
4784   "@
4785    ldebr\t%0,%1
4786    ldeb\t%0,%1
4787    wldeb\t%v0,%v1"
4788   [(set_attr "op_type" "RRE,RXE,VRR")
4789    (set_attr "type"    "fsimpdf, floaddf,fsimpdf")])
4790
4791 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4792 (define_insn "*extend<DSF:mode><BFP:mode>2"
4793   [(set (match_operand:BFP                   0 "register_operand"     "=f,f")
4794         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
4795   "TARGET_HARD_FLOAT
4796    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4797    && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4798   "@
4799    l<BFP:xde><DSF:xde>br\t%0,%1
4800    l<BFP:xde><DSF:xde>b\t%0,%1"
4801   [(set_attr "op_type" "RRE,RXE")
4802    (set_attr "type"    "fsimp<BFP:mode>, fload<BFP:mode>")])
4803
4804 (define_expand "extend<DSF:mode><BFP:mode>2"
4805   [(set (match_operand:BFP                   0 "register_operand"     "")
4806         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4807   "TARGET_HARD_FLOAT
4808    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4809
4810 ;
4811 ; extendddtd2 and extendsddd2 instruction pattern(s).
4812 ;
4813
4814 (define_insn "extendddtd2"
4815   [(set (match_operand:TD 0 "register_operand" "=f")
4816         (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4817   "TARGET_HARD_DFP"
4818   "lxdtr\t%0,%1,0"
4819   [(set_attr "op_type" "RRF")
4820    (set_attr "type"    "fsimptf")])
4821
4822 (define_insn "extendsddd2"
4823   [(set (match_operand:DD 0 "register_operand" "=f")
4824         (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4825   "TARGET_HARD_DFP"
4826   "ldetr\t%0,%1,0"
4827   [(set_attr "op_type" "RRF")
4828    (set_attr "type"    "fsimptf")])
4829
4830 (define_expand "extendsdtd2"
4831   [(set (match_dup 2)
4832         (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4833    (set (match_operand:TD 0 "register_operand" "")
4834         (float_extend:TD (match_dup 2)))]
4835   "TARGET_HARD_DFP"
4836 {
4837   operands[2] = gen_reg_rtx (DDmode);
4838 })
4839
4840 ; Binary Floating Point - load fp integer
4841
4842 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4843 ; For all of them the inexact exceptions are suppressed.
4844
4845 ; fiebra, fidbra, fixbra
4846 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4847   [(set (match_operand:BFP 0 "register_operand" "=f")
4848         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4849                     FPINT))]
4850   "TARGET_Z196"
4851   "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4852   [(set_attr "op_type"   "RRF")
4853    (set_attr "type"      "fsimp<BFP:mode>")])
4854
4855 ; rint is supposed to raise an inexact exception so we can use the
4856 ; older instructions.
4857
4858 ; fiebr, fidbr, fixbr
4859 (define_insn "rint<BFP:mode>2"
4860   [(set (match_operand:BFP 0 "register_operand" "=f")
4861         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4862                     UNSPEC_FPINT_RINT))]
4863   ""
4864   "fi<BFP:xde>br\t%0,0,%1"
4865   [(set_attr "op_type"   "RRF")
4866    (set_attr "type"      "fsimp<BFP:mode>")])
4867
4868
4869 ; Decimal Floating Point - load fp integer
4870
4871 ; fidtr, fixtr
4872 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4873   [(set (match_operand:DFP 0 "register_operand" "=f")
4874         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4875                     FPINT))]
4876   "TARGET_HARD_DFP"
4877   "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4878   [(set_attr "op_type"   "RRF")
4879    (set_attr "type"      "fsimp<DFP:mode>")])
4880
4881 ; fidtr, fixtr
4882 (define_insn "rint<DFP:mode>2"
4883   [(set (match_operand:DFP 0 "register_operand" "=f")
4884         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4885                     UNSPEC_FPINT_RINT))]
4886   "TARGET_HARD_DFP"
4887   "fi<DFP:xde>tr\t%0,0,%1,0"
4888   [(set_attr "op_type"   "RRF")
4889    (set_attr "type"      "fsimp<DFP:mode>")])
4890
4891 ;
4892 ; Binary <-> Decimal floating point trunc patterns
4893 ;
4894
4895 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4896   [(set (reg:DFP_ALL FPR0_REGNUM)
4897         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4898    (use (reg:SI GPR0_REGNUM))
4899    (clobber (reg:CC CC_REGNUM))
4900    (clobber (reg:SI GPR1_REGNUM))]
4901   "TARGET_HARD_DFP"
4902   "pfpo")
4903
4904 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4905   [(set (reg:BFP FPR0_REGNUM)
4906         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4907    (use (reg:SI GPR0_REGNUM))
4908    (clobber (reg:CC CC_REGNUM))
4909    (clobber (reg:SI GPR1_REGNUM))]
4910   "TARGET_HARD_DFP"
4911   "pfpo")
4912
4913 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4914   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4915    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4916    (parallel
4917     [(set (reg:DFP_ALL FPR0_REGNUM)
4918           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4919      (use (reg:SI GPR0_REGNUM))
4920      (clobber (reg:CC CC_REGNUM))
4921      (clobber (reg:SI GPR1_REGNUM))])
4922    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4923         (reg:DFP_ALL FPR0_REGNUM))]
4924   "TARGET_HARD_DFP
4925    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4926 {
4927   HOST_WIDE_INT flags;
4928
4929   flags = (PFPO_CONVERT |
4930            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4931            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4932
4933   operands[2] = GEN_INT (flags);
4934 })
4935
4936 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4937   [(set (reg:DFP_ALL FPR4_REGNUM)
4938         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4939    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4940    (parallel
4941     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4942      (use (reg:SI GPR0_REGNUM))
4943      (clobber (reg:CC CC_REGNUM))
4944      (clobber (reg:SI GPR1_REGNUM))])
4945    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4946   "TARGET_HARD_DFP
4947    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4948 {
4949   HOST_WIDE_INT flags;
4950
4951   flags = (PFPO_CONVERT |
4952            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4953            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4954
4955   operands[2] = GEN_INT (flags);
4956 })
4957
4958 ;
4959 ; Binary <-> Decimal floating point extend patterns
4960 ;
4961
4962 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4963   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4964    (use (reg:SI GPR0_REGNUM))
4965    (clobber (reg:CC CC_REGNUM))
4966    (clobber (reg:SI GPR1_REGNUM))]
4967   "TARGET_HARD_DFP"
4968   "pfpo")
4969
4970 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4971   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4972    (use (reg:SI GPR0_REGNUM))
4973    (clobber (reg:CC CC_REGNUM))
4974    (clobber (reg:SI GPR1_REGNUM))]
4975   "TARGET_HARD_DFP"
4976   "pfpo")
4977
4978 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4979   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4980    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4981    (parallel
4982     [(set (reg:DFP_ALL FPR0_REGNUM)
4983           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4984      (use (reg:SI GPR0_REGNUM))
4985      (clobber (reg:CC CC_REGNUM))
4986      (clobber (reg:SI GPR1_REGNUM))])
4987    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4988         (reg:DFP_ALL FPR0_REGNUM))]
4989   "TARGET_HARD_DFP
4990    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4991 {
4992   HOST_WIDE_INT flags;
4993
4994   flags = (PFPO_CONVERT |
4995            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4996            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4997
4998   operands[2] = GEN_INT (flags);
4999 })
5000
5001 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5002   [(set (reg:DFP_ALL FPR4_REGNUM)
5003         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5004    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5005    (parallel
5006     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5007      (use (reg:SI GPR0_REGNUM))
5008      (clobber (reg:CC CC_REGNUM))
5009      (clobber (reg:SI GPR1_REGNUM))])
5010    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5011   "TARGET_HARD_DFP
5012    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5013 {
5014   HOST_WIDE_INT flags;
5015
5016   flags = (PFPO_CONVERT |
5017            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5018            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5019
5020   operands[2] = GEN_INT (flags);
5021 })
5022
5023
5024 ;;
5025 ;; ARITHMETIC OPERATIONS
5026 ;;
5027 ;  arithmetic operations set the ConditionCode,
5028 ;  because of unpredictable Bits in Register for Halfword and Byte
5029 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
5030
5031 ;;
5032 ;;- Add instructions.
5033 ;;
5034
5035 ;
5036 ; addti3 instruction pattern(s).
5037 ;
5038
5039 (define_expand "addti3"
5040   [(parallel
5041     [(set (match_operand:TI          0 "register_operand"     "")
5042           (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5043                    (match_operand:TI 2 "general_operand"      "") ) )
5044      (clobber (reg:CC CC_REGNUM))])]
5045   "TARGET_ZARCH"
5046 {
5047   /* For z13 we have vaq which doesn't set CC.  */
5048   if (TARGET_VX)
5049     {
5050       emit_insn (gen_rtx_SET (operands[0],
5051                               gen_rtx_PLUS (TImode,
5052                                             copy_to_mode_reg (TImode, operands[1]),
5053                                             copy_to_mode_reg (TImode, operands[2]))));
5054       DONE;
5055     }
5056 })
5057
5058 (define_insn_and_split "*addti3"
5059   [(set (match_operand:TI          0 "register_operand"    "=&d")
5060         (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5061                  (match_operand:TI 2 "general_operand"      "do") ) )
5062    (clobber (reg:CC CC_REGNUM))]
5063   "TARGET_ZARCH"
5064   "#"
5065   "&& reload_completed"
5066   [(parallel
5067     [(set (reg:CCL1 CC_REGNUM)
5068           (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5069                         (match_dup 7)))
5070      (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5071    (parallel
5072     [(set (match_dup 3) (plus:DI
5073                           (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5074                                    (match_dup 4)) (match_dup 5)))
5075      (clobber (reg:CC CC_REGNUM))])]
5076   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5077    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5078    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5079    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5080    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5081    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5082   [(set_attr "op_type"  "*")
5083    (set_attr "cpu_facility" "*")])
5084
5085 ;
5086 ; adddi3 instruction pattern(s).
5087 ;
5088
5089 (define_expand "adddi3"
5090   [(parallel
5091     [(set (match_operand:DI 0 "nonimmediate_operand" "")
5092           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5093                    (match_operand:DI 2 "general_operand" "")))
5094      (clobber (reg:CC CC_REGNUM))])]
5095   ""
5096   "")
5097
5098 (define_insn "*adddi3_sign"
5099   [(set (match_operand:DI 0 "register_operand" "=d,d")
5100         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5101                  (match_operand:DI 1 "register_operand" "0,0")))
5102    (clobber (reg:CC CC_REGNUM))]
5103   "TARGET_ZARCH"
5104   "@
5105    agfr\t%0,%2
5106    agf\t%0,%2"
5107   [(set_attr "op_type"  "RRE,RXY")
5108    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5109
5110 (define_insn "*adddi3_zero_cc"
5111   [(set (reg CC_REGNUM)
5112         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5113                           (match_operand:DI 1 "register_operand" "0,0"))
5114                  (const_int 0)))
5115    (set (match_operand:DI 0 "register_operand" "=d,d")
5116         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5117   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5118   "@
5119    algfr\t%0,%2
5120    algf\t%0,%2"
5121   [(set_attr "op_type"  "RRE,RXY")
5122    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5123
5124 (define_insn "*adddi3_zero_cconly"
5125   [(set (reg CC_REGNUM)
5126         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5127                           (match_operand:DI 1 "register_operand" "0,0"))
5128                  (const_int 0)))
5129    (clobber (match_scratch:DI 0 "=d,d"))]
5130   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5131   "@
5132    algfr\t%0,%2
5133    algf\t%0,%2"
5134   [(set_attr "op_type"  "RRE,RXY")
5135    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5136
5137 (define_insn "*adddi3_zero"
5138   [(set (match_operand:DI 0 "register_operand" "=d,d")
5139         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5140                  (match_operand:DI 1 "register_operand" "0,0")))
5141    (clobber (reg:CC CC_REGNUM))]
5142   "TARGET_ZARCH"
5143   "@
5144    algfr\t%0,%2
5145    algf\t%0,%2"
5146   [(set_attr "op_type"  "RRE,RXY")
5147    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5148
5149 (define_insn_and_split "*adddi3_31z"
5150   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5151         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5152                  (match_operand:DI 2 "general_operand" "do") ) )
5153    (clobber (reg:CC CC_REGNUM))]
5154   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5155   "#"
5156   "&& reload_completed"
5157   [(parallel
5158     [(set (reg:CCL1 CC_REGNUM)
5159           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5160                         (match_dup 7)))
5161      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5162    (parallel
5163     [(set (match_dup 3) (plus:SI
5164                           (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5165                                    (match_dup 4)) (match_dup 5)))
5166      (clobber (reg:CC CC_REGNUM))])]
5167   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5168    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5169    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5170    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5171    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5172    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5173
5174 (define_insn_and_split "*adddi3_31"
5175   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5176         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5177                  (match_operand:DI 2 "general_operand" "do") ) )
5178    (clobber (reg:CC CC_REGNUM))]
5179   "!TARGET_CPU_ZARCH"
5180   "#"
5181   "&& reload_completed"
5182   [(parallel
5183     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5184      (clobber (reg:CC CC_REGNUM))])
5185    (parallel
5186     [(set (reg:CCL1 CC_REGNUM)
5187           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5188                         (match_dup 7)))
5189      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5190    (set (pc)
5191         (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5192                       (pc)
5193                       (label_ref (match_dup 9))))
5194    (parallel
5195     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5196      (clobber (reg:CC CC_REGNUM))])
5197    (match_dup 9)]
5198   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5199    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5200    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5201    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5202    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5203    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5204    operands[9] = gen_label_rtx ();")
5205
5206 ;
5207 ; addsi3 instruction pattern(s).
5208 ;
5209
5210 (define_expand "addsi3"
5211   [(parallel
5212     [(set (match_operand:SI 0 "nonimmediate_operand" "")
5213           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5214                    (match_operand:SI 2 "general_operand" "")))
5215      (clobber (reg:CC CC_REGNUM))])]
5216   ""
5217   "")
5218
5219 (define_insn "*addsi3_sign"
5220   [(set (match_operand:SI 0 "register_operand" "=d,d")
5221         (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5222                  (match_operand:SI 1 "register_operand" "0,0")))
5223    (clobber (reg:CC CC_REGNUM))]
5224   ""
5225   "@
5226    ah\t%0,%2
5227    ahy\t%0,%2"
5228   [(set_attr "op_type"  "RX,RXY")
5229    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5230
5231 ;
5232 ; add(di|si)3 instruction pattern(s).
5233 ;
5234
5235 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5236 (define_insn "*add<mode>3"
5237   [(set (match_operand:GPR 0 "nonimmediate_operand"           "=d,d,d,d, d, d,d,d,QS")
5238         (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
5239                   (match_operand:GPR 2 "general_operand"      " d,d,K,K,Op,On,R,T, C") ) )
5240    (clobber (reg:CC CC_REGNUM))]
5241   ""
5242   "@
5243    a<g>r\t%0,%2
5244    a<g>rk\t%0,%1,%2
5245    a<g>hi\t%0,%h2
5246    a<g>hik\t%0,%1,%h2
5247    al<g>fi\t%0,%2
5248    sl<g>fi\t%0,%n2
5249    a<g>\t%0,%2
5250    a<y>\t%0,%2
5251    a<g>si\t%0,%c2"
5252   [(set_attr "op_type"  "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5253    (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
5254    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5255                         z10_super_E1,z10_super_E1,z10_super_E1")])
5256
5257 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5258 (define_insn "*add<mode>3_carry1_cc"
5259   [(set (reg CC_REGNUM)
5260         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5261                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5262                  (match_dup 1)))
5263    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,d")
5264         (plus:GPR (match_dup 1) (match_dup 2)))]
5265   "s390_match_ccmode (insn, CCL1mode)"
5266   "@
5267    al<g>r\t%0,%2
5268    al<g>rk\t%0,%1,%2
5269    al<g>fi\t%0,%2
5270    sl<g>fi\t%0,%n2
5271    al<g>hsik\t%0,%1,%h2
5272    al<g>\t%0,%2
5273    al<y>\t%0,%2
5274    al<g>si\t%0,%c2"
5275   [(set_attr "op_type"      "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5276    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5277    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5278                         z10_super_E1,z10_super_E1,z10_super_E1")])
5279
5280 ; alr, al, aly, algr, alg, alrk, algrk
5281 (define_insn "*add<mode>3_carry1_cconly"
5282   [(set (reg CC_REGNUM)
5283         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5284                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5285                  (match_dup 1)))
5286    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5287   "s390_match_ccmode (insn, CCL1mode)"
5288   "@
5289    al<g>r\t%0,%2
5290    al<g>rk\t%0,%1,%2
5291    al<g>\t%0,%2
5292    al<y>\t%0,%2"
5293   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5294    (set_attr "cpu_facility" "*,z196,*,*")
5295    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5296
5297 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5298 (define_insn "*add<mode>3_carry2_cc"
5299   [(set (reg CC_REGNUM)
5300         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5301                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5302                  (match_dup 2)))
5303    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5304         (plus:GPR (match_dup 1) (match_dup 2)))]
5305   "s390_match_ccmode (insn, CCL1mode)"
5306   "@
5307    al<g>r\t%0,%2
5308    al<g>rk\t%0,%1,%2
5309    al<g>fi\t%0,%2
5310    sl<g>fi\t%0,%n2
5311    al<g>hsik\t%0,%1,%h2
5312    al<g>\t%0,%2
5313    al<y>\t%0,%2
5314    al<g>si\t%0,%c2"
5315   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5316    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5317    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5318                         z10_super_E1,z10_super_E1,z10_super_E1")])
5319
5320 ; alr, al, aly, algr, alg, alrk, algrk
5321 (define_insn "*add<mode>3_carry2_cconly"
5322   [(set (reg CC_REGNUM)
5323         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5324                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5325                  (match_dup 2)))
5326    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5327   "s390_match_ccmode (insn, CCL1mode)"
5328   "@
5329    al<g>r\t%0,%2
5330    al<g>rk\t%0,%1,%2
5331    al<g>\t%0,%2
5332    al<y>\t%0,%2"
5333   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5334    (set_attr "cpu_facility" "*,z196,*,*")
5335    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5336
5337 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5338 (define_insn "*add<mode>3_cc"
5339   [(set (reg CC_REGNUM)
5340         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5341                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5342                  (const_int 0)))
5343    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5344         (plus:GPR (match_dup 1) (match_dup 2)))]
5345   "s390_match_ccmode (insn, CCLmode)"
5346   "@
5347    al<g>r\t%0,%2
5348    al<g>rk\t%0,%1,%2
5349    al<g>fi\t%0,%2
5350    sl<g>fi\t%0,%n2
5351    al<g>hsik\t%0,%1,%h2
5352    al<g>\t%0,%2
5353    al<y>\t%0,%2
5354    al<g>si\t%0,%c2"
5355   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5356    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5357    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5358                         *,z10_super_E1,z10_super_E1,z10_super_E1")])
5359
5360 ; alr, al, aly, algr, alg, alrk, algrk
5361 (define_insn "*add<mode>3_cconly"
5362   [(set (reg CC_REGNUM)
5363         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5364                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5365                  (const_int 0)))
5366    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5367   "s390_match_ccmode (insn, CCLmode)"
5368   "@
5369    al<g>r\t%0,%2
5370    al<g>rk\t%0,%1,%2
5371    al<g>\t%0,%2
5372    al<y>\t%0,%2"
5373   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5374    (set_attr "cpu_facility" "*,z196,*,*")
5375    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5376
5377 ; alr, al, aly, algr, alg, alrk, algrk
5378 (define_insn "*add<mode>3_cconly2"
5379   [(set (reg CC_REGNUM)
5380         (compare (match_operand:GPR 1 "nonimmediate_operand"    "%0,d,0,0")
5381                  (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5382    (clobber (match_scratch:GPR 0                                "=d,d,d,d"))]
5383   "s390_match_ccmode(insn, CCLmode)"
5384   "@
5385    al<g>r\t%0,%2
5386    al<g>rk\t%0,%1,%2
5387    al<g>\t%0,%2
5388    al<y>\t%0,%2"
5389   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5390    (set_attr "cpu_facility" "*,z196,*,*")
5391    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5392
5393 ; ahi, afi, aghi, agfi, asi, agsi
5394 (define_insn "*add<mode>3_imm_cc"
5395   [(set (reg CC_REGNUM)
5396         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5397                            (match_operand:GPR 2 "const_int_operand"    " K, K,Os, C"))
5398                  (const_int 0)))
5399    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d, d,d,QS")
5400         (plus:GPR (match_dup 1) (match_dup 2)))]
5401   "s390_match_ccmode (insn, CCAmode)
5402    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5403        || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5404            /* Avoid INT32_MIN on 32 bit.  */
5405            && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5406   "@
5407    a<g>hi\t%0,%h2
5408    a<g>hik\t%0,%1,%h2
5409    a<g>fi\t%0,%2
5410    a<g>si\t%0,%c2"
5411   [(set_attr "op_type"      "RI,RIE,RIL,SIY")
5412    (set_attr "cpu_facility" "*,z196,extimm,z10")
5413    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5414
5415 ;
5416 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5417 ;
5418
5419 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5420 ; FIXME: wfadb does not clobber cc
5421 (define_insn "add<mode>3"
5422   [(set (match_operand:FP 0 "register_operand"                 "=f,   f,<vf>")
5423         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
5424                  (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))
5425    (clobber (reg:CC CC_REGNUM))]
5426   "TARGET_HARD_FLOAT"
5427   "@
5428    a<xde><bt>r\t%0,<op1>%2
5429    a<xde>b\t%0,%2
5430    wfadb\t%v0,%v1,%v2"
5431   [(set_attr "op_type"      "<RRer>,RXE,VRR")
5432    (set_attr "type"         "fsimp<mode>")
5433    (set_attr "cpu_facility" "*,*,vec")])
5434
5435 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5436 (define_insn "*add<mode>3_cc"
5437   [(set (reg CC_REGNUM)
5438         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5439                           (match_operand:FP 2 "general_operand"      " f,<Rf>"))
5440                  (match_operand:FP 3 "const0_operand" "")))
5441    (set (match_operand:FP 0 "register_operand" "=f,f")
5442         (plus:FP (match_dup 1) (match_dup 2)))]
5443   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5444   "@
5445    a<xde><bt>r\t%0,<op1>%2
5446    a<xde>b\t%0,%2"
5447   [(set_attr "op_type"  "<RRer>,RXE")
5448    (set_attr "type"     "fsimp<mode>")])
5449
5450 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5451 (define_insn "*add<mode>3_cconly"
5452   [(set (reg CC_REGNUM)
5453         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5454                            (match_operand:FP 2 "general_operand"      " f,<Rf>"))
5455                  (match_operand:FP 3 "const0_operand" "")))
5456    (clobber (match_scratch:FP 0 "=f,f"))]
5457   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5458   "@
5459    a<xde><bt>r\t%0,<op1>%2
5460    a<xde>b\t%0,%2"
5461   [(set_attr "op_type"  "<RRer>,RXE")
5462    (set_attr "type"     "fsimp<mode>")])
5463
5464 ;
5465 ; Pointer add instruction patterns
5466 ;
5467
5468 ; This will match "*la_64"
5469 (define_expand "addptrdi3"
5470   [(set (match_operand:DI 0 "register_operand" "")
5471         (plus:DI (match_operand:DI 1 "register_operand" "")
5472                  (match_operand:DI 2 "nonmemory_operand" "")))]
5473   "TARGET_64BIT"
5474 {
5475   if (GET_CODE (operands[2]) == CONST_INT)
5476     {
5477       HOST_WIDE_INT c = INTVAL (operands[2]);
5478
5479       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5480           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5481         {
5482           operands[2] = force_const_mem (DImode, operands[2]);
5483           operands[2] = force_reg (DImode, operands[2]);
5484         }
5485       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5486         operands[2] = force_reg (DImode, operands[2]);
5487     }
5488 })
5489
5490 ; For 31 bit we have to prevent the generated pattern from matching
5491 ; normal ADDs since la only does a 31 bit add.  This is supposed to
5492 ; match "force_la_31".
5493 (define_expand "addptrsi3"
5494   [(parallel
5495     [(set (match_operand:SI 0 "register_operand" "")
5496           (plus:SI (match_operand:SI 1 "register_operand" "")
5497                    (match_operand:SI 2 "nonmemory_operand" "")))
5498                    (use (const_int 0))])]
5499   "!TARGET_64BIT"
5500 {
5501   if (GET_CODE (operands[2]) == CONST_INT)
5502     {
5503       HOST_WIDE_INT c = INTVAL (operands[2]);
5504
5505       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5506           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5507         {
5508           operands[2] = force_const_mem (SImode, operands[2]);
5509           operands[2] = force_reg (SImode, operands[2]);
5510         }
5511       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5512         operands[2] = force_reg (SImode, operands[2]);
5513     }
5514 })
5515
5516 ;;
5517 ;;- Subtract instructions.
5518 ;;
5519
5520 ;
5521 ; subti3 instruction pattern(s).
5522 ;
5523
5524 (define_expand "subti3"
5525   [(parallel
5526     [(set (match_operand:TI           0 "register_operand" "")
5527           (minus:TI (match_operand:TI 1 "register_operand" "")
5528                     (match_operand:TI 2 "general_operand"  "") ) )
5529      (clobber (reg:CC CC_REGNUM))])]
5530   "TARGET_ZARCH"
5531 {
5532   /* For z13 we have vaq which doesn't set CC.  */
5533   if (TARGET_VX)
5534     {
5535       emit_insn (gen_rtx_SET (operands[0],
5536                               gen_rtx_MINUS (TImode,
5537                                             operands[1],
5538                                             copy_to_mode_reg (TImode, operands[2]))));
5539       DONE;
5540     }
5541 })
5542
5543 (define_insn_and_split "*subti3"
5544   [(set (match_operand:TI           0 "register_operand" "=&d")
5545         (minus:TI (match_operand:TI 1 "register_operand"   "0")
5546                   (match_operand:TI 2 "general_operand"   "do") ) )
5547    (clobber (reg:CC CC_REGNUM))]
5548   "TARGET_ZARCH"
5549   "#"
5550   "&& reload_completed"
5551   [(parallel
5552     [(set (reg:CCL2 CC_REGNUM)
5553           (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5554                         (match_dup 7)))
5555      (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5556    (parallel
5557     [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5558                                   (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5559      (clobber (reg:CC CC_REGNUM))])]
5560   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5561    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5562    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5563    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5564    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5565    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5566   [(set_attr "op_type"      "*")
5567    (set_attr "cpu_facility" "*")])
5568
5569 ;
5570 ; subdi3 instruction pattern(s).
5571 ;
5572
5573 (define_expand "subdi3"
5574   [(parallel
5575     [(set (match_operand:DI 0 "register_operand" "")
5576           (minus:DI (match_operand:DI 1 "register_operand" "")
5577                     (match_operand:DI 2 "general_operand" "")))
5578      (clobber (reg:CC CC_REGNUM))])]
5579   ""
5580   "")
5581
5582 (define_insn "*subdi3_sign"
5583   [(set (match_operand:DI 0 "register_operand" "=d,d")
5584         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5585                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5586    (clobber (reg:CC CC_REGNUM))]
5587   "TARGET_ZARCH"
5588   "@
5589    sgfr\t%0,%2
5590    sgf\t%0,%2"
5591   [(set_attr "op_type"  "RRE,RXY")
5592    (set_attr "z10prop" "z10_c,*")
5593    (set_attr "z196prop" "z196_cracked")])
5594
5595 (define_insn "*subdi3_zero_cc"
5596   [(set (reg CC_REGNUM)
5597         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5598                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5599                  (const_int 0)))
5600    (set (match_operand:DI 0 "register_operand" "=d,d")
5601         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5602   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5603   "@
5604    slgfr\t%0,%2
5605    slgf\t%0,%2"
5606   [(set_attr "op_type"  "RRE,RXY")
5607    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5608
5609 (define_insn "*subdi3_zero_cconly"
5610   [(set (reg CC_REGNUM)
5611         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5612                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5613                  (const_int 0)))
5614    (clobber (match_scratch:DI 0 "=d,d"))]
5615   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5616   "@
5617    slgfr\t%0,%2
5618    slgf\t%0,%2"
5619   [(set_attr "op_type"  "RRE,RXY")
5620    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5621
5622 (define_insn "*subdi3_zero"
5623   [(set (match_operand:DI 0 "register_operand" "=d,d")
5624         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5625                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5626    (clobber (reg:CC CC_REGNUM))]
5627   "TARGET_ZARCH"
5628   "@
5629    slgfr\t%0,%2
5630    slgf\t%0,%2"
5631   [(set_attr "op_type"  "RRE,RXY")
5632    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5633
5634 (define_insn_and_split "*subdi3_31z"
5635   [(set (match_operand:DI 0 "register_operand" "=&d")
5636         (minus:DI (match_operand:DI 1 "register_operand" "0")
5637                   (match_operand:DI 2 "general_operand" "do") ) )
5638    (clobber (reg:CC CC_REGNUM))]
5639   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5640   "#"
5641   "&& reload_completed"
5642   [(parallel
5643     [(set (reg:CCL2 CC_REGNUM)
5644           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5645                         (match_dup 7)))
5646      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5647    (parallel
5648     [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5649                                   (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5650      (clobber (reg:CC CC_REGNUM))])]
5651   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5652    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5653    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5654    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5655    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5656    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5657
5658 (define_insn_and_split "*subdi3_31"
5659   [(set (match_operand:DI 0 "register_operand" "=&d")
5660         (minus:DI (match_operand:DI 1 "register_operand" "0")
5661                   (match_operand:DI 2 "general_operand" "do") ) )
5662    (clobber (reg:CC CC_REGNUM))]
5663   "!TARGET_CPU_ZARCH"
5664   "#"
5665   "&& reload_completed"
5666   [(parallel
5667     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5668      (clobber (reg:CC CC_REGNUM))])
5669    (parallel
5670     [(set (reg:CCL2 CC_REGNUM)
5671           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5672                         (match_dup 7)))
5673      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5674    (set (pc)
5675         (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5676                       (pc)
5677                       (label_ref (match_dup 9))))
5678    (parallel
5679     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5680      (clobber (reg:CC CC_REGNUM))])
5681    (match_dup 9)]
5682   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5683    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5684    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5685    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5686    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5687    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5688    operands[9] = gen_label_rtx ();")
5689
5690 ;
5691 ; subsi3 instruction pattern(s).
5692 ;
5693
5694 (define_expand "subsi3"
5695   [(parallel
5696     [(set (match_operand:SI 0 "register_operand" "")
5697           (minus:SI (match_operand:SI 1 "register_operand" "")
5698                     (match_operand:SI 2 "general_operand" "")))
5699      (clobber (reg:CC CC_REGNUM))])]
5700   ""
5701   "")
5702
5703 (define_insn "*subsi3_sign"
5704   [(set (match_operand:SI 0 "register_operand" "=d,d")
5705         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5706                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5707    (clobber (reg:CC CC_REGNUM))]
5708   ""
5709   "@
5710    sh\t%0,%2
5711    shy\t%0,%2"
5712   [(set_attr "op_type"  "RX,RXY")
5713    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5714
5715 ;
5716 ; sub(di|si)3 instruction pattern(s).
5717 ;
5718
5719 ; sr, s, sy, sgr, sg, srk, sgrk
5720 (define_insn "*sub<mode>3"
5721   [(set (match_operand:GPR 0 "register_operand"           "=d,d,d,d")
5722         (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5723                    (match_operand:GPR 2 "general_operand"  "d,d,R,T") ) )
5724    (clobber (reg:CC CC_REGNUM))]
5725   ""
5726   "@
5727    s<g>r\t%0,%2
5728    s<g>rk\t%0,%1,%2
5729    s<g>\t%0,%2
5730    s<y>\t%0,%2"
5731   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5732    (set_attr "cpu_facility" "*,z196,*,*")
5733    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5734
5735 ; slr, sl, sly, slgr, slg, slrk, slgrk
5736 (define_insn "*sub<mode>3_borrow_cc"
5737   [(set (reg CC_REGNUM)
5738         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5739                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5740                  (match_dup 1)))
5741    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5742         (minus:GPR (match_dup 1) (match_dup 2)))]
5743   "s390_match_ccmode (insn, CCL2mode)"
5744   "@
5745    sl<g>r\t%0,%2
5746    sl<g>rk\t%0,%1,%2
5747    sl<g>\t%0,%2
5748    sl<y>\t%0,%2"
5749   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5750    (set_attr "cpu_facility" "*,z196,*,*")
5751    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5752
5753 ; slr, sl, sly, slgr, slg, slrk, slgrk
5754 (define_insn "*sub<mode>3_borrow_cconly"
5755   [(set (reg CC_REGNUM)
5756         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5757                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5758                  (match_dup 1)))
5759    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5760   "s390_match_ccmode (insn, CCL2mode)"
5761   "@
5762    sl<g>r\t%0,%2
5763    sl<g>rk\t%0,%1,%2
5764    sl<g>\t%0,%2
5765    sl<y>\t%0,%2"
5766   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5767    (set_attr "cpu_facility" "*,z196,*,*")
5768    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5769
5770 ; slr, sl, sly, slgr, slg, slrk, slgrk
5771 (define_insn "*sub<mode>3_cc"
5772   [(set (reg CC_REGNUM)
5773         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5774                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5775                  (const_int 0)))
5776    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5777         (minus:GPR (match_dup 1) (match_dup 2)))]
5778   "s390_match_ccmode (insn, CCLmode)"
5779   "@
5780    sl<g>r\t%0,%2
5781    sl<g>rk\t%0,%1,%2
5782    sl<g>\t%0,%2
5783    sl<y>\t%0,%2"
5784   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5785    (set_attr "cpu_facility" "*,z196,*,*")
5786    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5787
5788 ; slr, sl, sly, slgr, slg, slrk, slgrk
5789 (define_insn "*sub<mode>3_cc2"
5790   [(set (reg CC_REGNUM)
5791         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5792                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5793    (set (match_operand:GPR 0 "register_operand"         "=d,d,d,d")
5794         (minus:GPR (match_dup 1) (match_dup 2)))]
5795   "s390_match_ccmode (insn, CCL3mode)"
5796   "@
5797    sl<g>r\t%0,%2
5798    sl<g>rk\t%0,%1,%2
5799    sl<g>\t%0,%2
5800    sl<y>\t%0,%2"
5801   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5802    (set_attr "cpu_facility" "*,z196,*,*")
5803    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5804
5805 ; slr, sl, sly, slgr, slg, slrk, slgrk
5806 (define_insn "*sub<mode>3_cconly"
5807   [(set (reg CC_REGNUM)
5808         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5809                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5810                  (const_int 0)))
5811    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5812   "s390_match_ccmode (insn, CCLmode)"
5813   "@
5814    sl<g>r\t%0,%2
5815    sl<g>rk\t%0,%1,%2
5816    sl<g>\t%0,%2
5817    sl<y>\t%0,%2"
5818   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5819    (set_attr "cpu_facility" "*,z196,*,*")
5820    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5821
5822
5823 ; slr, sl, sly, slgr, slg, slrk, slgrk
5824 (define_insn "*sub<mode>3_cconly2"
5825   [(set (reg CC_REGNUM)
5826         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5827                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5828    (clobber (match_scratch:GPR 0                        "=d,d,d,d"))]
5829   "s390_match_ccmode (insn, CCL3mode)"
5830   "@
5831    sl<g>r\t%0,%2
5832    sl<g>rk\t%0,%1,%2
5833    sl<g>\t%0,%2
5834    sl<y>\t%0,%2"
5835   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5836    (set_attr "cpu_facility" "*,z196,*,*")
5837    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5838
5839
5840 ;
5841 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5842 ;
5843
5844 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5845 (define_insn "sub<mode>3"
5846   [(set (match_operand:FP           0 "register_operand"   "=f,   f,<vf>")
5847         (minus:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
5848                   (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))
5849    (clobber (reg:CC CC_REGNUM))]
5850   "TARGET_HARD_FLOAT"
5851   "@
5852    s<xde><bt>r\t%0,<op1>%2
5853    s<xde>b\t%0,%2
5854    wfsdb\t%v0,%v1,%v2"
5855   [(set_attr "op_type"      "<RRer>,RXE,VRR")
5856    (set_attr "type"         "fsimp<mode>")
5857    (set_attr "cpu_facility" "*,*,vec")])
5858
5859 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5860 (define_insn "*sub<mode>3_cc"
5861   [(set (reg CC_REGNUM)
5862         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5863                            (match_operand:FP 2 "general_operand"      "f,<Rf>"))
5864                  (match_operand:FP 3 "const0_operand" "")))
5865    (set (match_operand:FP 0 "register_operand" "=f,f")
5866         (minus:FP (match_dup 1) (match_dup 2)))]
5867   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5868   "@
5869    s<xde><bt>r\t%0,<op1>%2
5870    s<xde>b\t%0,%2"
5871   [(set_attr "op_type"  "<RRer>,RXE")
5872    (set_attr "type"     "fsimp<mode>")])
5873
5874 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5875 (define_insn "*sub<mode>3_cconly"
5876   [(set (reg CC_REGNUM)
5877         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5878                            (match_operand:FP 2 "general_operand"      "f,<Rf>"))
5879                  (match_operand:FP 3 "const0_operand" "")))
5880    (clobber (match_scratch:FP 0 "=f,f"))]
5881   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5882   "@
5883    s<xde><bt>r\t%0,<op1>%2
5884    s<xde>b\t%0,%2"
5885   [(set_attr "op_type"  "<RRer>,RXE")
5886    (set_attr "type"     "fsimp<mode>")])
5887
5888
5889 ;;
5890 ;;- Conditional add/subtract instructions.
5891 ;;
5892
5893 ;
5894 ; add(di|si)cc instruction pattern(s).
5895 ;
5896
5897 ; the following 4 patterns are used when the result of an add with
5898 ; carry is checked for an overflow condition
5899
5900 ; op1 + op2 + c < op1
5901
5902 ; alcr, alc, alcgr, alcg
5903 (define_insn "*add<mode>3_alc_carry1_cc"
5904   [(set (reg CC_REGNUM)
5905         (compare
5906           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5907                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5908                     (match_operand:GPR 2 "general_operand" "d,RT"))
5909           (match_dup 1)))
5910    (set (match_operand:GPR 0 "register_operand" "=d,d")
5911         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5912   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5913   "@
5914    alc<g>r\t%0,%2
5915    alc<g>\t%0,%2"
5916   [(set_attr "op_type"  "RRE,RXY")
5917    (set_attr "z196prop" "z196_alone,z196_alone")])
5918
5919 ; alcr, alc, alcgr, alcg
5920 (define_insn "*add<mode>3_alc_carry1_cconly"
5921   [(set (reg CC_REGNUM)
5922         (compare
5923           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5924                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5925                     (match_operand:GPR 2 "general_operand" "d,RT"))
5926           (match_dup 1)))
5927    (clobber (match_scratch:GPR 0 "=d,d"))]
5928   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5929   "@
5930    alc<g>r\t%0,%2
5931    alc<g>\t%0,%2"
5932   [(set_attr "op_type"  "RRE,RXY")
5933    (set_attr "z196prop" "z196_alone,z196_alone")])
5934
5935 ; op1 + op2 + c < op2
5936
5937 ; alcr, alc, alcgr, alcg
5938 (define_insn "*add<mode>3_alc_carry2_cc"
5939   [(set (reg CC_REGNUM)
5940         (compare
5941           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5942                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5943                     (match_operand:GPR 2 "general_operand" "d,RT"))
5944           (match_dup 2)))
5945    (set (match_operand:GPR 0 "register_operand" "=d,d")
5946         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5947   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5948   "@
5949    alc<g>r\t%0,%2
5950    alc<g>\t%0,%2"
5951   [(set_attr "op_type"  "RRE,RXY")])
5952
5953 ; alcr, alc, alcgr, alcg
5954 (define_insn "*add<mode>3_alc_carry2_cconly"
5955   [(set (reg CC_REGNUM)
5956         (compare
5957           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5958                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5959                     (match_operand:GPR 2 "general_operand" "d,RT"))
5960           (match_dup 2)))
5961    (clobber (match_scratch:GPR 0 "=d,d"))]
5962   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5963   "@
5964    alc<g>r\t%0,%2
5965    alc<g>\t%0,%2"
5966   [(set_attr "op_type"  "RRE,RXY")])
5967
5968 ; alcr, alc, alcgr, alcg
5969 (define_insn "*add<mode>3_alc_cc"
5970   [(set (reg CC_REGNUM)
5971         (compare
5972           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5973                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5974                     (match_operand:GPR 2 "general_operand" "d,RT"))
5975           (const_int 0)))
5976    (set (match_operand:GPR 0 "register_operand" "=d,d")
5977         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5978   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5979   "@
5980    alc<g>r\t%0,%2
5981    alc<g>\t%0,%2"
5982   [(set_attr "op_type"  "RRE,RXY")])
5983
5984 ; alcr, alc, alcgr, alcg
5985 (define_insn "*add<mode>3_alc"
5986   [(set (match_operand:GPR 0 "register_operand" "=d,d")
5987         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5988                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5989                   (match_operand:GPR 2 "general_operand" "d,RT")))
5990    (clobber (reg:CC CC_REGNUM))]
5991   "TARGET_CPU_ZARCH"
5992   "@
5993    alc<g>r\t%0,%2
5994    alc<g>\t%0,%2"
5995   [(set_attr "op_type"  "RRE,RXY")])
5996
5997 ; slbr, slb, slbgr, slbg
5998 (define_insn "*sub<mode>3_slb_cc"
5999   [(set (reg CC_REGNUM)
6000         (compare
6001           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6002                                 (match_operand:GPR 2 "general_operand" "d,RT"))
6003                      (match_operand:GPR 3 "s390_slb_comparison" ""))
6004           (const_int 0)))
6005    (set (match_operand:GPR 0 "register_operand" "=d,d")
6006         (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6007   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6008   "@
6009    slb<g>r\t%0,%2
6010    slb<g>\t%0,%2"
6011   [(set_attr "op_type"  "RRE,RXY")
6012    (set_attr "z10prop" "z10_c,*")])
6013
6014 ; slbr, slb, slbgr, slbg
6015 (define_insn "*sub<mode>3_slb"
6016   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6017         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6018                               (match_operand:GPR 2 "general_operand" "d,RT"))
6019                    (match_operand:GPR 3 "s390_slb_comparison" "")))
6020    (clobber (reg:CC CC_REGNUM))]
6021   "TARGET_CPU_ZARCH"
6022   "@
6023    slb<g>r\t%0,%2
6024    slb<g>\t%0,%2"
6025   [(set_attr "op_type"  "RRE,RXY")
6026    (set_attr "z10prop" "z10_c,*")])
6027
6028 (define_expand "add<mode>cc"
6029   [(match_operand:GPR 0 "register_operand" "")
6030    (match_operand 1 "comparison_operator" "")
6031    (match_operand:GPR 2 "register_operand" "")
6032    (match_operand:GPR 3 "const_int_operand" "")]
6033   "TARGET_CPU_ZARCH"
6034   "if (!s390_expand_addcc (GET_CODE (operands[1]),
6035                            XEXP (operands[1], 0), XEXP (operands[1], 1),
6036                            operands[0], operands[2],
6037                            operands[3])) FAIL; DONE;")
6038
6039 ;
6040 ; scond instruction pattern(s).
6041 ;
6042
6043 (define_insn_and_split "*scond<mode>"
6044   [(set (match_operand:GPR 0 "register_operand" "=&d")
6045         (match_operand:GPR 1 "s390_alc_comparison" ""))
6046    (clobber (reg:CC CC_REGNUM))]
6047   "TARGET_CPU_ZARCH"
6048   "#"
6049   "&& reload_completed"
6050   [(set (match_dup 0) (const_int 0))
6051    (parallel
6052     [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6053                                   (match_dup 0)))
6054      (clobber (reg:CC CC_REGNUM))])]
6055   "")
6056
6057 (define_insn_and_split "*scond<mode>_neg"
6058   [(set (match_operand:GPR 0 "register_operand" "=&d")
6059         (match_operand:GPR 1 "s390_slb_comparison" ""))
6060    (clobber (reg:CC CC_REGNUM))]
6061   "TARGET_CPU_ZARCH"
6062   "#"
6063   "&& reload_completed"
6064   [(set (match_dup 0) (const_int 0))
6065    (parallel
6066     [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6067                                    (match_dup 1)))
6068      (clobber (reg:CC CC_REGNUM))])
6069    (parallel
6070     [(set (match_dup 0) (neg:GPR (match_dup 0)))
6071      (clobber (reg:CC CC_REGNUM))])]
6072   "")
6073
6074
6075 (define_expand "cstore<mode>4"
6076   [(set (match_operand:SI 0 "register_operand" "")
6077         (match_operator:SI 1 "s390_scond_operator"
6078          [(match_operand:GPR 2 "register_operand" "")
6079           (match_operand:GPR 3 "general_operand" "")]))]
6080   "TARGET_CPU_ZARCH"
6081   "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6082                            operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6083
6084 (define_expand "cstorecc4"
6085   [(parallel
6086     [(set (match_operand:SI 0 "register_operand" "")
6087           (match_operator:SI 1 "s390_eqne_operator"
6088            [(match_operand:CCZ1 2 "register_operand")
6089             (match_operand 3 "const0_operand")]))
6090      (clobber (reg:CC CC_REGNUM))])]
6091   ""
6092   "emit_insn (gen_sne (operands[0], operands[2]));
6093    if (GET_CODE (operands[1]) == EQ)
6094      emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6095    DONE;")
6096
6097 (define_insn_and_split "sne"
6098   [(set (match_operand:SI 0 "register_operand" "=d")
6099         (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6100                (const_int 0)))
6101    (clobber (reg:CC CC_REGNUM))]
6102   ""
6103   "#"
6104   "reload_completed"
6105   [(parallel
6106     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6107      (clobber (reg:CC CC_REGNUM))])])
6108
6109
6110 ;;
6111 ;; - Conditional move instructions (introduced with z196)
6112 ;;
6113
6114 (define_expand "mov<mode>cc"
6115   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6116         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6117                           (match_operand:GPR 2 "nonimmediate_operand" "")
6118                           (match_operand:GPR 3 "nonimmediate_operand" "")))]
6119   "TARGET_Z196"
6120 {
6121   /* Emit the comparison insn in case we do not already have a comparison result.  */
6122   if (!s390_comparison (operands[1], VOIDmode))
6123     operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6124                                      XEXP (operands[1], 0),
6125                                      XEXP (operands[1], 1));
6126 })
6127
6128 ; locr, loc, stoc, locgr, locg, stocg
6129 (define_insn_and_split "*mov<mode>cc"
6130   [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d, d, d,QS,QS,&d")
6131         (if_then_else:GPR
6132           (match_operator 1 "s390_comparison"
6133             [(match_operand 2 "cc_reg_operand"        " c,c, c, c, c, c, c")
6134              (match_operand 5 "const_int_operand"     "")])
6135           (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
6136           (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
6137   "TARGET_Z196"
6138   "@
6139    loc<g>r%C1\t%0,%3
6140    loc<g>r%D1\t%0,%4
6141    loc<g>%C1\t%0,%3
6142    loc<g>%D1\t%0,%4
6143    stoc<g>%C1\t%3,%0
6144    stoc<g>%D1\t%4,%0
6145    #"
6146   "&& reload_completed
6147    && MEM_P (operands[3]) && MEM_P (operands[4])"
6148   [(set (match_dup 0)
6149         (if_then_else:GPR
6150          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6151          (match_dup 3)
6152          (match_dup 0)))
6153    (set (match_dup 0)
6154         (if_then_else:GPR
6155          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6156          (match_dup 0)
6157          (match_dup 4)))]
6158   ""
6159   [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
6160
6161 ;;
6162 ;;- Multiply instructions.
6163 ;;
6164
6165 ;
6166 ; muldi3 instruction pattern(s).
6167 ;
6168
6169 (define_insn "*muldi3_sign"
6170   [(set (match_operand:DI 0 "register_operand" "=d,d")
6171         (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
6172                  (match_operand:DI 1 "register_operand" "0,0")))]
6173   "TARGET_ZARCH"
6174   "@
6175    msgfr\t%0,%2
6176    msgf\t%0,%2"
6177   [(set_attr "op_type"      "RRE,RXY")
6178    (set_attr "type"         "imuldi")])
6179
6180 (define_insn "muldi3"
6181   [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6182         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6183                  (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
6184   "TARGET_ZARCH"
6185   "@
6186    msgr\t%0,%2
6187    mghi\t%0,%h2
6188    msg\t%0,%2
6189    msgfi\t%0,%2"
6190   [(set_attr "op_type"      "RRE,RI,RXY,RIL")
6191    (set_attr "type"         "imuldi")
6192    (set_attr "cpu_facility" "*,*,*,z10")])
6193
6194 ;
6195 ; mulsi3 instruction pattern(s).
6196 ;
6197
6198 (define_insn "*mulsi3_sign"
6199   [(set (match_operand:SI 0 "register_operand" "=d,d")
6200         (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6201                  (match_operand:SI 1 "register_operand" "0,0")))]
6202   ""
6203   "@
6204    mh\t%0,%2
6205    mhy\t%0,%2"
6206   [(set_attr "op_type"      "RX,RXY")
6207    (set_attr "type"         "imulhi")
6208    (set_attr "cpu_facility" "*,z10")])
6209
6210 (define_insn "mulsi3"
6211   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6212         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6213                   (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6214   ""
6215   "@
6216    msr\t%0,%2
6217    mhi\t%0,%h2
6218    ms\t%0,%2
6219    msy\t%0,%2
6220    msfi\t%0,%2"
6221   [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
6222    (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
6223    (set_attr "cpu_facility" "*,*,*,*,z10")])
6224
6225 ;
6226 ; mulsidi3 instruction pattern(s).
6227 ;
6228
6229 (define_insn "mulsidi3"
6230   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6231         (mult:DI (sign_extend:DI
6232                    (match_operand:SI 1 "register_operand" "%0,0,0"))
6233                  (sign_extend:DI
6234                    (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6235   "!TARGET_ZARCH"
6236   "@
6237    mr\t%0,%2
6238    m\t%0,%2
6239    mfy\t%0,%2"
6240   [(set_attr "op_type"      "RR,RX,RXY")
6241    (set_attr "type"         "imulsi")
6242    (set_attr "cpu_facility" "*,*,z10")])
6243
6244 ;
6245 ; umul instruction pattern(s).
6246 ;
6247
6248 ; mlr, ml, mlgr, mlg
6249 (define_insn "umul<dwh><mode>3"
6250   [(set (match_operand:DW 0 "register_operand"                   "=d, d")
6251         (mult:DW (zero_extend:DW
6252                    (match_operand:<DWH> 1 "register_operand"     "%0, 0"))
6253                  (zero_extend:DW
6254                    (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
6255   "TARGET_CPU_ZARCH"
6256   "@
6257    ml<tg>r\t%0,%2
6258    ml<tg>\t%0,%2"
6259   [(set_attr "op_type"  "RRE,RXY")
6260    (set_attr "type"     "imul<dwh>")])
6261
6262 ;
6263 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6264 ;
6265
6266 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6267 (define_insn "mul<mode>3"
6268   [(set (match_operand:FP          0 "register_operand"        "=f,   f,<vf>")
6269         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
6270                  (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))]
6271   "TARGET_HARD_FLOAT"
6272   "@
6273    m<xdee><bt>r\t%0,<op1>%2
6274    m<xdee>b\t%0,%2
6275    wfmdb\t%v0,%v1,%v2"
6276   [(set_attr "op_type"      "<RRer>,RXE,VRR")
6277    (set_attr "type"         "fmul<mode>")
6278    (set_attr "cpu_facility" "*,*,vec")])
6279
6280 ; madbr, maebr, maxb, madb, maeb
6281 (define_insn "fma<mode>4"
6282   [(set (match_operand:DSF          0 "register_operand"     "=f,f,<vf>")
6283         (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
6284                  (match_operand:DSF 2 "nonimmediate_operand"  "f,R,<vf>")
6285                  (match_operand:DSF 3 "register_operand"      "0,0,<v0>")))]
6286   "TARGET_HARD_FLOAT"
6287   "@
6288    ma<xde>br\t%0,%1,%2
6289    ma<xde>b\t%0,%1,%2
6290    wfmadb\t%v0,%v1,%v2,%v3"
6291   [(set_attr "op_type"      "RRE,RXE,VRR")
6292    (set_attr "type"         "fmadd<mode>")
6293    (set_attr "cpu_facility" "*,*,vec")])
6294
6295 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6296 (define_insn "fms<mode>4"
6297   [(set (match_operand:DSF                   0 "register_operand"     "=f,f,<vf>")
6298         (fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,<vf>")
6299                  (match_operand:DSF          2 "nonimmediate_operand"  "f,R,<vf>")
6300                  (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,<v0>"))))]
6301   "TARGET_HARD_FLOAT"
6302   "@
6303    ms<xde>br\t%0,%1,%2
6304    ms<xde>b\t%0,%1,%2
6305    wfmsdb\t%v0,%v1,%v2,%v3"
6306   [(set_attr "op_type"      "RRE,RXE,VRR")
6307    (set_attr "type"         "fmadd<mode>")
6308    (set_attr "cpu_facility" "*,*,vec")])
6309
6310 ;;
6311 ;;- Divide and modulo instructions.
6312 ;;
6313
6314 ;
6315 ; divmoddi4 instruction pattern(s).
6316 ;
6317
6318 (define_expand "divmoddi4"
6319   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6320                    (div:DI (match_operand:DI 1 "register_operand" "")
6321                            (match_operand:DI 2 "general_operand" "")))
6322               (set (match_operand:DI 3 "general_operand" "")
6323                    (mod:DI (match_dup 1) (match_dup 2)))])
6324    (clobber (match_dup 4))]
6325   "TARGET_ZARCH"
6326 {
6327   rtx insn, div_equal, mod_equal;
6328
6329   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6330   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6331
6332   operands[4] = gen_reg_rtx(TImode);
6333   emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6334
6335   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6336   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6337
6338   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6339   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6340
6341   DONE;
6342 })
6343
6344 (define_insn "divmodtidi3"
6345   [(set (match_operand:TI 0 "register_operand" "=d,d")
6346         (ior:TI
6347           (ashift:TI
6348             (zero_extend:TI
6349               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6350                       (match_operand:DI 2 "general_operand" "d,RT")))
6351             (const_int 64))
6352           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6353   "TARGET_ZARCH"
6354   "@
6355    dsgr\t%0,%2
6356    dsg\t%0,%2"
6357   [(set_attr "op_type"  "RRE,RXY")
6358    (set_attr "type"     "idiv")])
6359
6360 (define_insn "divmodtisi3"
6361   [(set (match_operand:TI 0 "register_operand" "=d,d")
6362         (ior:TI
6363           (ashift:TI
6364             (zero_extend:TI
6365               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6366                       (sign_extend:DI
6367                         (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6368             (const_int 64))
6369           (zero_extend:TI
6370             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6371   "TARGET_ZARCH"
6372   "@
6373    dsgfr\t%0,%2
6374    dsgf\t%0,%2"
6375   [(set_attr "op_type"  "RRE,RXY")
6376    (set_attr "type"     "idiv")])
6377
6378 ;
6379 ; udivmoddi4 instruction pattern(s).
6380 ;
6381
6382 (define_expand "udivmoddi4"
6383   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6384                    (udiv:DI (match_operand:DI 1 "general_operand" "")
6385                             (match_operand:DI 2 "nonimmediate_operand" "")))
6386               (set (match_operand:DI 3 "general_operand" "")
6387                    (umod:DI (match_dup 1) (match_dup 2)))])
6388    (clobber (match_dup 4))]
6389   "TARGET_ZARCH"
6390 {
6391   rtx insn, div_equal, mod_equal, equal;
6392
6393   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6394   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6395   equal = gen_rtx_IOR (TImode,
6396                        gen_rtx_ASHIFT (TImode,
6397                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6398                                        GEN_INT (64)),
6399                        gen_rtx_ZERO_EXTEND (TImode, div_equal));
6400
6401   operands[4] = gen_reg_rtx(TImode);
6402   emit_clobber (operands[4]);
6403   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6404   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6405
6406   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6407   set_unique_reg_note (insn, REG_EQUAL, equal);
6408
6409   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6410   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6411
6412   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6413   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6414
6415   DONE;
6416 })
6417
6418 (define_insn "udivmodtidi3"
6419   [(set (match_operand:TI 0 "register_operand" "=d,d")
6420         (ior:TI
6421           (ashift:TI
6422             (zero_extend:TI
6423               (truncate:DI
6424                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6425                          (zero_extend:TI
6426                            (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6427             (const_int 64))
6428           (zero_extend:TI
6429             (truncate:DI
6430               (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6431   "TARGET_ZARCH"
6432   "@
6433    dlgr\t%0,%2
6434    dlg\t%0,%2"
6435   [(set_attr "op_type"  "RRE,RXY")
6436    (set_attr "type"     "idiv")])
6437
6438 ;
6439 ; divmodsi4 instruction pattern(s).
6440 ;
6441
6442 (define_expand "divmodsi4"
6443   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6444                    (div:SI (match_operand:SI 1 "general_operand" "")
6445                            (match_operand:SI 2 "nonimmediate_operand" "")))
6446               (set (match_operand:SI 3 "general_operand" "")
6447                    (mod:SI (match_dup 1) (match_dup 2)))])
6448    (clobber (match_dup 4))]
6449   "!TARGET_ZARCH"
6450 {
6451   rtx insn, div_equal, mod_equal, equal;
6452
6453   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6454   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6455   equal = gen_rtx_IOR (DImode,
6456                        gen_rtx_ASHIFT (DImode,
6457                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6458                                        GEN_INT (32)),
6459                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6460
6461   operands[4] = gen_reg_rtx(DImode);
6462   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6463
6464   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6465   set_unique_reg_note (insn, REG_EQUAL, equal);
6466
6467   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6468   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6469
6470   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6471   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6472
6473   DONE;
6474 })
6475
6476 (define_insn "divmoddisi3"
6477   [(set (match_operand:DI 0 "register_operand" "=d,d")
6478         (ior:DI
6479           (ashift:DI
6480             (zero_extend:DI
6481               (truncate:SI
6482                 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6483                         (sign_extend:DI
6484                           (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6485             (const_int 32))
6486           (zero_extend:DI
6487             (truncate:SI
6488               (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6489   "!TARGET_ZARCH"
6490   "@
6491    dr\t%0,%2
6492    d\t%0,%2"
6493   [(set_attr "op_type"  "RR,RX")
6494    (set_attr "type"     "idiv")])
6495
6496 ;
6497 ; udivsi3 and umodsi3 instruction pattern(s).
6498 ;
6499
6500 (define_expand "udivmodsi4"
6501   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6502                    (udiv:SI (match_operand:SI 1 "general_operand" "")
6503                             (match_operand:SI 2 "nonimmediate_operand" "")))
6504               (set (match_operand:SI 3 "general_operand" "")
6505                    (umod:SI (match_dup 1) (match_dup 2)))])
6506    (clobber (match_dup 4))]
6507   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6508 {
6509   rtx insn, div_equal, mod_equal, equal;
6510
6511   div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6512   mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6513   equal = gen_rtx_IOR (DImode,
6514                        gen_rtx_ASHIFT (DImode,
6515                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6516                                        GEN_INT (32)),
6517                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6518
6519   operands[4] = gen_reg_rtx(DImode);
6520   emit_clobber (operands[4]);
6521   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6522   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6523
6524   insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6525   set_unique_reg_note (insn, REG_EQUAL, equal);
6526
6527   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6528   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6529
6530   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6531   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6532
6533   DONE;
6534 })
6535
6536 (define_insn "udivmoddisi3"
6537   [(set (match_operand:DI 0 "register_operand" "=d,d")
6538         (ior:DI
6539           (ashift:DI
6540             (zero_extend:DI
6541               (truncate:SI
6542                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6543                          (zero_extend:DI
6544                            (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6545             (const_int 32))
6546           (zero_extend:DI
6547             (truncate:SI
6548               (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6549   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6550   "@
6551    dlr\t%0,%2
6552    dl\t%0,%2"
6553   [(set_attr "op_type"  "RRE,RXY")
6554    (set_attr "type"     "idiv")])
6555
6556 (define_expand "udivsi3"
6557   [(set (match_operand:SI 0 "register_operand" "=d")
6558         (udiv:SI (match_operand:SI 1 "general_operand" "")
6559                  (match_operand:SI 2 "general_operand" "")))
6560    (clobber (match_dup 3))]
6561   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6562 {
6563   rtx insn, udiv_equal, umod_equal, equal;
6564
6565   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6566   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6567   equal = gen_rtx_IOR (DImode,
6568                        gen_rtx_ASHIFT (DImode,
6569                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6570                                        GEN_INT (32)),
6571                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6572
6573   operands[3] = gen_reg_rtx (DImode);
6574
6575   if (CONSTANT_P (operands[2]))
6576     {
6577       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6578         {
6579           rtx_code_label *label1 = gen_label_rtx ();
6580
6581           operands[1] = make_safe_from (operands[1], operands[0]);
6582           emit_move_insn (operands[0], const0_rtx);
6583           emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6584                                    SImode, 1, label1);
6585           emit_move_insn (operands[0], const1_rtx);
6586           emit_label (label1);
6587         }
6588       else
6589         {
6590           operands[2] = force_reg (SImode, operands[2]);
6591           operands[2] = make_safe_from (operands[2], operands[0]);
6592
6593           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6594           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6595                                              operands[2]));
6596           set_unique_reg_note (insn, REG_EQUAL, equal);
6597
6598           insn = emit_move_insn (operands[0],
6599                                  gen_lowpart (SImode, operands[3]));
6600           set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6601         }
6602     }
6603   else
6604     {
6605       rtx_code_label *label1 = gen_label_rtx ();
6606       rtx_code_label *label2 = gen_label_rtx ();
6607       rtx_code_label *label3 = gen_label_rtx ();
6608
6609       operands[1] = force_reg (SImode, operands[1]);
6610       operands[1] = make_safe_from (operands[1], operands[0]);
6611       operands[2] = force_reg (SImode, operands[2]);
6612       operands[2] = make_safe_from (operands[2], operands[0]);
6613
6614       emit_move_insn (operands[0], const0_rtx);
6615       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6616                                SImode, 1, label3);
6617       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6618                                SImode, 0, label2);
6619       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6620                                SImode, 0, label1);
6621       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6622       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6623                                          operands[2]));
6624       set_unique_reg_note (insn, REG_EQUAL, equal);
6625
6626       insn = emit_move_insn (operands[0],
6627                              gen_lowpart (SImode, operands[3]));
6628       set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6629
6630       emit_jump (label3);
6631       emit_label (label1);
6632       emit_move_insn (operands[0], operands[1]);
6633       emit_jump (label3);
6634       emit_label (label2);
6635       emit_move_insn (operands[0], const1_rtx);
6636       emit_label (label3);
6637     }
6638   emit_move_insn (operands[0], operands[0]);
6639   DONE;
6640 })
6641
6642 (define_expand "umodsi3"
6643   [(set (match_operand:SI 0 "register_operand" "=d")
6644         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6645                  (match_operand:SI 2 "nonimmediate_operand" "")))
6646    (clobber (match_dup 3))]
6647   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6648 {
6649   rtx insn, udiv_equal, umod_equal, equal;
6650
6651   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6652   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6653   equal = gen_rtx_IOR (DImode,
6654                        gen_rtx_ASHIFT (DImode,
6655                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6656                                        GEN_INT (32)),
6657                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6658
6659   operands[3] = gen_reg_rtx (DImode);
6660
6661   if (CONSTANT_P (operands[2]))
6662     {
6663       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6664         {
6665           rtx_code_label *label1 = gen_label_rtx ();
6666
6667           operands[1] = make_safe_from (operands[1], operands[0]);
6668           emit_move_insn (operands[0], operands[1]);
6669           emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6670                                    SImode, 1, label1);
6671           emit_insn (gen_abssi2 (operands[0], operands[2]));
6672           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6673           emit_label (label1);
6674         }
6675       else
6676         {
6677           operands[2] = force_reg (SImode, operands[2]);
6678           operands[2] = make_safe_from (operands[2], operands[0]);
6679
6680           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6681           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6682                                              operands[2]));
6683           set_unique_reg_note (insn, REG_EQUAL, equal);
6684
6685           insn = emit_move_insn (operands[0],
6686                                  gen_highpart (SImode, operands[3]));
6687           set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6688         }
6689     }
6690   else
6691     {
6692       rtx_code_label *label1 = gen_label_rtx ();
6693       rtx_code_label *label2 = gen_label_rtx ();
6694       rtx_code_label *label3 = gen_label_rtx ();
6695
6696       operands[1] = force_reg (SImode, operands[1]);
6697       operands[1] = make_safe_from (operands[1], operands[0]);
6698       operands[2] = force_reg (SImode, operands[2]);
6699       operands[2] = make_safe_from (operands[2], operands[0]);
6700
6701       emit_move_insn(operands[0], operands[1]);
6702       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6703                                SImode, 1, label3);
6704       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6705                                SImode, 0, label2);
6706       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6707                                SImode, 0, label1);
6708       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6709       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6710                                          operands[2]));
6711       set_unique_reg_note (insn, REG_EQUAL, equal);
6712
6713       insn = emit_move_insn (operands[0],
6714                              gen_highpart (SImode, operands[3]));
6715       set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6716
6717       emit_jump (label3);
6718       emit_label (label1);
6719       emit_move_insn (operands[0], const0_rtx);
6720       emit_jump (label3);
6721       emit_label (label2);
6722       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6723       emit_label (label3);
6724     }
6725   DONE;
6726 })
6727
6728 ;
6729 ; div(df|sf)3 instruction pattern(s).
6730 ;
6731
6732 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6733 (define_insn "div<mode>3"
6734   [(set (match_operand:FP         0 "register_operand"   "=f,   f,<vf>")
6735         (div:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
6736                 (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))]
6737   "TARGET_HARD_FLOAT"
6738   "@
6739    d<xde><bt>r\t%0,<op1>%2
6740    d<xde>b\t%0,%2
6741    wfddb\t%v0,%v1,%v2"
6742   [(set_attr "op_type"      "<RRer>,RXE,VRR")
6743    (set_attr "type"         "fdiv<mode>")
6744    (set_attr "cpu_facility" "*,*,vec")])
6745
6746
6747 ;;
6748 ;;- And instructions.
6749 ;;
6750
6751 (define_expand "and<mode>3"
6752   [(set (match_operand:INT 0 "nonimmediate_operand" "")
6753         (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6754                  (match_operand:INT 2 "general_operand" "")))
6755    (clobber (reg:CC CC_REGNUM))]
6756   ""
6757   "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6758
6759 ;
6760 ; anddi3 instruction pattern(s).
6761 ;
6762
6763 (define_insn "*anddi3_cc"
6764   [(set (reg CC_REGNUM)
6765         (compare
6766           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6767                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6768           (const_int 0)))
6769    (set (match_operand:DI 0 "register_operand"               "=d,d, d,    d")
6770         (and:DI (match_dup 1) (match_dup 2)))]
6771   "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6772   "@
6773    ngr\t%0,%2
6774    ngrk\t%0,%1,%2
6775    ng\t%0,%2
6776    risbg\t%0,%1,%s2,128+%e2,0"
6777   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6778    (set_attr "cpu_facility" "*,z196,*,z10")
6779    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6780
6781 (define_insn "*anddi3_cconly"
6782   [(set (reg CC_REGNUM)
6783         (compare
6784           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6785                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6786                  (const_int 0)))
6787    (clobber (match_scratch:DI 0                              "=d,d, d,    d"))]
6788   "TARGET_ZARCH
6789    && s390_match_ccmode(insn, CCTmode)
6790    /* Do not steal TM patterns.  */
6791    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6792   "@
6793    ngr\t%0,%2
6794    ngrk\t%0,%1,%2
6795    ng\t%0,%2
6796    risbg\t%0,%1,%s2,128+%e2,0"
6797   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6798    (set_attr "cpu_facility" "*,z196,*,z10")
6799    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6800
6801 (define_insn "*anddi3"
6802   [(set (match_operand:DI 0 "nonimmediate_operand"
6803             "=d,d,    d,    d,    d,    d,    d,    d,d,d, d,    d,   AQ,Q")
6804         (and:DI
6805           (match_operand:DI 1 "nonimmediate_operand"
6806             "%d,o,    0,    0,    0,    0,    0,    0,0,d, 0,    d,    0,0")
6807           (match_operand:DI 2 "general_operand"
6808             "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6809    (clobber (reg:CC CC_REGNUM))]
6810   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6811   "@
6812    #
6813    #
6814    nihh\t%0,%j2
6815    nihl\t%0,%j2
6816    nilh\t%0,%j2
6817    nill\t%0,%j2
6818    nihf\t%0,%m2
6819    nilf\t%0,%m2
6820    ngr\t%0,%2
6821    ngrk\t%0,%1,%2
6822    ng\t%0,%2
6823    risbg\t%0,%1,%s2,128+%e2,0
6824    #
6825    #"
6826   [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6827    (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6828    (set_attr "z10prop" "*,
6829                         *,
6830                         z10_super_E1,
6831                         z10_super_E1,
6832                         z10_super_E1,
6833                         z10_super_E1,
6834                         z10_super_E1,
6835                         z10_super_E1,
6836                         z10_super_E1,
6837                         *,
6838                         z10_super_E1,
6839                         z10_super_E1,
6840                         *,
6841                         *")])
6842
6843 (define_split
6844   [(set (match_operand:DI 0 "s_operand" "")
6845         (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6846    (clobber (reg:CC CC_REGNUM))]
6847   "reload_completed"
6848   [(parallel
6849     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6850      (clobber (reg:CC CC_REGNUM))])]
6851   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6852
6853 ;; These two are what combine generates for (ashift (zero_extract)).
6854 (define_insn "*extzv_<mode>_srl"
6855   [(set (match_operand:GPR 0 "register_operand" "=d")
6856         (and:GPR (lshiftrt:GPR
6857                    (match_operand:GPR 1 "register_operand" "d")
6858                    (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6859                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6860    (clobber (reg:CC CC_REGNUM))]
6861   "TARGET_Z10
6862    /* Note that even for the SImode pattern, the rotate is always DImode.  */
6863    && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6864                            INTVAL (operands[3]))"
6865   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6866   [(set_attr "op_type" "RIE")
6867    (set_attr "z10prop" "z10_super_E1")])
6868
6869 (define_insn "*extzv_<mode>_sll"
6870   [(set (match_operand:GPR 0 "register_operand" "=d")
6871         (and:GPR (ashift:GPR
6872                   (match_operand:GPR 1 "register_operand" "d")
6873                   (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6874                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6875    (clobber (reg:CC CC_REGNUM))]
6876   "TARGET_Z10
6877    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6878                            INTVAL (operands[3]))"
6879   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6880   [(set_attr "op_type" "RIE")
6881    (set_attr "z10prop" "z10_super_E1")])
6882
6883
6884 ;
6885 ; andsi3 instruction pattern(s).
6886 ;
6887
6888 (define_insn "*andsi3_cc"
6889   [(set (reg CC_REGNUM)
6890         (compare
6891           (and:SI
6892             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6893             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6894           (const_int 0)))
6895    (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
6896         (and:SI (match_dup 1) (match_dup 2)))]
6897   "s390_match_ccmode(insn, CCTmode)"
6898   "@
6899    nilf\t%0,%o2
6900    nr\t%0,%2
6901    nrk\t%0,%1,%2
6902    n\t%0,%2
6903    ny\t%0,%2
6904    risbg\t%0,%1,%t2,128+%f2,0"
6905   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6906    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6907    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6908                         z10_super_E1,z10_super_E1,z10_super_E1")])
6909
6910 (define_insn "*andsi3_cconly"
6911   [(set (reg CC_REGNUM)
6912         (compare
6913           (and:SI
6914             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6915             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6916           (const_int 0)))
6917    (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
6918   "s390_match_ccmode(insn, CCTmode)
6919    /* Do not steal TM patterns.  */
6920    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6921   "@
6922    nilf\t%0,%o2
6923    nr\t%0,%2
6924    nrk\t%0,%1,%2
6925    n\t%0,%2
6926    ny\t%0,%2
6927    risbg\t%0,%1,%t2,128+%f2,0"
6928   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6929    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6930    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6931                         z10_super_E1,z10_super_E1,z10_super_E1")])
6932
6933 (define_insn "*andsi3_zarch"
6934   [(set (match_operand:SI 0 "nonimmediate_operand"
6935                             "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
6936         (and:SI (match_operand:SI 1 "nonimmediate_operand"
6937                             "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
6938                 (match_operand:SI 2 "general_operand"
6939                             " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6940    (clobber (reg:CC CC_REGNUM))]
6941   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6942   "@
6943    #
6944    #
6945    nilh\t%0,%j2
6946    nill\t%0,%j2
6947    nilf\t%0,%o2
6948    nr\t%0,%2
6949    nrk\t%0,%1,%2
6950    n\t%0,%2
6951    ny\t%0,%2
6952    risbg\t%0,%1,%t2,128+%f2,0
6953    #
6954    #"
6955   [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6956    (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6957    (set_attr "z10prop" "*,
6958                         *,
6959                         z10_super_E1,
6960                         z10_super_E1,
6961                         z10_super_E1,
6962                         z10_super_E1,
6963                         *,
6964                         z10_super_E1,
6965                         z10_super_E1,
6966                         z10_super_E1,
6967                         *,
6968                         *")])
6969
6970 (define_insn "*andsi3_esa"
6971   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,   AQ,Q")
6972         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,    0,0")
6973                 (match_operand:SI 2 "general_operand"      " d,R,NxQSF,Q")))
6974    (clobber (reg:CC CC_REGNUM))]
6975   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6976   "@
6977    nr\t%0,%2
6978    n\t%0,%2
6979    #
6980    #"
6981   [(set_attr "op_type"  "RR,RX,SI,SS")
6982    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6983
6984
6985 (define_split
6986   [(set (match_operand:SI 0 "s_operand" "")
6987         (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6988    (clobber (reg:CC CC_REGNUM))]
6989   "reload_completed"
6990   [(parallel
6991     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6992      (clobber (reg:CC CC_REGNUM))])]
6993   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6994
6995 ;
6996 ; andhi3 instruction pattern(s).
6997 ;
6998
6999 (define_insn "*andhi3_zarch"
7000   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7001         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7002                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQHF,Q")))
7003    (clobber (reg:CC CC_REGNUM))]
7004   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7005   "@
7006    nr\t%0,%2
7007    nrk\t%0,%1,%2
7008    nill\t%0,%x2
7009    #
7010    #"
7011   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7012    (set_attr "cpu_facility" "*,z196,*,*,*")
7013    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7014 ])
7015
7016 (define_insn "*andhi3_esa"
7017   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7018         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7019                 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7020    (clobber (reg:CC CC_REGNUM))]
7021   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7022   "@
7023    nr\t%0,%2
7024    #
7025    #"
7026   [(set_attr "op_type"  "RR,SI,SS")
7027    (set_attr "z10prop" "z10_super_E1,*,*")
7028 ])
7029
7030 (define_split
7031   [(set (match_operand:HI 0 "s_operand" "")
7032         (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7033    (clobber (reg:CC CC_REGNUM))]
7034   "reload_completed"
7035   [(parallel
7036     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7037      (clobber (reg:CC CC_REGNUM))])]
7038   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7039
7040 ;
7041 ; andqi3 instruction pattern(s).
7042 ;
7043
7044 (define_insn "*andqi3_zarch"
7045   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7046         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7047                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7048    (clobber (reg:CC CC_REGNUM))]
7049   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7050   "@
7051    nr\t%0,%2
7052    nrk\t%0,%1,%2
7053    nill\t%0,%b2
7054    ni\t%S0,%b2
7055    niy\t%S0,%b2
7056    #"
7057   [(set_attr "op_type"  "RR,RRF,RI,SI,SIY,SS")
7058    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7059    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7060
7061 (define_insn "*andqi3_esa"
7062   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7063         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7064                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7065    (clobber (reg:CC CC_REGNUM))]
7066   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7067   "@
7068    nr\t%0,%2
7069    ni\t%S0,%b2
7070    #"
7071   [(set_attr "op_type"  "RR,SI,SS")
7072    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7073
7074 ;
7075 ; Block and (NC) patterns.
7076 ;
7077
7078 (define_insn "*nc"
7079   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7080         (and:BLK (match_dup 0)
7081                  (match_operand:BLK 1 "memory_operand" "Q")))
7082    (use (match_operand 2 "const_int_operand" "n"))
7083    (clobber (reg:CC CC_REGNUM))]
7084   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7085   "nc\t%O0(%2,%R0),%S1"
7086   [(set_attr "op_type" "SS")
7087    (set_attr "z196prop" "z196_cracked")])
7088
7089 (define_split
7090   [(set (match_operand 0 "memory_operand" "")
7091         (and (match_dup 0)
7092              (match_operand 1 "memory_operand" "")))
7093    (clobber (reg:CC CC_REGNUM))]
7094   "reload_completed
7095    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7096    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7097   [(parallel
7098     [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7099      (use (match_dup 2))
7100      (clobber (reg:CC CC_REGNUM))])]
7101 {
7102   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7103   operands[0] = adjust_address (operands[0], BLKmode, 0);
7104   operands[1] = adjust_address (operands[1], BLKmode, 0);
7105 })
7106
7107 (define_peephole2
7108   [(parallel
7109     [(set (match_operand:BLK 0 "memory_operand" "")
7110           (and:BLK (match_dup 0)
7111                    (match_operand:BLK 1 "memory_operand" "")))
7112      (use (match_operand 2 "const_int_operand" ""))
7113      (clobber (reg:CC CC_REGNUM))])
7114    (parallel
7115     [(set (match_operand:BLK 3 "memory_operand" "")
7116           (and:BLK (match_dup 3)
7117                    (match_operand:BLK 4 "memory_operand" "")))
7118      (use (match_operand 5 "const_int_operand" ""))
7119      (clobber (reg:CC CC_REGNUM))])]
7120   "s390_offset_p (operands[0], operands[3], operands[2])
7121    && s390_offset_p (operands[1], operands[4], operands[2])
7122    && !s390_overlap_p (operands[0], operands[1],
7123                        INTVAL (operands[2]) + INTVAL (operands[5]))
7124    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7125   [(parallel
7126     [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7127      (use (match_dup 8))
7128      (clobber (reg:CC CC_REGNUM))])]
7129   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7130    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7131    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7132
7133
7134 ;;
7135 ;;- Bit set (inclusive or) instructions.
7136 ;;
7137
7138 (define_expand "ior<mode>3"
7139   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7140         (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7141                  (match_operand:INT 2 "general_operand" "")))
7142    (clobber (reg:CC CC_REGNUM))]
7143   ""
7144   "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7145
7146 ;
7147 ; iordi3 instruction pattern(s).
7148 ;
7149
7150 (define_insn "*iordi3_cc"
7151   [(set (reg CC_REGNUM)
7152         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7153                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7154                  (const_int 0)))
7155    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7156         (ior:DI (match_dup 1) (match_dup 2)))]
7157   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7158   "@
7159    ogr\t%0,%2
7160    ogrk\t%0,%1,%2
7161    og\t%0,%2"
7162   [(set_attr "op_type"  "RRE,RRF,RXY")
7163    (set_attr "cpu_facility" "*,z196,*")
7164    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7165
7166 (define_insn "*iordi3_cconly"
7167   [(set (reg CC_REGNUM)
7168         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7169                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7170                  (const_int 0)))
7171    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7172   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7173   "@
7174    ogr\t%0,%2
7175    ogrk\t%0,%1,%2
7176    og\t%0,%2"
7177   [(set_attr "op_type"  "RRE,RRF,RXY")
7178    (set_attr "cpu_facility" "*,z196,*")
7179    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7180
7181 (define_insn "*iordi3"
7182   [(set (match_operand:DI 0 "nonimmediate_operand"
7183                                "=d,    d,    d,    d,    d,    d,d,d, d,   AQ,Q")
7184         (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7185                             "   %0,    0,    0,    0,    0,    0,0,d, 0,    0,0")
7186                 (match_operand:DI 2 "general_operand"
7187                             "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7188    (clobber (reg:CC CC_REGNUM))]
7189   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7190   "@
7191    oihh\t%0,%i2
7192    oihl\t%0,%i2
7193    oilh\t%0,%i2
7194    oill\t%0,%i2
7195    oihf\t%0,%k2
7196    oilf\t%0,%k2
7197    ogr\t%0,%2
7198    ogrk\t%0,%1,%2
7199    og\t%0,%2
7200    #
7201    #"
7202   [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7203    (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7204    (set_attr "z10prop" "z10_super_E1,
7205                         z10_super_E1,
7206                         z10_super_E1,
7207                         z10_super_E1,
7208                         z10_super_E1,
7209                         z10_super_E1,
7210                         z10_super_E1,
7211                         *,
7212                         z10_super_E1,
7213                         *,
7214                         *")])
7215
7216 (define_split
7217   [(set (match_operand:DI 0 "s_operand" "")
7218         (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7219    (clobber (reg:CC CC_REGNUM))]
7220   "reload_completed"
7221   [(parallel
7222     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7223      (clobber (reg:CC CC_REGNUM))])]
7224   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7225
7226 ;
7227 ; iorsi3 instruction pattern(s).
7228 ;
7229
7230 (define_insn "*iorsi3_cc"
7231   [(set (reg CC_REGNUM)
7232         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7233                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7234                  (const_int 0)))
7235    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7236         (ior:SI (match_dup 1) (match_dup 2)))]
7237   "s390_match_ccmode(insn, CCTmode)"
7238   "@
7239    oilf\t%0,%o2
7240    or\t%0,%2
7241    ork\t%0,%1,%2
7242    o\t%0,%2
7243    oy\t%0,%2"
7244   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7245    (set_attr "cpu_facility" "*,*,z196,*,*")
7246    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7247
7248 (define_insn "*iorsi3_cconly"
7249   [(set (reg CC_REGNUM)
7250         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7251                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7252                  (const_int 0)))
7253    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7254   "s390_match_ccmode(insn, CCTmode)"
7255   "@
7256    oilf\t%0,%o2
7257    or\t%0,%2
7258    ork\t%0,%1,%2
7259    o\t%0,%2
7260    oy\t%0,%2"
7261   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7262    (set_attr "cpu_facility" "*,*,z196,*,*")
7263    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7264
7265 (define_insn "*iorsi3_zarch"
7266   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,    d, d,d,d,d,d,   AQ,Q")
7267         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,    0, 0,0,d,0,0,    0,0")
7268                 (match_operand:SI 2 "general_operand"   "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7269    (clobber (reg:CC CC_REGNUM))]
7270   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7271   "@
7272    oilh\t%0,%i2
7273    oill\t%0,%i2
7274    oilf\t%0,%o2
7275    or\t%0,%2
7276    ork\t%0,%1,%2
7277    o\t%0,%2
7278    oy\t%0,%2
7279    #
7280    #"
7281   [(set_attr "op_type"  "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7282    (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7283    (set_attr "z10prop" "z10_super_E1,
7284                         z10_super_E1,
7285                         z10_super_E1,
7286                         z10_super_E1,
7287                         *,
7288                         z10_super_E1,
7289                         z10_super_E1,
7290                         *,
7291                         *")])
7292
7293 (define_insn "*iorsi3_esa"
7294   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7295         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7296                 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7297    (clobber (reg:CC CC_REGNUM))]
7298   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7299   "@
7300    or\t%0,%2
7301    o\t%0,%2
7302    #
7303    #"
7304   [(set_attr "op_type"  "RR,RX,SI,SS")
7305    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7306
7307 (define_split
7308   [(set (match_operand:SI 0 "s_operand" "")
7309         (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7310    (clobber (reg:CC CC_REGNUM))]
7311   "reload_completed"
7312   [(parallel
7313     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7314      (clobber (reg:CC CC_REGNUM))])]
7315   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7316
7317 ;
7318 ; iorhi3 instruction pattern(s).
7319 ;
7320
7321 (define_insn "*iorhi3_zarch"
7322   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7323         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7324                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQH0,Q")))
7325    (clobber (reg:CC CC_REGNUM))]
7326   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7327   "@
7328    or\t%0,%2
7329    ork\t%0,%1,%2
7330    oill\t%0,%x2
7331    #
7332    #"
7333   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7334    (set_attr "cpu_facility" "*,z196,*,*,*")
7335    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7336
7337 (define_insn "*iorhi3_esa"
7338   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7339         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7340                 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7341    (clobber (reg:CC CC_REGNUM))]
7342   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7343   "@
7344    or\t%0,%2
7345    #
7346    #"
7347   [(set_attr "op_type"  "RR,SI,SS")
7348    (set_attr "z10prop" "z10_super_E1,*,*")])
7349
7350 (define_split
7351   [(set (match_operand:HI 0 "s_operand" "")
7352         (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7353    (clobber (reg:CC CC_REGNUM))]
7354   "reload_completed"
7355   [(parallel
7356     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7357      (clobber (reg:CC CC_REGNUM))])]
7358   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7359
7360 ;
7361 ; iorqi3 instruction pattern(s).
7362 ;
7363
7364 (define_insn "*iorqi3_zarch"
7365   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7366         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7367                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7368    (clobber (reg:CC CC_REGNUM))]
7369   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7370   "@
7371    or\t%0,%2
7372    ork\t%0,%1,%2
7373    oill\t%0,%b2
7374    oi\t%S0,%b2
7375    oiy\t%S0,%b2
7376    #"
7377   [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7378    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7379    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7380                         z10_super,z10_super,*")])
7381
7382 (define_insn "*iorqi3_esa"
7383   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7384         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7385                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7386    (clobber (reg:CC CC_REGNUM))]
7387   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7388   "@
7389    or\t%0,%2
7390    oi\t%S0,%b2
7391    #"
7392   [(set_attr "op_type"  "RR,SI,SS")
7393    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7394
7395 ;
7396 ; Block inclusive or (OC) patterns.
7397 ;
7398
7399 (define_insn "*oc"
7400   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7401         (ior:BLK (match_dup 0)
7402                  (match_operand:BLK 1 "memory_operand" "Q")))
7403    (use (match_operand 2 "const_int_operand" "n"))
7404    (clobber (reg:CC CC_REGNUM))]
7405   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7406   "oc\t%O0(%2,%R0),%S1"
7407   [(set_attr "op_type" "SS")
7408    (set_attr "z196prop" "z196_cracked")])
7409
7410 (define_split
7411   [(set (match_operand 0 "memory_operand" "")
7412         (ior (match_dup 0)
7413              (match_operand 1 "memory_operand" "")))
7414    (clobber (reg:CC CC_REGNUM))]
7415   "reload_completed
7416    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7417    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7418   [(parallel
7419     [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7420      (use (match_dup 2))
7421      (clobber (reg:CC CC_REGNUM))])]
7422 {
7423   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7424   operands[0] = adjust_address (operands[0], BLKmode, 0);
7425   operands[1] = adjust_address (operands[1], BLKmode, 0);
7426 })
7427
7428 (define_peephole2
7429   [(parallel
7430     [(set (match_operand:BLK 0 "memory_operand" "")
7431           (ior:BLK (match_dup 0)
7432                    (match_operand:BLK 1 "memory_operand" "")))
7433      (use (match_operand 2 "const_int_operand" ""))
7434      (clobber (reg:CC CC_REGNUM))])
7435    (parallel
7436     [(set (match_operand:BLK 3 "memory_operand" "")
7437           (ior:BLK (match_dup 3)
7438                    (match_operand:BLK 4 "memory_operand" "")))
7439      (use (match_operand 5 "const_int_operand" ""))
7440      (clobber (reg:CC CC_REGNUM))])]
7441   "s390_offset_p (operands[0], operands[3], operands[2])
7442    && s390_offset_p (operands[1], operands[4], operands[2])
7443    && !s390_overlap_p (operands[0], operands[1],
7444                        INTVAL (operands[2]) + INTVAL (operands[5]))
7445    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7446   [(parallel
7447     [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7448      (use (match_dup 8))
7449      (clobber (reg:CC CC_REGNUM))])]
7450   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7451    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7452    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7453
7454
7455 ;;
7456 ;;- Xor instructions.
7457 ;;
7458
7459 (define_expand "xor<mode>3"
7460   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7461         (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7462                  (match_operand:INT 2 "general_operand" "")))
7463    (clobber (reg:CC CC_REGNUM))]
7464   ""
7465   "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7466
7467 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7468 ; simplifications.  So its better to have something matching.
7469 (define_split
7470   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7471         (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7472   ""
7473   [(parallel
7474     [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7475      (clobber (reg:CC CC_REGNUM))])]
7476 {
7477   operands[2] = constm1_rtx;
7478   if (!s390_logical_operator_ok_p (operands))
7479     FAIL;
7480 })
7481
7482 ;
7483 ; xordi3 instruction pattern(s).
7484 ;
7485
7486 (define_insn "*xordi3_cc"
7487   [(set (reg CC_REGNUM)
7488         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7489                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7490                  (const_int 0)))
7491    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7492         (xor:DI (match_dup 1) (match_dup 2)))]
7493   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7494   "@
7495    xgr\t%0,%2
7496    xgrk\t%0,%1,%2
7497    xg\t%0,%2"
7498   [(set_attr "op_type" "RRE,RRF,RXY")
7499    (set_attr "cpu_facility" "*,z196,*")
7500    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7501
7502 (define_insn "*xordi3_cconly"
7503   [(set (reg CC_REGNUM)
7504         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7505                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7506                  (const_int 0)))
7507    (clobber (match_scratch:DI 0                                     "=d,d, d"))]
7508   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7509   "@
7510    xgr\t%0,%2
7511    xgrk\t%0,%1,%2
7512    xg\t%0,%2"
7513   [(set_attr "op_type" "RRE,RRF,RXY")
7514    (set_attr "cpu_facility" "*,z196,*")
7515    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7516
7517 (define_insn "*xordi3"
7518   [(set (match_operand:DI 0 "nonimmediate_operand"         "=d,    d,d,d, d,   AQ,Q")
7519         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,    0,0,d, 0,    0,0")
7520                 (match_operand:DI 2 "general_operand"   "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7521    (clobber (reg:CC CC_REGNUM))]
7522   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7523   "@
7524    xihf\t%0,%k2
7525    xilf\t%0,%k2
7526    xgr\t%0,%2
7527    xgrk\t%0,%1,%2
7528    xg\t%0,%2
7529    #
7530    #"
7531   [(set_attr "op_type"  "RIL,RIL,RRE,RRF,RXY,SI,SS")
7532    (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7533    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7534                         *,z10_super_E1,*,*")])
7535
7536 (define_split
7537   [(set (match_operand:DI 0 "s_operand" "")
7538         (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7539    (clobber (reg:CC CC_REGNUM))]
7540   "reload_completed"
7541   [(parallel
7542     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7543      (clobber (reg:CC CC_REGNUM))])]
7544   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7545
7546 ;
7547 ; xorsi3 instruction pattern(s).
7548 ;
7549
7550 (define_insn "*xorsi3_cc"
7551   [(set (reg CC_REGNUM)
7552         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7553                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7554                  (const_int 0)))
7555    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7556         (xor:SI (match_dup 1) (match_dup 2)))]
7557   "s390_match_ccmode(insn, CCTmode)"
7558   "@
7559    xilf\t%0,%o2
7560    xr\t%0,%2
7561    xrk\t%0,%1,%2
7562    x\t%0,%2
7563    xy\t%0,%2"
7564   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7565    (set_attr "cpu_facility" "*,*,z196,*,*")
7566    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7567                         z10_super_E1,z10_super_E1")])
7568
7569 (define_insn "*xorsi3_cconly"
7570   [(set (reg CC_REGNUM)
7571         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7572                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7573                  (const_int 0)))
7574    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7575   "s390_match_ccmode(insn, CCTmode)"
7576   "@
7577    xilf\t%0,%o2
7578    xr\t%0,%2
7579    xrk\t%0,%1,%2
7580    x\t%0,%2
7581    xy\t%0,%2"
7582   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7583    (set_attr "cpu_facility" "*,*,z196,*,*")
7584    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7585                         z10_super_E1,z10_super_E1")])
7586
7587 (define_insn "*xorsi3"
7588   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,d,d,d,   AQ,Q")
7589         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    0,0")
7590                 (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxQS0,Q")))
7591    (clobber (reg:CC CC_REGNUM))]
7592   "s390_logical_operator_ok_p (operands)"
7593   "@
7594    xilf\t%0,%o2
7595    xr\t%0,%2
7596    xrk\t%0,%1,%2
7597    x\t%0,%2
7598    xy\t%0,%2
7599    #
7600    #"
7601   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,SI,SS")
7602    (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7603    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7604                         z10_super_E1,z10_super_E1,*,*")])
7605
7606 (define_split
7607   [(set (match_operand:SI 0 "s_operand" "")
7608         (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7609    (clobber (reg:CC CC_REGNUM))]
7610   "reload_completed"
7611   [(parallel
7612     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7613      (clobber (reg:CC CC_REGNUM))])]
7614   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7615
7616 ;
7617 ; xorhi3 instruction pattern(s).
7618 ;
7619
7620 (define_insn "*xorhi3"
7621   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7622         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d,    0,0")
7623                 (match_operand:HI 2 "general_operand"      "Os,d,d,NxQH0,Q")))
7624    (clobber (reg:CC CC_REGNUM))]
7625   "s390_logical_operator_ok_p (operands)"
7626   "@
7627    xilf\t%0,%x2
7628    xr\t%0,%2
7629    xrk\t%0,%1,%2
7630    #
7631    #"
7632   [(set_attr "op_type"  "RIL,RR,RRF,SI,SS")
7633    (set_attr "cpu_facility" "*,*,z196,*,*")
7634    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7635
7636 (define_split
7637   [(set (match_operand:HI 0 "s_operand" "")
7638         (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7639    (clobber (reg:CC CC_REGNUM))]
7640   "reload_completed"
7641   [(parallel
7642     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7643      (clobber (reg:CC CC_REGNUM))])]
7644   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7645
7646 ;
7647 ; xorqi3 instruction pattern(s).
7648 ;
7649
7650 (define_insn "*xorqi3"
7651   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7652         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7653                 (match_operand:QI 2 "general_operand"      "Os,d,d,n,n,Q")))
7654    (clobber (reg:CC CC_REGNUM))]
7655   "s390_logical_operator_ok_p (operands)"
7656   "@
7657    xilf\t%0,%b2
7658    xr\t%0,%2
7659    xrk\t%0,%1,%2
7660    xi\t%S0,%b2
7661    xiy\t%S0,%b2
7662    #"
7663   [(set_attr "op_type"  "RIL,RR,RRF,SI,SIY,SS")
7664    (set_attr "cpu_facility" "*,*,z196,*,*,*")
7665    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7666
7667
7668 ;
7669 ; Block exclusive or (XC) patterns.
7670 ;
7671
7672 (define_insn "*xc"
7673   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7674         (xor:BLK (match_dup 0)
7675                  (match_operand:BLK 1 "memory_operand" "Q")))
7676    (use (match_operand 2 "const_int_operand" "n"))
7677    (clobber (reg:CC CC_REGNUM))]
7678   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7679   "xc\t%O0(%2,%R0),%S1"
7680   [(set_attr "op_type" "SS")])
7681
7682 (define_split
7683   [(set (match_operand 0 "memory_operand" "")
7684         (xor (match_dup 0)
7685              (match_operand 1 "memory_operand" "")))
7686    (clobber (reg:CC CC_REGNUM))]
7687   "reload_completed
7688    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7689    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7690   [(parallel
7691     [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7692      (use (match_dup 2))
7693      (clobber (reg:CC CC_REGNUM))])]
7694 {
7695   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7696   operands[0] = adjust_address (operands[0], BLKmode, 0);
7697   operands[1] = adjust_address (operands[1], BLKmode, 0);
7698 })
7699
7700 (define_peephole2
7701   [(parallel
7702     [(set (match_operand:BLK 0 "memory_operand" "")
7703           (xor:BLK (match_dup 0)
7704                    (match_operand:BLK 1 "memory_operand" "")))
7705      (use (match_operand 2 "const_int_operand" ""))
7706      (clobber (reg:CC CC_REGNUM))])
7707    (parallel
7708     [(set (match_operand:BLK 3 "memory_operand" "")
7709           (xor:BLK (match_dup 3)
7710                    (match_operand:BLK 4 "memory_operand" "")))
7711      (use (match_operand 5 "const_int_operand" ""))
7712      (clobber (reg:CC CC_REGNUM))])]
7713   "s390_offset_p (operands[0], operands[3], operands[2])
7714    && s390_offset_p (operands[1], operands[4], operands[2])
7715    && !s390_overlap_p (operands[0], operands[1],
7716                        INTVAL (operands[2]) + INTVAL (operands[5]))
7717    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7718   [(parallel
7719     [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7720      (use (match_dup 8))
7721      (clobber (reg:CC CC_REGNUM))])]
7722   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7723    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7724    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7725
7726 ;
7727 ; Block xor (XC) patterns with src == dest.
7728 ;
7729
7730 (define_insn "*xc_zero"
7731   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7732         (const_int 0))
7733    (use (match_operand 1 "const_int_operand" "n"))
7734    (clobber (reg:CC CC_REGNUM))]
7735   "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7736   "xc\t%O0(%1,%R0),%S0"
7737   [(set_attr "op_type" "SS")
7738    (set_attr "z196prop" "z196_cracked")])
7739
7740 (define_peephole2
7741   [(parallel
7742     [(set (match_operand:BLK 0 "memory_operand" "")
7743           (const_int 0))
7744      (use (match_operand 1 "const_int_operand" ""))
7745      (clobber (reg:CC CC_REGNUM))])
7746    (parallel
7747     [(set (match_operand:BLK 2 "memory_operand" "")
7748           (const_int 0))
7749      (use (match_operand 3 "const_int_operand" ""))
7750      (clobber (reg:CC CC_REGNUM))])]
7751   "s390_offset_p (operands[0], operands[2], operands[1])
7752    && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7753   [(parallel
7754     [(set (match_dup 4) (const_int 0))
7755      (use (match_dup 5))
7756      (clobber (reg:CC CC_REGNUM))])]
7757   "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7758    operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7759
7760
7761 ;;
7762 ;;- Negate instructions.
7763 ;;
7764
7765 ;
7766 ; neg(di|si)2 instruction pattern(s).
7767 ;
7768
7769 (define_expand "neg<mode>2"
7770   [(parallel
7771     [(set (match_operand:DSI 0 "register_operand" "=d")
7772           (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7773      (clobber (reg:CC CC_REGNUM))])]
7774   ""
7775   "")
7776
7777 (define_insn "*negdi2_sign_cc"
7778   [(set (reg CC_REGNUM)
7779         (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7780                            (match_operand:SI 1 "register_operand" "d") 0)
7781                            (const_int 32)) (const_int 32)))
7782                  (const_int 0)))
7783    (set (match_operand:DI 0 "register_operand" "=d")
7784         (neg:DI (sign_extend:DI (match_dup 1))))]
7785   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7786   "lcgfr\t%0,%1"
7787   [(set_attr "op_type"  "RRE")
7788    (set_attr "z10prop" "z10_c")])
7789
7790 (define_insn "*negdi2_sign"
7791   [(set (match_operand:DI 0 "register_operand" "=d")
7792         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7793    (clobber (reg:CC CC_REGNUM))]
7794   "TARGET_ZARCH"
7795   "lcgfr\t%0,%1"
7796   [(set_attr "op_type"  "RRE")
7797    (set_attr "z10prop" "z10_c")])
7798
7799 ; lcr, lcgr
7800 (define_insn "*neg<mode>2_cc"
7801   [(set (reg CC_REGNUM)
7802         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7803                  (const_int 0)))
7804    (set (match_operand:GPR 0 "register_operand" "=d")
7805         (neg:GPR (match_dup 1)))]
7806   "s390_match_ccmode (insn, CCAmode)"
7807   "lc<g>r\t%0,%1"
7808   [(set_attr "op_type"  "RR<E>")
7809    (set_attr "z10prop" "z10_super_c_E1")])
7810
7811 ; lcr, lcgr
7812 (define_insn "*neg<mode>2_cconly"
7813   [(set (reg CC_REGNUM)
7814         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7815                  (const_int 0)))
7816    (clobber (match_scratch:GPR 0 "=d"))]
7817   "s390_match_ccmode (insn, CCAmode)"
7818   "lc<g>r\t%0,%1"
7819   [(set_attr "op_type"  "RR<E>")
7820    (set_attr "z10prop" "z10_super_c_E1")])
7821
7822 ; lcr, lcgr
7823 (define_insn "*neg<mode>2"
7824   [(set (match_operand:GPR 0 "register_operand" "=d")
7825         (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7826    (clobber (reg:CC CC_REGNUM))]
7827   ""
7828   "lc<g>r\t%0,%1"
7829   [(set_attr "op_type"  "RR<E>")
7830    (set_attr "z10prop" "z10_super_c_E1")])
7831
7832 (define_insn "*negdi2_31"
7833   [(set (match_operand:DI 0 "register_operand" "=d")
7834         (neg:DI (match_operand:DI 1 "register_operand" "d")))
7835    (clobber (reg:CC CC_REGNUM))]
7836   "!TARGET_ZARCH"
7837   "#")
7838
7839 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7840
7841 ; Doing the twos complement separately on the SImode parts does an
7842 ; unwanted +1 on the high part which needs to be subtracted afterwards
7843 ; ... unless the +1 on the low part created an overflow.
7844
7845 (define_split
7846   [(set (match_operand:DI 0 "register_operand" "")
7847         (neg:DI (match_operand:DI 1 "register_operand" "")))
7848    (clobber (reg:CC CC_REGNUM))]
7849   "!TARGET_ZARCH
7850    && (REGNO (operands[0]) == REGNO (operands[1])
7851       || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7852    && reload_completed"
7853   [(parallel
7854     [(set (match_dup 2) (neg:SI (match_dup 3)))
7855      (clobber (reg:CC CC_REGNUM))])
7856    (parallel
7857     [(set (reg:CCAP CC_REGNUM)
7858           (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7859      (set (match_dup 4) (neg:SI (match_dup 5)))])
7860    (set (pc)
7861         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7862                       (pc)
7863                       (label_ref (match_dup 6))))
7864    (parallel
7865     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7866      (clobber (reg:CC CC_REGNUM))])
7867    (match_dup 6)]
7868   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7869    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7870    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7871    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7872    operands[6] = gen_label_rtx ();")
7873
7874 ; Like above but first make a copy of the low part of the src operand
7875 ; since it might overlap with the high part of the destination.
7876
7877 (define_split
7878   [(set (match_operand:DI 0 "register_operand" "")
7879         (neg:DI (match_operand:DI 1 "register_operand" "")))
7880    (clobber (reg:CC CC_REGNUM))]
7881   "!TARGET_ZARCH
7882    && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7883    && reload_completed"
7884   [; Make a backup of op5 first
7885    (set (match_dup 4) (match_dup 5))
7886    ; Setting op2 here might clobber op5
7887    (parallel
7888     [(set (match_dup 2) (neg:SI (match_dup 3)))
7889      (clobber (reg:CC CC_REGNUM))])
7890    (parallel
7891     [(set (reg:CCAP CC_REGNUM)
7892           (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7893      (set (match_dup 4) (neg:SI (match_dup 4)))])
7894    (set (pc)
7895         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7896                       (pc)
7897                       (label_ref (match_dup 6))))
7898    (parallel
7899     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7900      (clobber (reg:CC CC_REGNUM))])
7901    (match_dup 6)]
7902   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7903    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7904    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7905    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7906    operands[6] = gen_label_rtx ();")
7907
7908 ;
7909 ; neg(df|sf)2 instruction pattern(s).
7910 ;
7911
7912 (define_expand "neg<mode>2"
7913   [(parallel
7914     [(set (match_operand:BFP 0 "register_operand" "=f")
7915           (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7916      (clobber (reg:CC CC_REGNUM))])]
7917   "TARGET_HARD_FLOAT"
7918   "")
7919
7920 ; lcxbr, lcdbr, lcebr
7921 (define_insn "*neg<mode>2_cc"
7922   [(set (reg CC_REGNUM)
7923         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7924                  (match_operand:BFP 2 "const0_operand" "")))
7925    (set (match_operand:BFP 0 "register_operand" "=f")
7926         (neg:BFP (match_dup 1)))]
7927   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7928   "lc<xde>br\t%0,%1"
7929   [(set_attr "op_type"  "RRE")
7930    (set_attr "type"     "fsimp<mode>")])
7931
7932 ; lcxbr, lcdbr, lcebr
7933 (define_insn "*neg<mode>2_cconly"
7934   [(set (reg CC_REGNUM)
7935         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7936                  (match_operand:BFP 2 "const0_operand" "")))
7937    (clobber (match_scratch:BFP 0 "=f"))]
7938   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7939   "lc<xde>br\t%0,%1"
7940   [(set_attr "op_type"  "RRE")
7941    (set_attr "type"     "fsimp<mode>")])
7942
7943 ; lcdfr
7944 (define_insn "*neg<mode>2_nocc"
7945   [(set (match_operand:FP 0 "register_operand"         "=f")
7946         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7947   "TARGET_DFP"
7948   "lcdfr\t%0,%1"
7949   [(set_attr "op_type"  "RRE")
7950    (set_attr "type"     "fsimp<mode>")])
7951
7952 ; lcxbr, lcdbr, lcebr
7953 ; FIXME: wflcdb does not clobber cc
7954 (define_insn "*neg<mode>2"
7955   [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
7956         (neg:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
7957    (clobber (reg:CC CC_REGNUM))]
7958   "TARGET_HARD_FLOAT"
7959   "@
7960    lc<xde>br\t%0,%1
7961    wflcdb\t%0,%1"
7962   [(set_attr "op_type"      "RRE,VRR")
7963    (set_attr "cpu_facility" "*,vec")
7964    (set_attr "type"         "fsimp<mode>,*")])
7965
7966
7967 ;;
7968 ;;- Absolute value instructions.
7969 ;;
7970
7971 ;
7972 ; abs(di|si)2 instruction pattern(s).
7973 ;
7974
7975 (define_insn "*absdi2_sign_cc"
7976   [(set (reg CC_REGNUM)
7977         (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7978                            (match_operand:SI 1 "register_operand" "d") 0)
7979                            (const_int 32)) (const_int 32)))
7980                  (const_int 0)))
7981    (set (match_operand:DI 0 "register_operand" "=d")
7982         (abs:DI (sign_extend:DI (match_dup 1))))]
7983   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7984   "lpgfr\t%0,%1"
7985   [(set_attr "op_type"  "RRE")
7986    (set_attr "z10prop" "z10_c")])
7987
7988 (define_insn "*absdi2_sign"
7989   [(set (match_operand:DI 0 "register_operand" "=d")
7990         (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7991    (clobber (reg:CC CC_REGNUM))]
7992   "TARGET_ZARCH"
7993   "lpgfr\t%0,%1"
7994   [(set_attr "op_type"  "RRE")
7995    (set_attr "z10prop" "z10_c")])
7996
7997 ; lpr, lpgr
7998 (define_insn "*abs<mode>2_cc"
7999   [(set (reg CC_REGNUM)
8000         (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8001                  (const_int 0)))
8002    (set (match_operand:GPR 0 "register_operand" "=d")
8003         (abs:GPR (match_dup 1)))]
8004   "s390_match_ccmode (insn, CCAmode)"
8005   "lp<g>r\t%0,%1"
8006   [(set_attr "op_type"  "RR<E>")
8007    (set_attr "z10prop" "z10_c")])
8008
8009 ; lpr, lpgr
8010 (define_insn "*abs<mode>2_cconly"
8011   [(set (reg CC_REGNUM)
8012         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8013                  (const_int 0)))
8014    (clobber (match_scratch:GPR 0 "=d"))]
8015   "s390_match_ccmode (insn, CCAmode)"
8016   "lp<g>r\t%0,%1"
8017   [(set_attr "op_type"  "RR<E>")
8018    (set_attr "z10prop" "z10_c")])
8019
8020 ; lpr, lpgr
8021 (define_insn "abs<mode>2"
8022   [(set (match_operand:GPR 0 "register_operand" "=d")
8023         (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8024    (clobber (reg:CC CC_REGNUM))]
8025   ""
8026   "lp<g>r\t%0,%1"
8027   [(set_attr "op_type"  "RR<E>")
8028    (set_attr "z10prop" "z10_c")])
8029
8030 ;
8031 ; abs(df|sf)2 instruction pattern(s).
8032 ;
8033
8034 (define_expand "abs<mode>2"
8035   [(parallel
8036     [(set (match_operand:BFP 0 "register_operand" "=f")
8037           (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8038      (clobber (reg:CC CC_REGNUM))])]
8039   "TARGET_HARD_FLOAT"
8040   "")
8041
8042 ; lpxbr, lpdbr, lpebr
8043 (define_insn "*abs<mode>2_cc"
8044   [(set (reg CC_REGNUM)
8045         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8046                  (match_operand:BFP 2 "const0_operand" "")))
8047    (set (match_operand:BFP 0 "register_operand" "=f")
8048         (abs:BFP (match_dup 1)))]
8049   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8050   "lp<xde>br\t%0,%1"
8051   [(set_attr "op_type"  "RRE")
8052    (set_attr "type"     "fsimp<mode>")])
8053
8054 ; lpxbr, lpdbr, lpebr
8055 (define_insn "*abs<mode>2_cconly"
8056   [(set (reg CC_REGNUM)
8057         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8058                  (match_operand:BFP 2 "const0_operand" "")))
8059    (clobber (match_scratch:BFP 0 "=f"))]
8060   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8061   "lp<xde>br\t%0,%1"
8062   [(set_attr "op_type"  "RRE")
8063    (set_attr "type"     "fsimp<mode>")])
8064
8065 ; lpdfr
8066 (define_insn "*abs<mode>2_nocc"
8067   [(set (match_operand:FP 0 "register_operand"         "=f")
8068         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8069   "TARGET_DFP"
8070   "lpdfr\t%0,%1"
8071   [(set_attr "op_type"  "RRE")
8072    (set_attr "type"     "fsimp<mode>")])
8073
8074 ; lpxbr, lpdbr, lpebr
8075 ; FIXME: wflpdb does not clobber cc
8076 (define_insn "*abs<mode>2"
8077   [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
8078         (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
8079    (clobber (reg:CC CC_REGNUM))]
8080   "TARGET_HARD_FLOAT"
8081   "@
8082     lp<xde>br\t%0,%1
8083     wflpdb\t%0,%1"
8084   [(set_attr "op_type"      "RRE,VRR")
8085    (set_attr "cpu_facility" "*,vec")
8086    (set_attr "type"         "fsimp<mode>,*")])
8087
8088
8089 ;;
8090 ;;- Negated absolute value instructions
8091 ;;
8092
8093 ;
8094 ; Integer
8095 ;
8096
8097 (define_insn "*negabsdi2_sign_cc"
8098   [(set (reg CC_REGNUM)
8099         (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8100                            (match_operand:SI 1 "register_operand" "d") 0)
8101                            (const_int 32)) (const_int 32))))
8102                  (const_int 0)))
8103    (set (match_operand:DI 0 "register_operand" "=d")
8104         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8105   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8106   "lngfr\t%0,%1"
8107   [(set_attr "op_type"  "RRE")
8108    (set_attr "z10prop" "z10_c")])
8109
8110 (define_insn "*negabsdi2_sign"
8111   [(set (match_operand:DI 0 "register_operand" "=d")
8112         (neg:DI (abs:DI (sign_extend:DI
8113                           (match_operand:SI 1 "register_operand" "d")))))
8114    (clobber (reg:CC CC_REGNUM))]
8115   "TARGET_ZARCH"
8116   "lngfr\t%0,%1"
8117   [(set_attr "op_type" "RRE")
8118    (set_attr "z10prop" "z10_c")])
8119
8120 ; lnr, lngr
8121 (define_insn "*negabs<mode>2_cc"
8122   [(set (reg CC_REGNUM)
8123         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8124                  (const_int 0)))
8125    (set (match_operand:GPR 0 "register_operand" "=d")
8126         (neg:GPR (abs:GPR (match_dup 1))))]
8127   "s390_match_ccmode (insn, CCAmode)"
8128   "ln<g>r\t%0,%1"
8129   [(set_attr "op_type"  "RR<E>")
8130    (set_attr "z10prop" "z10_c")])
8131
8132 ; lnr, lngr
8133 (define_insn "*negabs<mode>2_cconly"
8134   [(set (reg CC_REGNUM)
8135         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8136                  (const_int 0)))
8137    (clobber (match_scratch:GPR 0 "=d"))]
8138   "s390_match_ccmode (insn, CCAmode)"
8139   "ln<g>r\t%0,%1"
8140   [(set_attr "op_type"  "RR<E>")
8141    (set_attr "z10prop" "z10_c")])
8142
8143 ; lnr, lngr
8144 (define_insn "*negabs<mode>2"
8145   [(set (match_operand:GPR 0 "register_operand" "=d")
8146         (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8147    (clobber (reg:CC CC_REGNUM))]
8148   ""
8149   "ln<g>r\t%0,%1"
8150   [(set_attr "op_type" "RR<E>")
8151    (set_attr "z10prop" "z10_c")])
8152
8153 ;
8154 ; Floating point
8155 ;
8156
8157 ; lnxbr, lndbr, lnebr
8158 (define_insn "*negabs<mode>2_cc"
8159   [(set (reg CC_REGNUM)
8160         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8161                  (match_operand:BFP 2 "const0_operand" "")))
8162    (set (match_operand:BFP 0 "register_operand" "=f")
8163         (neg:BFP (abs:BFP (match_dup 1))))]
8164   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8165   "ln<xde>br\t%0,%1"
8166   [(set_attr "op_type"  "RRE")
8167    (set_attr "type"     "fsimp<mode>")])
8168
8169 ; lnxbr, lndbr, lnebr
8170 (define_insn "*negabs<mode>2_cconly"
8171   [(set (reg CC_REGNUM)
8172         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8173                  (match_operand:BFP 2 "const0_operand" "")))
8174    (clobber (match_scratch:BFP 0 "=f"))]
8175   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8176   "ln<xde>br\t%0,%1"
8177   [(set_attr "op_type"  "RRE")
8178    (set_attr "type"     "fsimp<mode>")])
8179
8180 ; lndfr
8181 (define_insn "*negabs<mode>2_nocc"
8182   [(set (match_operand:FP 0 "register_operand"                  "=f")
8183         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8184   "TARGET_DFP"
8185   "lndfr\t%0,%1"
8186   [(set_attr "op_type"  "RRE")
8187    (set_attr "type"     "fsimp<mode>")])
8188
8189 ; lnxbr, lndbr, lnebr
8190 ; FIXME: wflndb does not clobber cc
8191 (define_insn "*negabs<mode>2"
8192   [(set (match_operand:BFP                   0 "register_operand" "=f,<vf>")
8193         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>"))))
8194    (clobber (reg:CC CC_REGNUM))]
8195   "TARGET_HARD_FLOAT"
8196   "@
8197    ln<xde>br\t%0,%1
8198    wflndb\t%0,%1"
8199   [(set_attr "op_type"      "RRE,VRR")
8200    (set_attr "cpu_facility" "*,vec")
8201    (set_attr "type"         "fsimp<mode>,*")])
8202
8203 ;;
8204 ;;- Square root instructions.
8205 ;;
8206
8207 ;
8208 ; sqrt(df|sf)2 instruction pattern(s).
8209 ;
8210
8211 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8212 (define_insn "sqrt<mode>2"
8213   [(set (match_operand:BFP           0 "register_operand" "=f,   f,<vf>")
8214         (sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,<Rf>,<vf>")))]
8215   "TARGET_HARD_FLOAT"
8216   "@
8217    sq<xde>br\t%0,%1
8218    sq<xde>b\t%0,%1
8219    wfsqdb\t%v0,%v1"
8220   [(set_attr "op_type"      "RRE,RXE,VRR")
8221    (set_attr "type"         "fsqrt<mode>")
8222    (set_attr "cpu_facility" "*,*,vec")])
8223
8224
8225 ;;
8226 ;;- One complement instructions.
8227 ;;
8228
8229 ;
8230 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8231 ;
8232
8233 (define_expand "one_cmpl<mode>2"
8234   [(parallel
8235     [(set (match_operand:INT 0 "register_operand" "")
8236           (xor:INT (match_operand:INT 1 "register_operand" "")
8237                    (const_int -1)))
8238      (clobber (reg:CC CC_REGNUM))])]
8239   ""
8240   "")
8241
8242
8243 ;;
8244 ;; Find leftmost bit instructions.
8245 ;;
8246
8247 (define_expand "clzdi2"
8248   [(set (match_operand:DI 0 "register_operand" "=d")
8249         (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8250   "TARGET_EXTIMM && TARGET_ZARCH"
8251 {
8252   rtx insn, clz_equal;
8253   rtx wide_reg = gen_reg_rtx (TImode);
8254   rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8255
8256   clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8257
8258   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8259
8260   insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8261   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8262
8263   DONE;
8264 })
8265
8266 (define_insn "clztidi2"
8267   [(set (match_operand:TI 0 "register_operand" "=d")
8268         (ior:TI
8269           (ashift:TI
8270             (zero_extend:TI
8271               (xor:DI (match_operand:DI 1 "register_operand" "d")
8272                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8273                                 (subreg:SI (clz:DI (match_dup 1)) 4))))
8274
8275             (const_int 64))
8276           (zero_extend:TI (clz:DI (match_dup 1)))))
8277    (clobber (reg:CC CC_REGNUM))]
8278   "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8279    == (unsigned HOST_WIDE_INT) 1 << 63
8280    && TARGET_EXTIMM && TARGET_ZARCH"
8281   "flogr\t%0,%1"
8282   [(set_attr "op_type"  "RRE")])
8283
8284
8285 ;;
8286 ;;- Rotate instructions.
8287 ;;
8288
8289 ;
8290 ; rotl(di|si)3 instruction pattern(s).
8291 ;
8292
8293 ; rll, rllg
8294 (define_insn "rotl<mode>3"
8295   [(set (match_operand:GPR 0 "register_operand" "=d")
8296         (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8297                     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8298   "TARGET_CPU_ZARCH"
8299   "rll<g>\t%0,%1,%Y2"
8300   [(set_attr "op_type"  "RSE")
8301    (set_attr "atype"    "reg")
8302    (set_attr "z10prop" "z10_super_E1")])
8303
8304 ; rll, rllg
8305 (define_insn "*rotl<mode>3_and"
8306   [(set (match_operand:GPR 0 "register_operand" "=d")
8307         (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8308                     (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8309                             (match_operand:SI 3 "const_int_operand"   "n"))))]
8310   "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8311   "rll<g>\t%0,%1,%Y2"
8312   [(set_attr "op_type"  "RSE")
8313    (set_attr "atype"    "reg")
8314    (set_attr "z10prop" "z10_super_E1")])
8315
8316
8317 ;;
8318 ;;- Shift instructions.
8319 ;;
8320
8321 ;
8322 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8323 ; Left shifts and logical right shifts
8324
8325 (define_expand "<shift><mode>3"
8326   [(set (match_operand:DSI 0 "register_operand" "")
8327         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8328                    (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
8329   ""
8330   "")
8331
8332 ; sldl, srdl
8333 (define_insn "*<shift>di3_31"
8334   [(set (match_operand:DI 0 "register_operand" "=d")
8335         (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8336                   (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8337   "!TARGET_ZARCH"
8338   "s<lr>dl\t%0,%Y2"
8339   [(set_attr "op_type"  "RS")
8340    (set_attr "atype"    "reg")
8341    (set_attr "z196prop" "z196_cracked")])
8342
8343 ; sll, srl, sllg, srlg, sllk, srlk
8344 (define_insn "*<shift><mode>3"
8345   [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
8346         (SHIFT:GPR (match_operand:GPR 1 "register_operand"             "<d0>,d")
8347                    (match_operand:SI 2 "shift_count_or_setmem_operand"    "Y,Y")))]
8348   ""
8349   "@
8350    s<lr>l<g>\t%0,<1>%Y2
8351    s<lr>l<gk>\t%0,%1,%Y2"
8352   [(set_attr "op_type"  "RS<E>,RSY")
8353    (set_attr "atype"    "reg,reg")
8354    (set_attr "cpu_facility" "*,z196")
8355    (set_attr "z10prop" "z10_super_E1,*")])
8356
8357 ; sldl, srdl
8358 (define_insn "*<shift>di3_31_and"
8359   [(set (match_operand:DI 0 "register_operand" "=d")
8360         (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8361                   (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8362                           (match_operand:SI 3 "const_int_operand"   "n"))))]
8363   "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8364   "s<lr>dl\t%0,%Y2"
8365   [(set_attr "op_type"  "RS")
8366    (set_attr "atype"    "reg")])
8367
8368 ; sll, srl, sllg, srlg, sllk, srlk
8369 (define_insn "*<shift><mode>3_and"
8370   [(set (match_operand:GPR 0 "register_operand"                                 "=d,d")
8371         (SHIFT:GPR (match_operand:GPR 1 "register_operand"                    "<d0>,d")
8372                    (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand"   "Y,Y")
8373                            (match_operand:SI 3 "const_int_operand"               "n,n"))))]
8374   "(INTVAL (operands[3]) & 63) == 63"
8375   "@
8376    s<lr>l<g>\t%0,<1>%Y2
8377    s<lr>l<gk>\t%0,%1,%Y2"
8378   [(set_attr "op_type"  "RS<E>,RSY")
8379    (set_attr "atype"    "reg,reg")
8380    (set_attr "cpu_facility" "*,z196")
8381    (set_attr "z10prop" "z10_super_E1,*")])
8382
8383 ;
8384 ; ashr(di|si)3 instruction pattern(s).
8385 ; Arithmetic right shifts
8386
8387 (define_expand "ashr<mode>3"
8388   [(parallel
8389     [(set (match_operand:DSI 0 "register_operand" "")
8390           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8391                         (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
8392      (clobber (reg:CC CC_REGNUM))])]
8393   ""
8394   "")
8395
8396 (define_insn "*ashrdi3_cc_31"
8397   [(set (reg CC_REGNUM)
8398         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8399                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8400                  (const_int 0)))
8401    (set (match_operand:DI 0 "register_operand" "=d")
8402         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8403   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8404   "srda\t%0,%Y2"
8405   [(set_attr "op_type"  "RS")
8406    (set_attr "atype"    "reg")])
8407
8408 (define_insn "*ashrdi3_cconly_31"
8409   [(set (reg CC_REGNUM)
8410         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8411                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8412                  (const_int 0)))
8413    (clobber (match_scratch:DI 0 "=d"))]
8414   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8415   "srda\t%0,%Y2"
8416   [(set_attr "op_type"  "RS")
8417    (set_attr "atype"    "reg")])
8418
8419 (define_insn "*ashrdi3_31"
8420   [(set (match_operand:DI 0 "register_operand" "=d")
8421         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8422                      (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
8423    (clobber (reg:CC CC_REGNUM))]
8424   "!TARGET_ZARCH"
8425   "srda\t%0,%Y2"
8426   [(set_attr "op_type"  "RS")
8427    (set_attr "atype"    "reg")])
8428
8429 ; sra, srag, srak
8430 (define_insn "*ashr<mode>3_cc"
8431   [(set (reg CC_REGNUM)
8432         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8433                                (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8434                  (const_int 0)))
8435    (set (match_operand:GPR 0 "register_operand"                                   "=d,d")
8436         (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
8437   "s390_match_ccmode(insn, CCSmode)"
8438   "@
8439    sra<g>\t%0,<1>%Y2
8440    sra<gk>\t%0,%1,%Y2"
8441   [(set_attr "op_type"  "RS<E>,RSY")
8442    (set_attr "atype"    "reg,reg")
8443    (set_attr "cpu_facility" "*,z196")
8444    (set_attr "z10prop" "z10_super_E1,*")])
8445
8446 ; sra, srag, srak
8447 (define_insn "*ashr<mode>3_cconly"
8448   [(set (reg CC_REGNUM)
8449         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8450                                (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8451                  (const_int 0)))
8452    (clobber (match_scratch:GPR 0                                                  "=d,d"))]
8453   "s390_match_ccmode(insn, CCSmode)"
8454   "@
8455    sra<g>\t%0,<1>%Y2
8456    sra<gk>\t%0,%1,%Y2"
8457   [(set_attr "op_type"  "RS<E>,RSY")
8458    (set_attr "atype"    "reg,reg")
8459    (set_attr "cpu_facility" "*,z196")
8460    (set_attr "z10prop" "z10_super_E1,*")])
8461
8462 ; sra, srag
8463 (define_insn "*ashr<mode>3"
8464   [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
8465         (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8466                       (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8467    (clobber (reg:CC CC_REGNUM))]
8468   ""
8469   "@
8470    sra<g>\t%0,<1>%Y2
8471    sra<gk>\t%0,%1,%Y2"
8472   [(set_attr "op_type"  "RS<E>,RSY")
8473    (set_attr "atype"    "reg,reg")
8474    (set_attr "cpu_facility" "*,z196")
8475    (set_attr "z10prop" "z10_super_E1,*")])
8476
8477
8478 ; shift pattern with implicit ANDs
8479
8480 (define_insn "*ashrdi3_cc_31_and"
8481   [(set (reg CC_REGNUM)
8482         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8483                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8484                                       (match_operand:SI 3 "const_int_operand"   "n")))
8485                  (const_int 0)))
8486    (set (match_operand:DI 0 "register_operand" "=d")
8487         (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8488   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8489    && (INTVAL (operands[3]) & 63) == 63"
8490   "srda\t%0,%Y2"
8491   [(set_attr "op_type"  "RS")
8492    (set_attr "atype"    "reg")])
8493
8494 (define_insn "*ashrdi3_cconly_31_and"
8495   [(set (reg CC_REGNUM)
8496         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8497                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8498                                       (match_operand:SI 3 "const_int_operand"   "n")))
8499                  (const_int 0)))
8500    (clobber (match_scratch:DI 0 "=d"))]
8501   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8502    && (INTVAL (operands[3]) & 63) == 63"
8503   "srda\t%0,%Y2"
8504   [(set_attr "op_type"  "RS")
8505    (set_attr "atype"    "reg")])
8506
8507 (define_insn "*ashrdi3_31_and"
8508   [(set (match_operand:DI 0 "register_operand" "=d")
8509         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8510                      (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8511                              (match_operand:SI 3 "const_int_operand"   "n"))))
8512    (clobber (reg:CC CC_REGNUM))]
8513   "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8514   "srda\t%0,%Y2"
8515   [(set_attr "op_type"  "RS")
8516    (set_attr "atype"    "reg")])
8517
8518 ; sra, srag, srak
8519 (define_insn "*ashr<mode>3_cc_and"
8520   [(set (reg CC_REGNUM)
8521         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8522                                (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8523                                        (match_operand:SI 3 "const_int_operand"             "n,n")))
8524                  (const_int 0)))
8525    (set (match_operand:GPR 0 "register_operand"                                           "=d,d")
8526         (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8527   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8528   "@
8529    sra<g>\t%0,<1>%Y2
8530    sra<gk>\t%0,%1,%Y2"
8531   [(set_attr "op_type"  "RS<E>,RSY")
8532    (set_attr "atype"    "reg,reg")
8533    (set_attr "cpu_facility" "*,z196")
8534    (set_attr "z10prop" "z10_super_E1,*")])
8535
8536 ; sra, srag, srak
8537 (define_insn "*ashr<mode>3_cconly_and"
8538   [(set (reg CC_REGNUM)
8539         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8540                                (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8541                                        (match_operand:SI 3 "const_int_operand"             "n,n")))
8542                  (const_int 0)))
8543    (clobber (match_scratch:GPR 0                                                          "=d,d"))]
8544   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8545   "@
8546    sra<g>\t%0,<1>%Y2
8547    sra<gk>\t%0,%1,%Y2"
8548   [(set_attr "op_type"  "RS<E>,RSY")
8549    (set_attr "atype"    "reg,reg")
8550    (set_attr "cpu_facility" "*,z196")
8551    (set_attr "z10prop" "z10_super_E1,*")])
8552
8553 ; sra, srag, srak
8554 (define_insn "*ashr<mode>3_and"
8555   [(set (match_operand:GPR 0 "register_operand"                                  "=d,d")
8556         (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8557                       (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8558                               (match_operand:SI 3 "const_int_operand"             "n,n"))))
8559    (clobber (reg:CC CC_REGNUM))]
8560   "(INTVAL (operands[3]) & 63) == 63"
8561   "@
8562    sra<g>\t%0,<1>%Y2
8563    sra<gk>\t%0,%1,%Y2"
8564   [(set_attr "op_type"  "RS<E>,RSY")
8565    (set_attr "atype"    "reg,reg")
8566    (set_attr "cpu_facility" "*,z196")
8567    (set_attr "z10prop" "z10_super_E1,*")])
8568
8569
8570 ;;
8571 ;; Branch instruction patterns.
8572 ;;
8573
8574 (define_expand "cbranch<mode>4"
8575   [(set (pc)
8576         (if_then_else (match_operator 0 "comparison_operator"
8577                        [(match_operand:GPR 1 "register_operand" "")
8578                         (match_operand:GPR 2 "general_operand" "")])
8579                       (label_ref (match_operand 3 "" ""))
8580                       (pc)))]
8581   ""
8582   "s390_emit_jump (operands[3],
8583     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8584    DONE;")
8585
8586 (define_expand "cbranch<mode>4"
8587   [(set (pc)
8588         (if_then_else (match_operator 0 "comparison_operator"
8589                        [(match_operand:FP 1 "register_operand" "")
8590                         (match_operand:FP 2 "general_operand" "")])
8591                       (label_ref (match_operand 3 "" ""))
8592                       (pc)))]
8593   "TARGET_HARD_FLOAT"
8594   "s390_emit_jump (operands[3],
8595     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8596    DONE;")
8597
8598 (define_expand "cbranchcc4"
8599   [(set (pc)
8600         (if_then_else (match_operator 0 "s390_comparison"
8601                        [(match_operand 1 "cc_reg_operand" "")
8602                         (match_operand 2 "const_int_operand" "")])
8603                       (label_ref (match_operand 3 "" ""))
8604                       (pc)))]
8605   ""
8606   "")
8607
8608
8609 ;;
8610 ;;- Conditional jump instructions.
8611 ;;
8612
8613 (define_insn "*cjump_64"
8614   [(set (pc)
8615         (if_then_else
8616           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8617                                                (match_operand 2 "const_int_operand" "")])
8618           (label_ref (match_operand 0 "" ""))
8619           (pc)))]
8620   "TARGET_CPU_ZARCH"
8621 {
8622   if (get_attr_length (insn) == 4)
8623     return "j%C1\t%l0";
8624   else
8625     return "jg%C1\t%l0";
8626 }
8627   [(set_attr "op_type" "RI")
8628    (set_attr "type"    "branch")
8629    (set (attr "length")
8630         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8631                       (const_int 4) (const_int 6)))])
8632
8633 (define_insn "*cjump_31"
8634   [(set (pc)
8635         (if_then_else
8636           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8637                                                (match_operand 2 "const_int_operand" "")])
8638           (label_ref (match_operand 0 "" ""))
8639           (pc)))]
8640   "!TARGET_CPU_ZARCH"
8641 {
8642   gcc_assert (get_attr_length (insn) == 4);
8643   return "j%C1\t%l0";
8644 }
8645   [(set_attr "op_type" "RI")
8646    (set_attr "type"    "branch")
8647    (set (attr "length")
8648         (if_then_else (not (match_test "flag_pic"))
8649           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8650                         (const_int 4) (const_int 6))
8651           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8652                         (const_int 4) (const_int 8))))])
8653
8654 (define_insn "*cjump_long"
8655   [(set (pc)
8656         (if_then_else
8657           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8658           (match_operand 0 "address_operand" "ZQZR")
8659           (pc)))]
8660   ""
8661 {
8662   if (get_attr_op_type (insn) == OP_TYPE_RR)
8663     return "b%C1r\t%0";
8664   else
8665     return "b%C1\t%a0";
8666 }
8667   [(set (attr "op_type")
8668         (if_then_else (match_operand 0 "register_operand" "")
8669                       (const_string "RR") (const_string "RX")))
8670    (set_attr "type"  "branch")
8671    (set_attr "atype" "agen")])
8672
8673 ;; A conditional return instruction.
8674 (define_insn "*c<code>"
8675   [(set (pc)
8676         (if_then_else
8677           (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8678           (ANY_RETURN)
8679           (pc)))]
8680   "s390_can_use_<code>_insn ()"
8681   "b%C0r\t%%r14"
8682   [(set_attr "op_type" "RR")
8683    (set_attr "type"  "jsr")
8684    (set_attr "atype" "agen")])
8685
8686 ;;
8687 ;;- Negated conditional jump instructions.
8688 ;;
8689
8690 (define_insn "*icjump_64"
8691   [(set (pc)
8692         (if_then_else
8693           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8694           (pc)
8695           (label_ref (match_operand 0 "" ""))))]
8696   "TARGET_CPU_ZARCH"
8697 {
8698   if (get_attr_length (insn) == 4)
8699     return "j%D1\t%l0";
8700   else
8701     return "jg%D1\t%l0";
8702 }
8703   [(set_attr "op_type" "RI")
8704    (set_attr "type"    "branch")
8705    (set (attr "length")
8706         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8707                       (const_int 4) (const_int 6)))])
8708
8709 (define_insn "*icjump_31"
8710   [(set (pc)
8711         (if_then_else
8712           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8713           (pc)
8714           (label_ref (match_operand 0 "" ""))))]
8715   "!TARGET_CPU_ZARCH"
8716 {
8717   gcc_assert (get_attr_length (insn) == 4);
8718   return "j%D1\t%l0";
8719 }
8720   [(set_attr "op_type" "RI")
8721    (set_attr "type"    "branch")
8722    (set (attr "length")
8723         (if_then_else (not (match_test "flag_pic"))
8724           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8725                         (const_int 4) (const_int 6))
8726           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8727                         (const_int 4) (const_int 8))))])
8728
8729 (define_insn "*icjump_long"
8730   [(set (pc)
8731         (if_then_else
8732           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8733           (pc)
8734           (match_operand 0 "address_operand" "ZQZR")))]
8735   ""
8736 {
8737   if (get_attr_op_type (insn) == OP_TYPE_RR)
8738     return "b%D1r\t%0";
8739   else
8740     return "b%D1\t%a0";
8741 }
8742   [(set (attr "op_type")
8743         (if_then_else (match_operand 0 "register_operand" "")
8744                       (const_string "RR") (const_string "RX")))
8745    (set_attr "type"  "branch")
8746    (set_attr "atype" "agen")])
8747
8748 ;;
8749 ;;- Trap instructions.
8750 ;;
8751
8752 (define_insn "trap"
8753   [(trap_if (const_int 1) (const_int 0))]
8754   ""
8755   "j\t.+2"
8756   [(set_attr "op_type" "RI")
8757    (set_attr "type"  "branch")])
8758
8759 (define_expand "ctrap<mode>4"
8760   [(trap_if (match_operator 0 "comparison_operator"
8761              [(match_operand:GPR 1 "register_operand" "")
8762               (match_operand:GPR 2 "general_operand" "")])
8763              (match_operand 3 "const0_operand" ""))]
8764   ""
8765   {
8766     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8767                                   operands[1], operands[2]);
8768     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8769     DONE;
8770   })
8771
8772 (define_expand "ctrap<mode>4"
8773   [(trap_if (match_operator 0 "comparison_operator"
8774              [(match_operand:FP 1 "register_operand" "")
8775               (match_operand:FP 2 "general_operand" "")])
8776              (match_operand 3 "const0_operand" ""))]
8777   ""
8778   {
8779     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8780                                   operands[1], operands[2]);
8781     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8782     DONE;
8783   })
8784
8785 (define_insn "condtrap"
8786   [(trap_if (match_operator 0 "s390_comparison"
8787              [(match_operand 1 "cc_reg_operand" "c")
8788               (const_int 0)])
8789             (const_int 0))]
8790   ""
8791   "j%C0\t.+2";
8792   [(set_attr "op_type" "RI")
8793    (set_attr "type"  "branch")])
8794
8795 ; crt, cgrt, cit, cgit
8796 (define_insn "*cmp_and_trap_signed_int<mode>"
8797   [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8798                [(match_operand:GPR 1 "register_operand"  "d,d")
8799                 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8800             (const_int 0))]
8801   "TARGET_Z10"
8802   "@
8803    c<g>rt%C0\t%1,%2
8804    c<g>it%C0\t%1,%h2"
8805   [(set_attr "op_type" "RRF,RIE")
8806    (set_attr "type"    "branch")
8807    (set_attr "z10prop" "z10_super_c,z10_super")])
8808
8809 ; clrt, clgrt, clfit, clgit, clt, clgt
8810 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8811   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8812                [(match_operand:GPR 1 "register_operand" "d,d, d")
8813                 (match_operand:GPR 2 "general_operand"  "d,D,RT")])
8814             (const_int 0))]
8815   "TARGET_Z10"
8816   "@
8817    cl<g>rt%C0\t%1,%2
8818    cl<gf>it%C0\t%1,%x2
8819    cl<g>t%C0\t%1,%2"
8820   [(set_attr "op_type"      "RRF,RIE,RSY")
8821    (set_attr "type"         "branch")
8822    (set_attr "z10prop"      "z10_super_c,z10_super,*")
8823    (set_attr "cpu_facility" "z10,z10,zEC12")])
8824
8825 ; lat, lgat
8826 (define_insn "*load_and_trap<mode>"
8827   [(trap_if (eq (match_operand:GPR 0 "memory_operand"  "RT")
8828                 (const_int 0))
8829             (const_int 0))
8830    (set (match_operand:GPR 1 "register_operand" "=d")
8831         (match_dup 0))]
8832   "TARGET_ZEC12"
8833   "l<g>at\t%1,%0"
8834   [(set_attr "op_type" "RXY")])
8835
8836
8837 ;;
8838 ;;- Loop instructions.
8839 ;;
8840 ;;  This is all complicated by the fact that since this is a jump insn
8841 ;;  we must handle our own output reloads.
8842
8843 ;; branch on index
8844
8845 ; This splitter will be matched by combine and has to add the 2 moves
8846 ; necessary to load the compare and the increment values into a
8847 ; register pair as needed by brxle.
8848
8849 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8850   [(set (pc)
8851         (if_then_else
8852          (match_operator 6 "s390_brx_operator"
8853             [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8854                        (match_operand:GPR 2 "general_operand"  ""))
8855              (match_operand:GPR 3 "register_operand" "")])
8856          (label_ref (match_operand 0 "" ""))
8857          (pc)))
8858    (set (match_operand:GPR 4 "nonimmediate_operand" "")
8859         (plus:GPR (match_dup 1) (match_dup 2)))
8860    (clobber (match_scratch:GPR 5 ""))]
8861   "TARGET_CPU_ZARCH"
8862   "#"
8863   "!reload_completed && !reload_in_progress"
8864   [(set (match_dup 7) (match_dup 2)) ; the increment
8865    (set (match_dup 8) (match_dup 3)) ; the comparison value
8866    (parallel [(set (pc)
8867                    (if_then_else
8868                     (match_op_dup 6
8869                        [(plus:GPR (match_dup 1) (match_dup 7))
8870                         (match_dup 8)])
8871                     (label_ref (match_dup 0))
8872                     (pc)))
8873               (set (match_dup 4)
8874                    (plus:GPR (match_dup 1) (match_dup 7)))
8875               (clobber (match_dup 5))
8876               (clobber (reg:CC CC_REGNUM))])]
8877   {
8878     rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8879     operands[7] = gen_lowpart (<GPR:MODE>mode,
8880                                gen_highpart (word_mode, dreg));
8881     operands[8] = gen_lowpart (<GPR:MODE>mode,
8882                                gen_lowpart (word_mode, dreg));
8883   })
8884
8885 ; brxlg, brxhg
8886
8887 (define_insn_and_split "*brxg_64bit"
8888   [(set (pc)
8889         (if_then_else
8890           (match_operator 5 "s390_brx_operator"
8891              [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8892                        (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8893               (subreg:DI (match_dup 2) 8)])
8894           (label_ref (match_operand 0 "" ""))
8895           (pc)))
8896    (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8897         (plus:DI (match_dup 1)
8898                  (subreg:DI (match_dup 2) 0)))
8899    (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8900    (clobber (reg:CC CC_REGNUM))]
8901   "TARGET_ZARCH"
8902 {
8903   if (which_alternative != 0)
8904     return "#";
8905   else if (get_attr_length (insn) == 6)
8906     return "brx%E5g\t%1,%2,%l0";
8907   else
8908     return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8909 }
8910   "&& reload_completed
8911    && (!REG_P (operands[3])
8912        || !rtx_equal_p (operands[1], operands[3]))"
8913   [(set (match_dup 4) (match_dup 1))
8914    (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8915               (clobber (reg:CC CC_REGNUM))])
8916    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8917    (set (match_dup 3) (match_dup 4))
8918    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8919                            (label_ref (match_dup 0))
8920                            (pc)))]
8921   ""
8922   [(set_attr "op_type"  "RIE")
8923    (set_attr "type"  "branch")
8924    (set (attr "length")
8925         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8926                       (const_int 6) (const_int 16)))])
8927
8928 ; brxle, brxh
8929
8930 (define_insn_and_split "*brx_64bit"
8931   [(set (pc)
8932         (if_then_else
8933           (match_operator 5 "s390_brx_operator"
8934              [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8935                        (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8936               (subreg:SI (match_dup 2) 12)])
8937           (label_ref (match_operand 0 "" ""))
8938           (pc)))
8939    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8940         (plus:SI (match_dup 1)
8941                  (subreg:SI (match_dup 2) 4)))
8942    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8943    (clobber (reg:CC CC_REGNUM))]
8944   "TARGET_ZARCH"
8945 {
8946   if (which_alternative != 0)
8947     return "#";
8948   else if (get_attr_length (insn) == 6)
8949     return "brx%C5\t%1,%2,%l0";
8950   else
8951     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8952 }
8953   "&& reload_completed
8954    && (!REG_P (operands[3])
8955        || !rtx_equal_p (operands[1], operands[3]))"
8956   [(set (match_dup 4) (match_dup 1))
8957    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8958               (clobber (reg:CC CC_REGNUM))])
8959    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8960    (set (match_dup 3) (match_dup 4))
8961    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8962                            (label_ref (match_dup 0))
8963                            (pc)))]
8964   ""
8965   [(set_attr "op_type"  "RSI")
8966    (set_attr "type"  "branch")
8967    (set (attr "length")
8968         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8969                       (const_int 6) (const_int 14)))])
8970
8971 ; brxle, brxh
8972
8973 (define_insn_and_split "*brx_31bit"
8974   [(set (pc)
8975         (if_then_else
8976           (match_operator 5 "s390_brx_operator"
8977             [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8978                       (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8979              (subreg:SI (match_dup 2) 4)])
8980           (label_ref (match_operand 0 "" ""))
8981           (pc)))
8982    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8983         (plus:SI (match_dup 1)
8984                  (subreg:SI (match_dup 2) 0)))
8985    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8986    (clobber (reg:CC CC_REGNUM))]
8987   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8988 {
8989   if (which_alternative != 0)
8990     return "#";
8991   else if (get_attr_length (insn) == 6)
8992     return "brx%C5\t%1,%2,%l0";
8993   else
8994     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8995 }
8996   "&& reload_completed
8997    && (!REG_P (operands[3])
8998        || !rtx_equal_p (operands[1], operands[3]))"
8999   [(set (match_dup 4) (match_dup 1))
9000    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9001               (clobber (reg:CC CC_REGNUM))])
9002    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9003    (set (match_dup 3) (match_dup 4))
9004    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9005                            (label_ref (match_dup 0))
9006                            (pc)))]
9007   ""
9008   [(set_attr "op_type"  "RSI")
9009    (set_attr "type"  "branch")
9010    (set (attr "length")
9011         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9012                       (const_int 6) (const_int 14)))])
9013
9014
9015 ;; branch on count
9016
9017 (define_expand "doloop_end"
9018   [(use (match_operand 0 "" ""))        ; loop pseudo
9019    (use (match_operand 1 "" ""))]       ; label
9020   ""
9021 {
9022   if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9023     emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9024   else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9025     emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9026   else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9027     emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9028   else
9029     FAIL;
9030
9031   DONE;
9032 })
9033
9034 (define_insn_and_split "doloop_si64"
9035   [(set (pc)
9036         (if_then_else
9037           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9038               (const_int 1))
9039           (label_ref (match_operand 0 "" ""))
9040           (pc)))
9041    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9042         (plus:SI (match_dup 1) (const_int -1)))
9043    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9044    (clobber (reg:CC CC_REGNUM))]
9045   "TARGET_CPU_ZARCH"
9046 {
9047   if (which_alternative != 0)
9048     return "#";
9049   else if (get_attr_length (insn) == 4)
9050     return "brct\t%1,%l0";
9051   else
9052     return "ahi\t%1,-1\;jgne\t%l0";
9053 }
9054   "&& reload_completed
9055    && (! REG_P (operands[2])
9056        || ! rtx_equal_p (operands[1], operands[2]))"
9057   [(set (match_dup 3) (match_dup 1))
9058    (parallel [(set (reg:CCAN CC_REGNUM)
9059                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9060                                  (const_int 0)))
9061               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9062    (set (match_dup 2) (match_dup 3))
9063    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9064                            (label_ref (match_dup 0))
9065                            (pc)))]
9066   ""
9067   [(set_attr "op_type"  "RI")
9068    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9069    ; hurt us in the (rare) case of ahi.
9070    (set_attr "z10prop"  "z10_super_E1")
9071    (set_attr "type"  "branch")
9072    (set (attr "length")
9073         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9074                       (const_int 4) (const_int 10)))])
9075
9076 (define_insn_and_split "doloop_si31"
9077   [(set (pc)
9078         (if_then_else
9079           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9080               (const_int 1))
9081           (label_ref (match_operand 0 "" ""))
9082           (pc)))
9083    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9084         (plus:SI (match_dup 1) (const_int -1)))
9085    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9086    (clobber (reg:CC CC_REGNUM))]
9087   "!TARGET_CPU_ZARCH"
9088 {
9089   if (which_alternative != 0)
9090     return "#";
9091   else if (get_attr_length (insn) == 4)
9092     return "brct\t%1,%l0";
9093   else
9094     gcc_unreachable ();
9095 }
9096   "&& reload_completed
9097    && (! REG_P (operands[2])
9098        || ! rtx_equal_p (operands[1], operands[2]))"
9099   [(set (match_dup 3) (match_dup 1))
9100    (parallel [(set (reg:CCAN CC_REGNUM)
9101                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9102                                  (const_int 0)))
9103               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9104    (set (match_dup 2) (match_dup 3))
9105    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9106                            (label_ref (match_dup 0))
9107                            (pc)))]
9108   ""
9109   [(set_attr "op_type"  "RI")
9110    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9111    ; hurt us in the (rare) case of ahi.
9112    (set_attr "z10prop"  "z10_super_E1")
9113    (set_attr "type"  "branch")
9114    (set (attr "length")
9115         (if_then_else (not (match_test "flag_pic"))
9116           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9117                         (const_int 4) (const_int 6))
9118           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9119                         (const_int 4) (const_int 8))))])
9120
9121 (define_insn "*doloop_si_long"
9122   [(set (pc)
9123         (if_then_else
9124           (ne (match_operand:SI 1 "register_operand" "d")
9125               (const_int 1))
9126           (match_operand 0 "address_operand" "ZQZR")
9127           (pc)))
9128    (set (match_operand:SI 2 "register_operand" "=1")
9129         (plus:SI (match_dup 1) (const_int -1)))
9130    (clobber (match_scratch:SI 3 "=X"))
9131    (clobber (reg:CC CC_REGNUM))]
9132   "!TARGET_CPU_ZARCH"
9133 {
9134   if (get_attr_op_type (insn) == OP_TYPE_RR)
9135     return "bctr\t%1,%0";
9136   else
9137     return "bct\t%1,%a0";
9138 }
9139   [(set (attr "op_type")
9140         (if_then_else (match_operand 0 "register_operand" "")
9141                       (const_string "RR") (const_string "RX")))
9142    (set_attr "type"  "branch")
9143    (set_attr "atype" "agen")
9144    (set_attr "z10prop"  "z10_c")
9145    (set_attr "z196prop" "z196_cracked")])
9146
9147 (define_insn_and_split "doloop_di"
9148   [(set (pc)
9149         (if_then_else
9150           (ne (match_operand:DI 1 "register_operand" "d,d,d")
9151               (const_int 1))
9152           (label_ref (match_operand 0 "" ""))
9153           (pc)))
9154    (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9155         (plus:DI (match_dup 1) (const_int -1)))
9156    (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9157    (clobber (reg:CC CC_REGNUM))]
9158   "TARGET_ZARCH"
9159 {
9160   if (which_alternative != 0)
9161     return "#";
9162   else if (get_attr_length (insn) == 4)
9163     return "brctg\t%1,%l0";
9164   else
9165     return "aghi\t%1,-1\;jgne\t%l0";
9166 }
9167   "&& reload_completed
9168    && (! REG_P (operands[2])
9169        || ! rtx_equal_p (operands[1], operands[2]))"
9170   [(set (match_dup 3) (match_dup 1))
9171    (parallel [(set (reg:CCAN CC_REGNUM)
9172                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9173                                  (const_int 0)))
9174               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9175    (set (match_dup 2) (match_dup 3))
9176    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9177                            (label_ref (match_dup 0))
9178                            (pc)))]
9179   ""
9180   [(set_attr "op_type"  "RI")
9181    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9182    ; hurt us in the (rare) case of ahi.
9183    (set_attr "z10prop"  "z10_super_E1")
9184    (set_attr "type"  "branch")
9185    (set (attr "length")
9186         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9187                       (const_int 4) (const_int 10)))])
9188
9189 ;;
9190 ;;- Unconditional jump instructions.
9191 ;;
9192
9193 ;
9194 ; jump instruction pattern(s).
9195 ;
9196
9197 (define_expand "jump"
9198   [(match_operand 0 "" "")]
9199   ""
9200   "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9201
9202 (define_insn "*jump64"
9203   [(set (pc) (label_ref (match_operand 0 "" "")))]
9204   "TARGET_CPU_ZARCH"
9205 {
9206   if (get_attr_length (insn) == 4)
9207     return "j\t%l0";
9208   else
9209     return "jg\t%l0";
9210 }
9211   [(set_attr "op_type" "RI")
9212    (set_attr "type"  "branch")
9213    (set (attr "length")
9214         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9215                       (const_int 4) (const_int 6)))])
9216
9217 (define_insn "*jump31"
9218   [(set (pc) (label_ref (match_operand 0 "" "")))]
9219   "!TARGET_CPU_ZARCH"
9220 {
9221   gcc_assert (get_attr_length (insn) == 4);
9222   return "j\t%l0";
9223 }
9224   [(set_attr "op_type" "RI")
9225    (set_attr "type"  "branch")
9226    (set (attr "length")
9227         (if_then_else (not (match_test "flag_pic"))
9228           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9229                         (const_int 4) (const_int 6))
9230           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9231                         (const_int 4) (const_int 8))))])
9232
9233 ;
9234 ; indirect-jump instruction pattern(s).
9235 ;
9236
9237 (define_insn "indirect_jump"
9238  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
9239   ""
9240 {
9241   if (get_attr_op_type (insn) == OP_TYPE_RR)
9242     return "br\t%0";
9243   else
9244     return "b\t%a0";
9245 }
9246   [(set (attr "op_type")
9247         (if_then_else (match_operand 0 "register_operand" "")
9248                       (const_string "RR") (const_string "RX")))
9249    (set_attr "type"  "branch")
9250    (set_attr "atype" "agen")])
9251
9252 ;
9253 ; casesi instruction pattern(s).
9254 ;
9255
9256 (define_insn "casesi_jump"
9257  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
9258    (use (label_ref (match_operand 1 "" "")))]
9259   ""
9260 {
9261   if (get_attr_op_type (insn) == OP_TYPE_RR)
9262     return "br\t%0";
9263   else
9264     return "b\t%a0";
9265 }
9266   [(set (attr "op_type")
9267         (if_then_else (match_operand 0 "register_operand" "")
9268                       (const_string "RR") (const_string "RX")))
9269    (set_attr "type"  "branch")
9270    (set_attr "atype" "agen")])
9271
9272 (define_expand "casesi"
9273   [(match_operand:SI 0 "general_operand" "")
9274    (match_operand:SI 1 "general_operand" "")
9275    (match_operand:SI 2 "general_operand" "")
9276    (label_ref (match_operand 3 "" ""))
9277    (label_ref (match_operand 4 "" ""))]
9278   ""
9279 {
9280    rtx index  = gen_reg_rtx (SImode);
9281    rtx base   = gen_reg_rtx (Pmode);
9282    rtx target = gen_reg_rtx (Pmode);
9283
9284    emit_move_insn (index, operands[0]);
9285    emit_insn (gen_subsi3 (index, index, operands[1]));
9286    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9287                             operands[4]);
9288
9289    if (Pmode != SImode)
9290      index = convert_to_mode (Pmode, index, 1);
9291    if (GET_CODE (index) != REG)
9292      index = copy_to_mode_reg (Pmode, index);
9293
9294    if (TARGET_64BIT)
9295        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9296    else
9297        emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9298
9299    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9300
9301    index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9302    emit_move_insn (target, index);
9303
9304    if (flag_pic)
9305      target = gen_rtx_PLUS (Pmode, base, target);
9306    emit_jump_insn (gen_casesi_jump (target, operands[3]));
9307
9308    DONE;
9309 })
9310
9311
9312 ;;
9313 ;;- Jump to subroutine.
9314 ;;
9315 ;;
9316
9317 ;
9318 ; untyped call instruction pattern(s).
9319 ;
9320
9321 ;; Call subroutine returning any type.
9322 (define_expand "untyped_call"
9323   [(parallel [(call (match_operand 0 "" "")
9324                     (const_int 0))
9325               (match_operand 1 "" "")
9326               (match_operand 2 "" "")])]
9327   ""
9328 {
9329   int i;
9330
9331   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9332
9333   for (i = 0; i < XVECLEN (operands[2], 0); i++)
9334     {
9335       rtx set = XVECEXP (operands[2], 0, i);
9336       emit_move_insn (SET_DEST (set), SET_SRC (set));
9337     }
9338
9339   /* The optimizer does not know that the call sets the function value
9340      registers we stored in the result block.  We avoid problems by
9341      claiming that all hard registers are used and clobbered at this
9342      point.  */
9343   emit_insn (gen_blockage ());
9344
9345   DONE;
9346 })
9347
9348 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9349 ;; all of memory.  This blocks insns from being moved across this point.
9350
9351 (define_insn "blockage"
9352   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9353   ""
9354   ""
9355   [(set_attr "type"    "none")
9356    (set_attr "length"  "0")])
9357
9358 ;
9359 ; sibcall patterns
9360 ;
9361
9362 (define_expand "sibcall"
9363   [(call (match_operand 0 "" "")
9364          (match_operand 1 "" ""))]
9365   ""
9366 {
9367   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9368   DONE;
9369 })
9370
9371 (define_insn "*sibcall_br"
9372   [(call (mem:QI (reg SIBCALL_REGNUM))
9373          (match_operand 0 "const_int_operand" "n"))]
9374   "SIBLING_CALL_P (insn)
9375    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9376   "br\t%%r1"
9377   [(set_attr "op_type" "RR")
9378    (set_attr "type"  "branch")
9379    (set_attr "atype" "agen")])
9380
9381 (define_insn "*sibcall_brc"
9382   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9383          (match_operand 1 "const_int_operand" "n"))]
9384   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9385   "j\t%0"
9386   [(set_attr "op_type" "RI")
9387    (set_attr "type"    "branch")])
9388
9389 (define_insn "*sibcall_brcl"
9390   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9391          (match_operand 1 "const_int_operand" "n"))]
9392   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9393   "jg\t%0"
9394   [(set_attr "op_type" "RIL")
9395    (set_attr "type"    "branch")])
9396
9397 ;
9398 ; sibcall_value patterns
9399 ;
9400
9401 (define_expand "sibcall_value"
9402   [(set (match_operand 0 "" "")
9403         (call (match_operand 1 "" "")
9404               (match_operand 2 "" "")))]
9405   ""
9406 {
9407   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9408   DONE;
9409 })
9410
9411 (define_insn "*sibcall_value_br"
9412   [(set (match_operand 0 "" "")
9413         (call (mem:QI (reg SIBCALL_REGNUM))
9414               (match_operand 1 "const_int_operand" "n")))]
9415   "SIBLING_CALL_P (insn)
9416    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9417   "br\t%%r1"
9418   [(set_attr "op_type" "RR")
9419    (set_attr "type"  "branch")
9420    (set_attr "atype" "agen")])
9421
9422 (define_insn "*sibcall_value_brc"
9423   [(set (match_operand 0 "" "")
9424         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9425               (match_operand 2 "const_int_operand" "n")))]
9426   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9427   "j\t%1"
9428   [(set_attr "op_type" "RI")
9429    (set_attr "type"    "branch")])
9430
9431 (define_insn "*sibcall_value_brcl"
9432   [(set (match_operand 0 "" "")
9433         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9434               (match_operand 2 "const_int_operand" "n")))]
9435   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9436   "jg\t%1"
9437   [(set_attr "op_type" "RIL")
9438    (set_attr "type"    "branch")])
9439
9440
9441 ;
9442 ; call instruction pattern(s).
9443 ;
9444
9445 (define_expand "call"
9446   [(call (match_operand 0 "" "")
9447          (match_operand 1 "" ""))
9448    (use (match_operand 2 "" ""))]
9449   ""
9450 {
9451   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9452                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9453   DONE;
9454 })
9455
9456 (define_insn "*bras"
9457   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9458          (match_operand 1 "const_int_operand" "n"))
9459    (clobber (match_operand 2 "register_operand" "=r"))]
9460   "!SIBLING_CALL_P (insn)
9461    && TARGET_SMALL_EXEC
9462    && GET_MODE (operands[2]) == Pmode"
9463   "bras\t%2,%0"
9464   [(set_attr "op_type" "RI")
9465    (set_attr "type"    "jsr")
9466    (set_attr "z196prop" "z196_cracked")])
9467
9468 (define_insn "*brasl"
9469   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9470          (match_operand 1 "const_int_operand" "n"))
9471    (clobber (match_operand 2 "register_operand" "=r"))]
9472   "!SIBLING_CALL_P (insn)
9473    && TARGET_CPU_ZARCH
9474    && GET_MODE (operands[2]) == Pmode"
9475   "brasl\t%2,%0"
9476   [(set_attr "op_type" "RIL")
9477    (set_attr "type"    "jsr")
9478    (set_attr "z196prop" "z196_cracked")])
9479
9480 (define_insn "*basr"
9481   [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9482          (match_operand 1 "const_int_operand" "n"))
9483    (clobber (match_operand 2 "register_operand" "=r"))]
9484   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9485 {
9486   if (get_attr_op_type (insn) == OP_TYPE_RR)
9487     return "basr\t%2,%0";
9488   else
9489     return "bas\t%2,%a0";
9490 }
9491   [(set (attr "op_type")
9492         (if_then_else (match_operand 0 "register_operand" "")
9493                       (const_string "RR") (const_string "RX")))
9494    (set_attr "type"  "jsr")
9495    (set_attr "atype" "agen")
9496    (set_attr "z196prop" "z196_cracked")])
9497
9498 ;
9499 ; call_value instruction pattern(s).
9500 ;
9501
9502 (define_expand "call_value"
9503   [(set (match_operand 0 "" "")
9504         (call (match_operand 1 "" "")
9505               (match_operand 2 "" "")))
9506    (use (match_operand 3 "" ""))]
9507   ""
9508 {
9509   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9510                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9511   DONE;
9512 })
9513
9514 (define_insn "*bras_r"
9515   [(set (match_operand 0 "" "")
9516         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9517               (match_operand:SI 2 "const_int_operand" "n")))
9518    (clobber (match_operand 3 "register_operand" "=r"))]
9519   "!SIBLING_CALL_P (insn)
9520    && TARGET_SMALL_EXEC
9521    && GET_MODE (operands[3]) == Pmode"
9522   "bras\t%3,%1"
9523   [(set_attr "op_type" "RI")
9524    (set_attr "type"    "jsr")
9525    (set_attr "z196prop" "z196_cracked")])
9526
9527 (define_insn "*brasl_r"
9528   [(set (match_operand 0 "" "")
9529         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9530               (match_operand 2 "const_int_operand" "n")))
9531    (clobber (match_operand 3 "register_operand" "=r"))]
9532   "!SIBLING_CALL_P (insn)
9533    && TARGET_CPU_ZARCH
9534    && GET_MODE (operands[3]) == Pmode"
9535   "brasl\t%3,%1"
9536   [(set_attr "op_type" "RIL")
9537    (set_attr "type"    "jsr")
9538    (set_attr "z196prop" "z196_cracked")])
9539
9540 (define_insn "*basr_r"
9541   [(set (match_operand 0 "" "")
9542         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9543               (match_operand 2 "const_int_operand" "n")))
9544    (clobber (match_operand 3 "register_operand" "=r"))]
9545   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9546 {
9547   if (get_attr_op_type (insn) == OP_TYPE_RR)
9548     return "basr\t%3,%1";
9549   else
9550     return "bas\t%3,%a1";
9551 }
9552   [(set (attr "op_type")
9553         (if_then_else (match_operand 1 "register_operand" "")
9554                       (const_string "RR") (const_string "RX")))
9555    (set_attr "type"  "jsr")
9556    (set_attr "atype" "agen")
9557    (set_attr "z196prop" "z196_cracked")])
9558
9559 ;;
9560 ;;- Thread-local storage support.
9561 ;;
9562
9563 (define_expand "get_thread_pointer<mode>"
9564   [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9565   ""
9566   "")
9567
9568 (define_expand "set_thread_pointer<mode>"
9569   [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9570    (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9571   ""
9572   "")
9573
9574 (define_insn "*set_tp"
9575   [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9576   ""
9577   ""
9578   [(set_attr "type" "none")
9579    (set_attr "length" "0")])
9580
9581 (define_insn "*tls_load_64"
9582   [(set (match_operand:DI 0 "register_operand" "=d")
9583         (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9584                     (match_operand:DI 2 "" "")]
9585                    UNSPEC_TLS_LOAD))]
9586   "TARGET_64BIT"
9587   "lg\t%0,%1%J2"
9588   [(set_attr "op_type" "RXE")
9589    (set_attr "z10prop" "z10_fwd_A3")])
9590
9591 (define_insn "*tls_load_31"
9592   [(set (match_operand:SI 0 "register_operand" "=d,d")
9593         (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9594                     (match_operand:SI 2 "" "")]
9595                    UNSPEC_TLS_LOAD))]
9596   "!TARGET_64BIT"
9597   "@
9598    l\t%0,%1%J2
9599    ly\t%0,%1%J2"
9600   [(set_attr "op_type" "RX,RXY")
9601    (set_attr "type" "load")
9602    (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9603
9604 (define_insn "*bras_tls"
9605   [(set (match_operand 0 "" "")
9606         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9607               (match_operand 2 "const_int_operand" "n")))
9608    (clobber (match_operand 3 "register_operand" "=r"))
9609    (use (match_operand 4 "" ""))]
9610   "!SIBLING_CALL_P (insn)
9611    && TARGET_SMALL_EXEC
9612    && GET_MODE (operands[3]) == Pmode"
9613   "bras\t%3,%1%J4"
9614   [(set_attr "op_type" "RI")
9615    (set_attr "type"    "jsr")
9616    (set_attr "z196prop" "z196_cracked")])
9617
9618 (define_insn "*brasl_tls"
9619   [(set (match_operand 0 "" "")
9620         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9621               (match_operand 2 "const_int_operand" "n")))
9622    (clobber (match_operand 3 "register_operand" "=r"))
9623    (use (match_operand 4 "" ""))]
9624   "!SIBLING_CALL_P (insn)
9625    && TARGET_CPU_ZARCH
9626    && GET_MODE (operands[3]) == Pmode"
9627   "brasl\t%3,%1%J4"
9628   [(set_attr "op_type" "RIL")
9629    (set_attr "type"    "jsr")
9630    (set_attr "z196prop" "z196_cracked")])
9631
9632 (define_insn "*basr_tls"
9633   [(set (match_operand 0 "" "")
9634         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9635               (match_operand 2 "const_int_operand" "n")))
9636    (clobber (match_operand 3 "register_operand" "=r"))
9637    (use (match_operand 4 "" ""))]
9638   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9639 {
9640   if (get_attr_op_type (insn) == OP_TYPE_RR)
9641     return "basr\t%3,%1%J4";
9642   else
9643     return "bas\t%3,%a1%J4";
9644 }
9645   [(set (attr "op_type")
9646         (if_then_else (match_operand 1 "register_operand" "")
9647                       (const_string "RR") (const_string "RX")))
9648    (set_attr "type"  "jsr")
9649    (set_attr "atype" "agen")
9650    (set_attr "z196prop" "z196_cracked")])
9651
9652 ;;
9653 ;;- Atomic operations
9654 ;;
9655
9656 ;
9657 ; memory barrier patterns.
9658 ;
9659
9660 (define_expand "mem_signal_fence"
9661   [(match_operand:SI 0 "const_int_operand")]            ;; model
9662   ""
9663 {
9664   /* The s390 memory model is strong enough not to require any
9665      barrier in order to synchronize a thread with itself.  */
9666   DONE;
9667 })
9668
9669 (define_expand "mem_thread_fence"
9670   [(match_operand:SI 0 "const_int_operand")]            ;; model
9671   ""
9672 {
9673   /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9674      enough not to require barriers of any kind.  */
9675   if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9676     {
9677       rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9678       MEM_VOLATILE_P (mem) = 1;
9679       emit_insn (gen_mem_thread_fence_1 (mem));
9680     }
9681   DONE;
9682 })
9683
9684 ; Although bcr is superscalar on Z10, this variant will never
9685 ; become part of an execution group.
9686 ; With z196 we can make use of the fast-BCR-serialization facility.
9687 ; This allows for a slightly faster sync which is sufficient for our
9688 ; purposes.
9689 (define_insn "mem_thread_fence_1"
9690   [(set (match_operand:BLK 0 "" "")
9691         (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9692   ""
9693 {
9694   if (TARGET_Z196)
9695     return "bcr\t14,0";
9696   else
9697     return "bcr\t15,0";
9698 }
9699   [(set_attr "op_type" "RR")
9700    (set_attr "mnemonic" "bcr_flush")
9701    (set_attr "z196prop" "z196_alone")])
9702
9703 ;
9704 ; atomic load/store operations
9705 ;
9706
9707 ; Atomic loads need not examine the memory model at all.
9708 (define_expand "atomic_load<mode>"
9709   [(match_operand:DINT 0 "register_operand")    ;; output
9710    (match_operand:DINT 1 "memory_operand")      ;; memory
9711    (match_operand:SI 2 "const_int_operand")]    ;; model
9712   ""
9713 {
9714   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9715     FAIL;
9716
9717   if (<MODE>mode == TImode)
9718     emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9719   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9720     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9721   else
9722     emit_move_insn (operands[0], operands[1]);
9723   DONE;
9724 })
9725
9726 ; Different from movdi_31 in that we want no splitters.
9727 (define_insn "atomic_loaddi_1"
9728   [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9729         (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9730                    UNSPEC_MOVA))]
9731   "!TARGET_ZARCH"
9732   "@
9733    lm\t%0,%M0,%S1
9734    lmy\t%0,%M0,%S1
9735    ld\t%0,%1
9736    ldy\t%0,%1"
9737   [(set_attr "op_type" "RS,RSY,RS,RSY")
9738    (set_attr "type" "lm,lm,floaddf,floaddf")])
9739
9740 (define_insn "atomic_loadti_1"
9741   [(set (match_operand:TI 0 "register_operand" "=r")
9742         (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9743                    UNSPEC_MOVA))]
9744   "TARGET_ZARCH"
9745   "lpq\t%0,%1"
9746   [(set_attr "op_type" "RXY")
9747    (set_attr "type" "other")])
9748
9749 ; Atomic stores must(?) enforce sequential consistency.
9750 (define_expand "atomic_store<mode>"
9751   [(match_operand:DINT 0 "memory_operand")      ;; memory
9752    (match_operand:DINT 1 "register_operand")    ;; input
9753    (match_operand:SI 2 "const_int_operand")]    ;; model
9754   ""
9755 {
9756   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9757
9758   if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9759     FAIL;
9760
9761   if (<MODE>mode == TImode)
9762     emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9763   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9764     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9765   else
9766     emit_move_insn (operands[0], operands[1]);
9767   if (is_mm_seq_cst (model))
9768     emit_insn (gen_mem_thread_fence (operands[2]));
9769   DONE;
9770 })
9771
9772 ; Different from movdi_31 in that we want no splitters.
9773 (define_insn "atomic_storedi_1"
9774   [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9775         (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9776                    UNSPEC_MOVA))]
9777   "!TARGET_ZARCH"
9778   "@
9779    stm\t%1,%N1,%S0
9780    stmy\t%1,%N1,%S0
9781    std %1,%0
9782    stdy %1,%0"
9783   [(set_attr "op_type" "RS,RSY,RS,RSY")
9784    (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9785
9786 (define_insn "atomic_storeti_1"
9787   [(set (match_operand:TI 0 "memory_operand" "=RT")
9788         (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9789                    UNSPEC_MOVA))]
9790   "TARGET_ZARCH"
9791   "stpq\t%1,%0"
9792   [(set_attr "op_type" "RXY")
9793    (set_attr "type" "other")])
9794
9795 ;
9796 ; compare and swap patterns.
9797 ;
9798
9799 (define_expand "atomic_compare_and_swap<mode>"
9800   [(match_operand:SI 0 "register_operand")      ;; bool success output
9801    (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9802    (match_operand:DGPR 2 "memory_operand")      ;; memory
9803    (match_operand:DGPR 3 "register_operand")    ;; expected intput
9804    (match_operand:DGPR 4 "register_operand")    ;; newval intput
9805    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9806    (match_operand:SI 6 "const_int_operand")     ;; success model
9807    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9808   ""
9809 {
9810   rtx cc, cmp, output = operands[1];
9811
9812   if (!register_operand (output, <MODE>mode))
9813     output = gen_reg_rtx (<MODE>mode);
9814
9815   if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9816     FAIL;
9817
9818   emit_insn (gen_atomic_compare_and_swap<mode>_internal
9819              (output, operands[2], operands[3], operands[4]));
9820
9821   /* We deliberately accept non-register operands in the predicate
9822      to ensure the write back to the output operand happens *before*
9823      the store-flags code below.  This makes it easier for combine
9824      to merge the store-flags code with a potential test-and-branch
9825      pattern following (immediately!) afterwards.  */
9826   if (output != operands[1])
9827     emit_move_insn (operands[1], output);
9828
9829   cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9830   cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9831   emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9832   DONE;
9833 })
9834
9835 (define_expand "atomic_compare_and_swap<mode>"
9836   [(match_operand:SI 0 "register_operand")      ;; bool success output
9837    (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9838    (match_operand:HQI 2 "memory_operand")       ;; memory
9839    (match_operand:HQI 3 "general_operand")      ;; expected intput
9840    (match_operand:HQI 4 "general_operand")      ;; newval intput
9841    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9842    (match_operand:SI 6 "const_int_operand")     ;; success model
9843    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9844   ""
9845 {
9846   s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9847                       operands[3], operands[4], INTVAL (operands[5]));
9848   DONE;
9849 })
9850
9851 (define_expand "atomic_compare_and_swap<mode>_internal"
9852   [(parallel
9853      [(set (match_operand:DGPR 0 "register_operand")
9854            (match_operand:DGPR 1 "memory_operand"))
9855       (set (match_dup 1)
9856            (unspec_volatile:DGPR
9857              [(match_dup 1)
9858               (match_operand:DGPR 2 "register_operand")
9859               (match_operand:DGPR 3 "register_operand")]
9860              UNSPECV_CAS))
9861       (set (reg:CCZ1 CC_REGNUM)
9862            (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9863   "")
9864
9865 ; cdsg, csg
9866 (define_insn "*atomic_compare_and_swap<mode>_1"
9867   [(set (match_operand:TDI 0 "register_operand" "=r")
9868         (match_operand:TDI 1 "memory_operand" "+QS"))
9869    (set (match_dup 1)
9870         (unspec_volatile:TDI
9871           [(match_dup 1)
9872            (match_operand:TDI 2 "register_operand" "0")
9873            (match_operand:TDI 3 "register_operand" "r")]
9874           UNSPECV_CAS))
9875    (set (reg:CCZ1 CC_REGNUM)
9876         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9877   "TARGET_ZARCH"
9878   "c<td>sg\t%0,%3,%S1"
9879   [(set_attr "op_type" "RSY")
9880    (set_attr "type"   "sem")])
9881
9882 ; cds, cdsy
9883 (define_insn "*atomic_compare_and_swapdi_2"
9884   [(set (match_operand:DI 0 "register_operand" "=r,r")
9885         (match_operand:DI 1 "memory_operand" "+Q,S"))
9886    (set (match_dup 1)
9887         (unspec_volatile:DI
9888           [(match_dup 1)
9889            (match_operand:DI 2 "register_operand" "0,0")
9890            (match_operand:DI 3 "register_operand" "r,r")]
9891           UNSPECV_CAS))
9892    (set (reg:CCZ1 CC_REGNUM)
9893         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9894   "!TARGET_ZARCH"
9895   "@
9896    cds\t%0,%3,%S1
9897    cdsy\t%0,%3,%S1"
9898   [(set_attr "op_type" "RS,RSY")
9899    (set_attr "type" "sem")])
9900
9901 ; cs, csy
9902 (define_insn "*atomic_compare_and_swapsi_3"
9903   [(set (match_operand:SI 0 "register_operand" "=r,r")
9904         (match_operand:SI 1 "memory_operand" "+Q,S"))
9905    (set (match_dup 1)
9906         (unspec_volatile:SI
9907           [(match_dup 1)
9908            (match_operand:SI 2 "register_operand" "0,0")
9909            (match_operand:SI 3 "register_operand" "r,r")]
9910           UNSPECV_CAS))
9911    (set (reg:CCZ1 CC_REGNUM)
9912         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9913   ""
9914   "@
9915    cs\t%0,%3,%S1
9916    csy\t%0,%3,%S1"
9917   [(set_attr "op_type" "RS,RSY")
9918    (set_attr "type"   "sem")])
9919
9920 ;
9921 ; Other atomic instruction patterns.
9922 ;
9923
9924 ; z196 load and add, xor, or and and instructions
9925
9926 (define_expand "atomic_fetch_<atomic><mode>"
9927   [(match_operand:GPR 0 "register_operand")             ;; val out
9928    (ATOMIC_Z196:GPR
9929      (match_operand:GPR 1 "memory_operand")             ;; memory
9930      (match_operand:GPR 2 "register_operand"))          ;; val in
9931    (match_operand:SI 3 "const_int_operand")]            ;; model
9932   "TARGET_Z196"
9933 {
9934   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9935     FAIL;
9936
9937   emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9938              (operands[0], operands[1], operands[2]));
9939   DONE;
9940 })
9941
9942 ; lan, lang, lao, laog, lax, laxg, laa, laag
9943 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9944   [(set (match_operand:GPR 0 "register_operand" "=d")
9945         (match_operand:GPR 1 "memory_operand" "+QS"))
9946    (set (match_dup 1)
9947         (unspec_volatile:GPR
9948          [(ATOMIC_Z196:GPR (match_dup 1)
9949                            (match_operand:GPR 2 "general_operand" "d"))]
9950          UNSPECV_ATOMIC_OP))
9951    (clobber (reg:CC CC_REGNUM))]
9952   "TARGET_Z196"
9953   "la<noxa><g>\t%0,%2,%1"
9954   [(set_attr "op_type" "RSY")
9955    (set_attr "type" "sem")])
9956
9957 ;; For SImode and larger, the optabs.c code will do just fine in
9958 ;; expanding a compare-and-swap loop.  For QI/HImode, we can do
9959 ;; better by expanding our own loop.
9960
9961 (define_expand "atomic_<atomic><mode>"
9962   [(ATOMIC:HQI
9963      (match_operand:HQI 0 "memory_operand")             ;; memory
9964      (match_operand:HQI 1 "general_operand"))           ;; val in
9965    (match_operand:SI 2 "const_int_operand")]            ;; model
9966   ""
9967 {
9968   s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9969                        operands[1], false);
9970   DONE;
9971 })
9972
9973 (define_expand "atomic_fetch_<atomic><mode>"
9974   [(match_operand:HQI 0 "register_operand")             ;; val out
9975    (ATOMIC:HQI
9976      (match_operand:HQI 1 "memory_operand")             ;; memory
9977      (match_operand:HQI 2 "general_operand"))           ;; val in
9978    (match_operand:SI 3 "const_int_operand")]            ;; model
9979   ""
9980 {
9981   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9982                       operands[2], false);
9983   DONE;
9984 })
9985
9986 (define_expand "atomic_<atomic>_fetch<mode>"
9987   [(match_operand:HQI 0 "register_operand")             ;; val out
9988    (ATOMIC:HQI
9989      (match_operand:HQI 1 "memory_operand")             ;; memory
9990      (match_operand:HQI 2 "general_operand"))           ;; val in
9991    (match_operand:SI 3 "const_int_operand")]            ;; model
9992   ""
9993 {
9994   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9995                       operands[2], true);
9996   DONE;
9997 })
9998
9999 (define_expand "atomic_exchange<mode>"
10000   [(match_operand:HQI 0 "register_operand")             ;; val out
10001    (match_operand:HQI 1 "memory_operand")               ;; memory
10002    (match_operand:HQI 2 "general_operand")              ;; val in
10003    (match_operand:SI 3 "const_int_operand")]            ;; model
10004   ""
10005 {
10006   s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10007                       operands[2], false);
10008   DONE;
10009 })
10010
10011 ;;
10012 ;;- Miscellaneous instructions.
10013 ;;
10014
10015 ;
10016 ; allocate stack instruction pattern(s).
10017 ;
10018
10019 (define_expand "allocate_stack"
10020   [(match_operand 0 "general_operand" "")
10021    (match_operand 1 "general_operand" "")]
10022  "TARGET_BACKCHAIN"
10023 {
10024   rtx temp = gen_reg_rtx (Pmode);
10025
10026   emit_move_insn (temp, s390_back_chain_rtx ());
10027   anti_adjust_stack (operands[1]);
10028   emit_move_insn (s390_back_chain_rtx (), temp);
10029
10030   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10031   DONE;
10032 })
10033
10034
10035 ;
10036 ; setjmp instruction pattern.
10037 ;
10038
10039 (define_expand "builtin_setjmp_receiver"
10040   [(match_operand 0 "" "")]
10041   "flag_pic"
10042 {
10043   emit_insn (s390_load_got ());
10044   emit_use (pic_offset_table_rtx);
10045   DONE;
10046 })
10047
10048 ;; These patterns say how to save and restore the stack pointer.  We need not
10049 ;; save the stack pointer at function level since we are careful to
10050 ;; preserve the backchain.  At block level, we have to restore the backchain
10051 ;; when we restore the stack pointer.
10052 ;;
10053 ;; For nonlocal gotos, we must save both the stack pointer and its
10054 ;; backchain and restore both.  Note that in the nonlocal case, the
10055 ;; save area is a memory location.
10056
10057 (define_expand "save_stack_function"
10058   [(match_operand 0 "general_operand" "")
10059    (match_operand 1 "general_operand" "")]
10060   ""
10061   "DONE;")
10062
10063 (define_expand "restore_stack_function"
10064   [(match_operand 0 "general_operand" "")
10065    (match_operand 1 "general_operand" "")]
10066   ""
10067   "DONE;")
10068
10069 (define_expand "restore_stack_block"
10070   [(match_operand 0 "register_operand" "")
10071    (match_operand 1 "register_operand" "")]
10072   "TARGET_BACKCHAIN"
10073 {
10074   rtx temp = gen_reg_rtx (Pmode);
10075
10076   emit_move_insn (temp, s390_back_chain_rtx ());
10077   emit_move_insn (operands[0], operands[1]);
10078   emit_move_insn (s390_back_chain_rtx (), temp);
10079
10080   DONE;
10081 })
10082
10083 (define_expand "save_stack_nonlocal"
10084   [(match_operand 0 "memory_operand" "")
10085    (match_operand 1 "register_operand" "")]
10086   ""
10087 {
10088   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10089
10090   /* Copy the backchain to the first word, sp to the second and the
10091      literal pool base to the third.  */
10092
10093   rtx save_bc = adjust_address (operands[0], Pmode, 0);
10094   rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10095   rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10096
10097   if (TARGET_BACKCHAIN)
10098     emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10099
10100   emit_move_insn (save_sp, operands[1]);
10101   emit_move_insn (save_bp, base);
10102
10103   DONE;
10104 })
10105
10106 (define_expand "restore_stack_nonlocal"
10107   [(match_operand 0 "register_operand" "")
10108    (match_operand 1 "memory_operand" "")]
10109   ""
10110 {
10111   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10112   rtx temp = NULL_RTX;
10113
10114   /* Restore the backchain from the first word, sp from the second and the
10115      literal pool base from the third.  */
10116
10117   rtx save_bc = adjust_address (operands[1], Pmode, 0);
10118   rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10119   rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10120
10121   if (TARGET_BACKCHAIN)
10122     temp = force_reg (Pmode, save_bc);
10123
10124   emit_move_insn (base, save_bp);
10125   emit_move_insn (operands[0], save_sp);
10126
10127   if (temp)
10128     emit_move_insn (s390_back_chain_rtx (), temp);
10129
10130   emit_use (base);
10131   DONE;
10132 })
10133
10134 (define_expand "exception_receiver"
10135   [(const_int 0)]
10136   ""
10137 {
10138   s390_set_has_landing_pad_p (true);
10139   DONE;
10140 })
10141
10142 ;
10143 ; nop instruction pattern(s).
10144 ;
10145
10146 (define_insn "nop"
10147   [(const_int 0)]
10148   ""
10149   "lr\t0,0"
10150   [(set_attr "op_type" "RR")
10151    (set_attr "z10prop"  "z10_fr_E1")])
10152
10153 (define_insn "nop1"
10154   [(const_int 1)]
10155   ""
10156   "lr\t1,1"
10157   [(set_attr "op_type" "RR")])
10158
10159 ;;- Undeletable nops (used for hotpatching)
10160
10161 (define_insn "nop_2_byte"
10162   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10163   ""
10164   "nopr\t%%r7"
10165   [(set_attr "op_type" "RR")])
10166
10167 (define_insn "nop_4_byte"
10168   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10169   ""
10170   "nop\t0"
10171   [(set_attr "op_type" "RX")])
10172
10173 (define_insn "nop_6_byte"
10174   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10175   "TARGET_CPU_ZARCH"
10176   "brcl\t0, 0"
10177   [(set_attr "op_type" "RIL")])
10178
10179
10180 ;
10181 ; Special literal pool access instruction pattern(s).
10182 ;
10183
10184 (define_insn "*pool_entry"
10185   [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10186                     UNSPECV_POOL_ENTRY)]
10187   ""
10188 {
10189   machine_mode mode = GET_MODE (PATTERN (insn));
10190   unsigned int align = GET_MODE_BITSIZE (mode);
10191   s390_output_pool_entry (operands[0], mode, align);
10192   return "";
10193 }
10194   [(set (attr "length")
10195         (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10196
10197 (define_insn "pool_align"
10198   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10199                     UNSPECV_POOL_ALIGN)]
10200   ""
10201   ".align\t%0"
10202   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10203
10204 (define_insn "pool_section_start"
10205   [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10206   ""
10207   ".section\t.rodata"
10208   [(set_attr "length" "0")])
10209
10210 (define_insn "pool_section_end"
10211   [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10212   ""
10213   ".previous"
10214   [(set_attr "length" "0")])
10215
10216 (define_insn "main_base_31_small"
10217   [(set (match_operand 0 "register_operand" "=a")
10218         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10219   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10220   "basr\t%0,0"
10221   [(set_attr "op_type" "RR")
10222    (set_attr "type"    "la")
10223    (set_attr "z196prop" "z196_cracked")])
10224
10225 (define_insn "main_base_31_large"
10226   [(set (match_operand 0 "register_operand" "=a")
10227         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10228    (set (pc) (label_ref (match_operand 2 "" "")))]
10229   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10230   "bras\t%0,%2"
10231   [(set_attr "op_type" "RI")
10232    (set_attr "z196prop" "z196_cracked")])
10233
10234 (define_insn "main_base_64"
10235   [(set (match_operand 0 "register_operand" "=a")
10236         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10237   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10238   "larl\t%0,%1"
10239   [(set_attr "op_type" "RIL")
10240    (set_attr "type"    "larl")
10241    (set_attr "z10prop" "z10_fwd_A1")])
10242
10243 (define_insn "main_pool"
10244   [(set (match_operand 0 "register_operand" "=a")
10245         (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10246   "GET_MODE (operands[0]) == Pmode"
10247 {
10248   gcc_unreachable ();
10249 }
10250   [(set (attr "type")
10251         (if_then_else (match_test "TARGET_CPU_ZARCH")
10252                       (const_string "larl") (const_string "la")))])
10253
10254 (define_insn "reload_base_31"
10255   [(set (match_operand 0 "register_operand" "=a")
10256         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10257   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10258   "basr\t%0,0\;la\t%0,%1-.(%0)"
10259   [(set_attr "length" "6")
10260    (set_attr "type" "la")
10261    (set_attr "z196prop" "z196_cracked")])
10262
10263 (define_insn "reload_base_64"
10264   [(set (match_operand 0 "register_operand" "=a")
10265         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10266   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10267   "larl\t%0,%1"
10268   [(set_attr "op_type" "RIL")
10269    (set_attr "type"    "larl")
10270    (set_attr "z10prop" "z10_fwd_A1")])
10271
10272 (define_insn "pool"
10273   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10274   ""
10275 {
10276   gcc_unreachable ();
10277 }
10278   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10279
10280 ;;
10281 ;; Insns related to generating the function prologue and epilogue.
10282 ;;
10283
10284
10285 (define_expand "prologue"
10286   [(use (const_int 0))]
10287   ""
10288   "s390_emit_prologue (); DONE;")
10289
10290 (define_expand "epilogue"
10291   [(use (const_int 1))]
10292   ""
10293   "s390_emit_epilogue (false); DONE;")
10294
10295 (define_expand "sibcall_epilogue"
10296   [(use (const_int 0))]
10297   ""
10298   "s390_emit_epilogue (true); DONE;")
10299
10300 ;; A direct return instruction, without using an epilogue.
10301 (define_insn "<code>"
10302   [(ANY_RETURN)]
10303   "s390_can_use_<code>_insn ()"
10304   "br\t%%r14"
10305   [(set_attr "op_type" "RR")
10306    (set_attr "type"    "jsr")
10307    (set_attr "atype"   "agen")])
10308
10309 (define_insn "*return"
10310   [(return)
10311    (use (match_operand 0 "register_operand" "a"))]
10312   "GET_MODE (operands[0]) == Pmode"
10313   "br\t%0"
10314   [(set_attr "op_type" "RR")
10315    (set_attr "type"    "jsr")
10316    (set_attr "atype"   "agen")])
10317
10318
10319 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10320 ;; pointer. This is used for compatibility.
10321
10322 (define_expand "ptr_extend"
10323   [(set (match_operand:DI 0 "register_operand" "=r")
10324         (match_operand:SI 1 "register_operand" "r"))]
10325   "TARGET_64BIT"
10326 {
10327   emit_insn (gen_anddi3 (operands[0],
10328                          gen_lowpart (DImode, operands[1]),
10329                          GEN_INT (0x7fffffff)));
10330   DONE;
10331 })
10332
10333 ;; Instruction definition to expand eh_return macro to support
10334 ;; swapping in special linkage return addresses.
10335
10336 (define_expand "eh_return"
10337   [(use (match_operand 0 "register_operand" ""))]
10338   "TARGET_TPF"
10339 {
10340   s390_emit_tpf_eh_return (operands[0]);
10341   DONE;
10342 })
10343
10344 ;
10345 ; Stack Protector Patterns
10346 ;
10347
10348 (define_expand "stack_protect_set"
10349   [(set (match_operand 0 "memory_operand" "")
10350         (match_operand 1 "memory_operand" ""))]
10351   ""
10352 {
10353 #ifdef TARGET_THREAD_SSP_OFFSET
10354   operands[1]
10355     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10356                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10357 #endif
10358   if (TARGET_64BIT)
10359     emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10360   else
10361     emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10362
10363   DONE;
10364 })
10365
10366 (define_insn "stack_protect_set<mode>"
10367   [(set (match_operand:DSI 0 "memory_operand" "=Q")
10368         (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10369   ""
10370   "mvc\t%O0(%G0,%R0),%S1"
10371   [(set_attr "op_type" "SS")])
10372
10373 (define_expand "stack_protect_test"
10374   [(set (reg:CC CC_REGNUM)
10375         (compare (match_operand 0 "memory_operand" "")
10376                  (match_operand 1 "memory_operand" "")))
10377    (match_operand 2 "" "")]
10378   ""
10379 {
10380   rtx cc_reg, test;
10381 #ifdef TARGET_THREAD_SSP_OFFSET
10382   operands[1]
10383     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10384                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10385 #endif
10386   if (TARGET_64BIT)
10387     emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10388   else
10389     emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10390
10391   cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10392   test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10393   emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10394   DONE;
10395 })
10396
10397 (define_insn "stack_protect_test<mode>"
10398   [(set (reg:CCZ CC_REGNUM)
10399         (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10400                      (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10401   ""
10402   "clc\t%O0(%G0,%R0),%S1"
10403   [(set_attr "op_type" "SS")])
10404
10405 ; This is used in s390_emit_prologue in order to prevent insns
10406 ; adjusting the stack pointer to be moved over insns writing stack
10407 ; slots using a copy of the stack pointer in a different register.
10408 (define_insn "stack_tie"
10409   [(set (match_operand:BLK 0 "memory_operand" "+m")
10410         (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10411   ""
10412   ""
10413   [(set_attr "length" "0")])
10414
10415
10416 ;
10417 ; Data prefetch patterns
10418 ;
10419
10420 (define_insn "prefetch"
10421   [(prefetch (match_operand 0    "address_operand"   "ZQZRZSZT,X")
10422              (match_operand:SI 1 "const_int_operand" "       n,n")
10423              (match_operand:SI 2 "const_int_operand" "       n,n"))]
10424   "TARGET_Z10"
10425 {
10426   switch (which_alternative)
10427     {
10428       case 0:
10429         return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10430       case 1:
10431         if (larl_operand (operands[0], Pmode))
10432           return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10433       default:
10434
10435         /* This might be reached for symbolic operands with an odd
10436            addend.  We simply omit the prefetch for such rare cases.  */
10437
10438         return "";
10439      }
10440 }
10441   [(set_attr "type" "load,larl")
10442    (set_attr "op_type" "RXY,RIL")
10443    (set_attr "z10prop" "z10_super")
10444    (set_attr "z196prop" "z196_alone")])
10445
10446
10447 ;
10448 ; Byte swap instructions
10449 ;
10450
10451 (define_insn "bswap<mode>2"
10452   [(set (match_operand:GPR 0            "register_operand"     "=d, d")
10453         (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
10454   "TARGET_CPU_ZARCH"
10455   "@
10456    lrv<g>r\t%0,%1
10457    lrv<g>\t%0,%1"
10458   [(set_attr "type" "*,load")
10459    (set_attr "op_type" "RRE,RXY")
10460    (set_attr "z10prop" "z10_super")])
10461
10462
10463 ;
10464 ; Population count instruction
10465 ;
10466
10467 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10468 ; portions and stores the result in the corresponding bytes in op0.
10469 (define_insn "*popcount<mode>"
10470   [(set (match_operand:INT 0 "register_operand" "=d")
10471         (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10472    (clobber (reg:CC CC_REGNUM))]
10473   "TARGET_Z196"
10474   "popcnt\t%0,%1"
10475   [(set_attr "op_type" "RRE")])
10476
10477 (define_expand "popcountdi2"
10478   [; popcnt op0, op1
10479    (parallel [(set (match_operand:DI 0 "register_operand" "")
10480                    (unspec:DI [(match_operand:DI 1 "register_operand")]
10481                               UNSPEC_POPCNT))
10482               (clobber (reg:CC CC_REGNUM))])
10483    ; sllg op2, op0, 32
10484    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10485    ; agr op0, op2
10486    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10487               (clobber (reg:CC CC_REGNUM))])
10488    ; sllg op2, op0, 16
10489    (set (match_dup 2)
10490         (ashift:DI (match_dup 0) (const_int 16)))
10491    ; agr op0, op2
10492    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10493               (clobber (reg:CC CC_REGNUM))])
10494    ; sllg op2, op0, 8
10495    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10496    ; agr op0, op2
10497    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10498               (clobber (reg:CC CC_REGNUM))])
10499    ; srlg op0, op0, 56
10500    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10501   "TARGET_Z196 && TARGET_64BIT"
10502   "operands[2] = gen_reg_rtx (DImode);")
10503
10504 (define_expand "popcountsi2"
10505   [; popcnt op0, op1
10506    (parallel [(set (match_operand:SI 0 "register_operand" "")
10507                    (unspec:SI [(match_operand:SI 1 "register_operand")]
10508                               UNSPEC_POPCNT))
10509               (clobber (reg:CC CC_REGNUM))])
10510    ; sllk op2, op0, 16
10511    (set (match_dup 2)
10512         (ashift:SI (match_dup 0) (const_int 16)))
10513    ; ar op0, op2
10514    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10515               (clobber (reg:CC CC_REGNUM))])
10516    ; sllk op2, op0, 8
10517    (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10518    ; ar op0, op2
10519    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10520               (clobber (reg:CC CC_REGNUM))])
10521    ; srl op0, op0, 24
10522    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10523   "TARGET_Z196"
10524   "operands[2] = gen_reg_rtx (SImode);")
10525
10526 (define_expand "popcounthi2"
10527   [; popcnt op0, op1
10528    (parallel [(set (match_operand:HI 0 "register_operand" "")
10529                    (unspec:HI [(match_operand:HI 1 "register_operand")]
10530                               UNSPEC_POPCNT))
10531               (clobber (reg:CC CC_REGNUM))])
10532    ; sllk op2, op0, 8
10533    (set (match_dup 2)
10534         (ashift:SI (match_dup 0) (const_int 8)))
10535    ; ar op0, op2
10536    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10537               (clobber (reg:CC CC_REGNUM))])
10538    ; srl op0, op0, 8
10539    (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10540   "TARGET_Z196"
10541   "operands[2] = gen_reg_rtx (SImode);")
10542
10543 (define_expand "popcountqi2"
10544   [; popcnt op0, op1
10545    (parallel [(set (match_operand:QI 0 "register_operand" "")
10546                    (unspec:QI [(match_operand:QI 1 "register_operand")]
10547                               UNSPEC_POPCNT))
10548               (clobber (reg:CC CC_REGNUM))])]
10549   "TARGET_Z196"
10550   "")
10551
10552 ;;
10553 ;;- Copy sign instructions
10554 ;;
10555
10556 (define_insn "copysign<mode>3"
10557   [(set (match_operand:FP 0 "register_operand" "=f")
10558       (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10559                   (match_operand:FP 2 "register_operand" "f")]
10560                   UNSPEC_COPYSIGN))]
10561   "TARGET_Z196"
10562   "cpsdr\t%0,%2,%1"
10563   [(set_attr "op_type"  "RRF")
10564    (set_attr "type"     "fsimp<mode>")])
10565
10566
10567 ;;
10568 ;;- Transactional execution instructions
10569 ;;
10570
10571 ; This splitter helps combine to make use of CC directly when
10572 ; comparing the integer result of a tbegin builtin with a constant.
10573 ; The unspec is already removed by canonicalize_comparison. So this
10574 ; splitters only job is to turn the PARALLEL into separate insns
10575 ; again.  Unfortunately this only works with the very first cc/int
10576 ; compare since combine is not able to deal with data flow across
10577 ; basic block boundaries.
10578
10579 ; It needs to be an insn pattern as well since combine does not apply
10580 ; the splitter directly.  Combine would only use it if it actually
10581 ; would reduce the number of instructions.
10582 (define_insn_and_split "*ccraw_to_int"
10583   [(set (pc)
10584         (if_then_else
10585          (match_operator 0 "s390_eqne_operator"
10586                          [(reg:CCRAW CC_REGNUM)
10587                           (match_operand 1 "const_int_operand" "")])
10588          (label_ref (match_operand 2 "" ""))
10589          (pc)))
10590    (set (match_operand:SI 3 "register_operand" "=d")
10591         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10592   ""
10593   "#"
10594   ""
10595   [(set (match_dup 3)
10596         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10597    (set (pc)
10598         (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10599                       (label_ref (match_dup 2))
10600                       (pc)))]
10601   "")
10602
10603 ; Non-constrained transaction begin
10604
10605 (define_expand "tbegin"
10606   [(match_operand:SI 0 "register_operand" "")
10607    (match_operand:BLK 1 "memory_operand" "")]
10608   "TARGET_HTM"
10609 {
10610   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10611   DONE;
10612 })
10613
10614 (define_expand "tbegin_nofloat"
10615   [(match_operand:SI 0 "register_operand" "")
10616    (match_operand:BLK 1 "memory_operand" "")]
10617   "TARGET_HTM"
10618 {
10619   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10620   DONE;
10621 })
10622
10623 (define_expand "tbegin_retry"
10624   [(match_operand:SI 0 "register_operand" "")
10625    (match_operand:BLK 1 "memory_operand" "")
10626    (match_operand:SI 2 "general_operand" "")]
10627   "TARGET_HTM"
10628 {
10629   s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10630   DONE;
10631 })
10632
10633 (define_expand "tbegin_retry_nofloat"
10634   [(match_operand:SI 0 "register_operand" "")
10635    (match_operand:BLK 1 "memory_operand" "")
10636    (match_operand:SI 2 "general_operand" "")]
10637   "TARGET_HTM"
10638 {
10639   s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10640   DONE;
10641 })
10642
10643 ; Clobber VRs since they don't get restored
10644 (define_insn "tbegin_1_z13"
10645   [(set (reg:CCRAW CC_REGNUM)
10646         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10647                                UNSPECV_TBEGIN))
10648    (set (match_operand:BLK 1 "memory_operand" "=Q")
10649         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10650    (clobber (reg:TI 16)) (clobber (reg:TI 38))
10651    (clobber (reg:TI 17)) (clobber (reg:TI 39))
10652    (clobber (reg:TI 18)) (clobber (reg:TI 40))
10653    (clobber (reg:TI 19)) (clobber (reg:TI 41))
10654    (clobber (reg:TI 20)) (clobber (reg:TI 42))
10655    (clobber (reg:TI 21)) (clobber (reg:TI 43))
10656    (clobber (reg:TI 22)) (clobber (reg:TI 44))
10657    (clobber (reg:TI 23)) (clobber (reg:TI 45))
10658    (clobber (reg:TI 24)) (clobber (reg:TI 46))
10659    (clobber (reg:TI 25)) (clobber (reg:TI 47))
10660    (clobber (reg:TI 26)) (clobber (reg:TI 48))
10661    (clobber (reg:TI 27)) (clobber (reg:TI 49))
10662    (clobber (reg:TI 28)) (clobber (reg:TI 50))
10663    (clobber (reg:TI 29)) (clobber (reg:TI 51))
10664    (clobber (reg:TI 30)) (clobber (reg:TI 52))
10665    (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10666 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10667 ; not supposed to be used for immediates (see genpreds.c).
10668   "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10669   "tbegin\t%1,%x0"
10670   [(set_attr "op_type" "SIL")])
10671
10672 (define_insn "tbegin_1"
10673   [(set (reg:CCRAW CC_REGNUM)
10674         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10675                                UNSPECV_TBEGIN))
10676    (set (match_operand:BLK 1 "memory_operand" "=Q")
10677         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10678    (clobber (reg:DF 16))
10679    (clobber (reg:DF 17))
10680    (clobber (reg:DF 18))
10681    (clobber (reg:DF 19))
10682    (clobber (reg:DF 20))
10683    (clobber (reg:DF 21))
10684    (clobber (reg:DF 22))
10685    (clobber (reg:DF 23))
10686    (clobber (reg:DF 24))
10687    (clobber (reg:DF 25))
10688    (clobber (reg:DF 26))
10689    (clobber (reg:DF 27))
10690    (clobber (reg:DF 28))
10691    (clobber (reg:DF 29))
10692    (clobber (reg:DF 30))
10693    (clobber (reg:DF 31))]
10694 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10695 ; not supposed to be used for immediates (see genpreds.c).
10696   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10697   "tbegin\t%1,%x0"
10698   [(set_attr "op_type" "SIL")])
10699
10700 ; Same as above but without the FPR clobbers
10701 (define_insn "tbegin_nofloat_1"
10702   [(set (reg:CCRAW CC_REGNUM)
10703         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10704                                UNSPECV_TBEGIN))
10705    (set (match_operand:BLK 1 "memory_operand" "=Q")
10706         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10707   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10708   "tbegin\t%1,%x0"
10709   [(set_attr "op_type" "SIL")])
10710
10711
10712 ; Constrained transaction begin
10713
10714 (define_expand "tbeginc"
10715   [(set (reg:CCRAW CC_REGNUM)
10716         (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10717                                UNSPECV_TBEGINC))]
10718   "TARGET_HTM"
10719   "")
10720
10721 (define_insn "*tbeginc_1"
10722   [(set (reg:CCRAW CC_REGNUM)
10723         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10724                                UNSPECV_TBEGINC))]
10725   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10726   "tbeginc\t0,%x0"
10727   [(set_attr "op_type" "SIL")])
10728
10729 ; Transaction end
10730
10731 (define_expand "tend"
10732   [(set (reg:CCRAW CC_REGNUM)
10733         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10734    (set (match_operand:SI 0 "register_operand" "")
10735         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10736   "TARGET_HTM"
10737   "")
10738
10739 (define_insn "*tend_1"
10740   [(set (reg:CCRAW CC_REGNUM)
10741         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10742   "TARGET_HTM"
10743   "tend"
10744   [(set_attr "op_type" "S")])
10745
10746 ; Transaction abort
10747
10748 (define_expand "tabort"
10749   [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10750                     UNSPECV_TABORT)]
10751   "TARGET_HTM && operands != NULL"
10752 {
10753   if (CONST_INT_P (operands[0])
10754       && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10755     {
10756       error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10757              ".  Values in range 0 through 255 are reserved.",
10758              INTVAL (operands[0]));
10759       FAIL;
10760     }
10761 })
10762
10763 (define_insn "*tabort_1"
10764   [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10765                     UNSPECV_TABORT)]
10766   "TARGET_HTM && operands != NULL"
10767   "tabort\t%Y0"
10768   [(set_attr "op_type" "S")])
10769
10770 ; Transaction extract nesting depth
10771
10772 (define_insn "etnd"
10773   [(set (match_operand:SI 0 "register_operand" "=d")
10774         (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10775   "TARGET_HTM"
10776   "etnd\t%0"
10777   [(set_attr "op_type" "RRE")])
10778
10779 ; Non-transactional store
10780
10781 (define_insn "ntstg"
10782   [(set (match_operand:DI 0 "memory_operand" "=RT")
10783         (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10784                             UNSPECV_NTSTG))]
10785   "TARGET_HTM"
10786   "ntstg\t%1,%0"
10787   [(set_attr "op_type" "RXY")])
10788
10789 ; Transaction perform processor assist
10790
10791 (define_expand "tx_assist"
10792   [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10793                      (reg:SI GPR0_REGNUM)
10794                      (const_int 1)]
10795                     UNSPECV_PPA)]
10796   "TARGET_HTM"
10797   "")
10798
10799 (define_insn "*ppa"
10800   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10801                      (match_operand:SI 1 "register_operand" "d")
10802                      (match_operand 2 "const_int_operand" "I")]
10803                     UNSPECV_PPA)]
10804   "TARGET_HTM && INTVAL (operands[2]) < 16"
10805   "ppa\t%0,%1,%2"
10806   [(set_attr "op_type" "RRF")])
10807
10808
10809 ; Set and get floating point control register
10810
10811 (define_insn "sfpc"
10812   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10813                     UNSPECV_SFPC)]
10814   "TARGET_HARD_FLOAT"
10815   "sfpc\t%0")
10816
10817 (define_insn "efpc"
10818   [(set (match_operand:SI 0 "register_operand" "=d")
10819         (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10820   "TARGET_HARD_FLOAT"
10821   "efpc\t%0")
10822
10823
10824 ; Load count to block boundary
10825
10826 (define_insn "lcbb"
10827   [(set (match_operand:SI             0 "register_operand"  "=d")
10828         (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR")
10829                     (match_operand:SI 2 "immediate_operand"  "C")] UNSPEC_LCBB))
10830    (clobber (reg:CC CC_REGNUM))]
10831   "TARGET_Z13"
10832   "lcbb\t%0,%1,%b2"
10833   [(set_attr "op_type" "VRX")])