1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2013 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
67 ; GOT/PLT and lt-relative accesses
88 ; TLS relocation specifiers
104 ; Stack Smashing Protector
108 ; Test Data Class (TDC)
117 ;; UNSPEC_VOLATILE usage
120 (define_c_enum "unspecv" [
147 ; Registers with special meaning
151 ; Sibling call register.
153 ; Literal pool base register.
155 ; Return address register.
157 ; Condition code register.
159 ; Thread local storage pointer register.
163 ; Hardware register names
167 ; General purpose registers
169 ; Floating point registers.
175 ;; PFPO GPR0 argument format
180 ; PFPO operation type
181 (PFPO_CONVERT 0x1000000)
183 (PFPO_OP_TYPE_SF 0x5)
184 (PFPO_OP_TYPE_DF 0x6)
185 (PFPO_OP_TYPE_TF 0x7)
186 (PFPO_OP_TYPE_SD 0x8)
187 (PFPO_OP_TYPE_DD 0x9)
188 (PFPO_OP_TYPE_TD 0xa)
189 ; Bitposition of operand types
190 (PFPO_OP0_TYPE_SHIFT 16)
191 (PFPO_OP1_TYPE_SHIFT 8)
195 ;; Instruction operand type as used in the Principles of Operation.
196 ;; Used to determine defaults for length and other attribute values.
198 (define_attr "op_type"
199 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
202 ;; Instruction type attribute used for scheduling.
204 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
205 cs,vs,store,sem,idiv,
206 imulhi,imulsi,imuldi,
207 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
208 floadtf,floaddf,floadsf,fstoredf,fstoresf,
209 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
210 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
212 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
213 itoftf, itofdf, itofsf, itofdd, itoftd,
214 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
215 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
217 (cond [(eq_attr "op_type" "NN") (const_string "other")
218 (eq_attr "op_type" "SS") (const_string "cs")]
219 (const_string "integer")))
221 ;; Another attribute used for scheduling purposes:
222 ;; agen: Instruction uses the address generation unit
223 ;; reg: Instruction does not use the agen unit
225 (define_attr "atype" "agen,reg"
226 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
228 (const_string "agen")))
230 ;; Properties concerning Z10 execution grouping and value forwarding.
231 ;; z10_super: instruction is superscalar.
232 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
233 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
234 ;; target register. It can forward this value to a second instruction that reads
235 ;; the same register if that second instruction is issued in the same group.
236 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
237 ;; instruction in the S pipe writes to the register, then the T instruction
238 ;; can immediately read the new value.
239 ;; z10_fr: union of Z10_fwd and z10_rec.
240 ;; z10_c: second operand of instruction is a register and read with complemented bits.
242 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
245 (define_attr "z10prop" "none,
246 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
247 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
249 z10_fr, z10_fr_A3, z10_fr_E1,
251 (const_string "none"))
253 ;; Properties concerning Z196 decoding
254 ;; z196_alone: must group alone
255 ;; z196_end: ends a group
256 ;; z196_cracked: instruction is cracked or expanded
257 (define_attr "z196prop" "none,
258 z196_alone, z196_ends,
260 (const_string "none"))
262 (define_attr "mnemonic" "unknown" (const_string "unknown"))
266 (define_attr "length" ""
267 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
268 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
272 ;; Processor type. This attribute must exactly match the processor_type
273 ;; enumeration in s390.h. The current machine description does not
274 ;; distinguish between g5 and g6, but there are differences between the two
275 ;; CPUs could in theory be modeled.
277 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
278 (const (symbol_ref "s390_tune_attr")))
280 (define_attr "cpu_facility"
281 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12"
282 (const_string "standard"))
284 (define_attr "enabled" ""
285 (cond [(eq_attr "cpu_facility" "standard")
288 (and (eq_attr "cpu_facility" "ieee")
289 (match_test "TARGET_CPU_IEEE_FLOAT"))
292 (and (eq_attr "cpu_facility" "zarch")
293 (match_test "TARGET_ZARCH"))
296 (and (eq_attr "cpu_facility" "longdisp")
297 (match_test "TARGET_LONG_DISPLACEMENT"))
300 (and (eq_attr "cpu_facility" "extimm")
301 (match_test "TARGET_EXTIMM"))
304 (and (eq_attr "cpu_facility" "dfp")
305 (match_test "TARGET_DFP"))
308 (and (eq_attr "cpu_facility" "cpu_zarch")
309 (match_test "TARGET_CPU_ZARCH"))
312 (and (eq_attr "cpu_facility" "z10")
313 (match_test "TARGET_Z10"))
316 (and (eq_attr "cpu_facility" "z196")
317 (match_test "TARGET_Z196"))
320 (and (eq_attr "cpu_facility" "zEC12")
321 (match_test "TARGET_ZEC12"))
325 ;; Pipeline description for z900. For lack of anything better,
326 ;; this description is also used for the g5 and g6.
329 ;; Pipeline description for z990, z9-109 and z9-ec.
332 ;; Pipeline description for z10
335 ;; Pipeline description for z196
338 ;; Pipeline description for zEC12
342 (include "predicates.md")
344 ;; Constraint definitions
345 (include "constraints.md")
352 ;; These mode iterators allow floating point patterns to be generated from the
354 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
355 (SD "TARGET_HARD_DFP")])
356 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
357 (define_mode_iterator FPALL [TF DF SF TD DD SD])
358 (define_mode_iterator BFP [TF DF SF])
359 (define_mode_iterator DFP [TD DD])
360 (define_mode_iterator DFP_ALL [TD DD SD])
361 (define_mode_iterator DSF [DF SF])
362 (define_mode_iterator SD_SF [SF SD])
363 (define_mode_iterator DD_DF [DF DD])
364 (define_mode_iterator TD_TF [TF TD])
366 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
367 ;; from the same template.
368 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
369 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
370 (define_mode_iterator DSI [DI SI])
371 (define_mode_iterator TDI [TI DI])
373 ;; These mode iterators allow :P to be used for patterns that operate on
374 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
375 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
377 ;; These macros refer to the actual word_mode of the configuration.
378 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
379 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
380 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
382 ;; Used by the umul pattern to express modes having half the size.
383 (define_mode_attr DWH [(TI "DI") (DI "SI")])
384 (define_mode_attr dwh [(TI "di") (DI "si")])
386 ;; This mode iterator allows the QI and HI patterns to be defined from
387 ;; the same template.
388 (define_mode_iterator HQI [HI QI])
390 ;; This mode iterator allows the integer patterns to be defined from the
392 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
393 (define_mode_iterator INTALL [TI DI SI HI QI])
394 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
396 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
397 ;; the same template.
398 (define_code_iterator SHIFT [ashift lshiftrt])
400 ;; This iterator allow r[ox]sbg to be defined with the same template
401 (define_code_iterator IXOR [ior xor])
403 ;; This iterator and attribute allow to combine most atomic operations.
404 (define_code_iterator ATOMIC [and ior xor plus minus mult])
405 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
406 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
407 (plus "add") (minus "sub") (mult "nand")])
408 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
410 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
411 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
412 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
414 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
415 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
417 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
419 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
420 ;; Likewise for "<RXe>".
421 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
422 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
424 ;; The decimal floating point variants of add, sub, div and mul support 3
425 ;; fp register operands. The following attributes allow to merge the bfp and
426 ;; dfp variants in a single insn definition.
428 ;; This attribute is used to set op_type accordingly.
429 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
430 (DD "RRR") (SD "RRR")])
432 ;; This attribute is used in the operand constraint list in order to have the
433 ;; first and the second operand match for bfp modes.
434 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
436 ;; This attribute is used in the operand list of the instruction to have an
437 ;; additional operand for the dfp instructions.
438 (define_mode_attr op1 [(TF "") (DF "") (SF "")
439 (TD "%1,") (DD "%1,") (SD "%1,")])
442 ;; This attribute is used in the operand constraint list
443 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
444 ;; TFmode values are represented by a fp register pair. Since the
445 ;; sign bit instructions only handle single source and target fp registers
446 ;; these instructions can only be used for TFmode values if the source and
447 ;; target operand uses the same fp register.
448 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
450 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
451 ;; This is used to disable the memory alternative in TFmode patterns.
452 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
454 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
455 ;; within instruction mnemonics.
456 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
458 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
459 ;; modes and to an empty string for bfp modes.
460 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
462 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
463 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
464 ;; version only operates on one register.
465 (define_mode_attr d0 [(DI "d") (SI "0")])
467 ;; In combination with d0 this allows to combine instructions of which the 31bit
468 ;; version only operates on one register. The DImode version needs an additional
469 ;; register for the assembler output.
470 (define_mode_attr 1 [(DI "%1,") (SI "")])
472 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
473 ;; 'ashift' and "srdl" in 'lshiftrt'.
474 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
476 ;; In SHIFT templates, this attribute holds the correct standard name for the
477 ;; pattern itself and the corresponding function calls.
478 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
480 ;; This attribute handles differences in the instruction 'type' and will result
481 ;; in "RRE" for DImode and "RR" for SImode.
482 (define_mode_attr E [(DI "E") (SI "")])
484 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
485 ;; to result in "RXY" for DImode and "RX" for SImode.
486 (define_mode_attr Y [(DI "Y") (SI "")])
488 ;; This attribute handles differences in the instruction 'type' and will result
489 ;; in "RSE" for TImode and "RS" for DImode.
490 (define_mode_attr TE [(TI "E") (DI "")])
492 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
493 ;; and "lcr" in SImode.
494 (define_mode_attr g [(DI "g") (SI "")])
496 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
497 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
498 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
499 ;; variant for long displacements.
500 (define_mode_attr y [(DI "g") (SI "y")])
502 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
503 ;; and "cds" in DImode.
504 (define_mode_attr tg [(TI "g") (DI "")])
506 ;; In TDI templates, a string like "c<d>sg".
507 (define_mode_attr td [(TI "d") (DI "")])
509 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
510 ;; and "cfdbr" in SImode.
511 (define_mode_attr gf [(DI "g") (SI "f")])
513 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
514 ;; and sllk for SI. This way it is possible to merge the new z196 SI
515 ;; 3 operands shift instructions into the existing patterns.
516 (define_mode_attr gk [(DI "g") (SI "k")])
518 ;; ICM mask required to load MODE value into the lowest subreg
519 ;; of a SImode register.
520 (define_mode_attr icm_lo [(HI "3") (QI "1")])
522 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
523 ;; HImode and "llgc" in QImode.
524 (define_mode_attr hc [(HI "h") (QI "c")])
526 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
528 (define_mode_attr DBL [(DI "TI") (SI "DI")])
530 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
531 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
532 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
534 ;; Maximum unsigned integer that fits in MODE.
535 (define_mode_attr max_uint [(HI "65535") (QI "255")])
537 ;; Start and end field computations for RISBG et al.
538 (define_mode_attr bfstart [(DI "s") (SI "t")])
539 (define_mode_attr bfend [(DI "e") (SI "f")])
541 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
542 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
545 ;;- Compare instructions.
548 ; Test-under-Mask instructions
550 (define_insn "*tmqi_mem"
551 [(set (reg CC_REGNUM)
552 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
553 (match_operand:QI 1 "immediate_operand" "n,n"))
554 (match_operand:QI 2 "immediate_operand" "n,n")))]
555 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
559 [(set_attr "op_type" "SI,SIY")
560 (set_attr "z10prop" "z10_super,z10_super")])
562 (define_insn "*tmdi_reg"
563 [(set (reg CC_REGNUM)
564 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
565 (match_operand:DI 1 "immediate_operand"
566 "N0HD0,N1HD0,N2HD0,N3HD0"))
567 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
569 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
570 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
576 [(set_attr "op_type" "RI")
577 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
579 (define_insn "*tmsi_reg"
580 [(set (reg CC_REGNUM)
581 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
582 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
583 (match_operand:SI 2 "immediate_operand" "n,n")))]
584 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
585 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
589 [(set_attr "op_type" "RI")
590 (set_attr "z10prop" "z10_super,z10_super")])
592 (define_insn "*tm<mode>_full"
593 [(set (reg CC_REGNUM)
594 (compare (match_operand:HQI 0 "register_operand" "d")
595 (match_operand:HQI 1 "immediate_operand" "n")))]
596 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
598 [(set_attr "op_type" "RI")
599 (set_attr "z10prop" "z10_super")])
603 ; Load-and-Test instructions
606 ; tst(di|si) instruction pattern(s).
608 (define_insn "*tstdi_sign"
609 [(set (reg CC_REGNUM)
613 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
614 (const_int 32)) (const_int 32))
615 (match_operand:DI 1 "const0_operand" "")))
616 (set (match_operand:DI 2 "register_operand" "=d,d")
617 (sign_extend:DI (match_dup 0)))]
618 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
621 [(set_attr "op_type" "RRE,RXY")
622 (set_attr "cpu_facility" "*,z10")
623 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
626 (define_insn "*tst<mode>_extimm"
627 [(set (reg CC_REGNUM)
628 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
629 (match_operand:GPR 1 "const0_operand" "")))
630 (set (match_operand:GPR 2 "register_operand" "=d,d")
632 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
636 [(set_attr "op_type" "RR<E>,RXY")
637 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
640 (define_insn "*tst<mode>_cconly_extimm"
641 [(set (reg CC_REGNUM)
642 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
643 (match_operand:GPR 1 "const0_operand" "")))
644 (clobber (match_scratch:GPR 2 "=X,d"))]
645 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
649 [(set_attr "op_type" "RR<E>,RXY")
650 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
652 (define_insn "*tstdi"
653 [(set (reg CC_REGNUM)
654 (compare (match_operand:DI 0 "register_operand" "d")
655 (match_operand:DI 1 "const0_operand" "")))
656 (set (match_operand:DI 2 "register_operand" "=d")
658 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
660 [(set_attr "op_type" "RRE")
661 (set_attr "z10prop" "z10_fr_E1")])
663 (define_insn "*tstsi"
664 [(set (reg CC_REGNUM)
665 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
666 (match_operand:SI 1 "const0_operand" "")))
667 (set (match_operand:SI 2 "register_operand" "=d,d,d")
669 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
674 [(set_attr "op_type" "RR,RS,RSY")
675 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
677 (define_insn "*tstsi_cconly"
678 [(set (reg CC_REGNUM)
679 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
680 (match_operand:SI 1 "const0_operand" "")))
681 (clobber (match_scratch:SI 2 "=X,d,d"))]
682 "s390_match_ccmode(insn, CCSmode)"
687 [(set_attr "op_type" "RR,RS,RSY")
688 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
690 (define_insn "*tstdi_cconly_31"
691 [(set (reg CC_REGNUM)
692 (compare (match_operand:DI 0 "register_operand" "d")
693 (match_operand:DI 1 "const0_operand" "")))]
694 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
696 [(set_attr "op_type" "RS")
697 (set_attr "atype" "reg")])
700 (define_insn "*tst<mode>_cconly2"
701 [(set (reg CC_REGNUM)
702 (compare (match_operand:GPR 0 "register_operand" "d")
703 (match_operand:GPR 1 "const0_operand" "")))]
704 "s390_match_ccmode(insn, CCSmode)"
706 [(set_attr "op_type" "RR<E>")
707 (set_attr "z10prop" "z10_fr_E1")])
709 ; tst(hi|qi) instruction pattern(s).
711 (define_insn "*tst<mode>CCT"
712 [(set (reg CC_REGNUM)
713 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
714 (match_operand:HQI 1 "const0_operand" "")))
715 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
717 "s390_match_ccmode(insn, CCTmode)"
720 icmy\t%2,<icm_lo>,%S0
722 [(set_attr "op_type" "RS,RSY,RI")
723 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
725 (define_insn "*tsthiCCT_cconly"
726 [(set (reg CC_REGNUM)
727 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
728 (match_operand:HI 1 "const0_operand" "")))
729 (clobber (match_scratch:HI 2 "=d,d,X"))]
730 "s390_match_ccmode(insn, CCTmode)"
735 [(set_attr "op_type" "RS,RSY,RI")
736 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
738 (define_insn "*tstqiCCT_cconly"
739 [(set (reg CC_REGNUM)
740 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
741 (match_operand:QI 1 "const0_operand" "")))]
742 "s390_match_ccmode(insn, CCTmode)"
747 [(set_attr "op_type" "SI,SIY,RI")
748 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
750 (define_insn "*tst<mode>"
751 [(set (reg CC_REGNUM)
752 (compare (match_operand:HQI 0 "s_operand" "Q,S")
753 (match_operand:HQI 1 "const0_operand" "")))
754 (set (match_operand:HQI 2 "register_operand" "=d,d")
756 "s390_match_ccmode(insn, CCSmode)"
759 icmy\t%2,<icm_lo>,%S0"
760 [(set_attr "op_type" "RS,RSY")
761 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
763 (define_insn "*tst<mode>_cconly"
764 [(set (reg CC_REGNUM)
765 (compare (match_operand:HQI 0 "s_operand" "Q,S")
766 (match_operand:HQI 1 "const0_operand" "")))
767 (clobber (match_scratch:HQI 2 "=d,d"))]
768 "s390_match_ccmode(insn, CCSmode)"
771 icmy\t%2,<icm_lo>,%S0"
772 [(set_attr "op_type" "RS,RSY")
773 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
776 ; Compare (equality) instructions
778 (define_insn "*cmpdi_cct"
779 [(set (reg CC_REGNUM)
780 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
781 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
782 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
789 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
790 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
792 (define_insn "*cmpsi_cct"
793 [(set (reg CC_REGNUM)
794 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
795 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
796 "s390_match_ccmode (insn, CCTmode)"
804 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
805 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
807 ; Compare (signed) instructions
809 (define_insn "*cmpdi_ccs_sign"
810 [(set (reg CC_REGNUM)
811 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
813 (match_operand:DI 0 "register_operand" "d, d,d")))]
814 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
819 [(set_attr "op_type" "RRE,RXY,RIL")
820 (set_attr "z10prop" "z10_c,*,*")
821 (set_attr "type" "*,*,larl")])
825 (define_insn "*cmpsi_ccs_sign"
826 [(set (reg CC_REGNUM)
827 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
828 (match_operand:SI 0 "register_operand" "d,d,d")))]
829 "s390_match_ccmode(insn, CCSRmode)"
834 [(set_attr "op_type" "RX,RXY,RIL")
835 (set_attr "cpu_facility" "*,*,z10")
836 (set_attr "type" "*,*,larl")
837 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
839 (define_insn "*cmphi_ccs_z10"
840 [(set (reg CC_REGNUM)
841 (compare (match_operand:HI 0 "s_operand" "Q")
842 (match_operand:HI 1 "immediate_operand" "K")))]
843 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
845 [(set_attr "op_type" "SIL")
846 (set_attr "z196prop" "z196_cracked")])
848 (define_insn "*cmpdi_ccs_signhi_rl"
849 [(set (reg CC_REGNUM)
850 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
851 (match_operand:GPR 0 "register_operand" "d,d")))]
852 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
856 [(set_attr "op_type" "RXY,RIL")
857 (set_attr "type" "*,larl")])
859 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
860 (define_insn "*cmp<mode>_ccs"
861 [(set (reg CC_REGNUM)
862 (compare (match_operand:GPR 0 "nonimmediate_operand"
864 (match_operand:GPR 1 "general_operand"
866 "s390_match_ccmode(insn, CCSmode)"
875 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
876 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
877 (set_attr "type" "*,*,*,*,*,*,larl")
878 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
881 ; Compare (unsigned) instructions
883 (define_insn "*cmpsi_ccu_zerohi_rlsi"
884 [(set (reg CC_REGNUM)
885 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
886 "larl_operand" "X")))
887 (match_operand:SI 0 "register_operand" "d")))]
888 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
890 [(set_attr "op_type" "RIL")
891 (set_attr "type" "larl")
892 (set_attr "z10prop" "z10_super")])
895 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
896 [(set (reg CC_REGNUM)
897 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
898 "larl_operand" "X")))
899 (match_operand:GPR 0 "register_operand" "d")))]
900 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
902 [(set_attr "op_type" "RIL")
903 (set_attr "type" "larl")
904 (set_attr "z10prop" "z10_super")])
906 (define_insn "*cmpdi_ccu_zero"
907 [(set (reg CC_REGNUM)
908 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
910 (match_operand:DI 0 "register_operand" "d, d,d")))]
911 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
916 [(set_attr "op_type" "RRE,RXY,RIL")
917 (set_attr "cpu_facility" "*,*,z10")
918 (set_attr "type" "*,*,larl")
919 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
921 (define_insn "*cmpdi_ccu"
922 [(set (reg CC_REGNUM)
923 (compare (match_operand:DI 0 "nonimmediate_operand"
925 (match_operand:DI 1 "general_operand"
926 "d,Op,b,D,RT,BQ,Q")))]
927 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
936 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
937 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
938 (set_attr "type" "*,*,larl,*,*,*,*")
939 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
941 (define_insn "*cmpsi_ccu"
942 [(set (reg CC_REGNUM)
943 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
944 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
945 "s390_match_ccmode (insn, CCUmode)"
955 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
956 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
957 (set_attr "type" "*,*,larl,*,*,*,*,*")
958 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
960 (define_insn "*cmphi_ccu"
961 [(set (reg CC_REGNUM)
962 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
963 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
964 "s390_match_ccmode (insn, CCUmode)
965 && !register_operand (operands[1], HImode)"
972 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
973 (set_attr "cpu_facility" "*,*,z10,*,*")
974 (set_attr "z10prop" "*,*,z10_super,*,*")])
976 (define_insn "*cmpqi_ccu"
977 [(set (reg CC_REGNUM)
978 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
979 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
980 "s390_match_ccmode (insn, CCUmode)
981 && !register_operand (operands[1], QImode)"
989 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
990 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
993 ; Block compare (CLC) instruction patterns.
996 [(set (reg CC_REGNUM)
997 (compare (match_operand:BLK 0 "memory_operand" "Q")
998 (match_operand:BLK 1 "memory_operand" "Q")))
999 (use (match_operand 2 "const_int_operand" "n"))]
1000 "s390_match_ccmode (insn, CCUmode)
1001 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1002 "clc\t%O0(%2,%R0),%S1"
1003 [(set_attr "op_type" "SS")])
1006 [(set (reg CC_REGNUM)
1007 (compare (match_operand 0 "memory_operand" "")
1008 (match_operand 1 "memory_operand" "")))]
1010 && s390_match_ccmode (insn, CCUmode)
1011 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1012 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1014 [(set (match_dup 0) (match_dup 1))
1015 (use (match_dup 2))])]
1017 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1018 operands[0] = adjust_address (operands[0], BLKmode, 0);
1019 operands[1] = adjust_address (operands[1], BLKmode, 0);
1021 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1022 operands[0], operands[1]);
1023 operands[0] = SET_DEST (PATTERN (curr_insn));
1027 ; (TF|DF|SF|TD|DD|SD) instructions
1029 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1030 (define_insn "*cmp<mode>_ccs_0"
1031 [(set (reg CC_REGNUM)
1032 (compare (match_operand:FP 0 "register_operand" "f")
1033 (match_operand:FP 1 "const0_operand" "")))]
1034 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1035 "lt<xde><bt>r\t%0,%0"
1036 [(set_attr "op_type" "RRE")
1037 (set_attr "type" "fsimp<mode>")])
1039 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1040 (define_insn "*cmp<mode>_ccs"
1041 [(set (reg CC_REGNUM)
1042 (compare (match_operand:FP 0 "register_operand" "f,f")
1043 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1044 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1048 [(set_attr "op_type" "RRE,RXE")
1049 (set_attr "type" "fsimp<mode>")])
1052 ; Compare and Branch instructions
1054 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1055 ; The following instructions do a complementary access of their second
1056 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1057 (define_insn "*cmp_and_br_signed_<mode>"
1059 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1060 [(match_operand:GPR 1 "register_operand" "d,d")
1061 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1062 (label_ref (match_operand 3 "" ""))
1064 (clobber (reg:CC CC_REGNUM))]
1065 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1067 if (get_attr_length (insn) == 6)
1068 return which_alternative ?
1069 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1071 return which_alternative ?
1072 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1074 [(set_attr "op_type" "RIE")
1075 (set_attr "type" "branch")
1076 (set_attr "z10prop" "z10_super_c,z10_super")
1077 (set (attr "length")
1078 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1079 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1080 ; 10 byte for cgr/jg
1082 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1083 ; The following instructions do a complementary access of their second
1084 ; operand (z10 only): clrj, clgrj, clr, clgr
1085 (define_insn "*cmp_and_br_unsigned_<mode>"
1087 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1088 [(match_operand:GPR 1 "register_operand" "d,d")
1089 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1090 (label_ref (match_operand 3 "" ""))
1092 (clobber (reg:CC CC_REGNUM))]
1093 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1095 if (get_attr_length (insn) == 6)
1096 return which_alternative ?
1097 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1099 return which_alternative ?
1100 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1102 [(set_attr "op_type" "RIE")
1103 (set_attr "type" "branch")
1104 (set_attr "z10prop" "z10_super_c,z10_super")
1105 (set (attr "length")
1106 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1107 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1108 ; 10 byte for clgr/jg
1110 ; And now the same two patterns as above but with a negated CC mask.
1112 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1113 ; The following instructions do a complementary access of their second
1114 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1115 (define_insn "*icmp_and_br_signed_<mode>"
1117 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1118 [(match_operand:GPR 1 "register_operand" "d,d")
1119 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1121 (label_ref (match_operand 3 "" ""))))
1122 (clobber (reg:CC CC_REGNUM))]
1123 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1125 if (get_attr_length (insn) == 6)
1126 return which_alternative ?
1127 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1129 return which_alternative ?
1130 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1132 [(set_attr "op_type" "RIE")
1133 (set_attr "type" "branch")
1134 (set_attr "z10prop" "z10_super_c,z10_super")
1135 (set (attr "length")
1136 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1137 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1138 ; 10 byte for cgr/jg
1140 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1141 ; The following instructions do a complementary access of their second
1142 ; operand (z10 only): clrj, clgrj, clr, clgr
1143 (define_insn "*icmp_and_br_unsigned_<mode>"
1145 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1146 [(match_operand:GPR 1 "register_operand" "d,d")
1147 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1149 (label_ref (match_operand 3 "" ""))))
1150 (clobber (reg:CC CC_REGNUM))]
1151 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1153 if (get_attr_length (insn) == 6)
1154 return which_alternative ?
1155 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1157 return which_alternative ?
1158 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1160 [(set_attr "op_type" "RIE")
1161 (set_attr "type" "branch")
1162 (set_attr "z10prop" "z10_super_c,z10_super")
1163 (set (attr "length")
1164 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1165 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1166 ; 10 byte for clgr/jg
1169 ;;- Move instructions.
1173 ; movti instruction pattern(s).
1176 (define_insn "movti"
1177 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1178 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1185 [(set_attr "op_type" "RSY,RSY,*,*")
1186 (set_attr "type" "lm,stm,*,*")])
1189 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1190 (match_operand:TI 1 "general_operand" ""))]
1191 "TARGET_ZARCH && reload_completed
1192 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1193 [(set (match_dup 2) (match_dup 4))
1194 (set (match_dup 3) (match_dup 5))]
1196 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1197 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1198 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1199 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1203 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1204 (match_operand:TI 1 "general_operand" ""))]
1205 "TARGET_ZARCH && reload_completed
1206 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1207 [(set (match_dup 2) (match_dup 4))
1208 (set (match_dup 3) (match_dup 5))]
1210 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1211 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1212 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1213 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1217 [(set (match_operand:TI 0 "register_operand" "")
1218 (match_operand:TI 1 "memory_operand" ""))]
1219 "TARGET_ZARCH && reload_completed
1220 && !s_operand (operands[1], VOIDmode)"
1221 [(set (match_dup 0) (match_dup 1))]
1223 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1224 addr = gen_lowpart (Pmode, addr);
1225 s390_load_address (addr, XEXP (operands[1], 0));
1226 operands[1] = replace_equiv_address (operands[1], addr);
1231 ; Patterns used for secondary reloads
1234 ; z10 provides move instructions accepting larl memory operands.
1235 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1236 ; These patterns are also used for unaligned SI and DI accesses.
1238 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1239 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1240 (match_operand:INTALL 1 "register_operand" "=d")
1241 (match_operand:P 2 "register_operand" "=&a")])]
1244 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1248 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1249 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1250 (match_operand:INTALL 1 "memory_operand" "")
1251 (match_operand:P 2 "register_operand" "=a")])]
1254 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1258 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1259 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1260 (match_operand:FPALL 1 "register_operand" "=d")
1261 (match_operand:P 2 "register_operand" "=&a")])]
1264 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1268 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1269 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1270 (match_operand:FPALL 1 "memory_operand" "")
1271 (match_operand:P 2 "register_operand" "=a")])]
1274 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1278 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1279 [(parallel [(match_operand:P 0 "register_operand" "=d")
1280 (match_operand:P 1 "larl_operand" "")
1281 (match_operand:P 2 "register_operand" "=a")])]
1284 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1288 ; Handles loading a PLUS (load address) expression
1290 (define_expand "reload<mode>_plus"
1291 [(parallel [(match_operand:P 0 "register_operand" "=a")
1292 (match_operand:P 1 "s390_plus_operand" "")
1293 (match_operand:P 2 "register_operand" "=&a")])]
1296 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1300 ; Handles assessing a non-offsetable memory address
1302 (define_expand "reload<mode>_nonoffmem_in"
1303 [(parallel [(match_operand 0 "register_operand" "")
1304 (match_operand 1 "" "")
1305 (match_operand:P 2 "register_operand" "=&a")])]
1308 gcc_assert (MEM_P (operands[1]));
1309 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1310 operands[1] = replace_equiv_address (operands[1], operands[2]);
1311 emit_move_insn (operands[0], operands[1]);
1315 (define_expand "reload<mode>_nonoffmem_out"
1316 [(parallel [(match_operand 0 "" "")
1317 (match_operand 1 "register_operand" "")
1318 (match_operand:P 2 "register_operand" "=&a")])]
1321 gcc_assert (MEM_P (operands[0]));
1322 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1323 operands[0] = replace_equiv_address (operands[0], operands[2]);
1324 emit_move_insn (operands[0], operands[1]);
1328 (define_expand "reload<mode>_PIC_addr"
1329 [(parallel [(match_operand 0 "register_operand" "=d")
1330 (match_operand 1 "larl_operand" "")
1331 (match_operand:P 2 "register_operand" "=a")])]
1334 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1335 emit_move_insn (operands[0], new_rtx);
1339 ; movdi instruction pattern(s).
1342 (define_expand "movdi"
1343 [(set (match_operand:DI 0 "general_operand" "")
1344 (match_operand:DI 1 "general_operand" ""))]
1347 /* Handle symbolic constants. */
1349 && (SYMBOLIC_CONST (operands[1])
1350 || (GET_CODE (operands[1]) == PLUS
1351 && XEXP (operands[1], 0) == pic_offset_table_rtx
1352 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1353 emit_symbolic_move (operands);
1356 (define_insn "*movdi_larl"
1357 [(set (match_operand:DI 0 "register_operand" "=d")
1358 (match_operand:DI 1 "larl_operand" "X"))]
1360 && !FP_REG_P (operands[0])"
1362 [(set_attr "op_type" "RIL")
1363 (set_attr "type" "larl")
1364 (set_attr "z10prop" "z10_super_A1")])
1366 (define_insn "*movdi_64"
1367 [(set (match_operand:DI 0 "nonimmediate_operand"
1368 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1369 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1370 (match_operand:DI 1 "general_operand"
1371 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1372 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1401 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1402 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1403 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1404 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1406 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1407 z10,*,*,*,*,*,longdisp,*,longdisp,
1409 (set_attr "z10prop" "z10_fwd_A1,
1438 [(set (match_operand:DI 0 "register_operand" "")
1439 (match_operand:DI 1 "register_operand" ""))]
1440 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1441 [(set (match_dup 2) (match_dup 3))
1442 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1443 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1444 "operands[2] = gen_lowpart (SImode, operands[0]);
1445 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1448 [(set (match_operand:DI 0 "register_operand" "")
1449 (match_operand:DI 1 "register_operand" ""))]
1450 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1451 && dead_or_set_p (insn, operands[1])"
1452 [(set (match_dup 3) (match_dup 2))
1453 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1454 (set (match_dup 4) (match_dup 2))]
1455 "operands[2] = gen_lowpart (SImode, operands[1]);
1456 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1459 [(set (match_operand:DI 0 "register_operand" "")
1460 (match_operand:DI 1 "register_operand" ""))]
1461 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1462 && !dead_or_set_p (insn, operands[1])"
1463 [(set (match_dup 3) (match_dup 2))
1464 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1465 (set (match_dup 4) (match_dup 2))
1466 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1467 "operands[2] = gen_lowpart (SImode, operands[1]);
1468 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1470 (define_insn "*movdi_31"
1471 [(set (match_operand:DI 0 "nonimmediate_operand"
1472 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1473 (match_operand:DI 1 "general_operand"
1474 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1489 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1490 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1491 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1493 ; For a load from a symbol ref we can use one of the target registers
1494 ; together with larl to load the address.
1496 [(set (match_operand:DI 0 "register_operand" "")
1497 (match_operand:DI 1 "memory_operand" ""))]
1498 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1499 && larl_operand (XEXP (operands[1], 0), SImode)"
1500 [(set (match_dup 2) (match_dup 3))
1501 (set (match_dup 0) (match_dup 1))]
1503 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1504 operands[3] = XEXP (operands[1], 0);
1505 operands[1] = replace_equiv_address (operands[1], operands[2]);
1509 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1510 (match_operand:DI 1 "general_operand" ""))]
1511 "!TARGET_ZARCH && reload_completed
1512 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1513 [(set (match_dup 2) (match_dup 4))
1514 (set (match_dup 3) (match_dup 5))]
1516 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1517 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1518 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1519 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1523 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1524 (match_operand:DI 1 "general_operand" ""))]
1525 "!TARGET_ZARCH && reload_completed
1526 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1527 [(set (match_dup 2) (match_dup 4))
1528 (set (match_dup 3) (match_dup 5))]
1530 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1531 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1532 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1533 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1537 [(set (match_operand:DI 0 "register_operand" "")
1538 (match_operand:DI 1 "memory_operand" ""))]
1539 "!TARGET_ZARCH && reload_completed
1540 && !FP_REG_P (operands[0])
1541 && !s_operand (operands[1], VOIDmode)"
1542 [(set (match_dup 0) (match_dup 1))]
1544 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1545 s390_load_address (addr, XEXP (operands[1], 0));
1546 operands[1] = replace_equiv_address (operands[1], addr);
1550 [(set (match_operand:DI 0 "register_operand" "")
1551 (mem:DI (match_operand 1 "address_operand" "")))]
1553 && !FP_REG_P (operands[0])
1554 && GET_CODE (operands[1]) == SYMBOL_REF
1555 && CONSTANT_POOL_ADDRESS_P (operands[1])
1556 && get_pool_mode (operands[1]) == DImode
1557 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1558 [(set (match_dup 0) (match_dup 2))]
1559 "operands[2] = get_pool_constant (operands[1]);")
1561 (define_insn "*la_64"
1562 [(set (match_operand:DI 0 "register_operand" "=d,d")
1563 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1568 [(set_attr "op_type" "RX,RXY")
1569 (set_attr "type" "la")
1570 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1574 [(set (match_operand:DI 0 "register_operand" "")
1575 (match_operand:QI 1 "address_operand" ""))
1576 (clobber (reg:CC CC_REGNUM))])]
1578 && preferred_la_operand_p (operands[1], const0_rtx)"
1579 [(set (match_dup 0) (match_dup 1))]
1583 [(set (match_operand:DI 0 "register_operand" "")
1584 (match_operand:DI 1 "register_operand" ""))
1587 (plus:DI (match_dup 0)
1588 (match_operand:DI 2 "nonmemory_operand" "")))
1589 (clobber (reg:CC CC_REGNUM))])]
1591 && !reg_overlap_mentioned_p (operands[0], operands[2])
1592 && preferred_la_operand_p (operands[1], operands[2])"
1593 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1597 ; movsi instruction pattern(s).
1600 (define_expand "movsi"
1601 [(set (match_operand:SI 0 "general_operand" "")
1602 (match_operand:SI 1 "general_operand" ""))]
1605 /* Handle symbolic constants. */
1607 && (SYMBOLIC_CONST (operands[1])
1608 || (GET_CODE (operands[1]) == PLUS
1609 && XEXP (operands[1], 0) == pic_offset_table_rtx
1610 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1611 emit_symbolic_move (operands);
1614 (define_insn "*movsi_larl"
1615 [(set (match_operand:SI 0 "register_operand" "=d")
1616 (match_operand:SI 1 "larl_operand" "X"))]
1617 "!TARGET_64BIT && TARGET_CPU_ZARCH
1618 && !FP_REG_P (operands[0])"
1620 [(set_attr "op_type" "RIL")
1621 (set_attr "type" "larl")
1622 (set_attr "z10prop" "z10_fwd_A1")])
1624 (define_insn "*movsi_zarch"
1625 [(set (match_operand:SI 0 "nonimmediate_operand"
1626 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1627 (match_operand:SI 1 "general_operand"
1628 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1653 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1654 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1655 (set_attr "type" "*,
1677 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1678 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1679 (set_attr "z10prop" "z10_fwd_A1,
1702 (define_insn "*movsi_esa"
1703 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1704 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1718 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1719 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1720 (set_attr "z10prop" "z10_fwd_A1,
1734 [(set (match_operand:SI 0 "register_operand" "")
1735 (mem:SI (match_operand 1 "address_operand" "")))]
1736 "!FP_REG_P (operands[0])
1737 && GET_CODE (operands[1]) == SYMBOL_REF
1738 && CONSTANT_POOL_ADDRESS_P (operands[1])
1739 && get_pool_mode (operands[1]) == SImode
1740 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1741 [(set (match_dup 0) (match_dup 2))]
1742 "operands[2] = get_pool_constant (operands[1]);")
1744 (define_insn "*la_31"
1745 [(set (match_operand:SI 0 "register_operand" "=d,d")
1746 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1747 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1751 [(set_attr "op_type" "RX,RXY")
1752 (set_attr "type" "la")
1753 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1757 [(set (match_operand:SI 0 "register_operand" "")
1758 (match_operand:QI 1 "address_operand" ""))
1759 (clobber (reg:CC CC_REGNUM))])]
1761 && preferred_la_operand_p (operands[1], const0_rtx)"
1762 [(set (match_dup 0) (match_dup 1))]
1766 [(set (match_operand:SI 0 "register_operand" "")
1767 (match_operand:SI 1 "register_operand" ""))
1770 (plus:SI (match_dup 0)
1771 (match_operand:SI 2 "nonmemory_operand" "")))
1772 (clobber (reg:CC CC_REGNUM))])]
1774 && !reg_overlap_mentioned_p (operands[0], operands[2])
1775 && preferred_la_operand_p (operands[1], operands[2])"
1776 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1779 (define_insn "*la_31_and"
1780 [(set (match_operand:SI 0 "register_operand" "=d,d")
1781 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1782 (const_int 2147483647)))]
1787 [(set_attr "op_type" "RX,RXY")
1788 (set_attr "type" "la")
1789 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1791 (define_insn_and_split "*la_31_and_cc"
1792 [(set (match_operand:SI 0 "register_operand" "=d")
1793 (and:SI (match_operand:QI 1 "address_operand" "p")
1794 (const_int 2147483647)))
1795 (clobber (reg:CC CC_REGNUM))]
1798 "&& reload_completed"
1800 (and:SI (match_dup 1) (const_int 2147483647)))]
1802 [(set_attr "op_type" "RX")
1803 (set_attr "type" "la")])
1805 (define_insn "force_la_31"
1806 [(set (match_operand:SI 0 "register_operand" "=d,d")
1807 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1808 (use (const_int 0))]
1813 [(set_attr "op_type" "RX")
1814 (set_attr "type" "la")
1815 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1818 ; movhi instruction pattern(s).
1821 (define_expand "movhi"
1822 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1823 (match_operand:HI 1 "general_operand" ""))]
1826 /* Make it explicit that loading a register from memory
1827 always sign-extends (at least) to SImode. */
1828 if (optimize && can_create_pseudo_p ()
1829 && register_operand (operands[0], VOIDmode)
1830 && GET_CODE (operands[1]) == MEM)
1832 rtx tmp = gen_reg_rtx (SImode);
1833 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1834 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1835 operands[1] = gen_lowpart (HImode, tmp);
1839 (define_insn "*movhi"
1840 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1841 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1853 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1854 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1855 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1856 (set_attr "z10prop" "z10_fr_E1,
1867 [(set (match_operand:HI 0 "register_operand" "")
1868 (mem:HI (match_operand 1 "address_operand" "")))]
1869 "GET_CODE (operands[1]) == SYMBOL_REF
1870 && CONSTANT_POOL_ADDRESS_P (operands[1])
1871 && get_pool_mode (operands[1]) == HImode
1872 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1873 [(set (match_dup 0) (match_dup 2))]
1874 "operands[2] = get_pool_constant (operands[1]);")
1877 ; movqi instruction pattern(s).
1880 (define_expand "movqi"
1881 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1882 (match_operand:QI 1 "general_operand" ""))]
1885 /* On z/Architecture, zero-extending from memory to register
1886 is just as fast as a QImode load. */
1887 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1888 && register_operand (operands[0], VOIDmode)
1889 && GET_CODE (operands[1]) == MEM)
1891 rtx tmp = gen_reg_rtx (DImode);
1892 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1893 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1894 operands[1] = gen_lowpart (QImode, tmp);
1898 (define_insn "*movqi"
1899 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1900 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1912 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1913 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1914 (set_attr "z10prop" "z10_fr_E1,
1925 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1926 (mem:QI (match_operand 1 "address_operand" "")))]
1927 "GET_CODE (operands[1]) == SYMBOL_REF
1928 && CONSTANT_POOL_ADDRESS_P (operands[1])
1929 && get_pool_mode (operands[1]) == QImode
1930 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1931 [(set (match_dup 0) (match_dup 2))]
1932 "operands[2] = get_pool_constant (operands[1]);")
1935 ; movstrictqi instruction pattern(s).
1938 (define_insn "*movstrictqi"
1939 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1940 (match_operand:QI 1 "memory_operand" "R,T"))]
1945 [(set_attr "op_type" "RX,RXY")
1946 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1949 ; movstricthi instruction pattern(s).
1952 (define_insn "*movstricthi"
1953 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1954 (match_operand:HI 1 "memory_operand" "Q,S"))
1955 (clobber (reg:CC CC_REGNUM))]
1960 [(set_attr "op_type" "RS,RSY")
1961 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1964 ; movstrictsi instruction pattern(s).
1967 (define_insn "movstrictsi"
1968 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1969 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1976 [(set_attr "op_type" "RR,RX,RXY,RRE")
1977 (set_attr "type" "lr,load,load,*")
1978 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1981 ; mov(tf|td) instruction pattern(s).
1984 (define_expand "mov<mode>"
1985 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1986 (match_operand:TD_TF 1 "general_operand" ""))]
1990 (define_insn "*mov<mode>_64"
1991 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1992 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2003 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2004 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2005 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2007 (define_insn "*mov<mode>_31"
2008 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2009 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2016 [(set_attr "op_type" "RRE,RRE,*,*")
2017 (set_attr "type" "fsimptf,fsimptf,*,*")
2018 (set_attr "cpu_facility" "z196,*,*,*")])
2020 ; TFmode in GPRs splitters
2023 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2024 (match_operand:TD_TF 1 "general_operand" ""))]
2025 "TARGET_ZARCH && reload_completed
2026 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2027 [(set (match_dup 2) (match_dup 4))
2028 (set (match_dup 3) (match_dup 5))]
2030 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2031 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2032 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2033 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2037 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2038 (match_operand:TD_TF 1 "general_operand" ""))]
2039 "TARGET_ZARCH && reload_completed
2040 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2041 [(set (match_dup 2) (match_dup 4))
2042 (set (match_dup 3) (match_dup 5))]
2044 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2045 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2046 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2047 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2051 [(set (match_operand:TD_TF 0 "register_operand" "")
2052 (match_operand:TD_TF 1 "memory_operand" ""))]
2053 "TARGET_ZARCH && reload_completed
2054 && !FP_REG_P (operands[0])
2055 && !s_operand (operands[1], VOIDmode)"
2056 [(set (match_dup 0) (match_dup 1))]
2058 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2059 addr = gen_lowpart (Pmode, addr);
2060 s390_load_address (addr, XEXP (operands[1], 0));
2061 operands[1] = replace_equiv_address (operands[1], addr);
2064 ; TFmode in BFPs splitters
2067 [(set (match_operand:TD_TF 0 "register_operand" "")
2068 (match_operand:TD_TF 1 "memory_operand" ""))]
2069 "reload_completed && offsettable_memref_p (operands[1])
2070 && FP_REG_P (operands[0])"
2071 [(set (match_dup 2) (match_dup 4))
2072 (set (match_dup 3) (match_dup 5))]
2074 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2076 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2078 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2079 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2083 [(set (match_operand:TD_TF 0 "memory_operand" "")
2084 (match_operand:TD_TF 1 "register_operand" ""))]
2085 "reload_completed && offsettable_memref_p (operands[0])
2086 && FP_REG_P (operands[1])"
2087 [(set (match_dup 2) (match_dup 4))
2088 (set (match_dup 3) (match_dup 5))]
2090 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2091 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2092 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2094 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2099 ; mov(df|dd) instruction pattern(s).
2102 (define_expand "mov<mode>"
2103 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2104 (match_operand:DD_DF 1 "general_operand" ""))]
2108 (define_insn "*mov<mode>_64dfp"
2109 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2110 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2111 (match_operand:DD_DF 1 "general_operand"
2112 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2127 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2128 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2129 fstoredf,fstoredf,*,lr,load,store")
2130 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2131 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2133 (define_insn "*mov<mode>_64"
2134 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2135 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2148 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2149 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2150 fstore<mode>,fstore<mode>,*,lr,load,store")
2151 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2152 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2154 (define_insn "*mov<mode>_31"
2155 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2156 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2157 (match_operand:DD_DF 1 "general_operand"
2158 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2173 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2174 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2175 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2176 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2179 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2180 (match_operand:DD_DF 1 "general_operand" ""))]
2181 "!TARGET_ZARCH && reload_completed
2182 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2183 [(set (match_dup 2) (match_dup 4))
2184 (set (match_dup 3) (match_dup 5))]
2186 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2187 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2188 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2189 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2193 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2194 (match_operand:DD_DF 1 "general_operand" ""))]
2195 "!TARGET_ZARCH && reload_completed
2196 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2197 [(set (match_dup 2) (match_dup 4))
2198 (set (match_dup 3) (match_dup 5))]
2200 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2201 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2202 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2203 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2207 [(set (match_operand:DD_DF 0 "register_operand" "")
2208 (match_operand:DD_DF 1 "memory_operand" ""))]
2209 "!TARGET_ZARCH && reload_completed
2210 && !FP_REG_P (operands[0])
2211 && !s_operand (operands[1], VOIDmode)"
2212 [(set (match_dup 0) (match_dup 1))]
2214 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2215 s390_load_address (addr, XEXP (operands[1], 0));
2216 operands[1] = replace_equiv_address (operands[1], addr);
2220 ; mov(sf|sd) instruction pattern(s).
2223 (define_insn "mov<mode>"
2224 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2225 "=f,f,f,f,R,T,d,d,d,d,R,T")
2226 (match_operand:SD_SF 1 "general_operand"
2227 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2242 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2243 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2244 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2245 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2246 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2249 ; movcc instruction pattern
2252 (define_insn "movcc"
2253 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2254 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2264 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2265 (set_attr "type" "lr,*,*,store,store,load,load")
2266 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2267 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2270 ; Block move (MVC) patterns.
2274 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2275 (match_operand:BLK 1 "memory_operand" "Q"))
2276 (use (match_operand 2 "const_int_operand" "n"))]
2277 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2278 "mvc\t%O0(%2,%R0),%S1"
2279 [(set_attr "op_type" "SS")])
2281 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2282 ; order to have it implemented with mvc.
2285 [(set (match_operand:QI 0 "memory_operand" "")
2286 (match_operand:QI 1 "memory_operand" ""))]
2289 [(set (match_dup 0) (match_dup 1))
2290 (use (const_int 1))])]
2292 operands[0] = adjust_address (operands[0], BLKmode, 0);
2293 operands[1] = adjust_address (operands[1], BLKmode, 0);
2299 [(set (match_operand:BLK 0 "memory_operand" "")
2300 (match_operand:BLK 1 "memory_operand" ""))
2301 (use (match_operand 2 "const_int_operand" ""))])
2303 [(set (match_operand:BLK 3 "memory_operand" "")
2304 (match_operand:BLK 4 "memory_operand" ""))
2305 (use (match_operand 5 "const_int_operand" ""))])]
2306 "s390_offset_p (operands[0], operands[3], operands[2])
2307 && s390_offset_p (operands[1], operands[4], operands[2])
2308 && !s390_overlap_p (operands[0], operands[1],
2309 INTVAL (operands[2]) + INTVAL (operands[5]))
2310 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2312 [(set (match_dup 6) (match_dup 7))
2313 (use (match_dup 8))])]
2314 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2315 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2316 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2320 ; load_multiple pattern(s).
2322 ; ??? Due to reload problems with replacing registers inside match_parallel
2323 ; we currently support load_multiple/store_multiple only after reload.
2326 (define_expand "load_multiple"
2327 [(match_par_dup 3 [(set (match_operand 0 "" "")
2328 (match_operand 1 "" ""))
2329 (use (match_operand 2 "" ""))])]
2332 enum machine_mode mode;
2338 /* Support only loading a constant number of fixed-point registers from
2339 memory and only bother with this if more than two */
2340 if (GET_CODE (operands[2]) != CONST_INT
2341 || INTVAL (operands[2]) < 2
2342 || INTVAL (operands[2]) > 16
2343 || GET_CODE (operands[1]) != MEM
2344 || GET_CODE (operands[0]) != REG
2345 || REGNO (operands[0]) >= 16)
2348 count = INTVAL (operands[2]);
2349 regno = REGNO (operands[0]);
2350 mode = GET_MODE (operands[0]);
2351 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2354 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2355 if (!can_create_pseudo_p ())
2357 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2359 from = XEXP (operands[1], 0);
2362 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2363 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2364 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2366 from = XEXP (XEXP (operands[1], 0), 0);
2367 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2374 from = force_reg (Pmode, XEXP (operands[1], 0));
2378 for (i = 0; i < count; i++)
2379 XVECEXP (operands[3], 0, i)
2380 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2381 change_address (operands[1], mode,
2382 plus_constant (Pmode, from,
2383 off + i * GET_MODE_SIZE (mode))));
2386 (define_insn "*load_multiple_di"
2387 [(match_parallel 0 "load_multiple_operation"
2388 [(set (match_operand:DI 1 "register_operand" "=r")
2389 (match_operand:DI 2 "s_operand" "QS"))])]
2390 "reload_completed && TARGET_ZARCH"
2392 int words = XVECLEN (operands[0], 0);
2393 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2394 return "lmg\t%1,%0,%S2";
2396 [(set_attr "op_type" "RSY")
2397 (set_attr "type" "lm")])
2399 (define_insn "*load_multiple_si"
2400 [(match_parallel 0 "load_multiple_operation"
2401 [(set (match_operand:SI 1 "register_operand" "=r,r")
2402 (match_operand:SI 2 "s_operand" "Q,S"))])]
2405 int words = XVECLEN (operands[0], 0);
2406 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2407 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2409 [(set_attr "op_type" "RS,RSY")
2410 (set_attr "type" "lm")])
2413 ; store multiple pattern(s).
2416 (define_expand "store_multiple"
2417 [(match_par_dup 3 [(set (match_operand 0 "" "")
2418 (match_operand 1 "" ""))
2419 (use (match_operand 2 "" ""))])]
2422 enum machine_mode mode;
2428 /* Support only storing a constant number of fixed-point registers to
2429 memory and only bother with this if more than two. */
2430 if (GET_CODE (operands[2]) != CONST_INT
2431 || INTVAL (operands[2]) < 2
2432 || INTVAL (operands[2]) > 16
2433 || GET_CODE (operands[0]) != MEM
2434 || GET_CODE (operands[1]) != REG
2435 || REGNO (operands[1]) >= 16)
2438 count = INTVAL (operands[2]);
2439 regno = REGNO (operands[1]);
2440 mode = GET_MODE (operands[1]);
2441 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2444 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2446 if (!can_create_pseudo_p ())
2448 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2450 to = XEXP (operands[0], 0);
2453 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2454 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2455 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2457 to = XEXP (XEXP (operands[0], 0), 0);
2458 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2465 to = force_reg (Pmode, XEXP (operands[0], 0));
2469 for (i = 0; i < count; i++)
2470 XVECEXP (operands[3], 0, i)
2471 = gen_rtx_SET (VOIDmode,
2472 change_address (operands[0], mode,
2473 plus_constant (Pmode, to,
2474 off + i * GET_MODE_SIZE (mode))),
2475 gen_rtx_REG (mode, regno + i));
2478 (define_insn "*store_multiple_di"
2479 [(match_parallel 0 "store_multiple_operation"
2480 [(set (match_operand:DI 1 "s_operand" "=QS")
2481 (match_operand:DI 2 "register_operand" "r"))])]
2482 "reload_completed && TARGET_ZARCH"
2484 int words = XVECLEN (operands[0], 0);
2485 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2486 return "stmg\t%2,%0,%S1";
2488 [(set_attr "op_type" "RSY")
2489 (set_attr "type" "stm")])
2492 (define_insn "*store_multiple_si"
2493 [(match_parallel 0 "store_multiple_operation"
2494 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2495 (match_operand:SI 2 "register_operand" "r,r"))])]
2498 int words = XVECLEN (operands[0], 0);
2499 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2500 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2502 [(set_attr "op_type" "RS,RSY")
2503 (set_attr "type" "stm")])
2506 ;; String instructions.
2509 (define_insn "*execute_rl"
2510 [(match_parallel 0 "execute_operation"
2511 [(unspec [(match_operand 1 "register_operand" "a")
2512 (match_operand 2 "" "")
2513 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2514 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2515 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2517 [(set_attr "op_type" "RIL")
2518 (set_attr "type" "cs")])
2520 (define_insn "*execute"
2521 [(match_parallel 0 "execute_operation"
2522 [(unspec [(match_operand 1 "register_operand" "a")
2523 (match_operand:BLK 2 "memory_operand" "R")
2524 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2525 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2526 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2528 [(set_attr "op_type" "RX")
2529 (set_attr "type" "cs")])
2533 ; strlenM instruction pattern(s).
2536 (define_expand "strlen<mode>"
2537 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2540 (unspec:P [(const_int 0)
2541 (match_operand:BLK 1 "memory_operand" "")
2543 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2544 (clobber (scratch:P))
2545 (clobber (reg:CC CC_REGNUM))])
2547 [(set (match_operand:P 0 "register_operand" "")
2548 (minus:P (match_dup 4) (match_dup 5)))
2549 (clobber (reg:CC CC_REGNUM))])]
2552 operands[4] = gen_reg_rtx (Pmode);
2553 operands[5] = gen_reg_rtx (Pmode);
2554 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2555 operands[1] = replace_equiv_address (operands[1], operands[5]);
2558 (define_insn "*strlen<mode>"
2559 [(set (match_operand:P 0 "register_operand" "=a")
2560 (unspec:P [(match_operand:P 2 "general_operand" "0")
2561 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2563 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2564 (clobber (match_scratch:P 1 "=a"))
2565 (clobber (reg:CC CC_REGNUM))]
2567 "srst\t%0,%1\;jo\t.-4"
2568 [(set_attr "length" "8")
2569 (set_attr "type" "vs")])
2572 ; cmpstrM instruction pattern(s).
2575 (define_expand "cmpstrsi"
2576 [(set (reg:SI 0) (const_int 0))
2578 [(clobber (match_operand 3 "" ""))
2579 (clobber (match_dup 4))
2580 (set (reg:CCU CC_REGNUM)
2581 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2582 (match_operand:BLK 2 "memory_operand" "")))
2585 [(set (match_operand:SI 0 "register_operand" "=d")
2586 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2587 (clobber (reg:CC CC_REGNUM))])]
2590 /* As the result of CMPINT is inverted compared to what we need,
2591 we have to swap the operands. */
2592 rtx op1 = operands[2];
2593 rtx op2 = operands[1];
2594 rtx addr1 = gen_reg_rtx (Pmode);
2595 rtx addr2 = gen_reg_rtx (Pmode);
2597 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2598 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2599 operands[1] = replace_equiv_address_nv (op1, addr1);
2600 operands[2] = replace_equiv_address_nv (op2, addr2);
2601 operands[3] = addr1;
2602 operands[4] = addr2;
2605 (define_insn "*cmpstr<mode>"
2606 [(clobber (match_operand:P 0 "register_operand" "=d"))
2607 (clobber (match_operand:P 1 "register_operand" "=d"))
2608 (set (reg:CCU CC_REGNUM)
2609 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2610 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2613 "clst\t%0,%1\;jo\t.-4"
2614 [(set_attr "length" "8")
2615 (set_attr "type" "vs")])
2618 ; movstr instruction pattern.
2621 (define_expand "movstr"
2622 [(set (reg:SI 0) (const_int 0))
2624 [(clobber (match_dup 3))
2625 (set (match_operand:BLK 1 "memory_operand" "")
2626 (match_operand:BLK 2 "memory_operand" ""))
2627 (set (match_operand 0 "register_operand" "")
2628 (unspec [(match_dup 1)
2630 (reg:SI 0)] UNSPEC_MVST))
2631 (clobber (reg:CC CC_REGNUM))])]
2634 rtx addr1 = gen_reg_rtx (Pmode);
2635 rtx addr2 = gen_reg_rtx (Pmode);
2637 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2638 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2639 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2640 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2641 operands[3] = addr2;
2644 (define_insn "*movstr"
2645 [(clobber (match_operand:P 2 "register_operand" "=d"))
2646 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2647 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2648 (set (match_operand:P 0 "register_operand" "=d")
2649 (unspec [(mem:BLK (match_dup 1))
2650 (mem:BLK (match_dup 3))
2651 (reg:SI 0)] UNSPEC_MVST))
2652 (clobber (reg:CC CC_REGNUM))]
2654 "mvst\t%1,%2\;jo\t.-4"
2655 [(set_attr "length" "8")
2656 (set_attr "type" "vs")])
2660 ; movmemM instruction pattern(s).
2663 (define_expand "movmem<mode>"
2664 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2665 (match_operand:BLK 1 "memory_operand" "")) ; source
2666 (use (match_operand:GPR 2 "general_operand" "")) ; count
2667 (match_operand 3 "" "")]
2670 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2676 ; Move a block that is up to 256 bytes in length.
2677 ; The block length is taken as (operands[2] % 256) + 1.
2679 (define_expand "movmem_short"
2681 [(set (match_operand:BLK 0 "memory_operand" "")
2682 (match_operand:BLK 1 "memory_operand" ""))
2683 (use (match_operand 2 "nonmemory_operand" ""))
2684 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2685 (clobber (match_dup 3))])]
2687 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2689 (define_insn "*movmem_short"
2690 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2691 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2692 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2693 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2694 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2695 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2697 [(set_attr "type" "cs")
2698 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2701 [(set (match_operand:BLK 0 "memory_operand" "")
2702 (match_operand:BLK 1 "memory_operand" ""))
2703 (use (match_operand 2 "const_int_operand" ""))
2704 (use (match_operand 3 "immediate_operand" ""))
2705 (clobber (scratch))]
2708 [(set (match_dup 0) (match_dup 1))
2709 (use (match_dup 2))])]
2710 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2713 [(set (match_operand:BLK 0 "memory_operand" "")
2714 (match_operand:BLK 1 "memory_operand" ""))
2715 (use (match_operand 2 "register_operand" ""))
2716 (use (match_operand 3 "memory_operand" ""))
2717 (clobber (scratch))]
2720 [(unspec [(match_dup 2) (match_dup 3)
2721 (const_int 0)] UNSPEC_EXECUTE)
2722 (set (match_dup 0) (match_dup 1))
2723 (use (const_int 1))])]
2727 [(set (match_operand:BLK 0 "memory_operand" "")
2728 (match_operand:BLK 1 "memory_operand" ""))
2729 (use (match_operand 2 "register_operand" ""))
2730 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2731 (clobber (scratch))]
2732 "TARGET_Z10 && reload_completed"
2734 [(unspec [(match_dup 2) (const_int 0)
2735 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2736 (set (match_dup 0) (match_dup 1))
2737 (use (const_int 1))])]
2738 "operands[3] = gen_label_rtx ();")
2741 [(set (match_operand:BLK 0 "memory_operand" "")
2742 (match_operand:BLK 1 "memory_operand" ""))
2743 (use (match_operand 2 "register_operand" ""))
2744 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2745 (clobber (match_operand 3 "register_operand" ""))]
2746 "reload_completed && TARGET_CPU_ZARCH"
2747 [(set (match_dup 3) (label_ref (match_dup 4)))
2749 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2750 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2751 (set (match_dup 0) (match_dup 1))
2752 (use (const_int 1))])]
2753 "operands[4] = gen_label_rtx ();")
2755 ; Move a block of arbitrary length.
2757 (define_expand "movmem_long"
2759 [(clobber (match_dup 2))
2760 (clobber (match_dup 3))
2761 (set (match_operand:BLK 0 "memory_operand" "")
2762 (match_operand:BLK 1 "memory_operand" ""))
2763 (use (match_operand 2 "general_operand" ""))
2765 (clobber (reg:CC CC_REGNUM))])]
2768 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2769 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2770 rtx reg0 = gen_reg_rtx (dreg_mode);
2771 rtx reg1 = gen_reg_rtx (dreg_mode);
2772 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2773 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2774 rtx len0 = gen_lowpart (Pmode, reg0);
2775 rtx len1 = gen_lowpart (Pmode, reg1);
2777 emit_clobber (reg0);
2778 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2779 emit_move_insn (len0, operands[2]);
2781 emit_clobber (reg1);
2782 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2783 emit_move_insn (len1, operands[2]);
2785 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2786 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2791 (define_insn "*movmem_long"
2792 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2793 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2794 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2795 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2798 (clobber (reg:CC CC_REGNUM))]
2799 "TARGET_64BIT || !TARGET_ZARCH"
2800 "mvcle\t%0,%1,0\;jo\t.-4"
2801 [(set_attr "length" "8")
2802 (set_attr "type" "vs")])
2804 (define_insn "*movmem_long_31z"
2805 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2806 (clobber (match_operand:TI 1 "register_operand" "=d"))
2807 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2808 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2811 (clobber (reg:CC CC_REGNUM))]
2812 "!TARGET_64BIT && TARGET_ZARCH"
2813 "mvcle\t%0,%1,0\;jo\t.-4"
2814 [(set_attr "length" "8")
2815 (set_attr "type" "vs")])
2822 (define_expand "signbit<mode>2"
2823 [(set (reg:CCZ CC_REGNUM)
2824 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2827 (set (match_operand:SI 0 "register_operand" "=d")
2828 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2831 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2834 (define_expand "isinf<mode>2"
2835 [(set (reg:CCZ CC_REGNUM)
2836 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2839 (set (match_operand:SI 0 "register_operand" "=d")
2840 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2843 operands[2] = GEN_INT (S390_TDC_INFINITY);
2846 ; This insn is used to generate all variants of the Test Data Class
2847 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2848 ; is the register to be tested and the second one is the bit mask
2849 ; specifying the required test(s).
2851 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2852 (define_insn "*TDC_insn_<mode>"
2853 [(set (reg:CCZ CC_REGNUM)
2854 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2855 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2857 "t<_d>c<xde><bt>\t%0,%1"
2858 [(set_attr "op_type" "RXE")
2859 (set_attr "type" "fsimp<mode>")])
2861 (define_insn_and_split "*ccz_to_int"
2862 [(set (match_operand:SI 0 "register_operand" "=d")
2863 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2864 UNSPEC_CCZ_TO_INT))]
2868 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2872 ; setmemM instruction pattern(s).
2875 (define_expand "setmem<mode>"
2876 [(set (match_operand:BLK 0 "memory_operand" "")
2877 (match_operand:QI 2 "general_operand" ""))
2878 (use (match_operand:GPR 1 "general_operand" ""))
2879 (match_operand 3 "" "")]
2881 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2883 ; Clear a block that is up to 256 bytes in length.
2884 ; The block length is taken as (operands[1] % 256) + 1.
2886 (define_expand "clrmem_short"
2888 [(set (match_operand:BLK 0 "memory_operand" "")
2890 (use (match_operand 1 "nonmemory_operand" ""))
2891 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2892 (clobber (match_dup 2))
2893 (clobber (reg:CC CC_REGNUM))])]
2895 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2897 (define_insn "*clrmem_short"
2898 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2900 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2901 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2902 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2903 (clobber (reg:CC CC_REGNUM))]
2904 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2906 [(set_attr "type" "cs")
2907 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2910 [(set (match_operand:BLK 0 "memory_operand" "")
2912 (use (match_operand 1 "const_int_operand" ""))
2913 (use (match_operand 2 "immediate_operand" ""))
2915 (clobber (reg:CC CC_REGNUM))]
2918 [(set (match_dup 0) (const_int 0))
2920 (clobber (reg:CC CC_REGNUM))])]
2921 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2924 [(set (match_operand:BLK 0 "memory_operand" "")
2926 (use (match_operand 1 "register_operand" ""))
2927 (use (match_operand 2 "memory_operand" ""))
2929 (clobber (reg:CC CC_REGNUM))]
2932 [(unspec [(match_dup 1) (match_dup 2)
2933 (const_int 0)] UNSPEC_EXECUTE)
2934 (set (match_dup 0) (const_int 0))
2936 (clobber (reg:CC CC_REGNUM))])]
2940 [(set (match_operand:BLK 0 "memory_operand" "")
2942 (use (match_operand 1 "register_operand" ""))
2943 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2945 (clobber (reg:CC CC_REGNUM))]
2946 "TARGET_Z10 && reload_completed"
2948 [(unspec [(match_dup 1) (const_int 0)
2949 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2950 (set (match_dup 0) (const_int 0))
2952 (clobber (reg:CC CC_REGNUM))])]
2953 "operands[3] = gen_label_rtx ();")
2956 [(set (match_operand:BLK 0 "memory_operand" "")
2958 (use (match_operand 1 "register_operand" ""))
2959 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2960 (clobber (match_operand 2 "register_operand" ""))
2961 (clobber (reg:CC CC_REGNUM))]
2962 "reload_completed && TARGET_CPU_ZARCH"
2963 [(set (match_dup 2) (label_ref (match_dup 3)))
2965 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2966 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2967 (set (match_dup 0) (const_int 0))
2969 (clobber (reg:CC CC_REGNUM))])]
2970 "operands[3] = gen_label_rtx ();")
2972 ; Initialize a block of arbitrary length with (operands[2] % 256).
2974 (define_expand "setmem_long"
2976 [(clobber (match_dup 1))
2977 (set (match_operand:BLK 0 "memory_operand" "")
2978 (match_operand 2 "shift_count_or_setmem_operand" ""))
2979 (use (match_operand 1 "general_operand" ""))
2981 (clobber (reg:CC CC_REGNUM))])]
2984 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2985 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2986 rtx reg0 = gen_reg_rtx (dreg_mode);
2987 rtx reg1 = gen_reg_rtx (dreg_mode);
2988 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2989 rtx len0 = gen_lowpart (Pmode, reg0);
2991 emit_clobber (reg0);
2992 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2993 emit_move_insn (len0, operands[1]);
2995 emit_move_insn (reg1, const0_rtx);
2997 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3002 (define_insn "*setmem_long"
3003 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3004 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3005 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3007 (use (match_operand:<DBL> 1 "register_operand" "d"))
3008 (clobber (reg:CC CC_REGNUM))]
3009 "TARGET_64BIT || !TARGET_ZARCH"
3010 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3011 [(set_attr "length" "8")
3012 (set_attr "type" "vs")])
3014 (define_insn "*setmem_long_and"
3015 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3016 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3017 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3018 (match_operand 4 "const_int_operand" "n")))
3020 (use (match_operand:<DBL> 1 "register_operand" "d"))
3021 (clobber (reg:CC CC_REGNUM))]
3022 "(TARGET_64BIT || !TARGET_ZARCH) &&
3023 (INTVAL (operands[4]) & 255) == 255"
3024 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3025 [(set_attr "length" "8")
3026 (set_attr "type" "vs")])
3028 (define_insn "*setmem_long_31z"
3029 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3030 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3031 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3033 (use (match_operand:TI 1 "register_operand" "d"))
3034 (clobber (reg:CC CC_REGNUM))]
3035 "!TARGET_64BIT && TARGET_ZARCH"
3036 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3037 [(set_attr "length" "8")
3038 (set_attr "type" "vs")])
3041 ; cmpmemM instruction pattern(s).
3044 (define_expand "cmpmemsi"
3045 [(set (match_operand:SI 0 "register_operand" "")
3046 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3047 (match_operand:BLK 2 "memory_operand" "") ) )
3048 (use (match_operand:SI 3 "general_operand" ""))
3049 (use (match_operand:SI 4 "" ""))]
3052 if (s390_expand_cmpmem (operands[0], operands[1],
3053 operands[2], operands[3]))
3059 ; Compare a block that is up to 256 bytes in length.
3060 ; The block length is taken as (operands[2] % 256) + 1.
3062 (define_expand "cmpmem_short"
3064 [(set (reg:CCU CC_REGNUM)
3065 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3066 (match_operand:BLK 1 "memory_operand" "")))
3067 (use (match_operand 2 "nonmemory_operand" ""))
3068 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3069 (clobber (match_dup 3))])]
3071 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3073 (define_insn "*cmpmem_short"
3074 [(set (reg:CCU CC_REGNUM)
3075 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3076 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3077 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3078 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3079 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3080 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3082 [(set_attr "type" "cs")
3083 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3086 [(set (reg:CCU CC_REGNUM)
3087 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3088 (match_operand:BLK 1 "memory_operand" "")))
3089 (use (match_operand 2 "const_int_operand" ""))
3090 (use (match_operand 3 "immediate_operand" ""))
3091 (clobber (scratch))]
3094 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3095 (use (match_dup 2))])]
3096 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3099 [(set (reg:CCU CC_REGNUM)
3100 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3101 (match_operand:BLK 1 "memory_operand" "")))
3102 (use (match_operand 2 "register_operand" ""))
3103 (use (match_operand 3 "memory_operand" ""))
3104 (clobber (scratch))]
3107 [(unspec [(match_dup 2) (match_dup 3)
3108 (const_int 0)] UNSPEC_EXECUTE)
3109 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3110 (use (const_int 1))])]
3114 [(set (reg:CCU CC_REGNUM)
3115 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3116 (match_operand:BLK 1 "memory_operand" "")))
3117 (use (match_operand 2 "register_operand" ""))
3118 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3119 (clobber (scratch))]
3120 "TARGET_Z10 && reload_completed"
3122 [(unspec [(match_dup 2) (const_int 0)
3123 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3124 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3125 (use (const_int 1))])]
3126 "operands[4] = gen_label_rtx ();")
3129 [(set (reg:CCU CC_REGNUM)
3130 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3131 (match_operand:BLK 1 "memory_operand" "")))
3132 (use (match_operand 2 "register_operand" ""))
3133 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3134 (clobber (match_operand 3 "register_operand" ""))]
3135 "reload_completed && TARGET_CPU_ZARCH"
3136 [(set (match_dup 3) (label_ref (match_dup 4)))
3138 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3139 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3140 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3141 (use (const_int 1))])]
3142 "operands[4] = gen_label_rtx ();")
3144 ; Compare a block of arbitrary length.
3146 (define_expand "cmpmem_long"
3148 [(clobber (match_dup 2))
3149 (clobber (match_dup 3))
3150 (set (reg:CCU CC_REGNUM)
3151 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3152 (match_operand:BLK 1 "memory_operand" "")))
3153 (use (match_operand 2 "general_operand" ""))
3154 (use (match_dup 3))])]
3157 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3158 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3159 rtx reg0 = gen_reg_rtx (dreg_mode);
3160 rtx reg1 = gen_reg_rtx (dreg_mode);
3161 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3162 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3163 rtx len0 = gen_lowpart (Pmode, reg0);
3164 rtx len1 = gen_lowpart (Pmode, reg1);
3166 emit_clobber (reg0);
3167 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3168 emit_move_insn (len0, operands[2]);
3170 emit_clobber (reg1);
3171 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3172 emit_move_insn (len1, operands[2]);
3174 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3175 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3180 (define_insn "*cmpmem_long"
3181 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3182 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3183 (set (reg:CCU CC_REGNUM)
3184 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3185 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3187 (use (match_dup 3))]
3188 "TARGET_64BIT || !TARGET_ZARCH"
3189 "clcle\t%0,%1,0\;jo\t.-4"
3190 [(set_attr "length" "8")
3191 (set_attr "type" "vs")])
3193 (define_insn "*cmpmem_long_31z"
3194 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3195 (clobber (match_operand:TI 1 "register_operand" "=d"))
3196 (set (reg:CCU CC_REGNUM)
3197 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3198 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3200 (use (match_dup 3))]
3201 "!TARGET_64BIT && TARGET_ZARCH"
3202 "clcle\t%0,%1,0\;jo\t.-4"
3203 [(set_attr "op_type" "NN")
3204 (set_attr "type" "vs")
3205 (set_attr "length" "8")])
3207 ; Convert CCUmode condition code to integer.
3208 ; Result is zero if EQ, positive if LTU, negative if GTU.
3210 (define_insn_and_split "cmpint"
3211 [(set (match_operand:SI 0 "register_operand" "=d")
3212 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3214 (clobber (reg:CC CC_REGNUM))]
3218 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3220 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3221 (clobber (reg:CC CC_REGNUM))])])
3223 (define_insn_and_split "*cmpint_cc"
3224 [(set (reg CC_REGNUM)
3225 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3228 (set (match_operand:SI 0 "register_operand" "=d")
3229 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3230 "s390_match_ccmode (insn, CCSmode)"
3232 "&& reload_completed"
3233 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3235 [(set (match_dup 2) (match_dup 3))
3236 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3238 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3239 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3240 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3243 (define_insn_and_split "*cmpint_sign"
3244 [(set (match_operand:DI 0 "register_operand" "=d")
3245 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3246 UNSPEC_CCU_TO_INT)))
3247 (clobber (reg:CC CC_REGNUM))]
3250 "&& reload_completed"
3251 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3253 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3254 (clobber (reg:CC CC_REGNUM))])])
3256 (define_insn_and_split "*cmpint_sign_cc"
3257 [(set (reg CC_REGNUM)
3258 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3259 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3260 UNSPEC_CCU_TO_INT) 0)
3261 (const_int 32)) (const_int 32))
3263 (set (match_operand:DI 0 "register_operand" "=d")
3264 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3265 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3267 "&& reload_completed"
3268 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3270 [(set (match_dup 2) (match_dup 3))
3271 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3273 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3274 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3275 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3280 ;;- Conversion instructions.
3283 (define_insn "*sethighpartsi"
3284 [(set (match_operand:SI 0 "register_operand" "=d,d")
3285 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3286 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3287 (clobber (reg:CC CC_REGNUM))]
3292 [(set_attr "op_type" "RS,RSY")
3293 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3295 (define_insn "*sethighpartdi_64"
3296 [(set (match_operand:DI 0 "register_operand" "=d")
3297 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3298 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3299 (clobber (reg:CC CC_REGNUM))]
3302 [(set_attr "op_type" "RSY")
3303 (set_attr "z10prop" "z10_super")])
3305 (define_insn "*sethighpartdi_31"
3306 [(set (match_operand:DI 0 "register_operand" "=d,d")
3307 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3308 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3309 (clobber (reg:CC CC_REGNUM))]
3314 [(set_attr "op_type" "RS,RSY")
3315 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3318 ; extv instruction patterns
3321 ; FIXME: This expander needs to be converted from DI to GPR as well
3322 ; after resolving some issues with it.
3324 (define_expand "extzv"
3326 [(set (match_operand:DI 0 "register_operand" "=d")
3328 (match_operand:DI 1 "register_operand" "d")
3329 (match_operand 2 "const_int_operand" "") ; size
3330 (match_operand 3 "const_int_operand" ""))) ; start
3331 (clobber (reg:CC CC_REGNUM))])]
3334 /* Starting with zEC12 there is risbgn not clobbering CC. */
3337 emit_move_insn (operands[0],
3338 gen_rtx_ZERO_EXTRACT (DImode,
3346 (define_insn "*extzv<mode>_zEC12"
3347 [(set (match_operand:GPR 0 "register_operand" "=d")
3349 (match_operand:GPR 1 "register_operand" "d")
3350 (match_operand 2 "const_int_operand" "") ; size
3351 (match_operand 3 "const_int_operand" "")))] ; start]
3353 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3354 [(set_attr "op_type" "RIE")])
3356 (define_insn "*extzv<mode>_z10"
3357 [(set (match_operand:GPR 0 "register_operand" "=d")
3359 (match_operand:GPR 1 "register_operand" "d")
3360 (match_operand 2 "const_int_operand" "") ; size
3361 (match_operand 3 "const_int_operand" ""))) ; start
3362 (clobber (reg:CC CC_REGNUM))]
3364 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3365 [(set_attr "op_type" "RIE")
3366 (set_attr "z10prop" "z10_super_E1")])
3368 (define_insn_and_split "*pre_z10_extzv<mode>"
3369 [(set (match_operand:GPR 0 "register_operand" "=d")
3370 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3371 (match_operand 2 "nonzero_shift_count_operand" "")
3373 (clobber (reg:CC CC_REGNUM))]
3376 "&& reload_completed"
3378 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3379 (clobber (reg:CC CC_REGNUM))])
3380 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3382 int bitsize = INTVAL (operands[2]);
3383 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3384 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3386 operands[1] = adjust_address (operands[1], BLKmode, 0);
3387 set_mem_size (operands[1], size);
3388 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3389 operands[3] = GEN_INT (mask);
3392 (define_insn_and_split "*pre_z10_extv<mode>"
3393 [(set (match_operand:GPR 0 "register_operand" "=d")
3394 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3395 (match_operand 2 "nonzero_shift_count_operand" "")
3397 (clobber (reg:CC CC_REGNUM))]
3400 "&& reload_completed"
3402 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3403 (clobber (reg:CC CC_REGNUM))])
3405 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3406 (clobber (reg:CC CC_REGNUM))])]
3408 int bitsize = INTVAL (operands[2]);
3409 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3410 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3412 operands[1] = adjust_address (operands[1], BLKmode, 0);
3413 set_mem_size (operands[1], size);
3414 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3415 operands[3] = GEN_INT (mask);
3419 ; insv instruction patterns
3422 (define_expand "insv"
3423 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3424 (match_operand 1 "const_int_operand" "")
3425 (match_operand 2 "const_int_operand" ""))
3426 (match_operand 3 "general_operand" ""))]
3429 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3435 ; The normal RTL expansion will never generate a zero_extract where
3436 ; the location operand isn't word mode. However, we do this in the
3437 ; back-end when generating atomic operations. See s390_two_part_insv.
3438 (define_insn "*insv<mode>_zEC12"
3439 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3440 (match_operand 1 "const_int_operand" "I") ; size
3441 (match_operand 2 "const_int_operand" "I")) ; pos
3442 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3444 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3445 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3446 [(set_attr "op_type" "RIE")])
3448 (define_insn "*insv<mode>_z10"
3449 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3450 (match_operand 1 "const_int_operand" "I") ; size
3451 (match_operand 2 "const_int_operand" "I")) ; pos
3452 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3453 (clobber (reg:CC CC_REGNUM))]
3455 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3456 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3457 [(set_attr "op_type" "RIE")
3458 (set_attr "z10prop" "z10_super_E1")])
3460 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3461 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3462 (define_insn "*insv<mode>_zEC12_noshift"
3463 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3464 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3465 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3466 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3467 (match_operand:GPR 4 "const_int_operand" ""))))]
3468 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3469 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3470 [(set_attr "op_type" "RIE")])
3472 (define_insn "*insv<mode>_z10_noshift"
3473 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3474 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3475 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3476 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3477 (match_operand:GPR 4 "const_int_operand" ""))))
3478 (clobber (reg:CC CC_REGNUM))]
3479 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3480 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3481 [(set_attr "op_type" "RIE")
3482 (set_attr "z10prop" "z10_super_E1")])
3484 (define_insn "*r<noxa>sbg_<mode>_noshift"
3485 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3487 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3488 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3489 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3490 (clobber (reg:CC CC_REGNUM))]
3492 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3493 [(set_attr "op_type" "RIE")])
3495 (define_insn "*r<noxa>sbg_di_rotl"
3496 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3500 (match_operand:DI 1 "nonimmediate_operand" "d")
3501 (match_operand:DI 3 "const_int_operand" ""))
3502 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3503 (match_operand:DI 4 "nonimmediate_operand" "0")))
3504 (clobber (reg:CC CC_REGNUM))]
3506 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3507 [(set_attr "op_type" "RIE")])
3509 (define_insn "*r<noxa>sbg_<mode>_srl"
3510 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3514 (match_operand:GPR 1 "nonimmediate_operand" "d")
3515 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3516 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3517 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3518 (clobber (reg:CC CC_REGNUM))]
3520 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3521 INTVAL (operands[2]))"
3522 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3523 [(set_attr "op_type" "RIE")])
3525 (define_insn "*r<noxa>sbg_<mode>_sll"
3526 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3530 (match_operand:GPR 1 "nonimmediate_operand" "d")
3531 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3532 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3533 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3534 (clobber (reg:CC CC_REGNUM))]
3536 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3537 INTVAL (operands[2]))"
3538 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3539 [(set_attr "op_type" "RIE")])
3541 ;; These two are generated by combine for s.bf &= val.
3542 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3543 ;; shifts and ands, which results in some truly awful patterns
3544 ;; including subregs of operations. Rather unnecessisarily, IMO.
3547 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3548 ;; (const_int 24 [0x18])
3549 ;; (const_int 0 [0]))
3550 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3551 ;; (const_int 40 [0x28])) 4)
3552 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3554 ;; we should instead generate
3556 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3557 ;; (const_int 24 [0x18])
3558 ;; (const_int 0 [0]))
3559 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3560 ;; (const_int 40 [0x28]))
3561 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3563 ;; by noticing that we can push down the outer paradoxical subreg
3564 ;; into the operation.
3566 (define_insn "*insv_rnsbg_noshift"
3567 [(set (zero_extract:DI
3568 (match_operand:DI 0 "nonimmediate_operand" "+d")
3569 (match_operand 1 "const_int_operand" "")
3570 (match_operand 2 "const_int_operand" ""))
3573 (match_operand:DI 3 "nonimmediate_operand" "d")))
3574 (clobber (reg:CC CC_REGNUM))]
3576 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3577 "rnsbg\t%0,%3,%2,63,0"
3578 [(set_attr "op_type" "RIE")])
3580 (define_insn "*insv_rnsbg_srl"
3581 [(set (zero_extract:DI
3582 (match_operand:DI 0 "nonimmediate_operand" "+d")
3583 (match_operand 1 "const_int_operand" "")
3584 (match_operand 2 "const_int_operand" ""))
3588 (match_operand 3 "const_int_operand" ""))
3589 (match_operand:DI 4 "nonimmediate_operand" "d")))
3590 (clobber (reg:CC CC_REGNUM))]
3592 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3593 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3594 [(set_attr "op_type" "RIE")])
3596 (define_insn "*insv<mode>_mem_reg"
3597 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3598 (match_operand 1 "const_int_operand" "n,n")
3600 (match_operand:W 2 "register_operand" "d,d"))]
3601 "INTVAL (operands[1]) > 0
3602 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3603 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3605 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3607 operands[1] = GEN_INT ((1ul << size) - 1);
3608 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3609 : "stcmy\t%2,%1,%S0";
3611 [(set_attr "op_type" "RS,RSY")
3612 (set_attr "z10prop" "z10_super,z10_super")])
3614 (define_insn "*insvdi_mem_reghigh"
3615 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3616 (match_operand 1 "const_int_operand" "n")
3618 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3621 && INTVAL (operands[1]) > 0
3622 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3623 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3625 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3627 operands[1] = GEN_INT ((1ul << size) - 1);
3628 return "stcmh\t%2,%1,%S0";
3630 [(set_attr "op_type" "RSY")
3631 (set_attr "z10prop" "z10_super")])
3633 (define_insn "*insvdi_reg_imm"
3634 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3636 (match_operand 1 "const_int_operand" "n"))
3637 (match_operand:DI 2 "const_int_operand" "n"))]
3639 && INTVAL (operands[1]) >= 0
3640 && INTVAL (operands[1]) < BITS_PER_WORD
3641 && INTVAL (operands[1]) % 16 == 0"
3643 switch (BITS_PER_WORD - INTVAL (operands[1]))
3645 case 64: return "iihh\t%0,%x2"; break;
3646 case 48: return "iihl\t%0,%x2"; break;
3647 case 32: return "iilh\t%0,%x2"; break;
3648 case 16: return "iill\t%0,%x2"; break;
3649 default: gcc_unreachable();
3652 [(set_attr "op_type" "RI")
3653 (set_attr "z10prop" "z10_super_E1")])
3655 ; Update the left-most 32 bit of a DI.
3656 (define_insn "*insv_h_di_reg_extimm"
3657 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3660 (match_operand:DI 1 "const_int_operand" "n"))]
3663 [(set_attr "op_type" "RIL")
3664 (set_attr "z10prop" "z10_fwd_E1")])
3666 ; Update the right-most 32 bit of a DI.
3667 (define_insn "*insv_l_di_reg_extimm"
3668 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3671 (match_operand:DI 1 "const_int_operand" "n"))]
3674 [(set_attr "op_type" "RIL")
3675 (set_attr "z10prop" "z10_fwd_A1")])
3678 ; extendsidi2 instruction pattern(s).
3681 (define_expand "extendsidi2"
3682 [(set (match_operand:DI 0 "register_operand" "")
3683 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3688 emit_clobber (operands[0]);
3689 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3690 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3691 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3696 (define_insn "*extendsidi2"
3697 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3698 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3704 [(set_attr "op_type" "RRE,RXY,RIL")
3705 (set_attr "type" "*,*,larl")
3706 (set_attr "cpu_facility" "*,*,z10")
3707 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3710 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3713 (define_expand "extend<HQI:mode><DSI:mode>2"
3714 [(set (match_operand:DSI 0 "register_operand" "")
3715 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3718 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3720 rtx tmp = gen_reg_rtx (SImode);
3721 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3722 emit_insn (gen_extendsidi2 (operands[0], tmp));
3725 else if (!TARGET_EXTIMM)
3727 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3729 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3730 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3731 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3737 ; extendhidi2 instruction pattern(s).
3740 (define_insn "*extendhidi2_extimm"
3741 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3742 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3743 "TARGET_ZARCH && TARGET_EXTIMM"
3748 [(set_attr "op_type" "RRE,RXY,RIL")
3749 (set_attr "type" "*,*,larl")
3750 (set_attr "cpu_facility" "extimm,extimm,z10")
3751 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3753 (define_insn "*extendhidi2"
3754 [(set (match_operand:DI 0 "register_operand" "=d")
3755 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3758 [(set_attr "op_type" "RXY")
3759 (set_attr "z10prop" "z10_super_E1")])
3762 ; extendhisi2 instruction pattern(s).
3765 (define_insn "*extendhisi2_extimm"
3766 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3767 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3774 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3775 (set_attr "type" "*,*,*,larl")
3776 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3777 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3779 (define_insn "*extendhisi2"
3780 [(set (match_operand:SI 0 "register_operand" "=d,d")
3781 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3786 [(set_attr "op_type" "RX,RXY")
3787 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3790 ; extendqi(si|di)2 instruction pattern(s).
3793 ; lbr, lgbr, lb, lgb
3794 (define_insn "*extendqi<mode>2_extimm"
3795 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3796 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3801 [(set_attr "op_type" "RRE,RXY")
3802 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3805 (define_insn "*extendqi<mode>2"
3806 [(set (match_operand:GPR 0 "register_operand" "=d")
3807 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3808 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3810 [(set_attr "op_type" "RXY")
3811 (set_attr "z10prop" "z10_super_E1")])
3813 (define_insn_and_split "*extendqi<mode>2_short_displ"
3814 [(set (match_operand:GPR 0 "register_operand" "=d")
3815 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3816 (clobber (reg:CC CC_REGNUM))]
3817 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3819 "&& reload_completed"
3821 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3822 (clobber (reg:CC CC_REGNUM))])
3824 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3825 (clobber (reg:CC CC_REGNUM))])]
3827 operands[1] = adjust_address (operands[1], BLKmode, 0);
3828 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3829 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3833 ; zero_extendsidi2 instruction pattern(s).
3836 (define_expand "zero_extendsidi2"
3837 [(set (match_operand:DI 0 "register_operand" "")
3838 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3843 emit_clobber (operands[0]);
3844 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3845 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3850 (define_insn "*zero_extendsidi2"
3851 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3852 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3858 [(set_attr "op_type" "RRE,RXY,RIL")
3859 (set_attr "type" "*,*,larl")
3860 (set_attr "cpu_facility" "*,*,z10")
3861 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3864 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3867 (define_insn "*llgt_sidi"
3868 [(set (match_operand:DI 0 "register_operand" "=d")
3869 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3870 (const_int 2147483647)))]
3873 [(set_attr "op_type" "RXE")
3874 (set_attr "z10prop" "z10_super_E1")])
3876 (define_insn_and_split "*llgt_sidi_split"
3877 [(set (match_operand:DI 0 "register_operand" "=d")
3878 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3879 (const_int 2147483647)))
3880 (clobber (reg:CC CC_REGNUM))]
3883 "&& reload_completed"
3885 (and:DI (subreg:DI (match_dup 1) 0)
3886 (const_int 2147483647)))]
3889 (define_insn "*llgt_sisi"
3890 [(set (match_operand:SI 0 "register_operand" "=d,d")
3891 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3892 (const_int 2147483647)))]
3897 [(set_attr "op_type" "RRE,RXE")
3898 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3900 (define_insn "*llgt_didi"
3901 [(set (match_operand:DI 0 "register_operand" "=d,d")
3902 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3903 (const_int 2147483647)))]
3908 [(set_attr "op_type" "RRE,RXE")
3909 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3912 [(set (match_operand:DSI 0 "register_operand" "")
3913 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3914 (const_int 2147483647)))
3915 (clobber (reg:CC CC_REGNUM))]
3916 "TARGET_ZARCH && reload_completed"
3918 (and:DSI (match_dup 1)
3919 (const_int 2147483647)))]
3923 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3926 (define_expand "zero_extend<mode>di2"
3927 [(set (match_operand:DI 0 "register_operand" "")
3928 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3933 rtx tmp = gen_reg_rtx (SImode);
3934 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3935 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3938 else if (!TARGET_EXTIMM)
3940 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
3941 operands[1] = gen_lowpart (DImode, operands[1]);
3942 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3943 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3948 (define_expand "zero_extend<mode>si2"
3949 [(set (match_operand:SI 0 "register_operand" "")
3950 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3955 operands[1] = gen_lowpart (SImode, operands[1]);
3956 emit_insn (gen_andsi3 (operands[0], operands[1],
3957 GEN_INT ((1 << <HQI:bitsize>) - 1)));
3963 (define_insn "*zero_extendhi<mode>2_z10"
3964 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3965 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3971 [(set_attr "op_type" "RXY,RRE,RIL")
3972 (set_attr "type" "*,*,larl")
3973 (set_attr "cpu_facility" "*,*,z10")
3974 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3976 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3977 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3978 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3979 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3984 [(set_attr "op_type" "RRE,RXY")
3985 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3988 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3989 [(set (match_operand:GPR 0 "register_operand" "=d")
3990 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3991 "TARGET_ZARCH && !TARGET_EXTIMM"
3993 [(set_attr "op_type" "RXY")
3994 (set_attr "z10prop" "z10_fwd_A3")])
3996 (define_insn_and_split "*zero_extendhisi2_31"
3997 [(set (match_operand:SI 0 "register_operand" "=&d")
3998 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3999 (clobber (reg:CC CC_REGNUM))]
4002 "&& reload_completed"
4003 [(set (match_dup 0) (const_int 0))
4005 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4006 (clobber (reg:CC CC_REGNUM))])]
4007 "operands[2] = gen_lowpart (HImode, operands[0]);")
4009 (define_insn_and_split "*zero_extendqisi2_31"
4010 [(set (match_operand:SI 0 "register_operand" "=&d")
4011 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4014 "&& reload_completed"
4015 [(set (match_dup 0) (const_int 0))
4016 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4017 "operands[2] = gen_lowpart (QImode, operands[0]);")
4020 ; zero_extendqihi2 instruction pattern(s).
4023 (define_expand "zero_extendqihi2"
4024 [(set (match_operand:HI 0 "register_operand" "")
4025 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4026 "TARGET_ZARCH && !TARGET_EXTIMM"
4028 operands[1] = gen_lowpart (HImode, operands[1]);
4029 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4033 (define_insn "*zero_extendqihi2_64"
4034 [(set (match_operand:HI 0 "register_operand" "=d")
4035 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4036 "TARGET_ZARCH && !TARGET_EXTIMM"
4038 [(set_attr "op_type" "RXY")
4039 (set_attr "z10prop" "z10_fwd_A3")])
4041 (define_insn_and_split "*zero_extendqihi2_31"
4042 [(set (match_operand:HI 0 "register_operand" "=&d")
4043 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4046 "&& reload_completed"
4047 [(set (match_dup 0) (const_int 0))
4048 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4049 "operands[2] = gen_lowpart (QImode, operands[0]);")
4052 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4055 (define_expand "fixuns_truncdddi2"
4057 [(set (match_operand:DI 0 "register_operand" "")
4058 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4059 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4060 (clobber (reg:CC CC_REGNUM))])]
4066 rtx label1 = gen_label_rtx ();
4067 rtx label2 = gen_label_rtx ();
4068 rtx temp = gen_reg_rtx (TDmode);
4069 REAL_VALUE_TYPE cmp, sub;
4071 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4072 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4074 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4075 solution is doing the check and the subtraction in TD mode and using a
4076 TD -> DI convert afterwards. */
4077 emit_insn (gen_extendddtd2 (temp, operands[1]));
4078 temp = force_reg (TDmode, temp);
4079 emit_cmp_and_jump_insns (temp,
4080 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4081 LT, NULL_RTX, VOIDmode, 0, label1);
4082 emit_insn (gen_subtd3 (temp, temp,
4083 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4084 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4087 emit_label (label1);
4088 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4089 emit_label (label2);
4094 (define_expand "fixuns_trunctddi2"
4096 [(set (match_operand:DI 0 "register_operand" "")
4097 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4098 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4099 (clobber (reg:CC CC_REGNUM))])]
4105 rtx label1 = gen_label_rtx ();
4106 rtx label2 = gen_label_rtx ();
4107 rtx temp = gen_reg_rtx (TDmode);
4108 REAL_VALUE_TYPE cmp, sub;
4110 operands[1] = force_reg (TDmode, operands[1]);
4111 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4112 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4114 emit_cmp_and_jump_insns (operands[1],
4115 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4116 LT, NULL_RTX, VOIDmode, 0, label1);
4117 emit_insn (gen_subtd3 (temp, operands[1],
4118 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4119 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4122 emit_label (label1);
4123 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4124 emit_label (label2);
4130 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4131 ; instruction pattern(s).
4134 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4136 [(set (match_operand:GPR 0 "register_operand" "")
4137 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4138 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4139 (clobber (reg:CC CC_REGNUM))])]
4144 rtx label1 = gen_label_rtx ();
4145 rtx label2 = gen_label_rtx ();
4146 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4147 REAL_VALUE_TYPE cmp, sub;
4149 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4150 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4151 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4153 emit_cmp_and_jump_insns (operands[1],
4154 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4155 LT, NULL_RTX, VOIDmode, 0, label1);
4156 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4157 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4158 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4162 emit_label (label1);
4163 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4164 operands[1], GEN_INT (5)));
4165 emit_label (label2);
4170 ; fixuns_trunc(td|dd)si2 expander
4171 (define_expand "fixuns_trunc<mode>si2"
4173 [(set (match_operand:SI 0 "register_operand" "")
4174 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4175 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4176 (clobber (reg:CC CC_REGNUM))])]
4177 "TARGET_Z196 && TARGET_HARD_DFP"
4180 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4182 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4183 ; clfdtr, clfxtr, clgdtr, clgxtr
4184 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4185 [(set (match_operand:GPR 0 "register_operand" "=r")
4186 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4187 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4188 (clobber (reg:CC CC_REGNUM))]
4190 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4191 [(set_attr "op_type" "RRF")
4192 (set_attr "type" "ftoi")])
4194 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4195 [(set (match_operand:GPR 0 "register_operand" "")
4196 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4199 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4204 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4205 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4206 [(set (match_operand:GPR 0 "register_operand" "=d")
4207 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4208 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4209 (clobber (reg:CC CC_REGNUM))]
4211 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4212 [(set_attr "op_type" "RRE")
4213 (set_attr "type" "ftoi")])
4217 ; fix_trunc(td|dd)di2 instruction pattern(s).
4220 (define_expand "fix_trunc<mode>di2"
4221 [(set (match_operand:DI 0 "register_operand" "")
4222 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4223 "TARGET_ZARCH && TARGET_HARD_DFP"
4225 operands[1] = force_reg (<MODE>mode, operands[1]);
4226 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4232 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4233 [(set (match_operand:DI 0 "register_operand" "=d")
4234 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4235 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4236 (clobber (reg:CC CC_REGNUM))]
4237 "TARGET_ZARCH && TARGET_HARD_DFP"
4238 "cg<DFP:xde>tr\t%0,%h2,%1"
4239 [(set_attr "op_type" "RRF")
4240 (set_attr "type" "ftoidfp")])
4244 ; fix_trunctf(si|di)2 instruction pattern(s).
4247 (define_expand "fix_trunctf<mode>2"
4248 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4249 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4250 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4251 (clobber (reg:CC CC_REGNUM))])]
4257 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4260 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4261 (define_insn "floatdi<mode>2"
4262 [(set (match_operand:FP 0 "register_operand" "=f")
4263 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4264 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4265 "c<xde>g<bt>r\t%0,%1"
4266 [(set_attr "op_type" "RRE")
4267 (set_attr "type" "itof<mode>" )])
4269 ; cxfbr, cdfbr, cefbr
4270 (define_insn "floatsi<mode>2"
4271 [(set (match_operand:BFP 0 "register_operand" "=f")
4272 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4275 [(set_attr "op_type" "RRE")
4276 (set_attr "type" "itof<mode>" )])
4279 (define_insn "floatsi<mode>2"
4280 [(set (match_operand:DFP 0 "register_operand" "=f")
4281 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4282 "TARGET_Z196 && TARGET_HARD_FLOAT"
4283 "c<xde>ftr\t%0,0,%1,0"
4284 [(set_attr "op_type" "RRE")
4285 (set_attr "type" "itof<mode>" )])
4288 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4291 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4292 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4293 (define_insn "floatuns<GPR:mode><FP:mode>2"
4294 [(set (match_operand:FP 0 "register_operand" "=f")
4295 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4296 "TARGET_Z196 && TARGET_HARD_FLOAT"
4297 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4298 [(set_attr "op_type" "RRE")
4299 (set_attr "type" "itof<FP:mode>" )])
4302 ; truncdfsf2 instruction pattern(s).
4305 (define_insn "truncdfsf2"
4306 [(set (match_operand:SF 0 "register_operand" "=f")
4307 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4310 [(set_attr "op_type" "RRE")
4311 (set_attr "type" "ftruncdf")])
4314 ; trunctf(df|sf)2 instruction pattern(s).
4318 (define_insn "trunctf<mode>2"
4319 [(set (match_operand:DSF 0 "register_operand" "=f")
4320 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4321 (clobber (match_scratch:TF 2 "=f"))]
4323 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4324 [(set_attr "length" "6")
4325 (set_attr "type" "ftrunctf")])
4328 ; trunctddd2 and truncddsd2 instruction pattern(s).
4331 (define_insn "trunctddd2"
4332 [(set (match_operand:DD 0 "register_operand" "=f")
4333 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4334 (clobber (match_scratch:TD 2 "=f"))]
4336 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4337 [(set_attr "length" "6")
4338 (set_attr "type" "ftruncdd")])
4340 (define_insn "truncddsd2"
4341 [(set (match_operand:SD 0 "register_operand" "=f")
4342 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4345 [(set_attr "op_type" "RRF")
4346 (set_attr "type" "ftruncsd")])
4349 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4352 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4353 (define_insn "extend<DSF:mode><BFP:mode>2"
4354 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4355 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4357 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4359 l<BFP:xde><DSF:xde>br\t%0,%1
4360 l<BFP:xde><DSF:xde>b\t%0,%1"
4361 [(set_attr "op_type" "RRE,RXE")
4362 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4365 ; extendddtd2 and extendsddd2 instruction pattern(s).
4368 (define_insn "extendddtd2"
4369 [(set (match_operand:TD 0 "register_operand" "=f")
4370 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4373 [(set_attr "op_type" "RRF")
4374 (set_attr "type" "fsimptf")])
4376 (define_insn "extendsddd2"
4377 [(set (match_operand:DD 0 "register_operand" "=f")
4378 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4381 [(set_attr "op_type" "RRF")
4382 (set_attr "type" "fsimptf")])
4384 ; Binary <-> Decimal floating point trunc patterns
4387 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4388 [(set (reg:DFP_ALL FPR0_REGNUM)
4389 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4390 (use (reg:SI GPR0_REGNUM))
4391 (clobber (reg:CC CC_REGNUM))]
4395 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4396 [(set (reg:BFP FPR0_REGNUM)
4397 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4398 (use (reg:SI GPR0_REGNUM))
4399 (clobber (reg:CC CC_REGNUM))]
4403 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4404 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4405 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4407 [(set (reg:DFP_ALL FPR0_REGNUM)
4408 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4409 (use (reg:SI GPR0_REGNUM))
4410 (clobber (reg:CC CC_REGNUM))])
4411 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4412 (reg:DFP_ALL FPR0_REGNUM))]
4414 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4416 HOST_WIDE_INT flags;
4418 flags = (PFPO_CONVERT |
4419 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4420 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4422 operands[2] = GEN_INT (flags);
4425 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4426 [(set (reg:DFP_ALL FPR2_REGNUM)
4427 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4428 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4430 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4431 (use (reg:SI GPR0_REGNUM))
4432 (clobber (reg:CC CC_REGNUM))])
4433 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4435 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4437 HOST_WIDE_INT flags;
4439 flags = (PFPO_CONVERT |
4440 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4441 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4443 operands[2] = GEN_INT (flags);
4447 ; Binary <-> Decimal floating point extend patterns
4450 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4451 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4452 (use (reg:SI GPR0_REGNUM))
4453 (clobber (reg:CC CC_REGNUM))]
4457 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4458 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4459 (use (reg:SI GPR0_REGNUM))
4460 (clobber (reg:CC CC_REGNUM))]
4464 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4465 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4466 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4468 [(set (reg:DFP_ALL FPR0_REGNUM)
4469 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4470 (use (reg:SI GPR0_REGNUM))
4471 (clobber (reg:CC CC_REGNUM))])
4472 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4473 (reg:DFP_ALL FPR0_REGNUM))]
4475 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4477 HOST_WIDE_INT flags;
4479 flags = (PFPO_CONVERT |
4480 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4481 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4483 operands[2] = GEN_INT (flags);
4486 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4487 [(set (reg:DFP_ALL FPR2_REGNUM)
4488 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4489 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4491 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4492 (use (reg:SI GPR0_REGNUM))
4493 (clobber (reg:CC CC_REGNUM))])
4494 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4496 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4498 HOST_WIDE_INT flags;
4500 flags = (PFPO_CONVERT |
4501 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4502 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4504 operands[2] = GEN_INT (flags);
4509 ;; ARITHMETIC OPERATIONS
4511 ; arithmetic operations set the ConditionCode,
4512 ; because of unpredictable Bits in Register for Halfword and Byte
4513 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4516 ;;- Add instructions.
4520 ; addti3 instruction pattern(s).
4523 (define_insn_and_split "addti3"
4524 [(set (match_operand:TI 0 "register_operand" "=&d")
4525 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4526 (match_operand:TI 2 "general_operand" "do") ) )
4527 (clobber (reg:CC CC_REGNUM))]
4530 "&& reload_completed"
4532 [(set (reg:CCL1 CC_REGNUM)
4533 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4535 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4537 [(set (match_dup 3) (plus:DI
4538 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4539 (match_dup 4)) (match_dup 5)))
4540 (clobber (reg:CC CC_REGNUM))])]
4541 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4542 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4543 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4544 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4545 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4546 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4549 ; adddi3 instruction pattern(s).
4552 (define_expand "adddi3"
4554 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4555 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4556 (match_operand:DI 2 "general_operand" "")))
4557 (clobber (reg:CC CC_REGNUM))])]
4561 (define_insn "*adddi3_sign"
4562 [(set (match_operand:DI 0 "register_operand" "=d,d")
4563 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4564 (match_operand:DI 1 "register_operand" "0,0")))
4565 (clobber (reg:CC CC_REGNUM))]
4570 [(set_attr "op_type" "RRE,RXY")
4571 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4573 (define_insn "*adddi3_zero_cc"
4574 [(set (reg CC_REGNUM)
4575 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4576 (match_operand:DI 1 "register_operand" "0,0"))
4578 (set (match_operand:DI 0 "register_operand" "=d,d")
4579 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4580 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4584 [(set_attr "op_type" "RRE,RXY")
4585 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4587 (define_insn "*adddi3_zero_cconly"
4588 [(set (reg CC_REGNUM)
4589 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4590 (match_operand:DI 1 "register_operand" "0,0"))
4592 (clobber (match_scratch:DI 0 "=d,d"))]
4593 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4597 [(set_attr "op_type" "RRE,RXY")
4598 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4600 (define_insn "*adddi3_zero"
4601 [(set (match_operand:DI 0 "register_operand" "=d,d")
4602 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4603 (match_operand:DI 1 "register_operand" "0,0")))
4604 (clobber (reg:CC CC_REGNUM))]
4609 [(set_attr "op_type" "RRE,RXY")
4610 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4612 (define_insn_and_split "*adddi3_31z"
4613 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4614 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4615 (match_operand:DI 2 "general_operand" "do") ) )
4616 (clobber (reg:CC CC_REGNUM))]
4617 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4619 "&& reload_completed"
4621 [(set (reg:CCL1 CC_REGNUM)
4622 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4624 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4626 [(set (match_dup 3) (plus:SI
4627 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4628 (match_dup 4)) (match_dup 5)))
4629 (clobber (reg:CC CC_REGNUM))])]
4630 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4631 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4632 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4633 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4634 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4635 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4637 (define_insn_and_split "*adddi3_31"
4638 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4639 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4640 (match_operand:DI 2 "general_operand" "do") ) )
4641 (clobber (reg:CC CC_REGNUM))]
4644 "&& reload_completed"
4646 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4647 (clobber (reg:CC CC_REGNUM))])
4649 [(set (reg:CCL1 CC_REGNUM)
4650 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4652 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4654 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4656 (label_ref (match_dup 9))))
4658 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4659 (clobber (reg:CC CC_REGNUM))])
4661 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4662 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4663 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4664 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4665 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4666 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4667 operands[9] = gen_label_rtx ();")
4670 ; addsi3 instruction pattern(s).
4673 (define_expand "addsi3"
4675 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4676 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4677 (match_operand:SI 2 "general_operand" "")))
4678 (clobber (reg:CC CC_REGNUM))])]
4682 (define_insn "*addsi3_sign"
4683 [(set (match_operand:SI 0 "register_operand" "=d,d")
4684 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4685 (match_operand:SI 1 "register_operand" "0,0")))
4686 (clobber (reg:CC CC_REGNUM))]
4691 [(set_attr "op_type" "RX,RXY")
4692 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4695 ; add(di|si)3 instruction pattern(s).
4698 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4699 (define_insn "*add<mode>3"
4700 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4701 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4702 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4703 (clobber (reg:CC CC_REGNUM))]
4715 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4716 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4717 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4718 z10_super_E1,z10_super_E1,z10_super_E1")])
4720 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4721 (define_insn "*add<mode>3_carry1_cc"
4722 [(set (reg CC_REGNUM)
4723 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4724 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4726 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4727 (plus:GPR (match_dup 1) (match_dup 2)))]
4728 "s390_match_ccmode (insn, CCL1mode)"
4734 al<g>hsik\t%0,%1,%h2
4738 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4739 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4740 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4741 z10_super_E1,z10_super_E1,z10_super_E1")])
4743 ; alr, al, aly, algr, alg, alrk, algrk
4744 (define_insn "*add<mode>3_carry1_cconly"
4745 [(set (reg CC_REGNUM)
4746 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4747 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4749 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4750 "s390_match_ccmode (insn, CCL1mode)"
4756 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4757 (set_attr "cpu_facility" "*,z196,*,*")
4758 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4760 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4761 (define_insn "*add<mode>3_carry2_cc"
4762 [(set (reg CC_REGNUM)
4763 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4764 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4766 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4767 (plus:GPR (match_dup 1) (match_dup 2)))]
4768 "s390_match_ccmode (insn, CCL1mode)"
4774 al<g>hsik\t%0,%1,%h2
4778 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4779 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4780 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4781 z10_super_E1,z10_super_E1,z10_super_E1")])
4783 ; alr, al, aly, algr, alg, alrk, algrk
4784 (define_insn "*add<mode>3_carry2_cconly"
4785 [(set (reg CC_REGNUM)
4786 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4787 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4789 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4790 "s390_match_ccmode (insn, CCL1mode)"
4796 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4797 (set_attr "cpu_facility" "*,z196,*,*")
4798 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4800 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4801 (define_insn "*add<mode>3_cc"
4802 [(set (reg CC_REGNUM)
4803 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4804 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4806 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4807 (plus:GPR (match_dup 1) (match_dup 2)))]
4808 "s390_match_ccmode (insn, CCLmode)"
4814 al<g>hsik\t%0,%1,%h2
4818 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4819 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4820 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4821 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4823 ; alr, al, aly, algr, alg, alrk, algrk
4824 (define_insn "*add<mode>3_cconly"
4825 [(set (reg CC_REGNUM)
4826 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4827 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4829 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4830 "s390_match_ccmode (insn, CCLmode)"
4836 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4837 (set_attr "cpu_facility" "*,z196,*,*")
4838 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4840 ; alr, al, aly, algr, alg, alrk, algrk
4841 (define_insn "*add<mode>3_cconly2"
4842 [(set (reg CC_REGNUM)
4843 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4844 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4845 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4846 "s390_match_ccmode(insn, CCLmode)"
4852 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4853 (set_attr "cpu_facility" "*,z196,*,*")
4854 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4856 ; ahi, afi, aghi, agfi, asi, agsi
4857 (define_insn "*add<mode>3_imm_cc"
4858 [(set (reg CC_REGNUM)
4859 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4860 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4862 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4863 (plus:GPR (match_dup 1) (match_dup 2)))]
4864 "s390_match_ccmode (insn, CCAmode)
4865 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4866 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4867 /* Avoid INT32_MIN on 32 bit. */
4868 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
4874 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4875 (set_attr "cpu_facility" "*,z196,extimm,z10")
4876 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4879 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4882 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4883 (define_insn "add<mode>3"
4884 [(set (match_operand:FP 0 "register_operand" "=f, f")
4885 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4886 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4887 (clobber (reg:CC CC_REGNUM))]
4890 a<xde><bt>r\t%0,<op1>%2
4892 [(set_attr "op_type" "<RRer>,RXE")
4893 (set_attr "type" "fsimp<mode>")])
4895 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4896 (define_insn "*add<mode>3_cc"
4897 [(set (reg CC_REGNUM)
4898 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4899 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4900 (match_operand:FP 3 "const0_operand" "")))
4901 (set (match_operand:FP 0 "register_operand" "=f,f")
4902 (plus:FP (match_dup 1) (match_dup 2)))]
4903 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4905 a<xde><bt>r\t%0,<op1>%2
4907 [(set_attr "op_type" "<RRer>,RXE")
4908 (set_attr "type" "fsimp<mode>")])
4910 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4911 (define_insn "*add<mode>3_cconly"
4912 [(set (reg CC_REGNUM)
4913 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4914 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4915 (match_operand:FP 3 "const0_operand" "")))
4916 (clobber (match_scratch:FP 0 "=f,f"))]
4917 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4919 a<xde><bt>r\t%0,<op1>%2
4921 [(set_attr "op_type" "<RRer>,RXE")
4922 (set_attr "type" "fsimp<mode>")])
4926 ;;- Subtract instructions.
4930 ; subti3 instruction pattern(s).
4933 (define_insn_and_split "subti3"
4934 [(set (match_operand:TI 0 "register_operand" "=&d")
4935 (minus:TI (match_operand:TI 1 "register_operand" "0")
4936 (match_operand:TI 2 "general_operand" "do") ) )
4937 (clobber (reg:CC CC_REGNUM))]
4940 "&& reload_completed"
4942 [(set (reg:CCL2 CC_REGNUM)
4943 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4945 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4947 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4948 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4949 (clobber (reg:CC CC_REGNUM))])]
4950 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4951 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4952 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4953 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4954 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4955 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4958 ; subdi3 instruction pattern(s).
4961 (define_expand "subdi3"
4963 [(set (match_operand:DI 0 "register_operand" "")
4964 (minus:DI (match_operand:DI 1 "register_operand" "")
4965 (match_operand:DI 2 "general_operand" "")))
4966 (clobber (reg:CC CC_REGNUM))])]
4970 (define_insn "*subdi3_sign"
4971 [(set (match_operand:DI 0 "register_operand" "=d,d")
4972 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4973 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4974 (clobber (reg:CC CC_REGNUM))]
4979 [(set_attr "op_type" "RRE,RXY")
4980 (set_attr "z10prop" "z10_c,*")
4981 (set_attr "z196prop" "z196_cracked")])
4983 (define_insn "*subdi3_zero_cc"
4984 [(set (reg CC_REGNUM)
4985 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4986 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4988 (set (match_operand:DI 0 "register_operand" "=d,d")
4989 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4990 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4994 [(set_attr "op_type" "RRE,RXY")
4995 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4997 (define_insn "*subdi3_zero_cconly"
4998 [(set (reg CC_REGNUM)
4999 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5000 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5002 (clobber (match_scratch:DI 0 "=d,d"))]
5003 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5007 [(set_attr "op_type" "RRE,RXY")
5008 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5010 (define_insn "*subdi3_zero"
5011 [(set (match_operand:DI 0 "register_operand" "=d,d")
5012 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5013 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5014 (clobber (reg:CC CC_REGNUM))]
5019 [(set_attr "op_type" "RRE,RXY")
5020 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5022 (define_insn_and_split "*subdi3_31z"
5023 [(set (match_operand:DI 0 "register_operand" "=&d")
5024 (minus:DI (match_operand:DI 1 "register_operand" "0")
5025 (match_operand:DI 2 "general_operand" "do") ) )
5026 (clobber (reg:CC CC_REGNUM))]
5027 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5029 "&& reload_completed"
5031 [(set (reg:CCL2 CC_REGNUM)
5032 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5034 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5036 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5037 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5038 (clobber (reg:CC CC_REGNUM))])]
5039 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5040 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5041 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5042 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5043 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5044 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5046 (define_insn_and_split "*subdi3_31"
5047 [(set (match_operand:DI 0 "register_operand" "=&d")
5048 (minus:DI (match_operand:DI 1 "register_operand" "0")
5049 (match_operand:DI 2 "general_operand" "do") ) )
5050 (clobber (reg:CC CC_REGNUM))]
5053 "&& reload_completed"
5055 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5056 (clobber (reg:CC CC_REGNUM))])
5058 [(set (reg:CCL2 CC_REGNUM)
5059 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5061 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5063 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5065 (label_ref (match_dup 9))))
5067 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5068 (clobber (reg:CC CC_REGNUM))])
5070 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5071 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5072 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5073 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5074 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5075 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5076 operands[9] = gen_label_rtx ();")
5079 ; subsi3 instruction pattern(s).
5082 (define_expand "subsi3"
5084 [(set (match_operand:SI 0 "register_operand" "")
5085 (minus:SI (match_operand:SI 1 "register_operand" "")
5086 (match_operand:SI 2 "general_operand" "")))
5087 (clobber (reg:CC CC_REGNUM))])]
5091 (define_insn "*subsi3_sign"
5092 [(set (match_operand:SI 0 "register_operand" "=d,d")
5093 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5094 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5095 (clobber (reg:CC CC_REGNUM))]
5100 [(set_attr "op_type" "RX,RXY")
5101 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5104 ; sub(di|si)3 instruction pattern(s).
5107 ; sr, s, sy, sgr, sg, srk, sgrk
5108 (define_insn "*sub<mode>3"
5109 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5110 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5111 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5112 (clobber (reg:CC CC_REGNUM))]
5119 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5120 (set_attr "cpu_facility" "*,z196,*,*")
5121 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5123 ; slr, sl, sly, slgr, slg, slrk, slgrk
5124 (define_insn "*sub<mode>3_borrow_cc"
5125 [(set (reg CC_REGNUM)
5126 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5127 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5129 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5130 (minus:GPR (match_dup 1) (match_dup 2)))]
5131 "s390_match_ccmode (insn, CCL2mode)"
5137 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5138 (set_attr "cpu_facility" "*,z196,*,*")
5139 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5141 ; slr, sl, sly, slgr, slg, slrk, slgrk
5142 (define_insn "*sub<mode>3_borrow_cconly"
5143 [(set (reg CC_REGNUM)
5144 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5145 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5147 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5148 "s390_match_ccmode (insn, CCL2mode)"
5154 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5155 (set_attr "cpu_facility" "*,z196,*,*")
5156 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5158 ; slr, sl, sly, slgr, slg, slrk, slgrk
5159 (define_insn "*sub<mode>3_cc"
5160 [(set (reg CC_REGNUM)
5161 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5162 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5164 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5165 (minus:GPR (match_dup 1) (match_dup 2)))]
5166 "s390_match_ccmode (insn, CCLmode)"
5172 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5173 (set_attr "cpu_facility" "*,z196,*,*")
5174 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5176 ; slr, sl, sly, slgr, slg, slrk, slgrk
5177 (define_insn "*sub<mode>3_cc2"
5178 [(set (reg CC_REGNUM)
5179 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5180 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5181 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5182 (minus:GPR (match_dup 1) (match_dup 2)))]
5183 "s390_match_ccmode (insn, CCL3mode)"
5189 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5190 (set_attr "cpu_facility" "*,z196,*,*")
5191 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5193 ; slr, sl, sly, slgr, slg, slrk, slgrk
5194 (define_insn "*sub<mode>3_cconly"
5195 [(set (reg CC_REGNUM)
5196 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5197 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5199 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5200 "s390_match_ccmode (insn, CCLmode)"
5206 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5207 (set_attr "cpu_facility" "*,z196,*,*")
5208 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5211 ; slr, sl, sly, slgr, slg, slrk, slgrk
5212 (define_insn "*sub<mode>3_cconly2"
5213 [(set (reg CC_REGNUM)
5214 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5215 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5216 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5217 "s390_match_ccmode (insn, CCL3mode)"
5223 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5224 (set_attr "cpu_facility" "*,z196,*,*")
5225 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5229 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5232 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5233 (define_insn "sub<mode>3"
5234 [(set (match_operand:FP 0 "register_operand" "=f, f")
5235 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5236 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5237 (clobber (reg:CC CC_REGNUM))]
5240 s<xde><bt>r\t%0,<op1>%2
5242 [(set_attr "op_type" "<RRer>,RXE")
5243 (set_attr "type" "fsimp<mode>")])
5245 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5246 (define_insn "*sub<mode>3_cc"
5247 [(set (reg CC_REGNUM)
5248 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5249 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5250 (match_operand:FP 3 "const0_operand" "")))
5251 (set (match_operand:FP 0 "register_operand" "=f,f")
5252 (minus:FP (match_dup 1) (match_dup 2)))]
5253 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5255 s<xde><bt>r\t%0,<op1>%2
5257 [(set_attr "op_type" "<RRer>,RXE")
5258 (set_attr "type" "fsimp<mode>")])
5260 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5261 (define_insn "*sub<mode>3_cconly"
5262 [(set (reg CC_REGNUM)
5263 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5264 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5265 (match_operand:FP 3 "const0_operand" "")))
5266 (clobber (match_scratch:FP 0 "=f,f"))]
5267 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5269 s<xde><bt>r\t%0,<op1>%2
5271 [(set_attr "op_type" "<RRer>,RXE")
5272 (set_attr "type" "fsimp<mode>")])
5276 ;;- Conditional add/subtract instructions.
5280 ; add(di|si)cc instruction pattern(s).
5283 ; the following 4 patterns are used when the result of an add with
5284 ; carry is checked for an overflow condition
5286 ; op1 + op2 + c < op1
5288 ; alcr, alc, alcgr, alcg
5289 (define_insn "*add<mode>3_alc_carry1_cc"
5290 [(set (reg CC_REGNUM)
5292 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5293 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5294 (match_operand:GPR 2 "general_operand" "d,RT"))
5296 (set (match_operand:GPR 0 "register_operand" "=d,d")
5297 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5298 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5302 [(set_attr "op_type" "RRE,RXY")
5303 (set_attr "z196prop" "z196_alone,z196_alone")])
5305 ; alcr, alc, alcgr, alcg
5306 (define_insn "*add<mode>3_alc_carry1_cconly"
5307 [(set (reg CC_REGNUM)
5309 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5310 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5311 (match_operand:GPR 2 "general_operand" "d,RT"))
5313 (clobber (match_scratch:GPR 0 "=d,d"))]
5314 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5318 [(set_attr "op_type" "RRE,RXY")
5319 (set_attr "z196prop" "z196_alone,z196_alone")])
5321 ; op1 + op2 + c < op2
5323 ; alcr, alc, alcgr, alcg
5324 (define_insn "*add<mode>3_alc_carry2_cc"
5325 [(set (reg CC_REGNUM)
5327 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5328 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5329 (match_operand:GPR 2 "general_operand" "d,RT"))
5331 (set (match_operand:GPR 0 "register_operand" "=d,d")
5332 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5333 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5337 [(set_attr "op_type" "RRE,RXY")])
5339 ; alcr, alc, alcgr, alcg
5340 (define_insn "*add<mode>3_alc_carry2_cconly"
5341 [(set (reg CC_REGNUM)
5343 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5344 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5345 (match_operand:GPR 2 "general_operand" "d,RT"))
5347 (clobber (match_scratch:GPR 0 "=d,d"))]
5348 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5352 [(set_attr "op_type" "RRE,RXY")])
5354 ; alcr, alc, alcgr, alcg
5355 (define_insn "*add<mode>3_alc_cc"
5356 [(set (reg CC_REGNUM)
5358 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5359 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5360 (match_operand:GPR 2 "general_operand" "d,RT"))
5362 (set (match_operand:GPR 0 "register_operand" "=d,d")
5363 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5364 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5368 [(set_attr "op_type" "RRE,RXY")])
5370 ; alcr, alc, alcgr, alcg
5371 (define_insn "*add<mode>3_alc"
5372 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5373 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5374 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5375 (match_operand:GPR 2 "general_operand" "d,RT")))
5376 (clobber (reg:CC CC_REGNUM))]
5381 [(set_attr "op_type" "RRE,RXY")])
5383 ; slbr, slb, slbgr, slbg
5384 (define_insn "*sub<mode>3_slb_cc"
5385 [(set (reg CC_REGNUM)
5387 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5388 (match_operand:GPR 2 "general_operand" "d,RT"))
5389 (match_operand:GPR 3 "s390_slb_comparison" ""))
5391 (set (match_operand:GPR 0 "register_operand" "=d,d")
5392 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5393 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5397 [(set_attr "op_type" "RRE,RXY")
5398 (set_attr "z10prop" "z10_c,*")])
5400 ; slbr, slb, slbgr, slbg
5401 (define_insn "*sub<mode>3_slb"
5402 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5403 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5404 (match_operand:GPR 2 "general_operand" "d,RT"))
5405 (match_operand:GPR 3 "s390_slb_comparison" "")))
5406 (clobber (reg:CC CC_REGNUM))]
5411 [(set_attr "op_type" "RRE,RXY")
5412 (set_attr "z10prop" "z10_c,*")])
5414 (define_expand "add<mode>cc"
5415 [(match_operand:GPR 0 "register_operand" "")
5416 (match_operand 1 "comparison_operator" "")
5417 (match_operand:GPR 2 "register_operand" "")
5418 (match_operand:GPR 3 "const_int_operand" "")]
5420 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5421 XEXP (operands[1], 0), XEXP (operands[1], 1),
5422 operands[0], operands[2],
5423 operands[3])) FAIL; DONE;")
5426 ; scond instruction pattern(s).
5429 (define_insn_and_split "*scond<mode>"
5430 [(set (match_operand:GPR 0 "register_operand" "=&d")
5431 (match_operand:GPR 1 "s390_alc_comparison" ""))
5432 (clobber (reg:CC CC_REGNUM))]
5435 "&& reload_completed"
5436 [(set (match_dup 0) (const_int 0))
5438 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5440 (clobber (reg:CC CC_REGNUM))])]
5443 (define_insn_and_split "*scond<mode>_neg"
5444 [(set (match_operand:GPR 0 "register_operand" "=&d")
5445 (match_operand:GPR 1 "s390_slb_comparison" ""))
5446 (clobber (reg:CC CC_REGNUM))]
5449 "&& reload_completed"
5450 [(set (match_dup 0) (const_int 0))
5452 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5454 (clobber (reg:CC CC_REGNUM))])
5456 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5457 (clobber (reg:CC CC_REGNUM))])]
5461 (define_expand "cstore<mode>4"
5462 [(set (match_operand:SI 0 "register_operand" "")
5463 (match_operator:SI 1 "s390_scond_operator"
5464 [(match_operand:GPR 2 "register_operand" "")
5465 (match_operand:GPR 3 "general_operand" "")]))]
5467 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5468 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5470 (define_expand "cstorecc4"
5472 [(set (match_operand:SI 0 "register_operand" "")
5473 (match_operator:SI 1 "s390_eqne_operator"
5474 [(match_operand:CCZ1 2 "register_operand")
5475 (match_operand 3 "const0_operand")]))
5476 (clobber (reg:CC CC_REGNUM))])]
5478 "emit_insn (gen_sne (operands[0], operands[2]));
5479 if (GET_CODE (operands[1]) == EQ)
5480 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5483 (define_insn_and_split "sne"
5484 [(set (match_operand:SI 0 "register_operand" "=d")
5485 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5487 (clobber (reg:CC CC_REGNUM))]
5492 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5493 (clobber (reg:CC CC_REGNUM))])])
5497 ;; - Conditional move instructions (introduced with z196)
5500 (define_expand "mov<mode>cc"
5501 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5502 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5503 (match_operand:GPR 2 "nonimmediate_operand" "")
5504 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5506 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5507 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5509 ; locr, loc, stoc, locgr, locg, stocg
5510 (define_insn_and_split "*mov<mode>cc"
5511 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5513 (match_operator 1 "s390_comparison"
5514 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5516 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5517 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5527 "&& reload_completed
5528 && MEM_P (operands[3]) && MEM_P (operands[4])"
5531 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5536 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5540 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5543 ;;- Multiply instructions.
5547 ; muldi3 instruction pattern(s).
5550 (define_insn "*muldi3_sign"
5551 [(set (match_operand:DI 0 "register_operand" "=d,d")
5552 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5553 (match_operand:DI 1 "register_operand" "0,0")))]
5558 [(set_attr "op_type" "RRE,RXY")
5559 (set_attr "type" "imuldi")])
5561 (define_insn "muldi3"
5562 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5563 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5564 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5571 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5572 (set_attr "type" "imuldi")
5573 (set_attr "cpu_facility" "*,*,*,z10")])
5576 ; mulsi3 instruction pattern(s).
5579 (define_insn "*mulsi3_sign"
5580 [(set (match_operand:SI 0 "register_operand" "=d,d")
5581 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5582 (match_operand:SI 1 "register_operand" "0,0")))]
5587 [(set_attr "op_type" "RX,RXY")
5588 (set_attr "type" "imulhi")
5589 (set_attr "cpu_facility" "*,z10")])
5591 (define_insn "mulsi3"
5592 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5593 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5594 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5602 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5603 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5604 (set_attr "cpu_facility" "*,*,*,*,z10")])
5607 ; mulsidi3 instruction pattern(s).
5610 (define_insn "mulsidi3"
5611 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5612 (mult:DI (sign_extend:DI
5613 (match_operand:SI 1 "register_operand" "%0,0,0"))
5615 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5621 [(set_attr "op_type" "RR,RX,RXY")
5622 (set_attr "type" "imulsi")
5623 (set_attr "cpu_facility" "*,*,z10")])
5626 ; umul instruction pattern(s).
5629 ; mlr, ml, mlgr, mlg
5630 (define_insn "umul<dwh><mode>3"
5631 [(set (match_operand:DW 0 "register_operand" "=d, d")
5632 (mult:DW (zero_extend:DW
5633 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5635 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5640 [(set_attr "op_type" "RRE,RXY")
5641 (set_attr "type" "imul<dwh>")])
5644 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5647 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5648 (define_insn "mul<mode>3"
5649 [(set (match_operand:FP 0 "register_operand" "=f,f")
5650 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5651 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5654 m<xdee><bt>r\t%0,<op1>%2
5656 [(set_attr "op_type" "<RRer>,RXE")
5657 (set_attr "type" "fmul<mode>")])
5659 ; madbr, maebr, maxb, madb, maeb
5660 (define_insn "fma<mode>4"
5661 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5662 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5663 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5664 (match_operand:DSF 3 "register_operand" "0,0")))]
5669 [(set_attr "op_type" "RRE,RXE")
5670 (set_attr "type" "fmadd<mode>")])
5672 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5673 (define_insn "fms<mode>4"
5674 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5675 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5676 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5677 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5682 [(set_attr "op_type" "RRE,RXE")
5683 (set_attr "type" "fmadd<mode>")])
5686 ;;- Divide and modulo instructions.
5690 ; divmoddi4 instruction pattern(s).
5693 (define_expand "divmoddi4"
5694 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5695 (div:DI (match_operand:DI 1 "register_operand" "")
5696 (match_operand:DI 2 "general_operand" "")))
5697 (set (match_operand:DI 3 "general_operand" "")
5698 (mod:DI (match_dup 1) (match_dup 2)))])
5699 (clobber (match_dup 4))]
5702 rtx insn, div_equal, mod_equal;
5704 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5705 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5707 operands[4] = gen_reg_rtx(TImode);
5708 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5710 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5711 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5713 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5714 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5719 (define_insn "divmodtidi3"
5720 [(set (match_operand:TI 0 "register_operand" "=d,d")
5724 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5725 (match_operand:DI 2 "general_operand" "d,RT")))
5727 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5732 [(set_attr "op_type" "RRE,RXY")
5733 (set_attr "type" "idiv")])
5735 (define_insn "divmodtisi3"
5736 [(set (match_operand:TI 0 "register_operand" "=d,d")
5740 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5742 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5745 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5750 [(set_attr "op_type" "RRE,RXY")
5751 (set_attr "type" "idiv")])
5754 ; udivmoddi4 instruction pattern(s).
5757 (define_expand "udivmoddi4"
5758 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5759 (udiv:DI (match_operand:DI 1 "general_operand" "")
5760 (match_operand:DI 2 "nonimmediate_operand" "")))
5761 (set (match_operand:DI 3 "general_operand" "")
5762 (umod:DI (match_dup 1) (match_dup 2)))])
5763 (clobber (match_dup 4))]
5766 rtx insn, div_equal, mod_equal, equal;
5768 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5769 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5770 equal = gen_rtx_IOR (TImode,
5771 gen_rtx_ASHIFT (TImode,
5772 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5774 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5776 operands[4] = gen_reg_rtx(TImode);
5777 emit_clobber (operands[4]);
5778 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5779 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5781 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5782 set_unique_reg_note (insn, REG_EQUAL, equal);
5784 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5785 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5787 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5788 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5793 (define_insn "udivmodtidi3"
5794 [(set (match_operand:TI 0 "register_operand" "=d,d")
5799 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5801 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5805 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5810 [(set_attr "op_type" "RRE,RXY")
5811 (set_attr "type" "idiv")])
5814 ; divmodsi4 instruction pattern(s).
5817 (define_expand "divmodsi4"
5818 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5819 (div:SI (match_operand:SI 1 "general_operand" "")
5820 (match_operand:SI 2 "nonimmediate_operand" "")))
5821 (set (match_operand:SI 3 "general_operand" "")
5822 (mod:SI (match_dup 1) (match_dup 2)))])
5823 (clobber (match_dup 4))]
5826 rtx insn, div_equal, mod_equal, equal;
5828 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5829 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5830 equal = gen_rtx_IOR (DImode,
5831 gen_rtx_ASHIFT (DImode,
5832 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5834 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5836 operands[4] = gen_reg_rtx(DImode);
5837 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5839 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5840 set_unique_reg_note (insn, REG_EQUAL, equal);
5842 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5843 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5845 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5846 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5851 (define_insn "divmoddisi3"
5852 [(set (match_operand:DI 0 "register_operand" "=d,d")
5857 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5859 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5863 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5868 [(set_attr "op_type" "RR,RX")
5869 (set_attr "type" "idiv")])
5872 ; udivsi3 and umodsi3 instruction pattern(s).
5875 (define_expand "udivmodsi4"
5876 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5877 (udiv:SI (match_operand:SI 1 "general_operand" "")
5878 (match_operand:SI 2 "nonimmediate_operand" "")))
5879 (set (match_operand:SI 3 "general_operand" "")
5880 (umod:SI (match_dup 1) (match_dup 2)))])
5881 (clobber (match_dup 4))]
5882 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5884 rtx insn, div_equal, mod_equal, equal;
5886 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5887 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5888 equal = gen_rtx_IOR (DImode,
5889 gen_rtx_ASHIFT (DImode,
5890 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5892 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5894 operands[4] = gen_reg_rtx(DImode);
5895 emit_clobber (operands[4]);
5896 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5897 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5899 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5900 set_unique_reg_note (insn, REG_EQUAL, equal);
5902 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5903 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5905 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5906 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5911 (define_insn "udivmoddisi3"
5912 [(set (match_operand:DI 0 "register_operand" "=d,d")
5917 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5919 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5923 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5924 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5928 [(set_attr "op_type" "RRE,RXY")
5929 (set_attr "type" "idiv")])
5931 (define_expand "udivsi3"
5932 [(set (match_operand:SI 0 "register_operand" "=d")
5933 (udiv:SI (match_operand:SI 1 "general_operand" "")
5934 (match_operand:SI 2 "general_operand" "")))
5935 (clobber (match_dup 3))]
5936 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5938 rtx insn, udiv_equal, umod_equal, equal;
5940 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5941 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5942 equal = gen_rtx_IOR (DImode,
5943 gen_rtx_ASHIFT (DImode,
5944 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5946 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5948 operands[3] = gen_reg_rtx (DImode);
5950 if (CONSTANT_P (operands[2]))
5952 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5954 rtx label1 = gen_label_rtx ();
5956 operands[1] = make_safe_from (operands[1], operands[0]);
5957 emit_move_insn (operands[0], const0_rtx);
5958 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5960 emit_move_insn (operands[0], const1_rtx);
5961 emit_label (label1);
5965 operands[2] = force_reg (SImode, operands[2]);
5966 operands[2] = make_safe_from (operands[2], operands[0]);
5968 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5969 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5971 set_unique_reg_note (insn, REG_EQUAL, equal);
5973 insn = emit_move_insn (operands[0],
5974 gen_lowpart (SImode, operands[3]));
5975 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5980 rtx label1 = gen_label_rtx ();
5981 rtx label2 = gen_label_rtx ();
5982 rtx label3 = gen_label_rtx ();
5984 operands[1] = force_reg (SImode, operands[1]);
5985 operands[1] = make_safe_from (operands[1], operands[0]);
5986 operands[2] = force_reg (SImode, operands[2]);
5987 operands[2] = make_safe_from (operands[2], operands[0]);
5989 emit_move_insn (operands[0], const0_rtx);
5990 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5992 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5994 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5996 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5997 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5999 set_unique_reg_note (insn, REG_EQUAL, equal);
6001 insn = emit_move_insn (operands[0],
6002 gen_lowpart (SImode, operands[3]));
6003 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6006 emit_label (label1);
6007 emit_move_insn (operands[0], operands[1]);
6009 emit_label (label2);
6010 emit_move_insn (operands[0], const1_rtx);
6011 emit_label (label3);
6013 emit_move_insn (operands[0], operands[0]);
6017 (define_expand "umodsi3"
6018 [(set (match_operand:SI 0 "register_operand" "=d")
6019 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6020 (match_operand:SI 2 "nonimmediate_operand" "")))
6021 (clobber (match_dup 3))]
6022 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6024 rtx insn, udiv_equal, umod_equal, equal;
6026 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6027 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6028 equal = gen_rtx_IOR (DImode,
6029 gen_rtx_ASHIFT (DImode,
6030 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6032 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6034 operands[3] = gen_reg_rtx (DImode);
6036 if (CONSTANT_P (operands[2]))
6038 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6040 rtx label1 = gen_label_rtx ();
6042 operands[1] = make_safe_from (operands[1], operands[0]);
6043 emit_move_insn (operands[0], operands[1]);
6044 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6046 emit_insn (gen_abssi2 (operands[0], operands[2]));
6047 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6048 emit_label (label1);
6052 operands[2] = force_reg (SImode, operands[2]);
6053 operands[2] = make_safe_from (operands[2], operands[0]);
6055 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6056 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6058 set_unique_reg_note (insn, REG_EQUAL, equal);
6060 insn = emit_move_insn (operands[0],
6061 gen_highpart (SImode, operands[3]));
6062 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6067 rtx label1 = gen_label_rtx ();
6068 rtx label2 = gen_label_rtx ();
6069 rtx label3 = gen_label_rtx ();
6071 operands[1] = force_reg (SImode, operands[1]);
6072 operands[1] = make_safe_from (operands[1], operands[0]);
6073 operands[2] = force_reg (SImode, operands[2]);
6074 operands[2] = make_safe_from (operands[2], operands[0]);
6076 emit_move_insn(operands[0], operands[1]);
6077 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6079 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6081 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6083 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6084 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6086 set_unique_reg_note (insn, REG_EQUAL, equal);
6088 insn = emit_move_insn (operands[0],
6089 gen_highpart (SImode, operands[3]));
6090 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6093 emit_label (label1);
6094 emit_move_insn (operands[0], const0_rtx);
6096 emit_label (label2);
6097 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6098 emit_label (label3);
6104 ; div(df|sf)3 instruction pattern(s).
6107 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6108 (define_insn "div<mode>3"
6109 [(set (match_operand:FP 0 "register_operand" "=f,f")
6110 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6111 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6114 d<xde><bt>r\t%0,<op1>%2
6116 [(set_attr "op_type" "<RRer>,RXE")
6117 (set_attr "type" "fdiv<mode>")])
6121 ;;- And instructions.
6124 (define_expand "and<mode>3"
6125 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6126 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6127 (match_operand:INT 2 "general_operand" "")))
6128 (clobber (reg:CC CC_REGNUM))]
6130 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6133 ; anddi3 instruction pattern(s).
6136 (define_insn "*anddi3_cc"
6137 [(set (reg CC_REGNUM)
6139 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6140 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6142 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6143 (and:DI (match_dup 1) (match_dup 2)))]
6144 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6149 risbg\t%0,%1,%s2,128+%e2,0"
6150 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6151 (set_attr "cpu_facility" "*,z196,*,z10")
6152 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6154 (define_insn "*anddi3_cconly"
6155 [(set (reg CC_REGNUM)
6157 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6158 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6160 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6162 && s390_match_ccmode(insn, CCTmode)
6163 /* Do not steal TM patterns. */
6164 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6169 risbg\t%0,%1,%s2,128+%e2,0"
6170 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6171 (set_attr "cpu_facility" "*,z196,*,z10")
6172 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6174 (define_insn "*anddi3"
6175 [(set (match_operand:DI 0 "nonimmediate_operand"
6176 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6178 (match_operand:DI 1 "nonimmediate_operand"
6179 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6180 (match_operand:DI 2 "general_operand"
6181 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6182 (clobber (reg:CC CC_REGNUM))]
6183 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6196 risbg\t%0,%1,%s2,128+%e2,0
6199 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6200 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6201 (set_attr "z10prop" "*,
6217 [(set (match_operand:DI 0 "s_operand" "")
6218 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6219 (clobber (reg:CC CC_REGNUM))]
6222 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6223 (clobber (reg:CC CC_REGNUM))])]
6224 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6226 ;; These two are what combine generates for (ashift (zero_extract)).
6227 (define_insn "*extzv_<mode>_srl"
6228 [(set (match_operand:GPR 0 "register_operand" "=d")
6229 (and:GPR (lshiftrt:GPR
6230 (match_operand:GPR 1 "register_operand" "d")
6231 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6232 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6233 (clobber (reg:CC CC_REGNUM))]
6235 /* Note that even for the SImode pattern, the rotate is always DImode. */
6236 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6237 INTVAL (operands[3]))"
6238 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6239 [(set_attr "op_type" "RIE")
6240 (set_attr "z10prop" "z10_super_E1")])
6242 (define_insn "*extzv_<mode>_sll"
6243 [(set (match_operand:GPR 0 "register_operand" "=d")
6244 (and:GPR (ashift:GPR
6245 (match_operand:GPR 1 "register_operand" "d")
6246 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6247 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6248 (clobber (reg:CC CC_REGNUM))]
6250 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6251 INTVAL (operands[3]))"
6252 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6253 [(set_attr "op_type" "RIE")
6254 (set_attr "z10prop" "z10_super_E1")])
6258 ; andsi3 instruction pattern(s).
6261 (define_insn "*andsi3_cc"
6262 [(set (reg CC_REGNUM)
6265 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6266 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6268 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6269 (and:SI (match_dup 1) (match_dup 2)))]
6270 "s390_match_ccmode(insn, CCTmode)"
6277 risbg\t%0,%1,%t2,128+%f2,0"
6278 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6279 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6280 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6281 z10_super_E1,z10_super_E1,z10_super_E1")])
6283 (define_insn "*andsi3_cconly"
6284 [(set (reg CC_REGNUM)
6287 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6288 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6290 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6291 "s390_match_ccmode(insn, CCTmode)
6292 /* Do not steal TM patterns. */
6293 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6300 risbg\t%0,%1,%t2,128+%f2,0"
6301 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6302 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6303 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6304 z10_super_E1,z10_super_E1,z10_super_E1")])
6306 (define_insn "*andsi3_zarch"
6307 [(set (match_operand:SI 0 "nonimmediate_operand"
6308 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6309 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6310 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6311 (match_operand:SI 2 "general_operand"
6312 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6313 (clobber (reg:CC CC_REGNUM))]
6314 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6325 risbg\t%0,%1,%t2,128+%f2,0
6328 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6329 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6330 (set_attr "z10prop" "*,
6343 (define_insn "*andsi3_esa"
6344 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6345 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6346 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6347 (clobber (reg:CC CC_REGNUM))]
6348 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6354 [(set_attr "op_type" "RR,RX,SI,SS")
6355 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6359 [(set (match_operand:SI 0 "s_operand" "")
6360 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6361 (clobber (reg:CC CC_REGNUM))]
6364 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6365 (clobber (reg:CC CC_REGNUM))])]
6366 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6369 ; andhi3 instruction pattern(s).
6372 (define_insn "*andhi3_zarch"
6373 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6374 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6375 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6376 (clobber (reg:CC CC_REGNUM))]
6377 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6384 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6385 (set_attr "cpu_facility" "*,z196,*,*,*")
6386 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6389 (define_insn "*andhi3_esa"
6390 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6391 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6392 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6393 (clobber (reg:CC CC_REGNUM))]
6394 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6399 [(set_attr "op_type" "RR,SI,SS")
6400 (set_attr "z10prop" "z10_super_E1,*,*")
6404 [(set (match_operand:HI 0 "s_operand" "")
6405 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6406 (clobber (reg:CC CC_REGNUM))]
6409 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6410 (clobber (reg:CC CC_REGNUM))])]
6411 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6414 ; andqi3 instruction pattern(s).
6417 (define_insn "*andqi3_zarch"
6418 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6419 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6420 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6421 (clobber (reg:CC CC_REGNUM))]
6422 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6430 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6431 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6432 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6434 (define_insn "*andqi3_esa"
6435 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6436 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6437 (match_operand:QI 2 "general_operand" "d,n,Q")))
6438 (clobber (reg:CC CC_REGNUM))]
6439 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6444 [(set_attr "op_type" "RR,SI,SS")
6445 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6448 ; Block and (NC) patterns.
6452 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6453 (and:BLK (match_dup 0)
6454 (match_operand:BLK 1 "memory_operand" "Q")))
6455 (use (match_operand 2 "const_int_operand" "n"))
6456 (clobber (reg:CC CC_REGNUM))]
6457 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6458 "nc\t%O0(%2,%R0),%S1"
6459 [(set_attr "op_type" "SS")
6460 (set_attr "z196prop" "z196_cracked")])
6463 [(set (match_operand 0 "memory_operand" "")
6465 (match_operand 1 "memory_operand" "")))
6466 (clobber (reg:CC CC_REGNUM))]
6468 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6469 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6471 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6473 (clobber (reg:CC CC_REGNUM))])]
6475 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6476 operands[0] = adjust_address (operands[0], BLKmode, 0);
6477 operands[1] = adjust_address (operands[1], BLKmode, 0);
6482 [(set (match_operand:BLK 0 "memory_operand" "")
6483 (and:BLK (match_dup 0)
6484 (match_operand:BLK 1 "memory_operand" "")))
6485 (use (match_operand 2 "const_int_operand" ""))
6486 (clobber (reg:CC CC_REGNUM))])
6488 [(set (match_operand:BLK 3 "memory_operand" "")
6489 (and:BLK (match_dup 3)
6490 (match_operand:BLK 4 "memory_operand" "")))
6491 (use (match_operand 5 "const_int_operand" ""))
6492 (clobber (reg:CC CC_REGNUM))])]
6493 "s390_offset_p (operands[0], operands[3], operands[2])
6494 && s390_offset_p (operands[1], operands[4], operands[2])
6495 && !s390_overlap_p (operands[0], operands[1],
6496 INTVAL (operands[2]) + INTVAL (operands[5]))
6497 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6499 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6501 (clobber (reg:CC CC_REGNUM))])]
6502 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6503 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6504 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6508 ;;- Bit set (inclusive or) instructions.
6511 (define_expand "ior<mode>3"
6512 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6513 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6514 (match_operand:INT 2 "general_operand" "")))
6515 (clobber (reg:CC CC_REGNUM))]
6517 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6520 ; iordi3 instruction pattern(s).
6523 (define_insn "*iordi3_cc"
6524 [(set (reg CC_REGNUM)
6525 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6526 (match_operand:DI 2 "general_operand" " d,d,RT"))
6528 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6529 (ior:DI (match_dup 1) (match_dup 2)))]
6530 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6535 [(set_attr "op_type" "RRE,RRF,RXY")
6536 (set_attr "cpu_facility" "*,z196,*")
6537 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6539 (define_insn "*iordi3_cconly"
6540 [(set (reg CC_REGNUM)
6541 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6542 (match_operand:DI 2 "general_operand" " d,d,RT"))
6544 (clobber (match_scratch:DI 0 "=d,d,d"))]
6545 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6550 [(set_attr "op_type" "RRE,RRF,RXY")
6551 (set_attr "cpu_facility" "*,z196,*")
6552 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6554 (define_insn "*iordi3"
6555 [(set (match_operand:DI 0 "nonimmediate_operand"
6556 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6557 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6558 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6559 (match_operand:DI 2 "general_operand"
6560 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6561 (clobber (reg:CC CC_REGNUM))]
6562 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6575 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6576 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6577 (set_attr "z10prop" "z10_super_E1,
6590 [(set (match_operand:DI 0 "s_operand" "")
6591 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6592 (clobber (reg:CC CC_REGNUM))]
6595 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6596 (clobber (reg:CC CC_REGNUM))])]
6597 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6600 ; iorsi3 instruction pattern(s).
6603 (define_insn "*iorsi3_cc"
6604 [(set (reg CC_REGNUM)
6605 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6606 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6608 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6609 (ior:SI (match_dup 1) (match_dup 2)))]
6610 "s390_match_ccmode(insn, CCTmode)"
6617 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6618 (set_attr "cpu_facility" "*,*,z196,*,*")
6619 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6621 (define_insn "*iorsi3_cconly"
6622 [(set (reg CC_REGNUM)
6623 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6624 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6626 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6627 "s390_match_ccmode(insn, CCTmode)"
6634 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6635 (set_attr "cpu_facility" "*,*,z196,*,*")
6636 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6638 (define_insn "*iorsi3_zarch"
6639 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6640 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6641 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6642 (clobber (reg:CC CC_REGNUM))]
6643 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6654 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6655 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6656 (set_attr "z10prop" "z10_super_E1,
6666 (define_insn "*iorsi3_esa"
6667 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6668 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6669 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6670 (clobber (reg:CC CC_REGNUM))]
6671 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6677 [(set_attr "op_type" "RR,RX,SI,SS")
6678 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6681 [(set (match_operand:SI 0 "s_operand" "")
6682 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6683 (clobber (reg:CC CC_REGNUM))]
6686 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6687 (clobber (reg:CC CC_REGNUM))])]
6688 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6691 ; iorhi3 instruction pattern(s).
6694 (define_insn "*iorhi3_zarch"
6695 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6696 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6697 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6698 (clobber (reg:CC CC_REGNUM))]
6699 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6706 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6707 (set_attr "cpu_facility" "*,z196,*,*,*")
6708 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6710 (define_insn "*iorhi3_esa"
6711 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6712 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6713 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6714 (clobber (reg:CC CC_REGNUM))]
6715 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6720 [(set_attr "op_type" "RR,SI,SS")
6721 (set_attr "z10prop" "z10_super_E1,*,*")])
6724 [(set (match_operand:HI 0 "s_operand" "")
6725 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6726 (clobber (reg:CC CC_REGNUM))]
6729 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6730 (clobber (reg:CC CC_REGNUM))])]
6731 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6734 ; iorqi3 instruction pattern(s).
6737 (define_insn "*iorqi3_zarch"
6738 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6739 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6740 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6741 (clobber (reg:CC CC_REGNUM))]
6742 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6750 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6751 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6752 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6753 z10_super,z10_super,*")])
6755 (define_insn "*iorqi3_esa"
6756 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6757 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6758 (match_operand:QI 2 "general_operand" "d,n,Q")))
6759 (clobber (reg:CC CC_REGNUM))]
6760 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6765 [(set_attr "op_type" "RR,SI,SS")
6766 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6769 ; Block inclusive or (OC) patterns.
6773 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6774 (ior:BLK (match_dup 0)
6775 (match_operand:BLK 1 "memory_operand" "Q")))
6776 (use (match_operand 2 "const_int_operand" "n"))
6777 (clobber (reg:CC CC_REGNUM))]
6778 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6779 "oc\t%O0(%2,%R0),%S1"
6780 [(set_attr "op_type" "SS")
6781 (set_attr "z196prop" "z196_cracked")])
6784 [(set (match_operand 0 "memory_operand" "")
6786 (match_operand 1 "memory_operand" "")))
6787 (clobber (reg:CC CC_REGNUM))]
6789 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6790 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6792 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6794 (clobber (reg:CC CC_REGNUM))])]
6796 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6797 operands[0] = adjust_address (operands[0], BLKmode, 0);
6798 operands[1] = adjust_address (operands[1], BLKmode, 0);
6803 [(set (match_operand:BLK 0 "memory_operand" "")
6804 (ior:BLK (match_dup 0)
6805 (match_operand:BLK 1 "memory_operand" "")))
6806 (use (match_operand 2 "const_int_operand" ""))
6807 (clobber (reg:CC CC_REGNUM))])
6809 [(set (match_operand:BLK 3 "memory_operand" "")
6810 (ior:BLK (match_dup 3)
6811 (match_operand:BLK 4 "memory_operand" "")))
6812 (use (match_operand 5 "const_int_operand" ""))
6813 (clobber (reg:CC CC_REGNUM))])]
6814 "s390_offset_p (operands[0], operands[3], operands[2])
6815 && s390_offset_p (operands[1], operands[4], operands[2])
6816 && !s390_overlap_p (operands[0], operands[1],
6817 INTVAL (operands[2]) + INTVAL (operands[5]))
6818 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6820 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6822 (clobber (reg:CC CC_REGNUM))])]
6823 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6824 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6825 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6829 ;;- Xor instructions.
6832 (define_expand "xor<mode>3"
6833 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6834 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6835 (match_operand:INT 2 "general_operand" "")))
6836 (clobber (reg:CC CC_REGNUM))]
6838 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6841 ; xordi3 instruction pattern(s).
6844 (define_insn "*xordi3_cc"
6845 [(set (reg CC_REGNUM)
6846 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6847 (match_operand:DI 2 "general_operand" " d,d,RT"))
6849 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6850 (xor:DI (match_dup 1) (match_dup 2)))]
6851 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6856 [(set_attr "op_type" "RRE,RRF,RXY")
6857 (set_attr "cpu_facility" "*,z196,*")
6858 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6860 (define_insn "*xordi3_cconly"
6861 [(set (reg CC_REGNUM)
6862 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6863 (match_operand:DI 2 "general_operand" " d,d,RT"))
6865 (clobber (match_scratch:DI 0 "=d,d, d"))]
6866 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6871 [(set_attr "op_type" "RRE,RRF,RXY")
6872 (set_attr "cpu_facility" "*,z196,*")
6873 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6875 (define_insn "*xordi3"
6876 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6877 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6878 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6879 (clobber (reg:CC CC_REGNUM))]
6880 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6889 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6890 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6891 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6892 *,z10_super_E1,*,*")])
6895 [(set (match_operand:DI 0 "s_operand" "")
6896 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6897 (clobber (reg:CC CC_REGNUM))]
6900 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6901 (clobber (reg:CC CC_REGNUM))])]
6902 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6905 ; xorsi3 instruction pattern(s).
6908 (define_insn "*xorsi3_cc"
6909 [(set (reg CC_REGNUM)
6910 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6911 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6913 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6914 (xor:SI (match_dup 1) (match_dup 2)))]
6915 "s390_match_ccmode(insn, CCTmode)"
6922 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6923 (set_attr "cpu_facility" "*,*,z196,*,*")
6924 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6925 z10_super_E1,z10_super_E1")])
6927 (define_insn "*xorsi3_cconly"
6928 [(set (reg CC_REGNUM)
6929 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6930 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6932 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6933 "s390_match_ccmode(insn, CCTmode)"
6940 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6941 (set_attr "cpu_facility" "*,*,z196,*,*")
6942 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6943 z10_super_E1,z10_super_E1")])
6945 (define_insn "*xorsi3"
6946 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6947 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6948 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6949 (clobber (reg:CC CC_REGNUM))]
6950 "s390_logical_operator_ok_p (operands)"
6959 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6960 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6961 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6962 z10_super_E1,z10_super_E1,*,*")])
6965 [(set (match_operand:SI 0 "s_operand" "")
6966 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6967 (clobber (reg:CC CC_REGNUM))]
6970 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6971 (clobber (reg:CC CC_REGNUM))])]
6972 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6975 ; xorhi3 instruction pattern(s).
6978 (define_insn "*xorhi3"
6979 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6980 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6981 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6982 (clobber (reg:CC CC_REGNUM))]
6983 "s390_logical_operator_ok_p (operands)"
6990 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6991 (set_attr "cpu_facility" "*,*,z196,*,*")
6992 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6995 [(set (match_operand:HI 0 "s_operand" "")
6996 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6997 (clobber (reg:CC CC_REGNUM))]
7000 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7001 (clobber (reg:CC CC_REGNUM))])]
7002 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7005 ; xorqi3 instruction pattern(s).
7008 (define_insn "*xorqi3"
7009 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7010 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7011 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7012 (clobber (reg:CC CC_REGNUM))]
7013 "s390_logical_operator_ok_p (operands)"
7021 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7022 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7023 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7027 ; Block exclusive or (XC) patterns.
7031 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7032 (xor:BLK (match_dup 0)
7033 (match_operand:BLK 1 "memory_operand" "Q")))
7034 (use (match_operand 2 "const_int_operand" "n"))
7035 (clobber (reg:CC CC_REGNUM))]
7036 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7037 "xc\t%O0(%2,%R0),%S1"
7038 [(set_attr "op_type" "SS")])
7041 [(set (match_operand 0 "memory_operand" "")
7043 (match_operand 1 "memory_operand" "")))
7044 (clobber (reg:CC CC_REGNUM))]
7046 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7047 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7049 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7051 (clobber (reg:CC CC_REGNUM))])]
7053 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7054 operands[0] = adjust_address (operands[0], BLKmode, 0);
7055 operands[1] = adjust_address (operands[1], BLKmode, 0);
7060 [(set (match_operand:BLK 0 "memory_operand" "")
7061 (xor:BLK (match_dup 0)
7062 (match_operand:BLK 1 "memory_operand" "")))
7063 (use (match_operand 2 "const_int_operand" ""))
7064 (clobber (reg:CC CC_REGNUM))])
7066 [(set (match_operand:BLK 3 "memory_operand" "")
7067 (xor:BLK (match_dup 3)
7068 (match_operand:BLK 4 "memory_operand" "")))
7069 (use (match_operand 5 "const_int_operand" ""))
7070 (clobber (reg:CC CC_REGNUM))])]
7071 "s390_offset_p (operands[0], operands[3], operands[2])
7072 && s390_offset_p (operands[1], operands[4], operands[2])
7073 && !s390_overlap_p (operands[0], operands[1],
7074 INTVAL (operands[2]) + INTVAL (operands[5]))
7075 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7077 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7079 (clobber (reg:CC CC_REGNUM))])]
7080 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7081 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7082 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7085 ; Block xor (XC) patterns with src == dest.
7088 (define_insn "*xc_zero"
7089 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7091 (use (match_operand 1 "const_int_operand" "n"))
7092 (clobber (reg:CC CC_REGNUM))]
7093 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7094 "xc\t%O0(%1,%R0),%S0"
7095 [(set_attr "op_type" "SS")
7096 (set_attr "z196prop" "z196_cracked")])
7100 [(set (match_operand:BLK 0 "memory_operand" "")
7102 (use (match_operand 1 "const_int_operand" ""))
7103 (clobber (reg:CC CC_REGNUM))])
7105 [(set (match_operand:BLK 2 "memory_operand" "")
7107 (use (match_operand 3 "const_int_operand" ""))
7108 (clobber (reg:CC CC_REGNUM))])]
7109 "s390_offset_p (operands[0], operands[2], operands[1])
7110 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7112 [(set (match_dup 4) (const_int 0))
7114 (clobber (reg:CC CC_REGNUM))])]
7115 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7116 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7120 ;;- Negate instructions.
7124 ; neg(di|si)2 instruction pattern(s).
7127 (define_expand "neg<mode>2"
7129 [(set (match_operand:DSI 0 "register_operand" "=d")
7130 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7131 (clobber (reg:CC CC_REGNUM))])]
7135 (define_insn "*negdi2_sign_cc"
7136 [(set (reg CC_REGNUM)
7137 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7138 (match_operand:SI 1 "register_operand" "d") 0)
7139 (const_int 32)) (const_int 32)))
7141 (set (match_operand:DI 0 "register_operand" "=d")
7142 (neg:DI (sign_extend:DI (match_dup 1))))]
7143 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7145 [(set_attr "op_type" "RRE")
7146 (set_attr "z10prop" "z10_c")])
7148 (define_insn "*negdi2_sign"
7149 [(set (match_operand:DI 0 "register_operand" "=d")
7150 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7151 (clobber (reg:CC CC_REGNUM))]
7154 [(set_attr "op_type" "RRE")
7155 (set_attr "z10prop" "z10_c")])
7158 (define_insn "*neg<mode>2_cc"
7159 [(set (reg CC_REGNUM)
7160 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7162 (set (match_operand:GPR 0 "register_operand" "=d")
7163 (neg:GPR (match_dup 1)))]
7164 "s390_match_ccmode (insn, CCAmode)"
7166 [(set_attr "op_type" "RR<E>")
7167 (set_attr "z10prop" "z10_super_c_E1")])
7170 (define_insn "*neg<mode>2_cconly"
7171 [(set (reg CC_REGNUM)
7172 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7174 (clobber (match_scratch:GPR 0 "=d"))]
7175 "s390_match_ccmode (insn, CCAmode)"
7177 [(set_attr "op_type" "RR<E>")
7178 (set_attr "z10prop" "z10_super_c_E1")])
7181 (define_insn "*neg<mode>2"
7182 [(set (match_operand:GPR 0 "register_operand" "=d")
7183 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7184 (clobber (reg:CC CC_REGNUM))]
7187 [(set_attr "op_type" "RR<E>")
7188 (set_attr "z10prop" "z10_super_c_E1")])
7190 (define_insn_and_split "*negdi2_31"
7191 [(set (match_operand:DI 0 "register_operand" "=d")
7192 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7193 (clobber (reg:CC CC_REGNUM))]
7196 "&& reload_completed"
7198 [(set (match_dup 2) (neg:SI (match_dup 3)))
7199 (clobber (reg:CC CC_REGNUM))])
7201 [(set (reg:CCAP CC_REGNUM)
7202 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7203 (set (match_dup 4) (neg:SI (match_dup 5)))])
7205 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7207 (label_ref (match_dup 6))))
7209 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7210 (clobber (reg:CC CC_REGNUM))])
7212 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7213 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7214 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7215 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7216 operands[6] = gen_label_rtx ();")
7219 ; neg(df|sf)2 instruction pattern(s).
7222 (define_expand "neg<mode>2"
7224 [(set (match_operand:BFP 0 "register_operand" "=f")
7225 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7226 (clobber (reg:CC CC_REGNUM))])]
7230 ; lcxbr, lcdbr, lcebr
7231 (define_insn "*neg<mode>2_cc"
7232 [(set (reg CC_REGNUM)
7233 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7234 (match_operand:BFP 2 "const0_operand" "")))
7235 (set (match_operand:BFP 0 "register_operand" "=f")
7236 (neg:BFP (match_dup 1)))]
7237 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7239 [(set_attr "op_type" "RRE")
7240 (set_attr "type" "fsimp<mode>")])
7242 ; lcxbr, lcdbr, lcebr
7243 (define_insn "*neg<mode>2_cconly"
7244 [(set (reg CC_REGNUM)
7245 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7246 (match_operand:BFP 2 "const0_operand" "")))
7247 (clobber (match_scratch:BFP 0 "=f"))]
7248 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7250 [(set_attr "op_type" "RRE")
7251 (set_attr "type" "fsimp<mode>")])
7254 (define_insn "*neg<mode>2_nocc"
7255 [(set (match_operand:FP 0 "register_operand" "=f")
7256 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7259 [(set_attr "op_type" "RRE")
7260 (set_attr "type" "fsimp<mode>")])
7262 ; lcxbr, lcdbr, lcebr
7263 (define_insn "*neg<mode>2"
7264 [(set (match_operand:BFP 0 "register_operand" "=f")
7265 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7266 (clobber (reg:CC CC_REGNUM))]
7269 [(set_attr "op_type" "RRE")
7270 (set_attr "type" "fsimp<mode>")])
7274 ;;- Absolute value instructions.
7278 ; abs(di|si)2 instruction pattern(s).
7281 (define_insn "*absdi2_sign_cc"
7282 [(set (reg CC_REGNUM)
7283 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7284 (match_operand:SI 1 "register_operand" "d") 0)
7285 (const_int 32)) (const_int 32)))
7287 (set (match_operand:DI 0 "register_operand" "=d")
7288 (abs:DI (sign_extend:DI (match_dup 1))))]
7289 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7291 [(set_attr "op_type" "RRE")
7292 (set_attr "z10prop" "z10_c")])
7294 (define_insn "*absdi2_sign"
7295 [(set (match_operand:DI 0 "register_operand" "=d")
7296 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7297 (clobber (reg:CC CC_REGNUM))]
7300 [(set_attr "op_type" "RRE")
7301 (set_attr "z10prop" "z10_c")])
7304 (define_insn "*abs<mode>2_cc"
7305 [(set (reg CC_REGNUM)
7306 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7308 (set (match_operand:GPR 0 "register_operand" "=d")
7309 (abs:GPR (match_dup 1)))]
7310 "s390_match_ccmode (insn, CCAmode)"
7312 [(set_attr "op_type" "RR<E>")
7313 (set_attr "z10prop" "z10_c")])
7316 (define_insn "*abs<mode>2_cconly"
7317 [(set (reg CC_REGNUM)
7318 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7320 (clobber (match_scratch:GPR 0 "=d"))]
7321 "s390_match_ccmode (insn, CCAmode)"
7323 [(set_attr "op_type" "RR<E>")
7324 (set_attr "z10prop" "z10_c")])
7327 (define_insn "abs<mode>2"
7328 [(set (match_operand:GPR 0 "register_operand" "=d")
7329 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7330 (clobber (reg:CC CC_REGNUM))]
7333 [(set_attr "op_type" "RR<E>")
7334 (set_attr "z10prop" "z10_c")])
7337 ; abs(df|sf)2 instruction pattern(s).
7340 (define_expand "abs<mode>2"
7342 [(set (match_operand:BFP 0 "register_operand" "=f")
7343 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7344 (clobber (reg:CC CC_REGNUM))])]
7348 ; lpxbr, lpdbr, lpebr
7349 (define_insn "*abs<mode>2_cc"
7350 [(set (reg CC_REGNUM)
7351 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7352 (match_operand:BFP 2 "const0_operand" "")))
7353 (set (match_operand:BFP 0 "register_operand" "=f")
7354 (abs:BFP (match_dup 1)))]
7355 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7357 [(set_attr "op_type" "RRE")
7358 (set_attr "type" "fsimp<mode>")])
7360 ; lpxbr, lpdbr, lpebr
7361 (define_insn "*abs<mode>2_cconly"
7362 [(set (reg CC_REGNUM)
7363 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7364 (match_operand:BFP 2 "const0_operand" "")))
7365 (clobber (match_scratch:BFP 0 "=f"))]
7366 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7368 [(set_attr "op_type" "RRE")
7369 (set_attr "type" "fsimp<mode>")])
7372 (define_insn "*abs<mode>2_nocc"
7373 [(set (match_operand:FP 0 "register_operand" "=f")
7374 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7377 [(set_attr "op_type" "RRE")
7378 (set_attr "type" "fsimp<mode>")])
7380 ; lpxbr, lpdbr, lpebr
7381 (define_insn "*abs<mode>2"
7382 [(set (match_operand:BFP 0 "register_operand" "=f")
7383 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7384 (clobber (reg:CC CC_REGNUM))]
7387 [(set_attr "op_type" "RRE")
7388 (set_attr "type" "fsimp<mode>")])
7392 ;;- Negated absolute value instructions
7399 (define_insn "*negabsdi2_sign_cc"
7400 [(set (reg CC_REGNUM)
7401 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7402 (match_operand:SI 1 "register_operand" "d") 0)
7403 (const_int 32)) (const_int 32))))
7405 (set (match_operand:DI 0 "register_operand" "=d")
7406 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7407 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7409 [(set_attr "op_type" "RRE")
7410 (set_attr "z10prop" "z10_c")])
7412 (define_insn "*negabsdi2_sign"
7413 [(set (match_operand:DI 0 "register_operand" "=d")
7414 (neg:DI (abs:DI (sign_extend:DI
7415 (match_operand:SI 1 "register_operand" "d")))))
7416 (clobber (reg:CC CC_REGNUM))]
7419 [(set_attr "op_type" "RRE")
7420 (set_attr "z10prop" "z10_c")])
7423 (define_insn "*negabs<mode>2_cc"
7424 [(set (reg CC_REGNUM)
7425 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7427 (set (match_operand:GPR 0 "register_operand" "=d")
7428 (neg:GPR (abs:GPR (match_dup 1))))]
7429 "s390_match_ccmode (insn, CCAmode)"
7431 [(set_attr "op_type" "RR<E>")
7432 (set_attr "z10prop" "z10_c")])
7435 (define_insn "*negabs<mode>2_cconly"
7436 [(set (reg CC_REGNUM)
7437 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7439 (clobber (match_scratch:GPR 0 "=d"))]
7440 "s390_match_ccmode (insn, CCAmode)"
7442 [(set_attr "op_type" "RR<E>")
7443 (set_attr "z10prop" "z10_c")])
7446 (define_insn "*negabs<mode>2"
7447 [(set (match_operand:GPR 0 "register_operand" "=d")
7448 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7449 (clobber (reg:CC CC_REGNUM))]
7452 [(set_attr "op_type" "RR<E>")
7453 (set_attr "z10prop" "z10_c")])
7459 ; lnxbr, lndbr, lnebr
7460 (define_insn "*negabs<mode>2_cc"
7461 [(set (reg CC_REGNUM)
7462 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7463 (match_operand:BFP 2 "const0_operand" "")))
7464 (set (match_operand:BFP 0 "register_operand" "=f")
7465 (neg:BFP (abs:BFP (match_dup 1))))]
7466 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7468 [(set_attr "op_type" "RRE")
7469 (set_attr "type" "fsimp<mode>")])
7471 ; lnxbr, lndbr, lnebr
7472 (define_insn "*negabs<mode>2_cconly"
7473 [(set (reg CC_REGNUM)
7474 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7475 (match_operand:BFP 2 "const0_operand" "")))
7476 (clobber (match_scratch:BFP 0 "=f"))]
7477 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7479 [(set_attr "op_type" "RRE")
7480 (set_attr "type" "fsimp<mode>")])
7483 (define_insn "*negabs<mode>2_nocc"
7484 [(set (match_operand:FP 0 "register_operand" "=f")
7485 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7488 [(set_attr "op_type" "RRE")
7489 (set_attr "type" "fsimp<mode>")])
7491 ; lnxbr, lndbr, lnebr
7492 (define_insn "*negabs<mode>2"
7493 [(set (match_operand:BFP 0 "register_operand" "=f")
7494 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7495 (clobber (reg:CC CC_REGNUM))]
7498 [(set_attr "op_type" "RRE")
7499 (set_attr "type" "fsimp<mode>")])
7502 ;;- Square root instructions.
7506 ; sqrt(df|sf)2 instruction pattern(s).
7509 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7510 (define_insn "sqrt<mode>2"
7511 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7512 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7517 [(set_attr "op_type" "RRE,RXE")
7518 (set_attr "type" "fsqrt<mode>")])
7522 ;;- One complement instructions.
7526 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7529 (define_expand "one_cmpl<mode>2"
7531 [(set (match_operand:INT 0 "register_operand" "")
7532 (xor:INT (match_operand:INT 1 "register_operand" "")
7534 (clobber (reg:CC CC_REGNUM))])]
7540 ;; Find leftmost bit instructions.
7543 (define_expand "clzdi2"
7544 [(set (match_operand:DI 0 "register_operand" "=d")
7545 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7546 "TARGET_EXTIMM && TARGET_ZARCH"
7548 rtx insn, clz_equal;
7549 rtx wide_reg = gen_reg_rtx (TImode);
7550 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7552 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7554 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7556 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7557 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7562 (define_insn "clztidi2"
7563 [(set (match_operand:TI 0 "register_operand" "=d")
7567 (xor:DI (match_operand:DI 1 "register_operand" "d")
7568 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7569 (subreg:SI (clz:DI (match_dup 1)) 4))))
7572 (zero_extend:TI (clz:DI (match_dup 1)))))
7573 (clobber (reg:CC CC_REGNUM))]
7574 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7575 == (unsigned HOST_WIDE_INT) 1 << 63
7576 && TARGET_EXTIMM && TARGET_ZARCH"
7578 [(set_attr "op_type" "RRE")])
7582 ;;- Rotate instructions.
7586 ; rotl(di|si)3 instruction pattern(s).
7590 (define_insn "rotl<mode>3"
7591 [(set (match_operand:GPR 0 "register_operand" "=d")
7592 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7593 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7596 [(set_attr "op_type" "RSE")
7597 (set_attr "atype" "reg")
7598 (set_attr "z10prop" "z10_super_E1")])
7601 (define_insn "*rotl<mode>3_and"
7602 [(set (match_operand:GPR 0 "register_operand" "=d")
7603 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7604 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7605 (match_operand:SI 3 "const_int_operand" "n"))))]
7606 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7608 [(set_attr "op_type" "RSE")
7609 (set_attr "atype" "reg")
7610 (set_attr "z10prop" "z10_super_E1")])
7614 ;;- Shift instructions.
7618 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7619 ; Left shifts and logical right shifts
7621 (define_expand "<shift><mode>3"
7622 [(set (match_operand:DSI 0 "register_operand" "")
7623 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7624 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7629 (define_insn "*<shift>di3_31"
7630 [(set (match_operand:DI 0 "register_operand" "=d")
7631 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7632 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7635 [(set_attr "op_type" "RS")
7636 (set_attr "atype" "reg")
7637 (set_attr "z196prop" "z196_cracked")])
7639 ; sll, srl, sllg, srlg, sllk, srlk
7640 (define_insn "*<shift><mode>3"
7641 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7642 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7643 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7646 s<lr>l<g>\t%0,<1>%Y2
7647 s<lr>l<gk>\t%0,%1,%Y2"
7648 [(set_attr "op_type" "RS<E>,RSY")
7649 (set_attr "atype" "reg,reg")
7650 (set_attr "cpu_facility" "*,z196")
7651 (set_attr "z10prop" "z10_super_E1,*")])
7654 (define_insn "*<shift>di3_31_and"
7655 [(set (match_operand:DI 0 "register_operand" "=d")
7656 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7657 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7658 (match_operand:SI 3 "const_int_operand" "n"))))]
7659 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7661 [(set_attr "op_type" "RS")
7662 (set_attr "atype" "reg")])
7664 ; sll, srl, sllg, srlg, sllk, srlk
7665 (define_insn "*<shift><mode>3_and"
7666 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7667 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7668 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7669 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7670 "(INTVAL (operands[3]) & 63) == 63"
7672 s<lr>l<g>\t%0,<1>%Y2
7673 s<lr>l<gk>\t%0,%1,%Y2"
7674 [(set_attr "op_type" "RS<E>,RSY")
7675 (set_attr "atype" "reg,reg")
7676 (set_attr "cpu_facility" "*,z196")
7677 (set_attr "z10prop" "z10_super_E1,*")])
7680 ; ashr(di|si)3 instruction pattern(s).
7681 ; Arithmetic right shifts
7683 (define_expand "ashr<mode>3"
7685 [(set (match_operand:DSI 0 "register_operand" "")
7686 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7687 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7688 (clobber (reg:CC CC_REGNUM))])]
7692 (define_insn "*ashrdi3_cc_31"
7693 [(set (reg CC_REGNUM)
7694 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7695 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7697 (set (match_operand:DI 0 "register_operand" "=d")
7698 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7699 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7701 [(set_attr "op_type" "RS")
7702 (set_attr "atype" "reg")])
7704 (define_insn "*ashrdi3_cconly_31"
7705 [(set (reg CC_REGNUM)
7706 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7707 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7709 (clobber (match_scratch:DI 0 "=d"))]
7710 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7712 [(set_attr "op_type" "RS")
7713 (set_attr "atype" "reg")])
7715 (define_insn "*ashrdi3_31"
7716 [(set (match_operand:DI 0 "register_operand" "=d")
7717 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7718 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7719 (clobber (reg:CC CC_REGNUM))]
7722 [(set_attr "op_type" "RS")
7723 (set_attr "atype" "reg")])
7726 (define_insn "*ashr<mode>3_cc"
7727 [(set (reg CC_REGNUM)
7728 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7729 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7731 (set (match_operand:GPR 0 "register_operand" "=d,d")
7732 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7733 "s390_match_ccmode(insn, CCSmode)"
7737 [(set_attr "op_type" "RS<E>,RSY")
7738 (set_attr "atype" "reg,reg")
7739 (set_attr "cpu_facility" "*,z196")
7740 (set_attr "z10prop" "z10_super_E1,*")])
7743 (define_insn "*ashr<mode>3_cconly"
7744 [(set (reg CC_REGNUM)
7745 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7746 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7748 (clobber (match_scratch:GPR 0 "=d,d"))]
7749 "s390_match_ccmode(insn, CCSmode)"
7753 [(set_attr "op_type" "RS<E>,RSY")
7754 (set_attr "atype" "reg,reg")
7755 (set_attr "cpu_facility" "*,z196")
7756 (set_attr "z10prop" "z10_super_E1,*")])
7759 (define_insn "*ashr<mode>3"
7760 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7761 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7762 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7763 (clobber (reg:CC CC_REGNUM))]
7768 [(set_attr "op_type" "RS<E>,RSY")
7769 (set_attr "atype" "reg,reg")
7770 (set_attr "cpu_facility" "*,z196")
7771 (set_attr "z10prop" "z10_super_E1,*")])
7774 ; shift pattern with implicit ANDs
7776 (define_insn "*ashrdi3_cc_31_and"
7777 [(set (reg CC_REGNUM)
7778 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7779 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7780 (match_operand:SI 3 "const_int_operand" "n")))
7782 (set (match_operand:DI 0 "register_operand" "=d")
7783 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7784 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7785 && (INTVAL (operands[3]) & 63) == 63"
7787 [(set_attr "op_type" "RS")
7788 (set_attr "atype" "reg")])
7790 (define_insn "*ashrdi3_cconly_31_and"
7791 [(set (reg CC_REGNUM)
7792 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7793 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7794 (match_operand:SI 3 "const_int_operand" "n")))
7796 (clobber (match_scratch:DI 0 "=d"))]
7797 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7798 && (INTVAL (operands[3]) & 63) == 63"
7800 [(set_attr "op_type" "RS")
7801 (set_attr "atype" "reg")])
7803 (define_insn "*ashrdi3_31_and"
7804 [(set (match_operand:DI 0 "register_operand" "=d")
7805 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7806 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7807 (match_operand:SI 3 "const_int_operand" "n"))))
7808 (clobber (reg:CC CC_REGNUM))]
7809 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7811 [(set_attr "op_type" "RS")
7812 (set_attr "atype" "reg")])
7815 (define_insn "*ashr<mode>3_cc_and"
7816 [(set (reg CC_REGNUM)
7817 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7818 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7819 (match_operand:SI 3 "const_int_operand" "n,n")))
7821 (set (match_operand:GPR 0 "register_operand" "=d,d")
7822 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7823 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7827 [(set_attr "op_type" "RS<E>,RSY")
7828 (set_attr "atype" "reg,reg")
7829 (set_attr "cpu_facility" "*,z196")
7830 (set_attr "z10prop" "z10_super_E1,*")])
7833 (define_insn "*ashr<mode>3_cconly_and"
7834 [(set (reg CC_REGNUM)
7835 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7836 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7837 (match_operand:SI 3 "const_int_operand" "n,n")))
7839 (clobber (match_scratch:GPR 0 "=d,d"))]
7840 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7844 [(set_attr "op_type" "RS<E>,RSY")
7845 (set_attr "atype" "reg,reg")
7846 (set_attr "cpu_facility" "*,z196")
7847 (set_attr "z10prop" "z10_super_E1,*")])
7850 (define_insn "*ashr<mode>3_and"
7851 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7852 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7853 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7854 (match_operand:SI 3 "const_int_operand" "n,n"))))
7855 (clobber (reg:CC CC_REGNUM))]
7856 "(INTVAL (operands[3]) & 63) == 63"
7860 [(set_attr "op_type" "RS<E>,RSY")
7861 (set_attr "atype" "reg,reg")
7862 (set_attr "cpu_facility" "*,z196")
7863 (set_attr "z10prop" "z10_super_E1,*")])
7867 ;; Branch instruction patterns.
7870 (define_expand "cbranch<mode>4"
7872 (if_then_else (match_operator 0 "comparison_operator"
7873 [(match_operand:GPR 1 "register_operand" "")
7874 (match_operand:GPR 2 "general_operand" "")])
7875 (label_ref (match_operand 3 "" ""))
7878 "s390_emit_jump (operands[3],
7879 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7882 (define_expand "cbranch<mode>4"
7884 (if_then_else (match_operator 0 "comparison_operator"
7885 [(match_operand:FP 1 "register_operand" "")
7886 (match_operand:FP 2 "general_operand" "")])
7887 (label_ref (match_operand 3 "" ""))
7890 "s390_emit_jump (operands[3],
7891 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7894 (define_expand "cbranchcc4"
7896 (if_then_else (match_operator 0 "s390_eqne_operator"
7897 [(match_operand 1 "cc_reg_operand" "")
7898 (match_operand 2 "const0_operand" "")])
7899 (label_ref (match_operand 3 "" ""))
7902 "s390_emit_jump (operands[3],
7903 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7909 ;;- Conditional jump instructions.
7912 (define_insn "*cjump_64"
7915 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7916 (label_ref (match_operand 0 "" ""))
7920 if (get_attr_length (insn) == 4)
7923 return "jg%C1\t%l0";
7925 [(set_attr "op_type" "RI")
7926 (set_attr "type" "branch")
7927 (set (attr "length")
7928 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7929 (const_int 4) (const_int 6)))])
7931 (define_insn "*cjump_31"
7934 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7935 (label_ref (match_operand 0 "" ""))
7939 gcc_assert (get_attr_length (insn) == 4);
7942 [(set_attr "op_type" "RI")
7943 (set_attr "type" "branch")
7944 (set (attr "length")
7945 (if_then_else (not (match_test "flag_pic"))
7946 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7947 (const_int 4) (const_int 6))
7948 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7949 (const_int 4) (const_int 8))))])
7951 (define_insn "*cjump_long"
7954 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7955 (match_operand 0 "address_operand" "ZQZR")
7959 if (get_attr_op_type (insn) == OP_TYPE_RR)
7964 [(set (attr "op_type")
7965 (if_then_else (match_operand 0 "register_operand" "")
7966 (const_string "RR") (const_string "RX")))
7967 (set_attr "type" "branch")
7968 (set_attr "atype" "agen")])
7972 ;;- Negated conditional jump instructions.
7975 (define_insn "*icjump_64"
7978 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7980 (label_ref (match_operand 0 "" ""))))]
7983 if (get_attr_length (insn) == 4)
7986 return "jg%D1\t%l0";
7988 [(set_attr "op_type" "RI")
7989 (set_attr "type" "branch")
7990 (set (attr "length")
7991 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7992 (const_int 4) (const_int 6)))])
7994 (define_insn "*icjump_31"
7997 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7999 (label_ref (match_operand 0 "" ""))))]
8002 gcc_assert (get_attr_length (insn) == 4);
8005 [(set_attr "op_type" "RI")
8006 (set_attr "type" "branch")
8007 (set (attr "length")
8008 (if_then_else (not (match_test "flag_pic"))
8009 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8010 (const_int 4) (const_int 6))
8011 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8012 (const_int 4) (const_int 8))))])
8014 (define_insn "*icjump_long"
8017 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8019 (match_operand 0 "address_operand" "ZQZR")))]
8022 if (get_attr_op_type (insn) == OP_TYPE_RR)
8027 [(set (attr "op_type")
8028 (if_then_else (match_operand 0 "register_operand" "")
8029 (const_string "RR") (const_string "RX")))
8030 (set_attr "type" "branch")
8031 (set_attr "atype" "agen")])
8034 ;;- Trap instructions.
8038 [(trap_if (const_int 1) (const_int 0))]
8041 [(set_attr "op_type" "RI")
8042 (set_attr "type" "branch")])
8044 (define_expand "ctrap<mode>4"
8045 [(trap_if (match_operator 0 "comparison_operator"
8046 [(match_operand:GPR 1 "register_operand" "")
8047 (match_operand:GPR 2 "general_operand" "")])
8048 (match_operand 3 "const0_operand" ""))]
8051 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8052 operands[1], operands[2]);
8053 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8057 (define_expand "ctrap<mode>4"
8058 [(trap_if (match_operator 0 "comparison_operator"
8059 [(match_operand:FP 1 "register_operand" "")
8060 (match_operand:FP 2 "general_operand" "")])
8061 (match_operand 3 "const0_operand" ""))]
8064 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8065 operands[1], operands[2]);
8066 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8070 (define_insn "condtrap"
8071 [(trap_if (match_operator 0 "s390_comparison"
8072 [(match_operand 1 "cc_reg_operand" "c")
8077 [(set_attr "op_type" "RI")
8078 (set_attr "type" "branch")])
8080 ; crt, cgrt, cit, cgit
8081 (define_insn "*cmp_and_trap_signed_int<mode>"
8082 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8083 [(match_operand:GPR 1 "register_operand" "d,d")
8084 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8090 [(set_attr "op_type" "RRF,RIE")
8091 (set_attr "type" "branch")
8092 (set_attr "z10prop" "z10_super_c,z10_super")])
8094 ; clrt, clgrt, clfit, clgit, clt, clgt
8095 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8096 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8097 [(match_operand:GPR 1 "register_operand" "d,d, d")
8098 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8105 [(set_attr "op_type" "RRF,RIE,RSY")
8106 (set_attr "type" "branch")
8107 (set_attr "z10prop" "z10_super_c,z10_super,*")
8108 (set_attr "cpu_facility" "z10,z10,zEC12")])
8111 (define_insn "*load_and_trap<mode>"
8112 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8115 (set (match_operand:GPR 1 "register_operand" "=d")
8119 [(set_attr "op_type" "RXY")])
8123 ;;- Loop instructions.
8125 ;; This is all complicated by the fact that since this is a jump insn
8126 ;; we must handle our own output reloads.
8130 ; This splitter will be matched by combine and has to add the 2 moves
8131 ; necessary to load the compare and the increment values into a
8132 ; register pair as needed by brxle.
8134 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8137 (match_operator 6 "s390_brx_operator"
8138 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8139 (match_operand:GPR 2 "general_operand" ""))
8140 (match_operand:GPR 3 "register_operand" "")])
8141 (label_ref (match_operand 0 "" ""))
8143 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8144 (plus:GPR (match_dup 1) (match_dup 2)))
8145 (clobber (match_scratch:GPR 5 ""))]
8148 "!reload_completed && !reload_in_progress"
8149 [(set (match_dup 7) (match_dup 2)) ; the increment
8150 (set (match_dup 8) (match_dup 3)) ; the comparison value
8151 (parallel [(set (pc)
8154 [(plus:GPR (match_dup 1) (match_dup 7))
8156 (label_ref (match_dup 0))
8159 (plus:GPR (match_dup 1) (match_dup 7)))
8160 (clobber (match_dup 5))
8161 (clobber (reg:CC CC_REGNUM))])]
8163 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8164 operands[7] = gen_lowpart (<GPR:MODE>mode,
8165 gen_highpart (word_mode, dreg));
8166 operands[8] = gen_lowpart (<GPR:MODE>mode,
8167 gen_lowpart (word_mode, dreg));
8172 (define_insn_and_split "*brxg_64bit"
8175 (match_operator 5 "s390_brx_operator"
8176 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8177 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8178 (subreg:DI (match_dup 2) 8)])
8179 (label_ref (match_operand 0 "" ""))
8181 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8182 (plus:DI (match_dup 1)
8183 (subreg:DI (match_dup 2) 0)))
8184 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8185 (clobber (reg:CC CC_REGNUM))]
8188 if (which_alternative != 0)
8190 else if (get_attr_length (insn) == 6)
8191 return "brx%E5g\t%1,%2,%l0";
8193 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8195 "&& reload_completed
8196 && (!REG_P (operands[3])
8197 || !rtx_equal_p (operands[1], operands[3]))"
8198 [(set (match_dup 4) (match_dup 1))
8199 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8200 (clobber (reg:CC CC_REGNUM))])
8201 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8202 (set (match_dup 3) (match_dup 4))
8203 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8204 (label_ref (match_dup 0))
8207 [(set_attr "op_type" "RIE")
8208 (set_attr "type" "branch")
8209 (set (attr "length")
8210 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8211 (const_int 6) (const_int 16)))])
8215 (define_insn_and_split "*brx_64bit"
8218 (match_operator 5 "s390_brx_operator"
8219 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8220 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8221 (subreg:SI (match_dup 2) 12)])
8222 (label_ref (match_operand 0 "" ""))
8224 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8225 (plus:SI (match_dup 1)
8226 (subreg:SI (match_dup 2) 4)))
8227 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8228 (clobber (reg:CC CC_REGNUM))]
8231 if (which_alternative != 0)
8233 else if (get_attr_length (insn) == 6)
8234 return "brx%C5\t%1,%2,%l0";
8236 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8238 "&& reload_completed
8239 && (!REG_P (operands[3])
8240 || !rtx_equal_p (operands[1], operands[3]))"
8241 [(set (match_dup 4) (match_dup 1))
8242 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8243 (clobber (reg:CC CC_REGNUM))])
8244 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8245 (set (match_dup 3) (match_dup 4))
8246 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8247 (label_ref (match_dup 0))
8250 [(set_attr "op_type" "RSI")
8251 (set_attr "type" "branch")
8252 (set (attr "length")
8253 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8254 (const_int 6) (const_int 14)))])
8258 (define_insn_and_split "*brx_31bit"
8261 (match_operator 5 "s390_brx_operator"
8262 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8263 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8264 (subreg:SI (match_dup 2) 4)])
8265 (label_ref (match_operand 0 "" ""))
8267 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8268 (plus:SI (match_dup 1)
8269 (subreg:SI (match_dup 2) 0)))
8270 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8271 (clobber (reg:CC CC_REGNUM))]
8272 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8274 if (which_alternative != 0)
8276 else if (get_attr_length (insn) == 6)
8277 return "brx%C5\t%1,%2,%l0";
8279 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8281 "&& reload_completed
8282 && (!REG_P (operands[3])
8283 || !rtx_equal_p (operands[1], operands[3]))"
8284 [(set (match_dup 4) (match_dup 1))
8285 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8286 (clobber (reg:CC CC_REGNUM))])
8287 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8288 (set (match_dup 3) (match_dup 4))
8289 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8290 (label_ref (match_dup 0))
8293 [(set_attr "op_type" "RSI")
8294 (set_attr "type" "branch")
8295 (set (attr "length")
8296 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8297 (const_int 6) (const_int 14)))])
8302 (define_expand "doloop_end"
8303 [(use (match_operand 0 "" "")) ; loop pseudo
8304 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8305 (use (match_operand 2 "" "")) ; max iterations
8306 (use (match_operand 3 "" "")) ; loop level
8307 (use (match_operand 4 "" "")) ; label
8308 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8311 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8312 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8313 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8314 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8315 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8316 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8323 (define_insn_and_split "doloop_si64"
8326 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8328 (label_ref (match_operand 0 "" ""))
8330 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8331 (plus:SI (match_dup 1) (const_int -1)))
8332 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8333 (clobber (reg:CC CC_REGNUM))]
8336 if (which_alternative != 0)
8338 else if (get_attr_length (insn) == 4)
8339 return "brct\t%1,%l0";
8341 return "ahi\t%1,-1\;jgne\t%l0";
8343 "&& reload_completed
8344 && (! REG_P (operands[2])
8345 || ! rtx_equal_p (operands[1], operands[2]))"
8346 [(set (match_dup 3) (match_dup 1))
8347 (parallel [(set (reg:CCAN CC_REGNUM)
8348 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8350 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8351 (set (match_dup 2) (match_dup 3))
8352 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8353 (label_ref (match_dup 0))
8356 [(set_attr "op_type" "RI")
8357 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8358 ; hurt us in the (rare) case of ahi.
8359 (set_attr "z10prop" "z10_super_E1")
8360 (set_attr "type" "branch")
8361 (set (attr "length")
8362 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8363 (const_int 4) (const_int 10)))])
8365 (define_insn_and_split "doloop_si31"
8368 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8370 (label_ref (match_operand 0 "" ""))
8372 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8373 (plus:SI (match_dup 1) (const_int -1)))
8374 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8375 (clobber (reg:CC CC_REGNUM))]
8378 if (which_alternative != 0)
8380 else if (get_attr_length (insn) == 4)
8381 return "brct\t%1,%l0";
8385 "&& reload_completed
8386 && (! REG_P (operands[2])
8387 || ! rtx_equal_p (operands[1], operands[2]))"
8388 [(set (match_dup 3) (match_dup 1))
8389 (parallel [(set (reg:CCAN CC_REGNUM)
8390 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8392 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8393 (set (match_dup 2) (match_dup 3))
8394 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8395 (label_ref (match_dup 0))
8398 [(set_attr "op_type" "RI")
8399 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8400 ; hurt us in the (rare) case of ahi.
8401 (set_attr "z10prop" "z10_super_E1")
8402 (set_attr "type" "branch")
8403 (set (attr "length")
8404 (if_then_else (not (match_test "flag_pic"))
8405 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8406 (const_int 4) (const_int 6))
8407 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8408 (const_int 4) (const_int 8))))])
8410 (define_insn "*doloop_si_long"
8413 (ne (match_operand:SI 1 "register_operand" "d")
8415 (match_operand 0 "address_operand" "ZQZR")
8417 (set (match_operand:SI 2 "register_operand" "=1")
8418 (plus:SI (match_dup 1) (const_int -1)))
8419 (clobber (match_scratch:SI 3 "=X"))
8420 (clobber (reg:CC CC_REGNUM))]
8423 if (get_attr_op_type (insn) == OP_TYPE_RR)
8424 return "bctr\t%1,%0";
8426 return "bct\t%1,%a0";
8428 [(set (attr "op_type")
8429 (if_then_else (match_operand 0 "register_operand" "")
8430 (const_string "RR") (const_string "RX")))
8431 (set_attr "type" "branch")
8432 (set_attr "atype" "agen")
8433 (set_attr "z10prop" "z10_c")
8434 (set_attr "z196prop" "z196_cracked")])
8436 (define_insn_and_split "doloop_di"
8439 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8441 (label_ref (match_operand 0 "" ""))
8443 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8444 (plus:DI (match_dup 1) (const_int -1)))
8445 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8446 (clobber (reg:CC CC_REGNUM))]
8449 if (which_alternative != 0)
8451 else if (get_attr_length (insn) == 4)
8452 return "brctg\t%1,%l0";
8454 return "aghi\t%1,-1\;jgne\t%l0";
8456 "&& reload_completed
8457 && (! REG_P (operands[2])
8458 || ! rtx_equal_p (operands[1], operands[2]))"
8459 [(set (match_dup 3) (match_dup 1))
8460 (parallel [(set (reg:CCAN CC_REGNUM)
8461 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8463 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8464 (set (match_dup 2) (match_dup 3))
8465 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8466 (label_ref (match_dup 0))
8469 [(set_attr "op_type" "RI")
8470 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8471 ; hurt us in the (rare) case of ahi.
8472 (set_attr "z10prop" "z10_super_E1")
8473 (set_attr "type" "branch")
8474 (set (attr "length")
8475 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8476 (const_int 4) (const_int 10)))])
8479 ;;- Unconditional jump instructions.
8483 ; jump instruction pattern(s).
8486 (define_expand "jump"
8487 [(match_operand 0 "" "")]
8489 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8491 (define_insn "*jump64"
8492 [(set (pc) (label_ref (match_operand 0 "" "")))]
8495 if (get_attr_length (insn) == 4)
8500 [(set_attr "op_type" "RI")
8501 (set_attr "type" "branch")
8502 (set (attr "length")
8503 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8504 (const_int 4) (const_int 6)))])
8506 (define_insn "*jump31"
8507 [(set (pc) (label_ref (match_operand 0 "" "")))]
8510 gcc_assert (get_attr_length (insn) == 4);
8513 [(set_attr "op_type" "RI")
8514 (set_attr "type" "branch")
8515 (set (attr "length")
8516 (if_then_else (not (match_test "flag_pic"))
8517 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8518 (const_int 4) (const_int 6))
8519 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8520 (const_int 4) (const_int 8))))])
8523 ; indirect-jump instruction pattern(s).
8526 (define_insn "indirect_jump"
8527 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8530 if (get_attr_op_type (insn) == OP_TYPE_RR)
8535 [(set (attr "op_type")
8536 (if_then_else (match_operand 0 "register_operand" "")
8537 (const_string "RR") (const_string "RX")))
8538 (set_attr "type" "branch")
8539 (set_attr "atype" "agen")])
8542 ; casesi instruction pattern(s).
8545 (define_insn "casesi_jump"
8546 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8547 (use (label_ref (match_operand 1 "" "")))]
8550 if (get_attr_op_type (insn) == OP_TYPE_RR)
8555 [(set (attr "op_type")
8556 (if_then_else (match_operand 0 "register_operand" "")
8557 (const_string "RR") (const_string "RX")))
8558 (set_attr "type" "branch")
8559 (set_attr "atype" "agen")])
8561 (define_expand "casesi"
8562 [(match_operand:SI 0 "general_operand" "")
8563 (match_operand:SI 1 "general_operand" "")
8564 (match_operand:SI 2 "general_operand" "")
8565 (label_ref (match_operand 3 "" ""))
8566 (label_ref (match_operand 4 "" ""))]
8569 rtx index = gen_reg_rtx (SImode);
8570 rtx base = gen_reg_rtx (Pmode);
8571 rtx target = gen_reg_rtx (Pmode);
8573 emit_move_insn (index, operands[0]);
8574 emit_insn (gen_subsi3 (index, index, operands[1]));
8575 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8578 if (Pmode != SImode)
8579 index = convert_to_mode (Pmode, index, 1);
8580 if (GET_CODE (index) != REG)
8581 index = copy_to_mode_reg (Pmode, index);
8584 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8586 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8588 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8590 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8591 emit_move_insn (target, index);
8594 target = gen_rtx_PLUS (Pmode, base, target);
8595 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8602 ;;- Jump to subroutine.
8607 ; untyped call instruction pattern(s).
8610 ;; Call subroutine returning any type.
8611 (define_expand "untyped_call"
8612 [(parallel [(call (match_operand 0 "" "")
8614 (match_operand 1 "" "")
8615 (match_operand 2 "" "")])]
8620 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8622 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8624 rtx set = XVECEXP (operands[2], 0, i);
8625 emit_move_insn (SET_DEST (set), SET_SRC (set));
8628 /* The optimizer does not know that the call sets the function value
8629 registers we stored in the result block. We avoid problems by
8630 claiming that all hard registers are used and clobbered at this
8632 emit_insn (gen_blockage ());
8637 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8638 ;; all of memory. This blocks insns from being moved across this point.
8640 (define_insn "blockage"
8641 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8644 [(set_attr "type" "none")
8645 (set_attr "length" "0")])
8651 (define_expand "sibcall"
8652 [(call (match_operand 0 "" "")
8653 (match_operand 1 "" ""))]
8656 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8660 (define_insn "*sibcall_br"
8661 [(call (mem:QI (reg SIBCALL_REGNUM))
8662 (match_operand 0 "const_int_operand" "n"))]
8663 "SIBLING_CALL_P (insn)
8664 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8666 [(set_attr "op_type" "RR")
8667 (set_attr "type" "branch")
8668 (set_attr "atype" "agen")])
8670 (define_insn "*sibcall_brc"
8671 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8672 (match_operand 1 "const_int_operand" "n"))]
8673 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8675 [(set_attr "op_type" "RI")
8676 (set_attr "type" "branch")])
8678 (define_insn "*sibcall_brcl"
8679 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8680 (match_operand 1 "const_int_operand" "n"))]
8681 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8683 [(set_attr "op_type" "RIL")
8684 (set_attr "type" "branch")])
8687 ; sibcall_value patterns
8690 (define_expand "sibcall_value"
8691 [(set (match_operand 0 "" "")
8692 (call (match_operand 1 "" "")
8693 (match_operand 2 "" "")))]
8696 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8700 (define_insn "*sibcall_value_br"
8701 [(set (match_operand 0 "" "")
8702 (call (mem:QI (reg SIBCALL_REGNUM))
8703 (match_operand 1 "const_int_operand" "n")))]
8704 "SIBLING_CALL_P (insn)
8705 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8707 [(set_attr "op_type" "RR")
8708 (set_attr "type" "branch")
8709 (set_attr "atype" "agen")])
8711 (define_insn "*sibcall_value_brc"
8712 [(set (match_operand 0 "" "")
8713 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8714 (match_operand 2 "const_int_operand" "n")))]
8715 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8717 [(set_attr "op_type" "RI")
8718 (set_attr "type" "branch")])
8720 (define_insn "*sibcall_value_brcl"
8721 [(set (match_operand 0 "" "")
8722 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8723 (match_operand 2 "const_int_operand" "n")))]
8724 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8726 [(set_attr "op_type" "RIL")
8727 (set_attr "type" "branch")])
8731 ; call instruction pattern(s).
8734 (define_expand "call"
8735 [(call (match_operand 0 "" "")
8736 (match_operand 1 "" ""))
8737 (use (match_operand 2 "" ""))]
8740 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8741 gen_rtx_REG (Pmode, RETURN_REGNUM));
8745 (define_insn "*bras"
8746 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8747 (match_operand 1 "const_int_operand" "n"))
8748 (clobber (match_operand 2 "register_operand" "=r"))]
8749 "!SIBLING_CALL_P (insn)
8750 && TARGET_SMALL_EXEC
8751 && GET_MODE (operands[2]) == Pmode"
8753 [(set_attr "op_type" "RI")
8754 (set_attr "type" "jsr")
8755 (set_attr "z196prop" "z196_cracked")])
8757 (define_insn "*brasl"
8758 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8759 (match_operand 1 "const_int_operand" "n"))
8760 (clobber (match_operand 2 "register_operand" "=r"))]
8761 "!SIBLING_CALL_P (insn)
8763 && GET_MODE (operands[2]) == Pmode"
8765 [(set_attr "op_type" "RIL")
8766 (set_attr "type" "jsr")
8767 (set_attr "z196prop" "z196_cracked")])
8769 (define_insn "*basr"
8770 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8771 (match_operand 1 "const_int_operand" "n"))
8772 (clobber (match_operand 2 "register_operand" "=r"))]
8773 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8775 if (get_attr_op_type (insn) == OP_TYPE_RR)
8776 return "basr\t%2,%0";
8778 return "bas\t%2,%a0";
8780 [(set (attr "op_type")
8781 (if_then_else (match_operand 0 "register_operand" "")
8782 (const_string "RR") (const_string "RX")))
8783 (set_attr "type" "jsr")
8784 (set_attr "atype" "agen")
8785 (set_attr "z196prop" "z196_cracked")])
8788 ; call_value instruction pattern(s).
8791 (define_expand "call_value"
8792 [(set (match_operand 0 "" "")
8793 (call (match_operand 1 "" "")
8794 (match_operand 2 "" "")))
8795 (use (match_operand 3 "" ""))]
8798 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8799 gen_rtx_REG (Pmode, RETURN_REGNUM));
8803 (define_insn "*bras_r"
8804 [(set (match_operand 0 "" "")
8805 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8806 (match_operand:SI 2 "const_int_operand" "n")))
8807 (clobber (match_operand 3 "register_operand" "=r"))]
8808 "!SIBLING_CALL_P (insn)
8809 && TARGET_SMALL_EXEC
8810 && GET_MODE (operands[3]) == Pmode"
8812 [(set_attr "op_type" "RI")
8813 (set_attr "type" "jsr")
8814 (set_attr "z196prop" "z196_cracked")])
8816 (define_insn "*brasl_r"
8817 [(set (match_operand 0 "" "")
8818 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8819 (match_operand 2 "const_int_operand" "n")))
8820 (clobber (match_operand 3 "register_operand" "=r"))]
8821 "!SIBLING_CALL_P (insn)
8823 && GET_MODE (operands[3]) == Pmode"
8825 [(set_attr "op_type" "RIL")
8826 (set_attr "type" "jsr")
8827 (set_attr "z196prop" "z196_cracked")])
8829 (define_insn "*basr_r"
8830 [(set (match_operand 0 "" "")
8831 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8832 (match_operand 2 "const_int_operand" "n")))
8833 (clobber (match_operand 3 "register_operand" "=r"))]
8834 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8836 if (get_attr_op_type (insn) == OP_TYPE_RR)
8837 return "basr\t%3,%1";
8839 return "bas\t%3,%a1";
8841 [(set (attr "op_type")
8842 (if_then_else (match_operand 1 "register_operand" "")
8843 (const_string "RR") (const_string "RX")))
8844 (set_attr "type" "jsr")
8845 (set_attr "atype" "agen")
8846 (set_attr "z196prop" "z196_cracked")])
8849 ;;- Thread-local storage support.
8852 (define_expand "get_thread_pointer<mode>"
8853 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8857 (define_expand "set_thread_pointer<mode>"
8858 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8859 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8863 (define_insn "*set_tp"
8864 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8867 [(set_attr "type" "none")
8868 (set_attr "length" "0")])
8870 (define_insn "*tls_load_64"
8871 [(set (match_operand:DI 0 "register_operand" "=d")
8872 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8873 (match_operand:DI 2 "" "")]
8877 [(set_attr "op_type" "RXE")
8878 (set_attr "z10prop" "z10_fwd_A3")])
8880 (define_insn "*tls_load_31"
8881 [(set (match_operand:SI 0 "register_operand" "=d,d")
8882 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8883 (match_operand:SI 2 "" "")]
8889 [(set_attr "op_type" "RX,RXY")
8890 (set_attr "type" "load")
8891 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8893 (define_insn "*bras_tls"
8894 [(set (match_operand 0 "" "")
8895 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8896 (match_operand 2 "const_int_operand" "n")))
8897 (clobber (match_operand 3 "register_operand" "=r"))
8898 (use (match_operand 4 "" ""))]
8899 "!SIBLING_CALL_P (insn)
8900 && TARGET_SMALL_EXEC
8901 && GET_MODE (operands[3]) == Pmode"
8903 [(set_attr "op_type" "RI")
8904 (set_attr "type" "jsr")
8905 (set_attr "z196prop" "z196_cracked")])
8907 (define_insn "*brasl_tls"
8908 [(set (match_operand 0 "" "")
8909 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8910 (match_operand 2 "const_int_operand" "n")))
8911 (clobber (match_operand 3 "register_operand" "=r"))
8912 (use (match_operand 4 "" ""))]
8913 "!SIBLING_CALL_P (insn)
8915 && GET_MODE (operands[3]) == Pmode"
8917 [(set_attr "op_type" "RIL")
8918 (set_attr "type" "jsr")
8919 (set_attr "z196prop" "z196_cracked")])
8921 (define_insn "*basr_tls"
8922 [(set (match_operand 0 "" "")
8923 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8924 (match_operand 2 "const_int_operand" "n")))
8925 (clobber (match_operand 3 "register_operand" "=r"))
8926 (use (match_operand 4 "" ""))]
8927 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8929 if (get_attr_op_type (insn) == OP_TYPE_RR)
8930 return "basr\t%3,%1%J4";
8932 return "bas\t%3,%a1%J4";
8934 [(set (attr "op_type")
8935 (if_then_else (match_operand 1 "register_operand" "")
8936 (const_string "RR") (const_string "RX")))
8937 (set_attr "type" "jsr")
8938 (set_attr "atype" "agen")
8939 (set_attr "z196prop" "z196_cracked")])
8942 ;;- Atomic operations
8946 ; memory barrier patterns.
8949 (define_expand "mem_signal_fence"
8950 [(match_operand:SI 0 "const_int_operand")] ;; model
8953 /* The s390 memory model is strong enough not to require any
8954 barrier in order to synchronize a thread with itself. */
8958 (define_expand "mem_thread_fence"
8959 [(match_operand:SI 0 "const_int_operand")] ;; model
8962 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8963 enough not to require barriers of any kind. */
8964 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8966 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8967 MEM_VOLATILE_P (mem) = 1;
8968 emit_insn (gen_mem_thread_fence_1 (mem));
8973 ; Although bcr is superscalar on Z10, this variant will never
8974 ; become part of an execution group.
8975 (define_insn "mem_thread_fence_1"
8976 [(set (match_operand:BLK 0 "" "")
8977 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8980 [(set_attr "op_type" "RR")])
8983 ; atomic load/store operations
8986 ; Atomic loads need not examine the memory model at all.
8987 (define_expand "atomic_load<mode>"
8988 [(match_operand:DINT 0 "register_operand") ;; output
8989 (match_operand:DINT 1 "memory_operand") ;; memory
8990 (match_operand:SI 2 "const_int_operand")] ;; model
8993 if (<MODE>mode == TImode)
8994 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8995 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8996 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8998 emit_move_insn (operands[0], operands[1]);
9002 ; Different from movdi_31 in that we want no splitters.
9003 (define_insn "atomic_loaddi_1"
9004 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9005 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9013 [(set_attr "op_type" "RS,RSY,RS,RSY")
9014 (set_attr "type" "lm,lm,floaddf,floaddf")])
9016 (define_insn "atomic_loadti_1"
9017 [(set (match_operand:TI 0 "register_operand" "=r")
9018 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9022 [(set_attr "op_type" "RXY")
9023 (set_attr "type" "other")])
9025 ; Atomic stores must(?) enforce sequential consistency.
9026 (define_expand "atomic_store<mode>"
9027 [(match_operand:DINT 0 "memory_operand") ;; memory
9028 (match_operand:DINT 1 "register_operand") ;; input
9029 (match_operand:SI 2 "const_int_operand")] ;; model
9032 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9034 if (<MODE>mode == TImode)
9035 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9036 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9037 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9039 emit_move_insn (operands[0], operands[1]);
9040 if (model == MEMMODEL_SEQ_CST)
9041 emit_insn (gen_mem_thread_fence (operands[2]));
9045 ; Different from movdi_31 in that we want no splitters.
9046 (define_insn "atomic_storedi_1"
9047 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9048 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9056 [(set_attr "op_type" "RS,RSY,RS,RSY")
9057 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9059 (define_insn "atomic_storeti_1"
9060 [(set (match_operand:TI 0 "memory_operand" "=RT")
9061 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9065 [(set_attr "op_type" "RXY")
9066 (set_attr "type" "other")])
9069 ; compare and swap patterns.
9072 (define_expand "atomic_compare_and_swap<mode>"
9073 [(match_operand:SI 0 "register_operand") ;; bool success output
9074 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9075 (match_operand:DGPR 2 "memory_operand") ;; memory
9076 (match_operand:DGPR 3 "register_operand") ;; expected intput
9077 (match_operand:DGPR 4 "register_operand") ;; newval intput
9078 (match_operand:SI 5 "const_int_operand") ;; is_weak
9079 (match_operand:SI 6 "const_int_operand") ;; success model
9080 (match_operand:SI 7 "const_int_operand")] ;; failure model
9083 rtx cc, cmp, output = operands[1];
9085 if (!register_operand (output, <MODE>mode))
9086 output = gen_reg_rtx (<MODE>mode);
9088 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9089 (output, operands[2], operands[3], operands[4]));
9091 /* We deliberately accept non-register operands in the predicate
9092 to ensure the write back to the output operand happens *before*
9093 the store-flags code below. This makes it easier for combine
9094 to merge the store-flags code with a potential test-and-branch
9095 pattern following (immediately!) afterwards. */
9096 if (output != operands[1])
9097 emit_move_insn (operands[1], output);
9099 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9100 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9101 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9105 (define_expand "atomic_compare_and_swap<mode>"
9106 [(match_operand:SI 0 "register_operand") ;; bool success output
9107 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9108 (match_operand:HQI 2 "memory_operand") ;; memory
9109 (match_operand:HQI 3 "general_operand") ;; expected intput
9110 (match_operand:HQI 4 "general_operand") ;; newval intput
9111 (match_operand:SI 5 "const_int_operand") ;; is_weak
9112 (match_operand:SI 6 "const_int_operand") ;; success model
9113 (match_operand:SI 7 "const_int_operand")] ;; failure model
9116 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9117 operands[3], operands[4], INTVAL (operands[5]));
9121 (define_expand "atomic_compare_and_swap<mode>_internal"
9123 [(set (match_operand:DGPR 0 "register_operand")
9124 (match_operand:DGPR 1 "memory_operand"))
9126 (unspec_volatile:DGPR
9128 (match_operand:DGPR 2 "register_operand")
9129 (match_operand:DGPR 3 "register_operand")]
9131 (set (reg:CCZ1 CC_REGNUM)
9132 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9136 (define_insn "*atomic_compare_and_swap<mode>_1"
9137 [(set (match_operand:TDI 0 "register_operand" "=r")
9138 (match_operand:TDI 1 "memory_operand" "+QS"))
9140 (unspec_volatile:TDI
9142 (match_operand:TDI 2 "register_operand" "0")
9143 (match_operand:TDI 3 "register_operand" "r")]
9145 (set (reg:CCZ1 CC_REGNUM)
9146 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9148 "c<td>sg\t%0,%3,%S1"
9149 [(set_attr "op_type" "RSY")
9150 (set_attr "type" "sem")])
9153 (define_insn "*atomic_compare_and_swapdi_2"
9154 [(set (match_operand:DI 0 "register_operand" "=r,r")
9155 (match_operand:DI 1 "memory_operand" "+Q,S"))
9159 (match_operand:DI 2 "register_operand" "0,0")
9160 (match_operand:DI 3 "register_operand" "r,r")]
9162 (set (reg:CCZ1 CC_REGNUM)
9163 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9168 [(set_attr "op_type" "RS,RSY")
9169 (set_attr "type" "sem")])
9172 (define_insn "*atomic_compare_and_swapsi_3"
9173 [(set (match_operand:SI 0 "register_operand" "=r,r")
9174 (match_operand:SI 1 "memory_operand" "+Q,S"))
9178 (match_operand:SI 2 "register_operand" "0,0")
9179 (match_operand:SI 3 "register_operand" "r,r")]
9181 (set (reg:CCZ1 CC_REGNUM)
9182 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9187 [(set_attr "op_type" "RS,RSY")
9188 (set_attr "type" "sem")])
9191 ; Other atomic instruction patterns.
9194 ; z196 load and add, xor, or and and instructions
9196 (define_expand "atomic_fetch_<atomic><mode>"
9197 [(match_operand:GPR 0 "register_operand") ;; val out
9199 (match_operand:GPR 1 "memory_operand") ;; memory
9200 (match_operand:GPR 2 "register_operand")) ;; val in
9201 (match_operand:SI 3 "const_int_operand")] ;; model
9204 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9205 (operands[0], operands[1], operands[2]));
9209 ; lan, lang, lao, laog, lax, laxg, laa, laag
9210 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9211 [(set (match_operand:GPR 0 "register_operand" "=d")
9212 (match_operand:GPR 1 "memory_operand" "+QS"))
9214 (unspec_volatile:GPR
9215 [(ATOMIC_Z196:GPR (match_dup 1)
9216 (match_operand:GPR 2 "general_operand" "d"))]
9218 (clobber (reg:CC CC_REGNUM))]
9220 "la<noxa><g>\t%0,%2,%1"
9221 [(set_attr "op_type" "RSY")
9222 (set_attr "type" "sem")])
9224 ;; For SImode and larger, the optabs.c code will do just fine in
9225 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9226 ;; better by expanding our own loop.
9228 (define_expand "atomic_<atomic><mode>"
9230 (match_operand:HQI 0 "memory_operand") ;; memory
9231 (match_operand:HQI 1 "general_operand")) ;; val in
9232 (match_operand:SI 2 "const_int_operand")] ;; model
9235 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9236 operands[1], false);
9240 (define_expand "atomic_fetch_<atomic><mode>"
9241 [(match_operand:HQI 0 "register_operand") ;; val out
9243 (match_operand:HQI 1 "memory_operand") ;; memory
9244 (match_operand:HQI 2 "general_operand")) ;; val in
9245 (match_operand:SI 3 "const_int_operand")] ;; model
9248 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9249 operands[2], false);
9253 (define_expand "atomic_<atomic>_fetch<mode>"
9254 [(match_operand:HQI 0 "register_operand") ;; val out
9256 (match_operand:HQI 1 "memory_operand") ;; memory
9257 (match_operand:HQI 2 "general_operand")) ;; val in
9258 (match_operand:SI 3 "const_int_operand")] ;; model
9261 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9266 (define_expand "atomic_exchange<mode>"
9267 [(match_operand:HQI 0 "register_operand") ;; val out
9268 (match_operand:HQI 1 "memory_operand") ;; memory
9269 (match_operand:HQI 2 "general_operand") ;; val in
9270 (match_operand:SI 3 "const_int_operand")] ;; model
9273 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9274 operands[2], false);
9279 ;;- Miscellaneous instructions.
9283 ; allocate stack instruction pattern(s).
9286 (define_expand "allocate_stack"
9287 [(match_operand 0 "general_operand" "")
9288 (match_operand 1 "general_operand" "")]
9291 rtx temp = gen_reg_rtx (Pmode);
9293 emit_move_insn (temp, s390_back_chain_rtx ());
9294 anti_adjust_stack (operands[1]);
9295 emit_move_insn (s390_back_chain_rtx (), temp);
9297 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9303 ; setjmp instruction pattern.
9306 (define_expand "builtin_setjmp_receiver"
9307 [(match_operand 0 "" "")]
9310 emit_insn (s390_load_got ());
9311 emit_use (pic_offset_table_rtx);
9315 ;; These patterns say how to save and restore the stack pointer. We need not
9316 ;; save the stack pointer at function level since we are careful to
9317 ;; preserve the backchain. At block level, we have to restore the backchain
9318 ;; when we restore the stack pointer.
9320 ;; For nonlocal gotos, we must save both the stack pointer and its
9321 ;; backchain and restore both. Note that in the nonlocal case, the
9322 ;; save area is a memory location.
9324 (define_expand "save_stack_function"
9325 [(match_operand 0 "general_operand" "")
9326 (match_operand 1 "general_operand" "")]
9330 (define_expand "restore_stack_function"
9331 [(match_operand 0 "general_operand" "")
9332 (match_operand 1 "general_operand" "")]
9336 (define_expand "restore_stack_block"
9337 [(match_operand 0 "register_operand" "")
9338 (match_operand 1 "register_operand" "")]
9341 rtx temp = gen_reg_rtx (Pmode);
9343 emit_move_insn (temp, s390_back_chain_rtx ());
9344 emit_move_insn (operands[0], operands[1]);
9345 emit_move_insn (s390_back_chain_rtx (), temp);
9350 (define_expand "save_stack_nonlocal"
9351 [(match_operand 0 "memory_operand" "")
9352 (match_operand 1 "register_operand" "")]
9355 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9357 /* Copy the backchain to the first word, sp to the second and the
9358 literal pool base to the third. */
9360 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9361 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9362 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9364 if (TARGET_BACKCHAIN)
9365 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9367 emit_move_insn (save_sp, operands[1]);
9368 emit_move_insn (save_bp, base);
9373 (define_expand "restore_stack_nonlocal"
9374 [(match_operand 0 "register_operand" "")
9375 (match_operand 1 "memory_operand" "")]
9378 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9379 rtx temp = NULL_RTX;
9381 /* Restore the backchain from the first word, sp from the second and the
9382 literal pool base from the third. */
9384 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9385 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9386 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9388 if (TARGET_BACKCHAIN)
9389 temp = force_reg (Pmode, save_bc);
9391 emit_move_insn (base, save_bp);
9392 emit_move_insn (operands[0], save_sp);
9395 emit_move_insn (s390_back_chain_rtx (), temp);
9401 (define_expand "exception_receiver"
9405 s390_set_has_landing_pad_p (true);
9410 ; nop instruction pattern(s).
9417 [(set_attr "op_type" "RR")
9418 (set_attr "z10prop" "z10_fr_E1")])
9424 [(set_attr "op_type" "RR")])
9428 ; Special literal pool access instruction pattern(s).
9431 (define_insn "*pool_entry"
9432 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9433 UNSPECV_POOL_ENTRY)]
9436 enum machine_mode mode = GET_MODE (PATTERN (insn));
9437 unsigned int align = GET_MODE_BITSIZE (mode);
9438 s390_output_pool_entry (operands[0], mode, align);
9441 [(set (attr "length")
9442 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9444 (define_insn "pool_align"
9445 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9446 UNSPECV_POOL_ALIGN)]
9449 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9451 (define_insn "pool_section_start"
9452 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9455 [(set_attr "length" "0")])
9457 (define_insn "pool_section_end"
9458 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9461 [(set_attr "length" "0")])
9463 (define_insn "main_base_31_small"
9464 [(set (match_operand 0 "register_operand" "=a")
9465 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9466 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9468 [(set_attr "op_type" "RR")
9469 (set_attr "type" "la")
9470 (set_attr "z196prop" "z196_cracked")])
9472 (define_insn "main_base_31_large"
9473 [(set (match_operand 0 "register_operand" "=a")
9474 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9475 (set (pc) (label_ref (match_operand 2 "" "")))]
9476 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9478 [(set_attr "op_type" "RI")
9479 (set_attr "z196prop" "z196_cracked")])
9481 (define_insn "main_base_64"
9482 [(set (match_operand 0 "register_operand" "=a")
9483 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9484 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9486 [(set_attr "op_type" "RIL")
9487 (set_attr "type" "larl")
9488 (set_attr "z10prop" "z10_fwd_A1")])
9490 (define_insn "main_pool"
9491 [(set (match_operand 0 "register_operand" "=a")
9492 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9493 "GET_MODE (operands[0]) == Pmode"
9498 (if_then_else (match_test "TARGET_CPU_ZARCH")
9499 (const_string "larl") (const_string "la")))])
9501 (define_insn "reload_base_31"
9502 [(set (match_operand 0 "register_operand" "=a")
9503 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9504 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9505 "basr\t%0,0\;la\t%0,%1-.(%0)"
9506 [(set_attr "length" "6")
9507 (set_attr "type" "la")
9508 (set_attr "z196prop" "z196_cracked")])
9510 (define_insn "reload_base_64"
9511 [(set (match_operand 0 "register_operand" "=a")
9512 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9513 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9515 [(set_attr "op_type" "RIL")
9516 (set_attr "type" "larl")
9517 (set_attr "z10prop" "z10_fwd_A1")])
9520 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9525 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9528 ;; Insns related to generating the function prologue and epilogue.
9532 (define_expand "prologue"
9533 [(use (const_int 0))]
9535 "s390_emit_prologue (); DONE;")
9537 (define_expand "epilogue"
9538 [(use (const_int 1))]
9540 "s390_emit_epilogue (false); DONE;")
9542 (define_expand "sibcall_epilogue"
9543 [(use (const_int 0))]
9545 "s390_emit_epilogue (true); DONE;")
9547 (define_insn "*return"
9549 (use (match_operand 0 "register_operand" "a"))]
9550 "GET_MODE (operands[0]) == Pmode"
9552 [(set_attr "op_type" "RR")
9553 (set_attr "type" "jsr")
9554 (set_attr "atype" "agen")])
9557 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9558 ;; pointer. This is used for compatibility.
9560 (define_expand "ptr_extend"
9561 [(set (match_operand:DI 0 "register_operand" "=r")
9562 (match_operand:SI 1 "register_operand" "r"))]
9565 emit_insn (gen_anddi3 (operands[0],
9566 gen_lowpart (DImode, operands[1]),
9567 GEN_INT (0x7fffffff)));
9571 ;; Instruction definition to expand eh_return macro to support
9572 ;; swapping in special linkage return addresses.
9574 (define_expand "eh_return"
9575 [(use (match_operand 0 "register_operand" ""))]
9578 s390_emit_tpf_eh_return (operands[0]);
9583 ; Stack Protector Patterns
9586 (define_expand "stack_protect_set"
9587 [(set (match_operand 0 "memory_operand" "")
9588 (match_operand 1 "memory_operand" ""))]
9591 #ifdef TARGET_THREAD_SSP_OFFSET
9593 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9594 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9597 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9599 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9604 (define_insn "stack_protect_set<mode>"
9605 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9606 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9608 "mvc\t%O0(%G0,%R0),%S1"
9609 [(set_attr "op_type" "SS")])
9611 (define_expand "stack_protect_test"
9612 [(set (reg:CC CC_REGNUM)
9613 (compare (match_operand 0 "memory_operand" "")
9614 (match_operand 1 "memory_operand" "")))
9615 (match_operand 2 "" "")]
9619 #ifdef TARGET_THREAD_SSP_OFFSET
9621 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9622 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9625 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9627 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9629 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9630 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9631 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9635 (define_insn "stack_protect_test<mode>"
9636 [(set (reg:CCZ CC_REGNUM)
9637 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9638 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9640 "clc\t%O0(%G0,%R0),%S1"
9641 [(set_attr "op_type" "SS")])
9643 ; This is used in s390_emit_prologue in order to prevent insns
9644 ; adjusting the stack pointer to be moved over insns writing stack
9645 ; slots using a copy of the stack pointer in a different register.
9646 (define_insn "stack_tie"
9647 [(set (match_operand:BLK 0 "memory_operand" "+m")
9648 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9651 [(set_attr "length" "0")])
9655 ; Data prefetch patterns
9658 (define_insn "prefetch"
9659 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9660 (match_operand:SI 1 "const_int_operand" " n,n")
9661 (match_operand:SI 2 "const_int_operand" " n,n"))]
9664 switch (which_alternative)
9667 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9669 if (larl_operand (operands[0], Pmode))
9670 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9673 /* This might be reached for symbolic operands with an odd
9674 addend. We simply omit the prefetch for such rare cases. */
9679 [(set_attr "type" "load,larl")
9680 (set_attr "op_type" "RXY,RIL")
9681 (set_attr "z10prop" "z10_super")
9682 (set_attr "z196prop" "z196_alone")])
9686 ; Byte swap instructions
9689 (define_insn "bswap<mode>2"
9690 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9691 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9696 [(set_attr "type" "*,load")
9697 (set_attr "op_type" "RRE,RXY")
9698 (set_attr "z10prop" "z10_super")])
9702 ; Population count instruction
9705 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9706 ; portions and stores the result in the corresponding bytes in op0.
9707 (define_insn "*popcount<mode>"
9708 [(set (match_operand:INT 0 "register_operand" "=d")
9709 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9710 (clobber (reg:CC CC_REGNUM))]
9713 [(set_attr "op_type" "RRE")])
9715 (define_expand "popcountdi2"
9717 (parallel [(set (match_operand:DI 0 "register_operand" "")
9718 (unspec:DI [(match_operand:DI 1 "register_operand")]
9720 (clobber (reg:CC CC_REGNUM))])
9722 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9724 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9725 (clobber (reg:CC CC_REGNUM))])
9728 (ashift:DI (match_dup 0) (const_int 16)))
9730 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9731 (clobber (reg:CC CC_REGNUM))])
9733 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9735 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9736 (clobber (reg:CC CC_REGNUM))])
9738 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9739 "TARGET_Z196 && TARGET_64BIT"
9740 "operands[2] = gen_reg_rtx (DImode);")
9742 (define_expand "popcountsi2"
9744 (parallel [(set (match_operand:SI 0 "register_operand" "")
9745 (unspec:SI [(match_operand:SI 1 "register_operand")]
9747 (clobber (reg:CC CC_REGNUM))])
9750 (ashift:SI (match_dup 0) (const_int 16)))
9752 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9753 (clobber (reg:CC CC_REGNUM))])
9755 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9757 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9758 (clobber (reg:CC CC_REGNUM))])
9760 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9762 "operands[2] = gen_reg_rtx (SImode);")
9764 (define_expand "popcounthi2"
9766 (parallel [(set (match_operand:HI 0 "register_operand" "")
9767 (unspec:HI [(match_operand:HI 1 "register_operand")]
9769 (clobber (reg:CC CC_REGNUM))])
9772 (ashift:SI (match_dup 0) (const_int 8)))
9774 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9775 (clobber (reg:CC CC_REGNUM))])
9777 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9779 "operands[2] = gen_reg_rtx (SImode);")
9781 (define_expand "popcountqi2"
9783 (parallel [(set (match_operand:QI 0 "register_operand" "")
9784 (unspec:QI [(match_operand:QI 1 "register_operand")]
9786 (clobber (reg:CC CC_REGNUM))])]
9791 ;;- Copy sign instructions
9794 (define_insn "copysign<mode>3"
9795 [(set (match_operand:FP 0 "register_operand" "=f")
9796 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9797 (match_operand:FP 2 "register_operand" "f")]
9801 [(set_attr "op_type" "RRF")
9802 (set_attr "type" "fsimp<mode>")])