gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com).
   5 ;; This file is part of GNU CC.
   6
   7 ;; GNU CC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11
  12 ;; GNU CC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GNU CC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22 ;;
  23 ;; Special constraints for s/390 machine description:
  24 ;;
  25 ;;    a -- Any address register from 1 to 15.
  26 ;;    d -- Any register from 0 to 15.
  27 ;;    I -- An 8-bit constant (0..255).
  28 ;;    J -- A 12-bit constant (0..4095).
  29 ;;    K -- A 16-bit constant (-32768..32767).
  30 ;;    Q -- A memory reference without index-register.
  31 ;;    S -- Valid operand for the LARL instruction.
  32 ;;
  33 ;; Special formats used for outputting 390 instructions.
  34 ;;
  35 ;;   %b -- Print a constant byte integer.               xy
  36 ;;   %h -- Print a signed 16-bit.                       wxyz
  37 ;;   %N -- Print next register (second word of a DImode reg) or next word.
  38 ;;   %M -- Print next register (second word of a TImode reg) or next word.
  39 ;;   %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
  40 ;;   %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
  41 ;;
  42 ;; We have a special constraint for pattern matching.
  43 ;;
  44 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  45 ;;
  46
  47
  48 ;; Define an insn type attribute.  This is used in function unit delay
  49 ;; computations.
  50
  51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
  52   (const_string "integer"))
  53
  54 ;; Insn are devide in two classes:
  55 ;;   mem: Insn accessing memory
  56 ;;   reg: Insn operands all in registers
  57
  58 (define_attr "atype" "reg,mem"
  59   (const_string "reg"))
  60
  61 ;; Generic pipeline function unit.
  62
  63 (define_function_unit "integer" 1 0
  64   (eq_attr "type" "none") 0 0)
  65
  66 (define_function_unit "integer" 1 0
  67   (eq_attr "type" "integer") 1 1)
  68
  69 (define_function_unit "integer" 1 0
  70   (eq_attr "type" "load") 1 1)
  71
  72 (define_function_unit "integer" 1 0
  73   (eq_attr "type" "la") 1 1)
  74
  75 (define_function_unit "integer" 1 0
  76   (eq_attr "type" "lr") 1 1)
  77
  78 (define_function_unit "integer" 1 0
  79   (eq_attr "type" "store") 1 1)
  80
  81 (define_function_unit "integer" 1 0
  82   (eq_attr "type" "lm") 2 2)
  83
  84 (define_function_unit "integer" 1 0
  85   (eq_attr "type" "stm") 2 2)
  86
  87 (define_function_unit "integer" 1 0
  88   (eq_attr "type" "cs") 5 5)
  89
  90 (define_function_unit "integer" 1 0
  91   (eq_attr "type" "vs") 30 30)
  92
  93 (define_function_unit "integer" 1 0
  94   (eq_attr "type" "jsr") 5 5)
  95
  96 (define_function_unit "integer" 1 0
  97   (eq_attr "type" "imul") 7 7)
  98
  99 (define_function_unit "integer" 1 0
 100   (eq_attr "type" "fmul") 6 6)
 101
 102 (define_function_unit "integer" 1 0
 103   (eq_attr "type" "idiv") 33 33)
 104
 105 (define_function_unit "integer" 1 0
 106   (eq_attr "type" "fdiv") 33 33)
 107
 108 (define_function_unit "integer" 1 0
 109   (eq_attr "type" "o2") 2 2)
 110
 111 (define_function_unit "integer" 1 0
 112   (eq_attr "type" "o3") 3 3)
 113
 114 (define_function_unit "integer" 1 0
 115   (eq_attr "type" "other") 5 5)
 116
 117 ;; Operand type. Used to default length attribute values
 118
 119 (define_attr "op_type"
 120   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
 121   (const_string "RX"))
 122
 123 ;; Length in bytes.
 124
 125 (define_attr "length" ""
 126 (cond [ (eq_attr "op_type" "E")    (const_int 2)
 127          (eq_attr "op_type" "RR")  (const_int 2)
 128          (eq_attr "op_type" "RX")  (const_int 4)
 129          (eq_attr "op_type" "RI")  (const_int 4)
 130          (eq_attr "op_type" "RRE") (const_int 4)
 131          (eq_attr "op_type" "RS")  (const_int 4)
 132          (eq_attr "op_type" "RSI") (const_int 4)
 133          (eq_attr "op_type" "RX")  (const_int 4)
 134          (eq_attr "op_type" "S")   (const_int 4)
 135          (eq_attr "op_type" "SI")  (const_int 4)
 136          (eq_attr "op_type" "SS")  (const_int 6)
 137          (eq_attr "op_type" "SSE") (const_int 6)
 138          (eq_attr "op_type" "RXE") (const_int 6)
 139          (eq_attr "op_type" "RSE") (const_int 6)
 140          (eq_attr "op_type" "RIL") (const_int 6)]
 141          (const_int 4)))
 142
 143 ;; Define attributes for `asm' insns.
 144
 145 (define_asm_attributes [(set_attr "type" "other")
 146                         (set_attr "op_type" "NN")])
 147
 148 ;;
 149 ;;  Condition Codes
 150 ;;
 151 ;
 152 ;   CCL:  Zero     Nonzero   Zero      Nonzero      (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
 153 ;   CCA:  Zero     <Zero     >Zero     Overflow     (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
 154 ;   CCU:  Equal    ULess     UGreater  --           (CL, CLR, CLI, CLM)
 155 ;   CCS:  Equal    SLess     SGreater  --           (C, CR, CH, CHI, ICM)
 156 ;   CCT:  Zero     Mixed     Mixed     Ones         (TM, TMH, TML)
 157
 158 ;   CCZ  -> CCL / CCZ1
 159 ;   CCZ1 -> CCA/CCU/CCS/CCT
 160 ;   CCS  -> CCA
 161
 162 ;   String:    CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
 163 ;   Clobber:   CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
 164
 165
 166 ;;
 167 ;;- Compare instructions.
 168 ;;
 169
 170 (define_expand "cmpdi"
 171   [(set (reg:CC 33)
 172         (compare:CC (match_operand:DI 0 "register_operand" "")
 173                     (match_operand:DI 1 "general_operand" "")))]
 174   "TARGET_64BIT"
 175   "
 176 {
 177   s390_compare_op0 = operands[0];
 178   s390_compare_op1 = operands[1];
 179   DONE;
 180 }")
 181
 182 (define_expand "cmpsi"
 183   [(set (reg:CC 33)
 184         (compare:CC (match_operand:SI 0 "register_operand" "")
 185                     (match_operand:SI 1 "general_operand" "")))]
 186   ""
 187   "
 188 {
 189   s390_compare_op0 = operands[0];
 190   s390_compare_op1 = operands[1];
 191   DONE;
 192 }")
 193
 194 (define_expand "cmpdf"
 195   [(set (reg:CC 33)
 196         (compare:CC (match_operand:DF 0 "register_operand" "")
 197                     (match_operand:DF 1 "general_operand" "")))]
 198   "TARGET_HARD_FLOAT"
 199   "
 200 {
 201   s390_compare_op0 = operands[0];
 202   s390_compare_op1 = operands[1];
 203   DONE;
 204 }")
 205
 206 (define_expand "cmpsf"
 207   [(set (reg:CC 33)
 208         (compare:CC (match_operand:SF 0 "register_operand" "")
 209                     (match_operand:SF 1 "general_operand" "")))]
 210   "TARGET_HARD_FLOAT"
 211   "
 212 {
 213   s390_compare_op0 = operands[0];
 214   s390_compare_op1 = operands[1];
 215   DONE;
 216 }")
 217
 218
 219 ; Test-under-Mask (zero_extract) instructions
 220
 221 (define_insn "*tmdi_ext"
 222   [(set (reg 33)
 223         (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
 224                                   (match_operand:DI 1 "const_int_operand" "n")
 225                                   (match_operand:DI 2 "const_int_operand" "n"))
 226                  (const_int 0)))]
 227   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
 228    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 229    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
 230    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
 231       == INTVAL (operands[2]) >> 4"
 232   "*
 233 {
 234   int part = INTVAL (operands[2]) >> 4;
 235   int block = (1 << INTVAL (operands[1])) - 1;
 236   int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
 237
 238   operands[2] = GEN_INT (block << shift);
 239
 240   switch (part)
 241     {
 242       case 0: return \"tmhh\\t%0,%x2\";
 243       case 1: return \"tmhl\\t%0,%x2\";
 244       case 2: return \"tmlh\\t%0,%x2\";
 245       case 3: return \"tmll\\t%0,%x2\";
 246       default: abort ();
 247     }
 248 }"
 249   [(set_attr "op_type" "RI")])
 250
 251 (define_insn "*tmsi_ext"
 252   [(set (reg 33)
 253         (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
 254                                   (match_operand:SI 1 "const_int_operand" "n")
 255                                   (match_operand:SI 2 "const_int_operand" "n"))
 256                  (const_int 0)))]
 257   "s390_match_ccmode(insn, CCTmode)
 258    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 259    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
 260    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
 261       == INTVAL (operands[2]) >> 4"
 262   "*
 263 {
 264   int part = INTVAL (operands[2]) >> 4;
 265   int block = (1 << INTVAL (operands[1])) - 1;
 266   int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
 267
 268   operands[2] = GEN_INT (block << shift);
 269
 270   switch (part)
 271     {
 272       case 0: return \"tmh\\t%0,%x2\";
 273       case 1: return \"tml\\t%0,%x2\";
 274       default: abort ();
 275     }
 276 }"
 277   [(set_attr "op_type" "RI")])
 278
 279 (define_insn "*tmqi_ext"
 280   [(set (reg 33)
 281         (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
 282                                   (match_operand:SI 1 "const_int_operand" "n")
 283                                   (match_operand:SI 2 "const_int_operand" "n"))
 284                  (const_int 0)))]
 285   "s390_match_ccmode(insn, CCTmode)
 286    && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
 287    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
 288   "*
 289 {
 290   int block = (1 << INTVAL (operands[1])) - 1;
 291   int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
 292
 293   operands[2] = GEN_INT (block << shift);
 294   return \"tm\\t%0,%b2\";
 295 }"
 296   [(set_attr "op_type" "SI")
 297    (set_attr "atype"   "mem")])
 298
 299 ; Test-under-Mask instructions
 300
 301 (define_insn "*tmdi_mem"
 302   [(set (reg 33)
 303         (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
 304                          (match_operand:DI 1 "immediate_operand" "n"))
 305                  (match_operand:DI 2 "immediate_operand" "n")))]
 306   "TARGET_64BIT
 307    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
 308    && s390_single_qi (operands[1], DImode, 0) >= 0"
 309   "*
 310 {
 311   int part = s390_single_qi (operands[1], DImode, 0);
 312   operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
 313
 314   operands[0] = gen_rtx_MEM (QImode,
 315                              plus_constant (XEXP (operands[0], 0), part));
 316   return \"tm\\t%0,%b1\";
 317 }"
 318   [(set_attr "op_type" "SI")
 319    (set_attr "atype"   "mem")])
 320
 321 (define_insn "*tmsi_mem"
 322   [(set (reg 33)
 323         (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
 324                          (match_operand:SI 1 "immediate_operand" "n"))
 325                  (match_operand:SI 2 "immediate_operand" "n")))]
 326   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
 327    && s390_single_qi (operands[1], SImode, 0) >= 0"
 328   "*
 329 {
 330   int part = s390_single_qi (operands[1], SImode, 0);
 331   operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
 332
 333   operands[0] = gen_rtx_MEM (QImode,
 334                              plus_constant (XEXP (operands[0], 0), part));
 335   return \"tm\\t%0,%b1\";
 336 }"
 337   [(set_attr "op_type" "SI")
 338    (set_attr "atype"   "mem")])
 339
 340 (define_insn "*tmhi_mem"
 341   [(set (reg 33)
 342         (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
 343                          (match_operand:SI 1 "immediate_operand" "n"))
 344                  (match_operand:SI 2 "immediate_operand" "n")))]
 345   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
 346    && s390_single_qi (operands[1], HImode, 0) >= 0"
 347   "*
 348 {
 349   int part = s390_single_qi (operands[1], HImode, 0);
 350   operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
 351
 352   operands[0] = gen_rtx_MEM (QImode,
 353                              plus_constant (XEXP (operands[0], 0), part));
 354   return \"tm\\t%0,%b1\";
 355 }"
 356   [(set_attr "op_type" "SI")
 357    (set_attr "atype"   "mem")])
 358
 359 (define_insn "*tmqi_mem"
 360   [(set (reg 33)
 361         (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
 362                          (match_operand:SI 1 "immediate_operand" "n"))
 363                  (match_operand:SI 2 "immediate_operand" "n")))]
 364   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
 365   "tm\\t%0,%b1"
 366   [(set_attr "op_type" "SI")
 367    (set_attr "atype"   "mem")])
 368
 369 (define_insn "*tmdi_reg"
 370   [(set (reg 33)
 371         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
 372                          (match_operand:DI 1 "immediate_operand" "n"))
 373                  (match_operand:DI 2 "immediate_operand" "n")))]
 374   "TARGET_64BIT
 375    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
 376    && s390_single_hi (operands[1], DImode, 0) >= 0"
 377   "*
 378 {
 379   int part = s390_single_hi (operands[1], DImode, 0);
 380   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 381
 382   switch (part)
 383     {
 384       case 0: return \"tmhh\\t%0,%x1\";
 385       case 1: return \"tmhl\\t%0,%x1\";
 386       case 2: return \"tmlh\\t%0,%x1\";
 387       case 3: return \"tmll\\t%0,%x1\";
 388       default: abort ();
 389     }
 390 }"
 391   [(set_attr "op_type" "RI")])
 392
 393 (define_insn "*tmsi_reg"
 394   [(set (reg 33)
 395         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
 396                          (match_operand:SI 1 "immediate_operand" "n"))
 397                  (match_operand:SI 2 "immediate_operand" "n")))]
 398   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
 399    && s390_single_hi (operands[1], SImode, 0) >= 0"
 400   "*
 401 {
 402   int part = s390_single_hi (operands[1], SImode, 0);
 403   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
 404
 405   switch (part)
 406     {
 407       case 0: return \"tmh\\t%0,%x1\";
 408       case 1: return \"tml\\t%0,%x1\";
 409       default: abort ();
 410     }
 411 }"
 412   [(set_attr "op_type" "RI")])
 413
 414 (define_insn "*tmhi_full"
 415   [(set (reg 33)
 416         (compare (match_operand:HI 0 "register_operand" "d")
 417                  (match_operand:HI 1 "immediate_operand" "n")))]
 418   "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
 419   "tml\\t%0,65535"
 420   [(set_attr "op_type" "RX")])
 421
 422 (define_insn "*tmqi_full"
 423   [(set (reg 33)
 424         (compare (match_operand:QI 0 "register_operand" "d")
 425                  (match_operand:QI 1 "immediate_operand" "n")))]
 426   "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
 427   "tml\\t%0,255"
 428   [(set_attr "op_type" "RI")])
 429
 430
 431 ; Load-and-Test instructions
 432
 433 (define_insn "*tstdi_sign"
 434   [(set (reg 33)
 435         (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
 436                                          (const_int 32)) (const_int 32))
 437                  (match_operand:DI 1 "const0_operand" "")))
 438    (set (match_operand:DI 2 "register_operand" "=d")
 439         (sign_extend:DI (match_dup 0)))]
 440   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 441   "ltgfr\\t%2,%0"
 442   [(set_attr "op_type" "RRE")])
 443
 444 (define_insn "*tstdi"
 445   [(set (reg 33)
 446         (compare (match_operand:DI 0 "register_operand" "d")
 447                  (match_operand:DI 1 "const0_operand" "")))
 448    (set (match_operand:DI 2 "register_operand" "=d")
 449         (match_dup 0))]
 450   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 451   "ltgr\\t%2,%0"
 452   [(set_attr "op_type" "RRE")])
 453
 454 (define_insn "*tstdi_cconly"
 455   [(set (reg 33)
 456         (compare (match_operand:DI 0 "register_operand" "d")
 457                  (match_operand:DI 1 "const0_operand" "")))]
 458   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 459   "ltgr\\t%0,%0"
 460   [(set_attr "op_type" "RRE")])
 461
 462 (define_insn "*tstdi_cconly_31"
 463   [(set (reg 33)
 464         (compare (match_operand:DI 0 "register_operand" "d")
 465                  (match_operand:DI 1 "const0_operand" "")))]
 466   "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
 467   "srda\\t%0,0"
 468   [(set_attr "op_type" "RS")])
 469
 470 (define_insn "*tstsi"
 471   [(set (reg 33)
 472         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
 473                  (match_operand:SI 1 "const0_operand" "")))
 474    (set (match_operand:SI 2 "register_operand" "=d,d")
 475         (match_dup 0))]
 476   "s390_match_ccmode(insn, CCSmode)"
 477   "@
 478    ltr\\t%2,%0
 479    icm\\t%2,15,%0"
 480   [(set_attr "op_type" "RR,RS")
 481    (set_attr "atype"   "reg,mem")])
 482
 483 (define_insn "*tstsi_cconly"
 484   [(set (reg 33)
 485         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
 486                  (match_operand:SI 1 "const0_operand" "")))
 487    (clobber (match_scratch:SI 2 "=X,d"))]
 488   "s390_match_ccmode(insn, CCSmode)"
 489   "@
 490    ltr\\t%0,%0
 491    icm\\t%2,15,%0"
 492   [(set_attr "op_type" "RR,RS")
 493    (set_attr "atype"   "reg,mem")])
 494
 495 (define_insn "*tstsi_cconly2"
 496   [(set (reg 33)
 497         (compare (match_operand:SI 0 "register_operand" "d")
 498                  (match_operand:SI 1 "const0_operand" "")))]
 499   "s390_match_ccmode(insn, CCSmode)"
 500   "ltr\\t%0,%0"
 501   [(set_attr "op_type" "RR")])
 502
 503 (define_insn "*tsthi"
 504   [(set (reg 33)
 505         (compare (match_operand:HI 0 "s_operand" "Q")
 506                  (match_operand:HI 1 "const0_operand" "")))
 507    (set (match_operand:HI 2 "register_operand" "=d")
 508         (match_dup 0))]
 509   "s390_match_ccmode(insn, CCSmode)"
 510   "icm\\t%2,3,%0"
 511   [(set_attr "op_type" "RS")
 512    (set_attr "atype"   "mem")])
 513
 514 (define_insn "*tsthi_cconly"
 515   [(set (reg 33)
 516         (compare (match_operand:HI 0 "s_operand" "Q")
 517                  (match_operand:HI 1 "const0_operand" "")))
 518    (clobber (match_scratch:HI 2 "=d"))]
 519   "s390_match_ccmode(insn, CCSmode)"
 520   "icm\\t%2,3,%0"
 521   [(set_attr "op_type" "RS")
 522    (set_attr "atype"   "mem")])
 523
 524 (define_insn "*tstqi"
 525   [(set (reg 33)
 526         (compare (match_operand:QI 0 "s_operand" "Q")
 527                  (match_operand:QI 1 "const0_operand" "")))
 528    (set (match_operand:QI 2 "register_operand" "=d")
 529         (match_dup 0))]
 530   "s390_match_ccmode(insn, CCSmode)"
 531   "icm\\t%2,1,%0"
 532   [(set_attr "op_type" "RS")
 533    (set_attr "atype"   "mem")])
 534
 535 (define_insn "*tstqi_cconly"
 536   [(set (reg 33)
 537         (compare (match_operand:QI 0 "s_operand" "Q")
 538                  (match_operand:QI 1 "const0_operand" "")))
 539    (clobber (match_scratch:QI 2 "=d"))]
 540   "s390_match_ccmode(insn, CCSmode)"
 541   "icm\\t%2,1,%0"
 542   [(set_attr "op_type" "RS")
 543    (set_attr "atype"   "mem")])
 544
 545
 546 ; Compare (signed) instructions
 547
 548 (define_insn "*cmpdi_ccs_sign"
 549   [(set (reg 33)
 550         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
 551                  (match_operand:DI 0 "register_operand" "d,d")))]
 552   "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
 553   "@
 554    cgfr\\t%0,%1
 555    cgf\\t%0,%1"
 556   [(set_attr "op_type" "RRE,RXE")
 557    (set_attr "atype"   "reg,mem")])
 558
 559 (define_insn "*cmpdi_ccs"
 560   [(set (reg 33)
 561         (compare (match_operand:DI 0 "register_operand" "d,d,d")
 562                  (match_operand:DI 1 "general_operand" "d,K,m")))]
 563   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
 564   "@
 565    cgr\\t%0,%1
 566    cghi\\t%0,%c1
 567    cg\\t%0,%1"
 568   [(set_attr "op_type" "RRE,RI,RXE")
 569    (set_attr "atype"    "reg,reg,mem")])
 570
 571 (define_insn "*cmpsi_ccs_sign"
 572   [(set (reg 33)
 573         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
 574                  (match_operand:SI 0 "register_operand" "d")))]
 575   "s390_match_ccmode(insn, CCSRmode)"
 576   "ch\\t%0,%1"
 577   [(set_attr "op_type" "RX")
 578    (set_attr "atype"   "mem")])
 579
 580 (define_insn "*cmpsi_ccs"
 581   [(set (reg 33)
 582         (compare (match_operand:SI 0 "register_operand" "d,d,d")
 583                  (match_operand:SI 1 "general_operand" "d,K,m")))]
 584   "s390_match_ccmode(insn, CCSmode)"
 585   "@
 586    cr\\t%0,%1
 587    chi\\t%0,%c1
 588    c\\t%0,%1"
 589   [(set_attr "op_type" "RR,RI,RX")
 590    (set_attr "atype"   "reg,reg,mem")])
 591
 592
 593 ; Compare (unsigned) instructions
 594
 595 (define_insn "*cmpdi_ccu_zero"
 596   [(set (reg 33)
 597         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
 598                  (match_operand:DI 0 "register_operand" "d,d")))]
 599   "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
 600   "@
 601    clgfr\\t%0,%1
 602    clgf\\t%0,%1"
 603   [(set_attr "op_type" "RRE,RXE")
 604    (set_attr "atype"   "reg,mem")])
 605
 606 (define_insn "*cmpdi_ccu"
 607   [(set (reg 33)
 608         (compare (match_operand:DI 0 "register_operand" "d,d")
 609                  (match_operand:DI 1 "general_operand" "d,m")))]
 610   "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
 611   "@
 612    clgr\\t%0,%1
 613    clg\\t%0,%1"
 614   [(set_attr "op_type" "RRE,RXE")
 615    (set_attr "atype"   "reg,mem")])
 616
 617 (define_insn "*cmpsi_ccu"
 618   [(set (reg 33)
 619         (compare (match_operand:SI 0 "register_operand" "d,d")
 620                  (match_operand:SI 1 "general_operand" "d,m")))]
 621   "s390_match_ccmode(insn, CCUmode)"
 622   "@
 623    clr\\t%0,%1
 624    cl\\t%0,%1"
 625   [(set_attr "op_type" "RR,RX")
 626    (set_attr "atype"   "reg,mem")])
 627
 628 (define_insn "*cmphi_ccu"
 629   [(set (reg 33)
 630         (compare (match_operand:HI 0 "register_operand" "d")
 631                  (match_operand:HI 1 "s_imm_operand" "Q")))]
 632   "s390_match_ccmode(insn, CCUmode)"
 633   "clm\\t%0,3,%1"
 634   [(set_attr "op_type" "RS")
 635    (set_attr "atype"   "mem")])
 636
 637 (define_insn "*cmpqi_ccu"
 638   [(set (reg 33)
 639         (compare (match_operand:QI 0 "register_operand" "d")
 640                  (match_operand:QI 1 "s_imm_operand" "Q")))]
 641   "s390_match_ccmode(insn, CCUmode)"
 642   "clm\\t%0,1,%1"
 643   [(set_attr "op_type" "RS")
 644    (set_attr "atype"   "mem")])
 645
 646 (define_insn "*cli"
 647   [(set (reg 33)
 648         (compare (match_operand:QI 0 "memory_operand" "Q")
 649                  (match_operand:QI 1 "immediate_operand" "n")))]
 650   "s390_match_ccmode (insn, CCUmode)"
 651   "cli\\t%0,%b1"
 652   [(set_attr "op_type" "SI")
 653    (set_attr "atype"   "mem")])
 654
 655 (define_insn "*cmpdi_ccu_mem"
 656   [(set (reg 33)
 657         (compare (match_operand:DI 0 "s_operand" "Q")
 658                  (match_operand:DI 1 "s_imm_operand" "Q")))]
 659   "s390_match_ccmode(insn, CCUmode)"
 660   "clc\\t%O0(8,%R0),%1"
 661   [(set_attr "op_type" "SS")
 662    (set_attr "atype"   "mem")])
 663
 664 (define_insn "*cmpsi_ccu_mem"
 665   [(set (reg 33)
 666         (compare (match_operand:SI 0 "s_operand" "Q")
 667                  (match_operand:SI 1 "s_imm_operand" "Q")))]
 668   "s390_match_ccmode(insn, CCUmode)"
 669   "clc\\t%O0(4,%R0),%1"
 670    [(set_attr "op_type" "SS")
 671     (set_attr "atype"   "mem")])
 672
 673 (define_insn "*cmphi_ccu_mem"
 674   [(set (reg 33)
 675         (compare (match_operand:HI 0 "s_operand" "Q")
 676                  (match_operand:HI 1 "s_imm_operand" "Q")))]
 677   "s390_match_ccmode(insn, CCUmode)"
 678   "clc\\t%O0(2,%R0),%1"
 679   [(set_attr "op_type" "SS")
 680    (set_attr "atype"   "mem")])
 681
 682 (define_insn "*cmpqi_ccu_mem"
 683   [(set (reg 33)
 684         (compare (match_operand:QI 0 "s_operand" "Q")
 685                  (match_operand:QI 1 "s_imm_operand" "Q")))]
 686   "s390_match_ccmode(insn, CCUmode)"
 687   "clc\\t%O0(1,%R0),%1"
 688   [(set_attr "op_type" "SS")
 689    (set_attr "atype"   "mem")])
 690
 691
 692 ; DF instructions
 693
 694 (define_insn "*cmpdf_ccs_0"
 695   [(set (reg 33)
 696         (compare (match_operand:DF 0 "register_operand" "f")
 697                  (match_operand:DF 1 "const0_operand" "")))]
 698   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 699   "ltdbr\\t%0,%0"
 700    [(set_attr "op_type" "RRE")])
 701
 702 (define_insn "*cmpdf_ccs_0_ibm"
 703   [(set (reg 33)
 704         (compare (match_operand:DF 0 "register_operand" "f")
 705                  (match_operand:DF 1 "const0_operand" "")))]
 706   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 707   "ltdr\\t%0,%0"
 708    [(set_attr "op_type" "RR")])
 709
 710 (define_insn "*cmpdf_ccs"
 711   [(set (reg 33)
 712         (compare (match_operand:DF 0 "register_operand" "f,f")
 713                  (match_operand:DF 1 "general_operand" "f,m")))]
 714   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 715   "@
 716    cdbr\\t%0,%1
 717    cdb\\t%0,%1"
 718    [(set_attr "op_type" "RRE,RXE")
 719     (set_attr "atype"   "reg,mem")])
 720
 721 (define_insn "*cmpdf_ccs_ibm"
 722   [(set (reg 33)
 723         (compare (match_operand:DF 0 "register_operand" "f,f")
 724                  (match_operand:DF 1 "general_operand" "f,m")))]
 725   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 726   "@
 727    cdr\\t%0,%1
 728    cd\\t%0,%1"
 729    [(set_attr "op_type" "RR,RX")
 730     (set_attr "atype"   "reg,mem")])
 731
 732
 733 ; SF instructions
 734
 735 (define_insn "*cmpsf_ccs_0"
 736   [(set (reg 33)
 737         (compare (match_operand:SF 0 "register_operand" "f")
 738                  (match_operand:SF 1 "const0_operand" "")))]
 739   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 740   "ltebr\\t%0,%0"
 741    [(set_attr "op_type" "RRE")])
 742
 743 (define_insn "*cmpsf_ccs_0_ibm"
 744   [(set (reg 33)
 745         (compare (match_operand:SF 0 "register_operand" "f")
 746                  (match_operand:SF 1 "const0_operand" "")))]
 747   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 748   "lter\\t%0,%0"
 749    [(set_attr "op_type" "RR")])
 750
 751 (define_insn "*cmpsf_ccs"
 752   [(set (reg 33)
 753         (compare (match_operand:SF 0 "register_operand" "f,f")
 754                  (match_operand:SF 1 "general_operand" "f,m")))]
 755   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 756   "@
 757    cebr\\t%0,%1
 758    ceb\\t%0,%1"
 759   [(set_attr "op_type" "RRE,RXE")
 760    (set_attr "atype"   "reg,mem")])
 761
 762 (define_insn "*cmpsf_ccs"
 763   [(set (reg 33)
 764         (compare (match_operand:SF 0 "register_operand" "f,f")
 765                  (match_operand:SF 1 "general_operand" "f,m")))]
 766   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
 767   "@
 768    cer\\t%0,%1
 769    ce\\t%0,%1"
 770   [(set_attr "op_type" "RR,RX")
 771    (set_attr "atype"   "reg,mem")])
 772
 773
 774 ;;
 775 ;;- Move instructions.
 776 ;;
 777
 778 ;
 779 ; movti instruction pattern(s).
 780 ;
 781
 782 (define_insn "movti"
 783   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
 784         (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
 785   "TARGET_64BIT"
 786   "@
 787    lmg\\t%0,%N0,%1
 788    stmg\\t%1,%N1,%0
 789    #
 790    #
 791    mvc\\t%O0(16,%R0),%1"
 792   [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
 793    (set_attr "atype"   "mem")])
 794
 795 (define_split
 796   [(set (match_operand:TI 0 "nonimmediate_operand" "")
 797         (match_operand:TI 1 "general_operand" ""))]
 798   "TARGET_64BIT && reload_completed
 799    && !s_operand (operands[0], VOIDmode)
 800    && !s_operand (operands[1], VOIDmode)
 801    && (register_operand (operands[0], VOIDmode)
 802        || register_operand (operands[1], VOIDmode))
 803    && (!register_operand (operands[0], VOIDmode)
 804        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
 805                                     operands[1])
 806        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
 807                                     operands[1]))"
 808   [(set (match_dup 2) (match_dup 4))
 809    (set (match_dup 3) (match_dup 5))]
 810   "
 811 {
 812   if (!register_operand (operands[0], VOIDmode)
 813       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
 814                                    operands[1]))
 815     {
 816       operands[2] = operand_subword (operands[0], 0, 0, TImode);
 817       operands[3] = operand_subword (operands[0], 1, 0, TImode);
 818       operands[4] = operand_subword (operands[1], 0, 0, TImode);
 819       operands[5] = operand_subword (operands[1], 1, 0, TImode);
 820     }
 821   else
 822     {
 823       operands[2] = operand_subword (operands[0], 1, 0, TImode);
 824       operands[3] = operand_subword (operands[0], 0, 0, TImode);
 825       operands[4] = operand_subword (operands[1], 1, 0, TImode);
 826       operands[5] = operand_subword (operands[1], 0, 0, TImode);
 827     }
 828 }")
 829
 830 (define_split
 831   [(set (match_operand:TI 0 "register_operand" "")
 832         (match_operand:TI 1 "memory_operand" ""))]
 833   "TARGET_64BIT && reload_completed
 834    && !s_operand (operands[1], VOIDmode)"
 835   [(set (match_dup 0) (match_dup 1))]
 836   "
 837 {
 838   rtx addr = operand_subword (operands[0], 1, 0, TImode);
 839   s390_load_address (addr, XEXP (operands[1], 0));
 840   operands[1] = replace_equiv_address (operands[1], addr);
 841 }")
 842
 843 ;
 844 ; movdi instruction pattern(s).
 845 ;
 846
 847 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
 848 ;; move to get the address of the symbolic object from the GOT.
 849
 850 (define_expand "movdi"
 851   [(set (match_operand:DI 0 "general_operand" "")
 852         (match_operand:DI 1 "general_operand" ""))]
 853   ""
 854   "
 855 {
 856   /* Handle PIC symbolic constants.  */
 857   if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
 858     emit_pic_move (operands, DImode);
 859
 860   /* During and after reload, we need to force constants
 861      to the literal pool ourselves, if necessary.  */
 862   if ((reload_in_progress || reload_completed)
 863       && CONSTANT_P (operands[1])
 864       && (!legitimate_reload_constant_p (operands[1])
 865           || fp_operand (operands[0], VOIDmode)))
 866     operands[1] = force_const_mem (DImode, operands[1]);
 867 }")
 868
 869 (define_insn "*movdi_lhi"
 870   [(set (match_operand:DI 0 "register_operand" "=d")
 871         (match_operand:DI 1 "immediate_operand" "K"))]
 872   "TARGET_64BIT
 873    && GET_CODE (operands[1]) == CONST_INT
 874    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
 875    && !fp_operand (operands[0], VOIDmode)"
 876   "lghi\\t%0,%h1"
 877   [(set_attr "op_type" "RI")
 878    (set_attr "atype"   "reg")])
 879
 880 (define_insn "*movdi_lli"
 881   [(set (match_operand:DI 0 "register_operand" "=d")
 882         (match_operand:DI 1 "immediate_operand" "n"))]
 883   "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
 884    && !fp_operand (operands[0], VOIDmode)"
 885   "*
 886 {
 887   int part = s390_single_hi (operands[1], DImode, 0);
 888   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 889
 890   switch (part)
 891     {
 892       case 0: return \"llihh\\t%0,%x1\";
 893       case 1: return \"llihl\\t%0,%x1\";
 894       case 2: return \"llilh\\t%0,%x1\";
 895       case 3: return \"llill\\t%0,%x1\";
 896       default: abort ();
 897     }
 898 }"
 899   [(set_attr "op_type" "RI")
 900    (set_attr "atype"   "reg")])
 901
 902 (define_insn "*movdi_larl"
 903   [(set (match_operand:DI 0 "register_operand" "=d")
 904         (match_operand:DI 1 "larl_operand" "X"))]
 905   "TARGET_64BIT
 906    && !fp_operand (operands[0], VOIDmode)"
 907   "larl\\t%0,%1"
 908    [(set_attr "op_type" "RIL")
 909     (set_attr "atype"   "reg")
 910     (set_attr "type"    "la")])
 911
 912 (define_insn "*movdi_64"
 913   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
 914         (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
 915   "TARGET_64BIT"
 916   "@
 917    lgr\\t%0,%1
 918    lg\\t%0,%1
 919    stg\\t%1,%0
 920    ldr\\t%0,%1
 921    ld\\t%0,%1
 922    std\\t%1,%0
 923    mvc\\t%O0(8,%R0),%1"
 924   [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX,SS")
 925    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
 926
 927 (define_insn "*movdi_31"
 928   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
 929         (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
 930   "!TARGET_64BIT"
 931   "@
 932    lm\\t%0,%N0,%1
 933    stm\\t%1,%N1,%0
 934    #
 935    #
 936    ldr\\t%0,%1
 937    ld\\t%0,%1
 938    std\\t%1,%0
 939    mvc\\t%O0(8,%R0),%1"
 940   [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
 941    (set_attr "atype"   "mem,mem,*,*,reg,mem,mem,mem")])
 942
 943 (define_split
 944   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 945         (match_operand:DI 1 "general_operand" ""))]
 946   "!TARGET_64BIT && reload_completed
 947    && !fp_operand (operands[0], VOIDmode)
 948    && !fp_operand (operands[1], VOIDmode)
 949    && !s_operand (operands[0], VOIDmode)
 950    && !s_operand (operands[1], VOIDmode)
 951    && (register_operand (operands[0], VOIDmode)
 952        || register_operand (operands[1], VOIDmode))
 953    && (!register_operand (operands[0], VOIDmode)
 954        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
 955                                     operands[1])
 956        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
 957                                     operands[1]))"
 958   [(set (match_dup 2) (match_dup 4))
 959    (set (match_dup 3) (match_dup 5))]
 960   "
 961 {
 962   if (!register_operand (operands[0], VOIDmode)
 963       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
 964                                    operands[1]))
 965     {
 966       operands[2] = operand_subword (operands[0], 0, 0, DImode);
 967       operands[3] = operand_subword (operands[0], 1, 0, DImode);
 968       operands[4] = operand_subword (operands[1], 0, 0, DImode);
 969       operands[5] = operand_subword (operands[1], 1, 0, DImode);
 970     }
 971   else
 972     {
 973       operands[2] = operand_subword (operands[0], 1, 0, DImode);
 974       operands[3] = operand_subword (operands[0], 0, 0, DImode);
 975       operands[4] = operand_subword (operands[1], 1, 0, DImode);
 976       operands[5] = operand_subword (operands[1], 0, 0, DImode);
 977     }
 978 }")
 979
 980 (define_split
 981   [(set (match_operand:DI 0 "register_operand" "")
 982         (match_operand:DI 1 "memory_operand" ""))]
 983   "!TARGET_64BIT && reload_completed
 984    && !fp_operand (operands[0], VOIDmode)
 985    && !fp_operand (operands[1], VOIDmode)
 986    && !s_operand (operands[1], VOIDmode)"
 987   [(set (match_dup 0) (match_dup 1))]
 988   "
 989 {
 990   rtx addr = operand_subword (operands[0], 1, 0, DImode);
 991   s390_load_address (addr, XEXP (operands[1], 0));
 992   operands[1] = replace_equiv_address (operands[1], addr);
 993 }")
 994
 995 ;
 996 ; movsi instruction pattern(s).
 997 ;
 998
 999 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1000 ;; move to get the address of the symbolic object from the GOT.
1001
1002 (define_expand "movsi"
1003   [(set (match_operand:SI 0 "general_operand" "")
1004         (match_operand:SI 1 "general_operand" ""))]
1005   ""
1006   "
1007 {
1008   /* Handle PIC symbolic constants.  */
1009   if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1010     emit_pic_move (operands, SImode);
1011
1012   /* expr.c tries to load an effective address using
1013      force_reg.  This fails because we don't have a
1014      generic load_address pattern.  Convert the move
1015      to a proper arithmetic operation instead, unless
1016      it is guaranteed to be OK.  */
1017   if (GET_CODE (operands[1]) == PLUS
1018       && !legitimate_la_operand_p (operands[1]))
1019     {
1020       operands[1] = force_operand (operands[1], operands[0]);
1021       if (operands[1] == operands[0])
1022         DONE;
1023     }
1024
1025   /* During and after reload, we need to force constants
1026      to the literal pool ourselves, if necessary.  */
1027   if ((reload_in_progress || reload_completed)
1028       && CONSTANT_P (operands[1])
1029       && (!legitimate_reload_constant_p (operands[1])
1030           || fp_operand (operands[0], VOIDmode)))
1031     operands[1] = force_const_mem (SImode, operands[1]);
1032 }")
1033
1034 (define_insn "*movsi_lhi"
1035   [(set (match_operand:SI 0 "register_operand" "=d")
1036         (match_operand:SI 1 "immediate_operand" "K"))]
1037   "GET_CODE (operands[1]) == CONST_INT
1038    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1039    && !fp_operand (operands[0], VOIDmode)"
1040   "lhi\\t%0,%h1"
1041   [(set_attr "op_type" "RI")])
1042
1043 (define_insn "*movsi_lli"
1044   [(set (match_operand:SI 0 "register_operand" "=d")
1045         (match_operand:SI 1 "immediate_operand" "n"))]
1046   "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1047    && !fp_operand (operands[0], VOIDmode)"
1048   "*
1049 {
1050   int part = s390_single_hi (operands[1], SImode, 0);
1051   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1052
1053   switch (part)
1054     {
1055       case 0: return \"llilh\\t%0,%x1\";
1056       case 1: return \"llill\\t%0,%x1\";
1057       default: abort ();
1058     }
1059 }"
1060   [(set_attr "op_type" "RI")])
1061
1062 (define_insn "*movsi"
1063   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1064         (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1065   ""
1066   "@
1067    lr\\t%0,%1
1068    l\\t%0,%1
1069    st\\t%1,%0
1070    ler\\t%0,%1
1071    le\\t%0,%1
1072    ste\\t%1,%0
1073    mvc\\t%O0(4,%R0),%1"
1074   [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1075    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
1076
1077
1078 ;
1079 ; movhi instruction pattern(s).
1080 ;
1081
1082 (define_insn "movhi"
1083   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1084         (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1085   ""
1086   "@
1087    lr\\t%0,%1
1088    lhi\\t%0,%h1
1089    lh\\t%0,%1
1090    sth\\t%1,%0
1091    mvc\\t%O0(2,%R0),%1"
1092   [(set_attr "op_type" "RR,RI,RX,RX,SS")
1093    (set_attr "atype"   "reg,reg,mem,mem,mem")])
1094
1095
1096 ;
1097 ; movqi instruction pattern(s).
1098 ;
1099
1100 (define_insn "movqi_64"
1101   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1102         (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1103   "TARGET_64BIT"
1104   "@
1105    lr\\t%0,%1
1106    lhi\\t%0,%b1
1107    llgc\\t%0,%1
1108    stc\\t%1,%0
1109    mvi\\t%0,%b1
1110    mvc\\t%O0(1,%R0),%1"
1111   [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1112    (set_attr "atype"   "reg,reg,mem,mem,mem,mem")])
1113
1114
1115 (define_insn "movqi"
1116   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1117         (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1118   ""
1119   "@
1120    lr\\t%0,%1
1121    lhi\\t%0,%b1
1122    ic\\t%0,%1
1123    stc\\t%1,%0
1124    mvi\\t%0,%b1
1125    mvc\\t%O0(1,%R0),%1"
1126   [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1127    (set_attr "atype"   "reg,reg,mem,mem,mem,mem")])
1128
1129
1130 ;
1131 ; movstrictqi instruction pattern(s).
1132 ;
1133
1134 (define_insn "*movstrictqi"
1135   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1136                          (match_operand:QI 1 "memory_operand" "m"))]
1137   ""
1138   "ic\\t%0,%1"
1139   [(set_attr "op_type"  "RX")
1140    (set_attr "atype"    "mem")])
1141
1142 ;
1143 ; movstricthi instruction pattern(s).
1144 ;
1145
1146 (define_insn "*movstricthi"
1147   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1148                          (match_operand:HI 1 "s_imm_operand" "Q"))
1149    (clobber (reg:CC 33))]
1150   ""
1151   "icm\\t%0,3,%1"
1152   [(set_attr "op_type" "RS")
1153    (set_attr "atype"   "mem")])
1154
1155
1156 ;
1157 ; movstrictsi instruction pattern(s).
1158 ;
1159
1160 (define_insn "movstrictsi"
1161   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1162                          (match_operand:SI 1 "general_operand" "d,m"))]
1163   "TARGET_64BIT"
1164   "@
1165    lr\\t%0,%1
1166    l\\t%0,%1"
1167   [(set_attr "op_type" "RR,RS")
1168    (set_attr "atype"   "reg,mem")])
1169
1170
1171 ;
1172 ; movdf instruction pattern(s).
1173 ;
1174
1175 (define_expand "movdf"
1176   [(set (match_operand:DF 0 "nonimmediate_operand" "")
1177         (match_operand:DF 1 "general_operand"  ""))]
1178   ""
1179   "
1180 {
1181   /* During and after reload, we need to force constants
1182      to the literal pool ourselves, if necessary.  */
1183   if ((reload_in_progress || reload_completed)
1184       && CONSTANT_P (operands[1]))
1185     operands[1] = force_const_mem (DFmode, operands[1]);
1186 }")
1187
1188 (define_insn "*movdf_64"
1189   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1190         (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1191   "TARGET_64BIT"
1192   "@
1193    ldr\\t%0,%1
1194    ld\\t%0,%1
1195    std\\t%1,%0
1196    lgr\\t%0,%1
1197    lg\\t%0,%1
1198    stg\\t%1,%0
1199    mvc\\t%O0(8,%R0),%1"
1200   [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE,SS")
1201    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
1202
1203 (define_insn "*movdf_31"
1204   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1205         (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1206   "!TARGET_64BIT"
1207   "@
1208    ldr\\t%0,%1
1209    ld\\t%0,%1
1210    std\\t%1,%0
1211    lm\\t%0,%N0,%1
1212    stm\\t%1,%N1,%0
1213    #
1214    #
1215    mvc\\t%O0(8,%R0),%1"
1216   [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1217    (set_attr "atype"   "reg,mem,mem,mem,mem,*,*,mem")])
1218
1219 (define_split
1220   [(set (match_operand:DF 0 "nonimmediate_operand" "")
1221         (match_operand:DF 1 "general_operand" ""))]
1222   "!TARGET_64BIT && reload_completed
1223    && !fp_operand (operands[0], VOIDmode)
1224    && !fp_operand (operands[1], VOIDmode)
1225    && !s_operand (operands[0], VOIDmode)
1226    && !s_operand (operands[1], VOIDmode)
1227    && (register_operand (operands[0], VOIDmode)
1228        || register_operand (operands[1], VOIDmode))
1229    && (!register_operand (operands[0], VOIDmode)
1230        || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1231                                     operands[1])
1232        || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1233                                     operands[1]))"
1234   [(set (match_dup 2) (match_dup 4))
1235    (set (match_dup 3) (match_dup 5))]
1236   "
1237 {
1238   if (!register_operand (operands[0], VOIDmode)
1239       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1240                                    operands[1]))
1241     {
1242       operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1243       operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1244       operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1245       operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1246     }
1247   else
1248     {
1249       operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1250       operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1251       operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1252       operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1253     }
1254 }")
1255
1256 (define_split
1257   [(set (match_operand:DF 0 "register_operand" "")
1258         (match_operand:DF 1 "memory_operand" ""))]
1259   "!TARGET_64BIT && reload_completed
1260    && !fp_operand (operands[0], VOIDmode)
1261    && !fp_operand (operands[1], VOIDmode)
1262    && !s_operand (operands[1], VOIDmode)"
1263   [(set (match_dup 0) (match_dup 1))]
1264   "
1265 {
1266   rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1267   s390_load_address (addr, XEXP (operands[1], 0));
1268   operands[1] = replace_equiv_address (operands[1], addr);
1269 }")
1270
1271 ;
1272 ; movsf instruction pattern(s).
1273 ;
1274
1275 (define_expand "movsf"
1276   [(set (match_operand:SF 0 "nonimmediate_operand" "")
1277         (match_operand:SF 1 "general_operand"  ""))]
1278   ""
1279   "
1280 {
1281   /* During and after reload, we need to force constants
1282      to the literal pool ourselves, if necessary.  */
1283   if ((reload_in_progress || reload_completed)
1284       && CONSTANT_P (operands[1]))
1285     operands[1] = force_const_mem (SFmode, operands[1]);
1286 }")
1287
1288 (define_insn "*movsf"
1289   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1290         (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1291   ""
1292   "@
1293    ler\\t%0,%1
1294    le\\t%0,%1
1295    ste\\t%1,%0
1296    lr\\t%0,%1
1297    l\\t%0,%1
1298    st\\t%1,%0
1299    mvc\\t%O0(4,%R0),%1"
1300   [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1301    (set_attr "atype"   "reg,mem,mem,reg,mem,mem,mem")])
1302
1303 ;
1304 ; load_multiple pattern(s).
1305 ;
1306
1307 (define_expand "load_multiple"
1308   [(match_par_dup 3 [(set (match_operand 0 "" "")
1309                           (match_operand 1 "" ""))
1310                      (use (match_operand 2 "" ""))])]
1311   ""
1312   "
1313 {
1314   int regno;
1315   int count;
1316   rtx from;
1317   int i, off;
1318
1319   /* Support only loading a constant number of fixed-point registers from
1320      memory and only bother with this if more than two */
1321   if (GET_CODE (operands[2]) != CONST_INT
1322       || INTVAL (operands[2]) < 2
1323       || INTVAL (operands[2]) > 16
1324       || GET_CODE (operands[1]) != MEM
1325       || GET_CODE (operands[0]) != REG
1326       || REGNO (operands[0]) >= 16)
1327     FAIL;
1328
1329   count = INTVAL (operands[2]);
1330   regno = REGNO (operands[0]);
1331
1332   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1333   if (no_new_pseudos)
1334     {
1335       if (GET_CODE (XEXP (operands[1], 0)) == REG)
1336         {
1337           from = XEXP (operands[1], 0);
1338           off = 0;
1339         }
1340       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1341                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1342                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1343         {
1344           from = XEXP (XEXP (operands[1], 0), 0);
1345           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1346         }
1347       else
1348         FAIL;
1349
1350       if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1351         FAIL;
1352     }
1353   else
1354     {
1355       from = force_reg (Pmode, XEXP (operands[1], 0));
1356       off = 0;
1357     }
1358
1359   for (i = 0; i < count; i++)
1360     XVECEXP (operands[3], 0, i)
1361       = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1362                      change_address (operands[1], Pmode,
1363                                      plus_constant (from,
1364                                                     off + i * UNITS_PER_WORD)));
1365 }")
1366
1367 (define_insn "*load_multiple_di"
1368   [(match_parallel 0 "load_multiple_operation"
1369                    [(set (match_operand:DI 1 "register_operand" "=r")
1370                          (match_operand:DI 2 "s_operand" "Q"))])]
1371   ""
1372   "*
1373 {
1374   int words = XVECLEN (operands[0], 0);
1375
1376   if (XVECLEN (operands[0], 0) == 1)
1377     return \"lg\\t%1,0(%2)\";
1378
1379   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1380     return \"lmg\\t%1,%0,%2\";
1381 }"
1382    [(set_attr "op_type" "RXE")
1383     (set_attr "atype"   "mem")
1384     (set_attr "type"    "lm")])
1385
1386 (define_insn "*load_multiple_si"
1387   [(match_parallel 0 "load_multiple_operation"
1388                    [(set (match_operand:SI 1 "register_operand" "=r")
1389                          (match_operand:SI 2 "s_operand" "Q"))])]
1390   ""
1391   "*
1392 {
1393   int words = XVECLEN (operands[0], 0);
1394
1395   if (XVECLEN (operands[0], 0) == 1)
1396     return \"l\\t%1,0(%2)\";
1397
1398   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1399     return \"lm\\t%1,%0,%2\";
1400 }"
1401    [(set_attr "op_type" "RXE")
1402     (set_attr "atype"   "mem")
1403     (set_attr "type"    "lm")])
1404
1405 ;
1406 ; store multiple pattern(s).
1407 ;
1408
1409 (define_expand "store_multiple"
1410   [(match_par_dup 3 [(set (match_operand 0 "" "")
1411                           (match_operand 1 "" ""))
1412                      (use (match_operand 2 "" ""))])]
1413   ""
1414   "
1415 {
1416   int regno;
1417   int count;
1418   rtx to;
1419   int i, off;
1420
1421   /* Support only storing a constant number of fixed-point registers to
1422      memory and only bother with this if more than two.  */
1423   if (GET_CODE (operands[2]) != CONST_INT
1424       || INTVAL (operands[2]) < 2
1425       || INTVAL (operands[2]) > 16
1426       || GET_CODE (operands[0]) != MEM
1427       || GET_CODE (operands[1]) != REG
1428       || REGNO (operands[1]) >= 16)
1429     FAIL;
1430
1431   count = INTVAL (operands[2]);
1432   regno = REGNO (operands[1]);
1433
1434   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1435
1436   if (no_new_pseudos)
1437     {
1438       if (GET_CODE (XEXP (operands[0], 0)) == REG)
1439         {
1440           to = XEXP (operands[0], 0);
1441           off = 0;
1442         }
1443       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1444                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1445                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1446         {
1447           to = XEXP (XEXP (operands[0], 0), 0);
1448           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1449         }
1450       else
1451         FAIL;
1452
1453       if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1454         FAIL;
1455     }
1456   else
1457     {
1458       to = force_reg (Pmode, XEXP (operands[0], 0));
1459       off = 0;
1460     }
1461
1462   for (i = 0; i < count; i++)
1463     XVECEXP (operands[3], 0, i)
1464       = gen_rtx_SET (VOIDmode,
1465                      change_address (operands[0], Pmode,
1466                                      plus_constant (to,
1467                                                     off + i * UNITS_PER_WORD)),
1468                      gen_rtx_REG (Pmode, regno + i));
1469 }")
1470
1471 (define_insn "*store_multiple_di"
1472   [(match_parallel 0 "store_multiple_operation"
1473                    [(set (match_operand:DI 1 "s_operand" "=Q")
1474                          (match_operand:DI 2 "register_operand" "r"))])]
1475   ""
1476   "*
1477 {
1478   int words = XVECLEN (operands[0], 0);
1479
1480   if (XVECLEN (operands[0], 0) == 1)
1481     return \"stg\\t%1,0(%2)\";
1482
1483   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1484     return \"stmg\\t%2,%0,%1\";
1485 }"
1486    [(set_attr "op_type" "RXE")
1487     (set_attr "atype"   "mem")
1488     (set_attr "type"    "stm")])
1489
1490
1491 (define_insn "*store_multiple_si"
1492   [(match_parallel 0 "store_multiple_operation"
1493                    [(set (match_operand:SI 1 "s_operand" "=Q")
1494                          (match_operand:SI 2 "register_operand" "r"))])]
1495   ""
1496   "*
1497 {
1498   int words = XVECLEN (operands[0], 0);
1499
1500   if (XVECLEN (operands[0], 0) == 1)
1501     return \"st\\t%1,0(%2)\";
1502
1503   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1504     return \"stm\\t%2,%0,%1\";
1505 }"
1506    [(set_attr "op_type" "RXE")
1507     (set_attr "atype"   "mem")
1508     (set_attr "type"    "stm")])
1509
1510 ;;
1511 ;; String instructions.
1512 ;;
1513
1514 ;
1515 ; movstrM instruction pattern(s).
1516 ;
1517
1518 (define_expand "movstrdi"
1519   [(set (match_operand:BLK 0 "memory_operand" "")
1520         (match_operand:BLK 1 "memory_operand" ""))
1521    (use (match_operand:DI 2 "general_operand" ""))
1522    (match_operand 3 "" "")]
1523   "TARGET_64BIT"
1524   "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1525
1526 (define_expand "movstrsi"
1527   [(set (match_operand:BLK 0 "memory_operand" "")
1528         (match_operand:BLK 1 "memory_operand" ""))
1529    (use (match_operand:SI 2 "general_operand" ""))
1530    (match_operand 3 "" "")]
1531   ""
1532   "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1533
1534 ; Move a block that is up to 256 bytes in length.
1535 ; The block length is taken as (operands[2] % 256) + 1.
1536
1537 (define_insn "movstr_short_64"
1538   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1539         (match_operand:BLK 1 "memory_operand" "Q,Q"))
1540    (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1541    (clobber (match_scratch:DI 3 "=X,&a"))]
1542   "TARGET_64BIT"
1543   "*
1544 {
1545   switch (which_alternative)
1546     {
1547       case 0:
1548         return \"mvc\\t%O0(%b2+1,%R0),%1\";
1549
1550       case 1:
1551         output_asm_insn (\"bras\\t%3,.+10\", operands);
1552         output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1553         return \"ex\\t%2,0(%3)\";
1554
1555       default:
1556         abort ();
1557     }
1558 }"
1559   [(set_attr "op_type" "SS,NN")
1560    (set_attr "type"    "cs,cs")
1561    (set_attr "atype"   "mem,mem")
1562    (set_attr "length"  "*,14")])
1563
1564 (define_insn "movstr_short_31"
1565   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1566         (match_operand:BLK 1 "memory_operand" "Q,Q"))
1567    (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1568    (clobber (match_scratch:SI 3 "=X,&a"))]
1569   "!TARGET_64BIT"
1570   "*
1571 {
1572   switch (which_alternative)
1573     {
1574       case 0:
1575         return \"mvc\\t%O0(%b2+1,%R0),%1\";
1576
1577       case 1:
1578         output_asm_insn (\"bras\\t%3,.+10\", operands);
1579         output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1580         return \"ex\\t%2,0(%3)\";
1581
1582       default:
1583         abort ();
1584     }
1585 }"
1586   [(set_attr "op_type" "SS,NN")
1587    (set_attr "type"    "cs,cs")
1588    (set_attr "atype"   "mem,mem")
1589    (set_attr "length"  "*,14")])
1590
1591 ; Move a block of arbitrary length.
1592
1593 (define_insn "movstr_long_64"
1594   [(set (match_operand:TI 0 "register_operand" "=d")
1595         (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1596                             (lshiftrt:TI (match_dup 2) (const_int 64)))
1597                    (const_int 64)))
1598    (set (match_operand:TI 1 "register_operand" "=d")
1599         (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1600                             (lshiftrt:TI (match_dup 3) (const_int 64)))
1601                    (const_int 64)))
1602    (set (mem:BLK (subreg:DI (match_dup 2) 0))
1603         (mem:BLK (subreg:DI (match_dup 3) 0)))
1604    (clobber (reg:CC 33))]
1605   "TARGET_64BIT"
1606   "mvcle\\t%0,%1,0\;jo\\t.-4"
1607   [(set_attr "op_type" "NN")
1608    (set_attr "type"    "vs")
1609    (set_attr "atype"   "mem")
1610    (set_attr "length"  "8")])
1611
1612 (define_insn "movstr_long_31"
1613   [(set (match_operand:DI 0 "register_operand" "=d")
1614         (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1615                             (lshiftrt:DI (match_dup 2) (const_int 32)))
1616                    (const_int 32)))
1617    (set (match_operand:DI 1 "register_operand" "=d")
1618         (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1619                             (lshiftrt:DI (match_dup 3) (const_int 32)))
1620                    (const_int 32)))
1621    (set (mem:BLK (subreg:SI (match_dup 2) 0))
1622         (mem:BLK (subreg:SI (match_dup 3) 0)))
1623    (clobber (reg:CC 33))]
1624   "!TARGET_64BIT"
1625   "mvcle\\t%0,%1,0\;jo\\t.-4"
1626   [(set_attr "op_type" "NN")
1627    (set_attr "type"    "vs")
1628    (set_attr "atype"   "mem")
1629    (set_attr "length"  "8")])
1630
1631 ;
1632 ; clrstrM instruction pattern(s).
1633 ;
1634
1635 (define_expand "clrstrdi"
1636   [(set (match_operand:BLK 0 "memory_operand" "")
1637         (const_int 0))
1638    (use (match_operand:DI 1 "general_operand" ""))
1639    (match_operand 2 "" "")]
1640   "TARGET_64BIT"
1641   "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1642
1643 (define_expand "clrstrsi"
1644   [(set (match_operand:BLK 0 "memory_operand" "")
1645         (const_int 0))
1646    (use (match_operand:SI 1 "general_operand" ""))
1647    (match_operand 2 "" "")]
1648   ""
1649   "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1650
1651 ; Clear a block that is up to 256 bytes in length.
1652 ; The block length is taken as (operands[2] % 256) + 1.
1653
1654 (define_insn "clrstr_short_64"
1655   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1656         (const_int 0))
1657    (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1658    (clobber (match_scratch:DI 2 "=X,&a"))
1659    (clobber (reg:CC 33))]
1660   "TARGET_64BIT"
1661   "*
1662 {
1663   switch (which_alternative)
1664     {
1665       case 0:
1666         return \"xc\\t%O0(%b1+1,%R0),%0\";
1667
1668       case 1:
1669         output_asm_insn (\"bras\\t%2,.+10\", operands);
1670         output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1671         return \"ex\\t%1,0(%2)\";
1672
1673       default:
1674         abort ();
1675     }
1676 }"
1677   [(set_attr "op_type" "SS,NN")
1678    (set_attr "type"    "cs,cs")
1679    (set_attr "atype"   "mem,mem")
1680    (set_attr "length"  "*,14")])
1681
1682 (define_insn "clrstr_short_31"
1683   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1684         (const_int 0))
1685    (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1686    (clobber (match_scratch:SI 2 "=X,&a"))
1687    (clobber (reg:CC 33))]
1688   "!TARGET_64BIT"
1689   "*
1690 {
1691   switch (which_alternative)
1692     {
1693       case 0:
1694         return \"xc\\t%O0(%b1+1,%R0),%0\";
1695
1696       case 1:
1697         output_asm_insn (\"bras\\t%2,.+10\", operands);
1698         output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1699         return \"ex\\t%1,0(%2)\";
1700
1701       default:
1702         abort ();
1703     }
1704 }"
1705   [(set_attr "op_type" "SS,NN")
1706    (set_attr "type"    "cs,cs")
1707    (set_attr "atype"   "mem,mem")
1708    (set_attr "length"  "*,14")])
1709
1710 ; Clear a block of arbitrary length.
1711
1712 (define_insn "clrstr_long_64"
1713   [(set (match_operand:TI 0 "register_operand" "=d")
1714         (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1715                             (lshiftrt:TI (match_dup 2) (const_int 64)))
1716                    (const_int 64)))
1717    (set (mem:BLK (subreg:DI (match_dup 2) 0))
1718         (const_int 0))
1719    (use (match_operand:TI 1 "register_operand" "d"))
1720    (clobber (reg:CC 33))]
1721   "TARGET_64BIT"
1722   "mvcle\\t%0,%1,0\;jo\\t.-4"
1723   [(set_attr "op_type" "NN")
1724    (set_attr "atype"   "mem")
1725    (set_attr "type"    "vs")
1726    (set_attr "length"  "8")])
1727
1728 (define_insn "clrstr_long_31"
1729   [(set (match_operand:DI 0 "register_operand" "=d")
1730         (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1731                             (lshiftrt:DI (match_dup 2) (const_int 32)))
1732                    (const_int 32)))
1733    (set (mem:BLK (subreg:SI (match_dup 2) 0))
1734         (const_int 0))
1735    (use (match_operand:DI 1 "register_operand" "d"))
1736    (clobber (reg:CC 33))]
1737   "!TARGET_64BIT"
1738   "mvcle\\t%0,%1,0\;jo\\t.-4"
1739   [(set_attr "op_type" "NN")
1740    (set_attr "atype"   "mem")
1741    (set_attr "type"    "vs")
1742    (set_attr "length"  "8")])
1743
1744 ;
1745 ; cmpstrM instruction pattern(s).
1746 ;
1747
1748 (define_expand "cmpstrdi"
1749   [(set (match_operand:DI 0 "register_operand" "")
1750         (compare:DI (match_operand:BLK 1 "memory_operand" "")
1751                     (match_operand:BLK 2 "memory_operand" "") ) )
1752    (use (match_operand:DI 3 "general_operand" ""))
1753    (use (match_operand:DI 4 "" ""))]
1754   "TARGET_64BIT"
1755   "s390_expand_cmpstr (operands[0], operands[1],
1756                        operands[2], operands[3]); DONE;")
1757
1758 (define_expand "cmpstrsi"
1759   [(set (match_operand:SI 0 "register_operand" "")
1760         (compare:SI (match_operand:BLK 1 "memory_operand" "")
1761                     (match_operand:BLK 2 "memory_operand" "") ) )
1762    (use (match_operand:SI 3 "general_operand" ""))
1763    (use (match_operand:SI 4 "" ""))]
1764   ""
1765   "s390_expand_cmpstr (operands[0], operands[1],
1766                        operands[2], operands[3]); DONE;")
1767
1768 ; Compare a block that is up to 256 bytes in length.
1769 ; The block length is taken as (operands[2] % 256) + 1.
1770
1771 (define_insn "cmpstr_short_64"
1772   [(set (reg:CCS 33)
1773         (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1774                      (match_operand:BLK 1 "memory_operand" "Q,Q")))
1775    (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1776    (clobber (match_scratch:DI 3 "=X,&a"))]
1777   "TARGET_64BIT"
1778   "*
1779 {
1780   switch (which_alternative)
1781     {
1782       case 0:
1783         return \"clc\\t%O0(%b2+1,%R0),%1\";
1784
1785       case 1:
1786         output_asm_insn (\"bras\\t%3,.+10\", operands);
1787         output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1788         return \"ex\\t%2,0(%3)\";
1789
1790       default:
1791         abort ();
1792     }
1793 }"
1794   [(set_attr "op_type" "SS,NN")
1795    (set_attr "type"    "cs,cs")
1796    (set_attr "atype"   "mem,mem")
1797    (set_attr "length"  "*,14")])
1798
1799 (define_insn "cmpstr_short_31"
1800   [(set (reg:CCS 33)
1801         (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1802                      (match_operand:BLK 1 "memory_operand" "Q,Q")))
1803    (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1804    (clobber (match_scratch:SI 3 "=X,&a"))]
1805   "!TARGET_64BIT"
1806   "*
1807 {
1808   switch (which_alternative)
1809     {
1810       case 0:
1811         return \"clc\\t%O0(%b2+1,%R0),%1\";
1812
1813       case 1:
1814         output_asm_insn (\"bras\\t%3,.+10\", operands);
1815         output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1816         return \"ex\\t%2,0(%3)\";
1817
1818       default:
1819         abort ();
1820     }
1821 }"
1822   [(set_attr "op_type" "SS,NN")
1823    (set_attr "type"    "cs,cs")
1824    (set_attr "atype"   "mem,mem")
1825    (set_attr "length"  "*,14")])
1826
1827 ; Compare a block of arbitrary length.
1828
1829 (define_insn "cmpstr_long_64"
1830   [(clobber (match_operand:TI 0 "register_operand" "=d"))
1831    (clobber (match_operand:TI 1 "register_operand" "=d"))
1832    (set (reg:CCS 33)
1833         (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1834                      (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1835    (use (match_dup 2))
1836    (use (match_dup 3))]
1837   "TARGET_64BIT"
1838   "clcl\\t%0,%1"
1839   [(set_attr "op_type" "RR")
1840    (set_attr "atype"   "mem")
1841    (set_attr "type"    "vs")])
1842
1843 (define_insn "cmpstr_long_31"
1844   [(clobber (match_operand:DI 0 "register_operand" "=d"))
1845    (clobber (match_operand:DI 1 "register_operand" "=d"))
1846    (set (reg:CCS 33)
1847         (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1848                      (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1849    (use (match_dup 2))
1850    (use (match_dup 3))]
1851   "!TARGET_64BIT"
1852   "clcl\\t%0,%1"
1853   [(set_attr "op_type" "RR")
1854    (set_attr "atype"   "mem")
1855    (set_attr "type"    "vs")])
1856
1857 ; Convert condition code to integer in range (-1, 0, 1)
1858
1859 (define_insn "cmpint_si"
1860   [(set (match_operand:SI 0 "register_operand" "=d")
1861         (compare:SI (reg:CCS 33) (const_int 0)))]
1862   ""
1863   "*
1864 {
1865    output_asm_insn (\"lhi\\t%0,1\", operands);
1866    output_asm_insn (\"jh\\t.+12\", operands);
1867    output_asm_insn (\"jl\\t.+6\", operands);
1868    output_asm_insn (\"sr\\t%0,%0\", operands);
1869    return \"lcr\\t%0,%0\";
1870 }"
1871   [(set_attr "op_type" "NN")
1872    (set_attr "length"  "16")
1873    (set_attr "atype"   "reg")
1874    (set_attr "type"    "other")])
1875
1876 (define_insn "cmpint_di"
1877   [(set (match_operand:DI 0 "register_operand" "=d")
1878         (compare:DI (reg:CCS 33) (const_int 0)))]
1879   "TARGET_64BIT"
1880   "*
1881 {
1882    output_asm_insn (\"lghi\\t%0,1\", operands);
1883    output_asm_insn (\"jh\\t.+12\", operands);
1884    output_asm_insn (\"jl\\t.+6\", operands);
1885    output_asm_insn (\"sgr\\t%0,%0\", operands);
1886    return \"lcgr\\t%0,%0\";
1887 }"
1888   [(set_attr "op_type" "NN")
1889    (set_attr "length"  "22")
1890    (set_attr "atype"   "reg")
1891    (set_attr "type"    "other")])
1892
1893
1894 ;;
1895 ;;- Conversion instructions.
1896 ;;
1897
1898 (define_insn "*sethighqisi"
1899   [(set (match_operand:SI 0 "register_operand" "=d")
1900         (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
1901    (clobber (reg:CC 33))]
1902   ""
1903   "icm\\t%0,8,%1"
1904   [(set_attr "op_type" "RS")
1905    (set_attr "atype"   "mem")])
1906
1907 (define_insn "*sethighhisi"
1908   [(set (match_operand:SI 0 "register_operand" "=d")
1909         (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
1910    (clobber (reg:CC 33))]
1911   ""
1912   "icm\\t%0,12,%1"
1913   [(set_attr "op_type" "RS")
1914    (set_attr "atype"   "mem")])
1915
1916 (define_insn "*sethighqidi_64"
1917   [(set (match_operand:DI 0 "register_operand" "=d")
1918         (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1919    (clobber (reg:CC 33))]
1920   "TARGET_64BIT"
1921   "icmh\\t%0,8,%1"
1922   [(set_attr "op_type" "RSE")
1923    (set_attr "atype"   "mem")])
1924
1925 (define_insn "*sethighqidi_31"
1926   [(set (match_operand:DI 0 "register_operand" "=d")
1927         (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1928    (clobber (reg:CC 33))]
1929   "!TARGET_64BIT"
1930   "icm\\t%0,8,%1"
1931   [(set_attr "op_type" "RS")
1932    (set_attr "atype"   "mem")])
1933
1934 (define_insn_and_split "*extractqi"
1935   [(set (match_operand:SI 0 "register_operand" "=d")
1936         (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
1937                          (match_operand 2 "const_int_operand" "n")
1938                          (const_int 0)))
1939    (clobber (reg:CC 33))]
1940   "!TARGET_64BIT
1941    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
1942   "#"
1943   "&& reload_completed"
1944   [(parallel
1945     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1946      (clobber (reg:CC 33))])
1947     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1948   "
1949 {
1950   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1951   operands[1] = change_address (operands[1], QImode, 0);
1952 }"
1953   [(set_attr "type"    "o2")
1954    (set_attr "atype"   "mem")])
1955
1956 (define_insn_and_split "*extracthi"
1957   [(set (match_operand:SI 0 "register_operand" "=d")
1958         (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
1959                          (match_operand 2 "const_int_operand" "n")
1960                          (const_int 0)))
1961    (clobber (reg:CC 33))]
1962   "!TARGET_64BIT
1963    && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
1964   "#"
1965   "&& reload_completed"
1966   [(parallel
1967     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1968      (clobber (reg:CC 33))])
1969     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1970   "
1971 {
1972   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1973   operands[1] = change_address (operands[1], HImode, 0);
1974 }"
1975   [(set_attr "type"    "o2")
1976    (set_attr "atype"   "mem")])
1977
1978 ;
1979 ; extendsidi2 instruction pattern(s).
1980 ;
1981
1982 (define_expand "extendsidi2"
1983   [(set (match_operand:DI 0 "register_operand" "")
1984         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
1985   ""
1986   "
1987 {
1988   if (!TARGET_64BIT)
1989     {
1990       emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
1991       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
1992       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
1993       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
1994       DONE;
1995     }
1996 }
1997 ")
1998
1999 (define_insn "*extendsidi2"
2000   [(set (match_operand:DI 0 "register_operand" "=d,d")
2001         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2002   "TARGET_64BIT"
2003   "@
2004    lgfr\\t%0,%1
2005    lgf\\t%0,%1"
2006   [(set_attr "op_type" "RRE,RXE")
2007    (set_attr "atype"   "reg,mem")])
2008
2009 ;
2010 ; extendhidi2 instruction pattern(s).
2011 ;
2012
2013 (define_expand "extendhidi2"
2014   [(set (match_operand:DI 0 "register_operand" "")
2015         (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2016   ""
2017   "
2018 {
2019   if (!TARGET_64BIT)
2020     {
2021       rtx tmp = gen_reg_rtx (SImode);
2022       emit_insn (gen_extendhisi2 (tmp, operands[1]));
2023       emit_insn (gen_extendsidi2 (operands[0], tmp));
2024       DONE;
2025     }
2026   else
2027     {
2028       operands[1] = gen_lowpart (DImode, operands[1]);
2029       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2030       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2031       DONE;
2032     }
2033 }
2034 ")
2035
2036 (define_insn "*extendhidi2"
2037   [(set (match_operand:DI 0 "register_operand" "=d")
2038         (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2039   "TARGET_64BIT"
2040   "lgh\\t%0,%1"
2041   [(set_attr "op_type" "RXE")
2042    (set_attr "atype"   "mem")])
2043
2044 ;
2045 ; extendqidi2 instruction pattern(s).
2046 ;
2047
2048 (define_expand "extendqidi2"
2049   [(set (match_operand:DI 0 "register_operand" "")
2050         (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2051   ""
2052   "
2053 {
2054   if (!TARGET_64BIT)
2055     {
2056       rtx tmp = gen_reg_rtx (SImode);
2057       emit_insn (gen_extendqisi2 (tmp, operands[1]));
2058       emit_insn (gen_extendsidi2 (operands[0], tmp));
2059       DONE;
2060     }
2061   else
2062     {
2063       operands[1] = gen_lowpart (DImode, operands[1]);
2064       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2065       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2066       DONE;
2067     }
2068 }
2069 ")
2070
2071 (define_split
2072   [(set (match_operand:DI 0 "register_operand" "")
2073         (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2074   "TARGET_64BIT && !reload_completed"
2075   [(parallel
2076     [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2077      (clobber (reg:CC 33))])
2078    (parallel
2079     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2080      (clobber (reg:CC 33))])]
2081   "")
2082
2083 ;
2084 ; extendhisi2 instruction pattern(s).
2085 ;
2086
2087 (define_expand "extendhisi2"
2088   [(set (match_operand:SI 0 "register_operand" "")
2089         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2090   ""
2091   "
2092 {
2093   operands[1] = gen_lowpart (SImode, operands[1]);
2094   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2095   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2096   DONE;
2097 }
2098 ")
2099
2100 (define_insn "*extendhisi2"
2101   [(set (match_operand:SI 0 "register_operand" "=d")
2102         (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2103   ""
2104   "lh\\t%0,%1"
2105   [(set_attr "op_type" "RX")
2106    (set_attr "atype"   "mem")])
2107
2108 ;
2109 ; extendqisi2 instruction pattern(s).
2110 ;
2111
2112 (define_expand "extendqisi2"
2113   [(set (match_operand:SI 0 "register_operand" "")
2114         (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2115   ""
2116   "
2117 {
2118   operands[1] = gen_lowpart (SImode, operands[1]);
2119   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2120   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2121   DONE;
2122 }
2123 ")
2124
2125 (define_split
2126   [(set (match_operand:SI 0 "register_operand" "")
2127         (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2128   "!reload_completed"
2129   [(parallel
2130     [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2131      (clobber (reg:CC 33))])
2132    (parallel
2133     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2134      (clobber (reg:CC 33))])]
2135   "")
2136
2137 ;
2138 ; extendqihi2 instruction pattern(s).
2139 ;
2140
2141
2142 ;
2143 ; zero_extendsidi2 instruction pattern(s).
2144 ;
2145
2146 (define_expand "zero_extendsidi2"
2147   [(set (match_operand:DI 0 "register_operand" "")
2148         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2149   ""
2150   "
2151 {
2152   if (!TARGET_64BIT)
2153     {
2154       emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2155       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2156       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2157       DONE;
2158     }
2159 }
2160 ")
2161
2162 (define_insn "*zero_extendsidi2"
2163   [(set (match_operand:DI 0 "register_operand" "=d,d")
2164         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2165   "TARGET_64BIT"
2166   "@
2167    llgfr\\t%0,%1
2168    llgf\\t%0,%1"
2169   [(set_attr "op_type" "RRE,RXE")
2170    (set_attr "atype"   "reg,mem")])
2171
2172 ;
2173 ; zero_extendhidi2 instruction pattern(s).
2174 ;
2175
2176 (define_expand "zero_extendhidi2"
2177   [(set (match_operand:DI 0 "register_operand" "")
2178         (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2179   ""
2180   "
2181 {
2182   if (!TARGET_64BIT)
2183     {
2184       rtx tmp = gen_reg_rtx (SImode);
2185       emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2186       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2187       DONE;
2188     }
2189   else
2190     {
2191       operands[1] = gen_lowpart (DImode, operands[1]);
2192       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2193       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2194       DONE;
2195     }
2196 }
2197 ")
2198
2199 (define_insn "*zero_extendhidi2"
2200   [(set (match_operand:DI 0 "register_operand" "=d")
2201         (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2202   "TARGET_64BIT"
2203   "llgh\\t%0,%1"
2204   [(set_attr "op_type" "RXE")
2205    (set_attr "atype"   "mem")])
2206
2207 ;
2208 ; zero_extendqidi2 instruction pattern(s)
2209 ;
2210
2211 (define_expand "zero_extendqidi2"
2212   [(set (match_operand:DI 0 "register_operand" "")
2213         (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2214   ""
2215   "
2216 {
2217   if (!TARGET_64BIT)
2218     {
2219       rtx tmp = gen_reg_rtx (SImode);
2220       emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2221       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2222       DONE;
2223     }
2224   else
2225     {
2226       operands[1] = gen_lowpart (DImode, operands[1]);
2227       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2228       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2229       DONE;
2230     }
2231 }
2232 ")
2233
2234 (define_insn "*zero_extendqidi2"
2235   [(set (match_operand:DI 0 "register_operand" "=d")
2236         (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2237   "TARGET_64BIT"
2238   "llgc\\t%0,%1"
2239   [(set_attr "op_type" "RXE")
2240    (set_attr "atype"   "mem")])
2241
2242 ;
2243 ; zero_extendhisi2 instruction pattern(s).
2244 ;
2245
2246 (define_expand "zero_extendhisi2"
2247   [(set (match_operand:SI 0 "register_operand" "")
2248         (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2249   ""
2250   "
2251 {
2252   operands[1] = gen_lowpart (SImode, operands[1]);
2253   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2254   DONE;
2255 }
2256 ")
2257
2258 (define_insn "*zero_extendhisi2_64"
2259   [(set (match_operand:SI 0 "register_operand" "=d")
2260         (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2261   "TARGET_64BIT"
2262   "llgh\\t%0,%1"
2263   [(set_attr "op_type" "RXE")
2264    (set_attr "atype"   "mem")])
2265
2266 (define_insn_and_split "*zero_extendhisi2_31"
2267   [(set (match_operand:SI 0 "register_operand" "=&d")
2268         (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2269    (clobber (reg:CC 33))]
2270   "!TARGET_64BIT"
2271   "#"
2272   "&& reload_completed"
2273   [(set (match_dup 0) (const_int 0))
2274    (parallel
2275     [(set (strict_low_part (match_dup 2)) (match_dup 1))
2276      (clobber (reg:CC 33))])]
2277   "operands[2] = gen_lowpart (HImode, operands[0]);"
2278   [(set_attr "type" "o2")
2279    (set_attr "atype" "mem")])
2280
2281 ;
2282 ; zero_extendqisi2 instruction pattern(s).
2283 ;
2284
2285 (define_expand "zero_extendqisi2"
2286   [(set (match_operand:SI 0 "register_operand" "")
2287         (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2288   ""
2289   "
2290 {
2291   operands[1] = gen_lowpart (SImode, operands[1]);
2292   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2293   DONE;
2294 }
2295 ")
2296
2297 (define_insn "*zero_extendqisi2_64"
2298   [(set (match_operand:SI 0 "register_operand" "=d")
2299         (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2300   "TARGET_64BIT"
2301   "llgc\\t%0,%1"
2302   [(set_attr "op_type" "RXE")
2303    (set_attr "atype"   "mem")])
2304
2305 (define_insn_and_split "*zero_extendqisi2_31"
2306   [(set (match_operand:SI 0 "register_operand" "=&d")
2307         (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2308   "!TARGET_64BIT"
2309   "#"
2310   "&& reload_completed"
2311   [(set (match_dup 0) (const_int 0))
2312    (set (strict_low_part (match_dup 2)) (match_dup 1))]
2313   "operands[2] = gen_lowpart (QImode, operands[0]);"
2314   [(set_attr "type" "o2")
2315    (set_attr "atype" "mem")])
2316
2317 ;
2318 ; zero_extendqihi2 instruction pattern(s).
2319 ;
2320
2321 (define_expand "zero_extendqihi2"
2322   [(set (match_operand:HI 0 "register_operand" "")
2323         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2324   "TARGET_64BIT"
2325   "
2326 {
2327   operands[1] = gen_lowpart (HImode, operands[1]);
2328   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2329   DONE;
2330 }
2331 ")
2332
2333 (define_insn "*zero_extendqihi2_64"
2334   [(set (match_operand:HI 0 "register_operand" "=d")
2335         (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2336   "TARGET_64BIT"
2337   "llgc\\t%0,%1"
2338   [(set_attr "op_type" "RXE")
2339    (set_attr "atype"   "mem")])
2340
2341 (define_insn_and_split "*zero_extendqihi2_31"
2342   [(set (match_operand:HI 0 "register_operand" "=&d")
2343         (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2344   "!TARGET_64BIT"
2345   "#"
2346   "&& reload_completed"
2347   [(set (match_dup 0) (const_int 0))
2348    (set (strict_low_part (match_dup 2)) (match_dup 1))]
2349   "operands[2] = gen_lowpart (QImode, operands[0]);"
2350   [(set_attr "type" "o2")
2351    (set_attr "atype" "mem")])
2352
2353
2354 ;
2355 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2356 ;
2357
2358 (define_expand "fixuns_truncdfdi2"
2359   [(set (match_operand:DI 0 "register_operand" "")
2360         (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2361   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2362   "
2363 {
2364   rtx label1 = gen_label_rtx ();
2365   rtx label2 = gen_label_rtx ();
2366   rtx temp = gen_reg_rtx (DFmode);
2367   operands[1] = force_reg (DFmode, operands[1]);
2368
2369   emit_insn (gen_cmpdf (operands[1],
2370         CONST_DOUBLE_FROM_REAL_VALUE (
2371           REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2372   emit_jump_insn (gen_blt (label1));
2373   emit_insn (gen_subdf3 (temp, operands[1],
2374         CONST_DOUBLE_FROM_REAL_VALUE (
2375           REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2376   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2377   emit_jump (label2);
2378
2379   emit_label (label1);
2380   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2381   emit_label (label2);
2382   DONE;
2383 }")
2384
2385 (define_expand "fix_truncdfdi2"
2386   [(set (match_operand:DI 0 "register_operand" "")
2387         (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2388   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2389   "
2390 {
2391   operands[1] = force_reg (DFmode, operands[1]);
2392   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2393   DONE;
2394 }")
2395
2396 (define_insn "fix_truncdfdi2_ieee"
2397   [(set (match_operand:DI 0 "register_operand" "=d")
2398         (fix:DI (match_operand:DF 1 "register_operand" "f")))
2399    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2400    (clobber (reg:CC 33))]
2401   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2402   "cgdbr\\t%0,%h2,%1"
2403   [(set_attr "op_type" "RRE")
2404    (set_attr "type"    "other")])
2405
2406 ;
2407 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2408 ;
2409
2410 (define_expand "fixuns_truncdfsi2"
2411   [(set (match_operand:SI 0 "register_operand" "")
2412         (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2413   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2414   "
2415 {
2416   rtx label1 = gen_label_rtx ();
2417   rtx label2 = gen_label_rtx ();
2418   rtx temp = gen_reg_rtx (DFmode);
2419
2420   operands[1] = force_reg (DFmode,operands[1]);
2421   emit_insn (gen_cmpdf (operands[1],
2422         CONST_DOUBLE_FROM_REAL_VALUE (
2423           REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2424   emit_jump_insn (gen_blt (label1));
2425   emit_insn (gen_subdf3 (temp, operands[1],
2426         CONST_DOUBLE_FROM_REAL_VALUE (
2427           REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2428   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2429   emit_jump (label2);
2430
2431   emit_label (label1);
2432   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2433   emit_label (label2);
2434   DONE;
2435 }")
2436
2437 (define_expand "fix_truncdfsi2"
2438   [(set (match_operand:SI 0 "register_operand" "")
2439         (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2440   "TARGET_HARD_FLOAT"
2441   "
2442 {
2443   if (TARGET_IBM_FLOAT)
2444     {
2445       /* This is the algorithm from POP chapter A.5.7.2.  */
2446
2447       rtx temp   = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2448       rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2449       rtx two32  = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2450
2451       operands[1] = force_reg (DFmode, operands[1]);
2452       emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2453                                          two31r, two32, temp));
2454     }
2455   else
2456     {
2457       operands[1] = force_reg (DFmode, operands[1]);
2458       emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2459     }
2460
2461   DONE;
2462 }")
2463
2464 (define_insn "fix_truncdfsi2_ieee"
2465   [(set (match_operand:SI 0 "register_operand" "=d")
2466         (fix:SI (match_operand:DF 1 "register_operand" "f")))
2467     (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2468     (clobber (reg:CC 33))]
2469   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2470   "cfdbr\\t%0,%h2,%1"
2471    [(set_attr "op_type" "RRE")
2472     (set_attr "type"    "other" )])
2473
2474 (define_insn "fix_truncdfsi2_ibm"
2475   [(set (match_operand:SI 0 "register_operand" "=d")
2476         (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2477    (use (match_operand:DI 2 "immediate_operand" "m"))
2478    (use (match_operand:DI 3 "immediate_operand" "m"))
2479    (use (match_operand:BLK 4 "memory_operand" "m"))
2480    (clobber (reg:CC 33))]
2481   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2482   "*
2483 {
2484    output_asm_insn (\"sd\\t%1,%2\", operands);
2485    output_asm_insn (\"aw\\t%1,%3\", operands);
2486    output_asm_insn (\"std\\t%1,%4\", operands);
2487    output_asm_insn (\"xi\\t%N4,128\", operands);
2488    return \"l\\t%0,%N4\";
2489 }"
2490   [(set_attr "op_type" "NN")
2491    (set_attr "type"    "other")
2492    (set_attr "length"  "20")])
2493
2494 ;
2495 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2496 ;
2497
2498 (define_expand "fixuns_truncsfdi2"
2499   [(set (match_operand:DI 0 "register_operand" "")
2500         (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2501   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2502   "
2503 {
2504   rtx label1 = gen_label_rtx ();
2505   rtx label2 = gen_label_rtx ();
2506   rtx temp = gen_reg_rtx (SFmode);
2507
2508   operands[1] = force_reg (SFmode, operands[1]);
2509   emit_insn (gen_cmpsf (operands[1],
2510         CONST_DOUBLE_FROM_REAL_VALUE (
2511           REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2512   emit_jump_insn (gen_blt (label1));
2513
2514   emit_insn (gen_subsf3 (temp, operands[1],
2515         CONST_DOUBLE_FROM_REAL_VALUE (
2516           REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2517   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2518   emit_jump (label2);
2519
2520   emit_label (label1);
2521   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2522   emit_label (label2);
2523   DONE;
2524 }")
2525
2526 (define_expand "fix_truncsfdi2"
2527   [(set (match_operand:DI 0 "register_operand" "")
2528         (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2529   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2530   "
2531 {
2532   operands[1] = force_reg (SFmode, operands[1]);
2533   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2534   DONE;
2535 }")
2536
2537 (define_insn "fix_truncsfdi2_ieee"
2538   [(set (match_operand:DI 0 "register_operand" "=d")
2539         (fix:DI (match_operand:SF 1 "register_operand"  "f")))
2540    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2541    (clobber (reg:CC 33))]
2542   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2543   "cgebr\\t%0,%h2,%1"
2544   [(set_attr "op_type" "RRE")
2545    (set_attr "type"    "other")])
2546
2547 ;
2548 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2549 ;
2550
2551 (define_expand "fixuns_truncsfsi2"
2552   [(set (match_operand:SI 0 "register_operand" "")
2553         (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2554   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2555   "
2556 {
2557   rtx label1 = gen_label_rtx ();
2558   rtx label2 = gen_label_rtx ();
2559   rtx temp = gen_reg_rtx (SFmode);
2560
2561   operands[1] = force_reg (SFmode, operands[1]);
2562   emit_insn (gen_cmpsf (operands[1],
2563         CONST_DOUBLE_FROM_REAL_VALUE (
2564           REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2565   emit_jump_insn (gen_blt (label1));
2566   emit_insn (gen_subsf3 (temp, operands[1],
2567         CONST_DOUBLE_FROM_REAL_VALUE (
2568           REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2569   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2570   emit_jump (label2);
2571
2572   emit_label (label1);
2573   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2574   emit_label (label2);
2575   DONE;
2576 }")
2577
2578 (define_expand "fix_truncsfsi2"
2579   [(set (match_operand:SI 0 "register_operand" "")
2580         (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2581   "TARGET_HARD_FLOAT"
2582   "
2583 {
2584   if (TARGET_IBM_FLOAT)
2585     {
2586       /* Convert to DFmode and then use the POP algorithm.  */
2587       rtx temp = gen_reg_rtx (DFmode);
2588       emit_insn (gen_extendsfdf2 (temp, operands[1]));
2589       emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2590     }
2591   else
2592     {
2593       operands[1] = force_reg (SFmode, operands[1]);
2594       emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2595     }
2596
2597   DONE;
2598 }")
2599
2600 (define_insn "fix_truncsfsi2_ieee"
2601   [(set (match_operand:SI 0 "register_operand" "=d")
2602         (fix:SI (match_operand:SF 1 "register_operand" "f")))
2603     (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2604     (clobber (reg:CC 33))]
2605   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2606   "cfebr\\t%0,%h2,%1"
2607   [(set_attr "op_type" "RRE")
2608    (set_attr "type"    "other")])
2609
2610 ;
2611 ; floatdidf2 instruction pattern(s).
2612 ;
2613
2614 (define_insn "floatdidf2"
2615   [(set (match_operand:DF 0 "register_operand" "=f")
2616         (float:DF (match_operand:DI 1 "register_operand" "d")))
2617    (clobber (reg:CC 33))]
2618   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2619   "cdgbr\\t%0,%1"
2620   [(set_attr "op_type" "RRE")
2621    (set_attr "type"    "other" )])
2622
2623 ;
2624 ; floatdisf2 instruction pattern(s).
2625 ;
2626
2627 (define_insn "floatdisf2"
2628   [(set (match_operand:SF 0 "register_operand" "=f")
2629         (float:SF (match_operand:DI 1 "register_operand" "d")))
2630    (clobber (reg:CC 33))]
2631   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2632   "cegbr\\t%0,%1"
2633   [(set_attr "op_type" "RRE")
2634    (set_attr "type"    "other" )])
2635
2636 ;
2637 ; floatsidf2 instruction pattern(s).
2638 ;
2639
2640 (define_expand "floatsidf2"
2641   [(parallel
2642     [(set (match_operand:DF 0 "register_operand" "")
2643           (float:DF (match_operand:SI 1 "register_operand" "")))
2644      (clobber (reg:CC 33))])]
2645   "TARGET_HARD_FLOAT"
2646   "
2647 {
2648   if (TARGET_IBM_FLOAT)
2649     {
2650       /* This is the algorithm from POP chapter A.5.7.1.  */
2651
2652       rtx temp  = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2653       rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2654
2655       emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2656       DONE;
2657     }
2658 }")
2659
2660 (define_insn "floatsidf2_ieee"
2661   [(set (match_operand:DF 0 "register_operand" "=f")
2662         (float:DF (match_operand:SI 1 "register_operand"  "d")))
2663    (clobber (reg:CC 33))]
2664   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2665   "cdfbr\\t%0,%1"
2666   [(set_attr "op_type" "RRE")
2667    (set_attr "type"   "other" )])
2668
2669 (define_insn "floatsidf2_ibm"
2670   [(set (match_operand:DF 0 "register_operand" "=f")
2671         (float:DF (match_operand:SI 1 "register_operand" "d")))
2672    (use (match_operand:DI 2 "immediate_operand" "m"))
2673    (use (match_operand:BLK 3 "memory_operand" "m"))
2674    (clobber (reg:CC 33))]
2675   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2676   "*
2677 {
2678    output_asm_insn (\"st\\t%1,%N3\", operands);
2679    output_asm_insn (\"xi\\t%N3,128\", operands);
2680    output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2681    output_asm_insn (\"ld\\t%0,%3\", operands);
2682    return \"sd\\t%0,%2\";
2683 }"
2684   [(set_attr "op_type" "NN")
2685    (set_attr "type"    "other" )
2686    (set_attr "length"  "20")])
2687
2688 ;
2689 ; floatsisf2 instruction pattern(s).
2690 ;
2691
2692 (define_expand "floatsisf2"
2693   [(parallel
2694     [(set (match_operand:SF 0 "register_operand" "")
2695           (float:SF (match_operand:SI 1 "register_operand" "")))
2696      (clobber (reg:CC 33))])]
2697   "TARGET_HARD_FLOAT"
2698   "
2699 {
2700   if (TARGET_IBM_FLOAT)
2701     {
2702       /* Use the POP algorithm to convert to DFmode and then truncate.  */
2703       rtx temp = gen_reg_rtx (DFmode);
2704       emit_insn (gen_floatsidf2 (temp, operands[1]));
2705       emit_insn (gen_truncdfsf2 (operands[0], temp));
2706       DONE;
2707     }
2708 }")
2709
2710 (define_insn "floatsisf2_ieee"
2711   [(set (match_operand:SF 0 "register_operand" "=f")
2712         (float:SF (match_operand:SI 1 "register_operand" "d")))
2713    (clobber (reg:CC 33))]
2714   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2715   "cefbr\\t%0,%1"
2716   [(set_attr "op_type" "RRE")
2717    (set_attr "type"    "other" )])
2718
2719 ;
2720 ; truncdfsf2 instruction pattern(s).
2721 ;
2722
2723 (define_expand "truncdfsf2"
2724   [(set (match_operand:SF 0 "register_operand" "")
2725         (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2726   "TARGET_HARD_FLOAT"
2727   "")
2728
2729 (define_insn "truncdfsf2_ieee"
2730   [(set (match_operand:SF 0 "register_operand" "=f")
2731         (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2732   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2733   "ledbr\\t%0,%1"
2734   [(set_attr "op_type"  "RRE")])
2735
2736 (define_insn "truncdfsf2_ibm"
2737   [(set (match_operand:SF 0 "register_operand" "=f,f")
2738         (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2739   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2740   "@
2741    lrer\\t%0,%1
2742    le\\t%0,%1"
2743   [(set_attr "op_type"  "RR,RX")
2744    (set_attr "atype"    "reg,mem")])
2745
2746 ;
2747 ; extendsfdf2 instruction pattern(s).
2748 ;
2749
2750 (define_expand "extendsfdf2"
2751   [(set (match_operand:DF 0 "register_operand" "")
2752         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2753   "TARGET_HARD_FLOAT"
2754   "
2755 {
2756   if (TARGET_IBM_FLOAT)
2757     {
2758       emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2759       DONE;
2760     }
2761 }")
2762
2763 (define_insn "extendsfdf2_ieee"
2764   [(set (match_operand:DF 0 "register_operand" "=f,f")
2765         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,m")))]
2766   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2767   "@
2768    ldebr\\t%0,%1
2769    ldeb\\t%0,%1"
2770   [(set_attr "op_type"  "RRE,RXE")])
2771
2772 (define_insn "extendsfdf2_ibm"
2773   [(set (match_operand:DF 0 "register_operand" "=f,f")
2774         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2775    (clobber (reg:CC 33))]
2776   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2777   "@
2778    sdr\\t%0,%0\;ler\\t%0,%1
2779    sdr\\t%0,%0\;le\\t%0,%1"
2780   [(set_attr "op_type"  "RRE,RXE")
2781    (set_attr "atype"    "reg,mem")
2782    (set_attr "type"     "o2,o2")])
2783
2784
2785 ;;
2786 ;; ARITHMETRIC OPERATIONS
2787 ;;
2788 ;  arithmetric operations set the ConditionCode,
2789 ;  because of unpredictable Bits in Register for Halfword and Byte
2790 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
2791
2792 ;;
2793 ;;- Add instructions.
2794 ;;
2795
2796 ;
2797 ; adddi3 instruction pattern(s).
2798 ;
2799
2800 (define_insn "*la_64_cc"
2801   [(set (match_operand:DI 0 "register_operand" "=d")
2802         (match_operand:QI 1 "address_operand"  "p"))
2803    (clobber (reg:CC 33))]
2804   "TARGET_64BIT
2805    && preferred_la_operand_p (operands[1], 1)"
2806   "#"
2807   [(set_attr "op_type"  "RX")
2808    (set_attr "atype"    "mem")
2809    (set_attr "type"     "la")])
2810
2811 (define_split
2812   [(set (match_operand:DI 0 "register_operand" "")
2813         (match_operand:QI 1 "address_operand" ""))
2814    (clobber (reg:CC 33))]
2815   "TARGET_64BIT && reload_completed
2816    && preferred_la_operand_p (operands[1], 0)"
2817   [(set (match_dup 0) (match_dup 1))])
2818
2819 (define_insn "*adddi3_sign"
2820   [(set (match_operand:DI 0 "register_operand" "=d,d")
2821         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2822                  (match_operand:DI 1 "register_operand" "0,0")))
2823    (clobber (reg:CC 33))]
2824   "TARGET_64BIT"
2825   "@
2826    agfr\\t%0,%2
2827    agf\\t%0,%2"
2828   [(set_attr "op_type"  "RRE,RXE")
2829    (set_attr "atype"    "reg,mem")])
2830
2831 (define_insn "*adddi3_zero_cc"
2832   [(set (reg 33)
2833         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2834                           (match_operand:DI 1 "register_operand" "0,0"))
2835                  (const_int 0)))
2836    (set (match_operand:DI 0 "register_operand" "=d,d")
2837         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2838   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2839   "@
2840    algfr\\t%0,%2
2841    algf\\t%0,%2"
2842   [(set_attr "op_type"  "RRE,RXE")
2843    (set_attr "atype"    "reg,mem")])
2844
2845 (define_insn "*adddi3_zero_cconly"
2846   [(set (reg 33)
2847         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2848                           (match_operand:DI 1 "register_operand" "0,0"))
2849                  (const_int 0)))
2850    (clobber (match_scratch:DI 0 "=d,d"))]
2851   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2852   "@
2853    algfr\\t%0,%2
2854    algf\\t%0,%2"
2855   [(set_attr "op_type"  "RRE,RXE")
2856    (set_attr "atype"    "reg,mem")])
2857
2858 (define_insn "*adddi3_zero"
2859   [(set (match_operand:DI 0 "register_operand" "=d,d")
2860         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2861                  (match_operand:DI 1 "register_operand" "0,0")))
2862    (clobber (reg:CC 33))]
2863   "TARGET_64BIT"
2864   "@
2865    algfr\\t%0,%2
2866    algf\\t%0,%2"
2867   [(set_attr "op_type"  "RRE,RXE")
2868    (set_attr "atype"    "reg,mem")])
2869
2870 (define_insn "*adddi3_imm_cc"
2871   [(set (reg 33)
2872         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2873                           (match_operand:DI 2 "const_int_operand" "K"))
2874                  (const_int 0)))
2875    (set (match_operand:DI 0 "register_operand" "=d")
2876         (plus:DI (match_dup 1) (match_dup 2)))]
2877   "TARGET_64BIT
2878    && s390_match_ccmode (insn, CCAmode)
2879    && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2880   "aghi\\t%0,%h2"
2881   [(set_attr "op_type"  "RI")
2882    (set_attr "atype"    "reg")])
2883
2884 (define_insn "*adddi3_cc"
2885   [(set (reg 33)
2886         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2887                           (match_operand:DI 2 "general_operand" "d,m"))
2888                  (const_int 0)))
2889    (set (match_operand:DI 0 "register_operand" "=d,d")
2890         (plus:DI (match_dup 1) (match_dup 2)))]
2891   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2892   "@
2893    algr\\t%0,%2
2894    alg\\t%0,%2"
2895   [(set_attr "op_type"  "RRE,RXE")
2896    (set_attr "atype"    "reg,mem")])
2897
2898 (define_insn "*adddi3_cconly"
2899   [(set (reg 33)
2900         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2901                           (match_operand:DI 2 "general_operand" "d,m"))
2902                  (const_int 0)))
2903    (clobber (match_scratch:DI 0 "=d,d"))]
2904   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2905   "@
2906    algr\\t%0,%2
2907    alg\\t%0,%2"
2908   [(set_attr "op_type"  "RRE,RXE")
2909    (set_attr "atype"    "reg,mem")])
2910
2911 (define_insn "*adddi3_cconly2"
2912   [(set (reg 33)
2913         (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2914                  (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
2915    (clobber (match_scratch:DI 0 "=d,d"))]
2916   "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
2917   "@
2918    algr\\t%0,%2
2919    alg\\t%0,%2"
2920   [(set_attr "op_type"  "RRE,RXE")
2921    (set_attr "atype"    "reg,mem")])
2922
2923 (define_insn "*adddi3_64"
2924   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2925         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
2926                  (match_operand:DI 2 "general_operand" "d,K,m") ) )
2927    (clobber (reg:CC 33))]
2928   "TARGET_64BIT"
2929   "@
2930    agr\\t%0,%2
2931    aghi\\t%0,%h2
2932    ag\\t%0,%2"
2933   [(set_attr "op_type"  "RRE,RI,RXE")
2934    (set_attr "atype"    "reg,reg,mem")])
2935
2936 (define_insn_and_split "*adddi3_31"
2937   [(set (match_operand:DI 0 "register_operand" "=&d")
2938         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
2939                  (match_operand:DI 2 "general_operand" "dm") ) )
2940    (clobber (reg:CC 33))]
2941   "!TARGET_64BIT"
2942   "#"
2943   "&& reload_completed"
2944   [(parallel
2945     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
2946      (clobber (reg:CC 33))])
2947    (parallel
2948     [(set (reg:CCL1 33)
2949           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
2950                         (match_dup 7)))
2951      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
2952    (set (pc)
2953         (if_then_else (ltu (reg:CCL1 33) (const_int 0))
2954                       (pc)
2955                       (label_ref (match_dup 9))))
2956    (parallel
2957     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
2958      (clobber (reg:CC 33))])
2959    (match_dup 9)]
2960   "operands[3] = operand_subword (operands[0], 0, 1, DImode);
2961    operands[4] = operand_subword (operands[1], 0, 1, DImode);
2962    operands[5] = operand_subword (operands[2], 0, 1, DImode);
2963    operands[6] = operand_subword (operands[0], 1, 1, DImode);
2964    operands[7] = operand_subword (operands[1], 1, 1, DImode);
2965    operands[8] = operand_subword (operands[2], 1, 1, DImode);
2966    operands[9] = gen_label_rtx ();"
2967   [(set_attr "op_type"  "NN")
2968    (set_attr "type"     "o3")])
2969
2970 (define_expand "adddi3"
2971   [(parallel
2972     [(set (match_operand:DI 0 "register_operand" "")
2973           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
2974                    (match_operand:DI 2 "general_operand" "")))
2975      (clobber (reg:CC 33))])]
2976   ""
2977   "")
2978
2979 (define_insn "*la_64"
2980   [(set (match_operand:DI 0 "register_operand" "=d")
2981         (match_operand:QI 1 "address_operand" "p"))]
2982   "TARGET_64BIT"
2983   "la\\t%0,%a1"
2984   [(set_attr "op_type" "RX")
2985    (set_attr "atype"   "mem")
2986    (set_attr "type"    "la")])
2987
2988 (define_expand "reload_indi"
2989   [(parallel [(match_operand:DI 0 "register_operand" "=a")
2990               (match_operand:DI 1 "s390_plus_operand" "")
2991               (match_operand:DI 2 "register_operand" "=&a")])]
2992   "TARGET_64BIT"
2993   "
2994 {
2995   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
2996   DONE;
2997 }")
2998
2999
3000 ;
3001 ; addsi3 instruction pattern(s).
3002 ;
3003
3004 (define_insn "*la_31_cc"
3005   [(set (match_operand:SI 0 "register_operand" "=d")
3006         (match_operand:QI 1 "address_operand"  "p"))
3007    (clobber (reg:CC 33))]
3008   "!TARGET_64BIT
3009    && preferred_la_operand_p (operands[1], 1)"
3010   "#"
3011   [(set_attr "op_type"  "RX")
3012    (set_attr "atype"    "mem")
3013    (set_attr "type"     "la")])
3014
3015 (define_split
3016   [(set (match_operand:SI 0 "register_operand" "")
3017         (match_operand:QI 1 "address_operand" ""))
3018    (clobber (reg:CC 33))]
3019   "!TARGET_64BIT && reload_completed
3020    && preferred_la_operand_p (operands[1], 0)"
3021   [(set (match_dup 0) (match_dup 1))])
3022
3023 (define_insn "*addsi3_imm_cc"
3024   [(set (reg 33)
3025         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3026                           (match_operand:SI 2 "const_int_operand" "K"))
3027                  (const_int 0)))
3028    (set (match_operand:SI 0 "register_operand" "=d")
3029         (plus:SI (match_dup 1) (match_dup 2)))]
3030   "s390_match_ccmode (insn, CCAmode)
3031    && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3032   "ahi\\t%0,%h2"
3033   [(set_attr "op_type"  "RI")
3034    (set_attr "atype"    "reg")])
3035
3036 (define_insn "*addsi3_carry1_cc"
3037   [(set (reg 33)
3038         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3039                           (match_operand:SI 2 "general_operand" "d,m"))
3040                  (match_dup 1)))
3041    (set (match_operand:SI 0 "register_operand" "=d,d")
3042         (plus:SI (match_dup 1) (match_dup 2)))]
3043   "s390_match_ccmode (insn, CCL1mode)"
3044   "@
3045    alr\\t%0,%2
3046    al\\t%0,%2"
3047   [(set_attr "op_type"  "RR,RX")
3048    (set_attr "atype"    "reg,mem")])
3049
3050 (define_insn "*addsi3_carry1_cconly"
3051   [(set (reg 33)
3052         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3053                           (match_operand:SI 2 "general_operand" "d,m"))
3054                  (match_dup 1)))
3055    (clobber (match_scratch:SI 0 "=d,d"))]
3056   "s390_match_ccmode (insn, CCL1mode)"
3057   "@
3058    alr\\t%0,%2
3059    al\\t%0,%2"
3060   [(set_attr "op_type"  "RR,RX")
3061    (set_attr "atype"    "reg,mem")])
3062
3063 (define_insn "*addsi3_carry2_cc"
3064   [(set (reg 33)
3065         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3066                           (match_operand:SI 2 "general_operand" "d,m"))
3067                  (match_dup 2)))
3068    (set (match_operand:SI 0 "register_operand" "=d,d")
3069         (plus:SI (match_dup 1) (match_dup 2)))]
3070   "s390_match_ccmode (insn, CCL1mode)"
3071   "@
3072    alr\\t%0,%2
3073    al\\t%0,%2"
3074   [(set_attr "op_type"  "RR,RX")
3075    (set_attr "atype"    "reg,mem")])
3076
3077 (define_insn "*addsi3_carry2_cconly"
3078   [(set (reg 33)
3079         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3080                           (match_operand:SI 2 "general_operand" "d,m"))
3081                  (match_dup 2)))
3082    (clobber (match_scratch:SI 0 "=d,d"))]
3083   "s390_match_ccmode (insn, CCL1mode)"
3084   "@
3085    alr\\t%0,%2
3086    al\\t%0,%2"
3087   [(set_attr "op_type"  "RR,RX")
3088    (set_attr "atype"    "reg,mem")])
3089
3090 (define_insn "*addsi3_cc"
3091   [(set (reg 33)
3092         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3093                           (match_operand:SI 2 "general_operand" "d,m"))
3094                  (const_int 0)))
3095    (set (match_operand:SI 0 "register_operand" "=d,d")
3096         (plus:SI (match_dup 1) (match_dup 2)))]
3097   "s390_match_ccmode (insn, CCLmode)"
3098   "@
3099    alr\\t%0,%2
3100    al\\t%0,%2"
3101   [(set_attr "op_type"  "RR,RX")
3102    (set_attr "atype"    "reg,mem")])
3103
3104 (define_insn "*addsi3_cconly"
3105   [(set (reg 33)
3106         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3107                           (match_operand:SI 2 "general_operand" "d,m"))
3108                  (const_int 0)))
3109    (clobber (match_scratch:SI 0 "=d,d"))]
3110   "s390_match_ccmode (insn, CCLmode)"
3111   "@
3112    alr\\t%0,%2
3113    al\\t%0,%2"
3114   [(set_attr "op_type"  "RR,RX")
3115    (set_attr "atype"    "reg,mem")])
3116
3117 (define_insn "*addsi3_cconly2"
3118   [(set (reg 33)
3119         (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3120                  (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3121    (clobber (match_scratch:SI 0 "=d,d"))]
3122   "s390_match_ccmode(insn, CCLmode)"
3123   "@
3124    alr\\t%0,%2
3125    al\\t%0,%2"
3126   [(set_attr "op_type"  "RR,RX")
3127    (set_attr "atype"    "reg,mem")])
3128
3129 (define_insn "*addsi3_sign"
3130   [(set (match_operand:SI 0 "register_operand" "=d")
3131         (plus:SI (match_operand:SI 1 "register_operand" "0")
3132                  (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3133    (clobber (reg:CC 33))]
3134   ""
3135   "ah\\t%0,%2"
3136   [(set_attr "op_type"  "RX")
3137    (set_attr "atype"    "mem")])
3138
3139 (define_insn "*addsi3_sub"
3140   [(set (match_operand:SI 0 "register_operand" "=d")
3141         (plus:SI (match_operand:SI 1 "register_operand" "0")
3142                  (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3143    (clobber (reg:CC 33))]
3144   ""
3145   "ah\\t%0,%2"
3146   [(set_attr "op_type"  "RX")
3147    (set_attr "atype"    "mem")])
3148
3149 (define_insn "addsi3"
3150   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3151         (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3152                  (match_operand:SI 2 "general_operand" "d,K,m")))
3153    (clobber (reg:CC 33))]
3154   ""
3155   "@
3156    ar\\t%0,%2
3157    ahi\\t%0,%h2
3158    a\\t%0,%2"
3159   [(set_attr "op_type"  "RR,RI,RX")
3160    (set_attr "atype"    "reg,reg,mem")])
3161
3162 (define_insn "*la_31"
3163   [(set (match_operand:SI 0 "register_operand" "=d")
3164         (match_operand:QI 1 "address_operand" "p"))]
3165   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3166   "la\\t%0,%a1"
3167   [(set_attr "op_type"  "RX")
3168    (set_attr "atype"    "mem")
3169    (set_attr "type"     "la")])
3170
3171 (define_insn "*la_31_and"
3172   [(set (match_operand:SI 0 "register_operand" "=d")
3173         (and:SI (match_operand:QI 1 "address_operand" "p")
3174                 (const_int 2147483647)))]
3175   "!TARGET_64BIT"
3176   "la\\t%0,%a1"
3177   [(set_attr "op_type"  "RX")
3178    (set_attr "atype"    "mem")
3179    (set_attr "type"     "la")])
3180
3181 (define_insn_and_split "*la_31_and_cc"
3182   [(set (match_operand:SI 0 "register_operand" "=d")
3183         (and:SI (match_operand:QI 1 "address_operand" "p")
3184                 (const_int 2147483647)))
3185    (clobber (reg:CC 33))]
3186   "!TARGET_64BIT"
3187   "#"
3188   "&& reload_completed"
3189   [(set (match_dup 0)
3190         (and:SI (match_dup 1) (const_int 2147483647)))]
3191   ""
3192   [(set_attr "op_type"  "RX")
3193    (set_attr "atype"    "mem")
3194    (set_attr "type"     "la")])
3195
3196 (define_insn "force_la_31"
3197   [(set (match_operand:SI 0 "register_operand" "=d")
3198         (match_operand:QI 1 "address_operand" "p"))
3199    (use (const_int 0))]
3200   "!TARGET_64BIT"
3201   "la\\t%0,%a1"
3202   [(set_attr "op_type"  "RX")
3203    (set_attr "atype"    "mem")
3204    (set_attr "type"     "la")])
3205
3206 (define_expand "reload_insi"
3207   [(parallel [(match_operand:SI 0 "register_operand" "=a")
3208               (match_operand:SI 1 "s390_plus_operand" "")
3209               (match_operand:SI 2 "register_operand" "=&a")])]
3210   "!TARGET_64BIT"
3211   "
3212 {
3213   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3214   DONE;
3215 }")
3216
3217
3218 ;
3219 ; adddf3 instruction pattern(s).
3220 ;
3221
3222 (define_expand "adddf3"
3223   [(parallel
3224     [(set (match_operand:DF 0 "register_operand" "=f,f")
3225           (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3226                    (match_operand:DF 2 "general_operand" "f,m")))
3227      (clobber (reg:CC 33))])]
3228   "TARGET_HARD_FLOAT"
3229   "")
3230
3231 (define_insn "*adddf3"
3232   [(set (match_operand:DF 0 "register_operand" "=f,f")
3233         (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3234                  (match_operand:DF 2 "general_operand" "f,m")))
3235    (clobber (reg:CC 33))]
3236   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3237   "@
3238    adbr\\t%0,%2
3239    adb\\t%0,%2"
3240   [(set_attr "op_type"  "RRE,RXE")
3241    (set_attr "atype"    "reg,mem")])
3242
3243 (define_insn "*adddf3_ibm"
3244   [(set (match_operand:DF 0 "register_operand" "=f,f")
3245         (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3246                  (match_operand:DF 2 "general_operand" "f,m")))
3247    (clobber (reg:CC 33))]
3248   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3249   "@
3250    adr\\t%0,%2
3251    ad\\t%0,%2"
3252   [(set_attr "op_type"  "RR,RX")
3253    (set_attr "atype"    "reg,mem")])
3254
3255 ;
3256 ; addsf3 instruction pattern(s).
3257 ;
3258
3259 (define_expand "addsf3"
3260   [(parallel
3261     [(set (match_operand:SF 0 "register_operand" "=f,f")
3262           (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3263                    (match_operand:SF 2 "general_operand" "f,m")))
3264      (clobber (reg:CC 33))])]
3265   "TARGET_HARD_FLOAT"
3266   "")
3267
3268 (define_insn "*addsf3"
3269   [(set (match_operand:SF 0 "register_operand" "=f,f")
3270         (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3271                  (match_operand:SF 2 "general_operand" "f,m")))
3272    (clobber (reg:CC 33))]
3273   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3274   "@
3275    aebr\\t%0,%2
3276    aeb\\t%0,%2"
3277   [(set_attr "op_type"  "RRE,RXE")
3278    (set_attr "atype"    "reg,mem")])
3279
3280 (define_insn "*addsf3"
3281   [(set (match_operand:SF 0 "register_operand" "=f,f")
3282         (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3283                  (match_operand:SF 2 "general_operand" "f,m")))
3284    (clobber (reg:CC 33))]
3285   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3286   "@
3287    aer\\t%0,%2
3288    ae\\t%0,%2"
3289   [(set_attr "op_type"  "RR,RX")
3290    (set_attr "atype"    "reg,mem")])
3291
3292
3293 ;;
3294 ;;- Subtract instructions.
3295 ;;
3296
3297 ;
3298 ; subdi3 instruction pattern(s).
3299 ;
3300
3301 (define_insn "*subdi3_sign"
3302   [(set (match_operand:DI 0 "register_operand" "=d,d")
3303         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3304                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3305    (clobber (reg:CC 33))]
3306   "TARGET_64BIT"
3307   "@
3308    sgfr\\t%0,%2
3309    sgf\\t%0,%2"
3310   [(set_attr "op_type"  "RRE,RXE")
3311    (set_attr "atype"    "reg,mem")])
3312
3313 (define_insn "*subdi3_zero_cc"
3314   [(set (reg 33)
3315         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3316                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3317                  (const_int 0)))
3318    (set (match_operand:DI 0 "register_operand" "=d,d")
3319         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3320   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3321   "@
3322    slgfr\\t%0,%2
3323    slgf\\t%0,%2"
3324   [(set_attr "op_type"  "RRE,RXE")
3325    (set_attr "atype"    "reg,mem")])
3326
3327 (define_insn "*subdi3_zero_cconly"
3328   [(set (reg 33)
3329         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3330                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3331                  (const_int 0)))
3332    (clobber (match_scratch:DI 0 "=d,d"))]
3333   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3334   "@
3335    slgfr\\t%0,%2
3336    slgf\\t%0,%2"
3337   [(set_attr "op_type"  "RRE,RXE")
3338    (set_attr "atype"    "reg,mem")])
3339
3340 (define_insn "*subdi3_zero"
3341   [(set (match_operand:DI 0 "register_operand" "=d,d")
3342         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3343                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3344    (clobber (reg:CC 33))]
3345   "TARGET_64BIT"
3346   "@
3347    slgfr\\t%0,%2
3348    slgf\\t%0,%2"
3349   [(set_attr "op_type"  "RRE,RXE")
3350    (set_attr "atype"    "reg,mem")])
3351
3352 (define_insn "*subdi3_cc"
3353   [(set (reg 33)
3354         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3355                            (match_operand:DI 2 "general_operand" "d,m"))
3356                  (const_int 0)))
3357    (set (match_operand:DI 0 "register_operand" "=d,d")
3358         (minus:DI (match_dup 1) (match_dup 2)))]
3359   "s390_match_ccmode (insn, CCLmode)"
3360   "@
3361    slgr\\t%0,%2
3362    slg\\t%0,%2"
3363   [(set_attr "op_type"  "RRE,RXE")
3364    (set_attr "atype"    "reg,mem")])
3365
3366 (define_insn "*subdi3_cconly"
3367   [(set (reg 33)
3368         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3369                            (match_operand:DI 2 "general_operand" "d,m"))
3370                  (const_int 0)))
3371    (clobber (match_scratch:DI 0 "=d,d"))]
3372   "s390_match_ccmode (insn, CCLmode)"
3373   "@
3374    slgr\\t%0,%2
3375    slg\\t%0,%2"
3376   [(set_attr "op_type"  "RRE,RXE")
3377    (set_attr "atype"    "reg,mem")])
3378
3379 (define_insn "*subdi3_64"
3380   [(set (match_operand:DI 0 "register_operand" "=d,d")
3381         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3382                   (match_operand:DI 2 "general_operand" "d,m") ) )
3383    (clobber (reg:CC 33))]
3384   "TARGET_64BIT"
3385   "@
3386    sgr\\t%0,%2
3387    sg\\t%0,%2"
3388   [(set_attr "op_type"  "RRE,RRE")
3389    (set_attr "atype"    "reg,mem")])
3390
3391 (define_insn_and_split "*subdi3_31"
3392   [(set (match_operand:DI 0 "register_operand" "=&d")
3393         (minus:DI (match_operand:DI 1 "register_operand" "0")
3394                   (match_operand:DI 2 "general_operand" "dm") ) )
3395    (clobber (reg:CC 33))]
3396   "!TARGET_64BIT"
3397   "#"
3398   "&& reload_completed"
3399   [(parallel
3400     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3401      (clobber (reg:CC 33))])
3402    (parallel
3403     [(set (reg:CCL2 33)
3404           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3405                         (match_dup 7)))
3406      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3407    (set (pc)
3408         (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3409                       (pc)
3410                       (label_ref (match_dup 9))))
3411    (parallel
3412     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3413      (clobber (reg:CC 33))])
3414    (match_dup 9)]
3415   "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3416    operands[4] = operand_subword (operands[1], 0, 1, DImode);
3417    operands[5] = operand_subword (operands[2], 0, 1, DImode);
3418    operands[6] = operand_subword (operands[0], 1, 1, DImode);
3419    operands[7] = operand_subword (operands[1], 1, 1, DImode);
3420    operands[8] = operand_subword (operands[2], 1, 1, DImode);
3421    operands[9] = gen_label_rtx ();"
3422   [(set_attr "op_type"  "NN")
3423    (set_attr "type"     "o3")])
3424
3425 (define_expand "subdi3"
3426   [(parallel
3427     [(set (match_operand:DI 0 "register_operand" "")
3428           (minus:DI (match_operand:DI 1 "register_operand" "")
3429                     (match_operand:DI 2 "general_operand" "")))
3430      (clobber (reg:CC 33))])]
3431   ""
3432   "")
3433
3434 ;
3435 ; subsi3 instruction pattern(s).
3436 ;
3437
3438 (define_insn "*subsi3_borrow_cc"
3439   [(set (reg 33)
3440         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3441                            (match_operand:SI 2 "general_operand" "d,m"))
3442                  (match_dup 1)))
3443    (set (match_operand:SI 0 "register_operand" "=d,d")
3444         (minus:SI (match_dup 1) (match_dup 2)))]
3445   "s390_match_ccmode(insn, CCL2mode)"
3446   "@
3447    slr\\t%0,%2
3448    sl\\t%0,%2"
3449   [(set_attr "op_type"  "RR,RX")
3450    (set_attr "atype"    "reg,mem")])
3451
3452 (define_insn "*subsi3_borrow_cconly"
3453   [(set (reg 33)
3454         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3455                            (match_operand:SI 2 "general_operand" "d,m"))
3456                  (match_dup 1)))
3457    (clobber (match_scratch:SI 0 "=d,d"))]
3458   "s390_match_ccmode(insn, CCL2mode)"
3459   "@
3460    slr\\t%0,%2
3461    sl\\t%0,%2"
3462   [(set_attr "op_type"  "RR,RX")
3463    (set_attr "atype"    "reg,mem")])
3464
3465 (define_insn "*subsi3_cc"
3466   [(set (reg 33)
3467         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3468                            (match_operand:SI 2 "general_operand" "d,m"))
3469                  (const_int 0)))
3470    (set (match_operand:SI 0 "register_operand" "=d,d")
3471         (minus:SI (match_dup 1) (match_dup 2)))]
3472   "s390_match_ccmode(insn, CCLmode)"
3473   "@
3474    slr\\t%0,%2
3475    sl\\t%0,%2"
3476   [(set_attr "op_type"  "RR,RX")
3477    (set_attr "atype"    "reg,mem")])
3478
3479 (define_insn "*subsi3_cconly"
3480   [(set (reg 33)
3481         (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3482                            (match_operand:SI 2 "general_operand" "d,m"))
3483                  (const_int 0)))
3484    (clobber (match_scratch:SI 0 "=d,d"))]
3485   "s390_match_ccmode(insn, CCLmode)"
3486   "@
3487    slr\\t%0,%2
3488    sl\\t%0,%2"
3489   [(set_attr "op_type"  "RR,RX")
3490    (set_attr "atype"    "reg,mem")])
3491
3492 (define_insn "*subsi3_sign"
3493   [(set (match_operand:SI 0 "register_operand" "=d")
3494         (minus:SI (match_operand:SI 1 "register_operand" "0")
3495                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3496    (clobber (reg:CC 33))]
3497   ""
3498   "sh\\t%0,%2"
3499   [(set_attr "op_type"  "RX")
3500    (set_attr "atype"    "mem")])
3501
3502 (define_insn "*subsi3_sub"
3503   [(set (match_operand:SI 0 "register_operand" "=d")
3504         (minus:SI (match_operand:SI 1 "register_operand" "0")
3505                   (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3506    (clobber (reg:CC 33))]
3507   ""
3508   "sh\\t%0,%2"
3509   [(set_attr "op_type"  "RX")
3510    (set_attr "atype"    "mem")])
3511
3512 (define_insn "subsi3"
3513   [(set (match_operand:SI 0 "register_operand" "=d,d")
3514         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3515                   (match_operand:SI 2 "general_operand" "d,m")))
3516    (clobber (reg:CC 33))]
3517   ""
3518   "@
3519    sr\\t%0,%2
3520    s\\t%0,%2"
3521   [(set_attr "op_type"  "RR,RX")
3522    (set_attr "atype"    "reg,mem")])
3523
3524
3525 ;
3526 ; subdf3 instruction pattern(s).
3527 ;
3528
3529 (define_expand "subdf3"
3530   [(parallel
3531     [(set (match_operand:DF 0 "register_operand" "=f,f")
3532           (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3533                     (match_operand:DF 2 "general_operand" "f,m")))
3534      (clobber (reg:CC 33))])]
3535   "TARGET_HARD_FLOAT"
3536   "")
3537
3538 (define_insn "*subdf3"
3539   [(set (match_operand:DF 0 "register_operand" "=f,f")
3540         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3541                   (match_operand:DF 2 "general_operand" "f,m")))
3542    (clobber (reg:CC 33))]
3543   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3544   "@
3545    sdbr\\t%0,%2
3546    sdb\\t%0,%2"
3547   [(set_attr "op_type"  "RRE,RXE")
3548    (set_attr "atype"    "reg,mem")])
3549
3550 (define_insn "*subdf3_ibm"
3551   [(set (match_operand:DF 0 "register_operand" "=f,f")
3552         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3553                   (match_operand:DF 2 "general_operand" "f,m")))
3554    (clobber (reg:CC 33))]
3555   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3556   "@
3557    sdr\\t%0,%2
3558    sd\\t%0,%2"
3559   [(set_attr "op_type"  "RR,RX")
3560    (set_attr "atype"    "reg,mem")])
3561
3562 ;
3563 ; subsf3 instruction pattern(s).
3564 ;
3565
3566 (define_expand "subsf3"
3567   [(parallel
3568     [(set (match_operand:SF 0 "register_operand" "=f,f")
3569           (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3570                     (match_operand:SF 2 "general_operand" "f,m")))
3571      (clobber (reg:CC 33))])]
3572   "TARGET_HARD_FLOAT"
3573   "")
3574
3575 (define_insn "*subsf3"
3576   [(set (match_operand:SF 0 "register_operand" "=f,f")
3577         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3578                   (match_operand:SF 2 "general_operand" "f,m")))
3579    (clobber (reg:CC 33))]
3580   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3581   "@
3582    sebr\\t%0,%2
3583    seb\\t%0,%2"
3584   [(set_attr "op_type"  "RRE,RXE")
3585    (set_attr "atype"    "reg,mem")])
3586
3587 (define_insn "*subsf3_ibm"
3588   [(set (match_operand:SF 0 "register_operand" "=f,f")
3589         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3590                   (match_operand:SF 2 "general_operand" "f,m")))
3591    (clobber (reg:CC 33))]
3592   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3593   "@
3594    ser\\t%0,%2
3595    se\\t%0,%2"
3596   [(set_attr "op_type"  "RR,RX")
3597    (set_attr "atype"    "reg,mem")])
3598
3599
3600 ;;
3601 ;;- Multiply instructions.
3602 ;;
3603
3604 ;
3605 ; muldi3 instruction pattern(s).
3606 ;
3607
3608 (define_insn "*muldi3_sign"
3609   [(set (match_operand:DI 0 "register_operand" "=d,d")
3610         (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3611                  (match_operand:DI 1 "register_operand" "0,0")))]
3612   "TARGET_64BIT"
3613   "@
3614    msgfr\\t%0,%2
3615    msgf\\t%0,%2"
3616   [(set_attr "op_type"  "RRE,RXE")
3617    (set_attr "atype"    "reg,mem")
3618    (set_attr "type"     "imul")])
3619
3620
3621 (define_insn "muldi3"
3622   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3623         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3624                  (match_operand:DI 2 "general_operand" "d,K,m")))]
3625   "TARGET_64BIT"
3626   "@
3627    msgr\\t%0,%2
3628    mghi\\t%0,%h2
3629    msg\\t%0,%2"
3630   [(set_attr "op_type"  "RRE,RI,RXE")
3631    (set_attr "atype"    "reg,reg,mem")
3632    (set_attr "type"     "imul")])
3633
3634 ;
3635 ; mulsi3 instruction pattern(s).
3636 ;
3637
3638 (define_insn "mulsi3"
3639   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3640         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3641                   (match_operand:SI 2 "general_operand" "d,K,m")))]
3642   ""
3643   "@
3644    msr\\t%0,%2
3645    mhi\\t%0,%h2
3646    ms\\t%0,%2"
3647   [(set_attr "op_type"  "RRE,RI,RX")
3648    (set_attr "atype"    "reg,reg,mem")
3649    (set_attr "type"     "imul")])
3650
3651 ;
3652 ; mulsidi3 instruction pattern(s).
3653 ;
3654
3655 (define_expand "mulsidi3"
3656   [(set (match_operand:DI 0 "register_operand" "")
3657         (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3658                  (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3659   "!TARGET_64BIT"
3660   "
3661 {
3662   rtx insn;
3663
3664   emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3665   insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3666
3667   REG_NOTES (insn) =
3668         gen_rtx_EXPR_LIST (REG_EQUAL,
3669                            gen_rtx_MULT (DImode,
3670                                 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3671                                 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3672                            REG_NOTES (insn));
3673   DONE;
3674 }")
3675
3676 (define_insn "mulsi_6432"
3677    [(set (match_operand:DI 0 "register_operand" "=d,d")
3678          (mult:DI (sign_extend:DI
3679                     (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3680                   (sign_extend:DI
3681                     (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3682    "!TARGET_64BIT"
3683    "@
3684     mr\\t%0,%2
3685     m\\t%0,%2"
3686   [(set_attr "op_type"  "RR,RX")
3687    (set_attr "atype"    "reg,mem")
3688    (set_attr "type"     "imul")])
3689
3690 ;
3691 ; muldf3 instruction pattern(s).
3692 ;
3693
3694 (define_expand "muldf3"
3695   [(parallel
3696     [(set (match_operand:DF 0 "register_operand" "=f,f")
3697           (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3698                    (match_operand:DF 2 "general_operand" "f,m")))
3699      (clobber (reg:CC 33))])]
3700   "TARGET_HARD_FLOAT"
3701   "")
3702
3703 (define_insn "*muldf3"
3704   [(set (match_operand:DF 0 "register_operand" "=f,f")
3705         (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3706                  (match_operand:DF 2 "general_operand" "f,m")))
3707    (clobber (reg:CC 33))]
3708   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3709   "@
3710    mdbr\\t%0,%2
3711    mdb\\t%0,%2"
3712   [(set_attr "op_type"  "RRE,RXE")
3713    (set_attr "type"     "fmul")
3714    (set_attr "atype"    "reg,mem")])
3715
3716 (define_insn "*muldf3_ibm"
3717   [(set (match_operand:DF 0 "register_operand" "=f,f")
3718         (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3719                  (match_operand:DF 2 "general_operand" "f,m")))
3720    (clobber (reg:CC 33))]
3721   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3722   "@
3723    mdr\\t%0,%2
3724    md\\t%0,%2"
3725   [(set_attr "op_type"  "RR,RX")
3726    (set_attr "type"    "fmul")
3727    (set_attr "atype"    "reg,mem")])
3728
3729 ;
3730 ; mulsf3 instruction pattern(s).
3731 ;
3732
3733 (define_expand "mulsf3"
3734   [(parallel
3735     [(set (match_operand:SF 0 "register_operand" "=f,f")
3736           (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3737                    (match_operand:SF 2 "general_operand" "f,m")))
3738      (clobber (reg:CC 33))])]
3739   "TARGET_HARD_FLOAT"
3740   "")
3741
3742 (define_insn "*mulsf3"
3743   [(set (match_operand:SF 0 "register_operand" "=f,f")
3744         (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3745                  (match_operand:SF 2 "general_operand" "f,m")))
3746    (clobber (reg:CC 33))]
3747   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3748   "@
3749    meebr\\t%0,%2
3750    meeb\\t%0,%2"
3751   [(set_attr "op_type"  "RRE,RXE")
3752    (set_attr "type"     "fmul")
3753    (set_attr "atype"    "reg,mem")])
3754
3755 (define_insn "*mulsf3_ibm"
3756   [(set (match_operand:SF 0 "register_operand" "=f,f")
3757         (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3758                  (match_operand:SF 2 "general_operand" "f,m")))
3759    (clobber (reg:CC 33))]
3760   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3761   "@
3762    mer\\t%0,%2
3763    me\\t%0,%2"
3764   [(set_attr "op_type"  "RR,RX")
3765    (set_attr "type"     "fmul")
3766    (set_attr "atype"    "reg,mem")])
3767
3768
3769 ;;
3770 ;;- Divide and modulo instructions.
3771 ;;
3772
3773 ;
3774 ; divmoddi4 instruction pattern(s).
3775 ;
3776
3777 (define_expand "divmoddi4"
3778   [(parallel [(set (match_operand:DI 0 "general_operand" "")
3779                    (div:DI (match_operand:DI 1 "general_operand" "")
3780                            (match_operand:DI 2 "general_operand" "")))
3781               (set (match_operand:DI 3 "general_operand" "")
3782                    (mod:DI (match_dup 1) (match_dup 2)))])
3783    (clobber (match_dup 4))]
3784   "TARGET_64BIT"
3785   "
3786 {
3787   rtx insn, div_equal, mod_equal, equal;
3788
3789   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3790   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3791   equal = gen_rtx_IOR (TImode,
3792                        gen_rtx_ZERO_EXTEND (TImode, div_equal),
3793                        gen_rtx_ASHIFT (TImode,
3794                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3795                                        GEN_INT (64)));
3796
3797   operands[4] = gen_reg_rtx(TImode);
3798   emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3799   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3800   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3801   insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3802   REG_NOTES (insn) =
3803         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3804
3805   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3806   REG_NOTES (insn) =
3807         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3808
3809   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3810   REG_NOTES (insn) =
3811         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3812
3813   DONE;
3814 }")
3815
3816 (define_insn "divmodtidi3"
3817   [(set (match_operand:TI 0 "register_operand" "=d,d")
3818         (ior:TI
3819           (zero_extend:TI
3820             (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3821                     (match_operand:DI 2 "general_operand" "d,m")))
3822           (ashift:TI
3823             (zero_extend:TI
3824               (mod:DI (truncate:DI (match_dup 1))
3825                       (match_dup 2)))
3826             (const_int 64))))]
3827   "TARGET_64BIT"
3828   "@
3829    dsgr\\t%0,%2
3830    dsg\\t%0,%2"
3831   [(set_attr "op_type"  "RRE,RXE")
3832    (set_attr "type"     "idiv")
3833    (set_attr "atype"    "reg,mem")])
3834
3835 (define_insn "divmodtisi3"
3836   [(set (match_operand:TI 0 "register_operand" "=d,d")
3837         (ior:TI
3838           (zero_extend:TI
3839             (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3840                     (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3841           (ashift:TI
3842             (zero_extend:TI
3843               (mod:DI (truncate:DI (match_dup 1))
3844                       (sign_extend:DI (match_dup 2))))
3845             (const_int 64))))]
3846   "TARGET_64BIT"
3847   "@
3848    dsgfr\\t%0,%2
3849    dsgf\\t%0,%2"
3850   [(set_attr "op_type"  "RRE,RXE")
3851    (set_attr "type"     "idiv")
3852    (set_attr "atype"    "reg,mem")])
3853
3854 ;
3855 ; udivmoddi4 instruction pattern(s).
3856 ;
3857
3858 (define_expand "udivmoddi4"
3859   [(parallel [(set (match_operand:DI 0 "general_operand" "")
3860                    (udiv:DI (match_operand:DI 1 "general_operand" "")
3861                             (match_operand:DI 2 "nonimmediate_operand" "")))
3862               (set (match_operand:DI 3 "general_operand" "")
3863                    (umod:DI (match_dup 1) (match_dup 2)))])
3864    (clobber (match_dup 4))]
3865   "TARGET_64BIT"
3866   "
3867 {
3868   rtx insn, div_equal, mod_equal, equal;
3869
3870   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3871   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3872   equal = gen_rtx_IOR (TImode,
3873                        gen_rtx_ZERO_EXTEND (TImode, div_equal),
3874                        gen_rtx_ASHIFT (TImode,
3875                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3876                                        GEN_INT (64)));
3877
3878   operands[4] = gen_reg_rtx(TImode);
3879   emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3880   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3881   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3882   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3883   REG_NOTES (insn) =
3884         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3885
3886   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3887   REG_NOTES (insn) =
3888         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3889
3890   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3891   REG_NOTES (insn) =
3892         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3893
3894   DONE;
3895 }")
3896
3897 (define_insn "udivmodtidi3"
3898   [(set (match_operand:TI 0 "register_operand" "=d,d")
3899         (ior:TI (zero_extend:TI
3900                   (truncate:DI
3901                     (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3902                              (zero_extend:TI
3903                                (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3904                 (ashift:TI
3905                   (zero_extend:TI
3906                     (truncate:DI
3907                       (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3908                   (const_int 64))))]
3909   "TARGET_64BIT"
3910   "@
3911    dlgr\\t%0,%2
3912    dlg\\t%0,%2"
3913   [(set_attr "op_type"  "RRE,RXE")
3914    (set_attr "type"     "idiv")
3915    (set_attr "atype"    "reg,mem")])
3916
3917 ;
3918 ; divmodsi4 instruction pattern(s).
3919 ;
3920
3921 (define_expand "divmodsi4"
3922   [(parallel [(set (match_operand:SI 0 "general_operand" "")
3923                    (div:SI (match_operand:SI 1 "general_operand" "")
3924                            (match_operand:SI 2 "nonimmediate_operand" "")))
3925               (set (match_operand:SI 3 "general_operand" "")
3926                    (mod:SI (match_dup 1) (match_dup 2)))])
3927    (clobber (match_dup 4))]
3928   "!TARGET_64BIT"
3929   "
3930 {
3931   rtx insn, div_equal, mod_equal, equal;
3932
3933   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3934   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3935   equal = gen_rtx_IOR (DImode,
3936                        gen_rtx_ZERO_EXTEND (DImode, div_equal),
3937                        gen_rtx_ASHIFT (DImode,
3938                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3939                                        GEN_INT (32)));
3940
3941   operands[4] = gen_reg_rtx(DImode);
3942   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3943   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3944   REG_NOTES (insn) =
3945         gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3946
3947   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3948   REG_NOTES (insn) =
3949         gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3950
3951   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3952   REG_NOTES (insn) =
3953         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3954
3955   DONE;
3956 }")
3957
3958 (define_insn "divmoddisi3"
3959   [(set (match_operand:DI 0 "register_operand" "=d,d")
3960         (ior:DI (zero_extend:DI
3961                   (truncate:SI
3962                     (div:DI (match_operand:DI 1 "register_operand" "0,0")
3963                             (sign_extend:DI
3964                               (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3965                 (ashift:DI
3966                   (zero_extend:DI
3967                     (truncate:SI
3968                       (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
3969                   (const_int 32))))]
3970   "!TARGET_64BIT"
3971   "@
3972    dr\\t%0,%2
3973    d\\t%0,%2"
3974   [(set_attr "op_type"  "RR,RX")
3975    (set_attr "type"     "idiv")
3976    (set_attr "atype"    "reg,mem")])
3977
3978 ;
3979 ; udivsi3 and umodsi3 instruction pattern(s).
3980 ;
3981
3982
3983 (define_expand "udivsi3"
3984   [(set (match_operand:SI 0 "register_operand" "=d")
3985         (udiv:SI (match_operand:SI 1 "general_operand" "")
3986                  (match_operand:SI 2 "general_operand" "")))
3987    (clobber (match_dup 3))]
3988   "!TARGET_64BIT"
3989   "
3990 {
3991   rtx insn, udiv_equal, umod_equal, equal;
3992
3993   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3994   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
3995   equal = gen_rtx_IOR (DImode,
3996                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
3997                        gen_rtx_ASHIFT (DImode,
3998                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
3999                                        GEN_INT (32)));
4000
4001   operands[3] = gen_reg_rtx (DImode);
4002
4003   if (CONSTANT_P (operands[2]))
4004     {
4005       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4006         {
4007           rtx label1 = gen_label_rtx ();
4008
4009           operands[1] = make_safe_from (operands[1], operands[0]);
4010           emit_move_insn (operands[0], const0_rtx);
4011           emit_insn (gen_cmpsi (operands[1], operands[2]));
4012           emit_jump_insn (gen_bltu (label1));
4013           emit_move_insn (operands[0], const1_rtx);
4014           emit_label (label1);
4015         }
4016       else
4017         {
4018           operands[2] = force_reg (SImode, operands[2]);
4019           operands[2] = make_safe_from (operands[2], operands[0]);
4020
4021           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4022           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4023                                              operands[2]));
4024           REG_NOTES (insn) =
4025             gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4026
4027           insn = emit_move_insn (operands[0],
4028                                  gen_lowpart (SImode, operands[3]));
4029           REG_NOTES (insn) =
4030             gen_rtx_EXPR_LIST (REG_EQUAL,
4031                                udiv_equal, REG_NOTES (insn));
4032         }
4033     }
4034   else
4035     {
4036       rtx label1 = gen_label_rtx ();
4037       rtx label2 = gen_label_rtx ();
4038       rtx label3 = gen_label_rtx ();
4039
4040       operands[1] = force_reg (SImode, operands[1]);
4041       operands[1] = make_safe_from (operands[1], operands[0]);
4042       operands[2] = force_reg (SImode, operands[2]);
4043       operands[2] = make_safe_from (operands[2], operands[0]);
4044
4045       emit_move_insn (operands[0], const0_rtx);
4046       emit_insn (gen_cmpsi (operands[2], operands[1]));
4047       emit_jump_insn (gen_bgtu (label3));
4048       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4049       emit_jump_insn (gen_blt (label2));
4050       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4051       emit_jump_insn (gen_beq (label1));
4052       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4053       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4054                                          operands[2]));
4055       REG_NOTES (insn) =
4056       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4057
4058       insn = emit_move_insn (operands[0],
4059                              gen_lowpart (SImode, operands[3]));
4060       REG_NOTES (insn) =
4061       gen_rtx_EXPR_LIST (REG_EQUAL,
4062                                udiv_equal, REG_NOTES (insn));
4063       emit_jump (label3);
4064       emit_label (label1);
4065       emit_move_insn (operands[0], operands[1]);
4066       emit_jump (label3);
4067       emit_label (label2);
4068       emit_move_insn (operands[0], const1_rtx);
4069       emit_label (label3);
4070     }
4071   emit_move_insn (operands[0], operands[0]);
4072   DONE;
4073 }")
4074
4075 (define_expand "umodsi3"
4076   [(set (match_operand:SI 0 "register_operand" "=d")
4077         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4078                  (match_operand:SI 2 "nonimmediate_operand" "")))
4079    (clobber (match_dup 3))]
4080   "!TARGET_64BIT"
4081   "
4082 {
4083   rtx insn, udiv_equal, umod_equal, equal;
4084
4085   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4086   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4087   equal = gen_rtx_IOR (DImode,
4088                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4089                        gen_rtx_ASHIFT (DImode,
4090                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4091                                        GEN_INT (32)));
4092
4093   operands[3] = gen_reg_rtx (DImode);
4094
4095   if (CONSTANT_P (operands[2]))
4096     {
4097       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4098         {
4099           rtx label1 = gen_label_rtx ();
4100
4101           operands[1] = make_safe_from (operands[1], operands[0]);
4102           emit_move_insn (operands[0], operands[1]);
4103           emit_insn (gen_cmpsi (operands[0], operands[2]));
4104           emit_jump_insn (gen_bltu (label1));
4105           emit_insn (gen_abssi2 (operands[0], operands[2]));
4106           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4107           emit_label (label1);
4108         }
4109       else
4110         {
4111           operands[2] = force_reg (SImode, operands[2]);
4112           operands[2] = make_safe_from (operands[2], operands[0]);
4113
4114           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4115           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4116                                              operands[2]));
4117           REG_NOTES (insn) =
4118             gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4119
4120           insn = emit_move_insn (operands[0],
4121                                  gen_highpart (SImode, operands[3]));
4122           REG_NOTES (insn) =
4123             gen_rtx_EXPR_LIST (REG_EQUAL,
4124                                umod_equal, REG_NOTES (insn));
4125         }
4126     }
4127   else
4128     {
4129       rtx label1 = gen_label_rtx ();
4130       rtx label2 = gen_label_rtx ();
4131       rtx label3 = gen_label_rtx ();
4132
4133       operands[1] = force_reg (SImode, operands[1]);
4134       operands[1] = make_safe_from (operands[1], operands[0]);
4135       operands[2] = force_reg (SImode, operands[2]);
4136       operands[2] = make_safe_from (operands[2], operands[0]);
4137
4138       emit_move_insn(operands[0], operands[1]);
4139       emit_insn (gen_cmpsi (operands[2], operands[1]));
4140       emit_jump_insn (gen_bgtu (label3));
4141       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4142       emit_jump_insn (gen_blt (label2));
4143       emit_insn (gen_cmpsi (operands[2], const1_rtx));
4144       emit_jump_insn (gen_beq (label1));
4145       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4146       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4147                                          operands[2]));
4148       REG_NOTES (insn) =
4149       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4150
4151       insn = emit_move_insn (operands[0],
4152                              gen_highpart (SImode, operands[3]));
4153       REG_NOTES (insn) =
4154       gen_rtx_EXPR_LIST (REG_EQUAL,
4155                          umod_equal, REG_NOTES (insn));
4156       emit_jump (label3);
4157       emit_label (label1);
4158       emit_move_insn (operands[0], const0_rtx);
4159       emit_jump (label3);
4160       emit_label (label2);
4161       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4162       emit_label (label3);
4163     }
4164   DONE;
4165 }")
4166
4167 ;
4168 ; divdf3 instruction pattern(s).
4169 ;
4170
4171 (define_expand "divdf3"
4172   [(parallel
4173     [(set (match_operand:DF 0 "register_operand" "=f,f")
4174           (div:DF (match_operand:DF 1 "register_operand" "0,0")
4175                   (match_operand:DF 2 "general_operand" "f,m")))
4176      (clobber (reg:CC 33))])]
4177   "TARGET_HARD_FLOAT"
4178   "")
4179
4180 (define_insn "*divdf3"
4181   [(set (match_operand:DF 0 "register_operand" "=f,f")
4182         (div:DF (match_operand:DF 1 "register_operand" "0,0")
4183                 (match_operand:DF 2 "general_operand" "f,m")))
4184    (clobber (reg:CC 33))]
4185   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4186   "@
4187    ddbr\\t%0,%2
4188    ddb\\t%0,%2"
4189   [(set_attr "op_type"  "RRE,RXE")
4190    (set_attr "type"     "fdiv")
4191    (set_attr "atype"    "reg,mem")])
4192
4193 (define_insn "*divdf3_ibm"
4194   [(set (match_operand:DF 0 "register_operand" "=f,f")
4195         (div:DF (match_operand:DF 1 "register_operand" "0,0")
4196                 (match_operand:DF 2 "general_operand" "f,m")))
4197    (clobber (reg:CC 33))]
4198   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4199   "@
4200    ddr\\t%0,%2
4201    dd\\t%0,%2"
4202   [(set_attr "op_type"  "RR,RX")
4203    (set_attr "type"     "fdiv")
4204    (set_attr "atype"    "reg,mem")])
4205
4206 ;
4207 ; divsf3 instruction pattern(s).
4208 ;
4209
4210 (define_expand "divsf3"
4211   [(parallel
4212     [(set (match_operand:SF 0 "register_operand" "=f,f")
4213           (div:SF (match_operand:SF 1 "register_operand" "0,0")
4214                   (match_operand:SF 2 "general_operand" "f,m")))
4215      (clobber (reg:CC 33))])]
4216   "TARGET_HARD_FLOAT"
4217   "")
4218
4219 (define_insn "*divsf3"
4220   [(set (match_operand:SF 0 "register_operand" "=f,f")
4221         (div:SF (match_operand:SF 1 "register_operand" "0,0")
4222                 (match_operand:SF 2 "general_operand" "f,m")))
4223    (clobber (reg:CC 33))]
4224   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4225   "@
4226    debr\\t%0,%2
4227    deb\\t%0,%2"
4228   [(set_attr "op_type"  "RRE,RXE")
4229    (set_attr "type"     "fdiv")
4230    (set_attr "atype"    "reg,mem")])
4231
4232 (define_insn "*divsf3"
4233   [(set (match_operand:SF 0 "register_operand" "=f,f")
4234         (div:SF (match_operand:SF 1 "register_operand" "0,0")
4235                 (match_operand:SF 2 "general_operand" "f,m")))
4236    (clobber (reg:CC 33))]
4237   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4238   "@
4239    der\\t%0,%2
4240    de\\t%0,%2"
4241   [(set_attr "op_type"  "RR,RX")
4242    (set_attr "type"     "fdiv")
4243    (set_attr "atype"    "reg,mem")])
4244
4245
4246 ;;
4247 ;;- And instructions.
4248 ;;
4249
4250 ;
4251 ; anddi3 instruction pattern(s).
4252 ;
4253
4254 (define_insn "*anddi3_cc"
4255   [(set (reg 33)
4256         (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4257                          (match_operand:DI 2 "general_operand" "d,m"))
4258                  (const_int 0)))
4259    (set (match_operand:DI 0 "register_operand" "=d,d")
4260         (and:DI (match_dup 1) (match_dup 2)))]
4261   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4262   "@
4263    ngr\\t%0,%2
4264    ng\\t%0,%2"
4265   [(set_attr "op_type"  "RRE,RXE")
4266    (set_attr "atype"    "reg,mem")])
4267
4268 (define_insn "*anddi3_cconly"
4269   [(set (reg 33)
4270         (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4271                          (match_operand:DI 2 "general_operand" "d,m"))
4272                  (const_int 0)))
4273    (clobber (match_scratch:DI 0 "=d,d"))]
4274   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4275   "@
4276    ngr\\t%0,%2
4277    ng\\t%0,%2"
4278   [(set_attr "op_type"  "RRE,RXE")
4279    (set_attr "atype"    "reg,mem")])
4280
4281 (define_insn "*anddi3_ni"
4282   [(set (match_operand:DI 0 "register_operand" "=d")
4283         (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4284                 (match_operand:DI 2 "immediate_operand" "n")))
4285    (clobber (reg:CC 33))]
4286   "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4287   "*
4288 {
4289   int part = s390_single_hi (operands[2], DImode, -1);
4290   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4291
4292   switch (part)
4293     {
4294       case 0: return \"nihh\\t%0,%x2\";
4295       case 1: return \"nihl\\t%0,%x2\";
4296       case 2: return \"nilh\\t%0,%x2\";
4297       case 3: return \"nill\\t%0,%x2\";
4298       default: abort ();
4299     }
4300 }"
4301   [(set_attr "op_type"  "RI")
4302    (set_attr "atype"    "reg")])
4303
4304 (define_insn "anddi3"
4305   [(set (match_operand:DI 0 "register_operand" "=d,d")
4306         (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4307                 (match_operand:DI 2 "general_operand" "d,m")))
4308    (clobber (reg:CC 33))]
4309   "TARGET_64BIT"
4310   "@
4311    ngr\\t%0,%2
4312    ng\\t%0,%2"
4313   [(set_attr "op_type"  "RRE,RXE")
4314    (set_attr "atype"    "reg,mem")])
4315
4316 (define_insn "*anddi3_ss"
4317   [(set (match_operand:DI 0 "s_operand" "=Q")
4318         (and:DI (match_dup 0)
4319                 (match_operand:DI 1 "s_imm_operand" "Q")))
4320    (clobber (reg:CC 33))]
4321   ""
4322   "nc\\t%O0(8,%R0),%1"
4323   [(set_attr "op_type"  "SS")
4324    (set_attr "atype"    "mem")])
4325
4326 (define_insn "*anddi3_ss_inv"
4327   [(set (match_operand:DI 0 "s_operand" "=Q")
4328         (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4329                 (match_dup 0)))
4330    (clobber (reg:CC 33))]
4331   ""
4332   "nc\\t%O0(8,%R0),%1"
4333   [(set_attr "op_type"  "SS")
4334    (set_attr "atype"    "mem")])
4335
4336 ;
4337 ; andsi3 instruction pattern(s).
4338 ;
4339
4340 (define_insn "*andsi3_cc"
4341   [(set (reg 33)
4342         (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4343                          (match_operand:SI 2 "general_operand" "d,m"))
4344                  (const_int 0)))
4345    (set (match_operand:SI 0 "register_operand" "=d,d")
4346         (and:SI (match_dup 1) (match_dup 2)))]
4347   "s390_match_ccmode(insn, CCTmode)"
4348   "@
4349    nr\\t%0,%2
4350    n\\t%0,%2"
4351   [(set_attr "op_type"  "RR,RX")
4352    (set_attr "atype"    "reg,mem")])
4353
4354 (define_insn "*andsi3_cconly"
4355   [(set (reg 33)
4356         (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4357                          (match_operand:SI 2 "general_operand" "d,m"))
4358                  (const_int 0)))
4359    (clobber (match_scratch:SI 0 "=d,d"))]
4360   "s390_match_ccmode(insn, CCTmode)"
4361   "@
4362    nr\\t%0,%2
4363    n\\t%0,%2"
4364   [(set_attr "op_type"  "RR,RX")
4365    (set_attr "atype"    "reg,mem")])
4366
4367 (define_insn "*andsi3_ni"
4368   [(set (match_operand:SI 0 "register_operand" "=d")
4369         (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4370                 (match_operand:SI 2 "immediate_operand" "n")))
4371    (clobber (reg:CC 33))]
4372   "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4373   "*
4374 {
4375   int part = s390_single_hi (operands[2], SImode, -1);
4376   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4377
4378   switch (part)
4379     {
4380       case 0: return \"nilh\\t%0,%x2\";
4381       case 1: return \"nill\\t%0,%x2\";
4382       default: abort ();
4383     }
4384 }"
4385   [(set_attr "op_type"  "RI")
4386    (set_attr "atype"    "reg")])
4387
4388 (define_insn "andsi3"
4389   [(set (match_operand:SI 0 "register_operand" "=d,d")
4390         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4391                 (match_operand:SI 2 "general_operand" "d,m")))
4392    (clobber (reg:CC 33))]
4393   ""
4394   "@
4395    nr\\t%0,%2
4396    n\\t%0,%2"
4397   [(set_attr "op_type"  "RR,RX")
4398    (set_attr "atype"    "reg,mem")])
4399
4400 (define_insn "*andsi3_ss"
4401   [(set (match_operand:SI 0 "s_operand" "=Q")
4402         (and:SI (match_dup 0)
4403                 (match_operand:SI 1 "s_imm_operand" "Q")))
4404    (clobber (reg:CC 33))]
4405   ""
4406   "nc\\t%O0(4,%R0),%1"
4407   [(set_attr "op_type"  "SS")
4408    (set_attr "atype"    "mem")])
4409
4410 (define_insn "*andsi3_ss_inv"
4411   [(set (match_operand:SI 0 "s_operand" "=Q")
4412         (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4413                 (match_dup 0)))
4414    (clobber (reg:CC 33))]
4415   ""
4416   "nc\\t%O0(4,%R0),%1"
4417   [(set_attr "op_type"  "SS")
4418    (set_attr "atype"    "mem")])
4419
4420 ;
4421 ; andhi3 instruction pattern(s).
4422 ;
4423
4424 (define_insn "*andhi3_ni"
4425   [(set (match_operand:HI 0 "register_operand" "=d,d")
4426         (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4427                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4428    (clobber (reg:CC 33))]
4429   "TARGET_64BIT"
4430   "@
4431    nr\\t%0,%2
4432    nill\\t%0,%x2"
4433   [(set_attr "op_type"  "RR,RI")
4434    (set_attr "atype"    "reg")])
4435
4436 (define_insn "andhi3"
4437   [(set (match_operand:HI 0 "register_operand" "=d")
4438         (and:HI (match_operand:HI 1 "register_operand" "%0")
4439                 (match_operand:HI 2 "nonmemory_operand" "d")))
4440    (clobber (reg:CC 33))]
4441   ""
4442   "nr\\t%0,%2"
4443   [(set_attr "op_type"  "RR")
4444    (set_attr "atype"    "reg")])
4445
4446 (define_insn "*andhi3_ss"
4447   [(set (match_operand:HI 0 "s_operand" "=Q")
4448         (and:HI (match_dup 0)
4449                 (match_operand:HI 1 "s_imm_operand" "Q")))
4450    (clobber (reg:CC 33))]
4451   ""
4452   "nc\\t%O0(2,%R0),%1"
4453   [(set_attr "op_type"  "SS")
4454    (set_attr "atype"    "mem")])
4455
4456 (define_insn "*andhi3_ss_inv"
4457   [(set (match_operand:HI 0 "s_operand" "=Q")
4458         (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4459                 (match_dup 0)))
4460    (clobber (reg:CC 33))]
4461   ""
4462   "nc\\t%O0(2,%R0),%1"
4463   [(set_attr "op_type"  "SS")
4464    (set_attr "atype"    "mem")])
4465
4466 ;
4467 ; andqi3 instruction pattern(s).
4468 ;
4469
4470 (define_insn "*andqi3_ni"
4471   [(set (match_operand:QI 0 "register_operand" "=d,d")
4472         (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4473                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4474    (clobber (reg:CC 33))]
4475   "TARGET_64BIT"
4476   "@
4477    nr\\t%0,%2
4478    nill\\t%0,%b2"
4479   [(set_attr "op_type"  "RR,RI")
4480    (set_attr "atype"    "reg")])
4481
4482 (define_insn "andqi3"
4483   [(set (match_operand:QI 0 "register_operand" "=d")
4484         (and:QI (match_operand:QI 1 "register_operand" "%0")
4485                 (match_operand:QI 2 "nonmemory_operand" "d")))
4486    (clobber (reg:CC 33))]
4487   ""
4488   "nr\\t%0,%2"
4489   [(set_attr "op_type"  "RR")
4490    (set_attr "atype"    "reg")])
4491
4492 (define_insn "*andqi3_ss"
4493   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4494         (and:QI (match_dup 0)
4495                 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4496    (clobber (reg:CC 33))]
4497   ""
4498   "@
4499    ni\\t%0,%b1
4500    nc\\t%O0(1,%R0),%1"
4501   [(set_attr "op_type"  "SI,SS")
4502    (set_attr "atype"    "mem")])
4503
4504 (define_insn "*andqi3_ss_inv"
4505   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4506         (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4507                 (match_dup 0)))
4508    (clobber (reg:CC 33))]
4509   ""
4510   "@
4511    ni\\t%0,%b1
4512    nc\\t%O0(1,%R0),%1"
4513   [(set_attr "op_type"  "SI,SS")
4514    (set_attr "atype"    "mem")])
4515
4516
4517 ;;
4518 ;;- Bit set (inclusive or) instructions.
4519 ;;
4520
4521 ;
4522 ; iordi3 instruction pattern(s).
4523 ;
4524
4525 (define_insn "*iordi3_cc"
4526   [(set (reg 33)
4527         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4528                          (match_operand:DI 2 "general_operand" "d,m"))
4529                  (const_int 0)))
4530    (set (match_operand:DI 0 "register_operand" "=d,d")
4531         (ior:DI (match_dup 1) (match_dup 2)))]
4532   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4533   "@
4534    ogr\\t%0,%2
4535    og\\t%0,%2"
4536   [(set_attr "op_type"  "RRE,RXE")
4537    (set_attr "atype"    "reg,mem")])
4538
4539 (define_insn "*iordi3_cconly"
4540   [(set (reg 33)
4541         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4542                          (match_operand:DI 2 "general_operand" "d,m"))
4543                  (const_int 0)))
4544    (clobber (match_scratch:DI 0 "=d,d"))]
4545   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4546   "@
4547    ogr\\t%0,%2
4548    og\\t%0,%2"
4549   [(set_attr "op_type"  "RRE,RXE")
4550    (set_attr "atype"    "reg,mem")])
4551
4552 (define_insn "*iordi3_oi"
4553   [(set (match_operand:DI 0 "register_operand" "=d")
4554         (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4555                 (match_operand:DI 2 "immediate_operand" "n")))
4556    (clobber (reg:CC 33))]
4557   "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4558   "*
4559 {
4560   int part = s390_single_hi (operands[2], DImode, 0);
4561   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4562
4563   switch (part)
4564     {
4565       case 0: return \"oihh\\t%0,%x2\";
4566       case 1: return \"oihl\\t%0,%x2\";
4567       case 2: return \"oilh\\t%0,%x2\";
4568       case 3: return \"oill\\t%0,%x2\";
4569       default: abort ();
4570     }
4571 }"
4572   [(set_attr "op_type"  "RI")
4573    (set_attr "atype"    "reg")])
4574
4575 (define_insn "iordi3"
4576   [(set (match_operand:DI 0 "register_operand" "=d,d")
4577         (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4578                 (match_operand:DI 2 "general_operand" "d,m")))
4579    (clobber (reg:CC 33))]
4580   "TARGET_64BIT"
4581   "@
4582    ogr\\t%0,%2
4583    og\\t%0,%2"
4584   [(set_attr "op_type"  "RRE,RXE")
4585    (set_attr "atype"    "reg,mem")])
4586
4587 (define_insn "*iordi3_ss"
4588   [(set (match_operand:DI 0 "s_operand" "=Q")
4589         (ior:DI (match_dup 0)
4590                 (match_operand:DI 1 "s_imm_operand" "Q")))
4591    (clobber (reg:CC 33))]
4592   ""
4593   "oc\\t%O0(8,%R0),%1"
4594   [(set_attr "op_type"  "SS")
4595    (set_attr "atype"    "mem")])
4596
4597 (define_insn "*iordi3_ss_inv"
4598   [(set (match_operand:DI 0 "s_operand" "=Q")
4599         (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4600                 (match_dup 0)))
4601    (clobber (reg:CC 33))]
4602   ""
4603   "oc\\t%O0(8,%R0),%1"
4604   [(set_attr "op_type"  "SS")
4605    (set_attr "atype"    "mem")])
4606
4607 ;
4608 ; iorsi3 instruction pattern(s).
4609 ;
4610
4611 (define_insn "*iorsi3_cc"
4612   [(set (reg 33)
4613         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4614                          (match_operand:SI 2 "general_operand" "d,m"))
4615                  (const_int 0)))
4616    (set (match_operand:SI 0 "register_operand" "=d,d")
4617         (ior:SI (match_dup 1) (match_dup 2)))]
4618   "s390_match_ccmode(insn, CCTmode)"
4619   "@
4620    or\\t%0,%2
4621    o\\t%0,%2"
4622   [(set_attr "op_type"  "RR,RX")
4623    (set_attr "atype"    "reg,mem")])
4624
4625 (define_insn "*iorsi3_cconly"
4626   [(set (reg 33)
4627         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4628                          (match_operand:SI 2 "general_operand" "d,m"))
4629                  (const_int 0)))
4630    (clobber (match_scratch:SI 0 "=d,d"))]
4631   "s390_match_ccmode(insn, CCTmode)"
4632   "@
4633    or\\t%0,%2
4634    o\\t%0,%2"
4635   [(set_attr "op_type"  "RR,RX")
4636    (set_attr "atype"    "reg,mem")])
4637
4638 (define_insn "*iorsi3_oi"
4639   [(set (match_operand:SI 0 "register_operand" "=d")
4640         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4641                 (match_operand:SI 2 "immediate_operand" "n")))
4642    (clobber (reg:CC 33))]
4643   "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4644   "*
4645 {
4646   int part = s390_single_hi (operands[2], SImode, 0);
4647   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4648
4649   switch (part)
4650     {
4651       case 0: return \"oilh\\t%0,%x2\";
4652       case 1: return \"oill\\t%0,%x2\";
4653       default: abort ();
4654     }
4655 }"
4656   [(set_attr "op_type"  "RI")
4657    (set_attr "atype"    "reg")])
4658
4659 (define_insn "iorsi3"
4660   [(set (match_operand:SI 0 "register_operand" "=d,d")
4661         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4662                 (match_operand:SI 2 "general_operand" "d,m")))
4663    (clobber (reg:CC 33))]
4664   ""
4665   "@
4666    or\\t%0,%2
4667    o\\t%0,%2"
4668   [(set_attr "op_type"  "RR,RX")
4669    (set_attr "atype"    "reg,mem")])
4670
4671 (define_insn "*iorsi3_ss"
4672   [(set (match_operand:SI 0 "s_operand" "=Q")
4673         (ior:SI (match_dup 0)
4674                 (match_operand:SI 1 "s_imm_operand" "Q")))
4675    (clobber (reg:CC 33))]
4676   ""
4677   "oc\\t%O0(4,%R0),%1"
4678   [(set_attr "op_type"  "SS")
4679    (set_attr "atype"    "mem")])
4680
4681 (define_insn "*iorsi3_ss_inv"
4682   [(set (match_operand:SI 0 "s_operand" "=Q")
4683         (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4684                 (match_dup 0)))
4685    (clobber (reg:CC 33))]
4686   ""
4687   "oc\\t%O0(4,%R0),%1"
4688   [(set_attr "op_type"  "SS")
4689    (set_attr "atype"    "mem")])
4690
4691 ;
4692 ; iorhi3 instruction pattern(s).
4693 ;
4694
4695 (define_insn "*iorhi3_oi"
4696   [(set (match_operand:HI 0 "register_operand" "=d,d")
4697         (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4698                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4699    (clobber (reg:CC 33))]
4700   "TARGET_64BIT"
4701   "@
4702    or\\t%0,%2
4703    oill\\t%0,%x2"
4704   [(set_attr "op_type"  "RR,RI")
4705    (set_attr "atype"    "reg")])
4706
4707 (define_insn "iorhi3"
4708   [(set (match_operand:HI 0 "register_operand" "=d")
4709         (ior:HI (match_operand:HI 1 "register_operand" "%0")
4710                 (match_operand:HI 2 "nonmemory_operand" "d")))
4711    (clobber (reg:CC 33))]
4712   ""
4713   "or\\t%0,%2"
4714   [(set_attr "op_type"  "RR")
4715    (set_attr "atype"    "reg")])
4716
4717 (define_insn "*iorhi3_ss"
4718   [(set (match_operand:HI 0 "s_operand" "=Q")
4719         (ior:HI (match_dup 0)
4720                 (match_operand:HI 1 "s_imm_operand" "Q")))
4721    (clobber (reg:CC 33))]
4722   ""
4723   "oc\\t%O0(2,%R0),%1"
4724   [(set_attr "op_type"  "SS")
4725    (set_attr "atype"    "mem")])
4726
4727 (define_insn "*iorhi3_ss_inv"
4728   [(set (match_operand:HI 0 "s_operand" "=Q")
4729         (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4730                 (match_dup 0)))
4731    (clobber (reg:CC 33))]
4732   ""
4733   "oc\\t%O0(2,%R0),%1"
4734   [(set_attr "op_type"  "SS")
4735    (set_attr "atype"    "mem")])
4736
4737 ;
4738 ; iorqi3 instruction pattern(s).
4739 ;
4740
4741 (define_insn "*iorqi3_oi"
4742   [(set (match_operand:QI 0 "register_operand" "=d,d")
4743         (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4744                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4745    (clobber (reg:CC 33))]
4746   "TARGET_64BIT"
4747   "@
4748    or\\t%0,%2
4749    oill\\t%0,%b2"
4750   [(set_attr "op_type"  "RR,RI")
4751    (set_attr "atype"    "reg")])
4752
4753 (define_insn "iorqi3"
4754   [(set (match_operand:QI 0 "register_operand" "=d")
4755         (ior:QI (match_operand:QI 1 "register_operand" "%0")
4756                 (match_operand:QI 2 "nonmemory_operand" "d")))
4757    (clobber (reg:CC 33))]
4758   ""
4759   "or\\t%0,%2"
4760   [(set_attr "op_type"  "RR")
4761    (set_attr "atype"    "reg")])
4762
4763 (define_insn "*iorqi3_ss"
4764   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4765         (ior:QI (match_dup 0)
4766                 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4767    (clobber (reg:CC 33))]
4768   ""
4769   "@
4770    oi\\t%0,%b1
4771    oc\\t%O0(1,%R0),%1"
4772   [(set_attr "op_type"  "SI,SS")
4773    (set_attr "atype"    "reg,mem")])
4774
4775 (define_insn "*iorqi3_ss_inv"
4776   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4777         (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4778                 (match_dup 0)))
4779    (clobber (reg:CC 33))]
4780   ""
4781   "@
4782    oi\\t%0,%b1
4783    oc\\t%O0(1,%R0),%1"
4784   [(set_attr "op_type"  "SI,SS")
4785    (set_attr "atype"    "reg,mem")])
4786
4787
4788 ;;
4789 ;;- Xor instructions.
4790 ;;
4791
4792 ;
4793 ; xordi3 instruction pattern(s).
4794 ;
4795
4796 (define_insn "*xordi3_cc"
4797   [(set (reg 33)
4798         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4799                          (match_operand:DI 2 "general_operand" "d,m"))
4800                  (const_int 0)))
4801    (set (match_operand:DI 0 "register_operand" "=d,d")
4802         (xor:DI (match_dup 1) (match_dup 2)))]
4803   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4804   "@
4805    xgr\\t%0,%2
4806    xg\\t%0,%2"
4807   [(set_attr "op_type"  "RRE,RXE")
4808    (set_attr "atype"    "reg,mem")])
4809
4810 (define_insn "*xordi3_cconly"
4811   [(set (reg 33)
4812         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4813                          (match_operand:DI 2 "general_operand" "d,m"))
4814                  (const_int 0)))
4815    (clobber (match_scratch:DI 0 "=d,d"))]
4816   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4817   "@
4818    xgr\\t%0,%2
4819    xr\\t%0,%2"
4820   [(set_attr "op_type"  "RRE,RXE")
4821    (set_attr "atype"    "reg,mem")])
4822
4823 (define_insn "xordi3"
4824   [(set (match_operand:DI 0 "register_operand" "=d,d")
4825         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4826                 (match_operand:DI 2 "general_operand" "d,m")))
4827    (clobber (reg:CC 33))]
4828   "TARGET_64BIT"
4829   "@
4830    xgr\\t%0,%2
4831    xg\\t%0,%2"
4832   [(set_attr "op_type"  "RRE,RXE")
4833    (set_attr "atype"    "reg,mem")])
4834
4835 (define_insn "*xordi3_ss"
4836   [(set (match_operand:DI 0 "s_operand" "=Q")
4837         (xor:DI (match_dup 0)
4838                 (match_operand:DI 1 "s_imm_operand" "Q")))
4839    (clobber (reg:CC 33))]
4840   ""
4841   "xc\\t%O0(8,%R0),%1"
4842   [(set_attr "op_type"  "SS")
4843    (set_attr "atype"    "mem")])
4844
4845 (define_insn "*xordi3_ss_inv"
4846   [(set (match_operand:DI 0 "s_operand" "=Q")
4847         (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4848                 (match_dup 0)))
4849    (clobber (reg:CC 33))]
4850   ""
4851   "xc\\t%O0(8,%R0),%1"
4852   [(set_attr "op_type"  "SS")
4853    (set_attr "atype"    "mem")])
4854
4855 ;
4856 ; xorsi3 instruction pattern(s).
4857 ;
4858
4859 (define_insn "*xorsi3_cc"
4860   [(set (reg 33)
4861         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4862                          (match_operand:SI 2 "general_operand" "d,m"))
4863                  (const_int 0)))
4864    (set (match_operand:SI 0 "register_operand" "=d,d")
4865         (xor:SI (match_dup 1) (match_dup 2)))]
4866   "s390_match_ccmode(insn, CCTmode)"
4867   "@
4868    xr\\t%0,%2
4869    x\\t%0,%2"
4870   [(set_attr "op_type"  "RR,RX")
4871    (set_attr "atype"    "reg,mem")])
4872
4873 (define_insn "*xorsi3_cconly"
4874   [(set (reg 33)
4875         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4876                          (match_operand:SI 2 "general_operand" "d,m"))
4877                  (const_int 0)))
4878    (clobber (match_scratch:SI 0 "=d,d"))]
4879   "s390_match_ccmode(insn, CCTmode)"
4880   "@
4881    xr\\t%0,%2
4882    x\\t%0,%2"
4883   [(set_attr "op_type"  "RR,RX")
4884    (set_attr "atype"    "reg,mem")])
4885
4886 (define_insn "xorsi3"
4887   [(set (match_operand:SI 0 "register_operand" "=d,d")
4888         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4889                 (match_operand:SI 2 "general_operand" "d,m")))
4890    (clobber (reg:CC 33))]
4891   ""
4892   "@
4893    xr\\t%0,%2
4894    x\\t%0,%2"
4895   [(set_attr "op_type"  "RR,RX")
4896    (set_attr "atype"    "reg,mem")])
4897
4898 (define_insn "*xorsi3_ss"
4899   [(set (match_operand:SI 0 "s_operand" "=Q")
4900         (xor:SI (match_dup 0)
4901                 (match_operand:SI 1 "s_imm_operand" "Q")))
4902    (clobber (reg:CC 33))]
4903   ""
4904   "xc\\t%O0(4,%R0),%1"
4905   [(set_attr "op_type"  "SS")
4906    (set_attr "atype"    "mem")])
4907
4908 (define_insn "*xorsi3_ss_inv"
4909   [(set (match_operand:SI 0 "s_operand" "=Q")
4910         (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4911                 (match_dup 0)))
4912    (clobber (reg:CC 33))]
4913   ""
4914   "xc\\t%O0(4,%R0),%1"
4915   [(set_attr "op_type"  "SS")
4916    (set_attr "atype"    "mem")])
4917
4918 ;
4919 ; xorhi3 instruction pattern(s).
4920 ;
4921
4922 (define_insn "xorhi3"
4923   [(set (match_operand:HI 0 "register_operand" "=d")
4924         (xor:HI (match_operand:HI 1 "register_operand" "%0")
4925                 (match_operand:HI 2 "nonmemory_operand" "d")))
4926    (clobber (reg:CC 33))]
4927   ""
4928   "xr\\t%0,%2"
4929   [(set_attr "op_type"  "RR")
4930    (set_attr "atype"    "reg")])
4931
4932 (define_insn "*xorhi3_ss"
4933   [(set (match_operand:HI 0 "s_operand" "=Q")
4934         (xor:HI (match_dup 0)
4935                 (match_operand:HI 1 "s_imm_operand" "Q")))
4936    (clobber (reg:CC 33))]
4937   ""
4938   "xc\\t%O0(2,%R0),%1"
4939   [(set_attr "op_type"  "SS")
4940    (set_attr "atype"    "mem")])
4941
4942 (define_insn "*xorhi3_ss_inv"
4943   [(set (match_operand:HI 0 "s_operand" "=Q")
4944         (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4945                 (match_dup 0)))
4946    (clobber (reg:CC 33))]
4947   ""
4948   "xc\\t%O0(2,%R0),%1"
4949   [(set_attr "op_type"  "SS")
4950    (set_attr "atype"    "mem")])
4951
4952 ;
4953 ; xorqi3 instruction pattern(s).
4954 ;
4955
4956 (define_insn "xorqi3"
4957   [(set (match_operand:QI 0 "register_operand" "=d")
4958         (xor:QI (match_operand:QI 1 "register_operand" "%0")
4959                 (match_operand:QI 2 "nonmemory_operand" "d")))
4960    (clobber (reg:CC 33))]
4961   ""
4962   "xr\\t%0,%2"
4963   [(set_attr "op_type"  "RR")
4964    (set_attr "atype"    "reg")])
4965
4966 (define_insn "*xorqi3_ss"
4967   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4968         (xor:QI (match_dup 0)
4969                 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4970    (clobber (reg:CC 33))]
4971   ""
4972   "@
4973    xi\\t%0,%b1
4974    xc\\t%O0(1,%R0),%1"
4975   [(set_attr "op_type"  "SI,SS")
4976    (set_attr "atype"    "mem")])
4977
4978 (define_insn "*xorqi3_ss_inv"
4979   [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4980         (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4981                 (match_dup 0)))
4982    (clobber (reg:CC 33))]
4983   ""
4984   "@
4985    xi\\t%0,%b1
4986    xc\\t%O0(1,%R0),%1"
4987   [(set_attr "op_type"  "SI,SS")
4988    (set_attr "atype"    "mem")])
4989
4990
4991 ;;
4992 ;;- Negate instructions.
4993 ;;
4994
4995 ;
4996 ; negdi2 instruction pattern(s).
4997 ;
4998
4999 (define_expand "negdi2"
5000   [(parallel
5001     [(set (match_operand:DI 0 "register_operand" "=d")
5002           (neg:DI (match_operand:DI 1 "register_operand" "d")))
5003      (clobber (reg:CC 33))])]
5004   ""
5005   "")
5006
5007 (define_insn "*negdi2_64"
5008   [(set (match_operand:DI 0 "register_operand" "=d")
5009         (neg:DI (match_operand:DI 1 "register_operand" "d")))
5010    (clobber (reg:CC 33))]
5011   "TARGET_64BIT"
5012   "lcgr\\t%0,%1"
5013   [(set_attr "op_type"  "RR")])
5014
5015 (define_insn "*negdi2_31"
5016   [(set (match_operand:DI 0 "register_operand" "=d")
5017         (neg:DI (match_operand:DI 1 "register_operand" "d")))
5018    (clobber (reg:CC 33))]
5019   "!TARGET_64BIT"
5020   "*
5021 {
5022   rtx xop[1];
5023   xop[0] = gen_label_rtx ();
5024   output_asm_insn (\"lcr\\t%0,%1\", operands);
5025   output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5026   output_asm_insn (\"je\\t%l0\", xop);
5027   output_asm_insn (\"bctr\\t%0,0\", operands);
5028   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5029                              CODE_LABEL_NUMBER (xop[0]));
5030   return \"\";
5031 }"
5032   [(set_attr "op_type"  "NN")
5033    (set_attr "type"     "other")
5034    (set_attr "length"   "10")])
5035
5036 ;
5037 ; negsi2 instruction pattern(s).
5038 ;
5039
5040 (define_insn "negsi2"
5041   [(set (match_operand:SI 0 "register_operand" "=d")
5042         (neg:SI (match_operand:SI 1 "register_operand" "d")))
5043    (clobber (reg:CC 33))]
5044   ""
5045   "lcr\\t%0,%1"
5046   [(set_attr "op_type"  "RR")])
5047
5048 ;
5049 ; negdf2 instruction pattern(s).
5050 ;
5051
5052 (define_expand "negdf2"
5053   [(parallel
5054     [(set (match_operand:DF 0 "register_operand" "=f")
5055           (neg:DF (match_operand:DF 1 "register_operand" "f")))
5056      (clobber (reg:CC 33))])]
5057   "TARGET_HARD_FLOAT"
5058   "")
5059
5060 (define_insn "*negdf2"
5061   [(set (match_operand:DF 0 "register_operand" "=f")
5062         (neg:DF (match_operand:DF 1 "register_operand" "f")))
5063    (clobber (reg:CC 33))]
5064   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5065   "lcdbr\\t%0,%1"
5066   [(set_attr "op_type"  "RRE")])
5067
5068 (define_insn "*negdf2_ibm"
5069   [(set (match_operand:DF 0 "register_operand" "=f")
5070         (neg:DF (match_operand:DF 1 "register_operand" "f")))
5071    (clobber (reg:CC 33))]
5072   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5073   "lcdr\\t%0,%1"
5074   [(set_attr "op_type"  "RR")])
5075
5076 ;
5077 ; negsf2 instruction pattern(s).
5078 ;
5079
5080 (define_expand "negsf2"
5081   [(parallel
5082     [(set (match_operand:SF 0 "register_operand" "=f")
5083           (neg:SF (match_operand:SF 1 "register_operand" "f")))
5084      (clobber (reg:CC 33))])]
5085   "TARGET_HARD_FLOAT"
5086   "")
5087
5088 (define_insn "*negsf2"
5089   [(set (match_operand:SF 0 "register_operand" "=f")
5090         (neg:SF (match_operand:SF 1 "register_operand" "f")))
5091    (clobber (reg:CC 33))]
5092   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5093   "lcebr\\t%0,%1"
5094   [(set_attr "op_type"  "RRE")])
5095
5096 (define_insn "*negsf2"
5097   [(set (match_operand:SF 0 "register_operand" "=f")
5098         (neg:SF (match_operand:SF 1 "register_operand" "f")))
5099    (clobber (reg:CC 33))]
5100   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5101   "lcer\\t%0,%1"
5102   [(set_attr "op_type"  "RR")])
5103
5104
5105 ;;
5106 ;;- Absolute value instructions.
5107 ;;
5108
5109 ;
5110 ; absdi2 instruction pattern(s).
5111 ;
5112
5113 (define_insn "absdi2"
5114   [(set (match_operand:DI 0 "register_operand" "=d")
5115         (abs:DI (match_operand:DI 1 "register_operand" "d")))
5116    (clobber (reg:CC 33))]
5117   "TARGET_64BIT"
5118   "lpgr\\t%0,%1"
5119   [(set_attr "op_type"  "RRE")])
5120
5121 ;
5122 ; abssi2 instruction pattern(s).
5123 ;
5124
5125 (define_insn "abssi2"
5126   [(set (match_operand:SI 0 "register_operand" "=d")
5127         (abs:SI (match_operand:SI 1 "register_operand" "d")))
5128    (clobber (reg:CC 33))]
5129   ""
5130   "lpr\\t%0,%1"
5131   [(set_attr "op_type"  "RR")])
5132
5133 ;
5134 ; absdf2 instruction pattern(s).
5135 ;
5136
5137 (define_expand "absdf2"
5138   [(parallel
5139     [(set (match_operand:DF 0 "register_operand" "=f")
5140           (abs:DF (match_operand:DF 1 "register_operand" "f")))
5141      (clobber (reg:CC 33))])]
5142   "TARGET_HARD_FLOAT"
5143   "")
5144
5145 (define_insn "*absdf2"
5146   [(set (match_operand:DF 0 "register_operand" "=f")
5147         (abs:DF (match_operand:DF 1 "register_operand" "f")))
5148    (clobber (reg:CC 33))]
5149   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5150   "lpdbr\\t%0,%1"
5151   [(set_attr "op_type"  "RRE")])
5152
5153 (define_insn "*absdf2_ibm"
5154   [(set (match_operand:DF 0 "register_operand" "=f")
5155         (abs:DF (match_operand:DF 1 "register_operand" "f")))
5156    (clobber (reg:CC 33))]
5157   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5158   "lpdr\\t%0,%1"
5159   [(set_attr "op_type"  "RR")])
5160
5161 ;
5162 ; abssf2 instruction pattern(s).
5163 ;
5164
5165 (define_expand "abssf2"
5166   [(parallel
5167     [(set (match_operand:SF 0 "register_operand" "=f")
5168           (abs:SF (match_operand:SF 1 "register_operand" "f")))
5169      (clobber (reg:CC 33))])]
5170   "TARGET_HARD_FLOAT"
5171   "")
5172
5173 (define_insn "*abssf2"
5174   [(set (match_operand:SF 0 "register_operand" "=f")
5175         (abs:SF (match_operand:SF 1 "register_operand" "f")))
5176    (clobber (reg:CC 33))]
5177   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5178   "lpebr\\t%0,%1"
5179   [(set_attr "op_type"  "RRE")])
5180
5181 (define_insn "*abssf2_ibm"
5182   [(set (match_operand:SF 0 "register_operand" "=f")
5183         (abs:SF (match_operand:SF 1 "register_operand" "f")))
5184    (clobber (reg:CC 33))]
5185   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5186   "lper\\t%0,%1"
5187   [(set_attr "op_type"  "RR")])
5188
5189 ;;
5190 ;;- Square root instructions.
5191 ;;
5192
5193 ;
5194 ; sqrtdf2 instruction pattern(s).
5195 ;
5196
5197 (define_insn "sqrtdf2"
5198   [(set (match_operand:DF 0 "register_operand" "=f,f")
5199         (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5200   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5201   "@
5202    sqdbr\\t%0,%1
5203    sqdb\\t%0,%1"
5204   [(set_attr "op_type"  "RRE,RSE")])
5205
5206 ;
5207 ; sqrtsf2 instruction pattern(s).
5208 ;
5209
5210 (define_insn "sqrtsf2"
5211   [(set (match_operand:SF 0 "register_operand" "=f,f")
5212         (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5213   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5214   "@
5215    sqebr\\t%0,%1
5216    sqeb\\t%0,%1"
5217   [(set_attr "op_type"  "RRE,RSE")])
5218
5219 ;;
5220 ;;- One complement instructions.
5221 ;;
5222
5223 ;
5224 ; one_cmpldi2 instruction pattern(s).
5225 ;
5226
5227 (define_expand "one_cmpldi2"
5228   [(parallel
5229     [(set (match_operand:DI 0 "register_operand" "")
5230           (xor:DI (match_operand:DI 1 "register_operand" "")
5231                   (const_int -1)))
5232      (clobber (reg:CC 33))])]
5233   "TARGET_64BIT"
5234   "")
5235
5236 ;
5237 ; one_cmplsi2 instruction pattern(s).
5238 ;
5239
5240 (define_expand "one_cmplsi2"
5241   [(parallel
5242     [(set (match_operand:SI 0 "register_operand" "")
5243           (xor:SI (match_operand:SI 1 "register_operand" "")
5244                   (const_int -1)))
5245      (clobber (reg:CC 33))])]
5246   ""
5247   "")
5248
5249 ;
5250 ; one_cmplhi2 instruction pattern(s).
5251 ;
5252
5253 (define_expand "one_cmplhi2"
5254   [(parallel
5255     [(set (match_operand:HI 0 "register_operand" "")
5256           (xor:HI (match_operand:HI 1 "register_operand" "")
5257                   (const_int -1)))
5258      (clobber (reg:CC 33))])]
5259   ""
5260   "")
5261
5262 ;
5263 ; one_cmplqi2 instruction pattern(s).
5264 ;
5265
5266 (define_expand "one_cmplqi2"
5267   [(parallel
5268     [(set (match_operand:QI 0 "register_operand" "")
5269           (xor:QI (match_operand:QI 1 "register_operand" "")
5270                   (const_int -1)))
5271      (clobber (reg:CC 33))])]
5272   ""
5273   "")
5274
5275
5276 ;;
5277 ;;- Rotate instructions.
5278 ;;
5279
5280 ;
5281 ; rotldi3 instruction pattern(s).
5282 ;
5283
5284 (define_insn "rotldi3"
5285   [(set (match_operand:DI 0 "register_operand" "=d,d")
5286         (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5287                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5288   "TARGET_64BIT"
5289   "@
5290    rllg\\t%0,%1,%c2
5291    rllg\\t%0,%1,0(%2)"
5292   [(set_attr "op_type"  "RSE")])
5293
5294 ;
5295 ; rotlsi3 instruction pattern(s).
5296 ;
5297
5298 (define_insn "rotlsi3"
5299   [(set (match_operand:SI 0 "register_operand" "=d,d")
5300         (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5301                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5302   "TARGET_64BIT"
5303   "@
5304    rll\\t%0,%1,%c2
5305    rll\\t%0,%1,0(%2)"
5306   [(set_attr "op_type"  "RSE")])
5307
5308
5309 ;;
5310 ;;- Arithmetic shift instructions.
5311 ;;
5312
5313 ;
5314 ; ashldi3 instruction pattern(s).
5315 ;
5316
5317 (define_expand "ashldi3"
5318   [(set (match_operand:DI 0 "register_operand" "")
5319         (ashift:DI (match_operand:DI 1 "register_operand" "")
5320                    (match_operand:SI 2 "nonmemory_operand" "")))]
5321   ""
5322   "")
5323
5324 (define_insn "*ashldi3_31"
5325   [(set (match_operand:DI 0 "register_operand" "=d,d")
5326         (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5327                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5328   "!TARGET_64BIT"
5329   "@
5330    sldl\\t%0,%c2
5331    sldl\\t%0,0(%2)"
5332   [(set_attr "op_type"  "RS")])
5333
5334 (define_insn "*ashldi3_64"
5335   [(set (match_operand:DI 0 "register_operand" "=d,d")
5336         (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5337                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5338   "TARGET_64BIT"
5339   "@
5340    sllg\\t%0,%1,%2
5341    sllg\\t%0,%1,0(%2)"
5342   [(set_attr "op_type"  "RSE")])
5343
5344 ;
5345 ; ashrdi3 instruction pattern(s).
5346 ;
5347
5348 (define_expand "ashrdi3"
5349   [(parallel
5350     [(set (match_operand:DI 0 "register_operand" "")
5351           (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5352                        (match_operand:SI 2 "nonmemory_operand" "")))
5353      (clobber (reg:CC 33))])]
5354   ""
5355   "")
5356
5357 (define_insn "*ashrdi3_cc_31"
5358   [(set (reg 33)
5359         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5360                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5361                  (const_int 0)))
5362    (set (match_operand:DI 0 "register_operand" "=d,d")
5363         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5364   "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5365   "@
5366    srda\\t%0,%c2
5367    srda\\t%0,0(%2)"
5368   [(set_attr "op_type"  "RS")])
5369
5370 (define_insn "*ashrdi3_cconly_31"
5371   [(set (reg 33)
5372         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5373                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5374                  (const_int 0)))
5375    (clobber (match_scratch:DI 0 "=d,d"))]
5376   "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5377   "@
5378    srda\\t%0,%c2
5379    srda\\t%0,0(%2)"
5380   [(set_attr "op_type"  "RS")])
5381
5382 (define_insn "*ashrdi3_31"
5383   [(set (match_operand:DI 0 "register_operand" "=d,d")
5384         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5385                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5386    (clobber (reg:CC 33))]
5387   "!TARGET_64BIT"
5388   "@
5389    srda\\t%0,%c2
5390    srda\\t%0,0(%2)"
5391   [(set_attr "op_type"  "RS")])
5392
5393 (define_insn "*ashrdi3_cc_64"
5394   [(set (reg 33)
5395         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5396                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5397                  (const_int 0)))
5398    (set (match_operand:DI 0 "register_operand" "=d,d")
5399         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5400   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5401   "@
5402    srag\\t%0,%1,%c2
5403    srag\\t%0,%1,0(%2)"
5404   [(set_attr "op_type"  "RSE")])
5405
5406 (define_insn "*ashrdi3_cconly_64"
5407   [(set (reg 33)
5408         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5409                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5410                  (const_int 0)))
5411    (clobber (match_scratch:DI 0 "=d,d"))]
5412   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5413   "@
5414    srag\\t%0,%1,%c2
5415    srag\\t%0,%1,0(%2)"
5416   [(set_attr "op_type"  "RSE")])
5417
5418 (define_insn "*ashrdi3_64"
5419   [(set (match_operand:DI 0 "register_operand" "=d,d")
5420         (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5421                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5422    (clobber (reg:CC 33))]
5423   "TARGET_64BIT"
5424   "@
5425    srag\\t%0,%1,%c2
5426    srag\\t%0,%1,0(%2)"
5427   [(set_attr "op_type"  "RSE")])
5428
5429 ;
5430 ; ashlsi3 instruction pattern(s).
5431 ;
5432
5433 (define_insn "ashlsi3"
5434   [(set (match_operand:SI 0 "register_operand" "=d,d")
5435         (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5436                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5437   ""
5438   "@
5439    sll\\t%0,%c2
5440    sll\\t%0,0(%2)"
5441   [(set_attr "op_type"  "RS")])
5442
5443 ;
5444 ; ashrsi3 instruction pattern(s).
5445 ;
5446
5447 (define_insn "*ashrsi3_cc"
5448   [(set (reg 33)
5449         (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5450                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5451                  (const_int 0)))
5452    (set (match_operand:SI 0 "register_operand" "=d,d")
5453         (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5454   "s390_match_ccmode(insn, CCSmode)"
5455   "@
5456    sra\\t%0,%c2
5457    sra\\t%0,0(%2)"
5458   [(set_attr "op_type"  "RS")])
5459
5460 (define_insn "*ashrsi3_cconly"
5461   [(set (reg 33)
5462         (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5463                               (match_operand:SI 2 "nonmemory_operand" "J,a"))
5464                  (const_int 0)))
5465    (clobber (match_scratch:SI 0 "=d,d"))]
5466   "s390_match_ccmode(insn, CCSmode)"
5467   "@
5468    sra\\t%0,%c2
5469    sra\\t%0,0(%2)"
5470   [(set_attr "op_type"  "RS")])
5471
5472 (define_insn "ashrsi3"
5473   [(set (match_operand:SI 0 "register_operand" "=d,d")
5474         (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5475                      (match_operand:SI 2 "nonmemory_operand" "J,a")))
5476    (clobber (reg:CC 33))]
5477   ""
5478   "@
5479    sra\\t%0,%c2
5480    sra\\t%0,0(%2)"
5481   [(set_attr "op_type"  "RS")])
5482
5483
5484 ;;
5485 ;;- logical shift instructions.
5486 ;;
5487
5488 ;
5489 ; lshrdi3 instruction pattern(s).
5490 ;
5491
5492 (define_expand "lshrdi3"
5493   [(set (match_operand:DI 0 "register_operand" "")
5494         (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5495                      (match_operand:SI 2 "nonmemory_operand" "")))]
5496   ""
5497   "")
5498
5499 (define_insn "*lshrdi3_31"
5500   [(set (match_operand:DI 0 "register_operand" "=d,d")
5501         (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5502                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5503   "!TARGET_64BIT"
5504   "@
5505    srdl\\t%0,%c2
5506    srdl\\t%0,0(%2)"
5507    [(set_attr "op_type"  "RS,RS")])
5508
5509 (define_insn "*lshrdi3_64"
5510   [(set (match_operand:DI 0 "register_operand" "=d,d")
5511         (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5512                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5513   "TARGET_64BIT"
5514   "@
5515    srlg\\t%0,%1,%c2
5516    srlg\\t%0,%1,0(%2)"
5517   [(set_attr "op_type"  "RS,RS")])
5518
5519 ;
5520 ; lshrsi3 instruction pattern(s).
5521 ;
5522
5523 (define_insn "lshrsi3"
5524   [(set (match_operand:SI 0 "register_operand" "=d,d")
5525         (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5526                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5527   ""
5528   "@
5529    srl\\t%0,%c2
5530    srl\\t%0,0(%2)"
5531   [(set_attr "op_type"  "RS")])
5532
5533
5534 ;;
5535 ;; Branch instruction patterns.
5536 ;;
5537
5538 (define_expand "beq"
5539   [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5540    (set (pc)
5541         (if_then_else (eq (reg:CCZ 33) (const_int 0))
5542                       (label_ref (match_operand 0 "" ""))
5543                       (pc)))]
5544   ""
5545   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5546
5547 (define_expand "bne"
5548   [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5549    (set (pc)
5550         (if_then_else (ne (reg:CCZ 33) (const_int 0))
5551                       (label_ref (match_operand 0 "" ""))
5552                       (pc)))]
5553   ""
5554   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5555
5556 (define_expand "bgt"
5557   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5558    (set (pc)
5559         (if_then_else (gt (reg:CCS 33) (const_int 0))
5560                       (label_ref (match_operand 0 "" ""))
5561                       (pc)))]
5562   ""
5563   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5564
5565 (define_expand "bgtu"
5566   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5567    (set (pc)
5568         (if_then_else (gtu (reg:CCU 33) (const_int 0))
5569                       (label_ref (match_operand 0 "" ""))
5570                       (pc)))]
5571   ""
5572   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5573
5574 (define_expand "blt"
5575   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5576    (set (pc)
5577         (if_then_else (lt (reg:CCS 33) (const_int 0))
5578                       (label_ref (match_operand 0 "" ""))
5579                       (pc)))]
5580   ""
5581   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5582
5583 (define_expand "bltu"
5584   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5585    (set (pc)
5586         (if_then_else (ltu (reg:CCU 33) (const_int 0))
5587                       (label_ref (match_operand 0 "" ""))
5588                       (pc)))]
5589   ""
5590   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5591
5592 (define_expand "bge"
5593   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5594    (set (pc)
5595         (if_then_else (ge (reg:CCS 33) (const_int 0))
5596                       (label_ref (match_operand 0 "" ""))
5597                       (pc)))]
5598   ""
5599   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5600
5601 (define_expand "bgeu"
5602   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5603    (set (pc)
5604         (if_then_else (geu (reg:CCU 33) (const_int 0))
5605                       (label_ref (match_operand 0 "" ""))
5606                       (pc)))]
5607   ""
5608   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5609
5610 (define_expand "ble"
5611   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5612    (set (pc)
5613         (if_then_else (le (reg:CCS 33) (const_int 0))
5614                       (label_ref (match_operand 0 "" ""))
5615                       (pc)))]
5616   ""
5617   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5618
5619 (define_expand "bleu"
5620   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5621    (set (pc)
5622         (if_then_else (leu (reg:CCU 33) (const_int 0))
5623                       (label_ref (match_operand 0 "" ""))
5624                       (pc)))]
5625   ""
5626   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5627
5628 (define_expand "bunordered"
5629   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5630    (set (pc)
5631         (if_then_else (unordered (reg:CCS 33) (const_int 0))
5632                       (label_ref (match_operand 0 "" ""))
5633                       (pc)))]
5634   ""
5635   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5636
5637 (define_expand "bordered"
5638   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5639    (set (pc)
5640         (if_then_else (ordered (reg:CCS 33) (const_int 0))
5641                       (label_ref (match_operand 0 "" ""))
5642                       (pc)))]
5643   ""
5644   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5645
5646 (define_expand "buneq"
5647   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5648    (set (pc)
5649         (if_then_else (uneq (reg:CCS 33) (const_int 0))
5650                       (label_ref (match_operand 0 "" ""))
5651                       (pc)))]
5652   ""
5653   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5654
5655 (define_expand "bungt"
5656   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5657    (set (pc)
5658         (if_then_else (ungt (reg:CCS 33) (const_int 0))
5659                       (label_ref (match_operand 0 "" ""))
5660                       (pc)))]
5661   ""
5662   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5663
5664 (define_expand "bunlt"
5665   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5666    (set (pc)
5667         (if_then_else (unlt (reg:CCS 33) (const_int 0))
5668                       (label_ref (match_operand 0 "" ""))
5669                       (pc)))]
5670   ""
5671   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5672
5673 (define_expand "bunge"
5674   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5675    (set (pc)
5676         (if_then_else (unge (reg:CCS 33) (const_int 0))
5677                       (label_ref (match_operand 0 "" ""))
5678                       (pc)))]
5679   ""
5680   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5681
5682 (define_expand "bunle"
5683   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5684    (set (pc)
5685         (if_then_else (unle (reg:CCS 33) (const_int 0))
5686                       (label_ref (match_operand 0 "" ""))
5687                       (pc)))]
5688   ""
5689   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5690
5691 (define_expand "bltgt"
5692   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5693    (set (pc)
5694         (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5695                       (label_ref (match_operand 0 "" ""))
5696                       (pc)))]
5697   ""
5698   "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5699
5700
5701 ;;
5702 ;;- Conditional jump instructions.
5703 ;;
5704
5705 (define_insn "cjump"
5706  [(set (pc)
5707        (if_then_else
5708          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5709          (label_ref (match_operand 0 "" ""))
5710          (pc)))]
5711   ""
5712   "*
5713 {
5714   if (get_attr_length (insn) == 4)
5715     return \"j%C1\\t%l0\";
5716   else if (TARGET_64BIT)
5717     return \"jg%C1\\t%l0\";
5718   else
5719     abort ();
5720 }"
5721   [(set_attr "op_type" "RI")
5722    (set (attr "length")
5723         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5724                 (const_int 4)
5725                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5726                  (const_int 6)
5727                (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5728                  (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5729                                (const_int 12) (const_int 14))
5730                (eq (symbol_ref "flag_pic") (const_int 0))
5731                  (const_int 6)] (const_int 8)))])
5732
5733 (define_insn "*cjump_long"
5734  [(set (pc)
5735        (if_then_else
5736          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5737          (match_operand 0 "address_operand" "p")
5738          (pc)))]
5739   ""
5740   "*
5741 {
5742   if (get_attr_op_type (insn) == OP_TYPE_RR)
5743     return \"b%C1r\\t%0\";
5744   else
5745     return \"b%C1\\t%a0\";
5746 }"
5747   [(set (attr "op_type")
5748         (if_then_else (match_operand 0 "register_operand" "")
5749                       (const_string "RR") (const_string "RX")))
5750    (set_attr "atype" "mem")])
5751
5752
5753 ;;
5754 ;;- Negated conditional jump instructions.
5755 ;;
5756
5757 (define_insn "icjump"
5758  [(set (pc)
5759        (if_then_else
5760          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5761          (pc)
5762          (label_ref (match_operand 0 "" ""))))]
5763   ""
5764   "*
5765 {
5766   if (get_attr_length (insn) == 4)
5767     return \"j%D1\\t%l0\";
5768   else if (TARGET_64BIT)
5769     return \"jg%D1\\t%l0\";
5770   else
5771     abort ();
5772 }"
5773   [(set_attr "op_type" "RI")
5774    (set (attr "length")
5775         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5776                 (const_int 4)
5777                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5778                  (const_int 6)
5779                (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5780                  (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5781                                (const_int 12) (const_int 14))
5782                (eq (symbol_ref "flag_pic") (const_int 0))
5783                  (const_int 6)] (const_int 8)))])
5784
5785 (define_insn "*icjump_long"
5786  [(set (pc)
5787        (if_then_else
5788          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5789          (pc)
5790          (match_operand 0 "address_operand" "p")))]
5791   ""
5792   "*
5793 {
5794   if (get_attr_op_type (insn) == OP_TYPE_RR)
5795     return \"b%D1r\\t%0\";
5796   else
5797     return \"b%D1\\t%a0\";
5798 }"
5799   [(set (attr "op_type")
5800         (if_then_else (match_operand 0 "register_operand" "")
5801                       (const_string "RR") (const_string "RX")))
5802    (set_attr "atype" "mem")])
5803
5804 ;;
5805 ;;- Trap instructions.
5806 ;;
5807
5808 (define_insn "trap"
5809   [(trap_if (const_int 1) (const_int 0))]
5810   ""
5811   "j\\t.+2"
5812   [(set_attr "op_type" "RX")])
5813
5814 (define_expand "conditional_trap"
5815   [(set (match_dup 2) (match_dup 3))
5816    (trap_if (match_operator 0 "comparison_operator"
5817                             [(match_dup 2) (const_int 0)])
5818             (match_operand:SI 1 "general_operand" ""))]
5819   ""
5820   "
5821 {
5822    enum machine_mode ccmode;
5823
5824    if (operands[1] != const0_rtx) FAIL;
5825
5826    ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5827                                 s390_compare_op0, s390_compare_op1);
5828    operands[2] = gen_rtx_REG (ccmode, 33);
5829    operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5830 }")
5831
5832 (define_insn "*trap"
5833   [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5834             (const_int 0))]
5835   ""
5836   "j%C0\\t.+2";
5837   [(set_attr "op_type" "RX")])
5838
5839 ;;
5840 ;;- Loop instructions.
5841 ;;
5842 ;;  This is all complicated by the fact that since this is a jump insn
5843 ;;  we must handle our own output reloads.
5844
5845 (define_expand "doloop_end"
5846   [(use (match_operand 0 "" ""))        ; loop pseudo
5847    (use (match_operand 1 "" ""))        ; iterations; zero if unknown
5848    (use (match_operand 2 "" ""))        ; max iterations
5849    (use (match_operand 3 "" ""))        ; loop level
5850    (use (match_operand 4 "" ""))]       ; label
5851   ""
5852   "
5853 {
5854   if (GET_MODE (operands[0]) == SImode)
5855     emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5856   else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5857     emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5858   else
5859     FAIL;
5860
5861   DONE;
5862 }")
5863
5864 (define_insn "doloop_si"
5865   [(set (pc)
5866         (if_then_else
5867           (ne (match_operand:SI 1 "register_operand" "d,d")
5868               (const_int 1))
5869           (label_ref (match_operand 0 "" ""))
5870           (pc)))
5871    (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5872         (plus:SI (match_dup 1) (const_int -1)))
5873    (clobber (match_scratch:SI 3 "=X,&d"))
5874    (clobber (reg:CC 33))]
5875   ""
5876   "*
5877 {
5878   if (which_alternative != 0)
5879     return \"#\";
5880   else if (get_attr_length (insn) == 4)
5881     return \"brct\\t%1,%l0\";
5882   else
5883     abort ();
5884 }"
5885   [(set_attr "op_type"  "RI")
5886    (set (attr "length")
5887         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5888                 (const_int 4)
5889                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5890                  (const_int 10)
5891                (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5892                  (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5893                                (const_int 12) (const_int 14))
5894                (eq (symbol_ref "flag_pic") (const_int 0))
5895                  (const_int 6)] (const_int 8)))])
5896
5897 (define_insn "*doloop_si_long"
5898   [(set (pc)
5899         (if_then_else
5900           (ne (match_operand:SI 1 "register_operand" "d,d")
5901               (const_int 1))
5902           (match_operand 0 "address_operand" "p,p")
5903           (pc)))
5904    (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5905         (plus:SI (match_dup 1) (const_int -1)))
5906    (clobber (match_scratch:SI 3 "=X,&d"))
5907    (clobber (reg:CC 33))]
5908   ""
5909   "*
5910 {
5911   if (get_attr_op_type (insn) == OP_TYPE_RR)
5912     return \"bctr\\t%1,%0\";
5913   else
5914     return \"bct\\t%1,%a0\";
5915 }"
5916   [(set (attr "op_type")
5917         (if_then_else (match_operand 0 "register_operand" "")
5918                       (const_string "RR") (const_string "RX")))
5919    (set_attr "atype" "mem")])
5920
5921 (define_split
5922   [(set (pc)
5923         (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5924                           (const_int 1))
5925                       (match_operand 0 "" "")
5926                       (pc)))
5927    (set (match_operand:SI 2 "nonimmediate_operand" "")
5928         (plus:SI (match_dup 1) (const_int -1)))
5929    (clobber (match_scratch:SI 3 ""))
5930    (clobber (reg:CC 33))]
5931   "reload_completed
5932    && (! REG_P (operands[2])
5933        || ! rtx_equal_p (operands[1], operands[2]))"
5934   [(set (match_dup 3) (match_dup 1))
5935    (parallel [(set (reg:CCAN 33)
5936                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5937                                  (const_int 0)))
5938               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5939    (set (match_dup 2) (match_dup 3))
5940    (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5941                            (match_dup 0)
5942                            (pc)))]
5943   "")
5944
5945 (define_insn "doloop_di"
5946   [(set (pc)
5947         (if_then_else
5948           (ne (match_operand:DI 1 "register_operand" "d,d")
5949               (const_int 1))
5950           (label_ref (match_operand 0 "" ""))
5951           (pc)))
5952    (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
5953         (plus:DI (match_dup 1) (const_int -1)))
5954    (clobber (match_scratch:DI 3 "=X,&d"))
5955    (clobber (reg:CC 33))]
5956   "TARGET_64BIT"
5957   "*
5958 {
5959   if (which_alternative != 0)
5960     return \"#\";
5961   else if (get_attr_length (insn) == 4)
5962     return \"brctg\\t%1,%l0\";
5963   else
5964     abort ();
5965 }"
5966   [(set_attr "op_type"  "RI")
5967    (set (attr "length")
5968         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5969                       (const_int 4) (const_int 12)))])
5970
5971 (define_insn "*doloop_di_long"
5972   [(set (pc)
5973         (if_then_else
5974           (ne (match_operand:DI 1 "register_operand" "d,d")
5975               (const_int 1))
5976           (match_operand 0 "address_operand" "p,p")
5977           (pc)))
5978    (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
5979         (plus:DI (match_dup 1) (const_int -1)))
5980    (clobber (match_scratch:DI 3 "=X,&d"))
5981    (clobber (reg:CC 33))]
5982   ""
5983   "*
5984 {
5985   if (get_attr_op_type (insn) == OP_TYPE_RRE)
5986     return \"bctgr\\t%1,%0\";
5987   else
5988     return \"bctg\\t%1,%a0\";
5989 }"
5990   [(set (attr "op_type")
5991         (if_then_else (match_operand 0 "register_operand" "")
5992                       (const_string "RRE") (const_string "RXE")))
5993    (set_attr "atype" "mem")])
5994
5995 (define_split
5996   [(set (pc)
5997         (if_then_else (ne (match_operand:DI 1 "register_operand" "")
5998                           (const_int 1))
5999                       (match_operand 0 "" "")
6000                       (pc)))
6001    (set (match_operand:DI 2 "nonimmediate_operand" "")
6002         (plus:DI (match_dup 1) (const_int -1)))
6003    (clobber (match_scratch:DI 3 ""))
6004    (clobber (reg:CC 33))]
6005   "reload_completed
6006    && (! REG_P (operands[2])
6007        || ! rtx_equal_p (operands[1], operands[2]))"
6008   [(set (match_dup 3) (match_dup 1))
6009    (parallel [(set (reg:CCAN 33)
6010                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6011                                  (const_int 0)))
6012               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6013    (set (match_dup 2) (match_dup 3))
6014    (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6015                            (match_dup 0)
6016                            (pc)))]
6017   "")
6018
6019 ;;
6020 ;;- Unconditional jump instructions.
6021 ;;
6022
6023 ;
6024 ; jump instruction pattern(s).
6025 ;
6026
6027 (define_insn "jump"
6028   [(set (pc) (label_ref (match_operand 0 "" "")))]
6029   ""
6030   "*
6031 {
6032   if (get_attr_length (insn) == 4)
6033     return \"j\\t%l0\";
6034   else if (TARGET_64BIT)
6035     return \"jg\\t%l0\";
6036   else
6037     abort ();
6038 }"
6039   [(set_attr "op_type" "RI")
6040    (set (attr "length")
6041         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6042                 (const_int 4)
6043                (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6044                  (const_int 6)
6045                (eq (symbol_ref "flag_pic") (const_int 0))
6046                  (const_int 6)] (const_int 8)))])
6047
6048 ;
6049 ; indirect-jump instruction pattern(s).
6050 ;
6051
6052 (define_insn "indirect_jump"
6053  [(set (pc) (match_operand 0 "address_operand" "p"))]
6054   ""
6055   "*
6056 {
6057   if (get_attr_op_type (insn) == OP_TYPE_RR)
6058     return \"br\\t%0\";
6059   else
6060     return \"b\\t%a0\";
6061 }"
6062   [(set (attr "op_type")
6063         (if_then_else (match_operand 0 "register_operand" "")
6064                       (const_string "RR") (const_string "RX")))
6065    (set_attr "atype" "mem")])
6066
6067 ;
6068 ; casesi instruction pattern(s).
6069 ;
6070
6071 (define_insn "casesi_jump"
6072  [(set (pc) (match_operand 0 "address_operand" "p"))
6073    (use (label_ref (match_operand 1 "" "")))]
6074   ""
6075   "*
6076 {
6077   if (get_attr_op_type (insn) == OP_TYPE_RR)
6078     return \"br\\t%0\";
6079   else
6080     return \"b\\t%a0\";
6081 }"
6082   [(set (attr "op_type")
6083         (if_then_else (match_operand 0 "register_operand" "")
6084                       (const_string "RR") (const_string "RX")))
6085    (set_attr "atype" "mem")])
6086
6087 (define_expand "casesi"
6088   [(match_operand:SI 0 "general_operand" "")
6089    (match_operand:SI 1 "general_operand" "")
6090    (match_operand:SI 2 "general_operand" "")
6091    (label_ref (match_operand 3 "" ""))
6092    (label_ref (match_operand 4 "" ""))]
6093   ""
6094   "
6095 {
6096    rtx index  = gen_reg_rtx (SImode);
6097    rtx base   = gen_reg_rtx (Pmode);
6098    rtx target = gen_reg_rtx (Pmode);
6099
6100    emit_move_insn (index, operands[0]);
6101    emit_insn (gen_subsi3 (index, index, operands[1]));
6102    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6103                             operands[4]);
6104
6105    if (Pmode != SImode)
6106      index = convert_to_mode (Pmode, index, 1);
6107    if (GET_CODE (index) != REG)
6108      index = copy_to_mode_reg (Pmode, index);
6109
6110    if (TARGET_64BIT)
6111        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6112    else
6113        emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6114
6115    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6116
6117    index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6118    emit_move_insn (target, index);
6119
6120    if (flag_pic)
6121      target = gen_rtx_PLUS (Pmode, base, target);
6122    emit_jump_insn (gen_casesi_jump (target, operands[3]));
6123
6124    DONE;
6125 }")
6126
6127
6128 ;;
6129 ;;- Jump to subroutine.
6130 ;;
6131 ;;
6132
6133 ;
6134 ; untyped call instruction pattern(s).
6135 ;
6136
6137 ;; Call subroutine returning any type.
6138 (define_expand "untyped_call"
6139   [(parallel [(call (match_operand 0 "" "")
6140                     (const_int 0))
6141               (match_operand 1 "" "")
6142               (match_operand 2 "" "")])]
6143   ""
6144   "
6145 {
6146   int i;
6147
6148   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6149
6150   for (i = 0; i < XVECLEN (operands[2], 0); i++)
6151     {
6152       rtx set = XVECEXP (operands[2], 0, i);
6153       emit_move_insn (SET_DEST (set), SET_SRC (set));
6154     }
6155
6156   /* The optimizer does not know that the call sets the function value
6157      registers we stored in the result block.  We avoid problems by
6158      claiming that all hard registers are used and clobbered at this
6159      point.  */
6160   emit_insn (gen_blockage ());
6161
6162   DONE;
6163 }")
6164
6165 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6166 ;; all of memory.  This blocks insns from being moved across this point.
6167
6168 (define_insn "blockage"
6169   [(unspec_volatile [(const_int 0)] 0)]
6170   ""
6171   ""
6172   [(set_attr "type"    "none")])
6173
6174
6175
6176 ;
6177 ; call instruction pattern(s).
6178 ;
6179
6180 (define_expand "call"
6181   [(call (match_operand 0 "" "")
6182          (match_operand 1 "" ""))
6183    (use (match_operand 2 "" ""))]
6184   ""
6185   "
6186 {
6187   int plt_call = 0;
6188   rtx insn;
6189
6190   /* Direct function calls need special treatment.  */
6191   if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6192     {
6193       rtx sym = XEXP (operands[0], 0);
6194
6195       /* When calling a global routine in PIC mode, we must
6196          replace the symbol itself with the PLT stub.  */
6197       if (flag_pic && !SYMBOL_REF_FLAG (sym))
6198         {
6199           sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6200           sym = gen_rtx_CONST (Pmode, sym);
6201
6202           plt_call = 1;
6203         }
6204
6205       /* Unless we can use the bras(l) insn, force the
6206          routine address into a register.  */
6207       if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6208         {
6209           rtx target = gen_reg_rtx (Pmode);
6210           emit_move_insn (target, sym);
6211           sym = target;
6212         }
6213
6214       operands[0] = gen_rtx_MEM (QImode, sym);
6215     }
6216
6217   /* Emit insn.  */
6218   insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6219                                        gen_rtx_REG (Pmode, RETURN_REGNUM)));
6220
6221   /* In 31-bit, we must load the GOT register even if the
6222      compiler doesn't know about it, because the PLT glue
6223      code uses it.  In 64-bit, this is not necessary.  */
6224   if (plt_call && !TARGET_64BIT)
6225     use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6226
6227   DONE;
6228 }")
6229
6230 (define_expand "call_exp"
6231   [(parallel [(call (match_operand 0 "" "")
6232                     (match_operand 1 "" ""))
6233               (clobber (match_operand 2 "" ""))])]
6234   ""
6235   "")
6236
6237 (define_insn "brasl"
6238   [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6239          (match_operand:SI 1 "const_int_operand" "n"))
6240    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6241   "TARGET_64BIT"
6242   "brasl\\t%2,%0"
6243   [(set_attr "op_type" "RIL")
6244    (set_attr "type"    "jsr")])
6245
6246 (define_insn "bras"
6247   [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6248          (match_operand:SI 1 "const_int_operand" "n"))
6249    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6250   "TARGET_SMALL_EXEC"
6251   "bras\\t%2,%0"
6252   [(set_attr "op_type" "RI")
6253    (set_attr "type"    "jsr")])
6254
6255 (define_insn "basr_64"
6256   [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6257          (match_operand:SI 1 "const_int_operand" "n"))
6258    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6259   "TARGET_64BIT"
6260   "basr\\t%2,%0"
6261   [(set_attr "op_type" "RR")
6262    (set_attr "type"    "jsr")
6263    (set_attr "atype"   "mem")])
6264
6265 (define_insn "basr_31"
6266   [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6267          (match_operand:SI 1 "const_int_operand" "n"))
6268    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6269   "!TARGET_64BIT"
6270   "basr\\t%2,%0"
6271   [(set_attr "op_type" "RR")
6272    (set_attr "type"    "jsr")
6273    (set_attr "atype"    "mem")])
6274
6275 (define_insn "bas_64"
6276   [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6277          (match_operand:SI 1 "const_int_operand" "n"))
6278    (clobber (match_operand:DI 2 "register_operand" "=r"))]
6279   "TARGET_64BIT"
6280   "bas\\t%2,%a0"
6281   [(set_attr "op_type" "RX")
6282    (set_attr "type"    "jsr")
6283    (set_attr "atype"   "mem")])
6284
6285 (define_insn "bas_31"
6286   [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6287          (match_operand:SI 1 "const_int_operand" "n"))
6288    (clobber (match_operand:SI 2 "register_operand" "=r"))]
6289   "!TARGET_64BIT"
6290   "bas\\t%2,%a0"
6291   [(set_attr "op_type" "RX")
6292    (set_attr "type"    "jsr")
6293    (set_attr "atype"   "mem")])
6294
6295
6296 ;
6297 ; call_value instruction pattern(s).
6298 ;
6299
6300 (define_expand "call_value"
6301   [(set (match_operand 0 "" "")
6302         (call (match_operand 1 "" "")
6303               (match_operand 2 "" "")))
6304    (use (match_operand 3 "" ""))]
6305   ""
6306   "
6307 {
6308   int plt_call = 0;
6309   rtx insn;
6310
6311   /* Direct function calls need special treatment.  */
6312   if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6313     {
6314       rtx sym = XEXP (operands[1], 0);
6315
6316       /* When calling a global routine in PIC mode, we must
6317          replace the symbol itself with the PLT stub.  */
6318       if (flag_pic && !SYMBOL_REF_FLAG (sym))
6319         {
6320           sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6321           sym = gen_rtx_CONST (Pmode, sym);
6322
6323           plt_call = 1;
6324         }
6325
6326       /* Unless we can use the bras(l) insn, force the
6327          routine address into a register.  */
6328       if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6329         {
6330           rtx target = gen_reg_rtx (Pmode);
6331           emit_move_insn (target, sym);
6332           sym = target;
6333         }
6334
6335       operands[1] = gen_rtx_MEM (QImode, sym);
6336     }
6337
6338   /* Emit insn.  */
6339   insn = emit_call_insn (
6340             gen_call_value_exp (operands[0], operands[1], operands[2],
6341                                 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6342
6343   /* In 31-bit, we must load the GOT register even if the
6344      compiler doesn't know about it, because the PLT glue
6345      code uses it.  In 64-bit, this is not necessary.  */
6346   if (plt_call && !TARGET_64BIT)
6347     use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6348
6349   DONE;
6350 }")
6351
6352 (define_expand "call_value_exp"
6353   [(parallel [(set (match_operand 0 "" "")
6354                    (call (match_operand 1 "" "")
6355                          (match_operand 2 "" "")))
6356               (clobber (match_operand 3 "" ""))])]
6357   ""
6358   "")
6359
6360 (define_insn "brasl_r"
6361   [(set (match_operand 0 "register_operand" "=df")
6362         (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6363               (match_operand:SI 2 "const_int_operand" "n")))
6364    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6365   "TARGET_64BIT"
6366   "brasl\\t%3,%1"
6367   [(set_attr "op_type" "RIL")
6368    (set_attr "type"    "jsr")])
6369
6370 (define_insn "bras_r"
6371   [(set (match_operand 0 "register_operand" "=df")
6372         (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6373               (match_operand:SI 2 "const_int_operand" "n")))
6374    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6375   "TARGET_SMALL_EXEC"
6376   "bras\\t%3,%1"
6377   [(set_attr "op_type" "RI")
6378    (set_attr "type"    "jsr")])
6379
6380 (define_insn "basr_r_64"
6381   [(set (match_operand 0 "register_operand" "=df")
6382         (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6383               (match_operand:SI 2 "const_int_operand" "n")))
6384    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6385   "TARGET_64BIT"
6386   "basr\\t%3,%1"
6387   [(set_attr "op_type" "RR")
6388    (set_attr "type"    "jsr")])
6389
6390 (define_insn "basr_r_31"
6391   [(set (match_operand 0 "register_operand" "=df")
6392         (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6393               (match_operand:SI 2 "const_int_operand" "n")))
6394    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6395   "!TARGET_64BIT"
6396   "basr\\t%3,%1"
6397   [(set_attr "op_type" "RR")
6398    (set_attr "type"    "jsr")
6399    (set_attr "atype"   "mem")])
6400
6401 (define_insn "bas_r_64"
6402   [(set (match_operand 0 "register_operand" "=df")
6403         (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6404               (match_operand:SI 2 "const_int_operand" "n")))
6405    (clobber (match_operand:DI 3 "register_operand" "=r"))]
6406   "TARGET_64BIT"
6407   "bas\\t%3,%a1"
6408   [(set_attr "op_type" "RX")
6409    (set_attr "type"    "jsr")
6410    (set_attr "atype"   "mem")])
6411
6412 (define_insn "bas_r_31"
6413   [(set (match_operand 0 "register_operand" "=df")
6414         (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6415               (match_operand:SI 2 "const_int_operand" "n")))
6416    (clobber (match_operand:SI 3 "register_operand" "=r"))]
6417   "!TARGET_64BIT"
6418   "bas\\t%3,%a1"
6419    [(set_attr "op_type" "RX")
6420     (set_attr "type"    "jsr")
6421     (set_attr "atype"   "mem")])
6422
6423
6424 ;;
6425 ;;- Miscellaneous instructions.
6426 ;;
6427
6428 ;
6429 ; allocate stack instruction pattern(s).
6430 ;
6431
6432 (define_expand "allocate_stack"
6433   [(set (reg 15)
6434         (plus (reg 15) (match_operand 1 "general_operand" "")))
6435    (set (match_operand 0 "general_operand" "")
6436         (reg 15))]
6437  ""
6438  "
6439 {
6440     rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6441     rtx chain = gen_rtx (MEM, Pmode, stack);
6442     rtx temp = gen_reg_rtx (Pmode);
6443
6444     emit_move_insn (temp, chain);
6445
6446     if (TARGET_64BIT)
6447       emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6448     else
6449       emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6450
6451     emit_move_insn (chain, temp);
6452
6453     emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6454     DONE;
6455 }")
6456
6457
6458 ;
6459 ; setjmp/longjmp instruction pattern(s).
6460 ;
6461
6462 (define_expand "builtin_setjmp_setup"
6463   [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6464   ""
6465   "
6466 {
6467   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6468   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6469
6470   emit_move_insn (base, basereg);
6471   DONE;
6472 }")
6473
6474 (define_expand "builtin_setjmp_receiver"
6475   [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6476   "flag_pic"
6477   "
6478 {
6479   rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6480   rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6481   SYMBOL_REF_FLAG (got) = 1;
6482
6483   emit_move_insn (gotreg, got);
6484   emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6485   DONE;
6486 }")
6487
6488 (define_expand "builtin_longjmp"
6489   [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6490   ""
6491   "
6492 {
6493   /* The elements of the buffer are, in order:  */
6494   rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6495   rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6496   rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6497   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6498   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6499   rtx jmp = gen_rtx_REG (Pmode, 14);
6500
6501   emit_move_insn (jmp, lab);
6502   emit_move_insn (basereg, base);
6503   emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6504   emit_move_insn (hard_frame_pointer_rtx, fp);
6505
6506   emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6507   emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6508   emit_insn (gen_rtx_USE (VOIDmode, basereg));
6509   emit_indirect_jump (jmp);
6510   DONE;
6511 }")
6512
6513
6514 ;; These patterns say how to save and restore the stack pointer.  We need not
6515 ;; save the stack pointer at function level since we are careful to
6516 ;; preserve the backchain.  At block level, we have to restore the backchain
6517 ;; when we restore the stack pointer.
6518 ;;
6519 ;; For nonlocal gotos, we must save both the stack pointer and its
6520 ;; backchain and restore both.  Note that in the nonlocal case, the
6521 ;; save area is a memory location.
6522
6523 (define_expand "save_stack_function"
6524   [(match_operand 0 "general_operand" "")
6525    (match_operand 1 "general_operand" "")]
6526   ""
6527   "DONE;")
6528
6529 (define_expand "restore_stack_function"
6530   [(match_operand 0 "general_operand" "")
6531    (match_operand 1 "general_operand" "")]
6532   ""
6533   "DONE;")
6534
6535 (define_expand "restore_stack_block"
6536   [(use (match_operand 0 "register_operand" ""))
6537    (set (match_dup 2) (match_dup 3))
6538    (set (match_dup 0) (match_operand 1 "register_operand" ""))
6539    (set (match_dup 3) (match_dup 2))]
6540   ""
6541   "
6542 {
6543   operands[2] = gen_reg_rtx (Pmode);
6544   operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6545 }")
6546
6547 (define_expand "save_stack_nonlocal"
6548   [(match_operand 0 "memory_operand" "")
6549    (match_operand 1 "register_operand" "")]
6550   ""
6551   "
6552 {
6553   rtx temp = gen_reg_rtx (Pmode);
6554
6555   /* Copy the backchain to the first word, sp to the second.  */
6556   emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6557   emit_move_insn (operand_subword (operands[0], 0, 0,
6558                  TARGET_64BIT ? TImode : DImode),
6559                  temp);
6560   emit_move_insn (operand_subword (operands[0], 1, 0,
6561                  TARGET_64BIT ? TImode : DImode),
6562                  operands[1]);
6563   DONE;
6564 }")
6565
6566 (define_expand "restore_stack_nonlocal"
6567   [(match_operand 0 "register_operand" "")
6568    (match_operand 1 "memory_operand" "")]
6569   ""
6570   "
6571 {
6572   rtx temp = gen_reg_rtx (Pmode);
6573
6574   /* Restore the backchain from the first word, sp from the second.  */
6575   emit_move_insn (temp,
6576                  operand_subword (operands[1], 0, 0,
6577                  TARGET_64BIT ? TImode : DImode));
6578   emit_move_insn (operands[0],
6579                  operand_subword (operands[1], 1, 0,
6580                  TARGET_64BIT ? TImode : DImode));
6581   emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6582   DONE;
6583 }")
6584
6585
6586 ;
6587 ; nop instruction pattern(s).
6588 ;
6589
6590 (define_insn "nop"
6591   [(const_int 0)]
6592   ""
6593   "lr\\t0,0"
6594   [(set_attr "op_type" "RR")])
6595
6596
6597 ;
6598 ; Special literal pool access instruction pattern(s).
6599 ;
6600
6601 (define_insn "consttable_qi"
6602   [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6603   ""
6604   "*
6605 {
6606   assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6607   return \"\";
6608 }"
6609   [(set_attr "op_type"  "NN")
6610    (set_attr "length"   "1")])
6611
6612 (define_insn "consttable_hi"
6613   [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6614   ""
6615   "*
6616 {
6617   assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6618   return \"\";
6619 }"
6620   [(set_attr "op_type"  "NN")
6621    (set_attr "length"   "2")])
6622
6623 (define_insn "consttable_si"
6624   [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6625   ""
6626   "*
6627 {
6628   if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6629     return \".long\\t%0\";
6630
6631   assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6632   return \"\";
6633 }"
6634   [(set_attr "op_type"  "NN")
6635    (set_attr "length"   "4")])
6636
6637 (define_insn "consttable_di"
6638   [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6639   ""
6640   "*
6641 {
6642   assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6643   return \"\";
6644 }"
6645   [(set_attr "op_type"  "NN")
6646    (set_attr "length"   "8")])
6647
6648 (define_insn "consttable_sf"
6649   [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6650   ""
6651   "*
6652 {
6653   REAL_VALUE_TYPE r;
6654
6655   if (GET_CODE (operands[0]) != CONST_DOUBLE)
6656     abort ();
6657
6658   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6659   assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6660   return \"\";
6661 }"
6662   [(set_attr "op_type"  "NN")
6663    (set_attr "length"   "4")])
6664
6665 (define_insn "consttable_df"
6666   [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6667   ""
6668   "*
6669 {
6670   REAL_VALUE_TYPE r;
6671
6672   if (GET_CODE (operands[0]) != CONST_DOUBLE)
6673     abort ();
6674
6675   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6676   assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6677   return \"\";
6678 }"
6679   [(set_attr "op_type"  "NN")
6680    (set_attr "length"   "8")])
6681
6682 (define_insn "pool_start_31"
6683   [(unspec_volatile [(const_int 0)] 206)]
6684   "!TARGET_64BIT"
6685   ".align\\t4"
6686   [(set_attr "op_type"  "NN")
6687    (set_attr "length"   "2")])
6688
6689 (define_insn "pool_end_31"
6690   [(unspec_volatile [(const_int 0)] 207)]
6691   "!TARGET_64BIT"
6692   ".align\\t2"
6693   [(set_attr "op_type"  "NN")
6694    (set_attr "length"   "2")])
6695
6696 (define_insn "pool_start_64"
6697   [(unspec_volatile [(const_int 0)] 206)]
6698   "TARGET_64BIT"
6699   ".section\\t.rodata\;.align\\t8"
6700   [(set_attr "op_type"  "NN")
6701    (set_attr "length"   "0")])
6702
6703 (define_insn "pool_end_64"
6704   [(unspec_volatile [(const_int 0)] 207)]
6705   "TARGET_64BIT"
6706   ".previous"
6707   [(set_attr "op_type"  "NN")
6708    (set_attr "length"   "0")])
6709
6710 (define_insn "reload_base"
6711   [(set (match_operand:SI 0 "register_operand" "=a")
6712         (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6713   "!TARGET_64BIT"
6714   "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6715   [(set_attr "op_type" "NN")
6716    (set_attr "type"    "la")
6717    (set_attr "length"  "6")])
6718
6719 (define_insn "reload_base2"
6720   [(set (match_operand:SI 0 "register_operand" "=a")
6721         (unspec:SI [(label_ref (match_operand 1 "" ""))] 211))]
6722   "!TARGET_64BIT"
6723   "la\\t%0,%1-.(%0)"
6724   [(set_attr "op_type" "NN")
6725    (set_attr "type"    "la")
6726    (set_attr "length"  "4")])
6727
6728
6729 ;;
6730 ;; Insns related to generating the function prologue and epilogue.
6731 ;;
6732
6733
6734 (define_expand "prologue"
6735   [(use (const_int 0))]
6736   ""
6737   "
6738 {
6739       s390_emit_prologue ();
6740       DONE;
6741 }")
6742
6743 (define_expand "epilogue"
6744   [(use (const_int 1))]
6745   ""
6746   "
6747 {
6748       s390_emit_epilogue ();
6749       DONE;
6750 }")
6751
6752
6753 (define_insn "*return_si"
6754   [(return)
6755    (use (match_operand:SI 0 "register_operand" "a"))]
6756   "!TARGET_64BIT"
6757   "br\\t%0"
6758   [(set_attr "op_type" "RR")
6759    (set_attr "type"    "jsr")
6760    (set_attr "atype"   "mem")])
6761
6762 (define_insn "*return_di"
6763   [(return)
6764    (use (match_operand:DI 0 "register_operand" "a"))]
6765   "TARGET_64BIT"
6766   "br\\t%0"
6767   [(set_attr "op_type" "RR")
6768    (set_attr "type"    "jsr")
6769    (set_attr "atype"   "mem")])
6770
6771
6772 (define_insn "lit"
6773   [(set (reg 13) (pc))
6774    (unspec_volatile [(const_int 0)] 200)]
6775   ""
6776   "*
6777 {
6778    s390_output_constant_pool (asm_out_file);
6779    return \"\";
6780 }"
6781   [(set_attr "op_type" "NN")
6782    (set_attr "type"    "integer")])
6783
6784
6785 ;;
6786 ;; Peephole optimization patterns.
6787 ;;
6788
6789 (define_peephole
6790   [(set (match_operand:SI 0 "memory_operand" "m")
6791         (match_operand:SI 1 "register_operand" "d"))
6792    (set (match_dup 1)
6793         (match_dup 0))]
6794  ""
6795  "st\\t%1,%0")
6796
6797 (define_peephole
6798   [(set (match_operand:SI 0 "memory_operand" "m")
6799         (match_operand:SI 1 "register_operand" "d"))
6800    (set (match_dup 0)
6801         (match_dup 1))]
6802  ""
6803  "st\\t%1,%0")
6804
6805 (define_peephole
6806   [(set (match_operand:SI 0 "register_operand" "")
6807         (match_operand:SI 1 "register_operand" ""))
6808    (parallel
6809     [(set (match_dup 0)
6810           (plus:SI (match_dup 0)
6811                    (match_operand:SI 2 "immediate_operand" "")))
6812      (clobber (reg:CC 33))])]
6813  "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6814    REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6815    REGNO (operands[0]) == BASE_REGISTER ||
6816    REGNO (operands[1]) == BASE_REGISTER) &&
6817   INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6818  "la\\t%0,%c2(%1)")
6819
6820 ;
6821 ; peepholes for fast char instructions
6822 ;
6823
6824 ;(define_peephole
6825 ;  [(set (match_operand:QI 0 "register_operand" "d")
6826 ;        (match_operand:QI 1 "s_operand" "Q"))
6827 ;  (set  (match_operand:SI 2 "register_operand" "0")
6828 ;        (zero_extend:SI (match_dup 0)))]
6829 ; "REGNO(operands[0]) == REGNO(operands[2])"
6830 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6831
6832 ;(define_peephole
6833 ;  [(set (match_operand:QI 0 "register_operand" "d")
6834 ;        (match_operand:QI 1 "s_operand" "Q"))
6835 ;   (set (match_operand:SI 2 "register_operand" "0")
6836 ;        (sign_extend:SI (match_dup 0)))]
6837 ; "REGNO(operands[0]) == REGNO(operands[2])"
6838 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6839
6840 (define_peephole
6841   [(set (match_operand:QI 0 "register_operand" "d")
6842         (match_operand:QI 1 "immediate_operand" "J"))
6843    (set (match_operand:SI 2 "register_operand" "0" )
6844         (sign_extend:SI (match_dup 0) ) )]
6845  "REGNO(operands[0]) == REGNO(operands[2])"
6846  "lhi\\t%0,%h1")
6847
6848 ;
6849 ; peepholes for fast short instructions
6850 ;
6851
6852 ;(define_peephole
6853 ;  [(set (match_operand:HI 0 "register_operand" "d")
6854 ;        (match_operand:HI 1 "s_operand" "Q"))
6855 ;   (set (match_operand:SI 2 "register_operand" "0" )
6856 ;        (zero_extend:SI (match_dup 0)))]
6857 ; "REGNO(operands[0]) == REGNO(operands[2])"
6858 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6859
6860 (define_peephole
6861   [(set (match_operand:HI 0 "register_operand" "d")
6862         (match_operand:HI 1 "memory_operand" "m"))
6863    (set (match_operand:SI 2 "register_operand" "0" )
6864         (sign_extend:SI (match_dup 0)))]
6865  "REGNO(operands[0]) == REGNO(operands[2])"
6866  "lh\\t%0,%1")
6867
6868 (define_peephole
6869   [(set (match_operand:HI 0 "register_operand" "d")
6870         (match_operand:HI 1 "immediate_operand" "K"))
6871    (set (match_operand:SI 2 "register_operand" "0" )
6872         (sign_extend:SI (match_dup 0) ) )]
6873  "REGNO(operands[0]) == REGNO(operands[2])"
6874  "lhi\\t%0,%h1")
6875
6876 ;
6877 ; peepholes for divide instructions
6878 ;
6879
6880 (define_peephole
6881   [(set (match_operand:DI 0 "register_operand" "d")
6882         (match_operand:DI 1 "memory_operand" "m"))
6883    (set (match_dup 0)
6884         (lshiftrt:DI (match_dup 0)
6885         (match_operand:SI 2 "immediate_operand" "J")))
6886    (set (match_dup 0)
6887         (div:SI (match_dup 0)
6888         (match_operand:SI 3 "nonimmediate_operand" "g")))
6889    (set (match_dup 1)
6890         (match_dup 0))]
6891   ""
6892   "*
6893 {
6894    output_asm_insn (\"l\\t%0,%1\", operands);
6895    output_asm_insn (\"srdl\\t%0,%b2\", operands);
6896
6897    if (REG_P (operands[3]))
6898      output_asm_insn (\"dr\\t%0,%3\", operands);
6899    else
6900      output_asm_insn (\"d\\t%0,%3\", operands);
6901
6902    return \"st\\t%N0,%N1\";
6903 }")
6904
6905 (define_peephole
6906   [(set (match_operand:DI 0 "register_operand" "d")
6907         (match_operand:DI 1 "memory_operand" "m"))
6908    (set (match_dup 0)
6909         (lshiftrt:DI (match_dup 0)
6910         (match_operand:SI 2 "immediate_operand" "J")))
6911    (set (match_dup 0)
6912         (mod:SI (match_dup 0)
6913         (match_operand:SI 3 "nonimmediate_operand" "g")))
6914    (set (match_dup 1)
6915         (match_dup 0))]
6916   ""
6917   "*
6918 {
6919    output_asm_insn (\"l\\t%0,%1\", operands);
6920    output_asm_insn (\"srdl\\t%0,%b2\", operands);
6921
6922    if (REG_P (operands[3]))
6923      output_asm_insn (\"dr\\t%0,%3\", operands);
6924    else
6925      output_asm_insn (\"d\\t%0,%3\", operands);
6926
6927    return \"st\\t%0,%1\";
6928 }")
6929