1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
47 ;; Processor type. This attribute must exactly match the processor_type
48 ;; enumeration in s390.h.
50 (define_attr "cpu" "g5,g6,z900"
51 (const (symbol_ref "s390_cpu")))
53 ;; Define an insn type attribute. This is used in function unit delay
56 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
57 cs,vs,store,imul,idiv,
58 branch,jsr,fsimpd,fsimps,
59 floadd,floads,fstored, fstores,
60 fmuld,fmuls,fdivd,fdivs,
61 ftoi,itof,fsqrtd,fsqrts,
63 (const_string "integer"))
65 ;; Operand type. Used to default length attribute values
67 (define_attr "op_type"
68 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
71 ;; Insn are devide in two classes:
72 ;; agen: Insn using agen
73 ;; reg: Insn not using agen
75 (define_attr "atype" "agen,reg"
76 (cond [ (eq_attr "op_type" "E") (const_string "reg")
77 (eq_attr "op_type" "RR") (const_string "reg")
78 (eq_attr "op_type" "RX") (const_string "agen")
79 (eq_attr "op_type" "RI") (const_string "reg")
80 (eq_attr "op_type" "RRE") (const_string "reg")
81 (eq_attr "op_type" "RS") (const_string "agen")
82 (eq_attr "op_type" "RSI") (const_string "agen")
83 (eq_attr "op_type" "S") (const_string "agen")
84 (eq_attr "op_type" "SI") (const_string "agen")
85 (eq_attr "op_type" "SS") (const_string "agen")
86 (eq_attr "op_type" "SSE") (const_string "agen")
87 (eq_attr "op_type" "RXE") (const_string "agen")
88 (eq_attr "op_type" "RSE") (const_string "agen")
89 (eq_attr "op_type" "RIL") (const_string "agen")]
90 (const_string "reg")))
92 ;; Generic pipeline function unit.
94 (define_function_unit "integer" 1 0
95 (eq_attr "type" "none") 0 0)
97 (define_function_unit "integer" 1 0
98 (eq_attr "type" "integer") 1 1)
100 (define_function_unit "integer" 1 0
101 (eq_attr "type" "fsimpd") 1 1)
103 (define_function_unit "integer" 1 0
104 (eq_attr "type" "fsimps") 1 1)
106 (define_function_unit "integer" 1 0
107 (eq_attr "type" "load") 1 1)
109 (define_function_unit "integer" 1 0
110 (eq_attr "type" "floadd") 1 1)
112 (define_function_unit "integer" 1 0
113 (eq_attr "type" "floads") 1 1)
115 (define_function_unit "integer" 1 0
116 (eq_attr "type" "la") 1 1)
118 (define_function_unit "integer" 1 0
119 (eq_attr "type" "larl") 1 1)
121 (define_function_unit "integer" 1 0
122 (eq_attr "type" "lr") 1 1)
124 (define_function_unit "integer" 1 0
125 (eq_attr "type" "branch") 1 1)
127 (define_function_unit "integer" 1 0
128 (eq_attr "type" "store") 1 1)
130 (define_function_unit "integer" 1 0
131 (eq_attr "type" "fstored") 1 1)
133 (define_function_unit "integer" 1 0
134 (eq_attr "type" "fstores") 1 1)
136 (define_function_unit "integer" 1 0
137 (eq_attr "type" "lm") 2 2)
139 (define_function_unit "integer" 1 0
140 (eq_attr "type" "stm") 2 2)
142 (define_function_unit "integer" 1 0
143 (eq_attr "type" "cs") 5 5)
145 (define_function_unit "integer" 1 0
146 (eq_attr "type" "vs") 30 30)
148 (define_function_unit "integer" 1 0
149 (eq_attr "type" "jsr") 5 5)
151 (define_function_unit "integer" 1 0
152 (eq_attr "type" "imul") 7 7)
154 (define_function_unit "integer" 1 0
155 (eq_attr "type" "fmuld") 6 6)
157 (define_function_unit "integer" 1 0
158 (eq_attr "type" "fmuls") 6 6)
160 (define_function_unit "integer" 1 0
161 (eq_attr "type" "idiv") 33 33)
163 (define_function_unit "integer" 1 0
164 (eq_attr "type" "fdivd") 33 33)
166 (define_function_unit "integer" 1 0
167 (eq_attr "type" "fdivs") 33 33)
169 (define_function_unit "integer" 1 0
170 (eq_attr "type" "fsqrtd") 30 30)
172 (define_function_unit "integer" 1 0
173 (eq_attr "type" "fsqrts") 30 30)
175 (define_function_unit "integer" 1 0
176 (eq_attr "type" "ftoi") 2 2)
178 (define_function_unit "integer" 1 0
179 (eq_attr "type" "itof") 2 2)
181 (define_function_unit "integer" 1 0
182 (eq_attr "type" "o2") 2 2)
184 (define_function_unit "integer" 1 0
185 (eq_attr "type" "o3") 3 3)
187 (define_function_unit "integer" 1 0
188 (eq_attr "type" "other") 5 5)
190 ;; Pipeline description for z900
196 (define_attr "length" ""
197 (cond [ (eq_attr "op_type" "E") (const_int 2)
198 (eq_attr "op_type" "RR") (const_int 2)
199 (eq_attr "op_type" "RX") (const_int 4)
200 (eq_attr "op_type" "RI") (const_int 4)
201 (eq_attr "op_type" "RRE") (const_int 4)
202 (eq_attr "op_type" "RS") (const_int 4)
203 (eq_attr "op_type" "RSI") (const_int 4)
204 (eq_attr "op_type" "S") (const_int 4)
205 (eq_attr "op_type" "SI") (const_int 4)
206 (eq_attr "op_type" "SS") (const_int 6)
207 (eq_attr "op_type" "SSE") (const_int 6)
208 (eq_attr "op_type" "RXE") (const_int 6)
209 (eq_attr "op_type" "RSE") (const_int 6)
210 (eq_attr "op_type" "RIL") (const_int 6)]
213 ;; Define attributes for `asm' insns.
215 (define_asm_attributes [(set_attr "type" "other")
216 (set_attr "op_type" "NN")])
222 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
223 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
224 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
225 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
226 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
229 ; CCZ1 -> CCA/CCU/CCS/CCT
232 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
233 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
237 ;;- Compare instructions.
240 (define_expand "cmpdi"
242 (compare:CC (match_operand:DI 0 "register_operand" "")
243 (match_operand:DI 1 "general_operand" "")))]
247 s390_compare_op0 = operands[0];
248 s390_compare_op1 = operands[1];
252 (define_expand "cmpsi"
254 (compare:CC (match_operand:SI 0 "register_operand" "")
255 (match_operand:SI 1 "general_operand" "")))]
259 s390_compare_op0 = operands[0];
260 s390_compare_op1 = operands[1];
264 (define_expand "cmpdf"
266 (compare:CC (match_operand:DF 0 "register_operand" "")
267 (match_operand:DF 1 "general_operand" "")))]
271 s390_compare_op0 = operands[0];
272 s390_compare_op1 = operands[1];
276 (define_expand "cmpsf"
278 (compare:CC (match_operand:SF 0 "register_operand" "")
279 (match_operand:SF 1 "general_operand" "")))]
283 s390_compare_op0 = operands[0];
284 s390_compare_op1 = operands[1];
289 ; Test-under-Mask (zero_extract) instructions
291 (define_insn "*tmdi_ext"
293 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
294 (match_operand:DI 1 "const_int_operand" "n")
295 (match_operand:DI 2 "const_int_operand" "n"))
297 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
298 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
299 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
300 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
301 == INTVAL (operands[2]) >> 4"
304 int part = INTVAL (operands[2]) >> 4;
305 int block = (1 << INTVAL (operands[1])) - 1;
306 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
308 operands[2] = GEN_INT (block << shift);
312 case 0: return \"tmhh\\t%0,%x2\";
313 case 1: return \"tmhl\\t%0,%x2\";
314 case 2: return \"tmlh\\t%0,%x2\";
315 case 3: return \"tmll\\t%0,%x2\";
319 [(set_attr "op_type" "RI")])
321 (define_insn "*tmsi_ext"
323 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
324 (match_operand:SI 1 "const_int_operand" "n")
325 (match_operand:SI 2 "const_int_operand" "n"))
327 "s390_match_ccmode(insn, CCTmode)
328 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
329 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
330 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
331 == INTVAL (operands[2]) >> 4"
334 int part = INTVAL (operands[2]) >> 4;
335 int block = (1 << INTVAL (operands[1])) - 1;
336 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
338 operands[2] = GEN_INT (block << shift);
342 case 0: return \"tmh\\t%0,%x2\";
343 case 1: return \"tml\\t%0,%x2\";
347 [(set_attr "op_type" "RI")])
349 (define_insn "*tmqi_ext"
351 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
352 (match_operand:SI 1 "const_int_operand" "n")
353 (match_operand:SI 2 "const_int_operand" "n"))
355 "s390_match_ccmode(insn, CCTmode)
356 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
357 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
360 int block = (1 << INTVAL (operands[1])) - 1;
361 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
363 operands[2] = GEN_INT (block << shift);
364 return \"tm\\t%0,%b2\";
366 [(set_attr "op_type" "SI")])
368 ; Test-under-Mask instructions
370 (define_insn "*tmdi_mem"
372 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
373 (match_operand:DI 1 "immediate_operand" "n"))
374 (match_operand:DI 2 "immediate_operand" "n")))]
376 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
377 && s390_single_qi (operands[1], DImode, 0) >= 0"
380 int part = s390_single_qi (operands[1], DImode, 0);
381 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
383 operands[0] = gen_rtx_MEM (QImode,
384 plus_constant (XEXP (operands[0], 0), part));
385 return \"tm\\t%0,%b1\";
387 [(set_attr "op_type" "SI")])
389 (define_insn "*tmsi_mem"
391 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
392 (match_operand:SI 1 "immediate_operand" "n"))
393 (match_operand:SI 2 "immediate_operand" "n")))]
394 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
395 && s390_single_qi (operands[1], SImode, 0) >= 0"
398 int part = s390_single_qi (operands[1], SImode, 0);
399 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
401 operands[0] = gen_rtx_MEM (QImode,
402 plus_constant (XEXP (operands[0], 0), part));
403 return \"tm\\t%0,%b1\";
405 [(set_attr "op_type" "SI")])
407 (define_insn "*tmhi_mem"
409 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
410 (match_operand:SI 1 "immediate_operand" "n"))
411 (match_operand:SI 2 "immediate_operand" "n")))]
412 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
413 && s390_single_qi (operands[1], HImode, 0) >= 0"
416 int part = s390_single_qi (operands[1], HImode, 0);
417 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
419 operands[0] = gen_rtx_MEM (QImode,
420 plus_constant (XEXP (operands[0], 0), part));
421 return \"tm\\t%0,%b1\";
423 [(set_attr "op_type" "SI")])
425 (define_insn "*tmqi_mem"
427 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
428 (match_operand:SI 1 "immediate_operand" "n"))
429 (match_operand:SI 2 "immediate_operand" "n")))]
430 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
432 [(set_attr "op_type" "SI")])
434 (define_insn "*tmdi_reg"
436 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
437 (match_operand:DI 1 "immediate_operand" "n"))
438 (match_operand:DI 2 "immediate_operand" "n")))]
440 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
441 && s390_single_hi (operands[1], DImode, 0) >= 0"
444 int part = s390_single_hi (operands[1], DImode, 0);
445 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
449 case 0: return \"tmhh\\t%0,%x1\";
450 case 1: return \"tmhl\\t%0,%x1\";
451 case 2: return \"tmlh\\t%0,%x1\";
452 case 3: return \"tmll\\t%0,%x1\";
456 [(set_attr "op_type" "RI")])
458 (define_insn "*tmsi_reg"
460 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
461 (match_operand:SI 1 "immediate_operand" "n"))
462 (match_operand:SI 2 "immediate_operand" "n")))]
463 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
464 && s390_single_hi (operands[1], SImode, 0) >= 0"
467 int part = s390_single_hi (operands[1], SImode, 0);
468 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
472 case 0: return \"tmh\\t%0,%x1\";
473 case 1: return \"tml\\t%0,%x1\";
477 [(set_attr "op_type" "RI")])
479 (define_insn "*tmhi_full"
481 (compare (match_operand:HI 0 "register_operand" "d")
482 (match_operand:HI 1 "immediate_operand" "n")))]
483 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
485 [(set_attr "op_type" "RX")])
487 (define_insn "*tmqi_full"
489 (compare (match_operand:QI 0 "register_operand" "d")
490 (match_operand:QI 1 "immediate_operand" "n")))]
491 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
493 [(set_attr "op_type" "RI")])
496 ; Load-and-Test instructions
498 (define_insn "*tstdi_sign"
500 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
501 (const_int 32)) (const_int 32))
502 (match_operand:DI 1 "const0_operand" "")))
503 (set (match_operand:DI 2 "register_operand" "=d")
504 (sign_extend:DI (match_dup 0)))]
505 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
507 [(set_attr "op_type" "RRE")])
509 (define_insn "*tstdi"
511 (compare (match_operand:DI 0 "register_operand" "d")
512 (match_operand:DI 1 "const0_operand" "")))
513 (set (match_operand:DI 2 "register_operand" "=d")
515 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
517 [(set_attr "op_type" "RRE")])
519 (define_insn "*tstdi_cconly"
521 (compare (match_operand:DI 0 "register_operand" "d")
522 (match_operand:DI 1 "const0_operand" "")))]
523 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
525 [(set_attr "op_type" "RRE")])
527 (define_insn "*tstdi_cconly_31"
529 (compare (match_operand:DI 0 "register_operand" "d")
530 (match_operand:DI 1 "const0_operand" "")))]
531 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
533 [(set_attr "op_type" "RS")
534 (set_attr "atype" "reg")])
537 (define_insn "*tstsi"
539 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
540 (match_operand:SI 1 "const0_operand" "")))
541 (set (match_operand:SI 2 "register_operand" "=d,d")
543 "s390_match_ccmode(insn, CCSmode)"
547 [(set_attr "op_type" "RR,RS")])
549 (define_insn "*tstsi_cconly"
551 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
552 (match_operand:SI 1 "const0_operand" "")))
553 (clobber (match_scratch:SI 2 "=X,d"))]
554 "s390_match_ccmode(insn, CCSmode)"
558 [(set_attr "op_type" "RR,RS")])
560 (define_insn "*tstsi_cconly2"
562 (compare (match_operand:SI 0 "register_operand" "d")
563 (match_operand:SI 1 "const0_operand" "")))]
564 "s390_match_ccmode(insn, CCSmode)"
566 [(set_attr "op_type" "RR")])
568 (define_insn "*tsthiCCT"
570 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
571 (match_operand:HI 1 "const0_operand" "")))
572 (set (match_operand:HI 2 "register_operand" "=d,0")
574 "s390_match_ccmode(insn, CCTmode)"
578 [(set_attr "op_type" "RS,RI")])
580 (define_insn "*tsthiCCT_cconly"
582 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
583 (match_operand:HI 1 "const0_operand" "")))
584 (clobber (match_scratch:HI 2 "=d,X"))]
585 "s390_match_ccmode(insn, CCTmode)"
589 [(set_attr "op_type" "RS,RI")])
591 (define_insn "*tsthi"
593 (compare (match_operand:HI 0 "s_operand" "Q")
594 (match_operand:HI 1 "const0_operand" "")))
595 (set (match_operand:HI 2 "register_operand" "=d")
597 "s390_match_ccmode(insn, CCSmode)"
599 [(set_attr "op_type" "RS")])
601 (define_insn "*tsthi_cconly"
603 (compare (match_operand:HI 0 "s_operand" "Q")
604 (match_operand:HI 1 "const0_operand" "")))
605 (clobber (match_scratch:HI 2 "=d"))]
606 "s390_match_ccmode(insn, CCSmode)"
608 [(set_attr "op_type" "RS")])
610 (define_insn "*tstqiCCT"
612 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
613 (match_operand:QI 1 "const0_operand" "")))
614 (set (match_operand:QI 2 "register_operand" "=d,0")
616 "s390_match_ccmode(insn, CCTmode)"
620 [(set_attr "op_type" "RS,RI")])
622 (define_insn "*tstqiCCT_cconly"
624 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
625 (match_operand:QI 1 "const0_operand" "")))]
626 "s390_match_ccmode(insn, CCTmode)"
630 [(set_attr "op_type" "SI,RI")])
632 (define_insn "*tstqi"
634 (compare (match_operand:QI 0 "s_operand" "Q")
635 (match_operand:QI 1 "const0_operand" "")))
636 (set (match_operand:QI 2 "register_operand" "=d")
638 "s390_match_ccmode(insn, CCSmode)"
640 [(set_attr "op_type" "RS")])
642 (define_insn "*tstqi_cconly"
644 (compare (match_operand:QI 0 "s_operand" "Q")
645 (match_operand:QI 1 "const0_operand" "")))
646 (clobber (match_scratch:QI 2 "=d"))]
647 "s390_match_ccmode(insn, CCSmode)"
649 [(set_attr "op_type" "RS")])
651 ; Compare (signed) instructions
653 (define_insn "*cmpdi_ccs_sign"
655 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
656 (match_operand:DI 0 "register_operand" "d,d")))]
657 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
661 [(set_attr "op_type" "RRE,RXE")])
663 (define_insn "*cmpdi_ccs"
665 (compare (match_operand:DI 0 "register_operand" "d,d,d")
666 (match_operand:DI 1 "general_operand" "d,K,m")))]
667 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
672 [(set_attr "op_type" "RRE,RI,RXE")])
674 (define_insn "*cmpsi_ccs_sign"
676 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
677 (match_operand:SI 0 "register_operand" "d")))]
678 "s390_match_ccmode(insn, CCSRmode)"
680 [(set_attr "op_type" "RX")])
682 (define_insn "*cmpsi_ccs"
684 (compare (match_operand:SI 0 "register_operand" "d,d,d")
685 (match_operand:SI 1 "general_operand" "d,K,m")))]
686 "s390_match_ccmode(insn, CCSmode)"
691 [(set_attr "op_type" "RR,RI,RX")])
694 ; Compare (unsigned) instructions
696 (define_insn "*cmpdi_ccu_zero"
698 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
699 (match_operand:DI 0 "register_operand" "d,d")))]
700 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
704 [(set_attr "op_type" "RRE,RXE")])
706 (define_insn "*cmpdi_ccu"
708 (compare (match_operand:DI 0 "register_operand" "d,d")
709 (match_operand:DI 1 "general_operand" "d,m")))]
710 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
714 [(set_attr "op_type" "RRE,RXE")])
716 (define_insn "*cmpsi_ccu"
718 (compare (match_operand:SI 0 "register_operand" "d,d")
719 (match_operand:SI 1 "general_operand" "d,m")))]
720 "s390_match_ccmode(insn, CCUmode)"
724 [(set_attr "op_type" "RR,RX")])
726 (define_insn "*cmphi_ccu"
728 (compare (match_operand:HI 0 "register_operand" "d")
729 (match_operand:HI 1 "s_imm_operand" "Q")))]
730 "s390_match_ccmode(insn, CCUmode)"
732 [(set_attr "op_type" "RS")])
734 (define_insn "*cmpqi_ccu"
736 (compare (match_operand:QI 0 "register_operand" "d")
737 (match_operand:QI 1 "s_imm_operand" "Q")))]
738 "s390_match_ccmode(insn, CCUmode)"
740 [(set_attr "op_type" "RS")])
744 (compare (match_operand:QI 0 "memory_operand" "Q")
745 (match_operand:QI 1 "immediate_operand" "n")))]
746 "s390_match_ccmode (insn, CCUmode)"
748 [(set_attr "op_type" "SI")])
750 (define_insn "*cmpdi_ccu_mem"
752 (compare (match_operand:DI 0 "s_operand" "Q")
753 (match_operand:DI 1 "s_imm_operand" "Q")))]
754 "s390_match_ccmode(insn, CCUmode)"
755 "clc\\t%O0(8,%R0),%1"
756 [(set_attr "op_type" "SS")])
758 (define_insn "*cmpsi_ccu_mem"
760 (compare (match_operand:SI 0 "s_operand" "Q")
761 (match_operand:SI 1 "s_imm_operand" "Q")))]
762 "s390_match_ccmode(insn, CCUmode)"
763 "clc\\t%O0(4,%R0),%1"
764 [(set_attr "op_type" "SS")])
766 (define_insn "*cmphi_ccu_mem"
768 (compare (match_operand:HI 0 "s_operand" "Q")
769 (match_operand:HI 1 "s_imm_operand" "Q")))]
770 "s390_match_ccmode(insn, CCUmode)"
771 "clc\\t%O0(2,%R0),%1"
772 [(set_attr "op_type" "SS")])
774 (define_insn "*cmpqi_ccu_mem"
776 (compare (match_operand:QI 0 "s_operand" "Q")
777 (match_operand:QI 1 "s_imm_operand" "Q")))]
778 "s390_match_ccmode(insn, CCUmode)"
779 "clc\\t%O0(1,%R0),%1"
780 [(set_attr "op_type" "SS")])
785 (define_insn "*cmpdf_ccs_0"
787 (compare (match_operand:DF 0 "register_operand" "f")
788 (match_operand:DF 1 "const0_operand" "")))]
789 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
791 [(set_attr "op_type" "RRE")
792 (set_attr "type" "fsimpd")])
794 (define_insn "*cmpdf_ccs_0_ibm"
796 (compare (match_operand:DF 0 "register_operand" "f")
797 (match_operand:DF 1 "const0_operand" "")))]
798 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
800 [(set_attr "op_type" "RR")
801 (set_attr "type" "fsimpd")])
803 (define_insn "*cmpdf_ccs"
805 (compare (match_operand:DF 0 "register_operand" "f,f")
806 (match_operand:DF 1 "general_operand" "f,m")))]
807 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
811 [(set_attr "op_type" "RRE,RXE")
812 (set_attr "type" "fsimpd")])
814 (define_insn "*cmpdf_ccs_ibm"
816 (compare (match_operand:DF 0 "register_operand" "f,f")
817 (match_operand:DF 1 "general_operand" "f,m")))]
818 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
822 [(set_attr "op_type" "RR,RX")
823 (set_attr "type" "fsimpd")])
828 (define_insn "*cmpsf_ccs_0"
830 (compare (match_operand:SF 0 "register_operand" "f")
831 (match_operand:SF 1 "const0_operand" "")))]
832 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
834 [(set_attr "op_type" "RRE")
835 (set_attr "type" "fsimps")])
837 (define_insn "*cmpsf_ccs_0_ibm"
839 (compare (match_operand:SF 0 "register_operand" "f")
840 (match_operand:SF 1 "const0_operand" "")))]
841 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
843 [(set_attr "op_type" "RR")
844 (set_attr "type" "fsimps")])
846 (define_insn "*cmpsf_ccs"
848 (compare (match_operand:SF 0 "register_operand" "f,f")
849 (match_operand:SF 1 "general_operand" "f,m")))]
850 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
854 [(set_attr "op_type" "RRE,RXE")
855 (set_attr "type" "fsimps")])
857 (define_insn "*cmpsf_ccs"
859 (compare (match_operand:SF 0 "register_operand" "f,f")
860 (match_operand:SF 1 "general_operand" "f,m")))]
861 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
865 [(set_attr "op_type" "RR,RX")
866 (set_attr "type" "fsimps")])
870 ;;- Move instructions.
874 ; movti instruction pattern(s).
878 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
879 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
886 mvc\\t%O0(16,%R0),%1"
887 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")])
890 [(set (match_operand:TI 0 "nonimmediate_operand" "")
891 (match_operand:TI 1 "general_operand" ""))]
892 "TARGET_64BIT && reload_completed
893 && !s_operand (operands[0], VOIDmode)
894 && !s_operand (operands[1], VOIDmode)
895 && (register_operand (operands[0], VOIDmode)
896 || register_operand (operands[1], VOIDmode))
897 && (!register_operand (operands[0], VOIDmode)
898 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
900 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
902 [(set (match_dup 2) (match_dup 4))
903 (set (match_dup 3) (match_dup 5))]
906 if (!register_operand (operands[0], VOIDmode)
907 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
910 operands[2] = operand_subword (operands[0], 0, 0, TImode);
911 operands[3] = operand_subword (operands[0], 1, 0, TImode);
912 operands[4] = operand_subword (operands[1], 0, 0, TImode);
913 operands[5] = operand_subword (operands[1], 1, 0, TImode);
917 operands[2] = operand_subword (operands[0], 1, 0, TImode);
918 operands[3] = operand_subword (operands[0], 0, 0, TImode);
919 operands[4] = operand_subword (operands[1], 1, 0, TImode);
920 operands[5] = operand_subword (operands[1], 0, 0, TImode);
925 [(set (match_operand:TI 0 "register_operand" "")
926 (match_operand:TI 1 "memory_operand" ""))]
927 "TARGET_64BIT && reload_completed
928 && !s_operand (operands[1], VOIDmode)"
929 [(set (match_dup 0) (match_dup 1))]
932 rtx addr = operand_subword (operands[0], 1, 0, TImode);
933 s390_load_address (addr, XEXP (operands[1], 0));
934 operands[1] = replace_equiv_address (operands[1], addr);
938 ; movdi instruction pattern(s).
941 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
942 ;; move to get the address of the symbolic object from the GOT.
944 (define_expand "movdi"
945 [(set (match_operand:DI 0 "general_operand" "")
946 (match_operand:DI 1 "general_operand" ""))]
950 /* Handle PIC symbolic constants. */
951 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
952 emit_pic_move (operands, DImode);
954 /* During and after reload, we need to force constants
955 to the literal pool ourselves, if necessary. */
956 if ((reload_in_progress || reload_completed)
957 && CONSTANT_P (operands[1])
958 && (!legitimate_reload_constant_p (operands[1])
959 || FP_REG_P (operands[0])))
960 operands[1] = force_const_mem (DImode, operands[1]);
963 (define_insn "*movdi_lhi"
964 [(set (match_operand:DI 0 "register_operand" "=d")
965 (match_operand:DI 1 "immediate_operand" "K"))]
967 && GET_CODE (operands[1]) == CONST_INT
968 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
969 && !FP_REG_P (operands[0])"
971 [(set_attr "op_type" "RI")])
973 (define_insn "*movdi_lli"
974 [(set (match_operand:DI 0 "register_operand" "=d")
975 (match_operand:DI 1 "immediate_operand" "n"))]
976 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
977 && !FP_REG_P (operands[0])"
980 int part = s390_single_hi (operands[1], DImode, 0);
981 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
985 case 0: return \"llihh\\t%0,%x1\";
986 case 1: return \"llihl\\t%0,%x1\";
987 case 2: return \"llilh\\t%0,%x1\";
988 case 3: return \"llill\\t%0,%x1\";
992 [(set_attr "op_type" "RI")])
994 (define_insn "*movdi_larl"
995 [(set (match_operand:DI 0 "register_operand" "=d")
996 (match_operand:DI 1 "larl_operand" "X"))]
998 && !FP_REG_P (operands[0])"
1000 [(set_attr "op_type" "RIL")
1001 (set_attr "type" "larl")])
1003 (define_insn "*movdi_64"
1004 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1005 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1014 mvc\\t%O0(8,%R0),%1"
1015 [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
1016 (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
1018 (define_insn "*movdi_31"
1019 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
1020 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
1030 mvc\\t%O0(8,%R0),%1"
1031 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
1032 (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
1035 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1036 (match_operand:DI 1 "general_operand" ""))]
1037 "!TARGET_64BIT && reload_completed
1038 && !FP_REG_P (operands[0])
1039 && !FP_REG_P (operands[1])
1040 && !s_operand (operands[0], VOIDmode)
1041 && !s_operand (operands[1], VOIDmode)
1042 && (register_operand (operands[0], VOIDmode)
1043 || register_operand (operands[1], VOIDmode))
1044 && (!register_operand (operands[0], VOIDmode)
1045 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1047 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
1049 [(set (match_dup 2) (match_dup 4))
1050 (set (match_dup 3) (match_dup 5))]
1053 if (!register_operand (operands[0], VOIDmode)
1054 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1057 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1058 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1059 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1060 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1064 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1065 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1066 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1067 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1072 [(set (match_operand:DI 0 "register_operand" "")
1073 (match_operand:DI 1 "memory_operand" ""))]
1074 "!TARGET_64BIT && reload_completed
1075 && !FP_REG_P (operands[0])
1076 && !FP_REG_P (operands[1])
1077 && !s_operand (operands[1], VOIDmode)"
1078 [(set (match_dup 0) (match_dup 1))]
1081 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1082 s390_load_address (addr, XEXP (operands[1], 0));
1083 operands[1] = replace_equiv_address (operands[1], addr);
1087 [(set (match_operand:DI 0 "register_operand" "")
1088 (mem:DI (match_operand 1 "address_operand" "")))]
1090 && !FP_REG_P (operands[0])
1091 && GET_CODE (operands[1]) == SYMBOL_REF
1092 && CONSTANT_POOL_ADDRESS_P (operands[1])
1093 && get_pool_mode (operands[1]) == DImode
1094 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1095 [(set (match_dup 0) (match_dup 2))]
1096 "operands[2] = get_pool_constant (operands[1]);")
1099 ; movsi instruction pattern(s).
1102 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1103 ;; move to get the address of the symbolic object from the GOT.
1105 (define_expand "movsi"
1106 [(set (match_operand:SI 0 "general_operand" "")
1107 (match_operand:SI 1 "general_operand" ""))]
1111 /* Handle PIC symbolic constants. */
1112 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1113 emit_pic_move (operands, SImode);
1115 /* expr.c tries to load an effective address using
1116 force_reg. This fails because we don't have a
1117 generic load_address pattern. Convert the move
1118 to a proper arithmetic operation instead, unless
1119 it is guaranteed to be OK. */
1120 if (GET_CODE (operands[1]) == PLUS
1121 && !legitimate_la_operand_p (operands[1]))
1123 operands[1] = force_operand (operands[1], operands[0]);
1124 if (operands[1] == operands[0])
1128 /* During and after reload, we need to force constants
1129 to the literal pool ourselves, if necessary. */
1130 if ((reload_in_progress || reload_completed)
1131 && CONSTANT_P (operands[1])
1132 && (!legitimate_reload_constant_p (operands[1])
1133 || FP_REG_P (operands[0])))
1134 operands[1] = force_const_mem (SImode, operands[1]);
1137 (define_insn "*movsi_lhi"
1138 [(set (match_operand:SI 0 "register_operand" "=d")
1139 (match_operand:SI 1 "immediate_operand" "K"))]
1140 "GET_CODE (operands[1]) == CONST_INT
1141 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1142 && !FP_REG_P (operands[0])"
1144 [(set_attr "op_type" "RI")])
1146 (define_insn "*movsi_lli"
1147 [(set (match_operand:SI 0 "register_operand" "=d")
1148 (match_operand:SI 1 "immediate_operand" "n"))]
1149 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1150 && !FP_REG_P (operands[0])"
1153 int part = s390_single_hi (operands[1], SImode, 0);
1154 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1158 case 0: return \"llilh\\t%0,%x1\";
1159 case 1: return \"llill\\t%0,%x1\";
1163 [(set_attr "op_type" "RI")])
1165 (define_insn "*movsi"
1166 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1167 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1176 mvc\\t%O0(4,%R0),%1"
1177 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1178 (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
1181 [(set (match_operand:SI 0 "register_operand" "")
1182 (mem:SI (match_operand 1 "address_operand" "")))]
1183 "!FP_REG_P (operands[0])
1184 && GET_CODE (operands[1]) == SYMBOL_REF
1185 && CONSTANT_POOL_ADDRESS_P (operands[1])
1186 && get_pool_mode (operands[1]) == SImode
1187 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1188 [(set (match_dup 0) (match_dup 2))]
1189 "operands[2] = get_pool_constant (operands[1]);")
1192 ; movhi instruction pattern(s).
1195 (define_insn "movhi"
1196 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1197 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1204 mvc\\t%O0(2,%R0),%1"
1205 [(set_attr "op_type" "RR,RI,RX,RX,SS")])
1208 [(set (match_operand:HI 0 "register_operand" "")
1209 (mem:HI (match_operand 1 "address_operand" "")))]
1210 "GET_CODE (operands[1]) == SYMBOL_REF
1211 && CONSTANT_POOL_ADDRESS_P (operands[1])
1212 && get_pool_mode (operands[1]) == HImode
1213 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1214 [(set (match_dup 0) (match_dup 2))]
1215 "operands[2] = get_pool_constant (operands[1]);")
1218 ; movqi instruction pattern(s).
1221 (define_insn "movqi_64"
1222 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1223 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1231 mvc\\t%O0(1,%R0),%1"
1232 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1233 (set_attr "type" "lr,*,*,store,store,cs")])
1235 (define_insn "movqi"
1236 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1237 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1245 mvc\\t%O0(1,%R0),%1"
1246 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")])
1249 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1250 (mem:QI (match_operand 1 "address_operand" "")))]
1251 "GET_CODE (operands[1]) == SYMBOL_REF
1252 && CONSTANT_POOL_ADDRESS_P (operands[1])
1253 && get_pool_mode (operands[1]) == QImode
1254 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1255 [(set (match_dup 0) (match_dup 2))]
1256 "operands[2] = get_pool_constant (operands[1]);")
1259 ; movstrictqi instruction pattern(s).
1262 (define_insn "*movstrictqi"
1263 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1264 (match_operand:QI 1 "memory_operand" "m"))]
1267 [(set_attr "op_type" "RX")])
1270 ; movstricthi instruction pattern(s).
1273 (define_insn "*movstricthi"
1274 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1275 (match_operand:HI 1 "s_imm_operand" "Q"))
1276 (clobber (reg:CC 33))]
1279 [(set_attr "op_type" "RS")])
1283 ; movstrictsi instruction pattern(s).
1286 (define_insn "movstrictsi"
1287 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1288 (match_operand:SI 1 "general_operand" "d,m"))]
1293 [(set_attr "op_type" "RR,RS")
1294 (set_attr "type" "lr,load")])
1298 ; movdf instruction pattern(s).
1301 (define_expand "movdf"
1302 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1303 (match_operand:DF 1 "general_operand" ""))]
1307 /* During and after reload, we need to force constants
1308 to the literal pool ourselves, if necessary. */
1309 if ((reload_in_progress || reload_completed)
1310 && CONSTANT_P (operands[1]))
1311 operands[1] = force_const_mem (DFmode, operands[1]);
1314 (define_insn "*movdf_64"
1315 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1316 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1325 mvc\\t%O0(8,%R0),%1"
1326 [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
1327 (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
1329 (define_insn "*movdf_31"
1330 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1331 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1341 mvc\\t%O0(8,%R0),%1"
1342 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1343 (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
1346 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1347 (match_operand:DF 1 "general_operand" ""))]
1348 "!TARGET_64BIT && reload_completed
1349 && !FP_REG_P (operands[0])
1350 && !FP_REG_P (operands[1])
1351 && !s_operand (operands[0], VOIDmode)
1352 && !s_operand (operands[1], VOIDmode)
1353 && (register_operand (operands[0], VOIDmode)
1354 || register_operand (operands[1], VOIDmode))
1355 && (!register_operand (operands[0], VOIDmode)
1356 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1358 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1360 [(set (match_dup 2) (match_dup 4))
1361 (set (match_dup 3) (match_dup 5))]
1364 if (!register_operand (operands[0], VOIDmode)
1365 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1368 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1369 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1370 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1371 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1375 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1376 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1377 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1378 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1383 [(set (match_operand:DF 0 "register_operand" "")
1384 (match_operand:DF 1 "memory_operand" ""))]
1385 "!TARGET_64BIT && reload_completed
1386 && !FP_REG_P (operands[0])
1387 && !FP_REG_P (operands[1])
1388 && !s_operand (operands[1], VOIDmode)"
1389 [(set (match_dup 0) (match_dup 1))]
1392 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1393 s390_load_address (addr, XEXP (operands[1], 0));
1394 operands[1] = replace_equiv_address (operands[1], addr);
1398 ; movsf instruction pattern(s).
1401 (define_expand "movsf"
1402 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1403 (match_operand:SF 1 "general_operand" ""))]
1407 /* During and after reload, we need to force constants
1408 to the literal pool ourselves, if necessary. */
1409 if ((reload_in_progress || reload_completed)
1410 && CONSTANT_P (operands[1]))
1411 operands[1] = force_const_mem (SFmode, operands[1]);
1414 (define_insn "*movsf"
1415 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1416 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1425 mvc\\t%O0(4,%R0),%1"
1426 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1427 (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
1430 ; load_multiple pattern(s).
1433 (define_expand "load_multiple"
1434 [(match_par_dup 3 [(set (match_operand 0 "" "")
1435 (match_operand 1 "" ""))
1436 (use (match_operand 2 "" ""))])]
1445 /* Support only loading a constant number of fixed-point registers from
1446 memory and only bother with this if more than two */
1447 if (GET_CODE (operands[2]) != CONST_INT
1448 || INTVAL (operands[2]) < 2
1449 || INTVAL (operands[2]) > 16
1450 || GET_CODE (operands[1]) != MEM
1451 || GET_CODE (operands[0]) != REG
1452 || REGNO (operands[0]) >= 16)
1455 count = INTVAL (operands[2]);
1456 regno = REGNO (operands[0]);
1458 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1461 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1463 from = XEXP (operands[1], 0);
1466 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1467 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1468 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1470 from = XEXP (XEXP (operands[1], 0), 0);
1471 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1476 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1481 from = force_reg (Pmode, XEXP (operands[1], 0));
1485 for (i = 0; i < count; i++)
1486 XVECEXP (operands[3], 0, i)
1487 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1488 change_address (operands[1], Pmode,
1489 plus_constant (from,
1490 off + i * UNITS_PER_WORD)));
1493 (define_insn "*load_multiple_di"
1494 [(match_parallel 0 "load_multiple_operation"
1495 [(set (match_operand:DI 1 "register_operand" "=r")
1496 (match_operand:DI 2 "s_operand" "Q"))])]
1500 int words = XVECLEN (operands[0], 0);
1502 if (XVECLEN (operands[0], 0) == 1)
1503 return \"lg\\t%1,0(%2)\";
1505 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1506 return \"lmg\\t%1,%0,%2\";
1508 [(set_attr "op_type" "RXE")
1509 (set_attr "type" "lm")])
1511 (define_insn "*load_multiple_si"
1512 [(match_parallel 0 "load_multiple_operation"
1513 [(set (match_operand:SI 1 "register_operand" "=r")
1514 (match_operand:SI 2 "s_operand" "Q"))])]
1518 int words = XVECLEN (operands[0], 0);
1520 if (XVECLEN (operands[0], 0) == 1)
1521 return \"l\\t%1,0(%2)\";
1523 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1524 return \"lm\\t%1,%0,%2\";
1526 [(set_attr "op_type" "RXE")
1527 (set_attr "type" "lm")])
1530 ; store multiple pattern(s).
1533 (define_expand "store_multiple"
1534 [(match_par_dup 3 [(set (match_operand 0 "" "")
1535 (match_operand 1 "" ""))
1536 (use (match_operand 2 "" ""))])]
1545 /* Support only storing a constant number of fixed-point registers to
1546 memory and only bother with this if more than two. */
1547 if (GET_CODE (operands[2]) != CONST_INT
1548 || INTVAL (operands[2]) < 2
1549 || INTVAL (operands[2]) > 16
1550 || GET_CODE (operands[0]) != MEM
1551 || GET_CODE (operands[1]) != REG
1552 || REGNO (operands[1]) >= 16)
1555 count = INTVAL (operands[2]);
1556 regno = REGNO (operands[1]);
1558 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1562 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1564 to = XEXP (operands[0], 0);
1567 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1568 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1569 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1571 to = XEXP (XEXP (operands[0], 0), 0);
1572 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1577 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1582 to = force_reg (Pmode, XEXP (operands[0], 0));
1586 for (i = 0; i < count; i++)
1587 XVECEXP (operands[3], 0, i)
1588 = gen_rtx_SET (VOIDmode,
1589 change_address (operands[0], Pmode,
1591 off + i * UNITS_PER_WORD)),
1592 gen_rtx_REG (Pmode, regno + i));
1595 (define_insn "*store_multiple_di"
1596 [(match_parallel 0 "store_multiple_operation"
1597 [(set (match_operand:DI 1 "s_operand" "=Q")
1598 (match_operand:DI 2 "register_operand" "r"))])]
1602 int words = XVECLEN (operands[0], 0);
1604 if (XVECLEN (operands[0], 0) == 1)
1605 return \"stg\\t%1,0(%2)\";
1607 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1608 return \"stmg\\t%2,%0,%1\";
1610 [(set_attr "op_type" "RXE")
1611 (set_attr "type" "stm")])
1614 (define_insn "*store_multiple_si"
1615 [(match_parallel 0 "store_multiple_operation"
1616 [(set (match_operand:SI 1 "s_operand" "=Q")
1617 (match_operand:SI 2 "register_operand" "r"))])]
1621 int words = XVECLEN (operands[0], 0);
1623 if (XVECLEN (operands[0], 0) == 1)
1624 return \"st\\t%1,0(%2)\";
1626 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1627 return \"stm\\t%2,%0,%1\";
1629 [(set_attr "op_type" "RXE")
1630 (set_attr "type" "stm")])
1633 ;; String instructions.
1637 ; movstrM instruction pattern(s).
1640 (define_expand "movstrdi"
1641 [(set (match_operand:BLK 0 "memory_operand" "")
1642 (match_operand:BLK 1 "memory_operand" ""))
1643 (use (match_operand:DI 2 "general_operand" ""))
1644 (match_operand 3 "" "")]
1646 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1648 (define_expand "movstrsi"
1649 [(set (match_operand:BLK 0 "memory_operand" "")
1650 (match_operand:BLK 1 "memory_operand" ""))
1651 (use (match_operand:SI 2 "general_operand" ""))
1652 (match_operand 3 "" "")]
1654 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1656 ; Move a block that is up to 256 bytes in length.
1657 ; The block length is taken as (operands[2] % 256) + 1.
1659 (define_insn "movstr_short_64"
1660 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1661 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1662 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1663 (clobber (match_scratch:DI 3 "=X,&a"))]
1667 switch (which_alternative)
1670 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1673 output_asm_insn (\"bras\\t%3,.+10\", operands);
1674 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1675 return \"ex\\t%2,0(%3)\";
1681 [(set_attr "op_type" "SS,NN")
1682 (set_attr "type" "cs,cs")
1683 (set_attr "atype" "*,agen")
1684 (set_attr "length" "*,14")])
1686 (define_insn "movstr_short_31"
1687 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1688 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1689 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1690 (clobber (match_scratch:SI 3 "=X,&a"))]
1694 switch (which_alternative)
1697 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1700 output_asm_insn (\"bras\\t%3,.+10\", operands);
1701 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1702 return \"ex\\t%2,0(%3)\";
1708 [(set_attr "op_type" "SS,NN")
1709 (set_attr "type" "cs,cs")
1710 (set_attr "atype" "*,agen")
1711 (set_attr "length" "*,14")])
1713 ; Move a block of arbitrary length.
1715 (define_insn "movstr_long_64"
1716 [(set (match_operand:TI 0 "register_operand" "=d")
1717 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1718 (lshiftrt:TI (match_dup 2) (const_int 64)))
1720 (set (match_operand:TI 1 "register_operand" "=d")
1721 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1722 (lshiftrt:TI (match_dup 3) (const_int 64)))
1724 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1725 (mem:BLK (subreg:DI (match_dup 3) 0)))
1726 (clobber (reg:CC 33))]
1728 "mvcle\\t%0,%1,0\;jo\\t.-4"
1729 [(set_attr "op_type" "NN")
1730 (set_attr "type" "vs")
1731 (set_attr "length" "8")])
1733 (define_insn "movstr_long_31"
1734 [(set (match_operand:DI 0 "register_operand" "=d")
1735 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1736 (lshiftrt:DI (match_dup 2) (const_int 32)))
1738 (set (match_operand:DI 1 "register_operand" "=d")
1739 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1740 (lshiftrt:DI (match_dup 3) (const_int 32)))
1742 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1743 (mem:BLK (subreg:SI (match_dup 3) 0)))
1744 (clobber (reg:CC 33))]
1746 "mvcle\\t%0,%1,0\;jo\\t.-4"
1747 [(set_attr "op_type" "NN")
1748 (set_attr "type" "vs")
1749 (set_attr "length" "8")])
1752 ; clrstrM instruction pattern(s).
1755 (define_expand "clrstrdi"
1756 [(set (match_operand:BLK 0 "memory_operand" "")
1758 (use (match_operand:DI 1 "general_operand" ""))
1759 (match_operand 2 "" "")]
1761 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1763 (define_expand "clrstrsi"
1764 [(set (match_operand:BLK 0 "memory_operand" "")
1766 (use (match_operand:SI 1 "general_operand" ""))
1767 (match_operand 2 "" "")]
1769 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1771 ; Clear a block that is up to 256 bytes in length.
1772 ; The block length is taken as (operands[2] % 256) + 1.
1774 (define_insn "clrstr_short_64"
1775 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1777 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1778 (clobber (match_scratch:DI 2 "=X,&a"))
1779 (clobber (reg:CC 33))]
1783 switch (which_alternative)
1786 return \"xc\\t%O0(%b1+1,%R0),%0\";
1789 output_asm_insn (\"bras\\t%2,.+10\", operands);
1790 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1791 return \"ex\\t%1,0(%2)\";
1797 [(set_attr "op_type" "SS,NN")
1798 (set_attr "type" "cs,cs")
1799 (set_attr "atype" "*,agen")
1800 (set_attr "length" "*,14")])
1802 (define_insn "clrstr_short_31"
1803 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1805 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1806 (clobber (match_scratch:SI 2 "=X,&a"))
1807 (clobber (reg:CC 33))]
1811 switch (which_alternative)
1814 return \"xc\\t%O0(%b1+1,%R0),%0\";
1817 output_asm_insn (\"bras\\t%2,.+10\", operands);
1818 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1819 return \"ex\\t%1,0(%2)\";
1825 [(set_attr "op_type" "SS,NN")
1826 (set_attr "type" "cs,cs")
1827 (set_attr "atype" "*,agen")
1828 (set_attr "length" "*,14")])
1830 ; Clear a block of arbitrary length.
1832 (define_insn "clrstr_long_64"
1833 [(set (match_operand:TI 0 "register_operand" "=d")
1834 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1835 (lshiftrt:TI (match_dup 2) (const_int 64)))
1837 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1839 (use (match_operand:TI 1 "register_operand" "d"))
1840 (clobber (reg:CC 33))]
1842 "mvcle\\t%0,%1,0\;jo\\t.-4"
1843 [(set_attr "op_type" "NN")
1844 (set_attr "type" "vs")
1845 (set_attr "length" "8")])
1847 (define_insn "clrstr_long_31"
1848 [(set (match_operand:DI 0 "register_operand" "=d")
1849 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1850 (lshiftrt:DI (match_dup 2) (const_int 32)))
1852 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1854 (use (match_operand:DI 1 "register_operand" "d"))
1855 (clobber (reg:CC 33))]
1857 "mvcle\\t%0,%1,0\;jo\\t.-4"
1858 [(set_attr "op_type" "NN")
1859 (set_attr "type" "vs")
1860 (set_attr "length" "8")])
1863 ; cmpstrM instruction pattern(s).
1866 (define_expand "cmpstrdi"
1867 [(set (match_operand:DI 0 "register_operand" "")
1868 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1869 (match_operand:BLK 2 "memory_operand" "") ) )
1870 (use (match_operand:DI 3 "general_operand" ""))
1871 (use (match_operand:DI 4 "" ""))]
1873 "s390_expand_cmpstr (operands[0], operands[1],
1874 operands[2], operands[3]); DONE;")
1876 (define_expand "cmpstrsi"
1877 [(set (match_operand:SI 0 "register_operand" "")
1878 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1879 (match_operand:BLK 2 "memory_operand" "") ) )
1880 (use (match_operand:SI 3 "general_operand" ""))
1881 (use (match_operand:SI 4 "" ""))]
1883 "s390_expand_cmpstr (operands[0], operands[1],
1884 operands[2], operands[3]); DONE;")
1886 ; Compare a block that is up to 256 bytes in length.
1887 ; The block length is taken as (operands[2] % 256) + 1.
1889 (define_insn "cmpstr_short_64"
1891 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1892 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1893 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1894 (clobber (match_scratch:DI 3 "=X,&a"))]
1898 switch (which_alternative)
1901 return \"clc\\t%O0(%b2+1,%R0),%1\";
1904 output_asm_insn (\"bras\\t%3,.+10\", operands);
1905 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1906 return \"ex\\t%2,0(%3)\";
1912 [(set_attr "op_type" "SS,NN")
1913 (set_attr "type" "cs,cs")
1914 (set_attr "atype" "*,agen")
1915 (set_attr "length" "*,14")])
1917 (define_insn "cmpstr_short_31"
1919 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1920 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1921 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1922 (clobber (match_scratch:SI 3 "=X,&a"))]
1926 switch (which_alternative)
1929 return \"clc\\t%O0(%b2+1,%R0),%1\";
1932 output_asm_insn (\"bras\\t%3,.+10\", operands);
1933 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1934 return \"ex\\t%2,0(%3)\";
1940 [(set_attr "op_type" "SS,NN")
1941 (set_attr "type" "cs,cs")
1942 (set_attr "atype" "*,agen")
1943 (set_attr "length" "*,14")])
1945 ; Compare a block of arbitrary length.
1947 (define_insn "cmpstr_long_64"
1948 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1949 (clobber (match_operand:TI 1 "register_operand" "=d"))
1951 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1952 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1954 (use (match_dup 3))]
1957 [(set_attr "op_type" "RR")
1958 (set_attr "type" "vs")])
1960 (define_insn "cmpstr_long_31"
1961 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1962 (clobber (match_operand:DI 1 "register_operand" "=d"))
1964 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1965 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1967 (use (match_dup 3))]
1970 [(set_attr "op_type" "RR")
1971 (set_attr "type" "vs")])
1973 ; Convert condition code to integer in range (-1, 0, 1)
1975 (define_insn "cmpint_si"
1976 [(set (match_operand:SI 0 "register_operand" "=d")
1977 (compare:SI (reg:CCS 33) (const_int 0)))]
1981 output_asm_insn (\"lhi\\t%0,1\", operands);
1982 output_asm_insn (\"jh\\t.+12\", operands);
1983 output_asm_insn (\"jl\\t.+6\", operands);
1984 output_asm_insn (\"sr\\t%0,%0\", operands);
1985 return \"lcr\\t%0,%0\";
1987 [(set_attr "op_type" "NN")
1988 (set_attr "length" "16")
1989 (set_attr "type" "other")])
1991 (define_insn "cmpint_di"
1992 [(set (match_operand:DI 0 "register_operand" "=d")
1993 (compare:DI (reg:CCS 33) (const_int 0)))]
1997 output_asm_insn (\"lghi\\t%0,1\", operands);
1998 output_asm_insn (\"jh\\t.+12\", operands);
1999 output_asm_insn (\"jl\\t.+6\", operands);
2000 output_asm_insn (\"sgr\\t%0,%0\", operands);
2001 return \"lcgr\\t%0,%0\";
2003 [(set_attr "op_type" "NN")
2004 (set_attr "length" "22")
2005 (set_attr "type" "other")])
2009 ;;- Conversion instructions.
2012 (define_insn "*sethighqisi"
2013 [(set (match_operand:SI 0 "register_operand" "=d")
2014 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
2015 (clobber (reg:CC 33))]
2018 [(set_attr "op_type" "RS")])
2020 (define_insn "*sethighhisi"
2021 [(set (match_operand:SI 0 "register_operand" "=d")
2022 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
2023 (clobber (reg:CC 33))]
2026 [(set_attr "op_type" "RS")])
2028 (define_insn "*sethighqidi_64"
2029 [(set (match_operand:DI 0 "register_operand" "=d")
2030 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2031 (clobber (reg:CC 33))]
2034 [(set_attr "op_type" "RSE")])
2036 (define_insn "*sethighqidi_31"
2037 [(set (match_operand:DI 0 "register_operand" "=d")
2038 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2039 (clobber (reg:CC 33))]
2042 [(set_attr "op_type" "RS")])
2044 (define_insn_and_split "*extractqi"
2045 [(set (match_operand:SI 0 "register_operand" "=d")
2046 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2047 (match_operand 2 "const_int_operand" "n")
2049 (clobber (reg:CC 33))]
2051 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2053 "&& reload_completed"
2055 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2056 (clobber (reg:CC 33))])
2057 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2060 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2061 operands[1] = change_address (operands[1], QImode, 0);
2063 [(set_attr "type" "o2")
2064 (set_attr "atype" "agen")])
2066 (define_insn_and_split "*extracthi"
2067 [(set (match_operand:SI 0 "register_operand" "=d")
2068 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2069 (match_operand 2 "const_int_operand" "n")
2071 (clobber (reg:CC 33))]
2073 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2075 "&& reload_completed"
2077 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2078 (clobber (reg:CC 33))])
2079 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2082 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2083 operands[1] = change_address (operands[1], HImode, 0);
2085 [(set_attr "type" "o2")
2086 (set_attr "atype" "agen")])
2089 ; extendsidi2 instruction pattern(s).
2092 (define_expand "extendsidi2"
2093 [(set (match_operand:DI 0 "register_operand" "")
2094 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2100 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2101 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2102 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2103 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2109 (define_insn "*extendsidi2"
2110 [(set (match_operand:DI 0 "register_operand" "=d,d")
2111 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2116 [(set_attr "op_type" "RRE,RXE")])
2119 ; extendhidi2 instruction pattern(s).
2122 (define_expand "extendhidi2"
2123 [(set (match_operand:DI 0 "register_operand" "")
2124 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2130 rtx tmp = gen_reg_rtx (SImode);
2131 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2132 emit_insn (gen_extendsidi2 (operands[0], tmp));
2137 operands[1] = gen_lowpart (DImode, operands[1]);
2138 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2139 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2145 (define_insn "*extendhidi2"
2146 [(set (match_operand:DI 0 "register_operand" "=d")
2147 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2150 [(set_attr "op_type" "RXE")])
2153 ; extendqidi2 instruction pattern(s).
2156 (define_expand "extendqidi2"
2157 [(set (match_operand:DI 0 "register_operand" "")
2158 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2164 rtx tmp = gen_reg_rtx (SImode);
2165 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2166 emit_insn (gen_extendsidi2 (operands[0], tmp));
2171 operands[1] = gen_lowpart (DImode, operands[1]);
2172 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2173 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2180 [(set (match_operand:DI 0 "register_operand" "")
2181 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2182 "TARGET_64BIT && !reload_completed"
2184 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2185 (clobber (reg:CC 33))])
2187 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2188 (clobber (reg:CC 33))])]
2192 ; extendhisi2 instruction pattern(s).
2195 (define_expand "extendhisi2"
2196 [(set (match_operand:SI 0 "register_operand" "")
2197 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2201 operands[1] = gen_lowpart (SImode, operands[1]);
2202 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2203 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2208 (define_insn "*extendhisi2"
2209 [(set (match_operand:SI 0 "register_operand" "=d")
2210 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2213 [(set_attr "op_type" "RX")])
2216 ; extendqisi2 instruction pattern(s).
2219 (define_expand "extendqisi2"
2220 [(set (match_operand:SI 0 "register_operand" "")
2221 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2225 operands[1] = gen_lowpart (SImode, operands[1]);
2226 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2227 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2233 [(set (match_operand:SI 0 "register_operand" "")
2234 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2237 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2238 (clobber (reg:CC 33))])
2240 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2241 (clobber (reg:CC 33))])]
2245 ; extendqihi2 instruction pattern(s).
2250 ; zero_extendsidi2 instruction pattern(s).
2253 (define_expand "zero_extendsidi2"
2254 [(set (match_operand:DI 0 "register_operand" "")
2255 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2261 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2262 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2263 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2269 (define_insn "*zero_extendsidi2"
2270 [(set (match_operand:DI 0 "register_operand" "=d,d")
2271 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2276 [(set_attr "op_type" "RRE,RXE")])
2279 ; zero_extendhidi2 instruction pattern(s).
2282 (define_expand "zero_extendhidi2"
2283 [(set (match_operand:DI 0 "register_operand" "")
2284 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2290 rtx tmp = gen_reg_rtx (SImode);
2291 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2292 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2297 operands[1] = gen_lowpart (DImode, operands[1]);
2298 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2299 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2305 (define_insn "*zero_extendhidi2"
2306 [(set (match_operand:DI 0 "register_operand" "=d")
2307 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2310 [(set_attr "op_type" "RXE")])
2313 ; zero_extendqidi2 instruction pattern(s)
2316 (define_expand "zero_extendqidi2"
2317 [(set (match_operand:DI 0 "register_operand" "")
2318 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2324 rtx tmp = gen_reg_rtx (SImode);
2325 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2326 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2331 operands[1] = gen_lowpart (DImode, operands[1]);
2332 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2333 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2339 (define_insn "*zero_extendqidi2"
2340 [(set (match_operand:DI 0 "register_operand" "=d")
2341 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2344 [(set_attr "op_type" "RXE")])
2347 ; zero_extendhisi2 instruction pattern(s).
2350 (define_expand "zero_extendhisi2"
2351 [(set (match_operand:SI 0 "register_operand" "")
2352 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2356 operands[1] = gen_lowpart (SImode, operands[1]);
2357 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2362 (define_insn "*zero_extendhisi2_64"
2363 [(set (match_operand:SI 0 "register_operand" "=d")
2364 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2367 [(set_attr "op_type" "RXE")])
2369 (define_insn_and_split "*zero_extendhisi2_31"
2370 [(set (match_operand:SI 0 "register_operand" "=&d")
2371 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2372 (clobber (reg:CC 33))]
2375 "&& reload_completed"
2376 [(set (match_dup 0) (const_int 0))
2378 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2379 (clobber (reg:CC 33))])]
2380 "operands[2] = gen_lowpart (HImode, operands[0]);"
2381 [(set_attr "type" "o2")
2382 (set_attr "atype" "agen")])
2385 ; zero_extendqisi2 instruction pattern(s).
2388 (define_expand "zero_extendqisi2"
2389 [(set (match_operand:SI 0 "register_operand" "")
2390 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2394 operands[1] = gen_lowpart (SImode, operands[1]);
2395 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2400 (define_insn "*zero_extendqisi2_64"
2401 [(set (match_operand:SI 0 "register_operand" "=d")
2402 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2405 [(set_attr "op_type" "RXE")])
2407 (define_insn_and_split "*zero_extendqisi2_31"
2408 [(set (match_operand:SI 0 "register_operand" "=&d")
2409 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2412 "&& reload_completed"
2413 [(set (match_dup 0) (const_int 0))
2414 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2415 "operands[2] = gen_lowpart (QImode, operands[0]);"
2416 [(set_attr "type" "o2")
2417 (set_attr "atype" "agen")])
2420 ; zero_extendqihi2 instruction pattern(s).
2423 (define_expand "zero_extendqihi2"
2424 [(set (match_operand:HI 0 "register_operand" "")
2425 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2429 operands[1] = gen_lowpart (HImode, operands[1]);
2430 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2435 (define_insn "*zero_extendqihi2_64"
2436 [(set (match_operand:HI 0 "register_operand" "=d")
2437 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2440 [(set_attr "op_type" "RXE")])
2442 (define_insn_and_split "*zero_extendqihi2_31"
2443 [(set (match_operand:HI 0 "register_operand" "=&d")
2444 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2447 "&& reload_completed"
2448 [(set (match_dup 0) (const_int 0))
2449 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2450 "operands[2] = gen_lowpart (QImode, operands[0]);"
2451 [(set_attr "type" "o2")
2452 (set_attr "atype" "agen")])
2456 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2459 (define_expand "fixuns_truncdfdi2"
2460 [(set (match_operand:DI 0 "register_operand" "")
2461 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2462 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2465 rtx label1 = gen_label_rtx ();
2466 rtx label2 = gen_label_rtx ();
2467 rtx temp = gen_reg_rtx (DFmode);
2468 operands[1] = force_reg (DFmode, operands[1]);
2470 emit_insn (gen_cmpdf (operands[1],
2471 CONST_DOUBLE_FROM_REAL_VALUE (
2472 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2473 emit_jump_insn (gen_blt (label1));
2474 emit_insn (gen_subdf3 (temp, operands[1],
2475 CONST_DOUBLE_FROM_REAL_VALUE (
2476 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2477 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2480 emit_label (label1);
2481 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2482 emit_label (label2);
2486 (define_expand "fix_truncdfdi2"
2487 [(set (match_operand:DI 0 "register_operand" "")
2488 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2489 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2492 operands[1] = force_reg (DFmode, operands[1]);
2493 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2497 (define_insn "fix_truncdfdi2_ieee"
2498 [(set (match_operand:DI 0 "register_operand" "=d")
2499 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2500 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2501 (clobber (reg:CC 33))]
2502 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2504 [(set_attr "op_type" "RRE")
2505 (set_attr "type" "ftoi")])
2508 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2511 (define_expand "fixuns_truncdfsi2"
2512 [(set (match_operand:SI 0 "register_operand" "")
2513 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2514 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2517 rtx label1 = gen_label_rtx ();
2518 rtx label2 = gen_label_rtx ();
2519 rtx temp = gen_reg_rtx (DFmode);
2521 operands[1] = force_reg (DFmode,operands[1]);
2522 emit_insn (gen_cmpdf (operands[1],
2523 CONST_DOUBLE_FROM_REAL_VALUE (
2524 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2525 emit_jump_insn (gen_blt (label1));
2526 emit_insn (gen_subdf3 (temp, operands[1],
2527 CONST_DOUBLE_FROM_REAL_VALUE (
2528 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2529 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2532 emit_label (label1);
2533 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2534 emit_label (label2);
2538 (define_expand "fix_truncdfsi2"
2539 [(set (match_operand:SI 0 "register_operand" "")
2540 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2544 if (TARGET_IBM_FLOAT)
2546 /* This is the algorithm from POP chapter A.5.7.2. */
2548 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2549 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2550 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2552 operands[1] = force_reg (DFmode, operands[1]);
2553 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2554 two31r, two32, temp));
2558 operands[1] = force_reg (DFmode, operands[1]);
2559 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2565 (define_insn "fix_truncdfsi2_ieee"
2566 [(set (match_operand:SI 0 "register_operand" "=d")
2567 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2568 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2569 (clobber (reg:CC 33))]
2570 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2572 [(set_attr "op_type" "RRE")
2573 (set_attr "type" "other" )])
2575 (define_insn "fix_truncdfsi2_ibm"
2576 [(set (match_operand:SI 0 "register_operand" "=d")
2577 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2578 (use (match_operand:DI 2 "immediate_operand" "m"))
2579 (use (match_operand:DI 3 "immediate_operand" "m"))
2580 (use (match_operand:BLK 4 "memory_operand" "m"))
2581 (clobber (reg:CC 33))]
2582 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2585 output_asm_insn (\"sd\\t%1,%2\", operands);
2586 output_asm_insn (\"aw\\t%1,%3\", operands);
2587 output_asm_insn (\"std\\t%1,%4\", operands);
2588 output_asm_insn (\"xi\\t%N4,128\", operands);
2589 return \"l\\t%0,%N4\";
2591 [(set_attr "op_type" "NN")
2592 (set_attr "type" "ftoi")
2593 (set_attr "atype" "agen")
2594 (set_attr "length" "20")])
2597 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2600 (define_expand "fixuns_truncsfdi2"
2601 [(set (match_operand:DI 0 "register_operand" "")
2602 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2603 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2606 rtx label1 = gen_label_rtx ();
2607 rtx label2 = gen_label_rtx ();
2608 rtx temp = gen_reg_rtx (SFmode);
2610 operands[1] = force_reg (SFmode, operands[1]);
2611 emit_insn (gen_cmpsf (operands[1],
2612 CONST_DOUBLE_FROM_REAL_VALUE (
2613 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2614 emit_jump_insn (gen_blt (label1));
2616 emit_insn (gen_subsf3 (temp, operands[1],
2617 CONST_DOUBLE_FROM_REAL_VALUE (
2618 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2619 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2622 emit_label (label1);
2623 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2624 emit_label (label2);
2628 (define_expand "fix_truncsfdi2"
2629 [(set (match_operand:DI 0 "register_operand" "")
2630 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2631 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2634 operands[1] = force_reg (SFmode, operands[1]);
2635 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2639 (define_insn "fix_truncsfdi2_ieee"
2640 [(set (match_operand:DI 0 "register_operand" "=d")
2641 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2642 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2643 (clobber (reg:CC 33))]
2644 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2646 [(set_attr "op_type" "RRE")
2647 (set_attr "type" "ftoi")])
2650 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2653 (define_expand "fixuns_truncsfsi2"
2654 [(set (match_operand:SI 0 "register_operand" "")
2655 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2656 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2659 rtx label1 = gen_label_rtx ();
2660 rtx label2 = gen_label_rtx ();
2661 rtx temp = gen_reg_rtx (SFmode);
2663 operands[1] = force_reg (SFmode, operands[1]);
2664 emit_insn (gen_cmpsf (operands[1],
2665 CONST_DOUBLE_FROM_REAL_VALUE (
2666 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2667 emit_jump_insn (gen_blt (label1));
2668 emit_insn (gen_subsf3 (temp, operands[1],
2669 CONST_DOUBLE_FROM_REAL_VALUE (
2670 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2671 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2674 emit_label (label1);
2675 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2676 emit_label (label2);
2680 (define_expand "fix_truncsfsi2"
2681 [(set (match_operand:SI 0 "register_operand" "")
2682 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2686 if (TARGET_IBM_FLOAT)
2688 /* Convert to DFmode and then use the POP algorithm. */
2689 rtx temp = gen_reg_rtx (DFmode);
2690 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2691 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2695 operands[1] = force_reg (SFmode, operands[1]);
2696 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2702 (define_insn "fix_truncsfsi2_ieee"
2703 [(set (match_operand:SI 0 "register_operand" "=d")
2704 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2705 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2706 (clobber (reg:CC 33))]
2707 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2709 [(set_attr "op_type" "RRE")
2710 (set_attr "type" "ftoi")])
2713 ; floatdidf2 instruction pattern(s).
2716 (define_insn "floatdidf2"
2717 [(set (match_operand:DF 0 "register_operand" "=f")
2718 (float:DF (match_operand:DI 1 "register_operand" "d")))
2719 (clobber (reg:CC 33))]
2720 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2722 [(set_attr "op_type" "RRE")
2723 (set_attr "type" "other" )])
2726 ; floatdisf2 instruction pattern(s).
2729 (define_insn "floatdisf2"
2730 [(set (match_operand:SF 0 "register_operand" "=f")
2731 (float:SF (match_operand:DI 1 "register_operand" "d")))
2732 (clobber (reg:CC 33))]
2733 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2735 [(set_attr "op_type" "RRE")
2736 (set_attr "type" "itof" )])
2739 ; floatsidf2 instruction pattern(s).
2742 (define_expand "floatsidf2"
2744 [(set (match_operand:DF 0 "register_operand" "")
2745 (float:DF (match_operand:SI 1 "register_operand" "")))
2746 (clobber (reg:CC 33))])]
2750 if (TARGET_IBM_FLOAT)
2752 /* This is the algorithm from POP chapter A.5.7.1. */
2754 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2755 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2757 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2762 (define_insn "floatsidf2_ieee"
2763 [(set (match_operand:DF 0 "register_operand" "=f")
2764 (float:DF (match_operand:SI 1 "register_operand" "d")))
2765 (clobber (reg:CC 33))]
2766 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2768 [(set_attr "op_type" "RRE")
2769 (set_attr "type" "itof" )])
2771 (define_insn "floatsidf2_ibm"
2772 [(set (match_operand:DF 0 "register_operand" "=f")
2773 (float:DF (match_operand:SI 1 "register_operand" "d")))
2774 (use (match_operand:DI 2 "immediate_operand" "m"))
2775 (use (match_operand:BLK 3 "memory_operand" "m"))
2776 (clobber (reg:CC 33))]
2777 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2780 output_asm_insn (\"st\\t%1,%N3\", operands);
2781 output_asm_insn (\"xi\\t%N3,128\", operands);
2782 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2783 output_asm_insn (\"ld\\t%0,%3\", operands);
2784 return \"sd\\t%0,%2\";
2786 [(set_attr "op_type" "NN")
2787 (set_attr "type" "other" )
2788 (set_attr "atype" "agen")
2789 (set_attr "length" "20")])
2792 ; floatsisf2 instruction pattern(s).
2795 (define_expand "floatsisf2"
2797 [(set (match_operand:SF 0 "register_operand" "")
2798 (float:SF (match_operand:SI 1 "register_operand" "")))
2799 (clobber (reg:CC 33))])]
2803 if (TARGET_IBM_FLOAT)
2805 /* Use the POP algorithm to convert to DFmode and then truncate. */
2806 rtx temp = gen_reg_rtx (DFmode);
2807 emit_insn (gen_floatsidf2 (temp, operands[1]));
2808 emit_insn (gen_truncdfsf2 (operands[0], temp));
2813 (define_insn "floatsisf2_ieee"
2814 [(set (match_operand:SF 0 "register_operand" "=f")
2815 (float:SF (match_operand:SI 1 "register_operand" "d")))
2816 (clobber (reg:CC 33))]
2817 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2819 [(set_attr "op_type" "RRE")
2820 (set_attr "type" "itof" )])
2823 ; truncdfsf2 instruction pattern(s).
2826 (define_expand "truncdfsf2"
2827 [(set (match_operand:SF 0 "register_operand" "")
2828 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2832 (define_insn "truncdfsf2_ieee"
2833 [(set (match_operand:SF 0 "register_operand" "=f")
2834 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2835 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2837 [(set_attr "op_type" "RRE")])
2839 (define_insn "truncdfsf2_ibm"
2840 [(set (match_operand:SF 0 "register_operand" "=f,f")
2841 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2842 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2846 [(set_attr "op_type" "RR,RX")
2847 (set_attr "type" "floads,floads")])
2850 ; extendsfdf2 instruction pattern(s).
2853 (define_expand "extendsfdf2"
2854 [(set (match_operand:DF 0 "register_operand" "")
2855 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2859 if (TARGET_IBM_FLOAT)
2861 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2866 (define_insn "extendsfdf2_ieee"
2867 [(set (match_operand:DF 0 "register_operand" "=f,f")
2868 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2869 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2873 [(set_attr "op_type" "RRE,RXE")
2874 (set_attr "type" "floads,floads")])
2876 (define_insn "extendsfdf2_ibm"
2877 [(set (match_operand:DF 0 "register_operand" "=f,f")
2878 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2879 (clobber (reg:CC 33))]
2880 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2882 sdr\\t%0,%0\;ler\\t%0,%1
2883 sdr\\t%0,%0\;le\\t%0,%1"
2884 [(set_attr "op_type" "NN,NN")
2885 (set_attr "atype" "reg,agen")
2886 (set_attr "length" "4,6")
2887 (set_attr "type" "o2,o2")])
2891 ;; ARITHMETRIC OPERATIONS
2893 ; arithmetric operations set the ConditionCode,
2894 ; because of unpredictable Bits in Register for Halfword and Byte
2895 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2898 ;;- Add instructions.
2902 ; adddi3 instruction pattern(s).
2905 (define_insn "*la_64_cc"
2906 [(set (match_operand:DI 0 "register_operand" "=d")
2907 (match_operand:QI 1 "address_operand" "p"))
2908 (clobber (reg:CC 33))]
2910 && preferred_la_operand_p (operands[1], 1)"
2912 [(set_attr "op_type" "RX")
2913 (set_attr "type" "la")])
2916 [(set (match_operand:DI 0 "register_operand" "")
2917 (match_operand:QI 1 "address_operand" ""))
2918 (clobber (reg:CC 33))]
2919 "TARGET_64BIT && reload_completed
2920 && preferred_la_operand_p (operands[1], 0)"
2921 [(set (match_dup 0) (match_dup 1))])
2923 (define_insn "*adddi3_sign"
2924 [(set (match_operand:DI 0 "register_operand" "=d,d")
2925 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2926 (match_operand:DI 1 "register_operand" "0,0")))
2927 (clobber (reg:CC 33))]
2932 [(set_attr "op_type" "RRE,RXE")])
2934 (define_insn "*adddi3_zero_cc"
2936 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2937 (match_operand:DI 1 "register_operand" "0,0"))
2939 (set (match_operand:DI 0 "register_operand" "=d,d")
2940 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2941 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2945 [(set_attr "op_type" "RRE,RXE")])
2947 (define_insn "*adddi3_zero_cconly"
2949 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2950 (match_operand:DI 1 "register_operand" "0,0"))
2952 (clobber (match_scratch:DI 0 "=d,d"))]
2953 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2957 [(set_attr "op_type" "RRE,RXE")])
2959 (define_insn "*adddi3_zero"
2960 [(set (match_operand:DI 0 "register_operand" "=d,d")
2961 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2962 (match_operand:DI 1 "register_operand" "0,0")))
2963 (clobber (reg:CC 33))]
2968 [(set_attr "op_type" "RRE,RXE")])
2970 (define_insn "*adddi3_imm_cc"
2972 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2973 (match_operand:DI 2 "const_int_operand" "K"))
2975 (set (match_operand:DI 0 "register_operand" "=d")
2976 (plus:DI (match_dup 1) (match_dup 2)))]
2978 && s390_match_ccmode (insn, CCAmode)
2979 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2981 [(set_attr "op_type" "RI")])
2983 (define_insn "*adddi3_cc"
2985 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2986 (match_operand:DI 2 "general_operand" "d,m"))
2988 (set (match_operand:DI 0 "register_operand" "=d,d")
2989 (plus:DI (match_dup 1) (match_dup 2)))]
2990 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2994 [(set_attr "op_type" "RRE,RXE")])
2996 (define_insn "*adddi3_cconly"
2998 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2999 (match_operand:DI 2 "general_operand" "d,m"))
3001 (clobber (match_scratch:DI 0 "=d,d"))]
3002 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3006 [(set_attr "op_type" "RRE,RXE")])
3008 (define_insn "*adddi3_cconly2"
3010 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3011 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3012 (clobber (match_scratch:DI 0 "=d,d"))]
3013 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3017 [(set_attr "op_type" "RRE,RXE")])
3019 (define_insn "*adddi3_64"
3020 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3021 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3022 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3023 (clobber (reg:CC 33))]
3029 [(set_attr "op_type" "RRE,RI,RXE")])
3031 (define_insn_and_split "*adddi3_31"
3032 [(set (match_operand:DI 0 "register_operand" "=&d")
3033 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3034 (match_operand:DI 2 "general_operand" "dm") ) )
3035 (clobber (reg:CC 33))]
3038 "&& reload_completed"
3040 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3041 (clobber (reg:CC 33))])
3044 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3046 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3048 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3050 (label_ref (match_dup 9))))
3052 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3053 (clobber (reg:CC 33))])
3055 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3056 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3057 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3058 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3059 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3060 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3061 operands[9] = gen_label_rtx ();"
3062 [(set_attr "op_type" "NN")
3063 (set_attr "type" "o3")])
3065 (define_expand "adddi3"
3067 [(set (match_operand:DI 0 "register_operand" "")
3068 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3069 (match_operand:DI 2 "general_operand" "")))
3070 (clobber (reg:CC 33))])]
3074 (define_insn "*la_64"
3075 [(set (match_operand:DI 0 "register_operand" "=d")
3076 (match_operand:QI 1 "address_operand" "p"))]
3079 [(set_attr "op_type" "RX")
3080 (set_attr "type" "la")])
3082 (define_expand "reload_indi"
3083 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3084 (match_operand:DI 1 "s390_plus_operand" "")
3085 (match_operand:DI 2 "register_operand" "=&a")])]
3089 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3095 ; addsi3 instruction pattern(s).
3098 (define_insn "*la_31_cc"
3099 [(set (match_operand:SI 0 "register_operand" "=d")
3100 (match_operand:QI 1 "address_operand" "p"))
3101 (clobber (reg:CC 33))]
3103 && preferred_la_operand_p (operands[1], 1)"
3105 [(set_attr "op_type" "RX")
3106 (set_attr "type" "la")])
3109 [(set (match_operand:SI 0 "register_operand" "")
3110 (match_operand:QI 1 "address_operand" ""))
3111 (clobber (reg:CC 33))]
3112 "!TARGET_64BIT && reload_completed
3113 && preferred_la_operand_p (operands[1], 0)"
3114 [(set (match_dup 0) (match_dup 1))])
3116 (define_insn "*addsi3_imm_cc"
3118 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3119 (match_operand:SI 2 "const_int_operand" "K"))
3121 (set (match_operand:SI 0 "register_operand" "=d")
3122 (plus:SI (match_dup 1) (match_dup 2)))]
3123 "s390_match_ccmode (insn, CCAmode)
3124 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3126 [(set_attr "op_type" "RI")])
3128 (define_insn "*addsi3_carry1_cc"
3130 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3131 (match_operand:SI 2 "general_operand" "d,m"))
3133 (set (match_operand:SI 0 "register_operand" "=d,d")
3134 (plus:SI (match_dup 1) (match_dup 2)))]
3135 "s390_match_ccmode (insn, CCL1mode)"
3139 [(set_attr "op_type" "RR,RX")])
3141 (define_insn "*addsi3_carry1_cconly"
3143 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3144 (match_operand:SI 2 "general_operand" "d,m"))
3146 (clobber (match_scratch:SI 0 "=d,d"))]
3147 "s390_match_ccmode (insn, CCL1mode)"
3151 [(set_attr "op_type" "RR,RX")])
3153 (define_insn "*addsi3_carry2_cc"
3155 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3156 (match_operand:SI 2 "general_operand" "d,m"))
3158 (set (match_operand:SI 0 "register_operand" "=d,d")
3159 (plus:SI (match_dup 1) (match_dup 2)))]
3160 "s390_match_ccmode (insn, CCL1mode)"
3164 [(set_attr "op_type" "RR,RX")])
3166 (define_insn "*addsi3_carry2_cconly"
3168 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3169 (match_operand:SI 2 "general_operand" "d,m"))
3171 (clobber (match_scratch:SI 0 "=d,d"))]
3172 "s390_match_ccmode (insn, CCL1mode)"
3176 [(set_attr "op_type" "RR,RX")])
3178 (define_insn "*addsi3_cc"
3180 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3181 (match_operand:SI 2 "general_operand" "d,m"))
3183 (set (match_operand:SI 0 "register_operand" "=d,d")
3184 (plus:SI (match_dup 1) (match_dup 2)))]
3185 "s390_match_ccmode (insn, CCLmode)"
3189 [(set_attr "op_type" "RR,RX")])
3191 (define_insn "*addsi3_cconly"
3193 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3194 (match_operand:SI 2 "general_operand" "d,m"))
3196 (clobber (match_scratch:SI 0 "=d,d"))]
3197 "s390_match_ccmode (insn, CCLmode)"
3201 [(set_attr "op_type" "RR,RX")])
3203 (define_insn "*addsi3_cconly2"
3205 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3206 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3207 (clobber (match_scratch:SI 0 "=d,d"))]
3208 "s390_match_ccmode(insn, CCLmode)"
3212 [(set_attr "op_type" "RR,RX")])
3214 (define_insn "*addsi3_sign"
3215 [(set (match_operand:SI 0 "register_operand" "=d")
3216 (plus:SI (match_operand:SI 1 "register_operand" "0")
3217 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3218 (clobber (reg:CC 33))]
3221 [(set_attr "op_type" "RX")])
3223 (define_insn "*addsi3_sub"
3224 [(set (match_operand:SI 0 "register_operand" "=d")
3225 (plus:SI (match_operand:SI 1 "register_operand" "0")
3226 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3227 (clobber (reg:CC 33))]
3230 [(set_attr "op_type" "RX")])
3232 (define_insn "addsi3"
3233 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3234 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3235 (match_operand:SI 2 "general_operand" "d,K,m")))
3236 (clobber (reg:CC 33))]
3242 [(set_attr "op_type" "RR,RI,RX")])
3244 (define_insn "*la_31"
3245 [(set (match_operand:SI 0 "register_operand" "=d")
3246 (match_operand:QI 1 "address_operand" "p"))]
3247 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3249 [(set_attr "op_type" "RX")
3250 (set_attr "type" "la")])
3252 (define_insn "*la_31_and"
3253 [(set (match_operand:SI 0 "register_operand" "=d")
3254 (and:SI (match_operand:QI 1 "address_operand" "p")
3255 (const_int 2147483647)))]
3258 [(set_attr "op_type" "RX")
3259 (set_attr "type" "la")])
3261 (define_insn_and_split "*la_31_and_cc"
3262 [(set (match_operand:SI 0 "register_operand" "=d")
3263 (and:SI (match_operand:QI 1 "address_operand" "p")
3264 (const_int 2147483647)))
3265 (clobber (reg:CC 33))]
3268 "&& reload_completed"
3270 (and:SI (match_dup 1) (const_int 2147483647)))]
3272 [(set_attr "op_type" "RX")
3273 (set_attr "type" "la")])
3275 (define_insn "force_la_31"
3276 [(set (match_operand:SI 0 "register_operand" "=d")
3277 (match_operand:QI 1 "address_operand" "p"))
3278 (use (const_int 0))]
3281 [(set_attr "op_type" "RX")
3282 (set_attr "type" "la")])
3284 (define_expand "reload_insi"
3285 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3286 (match_operand:SI 1 "s390_plus_operand" "")
3287 (match_operand:SI 2 "register_operand" "=&a")])]
3291 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3297 ; adddf3 instruction pattern(s).
3300 (define_expand "adddf3"
3302 [(set (match_operand:DF 0 "register_operand" "=f,f")
3303 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3304 (match_operand:DF 2 "general_operand" "f,m")))
3305 (clobber (reg:CC 33))])]
3309 (define_insn "*adddf3"
3310 [(set (match_operand:DF 0 "register_operand" "=f,f")
3311 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3312 (match_operand:DF 2 "general_operand" "f,m")))
3313 (clobber (reg:CC 33))]
3314 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3318 [(set_attr "op_type" "RRE,RXE")
3319 (set_attr "type" "fsimpd,fsimpd")])
3321 (define_insn "*adddf3_ibm"
3322 [(set (match_operand:DF 0 "register_operand" "=f,f")
3323 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3324 (match_operand:DF 2 "general_operand" "f,m")))
3325 (clobber (reg:CC 33))]
3326 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3330 [(set_attr "op_type" "RR,RX")
3331 (set_attr "type" "fsimpd,fsimpd")])
3334 ; addsf3 instruction pattern(s).
3337 (define_expand "addsf3"
3339 [(set (match_operand:SF 0 "register_operand" "=f,f")
3340 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3341 (match_operand:SF 2 "general_operand" "f,m")))
3342 (clobber (reg:CC 33))])]
3346 (define_insn "*addsf3"
3347 [(set (match_operand:SF 0 "register_operand" "=f,f")
3348 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3349 (match_operand:SF 2 "general_operand" "f,m")))
3350 (clobber (reg:CC 33))]
3351 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3355 [(set_attr "op_type" "RRE,RXE")
3356 (set_attr "type" "fsimps,fsimps")])
3358 (define_insn "*addsf3"
3359 [(set (match_operand:SF 0 "register_operand" "=f,f")
3360 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3361 (match_operand:SF 2 "general_operand" "f,m")))
3362 (clobber (reg:CC 33))]
3363 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3367 [(set_attr "op_type" "RR,RX")
3368 (set_attr "type" "fsimps,fsimps")])
3372 ;;- Subtract instructions.
3376 ; subdi3 instruction pattern(s).
3379 (define_insn "*subdi3_sign"
3380 [(set (match_operand:DI 0 "register_operand" "=d,d")
3381 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3382 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3383 (clobber (reg:CC 33))]
3388 [(set_attr "op_type" "RRE,RXE")])
3390 (define_insn "*subdi3_zero_cc"
3392 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3393 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3395 (set (match_operand:DI 0 "register_operand" "=d,d")
3396 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3397 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3401 [(set_attr "op_type" "RRE,RXE")])
3403 (define_insn "*subdi3_zero_cconly"
3405 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3406 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3408 (clobber (match_scratch:DI 0 "=d,d"))]
3409 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3413 [(set_attr "op_type" "RRE,RXE")])
3415 (define_insn "*subdi3_zero"
3416 [(set (match_operand:DI 0 "register_operand" "=d,d")
3417 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3418 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3419 (clobber (reg:CC 33))]
3424 [(set_attr "op_type" "RRE,RXE")])
3426 (define_insn "*subdi3_cc"
3428 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3429 (match_operand:DI 2 "general_operand" "d,m"))
3431 (set (match_operand:DI 0 "register_operand" "=d,d")
3432 (minus:DI (match_dup 1) (match_dup 2)))]
3433 "s390_match_ccmode (insn, CCLmode)"
3437 [(set_attr "op_type" "RRE,RXE")])
3439 (define_insn "*subdi3_cconly"
3441 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3442 (match_operand:DI 2 "general_operand" "d,m"))
3444 (clobber (match_scratch:DI 0 "=d,d"))]
3445 "s390_match_ccmode (insn, CCLmode)"
3449 [(set_attr "op_type" "RRE,RXE")])
3451 (define_insn "*subdi3_64"
3452 [(set (match_operand:DI 0 "register_operand" "=d,d")
3453 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3454 (match_operand:DI 2 "general_operand" "d,m") ) )
3455 (clobber (reg:CC 33))]
3460 [(set_attr "op_type" "RRE,RRE")])
3462 (define_insn_and_split "*subdi3_31"
3463 [(set (match_operand:DI 0 "register_operand" "=&d")
3464 (minus:DI (match_operand:DI 1 "register_operand" "0")
3465 (match_operand:DI 2 "general_operand" "dm") ) )
3466 (clobber (reg:CC 33))]
3469 "&& reload_completed"
3471 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3472 (clobber (reg:CC 33))])
3475 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3477 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3479 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3481 (label_ref (match_dup 9))))
3483 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3484 (clobber (reg:CC 33))])
3486 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3487 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3488 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3489 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3490 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3491 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3492 operands[9] = gen_label_rtx ();"
3493 [(set_attr "op_type" "NN")
3494 (set_attr "type" "o3")])
3496 (define_expand "subdi3"
3498 [(set (match_operand:DI 0 "register_operand" "")
3499 (minus:DI (match_operand:DI 1 "register_operand" "")
3500 (match_operand:DI 2 "general_operand" "")))
3501 (clobber (reg:CC 33))])]
3506 ; subsi3 instruction pattern(s).
3509 (define_insn "*subsi3_borrow_cc"
3511 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3512 (match_operand:SI 2 "general_operand" "d,m"))
3514 (set (match_operand:SI 0 "register_operand" "=d,d")
3515 (minus:SI (match_dup 1) (match_dup 2)))]
3516 "s390_match_ccmode(insn, CCL2mode)"
3520 [(set_attr "op_type" "RR,RX")])
3522 (define_insn "*subsi3_borrow_cconly"
3524 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3525 (match_operand:SI 2 "general_operand" "d,m"))
3527 (clobber (match_scratch:SI 0 "=d,d"))]
3528 "s390_match_ccmode(insn, CCL2mode)"
3532 [(set_attr "op_type" "RR,RX")])
3534 (define_insn "*subsi3_cc"
3536 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3537 (match_operand:SI 2 "general_operand" "d,m"))
3539 (set (match_operand:SI 0 "register_operand" "=d,d")
3540 (minus:SI (match_dup 1) (match_dup 2)))]
3541 "s390_match_ccmode(insn, CCLmode)"
3545 [(set_attr "op_type" "RR,RX")])
3547 (define_insn "*subsi3_cconly"
3549 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3550 (match_operand:SI 2 "general_operand" "d,m"))
3552 (clobber (match_scratch:SI 0 "=d,d"))]
3553 "s390_match_ccmode(insn, CCLmode)"
3557 [(set_attr "op_type" "RR,RX")])
3559 (define_insn "*subsi3_sign"
3560 [(set (match_operand:SI 0 "register_operand" "=d")
3561 (minus:SI (match_operand:SI 1 "register_operand" "0")
3562 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3563 (clobber (reg:CC 33))]
3566 [(set_attr "op_type" "RX")])
3568 (define_insn "*subsi3_sub"
3569 [(set (match_operand:SI 0 "register_operand" "=d")
3570 (minus:SI (match_operand:SI 1 "register_operand" "0")
3571 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3572 (clobber (reg:CC 33))]
3575 [(set_attr "op_type" "RX")])
3577 (define_insn "subsi3"
3578 [(set (match_operand:SI 0 "register_operand" "=d,d")
3579 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3580 (match_operand:SI 2 "general_operand" "d,m")))
3581 (clobber (reg:CC 33))]
3586 [(set_attr "op_type" "RR,RX")])
3590 ; subdf3 instruction pattern(s).
3593 (define_expand "subdf3"
3595 [(set (match_operand:DF 0 "register_operand" "=f,f")
3596 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3597 (match_operand:DF 2 "general_operand" "f,m")))
3598 (clobber (reg:CC 33))])]
3602 (define_insn "*subdf3"
3603 [(set (match_operand:DF 0 "register_operand" "=f,f")
3604 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3605 (match_operand:DF 2 "general_operand" "f,m")))
3606 (clobber (reg:CC 33))]
3607 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3611 [(set_attr "op_type" "RRE,RXE")
3612 (set_attr "type" "fsimpd,fsimpd")])
3614 (define_insn "*subdf3_ibm"
3615 [(set (match_operand:DF 0 "register_operand" "=f,f")
3616 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3617 (match_operand:DF 2 "general_operand" "f,m")))
3618 (clobber (reg:CC 33))]
3619 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3623 [(set_attr "op_type" "RR,RX")
3624 (set_attr "type" "fsimpd,fsimpd")])
3627 ; subsf3 instruction pattern(s).
3630 (define_expand "subsf3"
3632 [(set (match_operand:SF 0 "register_operand" "=f,f")
3633 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3634 (match_operand:SF 2 "general_operand" "f,m")))
3635 (clobber (reg:CC 33))])]
3639 (define_insn "*subsf3"
3640 [(set (match_operand:SF 0 "register_operand" "=f,f")
3641 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3642 (match_operand:SF 2 "general_operand" "f,m")))
3643 (clobber (reg:CC 33))]
3644 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3648 [(set_attr "op_type" "RRE,RXE")
3649 (set_attr "type" "fsimps,fsimps")])
3651 (define_insn "*subsf3_ibm"
3652 [(set (match_operand:SF 0 "register_operand" "=f,f")
3653 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3654 (match_operand:SF 2 "general_operand" "f,m")))
3655 (clobber (reg:CC 33))]
3656 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3660 [(set_attr "op_type" "RR,RX")
3661 (set_attr "type" "fsimps,fsimps")])
3665 ;;- Multiply instructions.
3669 ; muldi3 instruction pattern(s).
3672 (define_insn "*muldi3_sign"
3673 [(set (match_operand:DI 0 "register_operand" "=d,d")
3674 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3675 (match_operand:DI 1 "register_operand" "0,0")))]
3680 [(set_attr "op_type" "RRE,RXE")
3681 (set_attr "type" "imul")])
3684 (define_insn "muldi3"
3685 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3686 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3687 (match_operand:DI 2 "general_operand" "d,K,m")))]
3693 [(set_attr "op_type" "RRE,RI,RXE")
3694 (set_attr "type" "imul")])
3697 ; mulsi3 instruction pattern(s).
3700 (define_insn "mulsi3"
3701 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3702 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3703 (match_operand:SI 2 "general_operand" "d,K,m")))]
3709 [(set_attr "op_type" "RRE,RI,RX")
3710 (set_attr "type" "imul")])
3713 ; mulsidi3 instruction pattern(s).
3716 (define_expand "mulsidi3"
3717 [(set (match_operand:DI 0 "register_operand" "")
3718 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3719 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3725 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3726 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3729 gen_rtx_EXPR_LIST (REG_EQUAL,
3730 gen_rtx_MULT (DImode,
3731 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3732 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3737 (define_insn "mulsi_6432"
3738 [(set (match_operand:DI 0 "register_operand" "=d,d")
3739 (mult:DI (sign_extend:DI
3740 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3742 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3747 [(set_attr "op_type" "RR,RX")
3748 (set_attr "type" "imul")])
3751 ; muldf3 instruction pattern(s).
3754 (define_expand "muldf3"
3756 [(set (match_operand:DF 0 "register_operand" "=f,f")
3757 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3758 (match_operand:DF 2 "general_operand" "f,m")))
3759 (clobber (reg:CC 33))])]
3763 (define_insn "*muldf3"
3764 [(set (match_operand:DF 0 "register_operand" "=f,f")
3765 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3766 (match_operand:DF 2 "general_operand" "f,m")))
3767 (clobber (reg:CC 33))]
3768 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3772 [(set_attr "op_type" "RRE,RXE")
3773 (set_attr "type" "fmuld")])
3775 (define_insn "*muldf3_ibm"
3776 [(set (match_operand:DF 0 "register_operand" "=f,f")
3777 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3778 (match_operand:DF 2 "general_operand" "f,m")))
3779 (clobber (reg:CC 33))]
3780 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3784 [(set_attr "op_type" "RR,RX")
3785 (set_attr "type" "fmuld")])
3788 ; mulsf3 instruction pattern(s).
3791 (define_expand "mulsf3"
3793 [(set (match_operand:SF 0 "register_operand" "=f,f")
3794 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3795 (match_operand:SF 2 "general_operand" "f,m")))
3796 (clobber (reg:CC 33))])]
3800 (define_insn "*mulsf3"
3801 [(set (match_operand:SF 0 "register_operand" "=f,f")
3802 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3803 (match_operand:SF 2 "general_operand" "f,m")))
3804 (clobber (reg:CC 33))]
3805 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3809 [(set_attr "op_type" "RRE,RXE")
3810 (set_attr "type" "fmuls")])
3812 (define_insn "*mulsf3_ibm"
3813 [(set (match_operand:SF 0 "register_operand" "=f,f")
3814 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3815 (match_operand:SF 2 "general_operand" "f,m")))
3816 (clobber (reg:CC 33))]
3817 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3821 [(set_attr "op_type" "RR,RX")
3822 (set_attr "type" "fmuls")])
3826 ;;- Divide and modulo instructions.
3830 ; divmoddi4 instruction pattern(s).
3833 (define_expand "divmoddi4"
3834 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3835 (div:DI (match_operand:DI 1 "general_operand" "")
3836 (match_operand:DI 2 "general_operand" "")))
3837 (set (match_operand:DI 3 "general_operand" "")
3838 (mod:DI (match_dup 1) (match_dup 2)))])
3839 (clobber (match_dup 4))]
3843 rtx insn, div_equal, mod_equal, equal;
3845 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3846 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3847 equal = gen_rtx_IOR (TImode,
3848 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3849 gen_rtx_ASHIFT (TImode,
3850 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3853 operands[4] = gen_reg_rtx(TImode);
3854 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3855 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3856 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3857 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3859 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3861 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3863 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3865 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3867 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3872 (define_insn "divmodtidi3"
3873 [(set (match_operand:TI 0 "register_operand" "=d,d")
3876 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3877 (match_operand:DI 2 "general_operand" "d,m")))
3880 (mod:DI (truncate:DI (match_dup 1))
3887 [(set_attr "op_type" "RRE,RXE")
3888 (set_attr "type" "idiv")])
3890 (define_insn "divmodtisi3"
3891 [(set (match_operand:TI 0 "register_operand" "=d,d")
3894 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3895 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3898 (mod:DI (truncate:DI (match_dup 1))
3899 (sign_extend:DI (match_dup 2))))
3905 [(set_attr "op_type" "RRE,RXE")
3906 (set_attr "type" "idiv")])
3909 ; udivmoddi4 instruction pattern(s).
3912 (define_expand "udivmoddi4"
3913 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3914 (udiv:DI (match_operand:DI 1 "general_operand" "")
3915 (match_operand:DI 2 "nonimmediate_operand" "")))
3916 (set (match_operand:DI 3 "general_operand" "")
3917 (umod:DI (match_dup 1) (match_dup 2)))])
3918 (clobber (match_dup 4))]
3922 rtx insn, div_equal, mod_equal, equal;
3924 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3925 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3926 equal = gen_rtx_IOR (TImode,
3927 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3928 gen_rtx_ASHIFT (TImode,
3929 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3932 operands[4] = gen_reg_rtx(TImode);
3933 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3934 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3935 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3936 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3938 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3940 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3942 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3944 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3946 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3951 (define_insn "udivmodtidi3"
3952 [(set (match_operand:TI 0 "register_operand" "=d,d")
3953 (ior:TI (zero_extend:TI
3955 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3957 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3961 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3967 [(set_attr "op_type" "RRE,RXE")
3968 (set_attr "type" "idiv")])
3971 ; divmodsi4 instruction pattern(s).
3974 (define_expand "divmodsi4"
3975 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3976 (div:SI (match_operand:SI 1 "general_operand" "")
3977 (match_operand:SI 2 "nonimmediate_operand" "")))
3978 (set (match_operand:SI 3 "general_operand" "")
3979 (mod:SI (match_dup 1) (match_dup 2)))])
3980 (clobber (match_dup 4))]
3984 rtx insn, div_equal, mod_equal, equal;
3986 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3987 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3988 equal = gen_rtx_IOR (DImode,
3989 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3990 gen_rtx_ASHIFT (DImode,
3991 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3994 operands[4] = gen_reg_rtx(DImode);
3995 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3996 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3998 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4000 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4002 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4004 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4006 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4011 (define_insn "divmoddisi3"
4012 [(set (match_operand:DI 0 "register_operand" "=d,d")
4013 (ior:DI (zero_extend:DI
4015 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4017 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4021 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4027 [(set_attr "op_type" "RR,RX")
4028 (set_attr "type" "idiv")])
4031 ; udivsi3 and umodsi3 instruction pattern(s).
4035 (define_expand "udivsi3"
4036 [(set (match_operand:SI 0 "register_operand" "=d")
4037 (udiv:SI (match_operand:SI 1 "general_operand" "")
4038 (match_operand:SI 2 "general_operand" "")))
4039 (clobber (match_dup 3))]
4043 rtx insn, udiv_equal, umod_equal, equal;
4045 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4046 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4047 equal = gen_rtx_IOR (DImode,
4048 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4049 gen_rtx_ASHIFT (DImode,
4050 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4053 operands[3] = gen_reg_rtx (DImode);
4055 if (CONSTANT_P (operands[2]))
4057 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4059 rtx label1 = gen_label_rtx ();
4061 operands[1] = make_safe_from (operands[1], operands[0]);
4062 emit_move_insn (operands[0], const0_rtx);
4063 emit_insn (gen_cmpsi (operands[1], operands[2]));
4064 emit_jump_insn (gen_bltu (label1));
4065 emit_move_insn (operands[0], const1_rtx);
4066 emit_label (label1);
4070 operands[2] = force_reg (SImode, operands[2]);
4071 operands[2] = make_safe_from (operands[2], operands[0]);
4073 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4074 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4077 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4079 insn = emit_move_insn (operands[0],
4080 gen_lowpart (SImode, operands[3]));
4082 gen_rtx_EXPR_LIST (REG_EQUAL,
4083 udiv_equal, REG_NOTES (insn));
4088 rtx label1 = gen_label_rtx ();
4089 rtx label2 = gen_label_rtx ();
4090 rtx label3 = gen_label_rtx ();
4092 operands[1] = force_reg (SImode, operands[1]);
4093 operands[1] = make_safe_from (operands[1], operands[0]);
4094 operands[2] = force_reg (SImode, operands[2]);
4095 operands[2] = make_safe_from (operands[2], operands[0]);
4097 emit_move_insn (operands[0], const0_rtx);
4098 emit_insn (gen_cmpsi (operands[2], operands[1]));
4099 emit_jump_insn (gen_bgtu (label3));
4100 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4101 emit_jump_insn (gen_blt (label2));
4102 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4103 emit_jump_insn (gen_beq (label1));
4104 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4105 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4108 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4110 insn = emit_move_insn (operands[0],
4111 gen_lowpart (SImode, operands[3]));
4113 gen_rtx_EXPR_LIST (REG_EQUAL,
4114 udiv_equal, REG_NOTES (insn));
4116 emit_label (label1);
4117 emit_move_insn (operands[0], operands[1]);
4119 emit_label (label2);
4120 emit_move_insn (operands[0], const1_rtx);
4121 emit_label (label3);
4123 emit_move_insn (operands[0], operands[0]);
4127 (define_expand "umodsi3"
4128 [(set (match_operand:SI 0 "register_operand" "=d")
4129 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4130 (match_operand:SI 2 "nonimmediate_operand" "")))
4131 (clobber (match_dup 3))]
4135 rtx insn, udiv_equal, umod_equal, equal;
4137 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4138 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4139 equal = gen_rtx_IOR (DImode,
4140 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4141 gen_rtx_ASHIFT (DImode,
4142 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4145 operands[3] = gen_reg_rtx (DImode);
4147 if (CONSTANT_P (operands[2]))
4149 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4151 rtx label1 = gen_label_rtx ();
4153 operands[1] = make_safe_from (operands[1], operands[0]);
4154 emit_move_insn (operands[0], operands[1]);
4155 emit_insn (gen_cmpsi (operands[0], operands[2]));
4156 emit_jump_insn (gen_bltu (label1));
4157 emit_insn (gen_abssi2 (operands[0], operands[2]));
4158 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4159 emit_label (label1);
4163 operands[2] = force_reg (SImode, operands[2]);
4164 operands[2] = make_safe_from (operands[2], operands[0]);
4166 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4167 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4170 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4172 insn = emit_move_insn (operands[0],
4173 gen_highpart (SImode, operands[3]));
4175 gen_rtx_EXPR_LIST (REG_EQUAL,
4176 umod_equal, REG_NOTES (insn));
4181 rtx label1 = gen_label_rtx ();
4182 rtx label2 = gen_label_rtx ();
4183 rtx label3 = gen_label_rtx ();
4185 operands[1] = force_reg (SImode, operands[1]);
4186 operands[1] = make_safe_from (operands[1], operands[0]);
4187 operands[2] = force_reg (SImode, operands[2]);
4188 operands[2] = make_safe_from (operands[2], operands[0]);
4190 emit_move_insn(operands[0], operands[1]);
4191 emit_insn (gen_cmpsi (operands[2], operands[1]));
4192 emit_jump_insn (gen_bgtu (label3));
4193 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4194 emit_jump_insn (gen_blt (label2));
4195 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4196 emit_jump_insn (gen_beq (label1));
4197 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4198 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4201 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4203 insn = emit_move_insn (operands[0],
4204 gen_highpart (SImode, operands[3]));
4206 gen_rtx_EXPR_LIST (REG_EQUAL,
4207 umod_equal, REG_NOTES (insn));
4209 emit_label (label1);
4210 emit_move_insn (operands[0], const0_rtx);
4212 emit_label (label2);
4213 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4214 emit_label (label3);
4220 ; divdf3 instruction pattern(s).
4223 (define_expand "divdf3"
4225 [(set (match_operand:DF 0 "register_operand" "=f,f")
4226 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4227 (match_operand:DF 2 "general_operand" "f,m")))
4228 (clobber (reg:CC 33))])]
4232 (define_insn "*divdf3"
4233 [(set (match_operand:DF 0 "register_operand" "=f,f")
4234 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4235 (match_operand:DF 2 "general_operand" "f,m")))
4236 (clobber (reg:CC 33))]
4237 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4241 [(set_attr "op_type" "RRE,RXE")
4242 (set_attr "type" "fdivd")])
4244 (define_insn "*divdf3_ibm"
4245 [(set (match_operand:DF 0 "register_operand" "=f,f")
4246 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4247 (match_operand:DF 2 "general_operand" "f,m")))
4248 (clobber (reg:CC 33))]
4249 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4253 [(set_attr "op_type" "RR,RX")
4254 (set_attr "type" "fdivd")])
4257 ; divsf3 instruction pattern(s).
4260 (define_expand "divsf3"
4262 [(set (match_operand:SF 0 "register_operand" "=f,f")
4263 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4264 (match_operand:SF 2 "general_operand" "f,m")))
4265 (clobber (reg:CC 33))])]
4269 (define_insn "*divsf3"
4270 [(set (match_operand:SF 0 "register_operand" "=f,f")
4271 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4272 (match_operand:SF 2 "general_operand" "f,m")))
4273 (clobber (reg:CC 33))]
4274 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4278 [(set_attr "op_type" "RRE,RXE")
4279 (set_attr "type" "fdivs")])
4281 (define_insn "*divsf3"
4282 [(set (match_operand:SF 0 "register_operand" "=f,f")
4283 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4284 (match_operand:SF 2 "general_operand" "f,m")))
4285 (clobber (reg:CC 33))]
4286 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4290 [(set_attr "op_type" "RR,RX")
4291 (set_attr "type" "fdivs")])
4295 ;;- And instructions.
4299 ; anddi3 instruction pattern(s).
4302 (define_insn "*anddi3_cc"
4304 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4305 (match_operand:DI 2 "general_operand" "d,m"))
4307 (set (match_operand:DI 0 "register_operand" "=d,d")
4308 (and:DI (match_dup 1) (match_dup 2)))]
4309 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4313 [(set_attr "op_type" "RRE,RXE")])
4315 (define_insn "*anddi3_cconly"
4317 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4318 (match_operand:DI 2 "general_operand" "d,m"))
4320 (clobber (match_scratch:DI 0 "=d,d"))]
4321 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4325 [(set_attr "op_type" "RRE,RXE")])
4327 (define_insn "*anddi3_ni"
4328 [(set (match_operand:DI 0 "register_operand" "=d")
4329 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4330 (match_operand:DI 2 "immediate_operand" "n")))
4331 (clobber (reg:CC 33))]
4332 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4335 int part = s390_single_hi (operands[2], DImode, -1);
4336 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4340 case 0: return \"nihh\\t%0,%x2\";
4341 case 1: return \"nihl\\t%0,%x2\";
4342 case 2: return \"nilh\\t%0,%x2\";
4343 case 3: return \"nill\\t%0,%x2\";
4347 [(set_attr "op_type" "RI")])
4349 (define_insn "anddi3"
4350 [(set (match_operand:DI 0 "register_operand" "=d,d")
4351 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4352 (match_operand:DI 2 "general_operand" "d,m")))
4353 (clobber (reg:CC 33))]
4358 [(set_attr "op_type" "RRE,RXE")])
4360 (define_insn "*anddi3_ss"
4361 [(set (match_operand:DI 0 "s_operand" "=Q")
4362 (and:DI (match_dup 0)
4363 (match_operand:DI 1 "s_imm_operand" "Q")))
4364 (clobber (reg:CC 33))]
4366 "nc\\t%O0(8,%R0),%1"
4367 [(set_attr "op_type" "SS")])
4369 (define_insn "*anddi3_ss_inv"
4370 [(set (match_operand:DI 0 "s_operand" "=Q")
4371 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4373 (clobber (reg:CC 33))]
4375 "nc\\t%O0(8,%R0),%1"
4376 [(set_attr "op_type" "SS")])
4379 ; andsi3 instruction pattern(s).
4382 (define_insn "*andsi3_cc"
4384 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4385 (match_operand:SI 2 "general_operand" "d,m"))
4387 (set (match_operand:SI 0 "register_operand" "=d,d")
4388 (and:SI (match_dup 1) (match_dup 2)))]
4389 "s390_match_ccmode(insn, CCTmode)"
4393 [(set_attr "op_type" "RR,RX")])
4395 (define_insn "*andsi3_cconly"
4397 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4398 (match_operand:SI 2 "general_operand" "d,m"))
4400 (clobber (match_scratch:SI 0 "=d,d"))]
4401 "s390_match_ccmode(insn, CCTmode)"
4405 [(set_attr "op_type" "RR,RX")])
4407 (define_insn "*andsi3_ni"
4408 [(set (match_operand:SI 0 "register_operand" "=d")
4409 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4410 (match_operand:SI 2 "immediate_operand" "n")))
4411 (clobber (reg:CC 33))]
4412 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4415 int part = s390_single_hi (operands[2], SImode, -1);
4416 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4420 case 0: return \"nilh\\t%0,%x2\";
4421 case 1: return \"nill\\t%0,%x2\";
4425 [(set_attr "op_type" "RI")])
4427 (define_insn "andsi3"
4428 [(set (match_operand:SI 0 "register_operand" "=d,d")
4429 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4430 (match_operand:SI 2 "general_operand" "d,m")))
4431 (clobber (reg:CC 33))]
4436 [(set_attr "op_type" "RR,RX")])
4438 (define_insn "*andsi3_ss"
4439 [(set (match_operand:SI 0 "s_operand" "=Q")
4440 (and:SI (match_dup 0)
4441 (match_operand:SI 1 "s_imm_operand" "Q")))
4442 (clobber (reg:CC 33))]
4444 "nc\\t%O0(4,%R0),%1"
4445 [(set_attr "op_type" "SS")])
4447 (define_insn "*andsi3_ss_inv"
4448 [(set (match_operand:SI 0 "s_operand" "=Q")
4449 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4451 (clobber (reg:CC 33))]
4453 "nc\\t%O0(4,%R0),%1"
4454 [(set_attr "op_type" "SS")])
4457 ; andhi3 instruction pattern(s).
4460 (define_insn "*andhi3_ni"
4461 [(set (match_operand:HI 0 "register_operand" "=d,d")
4462 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4463 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4464 (clobber (reg:CC 33))]
4469 [(set_attr "op_type" "RR,RI")])
4471 (define_insn "andhi3"
4472 [(set (match_operand:HI 0 "register_operand" "=d")
4473 (and:HI (match_operand:HI 1 "register_operand" "%0")
4474 (match_operand:HI 2 "nonmemory_operand" "d")))
4475 (clobber (reg:CC 33))]
4478 [(set_attr "op_type" "RR")])
4480 (define_insn "*andhi3_ss"
4481 [(set (match_operand:HI 0 "s_operand" "=Q")
4482 (and:HI (match_dup 0)
4483 (match_operand:HI 1 "s_imm_operand" "Q")))
4484 (clobber (reg:CC 33))]
4486 "nc\\t%O0(2,%R0),%1"
4487 [(set_attr "op_type" "SS")])
4489 (define_insn "*andhi3_ss_inv"
4490 [(set (match_operand:HI 0 "s_operand" "=Q")
4491 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4493 (clobber (reg:CC 33))]
4495 "nc\\t%O0(2,%R0),%1"
4496 [(set_attr "op_type" "SS")])
4499 ; andqi3 instruction pattern(s).
4502 (define_insn "*andqi3_ni"
4503 [(set (match_operand:QI 0 "register_operand" "=d,d")
4504 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4505 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4506 (clobber (reg:CC 33))]
4511 [(set_attr "op_type" "RR,RI")])
4513 (define_insn "andqi3"
4514 [(set (match_operand:QI 0 "register_operand" "=d")
4515 (and:QI (match_operand:QI 1 "register_operand" "%0")
4516 (match_operand:QI 2 "nonmemory_operand" "d")))
4517 (clobber (reg:CC 33))]
4520 [(set_attr "op_type" "RR")])
4522 (define_insn "*andqi3_ss"
4523 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4524 (and:QI (match_dup 0)
4525 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4526 (clobber (reg:CC 33))]
4531 [(set_attr "op_type" "SI,SS")])
4533 (define_insn "*andqi3_ss_inv"
4534 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4535 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4537 (clobber (reg:CC 33))]
4542 [(set_attr "op_type" "SI,SS")])
4546 ;;- Bit set (inclusive or) instructions.
4550 ; iordi3 instruction pattern(s).
4553 (define_insn "*iordi3_cc"
4555 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4556 (match_operand:DI 2 "general_operand" "d,m"))
4558 (set (match_operand:DI 0 "register_operand" "=d,d")
4559 (ior:DI (match_dup 1) (match_dup 2)))]
4560 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4564 [(set_attr "op_type" "RRE,RXE")])
4566 (define_insn "*iordi3_cconly"
4568 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4569 (match_operand:DI 2 "general_operand" "d,m"))
4571 (clobber (match_scratch:DI 0 "=d,d"))]
4572 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4576 [(set_attr "op_type" "RRE,RXE")])
4578 (define_insn "*iordi3_oi"
4579 [(set (match_operand:DI 0 "register_operand" "=d")
4580 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4581 (match_operand:DI 2 "immediate_operand" "n")))
4582 (clobber (reg:CC 33))]
4583 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4586 int part = s390_single_hi (operands[2], DImode, 0);
4587 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4591 case 0: return \"oihh\\t%0,%x2\";
4592 case 1: return \"oihl\\t%0,%x2\";
4593 case 2: return \"oilh\\t%0,%x2\";
4594 case 3: return \"oill\\t%0,%x2\";
4598 [(set_attr "op_type" "RI")])
4600 (define_insn "iordi3"
4601 [(set (match_operand:DI 0 "register_operand" "=d,d")
4602 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4603 (match_operand:DI 2 "general_operand" "d,m")))
4604 (clobber (reg:CC 33))]
4609 [(set_attr "op_type" "RRE,RXE")])
4611 (define_insn "*iordi3_ss"
4612 [(set (match_operand:DI 0 "s_operand" "=Q")
4613 (ior:DI (match_dup 0)
4614 (match_operand:DI 1 "s_imm_operand" "Q")))
4615 (clobber (reg:CC 33))]
4617 "oc\\t%O0(8,%R0),%1"
4618 [(set_attr "op_type" "SS")])
4620 (define_insn "*iordi3_ss_inv"
4621 [(set (match_operand:DI 0 "s_operand" "=Q")
4622 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4624 (clobber (reg:CC 33))]
4626 "oc\\t%O0(8,%R0),%1"
4627 [(set_attr "op_type" "SS")])
4630 ; iorsi3 instruction pattern(s).
4633 (define_insn "*iorsi3_cc"
4635 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4636 (match_operand:SI 2 "general_operand" "d,m"))
4638 (set (match_operand:SI 0 "register_operand" "=d,d")
4639 (ior:SI (match_dup 1) (match_dup 2)))]
4640 "s390_match_ccmode(insn, CCTmode)"
4644 [(set_attr "op_type" "RR,RX")])
4646 (define_insn "*iorsi3_cconly"
4648 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4649 (match_operand:SI 2 "general_operand" "d,m"))
4651 (clobber (match_scratch:SI 0 "=d,d"))]
4652 "s390_match_ccmode(insn, CCTmode)"
4656 [(set_attr "op_type" "RR,RX")])
4658 (define_insn "*iorsi3_oi"
4659 [(set (match_operand:SI 0 "register_operand" "=d")
4660 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4661 (match_operand:SI 2 "immediate_operand" "n")))
4662 (clobber (reg:CC 33))]
4663 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4666 int part = s390_single_hi (operands[2], SImode, 0);
4667 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4671 case 0: return \"oilh\\t%0,%x2\";
4672 case 1: return \"oill\\t%0,%x2\";
4676 [(set_attr "op_type" "RI")])
4678 (define_insn "iorsi3"
4679 [(set (match_operand:SI 0 "register_operand" "=d,d")
4680 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4681 (match_operand:SI 2 "general_operand" "d,m")))
4682 (clobber (reg:CC 33))]
4687 [(set_attr "op_type" "RR,RX")])
4689 (define_insn "*iorsi3_ss"
4690 [(set (match_operand:SI 0 "s_operand" "=Q")
4691 (ior:SI (match_dup 0)
4692 (match_operand:SI 1 "s_imm_operand" "Q")))
4693 (clobber (reg:CC 33))]
4695 "oc\\t%O0(4,%R0),%1"
4696 [(set_attr "op_type" "SS")])
4698 (define_insn "*iorsi3_ss_inv"
4699 [(set (match_operand:SI 0 "s_operand" "=Q")
4700 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4702 (clobber (reg:CC 33))]
4704 "oc\\t%O0(4,%R0),%1"
4705 [(set_attr "op_type" "SS")])
4708 ; iorhi3 instruction pattern(s).
4711 (define_insn "*iorhi3_oi"
4712 [(set (match_operand:HI 0 "register_operand" "=d,d")
4713 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4714 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4715 (clobber (reg:CC 33))]
4720 [(set_attr "op_type" "RR,RI")])
4722 (define_insn "iorhi3"
4723 [(set (match_operand:HI 0 "register_operand" "=d")
4724 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4725 (match_operand:HI 2 "nonmemory_operand" "d")))
4726 (clobber (reg:CC 33))]
4729 [(set_attr "op_type" "RR")])
4731 (define_insn "*iorhi3_ss"
4732 [(set (match_operand:HI 0 "s_operand" "=Q")
4733 (ior:HI (match_dup 0)
4734 (match_operand:HI 1 "s_imm_operand" "Q")))
4735 (clobber (reg:CC 33))]
4737 "oc\\t%O0(2,%R0),%1"
4738 [(set_attr "op_type" "SS")])
4740 (define_insn "*iorhi3_ss_inv"
4741 [(set (match_operand:HI 0 "s_operand" "=Q")
4742 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4744 (clobber (reg:CC 33))]
4746 "oc\\t%O0(2,%R0),%1"
4747 [(set_attr "op_type" "SS")])
4750 ; iorqi3 instruction pattern(s).
4753 (define_insn "*iorqi3_oi"
4754 [(set (match_operand:QI 0 "register_operand" "=d,d")
4755 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4756 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4757 (clobber (reg:CC 33))]
4762 [(set_attr "op_type" "RR,RI")])
4764 (define_insn "iorqi3"
4765 [(set (match_operand:QI 0 "register_operand" "=d")
4766 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4767 (match_operand:QI 2 "nonmemory_operand" "d")))
4768 (clobber (reg:CC 33))]
4771 [(set_attr "op_type" "RR")])
4773 (define_insn "*iorqi3_ss"
4774 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4775 (ior:QI (match_dup 0)
4776 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4777 (clobber (reg:CC 33))]
4782 [(set_attr "op_type" "SI,SS")])
4784 (define_insn "*iorqi3_ss_inv"
4785 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4786 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4788 (clobber (reg:CC 33))]
4793 [(set_attr "op_type" "SI,SS")])
4797 ;;- Xor instructions.
4801 ; xordi3 instruction pattern(s).
4804 (define_insn "*xordi3_cc"
4806 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4807 (match_operand:DI 2 "general_operand" "d,m"))
4809 (set (match_operand:DI 0 "register_operand" "=d,d")
4810 (xor:DI (match_dup 1) (match_dup 2)))]
4811 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4815 [(set_attr "op_type" "RRE,RXE")])
4817 (define_insn "*xordi3_cconly"
4819 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4820 (match_operand:DI 2 "general_operand" "d,m"))
4822 (clobber (match_scratch:DI 0 "=d,d"))]
4823 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4827 [(set_attr "op_type" "RRE,RXE")])
4829 (define_insn "xordi3"
4830 [(set (match_operand:DI 0 "register_operand" "=d,d")
4831 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4832 (match_operand:DI 2 "general_operand" "d,m")))
4833 (clobber (reg:CC 33))]
4838 [(set_attr "op_type" "RRE,RXE")])
4840 (define_insn "*xordi3_ss"
4841 [(set (match_operand:DI 0 "s_operand" "=Q")
4842 (xor:DI (match_dup 0)
4843 (match_operand:DI 1 "s_imm_operand" "Q")))
4844 (clobber (reg:CC 33))]
4846 "xc\\t%O0(8,%R0),%1"
4847 [(set_attr "op_type" "SS")])
4849 (define_insn "*xordi3_ss_inv"
4850 [(set (match_operand:DI 0 "s_operand" "=Q")
4851 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4853 (clobber (reg:CC 33))]
4855 "xc\\t%O0(8,%R0),%1"
4856 [(set_attr "op_type" "SS")])
4859 ; xorsi3 instruction pattern(s).
4862 (define_insn "*xorsi3_cc"
4864 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4865 (match_operand:SI 2 "general_operand" "d,m"))
4867 (set (match_operand:SI 0 "register_operand" "=d,d")
4868 (xor:SI (match_dup 1) (match_dup 2)))]
4869 "s390_match_ccmode(insn, CCTmode)"
4873 [(set_attr "op_type" "RR,RX")])
4875 (define_insn "*xorsi3_cconly"
4877 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4878 (match_operand:SI 2 "general_operand" "d,m"))
4880 (clobber (match_scratch:SI 0 "=d,d"))]
4881 "s390_match_ccmode(insn, CCTmode)"
4885 [(set_attr "op_type" "RR,RX")])
4887 (define_insn "xorsi3"
4888 [(set (match_operand:SI 0 "register_operand" "=d,d")
4889 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4890 (match_operand:SI 2 "general_operand" "d,m")))
4891 (clobber (reg:CC 33))]
4896 [(set_attr "op_type" "RR,RX")])
4898 (define_insn "*xorsi3_ss"
4899 [(set (match_operand:SI 0 "s_operand" "=Q")
4900 (xor:SI (match_dup 0)
4901 (match_operand:SI 1 "s_imm_operand" "Q")))
4902 (clobber (reg:CC 33))]
4904 "xc\\t%O0(4,%R0),%1"
4905 [(set_attr "op_type" "SS")])
4907 (define_insn "*xorsi3_ss_inv"
4908 [(set (match_operand:SI 0 "s_operand" "=Q")
4909 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4911 (clobber (reg:CC 33))]
4913 "xc\\t%O0(4,%R0),%1"
4914 [(set_attr "op_type" "SS")])
4917 ; xorhi3 instruction pattern(s).
4920 (define_insn "xorhi3"
4921 [(set (match_operand:HI 0 "register_operand" "=d")
4922 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4923 (match_operand:HI 2 "nonmemory_operand" "d")))
4924 (clobber (reg:CC 33))]
4927 [(set_attr "op_type" "RR")
4928 (set_attr "atype" "reg")])
4930 (define_insn "*xorhi3_ss"
4931 [(set (match_operand:HI 0 "s_operand" "=Q")
4932 (xor:HI (match_dup 0)
4933 (match_operand:HI 1 "s_imm_operand" "Q")))
4934 (clobber (reg:CC 33))]
4936 "xc\\t%O0(2,%R0),%1"
4937 [(set_attr "op_type" "SS")])
4939 (define_insn "*xorhi3_ss_inv"
4940 [(set (match_operand:HI 0 "s_operand" "=Q")
4941 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4943 (clobber (reg:CC 33))]
4945 "xc\\t%O0(2,%R0),%1"
4946 [(set_attr "op_type" "SS")])
4949 ; xorqi3 instruction pattern(s).
4952 (define_insn "xorqi3"
4953 [(set (match_operand:QI 0 "register_operand" "=d")
4954 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4955 (match_operand:QI 2 "nonmemory_operand" "d")))
4956 (clobber (reg:CC 33))]
4959 [(set_attr "op_type" "RR")])
4961 (define_insn "*xorqi3_ss"
4962 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4963 (xor:QI (match_dup 0)
4964 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4965 (clobber (reg:CC 33))]
4970 [(set_attr "op_type" "SI,SS")])
4972 (define_insn "*xorqi3_ss_inv"
4973 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4974 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4976 (clobber (reg:CC 33))]
4981 [(set_attr "op_type" "SI,SS")])
4985 ;;- Negate instructions.
4989 ; negdi2 instruction pattern(s).
4992 (define_expand "negdi2"
4994 [(set (match_operand:DI 0 "register_operand" "=d")
4995 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4996 (clobber (reg:CC 33))])]
5000 (define_insn "*negdi2_64"
5001 [(set (match_operand:DI 0 "register_operand" "=d")
5002 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5003 (clobber (reg:CC 33))]
5006 [(set_attr "op_type" "RR")])
5008 (define_insn "*negdi2_31"
5009 [(set (match_operand:DI 0 "register_operand" "=d")
5010 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5011 (clobber (reg:CC 33))]
5016 xop[0] = gen_label_rtx ();
5017 output_asm_insn (\"lcr\\t%0,%1\", operands);
5018 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5019 output_asm_insn (\"je\\t%l0\", xop);
5020 output_asm_insn (\"bctr\\t%0,0\", operands);
5021 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5022 CODE_LABEL_NUMBER (xop[0]));
5025 [(set_attr "op_type" "NN")
5026 (set_attr "type" "other")
5027 (set_attr "length" "10")])
5030 ; negsi2 instruction pattern(s).
5033 (define_insn "negsi2"
5034 [(set (match_operand:SI 0 "register_operand" "=d")
5035 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5036 (clobber (reg:CC 33))]
5039 [(set_attr "op_type" "RR")])
5042 ; negdf2 instruction pattern(s).
5045 (define_expand "negdf2"
5047 [(set (match_operand:DF 0 "register_operand" "=f")
5048 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5049 (clobber (reg:CC 33))])]
5053 (define_insn "*negdf2"
5054 [(set (match_operand:DF 0 "register_operand" "=f")
5055 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5056 (clobber (reg:CC 33))]
5057 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5059 [(set_attr "op_type" "RRE")
5060 (set_attr "type" "fsimpd")])
5062 (define_insn "*negdf2_ibm"
5063 [(set (match_operand:DF 0 "register_operand" "=f")
5064 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5065 (clobber (reg:CC 33))]
5066 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5068 [(set_attr "op_type" "RR")
5069 (set_attr "type" "fsimpd")])
5072 ; negsf2 instruction pattern(s).
5075 (define_expand "negsf2"
5077 [(set (match_operand:SF 0 "register_operand" "=f")
5078 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5079 (clobber (reg:CC 33))])]
5083 (define_insn "*negsf2"
5084 [(set (match_operand:SF 0 "register_operand" "=f")
5085 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5086 (clobber (reg:CC 33))]
5087 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5089 [(set_attr "op_type" "RRE")
5090 (set_attr "type" "fsimps")])
5092 (define_insn "*negsf2"
5093 [(set (match_operand:SF 0 "register_operand" "=f")
5094 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5095 (clobber (reg:CC 33))]
5096 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5098 [(set_attr "op_type" "RR")
5099 (set_attr "type" "fsimps")])
5103 ;;- Absolute value instructions.
5107 ; absdi2 instruction pattern(s).
5110 (define_insn "absdi2"
5111 [(set (match_operand:DI 0 "register_operand" "=d")
5112 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5113 (clobber (reg:CC 33))]
5116 [(set_attr "op_type" "RRE")])
5119 ; abssi2 instruction pattern(s).
5122 (define_insn "abssi2"
5123 [(set (match_operand:SI 0 "register_operand" "=d")
5124 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5125 (clobber (reg:CC 33))]
5128 [(set_attr "op_type" "RR")])
5131 ; absdf2 instruction pattern(s).
5134 (define_expand "absdf2"
5136 [(set (match_operand:DF 0 "register_operand" "=f")
5137 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5138 (clobber (reg:CC 33))])]
5142 (define_insn "*absdf2"
5143 [(set (match_operand:DF 0 "register_operand" "=f")
5144 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5145 (clobber (reg:CC 33))]
5146 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5148 [(set_attr "op_type" "RRE")
5149 (set_attr "type" "fsimpd")])
5151 (define_insn "*absdf2_ibm"
5152 [(set (match_operand:DF 0 "register_operand" "=f")
5153 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5154 (clobber (reg:CC 33))]
5155 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5157 [(set_attr "op_type" "RR")
5158 (set_attr "type" "fsimpd")])
5161 ; abssf2 instruction pattern(s).
5164 (define_expand "abssf2"
5166 [(set (match_operand:SF 0 "register_operand" "=f")
5167 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5168 (clobber (reg:CC 33))])]
5172 (define_insn "*abssf2"
5173 [(set (match_operand:SF 0 "register_operand" "=f")
5174 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5175 (clobber (reg:CC 33))]
5176 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5178 [(set_attr "op_type" "RRE")
5179 (set_attr "type" "fsimps")])
5181 (define_insn "*abssf2_ibm"
5182 [(set (match_operand:SF 0 "register_operand" "=f")
5183 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5184 (clobber (reg:CC 33))]
5185 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5187 [(set_attr "op_type" "RR")
5188 (set_attr "type" "fsimps")])
5191 ;;- Square root instructions.
5195 ; sqrtdf2 instruction pattern(s).
5198 (define_insn "sqrtdf2"
5199 [(set (match_operand:DF 0 "register_operand" "=f,f")
5200 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5201 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5205 [(set_attr "op_type" "RRE,RSE")
5206 (set_attr "type" "fsqrtd")])
5209 ; sqrtsf2 instruction pattern(s).
5212 (define_insn "sqrtsf2"
5213 [(set (match_operand:SF 0 "register_operand" "=f,f")
5214 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5215 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5219 [(set_attr "op_type" "RRE,RSE")
5220 (set_attr "type" "fsqrts")])
5223 ;;- One complement instructions.
5227 ; one_cmpldi2 instruction pattern(s).
5230 (define_expand "one_cmpldi2"
5232 [(set (match_operand:DI 0 "register_operand" "")
5233 (xor:DI (match_operand:DI 1 "register_operand" "")
5235 (clobber (reg:CC 33))])]
5240 ; one_cmplsi2 instruction pattern(s).
5243 (define_expand "one_cmplsi2"
5245 [(set (match_operand:SI 0 "register_operand" "")
5246 (xor:SI (match_operand:SI 1 "register_operand" "")
5248 (clobber (reg:CC 33))])]
5253 ; one_cmplhi2 instruction pattern(s).
5256 (define_expand "one_cmplhi2"
5258 [(set (match_operand:HI 0 "register_operand" "")
5259 (xor:HI (match_operand:HI 1 "register_operand" "")
5261 (clobber (reg:CC 33))])]
5266 ; one_cmplqi2 instruction pattern(s).
5269 (define_expand "one_cmplqi2"
5271 [(set (match_operand:QI 0 "register_operand" "")
5272 (xor:QI (match_operand:QI 1 "register_operand" "")
5274 (clobber (reg:CC 33))])]
5280 ;;- Rotate instructions.
5284 ; rotldi3 instruction pattern(s).
5287 (define_insn "rotldi3"
5288 [(set (match_operand:DI 0 "register_operand" "=d,d")
5289 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5290 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5295 [(set_attr "op_type" "RSE")
5296 (set_attr "atype" "reg")])
5299 ; rotlsi3 instruction pattern(s).
5302 (define_insn "rotlsi3"
5303 [(set (match_operand:SI 0 "register_operand" "=d,d")
5304 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5305 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5310 [(set_attr "op_type" "RSE")
5311 (set_attr "atype" "reg")])
5315 ;;- Arithmetic shift instructions.
5319 ; ashldi3 instruction pattern(s).
5322 (define_expand "ashldi3"
5323 [(set (match_operand:DI 0 "register_operand" "")
5324 (ashift:DI (match_operand:DI 1 "register_operand" "")
5325 (match_operand:SI 2 "nonmemory_operand" "")))]
5329 (define_insn "*ashldi3_31"
5330 [(set (match_operand:DI 0 "register_operand" "=d,d")
5331 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5332 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5337 [(set_attr "op_type" "RS")
5338 (set_attr "atype" "reg")])
5340 (define_insn "*ashldi3_64"
5341 [(set (match_operand:DI 0 "register_operand" "=d,d")
5342 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5343 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5348 [(set_attr "op_type" "RSE")
5349 (set_attr "atype" "reg")])
5352 ; ashrdi3 instruction pattern(s).
5355 (define_expand "ashrdi3"
5357 [(set (match_operand:DI 0 "register_operand" "")
5358 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5359 (match_operand:SI 2 "nonmemory_operand" "")))
5360 (clobber (reg:CC 33))])]
5364 (define_insn "*ashrdi3_cc_31"
5366 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5367 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5369 (set (match_operand:DI 0 "register_operand" "=d,d")
5370 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5371 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5375 [(set_attr "op_type" "RS")
5376 (set_attr "atype" "reg")])
5378 (define_insn "*ashrdi3_cconly_31"
5380 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5381 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5383 (clobber (match_scratch:DI 0 "=d,d"))]
5384 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5388 [(set_attr "op_type" "RS")
5389 (set_attr "atype" "reg")])
5391 (define_insn "*ashrdi3_31"
5392 [(set (match_operand:DI 0 "register_operand" "=d,d")
5393 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5394 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5395 (clobber (reg:CC 33))]
5400 [(set_attr "op_type" "RS")
5401 (set_attr "atype" "reg")])
5403 (define_insn "*ashrdi3_cc_64"
5405 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5406 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5408 (set (match_operand:DI 0 "register_operand" "=d,d")
5409 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5410 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5414 [(set_attr "op_type" "RSE")
5415 (set_attr "atype" "reg")])
5417 (define_insn "*ashrdi3_cconly_64"
5419 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5420 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5422 (clobber (match_scratch:DI 0 "=d,d"))]
5423 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5427 [(set_attr "op_type" "RSE")
5428 (set_attr "atype" "reg")])
5430 (define_insn "*ashrdi3_64"
5431 [(set (match_operand:DI 0 "register_operand" "=d,d")
5432 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5433 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5434 (clobber (reg:CC 33))]
5439 [(set_attr "op_type" "RSE")
5440 (set_attr "atype" "reg")])
5444 ; ashlsi3 instruction pattern(s).
5447 (define_insn "ashlsi3"
5448 [(set (match_operand:SI 0 "register_operand" "=d,d")
5449 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5450 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5455 [(set_attr "op_type" "RS")
5456 (set_attr "atype" "reg")])
5459 ; ashrsi3 instruction pattern(s).
5462 (define_insn "*ashrsi3_cc"
5464 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5465 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5467 (set (match_operand:SI 0 "register_operand" "=d,d")
5468 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5469 "s390_match_ccmode(insn, CCSmode)"
5473 [(set_attr "op_type" "RS")
5474 (set_attr "atype" "reg")])
5477 (define_insn "*ashrsi3_cconly"
5479 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5480 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5482 (clobber (match_scratch:SI 0 "=d,d"))]
5483 "s390_match_ccmode(insn, CCSmode)"
5487 [(set_attr "op_type" "RS")
5488 (set_attr "atype" "reg")])
5490 (define_insn "ashrsi3"
5491 [(set (match_operand:SI 0 "register_operand" "=d,d")
5492 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5493 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5494 (clobber (reg:CC 33))]
5499 [(set_attr "op_type" "RS")
5500 (set_attr "atype" "reg")])
5504 ;;- logical shift instructions.
5508 ; lshrdi3 instruction pattern(s).
5511 (define_expand "lshrdi3"
5512 [(set (match_operand:DI 0 "register_operand" "")
5513 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5514 (match_operand:SI 2 "nonmemory_operand" "")))]
5518 (define_insn "*lshrdi3_31"
5519 [(set (match_operand:DI 0 "register_operand" "=d,d")
5520 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5521 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5526 [(set_attr "op_type" "RS,RS")
5527 (set_attr "atype" "reg")])
5529 (define_insn "*lshrdi3_64"
5530 [(set (match_operand:DI 0 "register_operand" "=d,d")
5531 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5532 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5537 [(set_attr "op_type" "RSE,RSE")
5538 (set_attr "atype" "reg")])
5541 ; lshrsi3 instruction pattern(s).
5544 (define_insn "lshrsi3"
5545 [(set (match_operand:SI 0 "register_operand" "=d,d")
5546 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5547 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5552 [(set_attr "op_type" "RS")
5553 (set_attr "atype" "reg")])
5557 ;; Branch instruction patterns.
5560 (define_expand "beq"
5561 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5563 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5564 (label_ref (match_operand 0 "" ""))
5567 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5569 (define_expand "bne"
5570 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5572 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5573 (label_ref (match_operand 0 "" ""))
5576 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5578 (define_expand "bgt"
5579 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5581 (if_then_else (gt (reg:CCS 33) (const_int 0))
5582 (label_ref (match_operand 0 "" ""))
5585 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5587 (define_expand "bgtu"
5588 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5590 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5591 (label_ref (match_operand 0 "" ""))
5594 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5596 (define_expand "blt"
5597 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5599 (if_then_else (lt (reg:CCS 33) (const_int 0))
5600 (label_ref (match_operand 0 "" ""))
5603 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5605 (define_expand "bltu"
5606 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5608 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5609 (label_ref (match_operand 0 "" ""))
5612 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5614 (define_expand "bge"
5615 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5617 (if_then_else (ge (reg:CCS 33) (const_int 0))
5618 (label_ref (match_operand 0 "" ""))
5621 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5623 (define_expand "bgeu"
5624 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5626 (if_then_else (geu (reg:CCU 33) (const_int 0))
5627 (label_ref (match_operand 0 "" ""))
5630 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5632 (define_expand "ble"
5633 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5635 (if_then_else (le (reg:CCS 33) (const_int 0))
5636 (label_ref (match_operand 0 "" ""))
5639 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5641 (define_expand "bleu"
5642 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5644 (if_then_else (leu (reg:CCU 33) (const_int 0))
5645 (label_ref (match_operand 0 "" ""))
5648 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5650 (define_expand "bunordered"
5651 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5653 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5654 (label_ref (match_operand 0 "" ""))
5657 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5659 (define_expand "bordered"
5660 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5662 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5663 (label_ref (match_operand 0 "" ""))
5666 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5668 (define_expand "buneq"
5669 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5671 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5672 (label_ref (match_operand 0 "" ""))
5675 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5677 (define_expand "bungt"
5678 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5680 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5681 (label_ref (match_operand 0 "" ""))
5684 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5686 (define_expand "bunlt"
5687 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5689 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5690 (label_ref (match_operand 0 "" ""))
5693 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5695 (define_expand "bunge"
5696 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5698 (if_then_else (unge (reg:CCS 33) (const_int 0))
5699 (label_ref (match_operand 0 "" ""))
5702 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5704 (define_expand "bunle"
5705 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5707 (if_then_else (unle (reg:CCS 33) (const_int 0))
5708 (label_ref (match_operand 0 "" ""))
5711 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5713 (define_expand "bltgt"
5714 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5716 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5717 (label_ref (match_operand 0 "" ""))
5720 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5724 ;;- Conditional jump instructions.
5727 (define_insn "cjump"
5730 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5731 (label_ref (match_operand 0 "" ""))
5736 if (get_attr_length (insn) == 4)
5737 return \"j%C1\\t%l0\";
5738 else if (TARGET_64BIT)
5739 return \"jg%C1\\t%l0\";
5743 [(set_attr "op_type" "RI")
5744 (set_attr "type" "branch")
5745 (set (attr "length")
5746 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5748 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5750 (eq (symbol_ref "flag_pic") (const_int 0))
5751 (const_int 6)] (const_int 8)))])
5753 (define_insn "*cjump_long"
5756 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5757 (match_operand 0 "address_operand" "p")
5762 if (get_attr_op_type (insn) == OP_TYPE_RR)
5763 return \"b%C1r\\t%0\";
5765 return \"b%C1\\t%a0\";
5767 [(set (attr "op_type")
5768 (if_then_else (match_operand 0 "register_operand" "")
5769 (const_string "RR") (const_string "RX")))
5770 (set_attr "type" "branch")
5771 (set_attr "atype" "agen")])
5775 ;;- Negated conditional jump instructions.
5778 (define_insn "icjump"
5781 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5783 (label_ref (match_operand 0 "" ""))))]
5787 if (get_attr_length (insn) == 4)
5788 return \"j%D1\\t%l0\";
5789 else if (TARGET_64BIT)
5790 return \"jg%D1\\t%l0\";
5794 [(set_attr "op_type" "RI")
5795 (set_attr "type" "branch")
5796 (set (attr "length")
5797 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5799 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5801 (eq (symbol_ref "flag_pic") (const_int 0))
5802 (const_int 6)] (const_int 8)))])
5804 (define_insn "*icjump_long"
5807 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5809 (match_operand 0 "address_operand" "p")))]
5813 if (get_attr_op_type (insn) == OP_TYPE_RR)
5814 return \"b%D1r\\t%0\";
5816 return \"b%D1\\t%a0\";
5818 [(set (attr "op_type")
5819 (if_then_else (match_operand 0 "register_operand" "")
5820 (const_string "RR") (const_string "RX")))
5821 (set_attr "type" "branch")
5822 (set_attr "atype" "agen")])
5825 ;;- Trap instructions.
5829 [(trap_if (const_int 1) (const_int 0))]
5832 [(set_attr "op_type" "RX")
5833 (set_attr "type" "branch")])
5835 (define_expand "conditional_trap"
5836 [(set (match_dup 2) (match_dup 3))
5837 (trap_if (match_operator 0 "comparison_operator"
5838 [(match_dup 2) (const_int 0)])
5839 (match_operand:SI 1 "general_operand" ""))]
5843 enum machine_mode ccmode;
5845 if (operands[1] != const0_rtx) FAIL;
5847 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5848 s390_compare_op0, s390_compare_op1);
5849 operands[2] = gen_rtx_REG (ccmode, 33);
5850 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5853 (define_insn "*trap"
5854 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5858 [(set_attr "op_type" "RI")
5859 (set_attr "type" "branch")])
5862 ;;- Loop instructions.
5864 ;; This is all complicated by the fact that since this is a jump insn
5865 ;; we must handle our own output reloads.
5867 (define_expand "doloop_end"
5868 [(use (match_operand 0 "" "")) ; loop pseudo
5869 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5870 (use (match_operand 2 "" "")) ; max iterations
5871 (use (match_operand 3 "" "")) ; loop level
5872 (use (match_operand 4 "" ""))] ; label
5876 if (GET_MODE (operands[0]) == SImode)
5877 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5878 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5879 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5886 (define_insn "doloop_si"
5889 (ne (match_operand:SI 1 "register_operand" "d,d")
5891 (label_ref (match_operand 0 "" ""))
5893 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5894 (plus:SI (match_dup 1) (const_int -1)))
5895 (clobber (match_scratch:SI 3 "=X,&d"))
5896 (clobber (reg:CC 33))]
5900 if (which_alternative != 0)
5902 else if (get_attr_length (insn) == 4)
5903 return \"brct\\t%1,%l0\";
5907 [(set_attr "op_type" "RI")
5908 (set_attr "type" "branch")
5909 (set (attr "length")
5910 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5912 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5914 (eq (symbol_ref "flag_pic") (const_int 0))
5915 (const_int 6)] (const_int 8)))])
5917 (define_insn "*doloop_si_long"
5920 (ne (match_operand:SI 1 "register_operand" "d,d")
5922 (match_operand 0 "address_operand" "p,p")
5924 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5925 (plus:SI (match_dup 1) (const_int -1)))
5926 (clobber (match_scratch:SI 3 "=X,&d"))
5927 (clobber (reg:CC 33))]
5931 if (get_attr_op_type (insn) == OP_TYPE_RR)
5932 return \"bctr\\t%1,%0\";
5934 return \"bct\\t%1,%a0\";
5936 [(set (attr "op_type")
5937 (if_then_else (match_operand 0 "register_operand" "")
5938 (const_string "RR") (const_string "RX")))
5939 (set_attr "type" "branch")
5940 (set_attr "atype" "agen")])
5944 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5946 (match_operand 0 "" "")
5948 (set (match_operand:SI 2 "nonimmediate_operand" "")
5949 (plus:SI (match_dup 1) (const_int -1)))
5950 (clobber (match_scratch:SI 3 ""))
5951 (clobber (reg:CC 33))]
5953 && (! REG_P (operands[2])
5954 || ! rtx_equal_p (operands[1], operands[2]))"
5955 [(set (match_dup 3) (match_dup 1))
5956 (parallel [(set (reg:CCAN 33)
5957 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5959 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5960 (set (match_dup 2) (match_dup 3))
5961 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5966 (define_insn "doloop_di"
5969 (ne (match_operand:DI 1 "register_operand" "d,d")
5971 (label_ref (match_operand 0 "" ""))
5973 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
5974 (plus:DI (match_dup 1) (const_int -1)))
5975 (clobber (match_scratch:DI 3 "=X,&d"))
5976 (clobber (reg:CC 33))]
5980 if (which_alternative != 0)
5982 else if (get_attr_length (insn) == 4)
5983 return \"brctg\\t%1,%l0\";
5987 [(set_attr "op_type" "RI")
5988 (set_attr "type" "branch")
5989 (set (attr "length")
5990 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5991 (const_int 4) (const_int 12)))])
5993 (define_insn "*doloop_di_long"
5996 (ne (match_operand:DI 1 "register_operand" "d,d")
5998 (match_operand 0 "address_operand" "p,p")
6000 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6001 (plus:DI (match_dup 1) (const_int -1)))
6002 (clobber (match_scratch:DI 3 "=X,&d"))
6003 (clobber (reg:CC 33))]
6007 if (get_attr_op_type (insn) == OP_TYPE_RRE)
6008 return \"bctgr\\t%1,%0\";
6010 return \"bctg\\t%1,%a0\";
6012 [(set (attr "op_type")
6013 (if_then_else (match_operand 0 "register_operand" "")
6014 (const_string "RRE") (const_string "RXE")))
6015 (set_attr "type" "branch")
6016 (set_attr "atype" "agen")])
6020 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6022 (match_operand 0 "" "")
6024 (set (match_operand:DI 2 "nonimmediate_operand" "")
6025 (plus:DI (match_dup 1) (const_int -1)))
6026 (clobber (match_scratch:DI 3 ""))
6027 (clobber (reg:CC 33))]
6029 && (! REG_P (operands[2])
6030 || ! rtx_equal_p (operands[1], operands[2]))"
6031 [(set (match_dup 3) (match_dup 1))
6032 (parallel [(set (reg:CCAN 33)
6033 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6035 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6036 (set (match_dup 2) (match_dup 3))
6037 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6043 ;;- Unconditional jump instructions.
6047 ; jump instruction pattern(s).
6051 [(set (pc) (label_ref (match_operand 0 "" "")))]
6055 if (get_attr_length (insn) == 4)
6057 else if (TARGET_64BIT)
6058 return \"jg\\t%l0\";
6062 [(set_attr "op_type" "RI")
6063 (set_attr "type" "branch")
6064 (set (attr "length")
6065 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6067 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6069 (eq (symbol_ref "flag_pic") (const_int 0))
6070 (const_int 6)] (const_int 8)))])
6073 ; indirect-jump instruction pattern(s).
6076 (define_insn "indirect_jump"
6077 [(set (pc) (match_operand 0 "address_operand" "p"))]
6081 if (get_attr_op_type (insn) == OP_TYPE_RR)
6086 [(set (attr "op_type")
6087 (if_then_else (match_operand 0 "register_operand" "")
6088 (const_string "RR") (const_string "RX")))
6089 (set_attr "type" "branch")
6090 (set_attr "atype" "agen")])
6093 ; casesi instruction pattern(s).
6096 (define_insn "casesi_jump"
6097 [(set (pc) (match_operand 0 "address_operand" "p"))
6098 (use (label_ref (match_operand 1 "" "")))]
6102 if (get_attr_op_type (insn) == OP_TYPE_RR)
6107 [(set (attr "op_type")
6108 (if_then_else (match_operand 0 "register_operand" "")
6109 (const_string "RR") (const_string "RX")))
6110 (set_attr "type" "branch")
6111 (set_attr "atype" "agen")])
6113 (define_expand "casesi"
6114 [(match_operand:SI 0 "general_operand" "")
6115 (match_operand:SI 1 "general_operand" "")
6116 (match_operand:SI 2 "general_operand" "")
6117 (label_ref (match_operand 3 "" ""))
6118 (label_ref (match_operand 4 "" ""))]
6122 rtx index = gen_reg_rtx (SImode);
6123 rtx base = gen_reg_rtx (Pmode);
6124 rtx target = gen_reg_rtx (Pmode);
6126 emit_move_insn (index, operands[0]);
6127 emit_insn (gen_subsi3 (index, index, operands[1]));
6128 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6131 if (Pmode != SImode)
6132 index = convert_to_mode (Pmode, index, 1);
6133 if (GET_CODE (index) != REG)
6134 index = copy_to_mode_reg (Pmode, index);
6137 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6139 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6141 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6143 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6144 emit_move_insn (target, index);
6147 target = gen_rtx_PLUS (Pmode, base, target);
6148 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6155 ;;- Jump to subroutine.
6160 ; untyped call instruction pattern(s).
6163 ;; Call subroutine returning any type.
6164 (define_expand "untyped_call"
6165 [(parallel [(call (match_operand 0 "" "")
6167 (match_operand 1 "" "")
6168 (match_operand 2 "" "")])]
6174 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6176 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6178 rtx set = XVECEXP (operands[2], 0, i);
6179 emit_move_insn (SET_DEST (set), SET_SRC (set));
6182 /* The optimizer does not know that the call sets the function value
6183 registers we stored in the result block. We avoid problems by
6184 claiming that all hard registers are used and clobbered at this
6186 emit_insn (gen_blockage ());
6191 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6192 ;; all of memory. This blocks insns from being moved across this point.
6194 (define_insn "blockage"
6195 [(unspec_volatile [(const_int 0)] 0)]
6198 [(set_attr "type" "none")
6199 (set_attr "length" "0")])
6204 ; call instruction pattern(s).
6207 (define_expand "call"
6208 [(call (match_operand 0 "" "")
6209 (match_operand 1 "" ""))
6210 (use (match_operand 2 "" ""))]
6217 /* Direct function calls need special treatment. */
6218 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6220 rtx sym = XEXP (operands[0], 0);
6222 /* When calling a global routine in PIC mode, we must
6223 replace the symbol itself with the PLT stub. */
6224 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6226 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6227 sym = gen_rtx_CONST (Pmode, sym);
6232 /* Unless we can use the bras(l) insn, force the
6233 routine address into a register. */
6234 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6236 rtx target = gen_reg_rtx (Pmode);
6237 emit_move_insn (target, sym);
6241 operands[0] = gen_rtx_MEM (QImode, sym);
6245 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6246 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6248 /* In 31-bit, we must load the GOT register even if the
6249 compiler doesn't know about it, because the PLT glue
6250 code uses it. In 64-bit, this is not necessary. */
6251 if (plt_call && !TARGET_64BIT)
6252 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6257 (define_expand "call_exp"
6258 [(parallel [(call (match_operand 0 "" "")
6259 (match_operand 1 "" ""))
6260 (clobber (match_operand 2 "" ""))])]
6264 (define_insn "brasl"
6265 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6266 (match_operand:SI 1 "const_int_operand" "n"))
6267 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6270 [(set_attr "op_type" "RIL")
6271 (set_attr "type" "jsr")])
6274 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6275 (match_operand:SI 1 "const_int_operand" "n"))
6276 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6279 [(set_attr "op_type" "RI")
6280 (set_attr "type" "jsr")])
6282 (define_insn "basr_64"
6283 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6284 (match_operand:SI 1 "const_int_operand" "n"))
6285 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6288 [(set_attr "op_type" "RR")
6289 (set_attr "type" "jsr")
6290 (set_attr "atype" "agen")])
6292 (define_insn "basr_31"
6293 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6294 (match_operand:SI 1 "const_int_operand" "n"))
6295 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6298 [(set_attr "op_type" "RR")
6299 (set_attr "type" "jsr")
6300 (set_attr "atype" "agen")])
6302 (define_insn "bas_64"
6303 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6304 (match_operand:SI 1 "const_int_operand" "n"))
6305 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6308 [(set_attr "op_type" "RX")
6309 (set_attr "type" "jsr")])
6311 (define_insn "bas_31"
6312 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6313 (match_operand:SI 1 "const_int_operand" "n"))
6314 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6317 [(set_attr "op_type" "RX")
6318 (set_attr "type" "jsr")])
6322 ; call_value instruction pattern(s).
6325 (define_expand "call_value"
6326 [(set (match_operand 0 "" "")
6327 (call (match_operand 1 "" "")
6328 (match_operand 2 "" "")))
6329 (use (match_operand 3 "" ""))]
6336 /* Direct function calls need special treatment. */
6337 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6339 rtx sym = XEXP (operands[1], 0);
6341 /* When calling a global routine in PIC mode, we must
6342 replace the symbol itself with the PLT stub. */
6343 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6345 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6346 sym = gen_rtx_CONST (Pmode, sym);
6351 /* Unless we can use the bras(l) insn, force the
6352 routine address into a register. */
6353 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6355 rtx target = gen_reg_rtx (Pmode);
6356 emit_move_insn (target, sym);
6360 operands[1] = gen_rtx_MEM (QImode, sym);
6364 insn = emit_call_insn (
6365 gen_call_value_exp (operands[0], operands[1], operands[2],
6366 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6368 /* In 31-bit, we must load the GOT register even if the
6369 compiler doesn't know about it, because the PLT glue
6370 code uses it. In 64-bit, this is not necessary. */
6371 if (plt_call && !TARGET_64BIT)
6372 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6377 (define_expand "call_value_exp"
6378 [(parallel [(set (match_operand 0 "" "")
6379 (call (match_operand 1 "" "")
6380 (match_operand 2 "" "")))
6381 (clobber (match_operand 3 "" ""))])]
6385 (define_insn "brasl_r"
6386 [(set (match_operand 0 "register_operand" "=df")
6387 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6388 (match_operand:SI 2 "const_int_operand" "n")))
6389 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6392 [(set_attr "op_type" "RIL")
6393 (set_attr "type" "jsr")])
6395 (define_insn "bras_r"
6396 [(set (match_operand 0 "register_operand" "=df")
6397 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6398 (match_operand:SI 2 "const_int_operand" "n")))
6399 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6402 [(set_attr "op_type" "RI")
6403 (set_attr "type" "jsr")])
6405 (define_insn "basr_r_64"
6406 [(set (match_operand 0 "register_operand" "=df")
6407 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6408 (match_operand:SI 2 "const_int_operand" "n")))
6409 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6412 [(set_attr "op_type" "RR")
6413 (set_attr "type" "jsr")
6414 (set_attr "atype" "agen")])
6416 (define_insn "basr_r_31"
6417 [(set (match_operand 0 "register_operand" "=df")
6418 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6419 (match_operand:SI 2 "const_int_operand" "n")))
6420 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6423 [(set_attr "op_type" "RR")
6424 (set_attr "type" "jsr")
6425 (set_attr "atype" "agen")])
6427 (define_insn "bas_r_64"
6428 [(set (match_operand 0 "register_operand" "=df")
6429 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6430 (match_operand:SI 2 "const_int_operand" "n")))
6431 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6434 [(set_attr "op_type" "RX")
6435 (set_attr "type" "jsr")])
6437 (define_insn "bas_r_31"
6438 [(set (match_operand 0 "register_operand" "=df")
6439 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6440 (match_operand:SI 2 "const_int_operand" "n")))
6441 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6444 [(set_attr "op_type" "RX")
6445 (set_attr "type" "jsr")])
6449 ;;- Miscellaneous instructions.
6453 ; allocate stack instruction pattern(s).
6456 (define_expand "allocate_stack"
6458 (plus (reg 15) (match_operand 1 "general_operand" "")))
6459 (set (match_operand 0 "general_operand" "")
6464 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6465 rtx chain = gen_rtx (MEM, Pmode, stack);
6466 rtx temp = gen_reg_rtx (Pmode);
6468 emit_move_insn (temp, chain);
6471 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6473 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6475 emit_move_insn (chain, temp);
6477 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6483 ; setjmp/longjmp instruction pattern(s).
6486 (define_expand "builtin_setjmp_setup"
6487 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6491 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6492 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6494 emit_move_insn (base, basereg);
6498 (define_expand "builtin_setjmp_receiver"
6499 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6503 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6504 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6505 SYMBOL_REF_FLAG (got) = 1;
6507 emit_move_insn (gotreg, got);
6508 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6512 (define_expand "builtin_longjmp"
6513 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6517 /* The elements of the buffer are, in order: */
6518 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6519 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6520 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6521 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6522 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6523 rtx jmp = gen_rtx_REG (Pmode, 14);
6525 emit_move_insn (jmp, lab);
6526 emit_move_insn (basereg, base);
6527 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6528 emit_move_insn (hard_frame_pointer_rtx, fp);
6530 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6531 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6532 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6533 emit_indirect_jump (jmp);
6538 ;; These patterns say how to save and restore the stack pointer. We need not
6539 ;; save the stack pointer at function level since we are careful to
6540 ;; preserve the backchain. At block level, we have to restore the backchain
6541 ;; when we restore the stack pointer.
6543 ;; For nonlocal gotos, we must save both the stack pointer and its
6544 ;; backchain and restore both. Note that in the nonlocal case, the
6545 ;; save area is a memory location.
6547 (define_expand "save_stack_function"
6548 [(match_operand 0 "general_operand" "")
6549 (match_operand 1 "general_operand" "")]
6553 (define_expand "restore_stack_function"
6554 [(match_operand 0 "general_operand" "")
6555 (match_operand 1 "general_operand" "")]
6559 (define_expand "restore_stack_block"
6560 [(use (match_operand 0 "register_operand" ""))
6561 (set (match_dup 2) (match_dup 3))
6562 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6563 (set (match_dup 3) (match_dup 2))]
6567 operands[2] = gen_reg_rtx (Pmode);
6568 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6571 (define_expand "save_stack_nonlocal"
6572 [(match_operand 0 "memory_operand" "")
6573 (match_operand 1 "register_operand" "")]
6577 rtx temp = gen_reg_rtx (Pmode);
6579 /* Copy the backchain to the first word, sp to the second. */
6580 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6581 emit_move_insn (operand_subword (operands[0], 0, 0,
6582 TARGET_64BIT ? TImode : DImode),
6584 emit_move_insn (operand_subword (operands[0], 1, 0,
6585 TARGET_64BIT ? TImode : DImode),
6590 (define_expand "restore_stack_nonlocal"
6591 [(match_operand 0 "register_operand" "")
6592 (match_operand 1 "memory_operand" "")]
6596 rtx temp = gen_reg_rtx (Pmode);
6598 /* Restore the backchain from the first word, sp from the second. */
6599 emit_move_insn (temp,
6600 operand_subword (operands[1], 0, 0,
6601 TARGET_64BIT ? TImode : DImode));
6602 emit_move_insn (operands[0],
6603 operand_subword (operands[1], 1, 0,
6604 TARGET_64BIT ? TImode : DImode));
6605 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6611 ; nop instruction pattern(s).
6618 [(set_attr "op_type" "RR")])
6622 ; Special literal pool access instruction pattern(s).
6625 (define_insn "consttable_qi"
6626 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6630 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6633 [(set_attr "op_type" "NN")
6634 (set_attr "length" "1")])
6636 (define_insn "consttable_hi"
6637 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6641 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6644 [(set_attr "op_type" "NN")
6645 (set_attr "length" "2")])
6647 (define_insn "consttable_si"
6648 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6652 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6653 return \".long\\t%0\";
6655 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6658 [(set_attr "op_type" "NN")
6659 (set_attr "length" "4")])
6661 (define_insn "consttable_di"
6662 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6666 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6669 [(set_attr "op_type" "NN")
6670 (set_attr "length" "8")])
6672 (define_insn "consttable_sf"
6673 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6679 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6682 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6683 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6686 [(set_attr "op_type" "NN")
6687 (set_attr "length" "4")])
6689 (define_insn "consttable_df"
6690 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6696 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6699 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6700 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6703 [(set_attr "op_type" "NN")
6704 (set_attr "length" "8")])
6706 (define_insn "pool_start_31"
6707 [(unspec_volatile [(const_int 0)] 206)]
6710 [(set_attr "op_type" "NN")
6711 (set_attr "length" "2")])
6713 (define_insn "pool_end_31"
6714 [(unspec_volatile [(const_int 0)] 207)]
6717 [(set_attr "op_type" "NN")
6718 (set_attr "length" "2")])
6720 (define_insn "pool_start_64"
6721 [(unspec_volatile [(const_int 0)] 206)]
6723 ".section\\t.rodata\;.align\\t8"
6724 [(set_attr "op_type" "NN")
6725 (set_attr "length" "0")])
6727 (define_insn "pool_end_64"
6728 [(unspec_volatile [(const_int 0)] 207)]
6731 [(set_attr "op_type" "NN")
6732 (set_attr "length" "0")])
6734 (define_insn "reload_base_31"
6735 [(set (match_operand:SI 0 "register_operand" "=a")
6736 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6738 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6739 [(set_attr "op_type" "NN")
6740 (set_attr "type" "la")
6741 (set_attr "length" "6")])
6743 (define_insn "reload_base_64"
6744 [(set (match_operand:DI 0 "register_operand" "=a")
6745 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
6748 [(set_attr "op_type" "RIL")
6749 (set_attr "type" "larl")])
6751 (define_insn "reload_anchor"
6752 [(set (match_operand:SI 0 "register_operand" "=a")
6753 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
6755 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
6756 [(set_attr "op_type" "NN")
6757 (set_attr "type" "la")
6758 (set_attr "atype" "agen")
6759 (set_attr "length" "8")])
6762 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
6765 [(set_attr "op_type" "NN")
6766 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6769 ;; Insns related to generating the function prologue and epilogue.
6773 (define_expand "prologue"
6774 [(use (const_int 0))]
6778 s390_emit_prologue ();
6782 (define_expand "epilogue"
6783 [(use (const_int 1))]
6787 s390_emit_epilogue ();
6792 (define_insn "*return_si"
6794 (use (match_operand:SI 0 "register_operand" "a"))]
6797 [(set_attr "op_type" "RR")
6798 (set_attr "type" "jsr")
6799 (set_attr "atype" "agen")])
6801 (define_insn "*return_di"
6803 (use (match_operand:DI 0 "register_operand" "a"))]
6806 [(set_attr "op_type" "RR")
6807 (set_attr "type" "jsr")
6808 (set_attr "atype" "agen")])
6810 (define_insn "literal_pool_31"
6811 [(unspec_volatile [(const_int 0)] 300)
6812 (set (match_operand:SI 0 "register_operand" "=a")
6813 (label_ref (match_operand 1 "" "")))
6814 (use (label_ref (match_operand 2 "" "")))]
6818 if (s390_nr_constants) {
6819 output_asm_insn (\"bras\\t%0,%2\", operands);
6820 s390_output_constant_pool (operands[1], operands[2]);
6824 [(set_attr "op_type" "NN")
6825 (set_attr "type" "larl")])
6827 (define_insn "literal_pool_64"
6828 [(unspec_volatile [(const_int 0)] 300)
6829 (set (match_operand:DI 0 "register_operand" "=a")
6830 (label_ref (match_operand 1 "" "")))
6831 (use (label_ref (match_operand 2 "" "")))]
6835 if (s390_nr_constants) {
6836 output_asm_insn (\"larl\\t%0,%1\", operands);
6837 s390_output_constant_pool (operands[1], operands[2]);
6841 [(set_attr "op_type" "NN")
6842 (set_attr "type" "larl")])