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s390.c (s390_final_chunkify): Re-run shorten_branches after emitting ltorg insns.
[gcc.git] / gcc / config / s390 / s390.md
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
21
22 ;;
23 ;; Special constraints for s/390 machine description:
24 ;;
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
32 ;;
33 ;; Special formats used for outputting 390 instructions.
34 ;;
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
41 ;;
42 ;; We have a special constraint for pattern matching.
43 ;;
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
45 ;;
46
47
48 ;; Define an insn type attribute. This is used in function unit delay
49 ;; computations.
50
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
53
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
57
58 (define_attr "atype" "reg,mem"
59 (const_string "reg"))
60
61 ;; Generic pipeline function unit.
62
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
65
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
68
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
71
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
74
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
77
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
80
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
83
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
86
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
89
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
92
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
95
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
98
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
101
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
104
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
107
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
110
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
113
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
116
117 ;; Operand type. Used to default length attribute values
118
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
121 (const_string "RX"))
122
123 ;; Length in bytes.
124
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
141 (const_int 4)))
142
143 ;; Define attributes for `asm' insns.
144
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
147
148 ;;
149 ;; Condition Codes
150 ;;
151 ;
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
157
158 ; CCZ -> CCL / CCZ1
159 ; CCZ1 -> CCA/CCU/CCS/CCT
160 ; CCS -> CCA
161
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
164
165
166 ;;
167 ;;- Compare instructions.
168 ;;
169
170 (define_expand "cmpdi"
171 [(set (reg:CC 33)
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
174 "TARGET_64BIT"
175 "
176 {
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
179 DONE;
180 }")
181
182 (define_expand "cmpsi"
183 [(set (reg:CC 33)
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
186 ""
187 "
188 {
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
191 DONE;
192 }")
193
194 ;(define_expand "cmphi"
195 ; [(set (reg:CC 33)
196 ; (compare:CC (match_operand:HI 0 "register_operand" "")
197 ; (match_operand:HI 1 "general_operand" "")))]
198 ; ""
199 ; "
200 ;{
201 ; s390_compare_op0 = operands[0];
202 ; s390_compare_op1 = operands[1];
203 ; DONE;
204 ;}")
205
206 ;(define_expand "cmpqi"
207 ; [(set (reg:CC 33)
208 ; (compare:CC (match_operand:QI 0 "register_operand" "")
209 ; (match_operand:QI 1 "general_operand" "")))]
210 ; ""
211 ; "
212 ;{
213 ; s390_compare_op0 = operands[0];
214 ; s390_compare_op1 = operands[1];
215 ; DONE;
216 ;}")
217
218 (define_expand "cmpdf"
219 [(set (reg:CC 33)
220 (compare:CC (match_operand:DF 0 "register_operand" "")
221 (match_operand:DF 1 "general_operand" "")))]
222 "TARGET_HARD_FLOAT"
223 "
224 {
225 s390_compare_op0 = operands[0];
226 s390_compare_op1 = operands[1];
227 DONE;
228 }")
229
230 (define_expand "cmpsf"
231 [(set (reg:CC 33)
232 (compare:CC (match_operand:SF 0 "register_operand" "")
233 (match_operand:SF 1 "general_operand" "")))]
234 "TARGET_HARD_FLOAT"
235 "
236 {
237 s390_compare_op0 = operands[0];
238 s390_compare_op1 = operands[1];
239 DONE;
240 }")
241
242
243 ; DI instructions
244
245 (define_insn "*cmpdi_tm2"
246 [(set (reg 33)
247 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
248 (match_operand:DI 1 "const_int_operand" "n")
249 (match_operand:DI 2 "const_int_operand" "n"))
250 (const_int 0)))]
251 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
252 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
253 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
254 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
255 == INTVAL (operands[2]) >> 4"
256 "*
257 {
258 int part = INTVAL (operands[2]) >> 4;
259 int block = (1 << INTVAL (operands[1])) - 1;
260 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
261
262 operands[2] = GEN_INT (block << shift);
263
264 switch (part)
265 {
266 case 0: return \"tmhh\\t%0,%x2\";
267 case 1: return \"tmhl\\t%0,%x2\";
268 case 2: return \"tmlh\\t%0,%x2\";
269 case 3: return \"tmll\\t%0,%x2\";
270 default: abort ();
271 }
272 }"
273 [(set_attr "op_type" "RI")])
274
275 (define_insn "*cmpdi_tm_reg"
276 [(set (reg 33)
277 (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
278 (match_operand:DI 1 "immediate_operand" "n"))
279 (const_int 0)))]
280 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
281 && s390_single_hi (operands[1], DImode, 0) >= 0"
282 "*
283 {
284 int part = s390_single_hi (operands[1], DImode, 0);
285 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
286
287 switch (part)
288 {
289 case 0: return \"tmhh\\t%0,%x1\";
290 case 1: return \"tmhl\\t%0,%x1\";
291 case 2: return \"tmlh\\t%0,%x1\";
292 case 3: return \"tmll\\t%0,%x1\";
293 default: abort ();
294 }
295 }"
296 [(set_attr "op_type" "RI")])
297
298 (define_insn "*cmpdi_tm_mem"
299 [(set (reg 33)
300 (compare (and:DI (match_operand:DI 0 "s_operand" "%Qo")
301 (match_operand:DI 1 "immediate_operand" "n"))
302 (const_int 0)))]
303 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
304 && s390_single_qi (operands[1], DImode, 0) >= 0"
305 "*
306 {
307 int part = s390_single_qi (operands[1], DImode, 0);
308 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
309
310 operands[0] = gen_rtx_MEM (QImode,
311 plus_constant (XEXP (operands[0], 0), part));
312 return \"tm\\t%0,%b1\";
313 }"
314 [(set_attr "op_type" "SI")
315 (set_attr "atype" "mem")])
316
317 (define_insn "*ltgr"
318 [(set (reg 33)
319 (compare (match_operand:DI 0 "register_operand" "d")
320 (match_operand:DI 1 "const0_operand" "")))
321 (set (match_operand:DI 2 "register_operand" "=d")
322 (match_dup 0))]
323 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
324 "ltgr\\t%2,%0"
325 [(set_attr "op_type" "RRE")])
326
327 (define_insn "*cmpdi_ccs_0_64"
328 [(set (reg 33)
329 (compare (match_operand:DI 0 "register_operand" "d")
330 (match_operand:DI 1 "const0_operand" "")))]
331 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
332 "ltgr\\t%0,%0"
333 [(set_attr "op_type" "RRE")])
334
335 (define_insn "*cmpdi_ccs_0_31"
336 [(set (reg 33)
337 (compare (match_operand:DI 0 "register_operand" "d")
338 (match_operand:DI 1 "const0_operand" "")))]
339 "s390_match_ccmode(insn, CCSmode)"
340 "srda\\t%0,0"
341 [(set_attr "op_type" "RS")])
342
343 (define_insn "*cmpdi_ccs"
344 [(set (reg 33)
345 (compare (match_operand:DI 0 "register_operand" "d,d,d")
346 (match_operand:DI 1 "general_operand" "d,K,m")))]
347 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
348 "@
349 cgr\\t%0,%1
350 cghi\\t%0,%c1
351 cg\\t%0,%1"
352 [(set_attr "op_type" "RRE,RI,RXE")
353 (set_attr "atype" "reg,reg,mem")])
354
355 (define_insn "*cmpdi_ccu"
356 [(set (reg 33)
357 (compare (match_operand:DI 0 "register_operand" "d,d")
358 (match_operand:DI 1 "general_operand" "d,m")))]
359 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
360 "@
361 clgr\\t%0,%1
362 clg\\t%0,%1"
363 [(set_attr "op_type" "RRE,RXE")
364 (set_attr "atype" "reg,mem")])
365
366 (define_insn "*cmpdi_ccu_mem"
367 [(set (reg 33)
368 (compare (match_operand:DI 0 "s_operand" "oQ")
369 (match_operand:DI 1 "s_imm_operand" "oQ")))]
370 "s390_match_ccmode(insn, CCUmode)"
371 "clc\\t%O0(8,%R0),%1"
372 [(set_attr "op_type" "SS")
373 (set_attr "atype" "mem")])
374
375 ; SI instructions
376
377 (define_insn "*cmpsi_tm2"
378 [(set (reg 33)
379 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
380 (match_operand:SI 1 "const_int_operand" "n")
381 (match_operand:SI 2 "const_int_operand" "n"))
382 (const_int 0)))]
383 "s390_match_ccmode(insn, CCTmode)
384 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
385 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
386 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
387 == INTVAL (operands[2]) >> 4"
388 "*
389 {
390 int part = INTVAL (operands[2]) >> 4;
391 int block = (1 << INTVAL (operands[1])) - 1;
392 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
393
394 operands[2] = GEN_INT (block << shift);
395
396 switch (part)
397 {
398 case 0: return \"tmh\\t%0,%x2\";
399 case 1: return \"tml\\t%0,%x2\";
400 default: abort ();
401 }
402 }"
403 [(set_attr "op_type" "RI")])
404
405 (define_insn "*cmpsi_tm_reg"
406 [(set (reg 33)
407 (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
408 (match_operand:SI 1 "immediate_operand" "n"))
409 (const_int 0)))]
410 "s390_match_ccmode(insn, CCTmode)
411 && s390_single_hi (operands[1], SImode, 0) >= 0"
412 "*
413 {
414 int part = s390_single_hi (operands[1], SImode, 0);
415 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
416
417 switch (part)
418 {
419 case 0: return \"tmh\\t%0,%x1\";
420 case 1: return \"tml\\t%0,%x1\";
421 default: abort ();
422 }
423 }"
424 [(set_attr "op_type" "RI")])
425
426 (define_insn "*cmpsi_tm_mem"
427 [(set (reg 33)
428 (compare (and:SI (match_operand:SI 0 "s_operand" "%Qo")
429 (match_operand:SI 1 "immediate_operand" "n"))
430 (const_int 0)))]
431 "s390_match_ccmode(insn, CCTmode)
432 && s390_single_qi (operands[1], SImode, 0) >= 0"
433 "*
434 {
435 int part = s390_single_qi (operands[1], SImode, 0);
436 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
437
438 operands[0] = gen_rtx_MEM (QImode,
439 plus_constant (XEXP (operands[0], 0), part));
440 return \"tm\\t%0,%b1\";
441 }"
442 [(set_attr "op_type" "SI")
443 (set_attr "atype" "mem")])
444
445 (define_insn "*ltr"
446 [(set (reg 33)
447 (compare (match_operand:SI 0 "register_operand" "d")
448 (match_operand:SI 1 "const0_operand" "")))
449 (set (match_operand:SI 2 "register_operand" "=d")
450 (match_dup 0))]
451 "s390_match_ccmode(insn, CCSmode)"
452 "ltr\\t%2,%0"
453 [(set_attr "op_type" "RR")])
454
455 (define_insn "*icm15"
456 [(set (reg 33)
457 (compare (match_operand:SI 0 "s_operand" "Qo")
458 (match_operand:SI 1 "const0_operand" "")))
459 (set (match_operand:SI 2 "register_operand" "=d")
460 (match_dup 0))]
461 "s390_match_ccmode(insn, CCSmode)"
462 "icm\\t%2,15,%0"
463 [(set_attr "op_type" "RS")
464 (set_attr "atype" "mem")])
465
466 (define_insn "*icm15_cconly"
467 [(set (reg 33)
468 (compare (match_operand:SI 0 "s_operand" "Qo")
469 (match_operand:SI 1 "const0_operand" "")))
470 (clobber (match_scratch:SI 2 "=d"))]
471 "s390_match_ccmode(insn, CCSmode)"
472 "icm\\t%2,15,%0"
473 [(set_attr "op_type" "RS")
474 (set_attr "atype" "mem")])
475
476 (define_insn "*cmpsi_ccs_0"
477 [(set (reg 33)
478 (compare (match_operand:SI 0 "register_operand" "d")
479 (match_operand:SI 1 "const0_operand" "")))]
480 "s390_match_ccmode(insn, CCSmode)"
481 "ltr\\t%0,%0"
482 [(set_attr "op_type" "RR")])
483
484 (define_insn "*cmpsidi_ccs"
485 [(set (reg 33)
486 (compare (match_operand:SI 0 "register_operand" "d")
487 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
488 "s390_match_ccmode(insn, CCSmode)"
489 "ch\\t%0,%1"
490 [(set_attr "op_type" "RR")
491 (set_attr "atype" "mem")])
492
493 (define_insn "*cmpsi_ccs"
494 [(set (reg 33)
495 (compare (match_operand:SI 0 "register_operand" "d,d,d")
496 (match_operand:SI 1 "general_operand" "d,K,m")))]
497 "s390_match_ccmode(insn, CCSmode)"
498 "@
499 cr\\t%0,%1
500 chi\\t%0,%c1
501 c\\t%0,%1"
502 [(set_attr "op_type" "RR,RI,RX")
503 (set_attr "atype" "reg,reg,mem")])
504
505 (define_insn "*cmpsi_ccu"
506 [(set (reg 33)
507 (compare (match_operand:SI 0 "register_operand" "d,d")
508 (match_operand:SI 1 "general_operand" "d,m")))]
509 "s390_match_ccmode(insn, CCUmode)"
510 "@
511 clr\\t%0,%1
512 cl\\t%0,%1"
513 [(set_attr "op_type" "RR,RX")
514 (set_attr "atype" "reg,mem")])
515
516 (define_insn "*cmpsi_ccu_mem"
517 [(set (reg 33)
518 (compare (match_operand:SI 0 "s_operand" "oQ")
519 (match_operand:SI 1 "s_imm_operand" "oQ")))]
520 "s390_match_ccmode(insn, CCUmode)"
521 "clc\\t%O0(4,%R0),%1"
522 [(set_attr "op_type" "SS")
523 (set_attr "atype" "mem")])
524
525
526 ; HI instructions
527
528 (define_insn "*cmphi_tm_sub"
529 [(set (reg 33)
530 (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0)
531 (match_operand:SI 1 "immediate_operand" "n"))
532 (const_int 0)))]
533 "s390_match_ccmode(insn, CCTmode)
534 && s390_single_qi (operands[1], HImode, 0) >= 0"
535 "*
536 {
537 int part = s390_single_qi (operands[1], HImode, 0);
538 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
539
540 operands[0] = gen_rtx_MEM (QImode,
541 plus_constant (XEXP (operands[0], 0), part));
542 return \"tm\\t%0,%b1\";
543 }"
544 [(set_attr "op_type" "SI")
545 (set_attr "atype" "mem")])
546
547 (define_insn "*icm3"
548 [(set (reg 33)
549 (compare (match_operand:HI 0 "s_operand" "Qo")
550 (match_operand:HI 1 "const0_operand" "")))
551 (set (match_operand:HI 2 "register_operand" "=d")
552 (match_dup 0))]
553 "s390_match_ccmode(insn, CCSmode)"
554 "icm\\t%2,3,%0"
555 [(set_attr "op_type" "RS")
556 (set_attr "atype" "mem")])
557
558 (define_insn "*cmphi_cct_0"
559 [(set (reg 33)
560 (compare (match_operand:HI 0 "register_operand" "d")
561 (match_operand:HI 1 "const0_operand" "")))]
562 "s390_match_ccmode(insn, CCTmode)"
563 "tml\\t%0,65535"
564 [(set_attr "op_type" "RX")])
565
566 (define_insn "*cmphi_ccs_0"
567 [(set (reg 33)
568 (compare (match_operand:HI 0 "s_operand" "Qo")
569 (match_operand:HI 1 "const0_operand" "")))
570 (clobber (match_scratch:HI 2 "=d"))]
571 "s390_match_ccmode(insn, CCSmode)"
572 "icm\\t%2,3,%0"
573 [(set_attr "op_type" "RS")
574 (set_attr "atype" "mem")])
575
576 (define_insn "*cmphi_ccu"
577 [(set (reg 33)
578 (compare (match_operand:HI 0 "register_operand" "d")
579 (match_operand:HI 1 "s_imm_operand" "Qo")))]
580 "s390_match_ccmode(insn, CCUmode)"
581 "clm\\t%0,3,%1"
582 [(set_attr "op_type" "RS")
583 (set_attr "atype" "mem")])
584
585 (define_insn "*cmphi_ccu_mem"
586 [(set (reg 33)
587 (compare (match_operand:HI 0 "s_operand" "oQ")
588 (match_operand:HI 1 "s_imm_operand" "oQ")))]
589 "s390_match_ccmode(insn, CCUmode)"
590 "clc\\t%O0(2,%R0),%1"
591 [(set_attr "op_type" "SS")
592 (set_attr "atype" "mem")])
593
594
595 ; QI instructions
596
597 (define_insn "*cmpqi_tm2"
598 [(set (reg 33)
599 (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo")
600 (match_operand:SI 1 "const_int_operand" "n")
601 (match_operand:SI 2 "const_int_operand" "n"))
602 (const_int 0)))]
603 "s390_match_ccmode(insn, CCTmode)
604 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
605 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
606 "*
607 {
608 int block = (1 << INTVAL (operands[1])) - 1;
609 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
610
611 operands[2] = GEN_INT (block << shift);
612 return \"tm\\t%0,%b2\";
613 }"
614 [(set_attr "op_type" "SI")
615 (set_attr "atype" "mem")])
616
617 (define_insn "*cmpqi_tm"
618 [(set (reg 33)
619 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q")
620 (match_operand:QI 1 "immediate_operand" "n,n"))
621 (const_int 0)))]
622 "s390_match_ccmode(insn, CCTmode)"
623 "@
624 tml\\t%0,%b1
625 tm\\t%0,%b1"
626 [(set_attr "op_type" "RI,SI")
627 (set_attr "atype" "reg,mem")])
628
629 (define_insn "*cmpqi_tm_sub"
630 [(set (reg 33)
631 (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0)
632 (match_operand:SI 1 "immediate_operand" "n"))
633 (const_int 0)))]
634 "s390_match_ccmode(insn, CCTmode)"
635 "tm\\t%0,%b1"
636 [(set_attr "op_type" "SI")
637 (set_attr "atype" "mem")])
638
639 (define_insn "*icm1"
640 [(set (reg 33)
641 (compare (match_operand:QI 0 "s_operand" "Qo")
642 (match_operand:QI 1 "const0_operand" "")))
643 (set (match_operand:QI 2 "register_operand" "=d")
644 (match_dup 0))]
645 "s390_match_ccmode(insn, CCSmode)"
646 "icm\\t%2,1,%0"
647 [(set_attr "op_type" "RS")
648 (set_attr "atype" "mem")])
649
650 (define_insn "*tm_0"
651 [(set (reg 33)
652 (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
653 (match_operand:QI 1 "immediate_operand" "")))
654 (const_int 0)))]
655 "s390_match_ccmode(insn, CCTmode) &&
656 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
657 "tm\\t%0,%1"
658 [(set_attr "op_type" "RI")
659 (set_attr "atype" "mem")])
660
661 (define_insn "*cmpqi_cct_0"
662 [(set (reg 33)
663 (compare (match_operand:QI 0 "register_operand" "d")
664 (match_operand:QI 1 "const0_operand" "")))]
665 "s390_match_ccmode(insn, CCTmode)"
666 "tml\\t%0,255"
667 [(set_attr "op_type" "RI")])
668
669 (define_insn "*cmpqi_ccs_0"
670 [(set (reg 33)
671 (compare (match_operand:QI 0 "s_operand" "Qo")
672 (match_operand:QI 1 "const0_operand" "")))
673 (clobber (match_scratch:QI 2 "=d"))]
674 "s390_match_ccmode(insn, CCSmode)"
675 "icm\\t%2,1,%0"
676 [(set_attr "op_type" "RS")
677 (set_attr "atype" "mem")])
678
679 (define_insn "*cmpqi_ccu_0"
680 [(set (reg 33)
681 (compare (match_operand:QI 0 "s_operand" "Qo")
682 (match_operand:QI 1 "const0_operand" "")))]
683 "s390_match_ccmode(insn, CCUmode)"
684 "cli\\t%0,0"
685 [(set_attr "op_type" "SI")
686 (set_attr "atype" "mem")])
687
688 (define_insn "*cmpqi_ccu"
689 [(set (reg 33)
690 (compare (match_operand:QI 0 "register_operand" "d")
691 (match_operand:QI 1 "s_imm_operand" "Qo")))]
692 "s390_match_ccmode(insn, CCUmode)"
693 "clm\\t%0,1,%1"
694 [(set_attr "op_type" "RS")
695 (set_attr "atype" "mem")])
696
697 (define_insn "*cmpqi_ccu_immed"
698 [(set (reg 33)
699 (compare (match_operand:QI 0 "s_operand" "Qo")
700 (match_operand:QI 1 "const_int_operand" "n")))]
701 "s390_match_ccmode(insn, CCUmode) &&
702 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
703 "cli\\t%0,%1"
704 [(set_attr "op_type" "SI")
705 (set_attr "atype" "mem")])
706
707 (define_insn "*cmpqi_ccu_mem"
708 [(set (reg 33)
709 (compare (match_operand:QI 0 "s_operand" "oQ")
710 (match_operand:QI 1 "s_imm_operand" "oQ")))]
711 "s390_match_ccmode(insn, CCUmode)"
712 "clc\\t%O0(1,%R0),%1"
713 [(set_attr "op_type" "SS")
714 (set_attr "atype" "mem")])
715
716
717 ; DF instructions
718
719 (define_insn "*cmpdf_ccs_0"
720 [(set (reg 33)
721 (compare (match_operand:DF 0 "register_operand" "f")
722 (match_operand:DF 1 "const0_operand" "")))]
723 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
724 "ltdbr\\t%0,%0"
725 [(set_attr "op_type" "RRE")])
726
727 (define_insn "*cmpdf_ccs_0_ibm"
728 [(set (reg 33)
729 (compare (match_operand:DF 0 "register_operand" "f")
730 (match_operand:DF 1 "const0_operand" "")))]
731 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
732 "ltdr\\t%0,%0"
733 [(set_attr "op_type" "RR")])
734
735 (define_insn "*cmpdf_ccs"
736 [(set (reg 33)
737 (compare (match_operand:DF 0 "register_operand" "f,f")
738 (match_operand:DF 1 "general_operand" "f,m")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
740 "@
741 cdbr\\t%0,%1
742 cdb\\t%0,%1"
743 [(set_attr "op_type" "RRE,RXE")
744 (set_attr "atype" "reg,mem")])
745
746 (define_insn "*cmpdf_ccs_ibm"
747 [(set (reg 33)
748 (compare (match_operand:DF 0 "register_operand" "f,f")
749 (match_operand:DF 1 "general_operand" "f,m")))]
750 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
751 "@
752 cdr\\t%0,%1
753 cd\\t%0,%1"
754 [(set_attr "op_type" "RR,RX")
755 (set_attr "atype" "reg,mem")])
756
757
758 ; SF instructions
759
760 (define_insn "*cmpsf_ccs_0"
761 [(set (reg 33)
762 (compare (match_operand:SF 0 "register_operand" "f")
763 (match_operand:SF 1 "const0_operand" "")))]
764 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
765 "ltebr\\t%0,%0"
766 [(set_attr "op_type" "RRE")])
767
768 (define_insn "*cmpsf_ccs_0_ibm"
769 [(set (reg 33)
770 (compare (match_operand:SF 0 "register_operand" "f")
771 (match_operand:SF 1 "const0_operand" "")))]
772 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
773 "lter\\t%0,%0"
774 [(set_attr "op_type" "RR")])
775
776 (define_insn "*cmpsf_ccs"
777 [(set (reg 33)
778 (compare (match_operand:SF 0 "register_operand" "f,f")
779 (match_operand:SF 1 "general_operand" "f,m")))]
780 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
781 "@
782 cebr\\t%0,%1
783 ceb\\t%0,%1"
784 [(set_attr "op_type" "RRE,RXE")
785 (set_attr "atype" "reg,mem")])
786
787 (define_insn "*cmpsf_ccs"
788 [(set (reg 33)
789 (compare (match_operand:SF 0 "register_operand" "f,f")
790 (match_operand:SF 1 "general_operand" "f,m")))]
791 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
792 "@
793 cer\\t%0,%1
794 ce\\t%0,%1"
795 [(set_attr "op_type" "RR,RX")
796 (set_attr "atype" "reg,mem")])
797
798
799 ;;
800 ;;- Move instructions.
801 ;;
802
803 ;
804 ; movti instruction pattern(s).
805 ;
806
807 (define_insn "*movti_ss"
808 [(set (match_operand:TI 0 "s_operand" "=Qo")
809 (match_operand:TI 1 "s_imm_operand" "Qo"))]
810 ""
811 "mvc\\t%O0(16,%R0),%1"
812 [(set_attr "op_type" "SS")
813 (set_attr "atype" "mem")])
814
815 (define_insn "movti"
816 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m")
817 (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))]
818 "TARGET_64BIT"
819 "@
820 lmg\\t%0,%N0,%1
821 stmg\\t%1,%N1,%0
822 #
823 #"
824 [(set_attr "op_type" "RSE,RSE,NN,NN")
825 (set_attr "atype" "mem")])
826
827 (define_split
828 [(set (match_operand:TI 0 "nonimmediate_operand" "")
829 (match_operand:TI 1 "general_operand" ""))]
830 "TARGET_64BIT && reload_completed
831 && !s_operand (operands[0], VOIDmode)
832 && !s_operand (operands[1], VOIDmode)
833 && (register_operand (operands[0], VOIDmode)
834 || register_operand (operands[1], VOIDmode))
835 && (!register_operand (operands[0], VOIDmode)
836 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
837 operands[1])
838 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
839 operands[1]))"
840 [(set (match_dup 2) (match_dup 4))
841 (set (match_dup 3) (match_dup 5))]
842 "
843 {
844 if (!register_operand (operands[0], VOIDmode)
845 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
846 operands[1]))
847 {
848 operands[2] = operand_subword (operands[0], 0, 0, TImode);
849 operands[3] = operand_subword (operands[0], 1, 0, TImode);
850 operands[4] = operand_subword (operands[1], 0, 0, TImode);
851 operands[5] = operand_subword (operands[1], 1, 0, TImode);
852 }
853 else
854 {
855 operands[2] = operand_subword (operands[0], 1, 0, TImode);
856 operands[3] = operand_subword (operands[0], 0, 0, TImode);
857 operands[4] = operand_subword (operands[1], 1, 0, TImode);
858 operands[5] = operand_subword (operands[1], 0, 0, TImode);
859 }
860 }")
861
862 (define_split
863 [(set (match_operand:TI 0 "register_operand" "")
864 (match_operand:TI 1 "memory_operand" ""))]
865 "TARGET_64BIT && reload_completed
866 && !s_operand (operands[1], VOIDmode)"
867 [(set (match_dup 2) (match_dup 3))
868 (set (match_dup 0) (mem:TI (match_dup 2)))]
869 "operands[2] = operand_subword (operands[0], 1, 0, TImode);
870 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
871
872 ;
873 ; movdi instruction pattern(s).
874 ;
875
876 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
877 ;; move to get the address of the symbolic object from the GOT.
878
879 (define_expand "movdi"
880 [(set (match_operand:DI 0 "general_operand" "")
881 (match_operand:DI 1 "general_operand" ""))]
882 ""
883 "
884 {
885 /* Handle PIC symbolic constants. */
886 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
887 emit_pic_move (operands, DImode);
888
889 /* During and after reload, we need to force constants
890 to the literal pool ourselves, if necessary. */
891 if ((reload_in_progress || reload_completed)
892 && CONSTANT_P (operands[1])
893 && (!legitimate_reload_constant_p (operands[1])
894 || fp_operand (operands[0], VOIDmode)))
895 operands[1] = force_const_mem (DImode, operands[1]);
896 }")
897
898 (define_insn "*movdi_lhi"
899 [(set (match_operand:DI 0 "register_operand" "=d")
900 (match_operand:DI 1 "immediate_operand" "K"))]
901 "TARGET_64BIT
902 && GET_CODE (operands[1]) == CONST_INT
903 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
904 && !fp_operand (operands[0], VOIDmode)"
905 "lghi\\t%0,%h1"
906 [(set_attr "op_type" "RI")
907 (set_attr "atype" "reg")])
908
909 (define_insn "*movdi_lli"
910 [(set (match_operand:DI 0 "register_operand" "=d")
911 (match_operand:DI 1 "immediate_operand" "n"))]
912 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
913 && !fp_operand (operands[0], VOIDmode)"
914 "*
915 {
916 int part = s390_single_hi (operands[1], DImode, 0);
917 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
918
919 switch (part)
920 {
921 case 0: return \"llihh\\t%0,%x1\";
922 case 1: return \"llihl\\t%0,%x1\";
923 case 2: return \"llilh\\t%0,%x1\";
924 case 3: return \"llill\\t%0,%x1\";
925 default: abort ();
926 }
927 }"
928 [(set_attr "op_type" "RI")
929 (set_attr "atype" "reg")])
930
931 (define_insn "*movdi_larl"
932 [(set (match_operand:DI 0 "register_operand" "=d")
933 (match_operand:DI 1 "larl_operand" "X"))]
934 "TARGET_64BIT
935 && !fp_operand (operands[0], VOIDmode)"
936 "larl\\t%0,%1"
937 [(set_attr "op_type" "RIL")
938 (set_attr "atype" "reg")
939 (set_attr "type" "la")])
940
941 (define_insn "*movdi_ss"
942 [(set (match_operand:DI 0 "s_operand" "=Qo")
943 (match_operand:DI 1 "s_imm_operand" "Qo"))]
944 ""
945 "mvc\\t%O0(8,%R0),%1"
946 [(set_attr "op_type" "SS")
947 (set_attr "atype" "mem")])
948
949 (define_insn "*movdi_64"
950 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
951 (match_operand:DI 1 "general_operand" "d,m,d,f,m,f"))]
952 "TARGET_64BIT"
953 "@
954 lgr\\t%0,%1
955 lg\\t%0,%1
956 stg\\t%1,%0
957 ldr\\t%0,%1
958 ld\\t%0,%1
959 std\\t%1,%0"
960 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX")
961 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
962
963 (define_insn "*movdi_31"
964 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,f,f,m")
965 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,f,m,f"))]
966 "!TARGET_64BIT"
967 "@
968 lm\\t%0,%N0,%1
969 stm\\t%1,%N1,%0
970 #
971 #
972 ldr\\t%0,%1
973 ld\\t%0,%1
974 std\\t%1,%0"
975 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX")
976 (set_attr "atype" "mem,mem,*,*,reg,mem,mem")])
977
978 (define_split
979 [(set (match_operand:DI 0 "nonimmediate_operand" "")
980 (match_operand:DI 1 "general_operand" ""))]
981 "!TARGET_64BIT && reload_completed
982 && !fp_operand (operands[0], VOIDmode)
983 && !fp_operand (operands[1], VOIDmode)
984 && !s_operand (operands[0], VOIDmode)
985 && !s_operand (operands[1], VOIDmode)
986 && (register_operand (operands[0], VOIDmode)
987 || register_operand (operands[1], VOIDmode))
988 && (!register_operand (operands[0], VOIDmode)
989 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
990 operands[1])
991 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
992 operands[1]))"
993 [(set (match_dup 2) (match_dup 4))
994 (set (match_dup 3) (match_dup 5))]
995 "
996 {
997 if (!register_operand (operands[0], VOIDmode)
998 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
999 operands[1]))
1000 {
1001 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1002 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1003 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1004 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1005 }
1006 else
1007 {
1008 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1009 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1010 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1011 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1012 }
1013 }")
1014
1015 (define_split
1016 [(set (match_operand:DI 0 "register_operand" "")
1017 (match_operand:DI 1 "memory_operand" ""))]
1018 "!TARGET_64BIT && reload_completed
1019 && !fp_operand (operands[0], VOIDmode)
1020 && !fp_operand (operands[1], VOIDmode)
1021 && !s_operand (operands[1], VOIDmode)"
1022 [(set (match_dup 2) (match_dup 3))
1023 (set (match_dup 0) (mem:DI (match_dup 2)))]
1024 "operands[2] = operand_subword (operands[0], 1, 0, DImode);
1025 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1026
1027 ;
1028 ; movsi instruction pattern(s).
1029 ;
1030
1031 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1032 ;; move to get the address of the symbolic object from the GOT.
1033
1034 (define_expand "movsi"
1035 [(set (match_operand:SI 0 "general_operand" "")
1036 (match_operand:SI 1 "general_operand" ""))]
1037 ""
1038 "
1039 {
1040 /* Handle PIC symbolic constants. */
1041 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1042 emit_pic_move (operands, SImode);
1043
1044 /* expr.c tries to load an effective address using
1045 force_reg. This fails because we don't have a
1046 generic load_address pattern. Convert the move
1047 to a proper arithmetic operation instead, unless
1048 it is guaranteed to be OK. */
1049 if (GET_CODE (operands[1]) == PLUS
1050 && !legitimate_la_operand_p (operands[1]))
1051 {
1052 operands[1] = force_operand (operands[1], operands[0]);
1053 if (operands[1] == operands[0])
1054 DONE;
1055 }
1056
1057 /* During and after reload, we need to force constants
1058 to the literal pool ourselves, if necessary. */
1059 if ((reload_in_progress || reload_completed)
1060 && CONSTANT_P (operands[1])
1061 && (!legitimate_reload_constant_p (operands[1])
1062 || fp_operand (operands[0], VOIDmode)))
1063 operands[1] = force_const_mem (SImode, operands[1]);
1064 }")
1065
1066 (define_insn "*movsi_lhi"
1067 [(set (match_operand:SI 0 "register_operand" "=d")
1068 (match_operand:SI 1 "immediate_operand" "K"))]
1069 "GET_CODE (operands[1]) == CONST_INT
1070 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1071 && !fp_operand (operands[0], VOIDmode)"
1072 "lhi\\t%0,%h1"
1073 [(set_attr "op_type" "RI")])
1074
1075 (define_insn "*movsi_lli"
1076 [(set (match_operand:SI 0 "register_operand" "=d")
1077 (match_operand:SI 1 "immediate_operand" "n"))]
1078 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1079 && !fp_operand (operands[0], VOIDmode)"
1080 "*
1081 {
1082 int part = s390_single_hi (operands[1], SImode, 0);
1083 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1084
1085 switch (part)
1086 {
1087 case 0: return \"llilh\\t%0,%x1\";
1088 case 1: return \"llill\\t%0,%x1\";
1089 default: abort ();
1090 }
1091 }"
1092 [(set_attr "op_type" "RI")])
1093
1094 (define_insn "*movsi_ss"
1095 [(set (match_operand:SI 0 "s_operand" "=Qo")
1096 (match_operand:SI 1 "s_imm_operand" "Qo"))]
1097 ""
1098 "mvc\\t%O0(4,%R0),%1"
1099 [(set_attr "op_type" "SS")
1100 (set_attr "atype" "mem")])
1101
1102 (define_insn "*movsi"
1103 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,f,f,m")
1104 (match_operand:SI 1 "general_operand" "d,m,d,f,m,f"))]
1105 ""
1106 "@
1107 lr\\t%0,%1
1108 l\\t%0,%1
1109 st\\t%1,%0
1110 ler\\t%0,%1
1111 le\\t%0,%1
1112 ste\\t%1,%0"
1113 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1114 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1115
1116
1117 ;
1118 ; movhi instruction pattern(s).
1119 ;
1120
1121 (define_insn "movhi"
1122 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
1123 (match_operand:HI 1 "general_operand" "d,n,m,d"))]
1124 ""
1125 "@
1126 lr\\t%0,%1
1127 lhi\\t%0,%h1
1128 lh\\t%0,%1
1129 sth\\t%1,%0"
1130 [(set_attr "op_type" "RR,RI,RX,RX")
1131 (set_attr "atype" "reg,reg,mem,mem")])
1132
1133
1134 ;
1135 ; movqi instruction pattern(s).
1136 ;
1137
1138 (define_insn "movqi_64"
1139 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1140 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1141 "TARGET_64BIT"
1142 "@
1143 lr\\t%0,%1
1144 lhi\\t%0,%b1
1145 llgc\\t%0,%1
1146 stc\\t%1,%0
1147 mvi\\t%0,%b1"
1148 [(set_attr "op_type" "RR,RI,RXE,RX,SI")
1149 (set_attr "atype" "reg,reg,mem,mem,mem")])
1150
1151
1152 (define_insn "movqi"
1153 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1154 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1155 ""
1156 "@
1157 lr\\t%0,%1
1158 lhi\\t%0,%b1
1159 ic\\t%0,%1
1160 stc\\t%1,%0
1161 mvi\\t%0,%b1"
1162 [(set_attr "op_type" "RR,RI,RX,RX,SI")
1163 (set_attr "atype" "reg,reg,mem,mem,mem")])
1164
1165
1166 ;
1167 ; moveqstrictqi instruction pattern(s).
1168 ;
1169
1170 (define_insn "*movstrictqi"
1171 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1172 (match_operand:QI 1 "memory_operand" "m"))]
1173 ""
1174 "ic\\t%0,%1"
1175 [(set_attr "op_type" "RX")
1176 (set_attr "atype" "mem")])
1177
1178 ;
1179 ; movstricthi instruction pattern(s).
1180 ;
1181
1182 (define_insn "*movstricthi"
1183 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1184 (match_operand:HI 1 "s_imm_operand" "Qo"))
1185 (clobber (reg:CC 33))]
1186 ""
1187 "icm\\t%0,3,%1"
1188 [(set_attr "op_type" "RS")
1189 (set_attr "atype" "mem")])
1190
1191
1192 ;
1193 ; movstrictsi instruction pattern(s).
1194 ;
1195
1196 (define_insn "movestrictsi"
1197 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1198 (match_operand:SI 1 "general_operand" "d,m"))]
1199 "TARGET_64BIT"
1200 "@
1201 lr\\t%0,%1
1202 l\\t%0,%1"
1203 [(set_attr "op_type" "RR,RS")
1204 (set_attr "atype" "reg,mem")])
1205
1206
1207 ;
1208 ; movdf instruction pattern(s).
1209 ;
1210
1211 (define_expand "movdf"
1212 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1213 (match_operand:DF 1 "general_operand" ""))]
1214 ""
1215 "
1216 {
1217 /* During and after reload, we need to force constants
1218 to the literal pool ourselves, if necessary. */
1219 if ((reload_in_progress || reload_completed)
1220 && CONSTANT_P (operands[1]))
1221 operands[1] = force_const_mem (DFmode, operands[1]);
1222 }")
1223
1224 (define_insn "*movdf_ss"
1225 [(set (match_operand:DF 0 "s_operand" "=Qo")
1226 (match_operand:DF 1 "s_imm_operand" "Qo"))]
1227 ""
1228 "mvc\\t%O0(8,%R0),%1"
1229 [(set_attr "op_type" "SS")
1230 (set_attr "atype" "mem")])
1231
1232 (define_insn "*movdf_64"
1233 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1234 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d"))]
1235 "TARGET_64BIT"
1236 "@
1237 ldr\\t%0,%1
1238 ld\\t%0,%1
1239 std\\t%1,%0
1240 lgr\\t%0,%1
1241 lg\\t%0,%1
1242 stg\\t%1,%0"
1243 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE")
1244 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1245
1246 (define_insn "*movdf_31"
1247 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m")
1248 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d"))]
1249 "!TARGET_64BIT"
1250 "@
1251 ldr\\t%0,%1
1252 ld\\t%0,%1
1253 std\\t%1,%0
1254 lm\\t%0,%N0,%1
1255 stm\\t%1,%N1,%0
1256 #
1257 #"
1258 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN")
1259 (set_attr "atype" "reg,mem,mem,mem,mem,*,*")])
1260
1261 (define_split
1262 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1263 (match_operand:DF 1 "general_operand" ""))]
1264 "!TARGET_64BIT && reload_completed
1265 && !fp_operand (operands[0], VOIDmode)
1266 && !fp_operand (operands[1], VOIDmode)
1267 && !s_operand (operands[0], VOIDmode)
1268 && !s_operand (operands[1], VOIDmode)
1269 && (register_operand (operands[0], VOIDmode)
1270 || register_operand (operands[1], VOIDmode))
1271 && (!register_operand (operands[0], VOIDmode)
1272 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1273 operands[1])
1274 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1275 operands[1]))"
1276 [(set (match_dup 2) (match_dup 4))
1277 (set (match_dup 3) (match_dup 5))]
1278 "
1279 {
1280 if (!register_operand (operands[0], VOIDmode)
1281 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1282 operands[1]))
1283 {
1284 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1285 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1286 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1287 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1288 }
1289 else
1290 {
1291 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1292 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1293 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1294 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1295 }
1296 }")
1297
1298 (define_split
1299 [(set (match_operand:DF 0 "register_operand" "")
1300 (match_operand:DF 1 "memory_operand" ""))]
1301 "!TARGET_64BIT && reload_completed
1302 && !fp_operand (operands[0], VOIDmode)
1303 && !fp_operand (operands[1], VOIDmode)
1304 && !s_operand (operands[1], VOIDmode)"
1305 [(set (match_dup 2) (match_dup 3))
1306 (set (match_dup 0) (mem:DI (match_dup 2)))]
1307 "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1308 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1309
1310 ;
1311 ; movsf instruction pattern(s).
1312 ;
1313
1314 (define_expand "movsf"
1315 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1316 (match_operand:SF 1 "general_operand" ""))]
1317 ""
1318 "
1319 {
1320 /* During and after reload, we need to force constants
1321 to the literal pool ourselves, if necessary. */
1322 if ((reload_in_progress || reload_completed)
1323 && CONSTANT_P (operands[1]))
1324 operands[1] = force_const_mem (SFmode, operands[1]);
1325 }")
1326
1327 (define_insn "*movsf_ss"
1328 [(set (match_operand:SF 0 "s_operand" "=Qo")
1329 (match_operand:SF 1 "s_imm_operand" "Qo"))]
1330 ""
1331 "mvc\\t%O0(4,%R0),%1"
1332 [(set_attr "op_type" "SS")
1333 (set_attr "atype" "mem")])
1334
1335 (define_insn "*movsf"
1336 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1337 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d"))]
1338 ""
1339 "@
1340 ler\\t%0,%1
1341 le\\t%0,%1
1342 ste\\t%1,%0
1343 lr\\t%0,%1
1344 l\\t%0,%1
1345 st\\t%1,%0"
1346 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1347 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1348
1349 ;
1350 ; load_multiple pattern(s).
1351 ;
1352
1353 (define_expand "load_multiple"
1354 [(match_par_dup 3 [(set (match_operand 0 "" "")
1355 (match_operand 1 "" ""))
1356 (use (match_operand 2 "" ""))])]
1357 ""
1358 "
1359 {
1360 int regno;
1361 int count;
1362 rtx from;
1363 int i, off;
1364
1365 /* Support only loading a constant number of fixed-point registers from
1366 memory and only bother with this if more than two */
1367 if (GET_CODE (operands[2]) != CONST_INT
1368 || INTVAL (operands[2]) < 2
1369 || INTVAL (operands[2]) > 16
1370 || GET_CODE (operands[1]) != MEM
1371 || GET_CODE (operands[0]) != REG
1372 || REGNO (operands[0]) >= 16)
1373 FAIL;
1374
1375 count = INTVAL (operands[2]);
1376 regno = REGNO (operands[0]);
1377
1378 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1379 if (no_new_pseudos)
1380 {
1381 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1382 {
1383 from = XEXP (operands[1], 0);
1384 off = 0;
1385 }
1386 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1387 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1388 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1389 {
1390 from = XEXP (XEXP (operands[1], 0), 0);
1391 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1392 }
1393 else
1394 FAIL;
1395
1396 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1397 FAIL;
1398 }
1399 else
1400 {
1401 from = force_reg (Pmode, XEXP (operands[1], 0));
1402 off = 0;
1403 }
1404
1405 for (i = 0; i < count; i++)
1406 XVECEXP (operands[3], 0, i)
1407 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1408 change_address (operands[1], Pmode,
1409 plus_constant (from,
1410 off + i * UNITS_PER_WORD)));
1411 }")
1412
1413 (define_insn "*load_multiple_di"
1414 [(match_parallel 0 "load_multiple_operation"
1415 [(set (match_operand:DI 1 "register_operand" "=r")
1416 (match_operand:DI 2 "s_operand" "oQ"))])]
1417 ""
1418 "*
1419 {
1420 int words = XVECLEN (operands[0], 0);
1421
1422 if (XVECLEN (operands[0], 0) == 1)
1423 return \"lg\\t%1,0(%2)\";
1424
1425 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1426 return \"lmg\\t%1,%0,%2\";
1427 }"
1428 [(set_attr "op_type" "RXE")
1429 (set_attr "atype" "mem")
1430 (set_attr "type" "lm")])
1431
1432 (define_insn "*load_multiple_si"
1433 [(match_parallel 0 "load_multiple_operation"
1434 [(set (match_operand:SI 1 "register_operand" "=r")
1435 (match_operand:SI 2 "s_operand" "oQ"))])]
1436 ""
1437 "*
1438 {
1439 int words = XVECLEN (operands[0], 0);
1440
1441 if (XVECLEN (operands[0], 0) == 1)
1442 return \"l\\t%1,0(%2)\";
1443
1444 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1445 return \"lm\\t%1,%0,%2\";
1446 }"
1447 [(set_attr "op_type" "RXE")
1448 (set_attr "atype" "mem")
1449 (set_attr "type" "lm")])
1450
1451 ;
1452 ; store multiple pattern(s).
1453 ;
1454
1455 (define_expand "store_multiple"
1456 [(match_par_dup 3 [(set (match_operand 0 "" "")
1457 (match_operand 1 "" ""))
1458 (use (match_operand 2 "" ""))])]
1459 ""
1460 "
1461 {
1462 int regno;
1463 int count;
1464 rtx to;
1465 int i, off;
1466
1467 /* Support only storing a constant number of fixed-point registers to
1468 memory and only bother with this if more than two. */
1469 if (GET_CODE (operands[2]) != CONST_INT
1470 || INTVAL (operands[2]) < 2
1471 || INTVAL (operands[2]) > 16
1472 || GET_CODE (operands[0]) != MEM
1473 || GET_CODE (operands[1]) != REG
1474 || REGNO (operands[1]) >= 16)
1475 FAIL;
1476
1477 count = INTVAL (operands[2]);
1478 regno = REGNO (operands[1]);
1479
1480 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1481
1482 if (no_new_pseudos)
1483 {
1484 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1485 {
1486 to = XEXP (operands[0], 0);
1487 off = 0;
1488 }
1489 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1490 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1491 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1492 {
1493 to = XEXP (XEXP (operands[0], 0), 0);
1494 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1495 }
1496 else
1497 FAIL;
1498
1499 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1500 FAIL;
1501 }
1502 else
1503 {
1504 to = force_reg (Pmode, XEXP (operands[0], 0));
1505 off = 0;
1506 }
1507
1508 for (i = 0; i < count; i++)
1509 XVECEXP (operands[3], 0, i)
1510 = gen_rtx_SET (VOIDmode,
1511 change_address (operands[0], Pmode,
1512 plus_constant (to,
1513 off + i * UNITS_PER_WORD)),
1514 gen_rtx_REG (Pmode, regno + i));
1515 }")
1516
1517 (define_insn "*store_multiple_di"
1518 [(match_parallel 0 "store_multiple_operation"
1519 [(set (match_operand:DI 1 "s_operand" "=oQ")
1520 (match_operand:DI 2 "register_operand" "r"))])]
1521 ""
1522 "*
1523 {
1524 int words = XVECLEN (operands[0], 0);
1525
1526 if (XVECLEN (operands[0], 0) == 1)
1527 return \"stg\\t%1,0(%2)\";
1528
1529 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1530 return \"stmg\\t%2,%0,%1\";
1531 }"
1532 [(set_attr "op_type" "RXE")
1533 (set_attr "atype" "mem")
1534 (set_attr "type" "stm")])
1535
1536
1537 (define_insn "*store_multiple_si"
1538 [(match_parallel 0 "store_multiple_operation"
1539 [(set (match_operand:SI 1 "s_operand" "=oQ")
1540 (match_operand:SI 2 "register_operand" "r"))])]
1541 ""
1542 "*
1543 {
1544 int words = XVECLEN (operands[0], 0);
1545
1546 if (XVECLEN (operands[0], 0) == 1)
1547 return \"st\\t%1,0(%2)\";
1548
1549 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1550 return \"stm\\t%2,%0,%1\";
1551 }"
1552 [(set_attr "op_type" "RXE")
1553 (set_attr "atype" "mem")
1554 (set_attr "type" "stm")])
1555
1556 ;;
1557 ;; String instructions.
1558 ;;
1559
1560 ;
1561 ; movstrdi instruction pattern(s).
1562 ;
1563
1564 (define_expand "movstrdi"
1565 [(set (match_operand:BLK 0 "general_operand" "")
1566 (match_operand:BLK 1 "general_operand" ""))
1567 (use (match_operand:DI 2 "general_operand" ""))
1568 (match_operand 3 "" "")]
1569 "TARGET_64BIT"
1570 "
1571 {
1572 rtx addr0, addr1;
1573
1574 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1575 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1576
1577 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1578 {
1579 operands[0] = change_address (operands[0], VOIDmode, addr0);
1580 operands[1] = change_address (operands[1], VOIDmode, addr1);
1581 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1582
1583 emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2]));
1584 DONE;
1585 }
1586 else
1587 {
1588 if (TARGET_MVCLE)
1589 {
1590 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1591 rtx reg0 = gen_reg_rtx (TImode);
1592 rtx reg1 = gen_reg_rtx (TImode);
1593 rtx len = operands[2];
1594
1595 if (! CONSTANT_P (len))
1596 len = force_reg (DImode, len);
1597
1598 /* Load up the address+length pairs. */
1599
1600 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1601 emit_move_insn (gen_lowpart (DImode, reg0), len);
1602
1603 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1604 emit_move_insn (gen_lowpart (DImode, reg1), len);
1605
1606 /* MOVE */
1607 emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1608 DONE;
1609 }
1610 else
1611 {
1612 rtx label1 = gen_label_rtx ();
1613 rtx label2 = gen_label_rtx ();
1614 rtx reg0, reg1, len, blocks;
1615
1616 reg0 = gen_reg_rtx (DImode);
1617 reg1 = gen_reg_rtx (DImode);
1618 len = gen_reg_rtx (DImode);
1619 blocks = gen_reg_rtx (DImode);
1620
1621 emit_move_insn (len, operands[2]);
1622 emit_insn (gen_cmpdi (len, const0_rtx));
1623 emit_jump_insn (gen_beq (label1));
1624 emit_move_insn (reg0, addr0);
1625 emit_move_insn (reg1, addr1);
1626 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1627 emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8)));
1628 emit_insn (gen_cmpdi (blocks, const0_rtx));
1629 emit_jump_insn (gen_beq (label2));
1630 emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1631 emit_label (label2);
1632 operands[0] = change_address (operands[0], VOIDmode, reg0);
1633 operands[1] = change_address (operands[1], VOIDmode, reg1);
1634 emit_insn (gen_movstrdi_short (operands[0], operands[1], len));
1635 emit_label (label1);
1636 DONE;
1637 }
1638 }
1639 }")
1640
1641 ;
1642 ; movstrsi instruction pattern(s).
1643 ;
1644
1645 (define_expand "movstrsi"
1646 [(set (match_operand:BLK 0 "general_operand" "")
1647 (match_operand:BLK 1 "general_operand" ""))
1648 (use (match_operand:SI 2 "general_operand" ""))
1649 (match_operand 3 "" "")]
1650 "!TARGET_64BIT"
1651 "
1652 {
1653 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1654 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1655
1656 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1657 {
1658 operands[0] = change_address (operands[0], VOIDmode, addr0);
1659 operands[1] = change_address (operands[1], VOIDmode, addr1);
1660 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1661
1662 emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2]));
1663 DONE;
1664 }
1665 else
1666 {
1667 if (TARGET_MVCLE)
1668 {
1669 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1670 rtx reg0 = gen_reg_rtx (DImode);
1671 rtx reg1 = gen_reg_rtx (DImode);
1672 rtx len = operands[2];
1673
1674
1675 if (! CONSTANT_P (len))
1676 len = force_reg (SImode, len);
1677
1678 /* Load up the address+length pairs. */
1679
1680 emit_move_insn (gen_highpart (SImode, reg0), addr0);
1681 emit_move_insn (gen_lowpart (SImode, reg0), len);
1682
1683 emit_move_insn (gen_highpart (SImode, reg1), addr1);
1684 emit_move_insn (gen_lowpart (SImode, reg1), len);
1685
1686 /* MOVE */
1687 emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1688 DONE;
1689 }
1690 else
1691 {
1692 rtx label1 = gen_label_rtx ();
1693 rtx label2 = gen_label_rtx ();
1694 rtx reg0, reg1, len, blocks;
1695
1696 reg0 = gen_reg_rtx (SImode);
1697 reg1 = gen_reg_rtx (SImode);
1698 len = gen_reg_rtx (SImode);
1699 blocks = gen_reg_rtx (SImode);
1700
1701 emit_move_insn (len, operands[2]);
1702 emit_insn (gen_cmpsi (len, const0_rtx));
1703 emit_jump_insn (gen_beq (label1));
1704 emit_move_insn (reg0, addr0);
1705 emit_move_insn (reg1, addr1);
1706 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1707 emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8)));
1708 emit_insn (gen_cmpsi (blocks, const0_rtx));
1709 emit_jump_insn (gen_beq (label2));
1710 emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1711 emit_label (label2);
1712 operands[0] = change_address (operands[0], VOIDmode, reg0);
1713 operands[1] = change_address (operands[1], VOIDmode, reg1);
1714 emit_insn (gen_movstrsi_short (operands[0], operands[1], len));
1715 emit_label (label1);
1716 DONE;
1717 }
1718 }
1719 }")
1720
1721 ; Move a block that is up to 256 bytes in length.
1722 ; The block length is taken as (operands[2] % 256) + 1.
1723
1724 (define_insn "movstrdi_short"
1725 [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
1726 (match_operand:BLK 1 "s_operand" "oQ,oQ"))
1727 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1728 (clobber (match_scratch:DI 3 "=X,&a"))]
1729 "TARGET_64BIT"
1730 "*
1731 {
1732 switch (which_alternative)
1733 {
1734 case 0:
1735 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1736
1737 case 1:
1738 output_asm_insn (\"bras\\t%3,.+10\", operands);
1739 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1740 return \"ex\\t%2,0(%3)\";
1741
1742 default:
1743 abort ();
1744 }
1745 }"
1746 [(set_attr "op_type" "SS,NN")
1747 (set_attr "atype" "mem,mem")
1748 (set_attr "length" "*,14")])
1749
1750 (define_insn "movstrsi_short"
1751 [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
1752 (match_operand:BLK 1 "s_operand" "oQ,oQ"))
1753 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1754 (clobber (match_scratch:SI 3 "=X,&a"))]
1755 "!TARGET_64BIT"
1756 "*
1757 {
1758 switch (which_alternative)
1759 {
1760 case 0:
1761 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1762
1763 case 1:
1764 output_asm_insn (\"bras\\t%3,.+10\", operands);
1765 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1766 return \"ex\\t%2,0(%3)\";
1767
1768 default:
1769 abort ();
1770 }
1771 }"
1772 [(set_attr "op_type" "SS,NN")
1773 (set_attr "atype" "mem,mem")
1774 (set_attr "length" "*,14")])
1775
1776 ; Move a block that is a multiple of 256 bytes in length
1777
1778 (define_insn "movstrdi_long"
1779 [(set (match_operand:DI 4 "register_operand" "=d")
1780 (const_int 0))
1781 (set (match_operand:DI 0 "register_operand" "=a")
1782 (plus:DI (match_operand:DI 2 "register_operand" "0")
1783 (ashift:DI (match_operand:DI 5 "register_operand" "4")
1784 (const_int 8))))
1785 (set (match_operand:DI 1 "register_operand" "=a")
1786 (plus:DI (match_operand:DI 3 "register_operand" "1")
1787 (ashift:DI (match_dup 5) (const_int 8))))
1788 (set (mem:BLK (match_dup 2))
1789 (mem:BLK (match_dup 3)))
1790 (use (match_dup 5))]
1791 "TARGET_64BIT"
1792 "*
1793 {
1794 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1795 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1796 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1797 return \"brct\\t%4,.-14\";
1798 }"
1799 [(set_attr "op_type" "NN")
1800 (set_attr "atype" "mem")
1801 (set_attr "length" "18")])
1802
1803 (define_insn "movstrsi_long"
1804 [(set (match_operand:SI 4 "register_operand" "=d")
1805 (const_int 0))
1806 (set (match_operand:SI 0 "register_operand" "=a")
1807 (plus:SI (match_operand:SI 2 "register_operand" "0")
1808 (ashift:SI (match_operand:SI 5 "register_operand" "4")
1809 (const_int 8))))
1810 (set (match_operand:SI 1 "register_operand" "=a")
1811 (plus:SI (match_operand:SI 3 "register_operand" "1")
1812 (ashift:SI (match_dup 5) (const_int 8))))
1813 (set (mem:BLK (match_dup 2))
1814 (mem:BLK (match_dup 3)))
1815 (use (match_dup 5))]
1816 "!TARGET_64BIT"
1817 "*
1818 {
1819 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1820 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1821 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1822 return \"brct\\t%4,.-14\";
1823 }"
1824 [(set_attr "op_type" "NN")
1825 (set_attr "atype" "mem")
1826 (set_attr "length" "18")])
1827
1828 ; Move a block that is larger than 255 bytes in length.
1829
1830 (define_insn "movstrdi_64"
1831 [(set (match_operand:TI 0 "register_operand" "=d")
1832 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1833 (lshiftrt:TI (match_dup 2) (const_int 64)))
1834 (const_int 64)))
1835 (set (match_operand:TI 1 "register_operand" "=d")
1836 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1837 (lshiftrt:TI (match_dup 3) (const_int 64)))
1838 (const_int 64)))
1839 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1840 (mem:BLK (subreg:DI (match_dup 3) 0)))
1841 (clobber (reg:CC 33))]
1842 "TARGET_64BIT"
1843 "mvcle\\t%0,%1,0\;jo\\t.-4"
1844 [(set_attr "op_type" "NN")
1845 (set_attr "atype" "mem")
1846 (set_attr "length" "8")])
1847
1848 (define_insn "movstrsi_31"
1849 [(set (match_operand:DI 0 "register_operand" "=d")
1850 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1851 (lshiftrt:DI (match_dup 2) (const_int 32)))
1852 (const_int 32)))
1853 (set (match_operand:DI 1 "register_operand" "=d")
1854 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1855 (lshiftrt:DI (match_dup 3) (const_int 32)))
1856 (const_int 32)))
1857 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1858 (mem:BLK (subreg:SI (match_dup 3) 0)))
1859 (clobber (reg:CC 33))]
1860 "!TARGET_64BIT"
1861 "mvcle\\t%0,%1,0\;jo\\t.-4"
1862 [(set_attr "op_type" "NN")
1863 (set_attr "atype" "mem")
1864 (set_attr "length" "8")])
1865
1866 ;
1867 ; clrstrdi instruction pattern(s).
1868 ;
1869
1870 (define_expand "clrstrdi"
1871 [(set (match_operand:BLK 0 "general_operand" "")
1872 (const_int 0))
1873 (use (match_operand:DI 1 "general_operand" ""))
1874 (match_operand 2 "" "")]
1875 "TARGET_64BIT"
1876 "
1877 {
1878 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1879
1880 operands[0] = change_address (operands[0], VOIDmode, addr);
1881
1882 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1883 {
1884 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1885 DONE;
1886 }
1887 else
1888 {
1889 rtx reg0 = gen_reg_rtx (TImode);
1890 rtx reg1 = gen_reg_rtx (TImode);
1891 rtx len = operands[1];
1892
1893 if (! CONSTANT_P (len))
1894 len = force_reg (DImode, len);
1895
1896 /* Load up the address+length pairs. */
1897
1898 emit_move_insn (gen_highpart (DImode, reg0), addr);
1899 emit_move_insn (gen_lowpart (DImode, reg0), len);
1900
1901 emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1902
1903 /* Clear! */
1904 emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0));
1905 DONE;
1906 }
1907 }")
1908
1909 ;
1910 ; clrstrsi instruction pattern(s).
1911 ;
1912
1913 (define_expand "clrstrsi"
1914 [(set (match_operand:BLK 0 "general_operand" "")
1915 (const_int 0))
1916 (use (match_operand:SI 1 "general_operand" ""))
1917 (match_operand 2 "" "")]
1918 "!TARGET_64BIT"
1919 "
1920 {
1921 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1922
1923 operands[0] = change_address (operands[0], VOIDmode, addr);
1924
1925 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1926 {
1927 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1928 DONE;
1929 }
1930 else
1931 {
1932 rtx reg0 = gen_reg_rtx (DImode);
1933 rtx reg1 = gen_reg_rtx (DImode);
1934 rtx len = operands[1];
1935
1936 if (! CONSTANT_P (len))
1937 len = force_reg (SImode, len);
1938
1939 /* Load up the address+length pairs. */
1940
1941 emit_move_insn (gen_highpart (SImode, reg0), addr);
1942 emit_move_insn (gen_lowpart (SImode, reg0), len);
1943
1944 emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1945
1946 /* CLear! */
1947 emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0));
1948 DONE;
1949 }
1950 }")
1951
1952 ; Clear memory with length less than 256 bytes
1953
1954 (define_insn "clrstrsico"
1955 [(set (match_operand:BLK 0 "s_operand" "=Qo")
1956 (const_int 0))
1957 (use (match_operand 1 "immediate_operand" "I"))
1958 (clobber (reg:CC 33))]
1959 ""
1960 "xc\\t%O0(%1,%R0),%0"
1961 [(set_attr "op_type" "RS")
1962 (set_attr "type" "cs")
1963 (set_attr "atype" "mem")])
1964
1965 ; Clear memory with length greater 256 bytes or lenght not constant
1966
1967 (define_insn "clrstrsi_64"
1968 [(set (match_operand:TI 0 "register_operand" "=d")
1969 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1970 (lshiftrt:TI (match_dup 2) (const_int 64)))
1971 (const_int 64)))
1972 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1973 (const_int 0))
1974 (use (match_operand:TI 1 "register_operand" "d"))
1975 (clobber (reg:CC 33))]
1976 "TARGET_64BIT"
1977 "mvcle\\t%0,%1,0\;jo\\t.-4"
1978 [(set_attr "op_type" "NN")
1979 (set_attr "atype" "mem")
1980 (set_attr "type" "vs")
1981 (set_attr "length" "8")])
1982
1983 (define_insn "clrstrsi_31"
1984 [(set (match_operand:DI 0 "register_operand" "=d")
1985 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1986 (lshiftrt:DI (match_dup 2) (const_int 32)))
1987 (const_int 32)))
1988 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1989 (const_int 0))
1990 (use (match_operand:DI 1 "register_operand" "d"))
1991 (clobber (reg:CC 33))]
1992 "!TARGET_64BIT"
1993 "mvcle\\t%0,%1,0\;jo\\t.-4"
1994 [(set_attr "op_type" "NN")
1995 (set_attr "atype" "mem")
1996 (set_attr "type" "vs")
1997 (set_attr "length" "8")])
1998
1999 ;
2000 ; cmpstrdi instruction pattern(s).
2001 ;
2002
2003 (define_expand "cmpstrdi"
2004 [(set (match_operand:DI 0 "register_operand" "")
2005 (compare:DI (match_operand:BLK 1 "s_operand" "")
2006 (match_operand:BLK 2 "s_operand" "") ) )
2007 (use (match_operand:DI 3 "general_operand" ""))
2008 (use (match_operand:DI 4 "" ""))]
2009 "TARGET_64BIT"
2010 "
2011 {
2012 rtx addr0, addr1;
2013
2014 /* for pre/post increment */
2015 operands[1] = protect_from_queue (operands[1], 0);
2016 operands[2] = protect_from_queue (operands[2], 0);
2017 operands[3] = protect_from_queue (operands[3], 0);
2018
2019 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2020 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2021
2022 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2023 {
2024 if (INTVAL (operands[3]) == 0) {
2025 emit_move_insn (operands[0], operands[3]);
2026 DONE;
2027 }
2028
2029 operands[1] = change_address (operands[1], VOIDmode, addr0);
2030 operands[2] = change_address (operands[2], VOIDmode, addr1);
2031
2032 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2033 emit_insn (gen_cmpint_di (operands[0]));
2034 DONE;
2035 }
2036 else
2037 {
2038 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2039 rtx reg0 = gen_reg_rtx (TImode);
2040 rtx reg1 = gen_reg_rtx (TImode);
2041 rtx len = operands[3];
2042
2043 if (! CONSTANT_P (len))
2044 len = force_reg (DImode, len);
2045
2046 /* Load up the address+length pairs. */
2047 emit_move_insn (gen_highpart (DImode, reg0), addr0);
2048 emit_move_insn (gen_lowpart (DImode, reg0), len);
2049
2050 emit_move_insn (gen_highpart (DImode, reg1), addr1);
2051 emit_move_insn (gen_lowpart (DImode, reg1), len);
2052
2053 /* Compare! */
2054 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2055 emit_insn (gen_cmpint_di (operands[0]));
2056 DONE;
2057 }
2058 }")
2059
2060 ;
2061 ; cmpstrsi instruction pattern(s).
2062 ;
2063
2064 (define_expand "cmpstrsi"
2065 [(set (match_operand:SI 0 "register_operand" "")
2066 (compare:SI (match_operand:BLK 1 "s_operand" "")
2067 (match_operand:BLK 2 "s_operand" "") ) )
2068 (use (match_operand:SI 3 "general_operand" ""))
2069 (use (match_operand:SI 4 "" ""))]
2070 ""
2071 "
2072 {
2073 rtx addr0, addr1;
2074
2075 /* for pre/post increment */
2076 operands[1] = protect_from_queue (operands[1], 0);
2077 operands[2] = protect_from_queue (operands[2], 0);
2078 operands[3] = protect_from_queue (operands[3], 0);
2079
2080 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2081 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2082
2083 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2084 {
2085 if (INTVAL (operands[3]) == 0) {
2086 emit_move_insn (operands[0], operands[3]);
2087 DONE;
2088 }
2089
2090 operands[1] = change_address (operands[1], VOIDmode, addr0);
2091 operands[2] = change_address (operands[2], VOIDmode, addr1);
2092
2093 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2094 emit_insn (gen_cmpint_si (operands[0]));
2095 DONE;
2096 }
2097 else
2098 {
2099 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2100 rtx reg0, reg1;
2101 rtx len = operands[3];
2102
2103 if (TARGET_64BIT)
2104 {
2105 reg0 = gen_reg_rtx (TImode);
2106 reg1 = gen_reg_rtx (TImode);
2107 }
2108 else
2109 {
2110 reg0 = gen_reg_rtx (DImode);
2111 reg1 = gen_reg_rtx (DImode);
2112 }
2113
2114 if (! CONSTANT_P (len))
2115 len = force_reg (Pmode, len);
2116
2117 /* Load up the address+length pairs. */
2118 emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2119 emit_move_insn (gen_lowpart (Pmode, reg0), len);
2120
2121 emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2122 emit_move_insn (gen_lowpart (Pmode, reg1), len);
2123
2124 /* Compare! */
2125 if (TARGET_64BIT)
2126 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2127 else
2128 emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2129
2130 emit_insn (gen_cmpint_si (operands[0]));
2131 DONE;
2132 }
2133 }")
2134
2135 ; Compare a block that is less than 256 bytes in length.
2136
2137 (define_insn "cmpstr_const"
2138 [(set (reg:CCS 33)
2139 (compare:CCS (match_operand:BLK 0 "s_operand" "oQ")
2140 (match_operand:BLK 1 "s_operand" "oQ")))
2141 (use (match_operand 2 "immediate_operand" "I"))]
2142 "(unsigned) INTVAL (operands[2]) < 256"
2143 "clc\\t%O0(%c2,%R0),%1"
2144 [(set_attr "op_type" "SS")
2145 (set_attr "atype" "mem")
2146 (set_attr "type" "cs")])
2147
2148 ; Compare a block that is larger than 255 bytes in length.
2149
2150 (define_insn "cmpstr_64"
2151 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2152 (clobber (match_operand:TI 1 "register_operand" "=d"))
2153 (set (reg:CCS 33)
2154 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2155 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))]
2156 "TARGET_64BIT"
2157 "clcl\\t%0,%1"
2158 [(set_attr "op_type" "RR")
2159 (set_attr "atype" "mem")
2160 (set_attr "type" "vs")])
2161
2162 (define_insn "cmpstr_31"
2163 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2164 (clobber (match_operand:DI 1 "register_operand" "=d"))
2165 (set (reg:CCS 33)
2166 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2167 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))]
2168 "!TARGET_64BIT"
2169 "clcl\\t%0,%1"
2170 [(set_attr "op_type" "RR")
2171 (set_attr "atype" "mem")
2172 (set_attr "type" "vs")])
2173
2174 ; Convert condition code to integer in range (-1, 0, 1)
2175
2176 (define_insn "cmpint_si"
2177 [(set (match_operand:SI 0 "register_operand" "=d")
2178 (compare:SI (reg:CCS 33) (const_int 0)))]
2179 ""
2180 "*
2181 {
2182 output_asm_insn (\"lhi\\t%0,1\", operands);
2183 output_asm_insn (\"jh\\t.+12\", operands);
2184 output_asm_insn (\"jl\\t.+6\", operands);
2185 output_asm_insn (\"sr\\t%0,%0\", operands);
2186 return \"lcr\\t%0,%0\";
2187 }"
2188 [(set_attr "op_type" "NN")
2189 (set_attr "length" "16")
2190 (set_attr "atype" "reg")
2191 (set_attr "type" "other")])
2192
2193 (define_insn "cmpint_di"
2194 [(set (match_operand:DI 0 "register_operand" "=d")
2195 (compare:DI (reg:CCS 33) (const_int 0)))]
2196 "TARGET_64BIT"
2197 "*
2198 {
2199 output_asm_insn (\"lghi\\t%0,1\", operands);
2200 output_asm_insn (\"jh\\t.+12\", operands);
2201 output_asm_insn (\"jl\\t.+6\", operands);
2202 output_asm_insn (\"sgr\\t%0,%0\", operands);
2203 return \"lcgr\\t%0,%0\";
2204 }"
2205 [(set_attr "op_type" "NN")
2206 (set_attr "length" "22")
2207 (set_attr "atype" "reg")
2208 (set_attr "type" "other")])
2209
2210
2211 ;;
2212 ;;- Conversion instructions.
2213 ;;
2214
2215 (define_insn "*sethighqisi"
2216 [(set (match_operand:SI 0 "register_operand" "=d")
2217 (unspec:SI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2218 (clobber (reg:CC 33))]
2219 ""
2220 "icm\\t%0,8,%1"
2221 [(set_attr "op_type" "RS")
2222 (set_attr "atype" "mem")])
2223
2224 (define_insn "*sethighhisi"
2225 [(set (match_operand:SI 0 "register_operand" "=d")
2226 (unspec:SI [(match_operand:HI 1 "s_operand" "Qo")] 10))
2227 (clobber (reg:CC 33))]
2228 ""
2229 "icm\\t%0,12,%1"
2230 [(set_attr "op_type" "RS")
2231 (set_attr "atype" "mem")])
2232
2233 (define_insn "*sethighqidi_64"
2234 [(set (match_operand:DI 0 "register_operand" "=d")
2235 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2236 (clobber (reg:CC 33))]
2237 "TARGET_64BIT"
2238 "icmh\\t%0,8,%1"
2239 [(set_attr "op_type" "RSE")
2240 (set_attr "atype" "mem")])
2241
2242 (define_insn "*sethighqidi_31"
2243 [(set (match_operand:DI 0 "register_operand" "=d")
2244 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2245 (clobber (reg:CC 33))]
2246 "!TARGET_64BIT"
2247 "icm\\t%0,8,%1"
2248 [(set_attr "op_type" "RS")
2249 (set_attr "atype" "mem")])
2250
2251 (define_split
2252 [(set (match_operand:SI 0 "register_operand" "")
2253 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2254 (match_operand 2 "const_int_operand" "")
2255 (const_int 0)))]
2256 "!TARGET_64BIT && !reload_completed
2257 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2258 [(parallel
2259 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2260 (clobber (reg:CC 33))])
2261 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2262 "
2263 {
2264 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2265 operands[1] = change_address (operands[1], QImode, 0);
2266 }")
2267
2268 (define_split
2269 [(set (match_operand:SI 0 "register_operand" "")
2270 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2271 (match_operand 2 "const_int_operand" "")
2272 (const_int 0)))]
2273 "!TARGET_64BIT && !reload_completed
2274 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2275 [(parallel
2276 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2277 (clobber (reg:CC 33))])
2278 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2279 "
2280 {
2281 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2282 operands[1] = change_address (operands[1], HImode, 0);
2283 }")
2284
2285 ;
2286 ; extendsidi2 instruction pattern(s).
2287 ;
2288
2289 (define_expand "extendsidi2"
2290 [(set (match_operand:DI 0 "register_operand" "")
2291 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2292 ""
2293 "
2294 {
2295 if (!TARGET_64BIT)
2296 {
2297 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2298 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2299 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2300 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2301 DONE;
2302 }
2303 }
2304 ")
2305
2306 (define_insn "*extendsidi2"
2307 [(set (match_operand:DI 0 "register_operand" "=d,d")
2308 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2309 "TARGET_64BIT"
2310 "@
2311 lgfr\\t%0,%1
2312 lgf\\t%0,%1"
2313 [(set_attr "op_type" "RRE,RXE")
2314 (set_attr "atype" "reg,mem")])
2315
2316 ;
2317 ; extendhidi2 instruction pattern(s).
2318 ;
2319
2320 (define_expand "extendhidi2"
2321 [(set (match_operand:DI 0 "register_operand" "")
2322 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2323 ""
2324 "
2325 {
2326 if (!TARGET_64BIT)
2327 {
2328 rtx tmp = gen_reg_rtx (SImode);
2329 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2330 emit_insn (gen_extendsidi2 (operands[0], tmp));
2331 DONE;
2332 }
2333 else
2334 {
2335 operands[1] = gen_lowpart (DImode, operands[1]);
2336 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2337 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2338 DONE;
2339 }
2340 }
2341 ")
2342
2343 (define_insn "*extendhidi2"
2344 [(set (match_operand:DI 0 "register_operand" "=d")
2345 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2346 "TARGET_64BIT"
2347 "lgh\\t%0,%1"
2348 [(set_attr "op_type" "RXE")
2349 (set_attr "atype" "mem")])
2350
2351 ;
2352 ; extendqidi2 instruction pattern(s).
2353 ;
2354
2355 (define_expand "extendqidi2"
2356 [(set (match_operand:DI 0 "register_operand" "")
2357 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2358 ""
2359 "
2360 {
2361 if (!TARGET_64BIT)
2362 {
2363 rtx tmp = gen_reg_rtx (SImode);
2364 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2365 emit_insn (gen_extendsidi2 (operands[0], tmp));
2366 DONE;
2367 }
2368 else
2369 {
2370 operands[1] = gen_lowpart (DImode, operands[1]);
2371 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2372 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2373 DONE;
2374 }
2375 }
2376 ")
2377
2378 (define_split
2379 [(set (match_operand:DI 0 "register_operand" "")
2380 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2381 "TARGET_64BIT && !reload_completed"
2382 [(parallel
2383 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2384 (clobber (reg:CC 33))])
2385 (parallel
2386 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2387 (clobber (reg:CC 33))])]
2388 "")
2389
2390 ;
2391 ; extendhisi2 instruction pattern(s).
2392 ;
2393
2394 (define_expand "extendhisi2"
2395 [(set (match_operand:SI 0 "register_operand" "")
2396 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2397 ""
2398 "
2399 {
2400 operands[1] = gen_lowpart (SImode, operands[1]);
2401 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2402 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2403 DONE;
2404 }
2405 ")
2406
2407 (define_insn "*extendhisi2"
2408 [(set (match_operand:SI 0 "register_operand" "=d")
2409 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2410 ""
2411 "lh\\t%0,%1"
2412 [(set_attr "op_type" "RX")
2413 (set_attr "atype" "mem")])
2414
2415 ;
2416 ; extendqisi2 instruction pattern(s).
2417 ;
2418
2419 (define_expand "extendqisi2"
2420 [(set (match_operand:SI 0 "register_operand" "")
2421 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2422 ""
2423 "
2424 {
2425 operands[1] = gen_lowpart (SImode, operands[1]);
2426 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2427 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2428 DONE;
2429 }
2430 ")
2431
2432 (define_split
2433 [(set (match_operand:SI 0 "register_operand" "")
2434 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2435 "!reload_completed"
2436 [(parallel
2437 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2438 (clobber (reg:CC 33))])
2439 (parallel
2440 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2441 (clobber (reg:CC 33))])]
2442 "")
2443
2444 ;
2445 ; extendqihi2 instruction pattern(s).
2446 ;
2447
2448
2449 ;
2450 ; zero_extendsidi2 instruction pattern(s).
2451 ;
2452
2453 (define_expand "zero_extendsidi2"
2454 [(set (match_operand:DI 0 "register_operand" "")
2455 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2456 ""
2457 "
2458 {
2459 if (!TARGET_64BIT)
2460 {
2461 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2462 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2463 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2464 DONE;
2465 }
2466 }
2467 ")
2468
2469 (define_insn "*zero_extendsidi2"
2470 [(set (match_operand:DI 0 "register_operand" "=d,d")
2471 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2472 "TARGET_64BIT"
2473 "@
2474 llgfr\\t%0,%1
2475 llgf\\t%0,%1"
2476 [(set_attr "op_type" "RRE,RXE")
2477 (set_attr "atype" "reg,mem")])
2478
2479 ;
2480 ; zero_extendhidi2 instruction pattern(s).
2481 ;
2482
2483 (define_expand "zero_extendhidi2"
2484 [(set (match_operand:DI 0 "register_operand" "")
2485 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2486 ""
2487 "
2488 {
2489 if (!TARGET_64BIT)
2490 {
2491 rtx tmp = gen_reg_rtx (SImode);
2492 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2493 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2494 DONE;
2495 }
2496 else
2497 {
2498 operands[1] = gen_lowpart (DImode, operands[1]);
2499 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2500 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2501 DONE;
2502 }
2503 }
2504 ")
2505
2506 (define_insn "*zero_extendhidi2"
2507 [(set (match_operand:DI 0 "register_operand" "=d")
2508 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2509 "TARGET_64BIT"
2510 "llgh\\t%0,%1"
2511 [(set_attr "op_type" "RXE")
2512 (set_attr "atype" "mem")])
2513
2514 ;
2515 ; zero_extendqidi2 instruction pattern(s)
2516 ;
2517
2518 (define_expand "zero_extendqidi2"
2519 [(set (match_operand:DI 0 "register_operand" "")
2520 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2521 ""
2522 "
2523 {
2524 if (!TARGET_64BIT)
2525 {
2526 rtx tmp = gen_reg_rtx (SImode);
2527 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2528 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2529 DONE;
2530 }
2531 else
2532 {
2533 operands[1] = gen_lowpart (DImode, operands[1]);
2534 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2535 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2536 DONE;
2537 }
2538 }
2539 ")
2540
2541 (define_insn "*zero_extendqidi2"
2542 [(set (match_operand:DI 0 "register_operand" "=d")
2543 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2544 "TARGET_64BIT"
2545 "llgc\\t%0,%1"
2546 [(set_attr "op_type" "RXE")
2547 (set_attr "atype" "mem")])
2548
2549 ;
2550 ; zero_extendhisi2 instruction pattern(s).
2551 ;
2552
2553 (define_expand "zero_extendhisi2"
2554 [(set (match_operand:SI 0 "register_operand" "")
2555 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2556 ""
2557 "
2558 {
2559 operands[1] = gen_lowpart (SImode, operands[1]);
2560 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2561 DONE;
2562 }
2563 ")
2564
2565 (define_insn "*zero_extendhisi2_64"
2566 [(set (match_operand:SI 0 "register_operand" "=d")
2567 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2568 "TARGET_64BIT"
2569 "llgh\\t%0,%1"
2570 [(set_attr "op_type" "RXE")
2571 (set_attr "atype" "mem")])
2572
2573 ;
2574 ; zero_extendqisi2 instruction pattern(s).
2575 ;
2576
2577 (define_expand "zero_extendqisi2"
2578 [(set (match_operand:SI 0 "register_operand" "")
2579 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2580 ""
2581 "
2582 {
2583 operands[1] = gen_lowpart (SImode, operands[1]);
2584 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2585 DONE;
2586 }
2587 ")
2588
2589 (define_insn "*zero_extendqisi2_64"
2590 [(set (match_operand:SI 0 "register_operand" "=d")
2591 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2592 "TARGET_64BIT"
2593 "llgc\\t%0,%1"
2594 [(set_attr "op_type" "RXE")
2595 (set_attr "atype" "mem")])
2596
2597 ;
2598 ; zero_extendqihi2 instruction pattern(s).
2599 ;
2600
2601 (define_expand "zero_extendqihi2"
2602 [(set (match_operand:HI 0 "register_operand" "")
2603 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2604 "TARGET_64BIT"
2605 "
2606 {
2607 operands[1] = gen_lowpart (HImode, operands[1]);
2608 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2609 DONE;
2610 }
2611 ")
2612
2613 (define_insn "*zero_extendqihi2_64"
2614 [(set (match_operand:HI 0 "register_operand" "=d")
2615 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2616 (clobber (reg:CC 33))]
2617 "TARGET_64BIT"
2618 "llgc\\t%0,%1"
2619 [(set_attr "op_type" "RXE")
2620 (set_attr "atype" "mem")])
2621
2622 ;
2623 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2624 ;
2625
2626 (define_expand "fixuns_truncdfdi2"
2627 [(set (match_operand:DI 0 "register_operand" "")
2628 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2629 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2630 "
2631 {
2632 rtx label1 = gen_label_rtx ();
2633 rtx label2 = gen_label_rtx ();
2634 rtx temp = gen_reg_rtx (DFmode);
2635 operands[1] = force_reg (DFmode, operands[1]);
2636
2637 emit_insn (gen_cmpdf (operands[1],
2638 CONST_DOUBLE_FROM_REAL_VALUE (
2639 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2640 emit_jump_insn (gen_blt (label1));
2641 emit_insn (gen_subdf3 (temp, operands[1],
2642 CONST_DOUBLE_FROM_REAL_VALUE (
2643 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2644 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2645 emit_jump (label2);
2646
2647 emit_label (label1);
2648 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2649 emit_label (label2);
2650 DONE;
2651 }")
2652
2653 (define_expand "fix_truncdfdi2"
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2656 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2657 "
2658 {
2659 operands[1] = force_reg (DFmode, operands[1]);
2660 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2661 DONE;
2662 }")
2663
2664 (define_insn "fix_truncdfdi2_ieee"
2665 [(set (match_operand:DI 0 "register_operand" "=d")
2666 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2667 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2668 (clobber (reg:CC 33))]
2669 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2670 "cgdbr\\t%0,%h2,%1"
2671 [(set_attr "op_type" "RRE")
2672 (set_attr "type" "other")])
2673
2674 ;
2675 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2676 ;
2677
2678 (define_expand "fixuns_truncdfsi2"
2679 [(set (match_operand:SI 0 "register_operand" "")
2680 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2681 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2682 "
2683 {
2684 rtx label1 = gen_label_rtx ();
2685 rtx label2 = gen_label_rtx ();
2686 rtx temp = gen_reg_rtx (DFmode);
2687
2688 operands[1] = force_reg (DFmode,operands[1]);
2689 emit_insn (gen_cmpdf (operands[1],
2690 CONST_DOUBLE_FROM_REAL_VALUE (
2691 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2692 emit_jump_insn (gen_blt (label1));
2693 emit_insn (gen_subdf3 (temp, operands[1],
2694 CONST_DOUBLE_FROM_REAL_VALUE (
2695 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2696 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2697 emit_jump (label2);
2698
2699 emit_label (label1);
2700 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2701 emit_label (label2);
2702 DONE;
2703 }")
2704
2705 (define_expand "fix_truncdfsi2"
2706 [(set (match_operand:SI 0 "register_operand" "")
2707 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2708 "TARGET_HARD_FLOAT"
2709 "
2710 {
2711 if (TARGET_IBM_FLOAT)
2712 {
2713 /* This is the algorithm from POP chapter A.5.7.2. */
2714
2715 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2716 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2717 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2718
2719 operands[1] = force_reg (DFmode, operands[1]);
2720 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2721 two31r, two32, temp));
2722 }
2723 else
2724 {
2725 operands[1] = force_reg (DFmode, operands[1]);
2726 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2727 }
2728
2729 DONE;
2730 }")
2731
2732 (define_insn "fix_truncdfsi2_ieee"
2733 [(set (match_operand:SI 0 "register_operand" "=d")
2734 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2735 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2736 (clobber (reg:CC 33))]
2737 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2738 "cfdbr\\t%0,%h2,%1"
2739 [(set_attr "op_type" "RRE")
2740 (set_attr "type" "other" )])
2741
2742 (define_insn "fix_truncdfsi2_ibm"
2743 [(set (match_operand:SI 0 "register_operand" "=d")
2744 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2745 (use (match_operand:DI 2 "immediate_operand" "m"))
2746 (use (match_operand:DI 3 "immediate_operand" "m"))
2747 (use (match_operand:BLK 4 "memory_operand" "m"))
2748 (clobber (reg:CC 33))]
2749 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2750 "*
2751 {
2752 output_asm_insn (\"sd\\t%1,%2\", operands);
2753 output_asm_insn (\"aw\\t%1,%3\", operands);
2754 output_asm_insn (\"std\\t%1,%4\", operands);
2755 output_asm_insn (\"xi\\t%N4,128\", operands);
2756 return \"l\\t%0,%N4\";
2757 }"
2758 [(set_attr "op_type" "NN")
2759 (set_attr "type" "other")
2760 (set_attr "length" "20")])
2761
2762 ;
2763 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2764 ;
2765
2766 (define_expand "fixuns_truncsfdi2"
2767 [(set (match_operand:DI 0 "register_operand" "")
2768 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2769 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2770 "
2771 {
2772 rtx label1 = gen_label_rtx ();
2773 rtx label2 = gen_label_rtx ();
2774 rtx temp = gen_reg_rtx (SFmode);
2775
2776 operands[1] = force_reg (SFmode, operands[1]);
2777 emit_insn (gen_cmpsf (operands[1],
2778 CONST_DOUBLE_FROM_REAL_VALUE (
2779 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2780 emit_jump_insn (gen_blt (label1));
2781
2782 emit_insn (gen_subsf3 (temp, operands[1],
2783 CONST_DOUBLE_FROM_REAL_VALUE (
2784 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2785 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2786 emit_jump (label2);
2787
2788 emit_label (label1);
2789 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2790 emit_label (label2);
2791 DONE;
2792 }")
2793
2794 (define_expand "fix_truncsfdi2"
2795 [(set (match_operand:DI 0 "register_operand" "")
2796 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2797 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2798 "
2799 {
2800 operands[1] = force_reg (SFmode, operands[1]);
2801 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2802 DONE;
2803 }")
2804
2805 (define_insn "fix_truncsfdi2_ieee"
2806 [(set (match_operand:DI 0 "register_operand" "=d")
2807 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2808 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2809 (clobber (reg:CC 33))]
2810 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2811 "cgebr\\t%0,%h2,%1"
2812 [(set_attr "op_type" "RRE")
2813 (set_attr "type" "other")])
2814
2815 ;
2816 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2817 ;
2818
2819 (define_expand "fixuns_truncsfsi2"
2820 [(set (match_operand:SI 0 "register_operand" "")
2821 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2822 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2823 "
2824 {
2825 rtx label1 = gen_label_rtx ();
2826 rtx label2 = gen_label_rtx ();
2827 rtx temp = gen_reg_rtx (SFmode);
2828
2829 operands[1] = force_reg (SFmode, operands[1]);
2830 emit_insn (gen_cmpsf (operands[1],
2831 CONST_DOUBLE_FROM_REAL_VALUE (
2832 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2833 emit_jump_insn (gen_blt (label1));
2834 emit_insn (gen_subsf3 (temp, operands[1],
2835 CONST_DOUBLE_FROM_REAL_VALUE (
2836 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2837 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2838 emit_jump (label2);
2839
2840 emit_label (label1);
2841 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2842 emit_label (label2);
2843 DONE;
2844 }")
2845
2846 (define_expand "fix_truncsfsi2"
2847 [(set (match_operand:SI 0 "register_operand" "")
2848 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2849 "TARGET_HARD_FLOAT"
2850 "
2851 {
2852 if (TARGET_IBM_FLOAT)
2853 {
2854 /* Convert to DFmode and then use the POP algorithm. */
2855 rtx temp = gen_reg_rtx (DFmode);
2856 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2857 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2858 }
2859 else
2860 {
2861 operands[1] = force_reg (SFmode, operands[1]);
2862 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2863 }
2864
2865 DONE;
2866 }")
2867
2868 (define_insn "fix_truncsfsi2_ieee"
2869 [(set (match_operand:SI 0 "register_operand" "=d")
2870 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2871 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2872 (clobber (reg:CC 33))]
2873 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2874 "cfebr\\t%0,%h2,%1"
2875 [(set_attr "op_type" "RRE")
2876 (set_attr "type" "other")])
2877
2878 ;
2879 ; floatdidf2 instruction pattern(s).
2880 ;
2881
2882 (define_insn "floatdidf2"
2883 [(set (match_operand:DF 0 "register_operand" "=f")
2884 (float:DF (match_operand:DI 1 "register_operand" "d")))
2885 (clobber (reg:CC 33))]
2886 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2887 "cdgbr\\t%0,%1"
2888 [(set_attr "op_type" "RRE")
2889 (set_attr "type" "other" )])
2890
2891 ;
2892 ; floatdisf2 instruction pattern(s).
2893 ;
2894
2895 (define_insn "floatdisf2"
2896 [(set (match_operand:SF 0 "register_operand" "=f")
2897 (float:SF (match_operand:DI 1 "register_operand" "d")))
2898 (clobber (reg:CC 33))]
2899 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2900 "cegbr\\t%0,%1"
2901 [(set_attr "op_type" "RRE")
2902 (set_attr "type" "other" )])
2903
2904 ;
2905 ; floatsidf2 instruction pattern(s).
2906 ;
2907
2908 (define_expand "floatsidf2"
2909 [(parallel
2910 [(set (match_operand:DF 0 "register_operand" "")
2911 (float:DF (match_operand:SI 1 "register_operand" "")))
2912 (clobber (reg:CC 33))])]
2913 "TARGET_HARD_FLOAT"
2914 "
2915 {
2916 if (TARGET_IBM_FLOAT)
2917 {
2918 /* This is the algorithm from POP chapter A.5.7.1. */
2919
2920 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2921 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2922
2923 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2924 DONE;
2925 }
2926 }")
2927
2928 (define_insn "floatsidf2_ieee"
2929 [(set (match_operand:DF 0 "register_operand" "=f")
2930 (float:DF (match_operand:SI 1 "register_operand" "d")))
2931 (clobber (reg:CC 33))]
2932 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2933 "cdfbr\\t%0,%1"
2934 [(set_attr "op_type" "RRE")
2935 (set_attr "type" "other" )])
2936
2937 (define_insn "floatsidf2_ibm"
2938 [(set (match_operand:DF 0 "register_operand" "=f")
2939 (float:DF (match_operand:SI 1 "register_operand" "d")))
2940 (use (match_operand:DI 2 "immediate_operand" "m"))
2941 (use (match_operand:BLK 3 "memory_operand" "m"))
2942 (clobber (reg:CC 33))]
2943 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2944 "*
2945 {
2946 output_asm_insn (\"st\\t%1,%N3\", operands);
2947 output_asm_insn (\"xi\\t%N3,128\", operands);
2948 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2949 output_asm_insn (\"ld\\t%0,%3\", operands);
2950 return \"sd\\t%0,%2\";
2951 }"
2952 [(set_attr "op_type" "NN")
2953 (set_attr "type" "other" )
2954 (set_attr "length" "20")])
2955
2956 ;
2957 ; floatsisf2 instruction pattern(s).
2958 ;
2959
2960 (define_expand "floatsisf2"
2961 [(parallel
2962 [(set (match_operand:SF 0 "register_operand" "")
2963 (float:SF (match_operand:SI 1 "register_operand" "")))
2964 (clobber (reg:CC 33))])]
2965 "TARGET_HARD_FLOAT"
2966 "
2967 {
2968 if (TARGET_IBM_FLOAT)
2969 {
2970 /* Use the POP algorithm to convert to DFmode and then truncate. */
2971 rtx temp = gen_reg_rtx (DFmode);
2972 emit_insn (gen_floatsidf2 (temp, operands[1]));
2973 emit_insn (gen_truncdfsf2 (operands[0], temp));
2974 DONE;
2975 }
2976 }")
2977
2978 (define_insn "floatsisf2_ieee"
2979 [(set (match_operand:SF 0 "register_operand" "=f")
2980 (float:SF (match_operand:SI 1 "register_operand" "d")))
2981 (clobber (reg:CC 33))]
2982 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2983 "cefbr\\t%0,%1"
2984 [(set_attr "op_type" "RRE")
2985 (set_attr "type" "other" )])
2986
2987 ;
2988 ; truncdfsf2 instruction pattern(s).
2989 ;
2990
2991 (define_expand "truncdfsf2"
2992 [(set (match_operand:SF 0 "register_operand" "")
2993 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2994 "TARGET_HARD_FLOAT"
2995 "")
2996
2997 (define_insn "truncdfsf2_ieee"
2998 [(set (match_operand:SF 0 "register_operand" "=f")
2999 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
3000 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3001 "ledbr\\t%0,%1"
3002 [(set_attr "op_type" "RRE")])
3003
3004 (define_insn "truncdfsf2_ibm"
3005 [(set (match_operand:SF 0 "register_operand" "=f,f")
3006 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
3007 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3008 "@
3009 lrer\\t%0,%1
3010 le\\t%0,%1"
3011 [(set_attr "op_type" "RR,RX")
3012 (set_attr "atype" "reg,mem")])
3013
3014 ;
3015 ; extendsfdf2 instruction pattern(s).
3016 ;
3017
3018 (define_expand "extendsfdf2"
3019 [(set (match_operand:DF 0 "register_operand" "")
3020 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3021 "TARGET_HARD_FLOAT"
3022 "
3023 {
3024 if (TARGET_IBM_FLOAT)
3025 {
3026 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3027 DONE;
3028 }
3029 }")
3030
3031 (define_insn "extendsfdf2_ieee"
3032 [(set (match_operand:DF 0 "register_operand" "=f,f")
3033 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
3034 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3035 "@
3036 ldebr\\t%0,%1
3037 ldeb\\t%0,%1"
3038 [(set_attr "op_type" "RRE,RXE")])
3039
3040 (define_insn "extendsfdf2_ibm"
3041 [(set (match_operand:DF 0 "register_operand" "=f,f")
3042 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
3043 (clobber (reg:CC 33))]
3044 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3045 "@
3046 sdr\\t%0,%0\;ler\\t%0,%1
3047 sdr\\t%0,%0\;le\\t%0,%1"
3048 [(set_attr "op_type" "RRE,RXE")
3049 (set_attr "atype" "reg,mem")
3050 (set_attr "type" "o2,o2")])
3051
3052
3053 ;;
3054 ;; ARITHMETRIC OPERATIONS
3055 ;;
3056 ; arithmetric operations set the ConditionCode,
3057 ; because of unpredictable Bits in Register for Halfword and Byte
3058 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3059
3060 ;;
3061 ;;- Add instructions.
3062 ;;
3063
3064 ;
3065 ; adddi3 instruction pattern(s).
3066 ;
3067
3068 (define_insn "addaddr_esame"
3069 [(set (match_operand:DI 0 "register_operand" "=a,a")
3070 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3071 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3072 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3073 (REGNO (operands[1]) == BASE_REGISTER)) &&
3074 (GET_CODE (operands[2]) == REG ||
3075 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3076 "@
3077 la\\t%0,%c2(,%1)
3078 la\\t%0,0(%1,%2)"
3079 [(set_attr "op_type" "RX")
3080 (set_attr "atype" "mem")
3081 (set_attr "type" "la")])
3082
3083 (define_insn "adddi3_64"
3084 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3085 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3086 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3087 (clobber (reg:CC 33))]
3088 "TARGET_64BIT"
3089 "@
3090 agr\\t%0,%2
3091 aghi\\t%0,%h2
3092 ag\\t%0,%2"
3093 [(set_attr "op_type" "RRE,RI,RXE")
3094 (set_attr "atype" "reg,reg,mem")])
3095
3096 (define_insn "adddi3_31"
3097 [(set (match_operand:DI 0 "register_operand" "=d,d")
3098 (plus:DI (match_operand:DI 1 "register_operand" "0,0")
3099 (match_operand:DI 2 "general_operand" "d,m") ) )
3100 (clobber (reg:CC 33))]
3101 "!TARGET_64BIT"
3102 "*
3103 {
3104 switch (which_alternative)
3105 {
3106 case 0: /* d <- d */
3107 output_asm_insn (\"ar\\t%0,%2\", operands);
3108 output_asm_insn (\"alr\\t%N0,%N2\", operands);
3109 break;
3110
3111 case 1: /* d <- m */
3112 output_asm_insn (\"a\\t%0,%2\", operands);
3113 output_asm_insn (\"al\\t%N0,%N2\", operands);
3114 break;
3115
3116 default:
3117 abort ();
3118 }
3119
3120 output_asm_insn (\"brc\\t12,.+8\", operands);
3121 return \"ahi\\t%0,1\";
3122 }"
3123 [(set_attr "op_type" "NN,NN")
3124 (set_attr "atype" "reg,mem")
3125 (set_attr "type" "o2,o2")
3126 (set_attr "length" "12,16")])
3127
3128 (define_expand "adddi3"
3129 [(set (match_operand:DI 0 "register_operand" "")
3130 (plus:DI (match_operand:DI 1 "register_operand" "")
3131 (match_operand:DI 2 "general_operand" "")))]
3132 ""
3133 "
3134 {
3135 if (TARGET_64BIT)
3136 emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2]));
3137 else
3138 emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2]));
3139 DONE;
3140 }")
3141
3142 (define_insn "*la_64"
3143 [(set (match_operand:DI 0 "register_operand" "=d")
3144 (match_operand:QI 1 "address_operand" "p"))]
3145 "TARGET_64BIT"
3146 "la\\t%0,%a1"
3147 [(set_attr "op_type" "RX")
3148 (set_attr "atype" "mem")
3149 (set_attr "type" "la")])
3150
3151 (define_expand "reload_indi"
3152 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3153 (match_operand:DI 1 "s390_plus_operand" "")
3154 (match_operand:DI 2 "register_operand" "=&a")])]
3155 "TARGET_64BIT"
3156 "
3157 {
3158 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3159 DONE;
3160 }")
3161
3162
3163 ;
3164 ; addsi3 instruction pattern(s).
3165 ;
3166
3167 (define_insn "*la_ccclobber"
3168 [(set (match_operand:SI 0 "register_operand" "=d")
3169 (match_operand:QI 1 "address_operand" "p"))
3170 (clobber (reg:CC 33))]
3171 "legitimate_la_operand_p (operands[1])"
3172 "la\\t%0,%a1"
3173 [(set_attr "op_type" "RX")
3174 (set_attr "atype" "mem")
3175 (set_attr "type" "la")])
3176
3177 (define_insn "*addsi3_cc"
3178 [(set (reg 33)
3179 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3180 (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3181 (const_int 0)))
3182 (set (match_operand:SI 0 "register_operand" "=d,d")
3183 (plus:SI (match_dup 1) (match_dup 2)))]
3184 "s390_match_ccmode(insn, CCLmode)"
3185 "@
3186 alr\\t%0,%2
3187 al\\t%0,%2"
3188 [(set_attr "op_type" "RR,RX")
3189 (set_attr "atype" "reg,mem")])
3190
3191 (define_insn "*addsi3_cconly"
3192 [(set (reg 33)
3193 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3194 (match_operand:SI 2 "general_operand" "d,m"))
3195 (const_int 0)))
3196 (clobber (match_scratch:SI 0 "=d,d"))]
3197 "s390_match_ccmode(insn, CCLmode)"
3198 "@
3199 alr\\t%0,%2
3200 al\\t%0,%2"
3201 [(set_attr "op_type" "RR,RX")
3202 (set_attr "atype" "reg,mem")])
3203
3204 (define_insn "*addsi3_cconly2"
3205 [(set (reg 33)
3206 (compare (match_operand:SI 1 "register_operand" "%0,0")
3207 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3208 (clobber (match_scratch:SI 0 "=d,d"))]
3209 "s390_match_ccmode(insn, CCLmode)"
3210 "@
3211 alr\\t%0,%2
3212 al\\t%0,%2"
3213 [(set_attr "op_type" "RR,RX")
3214 (set_attr "atype" "reg,mem")])
3215
3216 (define_insn "addsi3"
3217 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3218 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3219 (match_operand:SI 2 "general_operand" "d,K,m")))
3220 (clobber (reg:CC 33))]
3221 ""
3222 "@
3223 ar\\t%0,%2
3224 ahi\\t%0,%h2
3225 a\\t%0,%2"
3226 [(set_attr "op_type" "RR,RI,RX")
3227 (set_attr "atype" "reg,reg,mem")])
3228
3229 (define_insn "*la_31"
3230 [(set (match_operand:SI 0 "register_operand" "=d")
3231 (match_operand:QI 1 "address_operand" "p"))]
3232 "legitimate_la_operand_p (operands[1])"
3233 "la\\t%0,%a1"
3234 [(set_attr "op_type" "RX")
3235 (set_attr "atype" "mem")
3236 (set_attr "type" "la")])
3237
3238 (define_expand "reload_insi"
3239 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3240 (match_operand:SI 1 "s390_plus_operand" "")
3241 (match_operand:SI 2 "register_operand" "=&a")])]
3242 "!TARGET_64BIT"
3243 "
3244 {
3245 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3246 DONE;
3247 }")
3248
3249
3250 ;
3251 ; addhi3 instruction pattern(s).
3252 ;
3253
3254 (define_insn "addhi3"
3255 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3256 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
3257 (match_operand:HI 2 "general_operand" "d,K,m")))
3258 (clobber (reg:CC 33))]
3259 ""
3260 "@
3261 ar\\t%0,%2
3262 ahi\\t%0,%h2
3263 ah\\t%0,%2"
3264 [(set_attr "op_type" "RR,RI,RX")
3265 (set_attr "atype" "reg,reg,mem")])
3266
3267
3268 ;
3269 ; addqi3 instruction pattern(s).
3270 ;
3271
3272 (define_insn "addqi3"
3273 [(set (match_operand:QI 0 "register_operand" "=d,d")
3274 (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
3275 (match_operand:QI 2 "general_operand" "a,n")))
3276 (clobber (reg:CC 33))]
3277 ""
3278 "@
3279 ar\\t%0,%2
3280 ahi\\t%0,%h2"
3281 [(set_attr "op_type" "RX,RX")
3282 (set_attr "atype" "reg,mem")])
3283
3284
3285 ;
3286 ; adddf3 instruction pattern(s).
3287 ;
3288
3289 (define_expand "adddf3"
3290 [(parallel
3291 [(set (match_operand:DF 0 "register_operand" "=f,f")
3292 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3293 (match_operand:DF 2 "general_operand" "f,m")))
3294 (clobber (reg:CC 33))])]
3295 "TARGET_HARD_FLOAT"
3296 "")
3297
3298 (define_insn "*adddf3"
3299 [(set (match_operand:DF 0 "register_operand" "=f,f")
3300 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3301 (match_operand:DF 2 "general_operand" "f,m")))
3302 (clobber (reg:CC 33))]
3303 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3304 "@
3305 adbr\\t%0,%2
3306 adb\\t%0,%2"
3307 [(set_attr "op_type" "RRE,RXE")
3308 (set_attr "atype" "reg,mem")])
3309
3310 (define_insn "*adddf3_ibm"
3311 [(set (match_operand:DF 0 "register_operand" "=f,f")
3312 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3313 (match_operand:DF 2 "general_operand" "f,m")))
3314 (clobber (reg:CC 33))]
3315 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3316 "@
3317 adr\\t%0,%2
3318 ad\\t%0,%2"
3319 [(set_attr "op_type" "RR,RX")
3320 (set_attr "atype" "reg,mem")])
3321
3322 ;
3323 ; addsf3 instruction pattern(s).
3324 ;
3325
3326 (define_expand "addsf3"
3327 [(parallel
3328 [(set (match_operand:SF 0 "register_operand" "=f,f")
3329 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3330 (match_operand:SF 2 "general_operand" "f,m")))
3331 (clobber (reg:CC 33))])]
3332 "TARGET_HARD_FLOAT"
3333 "")
3334
3335 (define_insn "*addsf3"
3336 [(set (match_operand:SF 0 "register_operand" "=f,f")
3337 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3338 (match_operand:SF 2 "general_operand" "f,m")))
3339 (clobber (reg:CC 33))]
3340 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3341 "@
3342 aebr\\t%0,%2
3343 aeb\\t%0,%2"
3344 [(set_attr "op_type" "RRE,RXE")
3345 (set_attr "atype" "reg,mem")])
3346
3347 (define_insn "*addsf3"
3348 [(set (match_operand:SF 0 "register_operand" "=f,f")
3349 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3350 (match_operand:SF 2 "general_operand" "f,m")))
3351 (clobber (reg:CC 33))]
3352 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3353 "@
3354 aer\\t%0,%2
3355 ae\\t%0,%2"
3356 [(set_attr "op_type" "RR,RX")
3357 (set_attr "atype" "reg,mem")])
3358
3359
3360 ;;
3361 ;;- Subtract instructions.
3362 ;;
3363
3364 ;
3365 ; subdi3 instruction pattern(s).
3366 ;
3367
3368 (define_insn "*subdi3_64"
3369 [(set (match_operand:DI 0 "register_operand" "=d,d")
3370 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3371 (match_operand:DI 2 "general_operand" "d,m") ) )
3372 (clobber (reg:CC 33))]
3373 "TARGET_64BIT"
3374 "@
3375 sgr\\t%0,%2
3376 sg\\t%0,%2"
3377 [(set_attr "op_type" "RRE,RRE")
3378 (set_attr "atype" "reg,mem")])
3379
3380 (define_insn "subdi3"
3381 [(set (match_operand:DI 0 "register_operand" "=d,d")
3382 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3383 (match_operand:DI 2 "general_operand" "d,m")))
3384 (clobber (reg:CC 33))]
3385 ""
3386 "*
3387 {
3388 switch (which_alternative)
3389 {
3390 case 0: /* d <- d */
3391 output_asm_insn (\"sr\\t%0,%2\", operands);
3392 output_asm_insn (\"slr\\t%N0,%N2\", operands);
3393 break;
3394 case 1: /* d <- m */
3395 output_asm_insn (\"s\\t%0,%2\", operands);
3396 output_asm_insn (\"sl\\t%N0,%N2\", operands);
3397 break;
3398
3399 default:
3400 abort ();
3401 }
3402
3403 output_asm_insn (\"brc\\t11,.+8\", operands);
3404 return \"ahi\\t%0,-1\";
3405 }"
3406 [(set_attr "op_type" "NN,NN")
3407 (set_attr "atype" "reg,mem")
3408 (set_attr "type" "other,other")
3409 (set_attr "length" "12,16")])
3410
3411 ;
3412 ; subsi3 instruction pattern(s).
3413 ;
3414
3415 (define_insn "*subsi3_cc"
3416 [(set (reg 33)
3417 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3418 (match_operand:SI 2 "general_operand" "d,m"))
3419 (const_int 0)))
3420 (set (match_operand:SI 0 "register_operand" "=d,d")
3421 (minus:SI (match_dup 1) (match_dup 2)))]
3422 "s390_match_ccmode(insn, CCLmode)"
3423 "@
3424 slr\\t%0,%2
3425 sl\\t%0,%2"
3426 [(set_attr "op_type" "RR,RX")
3427 (set_attr "atype" "reg,mem")])
3428
3429 (define_insn "*subsi3_cconly"
3430 [(set (reg 33)
3431 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3432 (match_operand:SI 2 "general_operand" "d,m"))
3433 (const_int 0)))
3434 (clobber (match_scratch:SI 0 "=d,d"))]
3435 "s390_match_ccmode(insn, CCLmode)"
3436 "@
3437 slr\\t%0,%2
3438 sl\\t%0,%2"
3439 [(set_attr "op_type" "RR,RX")
3440 (set_attr "atype" "reg,mem")])
3441
3442 (define_insn "subsi3"
3443 [(set (match_operand:SI 0 "register_operand" "=d,d")
3444 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3445 (match_operand:SI 2 "general_operand" "d,m")))
3446 (clobber (reg:CC 33))]
3447 ""
3448 "@
3449 sr\\t%0,%2
3450 s\\t%0,%2"
3451 [(set_attr "op_type" "RR,RX")
3452 (set_attr "atype" "reg,mem")])
3453
3454 ;
3455 ; subhi3 instruction pattern(s).
3456 ;
3457
3458 (define_insn "subhi3"
3459 [(set (match_operand:HI 0 "register_operand" "=d,d")
3460 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
3461 (match_operand:HI 2 "general_operand" "d,m")))
3462 (clobber (reg:CC 33))]
3463 ""
3464 "@
3465 sr\\t%0,%2
3466 sh\\t%0,%2"
3467 [(set_attr "op_type" "RR,RX")
3468 (set_attr "atype" "reg,mem")])
3469
3470 ;
3471 ; subqi3 instruction pattern(s).
3472 ;
3473
3474 (define_insn "subqi3"
3475 [(set (match_operand:QI 0 "register_operand" "=d")
3476 (minus:QI (match_operand:QI 1 "register_operand" "0")
3477 (match_operand:QI 2 "register_operand" "d")))
3478 (clobber (reg:CC 33))]
3479 ""
3480 "sr\\t%0,%2"
3481 [(set_attr "op_type" "RR")])
3482
3483 ;
3484 ; subdf3 instruction pattern(s).
3485 ;
3486
3487 (define_expand "subdf3"
3488 [(parallel
3489 [(set (match_operand:DF 0 "register_operand" "=f,f")
3490 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3491 (match_operand:DF 2 "general_operand" "f,m")))
3492 (clobber (reg:CC 33))])]
3493 "TARGET_HARD_FLOAT"
3494 "")
3495
3496 (define_insn "*subdf3"
3497 [(set (match_operand:DF 0 "register_operand" "=f,f")
3498 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3499 (match_operand:DF 2 "general_operand" "f,m")))
3500 (clobber (reg:CC 33))]
3501 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3502 "@
3503 sdbr\\t%0,%2
3504 sdb\\t%0,%2"
3505 [(set_attr "op_type" "RRE,RXE")
3506 (set_attr "atype" "reg,mem")])
3507
3508 (define_insn "*subdf3_ibm"
3509 [(set (match_operand:DF 0 "register_operand" "=f,f")
3510 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3511 (match_operand:DF 2 "general_operand" "f,m")))
3512 (clobber (reg:CC 33))]
3513 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3514 "@
3515 sdr\\t%0,%2
3516 sd\\t%0,%2"
3517 [(set_attr "op_type" "RR,RX")
3518 (set_attr "atype" "reg,mem")])
3519
3520 ;
3521 ; subsf3 instruction pattern(s).
3522 ;
3523
3524 (define_expand "subsf3"
3525 [(parallel
3526 [(set (match_operand:SF 0 "register_operand" "=f,f")
3527 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3528 (match_operand:SF 2 "general_operand" "f,m")))
3529 (clobber (reg:CC 33))])]
3530 "TARGET_HARD_FLOAT"
3531 "")
3532
3533 (define_insn "*subsf3"
3534 [(set (match_operand:SF 0 "register_operand" "=f,f")
3535 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3536 (match_operand:SF 2 "general_operand" "f,m")))
3537 (clobber (reg:CC 33))]
3538 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3539 "@
3540 sebr\\t%0,%2
3541 seb\\t%0,%2"
3542 [(set_attr "op_type" "RRE,RXE")
3543 (set_attr "atype" "reg,mem")])
3544
3545 (define_insn "*subsf3_ibm"
3546 [(set (match_operand:SF 0 "register_operand" "=f,f")
3547 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3548 (match_operand:SF 2 "general_operand" "f,m")))
3549 (clobber (reg:CC 33))]
3550 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3551 "@
3552 ser\\t%0,%2
3553 se\\t%0,%2"
3554 [(set_attr "op_type" "RR,RX")
3555 (set_attr "atype" "reg,mem")])
3556
3557
3558 ;;
3559 ;;- Multiply instructions.
3560 ;;
3561
3562 ;
3563 ; muldi3 instruction pattern(s).
3564 ;
3565
3566 (define_insn "muldi3"
3567 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3568 (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3569 (match_operand:DI 2 "general_operand" "d,K,m")))
3570 (clobber (reg:CC 33))]
3571 "TARGET_64BIT"
3572 "@
3573 msgr\\t%0,%2
3574 mghi\\t%0,%h2
3575 msg\\t%0,%2"
3576 [(set_attr "op_type" "RRE,RI,RX")
3577 (set_attr "atype" "reg,reg,mem")
3578 (set_attr "type" "imul")])
3579
3580 ;
3581 ; mulsi3 instruction pattern(s).
3582 ;
3583
3584 (define_insn "mulsi3"
3585 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3586 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3587 (match_operand:SI 2 "general_operand" "d,K,m")))
3588 (clobber (reg:CC 33))]
3589 ""
3590 "@
3591 msr\\t%0,%2
3592 mhi\\t%0,%h2
3593 ms\\t%0,%2"
3594 [(set_attr "op_type" "RRE,RI,RX")
3595 (set_attr "atype" "reg,reg,mem")
3596 (set_attr "type" "imul")])
3597
3598 ;
3599 ; mulsidi3 instruction pattern(s).
3600 ;
3601
3602 (define_expand "mulsidi3"
3603 [(set (match_operand:DI 0 "register_operand" "")
3604 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3605 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3606 "!TARGET_64BIT"
3607 "
3608 {
3609 rtx insn;
3610
3611 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
3612 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3613 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3614
3615 REG_NOTES (insn) =
3616 gen_rtx_EXPR_LIST (REG_EQUAL,
3617 gen_rtx_MULT (DImode,
3618 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3619 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3620 REG_NOTES (insn));
3621 DONE;
3622 }")
3623
3624 (define_insn "mulsi_6432"
3625 [(set (match_operand:DI 0 "register_operand" "=d,d")
3626 (mult:DI (sign_extend:DI
3627 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3628 (sign_extend:DI
3629 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3630 (clobber (reg:CC 33))]
3631 "!TARGET_64BIT"
3632 "@
3633 mr\\t%0,%2
3634 m\\t%0,%2"
3635 [(set_attr "op_type" "RR,RX")
3636 (set_attr "atype" "reg,mem")
3637 (set_attr "type" "imul")])
3638
3639 ;
3640 ; muldf3 instruction pattern(s).
3641 ;
3642
3643 (define_expand "muldf3"
3644 [(parallel
3645 [(set (match_operand:DF 0 "register_operand" "=f,f")
3646 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3647 (match_operand:DF 2 "general_operand" "f,m")))
3648 (clobber (reg:CC 33))])]
3649 "TARGET_HARD_FLOAT"
3650 "")
3651
3652 (define_insn "*muldf3"
3653 [(set (match_operand:DF 0 "register_operand" "=f,f")
3654 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3655 (match_operand:DF 2 "general_operand" "f,m")))
3656 (clobber (reg:CC 33))]
3657 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3658 "@
3659 mdbr\\t%0,%2
3660 mdb\\t%0,%2"
3661 [(set_attr "op_type" "RRE,RXE")
3662 (set_attr "type" "fmul")
3663 (set_attr "atype" "reg,mem")])
3664
3665 (define_insn "*muldf3_ibm"
3666 [(set (match_operand:DF 0 "register_operand" "=f,f")
3667 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3668 (match_operand:DF 2 "general_operand" "f,m")))
3669 (clobber (reg:CC 33))]
3670 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3671 "@
3672 mdr\\t%0,%2
3673 md\\t%0,%2"
3674 [(set_attr "op_type" "RR,RX")
3675 (set_attr "type" "fmul")
3676 (set_attr "atype" "reg,mem")])
3677
3678 ;
3679 ; mulsf3 instruction pattern(s).
3680 ;
3681
3682 (define_expand "mulsf3"
3683 [(parallel
3684 [(set (match_operand:SF 0 "register_operand" "=f,f")
3685 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3686 (match_operand:SF 2 "general_operand" "f,m")))
3687 (clobber (reg:CC 33))])]
3688 "TARGET_HARD_FLOAT"
3689 "")
3690
3691 (define_insn "*mulsf3"
3692 [(set (match_operand:SF 0 "register_operand" "=f,f")
3693 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3694 (match_operand:SF 2 "general_operand" "f,m")))
3695 (clobber (reg:CC 33))]
3696 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3697 "@
3698 meebr\\t%0,%2
3699 meeb\\t%0,%2"
3700 [(set_attr "op_type" "RRE,RXE")
3701 (set_attr "type" "fmul")
3702 (set_attr "atype" "reg,mem")])
3703
3704 (define_insn "*mulsf3_ibm"
3705 [(set (match_operand:SF 0 "register_operand" "=f,f")
3706 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3707 (match_operand:SF 2 "general_operand" "f,m")))
3708 (clobber (reg:CC 33))]
3709 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3710 "@
3711 mer\\t%0,%2
3712 me\\t%0,%2"
3713 [(set_attr "op_type" "RR,RX")
3714 (set_attr "type" "fmul")
3715 (set_attr "atype" "reg,mem")])
3716
3717
3718 ;;
3719 ;;- Divide and modulo instructions.
3720 ;;
3721
3722 ;
3723 ; divmoddi4 instruction pattern(s).
3724 ;
3725
3726 (define_expand "divmoddi4"
3727 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3728 (div:DI (match_operand:DI 1 "general_operand" "")
3729 (match_operand:DI 2 "general_operand" "")))
3730 (set (match_operand:DI 3 "general_operand" "")
3731 (mod:DI (match_dup 1) (match_dup 2)))])
3732 (clobber (match_dup 4))]
3733 "TARGET_64BIT"
3734 "
3735 {
3736 rtx insn, div_equal, mod_equal, equal;
3737
3738 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3739 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3740 equal = gen_rtx_IOR (TImode,
3741 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3742 gen_rtx_ASHIFT (TImode,
3743 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3744 GEN_INT (64)));
3745
3746 operands[4] = gen_reg_rtx(TImode);
3747 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3748 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3749 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3750 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3751 REG_NOTES (insn) =
3752 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3753
3754 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3755 REG_NOTES (insn) =
3756 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3757
3758 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3759 REG_NOTES (insn) =
3760 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3761
3762 DONE;
3763 }")
3764
3765 (define_insn "divmodtidi3"
3766 [(set (match_operand:TI 0 "register_operand" "=d,d")
3767 (ior:TI
3768 (zero_extend:TI
3769 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3770 (match_operand:DI 2 "general_operand" "d,m")))
3771 (ashift:TI
3772 (zero_extend:TI
3773 (mod:DI (truncate:DI (match_dup 1))
3774 (match_dup 2)))
3775 (const_int 64))))]
3776 "TARGET_64BIT"
3777 "@
3778 dsgr\\t%0,%2
3779 dsg\\t%0,%2"
3780 [(set_attr "op_type" "RRE,RXE")
3781 (set_attr "type" "idiv")
3782 (set_attr "atype" "reg,mem")])
3783
3784 (define_insn "divmodtisi3"
3785 [(set (match_operand:TI 0 "register_operand" "=d,d")
3786 (ior:TI
3787 (zero_extend:TI
3788 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3789 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3790 (ashift:TI
3791 (zero_extend:TI
3792 (mod:DI (truncate:DI (match_dup 1))
3793 (sign_extend:DI (match_dup 2))))
3794 (const_int 64))))]
3795 "TARGET_64BIT"
3796 "@
3797 dsgfr\\t%0,%2
3798 dsgf\\t%0,%2"
3799 [(set_attr "op_type" "RRE,RXE")
3800 (set_attr "type" "idiv")
3801 (set_attr "atype" "reg,mem")])
3802
3803 ;
3804 ; udivmoddi4 instruction pattern(s).
3805 ;
3806
3807 (define_expand "udivmoddi4"
3808 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3809 (udiv:DI (match_operand:DI 1 "general_operand" "")
3810 (match_operand:DI 2 "nonimmediate_operand" "")))
3811 (set (match_operand:DI 3 "general_operand" "")
3812 (umod:DI (match_dup 1) (match_dup 2)))])
3813 (clobber (match_dup 4))]
3814 "TARGET_64BIT"
3815 "
3816 {
3817 rtx insn, div_equal, mod_equal, equal;
3818
3819 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3820 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3821 equal = gen_rtx_IOR (TImode,
3822 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3823 gen_rtx_ASHIFT (TImode,
3824 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3825 GEN_INT (64)));
3826
3827 operands[4] = gen_reg_rtx(TImode);
3828 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3829 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3830 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3831 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3832 REG_NOTES (insn) =
3833 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3834
3835 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3836 REG_NOTES (insn) =
3837 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3838
3839 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3840 REG_NOTES (insn) =
3841 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3842
3843 DONE;
3844 }")
3845
3846 (define_insn "udivmodtidi3"
3847 [(set (match_operand:TI 0 "register_operand" "=d,d")
3848 (ior:TI (zero_extend:TI
3849 (truncate:DI
3850 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3851 (zero_extend:TI
3852 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3853 (ashift:TI
3854 (zero_extend:TI
3855 (truncate:DI
3856 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3857 (const_int 64))))]
3858 "TARGET_64BIT"
3859 "@
3860 dlgr\\t%0,%2
3861 dlg\\t%0,%2"
3862 [(set_attr "op_type" "RRE,RXE")
3863 (set_attr "type" "idiv")
3864 (set_attr "atype" "reg,mem")])
3865
3866 ;
3867 ; divmodsi4 instruction pattern(s).
3868 ;
3869
3870 (define_expand "divmodsi4"
3871 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3872 (div:SI (match_operand:SI 1 "general_operand" "")
3873 (match_operand:SI 2 "nonimmediate_operand" "")))
3874 (set (match_operand:SI 3 "general_operand" "")
3875 (mod:SI (match_dup 1) (match_dup 2)))])
3876 (clobber (match_dup 4))]
3877 "!TARGET_64BIT"
3878 "
3879 {
3880 rtx insn, div_equal, mod_equal, equal;
3881
3882 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3883 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3884 equal = gen_rtx_IOR (DImode,
3885 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3886 gen_rtx_ASHIFT (DImode,
3887 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3888 GEN_INT (32)));
3889
3890 operands[4] = gen_reg_rtx(DImode);
3891 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3892 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3893 REG_NOTES (insn) =
3894 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3895
3896 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3897 REG_NOTES (insn) =
3898 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3899
3900 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3901 REG_NOTES (insn) =
3902 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3903
3904 DONE;
3905 }")
3906
3907 (define_insn "divmoddisi3"
3908 [(set (match_operand:DI 0 "register_operand" "=d,d")
3909 (ior:DI (zero_extend:DI
3910 (truncate:SI
3911 (div:DI (match_operand:DI 1 "register_operand" "0,0")
3912 (sign_extend:DI
3913 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3914 (ashift:DI
3915 (zero_extend:DI
3916 (truncate:SI
3917 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
3918 (const_int 32))))]
3919 "!TARGET_64BIT"
3920 "@
3921 dr\\t%0,%2
3922 d\\t%0,%2"
3923 [(set_attr "op_type" "RR,RX")
3924 (set_attr "type" "idiv")
3925 (set_attr "atype" "reg,mem")])
3926
3927 ;
3928 ; udivsi3 and umodsi3 instruction pattern(s).
3929 ;
3930
3931
3932 (define_expand "udivsi3"
3933 [(set (match_operand:SI 0 "register_operand" "=d")
3934 (udiv:SI (match_operand:SI 1 "general_operand" "")
3935 (match_operand:SI 2 "general_operand" "")))
3936 (clobber (match_dup 3))]
3937 "!TARGET_64BIT"
3938 "
3939 {
3940 rtx insn, udiv_equal, umod_equal, equal;
3941
3942 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3943 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
3944 equal = gen_rtx_IOR (DImode,
3945 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
3946 gen_rtx_ASHIFT (DImode,
3947 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
3948 GEN_INT (32)));
3949
3950 operands[3] = gen_reg_rtx (DImode);
3951
3952 if (CONSTANT_P (operands[2]))
3953 {
3954 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3955 {
3956 rtx label1 = gen_label_rtx ();
3957
3958 operands[1] = make_safe_from (operands[1], operands[0]);
3959 emit_move_insn (operands[0], const0_rtx);
3960 emit_insn (gen_cmpsi (operands[1], operands[2]));
3961 emit_jump_insn (gen_bltu (label1));
3962 emit_move_insn (operands[0], const1_rtx);
3963 emit_label (label1);
3964 }
3965 else
3966 {
3967 operands[2] = force_reg (SImode, operands[2]);
3968 operands[2] = make_safe_from (operands[2], operands[0]);
3969
3970 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
3971 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
3972 operands[2]));
3973 REG_NOTES (insn) =
3974 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3975
3976 insn = emit_move_insn (operands[0],
3977 gen_lowpart (SImode, operands[3]));
3978 REG_NOTES (insn) =
3979 gen_rtx_EXPR_LIST (REG_EQUAL,
3980 udiv_equal, REG_NOTES (insn));
3981 }
3982 }
3983 else
3984 {
3985 rtx label1 = gen_label_rtx ();
3986 rtx label2 = gen_label_rtx ();
3987 rtx label3 = gen_label_rtx ();
3988
3989 operands[1] = force_reg (SImode, operands[1]);
3990 operands[1] = make_safe_from (operands[1], operands[0]);
3991 operands[2] = force_reg (SImode, operands[2]);
3992 operands[2] = make_safe_from (operands[2], operands[0]);
3993
3994 emit_move_insn (operands[0], const0_rtx);
3995 emit_insn (gen_cmpsi (operands[2], operands[1]));
3996 emit_jump_insn (gen_bgtu (label3));
3997 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3998 emit_jump_insn (gen_blt (label2));
3999 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4000 emit_jump_insn (gen_beq (label1));
4001 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4002 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4003 operands[2]));
4004 REG_NOTES (insn) =
4005 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4006
4007 insn = emit_move_insn (operands[0],
4008 gen_lowpart (SImode, operands[3]));
4009 REG_NOTES (insn) =
4010 gen_rtx_EXPR_LIST (REG_EQUAL,
4011 udiv_equal, REG_NOTES (insn));
4012 emit_jump (label3);
4013 emit_label (label1);
4014 emit_move_insn (operands[0], operands[1]);
4015 emit_jump (label3);
4016 emit_label (label2);
4017 emit_move_insn (operands[0], const1_rtx);
4018 emit_label (label3);
4019 }
4020 emit_move_insn (operands[0], operands[0]);
4021 DONE;
4022 }")
4023
4024 (define_expand "umodsi3"
4025 [(set (match_operand:SI 0 "register_operand" "=d")
4026 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4027 (match_operand:SI 2 "nonimmediate_operand" "")))
4028 (clobber (match_dup 3))]
4029 "!TARGET_64BIT"
4030 "
4031 {
4032 rtx insn, udiv_equal, umod_equal, equal;
4033
4034 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4035 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4036 equal = gen_rtx_IOR (DImode,
4037 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4038 gen_rtx_ASHIFT (DImode,
4039 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4040 GEN_INT (32)));
4041
4042 operands[3] = gen_reg_rtx (DImode);
4043
4044 if (CONSTANT_P (operands[2]))
4045 {
4046 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4047 {
4048 rtx label1 = gen_label_rtx ();
4049
4050 operands[1] = make_safe_from (operands[1], operands[0]);
4051 emit_move_insn (operands[0], operands[1]);
4052 emit_insn (gen_cmpsi (operands[0], operands[2]));
4053 emit_jump_insn (gen_bltu (label1));
4054 emit_insn (gen_abssi2 (operands[0], operands[2]));
4055 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4056 emit_label (label1);
4057 }
4058 else
4059 {
4060 operands[2] = force_reg (SImode, operands[2]);
4061 operands[2] = make_safe_from (operands[2], operands[0]);
4062
4063 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4064 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4065 operands[2]));
4066 REG_NOTES (insn) =
4067 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4068
4069 insn = emit_move_insn (operands[0],
4070 gen_highpart (SImode, operands[3]));
4071 REG_NOTES (insn) =
4072 gen_rtx_EXPR_LIST (REG_EQUAL,
4073 umod_equal, REG_NOTES (insn));
4074 }
4075 }
4076 else
4077 {
4078 rtx label1 = gen_label_rtx ();
4079 rtx label2 = gen_label_rtx ();
4080 rtx label3 = gen_label_rtx ();
4081
4082 operands[1] = force_reg (SImode, operands[1]);
4083 operands[1] = make_safe_from (operands[1], operands[0]);
4084 operands[2] = force_reg (SImode, operands[2]);
4085 operands[2] = make_safe_from (operands[2], operands[0]);
4086
4087 emit_move_insn(operands[0], operands[1]);
4088 emit_insn (gen_cmpsi (operands[2], operands[1]));
4089 emit_jump_insn (gen_bgtu (label3));
4090 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4091 emit_jump_insn (gen_blt (label2));
4092 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4093 emit_jump_insn (gen_beq (label1));
4094 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4095 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4096 operands[2]));
4097 REG_NOTES (insn) =
4098 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4099
4100 insn = emit_move_insn (operands[0],
4101 gen_highpart (SImode, operands[3]));
4102 REG_NOTES (insn) =
4103 gen_rtx_EXPR_LIST (REG_EQUAL,
4104 umod_equal, REG_NOTES (insn));
4105 emit_jump (label3);
4106 emit_label (label1);
4107 emit_move_insn (operands[0], const0_rtx);
4108 emit_jump (label3);
4109 emit_label (label2);
4110 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4111 emit_label (label3);
4112 }
4113 DONE;
4114 }")
4115
4116 ;
4117 ; divdf3 instruction pattern(s).
4118 ;
4119
4120 (define_expand "divdf3"
4121 [(parallel
4122 [(set (match_operand:DF 0 "register_operand" "=f,f")
4123 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4124 (match_operand:DF 2 "general_operand" "f,m")))
4125 (clobber (reg:CC 33))])]
4126 "TARGET_HARD_FLOAT"
4127 "")
4128
4129 (define_insn "*divdf3"
4130 [(set (match_operand:DF 0 "register_operand" "=f,f")
4131 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4132 (match_operand:DF 2 "general_operand" "f,m")))
4133 (clobber (reg:CC 33))]
4134 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4135 "@
4136 ddbr\\t%0,%2
4137 ddb\\t%0,%2"
4138 [(set_attr "op_type" "RRE,RXE")
4139 (set_attr "type" "fdiv")
4140 (set_attr "atype" "reg,mem")])
4141
4142 (define_insn "*divdf3_ibm"
4143 [(set (match_operand:DF 0 "register_operand" "=f,f")
4144 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4145 (match_operand:DF 2 "general_operand" "f,m")))
4146 (clobber (reg:CC 33))]
4147 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4148 "@
4149 ddr\\t%0,%2
4150 dd\\t%0,%2"
4151 [(set_attr "op_type" "RR,RX")
4152 (set_attr "type" "fdiv")
4153 (set_attr "atype" "reg,mem")])
4154
4155 ;
4156 ; divsf3 instruction pattern(s).
4157 ;
4158
4159 (define_expand "divsf3"
4160 [(parallel
4161 [(set (match_operand:SF 0 "register_operand" "=f,f")
4162 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4163 (match_operand:SF 2 "general_operand" "f,m")))
4164 (clobber (reg:CC 33))])]
4165 "TARGET_HARD_FLOAT"
4166 "")
4167
4168 (define_insn "*divsf3"
4169 [(set (match_operand:SF 0 "register_operand" "=f,f")
4170 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4171 (match_operand:SF 2 "general_operand" "f,m")))
4172 (clobber (reg:CC 33))]
4173 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4174 "@
4175 debr\\t%0,%2
4176 deb\\t%0,%2"
4177 [(set_attr "op_type" "RRE,RXE")
4178 (set_attr "type" "fdiv")
4179 (set_attr "atype" "reg,mem")])
4180
4181 (define_insn "*divsf3"
4182 [(set (match_operand:SF 0 "register_operand" "=f,f")
4183 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4184 (match_operand:SF 2 "general_operand" "f,m")))
4185 (clobber (reg:CC 33))]
4186 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4187 "@
4188 der\\t%0,%2
4189 de\\t%0,%2"
4190 [(set_attr "op_type" "RR,RX")
4191 (set_attr "type" "fdiv")
4192 (set_attr "atype" "reg,mem")])
4193
4194
4195 ;;
4196 ;;- And instructions.
4197 ;;
4198
4199 ;
4200 ; anddi3 instruction pattern(s).
4201 ;
4202
4203 (define_insn "*anddi3_cc"
4204 [(set (reg 33)
4205 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4206 (match_operand:DI 2 "general_operand" "d,m"))
4207 (const_int 0)))
4208 (set (match_operand:DI 0 "register_operand" "=d,d")
4209 (and:DI (match_dup 1) (match_dup 2)))]
4210 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4211 "@
4212 ngr\\t%0,%2
4213 ng\\t%0,%2"
4214 [(set_attr "op_type" "RRE,RXE")
4215 (set_attr "atype" "reg,mem")])
4216
4217 (define_insn "*anddi3_cconly"
4218 [(set (reg 33)
4219 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4220 (match_operand:DI 2 "general_operand" "d,m"))
4221 (const_int 0)))
4222 (clobber (match_scratch:DI 0 "=d,d"))]
4223 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4224 "@
4225 ngr\\t%0,%2
4226 ng\\t%0,%2"
4227 [(set_attr "op_type" "RRE,RXE")
4228 (set_attr "atype" "reg,mem")])
4229
4230 (define_insn "*anddi3_ni"
4231 [(set (match_operand:DI 0 "register_operand" "=d")
4232 (and:DI (match_operand:DI 1 "register_operand" "%0")
4233 (match_operand:DI 2 "immediate_operand" "n")))
4234 (clobber (reg:CC 33))]
4235 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4236 "*
4237 {
4238 int part = s390_single_hi (operands[2], DImode, -1);
4239 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4240
4241 switch (part)
4242 {
4243 case 0: return \"nihh\\t%0,%x2\";
4244 case 1: return \"nihl\\t%0,%x2\";
4245 case 2: return \"nilh\\t%0,%x2\";
4246 case 3: return \"nill\\t%0,%x2\";
4247 default: abort ();
4248 }
4249 }"
4250 [(set_attr "op_type" "RI")
4251 (set_attr "atype" "reg")])
4252
4253 (define_insn "anddi3"
4254 [(set (match_operand:DI 0 "register_operand" "=d,d")
4255 (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4256 (match_operand:DI 2 "general_operand" "d,m")))
4257 (clobber (reg:CC 33))]
4258 "TARGET_64BIT"
4259 "@
4260 ngr\\t%0,%2
4261 ng\\t%0,%2"
4262 [(set_attr "op_type" "RRE,RXE")
4263 (set_attr "atype" "reg,mem")])
4264
4265 (define_insn "*anddi3_ss"
4266 [(set (match_operand:DI 0 "s_operand" "=Qo")
4267 (and:DI (match_dup 0)
4268 (match_operand:DI 1 "s_imm_operand" "Qo")))
4269 (clobber (reg:CC 33))]
4270 ""
4271 "nc\\t%O0(8,%R0),%1"
4272 [(set_attr "op_type" "SS")
4273 (set_attr "atype" "mem")])
4274
4275 (define_insn "*anddi3_ss_inv"
4276 [(set (match_operand:DI 0 "s_operand" "=Qo")
4277 (and:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4278 (match_dup 0)))
4279 (clobber (reg:CC 33))]
4280 ""
4281 "nc\\t%O0(8,%R0),%1"
4282 [(set_attr "op_type" "SS")
4283 (set_attr "atype" "mem")])
4284
4285 ;
4286 ; andsi3 instruction pattern(s).
4287 ;
4288
4289 (define_insn "*andsi3_cc"
4290 [(set (reg 33)
4291 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4292 (match_operand:SI 2 "general_operand" "d,m"))
4293 (const_int 0)))
4294 (set (match_operand:SI 0 "register_operand" "=d,d")
4295 (and:SI (match_dup 1) (match_dup 2)))]
4296 "s390_match_ccmode(insn, CCTmode)"
4297 "@
4298 nr\\t%0,%2
4299 n\\t%0,%2"
4300 [(set_attr "op_type" "RR,RX")
4301 (set_attr "atype" "reg,mem")])
4302
4303 (define_insn "*andsi3_cconly"
4304 [(set (reg 33)
4305 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4306 (match_operand:SI 2 "general_operand" "d,m"))
4307 (const_int 0)))
4308 (clobber (match_scratch:SI 0 "=d,d"))]
4309 "s390_match_ccmode(insn, CCTmode)"
4310 "@
4311 nr\\t%0,%2
4312 n\\t%0,%2"
4313 [(set_attr "op_type" "RR,RX")
4314 (set_attr "atype" "reg,mem")])
4315
4316 (define_insn "*andsi3_ni"
4317 [(set (match_operand:SI 0 "register_operand" "=d")
4318 (and:SI (match_operand:SI 1 "register_operand" "%0")
4319 (match_operand:SI 2 "immediate_operand" "n")))
4320 (clobber (reg:CC 33))]
4321 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4322 "*
4323 {
4324 int part = s390_single_hi (operands[2], SImode, -1);
4325 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4326
4327 switch (part)
4328 {
4329 case 0: return \"nilh\\t%0,%x2\";
4330 case 1: return \"nill\\t%0,%x2\";
4331 default: abort ();
4332 }
4333 }"
4334 [(set_attr "op_type" "RI")
4335 (set_attr "atype" "reg")])
4336
4337 (define_insn "andsi3"
4338 [(set (match_operand:SI 0 "register_operand" "=d,d")
4339 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4340 (match_operand:SI 2 "general_operand" "d,m")))
4341 (clobber (reg:CC 33))]
4342 ""
4343 "@
4344 nr\\t%0,%2
4345 n\\t%0,%2"
4346 [(set_attr "op_type" "RR,RX")
4347 (set_attr "atype" "reg,mem")])
4348
4349 (define_insn "*andsi3_ss"
4350 [(set (match_operand:SI 0 "s_operand" "=Qo")
4351 (and:SI (match_dup 0)
4352 (match_operand:SI 1 "s_imm_operand" "Qo")))
4353 (clobber (reg:CC 33))]
4354 ""
4355 "nc\\t%O0(4,%R0),%1"
4356 [(set_attr "op_type" "SS")
4357 (set_attr "atype" "mem")])
4358
4359 (define_insn "*andsi3_ss_inv"
4360 [(set (match_operand:SI 0 "s_operand" "=Qo")
4361 (and:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4362 (match_dup 0)))
4363 (clobber (reg:CC 33))]
4364 ""
4365 "nc\\t%O0(4,%R0),%1"
4366 [(set_attr "op_type" "SS")
4367 (set_attr "atype" "mem")])
4368
4369 ;
4370 ; andhi3 instruction pattern(s).
4371 ;
4372
4373 (define_insn "*andhi3_ni"
4374 [(set (match_operand:HI 0 "register_operand" "=d,d")
4375 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4376 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4377 (clobber (reg:CC 33))]
4378 "TARGET_64BIT"
4379 "@
4380 nr\\t%0,%2
4381 nill\\t%0,%x2"
4382 [(set_attr "op_type" "RR,RI")
4383 (set_attr "atype" "reg")])
4384
4385 (define_insn "andhi3"
4386 [(set (match_operand:HI 0 "register_operand" "=d")
4387 (and:HI (match_operand:HI 1 "register_operand" "%0")
4388 (match_operand:HI 2 "nonmemory_operand" "d")))
4389 (clobber (reg:CC 33))]
4390 ""
4391 "nr\\t%0,%2"
4392 [(set_attr "op_type" "RR")
4393 (set_attr "atype" "reg")])
4394
4395 (define_insn "*andhi3_ss"
4396 [(set (match_operand:HI 0 "s_operand" "=Qo")
4397 (and:HI (match_dup 0)
4398 (match_operand:HI 1 "s_imm_operand" "Qo")))
4399 (clobber (reg:CC 33))]
4400 ""
4401 "nc\\t%O0(2,%R0),%1"
4402 [(set_attr "op_type" "SS")
4403 (set_attr "atype" "mem")])
4404
4405 (define_insn "*andhi3_ss_inv"
4406 [(set (match_operand:HI 0 "s_operand" "=Qo")
4407 (and:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4408 (match_dup 0)))
4409 (clobber (reg:CC 33))]
4410 ""
4411 "nc\\t%O0(2,%R0),%1"
4412 [(set_attr "op_type" "SS")
4413 (set_attr "atype" "mem")])
4414
4415 ;
4416 ; andqi3 instruction pattern(s).
4417 ;
4418
4419 (define_insn "*andqi3_ni"
4420 [(set (match_operand:QI 0 "register_operand" "=d,d")
4421 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4422 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4423 (clobber (reg:CC 33))]
4424 "TARGET_64BIT"
4425 "@
4426 nr\\t%0,%2
4427 nill\\t%0,%b2"
4428 [(set_attr "op_type" "RR,RI")
4429 (set_attr "atype" "reg")])
4430
4431 (define_insn "andqi3"
4432 [(set (match_operand:QI 0 "register_operand" "=d")
4433 (and:QI (match_operand:QI 1 "register_operand" "%0")
4434 (match_operand:QI 2 "nonmemory_operand" "d")))
4435 (clobber (reg:CC 33))]
4436 ""
4437 "nr\\t%0,%2"
4438 [(set_attr "op_type" "RR")
4439 (set_attr "atype" "reg")])
4440
4441 (define_insn "*andqi3_ss"
4442 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4443 (and:QI (match_dup 0)
4444 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4445 (clobber (reg:CC 33))]
4446 ""
4447 "@
4448 ni\\t%0,%b1
4449 nc\\t%O0(1,%R0),%1"
4450 [(set_attr "op_type" "SI,SS")
4451 (set_attr "atype" "mem")])
4452
4453 (define_insn "*andqi3_ss_inv"
4454 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4455 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4456 (match_dup 0)))
4457 (clobber (reg:CC 33))]
4458 ""
4459 "@
4460 ni\\t%0,%b1
4461 nc\\t%O0(1,%R0),%1"
4462 [(set_attr "op_type" "SI,SS")
4463 (set_attr "atype" "mem")])
4464
4465
4466 ;;
4467 ;;- Bit set (inclusive or) instructions.
4468 ;;
4469
4470 ;
4471 ; iordi3 instruction pattern(s).
4472 ;
4473
4474 (define_insn "*iordi3_cc"
4475 [(set (reg 33)
4476 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4477 (match_operand:DI 2 "general_operand" "d,m"))
4478 (const_int 0)))
4479 (set (match_operand:DI 0 "register_operand" "=d,d")
4480 (ior:DI (match_dup 1) (match_dup 2)))]
4481 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4482 "@
4483 ogr\\t%0,%2
4484 og\\t%0,%2"
4485 [(set_attr "op_type" "RRE,RXE")
4486 (set_attr "atype" "reg,mem")])
4487
4488 (define_insn "*iordi3_cconly"
4489 [(set (reg 33)
4490 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4491 (match_operand:DI 2 "general_operand" "d,m"))
4492 (const_int 0)))
4493 (clobber (match_scratch:DI 0 "=d,d"))]
4494 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4495 "@
4496 ogr\\t%0,%2
4497 og\\t%0,%2"
4498 [(set_attr "op_type" "RRE,RXE")
4499 (set_attr "atype" "reg,mem")])
4500
4501 (define_insn "*iordi3_oi"
4502 [(set (match_operand:DI 0 "register_operand" "=d")
4503 (ior:DI (match_operand:DI 1 "register_operand" "%0")
4504 (match_operand:DI 2 "immediate_operand" "n")))
4505 (clobber (reg:CC 33))]
4506 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4507 "*
4508 {
4509 int part = s390_single_hi (operands[2], DImode, 0);
4510 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4511
4512 switch (part)
4513 {
4514 case 0: return \"oihh\\t%0,%x2\";
4515 case 1: return \"oihl\\t%0,%x2\";
4516 case 2: return \"oilh\\t%0,%x2\";
4517 case 3: return \"oill\\t%0,%x2\";
4518 default: abort ();
4519 }
4520 }"
4521 [(set_attr "op_type" "RI")
4522 (set_attr "atype" "reg")])
4523
4524 (define_insn "iordi3"
4525 [(set (match_operand:DI 0 "register_operand" "=d,d")
4526 (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4527 (match_operand:DI 2 "general_operand" "d,m")))
4528 (clobber (reg:CC 33))]
4529 "TARGET_64BIT"
4530 "@
4531 ogr\\t%0,%2
4532 og\\t%0,%2"
4533 [(set_attr "op_type" "RRE,RXE")
4534 (set_attr "atype" "reg,mem")])
4535
4536 (define_insn "*iordi3_ss"
4537 [(set (match_operand:DI 0 "s_operand" "=Qo")
4538 (ior:DI (match_dup 0)
4539 (match_operand:DI 1 "s_imm_operand" "Qo")))
4540 (clobber (reg:CC 33))]
4541 ""
4542 "oc\\t%O0(8,%R0),%1"
4543 [(set_attr "op_type" "SS")
4544 (set_attr "atype" "mem")])
4545
4546 (define_insn "*iordi3_ss_inv"
4547 [(set (match_operand:DI 0 "s_operand" "=Qo")
4548 (ior:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4549 (match_dup 0)))
4550 (clobber (reg:CC 33))]
4551 ""
4552 "oc\\t%O0(8,%R0),%1"
4553 [(set_attr "op_type" "SS")
4554 (set_attr "atype" "mem")])
4555
4556 ;
4557 ; iorsi3 instruction pattern(s).
4558 ;
4559
4560 (define_insn "*iorsi3_cc"
4561 [(set (reg 33)
4562 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4563 (match_operand:SI 2 "general_operand" "d,m"))
4564 (const_int 0)))
4565 (set (match_operand:SI 0 "register_operand" "=d,d")
4566 (ior:SI (match_dup 1) (match_dup 2)))]
4567 "s390_match_ccmode(insn, CCTmode)"
4568 "@
4569 or\\t%0,%2
4570 o\\t%0,%2"
4571 [(set_attr "op_type" "RR,RX")
4572 (set_attr "atype" "reg,mem")])
4573
4574 (define_insn "*iorsi3_cconly"
4575 [(set (reg 33)
4576 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4577 (match_operand:SI 2 "general_operand" "d,m"))
4578 (const_int 0)))
4579 (clobber (match_scratch:SI 0 "=d,d"))]
4580 "s390_match_ccmode(insn, CCTmode)"
4581 "@
4582 or\\t%0,%2
4583 o\\t%0,%2"
4584 [(set_attr "op_type" "RR,RX")
4585 (set_attr "atype" "reg,mem")])
4586
4587 (define_insn "*iorsi3_oi"
4588 [(set (match_operand:SI 0 "register_operand" "=d")
4589 (ior:SI (match_operand:SI 1 "register_operand" "%0")
4590 (match_operand:SI 2 "immediate_operand" "n")))
4591 (clobber (reg:CC 33))]
4592 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4593 "*
4594 {
4595 int part = s390_single_hi (operands[2], SImode, 0);
4596 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4597
4598 switch (part)
4599 {
4600 case 0: return \"oilh\\t%0,%x2\";
4601 case 1: return \"oill\\t%0,%x2\";
4602 default: abort ();
4603 }
4604 }"
4605 [(set_attr "op_type" "RI")
4606 (set_attr "atype" "reg")])
4607
4608 (define_insn "iorsi3"
4609 [(set (match_operand:SI 0 "register_operand" "=d,d")
4610 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4611 (match_operand:SI 2 "general_operand" "d,m")))
4612 (clobber (reg:CC 33))]
4613 ""
4614 "@
4615 or\\t%0,%2
4616 o\\t%0,%2"
4617 [(set_attr "op_type" "RR,RX")
4618 (set_attr "atype" "reg,mem")])
4619
4620 (define_insn "*iorsi3_ss"
4621 [(set (match_operand:SI 0 "s_operand" "=Qo")
4622 (ior:SI (match_dup 0)
4623 (match_operand:SI 1 "s_imm_operand" "Qo")))
4624 (clobber (reg:CC 33))]
4625 ""
4626 "oc\\t%O0(4,%R0),%1"
4627 [(set_attr "op_type" "SS")
4628 (set_attr "atype" "mem")])
4629
4630 (define_insn "*iorsi3_ss_inv"
4631 [(set (match_operand:SI 0 "s_operand" "=Qo")
4632 (ior:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4633 (match_dup 0)))
4634 (clobber (reg:CC 33))]
4635 ""
4636 "oc\\t%O0(4,%R0),%1"
4637 [(set_attr "op_type" "SS")
4638 (set_attr "atype" "mem")])
4639
4640 ;
4641 ; iorhi3 instruction pattern(s).
4642 ;
4643
4644 (define_insn "*iorhi3_oi"
4645 [(set (match_operand:HI 0 "register_operand" "=d,d")
4646 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4647 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4648 (clobber (reg:CC 33))]
4649 "TARGET_64BIT"
4650 "@
4651 or\\t%0,%2
4652 oill\\t%0,%x2"
4653 [(set_attr "op_type" "RR,RI")
4654 (set_attr "atype" "reg")])
4655
4656 (define_insn "iorhi3"
4657 [(set (match_operand:HI 0 "register_operand" "=d")
4658 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4659 (match_operand:HI 2 "nonmemory_operand" "d")))
4660 (clobber (reg:CC 33))]
4661 ""
4662 "or\\t%0,%2"
4663 [(set_attr "op_type" "RR")
4664 (set_attr "atype" "reg")])
4665
4666 (define_insn "*iorhi3_ss"
4667 [(set (match_operand:HI 0 "s_operand" "=Qo")
4668 (ior:HI (match_dup 0)
4669 (match_operand:HI 1 "s_imm_operand" "Qo")))
4670 (clobber (reg:CC 33))]
4671 ""
4672 "oc\\t%O0(2,%R0),%1"
4673 [(set_attr "op_type" "SS")
4674 (set_attr "atype" "mem")])
4675
4676 (define_insn "*iorhi3_ss_inv"
4677 [(set (match_operand:HI 0 "s_operand" "=Qo")
4678 (ior:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4679 (match_dup 0)))
4680 (clobber (reg:CC 33))]
4681 ""
4682 "oc\\t%O0(2,%R0),%1"
4683 [(set_attr "op_type" "SS")
4684 (set_attr "atype" "mem")])
4685
4686 ;
4687 ; iorqi3 instruction pattern(s).
4688 ;
4689
4690 (define_insn "*iorqi3_oi"
4691 [(set (match_operand:QI 0 "register_operand" "=d,d")
4692 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4693 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4694 (clobber (reg:CC 33))]
4695 "TARGET_64BIT"
4696 "@
4697 or\\t%0,%2
4698 oill\\t%0,%b2"
4699 [(set_attr "op_type" "RR,RI")
4700 (set_attr "atype" "reg")])
4701
4702 (define_insn "iorqi3"
4703 [(set (match_operand:QI 0 "register_operand" "=d")
4704 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4705 (match_operand:QI 2 "nonmemory_operand" "d")))
4706 (clobber (reg:CC 33))]
4707 ""
4708 "or\\t%0,%2"
4709 [(set_attr "op_type" "RR")
4710 (set_attr "atype" "reg")])
4711
4712 (define_insn "*iorqi3_ss"
4713 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4714 (ior:QI (match_dup 0)
4715 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4716 (clobber (reg:CC 33))]
4717 ""
4718 "@
4719 oi\\t%0,%b1
4720 oc\\t%O0(1,%R0),%1"
4721 [(set_attr "op_type" "SI,SS")
4722 (set_attr "atype" "reg,mem")])
4723
4724 (define_insn "*iorqi3_ss_inv"
4725 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4726 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4727 (match_dup 0)))
4728 (clobber (reg:CC 33))]
4729 ""
4730 "@
4731 oi\\t%0,%b1
4732 oc\\t%O0(1,%R0),%1"
4733 [(set_attr "op_type" "SI,SS")
4734 (set_attr "atype" "reg,mem")])
4735
4736
4737 ;;
4738 ;;- Xor instructions.
4739 ;;
4740
4741 ;
4742 ; xordi3 instruction pattern(s).
4743 ;
4744
4745 (define_insn "*xordi3_cc"
4746 [(set (reg 33)
4747 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4748 (match_operand:DI 2 "general_operand" "d,m"))
4749 (const_int 0)))
4750 (set (match_operand:DI 0 "register_operand" "=d,d")
4751 (xor:DI (match_dup 1) (match_dup 2)))]
4752 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4753 "@
4754 xgr\\t%0,%2
4755 xg\\t%0,%2"
4756 [(set_attr "op_type" "RRE,RXE")
4757 (set_attr "atype" "reg,mem")])
4758
4759 (define_insn "*xordi3_cconly"
4760 [(set (reg 33)
4761 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4762 (match_operand:DI 2 "general_operand" "d,m"))
4763 (const_int 0)))
4764 (clobber (match_scratch:DI 0 "=d,d"))]
4765 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4766 "@
4767 xgr\\t%0,%2
4768 xr\\t%0,%2"
4769 [(set_attr "op_type" "RRE,RXE")
4770 (set_attr "atype" "reg,mem")])
4771
4772 (define_insn "xordi3"
4773 [(set (match_operand:DI 0 "register_operand" "=d,d")
4774 (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4775 (match_operand:DI 2 "general_operand" "d,m")))
4776 (clobber (reg:CC 33))]
4777 "TARGET_64BIT"
4778 "@
4779 xgr\\t%0,%2
4780 xg\\t%0,%2"
4781 [(set_attr "op_type" "RRE,RXE")
4782 (set_attr "atype" "reg,mem")])
4783
4784 (define_insn "*xordi3_ss"
4785 [(set (match_operand:DI 0 "s_operand" "=Qo")
4786 (xor:DI (match_dup 0)
4787 (match_operand:DI 1 "s_imm_operand" "Qo")))
4788 (clobber (reg:CC 33))]
4789 ""
4790 "xc\\t%O0(8,%R0),%1"
4791 [(set_attr "op_type" "SS")
4792 (set_attr "atype" "mem")])
4793
4794 (define_insn "*xordi3_ss_inv"
4795 [(set (match_operand:DI 0 "s_operand" "=Qo")
4796 (xor:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4797 (match_dup 0)))
4798 (clobber (reg:CC 33))]
4799 ""
4800 "xc\\t%O0(8,%R0),%1"
4801 [(set_attr "op_type" "SS")
4802 (set_attr "atype" "mem")])
4803
4804 ;
4805 ; xorsi3 instruction pattern(s).
4806 ;
4807
4808 (define_insn "*xorsi3_cc"
4809 [(set (reg 33)
4810 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4811 (match_operand:SI 2 "general_operand" "d,m"))
4812 (const_int 0)))
4813 (set (match_operand:SI 0 "register_operand" "=d,d")
4814 (xor:SI (match_dup 1) (match_dup 2)))]
4815 "s390_match_ccmode(insn, CCTmode)"
4816 "@
4817 xr\\t%0,%2
4818 x\\t%0,%2"
4819 [(set_attr "op_type" "RR,RX")
4820 (set_attr "atype" "reg,mem")])
4821
4822 (define_insn "*xorsi3_cconly"
4823 [(set (reg 33)
4824 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4825 (match_operand:SI 2 "general_operand" "d,m"))
4826 (const_int 0)))
4827 (clobber (match_scratch:SI 0 "=d,d"))]
4828 "s390_match_ccmode(insn, CCTmode)"
4829 "@
4830 xr\\t%0,%2
4831 x\\t%0,%2"
4832 [(set_attr "op_type" "RR,RX")
4833 (set_attr "atype" "reg,mem")])
4834
4835 (define_insn "xorsi3"
4836 [(set (match_operand:SI 0 "register_operand" "=d,d")
4837 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4838 (match_operand:SI 2 "general_operand" "d,m")))
4839 (clobber (reg:CC 33))]
4840 ""
4841 "@
4842 xr\\t%0,%2
4843 x\\t%0,%2"
4844 [(set_attr "op_type" "RR,RX")
4845 (set_attr "atype" "reg,mem")])
4846
4847 (define_insn "*xorsi3_ss"
4848 [(set (match_operand:SI 0 "s_operand" "=Qo")
4849 (xor:SI (match_dup 0)
4850 (match_operand:SI 1 "s_imm_operand" "Qo")))
4851 (clobber (reg:CC 33))]
4852 ""
4853 "xc\\t%O0(4,%R0),%1"
4854 [(set_attr "op_type" "SS")
4855 (set_attr "atype" "mem")])
4856
4857 (define_insn "*xorsi3_ss_inv"
4858 [(set (match_operand:SI 0 "s_operand" "=Qo")
4859 (xor:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4860 (match_dup 0)))
4861 (clobber (reg:CC 33))]
4862 ""
4863 "xc\\t%O0(4,%R0),%1"
4864 [(set_attr "op_type" "SS")
4865 (set_attr "atype" "mem")])
4866
4867 ;
4868 ; xorhi3 instruction pattern(s).
4869 ;
4870
4871 (define_insn "xorhi3"
4872 [(set (match_operand:HI 0 "register_operand" "=d")
4873 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4874 (match_operand:HI 2 "nonmemory_operand" "d")))
4875 (clobber (reg:CC 33))]
4876 ""
4877 "xr\\t%0,%2"
4878 [(set_attr "op_type" "RR")
4879 (set_attr "atype" "reg")])
4880
4881 (define_insn "*xorhi3_ss"
4882 [(set (match_operand:HI 0 "s_operand" "=Qo")
4883 (xor:HI (match_dup 0)
4884 (match_operand:HI 1 "s_imm_operand" "Qo")))
4885 (clobber (reg:CC 33))]
4886 ""
4887 "xc\\t%O0(2,%R0),%1"
4888 [(set_attr "op_type" "SS")
4889 (set_attr "atype" "mem")])
4890
4891 (define_insn "*xorhi3_ss_inv"
4892 [(set (match_operand:HI 0 "s_operand" "=Qo")
4893 (xor:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4894 (match_dup 0)))
4895 (clobber (reg:CC 33))]
4896 ""
4897 "xc\\t%O0(2,%R0),%1"
4898 [(set_attr "op_type" "SS")
4899 (set_attr "atype" "mem")])
4900
4901 ;
4902 ; xorqi3 instruction pattern(s).
4903 ;
4904
4905 (define_insn "xorqi3"
4906 [(set (match_operand:QI 0 "register_operand" "=d")
4907 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4908 (match_operand:QI 2 "nonmemory_operand" "d")))
4909 (clobber (reg:CC 33))]
4910 ""
4911 "xr\\t%0,%2"
4912 [(set_attr "op_type" "RR")
4913 (set_attr "atype" "reg")])
4914
4915 (define_insn "*xorqi3_ss"
4916 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4917 (xor:QI (match_dup 0)
4918 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4919 (clobber (reg:CC 33))]
4920 ""
4921 "@
4922 xi\\t%0,%b1
4923 xc\\t%O0(1,%R0),%1"
4924 [(set_attr "op_type" "SI,SS")
4925 (set_attr "atype" "mem")])
4926
4927 (define_insn "*xorqi3_ss_inv"
4928 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4929 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4930 (match_dup 0)))
4931 (clobber (reg:CC 33))]
4932 ""
4933 "@
4934 xi\\t%0,%b1
4935 xc\\t%O0(1,%R0),%1"
4936 [(set_attr "op_type" "SI,SS")
4937 (set_attr "atype" "mem")])
4938
4939
4940 ;;
4941 ;;- Negate instructions.
4942 ;;
4943
4944 ;
4945 ; negdi2 instruction pattern(s).
4946 ;
4947
4948 (define_expand "negdi2"
4949 [(parallel
4950 [(set (match_operand:DI 0 "register_operand" "=d")
4951 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4952 (clobber (reg:CC 33))])]
4953 ""
4954 "")
4955
4956 (define_insn "*negdi2_64"
4957 [(set (match_operand:DI 0 "register_operand" "=d")
4958 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4959 (clobber (reg:CC 33))]
4960 "TARGET_64BIT"
4961 "lcgr\\t%0,%1"
4962 [(set_attr "op_type" "RR")])
4963
4964 (define_insn "*negdi2_31"
4965 [(set (match_operand:DI 0 "register_operand" "=d")
4966 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4967 (clobber (reg:CC 33))]
4968 "!TARGET_64BIT"
4969 "*
4970 {
4971 rtx xop[1];
4972 xop[0] = gen_label_rtx ();
4973 output_asm_insn (\"lcr\\t%0,%1\", operands);
4974 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
4975 output_asm_insn (\"je\\t%l0\", xop);
4976 output_asm_insn (\"bctr\\t%0,0\", operands);
4977 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4978 CODE_LABEL_NUMBER (xop[0]));
4979 return \"\";
4980 }"
4981 [(set_attr "op_type" "NN")
4982 (set_attr "type" "other")
4983 (set_attr "length" "10")])
4984
4985 ;
4986 ; negsi2 instruction pattern(s).
4987 ;
4988
4989 (define_insn "negsi2"
4990 [(set (match_operand:SI 0 "register_operand" "=d")
4991 (neg:SI (match_operand:SI 1 "register_operand" "d")))
4992 (clobber (reg:CC 33))]
4993 ""
4994 "lcr\\t%0,%1"
4995 [(set_attr "op_type" "RR")])
4996
4997 ;
4998 ; negdf2 instruction pattern(s).
4999 ;
5000
5001 (define_expand "negdf2"
5002 [(parallel
5003 [(set (match_operand:DF 0 "register_operand" "=f")
5004 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5005 (clobber (reg:CC 33))])]
5006 "TARGET_HARD_FLOAT"
5007 "")
5008
5009 (define_insn "*negdf2"
5010 [(set (match_operand:DF 0 "register_operand" "=f")
5011 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5012 (clobber (reg:CC 33))]
5013 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5014 "lcdbr\\t%0,%1"
5015 [(set_attr "op_type" "RRE")])
5016
5017 (define_insn "*negdf2_ibm"
5018 [(set (match_operand:DF 0 "register_operand" "=f")
5019 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5020 (clobber (reg:CC 33))]
5021 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5022 "lcdr\\t%0,%1"
5023 [(set_attr "op_type" "RR")])
5024
5025 ;
5026 ; negsf2 instruction pattern(s).
5027 ;
5028
5029 (define_expand "negsf2"
5030 [(parallel
5031 [(set (match_operand:SF 0 "register_operand" "=f")
5032 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5033 (clobber (reg:CC 33))])]
5034 "TARGET_HARD_FLOAT"
5035 "")
5036
5037 (define_insn "*negsf2"
5038 [(set (match_operand:SF 0 "register_operand" "=f")
5039 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5040 (clobber (reg:CC 33))]
5041 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5042 "lcebr\\t%0,%1"
5043 [(set_attr "op_type" "RRE")])
5044
5045 (define_insn "*negsf2"
5046 [(set (match_operand:SF 0 "register_operand" "=f")
5047 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5048 (clobber (reg:CC 33))]
5049 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5050 "lcer\\t%0,%1"
5051 [(set_attr "op_type" "RR")])
5052
5053
5054 ;;
5055 ;;- Absolute value instructions.
5056 ;;
5057
5058 ;
5059 ; absdi2 instruction pattern(s).
5060 ;
5061
5062 (define_insn "absdi2"
5063 [(set (match_operand:DI 0 "register_operand" "=d")
5064 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5065 (clobber (reg:CC 33))]
5066 "TARGET_64BIT"
5067 "lpgr\\t%0,%1"
5068 [(set_attr "op_type" "RRE")])
5069
5070 ;
5071 ; abssi2 instruction pattern(s).
5072 ;
5073
5074 (define_insn "abssi2"
5075 [(set (match_operand:SI 0 "register_operand" "=d")
5076 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5077 (clobber (reg:CC 33))]
5078 ""
5079 "lpr\\t%0,%1"
5080 [(set_attr "op_type" "RR")])
5081
5082 ;
5083 ; absdf2 instruction pattern(s).
5084 ;
5085
5086 (define_expand "absdf2"
5087 [(parallel
5088 [(set (match_operand:DF 0 "register_operand" "=f")
5089 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5090 (clobber (reg:CC 33))])]
5091 "TARGET_HARD_FLOAT"
5092 "")
5093
5094 (define_insn "*absdf2"
5095 [(set (match_operand:DF 0 "register_operand" "=f")
5096 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5097 (clobber (reg:CC 33))]
5098 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5099 "lpdbr\\t%0,%1"
5100 [(set_attr "op_type" "RRE")])
5101
5102 (define_insn "*absdf2_ibm"
5103 [(set (match_operand:DF 0 "register_operand" "=f")
5104 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5105 (clobber (reg:CC 33))]
5106 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5107 "lpdr\\t%0,%1"
5108 [(set_attr "op_type" "RR")])
5109
5110 ;
5111 ; abssf2 instruction pattern(s).
5112 ;
5113
5114 (define_expand "abssf2"
5115 [(parallel
5116 [(set (match_operand:SF 0 "register_operand" "=f")
5117 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5118 (clobber (reg:CC 33))])]
5119 "TARGET_HARD_FLOAT"
5120 "")
5121
5122 (define_insn "*abssf2"
5123 [(set (match_operand:SF 0 "register_operand" "=f")
5124 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5125 (clobber (reg:CC 33))]
5126 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5127 "lpebr\\t%0,%1"
5128 [(set_attr "op_type" "RRE")])
5129
5130 (define_insn "*abssf2_ibm"
5131 [(set (match_operand:SF 0 "register_operand" "=f")
5132 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5133 (clobber (reg:CC 33))]
5134 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5135 "lper\\t%0,%1"
5136 [(set_attr "op_type" "RR")])
5137
5138 ;;
5139 ;;- Square root instructions.
5140 ;;
5141
5142 ;
5143 ; sqrtdf2 instruction pattern(s).
5144 ;
5145
5146 (define_insn "sqrtdf2"
5147 [(set (match_operand:DF 0 "register_operand" "=f,f")
5148 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5149 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5150 "@
5151 sqdbr\\t%0,%1
5152 sqdb\\t%0,%1"
5153 [(set_attr "op_type" "RRE,RSE")])
5154
5155 ;
5156 ; sqrtsf2 instruction pattern(s).
5157 ;
5158
5159 (define_insn "sqrtsf2"
5160 [(set (match_operand:SF 0 "register_operand" "=f,f")
5161 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5162 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5163 "@
5164 sqebr\\t%0,%1
5165 sqeb\\t%0,%1"
5166 [(set_attr "op_type" "RRE,RSE")])
5167
5168 ;;
5169 ;;- One complement instructions.
5170 ;;
5171
5172 ;
5173 ; one_cmpldi2 instruction pattern(s).
5174 ;
5175
5176 (define_expand "one_cmpldi2"
5177 [(parallel
5178 [(set (match_operand:DI 0 "register_operand" "")
5179 (xor:DI (match_operand:DI 1 "register_operand" "")
5180 (const_int -1)))
5181 (clobber (reg:CC 33))])]
5182 "TARGET_64BIT"
5183 "")
5184
5185 ;
5186 ; one_cmplsi2 instruction pattern(s).
5187 ;
5188
5189 (define_expand "one_cmplsi2"
5190 [(parallel
5191 [(set (match_operand:SI 0 "register_operand" "")
5192 (xor:SI (match_operand:SI 1 "register_operand" "")
5193 (const_int -1)))
5194 (clobber (reg:CC 33))])]
5195 ""
5196 "")
5197
5198 ;
5199 ; one_cmplhi2 instruction pattern(s).
5200 ;
5201
5202 (define_expand "one_cmplhi2"
5203 [(parallel
5204 [(set (match_operand:HI 0 "register_operand" "")
5205 (xor:HI (match_operand:HI 1 "register_operand" "")
5206 (const_int -1)))
5207 (clobber (reg:CC 33))])]
5208 ""
5209 "")
5210
5211 ;
5212 ; one_cmplqi2 instruction pattern(s).
5213 ;
5214
5215 (define_expand "one_cmplqi2"
5216 [(parallel
5217 [(set (match_operand:QI 0 "register_operand" "")
5218 (xor:QI (match_operand:QI 1 "register_operand" "")
5219 (const_int -1)))
5220 (clobber (reg:CC 33))])]
5221 ""
5222 "")
5223
5224
5225 ;;
5226 ;;- Rotate instructions.
5227 ;;
5228
5229 ;
5230 ; rotldi3 instruction pattern(s).
5231 ;
5232
5233 (define_insn "rotldi3"
5234 [(set (match_operand:DI 0 "register_operand" "=d,d")
5235 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5236 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5237 "TARGET_64BIT"
5238 "@
5239 rllg\\t%0,%1,%c2
5240 rllg\\t%0,%1,0(%2)"
5241 [(set_attr "op_type" "RSE")])
5242
5243 ;
5244 ; rotlsi3 instruction pattern(s).
5245 ;
5246
5247 (define_insn "rotlsi3"
5248 [(set (match_operand:SI 0 "register_operand" "=d,d")
5249 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5250 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5251 "TARGET_64BIT"
5252 "@
5253 rll\\t%0,%1,%c2
5254 rll\\t%0,%1,0(%2)"
5255 [(set_attr "op_type" "RSE")])
5256
5257
5258 ;;
5259 ;;- Arithmetic shift instructions.
5260 ;;
5261
5262 ;
5263 ; ashldi3 instruction pattern(s).
5264 ;
5265
5266 (define_expand "ashldi3"
5267 [(set (match_operand:DI 0 "register_operand" "")
5268 (ashift:DI (match_operand:DI 1 "register_operand" "")
5269 (match_operand:SI 2 "nonmemory_operand" "")))]
5270 ""
5271 "")
5272
5273 (define_insn "*ashldi3_31"
5274 [(set (match_operand:DI 0 "register_operand" "=d,d")
5275 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5276 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5277 "!TARGET_64BIT"
5278 "@
5279 sldl\\t%0,%c2
5280 sldl\\t%0,0(%2)"
5281 [(set_attr "op_type" "RS")])
5282
5283 (define_insn "*ashldi3_64"
5284 [(set (match_operand:DI 0 "register_operand" "=d,d")
5285 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5286 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5287 "TARGET_64BIT"
5288 "@
5289 sllg\\t%0,%1,%2
5290 sllg\\t%0,%1,0(%2)"
5291 [(set_attr "op_type" "RSE")])
5292
5293 ;
5294 ; ashrdi3 instruction pattern(s).
5295 ;
5296
5297 (define_expand "ashrdi3"
5298 [(parallel
5299 [(set (match_operand:DI 0 "register_operand" "")
5300 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5301 (match_operand:SI 2 "nonmemory_operand" "")))
5302 (clobber (reg:CC 33))])]
5303 ""
5304 "")
5305
5306 (define_insn "*ashrdi3_cc_31"
5307 [(set (reg 33)
5308 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5309 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5310 (const_int 0)))
5311 (set (match_operand:DI 0 "register_operand" "=d,d")
5312 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5313 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5314 "@
5315 srda\\t%0,%c2
5316 srda\\t%0,0(%2)"
5317 [(set_attr "op_type" "RS")])
5318
5319 (define_insn "*ashrdi3_cconly_31"
5320 [(set (reg 33)
5321 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5322 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5323 (const_int 0)))
5324 (clobber (match_scratch:DI 0 "=d,d"))]
5325 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5326 "@
5327 srda\\t%0,%c2
5328 srda\\t%0,0(%2)"
5329 [(set_attr "op_type" "RS")])
5330
5331 (define_insn "*ashrdi3_31"
5332 [(set (match_operand:DI 0 "register_operand" "=d,d")
5333 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5334 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5335 (clobber (reg:CC 33))]
5336 "!TARGET_64BIT"
5337 "@
5338 srda\\t%0,%c2
5339 srda\\t%0,0(%2)"
5340 [(set_attr "op_type" "RS")])
5341
5342 (define_insn "*ashrdi3_cc_64"
5343 [(set (reg 33)
5344 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5345 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5346 (const_int 0)))
5347 (set (match_operand:DI 0 "register_operand" "=d,d")
5348 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5349 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5350 "@
5351 srag\\t%0,%1,%c2
5352 srag\\t%0,%1,0(%2)"
5353 [(set_attr "op_type" "RSE")])
5354
5355 (define_insn "*ashrdi3_cconly_64"
5356 [(set (reg 33)
5357 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5358 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5359 (const_int 0)))
5360 (clobber (match_scratch:DI 0 "=d,d"))]
5361 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5362 "@
5363 srag\\t%0,%1,%c2
5364 srag\\t%0,%1,0(%2)"
5365 [(set_attr "op_type" "RSE")])
5366
5367 (define_insn "*ashrdi3_64"
5368 [(set (match_operand:DI 0 "register_operand" "=d,d")
5369 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5370 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5371 (clobber (reg:CC 33))]
5372 "TARGET_64BIT"
5373 "@
5374 srag\\t%0,%1,%c2
5375 srag\\t%0,%1,0(%2)"
5376 [(set_attr "op_type" "RSE")])
5377
5378 ;
5379 ; ashlsi3 instruction pattern(s).
5380 ;
5381
5382 (define_insn "ashlsi3"
5383 [(set (match_operand:SI 0 "register_operand" "=d,d")
5384 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5385 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5386 ""
5387 "@
5388 sll\\t%0,%c2
5389 sll\\t%0,0(%2)"
5390 [(set_attr "op_type" "RS")])
5391
5392 ;
5393 ; ashrsi3 instruction pattern(s).
5394 ;
5395
5396 (define_insn "*ashrsi3_cc"
5397 [(set (reg 33)
5398 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5399 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5400 (const_int 0)))
5401 (set (match_operand:SI 0 "register_operand" "=d,d")
5402 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5403 "s390_match_ccmode(insn, CCSmode)"
5404 "@
5405 sra\\t%0,%c2
5406 sra\\t%0,0(%2)"
5407 [(set_attr "op_type" "RS")])
5408
5409 (define_insn "*ashrsi3_cconly"
5410 [(set (reg 33)
5411 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5412 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5413 (const_int 0)))
5414 (clobber (match_scratch:SI 0 "=d,d"))]
5415 "s390_match_ccmode(insn, CCSmode)"
5416 "@
5417 sra\\t%0,%c2
5418 sra\\t%0,0(%2)"
5419 [(set_attr "op_type" "RS")])
5420
5421 (define_insn "ashrsi3"
5422 [(set (match_operand:SI 0 "register_operand" "=d,d")
5423 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5424 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5425 (clobber (reg:CC 33))]
5426 ""
5427 "@
5428 sra\\t%0,%c2
5429 sra\\t%0,0(%2)"
5430 [(set_attr "op_type" "RS")])
5431
5432
5433 ;;
5434 ;;- logical shift instructions.
5435 ;;
5436
5437 ;
5438 ; lshrdi3 instruction pattern(s).
5439 ;
5440
5441 (define_expand "lshrdi3"
5442 [(set (match_operand:DI 0 "register_operand" "")
5443 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5444 (match_operand:SI 2 "nonmemory_operand" "")))]
5445 ""
5446 "")
5447
5448 (define_insn "*lshrdi3_31"
5449 [(set (match_operand:DI 0 "register_operand" "=d,d")
5450 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5451 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5452 "!TARGET_64BIT"
5453 "@
5454 srdl\\t%0,%c2
5455 srdl\\t%0,0(%2)"
5456 [(set_attr "op_type" "RS,RS")])
5457
5458 (define_insn "*lshrdi3_64"
5459 [(set (match_operand:DI 0 "register_operand" "=d,d")
5460 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5461 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5462 "TARGET_64BIT"
5463 "@
5464 srlg\\t%0,%1,%c2
5465 srlg\\t%0,%1,0(%2)"
5466 [(set_attr "op_type" "RS,RS")])
5467
5468 ;
5469 ; lshrsi3 instruction pattern(s).
5470 ;
5471
5472 (define_insn "lshrsi3"
5473 [(set (match_operand:SI 0 "register_operand" "=d,d")
5474 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5475 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5476 ""
5477 "@
5478 srl\\t%0,%c2
5479 srl\\t%0,0(%2)"
5480 [(set_attr "op_type" "RS")])
5481
5482
5483 ;;
5484 ;; Branch instruction patterns.
5485 ;;
5486
5487 (define_expand "beq"
5488 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5489 (set (pc)
5490 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5491 (label_ref (match_operand 0 "" ""))
5492 (pc)))]
5493 ""
5494 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5495
5496 (define_expand "bne"
5497 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5498 (set (pc)
5499 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5500 (label_ref (match_operand 0 "" ""))
5501 (pc)))]
5502 ""
5503 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5504
5505 (define_expand "bgt"
5506 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5507 (set (pc)
5508 (if_then_else (gt (reg:CCS 33) (const_int 0))
5509 (label_ref (match_operand 0 "" ""))
5510 (pc)))]
5511 ""
5512 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5513
5514 (define_expand "bgtu"
5515 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5516 (set (pc)
5517 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5518 (label_ref (match_operand 0 "" ""))
5519 (pc)))]
5520 ""
5521 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5522
5523 (define_expand "blt"
5524 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5525 (set (pc)
5526 (if_then_else (lt (reg:CCS 33) (const_int 0))
5527 (label_ref (match_operand 0 "" ""))
5528 (pc)))]
5529 ""
5530 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5531
5532 (define_expand "bltu"
5533 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5534 (set (pc)
5535 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5536 (label_ref (match_operand 0 "" ""))
5537 (pc)))]
5538 ""
5539 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5540
5541 (define_expand "bge"
5542 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5543 (set (pc)
5544 (if_then_else (ge (reg:CCS 33) (const_int 0))
5545 (label_ref (match_operand 0 "" ""))
5546 (pc)))]
5547 ""
5548 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5549
5550 (define_expand "bgeu"
5551 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5552 (set (pc)
5553 (if_then_else (geu (reg:CCU 33) (const_int 0))
5554 (label_ref (match_operand 0 "" ""))
5555 (pc)))]
5556 ""
5557 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5558
5559 (define_expand "ble"
5560 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5561 (set (pc)
5562 (if_then_else (le (reg:CCS 33) (const_int 0))
5563 (label_ref (match_operand 0 "" ""))
5564 (pc)))]
5565 ""
5566 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5567
5568 (define_expand "bleu"
5569 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5570 (set (pc)
5571 (if_then_else (leu (reg:CCU 33) (const_int 0))
5572 (label_ref (match_operand 0 "" ""))
5573 (pc)))]
5574 ""
5575 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5576
5577 (define_expand "bunordered"
5578 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5579 (set (pc)
5580 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5581 (label_ref (match_operand 0 "" ""))
5582 (pc)))]
5583 ""
5584 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5585
5586 (define_expand "bordered"
5587 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5588 (set (pc)
5589 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5590 (label_ref (match_operand 0 "" ""))
5591 (pc)))]
5592 ""
5593 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5594
5595 (define_expand "buneq"
5596 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5597 (set (pc)
5598 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5599 (label_ref (match_operand 0 "" ""))
5600 (pc)))]
5601 ""
5602 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5603
5604 (define_expand "bungt"
5605 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5606 (set (pc)
5607 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5608 (label_ref (match_operand 0 "" ""))
5609 (pc)))]
5610 ""
5611 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5612
5613 (define_expand "bunlt"
5614 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5615 (set (pc)
5616 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5617 (label_ref (match_operand 0 "" ""))
5618 (pc)))]
5619 ""
5620 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5621
5622 (define_expand "bunge"
5623 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5624 (set (pc)
5625 (if_then_else (unge (reg:CCS 33) (const_int 0))
5626 (label_ref (match_operand 0 "" ""))
5627 (pc)))]
5628 ""
5629 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5630
5631 (define_expand "bunle"
5632 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5633 (set (pc)
5634 (if_then_else (unle (reg:CCS 33) (const_int 0))
5635 (label_ref (match_operand 0 "" ""))
5636 (pc)))]
5637 ""
5638 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5639
5640 (define_expand "bltgt"
5641 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5642 (set (pc)
5643 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5644 (label_ref (match_operand 0 "" ""))
5645 (pc)))]
5646 ""
5647 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5648
5649
5650 ;;
5651 ;;- Conditional jump instructions.
5652 ;;
5653
5654 (define_insn "cjump"
5655 [(set (pc)
5656 (if_then_else
5657 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5658 (label_ref (match_operand 0 "" ""))
5659 (pc)))]
5660 ""
5661 "*
5662 {
5663 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5664 return \"j%C1\\t%l0\";
5665 else
5666 return \"jg%C1\\t%l0\";
5667 }"
5668 [(set_attr "op_type" "RI")
5669 (set (attr "length") (if_then_else
5670 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5671 (const_int 4) (const_int 6)))])
5672
5673 (define_insn "*cjump_long"
5674 [(set (pc)
5675 (if_then_else
5676 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5677 (match_operand 0 "address_operand" "p")
5678 (pc)))]
5679 ""
5680 "*
5681 {
5682 if (get_attr_op_type (insn) == OP_TYPE_RR)
5683 return \"b%C1r\\t%0\";
5684 else
5685 return \"b%C1\\t%a0\";
5686 }"
5687 [(set (attr "op_type")
5688 (if_then_else (match_operand 0 "register_operand" "")
5689 (const_string "RR") (const_string "RX")))
5690 (set_attr "atype" "mem")])
5691
5692
5693 ;;
5694 ;;- Negated conditional jump instructions.
5695 ;;
5696
5697 (define_insn "icjump"
5698 [(set (pc)
5699 (if_then_else
5700 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5701 (pc)
5702 (label_ref (match_operand 0 "" ""))))]
5703 ""
5704 "*
5705 {
5706 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5707 return \"j%D1\\t%l0\";
5708 else
5709 return \"jg%D1\\t%l0\";
5710 }"
5711 [(set_attr "op_type" "RI")
5712 (set (attr "length") (if_then_else
5713 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5714 (const_int 4) (const_int 6)))])
5715
5716 (define_insn "*icjump_long"
5717 [(set (pc)
5718 (if_then_else
5719 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5720 (pc)
5721 (match_operand 0 "address_operand" "p")))]
5722 ""
5723 "*
5724 {
5725 if (get_attr_op_type (insn) == OP_TYPE_RR)
5726 return \"b%D1r\\t%0\";
5727 else
5728 return \"b%D1\\t%a0\";
5729 }"
5730 [(set (attr "op_type")
5731 (if_then_else (match_operand 0 "register_operand" "")
5732 (const_string "RR") (const_string "RX")))
5733 (set_attr "atype" "mem")])
5734
5735
5736 ;;
5737 ;;- Subtract one and jump if not zero.
5738 ;;
5739
5740 ;(define_expand "decrement_and_branch_on_count"
5741 ; [(use (match_operand 0 "register_operand" ""))
5742 ; (use (label_ref (match_operand 1 "" "")))]
5743 ; ""
5744 ; "
5745 ;{
5746 ;/* if (TARGET_64BIT)
5747 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5748 ; else */
5749 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5750 ; DONE;
5751 ;}")
5752 ;
5753 ;(define_insn "brctsi"
5754 ; [(set (pc)
5755 ; (if_then_else
5756 ; (ne (match_operand:SI 0 "register_operand" "+a")
5757 ; (const_int 1))
5758 ; (label_ref (match_operand 1 "" ""))
5759 ; (pc)))
5760 ; (set (match_dup 0)
5761 ; (plus:SI (match_dup 0) (const_int -1)))]
5762 ; ""
5763 ; "brct\\t%0,%l1"
5764 ; [(set_attr "op_type" "RI")
5765 ; (set_attr "type" "branch")]
5766 ;)
5767 ;
5768 ;(define_insn "ibrctsi"
5769 ; [(set (pc)
5770 ; (if_then_else
5771 ; (eq (match_operand:SI 0 "register_operand" "+a")
5772 ; (const_int 1))
5773 ; (pc)
5774 ; (label_ref (match_operand 1 "" ""))))
5775 ; (set (match_dup 0)
5776 ; (plus:SI (match_dup 0) (const_int -1)))]
5777 ; ""
5778 ; "brct\\t%0,%l1"
5779 ; [(set_attr "op_type" "RI")
5780 ; (set_attr "type" "branch")]
5781 ;)
5782
5783
5784 ;;
5785 ;;- Unconditional jump instructions.
5786 ;;
5787
5788 ;
5789 ; jump instruction pattern(s).
5790 ;
5791
5792 (define_insn "jump"
5793 [(set (pc) (label_ref (match_operand 0 "" "")))]
5794 ""
5795 "*
5796 {
5797 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5798 return \"j\\t%l0\";
5799 else
5800 return \"jg\\t%l0\";
5801 }"
5802 [(set_attr "op_type" "RI")
5803 (set (attr "length") (if_then_else
5804 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5805 (const_int 4) (const_int 6)))])
5806
5807 ;
5808 ; indirect-jump instruction pattern(s).
5809 ;
5810
5811 (define_insn "indirect_jump"
5812 [(set (pc) (match_operand 0 "address_operand" "p"))]
5813 ""
5814 "*
5815 {
5816 if (get_attr_op_type (insn) == OP_TYPE_RR)
5817 return \"br\\t%0\";
5818 else
5819 return \"b\\t%a0\";
5820 }"
5821 [(set (attr "op_type")
5822 (if_then_else (match_operand 0 "register_operand" "")
5823 (const_string "RR") (const_string "RX")))
5824 (set_attr "atype" "mem")])
5825
5826 ;
5827 ; casesi instruction pattern(s).
5828 ;
5829
5830 (define_insn "casesi_jump"
5831 [(set (pc) (match_operand 0 "address_operand" "p"))
5832 (use (label_ref (match_operand 1 "" "")))]
5833 ""
5834 "*
5835 {
5836 if (get_attr_op_type (insn) == OP_TYPE_RR)
5837 return \"br\\t%0\";
5838 else
5839 return \"b\\t%a0\";
5840 }"
5841 [(set (attr "op_type")
5842 (if_then_else (match_operand 0 "register_operand" "")
5843 (const_string "RR") (const_string "RX")))
5844 (set_attr "atype" "mem")])
5845
5846 (define_expand "casesi"
5847 [(match_operand:SI 0 "general_operand" "")
5848 (match_operand:SI 1 "general_operand" "")
5849 (match_operand:SI 2 "general_operand" "")
5850 (label_ref (match_operand 3 "" ""))
5851 (label_ref (match_operand 4 "" ""))]
5852 ""
5853 "
5854 {
5855 rtx index = gen_reg_rtx (SImode);
5856 rtx base = gen_reg_rtx (Pmode);
5857 rtx target = gen_reg_rtx (Pmode);
5858
5859 emit_move_insn (index, operands[0]);
5860 emit_insn (gen_subsi3 (index, index, operands[1]));
5861 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
5862 operands[4]);
5863
5864 if (Pmode != SImode)
5865 index = convert_to_mode (Pmode, index, 1);
5866 if (GET_CODE (index) != REG)
5867 index = copy_to_mode_reg (Pmode, index);
5868
5869 if (TARGET_64BIT)
5870 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
5871 else
5872 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
5873
5874 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
5875
5876 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
5877 emit_move_insn (target, index);
5878
5879 if (flag_pic)
5880 target = gen_rtx_PLUS (Pmode, base, target);
5881 emit_jump_insn (gen_casesi_jump (target, operands[3]));
5882
5883 DONE;
5884 }")
5885
5886
5887 ;;
5888 ;;- Jump to subroutine.
5889 ;;
5890 ;;
5891
5892 ;
5893 ; untyped call instruction pattern(s).
5894 ;
5895
5896 ;; Call subroutine returning any type.
5897 (define_expand "untyped_call"
5898 [(parallel [(call (match_operand 0 "" "")
5899 (const_int 0))
5900 (match_operand 1 "" "")
5901 (match_operand 2 "" "")])]
5902 ""
5903 "
5904 {
5905 int i;
5906
5907 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
5908
5909 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5910 {
5911 rtx set = XVECEXP (operands[2], 0, i);
5912 emit_move_insn (SET_DEST (set), SET_SRC (set));
5913 }
5914
5915 /* The optimizer does not know that the call sets the function value
5916 registers we stored in the result block. We avoid problems by
5917 claiming that all hard registers are used and clobbered at this
5918 point. */
5919 emit_insn (gen_blockage ());
5920
5921 DONE;
5922 }")
5923
5924 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5925 ;; all of memory. This blocks insns from being moved across this point.
5926
5927 (define_insn "blockage"
5928 [(unspec_volatile [(const_int 0)] 0)]
5929 ""
5930 ""
5931 [(set_attr "type" "none")])
5932
5933
5934
5935 ;
5936 ; call instruction pattern(s).
5937 ;
5938
5939 (define_expand "call"
5940 [(call (match_operand 0 "" "")
5941 (match_operand 1 "" ""))
5942 (use (match_operand 2 "" ""))]
5943 ""
5944 "
5945 {
5946 int plt_call = 0;
5947 rtx insn;
5948
5949 /* Direct function calls need special treatment. */
5950 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5951 {
5952 rtx sym = XEXP (operands[0], 0);
5953
5954 /* When calling a global routine in PIC mode, we must
5955 replace the symbol itself with the PLT stub. */
5956 if (flag_pic && !SYMBOL_REF_FLAG (sym))
5957 {
5958 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5959 sym = gen_rtx_CONST (Pmode, sym);
5960
5961 plt_call = 1;
5962 }
5963
5964 /* Unless we can use the bras(l) insn, force the
5965 routine address into a register. */
5966 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5967 {
5968 rtx target = gen_reg_rtx (Pmode);
5969 emit_move_insn (target, sym);
5970 sym = target;
5971 }
5972
5973 operands[0] = gen_rtx_MEM (QImode, sym);
5974 }
5975
5976 /* Emit insn. */
5977 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
5978 gen_rtx_REG (Pmode, RETURN_REGNUM)));
5979
5980 /* In 31-bit, we must load the GOT register even if the
5981 compiler doesn't know about it, because the PLT glue
5982 code uses it. In 64-bit, this is not necessary. */
5983 if (plt_call && !TARGET_64BIT)
5984 {
5985 current_function_uses_pic_offset_table = 1;
5986 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
5987 }
5988
5989 DONE;
5990 }")
5991
5992 (define_expand "call_exp"
5993 [(parallel [(call (match_operand 0 "" "")
5994 (match_operand 1 "" ""))
5995 (clobber (match_operand 2 "" ""))])]
5996 ""
5997 "")
5998
5999 (define_insn "brasl"
6000 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6001 (match_operand:SI 1 "const_int_operand" "n"))
6002 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6003 "TARGET_64BIT"
6004 "brasl\\t%2,%0"
6005 [(set_attr "op_type" "RIL")
6006 (set_attr "type" "jsr")])
6007
6008 (define_insn "bras"
6009 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6010 (match_operand:SI 1 "const_int_operand" "n"))
6011 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6012 "TARGET_SMALL_EXEC"
6013 "bras\\t%2,%0"
6014 [(set_attr "op_type" "RI")
6015 (set_attr "type" "jsr")])
6016
6017 (define_insn "basr_64"
6018 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6019 (match_operand:SI 1 "const_int_operand" "n"))
6020 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6021 "TARGET_64BIT"
6022 "basr\\t%2,%0"
6023 [(set_attr "op_type" "RR")
6024 (set_attr "type" "jsr")
6025 (set_attr "atype" "mem")])
6026
6027 (define_insn "basr_31"
6028 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6029 (match_operand:SI 1 "const_int_operand" "n"))
6030 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6031 "!TARGET_64BIT"
6032 "basr\\t%2,%0"
6033 [(set_attr "op_type" "RR")
6034 (set_attr "type" "jsr")
6035 (set_attr "atype" "mem")])
6036
6037 (define_insn "bas_64"
6038 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6039 (match_operand:SI 1 "const_int_operand" "n"))
6040 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6041 "TARGET_64BIT"
6042 "bas\\t%2,%a0"
6043 [(set_attr "op_type" "RX")
6044 (set_attr "type" "jsr")
6045 (set_attr "atype" "mem")])
6046
6047 (define_insn "bas_31"
6048 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6049 (match_operand:SI 1 "const_int_operand" "n"))
6050 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6051 "!TARGET_64BIT"
6052 "bas\\t%2,%a0"
6053 [(set_attr "op_type" "RX")
6054 (set_attr "type" "jsr")
6055 (set_attr "atype" "mem")])
6056
6057
6058 ;
6059 ; call_value instruction pattern(s).
6060 ;
6061
6062 (define_expand "call_value"
6063 [(set (match_operand 0 "" "")
6064 (call (match_operand 1 "" "")
6065 (match_operand 2 "" "")))
6066 (use (match_operand 3 "" ""))]
6067 ""
6068 "
6069 {
6070 int plt_call = 0;
6071 rtx insn;
6072
6073 /* Direct function calls need special treatment. */
6074 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6075 {
6076 rtx sym = XEXP (operands[1], 0);
6077
6078 /* When calling a global routine in PIC mode, we must
6079 replace the symbol itself with the PLT stub. */
6080 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6081 {
6082 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6083 sym = gen_rtx_CONST (Pmode, sym);
6084
6085 plt_call = 1;
6086 }
6087
6088 /* Unless we can use the bras(l) insn, force the
6089 routine address into a register. */
6090 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6091 {
6092 rtx target = gen_reg_rtx (Pmode);
6093 emit_move_insn (target, sym);
6094 sym = target;
6095 }
6096
6097 operands[1] = gen_rtx_MEM (QImode, sym);
6098 }
6099
6100 /* Emit insn. */
6101 insn = emit_call_insn (
6102 gen_call_value_exp (operands[0], operands[1], operands[2],
6103 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6104
6105 /* In 31-bit, we must load the GOT register even if the
6106 compiler doesn't know about it, because the PLT glue
6107 code uses it. In 64-bit, this is not necessary. */
6108 if (plt_call && !TARGET_64BIT)
6109 {
6110 current_function_uses_pic_offset_table = 1;
6111 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6112 }
6113
6114 DONE;
6115 }")
6116
6117 (define_expand "call_value_exp"
6118 [(parallel [(set (match_operand 0 "" "")
6119 (call (match_operand 1 "" "")
6120 (match_operand 2 "" "")))
6121 (clobber (match_operand 3 "" ""))])]
6122 ""
6123 "")
6124
6125 (define_insn "brasl_r"
6126 [(set (match_operand 0 "register_operand" "=df")
6127 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6128 (match_operand:SI 2 "const_int_operand" "n")))
6129 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6130 "TARGET_64BIT"
6131 "brasl\\t%3,%1"
6132 [(set_attr "op_type" "RIL")
6133 (set_attr "type" "jsr")])
6134
6135 (define_insn "bras_r"
6136 [(set (match_operand 0 "register_operand" "=df")
6137 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6138 (match_operand:SI 2 "const_int_operand" "n")))
6139 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6140 "TARGET_SMALL_EXEC"
6141 "bras\\t%3,%1"
6142 [(set_attr "op_type" "RI")
6143 (set_attr "type" "jsr")])
6144
6145 (define_insn "basr_r_64"
6146 [(set (match_operand 0 "register_operand" "=df")
6147 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6148 (match_operand:SI 2 "const_int_operand" "n")))
6149 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6150 "TARGET_64BIT"
6151 "basr\\t%3,%1"
6152 [(set_attr "op_type" "RR")
6153 (set_attr "type" "jsr")])
6154
6155 (define_insn "basr_r_31"
6156 [(set (match_operand 0 "register_operand" "=df")
6157 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6158 (match_operand:SI 2 "const_int_operand" "n")))
6159 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6160 "!TARGET_64BIT"
6161 "basr\\t%3,%1"
6162 [(set_attr "op_type" "RR")
6163 (set_attr "type" "jsr")
6164 (set_attr "atype" "mem")])
6165
6166 (define_insn "bas_r_64"
6167 [(set (match_operand 0 "register_operand" "=df")
6168 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6169 (match_operand:SI 2 "const_int_operand" "n")))
6170 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6171 "TARGET_64BIT"
6172 "bas\\t%3,%a1"
6173 [(set_attr "op_type" "RX")
6174 (set_attr "type" "jsr")
6175 (set_attr "atype" "mem")])
6176
6177 (define_insn "bas_r_31"
6178 [(set (match_operand 0 "register_operand" "=df")
6179 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6180 (match_operand:SI 2 "const_int_operand" "n")))
6181 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6182 "!TARGET_64BIT"
6183 "bas\\t%3,%a1"
6184 [(set_attr "op_type" "RX")
6185 (set_attr "type" "jsr")
6186 (set_attr "atype" "mem")])
6187
6188
6189 ;;
6190 ;;- Miscellaneous instructions.
6191 ;;
6192
6193 ;
6194 ; allocate stack instruction pattern(s).
6195 ;
6196
6197 (define_expand "allocate_stack"
6198 [(set (reg 15)
6199 (plus (reg 15) (match_operand 1 "general_operand" "")))
6200 (set (match_operand 0 "general_operand" "")
6201 (reg 15))]
6202 ""
6203 "
6204 {
6205 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6206 rtx chain = gen_rtx (MEM, Pmode, stack);
6207 rtx temp = gen_reg_rtx (Pmode);
6208
6209 emit_move_insn (temp, chain);
6210
6211 if (TARGET_64BIT)
6212 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6213 else
6214 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6215
6216 emit_move_insn (chain, temp);
6217
6218 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6219 DONE;
6220 }")
6221
6222
6223 ;
6224 ; setjmp/longjmp instruction pattern(s).
6225 ;
6226
6227 (define_expand "builtin_setjmp_setup"
6228 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6229 ""
6230 "
6231 {
6232 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6233 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6234
6235 emit_move_insn (base, basereg);
6236 DONE;
6237 }")
6238
6239 (define_expand "builtin_setjmp_receiver"
6240 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6241 "flag_pic"
6242 "
6243 {
6244 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6245 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6246 SYMBOL_REF_FLAG (got) = 1;
6247
6248 emit_move_insn (gotreg, got);
6249 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6250 DONE;
6251 }")
6252
6253 (define_expand "builtin_longjmp"
6254 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6255 ""
6256 "
6257 {
6258 /* The elements of the buffer are, in order: */
6259 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6260 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6261 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6262 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6263 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6264 rtx jmp = gen_rtx_REG (Pmode, 14);
6265
6266 emit_move_insn (jmp, lab);
6267 emit_move_insn (basereg, base);
6268 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6269 emit_move_insn (hard_frame_pointer_rtx, fp);
6270
6271 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6272 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6273 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6274 emit_indirect_jump (jmp);
6275 DONE;
6276 }")
6277
6278
6279 ;; These patterns say how to save and restore the stack pointer. We need not
6280 ;; save the stack pointer at function level since we are careful to
6281 ;; preserve the backchain. At block level, we have to restore the backchain
6282 ;; when we restore the stack pointer.
6283 ;;
6284 ;; For nonlocal gotos, we must save both the stack pointer and its
6285 ;; backchain and restore both. Note that in the nonlocal case, the
6286 ;; save area is a memory location.
6287
6288 (define_expand "save_stack_function"
6289 [(match_operand 0 "general_operand" "")
6290 (match_operand 1 "general_operand" "")]
6291 ""
6292 "DONE;")
6293
6294 (define_expand "restore_stack_function"
6295 [(match_operand 0 "general_operand" "")
6296 (match_operand 1 "general_operand" "")]
6297 ""
6298 "DONE;")
6299
6300 (define_expand "restore_stack_block"
6301 [(use (match_operand 0 "register_operand" ""))
6302 (set (match_dup 2) (match_dup 3))
6303 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6304 (set (match_dup 3) (match_dup 2))]
6305 ""
6306 "
6307 {
6308 operands[2] = gen_reg_rtx (Pmode);
6309 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6310 }")
6311
6312 (define_expand "save_stack_nonlocal"
6313 [(match_operand 0 "memory_operand" "")
6314 (match_operand 1 "register_operand" "")]
6315 ""
6316 "
6317 {
6318 rtx temp = gen_reg_rtx (Pmode);
6319
6320 /* Copy the backchain to the first word, sp to the second. */
6321 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6322 emit_move_insn (operand_subword (operands[0], 0, 0,
6323 TARGET_64BIT ? TImode : DImode),
6324 temp);
6325 emit_move_insn (operand_subword (operands[0], 1, 0,
6326 TARGET_64BIT ? TImode : DImode),
6327 operands[1]);
6328 DONE;
6329 }")
6330
6331 (define_expand "restore_stack_nonlocal"
6332 [(match_operand 0 "register_operand" "")
6333 (match_operand 1 "memory_operand" "")]
6334 ""
6335 "
6336 {
6337 rtx temp = gen_reg_rtx (Pmode);
6338
6339 /* Restore the backchain from the first word, sp from the second. */
6340 emit_move_insn (temp,
6341 operand_subword (operands[1], 0, 0,
6342 TARGET_64BIT ? TImode : DImode));
6343 emit_move_insn (operands[0],
6344 operand_subword (operands[1], 1, 0,
6345 TARGET_64BIT ? TImode : DImode));
6346 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6347 DONE;
6348 }")
6349
6350
6351 ;
6352 ; nop instruction pattern(s).
6353 ;
6354
6355 (define_insn "nop"
6356 [(const_int 0)]
6357 ""
6358 "lr\\t0,0"
6359 [(set_attr "op_type" "RR")])
6360
6361
6362 ;
6363 ; Special literal pool access instruction pattern(s).
6364 ;
6365
6366 (define_insn "reload_base"
6367 [(parallel [(set (reg 13) (pc))
6368 (use (label_ref (match_operand 0 "" "")))])]
6369 ""
6370 "*
6371 {
6372 if (TARGET_64BIT)
6373 return \"larl\\t13,%y0\";
6374 else
6375 return \"basr\\t13,0\;ahi\\t13,%Y0\";
6376 }"
6377 [(set_attr "op_type" "NN")
6378 (set_attr "type" "la")
6379 (set_attr "length" "8")])
6380
6381 (define_insn "ltorg"
6382 [(parallel [(set (reg 13) (pc))
6383 (use (match_operand:SI 0 "const_int_operand" ""))])]
6384 ""
6385 "*
6386 {
6387 s390_dump_literal_pool (insn, operands[0]);
6388 return \"0:\";
6389 }"
6390 [(set_attr "op_type" "NN")
6391 (set_attr "type" "other")
6392 (set_attr "length" "4096")])
6393
6394 ;;
6395 ;; Insns related to generating the function prologue and epilogue.
6396 ;;
6397
6398
6399 (define_expand "prologue"
6400 [(use (const_int 0))]
6401 ""
6402 "
6403 {
6404 s390_emit_prologue ();
6405 DONE;
6406 }")
6407
6408 (define_expand "epilogue"
6409 [(use (const_int 1))]
6410 ""
6411 "
6412 {
6413 s390_emit_epilogue ();
6414 DONE;
6415 }")
6416
6417
6418 (define_insn "*return_si"
6419 [(return)
6420 (use (match_operand:SI 0 "register_operand" "a"))]
6421 "!TARGET_64BIT"
6422 "br\\t%0"
6423 [(set_attr "op_type" "RR")
6424 (set_attr "type" "jsr")
6425 (set_attr "atype" "mem")])
6426
6427 (define_insn "*return_di"
6428 [(return)
6429 (use (match_operand:DI 0 "register_operand" "a"))]
6430 "TARGET_64BIT"
6431 "br\\t%0"
6432 [(set_attr "op_type" "RR")
6433 (set_attr "type" "jsr")
6434 (set_attr "atype" "mem")])
6435
6436
6437 (define_insn "lit"
6438 [(set (reg 13) (pc))
6439 (unspec_volatile [(const_int 0)] 200)]
6440 ""
6441 "*
6442 {
6443 s390_output_constant_pool (asm_out_file);
6444 return \"\";
6445 }"
6446 [(set_attr "op_type" "NN")
6447 (set_attr "type" "integer")])
6448
6449
6450 ;;
6451 ;; Peephole optimization patterns.
6452 ;;
6453
6454 (define_peephole
6455 [(set (match_operand:SI 0 "memory_operand" "m")
6456 (match_operand:SI 1 "register_operand" "d"))
6457 (set (match_dup 1)
6458 (match_dup 0))]
6459 ""
6460 "st\\t%1,%0")
6461
6462 (define_peephole
6463 [(set (match_operand:SI 0 "memory_operand" "m")
6464 (match_operand:SI 1 "register_operand" "d"))
6465 (set (match_dup 0)
6466 (match_dup 1))]
6467 ""
6468 "st\\t%1,%0")
6469
6470 (define_peephole
6471 [(set (match_operand:SI 0 "register_operand" "")
6472 (match_operand:SI 1 "register_operand" ""))
6473 (parallel
6474 [(set (match_dup 0)
6475 (plus:SI (match_dup 0)
6476 (match_operand:SI 2 "immediate_operand" "")))
6477 (clobber (reg:CC 33))])]
6478 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6479 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6480 REGNO (operands[0]) == BASE_REGISTER ||
6481 REGNO (operands[1]) == BASE_REGISTER) &&
6482 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6483 "la\\t%0,%c2(%1)")
6484
6485 ;
6486 ; peepholes for fast char instructions
6487 ;
6488
6489 ;(define_peephole
6490 ; [(set (match_operand:QI 0 "register_operand" "d")
6491 ; (match_operand:QI 1 "s_operand" "Q"))
6492 ; (set (match_operand:SI 2 "register_operand" "0")
6493 ; (zero_extend:SI (match_dup 0)))]
6494 ; "REGNO(operands[0]) == REGNO(operands[2])"
6495 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6496
6497 ;(define_peephole
6498 ; [(set (match_operand:QI 0 "register_operand" "d")
6499 ; (match_operand:QI 1 "s_operand" "Q"))
6500 ; (set (match_operand:SI 2 "register_operand" "0")
6501 ; (sign_extend:SI (match_dup 0)))]
6502 ; "REGNO(operands[0]) == REGNO(operands[2])"
6503 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6504
6505 (define_peephole
6506 [(set (match_operand:QI 0 "register_operand" "d")
6507 (match_operand:QI 1 "immediate_operand" "J"))
6508 (set (match_operand:SI 2 "register_operand" "0" )
6509 (sign_extend:SI (match_dup 0) ) )]
6510 "REGNO(operands[0]) == REGNO(operands[2])"
6511 "lhi\\t%0,%h1")
6512
6513 ;
6514 ; peepholes for fast short instructions
6515 ;
6516
6517 ;(define_peephole
6518 ; [(set (match_operand:HI 0 "register_operand" "d")
6519 ; (match_operand:HI 1 "s_operand" "Q"))
6520 ; (set (match_operand:SI 2 "register_operand" "0" )
6521 ; (zero_extend:SI (match_dup 0)))]
6522 ; "REGNO(operands[0]) == REGNO(operands[2])"
6523 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6524
6525 (define_peephole
6526 [(set (match_operand:HI 0 "register_operand" "d")
6527 (match_operand:HI 1 "memory_operand" "m"))
6528 (set (match_operand:SI 2 "register_operand" "0" )
6529 (sign_extend:SI (match_dup 0)))]
6530 "REGNO(operands[0]) == REGNO(operands[2])"
6531 "lh\\t%0,%1")
6532
6533 (define_peephole
6534 [(set (match_operand:HI 0 "register_operand" "d")
6535 (match_operand:HI 1 "immediate_operand" "K"))
6536 (set (match_operand:SI 2 "register_operand" "0" )
6537 (sign_extend:SI (match_dup 0) ) )]
6538 "REGNO(operands[0]) == REGNO(operands[2])"
6539 "lhi\\t%0,%h1")
6540
6541 ;
6542 ; peepholes for divide instructions
6543 ;
6544
6545 (define_peephole
6546 [(set (match_operand:DI 0 "register_operand" "d")
6547 (match_operand:DI 1 "memory_operand" "m"))
6548 (set (match_dup 0)
6549 (lshiftrt:DI (match_dup 0)
6550 (match_operand:SI 2 "immediate_operand" "J")))
6551 (set (match_dup 0)
6552 (div:SI (match_dup 0)
6553 (match_operand:SI 3 "nonimmediate_operand" "g")))
6554 (set (match_dup 1)
6555 (match_dup 0))]
6556 ""
6557 "*
6558 {
6559 output_asm_insn (\"l\\t%0,%1\", operands);
6560 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6561
6562 if (REG_P (operands[3]))
6563 output_asm_insn (\"dr\\t%0,%3\", operands);
6564 else
6565 output_asm_insn (\"d\\t%0,%3\", operands);
6566
6567 return \"st\\t%N0,%N1\";
6568 }")
6569
6570 (define_peephole
6571 [(set (match_operand:DI 0 "register_operand" "d")
6572 (match_operand:DI 1 "memory_operand" "m"))
6573 (set (match_dup 0)
6574 (lshiftrt:DI (match_dup 0)
6575 (match_operand:SI 2 "immediate_operand" "J")))
6576 (set (match_dup 0)
6577 (mod:SI (match_dup 0)
6578 (match_operand:SI 3 "nonimmediate_operand" "g")))
6579 (set (match_dup 1)
6580 (match_dup 0))]
6581 ""
6582 "*
6583 {
6584 output_asm_insn (\"l\\t%0,%1\", operands);
6585 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6586
6587 if (REG_P (operands[3]))
6588 output_asm_insn (\"dr\\t%0,%3\", operands);
6589 else
6590 output_asm_insn (\"d\\t%0,%3\", operands);
6591
6592 return \"st\\t%0,%1\";
6593 }")
6594