1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; GOT/PLT and lt-relative accesses
94 ; TLS relocation specifiers
110 ; Stack Smashing Protector
114 ; Test Data Class (TDC)
126 UNSPEC_FPINT_NEARBYINT
131 ;; UNSPEC_VOLATILE usage
134 (define_c_enum "unspecv" [
156 ; Transactional Execution support
171 ; Registers with special meaning
175 ; Sibling call register.
177 ; Literal pool base register.
179 ; Return address register.
181 ; Condition code register.
183 ; Thread local storage pointer register.
187 ; Hardware register names
191 ; General purpose registers
193 ; Floating point registers.
213 ;; PFPO GPR0 argument format
218 ; PFPO operation type
219 (PFPO_CONVERT 0x1000000)
221 (PFPO_OP_TYPE_SF 0x5)
222 (PFPO_OP_TYPE_DF 0x6)
223 (PFPO_OP_TYPE_TF 0x7)
224 (PFPO_OP_TYPE_SD 0x8)
225 (PFPO_OP_TYPE_DD 0x9)
226 (PFPO_OP_TYPE_TD 0xa)
227 ; Bitposition of operand types
228 (PFPO_OP0_TYPE_SHIFT 16)
229 (PFPO_OP1_TYPE_SHIFT 8)
232 ; Immediate operands for tbegin and tbeginc
233 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
234 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
236 ;; Instruction operand type as used in the Principles of Operation.
237 ;; Used to determine defaults for length and other attribute values.
239 (define_attr "op_type"
240 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
243 ;; Instruction type attribute used for scheduling.
245 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
246 cs,vs,store,sem,idiv,
247 imulhi,imulsi,imuldi,
248 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
249 floadtf,floaddf,floadsf,fstoredf,fstoresf,
250 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
251 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
253 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
254 itoftf, itofdf, itofsf, itofdd, itoftd,
255 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
256 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
258 (cond [(eq_attr "op_type" "NN") (const_string "other")
259 (eq_attr "op_type" "SS") (const_string "cs")]
260 (const_string "integer")))
262 ;; Another attribute used for scheduling purposes:
263 ;; agen: Instruction uses the address generation unit
264 ;; reg: Instruction does not use the agen unit
266 (define_attr "atype" "agen,reg"
267 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
269 (const_string "agen")))
271 ;; Properties concerning Z10 execution grouping and value forwarding.
272 ;; z10_super: instruction is superscalar.
273 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
274 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
275 ;; target register. It can forward this value to a second instruction that reads
276 ;; the same register if that second instruction is issued in the same group.
277 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
278 ;; instruction in the S pipe writes to the register, then the T instruction
279 ;; can immediately read the new value.
280 ;; z10_fr: union of Z10_fwd and z10_rec.
281 ;; z10_c: second operand of instruction is a register and read with complemented bits.
283 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
286 (define_attr "z10prop" "none,
287 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
288 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
290 z10_fr, z10_fr_A3, z10_fr_E1,
292 (const_string "none"))
294 ;; Properties concerning Z196 decoding
295 ;; z196_alone: must group alone
296 ;; z196_end: ends a group
297 ;; z196_cracked: instruction is cracked or expanded
298 (define_attr "z196prop" "none,
299 z196_alone, z196_ends,
301 (const_string "none"))
303 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
307 (define_attr "length" ""
308 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
309 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
313 ;; Processor type. This attribute must exactly match the processor_type
314 ;; enumeration in s390.h. The current machine description does not
315 ;; distinguish between g5 and g6, but there are differences between the two
316 ;; CPUs could in theory be modeled.
318 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
319 (const (symbol_ref "s390_tune_attr")))
321 (define_attr "cpu_facility"
322 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12"
323 (const_string "standard"))
325 (define_attr "enabled" ""
326 (cond [(eq_attr "cpu_facility" "standard")
329 (and (eq_attr "cpu_facility" "ieee")
330 (match_test "TARGET_CPU_IEEE_FLOAT"))
333 (and (eq_attr "cpu_facility" "zarch")
334 (match_test "TARGET_ZARCH"))
337 (and (eq_attr "cpu_facility" "longdisp")
338 (match_test "TARGET_LONG_DISPLACEMENT"))
341 (and (eq_attr "cpu_facility" "extimm")
342 (match_test "TARGET_EXTIMM"))
345 (and (eq_attr "cpu_facility" "dfp")
346 (match_test "TARGET_DFP"))
349 (and (eq_attr "cpu_facility" "cpu_zarch")
350 (match_test "TARGET_CPU_ZARCH"))
353 (and (eq_attr "cpu_facility" "z10")
354 (match_test "TARGET_Z10"))
357 (and (eq_attr "cpu_facility" "z196")
358 (match_test "TARGET_Z196"))
361 (and (eq_attr "cpu_facility" "zEC12")
362 (match_test "TARGET_ZEC12"))
366 ;; Pipeline description for z900. For lack of anything better,
367 ;; this description is also used for the g5 and g6.
370 ;; Pipeline description for z990, z9-109 and z9-ec.
373 ;; Pipeline description for z10
376 ;; Pipeline description for z196
379 ;; Pipeline description for zEC12
383 (include "predicates.md")
385 ;; Constraint definitions
386 (include "constraints.md")
393 ;; These mode iterators allow floating point patterns to be generated from the
395 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
396 (SD "TARGET_HARD_DFP")])
397 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
398 (define_mode_iterator FPALL [TF DF SF TD DD SD])
399 (define_mode_iterator BFP [TF DF SF])
400 (define_mode_iterator DFP [TD DD])
401 (define_mode_iterator DFP_ALL [TD DD SD])
402 (define_mode_iterator DSF [DF SF])
403 (define_mode_iterator SD_SF [SF SD])
404 (define_mode_iterator DD_DF [DF DD])
405 (define_mode_iterator TD_TF [TF TD])
407 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
408 ;; from the same template.
409 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
410 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
411 (define_mode_iterator DSI [DI SI])
412 (define_mode_iterator TDI [TI DI])
414 ;; These mode iterators allow :P to be used for patterns that operate on
415 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
416 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
418 ;; These macros refer to the actual word_mode of the configuration.
419 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
420 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
421 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
423 ;; Used by the umul pattern to express modes having half the size.
424 (define_mode_attr DWH [(TI "DI") (DI "SI")])
425 (define_mode_attr dwh [(TI "di") (DI "si")])
427 ;; This mode iterator allows the QI and HI patterns to be defined from
428 ;; the same template.
429 (define_mode_iterator HQI [HI QI])
431 ;; This mode iterator allows the integer patterns to be defined from the
433 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
434 (define_mode_iterator INTALL [TI DI SI HI QI])
435 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
437 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
438 ;; the same template.
439 (define_code_iterator SHIFT [ashift lshiftrt])
441 ;; This iterator allows r[ox]sbg to be defined with the same template
442 (define_code_iterator IXOR [ior xor])
444 ;; This iterator is used to expand the patterns for the nearest
445 ;; integer functions.
446 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
447 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
448 UNSPEC_FPINT_NEARBYINT])
449 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
450 (UNSPEC_FPINT_BTRUNC "btrunc")
451 (UNSPEC_FPINT_ROUND "round")
452 (UNSPEC_FPINT_CEIL "ceil")
453 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
454 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
455 (UNSPEC_FPINT_BTRUNC "5")
456 (UNSPEC_FPINT_ROUND "1")
457 (UNSPEC_FPINT_CEIL "6")
458 (UNSPEC_FPINT_NEARBYINT "0")])
460 ;; This iterator and attribute allow to combine most atomic operations.
461 (define_code_iterator ATOMIC [and ior xor plus minus mult])
462 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
463 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
464 (plus "add") (minus "sub") (mult "nand")])
465 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
467 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
468 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
469 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
471 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
472 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
474 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
476 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
477 ;; Likewise for "<RXe>".
478 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
479 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
481 ;; The decimal floating point variants of add, sub, div and mul support 3
482 ;; fp register operands. The following attributes allow to merge the bfp and
483 ;; dfp variants in a single insn definition.
485 ;; This attribute is used to set op_type accordingly.
486 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
487 (DD "RRR") (SD "RRR")])
489 ;; This attribute is used in the operand constraint list in order to have the
490 ;; first and the second operand match for bfp modes.
491 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
493 ;; This attribute is used in the operand list of the instruction to have an
494 ;; additional operand for the dfp instructions.
495 (define_mode_attr op1 [(TF "") (DF "") (SF "")
496 (TD "%1,") (DD "%1,") (SD "%1,")])
499 ;; This attribute is used in the operand constraint list
500 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
501 ;; TFmode values are represented by a fp register pair. Since the
502 ;; sign bit instructions only handle single source and target fp registers
503 ;; these instructions can only be used for TFmode values if the source and
504 ;; target operand uses the same fp register.
505 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
507 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
508 ;; This is used to disable the memory alternative in TFmode patterns.
509 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
511 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
512 ;; within instruction mnemonics.
513 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
515 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
516 ;; modes and to an empty string for bfp modes.
517 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
519 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
520 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
521 ;; version only operates on one register.
522 (define_mode_attr d0 [(DI "d") (SI "0")])
524 ;; In combination with d0 this allows to combine instructions of which the 31bit
525 ;; version only operates on one register. The DImode version needs an additional
526 ;; register for the assembler output.
527 (define_mode_attr 1 [(DI "%1,") (SI "")])
529 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
530 ;; 'ashift' and "srdl" in 'lshiftrt'.
531 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
533 ;; In SHIFT templates, this attribute holds the correct standard name for the
534 ;; pattern itself and the corresponding function calls.
535 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
537 ;; This attribute handles differences in the instruction 'type' and will result
538 ;; in "RRE" for DImode and "RR" for SImode.
539 (define_mode_attr E [(DI "E") (SI "")])
541 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
542 ;; to result in "RXY" for DImode and "RX" for SImode.
543 (define_mode_attr Y [(DI "Y") (SI "")])
545 ;; This attribute handles differences in the instruction 'type' and will result
546 ;; in "RSE" for TImode and "RS" for DImode.
547 (define_mode_attr TE [(TI "E") (DI "")])
549 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
550 ;; and "lcr" in SImode.
551 (define_mode_attr g [(DI "g") (SI "")])
553 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
554 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
555 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
556 ;; variant for long displacements.
557 (define_mode_attr y [(DI "g") (SI "y")])
559 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
560 ;; and "cds" in DImode.
561 (define_mode_attr tg [(TI "g") (DI "")])
563 ;; In TDI templates, a string like "c<d>sg".
564 (define_mode_attr td [(TI "d") (DI "")])
566 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
567 ;; and "cfdbr" in SImode.
568 (define_mode_attr gf [(DI "g") (SI "f")])
570 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
571 ;; and sllk for SI. This way it is possible to merge the new z196 SI
572 ;; 3 operands shift instructions into the existing patterns.
573 (define_mode_attr gk [(DI "g") (SI "k")])
575 ;; ICM mask required to load MODE value into the lowest subreg
576 ;; of a SImode register.
577 (define_mode_attr icm_lo [(HI "3") (QI "1")])
579 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
580 ;; HImode and "llgc" in QImode.
581 (define_mode_attr hc [(HI "h") (QI "c")])
583 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
585 (define_mode_attr DBL [(DI "TI") (SI "DI")])
587 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
588 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
589 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
591 ;; Maximum unsigned integer that fits in MODE.
592 (define_mode_attr max_uint [(HI "65535") (QI "255")])
594 ;; Start and end field computations for RISBG et al.
595 (define_mode_attr bfstart [(DI "s") (SI "t")])
596 (define_mode_attr bfend [(DI "e") (SI "f")])
598 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
599 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
601 ;; Allow return and simple_return to be defined from a single template.
602 (define_code_iterator ANY_RETURN [return simple_return])
605 ;;- Compare instructions.
608 ; Test-under-Mask instructions
610 (define_insn "*tmqi_mem"
611 [(set (reg CC_REGNUM)
612 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
613 (match_operand:QI 1 "immediate_operand" "n,n"))
614 (match_operand:QI 2 "immediate_operand" "n,n")))]
615 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
619 [(set_attr "op_type" "SI,SIY")
620 (set_attr "z10prop" "z10_super,z10_super")])
622 (define_insn "*tmdi_reg"
623 [(set (reg CC_REGNUM)
624 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
625 (match_operand:DI 1 "immediate_operand"
626 "N0HD0,N1HD0,N2HD0,N3HD0"))
627 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
629 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
630 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
636 [(set_attr "op_type" "RI")
637 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
639 (define_insn "*tmsi_reg"
640 [(set (reg CC_REGNUM)
641 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
642 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
643 (match_operand:SI 2 "immediate_operand" "n,n")))]
644 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
645 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
649 [(set_attr "op_type" "RI")
650 (set_attr "z10prop" "z10_super,z10_super")])
652 (define_insn "*tm<mode>_full"
653 [(set (reg CC_REGNUM)
654 (compare (match_operand:HQI 0 "register_operand" "d")
655 (match_operand:HQI 1 "immediate_operand" "n")))]
656 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
658 [(set_attr "op_type" "RI")
659 (set_attr "z10prop" "z10_super")])
663 ; Load-and-Test instructions
666 ; tst(di|si) instruction pattern(s).
668 (define_insn "*tstdi_sign"
669 [(set (reg CC_REGNUM)
673 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
674 (const_int 32)) (const_int 32))
675 (match_operand:DI 1 "const0_operand" "")))
676 (set (match_operand:DI 2 "register_operand" "=d,d")
677 (sign_extend:DI (match_dup 0)))]
678 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
681 [(set_attr "op_type" "RRE,RXY")
682 (set_attr "cpu_facility" "*,z10")
683 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
686 (define_insn "*tst<mode>_extimm"
687 [(set (reg CC_REGNUM)
688 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
689 (match_operand:GPR 1 "const0_operand" "")))
690 (set (match_operand:GPR 2 "register_operand" "=d,d")
692 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
696 [(set_attr "op_type" "RR<E>,RXY")
697 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
700 (define_insn "*tst<mode>_cconly_extimm"
701 [(set (reg CC_REGNUM)
702 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
703 (match_operand:GPR 1 "const0_operand" "")))
704 (clobber (match_scratch:GPR 2 "=X,d"))]
705 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
709 [(set_attr "op_type" "RR<E>,RXY")
710 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
712 (define_insn "*tstdi"
713 [(set (reg CC_REGNUM)
714 (compare (match_operand:DI 0 "register_operand" "d")
715 (match_operand:DI 1 "const0_operand" "")))
716 (set (match_operand:DI 2 "register_operand" "=d")
718 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
720 [(set_attr "op_type" "RRE")
721 (set_attr "z10prop" "z10_fr_E1")])
723 (define_insn "*tstsi"
724 [(set (reg CC_REGNUM)
725 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
726 (match_operand:SI 1 "const0_operand" "")))
727 (set (match_operand:SI 2 "register_operand" "=d,d,d")
729 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
734 [(set_attr "op_type" "RR,RS,RSY")
735 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
737 (define_insn "*tstsi_cconly"
738 [(set (reg CC_REGNUM)
739 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
740 (match_operand:SI 1 "const0_operand" "")))
741 (clobber (match_scratch:SI 2 "=X,d,d"))]
742 "s390_match_ccmode(insn, CCSmode)"
747 [(set_attr "op_type" "RR,RS,RSY")
748 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
750 (define_insn "*tstdi_cconly_31"
751 [(set (reg CC_REGNUM)
752 (compare (match_operand:DI 0 "register_operand" "d")
753 (match_operand:DI 1 "const0_operand" "")))]
754 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
756 [(set_attr "op_type" "RS")
757 (set_attr "atype" "reg")])
760 (define_insn "*tst<mode>_cconly2"
761 [(set (reg CC_REGNUM)
762 (compare (match_operand:GPR 0 "register_operand" "d")
763 (match_operand:GPR 1 "const0_operand" "")))]
764 "s390_match_ccmode(insn, CCSmode)"
766 [(set_attr "op_type" "RR<E>")
767 (set_attr "z10prop" "z10_fr_E1")])
769 ; tst(hi|qi) instruction pattern(s).
771 (define_insn "*tst<mode>CCT"
772 [(set (reg CC_REGNUM)
773 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
774 (match_operand:HQI 1 "const0_operand" "")))
775 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
777 "s390_match_ccmode(insn, CCTmode)"
780 icmy\t%2,<icm_lo>,%S0
782 [(set_attr "op_type" "RS,RSY,RI")
783 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
785 (define_insn "*tsthiCCT_cconly"
786 [(set (reg CC_REGNUM)
787 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
788 (match_operand:HI 1 "const0_operand" "")))
789 (clobber (match_scratch:HI 2 "=d,d,X"))]
790 "s390_match_ccmode(insn, CCTmode)"
795 [(set_attr "op_type" "RS,RSY,RI")
796 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
798 (define_insn "*tstqiCCT_cconly"
799 [(set (reg CC_REGNUM)
800 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
801 (match_operand:QI 1 "const0_operand" "")))]
802 "s390_match_ccmode(insn, CCTmode)"
807 [(set_attr "op_type" "SI,SIY,RI")
808 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
810 (define_insn "*tst<mode>"
811 [(set (reg CC_REGNUM)
812 (compare (match_operand:HQI 0 "s_operand" "Q,S")
813 (match_operand:HQI 1 "const0_operand" "")))
814 (set (match_operand:HQI 2 "register_operand" "=d,d")
816 "s390_match_ccmode(insn, CCSmode)"
819 icmy\t%2,<icm_lo>,%S0"
820 [(set_attr "op_type" "RS,RSY")
821 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
823 (define_insn "*tst<mode>_cconly"
824 [(set (reg CC_REGNUM)
825 (compare (match_operand:HQI 0 "s_operand" "Q,S")
826 (match_operand:HQI 1 "const0_operand" "")))
827 (clobber (match_scratch:HQI 2 "=d,d"))]
828 "s390_match_ccmode(insn, CCSmode)"
831 icmy\t%2,<icm_lo>,%S0"
832 [(set_attr "op_type" "RS,RSY")
833 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
836 ; Compare (equality) instructions
838 (define_insn "*cmpdi_cct"
839 [(set (reg CC_REGNUM)
840 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
841 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
842 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
849 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
850 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
852 (define_insn "*cmpsi_cct"
853 [(set (reg CC_REGNUM)
854 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
855 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
856 "s390_match_ccmode (insn, CCTmode)"
864 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
865 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
867 ; Compare (signed) instructions
869 (define_insn "*cmpdi_ccs_sign"
870 [(set (reg CC_REGNUM)
871 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
873 (match_operand:DI 0 "register_operand" "d, d,d")))]
874 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
879 [(set_attr "op_type" "RRE,RXY,RIL")
880 (set_attr "z10prop" "z10_c,*,*")
881 (set_attr "type" "*,*,larl")])
885 (define_insn "*cmpsi_ccs_sign"
886 [(set (reg CC_REGNUM)
887 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
888 (match_operand:SI 0 "register_operand" "d,d,d")))]
889 "s390_match_ccmode(insn, CCSRmode)"
894 [(set_attr "op_type" "RX,RXY,RIL")
895 (set_attr "cpu_facility" "*,*,z10")
896 (set_attr "type" "*,*,larl")
897 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
899 (define_insn "*cmphi_ccs_z10"
900 [(set (reg CC_REGNUM)
901 (compare (match_operand:HI 0 "s_operand" "Q")
902 (match_operand:HI 1 "immediate_operand" "K")))]
903 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
905 [(set_attr "op_type" "SIL")
906 (set_attr "z196prop" "z196_cracked")])
908 (define_insn "*cmpdi_ccs_signhi_rl"
909 [(set (reg CC_REGNUM)
910 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
911 (match_operand:GPR 0 "register_operand" "d,d")))]
912 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
916 [(set_attr "op_type" "RXY,RIL")
917 (set_attr "type" "*,larl")])
919 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
920 (define_insn "*cmp<mode>_ccs"
921 [(set (reg CC_REGNUM)
922 (compare (match_operand:GPR 0 "nonimmediate_operand"
924 (match_operand:GPR 1 "general_operand"
926 "s390_match_ccmode(insn, CCSmode)"
935 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
936 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
937 (set_attr "type" "*,*,*,*,*,*,larl")
938 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
941 ; Compare (unsigned) instructions
943 (define_insn "*cmpsi_ccu_zerohi_rlsi"
944 [(set (reg CC_REGNUM)
945 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
946 "larl_operand" "X")))
947 (match_operand:SI 0 "register_operand" "d")))]
948 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
950 [(set_attr "op_type" "RIL")
951 (set_attr "type" "larl")
952 (set_attr "z10prop" "z10_super")])
955 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
956 [(set (reg CC_REGNUM)
957 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
958 "larl_operand" "X")))
959 (match_operand:GPR 0 "register_operand" "d")))]
960 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
962 [(set_attr "op_type" "RIL")
963 (set_attr "type" "larl")
964 (set_attr "z10prop" "z10_super")])
966 (define_insn "*cmpdi_ccu_zero"
967 [(set (reg CC_REGNUM)
968 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
970 (match_operand:DI 0 "register_operand" "d, d,d")))]
971 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
976 [(set_attr "op_type" "RRE,RXY,RIL")
977 (set_attr "cpu_facility" "*,*,z10")
978 (set_attr "type" "*,*,larl")
979 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
981 (define_insn "*cmpdi_ccu"
982 [(set (reg CC_REGNUM)
983 (compare (match_operand:DI 0 "nonimmediate_operand"
985 (match_operand:DI 1 "general_operand"
986 "d,Op,b,D,RT,BQ,Q")))]
987 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
996 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
997 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
998 (set_attr "type" "*,*,larl,*,*,*,*")
999 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1001 (define_insn "*cmpsi_ccu"
1002 [(set (reg CC_REGNUM)
1003 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1004 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1005 "s390_match_ccmode (insn, CCUmode)"
1015 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1016 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1017 (set_attr "type" "*,*,larl,*,*,*,*,*")
1018 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1020 (define_insn "*cmphi_ccu"
1021 [(set (reg CC_REGNUM)
1022 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1023 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1024 "s390_match_ccmode (insn, CCUmode)
1025 && !register_operand (operands[1], HImode)"
1032 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1033 (set_attr "cpu_facility" "*,*,z10,*,*")
1034 (set_attr "z10prop" "*,*,z10_super,*,*")])
1036 (define_insn "*cmpqi_ccu"
1037 [(set (reg CC_REGNUM)
1038 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1039 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1040 "s390_match_ccmode (insn, CCUmode)
1041 && !register_operand (operands[1], QImode)"
1049 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1050 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1053 ; Block compare (CLC) instruction patterns.
1056 [(set (reg CC_REGNUM)
1057 (compare (match_operand:BLK 0 "memory_operand" "Q")
1058 (match_operand:BLK 1 "memory_operand" "Q")))
1059 (use (match_operand 2 "const_int_operand" "n"))]
1060 "s390_match_ccmode (insn, CCUmode)
1061 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1062 "clc\t%O0(%2,%R0),%S1"
1063 [(set_attr "op_type" "SS")])
1066 [(set (reg CC_REGNUM)
1067 (compare (match_operand 0 "memory_operand" "")
1068 (match_operand 1 "memory_operand" "")))]
1070 && s390_match_ccmode (insn, CCUmode)
1071 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1072 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1074 [(set (match_dup 0) (match_dup 1))
1075 (use (match_dup 2))])]
1077 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1078 operands[0] = adjust_address (operands[0], BLKmode, 0);
1079 operands[1] = adjust_address (operands[1], BLKmode, 0);
1081 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1082 operands[0], operands[1]);
1083 operands[0] = SET_DEST (PATTERN (curr_insn));
1087 ; (TF|DF|SF|TD|DD|SD) instructions
1089 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1090 (define_insn "*cmp<mode>_ccs_0"
1091 [(set (reg CC_REGNUM)
1092 (compare (match_operand:FP 0 "register_operand" "f")
1093 (match_operand:FP 1 "const0_operand" "")))]
1094 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1095 "lt<xde><bt>r\t%0,%0"
1096 [(set_attr "op_type" "RRE")
1097 (set_attr "type" "fsimp<mode>")])
1099 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1100 (define_insn "*cmp<mode>_ccs"
1101 [(set (reg CC_REGNUM)
1102 (compare (match_operand:FP 0 "register_operand" "f,f")
1103 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1104 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1108 [(set_attr "op_type" "RRE,RXE")
1109 (set_attr "type" "fsimp<mode>")])
1112 ; Compare and Branch instructions
1114 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1115 ; The following instructions do a complementary access of their second
1116 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1117 (define_insn "*cmp_and_br_signed_<mode>"
1119 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1120 [(match_operand:GPR 1 "register_operand" "d,d")
1121 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1122 (label_ref (match_operand 3 "" ""))
1124 (clobber (reg:CC CC_REGNUM))]
1125 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1127 if (get_attr_length (insn) == 6)
1128 return which_alternative ?
1129 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1131 return which_alternative ?
1132 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1134 [(set_attr "op_type" "RIE")
1135 (set_attr "type" "branch")
1136 (set_attr "z10prop" "z10_super_c,z10_super")
1137 (set (attr "length")
1138 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1139 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1140 ; 10 byte for cgr/jg
1142 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1143 ; The following instructions do a complementary access of their second
1144 ; operand (z10 only): clrj, clgrj, clr, clgr
1145 (define_insn "*cmp_and_br_unsigned_<mode>"
1147 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1148 [(match_operand:GPR 1 "register_operand" "d,d")
1149 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1150 (label_ref (match_operand 3 "" ""))
1152 (clobber (reg:CC CC_REGNUM))]
1153 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1155 if (get_attr_length (insn) == 6)
1156 return which_alternative ?
1157 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1159 return which_alternative ?
1160 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1162 [(set_attr "op_type" "RIE")
1163 (set_attr "type" "branch")
1164 (set_attr "z10prop" "z10_super_c,z10_super")
1165 (set (attr "length")
1166 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1167 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1168 ; 10 byte for clgr/jg
1170 ; And now the same two patterns as above but with a negated CC mask.
1172 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1173 ; The following instructions do a complementary access of their second
1174 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1175 (define_insn "*icmp_and_br_signed_<mode>"
1177 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1178 [(match_operand:GPR 1 "register_operand" "d,d")
1179 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1181 (label_ref (match_operand 3 "" ""))))
1182 (clobber (reg:CC CC_REGNUM))]
1183 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1185 if (get_attr_length (insn) == 6)
1186 return which_alternative ?
1187 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1189 return which_alternative ?
1190 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1192 [(set_attr "op_type" "RIE")
1193 (set_attr "type" "branch")
1194 (set_attr "z10prop" "z10_super_c,z10_super")
1195 (set (attr "length")
1196 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1197 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1198 ; 10 byte for cgr/jg
1200 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1201 ; The following instructions do a complementary access of their second
1202 ; operand (z10 only): clrj, clgrj, clr, clgr
1203 (define_insn "*icmp_and_br_unsigned_<mode>"
1205 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1206 [(match_operand:GPR 1 "register_operand" "d,d")
1207 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1209 (label_ref (match_operand 3 "" ""))))
1210 (clobber (reg:CC CC_REGNUM))]
1211 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1213 if (get_attr_length (insn) == 6)
1214 return which_alternative ?
1215 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1217 return which_alternative ?
1218 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1220 [(set_attr "op_type" "RIE")
1221 (set_attr "type" "branch")
1222 (set_attr "z10prop" "z10_super_c,z10_super")
1223 (set (attr "length")
1224 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1225 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1226 ; 10 byte for clgr/jg
1229 ;;- Move instructions.
1233 ; movti instruction pattern(s).
1236 (define_insn "movti"
1237 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1238 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1245 [(set_attr "op_type" "RSY,RSY,*,*")
1246 (set_attr "type" "lm,stm,*,*")])
1249 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1250 (match_operand:TI 1 "general_operand" ""))]
1251 "TARGET_ZARCH && reload_completed
1252 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1253 [(set (match_dup 2) (match_dup 4))
1254 (set (match_dup 3) (match_dup 5))]
1256 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1257 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1258 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1259 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1263 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1264 (match_operand:TI 1 "general_operand" ""))]
1265 "TARGET_ZARCH && reload_completed
1266 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1267 [(set (match_dup 2) (match_dup 4))
1268 (set (match_dup 3) (match_dup 5))]
1270 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1271 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1272 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1273 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1277 [(set (match_operand:TI 0 "register_operand" "")
1278 (match_operand:TI 1 "memory_operand" ""))]
1279 "TARGET_ZARCH && reload_completed
1280 && !s_operand (operands[1], VOIDmode)"
1281 [(set (match_dup 0) (match_dup 1))]
1283 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1284 addr = gen_lowpart (Pmode, addr);
1285 s390_load_address (addr, XEXP (operands[1], 0));
1286 operands[1] = replace_equiv_address (operands[1], addr);
1291 ; Patterns used for secondary reloads
1294 ; z10 provides move instructions accepting larl memory operands.
1295 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1296 ; These patterns are also used for unaligned SI and DI accesses.
1298 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1299 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1300 (match_operand:INTALL 1 "register_operand" "=d")
1301 (match_operand:P 2 "register_operand" "=&a")])]
1304 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1308 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1309 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1310 (match_operand:INTALL 1 "memory_operand" "")
1311 (match_operand:P 2 "register_operand" "=a")])]
1314 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1318 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1319 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1320 (match_operand:FPALL 1 "register_operand" "=d")
1321 (match_operand:P 2 "register_operand" "=&a")])]
1324 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1328 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1329 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1330 (match_operand:FPALL 1 "memory_operand" "")
1331 (match_operand:P 2 "register_operand" "=a")])]
1334 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1338 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1339 [(parallel [(match_operand:P 0 "register_operand" "=d")
1340 (match_operand:P 1 "larl_operand" "")
1341 (match_operand:P 2 "register_operand" "=a")])]
1344 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1348 ; Handles loading a PLUS (load address) expression
1350 (define_expand "reload<mode>_plus"
1351 [(parallel [(match_operand:P 0 "register_operand" "=a")
1352 (match_operand:P 1 "s390_plus_operand" "")
1353 (match_operand:P 2 "register_operand" "=&a")])]
1356 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1360 ; Handles assessing a non-offsetable memory address
1362 (define_expand "reload<mode>_nonoffmem_in"
1363 [(parallel [(match_operand 0 "register_operand" "")
1364 (match_operand 1 "" "")
1365 (match_operand:P 2 "register_operand" "=&a")])]
1368 gcc_assert (MEM_P (operands[1]));
1369 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1370 operands[1] = replace_equiv_address (operands[1], operands[2]);
1371 emit_move_insn (operands[0], operands[1]);
1375 (define_expand "reload<mode>_nonoffmem_out"
1376 [(parallel [(match_operand 0 "" "")
1377 (match_operand 1 "register_operand" "")
1378 (match_operand:P 2 "register_operand" "=&a")])]
1381 gcc_assert (MEM_P (operands[0]));
1382 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1383 operands[0] = replace_equiv_address (operands[0], operands[2]);
1384 emit_move_insn (operands[0], operands[1]);
1388 (define_expand "reload<mode>_PIC_addr"
1389 [(parallel [(match_operand 0 "register_operand" "=d")
1390 (match_operand 1 "larl_operand" "")
1391 (match_operand:P 2 "register_operand" "=a")])]
1394 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1395 emit_move_insn (operands[0], new_rtx);
1399 ; movdi instruction pattern(s).
1402 (define_expand "movdi"
1403 [(set (match_operand:DI 0 "general_operand" "")
1404 (match_operand:DI 1 "general_operand" ""))]
1407 /* Handle symbolic constants. */
1409 && (SYMBOLIC_CONST (operands[1])
1410 || (GET_CODE (operands[1]) == PLUS
1411 && XEXP (operands[1], 0) == pic_offset_table_rtx
1412 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1413 emit_symbolic_move (operands);
1416 (define_insn "*movdi_larl"
1417 [(set (match_operand:DI 0 "register_operand" "=d")
1418 (match_operand:DI 1 "larl_operand" "X"))]
1420 && !FP_REG_P (operands[0])"
1422 [(set_attr "op_type" "RIL")
1423 (set_attr "type" "larl")
1424 (set_attr "z10prop" "z10_super_A1")])
1426 (define_insn "*movdi_64"
1427 [(set (match_operand:DI 0 "nonimmediate_operand"
1428 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1429 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1430 (match_operand:DI 1 "general_operand"
1431 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1432 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1461 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1462 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1463 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1464 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1466 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1467 z10,*,*,*,*,*,longdisp,*,longdisp,
1469 (set_attr "z10prop" "z10_fwd_A1,
1498 [(set (match_operand:DI 0 "register_operand" "")
1499 (match_operand:DI 1 "register_operand" ""))]
1500 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1501 [(set (match_dup 2) (match_dup 3))
1502 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1503 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1504 "operands[2] = gen_lowpart (SImode, operands[0]);
1505 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1508 [(set (match_operand:DI 0 "register_operand" "")
1509 (match_operand:DI 1 "register_operand" ""))]
1510 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1511 && dead_or_set_p (insn, operands[1])"
1512 [(set (match_dup 3) (match_dup 2))
1513 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1514 (set (match_dup 4) (match_dup 2))]
1515 "operands[2] = gen_lowpart (SImode, operands[1]);
1516 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1519 [(set (match_operand:DI 0 "register_operand" "")
1520 (match_operand:DI 1 "register_operand" ""))]
1521 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1522 && !dead_or_set_p (insn, operands[1])"
1523 [(set (match_dup 3) (match_dup 2))
1524 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1525 (set (match_dup 4) (match_dup 2))
1526 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1527 "operands[2] = gen_lowpart (SImode, operands[1]);
1528 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1530 (define_insn "*movdi_31"
1531 [(set (match_operand:DI 0 "nonimmediate_operand"
1532 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1533 (match_operand:DI 1 "general_operand"
1534 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1549 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1550 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1551 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1553 ; For a load from a symbol ref we can use one of the target registers
1554 ; together with larl to load the address.
1556 [(set (match_operand:DI 0 "register_operand" "")
1557 (match_operand:DI 1 "memory_operand" ""))]
1558 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1559 && larl_operand (XEXP (operands[1], 0), SImode)"
1560 [(set (match_dup 2) (match_dup 3))
1561 (set (match_dup 0) (match_dup 1))]
1563 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1564 operands[3] = XEXP (operands[1], 0);
1565 operands[1] = replace_equiv_address (operands[1], operands[2]);
1569 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1570 (match_operand:DI 1 "general_operand" ""))]
1571 "!TARGET_ZARCH && reload_completed
1572 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1573 [(set (match_dup 2) (match_dup 4))
1574 (set (match_dup 3) (match_dup 5))]
1576 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1577 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1578 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1579 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1583 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1584 (match_operand:DI 1 "general_operand" ""))]
1585 "!TARGET_ZARCH && reload_completed
1586 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1587 [(set (match_dup 2) (match_dup 4))
1588 (set (match_dup 3) (match_dup 5))]
1590 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1591 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1592 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1593 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1597 [(set (match_operand:DI 0 "register_operand" "")
1598 (match_operand:DI 1 "memory_operand" ""))]
1599 "!TARGET_ZARCH && reload_completed
1600 && !FP_REG_P (operands[0])
1601 && !s_operand (operands[1], VOIDmode)"
1602 [(set (match_dup 0) (match_dup 1))]
1604 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1605 s390_load_address (addr, XEXP (operands[1], 0));
1606 operands[1] = replace_equiv_address (operands[1], addr);
1610 [(set (match_operand:DI 0 "register_operand" "")
1611 (mem:DI (match_operand 1 "address_operand" "")))]
1613 && !FP_REG_P (operands[0])
1614 && GET_CODE (operands[1]) == SYMBOL_REF
1615 && CONSTANT_POOL_ADDRESS_P (operands[1])
1616 && get_pool_mode (operands[1]) == DImode
1617 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1618 [(set (match_dup 0) (match_dup 2))]
1619 "operands[2] = get_pool_constant (operands[1]);")
1621 (define_insn "*la_64"
1622 [(set (match_operand:DI 0 "register_operand" "=d,d")
1623 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1628 [(set_attr "op_type" "RX,RXY")
1629 (set_attr "type" "la")
1630 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1634 [(set (match_operand:DI 0 "register_operand" "")
1635 (match_operand:QI 1 "address_operand" ""))
1636 (clobber (reg:CC CC_REGNUM))])]
1638 && preferred_la_operand_p (operands[1], const0_rtx)"
1639 [(set (match_dup 0) (match_dup 1))]
1643 [(set (match_operand:DI 0 "register_operand" "")
1644 (match_operand:DI 1 "register_operand" ""))
1647 (plus:DI (match_dup 0)
1648 (match_operand:DI 2 "nonmemory_operand" "")))
1649 (clobber (reg:CC CC_REGNUM))])]
1651 && !reg_overlap_mentioned_p (operands[0], operands[2])
1652 && preferred_la_operand_p (operands[1], operands[2])"
1653 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1657 ; movsi instruction pattern(s).
1660 (define_expand "movsi"
1661 [(set (match_operand:SI 0 "general_operand" "")
1662 (match_operand:SI 1 "general_operand" ""))]
1665 /* Handle symbolic constants. */
1667 && (SYMBOLIC_CONST (operands[1])
1668 || (GET_CODE (operands[1]) == PLUS
1669 && XEXP (operands[1], 0) == pic_offset_table_rtx
1670 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1671 emit_symbolic_move (operands);
1674 (define_insn "*movsi_larl"
1675 [(set (match_operand:SI 0 "register_operand" "=d")
1676 (match_operand:SI 1 "larl_operand" "X"))]
1677 "!TARGET_64BIT && TARGET_CPU_ZARCH
1678 && !FP_REG_P (operands[0])"
1680 [(set_attr "op_type" "RIL")
1681 (set_attr "type" "larl")
1682 (set_attr "z10prop" "z10_fwd_A1")])
1684 (define_insn "*movsi_zarch"
1685 [(set (match_operand:SI 0 "nonimmediate_operand"
1686 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1687 (match_operand:SI 1 "general_operand"
1688 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1713 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1714 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1715 (set_attr "type" "*,
1737 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1738 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1739 (set_attr "z10prop" "z10_fwd_A1,
1762 (define_insn "*movsi_esa"
1763 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1764 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1778 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1779 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1780 (set_attr "z10prop" "z10_fwd_A1,
1794 [(set (match_operand:SI 0 "register_operand" "")
1795 (mem:SI (match_operand 1 "address_operand" "")))]
1796 "!FP_REG_P (operands[0])
1797 && GET_CODE (operands[1]) == SYMBOL_REF
1798 && CONSTANT_POOL_ADDRESS_P (operands[1])
1799 && get_pool_mode (operands[1]) == SImode
1800 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1801 [(set (match_dup 0) (match_dup 2))]
1802 "operands[2] = get_pool_constant (operands[1]);")
1804 (define_insn "*la_31"
1805 [(set (match_operand:SI 0 "register_operand" "=d,d")
1806 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1807 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1811 [(set_attr "op_type" "RX,RXY")
1812 (set_attr "type" "la")
1813 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1817 [(set (match_operand:SI 0 "register_operand" "")
1818 (match_operand:QI 1 "address_operand" ""))
1819 (clobber (reg:CC CC_REGNUM))])]
1821 && preferred_la_operand_p (operands[1], const0_rtx)"
1822 [(set (match_dup 0) (match_dup 1))]
1826 [(set (match_operand:SI 0 "register_operand" "")
1827 (match_operand:SI 1 "register_operand" ""))
1830 (plus:SI (match_dup 0)
1831 (match_operand:SI 2 "nonmemory_operand" "")))
1832 (clobber (reg:CC CC_REGNUM))])]
1834 && !reg_overlap_mentioned_p (operands[0], operands[2])
1835 && preferred_la_operand_p (operands[1], operands[2])"
1836 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1839 (define_insn "*la_31_and"
1840 [(set (match_operand:SI 0 "register_operand" "=d,d")
1841 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1842 (const_int 2147483647)))]
1847 [(set_attr "op_type" "RX,RXY")
1848 (set_attr "type" "la")
1849 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1851 (define_insn_and_split "*la_31_and_cc"
1852 [(set (match_operand:SI 0 "register_operand" "=d")
1853 (and:SI (match_operand:QI 1 "address_operand" "p")
1854 (const_int 2147483647)))
1855 (clobber (reg:CC CC_REGNUM))]
1858 "&& reload_completed"
1860 (and:SI (match_dup 1) (const_int 2147483647)))]
1862 [(set_attr "op_type" "RX")
1863 (set_attr "type" "la")])
1865 (define_insn "force_la_31"
1866 [(set (match_operand:SI 0 "register_operand" "=d,d")
1867 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1868 (use (const_int 0))]
1873 [(set_attr "op_type" "RX")
1874 (set_attr "type" "la")
1875 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1878 ; movhi instruction pattern(s).
1881 (define_expand "movhi"
1882 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1883 (match_operand:HI 1 "general_operand" ""))]
1886 /* Make it explicit that loading a register from memory
1887 always sign-extends (at least) to SImode. */
1888 if (optimize && can_create_pseudo_p ()
1889 && register_operand (operands[0], VOIDmode)
1890 && GET_CODE (operands[1]) == MEM)
1892 rtx tmp = gen_reg_rtx (SImode);
1893 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1894 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1895 operands[1] = gen_lowpart (HImode, tmp);
1899 (define_insn "*movhi"
1900 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1901 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1913 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1914 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1915 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1916 (set_attr "z10prop" "z10_fr_E1,
1927 [(set (match_operand:HI 0 "register_operand" "")
1928 (mem:HI (match_operand 1 "address_operand" "")))]
1929 "GET_CODE (operands[1]) == SYMBOL_REF
1930 && CONSTANT_POOL_ADDRESS_P (operands[1])
1931 && get_pool_mode (operands[1]) == HImode
1932 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1933 [(set (match_dup 0) (match_dup 2))]
1934 "operands[2] = get_pool_constant (operands[1]);")
1937 ; movqi instruction pattern(s).
1940 (define_expand "movqi"
1941 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1942 (match_operand:QI 1 "general_operand" ""))]
1945 /* On z/Architecture, zero-extending from memory to register
1946 is just as fast as a QImode load. */
1947 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1948 && register_operand (operands[0], VOIDmode)
1949 && GET_CODE (operands[1]) == MEM)
1951 rtx tmp = gen_reg_rtx (DImode);
1952 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1953 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1954 operands[1] = gen_lowpart (QImode, tmp);
1958 (define_insn "*movqi"
1959 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1960 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1972 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1973 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1974 (set_attr "z10prop" "z10_fr_E1,
1985 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1986 (mem:QI (match_operand 1 "address_operand" "")))]
1987 "GET_CODE (operands[1]) == SYMBOL_REF
1988 && CONSTANT_POOL_ADDRESS_P (operands[1])
1989 && get_pool_mode (operands[1]) == QImode
1990 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1991 [(set (match_dup 0) (match_dup 2))]
1992 "operands[2] = get_pool_constant (operands[1]);")
1995 ; movstrictqi instruction pattern(s).
1998 (define_insn "*movstrictqi"
1999 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2000 (match_operand:QI 1 "memory_operand" "R,T"))]
2005 [(set_attr "op_type" "RX,RXY")
2006 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2009 ; movstricthi instruction pattern(s).
2012 (define_insn "*movstricthi"
2013 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2014 (match_operand:HI 1 "memory_operand" "Q,S"))
2015 (clobber (reg:CC CC_REGNUM))]
2020 [(set_attr "op_type" "RS,RSY")
2021 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2024 ; movstrictsi instruction pattern(s).
2027 (define_insn "movstrictsi"
2028 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2029 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2036 [(set_attr "op_type" "RR,RX,RXY,RRE")
2037 (set_attr "type" "lr,load,load,*")
2038 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2041 ; mov(tf|td) instruction pattern(s).
2044 (define_expand "mov<mode>"
2045 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2046 (match_operand:TD_TF 1 "general_operand" ""))]
2050 (define_insn "*mov<mode>_64"
2051 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2052 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2063 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2064 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2065 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2067 (define_insn "*mov<mode>_31"
2068 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2069 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2076 [(set_attr "op_type" "RRE,RRE,*,*")
2077 (set_attr "type" "fsimptf,fsimptf,*,*")
2078 (set_attr "cpu_facility" "z196,*,*,*")])
2080 ; TFmode in GPRs splitters
2083 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2084 (match_operand:TD_TF 1 "general_operand" ""))]
2085 "TARGET_ZARCH && reload_completed
2086 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2087 [(set (match_dup 2) (match_dup 4))
2088 (set (match_dup 3) (match_dup 5))]
2090 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2091 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2092 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2093 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2097 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2098 (match_operand:TD_TF 1 "general_operand" ""))]
2099 "TARGET_ZARCH && reload_completed
2100 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2101 [(set (match_dup 2) (match_dup 4))
2102 (set (match_dup 3) (match_dup 5))]
2104 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2105 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2106 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2107 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2111 [(set (match_operand:TD_TF 0 "register_operand" "")
2112 (match_operand:TD_TF 1 "memory_operand" ""))]
2113 "TARGET_ZARCH && reload_completed
2114 && !FP_REG_P (operands[0])
2115 && !s_operand (operands[1], VOIDmode)"
2116 [(set (match_dup 0) (match_dup 1))]
2118 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2119 addr = gen_lowpart (Pmode, addr);
2120 s390_load_address (addr, XEXP (operands[1], 0));
2121 operands[1] = replace_equiv_address (operands[1], addr);
2124 ; TFmode in BFPs splitters
2127 [(set (match_operand:TD_TF 0 "register_operand" "")
2128 (match_operand:TD_TF 1 "memory_operand" ""))]
2129 "reload_completed && offsettable_memref_p (operands[1])
2130 && FP_REG_P (operands[0])"
2131 [(set (match_dup 2) (match_dup 4))
2132 (set (match_dup 3) (match_dup 5))]
2134 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2136 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2138 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2139 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2143 [(set (match_operand:TD_TF 0 "memory_operand" "")
2144 (match_operand:TD_TF 1 "register_operand" ""))]
2145 "reload_completed && offsettable_memref_p (operands[0])
2146 && FP_REG_P (operands[1])"
2147 [(set (match_dup 2) (match_dup 4))
2148 (set (match_dup 3) (match_dup 5))]
2150 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2151 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2152 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2154 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2159 ; mov(df|dd) instruction pattern(s).
2162 (define_expand "mov<mode>"
2163 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2164 (match_operand:DD_DF 1 "general_operand" ""))]
2168 (define_insn "*mov<mode>_64dfp"
2169 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2170 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2171 (match_operand:DD_DF 1 "general_operand"
2172 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2187 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2188 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2189 fstoredf,fstoredf,*,lr,load,store")
2190 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2191 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2193 (define_insn "*mov<mode>_64"
2194 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2195 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2208 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2209 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2210 fstore<mode>,fstore<mode>,*,lr,load,store")
2211 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2212 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2214 (define_insn "*mov<mode>_31"
2215 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2216 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2217 (match_operand:DD_DF 1 "general_operand"
2218 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2233 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2234 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2235 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2236 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2239 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2240 (match_operand:DD_DF 1 "general_operand" ""))]
2241 "!TARGET_ZARCH && reload_completed
2242 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2243 [(set (match_dup 2) (match_dup 4))
2244 (set (match_dup 3) (match_dup 5))]
2246 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2247 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2248 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2249 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2253 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2254 (match_operand:DD_DF 1 "general_operand" ""))]
2255 "!TARGET_ZARCH && reload_completed
2256 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2257 [(set (match_dup 2) (match_dup 4))
2258 (set (match_dup 3) (match_dup 5))]
2260 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2261 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2262 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2263 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2267 [(set (match_operand:DD_DF 0 "register_operand" "")
2268 (match_operand:DD_DF 1 "memory_operand" ""))]
2269 "!TARGET_ZARCH && reload_completed
2270 && !FP_REG_P (operands[0])
2271 && !s_operand (operands[1], VOIDmode)"
2272 [(set (match_dup 0) (match_dup 1))]
2274 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2275 s390_load_address (addr, XEXP (operands[1], 0));
2276 operands[1] = replace_equiv_address (operands[1], addr);
2280 ; mov(sf|sd) instruction pattern(s).
2283 (define_insn "mov<mode>"
2284 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2285 "=f,f,f,f,R,T,d,d,d,d,R,T")
2286 (match_operand:SD_SF 1 "general_operand"
2287 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2302 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2303 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2304 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2305 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2306 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2309 ; movcc instruction pattern
2312 (define_insn "movcc"
2313 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2314 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2324 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2325 (set_attr "type" "lr,*,*,load,load,store,store")
2326 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2327 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2330 ; Block move (MVC) patterns.
2334 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2335 (match_operand:BLK 1 "memory_operand" "Q"))
2336 (use (match_operand 2 "const_int_operand" "n"))]
2337 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2338 "mvc\t%O0(%2,%R0),%S1"
2339 [(set_attr "op_type" "SS")])
2341 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2342 ; order to have it implemented with mvc.
2345 [(set (match_operand:QI 0 "memory_operand" "")
2346 (match_operand:QI 1 "memory_operand" ""))]
2349 [(set (match_dup 0) (match_dup 1))
2350 (use (const_int 1))])]
2352 operands[0] = adjust_address (operands[0], BLKmode, 0);
2353 operands[1] = adjust_address (operands[1], BLKmode, 0);
2359 [(set (match_operand:BLK 0 "memory_operand" "")
2360 (match_operand:BLK 1 "memory_operand" ""))
2361 (use (match_operand 2 "const_int_operand" ""))])
2363 [(set (match_operand:BLK 3 "memory_operand" "")
2364 (match_operand:BLK 4 "memory_operand" ""))
2365 (use (match_operand 5 "const_int_operand" ""))])]
2366 "s390_offset_p (operands[0], operands[3], operands[2])
2367 && s390_offset_p (operands[1], operands[4], operands[2])
2368 && !s390_overlap_p (operands[0], operands[1],
2369 INTVAL (operands[2]) + INTVAL (operands[5]))
2370 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2372 [(set (match_dup 6) (match_dup 7))
2373 (use (match_dup 8))])]
2374 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2375 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2376 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2380 ; load_multiple pattern(s).
2382 ; ??? Due to reload problems with replacing registers inside match_parallel
2383 ; we currently support load_multiple/store_multiple only after reload.
2386 (define_expand "load_multiple"
2387 [(match_par_dup 3 [(set (match_operand 0 "" "")
2388 (match_operand 1 "" ""))
2389 (use (match_operand 2 "" ""))])]
2398 /* Support only loading a constant number of fixed-point registers from
2399 memory and only bother with this if more than two */
2400 if (GET_CODE (operands[2]) != CONST_INT
2401 || INTVAL (operands[2]) < 2
2402 || INTVAL (operands[2]) > 16
2403 || GET_CODE (operands[1]) != MEM
2404 || GET_CODE (operands[0]) != REG
2405 || REGNO (operands[0]) >= 16)
2408 count = INTVAL (operands[2]);
2409 regno = REGNO (operands[0]);
2410 mode = GET_MODE (operands[0]);
2411 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2414 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2415 if (!can_create_pseudo_p ())
2417 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2419 from = XEXP (operands[1], 0);
2422 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2423 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2424 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2426 from = XEXP (XEXP (operands[1], 0), 0);
2427 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2434 from = force_reg (Pmode, XEXP (operands[1], 0));
2438 for (i = 0; i < count; i++)
2439 XVECEXP (operands[3], 0, i)
2440 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2441 change_address (operands[1], mode,
2442 plus_constant (Pmode, from,
2443 off + i * GET_MODE_SIZE (mode))));
2446 (define_insn "*load_multiple_di"
2447 [(match_parallel 0 "load_multiple_operation"
2448 [(set (match_operand:DI 1 "register_operand" "=r")
2449 (match_operand:DI 2 "s_operand" "QS"))])]
2450 "reload_completed && TARGET_ZARCH"
2452 int words = XVECLEN (operands[0], 0);
2453 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2454 return "lmg\t%1,%0,%S2";
2456 [(set_attr "op_type" "RSY")
2457 (set_attr "type" "lm")])
2459 (define_insn "*load_multiple_si"
2460 [(match_parallel 0 "load_multiple_operation"
2461 [(set (match_operand:SI 1 "register_operand" "=r,r")
2462 (match_operand:SI 2 "s_operand" "Q,S"))])]
2465 int words = XVECLEN (operands[0], 0);
2466 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2467 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2469 [(set_attr "op_type" "RS,RSY")
2470 (set_attr "type" "lm")])
2473 ; store multiple pattern(s).
2476 (define_expand "store_multiple"
2477 [(match_par_dup 3 [(set (match_operand 0 "" "")
2478 (match_operand 1 "" ""))
2479 (use (match_operand 2 "" ""))])]
2488 /* Support only storing a constant number of fixed-point registers to
2489 memory and only bother with this if more than two. */
2490 if (GET_CODE (operands[2]) != CONST_INT
2491 || INTVAL (operands[2]) < 2
2492 || INTVAL (operands[2]) > 16
2493 || GET_CODE (operands[0]) != MEM
2494 || GET_CODE (operands[1]) != REG
2495 || REGNO (operands[1]) >= 16)
2498 count = INTVAL (operands[2]);
2499 regno = REGNO (operands[1]);
2500 mode = GET_MODE (operands[1]);
2501 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2504 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2506 if (!can_create_pseudo_p ())
2508 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2510 to = XEXP (operands[0], 0);
2513 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2514 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2515 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2517 to = XEXP (XEXP (operands[0], 0), 0);
2518 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2525 to = force_reg (Pmode, XEXP (operands[0], 0));
2529 for (i = 0; i < count; i++)
2530 XVECEXP (operands[3], 0, i)
2531 = gen_rtx_SET (VOIDmode,
2532 change_address (operands[0], mode,
2533 plus_constant (Pmode, to,
2534 off + i * GET_MODE_SIZE (mode))),
2535 gen_rtx_REG (mode, regno + i));
2538 (define_insn "*store_multiple_di"
2539 [(match_parallel 0 "store_multiple_operation"
2540 [(set (match_operand:DI 1 "s_operand" "=QS")
2541 (match_operand:DI 2 "register_operand" "r"))])]
2542 "reload_completed && TARGET_ZARCH"
2544 int words = XVECLEN (operands[0], 0);
2545 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2546 return "stmg\t%2,%0,%S1";
2548 [(set_attr "op_type" "RSY")
2549 (set_attr "type" "stm")])
2552 (define_insn "*store_multiple_si"
2553 [(match_parallel 0 "store_multiple_operation"
2554 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2555 (match_operand:SI 2 "register_operand" "r,r"))])]
2558 int words = XVECLEN (operands[0], 0);
2559 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2560 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2562 [(set_attr "op_type" "RS,RSY")
2563 (set_attr "type" "stm")])
2566 ;; String instructions.
2569 (define_insn "*execute_rl"
2570 [(match_parallel 0 "execute_operation"
2571 [(unspec [(match_operand 1 "register_operand" "a")
2572 (match_operand 2 "" "")
2573 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2574 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2575 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2577 [(set_attr "op_type" "RIL")
2578 (set_attr "type" "cs")])
2580 (define_insn "*execute"
2581 [(match_parallel 0 "execute_operation"
2582 [(unspec [(match_operand 1 "register_operand" "a")
2583 (match_operand:BLK 2 "memory_operand" "R")
2584 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2585 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2586 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2588 [(set_attr "op_type" "RX")
2589 (set_attr "type" "cs")])
2593 ; strlenM instruction pattern(s).
2596 (define_expand "strlen<mode>"
2597 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2600 (unspec:P [(const_int 0)
2601 (match_operand:BLK 1 "memory_operand" "")
2603 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2604 (clobber (scratch:P))
2605 (clobber (reg:CC CC_REGNUM))])
2607 [(set (match_operand:P 0 "register_operand" "")
2608 (minus:P (match_dup 4) (match_dup 5)))
2609 (clobber (reg:CC CC_REGNUM))])]
2612 operands[4] = gen_reg_rtx (Pmode);
2613 operands[5] = gen_reg_rtx (Pmode);
2614 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2615 operands[1] = replace_equiv_address (operands[1], operands[5]);
2618 (define_insn "*strlen<mode>"
2619 [(set (match_operand:P 0 "register_operand" "=a")
2620 (unspec:P [(match_operand:P 2 "general_operand" "0")
2621 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2623 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2624 (clobber (match_scratch:P 1 "=a"))
2625 (clobber (reg:CC CC_REGNUM))]
2627 "srst\t%0,%1\;jo\t.-4"
2628 [(set_attr "length" "8")
2629 (set_attr "type" "vs")])
2632 ; cmpstrM instruction pattern(s).
2635 (define_expand "cmpstrsi"
2636 [(set (reg:SI 0) (const_int 0))
2638 [(clobber (match_operand 3 "" ""))
2639 (clobber (match_dup 4))
2640 (set (reg:CCU CC_REGNUM)
2641 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2642 (match_operand:BLK 2 "memory_operand" "")))
2645 [(set (match_operand:SI 0 "register_operand" "=d")
2646 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2647 (clobber (reg:CC CC_REGNUM))])]
2650 /* As the result of CMPINT is inverted compared to what we need,
2651 we have to swap the operands. */
2652 rtx op1 = operands[2];
2653 rtx op2 = operands[1];
2654 rtx addr1 = gen_reg_rtx (Pmode);
2655 rtx addr2 = gen_reg_rtx (Pmode);
2657 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2658 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2659 operands[1] = replace_equiv_address_nv (op1, addr1);
2660 operands[2] = replace_equiv_address_nv (op2, addr2);
2661 operands[3] = addr1;
2662 operands[4] = addr2;
2665 (define_insn "*cmpstr<mode>"
2666 [(clobber (match_operand:P 0 "register_operand" "=d"))
2667 (clobber (match_operand:P 1 "register_operand" "=d"))
2668 (set (reg:CCU CC_REGNUM)
2669 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2670 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2673 "clst\t%0,%1\;jo\t.-4"
2674 [(set_attr "length" "8")
2675 (set_attr "type" "vs")])
2678 ; movstr instruction pattern.
2681 (define_expand "movstr"
2682 [(set (reg:SI 0) (const_int 0))
2684 [(clobber (match_dup 3))
2685 (set (match_operand:BLK 1 "memory_operand" "")
2686 (match_operand:BLK 2 "memory_operand" ""))
2687 (set (match_operand 0 "register_operand" "")
2688 (unspec [(match_dup 1)
2690 (reg:SI 0)] UNSPEC_MVST))
2691 (clobber (reg:CC CC_REGNUM))])]
2694 rtx addr1 = gen_reg_rtx (Pmode);
2695 rtx addr2 = gen_reg_rtx (Pmode);
2697 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2698 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2699 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2700 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2701 operands[3] = addr2;
2704 (define_insn "*movstr"
2705 [(clobber (match_operand:P 2 "register_operand" "=d"))
2706 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2707 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2708 (set (match_operand:P 0 "register_operand" "=d")
2709 (unspec [(mem:BLK (match_dup 1))
2710 (mem:BLK (match_dup 3))
2711 (reg:SI 0)] UNSPEC_MVST))
2712 (clobber (reg:CC CC_REGNUM))]
2714 "mvst\t%1,%2\;jo\t.-4"
2715 [(set_attr "length" "8")
2716 (set_attr "type" "vs")])
2720 ; movmemM instruction pattern(s).
2723 (define_expand "movmem<mode>"
2724 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2725 (match_operand:BLK 1 "memory_operand" "")) ; source
2726 (use (match_operand:GPR 2 "general_operand" "")) ; count
2727 (match_operand 3 "" "")]
2730 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2736 ; Move a block that is up to 256 bytes in length.
2737 ; The block length is taken as (operands[2] % 256) + 1.
2739 (define_expand "movmem_short"
2741 [(set (match_operand:BLK 0 "memory_operand" "")
2742 (match_operand:BLK 1 "memory_operand" ""))
2743 (use (match_operand 2 "nonmemory_operand" ""))
2744 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2745 (clobber (match_dup 3))])]
2747 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2749 (define_insn "*movmem_short"
2750 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2751 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2752 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2753 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2754 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2755 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2757 [(set_attr "type" "cs")
2758 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2761 [(set (match_operand:BLK 0 "memory_operand" "")
2762 (match_operand:BLK 1 "memory_operand" ""))
2763 (use (match_operand 2 "const_int_operand" ""))
2764 (use (match_operand 3 "immediate_operand" ""))
2765 (clobber (scratch))]
2768 [(set (match_dup 0) (match_dup 1))
2769 (use (match_dup 2))])]
2770 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2773 [(set (match_operand:BLK 0 "memory_operand" "")
2774 (match_operand:BLK 1 "memory_operand" ""))
2775 (use (match_operand 2 "register_operand" ""))
2776 (use (match_operand 3 "memory_operand" ""))
2777 (clobber (scratch))]
2780 [(unspec [(match_dup 2) (match_dup 3)
2781 (const_int 0)] UNSPEC_EXECUTE)
2782 (set (match_dup 0) (match_dup 1))
2783 (use (const_int 1))])]
2787 [(set (match_operand:BLK 0 "memory_operand" "")
2788 (match_operand:BLK 1 "memory_operand" ""))
2789 (use (match_operand 2 "register_operand" ""))
2790 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2791 (clobber (scratch))]
2792 "TARGET_Z10 && reload_completed"
2794 [(unspec [(match_dup 2) (const_int 0)
2795 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2796 (set (match_dup 0) (match_dup 1))
2797 (use (const_int 1))])]
2798 "operands[3] = gen_label_rtx ();")
2801 [(set (match_operand:BLK 0 "memory_operand" "")
2802 (match_operand:BLK 1 "memory_operand" ""))
2803 (use (match_operand 2 "register_operand" ""))
2804 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2805 (clobber (match_operand 3 "register_operand" ""))]
2806 "reload_completed && TARGET_CPU_ZARCH"
2807 [(set (match_dup 3) (label_ref (match_dup 4)))
2809 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2810 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2811 (set (match_dup 0) (match_dup 1))
2812 (use (const_int 1))])]
2813 "operands[4] = gen_label_rtx ();")
2815 ; Move a block of arbitrary length.
2817 (define_expand "movmem_long"
2819 [(clobber (match_dup 2))
2820 (clobber (match_dup 3))
2821 (set (match_operand:BLK 0 "memory_operand" "")
2822 (match_operand:BLK 1 "memory_operand" ""))
2823 (use (match_operand 2 "general_operand" ""))
2825 (clobber (reg:CC CC_REGNUM))])]
2828 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2829 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2830 rtx reg0 = gen_reg_rtx (dreg_mode);
2831 rtx reg1 = gen_reg_rtx (dreg_mode);
2832 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2833 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2834 rtx len0 = gen_lowpart (Pmode, reg0);
2835 rtx len1 = gen_lowpart (Pmode, reg1);
2837 emit_clobber (reg0);
2838 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2839 emit_move_insn (len0, operands[2]);
2841 emit_clobber (reg1);
2842 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2843 emit_move_insn (len1, operands[2]);
2845 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2846 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2851 (define_insn "*movmem_long"
2852 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2853 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2854 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2855 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2858 (clobber (reg:CC CC_REGNUM))]
2859 "TARGET_64BIT || !TARGET_ZARCH"
2860 "mvcle\t%0,%1,0\;jo\t.-4"
2861 [(set_attr "length" "8")
2862 (set_attr "type" "vs")])
2864 (define_insn "*movmem_long_31z"
2865 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2866 (clobber (match_operand:TI 1 "register_operand" "=d"))
2867 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2868 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2871 (clobber (reg:CC CC_REGNUM))]
2872 "!TARGET_64BIT && TARGET_ZARCH"
2873 "mvcle\t%0,%1,0\;jo\t.-4"
2874 [(set_attr "length" "8")
2875 (set_attr "type" "vs")])
2882 (define_expand "signbit<mode>2"
2883 [(set (reg:CCZ CC_REGNUM)
2884 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2887 (set (match_operand:SI 0 "register_operand" "=d")
2888 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2891 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2894 (define_expand "isinf<mode>2"
2895 [(set (reg:CCZ CC_REGNUM)
2896 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2899 (set (match_operand:SI 0 "register_operand" "=d")
2900 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2903 operands[2] = GEN_INT (S390_TDC_INFINITY);
2906 (define_insn_and_split "*cc_to_int"
2907 [(set (match_operand:SI 0 "register_operand" "=d")
2908 (unspec:SI [(match_operand 1 "register_operand" "0")]
2913 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2915 ; This insn is used to generate all variants of the Test Data Class
2916 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2917 ; is the register to be tested and the second one is the bit mask
2918 ; specifying the required test(s).
2920 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2921 (define_insn "*TDC_insn_<mode>"
2922 [(set (reg:CCZ CC_REGNUM)
2923 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2924 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2926 "t<_d>c<xde><bt>\t%0,%1"
2927 [(set_attr "op_type" "RXE")
2928 (set_attr "type" "fsimp<mode>")])
2933 ; setmemM instruction pattern(s).
2936 (define_expand "setmem<mode>"
2937 [(set (match_operand:BLK 0 "memory_operand" "")
2938 (match_operand:QI 2 "general_operand" ""))
2939 (use (match_operand:GPR 1 "general_operand" ""))
2940 (match_operand 3 "" "")]
2942 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2944 ; Clear a block that is up to 256 bytes in length.
2945 ; The block length is taken as (operands[1] % 256) + 1.
2947 (define_expand "clrmem_short"
2949 [(set (match_operand:BLK 0 "memory_operand" "")
2951 (use (match_operand 1 "nonmemory_operand" ""))
2952 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2953 (clobber (match_dup 2))
2954 (clobber (reg:CC CC_REGNUM))])]
2956 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2958 (define_insn "*clrmem_short"
2959 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2961 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2962 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2963 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2964 (clobber (reg:CC CC_REGNUM))]
2965 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2967 [(set_attr "type" "cs")
2968 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2971 [(set (match_operand:BLK 0 "memory_operand" "")
2973 (use (match_operand 1 "const_int_operand" ""))
2974 (use (match_operand 2 "immediate_operand" ""))
2976 (clobber (reg:CC CC_REGNUM))]
2979 [(set (match_dup 0) (const_int 0))
2981 (clobber (reg:CC CC_REGNUM))])]
2982 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2985 [(set (match_operand:BLK 0 "memory_operand" "")
2987 (use (match_operand 1 "register_operand" ""))
2988 (use (match_operand 2 "memory_operand" ""))
2990 (clobber (reg:CC CC_REGNUM))]
2993 [(unspec [(match_dup 1) (match_dup 2)
2994 (const_int 0)] UNSPEC_EXECUTE)
2995 (set (match_dup 0) (const_int 0))
2997 (clobber (reg:CC CC_REGNUM))])]
3001 [(set (match_operand:BLK 0 "memory_operand" "")
3003 (use (match_operand 1 "register_operand" ""))
3004 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3006 (clobber (reg:CC CC_REGNUM))]
3007 "TARGET_Z10 && reload_completed"
3009 [(unspec [(match_dup 1) (const_int 0)
3010 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3011 (set (match_dup 0) (const_int 0))
3013 (clobber (reg:CC CC_REGNUM))])]
3014 "operands[3] = gen_label_rtx ();")
3017 [(set (match_operand:BLK 0 "memory_operand" "")
3019 (use (match_operand 1 "register_operand" ""))
3020 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3021 (clobber (match_operand 2 "register_operand" ""))
3022 (clobber (reg:CC CC_REGNUM))]
3023 "reload_completed && TARGET_CPU_ZARCH"
3024 [(set (match_dup 2) (label_ref (match_dup 3)))
3026 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3027 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3028 (set (match_dup 0) (const_int 0))
3030 (clobber (reg:CC CC_REGNUM))])]
3031 "operands[3] = gen_label_rtx ();")
3033 ; Initialize a block of arbitrary length with (operands[2] % 256).
3035 (define_expand "setmem_long"
3037 [(clobber (match_dup 1))
3038 (set (match_operand:BLK 0 "memory_operand" "")
3039 (match_operand 2 "shift_count_or_setmem_operand" ""))
3040 (use (match_operand 1 "general_operand" ""))
3042 (clobber (reg:CC CC_REGNUM))])]
3045 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3046 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3047 rtx reg0 = gen_reg_rtx (dreg_mode);
3048 rtx reg1 = gen_reg_rtx (dreg_mode);
3049 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3050 rtx len0 = gen_lowpart (Pmode, reg0);
3052 emit_clobber (reg0);
3053 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3054 emit_move_insn (len0, operands[1]);
3056 emit_move_insn (reg1, const0_rtx);
3058 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3063 (define_insn "*setmem_long"
3064 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3065 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3066 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3068 (use (match_operand:<DBL> 1 "register_operand" "d"))
3069 (clobber (reg:CC CC_REGNUM))]
3070 "TARGET_64BIT || !TARGET_ZARCH"
3071 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3072 [(set_attr "length" "8")
3073 (set_attr "type" "vs")])
3075 (define_insn "*setmem_long_and"
3076 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3077 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3078 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3079 (match_operand 4 "const_int_operand" "n")))
3081 (use (match_operand:<DBL> 1 "register_operand" "d"))
3082 (clobber (reg:CC CC_REGNUM))]
3083 "(TARGET_64BIT || !TARGET_ZARCH) &&
3084 (INTVAL (operands[4]) & 255) == 255"
3085 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3086 [(set_attr "length" "8")
3087 (set_attr "type" "vs")])
3089 (define_insn "*setmem_long_31z"
3090 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3091 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3092 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3094 (use (match_operand:TI 1 "register_operand" "d"))
3095 (clobber (reg:CC CC_REGNUM))]
3096 "!TARGET_64BIT && TARGET_ZARCH"
3097 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3098 [(set_attr "length" "8")
3099 (set_attr "type" "vs")])
3102 ; cmpmemM instruction pattern(s).
3105 (define_expand "cmpmemsi"
3106 [(set (match_operand:SI 0 "register_operand" "")
3107 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3108 (match_operand:BLK 2 "memory_operand" "") ) )
3109 (use (match_operand:SI 3 "general_operand" ""))
3110 (use (match_operand:SI 4 "" ""))]
3113 if (s390_expand_cmpmem (operands[0], operands[1],
3114 operands[2], operands[3]))
3120 ; Compare a block that is up to 256 bytes in length.
3121 ; The block length is taken as (operands[2] % 256) + 1.
3123 (define_expand "cmpmem_short"
3125 [(set (reg:CCU CC_REGNUM)
3126 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3127 (match_operand:BLK 1 "memory_operand" "")))
3128 (use (match_operand 2 "nonmemory_operand" ""))
3129 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3130 (clobber (match_dup 3))])]
3132 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3134 (define_insn "*cmpmem_short"
3135 [(set (reg:CCU CC_REGNUM)
3136 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3137 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3138 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3139 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3140 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3141 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3143 [(set_attr "type" "cs")
3144 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3147 [(set (reg:CCU CC_REGNUM)
3148 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3149 (match_operand:BLK 1 "memory_operand" "")))
3150 (use (match_operand 2 "const_int_operand" ""))
3151 (use (match_operand 3 "immediate_operand" ""))
3152 (clobber (scratch))]
3155 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3156 (use (match_dup 2))])]
3157 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3160 [(set (reg:CCU CC_REGNUM)
3161 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3162 (match_operand:BLK 1 "memory_operand" "")))
3163 (use (match_operand 2 "register_operand" ""))
3164 (use (match_operand 3 "memory_operand" ""))
3165 (clobber (scratch))]
3168 [(unspec [(match_dup 2) (match_dup 3)
3169 (const_int 0)] UNSPEC_EXECUTE)
3170 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3171 (use (const_int 1))])]
3175 [(set (reg:CCU CC_REGNUM)
3176 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3177 (match_operand:BLK 1 "memory_operand" "")))
3178 (use (match_operand 2 "register_operand" ""))
3179 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3180 (clobber (scratch))]
3181 "TARGET_Z10 && reload_completed"
3183 [(unspec [(match_dup 2) (const_int 0)
3184 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3185 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3186 (use (const_int 1))])]
3187 "operands[4] = gen_label_rtx ();")
3190 [(set (reg:CCU CC_REGNUM)
3191 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3192 (match_operand:BLK 1 "memory_operand" "")))
3193 (use (match_operand 2 "register_operand" ""))
3194 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3195 (clobber (match_operand 3 "register_operand" ""))]
3196 "reload_completed && TARGET_CPU_ZARCH"
3197 [(set (match_dup 3) (label_ref (match_dup 4)))
3199 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3200 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3201 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3202 (use (const_int 1))])]
3203 "operands[4] = gen_label_rtx ();")
3205 ; Compare a block of arbitrary length.
3207 (define_expand "cmpmem_long"
3209 [(clobber (match_dup 2))
3210 (clobber (match_dup 3))
3211 (set (reg:CCU CC_REGNUM)
3212 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3213 (match_operand:BLK 1 "memory_operand" "")))
3214 (use (match_operand 2 "general_operand" ""))
3215 (use (match_dup 3))])]
3218 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3219 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3220 rtx reg0 = gen_reg_rtx (dreg_mode);
3221 rtx reg1 = gen_reg_rtx (dreg_mode);
3222 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3223 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3224 rtx len0 = gen_lowpart (Pmode, reg0);
3225 rtx len1 = gen_lowpart (Pmode, reg1);
3227 emit_clobber (reg0);
3228 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3229 emit_move_insn (len0, operands[2]);
3231 emit_clobber (reg1);
3232 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3233 emit_move_insn (len1, operands[2]);
3235 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3236 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3241 (define_insn "*cmpmem_long"
3242 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3243 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3244 (set (reg:CCU CC_REGNUM)
3245 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3246 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3248 (use (match_dup 3))]
3249 "TARGET_64BIT || !TARGET_ZARCH"
3250 "clcle\t%0,%1,0\;jo\t.-4"
3251 [(set_attr "length" "8")
3252 (set_attr "type" "vs")])
3254 (define_insn "*cmpmem_long_31z"
3255 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3256 (clobber (match_operand:TI 1 "register_operand" "=d"))
3257 (set (reg:CCU CC_REGNUM)
3258 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3259 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3261 (use (match_dup 3))]
3262 "!TARGET_64BIT && TARGET_ZARCH"
3263 "clcle\t%0,%1,0\;jo\t.-4"
3264 [(set_attr "op_type" "NN")
3265 (set_attr "type" "vs")
3266 (set_attr "length" "8")])
3268 ; Convert CCUmode condition code to integer.
3269 ; Result is zero if EQ, positive if LTU, negative if GTU.
3271 (define_insn_and_split "cmpint"
3272 [(set (match_operand:SI 0 "register_operand" "=d")
3273 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3274 UNSPEC_STRCMPCC_TO_INT))
3275 (clobber (reg:CC CC_REGNUM))]
3279 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3281 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3282 (clobber (reg:CC CC_REGNUM))])])
3284 (define_insn_and_split "*cmpint_cc"
3285 [(set (reg CC_REGNUM)
3286 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3287 UNSPEC_STRCMPCC_TO_INT)
3289 (set (match_operand:SI 0 "register_operand" "=d")
3290 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3291 "s390_match_ccmode (insn, CCSmode)"
3293 "&& reload_completed"
3294 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3296 [(set (match_dup 2) (match_dup 3))
3297 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3299 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3300 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3301 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3304 (define_insn_and_split "*cmpint_sign"
3305 [(set (match_operand:DI 0 "register_operand" "=d")
3306 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3307 UNSPEC_STRCMPCC_TO_INT)))
3308 (clobber (reg:CC CC_REGNUM))]
3311 "&& reload_completed"
3312 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3314 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3315 (clobber (reg:CC CC_REGNUM))])])
3317 (define_insn_and_split "*cmpint_sign_cc"
3318 [(set (reg CC_REGNUM)
3319 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3320 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3321 UNSPEC_STRCMPCC_TO_INT) 0)
3322 (const_int 32)) (const_int 32))
3324 (set (match_operand:DI 0 "register_operand" "=d")
3325 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3326 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3328 "&& reload_completed"
3329 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3331 [(set (match_dup 2) (match_dup 3))
3332 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3334 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3335 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3336 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3341 ;;- Conversion instructions.
3344 (define_insn "*sethighpartsi"
3345 [(set (match_operand:SI 0 "register_operand" "=d,d")
3346 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3347 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3348 (clobber (reg:CC CC_REGNUM))]
3353 [(set_attr "op_type" "RS,RSY")
3354 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3356 (define_insn "*sethighpartdi_64"
3357 [(set (match_operand:DI 0 "register_operand" "=d")
3358 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3359 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3360 (clobber (reg:CC CC_REGNUM))]
3363 [(set_attr "op_type" "RSY")
3364 (set_attr "z10prop" "z10_super")])
3366 (define_insn "*sethighpartdi_31"
3367 [(set (match_operand:DI 0 "register_operand" "=d,d")
3368 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3369 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3370 (clobber (reg:CC CC_REGNUM))]
3375 [(set_attr "op_type" "RS,RSY")
3376 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3379 ; extv instruction patterns
3382 ; FIXME: This expander needs to be converted from DI to GPR as well
3383 ; after resolving some issues with it.
3385 (define_expand "extzv"
3387 [(set (match_operand:DI 0 "register_operand" "=d")
3389 (match_operand:DI 1 "register_operand" "d")
3390 (match_operand 2 "const_int_operand" "") ; size
3391 (match_operand 3 "const_int_operand" ""))) ; start
3392 (clobber (reg:CC CC_REGNUM))])]
3395 /* Starting with zEC12 there is risbgn not clobbering CC. */
3398 emit_move_insn (operands[0],
3399 gen_rtx_ZERO_EXTRACT (DImode,
3407 (define_insn "*extzv<mode>_zEC12"
3408 [(set (match_operand:GPR 0 "register_operand" "=d")
3410 (match_operand:GPR 1 "register_operand" "d")
3411 (match_operand 2 "const_int_operand" "") ; size
3412 (match_operand 3 "const_int_operand" "")))] ; start]
3414 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3415 [(set_attr "op_type" "RIE")])
3417 (define_insn "*extzv<mode>_z10"
3418 [(set (match_operand:GPR 0 "register_operand" "=d")
3420 (match_operand:GPR 1 "register_operand" "d")
3421 (match_operand 2 "const_int_operand" "") ; size
3422 (match_operand 3 "const_int_operand" ""))) ; start
3423 (clobber (reg:CC CC_REGNUM))]
3425 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3426 [(set_attr "op_type" "RIE")
3427 (set_attr "z10prop" "z10_super_E1")])
3429 (define_insn_and_split "*pre_z10_extzv<mode>"
3430 [(set (match_operand:GPR 0 "register_operand" "=d")
3431 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3432 (match_operand 2 "nonzero_shift_count_operand" "")
3434 (clobber (reg:CC CC_REGNUM))]
3437 "&& reload_completed"
3439 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3440 (clobber (reg:CC CC_REGNUM))])
3441 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3443 int bitsize = INTVAL (operands[2]);
3444 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3445 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3447 operands[1] = adjust_address (operands[1], BLKmode, 0);
3448 set_mem_size (operands[1], size);
3449 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3450 operands[3] = GEN_INT (mask);
3453 (define_insn_and_split "*pre_z10_extv<mode>"
3454 [(set (match_operand:GPR 0 "register_operand" "=d")
3455 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3456 (match_operand 2 "nonzero_shift_count_operand" "")
3458 (clobber (reg:CC CC_REGNUM))]
3461 "&& reload_completed"
3463 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3464 (clobber (reg:CC CC_REGNUM))])
3466 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3467 (clobber (reg:CC CC_REGNUM))])]
3469 int bitsize = INTVAL (operands[2]);
3470 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3471 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3473 operands[1] = adjust_address (operands[1], BLKmode, 0);
3474 set_mem_size (operands[1], size);
3475 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3476 operands[3] = GEN_INT (mask);
3480 ; insv instruction patterns
3483 (define_expand "insv"
3484 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3485 (match_operand 1 "const_int_operand" "")
3486 (match_operand 2 "const_int_operand" ""))
3487 (match_operand 3 "general_operand" ""))]
3490 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3496 ; The normal RTL expansion will never generate a zero_extract where
3497 ; the location operand isn't word mode. However, we do this in the
3498 ; back-end when generating atomic operations. See s390_two_part_insv.
3499 (define_insn "*insv<mode>_zEC12"
3500 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3501 (match_operand 1 "const_int_operand" "I") ; size
3502 (match_operand 2 "const_int_operand" "I")) ; pos
3503 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3505 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3506 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3507 [(set_attr "op_type" "RIE")])
3509 (define_insn "*insv<mode>_z10"
3510 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3511 (match_operand 1 "const_int_operand" "I") ; size
3512 (match_operand 2 "const_int_operand" "I")) ; pos
3513 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3514 (clobber (reg:CC CC_REGNUM))]
3516 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3517 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3518 [(set_attr "op_type" "RIE")
3519 (set_attr "z10prop" "z10_super_E1")])
3521 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3522 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3523 (define_insn "*insv<mode>_zEC12_noshift"
3524 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3525 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3526 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3527 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3528 (match_operand:GPR 4 "const_int_operand" ""))))]
3529 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3530 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3531 [(set_attr "op_type" "RIE")])
3533 (define_insn "*insv<mode>_z10_noshift"
3534 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3535 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3536 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3537 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3538 (match_operand:GPR 4 "const_int_operand" ""))))
3539 (clobber (reg:CC CC_REGNUM))]
3540 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3541 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3542 [(set_attr "op_type" "RIE")
3543 (set_attr "z10prop" "z10_super_E1")])
3545 (define_insn "*r<noxa>sbg_<mode>_noshift"
3546 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3548 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3549 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3550 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3551 (clobber (reg:CC CC_REGNUM))]
3553 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3554 [(set_attr "op_type" "RIE")])
3556 (define_insn "*r<noxa>sbg_di_rotl"
3557 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3561 (match_operand:DI 1 "nonimmediate_operand" "d")
3562 (match_operand:DI 3 "const_int_operand" ""))
3563 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3564 (match_operand:DI 4 "nonimmediate_operand" "0")))
3565 (clobber (reg:CC CC_REGNUM))]
3567 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3568 [(set_attr "op_type" "RIE")])
3570 (define_insn "*r<noxa>sbg_<mode>_srl"
3571 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3575 (match_operand:GPR 1 "nonimmediate_operand" "d")
3576 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3577 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3578 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3579 (clobber (reg:CC CC_REGNUM))]
3581 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3582 INTVAL (operands[2]))"
3583 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3584 [(set_attr "op_type" "RIE")])
3586 (define_insn "*r<noxa>sbg_<mode>_sll"
3587 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3591 (match_operand:GPR 1 "nonimmediate_operand" "d")
3592 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3593 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3594 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3595 (clobber (reg:CC CC_REGNUM))]
3597 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3598 INTVAL (operands[2]))"
3599 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3600 [(set_attr "op_type" "RIE")])
3602 ;; These two are generated by combine for s.bf &= val.
3603 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3604 ;; shifts and ands, which results in some truly awful patterns
3605 ;; including subregs of operations. Rather unnecessisarily, IMO.
3608 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3609 ;; (const_int 24 [0x18])
3610 ;; (const_int 0 [0]))
3611 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3612 ;; (const_int 40 [0x28])) 4)
3613 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3615 ;; we should instead generate
3617 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3618 ;; (const_int 24 [0x18])
3619 ;; (const_int 0 [0]))
3620 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3621 ;; (const_int 40 [0x28]))
3622 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3624 ;; by noticing that we can push down the outer paradoxical subreg
3625 ;; into the operation.
3627 (define_insn "*insv_rnsbg_noshift"
3628 [(set (zero_extract:DI
3629 (match_operand:DI 0 "nonimmediate_operand" "+d")
3630 (match_operand 1 "const_int_operand" "")
3631 (match_operand 2 "const_int_operand" ""))
3634 (match_operand:DI 3 "nonimmediate_operand" "d")))
3635 (clobber (reg:CC CC_REGNUM))]
3637 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3638 "rnsbg\t%0,%3,%2,63,0"
3639 [(set_attr "op_type" "RIE")])
3641 (define_insn "*insv_rnsbg_srl"
3642 [(set (zero_extract:DI
3643 (match_operand:DI 0 "nonimmediate_operand" "+d")
3644 (match_operand 1 "const_int_operand" "")
3645 (match_operand 2 "const_int_operand" ""))
3649 (match_operand 3 "const_int_operand" ""))
3650 (match_operand:DI 4 "nonimmediate_operand" "d")))
3651 (clobber (reg:CC CC_REGNUM))]
3653 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3654 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3655 [(set_attr "op_type" "RIE")])
3657 (define_insn "*insv<mode>_mem_reg"
3658 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3659 (match_operand 1 "const_int_operand" "n,n")
3661 (match_operand:W 2 "register_operand" "d,d"))]
3662 "INTVAL (operands[1]) > 0
3663 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3664 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3666 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3668 operands[1] = GEN_INT ((1ul << size) - 1);
3669 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3670 : "stcmy\t%2,%1,%S0";
3672 [(set_attr "op_type" "RS,RSY")
3673 (set_attr "z10prop" "z10_super,z10_super")])
3675 (define_insn "*insvdi_mem_reghigh"
3676 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3677 (match_operand 1 "const_int_operand" "n")
3679 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3682 && INTVAL (operands[1]) > 0
3683 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3684 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3686 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3688 operands[1] = GEN_INT ((1ul << size) - 1);
3689 return "stcmh\t%2,%1,%S0";
3691 [(set_attr "op_type" "RSY")
3692 (set_attr "z10prop" "z10_super")])
3694 (define_insn "*insvdi_reg_imm"
3695 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3697 (match_operand 1 "const_int_operand" "n"))
3698 (match_operand:DI 2 "const_int_operand" "n"))]
3700 && INTVAL (operands[1]) >= 0
3701 && INTVAL (operands[1]) < BITS_PER_WORD
3702 && INTVAL (operands[1]) % 16 == 0"
3704 switch (BITS_PER_WORD - INTVAL (operands[1]))
3706 case 64: return "iihh\t%0,%x2"; break;
3707 case 48: return "iihl\t%0,%x2"; break;
3708 case 32: return "iilh\t%0,%x2"; break;
3709 case 16: return "iill\t%0,%x2"; break;
3710 default: gcc_unreachable();
3713 [(set_attr "op_type" "RI")
3714 (set_attr "z10prop" "z10_super_E1")])
3716 ; Update the left-most 32 bit of a DI.
3717 (define_insn "*insv_h_di_reg_extimm"
3718 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3721 (match_operand:DI 1 "const_int_operand" "n"))]
3724 [(set_attr "op_type" "RIL")
3725 (set_attr "z10prop" "z10_fwd_E1")])
3727 ; Update the right-most 32 bit of a DI.
3728 (define_insn "*insv_l_di_reg_extimm"
3729 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3732 (match_operand:DI 1 "const_int_operand" "n"))]
3735 [(set_attr "op_type" "RIL")
3736 (set_attr "z10prop" "z10_fwd_A1")])
3739 ; extendsidi2 instruction pattern(s).
3742 (define_expand "extendsidi2"
3743 [(set (match_operand:DI 0 "register_operand" "")
3744 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3749 emit_clobber (operands[0]);
3750 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3751 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3752 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3757 (define_insn "*extendsidi2"
3758 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3759 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3765 [(set_attr "op_type" "RRE,RXY,RIL")
3766 (set_attr "type" "*,*,larl")
3767 (set_attr "cpu_facility" "*,*,z10")
3768 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3771 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3774 (define_expand "extend<HQI:mode><DSI:mode>2"
3775 [(set (match_operand:DSI 0 "register_operand" "")
3776 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3779 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3781 rtx tmp = gen_reg_rtx (SImode);
3782 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3783 emit_insn (gen_extendsidi2 (operands[0], tmp));
3786 else if (!TARGET_EXTIMM)
3788 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3790 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3791 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3792 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3798 ; extendhidi2 instruction pattern(s).
3801 (define_insn "*extendhidi2_extimm"
3802 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3803 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3804 "TARGET_ZARCH && TARGET_EXTIMM"
3809 [(set_attr "op_type" "RRE,RXY,RIL")
3810 (set_attr "type" "*,*,larl")
3811 (set_attr "cpu_facility" "extimm,extimm,z10")
3812 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3814 (define_insn "*extendhidi2"
3815 [(set (match_operand:DI 0 "register_operand" "=d")
3816 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3819 [(set_attr "op_type" "RXY")
3820 (set_attr "z10prop" "z10_super_E1")])
3823 ; extendhisi2 instruction pattern(s).
3826 (define_insn "*extendhisi2_extimm"
3827 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3828 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3835 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3836 (set_attr "type" "*,*,*,larl")
3837 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3838 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3840 (define_insn "*extendhisi2"
3841 [(set (match_operand:SI 0 "register_operand" "=d,d")
3842 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3847 [(set_attr "op_type" "RX,RXY")
3848 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3851 ; extendqi(si|di)2 instruction pattern(s).
3854 ; lbr, lgbr, lb, lgb
3855 (define_insn "*extendqi<mode>2_extimm"
3856 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3857 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3862 [(set_attr "op_type" "RRE,RXY")
3863 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3866 (define_insn "*extendqi<mode>2"
3867 [(set (match_operand:GPR 0 "register_operand" "=d")
3868 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3869 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3871 [(set_attr "op_type" "RXY")
3872 (set_attr "z10prop" "z10_super_E1")])
3874 (define_insn_and_split "*extendqi<mode>2_short_displ"
3875 [(set (match_operand:GPR 0 "register_operand" "=d")
3876 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3877 (clobber (reg:CC CC_REGNUM))]
3878 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3880 "&& reload_completed"
3882 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3883 (clobber (reg:CC CC_REGNUM))])
3885 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3886 (clobber (reg:CC CC_REGNUM))])]
3888 operands[1] = adjust_address (operands[1], BLKmode, 0);
3889 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3890 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3894 ; zero_extendsidi2 instruction pattern(s).
3897 (define_expand "zero_extendsidi2"
3898 [(set (match_operand:DI 0 "register_operand" "")
3899 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3904 emit_clobber (operands[0]);
3905 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3906 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3911 (define_insn "*zero_extendsidi2"
3912 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3913 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3919 [(set_attr "op_type" "RRE,RXY,RIL")
3920 (set_attr "type" "*,*,larl")
3921 (set_attr "cpu_facility" "*,*,z10")
3922 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3925 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3928 (define_insn "*llgt_sidi"
3929 [(set (match_operand:DI 0 "register_operand" "=d")
3930 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3931 (const_int 2147483647)))]
3934 [(set_attr "op_type" "RXE")
3935 (set_attr "z10prop" "z10_super_E1")])
3937 (define_insn_and_split "*llgt_sidi_split"
3938 [(set (match_operand:DI 0 "register_operand" "=d")
3939 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3940 (const_int 2147483647)))
3941 (clobber (reg:CC CC_REGNUM))]
3944 "&& reload_completed"
3946 (and:DI (subreg:DI (match_dup 1) 0)
3947 (const_int 2147483647)))]
3950 (define_insn "*llgt_sisi"
3951 [(set (match_operand:SI 0 "register_operand" "=d,d")
3952 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3953 (const_int 2147483647)))]
3958 [(set_attr "op_type" "RRE,RXE")
3959 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3961 (define_insn "*llgt_didi"
3962 [(set (match_operand:DI 0 "register_operand" "=d,d")
3963 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3964 (const_int 2147483647)))]
3969 [(set_attr "op_type" "RRE,RXE")
3970 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3973 [(set (match_operand:DSI 0 "register_operand" "")
3974 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3975 (const_int 2147483647)))
3976 (clobber (reg:CC CC_REGNUM))]
3977 "TARGET_ZARCH && reload_completed"
3979 (and:DSI (match_dup 1)
3980 (const_int 2147483647)))]
3984 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3987 (define_expand "zero_extend<mode>di2"
3988 [(set (match_operand:DI 0 "register_operand" "")
3989 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3994 rtx tmp = gen_reg_rtx (SImode);
3995 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3996 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3999 else if (!TARGET_EXTIMM)
4001 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4002 operands[1] = gen_lowpart (DImode, operands[1]);
4003 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4004 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4009 (define_expand "zero_extend<mode>si2"
4010 [(set (match_operand:SI 0 "register_operand" "")
4011 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4016 operands[1] = gen_lowpart (SImode, operands[1]);
4017 emit_insn (gen_andsi3 (operands[0], operands[1],
4018 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4024 (define_insn "*zero_extendhi<mode>2_z10"
4025 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4026 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4032 [(set_attr "op_type" "RXY,RRE,RIL")
4033 (set_attr "type" "*,*,larl")
4034 (set_attr "cpu_facility" "*,*,z10")
4035 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4037 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4038 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4039 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4040 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4045 [(set_attr "op_type" "RRE,RXY")
4046 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4049 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4050 [(set (match_operand:GPR 0 "register_operand" "=d")
4051 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4052 "TARGET_ZARCH && !TARGET_EXTIMM"
4054 [(set_attr "op_type" "RXY")
4055 (set_attr "z10prop" "z10_fwd_A3")])
4057 (define_insn_and_split "*zero_extendhisi2_31"
4058 [(set (match_operand:SI 0 "register_operand" "=&d")
4059 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4060 (clobber (reg:CC CC_REGNUM))]
4063 "&& reload_completed"
4064 [(set (match_dup 0) (const_int 0))
4066 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4067 (clobber (reg:CC CC_REGNUM))])]
4068 "operands[2] = gen_lowpart (HImode, operands[0]);")
4070 (define_insn_and_split "*zero_extendqisi2_31"
4071 [(set (match_operand:SI 0 "register_operand" "=&d")
4072 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4075 "&& reload_completed"
4076 [(set (match_dup 0) (const_int 0))
4077 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4078 "operands[2] = gen_lowpart (QImode, operands[0]);")
4081 ; zero_extendqihi2 instruction pattern(s).
4084 (define_expand "zero_extendqihi2"
4085 [(set (match_operand:HI 0 "register_operand" "")
4086 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4087 "TARGET_ZARCH && !TARGET_EXTIMM"
4089 operands[1] = gen_lowpart (HImode, operands[1]);
4090 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4094 (define_insn "*zero_extendqihi2_64"
4095 [(set (match_operand:HI 0 "register_operand" "=d")
4096 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4097 "TARGET_ZARCH && !TARGET_EXTIMM"
4099 [(set_attr "op_type" "RXY")
4100 (set_attr "z10prop" "z10_fwd_A3")])
4102 (define_insn_and_split "*zero_extendqihi2_31"
4103 [(set (match_operand:HI 0 "register_operand" "=&d")
4104 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4107 "&& reload_completed"
4108 [(set (match_dup 0) (const_int 0))
4109 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4110 "operands[2] = gen_lowpart (QImode, operands[0]);")
4113 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4116 (define_expand "fixuns_truncdddi2"
4118 [(set (match_operand:DI 0 "register_operand" "")
4119 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4120 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4121 (clobber (reg:CC CC_REGNUM))])]
4127 rtx_code_label *label1 = gen_label_rtx ();
4128 rtx_code_label *label2 = gen_label_rtx ();
4129 rtx temp = gen_reg_rtx (TDmode);
4130 REAL_VALUE_TYPE cmp, sub;
4132 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4133 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4135 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4136 solution is doing the check and the subtraction in TD mode and using a
4137 TD -> DI convert afterwards. */
4138 emit_insn (gen_extendddtd2 (temp, operands[1]));
4139 temp = force_reg (TDmode, temp);
4140 emit_cmp_and_jump_insns (temp,
4141 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4142 LT, NULL_RTX, VOIDmode, 0, label1);
4143 emit_insn (gen_subtd3 (temp, temp,
4144 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4145 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4148 emit_label (label1);
4149 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4150 emit_label (label2);
4155 (define_expand "fixuns_trunctddi2"
4157 [(set (match_operand:DI 0 "register_operand" "")
4158 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4159 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4160 (clobber (reg:CC CC_REGNUM))])]
4166 rtx_code_label *label1 = gen_label_rtx ();
4167 rtx_code_label *label2 = gen_label_rtx ();
4168 rtx temp = gen_reg_rtx (TDmode);
4169 REAL_VALUE_TYPE cmp, sub;
4171 operands[1] = force_reg (TDmode, operands[1]);
4172 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4173 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4175 emit_cmp_and_jump_insns (operands[1],
4176 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4177 LT, NULL_RTX, VOIDmode, 0, label1);
4178 emit_insn (gen_subtd3 (temp, operands[1],
4179 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4180 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4183 emit_label (label1);
4184 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4185 emit_label (label2);
4191 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4192 ; instruction pattern(s).
4195 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4197 [(set (match_operand:GPR 0 "register_operand" "")
4198 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4199 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4200 (clobber (reg:CC CC_REGNUM))])]
4205 rtx_code_label *label1 = gen_label_rtx ();
4206 rtx_code_label *label2 = gen_label_rtx ();
4207 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4208 REAL_VALUE_TYPE cmp, sub;
4210 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4211 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4212 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4214 emit_cmp_and_jump_insns (operands[1],
4215 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4216 LT, NULL_RTX, VOIDmode, 0, label1);
4217 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4218 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4219 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4223 emit_label (label1);
4224 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4225 operands[1], GEN_INT (5)));
4226 emit_label (label2);
4231 ; fixuns_trunc(td|dd)si2 expander
4232 (define_expand "fixuns_trunc<mode>si2"
4234 [(set (match_operand:SI 0 "register_operand" "")
4235 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4236 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4237 (clobber (reg:CC CC_REGNUM))])]
4238 "TARGET_Z196 && TARGET_HARD_DFP"
4241 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4243 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4244 ; clfdtr, clfxtr, clgdtr, clgxtr
4245 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4246 [(set (match_operand:GPR 0 "register_operand" "=r")
4247 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4248 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4249 (clobber (reg:CC CC_REGNUM))]
4251 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4252 [(set_attr "op_type" "RRF")
4253 (set_attr "type" "ftoi")])
4255 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4256 [(set (match_operand:GPR 0 "register_operand" "")
4257 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4260 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4265 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4266 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4267 [(set (match_operand:GPR 0 "register_operand" "=d")
4268 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4269 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4270 (clobber (reg:CC CC_REGNUM))]
4272 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4273 [(set_attr "op_type" "RRE")
4274 (set_attr "type" "ftoi")])
4278 ; fix_trunc(td|dd)di2 instruction pattern(s).
4281 (define_expand "fix_trunc<mode>di2"
4282 [(set (match_operand:DI 0 "register_operand" "")
4283 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4284 "TARGET_ZARCH && TARGET_HARD_DFP"
4286 operands[1] = force_reg (<MODE>mode, operands[1]);
4287 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4293 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4294 [(set (match_operand:DI 0 "register_operand" "=d")
4295 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4296 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4297 (clobber (reg:CC CC_REGNUM))]
4298 "TARGET_ZARCH && TARGET_HARD_DFP"
4299 "cg<DFP:xde>tr\t%0,%h2,%1"
4300 [(set_attr "op_type" "RRF")
4301 (set_attr "type" "ftoidfp")])
4305 ; fix_trunctf(si|di)2 instruction pattern(s).
4308 (define_expand "fix_trunctf<mode>2"
4309 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4310 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4311 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4312 (clobber (reg:CC CC_REGNUM))])]
4318 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4321 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4322 (define_insn "floatdi<mode>2"
4323 [(set (match_operand:FP 0 "register_operand" "=f")
4324 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4325 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4326 "c<xde>g<bt>r\t%0,%1"
4327 [(set_attr "op_type" "RRE")
4328 (set_attr "type" "itof<mode>" )])
4330 ; cxfbr, cdfbr, cefbr
4331 (define_insn "floatsi<mode>2"
4332 [(set (match_operand:BFP 0 "register_operand" "=f")
4333 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4336 [(set_attr "op_type" "RRE")
4337 (set_attr "type" "itof<mode>" )])
4340 (define_insn "floatsi<mode>2"
4341 [(set (match_operand:DFP 0 "register_operand" "=f")
4342 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4343 "TARGET_Z196 && TARGET_HARD_FLOAT"
4344 "c<xde>ftr\t%0,0,%1,0"
4345 [(set_attr "op_type" "RRE")
4346 (set_attr "type" "itof<mode>" )])
4349 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4352 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4353 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4354 (define_insn "floatuns<GPR:mode><FP:mode>2"
4355 [(set (match_operand:FP 0 "register_operand" "=f")
4356 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4357 "TARGET_Z196 && TARGET_HARD_FLOAT"
4358 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4359 [(set_attr "op_type" "RRE")
4360 (set_attr "type" "itof<FP:mode>" )])
4363 ; truncdfsf2 instruction pattern(s).
4366 (define_insn "truncdfsf2"
4367 [(set (match_operand:SF 0 "register_operand" "=f")
4368 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4371 [(set_attr "op_type" "RRE")
4372 (set_attr "type" "ftruncdf")])
4375 ; trunctf(df|sf)2 instruction pattern(s).
4379 (define_insn "trunctf<mode>2"
4380 [(set (match_operand:DSF 0 "register_operand" "=f")
4381 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4382 (clobber (match_scratch:TF 2 "=f"))]
4384 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4385 [(set_attr "length" "6")
4386 (set_attr "type" "ftrunctf")])
4389 ; trunctddd2 and truncddsd2 instruction pattern(s).
4392 (define_insn "trunctddd2"
4393 [(set (match_operand:DD 0 "register_operand" "=f")
4394 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4395 (clobber (match_scratch:TD 2 "=f"))]
4397 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4398 [(set_attr "length" "6")
4399 (set_attr "type" "ftruncdd")])
4401 (define_insn "truncddsd2"
4402 [(set (match_operand:SD 0 "register_operand" "=f")
4403 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4406 [(set_attr "op_type" "RRF")
4407 (set_attr "type" "ftruncsd")])
4409 (define_expand "trunctdsd2"
4412 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4413 (clobber (match_scratch:TD 2 ""))])
4414 (set (match_operand:SD 0 "register_operand" "")
4415 (float_truncate:SD (match_dup 3)))]
4418 operands[3] = gen_reg_rtx (DDmode);
4422 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4425 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4426 (define_insn "extend<DSF:mode><BFP:mode>2"
4427 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4428 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4430 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4432 l<BFP:xde><DSF:xde>br\t%0,%1
4433 l<BFP:xde><DSF:xde>b\t%0,%1"
4434 [(set_attr "op_type" "RRE,RXE")
4435 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4438 ; extendddtd2 and extendsddd2 instruction pattern(s).
4441 (define_insn "extendddtd2"
4442 [(set (match_operand:TD 0 "register_operand" "=f")
4443 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4446 [(set_attr "op_type" "RRF")
4447 (set_attr "type" "fsimptf")])
4449 (define_insn "extendsddd2"
4450 [(set (match_operand:DD 0 "register_operand" "=f")
4451 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4454 [(set_attr "op_type" "RRF")
4455 (set_attr "type" "fsimptf")])
4457 (define_expand "extendsdtd2"
4459 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4460 (set (match_operand:TD 0 "register_operand" "")
4461 (float_extend:TD (match_dup 2)))]
4464 operands[2] = gen_reg_rtx (DDmode);
4467 ; Binary Floating Point - load fp integer
4469 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4470 ; For all of them the inexact exceptions are suppressed.
4472 ; fiebra, fidbra, fixbra
4473 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4474 [(set (match_operand:BFP 0 "register_operand" "=f")
4475 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4478 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4479 [(set_attr "op_type" "RRF")
4480 (set_attr "type" "fsimp<BFP:mode>")])
4482 ; rint is supposed to raise an inexact exception so we can use the
4483 ; older instructions.
4485 ; fiebr, fidbr, fixbr
4486 (define_insn "rint<BFP:mode>2"
4487 [(set (match_operand:BFP 0 "register_operand" "=f")
4488 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4489 UNSPEC_FPINT_RINT))]
4491 "fi<BFP:xde>br\t%0,0,%1"
4492 [(set_attr "op_type" "RRF")
4493 (set_attr "type" "fsimp<BFP:mode>")])
4496 ; Decimal Floating Point - load fp integer
4499 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4500 [(set (match_operand:DFP 0 "register_operand" "=f")
4501 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4504 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4505 [(set_attr "op_type" "RRF")
4506 (set_attr "type" "fsimp<DFP:mode>")])
4509 (define_insn "rint<DFP:mode>2"
4510 [(set (match_operand:DFP 0 "register_operand" "=f")
4511 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4512 UNSPEC_FPINT_RINT))]
4514 "fi<DFP:xde>tr\t%0,0,%1,0"
4515 [(set_attr "op_type" "RRF")
4516 (set_attr "type" "fsimp<DFP:mode>")])
4519 ; Binary <-> Decimal floating point trunc patterns
4522 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4523 [(set (reg:DFP_ALL FPR0_REGNUM)
4524 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4525 (use (reg:SI GPR0_REGNUM))
4526 (clobber (reg:CC CC_REGNUM))]
4530 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4531 [(set (reg:BFP FPR0_REGNUM)
4532 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4533 (use (reg:SI GPR0_REGNUM))
4534 (clobber (reg:CC CC_REGNUM))]
4538 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4539 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4540 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4542 [(set (reg:DFP_ALL FPR0_REGNUM)
4543 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4544 (use (reg:SI GPR0_REGNUM))
4545 (clobber (reg:CC CC_REGNUM))])
4546 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4547 (reg:DFP_ALL FPR0_REGNUM))]
4549 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4551 HOST_WIDE_INT flags;
4553 flags = (PFPO_CONVERT |
4554 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4555 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4557 operands[2] = GEN_INT (flags);
4560 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4561 [(set (reg:DFP_ALL FPR4_REGNUM)
4562 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4563 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4565 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4566 (use (reg:SI GPR0_REGNUM))
4567 (clobber (reg:CC CC_REGNUM))])
4568 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4570 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4572 HOST_WIDE_INT flags;
4574 flags = (PFPO_CONVERT |
4575 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4576 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4578 operands[2] = GEN_INT (flags);
4582 ; Binary <-> Decimal floating point extend patterns
4585 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4586 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4587 (use (reg:SI GPR0_REGNUM))
4588 (clobber (reg:CC CC_REGNUM))]
4592 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4593 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4594 (use (reg:SI GPR0_REGNUM))
4595 (clobber (reg:CC CC_REGNUM))]
4599 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4600 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4601 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4603 [(set (reg:DFP_ALL FPR0_REGNUM)
4604 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4605 (use (reg:SI GPR0_REGNUM))
4606 (clobber (reg:CC CC_REGNUM))])
4607 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4608 (reg:DFP_ALL FPR0_REGNUM))]
4610 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4612 HOST_WIDE_INT flags;
4614 flags = (PFPO_CONVERT |
4615 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4616 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4618 operands[2] = GEN_INT (flags);
4621 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4622 [(set (reg:DFP_ALL FPR4_REGNUM)
4623 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4624 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4626 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4627 (use (reg:SI GPR0_REGNUM))
4628 (clobber (reg:CC CC_REGNUM))])
4629 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4631 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4633 HOST_WIDE_INT flags;
4635 flags = (PFPO_CONVERT |
4636 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4637 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4639 operands[2] = GEN_INT (flags);
4644 ;; ARITHMETIC OPERATIONS
4646 ; arithmetic operations set the ConditionCode,
4647 ; because of unpredictable Bits in Register for Halfword and Byte
4648 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4651 ;;- Add instructions.
4655 ; addti3 instruction pattern(s).
4658 (define_insn_and_split "addti3"
4659 [(set (match_operand:TI 0 "register_operand" "=&d")
4660 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4661 (match_operand:TI 2 "general_operand" "do") ) )
4662 (clobber (reg:CC CC_REGNUM))]
4665 "&& reload_completed"
4667 [(set (reg:CCL1 CC_REGNUM)
4668 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4670 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4672 [(set (match_dup 3) (plus:DI
4673 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4674 (match_dup 4)) (match_dup 5)))
4675 (clobber (reg:CC CC_REGNUM))])]
4676 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4677 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4678 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4679 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4680 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4681 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4684 ; adddi3 instruction pattern(s).
4687 (define_expand "adddi3"
4689 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4690 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4691 (match_operand:DI 2 "general_operand" "")))
4692 (clobber (reg:CC CC_REGNUM))])]
4696 (define_insn "*adddi3_sign"
4697 [(set (match_operand:DI 0 "register_operand" "=d,d")
4698 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4699 (match_operand:DI 1 "register_operand" "0,0")))
4700 (clobber (reg:CC CC_REGNUM))]
4705 [(set_attr "op_type" "RRE,RXY")
4706 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4708 (define_insn "*adddi3_zero_cc"
4709 [(set (reg CC_REGNUM)
4710 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4711 (match_operand:DI 1 "register_operand" "0,0"))
4713 (set (match_operand:DI 0 "register_operand" "=d,d")
4714 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4715 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4719 [(set_attr "op_type" "RRE,RXY")
4720 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4722 (define_insn "*adddi3_zero_cconly"
4723 [(set (reg CC_REGNUM)
4724 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4725 (match_operand:DI 1 "register_operand" "0,0"))
4727 (clobber (match_scratch:DI 0 "=d,d"))]
4728 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4732 [(set_attr "op_type" "RRE,RXY")
4733 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4735 (define_insn "*adddi3_zero"
4736 [(set (match_operand:DI 0 "register_operand" "=d,d")
4737 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4738 (match_operand:DI 1 "register_operand" "0,0")))
4739 (clobber (reg:CC CC_REGNUM))]
4744 [(set_attr "op_type" "RRE,RXY")
4745 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4747 (define_insn_and_split "*adddi3_31z"
4748 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4749 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4750 (match_operand:DI 2 "general_operand" "do") ) )
4751 (clobber (reg:CC CC_REGNUM))]
4752 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4754 "&& reload_completed"
4756 [(set (reg:CCL1 CC_REGNUM)
4757 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4759 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4761 [(set (match_dup 3) (plus:SI
4762 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4763 (match_dup 4)) (match_dup 5)))
4764 (clobber (reg:CC CC_REGNUM))])]
4765 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4766 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4767 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4768 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4769 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4770 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4772 (define_insn_and_split "*adddi3_31"
4773 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4774 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4775 (match_operand:DI 2 "general_operand" "do") ) )
4776 (clobber (reg:CC CC_REGNUM))]
4779 "&& reload_completed"
4781 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4782 (clobber (reg:CC CC_REGNUM))])
4784 [(set (reg:CCL1 CC_REGNUM)
4785 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4787 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4789 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4791 (label_ref (match_dup 9))))
4793 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4794 (clobber (reg:CC CC_REGNUM))])
4796 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4797 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4798 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4799 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4800 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4801 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4802 operands[9] = gen_label_rtx ();")
4805 ; addsi3 instruction pattern(s).
4808 (define_expand "addsi3"
4810 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4811 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4812 (match_operand:SI 2 "general_operand" "")))
4813 (clobber (reg:CC CC_REGNUM))])]
4817 (define_insn "*addsi3_sign"
4818 [(set (match_operand:SI 0 "register_operand" "=d,d")
4819 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4820 (match_operand:SI 1 "register_operand" "0,0")))
4821 (clobber (reg:CC CC_REGNUM))]
4826 [(set_attr "op_type" "RX,RXY")
4827 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4830 ; add(di|si)3 instruction pattern(s).
4833 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4834 (define_insn "*add<mode>3"
4835 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4836 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4837 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4838 (clobber (reg:CC CC_REGNUM))]
4850 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4851 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4852 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4853 z10_super_E1,z10_super_E1,z10_super_E1")])
4855 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4856 (define_insn "*add<mode>3_carry1_cc"
4857 [(set (reg CC_REGNUM)
4858 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4859 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4861 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4862 (plus:GPR (match_dup 1) (match_dup 2)))]
4863 "s390_match_ccmode (insn, CCL1mode)"
4869 al<g>hsik\t%0,%1,%h2
4873 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4874 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4875 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4876 z10_super_E1,z10_super_E1,z10_super_E1")])
4878 ; alr, al, aly, algr, alg, alrk, algrk
4879 (define_insn "*add<mode>3_carry1_cconly"
4880 [(set (reg CC_REGNUM)
4881 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4882 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4884 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4885 "s390_match_ccmode (insn, CCL1mode)"
4891 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4892 (set_attr "cpu_facility" "*,z196,*,*")
4893 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4895 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4896 (define_insn "*add<mode>3_carry2_cc"
4897 [(set (reg CC_REGNUM)
4898 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4899 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4901 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4902 (plus:GPR (match_dup 1) (match_dup 2)))]
4903 "s390_match_ccmode (insn, CCL1mode)"
4909 al<g>hsik\t%0,%1,%h2
4913 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4914 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4915 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4916 z10_super_E1,z10_super_E1,z10_super_E1")])
4918 ; alr, al, aly, algr, alg, alrk, algrk
4919 (define_insn "*add<mode>3_carry2_cconly"
4920 [(set (reg CC_REGNUM)
4921 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4922 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4924 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4925 "s390_match_ccmode (insn, CCL1mode)"
4931 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4932 (set_attr "cpu_facility" "*,z196,*,*")
4933 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4935 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4936 (define_insn "*add<mode>3_cc"
4937 [(set (reg CC_REGNUM)
4938 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4939 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4941 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4942 (plus:GPR (match_dup 1) (match_dup 2)))]
4943 "s390_match_ccmode (insn, CCLmode)"
4949 al<g>hsik\t%0,%1,%h2
4953 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4954 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4955 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4956 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4958 ; alr, al, aly, algr, alg, alrk, algrk
4959 (define_insn "*add<mode>3_cconly"
4960 [(set (reg CC_REGNUM)
4961 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4962 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4964 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4965 "s390_match_ccmode (insn, CCLmode)"
4971 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4972 (set_attr "cpu_facility" "*,z196,*,*")
4973 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4975 ; alr, al, aly, algr, alg, alrk, algrk
4976 (define_insn "*add<mode>3_cconly2"
4977 [(set (reg CC_REGNUM)
4978 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4979 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4980 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4981 "s390_match_ccmode(insn, CCLmode)"
4987 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4988 (set_attr "cpu_facility" "*,z196,*,*")
4989 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4991 ; ahi, afi, aghi, agfi, asi, agsi
4992 (define_insn "*add<mode>3_imm_cc"
4993 [(set (reg CC_REGNUM)
4994 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4995 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4997 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4998 (plus:GPR (match_dup 1) (match_dup 2)))]
4999 "s390_match_ccmode (insn, CCAmode)
5000 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5001 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5002 /* Avoid INT32_MIN on 32 bit. */
5003 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5009 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5010 (set_attr "cpu_facility" "*,z196,extimm,z10")
5011 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5014 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5017 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5018 (define_insn "add<mode>3"
5019 [(set (match_operand:FP 0 "register_operand" "=f, f")
5020 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5021 (match_operand:FP 2 "general_operand" " f,<Rf>")))
5022 (clobber (reg:CC CC_REGNUM))]
5025 a<xde><bt>r\t%0,<op1>%2
5027 [(set_attr "op_type" "<RRer>,RXE")
5028 (set_attr "type" "fsimp<mode>")])
5030 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5031 (define_insn "*add<mode>3_cc"
5032 [(set (reg CC_REGNUM)
5033 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5034 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5035 (match_operand:FP 3 "const0_operand" "")))
5036 (set (match_operand:FP 0 "register_operand" "=f,f")
5037 (plus:FP (match_dup 1) (match_dup 2)))]
5038 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5040 a<xde><bt>r\t%0,<op1>%2
5042 [(set_attr "op_type" "<RRer>,RXE")
5043 (set_attr "type" "fsimp<mode>")])
5045 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5046 (define_insn "*add<mode>3_cconly"
5047 [(set (reg CC_REGNUM)
5048 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5049 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5050 (match_operand:FP 3 "const0_operand" "")))
5051 (clobber (match_scratch:FP 0 "=f,f"))]
5052 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5054 a<xde><bt>r\t%0,<op1>%2
5056 [(set_attr "op_type" "<RRer>,RXE")
5057 (set_attr "type" "fsimp<mode>")])
5060 ; Pointer add instruction patterns
5063 ; This will match "*la_64"
5064 (define_expand "addptrdi3"
5065 [(set (match_operand:DI 0 "register_operand" "")
5066 (plus:DI (match_operand:DI 1 "register_operand" "")
5067 (match_operand:DI 2 "nonmemory_operand" "")))]
5070 if (GET_CODE (operands[2]) == CONST_INT)
5072 HOST_WIDE_INT c = INTVAL (operands[2]);
5074 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5075 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5077 operands[2] = force_const_mem (DImode, operands[2]);
5078 operands[2] = force_reg (DImode, operands[2]);
5080 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5081 operands[2] = force_reg (DImode, operands[2]);
5085 ; For 31 bit we have to prevent the generated pattern from matching
5086 ; normal ADDs since la only does a 31 bit add. This is supposed to
5087 ; match "force_la_31".
5088 (define_expand "addptrsi3"
5090 [(set (match_operand:SI 0 "register_operand" "")
5091 (plus:SI (match_operand:SI 1 "register_operand" "")
5092 (match_operand:SI 2 "nonmemory_operand" "")))
5093 (use (const_int 0))])]
5096 if (GET_CODE (operands[2]) == CONST_INT)
5098 HOST_WIDE_INT c = INTVAL (operands[2]);
5100 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5101 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5103 operands[2] = force_const_mem (SImode, operands[2]);
5104 operands[2] = force_reg (SImode, operands[2]);
5106 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5107 operands[2] = force_reg (SImode, operands[2]);
5112 ;;- Subtract instructions.
5116 ; subti3 instruction pattern(s).
5119 (define_insn_and_split "subti3"
5120 [(set (match_operand:TI 0 "register_operand" "=&d")
5121 (minus:TI (match_operand:TI 1 "register_operand" "0")
5122 (match_operand:TI 2 "general_operand" "do") ) )
5123 (clobber (reg:CC CC_REGNUM))]
5126 "&& reload_completed"
5128 [(set (reg:CCL2 CC_REGNUM)
5129 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5131 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5133 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5134 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5135 (clobber (reg:CC CC_REGNUM))])]
5136 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5137 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5138 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5139 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5140 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5141 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
5144 ; subdi3 instruction pattern(s).
5147 (define_expand "subdi3"
5149 [(set (match_operand:DI 0 "register_operand" "")
5150 (minus:DI (match_operand:DI 1 "register_operand" "")
5151 (match_operand:DI 2 "general_operand" "")))
5152 (clobber (reg:CC CC_REGNUM))])]
5156 (define_insn "*subdi3_sign"
5157 [(set (match_operand:DI 0 "register_operand" "=d,d")
5158 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5159 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5160 (clobber (reg:CC CC_REGNUM))]
5165 [(set_attr "op_type" "RRE,RXY")
5166 (set_attr "z10prop" "z10_c,*")
5167 (set_attr "z196prop" "z196_cracked")])
5169 (define_insn "*subdi3_zero_cc"
5170 [(set (reg CC_REGNUM)
5171 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5172 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5174 (set (match_operand:DI 0 "register_operand" "=d,d")
5175 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5176 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5180 [(set_attr "op_type" "RRE,RXY")
5181 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5183 (define_insn "*subdi3_zero_cconly"
5184 [(set (reg CC_REGNUM)
5185 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5186 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5188 (clobber (match_scratch:DI 0 "=d,d"))]
5189 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5193 [(set_attr "op_type" "RRE,RXY")
5194 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5196 (define_insn "*subdi3_zero"
5197 [(set (match_operand:DI 0 "register_operand" "=d,d")
5198 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5199 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5200 (clobber (reg:CC CC_REGNUM))]
5205 [(set_attr "op_type" "RRE,RXY")
5206 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5208 (define_insn_and_split "*subdi3_31z"
5209 [(set (match_operand:DI 0 "register_operand" "=&d")
5210 (minus:DI (match_operand:DI 1 "register_operand" "0")
5211 (match_operand:DI 2 "general_operand" "do") ) )
5212 (clobber (reg:CC CC_REGNUM))]
5213 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5215 "&& reload_completed"
5217 [(set (reg:CCL2 CC_REGNUM)
5218 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5220 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5222 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5223 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5224 (clobber (reg:CC CC_REGNUM))])]
5225 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5226 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5227 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5228 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5229 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5230 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5232 (define_insn_and_split "*subdi3_31"
5233 [(set (match_operand:DI 0 "register_operand" "=&d")
5234 (minus:DI (match_operand:DI 1 "register_operand" "0")
5235 (match_operand:DI 2 "general_operand" "do") ) )
5236 (clobber (reg:CC CC_REGNUM))]
5239 "&& reload_completed"
5241 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5242 (clobber (reg:CC CC_REGNUM))])
5244 [(set (reg:CCL2 CC_REGNUM)
5245 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5247 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5249 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5251 (label_ref (match_dup 9))))
5253 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5254 (clobber (reg:CC CC_REGNUM))])
5256 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5257 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5258 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5259 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5260 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5261 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5262 operands[9] = gen_label_rtx ();")
5265 ; subsi3 instruction pattern(s).
5268 (define_expand "subsi3"
5270 [(set (match_operand:SI 0 "register_operand" "")
5271 (minus:SI (match_operand:SI 1 "register_operand" "")
5272 (match_operand:SI 2 "general_operand" "")))
5273 (clobber (reg:CC CC_REGNUM))])]
5277 (define_insn "*subsi3_sign"
5278 [(set (match_operand:SI 0 "register_operand" "=d,d")
5279 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5280 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5281 (clobber (reg:CC CC_REGNUM))]
5286 [(set_attr "op_type" "RX,RXY")
5287 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5290 ; sub(di|si)3 instruction pattern(s).
5293 ; sr, s, sy, sgr, sg, srk, sgrk
5294 (define_insn "*sub<mode>3"
5295 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5296 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5297 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5298 (clobber (reg:CC CC_REGNUM))]
5305 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5306 (set_attr "cpu_facility" "*,z196,*,*")
5307 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5309 ; slr, sl, sly, slgr, slg, slrk, slgrk
5310 (define_insn "*sub<mode>3_borrow_cc"
5311 [(set (reg CC_REGNUM)
5312 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5313 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5315 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5316 (minus:GPR (match_dup 1) (match_dup 2)))]
5317 "s390_match_ccmode (insn, CCL2mode)"
5323 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5324 (set_attr "cpu_facility" "*,z196,*,*")
5325 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5327 ; slr, sl, sly, slgr, slg, slrk, slgrk
5328 (define_insn "*sub<mode>3_borrow_cconly"
5329 [(set (reg CC_REGNUM)
5330 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5331 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5333 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5334 "s390_match_ccmode (insn, CCL2mode)"
5340 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5341 (set_attr "cpu_facility" "*,z196,*,*")
5342 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5344 ; slr, sl, sly, slgr, slg, slrk, slgrk
5345 (define_insn "*sub<mode>3_cc"
5346 [(set (reg CC_REGNUM)
5347 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5348 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5350 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5351 (minus:GPR (match_dup 1) (match_dup 2)))]
5352 "s390_match_ccmode (insn, CCLmode)"
5358 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5359 (set_attr "cpu_facility" "*,z196,*,*")
5360 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5362 ; slr, sl, sly, slgr, slg, slrk, slgrk
5363 (define_insn "*sub<mode>3_cc2"
5364 [(set (reg CC_REGNUM)
5365 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5366 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5367 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5368 (minus:GPR (match_dup 1) (match_dup 2)))]
5369 "s390_match_ccmode (insn, CCL3mode)"
5375 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5376 (set_attr "cpu_facility" "*,z196,*,*")
5377 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5379 ; slr, sl, sly, slgr, slg, slrk, slgrk
5380 (define_insn "*sub<mode>3_cconly"
5381 [(set (reg CC_REGNUM)
5382 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5383 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5385 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5386 "s390_match_ccmode (insn, CCLmode)"
5392 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5393 (set_attr "cpu_facility" "*,z196,*,*")
5394 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5397 ; slr, sl, sly, slgr, slg, slrk, slgrk
5398 (define_insn "*sub<mode>3_cconly2"
5399 [(set (reg CC_REGNUM)
5400 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5401 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5402 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5403 "s390_match_ccmode (insn, CCL3mode)"
5409 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5410 (set_attr "cpu_facility" "*,z196,*,*")
5411 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5415 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5418 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5419 (define_insn "sub<mode>3"
5420 [(set (match_operand:FP 0 "register_operand" "=f, f")
5421 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5422 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5423 (clobber (reg:CC CC_REGNUM))]
5426 s<xde><bt>r\t%0,<op1>%2
5428 [(set_attr "op_type" "<RRer>,RXE")
5429 (set_attr "type" "fsimp<mode>")])
5431 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5432 (define_insn "*sub<mode>3_cc"
5433 [(set (reg CC_REGNUM)
5434 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5435 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5436 (match_operand:FP 3 "const0_operand" "")))
5437 (set (match_operand:FP 0 "register_operand" "=f,f")
5438 (minus:FP (match_dup 1) (match_dup 2)))]
5439 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5441 s<xde><bt>r\t%0,<op1>%2
5443 [(set_attr "op_type" "<RRer>,RXE")
5444 (set_attr "type" "fsimp<mode>")])
5446 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5447 (define_insn "*sub<mode>3_cconly"
5448 [(set (reg CC_REGNUM)
5449 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5450 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5451 (match_operand:FP 3 "const0_operand" "")))
5452 (clobber (match_scratch:FP 0 "=f,f"))]
5453 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5455 s<xde><bt>r\t%0,<op1>%2
5457 [(set_attr "op_type" "<RRer>,RXE")
5458 (set_attr "type" "fsimp<mode>")])
5462 ;;- Conditional add/subtract instructions.
5466 ; add(di|si)cc instruction pattern(s).
5469 ; the following 4 patterns are used when the result of an add with
5470 ; carry is checked for an overflow condition
5472 ; op1 + op2 + c < op1
5474 ; alcr, alc, alcgr, alcg
5475 (define_insn "*add<mode>3_alc_carry1_cc"
5476 [(set (reg CC_REGNUM)
5478 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5479 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5480 (match_operand:GPR 2 "general_operand" "d,RT"))
5482 (set (match_operand:GPR 0 "register_operand" "=d,d")
5483 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5484 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5488 [(set_attr "op_type" "RRE,RXY")
5489 (set_attr "z196prop" "z196_alone,z196_alone")])
5491 ; alcr, alc, alcgr, alcg
5492 (define_insn "*add<mode>3_alc_carry1_cconly"
5493 [(set (reg CC_REGNUM)
5495 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5496 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5497 (match_operand:GPR 2 "general_operand" "d,RT"))
5499 (clobber (match_scratch:GPR 0 "=d,d"))]
5500 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5504 [(set_attr "op_type" "RRE,RXY")
5505 (set_attr "z196prop" "z196_alone,z196_alone")])
5507 ; op1 + op2 + c < op2
5509 ; alcr, alc, alcgr, alcg
5510 (define_insn "*add<mode>3_alc_carry2_cc"
5511 [(set (reg CC_REGNUM)
5513 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5514 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5515 (match_operand:GPR 2 "general_operand" "d,RT"))
5517 (set (match_operand:GPR 0 "register_operand" "=d,d")
5518 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5519 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5523 [(set_attr "op_type" "RRE,RXY")])
5525 ; alcr, alc, alcgr, alcg
5526 (define_insn "*add<mode>3_alc_carry2_cconly"
5527 [(set (reg CC_REGNUM)
5529 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5530 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5531 (match_operand:GPR 2 "general_operand" "d,RT"))
5533 (clobber (match_scratch:GPR 0 "=d,d"))]
5534 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5538 [(set_attr "op_type" "RRE,RXY")])
5540 ; alcr, alc, alcgr, alcg
5541 (define_insn "*add<mode>3_alc_cc"
5542 [(set (reg CC_REGNUM)
5544 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5545 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5546 (match_operand:GPR 2 "general_operand" "d,RT"))
5548 (set (match_operand:GPR 0 "register_operand" "=d,d")
5549 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5550 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5554 [(set_attr "op_type" "RRE,RXY")])
5556 ; alcr, alc, alcgr, alcg
5557 (define_insn "*add<mode>3_alc"
5558 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5559 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5560 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5561 (match_operand:GPR 2 "general_operand" "d,RT")))
5562 (clobber (reg:CC CC_REGNUM))]
5567 [(set_attr "op_type" "RRE,RXY")])
5569 ; slbr, slb, slbgr, slbg
5570 (define_insn "*sub<mode>3_slb_cc"
5571 [(set (reg CC_REGNUM)
5573 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5574 (match_operand:GPR 2 "general_operand" "d,RT"))
5575 (match_operand:GPR 3 "s390_slb_comparison" ""))
5577 (set (match_operand:GPR 0 "register_operand" "=d,d")
5578 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5579 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5583 [(set_attr "op_type" "RRE,RXY")
5584 (set_attr "z10prop" "z10_c,*")])
5586 ; slbr, slb, slbgr, slbg
5587 (define_insn "*sub<mode>3_slb"
5588 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5589 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5590 (match_operand:GPR 2 "general_operand" "d,RT"))
5591 (match_operand:GPR 3 "s390_slb_comparison" "")))
5592 (clobber (reg:CC CC_REGNUM))]
5597 [(set_attr "op_type" "RRE,RXY")
5598 (set_attr "z10prop" "z10_c,*")])
5600 (define_expand "add<mode>cc"
5601 [(match_operand:GPR 0 "register_operand" "")
5602 (match_operand 1 "comparison_operator" "")
5603 (match_operand:GPR 2 "register_operand" "")
5604 (match_operand:GPR 3 "const_int_operand" "")]
5606 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5607 XEXP (operands[1], 0), XEXP (operands[1], 1),
5608 operands[0], operands[2],
5609 operands[3])) FAIL; DONE;")
5612 ; scond instruction pattern(s).
5615 (define_insn_and_split "*scond<mode>"
5616 [(set (match_operand:GPR 0 "register_operand" "=&d")
5617 (match_operand:GPR 1 "s390_alc_comparison" ""))
5618 (clobber (reg:CC CC_REGNUM))]
5621 "&& reload_completed"
5622 [(set (match_dup 0) (const_int 0))
5624 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5626 (clobber (reg:CC CC_REGNUM))])]
5629 (define_insn_and_split "*scond<mode>_neg"
5630 [(set (match_operand:GPR 0 "register_operand" "=&d")
5631 (match_operand:GPR 1 "s390_slb_comparison" ""))
5632 (clobber (reg:CC CC_REGNUM))]
5635 "&& reload_completed"
5636 [(set (match_dup 0) (const_int 0))
5638 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5640 (clobber (reg:CC CC_REGNUM))])
5642 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5643 (clobber (reg:CC CC_REGNUM))])]
5647 (define_expand "cstore<mode>4"
5648 [(set (match_operand:SI 0 "register_operand" "")
5649 (match_operator:SI 1 "s390_scond_operator"
5650 [(match_operand:GPR 2 "register_operand" "")
5651 (match_operand:GPR 3 "general_operand" "")]))]
5653 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5654 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5656 (define_expand "cstorecc4"
5658 [(set (match_operand:SI 0 "register_operand" "")
5659 (match_operator:SI 1 "s390_eqne_operator"
5660 [(match_operand:CCZ1 2 "register_operand")
5661 (match_operand 3 "const0_operand")]))
5662 (clobber (reg:CC CC_REGNUM))])]
5664 "emit_insn (gen_sne (operands[0], operands[2]));
5665 if (GET_CODE (operands[1]) == EQ)
5666 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5669 (define_insn_and_split "sne"
5670 [(set (match_operand:SI 0 "register_operand" "=d")
5671 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5673 (clobber (reg:CC CC_REGNUM))]
5678 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5679 (clobber (reg:CC CC_REGNUM))])])
5683 ;; - Conditional move instructions (introduced with z196)
5686 (define_expand "mov<mode>cc"
5687 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5688 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5689 (match_operand:GPR 2 "nonimmediate_operand" "")
5690 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5692 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5693 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5695 ; locr, loc, stoc, locgr, locg, stocg
5696 (define_insn_and_split "*mov<mode>cc"
5697 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5699 (match_operator 1 "s390_comparison"
5700 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5701 (match_operand 5 "const_int_operand" "")])
5702 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5703 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5713 "&& reload_completed
5714 && MEM_P (operands[3]) && MEM_P (operands[4])"
5717 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5722 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5726 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5729 ;;- Multiply instructions.
5733 ; muldi3 instruction pattern(s).
5736 (define_insn "*muldi3_sign"
5737 [(set (match_operand:DI 0 "register_operand" "=d,d")
5738 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5739 (match_operand:DI 1 "register_operand" "0,0")))]
5744 [(set_attr "op_type" "RRE,RXY")
5745 (set_attr "type" "imuldi")])
5747 (define_insn "muldi3"
5748 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5749 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5750 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5757 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5758 (set_attr "type" "imuldi")
5759 (set_attr "cpu_facility" "*,*,*,z10")])
5762 ; mulsi3 instruction pattern(s).
5765 (define_insn "*mulsi3_sign"
5766 [(set (match_operand:SI 0 "register_operand" "=d,d")
5767 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5768 (match_operand:SI 1 "register_operand" "0,0")))]
5773 [(set_attr "op_type" "RX,RXY")
5774 (set_attr "type" "imulhi")
5775 (set_attr "cpu_facility" "*,z10")])
5777 (define_insn "mulsi3"
5778 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5779 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5780 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5788 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5789 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5790 (set_attr "cpu_facility" "*,*,*,*,z10")])
5793 ; mulsidi3 instruction pattern(s).
5796 (define_insn "mulsidi3"
5797 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5798 (mult:DI (sign_extend:DI
5799 (match_operand:SI 1 "register_operand" "%0,0,0"))
5801 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5807 [(set_attr "op_type" "RR,RX,RXY")
5808 (set_attr "type" "imulsi")
5809 (set_attr "cpu_facility" "*,*,z10")])
5812 ; umul instruction pattern(s).
5815 ; mlr, ml, mlgr, mlg
5816 (define_insn "umul<dwh><mode>3"
5817 [(set (match_operand:DW 0 "register_operand" "=d, d")
5818 (mult:DW (zero_extend:DW
5819 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5821 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5826 [(set_attr "op_type" "RRE,RXY")
5827 (set_attr "type" "imul<dwh>")])
5830 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5833 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5834 (define_insn "mul<mode>3"
5835 [(set (match_operand:FP 0 "register_operand" "=f,f")
5836 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5837 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5840 m<xdee><bt>r\t%0,<op1>%2
5842 [(set_attr "op_type" "<RRer>,RXE")
5843 (set_attr "type" "fmul<mode>")])
5845 ; madbr, maebr, maxb, madb, maeb
5846 (define_insn "fma<mode>4"
5847 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5848 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5849 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5850 (match_operand:DSF 3 "register_operand" "0,0")))]
5855 [(set_attr "op_type" "RRE,RXE")
5856 (set_attr "type" "fmadd<mode>")])
5858 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5859 (define_insn "fms<mode>4"
5860 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5861 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5862 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5863 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5868 [(set_attr "op_type" "RRE,RXE")
5869 (set_attr "type" "fmadd<mode>")])
5872 ;;- Divide and modulo instructions.
5876 ; divmoddi4 instruction pattern(s).
5879 (define_expand "divmoddi4"
5880 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5881 (div:DI (match_operand:DI 1 "register_operand" "")
5882 (match_operand:DI 2 "general_operand" "")))
5883 (set (match_operand:DI 3 "general_operand" "")
5884 (mod:DI (match_dup 1) (match_dup 2)))])
5885 (clobber (match_dup 4))]
5888 rtx insn, div_equal, mod_equal;
5890 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5891 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5893 operands[4] = gen_reg_rtx(TImode);
5894 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5896 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5897 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5899 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5900 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5905 (define_insn "divmodtidi3"
5906 [(set (match_operand:TI 0 "register_operand" "=d,d")
5910 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5911 (match_operand:DI 2 "general_operand" "d,RT")))
5913 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5918 [(set_attr "op_type" "RRE,RXY")
5919 (set_attr "type" "idiv")])
5921 (define_insn "divmodtisi3"
5922 [(set (match_operand:TI 0 "register_operand" "=d,d")
5926 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5928 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5931 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5936 [(set_attr "op_type" "RRE,RXY")
5937 (set_attr "type" "idiv")])
5940 ; udivmoddi4 instruction pattern(s).
5943 (define_expand "udivmoddi4"
5944 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5945 (udiv:DI (match_operand:DI 1 "general_operand" "")
5946 (match_operand:DI 2 "nonimmediate_operand" "")))
5947 (set (match_operand:DI 3 "general_operand" "")
5948 (umod:DI (match_dup 1) (match_dup 2)))])
5949 (clobber (match_dup 4))]
5952 rtx insn, div_equal, mod_equal, equal;
5954 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5955 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5956 equal = gen_rtx_IOR (TImode,
5957 gen_rtx_ASHIFT (TImode,
5958 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5960 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5962 operands[4] = gen_reg_rtx(TImode);
5963 emit_clobber (operands[4]);
5964 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5965 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5967 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5968 set_unique_reg_note (insn, REG_EQUAL, equal);
5970 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5971 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5973 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5974 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5979 (define_insn "udivmodtidi3"
5980 [(set (match_operand:TI 0 "register_operand" "=d,d")
5985 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5987 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5991 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5996 [(set_attr "op_type" "RRE,RXY")
5997 (set_attr "type" "idiv")])
6000 ; divmodsi4 instruction pattern(s).
6003 (define_expand "divmodsi4"
6004 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6005 (div:SI (match_operand:SI 1 "general_operand" "")
6006 (match_operand:SI 2 "nonimmediate_operand" "")))
6007 (set (match_operand:SI 3 "general_operand" "")
6008 (mod:SI (match_dup 1) (match_dup 2)))])
6009 (clobber (match_dup 4))]
6012 rtx insn, div_equal, mod_equal, equal;
6014 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6015 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6016 equal = gen_rtx_IOR (DImode,
6017 gen_rtx_ASHIFT (DImode,
6018 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6020 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6022 operands[4] = gen_reg_rtx(DImode);
6023 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6025 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6026 set_unique_reg_note (insn, REG_EQUAL, equal);
6028 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6029 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6031 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6032 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6037 (define_insn "divmoddisi3"
6038 [(set (match_operand:DI 0 "register_operand" "=d,d")
6043 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6045 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6049 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6054 [(set_attr "op_type" "RR,RX")
6055 (set_attr "type" "idiv")])
6058 ; udivsi3 and umodsi3 instruction pattern(s).
6061 (define_expand "udivmodsi4"
6062 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6063 (udiv:SI (match_operand:SI 1 "general_operand" "")
6064 (match_operand:SI 2 "nonimmediate_operand" "")))
6065 (set (match_operand:SI 3 "general_operand" "")
6066 (umod:SI (match_dup 1) (match_dup 2)))])
6067 (clobber (match_dup 4))]
6068 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6070 rtx insn, div_equal, mod_equal, equal;
6072 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6073 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6074 equal = gen_rtx_IOR (DImode,
6075 gen_rtx_ASHIFT (DImode,
6076 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6078 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6080 operands[4] = gen_reg_rtx(DImode);
6081 emit_clobber (operands[4]);
6082 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6083 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6085 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6086 set_unique_reg_note (insn, REG_EQUAL, equal);
6088 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6089 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6091 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6092 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6097 (define_insn "udivmoddisi3"
6098 [(set (match_operand:DI 0 "register_operand" "=d,d")
6103 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6105 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6109 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6110 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6114 [(set_attr "op_type" "RRE,RXY")
6115 (set_attr "type" "idiv")])
6117 (define_expand "udivsi3"
6118 [(set (match_operand:SI 0 "register_operand" "=d")
6119 (udiv:SI (match_operand:SI 1 "general_operand" "")
6120 (match_operand:SI 2 "general_operand" "")))
6121 (clobber (match_dup 3))]
6122 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6124 rtx insn, udiv_equal, umod_equal, equal;
6126 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6127 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6128 equal = gen_rtx_IOR (DImode,
6129 gen_rtx_ASHIFT (DImode,
6130 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6132 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6134 operands[3] = gen_reg_rtx (DImode);
6136 if (CONSTANT_P (operands[2]))
6138 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6140 rtx_code_label *label1 = gen_label_rtx ();
6142 operands[1] = make_safe_from (operands[1], operands[0]);
6143 emit_move_insn (operands[0], const0_rtx);
6144 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6146 emit_move_insn (operands[0], const1_rtx);
6147 emit_label (label1);
6151 operands[2] = force_reg (SImode, operands[2]);
6152 operands[2] = make_safe_from (operands[2], operands[0]);
6154 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6155 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6157 set_unique_reg_note (insn, REG_EQUAL, equal);
6159 insn = emit_move_insn (operands[0],
6160 gen_lowpart (SImode, operands[3]));
6161 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6166 rtx_code_label *label1 = gen_label_rtx ();
6167 rtx_code_label *label2 = gen_label_rtx ();
6168 rtx_code_label *label3 = gen_label_rtx ();
6170 operands[1] = force_reg (SImode, operands[1]);
6171 operands[1] = make_safe_from (operands[1], operands[0]);
6172 operands[2] = force_reg (SImode, operands[2]);
6173 operands[2] = make_safe_from (operands[2], operands[0]);
6175 emit_move_insn (operands[0], const0_rtx);
6176 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6178 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6180 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6182 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6183 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6185 set_unique_reg_note (insn, REG_EQUAL, equal);
6187 insn = emit_move_insn (operands[0],
6188 gen_lowpart (SImode, operands[3]));
6189 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6192 emit_label (label1);
6193 emit_move_insn (operands[0], operands[1]);
6195 emit_label (label2);
6196 emit_move_insn (operands[0], const1_rtx);
6197 emit_label (label3);
6199 emit_move_insn (operands[0], operands[0]);
6203 (define_expand "umodsi3"
6204 [(set (match_operand:SI 0 "register_operand" "=d")
6205 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6206 (match_operand:SI 2 "nonimmediate_operand" "")))
6207 (clobber (match_dup 3))]
6208 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6210 rtx insn, udiv_equal, umod_equal, equal;
6212 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6213 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6214 equal = gen_rtx_IOR (DImode,
6215 gen_rtx_ASHIFT (DImode,
6216 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6218 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6220 operands[3] = gen_reg_rtx (DImode);
6222 if (CONSTANT_P (operands[2]))
6224 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6226 rtx_code_label *label1 = gen_label_rtx ();
6228 operands[1] = make_safe_from (operands[1], operands[0]);
6229 emit_move_insn (operands[0], operands[1]);
6230 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6232 emit_insn (gen_abssi2 (operands[0], operands[2]));
6233 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6234 emit_label (label1);
6238 operands[2] = force_reg (SImode, operands[2]);
6239 operands[2] = make_safe_from (operands[2], operands[0]);
6241 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6242 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6244 set_unique_reg_note (insn, REG_EQUAL, equal);
6246 insn = emit_move_insn (operands[0],
6247 gen_highpart (SImode, operands[3]));
6248 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6253 rtx_code_label *label1 = gen_label_rtx ();
6254 rtx_code_label *label2 = gen_label_rtx ();
6255 rtx_code_label *label3 = gen_label_rtx ();
6257 operands[1] = force_reg (SImode, operands[1]);
6258 operands[1] = make_safe_from (operands[1], operands[0]);
6259 operands[2] = force_reg (SImode, operands[2]);
6260 operands[2] = make_safe_from (operands[2], operands[0]);
6262 emit_move_insn(operands[0], operands[1]);
6263 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6265 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6267 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6269 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6270 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6272 set_unique_reg_note (insn, REG_EQUAL, equal);
6274 insn = emit_move_insn (operands[0],
6275 gen_highpart (SImode, operands[3]));
6276 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6279 emit_label (label1);
6280 emit_move_insn (operands[0], const0_rtx);
6282 emit_label (label2);
6283 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6284 emit_label (label3);
6290 ; div(df|sf)3 instruction pattern(s).
6293 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6294 (define_insn "div<mode>3"
6295 [(set (match_operand:FP 0 "register_operand" "=f,f")
6296 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6297 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6300 d<xde><bt>r\t%0,<op1>%2
6302 [(set_attr "op_type" "<RRer>,RXE")
6303 (set_attr "type" "fdiv<mode>")])
6307 ;;- And instructions.
6310 (define_expand "and<mode>3"
6311 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6312 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6313 (match_operand:INT 2 "general_operand" "")))
6314 (clobber (reg:CC CC_REGNUM))]
6316 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6319 ; anddi3 instruction pattern(s).
6322 (define_insn "*anddi3_cc"
6323 [(set (reg CC_REGNUM)
6325 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6326 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6328 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6329 (and:DI (match_dup 1) (match_dup 2)))]
6330 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6335 risbg\t%0,%1,%s2,128+%e2,0"
6336 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6337 (set_attr "cpu_facility" "*,z196,*,z10")
6338 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6340 (define_insn "*anddi3_cconly"
6341 [(set (reg CC_REGNUM)
6343 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6344 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6346 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6348 && s390_match_ccmode(insn, CCTmode)
6349 /* Do not steal TM patterns. */
6350 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6355 risbg\t%0,%1,%s2,128+%e2,0"
6356 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6357 (set_attr "cpu_facility" "*,z196,*,z10")
6358 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6360 (define_insn "*anddi3"
6361 [(set (match_operand:DI 0 "nonimmediate_operand"
6362 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6364 (match_operand:DI 1 "nonimmediate_operand"
6365 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6366 (match_operand:DI 2 "general_operand"
6367 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6368 (clobber (reg:CC CC_REGNUM))]
6369 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6382 risbg\t%0,%1,%s2,128+%e2,0
6385 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6386 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6387 (set_attr "z10prop" "*,
6403 [(set (match_operand:DI 0 "s_operand" "")
6404 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6405 (clobber (reg:CC CC_REGNUM))]
6408 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6409 (clobber (reg:CC CC_REGNUM))])]
6410 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6412 ;; These two are what combine generates for (ashift (zero_extract)).
6413 (define_insn "*extzv_<mode>_srl"
6414 [(set (match_operand:GPR 0 "register_operand" "=d")
6415 (and:GPR (lshiftrt:GPR
6416 (match_operand:GPR 1 "register_operand" "d")
6417 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6418 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6419 (clobber (reg:CC CC_REGNUM))]
6421 /* Note that even for the SImode pattern, the rotate is always DImode. */
6422 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6423 INTVAL (operands[3]))"
6424 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6425 [(set_attr "op_type" "RIE")
6426 (set_attr "z10prop" "z10_super_E1")])
6428 (define_insn "*extzv_<mode>_sll"
6429 [(set (match_operand:GPR 0 "register_operand" "=d")
6430 (and:GPR (ashift:GPR
6431 (match_operand:GPR 1 "register_operand" "d")
6432 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6433 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6434 (clobber (reg:CC CC_REGNUM))]
6436 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6437 INTVAL (operands[3]))"
6438 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6439 [(set_attr "op_type" "RIE")
6440 (set_attr "z10prop" "z10_super_E1")])
6444 ; andsi3 instruction pattern(s).
6447 (define_insn "*andsi3_cc"
6448 [(set (reg CC_REGNUM)
6451 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6452 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6454 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6455 (and:SI (match_dup 1) (match_dup 2)))]
6456 "s390_match_ccmode(insn, CCTmode)"
6463 risbg\t%0,%1,%t2,128+%f2,0"
6464 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6465 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6466 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6467 z10_super_E1,z10_super_E1,z10_super_E1")])
6469 (define_insn "*andsi3_cconly"
6470 [(set (reg CC_REGNUM)
6473 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6474 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6476 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6477 "s390_match_ccmode(insn, CCTmode)
6478 /* Do not steal TM patterns. */
6479 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6486 risbg\t%0,%1,%t2,128+%f2,0"
6487 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6488 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6489 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6490 z10_super_E1,z10_super_E1,z10_super_E1")])
6492 (define_insn "*andsi3_zarch"
6493 [(set (match_operand:SI 0 "nonimmediate_operand"
6494 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6495 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6496 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6497 (match_operand:SI 2 "general_operand"
6498 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6499 (clobber (reg:CC CC_REGNUM))]
6500 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6511 risbg\t%0,%1,%t2,128+%f2,0
6514 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6515 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6516 (set_attr "z10prop" "*,
6529 (define_insn "*andsi3_esa"
6530 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6531 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6532 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6533 (clobber (reg:CC CC_REGNUM))]
6534 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6540 [(set_attr "op_type" "RR,RX,SI,SS")
6541 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6545 [(set (match_operand:SI 0 "s_operand" "")
6546 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6547 (clobber (reg:CC CC_REGNUM))]
6550 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6551 (clobber (reg:CC CC_REGNUM))])]
6552 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6555 ; andhi3 instruction pattern(s).
6558 (define_insn "*andhi3_zarch"
6559 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6560 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6561 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6562 (clobber (reg:CC CC_REGNUM))]
6563 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6570 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6571 (set_attr "cpu_facility" "*,z196,*,*,*")
6572 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6575 (define_insn "*andhi3_esa"
6576 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6577 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6578 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6579 (clobber (reg:CC CC_REGNUM))]
6580 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6585 [(set_attr "op_type" "RR,SI,SS")
6586 (set_attr "z10prop" "z10_super_E1,*,*")
6590 [(set (match_operand:HI 0 "s_operand" "")
6591 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6592 (clobber (reg:CC CC_REGNUM))]
6595 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6596 (clobber (reg:CC CC_REGNUM))])]
6597 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6600 ; andqi3 instruction pattern(s).
6603 (define_insn "*andqi3_zarch"
6604 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6605 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6606 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6607 (clobber (reg:CC CC_REGNUM))]
6608 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6616 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6617 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6618 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6620 (define_insn "*andqi3_esa"
6621 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6622 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6623 (match_operand:QI 2 "general_operand" "d,n,Q")))
6624 (clobber (reg:CC CC_REGNUM))]
6625 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6630 [(set_attr "op_type" "RR,SI,SS")
6631 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6634 ; Block and (NC) patterns.
6638 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6639 (and:BLK (match_dup 0)
6640 (match_operand:BLK 1 "memory_operand" "Q")))
6641 (use (match_operand 2 "const_int_operand" "n"))
6642 (clobber (reg:CC CC_REGNUM))]
6643 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6644 "nc\t%O0(%2,%R0),%S1"
6645 [(set_attr "op_type" "SS")
6646 (set_attr "z196prop" "z196_cracked")])
6649 [(set (match_operand 0 "memory_operand" "")
6651 (match_operand 1 "memory_operand" "")))
6652 (clobber (reg:CC CC_REGNUM))]
6654 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6655 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6657 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6659 (clobber (reg:CC CC_REGNUM))])]
6661 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6662 operands[0] = adjust_address (operands[0], BLKmode, 0);
6663 operands[1] = adjust_address (operands[1], BLKmode, 0);
6668 [(set (match_operand:BLK 0 "memory_operand" "")
6669 (and:BLK (match_dup 0)
6670 (match_operand:BLK 1 "memory_operand" "")))
6671 (use (match_operand 2 "const_int_operand" ""))
6672 (clobber (reg:CC CC_REGNUM))])
6674 [(set (match_operand:BLK 3 "memory_operand" "")
6675 (and:BLK (match_dup 3)
6676 (match_operand:BLK 4 "memory_operand" "")))
6677 (use (match_operand 5 "const_int_operand" ""))
6678 (clobber (reg:CC CC_REGNUM))])]
6679 "s390_offset_p (operands[0], operands[3], operands[2])
6680 && s390_offset_p (operands[1], operands[4], operands[2])
6681 && !s390_overlap_p (operands[0], operands[1],
6682 INTVAL (operands[2]) + INTVAL (operands[5]))
6683 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6685 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6687 (clobber (reg:CC CC_REGNUM))])]
6688 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6689 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6690 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6694 ;;- Bit set (inclusive or) instructions.
6697 (define_expand "ior<mode>3"
6698 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6699 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6700 (match_operand:INT 2 "general_operand" "")))
6701 (clobber (reg:CC CC_REGNUM))]
6703 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6706 ; iordi3 instruction pattern(s).
6709 (define_insn "*iordi3_cc"
6710 [(set (reg CC_REGNUM)
6711 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6712 (match_operand:DI 2 "general_operand" " d,d,RT"))
6714 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6715 (ior:DI (match_dup 1) (match_dup 2)))]
6716 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6721 [(set_attr "op_type" "RRE,RRF,RXY")
6722 (set_attr "cpu_facility" "*,z196,*")
6723 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6725 (define_insn "*iordi3_cconly"
6726 [(set (reg CC_REGNUM)
6727 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6728 (match_operand:DI 2 "general_operand" " d,d,RT"))
6730 (clobber (match_scratch:DI 0 "=d,d,d"))]
6731 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6736 [(set_attr "op_type" "RRE,RRF,RXY")
6737 (set_attr "cpu_facility" "*,z196,*")
6738 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6740 (define_insn "*iordi3"
6741 [(set (match_operand:DI 0 "nonimmediate_operand"
6742 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6743 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6744 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6745 (match_operand:DI 2 "general_operand"
6746 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6747 (clobber (reg:CC CC_REGNUM))]
6748 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6761 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6762 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6763 (set_attr "z10prop" "z10_super_E1,
6776 [(set (match_operand:DI 0 "s_operand" "")
6777 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6778 (clobber (reg:CC CC_REGNUM))]
6781 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6782 (clobber (reg:CC CC_REGNUM))])]
6783 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6786 ; iorsi3 instruction pattern(s).
6789 (define_insn "*iorsi3_cc"
6790 [(set (reg CC_REGNUM)
6791 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6792 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6794 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6795 (ior:SI (match_dup 1) (match_dup 2)))]
6796 "s390_match_ccmode(insn, CCTmode)"
6803 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6804 (set_attr "cpu_facility" "*,*,z196,*,*")
6805 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6807 (define_insn "*iorsi3_cconly"
6808 [(set (reg CC_REGNUM)
6809 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6810 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6812 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6813 "s390_match_ccmode(insn, CCTmode)"
6820 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6821 (set_attr "cpu_facility" "*,*,z196,*,*")
6822 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6824 (define_insn "*iorsi3_zarch"
6825 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6826 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6827 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6828 (clobber (reg:CC CC_REGNUM))]
6829 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6840 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6841 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6842 (set_attr "z10prop" "z10_super_E1,
6852 (define_insn "*iorsi3_esa"
6853 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6854 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6855 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6856 (clobber (reg:CC CC_REGNUM))]
6857 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6863 [(set_attr "op_type" "RR,RX,SI,SS")
6864 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6867 [(set (match_operand:SI 0 "s_operand" "")
6868 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6869 (clobber (reg:CC CC_REGNUM))]
6872 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6873 (clobber (reg:CC CC_REGNUM))])]
6874 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6877 ; iorhi3 instruction pattern(s).
6880 (define_insn "*iorhi3_zarch"
6881 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6882 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6883 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6884 (clobber (reg:CC CC_REGNUM))]
6885 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6892 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6893 (set_attr "cpu_facility" "*,z196,*,*,*")
6894 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6896 (define_insn "*iorhi3_esa"
6897 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6898 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6899 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6900 (clobber (reg:CC CC_REGNUM))]
6901 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6906 [(set_attr "op_type" "RR,SI,SS")
6907 (set_attr "z10prop" "z10_super_E1,*,*")])
6910 [(set (match_operand:HI 0 "s_operand" "")
6911 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6912 (clobber (reg:CC CC_REGNUM))]
6915 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6916 (clobber (reg:CC CC_REGNUM))])]
6917 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6920 ; iorqi3 instruction pattern(s).
6923 (define_insn "*iorqi3_zarch"
6924 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6925 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6926 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6927 (clobber (reg:CC CC_REGNUM))]
6928 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6936 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6937 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6938 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6939 z10_super,z10_super,*")])
6941 (define_insn "*iorqi3_esa"
6942 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6943 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6944 (match_operand:QI 2 "general_operand" "d,n,Q")))
6945 (clobber (reg:CC CC_REGNUM))]
6946 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6951 [(set_attr "op_type" "RR,SI,SS")
6952 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6955 ; Block inclusive or (OC) patterns.
6959 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6960 (ior:BLK (match_dup 0)
6961 (match_operand:BLK 1 "memory_operand" "Q")))
6962 (use (match_operand 2 "const_int_operand" "n"))
6963 (clobber (reg:CC CC_REGNUM))]
6964 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6965 "oc\t%O0(%2,%R0),%S1"
6966 [(set_attr "op_type" "SS")
6967 (set_attr "z196prop" "z196_cracked")])
6970 [(set (match_operand 0 "memory_operand" "")
6972 (match_operand 1 "memory_operand" "")))
6973 (clobber (reg:CC CC_REGNUM))]
6975 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6976 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6978 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6980 (clobber (reg:CC CC_REGNUM))])]
6982 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6983 operands[0] = adjust_address (operands[0], BLKmode, 0);
6984 operands[1] = adjust_address (operands[1], BLKmode, 0);
6989 [(set (match_operand:BLK 0 "memory_operand" "")
6990 (ior:BLK (match_dup 0)
6991 (match_operand:BLK 1 "memory_operand" "")))
6992 (use (match_operand 2 "const_int_operand" ""))
6993 (clobber (reg:CC CC_REGNUM))])
6995 [(set (match_operand:BLK 3 "memory_operand" "")
6996 (ior:BLK (match_dup 3)
6997 (match_operand:BLK 4 "memory_operand" "")))
6998 (use (match_operand 5 "const_int_operand" ""))
6999 (clobber (reg:CC CC_REGNUM))])]
7000 "s390_offset_p (operands[0], operands[3], operands[2])
7001 && s390_offset_p (operands[1], operands[4], operands[2])
7002 && !s390_overlap_p (operands[0], operands[1],
7003 INTVAL (operands[2]) + INTVAL (operands[5]))
7004 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7006 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7008 (clobber (reg:CC CC_REGNUM))])]
7009 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7010 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7011 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7015 ;;- Xor instructions.
7018 (define_expand "xor<mode>3"
7019 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7020 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7021 (match_operand:INT 2 "general_operand" "")))
7022 (clobber (reg:CC CC_REGNUM))]
7024 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7026 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7027 ; simplifications. So its better to have something matching.
7029 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7030 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7033 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7034 (clobber (reg:CC CC_REGNUM))])]
7036 operands[2] = constm1_rtx;
7037 if (!s390_logical_operator_ok_p (operands))
7042 ; xordi3 instruction pattern(s).
7045 (define_insn "*xordi3_cc"
7046 [(set (reg CC_REGNUM)
7047 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7048 (match_operand:DI 2 "general_operand" " d,d,RT"))
7050 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7051 (xor:DI (match_dup 1) (match_dup 2)))]
7052 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7057 [(set_attr "op_type" "RRE,RRF,RXY")
7058 (set_attr "cpu_facility" "*,z196,*")
7059 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7061 (define_insn "*xordi3_cconly"
7062 [(set (reg CC_REGNUM)
7063 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7064 (match_operand:DI 2 "general_operand" " d,d,RT"))
7066 (clobber (match_scratch:DI 0 "=d,d, d"))]
7067 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7072 [(set_attr "op_type" "RRE,RRF,RXY")
7073 (set_attr "cpu_facility" "*,z196,*")
7074 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7076 (define_insn "*xordi3"
7077 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7078 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7079 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7080 (clobber (reg:CC CC_REGNUM))]
7081 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7090 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7091 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7092 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7093 *,z10_super_E1,*,*")])
7096 [(set (match_operand:DI 0 "s_operand" "")
7097 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7098 (clobber (reg:CC CC_REGNUM))]
7101 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7102 (clobber (reg:CC CC_REGNUM))])]
7103 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7106 ; xorsi3 instruction pattern(s).
7109 (define_insn "*xorsi3_cc"
7110 [(set (reg CC_REGNUM)
7111 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7112 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7114 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7115 (xor:SI (match_dup 1) (match_dup 2)))]
7116 "s390_match_ccmode(insn, CCTmode)"
7123 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7124 (set_attr "cpu_facility" "*,*,z196,*,*")
7125 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7126 z10_super_E1,z10_super_E1")])
7128 (define_insn "*xorsi3_cconly"
7129 [(set (reg CC_REGNUM)
7130 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7131 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7133 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7134 "s390_match_ccmode(insn, CCTmode)"
7141 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7142 (set_attr "cpu_facility" "*,*,z196,*,*")
7143 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7144 z10_super_E1,z10_super_E1")])
7146 (define_insn "*xorsi3"
7147 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7148 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7149 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7150 (clobber (reg:CC CC_REGNUM))]
7151 "s390_logical_operator_ok_p (operands)"
7160 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7161 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7162 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7163 z10_super_E1,z10_super_E1,*,*")])
7166 [(set (match_operand:SI 0 "s_operand" "")
7167 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7168 (clobber (reg:CC CC_REGNUM))]
7171 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7172 (clobber (reg:CC CC_REGNUM))])]
7173 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7176 ; xorhi3 instruction pattern(s).
7179 (define_insn "*xorhi3"
7180 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7181 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7182 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7183 (clobber (reg:CC CC_REGNUM))]
7184 "s390_logical_operator_ok_p (operands)"
7191 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7192 (set_attr "cpu_facility" "*,*,z196,*,*")
7193 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7196 [(set (match_operand:HI 0 "s_operand" "")
7197 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7198 (clobber (reg:CC CC_REGNUM))]
7201 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7202 (clobber (reg:CC CC_REGNUM))])]
7203 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7206 ; xorqi3 instruction pattern(s).
7209 (define_insn "*xorqi3"
7210 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7211 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7212 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7213 (clobber (reg:CC CC_REGNUM))]
7214 "s390_logical_operator_ok_p (operands)"
7222 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7223 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7224 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7228 ; Block exclusive or (XC) patterns.
7232 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7233 (xor:BLK (match_dup 0)
7234 (match_operand:BLK 1 "memory_operand" "Q")))
7235 (use (match_operand 2 "const_int_operand" "n"))
7236 (clobber (reg:CC CC_REGNUM))]
7237 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7238 "xc\t%O0(%2,%R0),%S1"
7239 [(set_attr "op_type" "SS")])
7242 [(set (match_operand 0 "memory_operand" "")
7244 (match_operand 1 "memory_operand" "")))
7245 (clobber (reg:CC CC_REGNUM))]
7247 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7248 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7250 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7252 (clobber (reg:CC CC_REGNUM))])]
7254 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7255 operands[0] = adjust_address (operands[0], BLKmode, 0);
7256 operands[1] = adjust_address (operands[1], BLKmode, 0);
7261 [(set (match_operand:BLK 0 "memory_operand" "")
7262 (xor:BLK (match_dup 0)
7263 (match_operand:BLK 1 "memory_operand" "")))
7264 (use (match_operand 2 "const_int_operand" ""))
7265 (clobber (reg:CC CC_REGNUM))])
7267 [(set (match_operand:BLK 3 "memory_operand" "")
7268 (xor:BLK (match_dup 3)
7269 (match_operand:BLK 4 "memory_operand" "")))
7270 (use (match_operand 5 "const_int_operand" ""))
7271 (clobber (reg:CC CC_REGNUM))])]
7272 "s390_offset_p (operands[0], operands[3], operands[2])
7273 && s390_offset_p (operands[1], operands[4], operands[2])
7274 && !s390_overlap_p (operands[0], operands[1],
7275 INTVAL (operands[2]) + INTVAL (operands[5]))
7276 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7278 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7280 (clobber (reg:CC CC_REGNUM))])]
7281 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7282 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7283 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7286 ; Block xor (XC) patterns with src == dest.
7289 (define_insn "*xc_zero"
7290 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7292 (use (match_operand 1 "const_int_operand" "n"))
7293 (clobber (reg:CC CC_REGNUM))]
7294 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7295 "xc\t%O0(%1,%R0),%S0"
7296 [(set_attr "op_type" "SS")
7297 (set_attr "z196prop" "z196_cracked")])
7301 [(set (match_operand:BLK 0 "memory_operand" "")
7303 (use (match_operand 1 "const_int_operand" ""))
7304 (clobber (reg:CC CC_REGNUM))])
7306 [(set (match_operand:BLK 2 "memory_operand" "")
7308 (use (match_operand 3 "const_int_operand" ""))
7309 (clobber (reg:CC CC_REGNUM))])]
7310 "s390_offset_p (operands[0], operands[2], operands[1])
7311 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7313 [(set (match_dup 4) (const_int 0))
7315 (clobber (reg:CC CC_REGNUM))])]
7316 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7317 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7321 ;;- Negate instructions.
7325 ; neg(di|si)2 instruction pattern(s).
7328 (define_expand "neg<mode>2"
7330 [(set (match_operand:DSI 0 "register_operand" "=d")
7331 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7332 (clobber (reg:CC CC_REGNUM))])]
7336 (define_insn "*negdi2_sign_cc"
7337 [(set (reg CC_REGNUM)
7338 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7339 (match_operand:SI 1 "register_operand" "d") 0)
7340 (const_int 32)) (const_int 32)))
7342 (set (match_operand:DI 0 "register_operand" "=d")
7343 (neg:DI (sign_extend:DI (match_dup 1))))]
7344 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7346 [(set_attr "op_type" "RRE")
7347 (set_attr "z10prop" "z10_c")])
7349 (define_insn "*negdi2_sign"
7350 [(set (match_operand:DI 0 "register_operand" "=d")
7351 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7352 (clobber (reg:CC CC_REGNUM))]
7355 [(set_attr "op_type" "RRE")
7356 (set_attr "z10prop" "z10_c")])
7359 (define_insn "*neg<mode>2_cc"
7360 [(set (reg CC_REGNUM)
7361 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7363 (set (match_operand:GPR 0 "register_operand" "=d")
7364 (neg:GPR (match_dup 1)))]
7365 "s390_match_ccmode (insn, CCAmode)"
7367 [(set_attr "op_type" "RR<E>")
7368 (set_attr "z10prop" "z10_super_c_E1")])
7371 (define_insn "*neg<mode>2_cconly"
7372 [(set (reg CC_REGNUM)
7373 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7375 (clobber (match_scratch:GPR 0 "=d"))]
7376 "s390_match_ccmode (insn, CCAmode)"
7378 [(set_attr "op_type" "RR<E>")
7379 (set_attr "z10prop" "z10_super_c_E1")])
7382 (define_insn "*neg<mode>2"
7383 [(set (match_operand:GPR 0 "register_operand" "=d")
7384 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7385 (clobber (reg:CC CC_REGNUM))]
7388 [(set_attr "op_type" "RR<E>")
7389 (set_attr "z10prop" "z10_super_c_E1")])
7391 (define_insn "*negdi2_31"
7392 [(set (match_operand:DI 0 "register_operand" "=d")
7393 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7394 (clobber (reg:CC CC_REGNUM))]
7398 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7400 ; Doing the twos complement separately on the SImode parts does an
7401 ; unwanted +1 on the high part which needs to be subtracted afterwards
7402 ; ... unless the +1 on the low part created an overflow.
7405 [(set (match_operand:DI 0 "register_operand" "")
7406 (neg:DI (match_operand:DI 1 "register_operand" "")))
7407 (clobber (reg:CC CC_REGNUM))]
7409 && (REGNO (operands[0]) == REGNO (operands[1])
7410 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7411 && reload_completed"
7413 [(set (match_dup 2) (neg:SI (match_dup 3)))
7414 (clobber (reg:CC CC_REGNUM))])
7416 [(set (reg:CCAP CC_REGNUM)
7417 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7418 (set (match_dup 4) (neg:SI (match_dup 5)))])
7420 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7422 (label_ref (match_dup 6))))
7424 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7425 (clobber (reg:CC CC_REGNUM))])
7427 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7428 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7429 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7430 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7431 operands[6] = gen_label_rtx ();")
7433 ; Like above but first make a copy of the low part of the src operand
7434 ; since it might overlap with the high part of the destination.
7437 [(set (match_operand:DI 0 "register_operand" "")
7438 (neg:DI (match_operand:DI 1 "register_operand" "")))
7439 (clobber (reg:CC CC_REGNUM))]
7441 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7442 && reload_completed"
7443 [; Make a backup of op5 first
7444 (set (match_dup 4) (match_dup 5))
7445 ; Setting op2 here might clobber op5
7447 [(set (match_dup 2) (neg:SI (match_dup 3)))
7448 (clobber (reg:CC CC_REGNUM))])
7450 [(set (reg:CCAP CC_REGNUM)
7451 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7452 (set (match_dup 4) (neg:SI (match_dup 4)))])
7454 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7456 (label_ref (match_dup 6))))
7458 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7459 (clobber (reg:CC CC_REGNUM))])
7461 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7462 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7463 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7464 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7465 operands[6] = gen_label_rtx ();")
7468 ; neg(df|sf)2 instruction pattern(s).
7471 (define_expand "neg<mode>2"
7473 [(set (match_operand:BFP 0 "register_operand" "=f")
7474 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7475 (clobber (reg:CC CC_REGNUM))])]
7479 ; lcxbr, lcdbr, lcebr
7480 (define_insn "*neg<mode>2_cc"
7481 [(set (reg CC_REGNUM)
7482 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7483 (match_operand:BFP 2 "const0_operand" "")))
7484 (set (match_operand:BFP 0 "register_operand" "=f")
7485 (neg:BFP (match_dup 1)))]
7486 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7488 [(set_attr "op_type" "RRE")
7489 (set_attr "type" "fsimp<mode>")])
7491 ; lcxbr, lcdbr, lcebr
7492 (define_insn "*neg<mode>2_cconly"
7493 [(set (reg CC_REGNUM)
7494 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7495 (match_operand:BFP 2 "const0_operand" "")))
7496 (clobber (match_scratch:BFP 0 "=f"))]
7497 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7499 [(set_attr "op_type" "RRE")
7500 (set_attr "type" "fsimp<mode>")])
7503 (define_insn "*neg<mode>2_nocc"
7504 [(set (match_operand:FP 0 "register_operand" "=f")
7505 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7508 [(set_attr "op_type" "RRE")
7509 (set_attr "type" "fsimp<mode>")])
7511 ; lcxbr, lcdbr, lcebr
7512 (define_insn "*neg<mode>2"
7513 [(set (match_operand:BFP 0 "register_operand" "=f")
7514 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7515 (clobber (reg:CC CC_REGNUM))]
7518 [(set_attr "op_type" "RRE")
7519 (set_attr "type" "fsimp<mode>")])
7523 ;;- Absolute value instructions.
7527 ; abs(di|si)2 instruction pattern(s).
7530 (define_insn "*absdi2_sign_cc"
7531 [(set (reg CC_REGNUM)
7532 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7533 (match_operand:SI 1 "register_operand" "d") 0)
7534 (const_int 32)) (const_int 32)))
7536 (set (match_operand:DI 0 "register_operand" "=d")
7537 (abs:DI (sign_extend:DI (match_dup 1))))]
7538 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7540 [(set_attr "op_type" "RRE")
7541 (set_attr "z10prop" "z10_c")])
7543 (define_insn "*absdi2_sign"
7544 [(set (match_operand:DI 0 "register_operand" "=d")
7545 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7546 (clobber (reg:CC CC_REGNUM))]
7549 [(set_attr "op_type" "RRE")
7550 (set_attr "z10prop" "z10_c")])
7553 (define_insn "*abs<mode>2_cc"
7554 [(set (reg CC_REGNUM)
7555 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7557 (set (match_operand:GPR 0 "register_operand" "=d")
7558 (abs:GPR (match_dup 1)))]
7559 "s390_match_ccmode (insn, CCAmode)"
7561 [(set_attr "op_type" "RR<E>")
7562 (set_attr "z10prop" "z10_c")])
7565 (define_insn "*abs<mode>2_cconly"
7566 [(set (reg CC_REGNUM)
7567 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7569 (clobber (match_scratch:GPR 0 "=d"))]
7570 "s390_match_ccmode (insn, CCAmode)"
7572 [(set_attr "op_type" "RR<E>")
7573 (set_attr "z10prop" "z10_c")])
7576 (define_insn "abs<mode>2"
7577 [(set (match_operand:GPR 0 "register_operand" "=d")
7578 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7579 (clobber (reg:CC CC_REGNUM))]
7582 [(set_attr "op_type" "RR<E>")
7583 (set_attr "z10prop" "z10_c")])
7586 ; abs(df|sf)2 instruction pattern(s).
7589 (define_expand "abs<mode>2"
7591 [(set (match_operand:BFP 0 "register_operand" "=f")
7592 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7593 (clobber (reg:CC CC_REGNUM))])]
7597 ; lpxbr, lpdbr, lpebr
7598 (define_insn "*abs<mode>2_cc"
7599 [(set (reg CC_REGNUM)
7600 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7601 (match_operand:BFP 2 "const0_operand" "")))
7602 (set (match_operand:BFP 0 "register_operand" "=f")
7603 (abs:BFP (match_dup 1)))]
7604 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7606 [(set_attr "op_type" "RRE")
7607 (set_attr "type" "fsimp<mode>")])
7609 ; lpxbr, lpdbr, lpebr
7610 (define_insn "*abs<mode>2_cconly"
7611 [(set (reg CC_REGNUM)
7612 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7613 (match_operand:BFP 2 "const0_operand" "")))
7614 (clobber (match_scratch:BFP 0 "=f"))]
7615 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7617 [(set_attr "op_type" "RRE")
7618 (set_attr "type" "fsimp<mode>")])
7621 (define_insn "*abs<mode>2_nocc"
7622 [(set (match_operand:FP 0 "register_operand" "=f")
7623 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7626 [(set_attr "op_type" "RRE")
7627 (set_attr "type" "fsimp<mode>")])
7629 ; lpxbr, lpdbr, lpebr
7630 (define_insn "*abs<mode>2"
7631 [(set (match_operand:BFP 0 "register_operand" "=f")
7632 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7633 (clobber (reg:CC CC_REGNUM))]
7636 [(set_attr "op_type" "RRE")
7637 (set_attr "type" "fsimp<mode>")])
7641 ;;- Negated absolute value instructions
7648 (define_insn "*negabsdi2_sign_cc"
7649 [(set (reg CC_REGNUM)
7650 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7651 (match_operand:SI 1 "register_operand" "d") 0)
7652 (const_int 32)) (const_int 32))))
7654 (set (match_operand:DI 0 "register_operand" "=d")
7655 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7656 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7658 [(set_attr "op_type" "RRE")
7659 (set_attr "z10prop" "z10_c")])
7661 (define_insn "*negabsdi2_sign"
7662 [(set (match_operand:DI 0 "register_operand" "=d")
7663 (neg:DI (abs:DI (sign_extend:DI
7664 (match_operand:SI 1 "register_operand" "d")))))
7665 (clobber (reg:CC CC_REGNUM))]
7668 [(set_attr "op_type" "RRE")
7669 (set_attr "z10prop" "z10_c")])
7672 (define_insn "*negabs<mode>2_cc"
7673 [(set (reg CC_REGNUM)
7674 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7676 (set (match_operand:GPR 0 "register_operand" "=d")
7677 (neg:GPR (abs:GPR (match_dup 1))))]
7678 "s390_match_ccmode (insn, CCAmode)"
7680 [(set_attr "op_type" "RR<E>")
7681 (set_attr "z10prop" "z10_c")])
7684 (define_insn "*negabs<mode>2_cconly"
7685 [(set (reg CC_REGNUM)
7686 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7688 (clobber (match_scratch:GPR 0 "=d"))]
7689 "s390_match_ccmode (insn, CCAmode)"
7691 [(set_attr "op_type" "RR<E>")
7692 (set_attr "z10prop" "z10_c")])
7695 (define_insn "*negabs<mode>2"
7696 [(set (match_operand:GPR 0 "register_operand" "=d")
7697 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7698 (clobber (reg:CC CC_REGNUM))]
7701 [(set_attr "op_type" "RR<E>")
7702 (set_attr "z10prop" "z10_c")])
7708 ; lnxbr, lndbr, lnebr
7709 (define_insn "*negabs<mode>2_cc"
7710 [(set (reg CC_REGNUM)
7711 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7712 (match_operand:BFP 2 "const0_operand" "")))
7713 (set (match_operand:BFP 0 "register_operand" "=f")
7714 (neg:BFP (abs:BFP (match_dup 1))))]
7715 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7717 [(set_attr "op_type" "RRE")
7718 (set_attr "type" "fsimp<mode>")])
7720 ; lnxbr, lndbr, lnebr
7721 (define_insn "*negabs<mode>2_cconly"
7722 [(set (reg CC_REGNUM)
7723 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7724 (match_operand:BFP 2 "const0_operand" "")))
7725 (clobber (match_scratch:BFP 0 "=f"))]
7726 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7728 [(set_attr "op_type" "RRE")
7729 (set_attr "type" "fsimp<mode>")])
7732 (define_insn "*negabs<mode>2_nocc"
7733 [(set (match_operand:FP 0 "register_operand" "=f")
7734 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7737 [(set_attr "op_type" "RRE")
7738 (set_attr "type" "fsimp<mode>")])
7740 ; lnxbr, lndbr, lnebr
7741 (define_insn "*negabs<mode>2"
7742 [(set (match_operand:BFP 0 "register_operand" "=f")
7743 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7744 (clobber (reg:CC CC_REGNUM))]
7747 [(set_attr "op_type" "RRE")
7748 (set_attr "type" "fsimp<mode>")])
7751 ;;- Square root instructions.
7755 ; sqrt(df|sf)2 instruction pattern(s).
7758 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7759 (define_insn "sqrt<mode>2"
7760 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7761 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7766 [(set_attr "op_type" "RRE,RXE")
7767 (set_attr "type" "fsqrt<mode>")])
7771 ;;- One complement instructions.
7775 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7778 (define_expand "one_cmpl<mode>2"
7780 [(set (match_operand:INT 0 "register_operand" "")
7781 (xor:INT (match_operand:INT 1 "register_operand" "")
7783 (clobber (reg:CC CC_REGNUM))])]
7789 ;; Find leftmost bit instructions.
7792 (define_expand "clzdi2"
7793 [(set (match_operand:DI 0 "register_operand" "=d")
7794 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7795 "TARGET_EXTIMM && TARGET_ZARCH"
7797 rtx insn, clz_equal;
7798 rtx wide_reg = gen_reg_rtx (TImode);
7799 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7801 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7803 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7805 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7806 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7811 (define_insn "clztidi2"
7812 [(set (match_operand:TI 0 "register_operand" "=d")
7816 (xor:DI (match_operand:DI 1 "register_operand" "d")
7817 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7818 (subreg:SI (clz:DI (match_dup 1)) 4))))
7821 (zero_extend:TI (clz:DI (match_dup 1)))))
7822 (clobber (reg:CC CC_REGNUM))]
7823 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7824 == (unsigned HOST_WIDE_INT) 1 << 63
7825 && TARGET_EXTIMM && TARGET_ZARCH"
7827 [(set_attr "op_type" "RRE")])
7831 ;;- Rotate instructions.
7835 ; rotl(di|si)3 instruction pattern(s).
7839 (define_insn "rotl<mode>3"
7840 [(set (match_operand:GPR 0 "register_operand" "=d")
7841 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7842 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7845 [(set_attr "op_type" "RSE")
7846 (set_attr "atype" "reg")
7847 (set_attr "z10prop" "z10_super_E1")])
7850 (define_insn "*rotl<mode>3_and"
7851 [(set (match_operand:GPR 0 "register_operand" "=d")
7852 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7853 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7854 (match_operand:SI 3 "const_int_operand" "n"))))]
7855 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7857 [(set_attr "op_type" "RSE")
7858 (set_attr "atype" "reg")
7859 (set_attr "z10prop" "z10_super_E1")])
7863 ;;- Shift instructions.
7867 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7868 ; Left shifts and logical right shifts
7870 (define_expand "<shift><mode>3"
7871 [(set (match_operand:DSI 0 "register_operand" "")
7872 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7873 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7878 (define_insn "*<shift>di3_31"
7879 [(set (match_operand:DI 0 "register_operand" "=d")
7880 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7881 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7884 [(set_attr "op_type" "RS")
7885 (set_attr "atype" "reg")
7886 (set_attr "z196prop" "z196_cracked")])
7888 ; sll, srl, sllg, srlg, sllk, srlk
7889 (define_insn "*<shift><mode>3"
7890 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7891 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7892 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7895 s<lr>l<g>\t%0,<1>%Y2
7896 s<lr>l<gk>\t%0,%1,%Y2"
7897 [(set_attr "op_type" "RS<E>,RSY")
7898 (set_attr "atype" "reg,reg")
7899 (set_attr "cpu_facility" "*,z196")
7900 (set_attr "z10prop" "z10_super_E1,*")])
7903 (define_insn "*<shift>di3_31_and"
7904 [(set (match_operand:DI 0 "register_operand" "=d")
7905 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7906 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7907 (match_operand:SI 3 "const_int_operand" "n"))))]
7908 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7910 [(set_attr "op_type" "RS")
7911 (set_attr "atype" "reg")])
7913 ; sll, srl, sllg, srlg, sllk, srlk
7914 (define_insn "*<shift><mode>3_and"
7915 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7916 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7917 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7918 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7919 "(INTVAL (operands[3]) & 63) == 63"
7921 s<lr>l<g>\t%0,<1>%Y2
7922 s<lr>l<gk>\t%0,%1,%Y2"
7923 [(set_attr "op_type" "RS<E>,RSY")
7924 (set_attr "atype" "reg,reg")
7925 (set_attr "cpu_facility" "*,z196")
7926 (set_attr "z10prop" "z10_super_E1,*")])
7929 ; ashr(di|si)3 instruction pattern(s).
7930 ; Arithmetic right shifts
7932 (define_expand "ashr<mode>3"
7934 [(set (match_operand:DSI 0 "register_operand" "")
7935 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7936 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7937 (clobber (reg:CC CC_REGNUM))])]
7941 (define_insn "*ashrdi3_cc_31"
7942 [(set (reg CC_REGNUM)
7943 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7944 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7946 (set (match_operand:DI 0 "register_operand" "=d")
7947 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7948 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7950 [(set_attr "op_type" "RS")
7951 (set_attr "atype" "reg")])
7953 (define_insn "*ashrdi3_cconly_31"
7954 [(set (reg CC_REGNUM)
7955 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7956 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7958 (clobber (match_scratch:DI 0 "=d"))]
7959 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7961 [(set_attr "op_type" "RS")
7962 (set_attr "atype" "reg")])
7964 (define_insn "*ashrdi3_31"
7965 [(set (match_operand:DI 0 "register_operand" "=d")
7966 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7967 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7968 (clobber (reg:CC CC_REGNUM))]
7971 [(set_attr "op_type" "RS")
7972 (set_attr "atype" "reg")])
7975 (define_insn "*ashr<mode>3_cc"
7976 [(set (reg CC_REGNUM)
7977 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7978 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7980 (set (match_operand:GPR 0 "register_operand" "=d,d")
7981 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7982 "s390_match_ccmode(insn, CCSmode)"
7986 [(set_attr "op_type" "RS<E>,RSY")
7987 (set_attr "atype" "reg,reg")
7988 (set_attr "cpu_facility" "*,z196")
7989 (set_attr "z10prop" "z10_super_E1,*")])
7992 (define_insn "*ashr<mode>3_cconly"
7993 [(set (reg CC_REGNUM)
7994 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7995 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7997 (clobber (match_scratch:GPR 0 "=d,d"))]
7998 "s390_match_ccmode(insn, CCSmode)"
8002 [(set_attr "op_type" "RS<E>,RSY")
8003 (set_attr "atype" "reg,reg")
8004 (set_attr "cpu_facility" "*,z196")
8005 (set_attr "z10prop" "z10_super_E1,*")])
8008 (define_insn "*ashr<mode>3"
8009 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8010 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8011 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8012 (clobber (reg:CC CC_REGNUM))]
8017 [(set_attr "op_type" "RS<E>,RSY")
8018 (set_attr "atype" "reg,reg")
8019 (set_attr "cpu_facility" "*,z196")
8020 (set_attr "z10prop" "z10_super_E1,*")])
8023 ; shift pattern with implicit ANDs
8025 (define_insn "*ashrdi3_cc_31_and"
8026 [(set (reg CC_REGNUM)
8027 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8028 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8029 (match_operand:SI 3 "const_int_operand" "n")))
8031 (set (match_operand:DI 0 "register_operand" "=d")
8032 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8033 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8034 && (INTVAL (operands[3]) & 63) == 63"
8036 [(set_attr "op_type" "RS")
8037 (set_attr "atype" "reg")])
8039 (define_insn "*ashrdi3_cconly_31_and"
8040 [(set (reg CC_REGNUM)
8041 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8042 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8043 (match_operand:SI 3 "const_int_operand" "n")))
8045 (clobber (match_scratch:DI 0 "=d"))]
8046 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8047 && (INTVAL (operands[3]) & 63) == 63"
8049 [(set_attr "op_type" "RS")
8050 (set_attr "atype" "reg")])
8052 (define_insn "*ashrdi3_31_and"
8053 [(set (match_operand:DI 0 "register_operand" "=d")
8054 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8055 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8056 (match_operand:SI 3 "const_int_operand" "n"))))
8057 (clobber (reg:CC CC_REGNUM))]
8058 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8060 [(set_attr "op_type" "RS")
8061 (set_attr "atype" "reg")])
8064 (define_insn "*ashr<mode>3_cc_and"
8065 [(set (reg CC_REGNUM)
8066 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8067 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8068 (match_operand:SI 3 "const_int_operand" "n,n")))
8070 (set (match_operand:GPR 0 "register_operand" "=d,d")
8071 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8072 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8076 [(set_attr "op_type" "RS<E>,RSY")
8077 (set_attr "atype" "reg,reg")
8078 (set_attr "cpu_facility" "*,z196")
8079 (set_attr "z10prop" "z10_super_E1,*")])
8082 (define_insn "*ashr<mode>3_cconly_and"
8083 [(set (reg CC_REGNUM)
8084 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8085 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8086 (match_operand:SI 3 "const_int_operand" "n,n")))
8088 (clobber (match_scratch:GPR 0 "=d,d"))]
8089 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8093 [(set_attr "op_type" "RS<E>,RSY")
8094 (set_attr "atype" "reg,reg")
8095 (set_attr "cpu_facility" "*,z196")
8096 (set_attr "z10prop" "z10_super_E1,*")])
8099 (define_insn "*ashr<mode>3_and"
8100 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8101 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8102 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8103 (match_operand:SI 3 "const_int_operand" "n,n"))))
8104 (clobber (reg:CC CC_REGNUM))]
8105 "(INTVAL (operands[3]) & 63) == 63"
8109 [(set_attr "op_type" "RS<E>,RSY")
8110 (set_attr "atype" "reg,reg")
8111 (set_attr "cpu_facility" "*,z196")
8112 (set_attr "z10prop" "z10_super_E1,*")])
8116 ;; Branch instruction patterns.
8119 (define_expand "cbranch<mode>4"
8121 (if_then_else (match_operator 0 "comparison_operator"
8122 [(match_operand:GPR 1 "register_operand" "")
8123 (match_operand:GPR 2 "general_operand" "")])
8124 (label_ref (match_operand 3 "" ""))
8127 "s390_emit_jump (operands[3],
8128 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8131 (define_expand "cbranch<mode>4"
8133 (if_then_else (match_operator 0 "comparison_operator"
8134 [(match_operand:FP 1 "register_operand" "")
8135 (match_operand:FP 2 "general_operand" "")])
8136 (label_ref (match_operand 3 "" ""))
8139 "s390_emit_jump (operands[3],
8140 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8143 (define_expand "cbranchcc4"
8145 (if_then_else (match_operator 0 "s390_comparison"
8146 [(match_operand 1 "cc_reg_operand" "")
8147 (match_operand 2 "const_int_operand" "")])
8148 (label_ref (match_operand 3 "" ""))
8155 ;;- Conditional jump instructions.
8158 (define_insn "*cjump_64"
8161 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8162 (match_operand 2 "const_int_operand" "")])
8163 (label_ref (match_operand 0 "" ""))
8167 if (get_attr_length (insn) == 4)
8170 return "jg%C1\t%l0";
8172 [(set_attr "op_type" "RI")
8173 (set_attr "type" "branch")
8174 (set (attr "length")
8175 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8176 (const_int 4) (const_int 6)))])
8178 (define_insn "*cjump_31"
8181 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8182 (match_operand 2 "const_int_operand" "")])
8183 (label_ref (match_operand 0 "" ""))
8187 gcc_assert (get_attr_length (insn) == 4);
8190 [(set_attr "op_type" "RI")
8191 (set_attr "type" "branch")
8192 (set (attr "length")
8193 (if_then_else (not (match_test "flag_pic"))
8194 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8195 (const_int 4) (const_int 6))
8196 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8197 (const_int 4) (const_int 8))))])
8199 (define_insn "*cjump_long"
8202 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8203 (match_operand 0 "address_operand" "ZQZR")
8207 if (get_attr_op_type (insn) == OP_TYPE_RR)
8212 [(set (attr "op_type")
8213 (if_then_else (match_operand 0 "register_operand" "")
8214 (const_string "RR") (const_string "RX")))
8215 (set_attr "type" "branch")
8216 (set_attr "atype" "agen")])
8218 ;; A conditional return instruction.
8219 (define_insn "*c<code>"
8222 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8225 "s390_can_use_<code>_insn ()"
8227 [(set_attr "op_type" "RR")
8228 (set_attr "type" "jsr")
8229 (set_attr "atype" "agen")])
8232 ;;- Negated conditional jump instructions.
8235 (define_insn "*icjump_64"
8238 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8240 (label_ref (match_operand 0 "" ""))))]
8243 if (get_attr_length (insn) == 4)
8246 return "jg%D1\t%l0";
8248 [(set_attr "op_type" "RI")
8249 (set_attr "type" "branch")
8250 (set (attr "length")
8251 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8252 (const_int 4) (const_int 6)))])
8254 (define_insn "*icjump_31"
8257 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8259 (label_ref (match_operand 0 "" ""))))]
8262 gcc_assert (get_attr_length (insn) == 4);
8265 [(set_attr "op_type" "RI")
8266 (set_attr "type" "branch")
8267 (set (attr "length")
8268 (if_then_else (not (match_test "flag_pic"))
8269 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8270 (const_int 4) (const_int 6))
8271 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8272 (const_int 4) (const_int 8))))])
8274 (define_insn "*icjump_long"
8277 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8279 (match_operand 0 "address_operand" "ZQZR")))]
8282 if (get_attr_op_type (insn) == OP_TYPE_RR)
8287 [(set (attr "op_type")
8288 (if_then_else (match_operand 0 "register_operand" "")
8289 (const_string "RR") (const_string "RX")))
8290 (set_attr "type" "branch")
8291 (set_attr "atype" "agen")])
8294 ;;- Trap instructions.
8298 [(trap_if (const_int 1) (const_int 0))]
8301 [(set_attr "op_type" "RI")
8302 (set_attr "type" "branch")])
8304 (define_expand "ctrap<mode>4"
8305 [(trap_if (match_operator 0 "comparison_operator"
8306 [(match_operand:GPR 1 "register_operand" "")
8307 (match_operand:GPR 2 "general_operand" "")])
8308 (match_operand 3 "const0_operand" ""))]
8311 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8312 operands[1], operands[2]);
8313 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8317 (define_expand "ctrap<mode>4"
8318 [(trap_if (match_operator 0 "comparison_operator"
8319 [(match_operand:FP 1 "register_operand" "")
8320 (match_operand:FP 2 "general_operand" "")])
8321 (match_operand 3 "const0_operand" ""))]
8324 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8325 operands[1], operands[2]);
8326 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8330 (define_insn "condtrap"
8331 [(trap_if (match_operator 0 "s390_comparison"
8332 [(match_operand 1 "cc_reg_operand" "c")
8337 [(set_attr "op_type" "RI")
8338 (set_attr "type" "branch")])
8340 ; crt, cgrt, cit, cgit
8341 (define_insn "*cmp_and_trap_signed_int<mode>"
8342 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8343 [(match_operand:GPR 1 "register_operand" "d,d")
8344 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8350 [(set_attr "op_type" "RRF,RIE")
8351 (set_attr "type" "branch")
8352 (set_attr "z10prop" "z10_super_c,z10_super")])
8354 ; clrt, clgrt, clfit, clgit, clt, clgt
8355 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8356 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8357 [(match_operand:GPR 1 "register_operand" "d,d, d")
8358 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8365 [(set_attr "op_type" "RRF,RIE,RSY")
8366 (set_attr "type" "branch")
8367 (set_attr "z10prop" "z10_super_c,z10_super,*")
8368 (set_attr "cpu_facility" "z10,z10,zEC12")])
8371 (define_insn "*load_and_trap<mode>"
8372 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8375 (set (match_operand:GPR 1 "register_operand" "=d")
8379 [(set_attr "op_type" "RXY")])
8383 ;;- Loop instructions.
8385 ;; This is all complicated by the fact that since this is a jump insn
8386 ;; we must handle our own output reloads.
8390 ; This splitter will be matched by combine and has to add the 2 moves
8391 ; necessary to load the compare and the increment values into a
8392 ; register pair as needed by brxle.
8394 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8397 (match_operator 6 "s390_brx_operator"
8398 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8399 (match_operand:GPR 2 "general_operand" ""))
8400 (match_operand:GPR 3 "register_operand" "")])
8401 (label_ref (match_operand 0 "" ""))
8403 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8404 (plus:GPR (match_dup 1) (match_dup 2)))
8405 (clobber (match_scratch:GPR 5 ""))]
8408 "!reload_completed && !reload_in_progress"
8409 [(set (match_dup 7) (match_dup 2)) ; the increment
8410 (set (match_dup 8) (match_dup 3)) ; the comparison value
8411 (parallel [(set (pc)
8414 [(plus:GPR (match_dup 1) (match_dup 7))
8416 (label_ref (match_dup 0))
8419 (plus:GPR (match_dup 1) (match_dup 7)))
8420 (clobber (match_dup 5))
8421 (clobber (reg:CC CC_REGNUM))])]
8423 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8424 operands[7] = gen_lowpart (<GPR:MODE>mode,
8425 gen_highpart (word_mode, dreg));
8426 operands[8] = gen_lowpart (<GPR:MODE>mode,
8427 gen_lowpart (word_mode, dreg));
8432 (define_insn_and_split "*brxg_64bit"
8435 (match_operator 5 "s390_brx_operator"
8436 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8437 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8438 (subreg:DI (match_dup 2) 8)])
8439 (label_ref (match_operand 0 "" ""))
8441 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8442 (plus:DI (match_dup 1)
8443 (subreg:DI (match_dup 2) 0)))
8444 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8445 (clobber (reg:CC CC_REGNUM))]
8448 if (which_alternative != 0)
8450 else if (get_attr_length (insn) == 6)
8451 return "brx%E5g\t%1,%2,%l0";
8453 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8455 "&& reload_completed
8456 && (!REG_P (operands[3])
8457 || !rtx_equal_p (operands[1], operands[3]))"
8458 [(set (match_dup 4) (match_dup 1))
8459 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8460 (clobber (reg:CC CC_REGNUM))])
8461 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8462 (set (match_dup 3) (match_dup 4))
8463 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8464 (label_ref (match_dup 0))
8467 [(set_attr "op_type" "RIE")
8468 (set_attr "type" "branch")
8469 (set (attr "length")
8470 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8471 (const_int 6) (const_int 16)))])
8475 (define_insn_and_split "*brx_64bit"
8478 (match_operator 5 "s390_brx_operator"
8479 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8480 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8481 (subreg:SI (match_dup 2) 12)])
8482 (label_ref (match_operand 0 "" ""))
8484 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8485 (plus:SI (match_dup 1)
8486 (subreg:SI (match_dup 2) 4)))
8487 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8488 (clobber (reg:CC CC_REGNUM))]
8491 if (which_alternative != 0)
8493 else if (get_attr_length (insn) == 6)
8494 return "brx%C5\t%1,%2,%l0";
8496 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8498 "&& reload_completed
8499 && (!REG_P (operands[3])
8500 || !rtx_equal_p (operands[1], operands[3]))"
8501 [(set (match_dup 4) (match_dup 1))
8502 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8503 (clobber (reg:CC CC_REGNUM))])
8504 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8505 (set (match_dup 3) (match_dup 4))
8506 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8507 (label_ref (match_dup 0))
8510 [(set_attr "op_type" "RSI")
8511 (set_attr "type" "branch")
8512 (set (attr "length")
8513 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8514 (const_int 6) (const_int 14)))])
8518 (define_insn_and_split "*brx_31bit"
8521 (match_operator 5 "s390_brx_operator"
8522 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8523 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8524 (subreg:SI (match_dup 2) 4)])
8525 (label_ref (match_operand 0 "" ""))
8527 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8528 (plus:SI (match_dup 1)
8529 (subreg:SI (match_dup 2) 0)))
8530 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8531 (clobber (reg:CC CC_REGNUM))]
8532 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8534 if (which_alternative != 0)
8536 else if (get_attr_length (insn) == 6)
8537 return "brx%C5\t%1,%2,%l0";
8539 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8541 "&& reload_completed
8542 && (!REG_P (operands[3])
8543 || !rtx_equal_p (operands[1], operands[3]))"
8544 [(set (match_dup 4) (match_dup 1))
8545 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8546 (clobber (reg:CC CC_REGNUM))])
8547 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8548 (set (match_dup 3) (match_dup 4))
8549 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8550 (label_ref (match_dup 0))
8553 [(set_attr "op_type" "RSI")
8554 (set_attr "type" "branch")
8555 (set (attr "length")
8556 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8557 (const_int 6) (const_int 14)))])
8562 (define_expand "doloop_end"
8563 [(use (match_operand 0 "" "")) ; loop pseudo
8564 (use (match_operand 1 "" ""))] ; label
8567 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8568 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8569 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8570 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8571 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8572 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8579 (define_insn_and_split "doloop_si64"
8582 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8584 (label_ref (match_operand 0 "" ""))
8586 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8587 (plus:SI (match_dup 1) (const_int -1)))
8588 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8589 (clobber (reg:CC CC_REGNUM))]
8592 if (which_alternative != 0)
8594 else if (get_attr_length (insn) == 4)
8595 return "brct\t%1,%l0";
8597 return "ahi\t%1,-1\;jgne\t%l0";
8599 "&& reload_completed
8600 && (! REG_P (operands[2])
8601 || ! rtx_equal_p (operands[1], operands[2]))"
8602 [(set (match_dup 3) (match_dup 1))
8603 (parallel [(set (reg:CCAN CC_REGNUM)
8604 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8606 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8607 (set (match_dup 2) (match_dup 3))
8608 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8609 (label_ref (match_dup 0))
8612 [(set_attr "op_type" "RI")
8613 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8614 ; hurt us in the (rare) case of ahi.
8615 (set_attr "z10prop" "z10_super_E1")
8616 (set_attr "type" "branch")
8617 (set (attr "length")
8618 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8619 (const_int 4) (const_int 10)))])
8621 (define_insn_and_split "doloop_si31"
8624 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8626 (label_ref (match_operand 0 "" ""))
8628 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8629 (plus:SI (match_dup 1) (const_int -1)))
8630 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8631 (clobber (reg:CC CC_REGNUM))]
8634 if (which_alternative != 0)
8636 else if (get_attr_length (insn) == 4)
8637 return "brct\t%1,%l0";
8641 "&& reload_completed
8642 && (! REG_P (operands[2])
8643 || ! rtx_equal_p (operands[1], operands[2]))"
8644 [(set (match_dup 3) (match_dup 1))
8645 (parallel [(set (reg:CCAN CC_REGNUM)
8646 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8648 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8649 (set (match_dup 2) (match_dup 3))
8650 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8651 (label_ref (match_dup 0))
8654 [(set_attr "op_type" "RI")
8655 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8656 ; hurt us in the (rare) case of ahi.
8657 (set_attr "z10prop" "z10_super_E1")
8658 (set_attr "type" "branch")
8659 (set (attr "length")
8660 (if_then_else (not (match_test "flag_pic"))
8661 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8662 (const_int 4) (const_int 6))
8663 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8664 (const_int 4) (const_int 8))))])
8666 (define_insn "*doloop_si_long"
8669 (ne (match_operand:SI 1 "register_operand" "d")
8671 (match_operand 0 "address_operand" "ZQZR")
8673 (set (match_operand:SI 2 "register_operand" "=1")
8674 (plus:SI (match_dup 1) (const_int -1)))
8675 (clobber (match_scratch:SI 3 "=X"))
8676 (clobber (reg:CC CC_REGNUM))]
8679 if (get_attr_op_type (insn) == OP_TYPE_RR)
8680 return "bctr\t%1,%0";
8682 return "bct\t%1,%a0";
8684 [(set (attr "op_type")
8685 (if_then_else (match_operand 0 "register_operand" "")
8686 (const_string "RR") (const_string "RX")))
8687 (set_attr "type" "branch")
8688 (set_attr "atype" "agen")
8689 (set_attr "z10prop" "z10_c")
8690 (set_attr "z196prop" "z196_cracked")])
8692 (define_insn_and_split "doloop_di"
8695 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8697 (label_ref (match_operand 0 "" ""))
8699 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8700 (plus:DI (match_dup 1) (const_int -1)))
8701 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8702 (clobber (reg:CC CC_REGNUM))]
8705 if (which_alternative != 0)
8707 else if (get_attr_length (insn) == 4)
8708 return "brctg\t%1,%l0";
8710 return "aghi\t%1,-1\;jgne\t%l0";
8712 "&& reload_completed
8713 && (! REG_P (operands[2])
8714 || ! rtx_equal_p (operands[1], operands[2]))"
8715 [(set (match_dup 3) (match_dup 1))
8716 (parallel [(set (reg:CCAN CC_REGNUM)
8717 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8719 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8720 (set (match_dup 2) (match_dup 3))
8721 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8722 (label_ref (match_dup 0))
8725 [(set_attr "op_type" "RI")
8726 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8727 ; hurt us in the (rare) case of ahi.
8728 (set_attr "z10prop" "z10_super_E1")
8729 (set_attr "type" "branch")
8730 (set (attr "length")
8731 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8732 (const_int 4) (const_int 10)))])
8735 ;;- Unconditional jump instructions.
8739 ; jump instruction pattern(s).
8742 (define_expand "jump"
8743 [(match_operand 0 "" "")]
8745 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8747 (define_insn "*jump64"
8748 [(set (pc) (label_ref (match_operand 0 "" "")))]
8751 if (get_attr_length (insn) == 4)
8756 [(set_attr "op_type" "RI")
8757 (set_attr "type" "branch")
8758 (set (attr "length")
8759 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8760 (const_int 4) (const_int 6)))])
8762 (define_insn "*jump31"
8763 [(set (pc) (label_ref (match_operand 0 "" "")))]
8766 gcc_assert (get_attr_length (insn) == 4);
8769 [(set_attr "op_type" "RI")
8770 (set_attr "type" "branch")
8771 (set (attr "length")
8772 (if_then_else (not (match_test "flag_pic"))
8773 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8774 (const_int 4) (const_int 6))
8775 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8776 (const_int 4) (const_int 8))))])
8779 ; indirect-jump instruction pattern(s).
8782 (define_insn "indirect_jump"
8783 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8786 if (get_attr_op_type (insn) == OP_TYPE_RR)
8791 [(set (attr "op_type")
8792 (if_then_else (match_operand 0 "register_operand" "")
8793 (const_string "RR") (const_string "RX")))
8794 (set_attr "type" "branch")
8795 (set_attr "atype" "agen")])
8798 ; casesi instruction pattern(s).
8801 (define_insn "casesi_jump"
8802 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8803 (use (label_ref (match_operand 1 "" "")))]
8806 if (get_attr_op_type (insn) == OP_TYPE_RR)
8811 [(set (attr "op_type")
8812 (if_then_else (match_operand 0 "register_operand" "")
8813 (const_string "RR") (const_string "RX")))
8814 (set_attr "type" "branch")
8815 (set_attr "atype" "agen")])
8817 (define_expand "casesi"
8818 [(match_operand:SI 0 "general_operand" "")
8819 (match_operand:SI 1 "general_operand" "")
8820 (match_operand:SI 2 "general_operand" "")
8821 (label_ref (match_operand 3 "" ""))
8822 (label_ref (match_operand 4 "" ""))]
8825 rtx index = gen_reg_rtx (SImode);
8826 rtx base = gen_reg_rtx (Pmode);
8827 rtx target = gen_reg_rtx (Pmode);
8829 emit_move_insn (index, operands[0]);
8830 emit_insn (gen_subsi3 (index, index, operands[1]));
8831 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8834 if (Pmode != SImode)
8835 index = convert_to_mode (Pmode, index, 1);
8836 if (GET_CODE (index) != REG)
8837 index = copy_to_mode_reg (Pmode, index);
8840 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8842 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8844 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8846 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8847 emit_move_insn (target, index);
8850 target = gen_rtx_PLUS (Pmode, base, target);
8851 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8858 ;;- Jump to subroutine.
8863 ; untyped call instruction pattern(s).
8866 ;; Call subroutine returning any type.
8867 (define_expand "untyped_call"
8868 [(parallel [(call (match_operand 0 "" "")
8870 (match_operand 1 "" "")
8871 (match_operand 2 "" "")])]
8876 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8878 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8880 rtx set = XVECEXP (operands[2], 0, i);
8881 emit_move_insn (SET_DEST (set), SET_SRC (set));
8884 /* The optimizer does not know that the call sets the function value
8885 registers we stored in the result block. We avoid problems by
8886 claiming that all hard registers are used and clobbered at this
8888 emit_insn (gen_blockage ());
8893 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8894 ;; all of memory. This blocks insns from being moved across this point.
8896 (define_insn "blockage"
8897 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8900 [(set_attr "type" "none")
8901 (set_attr "length" "0")])
8907 (define_expand "sibcall"
8908 [(call (match_operand 0 "" "")
8909 (match_operand 1 "" ""))]
8912 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8916 (define_insn "*sibcall_br"
8917 [(call (mem:QI (reg SIBCALL_REGNUM))
8918 (match_operand 0 "const_int_operand" "n"))]
8919 "SIBLING_CALL_P (insn)
8920 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8922 [(set_attr "op_type" "RR")
8923 (set_attr "type" "branch")
8924 (set_attr "atype" "agen")])
8926 (define_insn "*sibcall_brc"
8927 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8928 (match_operand 1 "const_int_operand" "n"))]
8929 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8931 [(set_attr "op_type" "RI")
8932 (set_attr "type" "branch")])
8934 (define_insn "*sibcall_brcl"
8935 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8936 (match_operand 1 "const_int_operand" "n"))]
8937 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8939 [(set_attr "op_type" "RIL")
8940 (set_attr "type" "branch")])
8943 ; sibcall_value patterns
8946 (define_expand "sibcall_value"
8947 [(set (match_operand 0 "" "")
8948 (call (match_operand 1 "" "")
8949 (match_operand 2 "" "")))]
8952 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8956 (define_insn "*sibcall_value_br"
8957 [(set (match_operand 0 "" "")
8958 (call (mem:QI (reg SIBCALL_REGNUM))
8959 (match_operand 1 "const_int_operand" "n")))]
8960 "SIBLING_CALL_P (insn)
8961 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8963 [(set_attr "op_type" "RR")
8964 (set_attr "type" "branch")
8965 (set_attr "atype" "agen")])
8967 (define_insn "*sibcall_value_brc"
8968 [(set (match_operand 0 "" "")
8969 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8970 (match_operand 2 "const_int_operand" "n")))]
8971 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8973 [(set_attr "op_type" "RI")
8974 (set_attr "type" "branch")])
8976 (define_insn "*sibcall_value_brcl"
8977 [(set (match_operand 0 "" "")
8978 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8979 (match_operand 2 "const_int_operand" "n")))]
8980 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8982 [(set_attr "op_type" "RIL")
8983 (set_attr "type" "branch")])
8987 ; call instruction pattern(s).
8990 (define_expand "call"
8991 [(call (match_operand 0 "" "")
8992 (match_operand 1 "" ""))
8993 (use (match_operand 2 "" ""))]
8996 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8997 gen_rtx_REG (Pmode, RETURN_REGNUM));
9001 (define_insn "*bras"
9002 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9003 (match_operand 1 "const_int_operand" "n"))
9004 (clobber (match_operand 2 "register_operand" "=r"))]
9005 "!SIBLING_CALL_P (insn)
9006 && TARGET_SMALL_EXEC
9007 && GET_MODE (operands[2]) == Pmode"
9009 [(set_attr "op_type" "RI")
9010 (set_attr "type" "jsr")
9011 (set_attr "z196prop" "z196_cracked")])
9013 (define_insn "*brasl"
9014 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9015 (match_operand 1 "const_int_operand" "n"))
9016 (clobber (match_operand 2 "register_operand" "=r"))]
9017 "!SIBLING_CALL_P (insn)
9019 && GET_MODE (operands[2]) == Pmode"
9021 [(set_attr "op_type" "RIL")
9022 (set_attr "type" "jsr")
9023 (set_attr "z196prop" "z196_cracked")])
9025 (define_insn "*basr"
9026 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9027 (match_operand 1 "const_int_operand" "n"))
9028 (clobber (match_operand 2 "register_operand" "=r"))]
9029 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9031 if (get_attr_op_type (insn) == OP_TYPE_RR)
9032 return "basr\t%2,%0";
9034 return "bas\t%2,%a0";
9036 [(set (attr "op_type")
9037 (if_then_else (match_operand 0 "register_operand" "")
9038 (const_string "RR") (const_string "RX")))
9039 (set_attr "type" "jsr")
9040 (set_attr "atype" "agen")
9041 (set_attr "z196prop" "z196_cracked")])
9044 ; call_value instruction pattern(s).
9047 (define_expand "call_value"
9048 [(set (match_operand 0 "" "")
9049 (call (match_operand 1 "" "")
9050 (match_operand 2 "" "")))
9051 (use (match_operand 3 "" ""))]
9054 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9055 gen_rtx_REG (Pmode, RETURN_REGNUM));
9059 (define_insn "*bras_r"
9060 [(set (match_operand 0 "" "")
9061 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9062 (match_operand:SI 2 "const_int_operand" "n")))
9063 (clobber (match_operand 3 "register_operand" "=r"))]
9064 "!SIBLING_CALL_P (insn)
9065 && TARGET_SMALL_EXEC
9066 && GET_MODE (operands[3]) == Pmode"
9068 [(set_attr "op_type" "RI")
9069 (set_attr "type" "jsr")
9070 (set_attr "z196prop" "z196_cracked")])
9072 (define_insn "*brasl_r"
9073 [(set (match_operand 0 "" "")
9074 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9075 (match_operand 2 "const_int_operand" "n")))
9076 (clobber (match_operand 3 "register_operand" "=r"))]
9077 "!SIBLING_CALL_P (insn)
9079 && GET_MODE (operands[3]) == Pmode"
9081 [(set_attr "op_type" "RIL")
9082 (set_attr "type" "jsr")
9083 (set_attr "z196prop" "z196_cracked")])
9085 (define_insn "*basr_r"
9086 [(set (match_operand 0 "" "")
9087 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9088 (match_operand 2 "const_int_operand" "n")))
9089 (clobber (match_operand 3 "register_operand" "=r"))]
9090 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9092 if (get_attr_op_type (insn) == OP_TYPE_RR)
9093 return "basr\t%3,%1";
9095 return "bas\t%3,%a1";
9097 [(set (attr "op_type")
9098 (if_then_else (match_operand 1 "register_operand" "")
9099 (const_string "RR") (const_string "RX")))
9100 (set_attr "type" "jsr")
9101 (set_attr "atype" "agen")
9102 (set_attr "z196prop" "z196_cracked")])
9105 ;;- Thread-local storage support.
9108 (define_expand "get_thread_pointer<mode>"
9109 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9113 (define_expand "set_thread_pointer<mode>"
9114 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9115 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9119 (define_insn "*set_tp"
9120 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9123 [(set_attr "type" "none")
9124 (set_attr "length" "0")])
9126 (define_insn "*tls_load_64"
9127 [(set (match_operand:DI 0 "register_operand" "=d")
9128 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9129 (match_operand:DI 2 "" "")]
9133 [(set_attr "op_type" "RXE")
9134 (set_attr "z10prop" "z10_fwd_A3")])
9136 (define_insn "*tls_load_31"
9137 [(set (match_operand:SI 0 "register_operand" "=d,d")
9138 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9139 (match_operand:SI 2 "" "")]
9145 [(set_attr "op_type" "RX,RXY")
9146 (set_attr "type" "load")
9147 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9149 (define_insn "*bras_tls"
9150 [(set (match_operand 0 "" "")
9151 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9152 (match_operand 2 "const_int_operand" "n")))
9153 (clobber (match_operand 3 "register_operand" "=r"))
9154 (use (match_operand 4 "" ""))]
9155 "!SIBLING_CALL_P (insn)
9156 && TARGET_SMALL_EXEC
9157 && GET_MODE (operands[3]) == Pmode"
9159 [(set_attr "op_type" "RI")
9160 (set_attr "type" "jsr")
9161 (set_attr "z196prop" "z196_cracked")])
9163 (define_insn "*brasl_tls"
9164 [(set (match_operand 0 "" "")
9165 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9166 (match_operand 2 "const_int_operand" "n")))
9167 (clobber (match_operand 3 "register_operand" "=r"))
9168 (use (match_operand 4 "" ""))]
9169 "!SIBLING_CALL_P (insn)
9171 && GET_MODE (operands[3]) == Pmode"
9173 [(set_attr "op_type" "RIL")
9174 (set_attr "type" "jsr")
9175 (set_attr "z196prop" "z196_cracked")])
9177 (define_insn "*basr_tls"
9178 [(set (match_operand 0 "" "")
9179 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9180 (match_operand 2 "const_int_operand" "n")))
9181 (clobber (match_operand 3 "register_operand" "=r"))
9182 (use (match_operand 4 "" ""))]
9183 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9185 if (get_attr_op_type (insn) == OP_TYPE_RR)
9186 return "basr\t%3,%1%J4";
9188 return "bas\t%3,%a1%J4";
9190 [(set (attr "op_type")
9191 (if_then_else (match_operand 1 "register_operand" "")
9192 (const_string "RR") (const_string "RX")))
9193 (set_attr "type" "jsr")
9194 (set_attr "atype" "agen")
9195 (set_attr "z196prop" "z196_cracked")])
9198 ;;- Atomic operations
9202 ; memory barrier patterns.
9205 (define_expand "mem_signal_fence"
9206 [(match_operand:SI 0 "const_int_operand")] ;; model
9209 /* The s390 memory model is strong enough not to require any
9210 barrier in order to synchronize a thread with itself. */
9214 (define_expand "mem_thread_fence"
9215 [(match_operand:SI 0 "const_int_operand")] ;; model
9218 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9219 enough not to require barriers of any kind. */
9220 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
9222 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9223 MEM_VOLATILE_P (mem) = 1;
9224 emit_insn (gen_mem_thread_fence_1 (mem));
9229 ; Although bcr is superscalar on Z10, this variant will never
9230 ; become part of an execution group.
9231 ; With z196 we can make use of the fast-BCR-serialization facility.
9232 ; This allows for a slightly faster sync which is sufficient for our
9234 (define_insn "mem_thread_fence_1"
9235 [(set (match_operand:BLK 0 "" "")
9236 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9244 [(set_attr "op_type" "RR")
9245 (set_attr "mnemonic" "bcr_flush")
9246 (set_attr "z196prop" "z196_alone")])
9249 ; atomic load/store operations
9252 ; Atomic loads need not examine the memory model at all.
9253 (define_expand "atomic_load<mode>"
9254 [(match_operand:DINT 0 "register_operand") ;; output
9255 (match_operand:DINT 1 "memory_operand") ;; memory
9256 (match_operand:SI 2 "const_int_operand")] ;; model
9259 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9262 if (<MODE>mode == TImode)
9263 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9264 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9265 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9267 emit_move_insn (operands[0], operands[1]);
9271 ; Different from movdi_31 in that we want no splitters.
9272 (define_insn "atomic_loaddi_1"
9273 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9274 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9282 [(set_attr "op_type" "RS,RSY,RS,RSY")
9283 (set_attr "type" "lm,lm,floaddf,floaddf")])
9285 (define_insn "atomic_loadti_1"
9286 [(set (match_operand:TI 0 "register_operand" "=r")
9287 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9291 [(set_attr "op_type" "RXY")
9292 (set_attr "type" "other")])
9294 ; Atomic stores must(?) enforce sequential consistency.
9295 (define_expand "atomic_store<mode>"
9296 [(match_operand:DINT 0 "memory_operand") ;; memory
9297 (match_operand:DINT 1 "register_operand") ;; input
9298 (match_operand:SI 2 "const_int_operand")] ;; model
9301 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9303 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9306 if (<MODE>mode == TImode)
9307 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9308 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9309 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9311 emit_move_insn (operands[0], operands[1]);
9312 if (model == MEMMODEL_SEQ_CST)
9313 emit_insn (gen_mem_thread_fence (operands[2]));
9317 ; Different from movdi_31 in that we want no splitters.
9318 (define_insn "atomic_storedi_1"
9319 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9320 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9328 [(set_attr "op_type" "RS,RSY,RS,RSY")
9329 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9331 (define_insn "atomic_storeti_1"
9332 [(set (match_operand:TI 0 "memory_operand" "=RT")
9333 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9337 [(set_attr "op_type" "RXY")
9338 (set_attr "type" "other")])
9341 ; compare and swap patterns.
9344 (define_expand "atomic_compare_and_swap<mode>"
9345 [(match_operand:SI 0 "register_operand") ;; bool success output
9346 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9347 (match_operand:DGPR 2 "memory_operand") ;; memory
9348 (match_operand:DGPR 3 "register_operand") ;; expected intput
9349 (match_operand:DGPR 4 "register_operand") ;; newval intput
9350 (match_operand:SI 5 "const_int_operand") ;; is_weak
9351 (match_operand:SI 6 "const_int_operand") ;; success model
9352 (match_operand:SI 7 "const_int_operand")] ;; failure model
9355 rtx cc, cmp, output = operands[1];
9357 if (!register_operand (output, <MODE>mode))
9358 output = gen_reg_rtx (<MODE>mode);
9360 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9363 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9364 (output, operands[2], operands[3], operands[4]));
9366 /* We deliberately accept non-register operands in the predicate
9367 to ensure the write back to the output operand happens *before*
9368 the store-flags code below. This makes it easier for combine
9369 to merge the store-flags code with a potential test-and-branch
9370 pattern following (immediately!) afterwards. */
9371 if (output != operands[1])
9372 emit_move_insn (operands[1], output);
9374 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9375 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9376 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9380 (define_expand "atomic_compare_and_swap<mode>"
9381 [(match_operand:SI 0 "register_operand") ;; bool success output
9382 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9383 (match_operand:HQI 2 "memory_operand") ;; memory
9384 (match_operand:HQI 3 "general_operand") ;; expected intput
9385 (match_operand:HQI 4 "general_operand") ;; newval intput
9386 (match_operand:SI 5 "const_int_operand") ;; is_weak
9387 (match_operand:SI 6 "const_int_operand") ;; success model
9388 (match_operand:SI 7 "const_int_operand")] ;; failure model
9391 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9392 operands[3], operands[4], INTVAL (operands[5]));
9396 (define_expand "atomic_compare_and_swap<mode>_internal"
9398 [(set (match_operand:DGPR 0 "register_operand")
9399 (match_operand:DGPR 1 "memory_operand"))
9401 (unspec_volatile:DGPR
9403 (match_operand:DGPR 2 "register_operand")
9404 (match_operand:DGPR 3 "register_operand")]
9406 (set (reg:CCZ1 CC_REGNUM)
9407 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9411 (define_insn "*atomic_compare_and_swap<mode>_1"
9412 [(set (match_operand:TDI 0 "register_operand" "=r")
9413 (match_operand:TDI 1 "memory_operand" "+QS"))
9415 (unspec_volatile:TDI
9417 (match_operand:TDI 2 "register_operand" "0")
9418 (match_operand:TDI 3 "register_operand" "r")]
9420 (set (reg:CCZ1 CC_REGNUM)
9421 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9423 "c<td>sg\t%0,%3,%S1"
9424 [(set_attr "op_type" "RSY")
9425 (set_attr "type" "sem")])
9428 (define_insn "*atomic_compare_and_swapdi_2"
9429 [(set (match_operand:DI 0 "register_operand" "=r,r")
9430 (match_operand:DI 1 "memory_operand" "+Q,S"))
9434 (match_operand:DI 2 "register_operand" "0,0")
9435 (match_operand:DI 3 "register_operand" "r,r")]
9437 (set (reg:CCZ1 CC_REGNUM)
9438 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9443 [(set_attr "op_type" "RS,RSY")
9444 (set_attr "type" "sem")])
9447 (define_insn "*atomic_compare_and_swapsi_3"
9448 [(set (match_operand:SI 0 "register_operand" "=r,r")
9449 (match_operand:SI 1 "memory_operand" "+Q,S"))
9453 (match_operand:SI 2 "register_operand" "0,0")
9454 (match_operand:SI 3 "register_operand" "r,r")]
9456 (set (reg:CCZ1 CC_REGNUM)
9457 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9462 [(set_attr "op_type" "RS,RSY")
9463 (set_attr "type" "sem")])
9466 ; Other atomic instruction patterns.
9469 ; z196 load and add, xor, or and and instructions
9471 (define_expand "atomic_fetch_<atomic><mode>"
9472 [(match_operand:GPR 0 "register_operand") ;; val out
9474 (match_operand:GPR 1 "memory_operand") ;; memory
9475 (match_operand:GPR 2 "register_operand")) ;; val in
9476 (match_operand:SI 3 "const_int_operand")] ;; model
9479 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9482 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9483 (operands[0], operands[1], operands[2]));
9487 ; lan, lang, lao, laog, lax, laxg, laa, laag
9488 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9489 [(set (match_operand:GPR 0 "register_operand" "=d")
9490 (match_operand:GPR 1 "memory_operand" "+QS"))
9492 (unspec_volatile:GPR
9493 [(ATOMIC_Z196:GPR (match_dup 1)
9494 (match_operand:GPR 2 "general_operand" "d"))]
9496 (clobber (reg:CC CC_REGNUM))]
9498 "la<noxa><g>\t%0,%2,%1"
9499 [(set_attr "op_type" "RSY")
9500 (set_attr "type" "sem")])
9502 ;; For SImode and larger, the optabs.c code will do just fine in
9503 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9504 ;; better by expanding our own loop.
9506 (define_expand "atomic_<atomic><mode>"
9508 (match_operand:HQI 0 "memory_operand") ;; memory
9509 (match_operand:HQI 1 "general_operand")) ;; val in
9510 (match_operand:SI 2 "const_int_operand")] ;; model
9513 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9514 operands[1], false);
9518 (define_expand "atomic_fetch_<atomic><mode>"
9519 [(match_operand:HQI 0 "register_operand") ;; val out
9521 (match_operand:HQI 1 "memory_operand") ;; memory
9522 (match_operand:HQI 2 "general_operand")) ;; val in
9523 (match_operand:SI 3 "const_int_operand")] ;; model
9526 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9527 operands[2], false);
9531 (define_expand "atomic_<atomic>_fetch<mode>"
9532 [(match_operand:HQI 0 "register_operand") ;; val out
9534 (match_operand:HQI 1 "memory_operand") ;; memory
9535 (match_operand:HQI 2 "general_operand")) ;; val in
9536 (match_operand:SI 3 "const_int_operand")] ;; model
9539 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9544 (define_expand "atomic_exchange<mode>"
9545 [(match_operand:HQI 0 "register_operand") ;; val out
9546 (match_operand:HQI 1 "memory_operand") ;; memory
9547 (match_operand:HQI 2 "general_operand") ;; val in
9548 (match_operand:SI 3 "const_int_operand")] ;; model
9551 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9552 operands[2], false);
9557 ;;- Miscellaneous instructions.
9561 ; allocate stack instruction pattern(s).
9564 (define_expand "allocate_stack"
9565 [(match_operand 0 "general_operand" "")
9566 (match_operand 1 "general_operand" "")]
9569 rtx temp = gen_reg_rtx (Pmode);
9571 emit_move_insn (temp, s390_back_chain_rtx ());
9572 anti_adjust_stack (operands[1]);
9573 emit_move_insn (s390_back_chain_rtx (), temp);
9575 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9581 ; setjmp instruction pattern.
9584 (define_expand "builtin_setjmp_receiver"
9585 [(match_operand 0 "" "")]
9588 emit_insn (s390_load_got ());
9589 emit_use (pic_offset_table_rtx);
9593 ;; These patterns say how to save and restore the stack pointer. We need not
9594 ;; save the stack pointer at function level since we are careful to
9595 ;; preserve the backchain. At block level, we have to restore the backchain
9596 ;; when we restore the stack pointer.
9598 ;; For nonlocal gotos, we must save both the stack pointer and its
9599 ;; backchain and restore both. Note that in the nonlocal case, the
9600 ;; save area is a memory location.
9602 (define_expand "save_stack_function"
9603 [(match_operand 0 "general_operand" "")
9604 (match_operand 1 "general_operand" "")]
9608 (define_expand "restore_stack_function"
9609 [(match_operand 0 "general_operand" "")
9610 (match_operand 1 "general_operand" "")]
9614 (define_expand "restore_stack_block"
9615 [(match_operand 0 "register_operand" "")
9616 (match_operand 1 "register_operand" "")]
9619 rtx temp = gen_reg_rtx (Pmode);
9621 emit_move_insn (temp, s390_back_chain_rtx ());
9622 emit_move_insn (operands[0], operands[1]);
9623 emit_move_insn (s390_back_chain_rtx (), temp);
9628 (define_expand "save_stack_nonlocal"
9629 [(match_operand 0 "memory_operand" "")
9630 (match_operand 1 "register_operand" "")]
9633 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9635 /* Copy the backchain to the first word, sp to the second and the
9636 literal pool base to the third. */
9638 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9639 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9640 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9642 if (TARGET_BACKCHAIN)
9643 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9645 emit_move_insn (save_sp, operands[1]);
9646 emit_move_insn (save_bp, base);
9651 (define_expand "restore_stack_nonlocal"
9652 [(match_operand 0 "register_operand" "")
9653 (match_operand 1 "memory_operand" "")]
9656 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9657 rtx temp = NULL_RTX;
9659 /* Restore the backchain from the first word, sp from the second and the
9660 literal pool base from the third. */
9662 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9663 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9664 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9666 if (TARGET_BACKCHAIN)
9667 temp = force_reg (Pmode, save_bc);
9669 emit_move_insn (base, save_bp);
9670 emit_move_insn (operands[0], save_sp);
9673 emit_move_insn (s390_back_chain_rtx (), temp);
9679 (define_expand "exception_receiver"
9683 s390_set_has_landing_pad_p (true);
9688 ; nop instruction pattern(s).
9695 [(set_attr "op_type" "RR")
9696 (set_attr "z10prop" "z10_fr_E1")])
9702 [(set_attr "op_type" "RR")])
9706 ; Special literal pool access instruction pattern(s).
9709 (define_insn "*pool_entry"
9710 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9711 UNSPECV_POOL_ENTRY)]
9714 machine_mode mode = GET_MODE (PATTERN (insn));
9715 unsigned int align = GET_MODE_BITSIZE (mode);
9716 s390_output_pool_entry (operands[0], mode, align);
9719 [(set (attr "length")
9720 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9722 (define_insn "pool_align"
9723 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9724 UNSPECV_POOL_ALIGN)]
9727 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9729 (define_insn "pool_section_start"
9730 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9733 [(set_attr "length" "0")])
9735 (define_insn "pool_section_end"
9736 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9739 [(set_attr "length" "0")])
9741 (define_insn "main_base_31_small"
9742 [(set (match_operand 0 "register_operand" "=a")
9743 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9744 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9746 [(set_attr "op_type" "RR")
9747 (set_attr "type" "la")
9748 (set_attr "z196prop" "z196_cracked")])
9750 (define_insn "main_base_31_large"
9751 [(set (match_operand 0 "register_operand" "=a")
9752 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9753 (set (pc) (label_ref (match_operand 2 "" "")))]
9754 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9756 [(set_attr "op_type" "RI")
9757 (set_attr "z196prop" "z196_cracked")])
9759 (define_insn "main_base_64"
9760 [(set (match_operand 0 "register_operand" "=a")
9761 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9762 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9764 [(set_attr "op_type" "RIL")
9765 (set_attr "type" "larl")
9766 (set_attr "z10prop" "z10_fwd_A1")])
9768 (define_insn "main_pool"
9769 [(set (match_operand 0 "register_operand" "=a")
9770 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9771 "GET_MODE (operands[0]) == Pmode"
9776 (if_then_else (match_test "TARGET_CPU_ZARCH")
9777 (const_string "larl") (const_string "la")))])
9779 (define_insn "reload_base_31"
9780 [(set (match_operand 0 "register_operand" "=a")
9781 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9782 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9783 "basr\t%0,0\;la\t%0,%1-.(%0)"
9784 [(set_attr "length" "6")
9785 (set_attr "type" "la")
9786 (set_attr "z196prop" "z196_cracked")])
9788 (define_insn "reload_base_64"
9789 [(set (match_operand 0 "register_operand" "=a")
9790 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9791 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9793 [(set_attr "op_type" "RIL")
9794 (set_attr "type" "larl")
9795 (set_attr "z10prop" "z10_fwd_A1")])
9798 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9803 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9806 ;; Insns related to generating the function prologue and epilogue.
9810 (define_expand "prologue"
9811 [(use (const_int 0))]
9813 "s390_emit_prologue (); DONE;")
9815 (define_expand "epilogue"
9816 [(use (const_int 1))]
9818 "s390_emit_epilogue (false); DONE;")
9820 (define_expand "sibcall_epilogue"
9821 [(use (const_int 0))]
9823 "s390_emit_epilogue (true); DONE;")
9825 ;; A direct return instruction, without using an epilogue.
9826 (define_insn "<code>"
9828 "s390_can_use_<code>_insn ()"
9830 [(set_attr "op_type" "RR")
9831 (set_attr "type" "jsr")
9832 (set_attr "atype" "agen")])
9834 (define_insn "*return"
9836 (use (match_operand 0 "register_operand" "a"))]
9837 "GET_MODE (operands[0]) == Pmode"
9839 [(set_attr "op_type" "RR")
9840 (set_attr "type" "jsr")
9841 (set_attr "atype" "agen")])
9844 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9845 ;; pointer. This is used for compatibility.
9847 (define_expand "ptr_extend"
9848 [(set (match_operand:DI 0 "register_operand" "=r")
9849 (match_operand:SI 1 "register_operand" "r"))]
9852 emit_insn (gen_anddi3 (operands[0],
9853 gen_lowpart (DImode, operands[1]),
9854 GEN_INT (0x7fffffff)));
9858 ;; Instruction definition to expand eh_return macro to support
9859 ;; swapping in special linkage return addresses.
9861 (define_expand "eh_return"
9862 [(use (match_operand 0 "register_operand" ""))]
9865 s390_emit_tpf_eh_return (operands[0]);
9870 ; Stack Protector Patterns
9873 (define_expand "stack_protect_set"
9874 [(set (match_operand 0 "memory_operand" "")
9875 (match_operand 1 "memory_operand" ""))]
9878 #ifdef TARGET_THREAD_SSP_OFFSET
9880 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9881 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9884 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9886 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9891 (define_insn "stack_protect_set<mode>"
9892 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9893 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9895 "mvc\t%O0(%G0,%R0),%S1"
9896 [(set_attr "op_type" "SS")])
9898 (define_expand "stack_protect_test"
9899 [(set (reg:CC CC_REGNUM)
9900 (compare (match_operand 0 "memory_operand" "")
9901 (match_operand 1 "memory_operand" "")))
9902 (match_operand 2 "" "")]
9906 #ifdef TARGET_THREAD_SSP_OFFSET
9908 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9909 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9912 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9914 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9916 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9917 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9918 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9922 (define_insn "stack_protect_test<mode>"
9923 [(set (reg:CCZ CC_REGNUM)
9924 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9925 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9927 "clc\t%O0(%G0,%R0),%S1"
9928 [(set_attr "op_type" "SS")])
9930 ; This is used in s390_emit_prologue in order to prevent insns
9931 ; adjusting the stack pointer to be moved over insns writing stack
9932 ; slots using a copy of the stack pointer in a different register.
9933 (define_insn "stack_tie"
9934 [(set (match_operand:BLK 0 "memory_operand" "+m")
9935 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9938 [(set_attr "length" "0")])
9942 ; Data prefetch patterns
9945 (define_insn "prefetch"
9946 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9947 (match_operand:SI 1 "const_int_operand" " n,n")
9948 (match_operand:SI 2 "const_int_operand" " n,n"))]
9951 switch (which_alternative)
9954 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9956 if (larl_operand (operands[0], Pmode))
9957 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9960 /* This might be reached for symbolic operands with an odd
9961 addend. We simply omit the prefetch for such rare cases. */
9966 [(set_attr "type" "load,larl")
9967 (set_attr "op_type" "RXY,RIL")
9968 (set_attr "z10prop" "z10_super")
9969 (set_attr "z196prop" "z196_alone")])
9973 ; Byte swap instructions
9976 (define_insn "bswap<mode>2"
9977 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9978 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9983 [(set_attr "type" "*,load")
9984 (set_attr "op_type" "RRE,RXY")
9985 (set_attr "z10prop" "z10_super")])
9989 ; Population count instruction
9992 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9993 ; portions and stores the result in the corresponding bytes in op0.
9994 (define_insn "*popcount<mode>"
9995 [(set (match_operand:INT 0 "register_operand" "=d")
9996 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9997 (clobber (reg:CC CC_REGNUM))]
10000 [(set_attr "op_type" "RRE")])
10002 (define_expand "popcountdi2"
10004 (parallel [(set (match_operand:DI 0 "register_operand" "")
10005 (unspec:DI [(match_operand:DI 1 "register_operand")]
10007 (clobber (reg:CC CC_REGNUM))])
10008 ; sllg op2, op0, 32
10009 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10011 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10012 (clobber (reg:CC CC_REGNUM))])
10013 ; sllg op2, op0, 16
10015 (ashift:DI (match_dup 0) (const_int 16)))
10017 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10018 (clobber (reg:CC CC_REGNUM))])
10020 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10022 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10023 (clobber (reg:CC CC_REGNUM))])
10024 ; srlg op0, op0, 56
10025 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10026 "TARGET_Z196 && TARGET_64BIT"
10027 "operands[2] = gen_reg_rtx (DImode);")
10029 (define_expand "popcountsi2"
10031 (parallel [(set (match_operand:SI 0 "register_operand" "")
10032 (unspec:SI [(match_operand:SI 1 "register_operand")]
10034 (clobber (reg:CC CC_REGNUM))])
10035 ; sllk op2, op0, 16
10037 (ashift:SI (match_dup 0) (const_int 16)))
10039 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10040 (clobber (reg:CC CC_REGNUM))])
10042 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10044 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10045 (clobber (reg:CC CC_REGNUM))])
10047 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10049 "operands[2] = gen_reg_rtx (SImode);")
10051 (define_expand "popcounthi2"
10053 (parallel [(set (match_operand:HI 0 "register_operand" "")
10054 (unspec:HI [(match_operand:HI 1 "register_operand")]
10056 (clobber (reg:CC CC_REGNUM))])
10059 (ashift:SI (match_dup 0) (const_int 8)))
10061 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10062 (clobber (reg:CC CC_REGNUM))])
10064 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10066 "operands[2] = gen_reg_rtx (SImode);")
10068 (define_expand "popcountqi2"
10070 (parallel [(set (match_operand:QI 0 "register_operand" "")
10071 (unspec:QI [(match_operand:QI 1 "register_operand")]
10073 (clobber (reg:CC CC_REGNUM))])]
10078 ;;- Copy sign instructions
10081 (define_insn "copysign<mode>3"
10082 [(set (match_operand:FP 0 "register_operand" "=f")
10083 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10084 (match_operand:FP 2 "register_operand" "f")]
10088 [(set_attr "op_type" "RRF")
10089 (set_attr "type" "fsimp<mode>")])
10093 ;;- Transactional execution instructions
10096 ; This splitter helps combine to make use of CC directly when
10097 ; comparing the integer result of a tbegin builtin with a constant.
10098 ; The unspec is already removed by canonicalize_comparison. So this
10099 ; splitters only job is to turn the PARALLEL into separate insns
10100 ; again. Unfortunately this only works with the very first cc/int
10101 ; compare since combine is not able to deal with data flow across
10102 ; basic block boundaries.
10104 ; It needs to be an insn pattern as well since combine does not apply
10105 ; the splitter directly. Combine would only use it if it actually
10106 ; would reduce the number of instructions.
10107 (define_insn_and_split "*ccraw_to_int"
10110 (match_operator 0 "s390_eqne_operator"
10111 [(reg:CCRAW CC_REGNUM)
10112 (match_operand 1 "const_int_operand" "")])
10113 (label_ref (match_operand 2 "" ""))
10115 (set (match_operand:SI 3 "register_operand" "=d")
10116 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10120 [(set (match_dup 3)
10121 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10123 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10124 (label_ref (match_dup 2))
10128 ; Non-constrained transaction begin
10130 (define_expand "tbegin"
10131 [(match_operand:SI 0 "register_operand" "")
10132 (match_operand:BLK 1 "memory_operand" "")]
10135 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10139 (define_expand "tbegin_nofloat"
10140 [(match_operand:SI 0 "register_operand" "")
10141 (match_operand:BLK 1 "memory_operand" "")]
10144 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10148 (define_expand "tbegin_retry"
10149 [(match_operand:SI 0 "register_operand" "")
10150 (match_operand:BLK 1 "memory_operand" "")
10151 (match_operand:SI 2 "general_operand" "")]
10154 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10158 (define_expand "tbegin_retry_nofloat"
10159 [(match_operand:SI 0 "register_operand" "")
10160 (match_operand:BLK 1 "memory_operand" "")
10161 (match_operand:SI 2 "general_operand" "")]
10164 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10168 (define_insn "tbegin_1"
10169 [(set (reg:CCRAW CC_REGNUM)
10170 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10172 (set (match_operand:BLK 1 "memory_operand" "=Q")
10173 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10174 (clobber (reg:DF 16))
10175 (clobber (reg:DF 17))
10176 (clobber (reg:DF 18))
10177 (clobber (reg:DF 19))
10178 (clobber (reg:DF 20))
10179 (clobber (reg:DF 21))
10180 (clobber (reg:DF 22))
10181 (clobber (reg:DF 23))
10182 (clobber (reg:DF 24))
10183 (clobber (reg:DF 25))
10184 (clobber (reg:DF 26))
10185 (clobber (reg:DF 27))
10186 (clobber (reg:DF 28))
10187 (clobber (reg:DF 29))
10188 (clobber (reg:DF 30))
10189 (clobber (reg:DF 31))]
10190 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10191 ; not supposed to be used for immediates (see genpreds.c).
10192 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10194 [(set_attr "op_type" "SIL")])
10196 ; Same as above but without the FPR clobbers
10197 (define_insn "tbegin_nofloat_1"
10198 [(set (reg:CCRAW CC_REGNUM)
10199 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10201 (set (match_operand:BLK 1 "memory_operand" "=Q")
10202 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10203 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10205 [(set_attr "op_type" "SIL")])
10208 ; Constrained transaction begin
10210 (define_expand "tbeginc"
10211 [(set (reg:CCRAW CC_REGNUM)
10212 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10217 (define_insn "*tbeginc_1"
10218 [(set (reg:CCRAW CC_REGNUM)
10219 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10221 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10223 [(set_attr "op_type" "SIL")])
10227 (define_expand "tend"
10228 [(set (reg:CCRAW CC_REGNUM)
10229 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10230 (set (match_operand:SI 0 "register_operand" "")
10231 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10235 (define_insn "*tend_1"
10236 [(set (reg:CCRAW CC_REGNUM)
10237 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10240 [(set_attr "op_type" "S")])
10242 ; Transaction abort
10244 (define_expand "tabort"
10245 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10247 "TARGET_HTM && operands != NULL"
10249 if (CONST_INT_P (operands[0])
10250 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10252 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10253 ". Values in range 0 through 255 are reserved.",
10254 INTVAL (operands[0]));
10259 (define_insn "*tabort_1"
10260 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10262 "TARGET_HTM && operands != NULL"
10264 [(set_attr "op_type" "S")])
10266 ; Transaction extract nesting depth
10268 (define_insn "etnd"
10269 [(set (match_operand:SI 0 "register_operand" "=d")
10270 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10273 [(set_attr "op_type" "RRE")])
10275 ; Non-transactional store
10277 (define_insn "ntstg"
10278 [(set (match_operand:DI 0 "memory_operand" "=RT")
10279 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10283 [(set_attr "op_type" "RXY")])
10285 ; Transaction perform processor assist
10287 (define_expand "tx_assist"
10288 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10289 (reg:SI GPR0_REGNUM)
10295 (define_insn "*ppa"
10296 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10297 (match_operand:SI 1 "register_operand" "d")
10298 (match_operand 2 "const_int_operand" "I")]
10300 "TARGET_HTM && INTVAL (operands[2]) < 16"
10302 [(set_attr "op_type" "RRF")])