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s390.c: Fix comment typos.
[gcc.git] / gcc / config / s390 / s390.md
1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
21
22 ;;
23 ;; Special constraints for s/390 machine description:
24 ;;
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
32 ;;
33 ;; Special formats used for outputting 390 instructions.
34 ;;
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
41 ;;
42 ;; We have a special constraint for pattern matching.
43 ;;
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
45 ;;
46 ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI
47 ;; or SS type instruction or a register
48 ;;
49
50 ;; Insn type. Used to default other attribute values.
51
52
53 ;; Define an insn type attribute. This is used in function unit delay
54 ;; computations.
55
56 (define_attr "type" "integer,load,lr,la,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
57 (const_string "integer"))
58
59 ;; Insn are devide in two classes:
60 ;; mem: Insn accesssing memory
61 ;; reg: Insn operands all in registers
62
63 (define_attr "atype" "reg,mem"
64 (const_string "reg"))
65
66 ;; Generic pipeline function unit.
67
68 (define_function_unit "integer" 1 0
69 (eq_attr "type" "integer") 1 1)
70
71 (define_function_unit "integer" 1 0
72 (eq_attr "type" "load") 1 1)
73
74 (define_function_unit "integer" 1 0
75 (eq_attr "type" "la") 1 1)
76
77 (define_function_unit "integer" 1 0
78 (eq_attr "type" "lr") 1 1)
79
80 (define_function_unit "integer" 1 0
81 (eq_attr "type" "store") 1 1)
82
83 (define_function_unit "integer" 1 0
84 (eq_attr "type" "jsr") 5 5)
85
86 (define_function_unit "integer" 1 0
87 (eq_attr "type" "imul") 7 7)
88
89 (define_function_unit "integer" 1 0
90 (eq_attr "type" "fmul") 6 6)
91
92 (define_function_unit "integer" 1 0
93 (eq_attr "type" "idiv") 33 33)
94
95 (define_function_unit "integer" 1 0
96 (eq_attr "type" "fdiv") 33 33)
97
98 (define_function_unit "integer" 1 0
99 (eq_attr "type" "o2") 2 2)
100
101 (define_function_unit "integer" 1 0
102 (eq_attr "type" "o3") 3 3)
103
104 (define_function_unit "integer" 1 0
105 (eq_attr "type" "other") 5 5)
106
107 ;; Operand type. Used to default length attribute values
108
109 (define_attr "op_type"
110 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
111 (const_string "RX"))
112
113 ;; Length in bytes.
114
115 (define_attr "length" ""
116 (cond [ (eq_attr "op_type" "E") (const_int 2)
117 (eq_attr "op_type" "RR") (const_int 2)
118 (eq_attr "op_type" "RX") (const_int 4)
119 (eq_attr "op_type" "RI") (const_int 4)
120 (eq_attr "op_type" "RRE") (const_int 4)
121 (eq_attr "op_type" "RS") (const_int 4)
122 (eq_attr "op_type" "RSI") (const_int 4)
123 (eq_attr "op_type" "RX") (const_int 4)
124 (eq_attr "op_type" "S") (const_int 4)
125 (eq_attr "op_type" "SI") (const_int 4)
126 (eq_attr "op_type" "SS") (const_int 6)
127 (eq_attr "op_type" "SSE") (const_int 6)
128 (eq_attr "op_type" "RXE") (const_int 6)
129 (eq_attr "op_type" "RSE") (const_int 6)
130 (eq_attr "op_type" "RIL") (const_int 6)]
131 (const_int 4)))
132
133 ;; Define attributes for `asm' insns.
134
135 (define_asm_attributes [(set_attr "type" "other")
136 (set_attr "op_type" "NN")])
137
138 ;;
139 ;; Condition Codes
140 ;;
141 ;
142 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
143 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
144 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
145 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
146 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
147
148 ; CCZ -> CCL / CCZ1
149 ; CCZ1 -> CCA/CCU/CCS/CCT
150 ; CCS -> CCA
151
152 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
153 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
154
155
156 ;;
157 ;;- Compare instructions.
158 ;;
159
160 (define_expand "cmpdi"
161 [(set (reg:CC 33)
162 (compare:CC (match_operand:DI 0 "register_operand" "")
163 (match_operand:DI 1 "general_operand" "")))]
164 "TARGET_64BIT"
165 "
166 {
167 s390_compare_op0 = operands[0];
168 s390_compare_op1 = operands[1];
169 DONE;
170 }")
171
172 (define_expand "cmpsi"
173 [(set (reg:CC 33)
174 (compare:CC (match_operand:SI 0 "register_operand" "")
175 (match_operand:SI 1 "general_operand" "")))]
176 ""
177 "
178 {
179 s390_compare_op0 = operands[0];
180 s390_compare_op1 = operands[1];
181 DONE;
182 }")
183
184 ;(define_expand "cmphi"
185 ; [(set (reg:CC 33)
186 ; (compare:CC (match_operand:HI 0 "register_operand" "")
187 ; (match_operand:HI 1 "general_operand" "")))]
188 ; ""
189 ; "
190 ;{
191 ; s390_compare_op0 = operands[0];
192 ; s390_compare_op1 = operands[1];
193 ; DONE;
194 ;}")
195
196 ;(define_expand "cmpqi"
197 ; [(set (reg:CC 33)
198 ; (compare:CC (match_operand:QI 0 "register_operand" "")
199 ; (match_operand:QI 1 "general_operand" "")))]
200 ; ""
201 ; "
202 ;{
203 ; s390_compare_op0 = operands[0];
204 ; s390_compare_op1 = operands[1];
205 ; DONE;
206 ;}")
207
208 (define_expand "cmpdf"
209 [(set (reg:CC 33)
210 (compare:CC (match_operand:DF 0 "register_operand" "")
211 (match_operand:DF 1 "general_operand" "")))]
212 "TARGET_HARD_FLOAT"
213 "
214 {
215 s390_compare_op0 = operands[0];
216 s390_compare_op1 = operands[1];
217 DONE;
218 }")
219
220 (define_expand "cmpsf"
221 [(set (reg:CC 33)
222 (compare:CC (match_operand:SF 0 "register_operand" "")
223 (match_operand:SF 1 "general_operand" "")))]
224 "TARGET_HARD_FLOAT"
225 "
226 {
227 s390_compare_op0 = operands[0];
228 s390_compare_op1 = operands[1];
229 DONE;
230 }")
231
232
233 ; DI instructions
234
235 (define_insn "*cmpdi_tm2"
236 [(set (reg 33)
237 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
238 (match_operand:DI 1 "const1_operand" "")
239 (match_operand:DI 2 "immediate_operand" "I"))
240 (const_int 0)))]
241 "s390_match_ccmode(insn, CCTmode) &&
242 INTVAL(operands[2]) >= 0 && INTVAL(operands[2]) < 64"
243 "*
244 {
245 if (INTVAL (operands[2]) > 47)
246 {
247 operands[1] = GEN_INT (1 << (63 - INTVAL(operands[2])));
248 return \"tmll\\t%0,%x1\";
249 }
250 else if (INTVAL (operands[2]) > 31)
251 {
252 operands[1] = GEN_INT (1 << (47 - INTVAL(operands[2])));
253 return \"tmlh\\t%0,%x1\";
254 }
255 else if (INTVAL (operands[2]) > 15)
256 {
257 operands[1] = GEN_INT (1 << (31 - INTVAL(operands[2])));
258 return \"tmhl\\t%0,%x1\";
259 }
260 operands[1] = GEN_INT (1 << (15 - INTVAL(operands[2])));
261 return \"tmhh\\t%0,%x1\";
262 }"
263 [(set_attr "op_type" "RX")
264 (set_attr "type" "integer")])
265
266
267 (define_insn "*cmpdi_tm"
268 [(set (reg 33)
269 (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
270 (match_operand:DI 1 "tmxx_operand" "Lm"))
271 (const_int 0)))]
272 "s390_match_ccmode(insn, CCTmode)"
273 "*
274 {
275 unsigned HOST_WIDEST_INT i;
276 if (GET_CODE (operands[1]) == MEM &&
277 GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF &&
278 CONSTANT_POOL_ADDRESS_P (XEXP (operands[1],0)))
279 {
280 operands[1] = get_pool_constant (XEXP (operands[1],0));
281 }
282
283 i = (unsigned HOST_WIDEST_INT) INTVAL (operands[1]);
284
285 if (i >= 0x1000000000000ULL)
286 {
287 operands[1] = GEN_INT (i >> 48);
288 return \"tmhh\\t%0,%x1\";
289 }
290 else if (i > 0x100000000ULL)
291 {
292 operands[1] = GEN_INT (i >> 32);
293 return \"tmhl\\t%0,%x1\";
294 }
295 else if (i >= 0x10000ULL)
296 {
297 operands[1] = GEN_INT (i >> 16);
298 return \"tmlh\\t%0,%x1\";
299 }
300 else
301 return \"tmll\\t%0,%x1\";
302 }"
303 [(set_attr "op_type" "RX")
304 (set_attr "type" "integer")])
305
306
307 (define_insn "*ltgr"
308 [(set (reg 33)
309 (compare (match_operand:DI 0 "register_operand" "d")
310 (match_operand:DI 1 "const0_operand" "")))
311 (set (match_operand:DI 2 "register_operand" "=d")
312 (match_dup 0))]
313 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
314 "ltgr\\t%2,%0"
315 [(set_attr "op_type" "RRE")
316 (set_attr "type" "integer")])
317
318 (define_insn "*cmpdi_ccs_0_64"
319 [(set (reg 33)
320 (compare (match_operand:DI 0 "register_operand" "d")
321 (match_operand:DI 1 "const0_operand" "")))]
322 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
323 "ltgr\\t%0,%0"
324 [(set_attr "op_type" "RRE")
325 (set_attr "type" "integer")])
326
327 (define_insn "*cmpdi_ccs_0_31"
328 [(set (reg 33)
329 (compare (match_operand:DI 0 "register_operand" "d")
330 (match_operand:DI 1 "const0_operand" "")))]
331 "s390_match_ccmode(insn, CCSmode)"
332 "srda\\t%0,0"
333 [(set_attr "op_type" "RS")
334 (set_attr "type" "integer")])
335
336 (define_insn "*cmpdi_ccs"
337 [(set (reg 33)
338 (compare (match_operand:DI 0 "register_operand" "d,d,d")
339 (match_operand:DI 1 "general_operand" "d,K,m")))]
340 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
341 "@
342 cgr\\t%0,%1
343 cghi\\t%0,%c1
344 cg\\t%0,%1"
345 [(set_attr "op_type" "RRE,RI,RXE")
346 (set_attr "atype" "reg,reg,mem")])
347
348 (define_insn "*cmpdi_ccu"
349 [(set (reg 33)
350 (compare (match_operand:DI 0 "register_operand" "d,d")
351 (match_operand:DI 1 "general_operand" "d,m")))]
352 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
353 "@
354 clgr\\t%0,%1
355 clg\\t%0,%1"
356 [(set_attr "op_type" "RRE,RXE")
357 (set_attr "atype" "reg,mem")])
358
359 (define_insn "*cmpdi_ccu_mem"
360 [(set (reg 33)
361 (compare (match_operand:DI 0 "s_operand" "oQ")
362 (match_operand:DI 1 "s_operand" "oQ")))]
363 "s390_match_ccmode(insn, CCUmode)"
364 "clc\\t%O0(8,%R0),%1"
365 [(set_attr "op_type" "SS")
366 (set_attr "atype" "mem")])
367
368 ; SI instructions
369
370 (define_insn "*cmpsi_cct"
371 [(set (reg 33)
372 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
373 (match_operand:SI 1 "const1_operand" "")
374 (match_operand:SI 2 "immediate_operand" "I"))
375 (const_int 0)))]
376 "s390_match_ccmode(insn, CCTmode) &&
377 INTVAL(operands[2]) >= 0 && INTVAL(operands[2]) < 32"
378 "*
379 {
380 if (INTVAL (operands[2]) > 15)
381 {
382 operands[1] = GEN_INT (1 << (31 - INTVAL(operands[2])));
383 return \"tml\\t%0,%x1\";
384 }
385 operands[1] = GEN_INT (1 << (15 - INTVAL(operands[2])));
386 return \"tmh\\t%0,%x1\";
387 }"
388 [(set_attr "op_type" "RI")])
389
390 (define_insn "*cmpsi_tm"
391 [(set (reg 33)
392 (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
393 (match_operand:SI 1 "tmxx_operand" "Lm"))
394 (const_int 0)))]
395 "s390_match_ccmode(insn, CCTmode)"
396 "*
397 {
398 unsigned long i;
399 if (GET_CODE (operands[1]) == MEM &&
400 GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF &&
401 CONSTANT_POOL_ADDRESS_P (XEXP (operands[1],0)))
402 {
403 operands[1] = get_pool_constant (XEXP (operands[1],0));
404 }
405
406 i = (unsigned long) INTVAL (operands[1]);
407 if (i > 0xffff)
408 {
409 operands[1] = GEN_INT (i / 0x10000);
410 return \"tmh\\t%0,%x1\";
411 }
412 return \"tml\\t%0,%x1\";
413 }"
414 [(set_attr "op_type" "RX")])
415
416 (define_insn "*ltr"
417 [(set (reg 33)
418 (compare (match_operand:SI 0 "register_operand" "d")
419 (match_operand:SI 1 "const0_operand" "")))
420 (set (match_operand:SI 2 "register_operand" "=d")
421 (match_dup 0))]
422 "s390_match_ccmode(insn, CCSmode)"
423 "ltr\\t%2,%0"
424 [(set_attr "op_type" "RR")])
425
426 (define_insn "*icm15"
427 [(set (reg 33)
428 (compare (match_operand:SI 0 "s_operand" "Qo")
429 (match_operand:SI 1 "const0_operand" "")))
430 (set (match_operand:SI 2 "register_operand" "=d")
431 (match_dup 0))]
432 "s390_match_ccmode(insn, CCSmode)"
433 "icm\\t%2,15,%0"
434 [(set_attr "op_type" "RS")
435 (set_attr "atype" "mem")])
436
437 (define_insn "*icm15_cconly"
438 [(set (reg 33)
439 (compare (match_operand:SI 0 "s_operand" "Qo")
440 (match_operand:SI 1 "const0_operand" "")))
441 (clobber (match_scratch:SI 2 "=d"))]
442 "s390_match_ccmode(insn, CCSmode)"
443 "icm\\t%2,15,%0"
444 [(set_attr "op_type" "RS")
445 (set_attr "atype" "mem")])
446
447 (define_insn "*cmpsi_ccs_0"
448 [(set (reg 33)
449 (compare (match_operand:SI 0 "register_operand" "d")
450 (match_operand:SI 1 "const0_operand" "")))]
451 "s390_match_ccmode(insn, CCSmode)"
452 "ltr\\t%0,%0"
453 [(set_attr "op_type" "RR")])
454
455 (define_insn "*cmpsidi_ccs"
456 [(set (reg 33)
457 (compare (match_operand:SI 0 "register_operand" "d")
458 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
459 "s390_match_ccmode(insn, CCSmode)"
460 "ch\\t%0,%1"
461 [(set_attr "op_type" "RR")
462 (set_attr "atype" "mem")])
463
464 (define_insn "*cmpsi_ccs"
465 [(set (reg 33)
466 (compare (match_operand:SI 0 "register_operand" "d,d,d")
467 (match_operand:SI 1 "general_operand" "d,K,m")))]
468 "s390_match_ccmode(insn, CCSmode)"
469 "@
470 cr\\t%0,%1
471 chi\\t%0,%c1
472 c\\t%0,%1"
473 [(set_attr "op_type" "RR,RI,RX")
474 (set_attr "atype" "reg,reg,mem")])
475
476 (define_insn "*cmpsi_ccu"
477 [(set (reg 33)
478 (compare (match_operand:SI 0 "register_operand" "d,d")
479 (match_operand:SI 1 "general_operand" "d,m")))]
480 "s390_match_ccmode(insn, CCUmode)"
481 "@
482 clr\\t%0,%1
483 cl\\t%0,%1"
484 [(set_attr "op_type" "RR,RX")
485 (set_attr "atype" "reg,mem")])
486
487 (define_insn "*cmpsi_ccu_mem"
488 [(set (reg 33)
489 (compare (match_operand:SI 0 "s_operand" "oQ")
490 (match_operand:SI 1 "s_operand" "oQ")))]
491 "s390_match_ccmode(insn, CCUmode)"
492 "clc\\t%O0(4,%R0),%1"
493 [(set_attr "op_type" "SS")
494 (set_attr "atype" "mem")])
495
496 ; HI instructions
497
498 (define_insn "*icm3"
499 [(set (reg 33)
500 (compare (match_operand:HI 0 "s_operand" "Qo")
501 (match_operand:HI 1 "const0_operand" "")))
502 (set (match_operand:HI 2 "register_operand" "=d")
503 (match_dup 0))]
504 "s390_match_ccmode(insn, CCSmode)"
505 "icm\\t%2,3,%0"
506 [(set_attr "op_type" "RS")
507 (set_attr "atype" "mem")])
508
509 (define_insn "*cmphi_cct_0"
510 [(set (reg 33)
511 (compare (match_operand:HI 0 "register_operand" "d")
512 (match_operand:HI 1 "const0_operand" "")))]
513 "s390_match_ccmode(insn, CCTmode)"
514 "tml\\t%0,65535"
515 [(set_attr "op_type" "RX")])
516
517 (define_insn "*cmphi_ccs_0"
518 [(set (reg 33)
519 (compare (match_operand:HI 0 "s_operand" "Qo")
520 (match_operand:HI 1 "const0_operand" "")))
521 (clobber (match_scratch:HI 2 "=d"))]
522 "s390_match_ccmode(insn, CCSmode)"
523 "icm\\t%2,3,%0"
524 [(set_attr "op_type" "RS")
525 (set_attr "atype" "mem")])
526
527 (define_insn "*cmphi_ccu"
528 [(set (reg 33)
529 (compare (match_operand:HI 0 "register_operand" "d")
530 (match_operand:HI 1 "s_operand" "Qo")))]
531 "s390_match_ccmode(insn, CCUmode)"
532 "clm\\t%0,3,%1"
533 [(set_attr "op_type" "RS")
534 (set_attr "atype" "mem")])
535
536 (define_insn "*cmphi_ccu_mem"
537 [(set (reg 33)
538 (compare (match_operand:HI 0 "s_operand" "oQ")
539 (match_operand:HI 1 "s_operand" "oQ")))]
540 "s390_match_ccmode(insn, CCUmode)"
541 "clc\\t%O0(2,%R0),%1"
542 [(set_attr "op_type" "SS")
543 (set_attr "atype" "mem")])
544
545
546 ; QI instructions
547
548 (define_insn "*icm1"
549 [(set (reg 33)
550 (compare (match_operand:QI 0 "s_operand" "Qo")
551 (match_operand:QI 1 "const0_operand" "")))
552 (set (match_operand:QI 2 "register_operand" "=d")
553 (match_dup 0))]
554 "s390_match_ccmode(insn, CCSmode)"
555 "icm\\t%2,1,%0"
556 [(set_attr "op_type" "RS")
557 (set_attr "atype" "mem")])
558
559 (define_insn "*tm_0"
560 [(set (reg 33)
561 (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
562 (match_operand:QI 1 "immediate_operand" "")))
563 (const_int 0)))]
564 "s390_match_ccmode(insn, CCTmode) &&
565 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
566 "tm\\t%0,%1"
567 [(set_attr "op_type" "RI")
568 (set_attr "atype" "mem")])
569
570 (define_insn "*cmpqi_cct_0"
571 [(set (reg 33)
572 (compare (match_operand:QI 0 "register_operand" "d")
573 (match_operand:QI 1 "const0_operand" "")))]
574 "s390_match_ccmode(insn, CCTmode)"
575 "tml\\t%0,255"
576 [(set_attr "op_type" "RI")])
577
578 (define_insn "*cmpqi_ccs_0"
579 [(set (reg 33)
580 (compare (match_operand:QI 0 "s_operand" "Qo")
581 (match_operand:QI 1 "const0_operand" "")))
582 (clobber (match_scratch:QI 2 "=d"))]
583 "s390_match_ccmode(insn, CCSmode)"
584 "icm\\t%2,1,%0"
585 [(set_attr "op_type" "RS")])
586
587 (define_insn "*cmpqi_ccu_0"
588 [(set (reg 33)
589 (compare (match_operand:QI 0 "s_operand" "Qo")
590 (match_operand:QI 1 "const0_operand" "")))]
591 "s390_match_ccmode(insn, CCUmode)"
592 "cli\\t%0,0"
593 [(set_attr "op_type" "SI")
594 (set_attr "atype" "mem")])
595
596 (define_insn "*cmpqi_ccu"
597 [(set (reg 33)
598 (compare (match_operand:QI 0 "register_operand" "d")
599 (match_operand:QI 1 "s_operand" "Qo")))]
600 "s390_match_ccmode(insn, CCUmode)"
601 "clm\\t%0,1,%1"
602 [(set_attr "op_type" "RS")
603 (set_attr "atype" "mem")])
604
605 (define_insn "*cmpqi_ccu_immed"
606 [(set (reg 33)
607 (compare (match_operand:QI 0 "s_operand" "Qo")
608 (match_operand:QI 1 "immediate_operand" "")))]
609 "s390_match_ccmode(insn, CCUmode) &&
610 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
611 "cli\\t%0,%1"
612 [(set_attr "op_type" "SI")
613 (set_attr "atype" "mem")])
614
615 (define_insn "*cmpqi_ccu_mem"
616 [(set (reg 33)
617 (compare (match_operand:QI 0 "s_operand" "oQ")
618 (match_operand:QI 1 "s_operand" "oQ")))]
619 "s390_match_ccmode(insn, CCUmode)"
620 "clc\\t%O0(1,%R0),%1"
621 [(set_attr "op_type" "SS")
622 (set_attr "atype" "mem")])
623
624
625 ; DF instructions
626
627 (define_insn "*cmpdf_ccs_0"
628 [(set (reg 33)
629 (compare (match_operand:DF 0 "register_operand" "f")
630 (match_operand:DF 1 "const0_operand" "")))]
631 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
632 "ltdbr\\t%0,%0"
633 [(set_attr "op_type" "RR")])
634
635 (define_insn "*cmpdf_ccs_0_ibm"
636 [(set (reg 33)
637 (compare (match_operand:DF 0 "register_operand" "f")
638 (match_operand:DF 1 "const0_operand" "")))]
639 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
640 "ltdr\\t%0,%0"
641 [(set_attr "op_type" "RR")])
642
643 (define_insn "*cmpdf_ccs"
644 [(set (reg 33)
645 (compare (match_operand:DF 0 "register_operand" "f,f")
646 (match_operand:DF 1 "nonimmediate_operand" "f,m")))]
647 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
648 "@
649 cdbr\\t%0,%1
650 cdb\\t%0,%1"
651 [(set_attr "op_type" "RR,RX")
652 (set_attr "atype" "reg,mem")])
653
654 (define_insn "*cmpdf_ccs_ibm"
655 [(set (reg 33)
656 (compare (match_operand:DF 0 "register_operand" "f,f")
657 (match_operand:DF 1 "nonimmediate_operand" "f,m")))]
658 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
659 "@
660 cdr\\t%0,%1
661 cd\\t%0,%1"
662 [(set_attr "op_type" "RR,RX")
663 (set_attr "atype" "reg,mem")])
664
665
666 ; SF instructions
667
668 (define_insn "*cmpsf_ccs_0"
669 [(set (reg 33)
670 (compare (match_operand:SF 0 "register_operand" "f")
671 (match_operand:SF 1 "const0_operand" "")))]
672 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
673 "ltebr\\t%0,%0"
674 [(set_attr "op_type" "RR")])
675
676 (define_insn "*cmpsf_ccs_0_ibm"
677 [(set (reg 33)
678 (compare (match_operand:SF 0 "register_operand" "f")
679 (match_operand:SF 1 "const0_operand" "")))]
680 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
681 "lter\\t%0,%0"
682 [(set_attr "op_type" "RR")])
683
684 (define_insn "*cmpsf_ccs"
685 [(set (reg 33)
686 (compare (match_operand:SF 0 "register_operand" "f,f")
687 (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
688 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
689 "@
690 cebr\\t%0,%1
691 ceb\\t%0,%1"
692 [(set_attr "op_type" "RR,RX")
693 (set_attr "atype" "reg,mem")])
694
695 (define_insn "*cmpsf_ccs"
696 [(set (reg 33)
697 (compare (match_operand:SF 0 "register_operand" "f,f")
698 (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
699 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
700 "@
701 cer\\t%0,%1
702 ce\\t%0,%1"
703 [(set_attr "op_type" "RR,RX")
704 (set_attr "atype" "reg,mem")])
705
706
707 ;;
708 ;;- Move instructions.
709 ;;
710
711 ;
712 ; movti instruction pattern(s).
713 ;
714
715 (define_insn "movti"
716 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,Q")
717 (match_operand:TI 1 "general_operand" "d,K,m,d,Q"))]
718 "TARGET_64BIT"
719 "*
720 {
721 switch (which_alternative)
722 {
723 case 0: /* d <- d */
724 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
725 return \"lgr\\t%M0,%M1\;lgr\\t%0,%1\";
726 else
727 return \"lgr\\t%0,%1\;lgr\\t%M0,%M1\";
728
729 case 1: /* d <- K */
730 if (INTVAL(operands[1]) < 0)
731 return \"lghi\\t%0,-1\;lghi\\t%M0,%h1\";
732 else
733 return \"lghi\\t%0,0\;lghi\\t%M0,%h1\";
734
735 case 2: /* d <- m */
736 if (s_operand (operands[1], GET_MODE (operands[1])))
737 return \"lmg\\t%0,%M0,%1\";
738 else
739 return \"la\\t%M0,%1\;lmg\\t%0,%M0,0(%M0)\";
740
741 case 3: /* m <- d */
742 if (!s_operand (operands[0], GET_MODE (operands[0])))
743 return \"stg\\t%1,%0\;stg\\t%M1,%M0\";
744 else
745 return \"stmg\\t%1,%M1,%0\";
746
747 case 4: /* m <- m */
748 return \"mvc\\t%O0(16,%R0),%1\";
749
750 default:
751 abort();
752 }
753 }"
754 [(set_attr "op_type" "NN,NN,RS,RS,SS")
755 (set_attr "atype" "reg,reg,mem,mem,mem")
756 (set_attr "type" "o2")
757 (set_attr "length" "12,8,10,10,*")])
758
759 ;
760 ; movdi instruction pattern(s).
761 ;
762
763 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
764 ;; move to get the address of the symbolic object from the GOT.
765
766 (define_expand "movdi"
767 [(set (match_operand:DI 0 "general_operand" "")
768 (match_operand:DI 1 "general_operand" ""))]
769 ""
770 "
771 {
772 if (CONSTANT_P (operands[1])
773 && !LEGITIMATE_CONSTANT_P (operands[1]))
774 operands[1] = force_const_mem (DImode, operands[1]);
775
776 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
777 emit_pic_move (operands, DImode);
778 }")
779
780 (define_insn "*movdi_64"
781 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,m,Q")
782 (match_operand:DI 1 "general_operand" "d,K,S,m,d,Q"))]
783 "TARGET_64BIT"
784 "@
785 lgr\\t%0,%1
786 lghi\\t%0,%h1
787 larl\\t%0,%1
788 lg\\t%0,%1
789 stg\\t%1,%0
790 mvc\\t%O0(8,%R0),%1"
791 [(set_attr "op_type" "RRE,RI,RIL,RXE,RXE,SS")
792 (set_attr "type" "integer,integer,la,integer,integer,integer")
793 (set_attr "atype" "reg,reg,reg,mem,mem,mem")])
794
795 (define_insn "*movdi_31"
796 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,Q")
797 (match_operand:DI 1 "general_operand" "d,K,m,d,Q"))]
798 "!TARGET_64BIT"
799 "*
800 {
801 switch (which_alternative)
802 {
803 case 0: /* d <- d */
804 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
805 return \"lr\\t%N0,%N1\;lr\\t%0,%1\";
806 else
807 return \"lr\\t%0,%1\;lr\\t%N0,%N1\";
808
809 case 1: /* d <- K */
810 if (INTVAL (operands[1]) < 0)
811 return \"lhi\\t%0,-1\;lhi\\t%N0,%h1\";
812 else
813 return \"lhi\\t%0,0\;lhi\\t%N0,%h1\";
814
815 case 2: /* d <- m */
816 if (s_operand (operands[1], GET_MODE (operands[1])))
817 return \"lm\\t%0,%N0,%1\";
818 else
819 return \"la\\t%N0,%1\;lm\\t%0,%N0,0(%N0)\";
820
821 case 3: /* m <- d */
822 if (s_operand (operands[0], GET_MODE (operands[0])))
823 return \"stm\\t%1,%N1,%0\";
824 else
825 return \"st\\t%1,%0\;st\\t%N1,%N0\";
826
827 case 4: /* m <- m */
828 return \"mvc\\t%O0(8,%R0),%1\";
829
830 default:
831 abort();
832 }
833 }"
834 [(set_attr "op_type" "NN,NN,RS,RS,SS")
835 (set_attr "atype" "reg,reg,mem,mem,mem")
836 (set_attr "type" "o2")
837 (set_attr "length" "4,8,8,8,*")])
838
839
840 ;
841 ; movsi instruction pattern(s).
842 ;
843
844 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
845 ;; move to get the address of the symbolic object from the GOT.
846
847 (define_expand "movsi"
848 [(set (match_operand:SI 0 "general_operand" "")
849 (match_operand:SI 1 "general_operand" ""))]
850 ""
851 "
852 {
853 if (CONSTANT_P (operands[1])
854 && !LEGITIMATE_CONSTANT_P (operands[1]))
855 operands[1] = force_const_mem (SImode, operands[1]);
856
857 if (flag_pic && SYMBOLIC_CONST (operands[1]))
858 emit_pic_move (operands, SImode);
859
860 /* expr.c tries to load an effective address using
861 force_reg. This fails because we don't have a
862 generic load_address pattern. Convert the move
863 to a proper arithmetic operation instead, unless
864 it is guaranteed to be OK. */
865 if (GET_CODE (operands[1]) == PLUS
866 && !legitimate_la_operand_p (operands[1]))
867 {
868 operands[1] = force_operand (operands[1], operands[0]);
869 if (operands[1] == operands[0])
870 DONE;
871 }
872 }")
873
874 (define_insn "*movsi"
875 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,Q")
876 (match_operand:SI 1 "general_operand" "d,K,m,d,Q"))]
877 ""
878 "@
879 lr\\t%0,%1
880 lhi\\t%0,%h1
881 l\\t%0,%1
882 st\\t%1,%0
883 mvc\\t%O0(4,%R0),%1"
884 [(set_attr "op_type" "RR,RI,RX,RX,SS")
885 (set_attr "type" "lr,*,load,store,store")
886 (set_attr "atype" "reg,reg,mem,mem,mem")])
887
888
889 ;
890 ; movhi instruction pattern(s).
891 ;
892
893 (define_insn "movhi"
894 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
895 (match_operand:HI 1 "r_or_x_or_im16_operand" "d,K,m,d"))]
896 ""
897 "@
898 lr\\t%0,%1
899 lhi\\t%0,%h1
900 lh\\t%0,%1
901 sth\\t%1,%0"
902 [(set_attr "op_type" "RR,RI,RX,RX")
903 (set_attr "atype" "reg,reg,mem,mem")])
904
905 ;
906 ; movqi instruction pattern(s).
907 ;
908
909 (define_insn "movqi_64"
910 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
911 (match_operand:QI 1 "general_operand" "d,K,m,d,n"))]
912 "TARGET_64BIT"
913 "@
914 lr\\t%0,%1
915 llill\\t%0,%x1
916 llgc\\t%0,%1
917 stc\\t%1,%0
918 mvi\\t%0,%b1"
919 [(set_attr "op_type" "RR,RI,RXE,RX,SI")
920 (set_attr "atype" "reg,reg,mem,mem,mem")])
921
922 (define_insn "movqi"
923 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
924 (match_operand:QI 1 "r_or_x_or_im16_operand" "d,n,m,d,n"))]
925 ""
926 "@
927 lr\\t%0,%1
928 lhi\\t%0,%c1
929 ic\\t%0,%1
930 stc\\t%1,%0
931 mvi\\t%0,%b1"
932 [(set_attr "op_type" "RR,RX,RX,RX,SI")
933 (set_attr "atype" "reg,reg,mem,mem,mem")])
934
935 ;
936 ; moveqstrictqi instruction pattern(s).
937 ;
938
939 (define_insn "*movstrictqi"
940 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
941 (match_operand:QI 1 "nonimmediate_operand" "m,d"))]
942 ""
943 "@
944 ic\\t%0,%1
945 stc\\t%1,%0"
946 [(set_attr "op_type" "RX,RX")
947 (set_attr "atype" "mem,mem")])
948
949
950 ;
951 ; movstricthi instruction pattern(s).
952 ;
953
954 (define_insn "*movstricthi"
955 [(set (strict_low_part (match_operand:HI 0 "r_or_s_operand" "+d,Q"))
956 (match_operand:HI 1 "r_or_s_operand" "Q,d"))
957 (clobber (reg:CC 33))]
958 ""
959 "@
960 icm\\t%0,3,%1
961 stcm\\t%1,3,%0"
962 [(set_attr "op_type" "RS,RS")
963 (set_attr "atype" "mem")])
964
965
966 ;
967 ; movstrictsi instruction pattern(s).
968 ;
969
970 (define_insn "movestrictsi"
971 [(set (strict_low_part (match_operand:SI 0 "nonimmediate_operand" "+d,d,m"))
972 (match_operand:SI 1 "nonimmediate_operand" "d,m,d"))]
973 "TARGET_64BIT"
974 "@
975 lr\\t%0,%1
976 l\\t%0,%1
977 st\\t%1,%0"
978 [(set_attr "op_type" "RR,RS,RS")
979 (set_attr "atype" "reg,mem,mem")])
980
981
982 ;
983 ; movdf instruction pattern(s).
984 ;
985
986 (define_expand "movdf"
987 [(set (match_operand:DF 0 "nonimmediate_operand" "")
988 (match_operand:DF 1 "general_operand" ""))]
989 ""
990 "
991 {
992 if (GET_CODE (operands[1]) == CONST_DOUBLE)
993 operands[1] = force_const_mem (DFmode, operands[1]);
994 }")
995
996 (define_insn "*movdf_64"
997 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
998 (match_operand:DF 1 "general_operand" "f,m,f,m,d,d,Q"))]
999 "TARGET_64BIT && TARGET_HARD_FLOAT"
1000 "@
1001 ldr\\t%0,%1
1002 ld\\t%0,%1
1003 std\\t%1,%0
1004 lg\\t%0,%1
1005 stg\\t%1,%0
1006 lgr\\t%0,%1
1007 mvc\\t%O0(8,%R0),%1"
1008 [(set_attr "op_type" "RR,RX,RX,RXE,RXE,RR,SS")
1009 (set_attr "atype" "reg,mem,mem,mem,mem,mem,mem")])
1010
1011 (define_insn "*movdf_31"
1012 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
1013 (match_operand:DF 1 "general_operand" "f,m,f,m,d,d,Q"))]
1014 "TARGET_HARD_FLOAT"
1015 "*
1016 {
1017 switch (which_alternative)
1018 {
1019 case 0: /* f <- f */
1020 return \"ldr\\t%0,%1\";
1021
1022 case 1: /* f <- m */
1023 return \"ld\\t%0,%1\";
1024
1025 case 2: /* m <- f */
1026 return \"std\\t%1,%0\";
1027
1028 case 3: /* d <- m */
1029 if (s_operand (operands[1], GET_MODE (operands[1])))
1030 return \"lm\\t%0,%N0,%1\";
1031 else
1032 return \"la\\t%N0,%1\;lm\\t%0,%N0,0(%N0)\";
1033
1034 case 4: /* m <- d */
1035 if (s_operand (operands[0], GET_MODE (operands[0])))
1036 return \"stm\\t%1,%N1,%0\";
1037 else
1038 return \"st\\t%1,%0\;st\\t%N1,%N0\";
1039
1040 case 5: /* d <- d */
1041 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
1042 return \"lr\\t%N0,%N1\;lr\\t%0,%1\";
1043 else
1044 return \"lr\\t%0,%1\;lr\\t%N0,%N1\";
1045
1046 case 6: /* m <- m */
1047 return \"mvc\\t%O0(8,%R0),%1\";
1048
1049 default:
1050 abort();
1051 }
1052 }"
1053 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,SS")
1054 (set_attr "atype" "reg,mem,mem,mem,mem,reg,mem")
1055 (set_attr "length" "*,*,*,*,*,4,*")])
1056
1057 (define_insn "*movdf_soft_64"
1058 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,m,d,Q")
1059 (match_operand:DF 1 "general_operand" "m,d,d,Q"))]
1060 "TARGET_64BIT && TARGET_SOFT_FLOAT"
1061 "@
1062 lg\\t%0,%1
1063 stg\\t%1,%0
1064 lgr\\t%0,%1
1065 mvc\\t%O0(8,%R0),%1"
1066 [(set_attr "op_type" "RXE,RXE,RR,SS")
1067 (set_attr "atype" "mem,mem,mem,mem")])
1068
1069 (define_insn "*movdf_soft_31"
1070 [(set (match_operand:DF 0 "nonimmediate_operand" "=!d,d,m,Q")
1071 (match_operand:DF 1 "general_operand" "!d,m,d,Q"))]
1072 "TARGET_SOFT_FLOAT"
1073 "*
1074 {
1075 switch (which_alternative)
1076 {
1077 case 0: /* d <- d */
1078 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
1079 return \"lr\\t%N0,%N1\;lr\\t%0,%1\";
1080 else
1081 return \"lr\\t%0,%1\;lr\\t%N0,%N1\";
1082
1083 case 1: /* d <- m */
1084 if (s_operand (operands[1], GET_MODE (operands[1])))
1085 return \"lm\\t%0,%N0,%1\";
1086 else
1087 return \"la\\t%N0,%1\;lm\\t%0,%N0,0(%N0)\";
1088
1089 case 2: /* m <- d */
1090 if (s_operand (operands[0], GET_MODE (operands[0])))
1091 return \"stm\\t%1,%N1,%0\";
1092 else
1093 return \"st\\t%1,%0\;st\\t%N1,%N0\";
1094
1095 case 3: /* m <- m */
1096 return \"mvc\\t%O0(8,%R0),%1\";
1097
1098 default:
1099 abort();
1100 }
1101 }"
1102 [(set_attr "op_type" "NN,RS,RS,SS")
1103 (set_attr "atype" "reg,mem,mem,mem")
1104 (set_attr "length" "8,*,*,*")])
1105
1106
1107 ;
1108 ; movsf instruction pattern(s).
1109 ;
1110
1111 (define_expand "movsf"
1112 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1113 (match_operand:SF 1 "general_operand" ""))]
1114 ""
1115 "
1116 {
1117 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1118 operands[1] = force_const_mem (SFmode, operands[1]);
1119 }")
1120
1121 (define_insn "*movsf_64"
1122 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
1123 (match_operand:SF 1 "general_operand" "f,m,f,m,d,d,Q"))]
1124 "TARGET_64BIT && TARGET_HARD_FLOAT"
1125 "@
1126 ler\\t%0,%1
1127 le\\t%0,%1
1128 ste\\t%1,%0
1129 llgf\\t%0,%1
1130 st\\t%1,%0
1131 lgr\\t%0,%1
1132 mvc\\t%O0(4,%R0),%1"
1133 [(set_attr "op_type" "RR,RX,RX,RXE,RX,RR,SS")
1134 (set_attr "atype" "reg,mem,mem,mem,mem,reg,mem")])
1135
1136 (define_insn "*movsf_31"
1137 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
1138 (match_operand:SF 1 "general_operand" "f,m,f,m,d,d,Q"))]
1139 "TARGET_HARD_FLOAT"
1140 "@
1141 ler\\t%0,%1
1142 le\\t%0,%1
1143 ste\\t%1,%0
1144 l\\t%0,%1
1145 st\\t%1,%0
1146 lr\\t%0,%1
1147 mvc\\t%O0(4,%R0),%1"
1148 [(set_attr "op_type" "RR,RX,RX,RX,RX,RR,SS")
1149 (set_attr "atype" "reg,mem,mem,mem,mem,reg,mem")])
1150
1151 (define_insn "*movsf_soft"
1152 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m,Q")
1153 (match_operand:SF 1 "general_operand" "d,m,d,Q"))]
1154 "TARGET_SOFT_FLOAT"
1155 "@
1156 lr\\t%0,%1
1157 l\\t%0,%1
1158 st\\t%1,%0
1159 mvc\\t%O0(4,%R0),%1"
1160 [(set_attr "op_type" "RR,RX,RX,SS")
1161 (set_attr "atype" "reg,mem,mem,mem")])
1162 ;
1163 ; load_multiple pattern(s).
1164 ;
1165
1166 (define_expand "load_multiple"
1167 [(match_par_dup 3 [(set (match_operand 0 "" "")
1168 (match_operand 1 "" ""))
1169 (use (match_operand 2 "" ""))])]
1170 ""
1171 "
1172 {
1173 int regno;
1174 int count;
1175 rtx from;
1176 int i;
1177
1178 /* Support only loading a constant number of fixed-point registers from
1179 memory and only bother with this if more than two */
1180 if (GET_CODE (operands[2]) != CONST_INT
1181 || INTVAL (operands[2]) <= 2
1182 || INTVAL (operands[2]) > 16
1183 || GET_CODE (operands[1]) != MEM
1184 || GET_CODE (operands[0]) != REG
1185 || REGNO (operands[0]) >= 16)
1186 FAIL;
1187
1188 count = INTVAL (operands[2]);
1189 regno = REGNO (operands[0]);
1190
1191 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1192 from = force_reg (Pmode, XEXP (operands[1], 0));
1193
1194 for (i = 0; i < count; i++)
1195 XVECEXP (operands[3], 0, i)
1196 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1197 change_address (operands[1], Pmode,
1198 plus_constant (from, i * 4)));
1199 }")
1200
1201 (define_insn "*load_multiple_di"
1202 [(match_parallel 0 "load_multiple_operation"
1203 [(set (match_operand:DI 1 "register_operand" "=r")
1204 (match_operand:DI 2 "s_operand" "oQ"))])]
1205 ""
1206 "*
1207 {
1208 int words = XVECLEN (operands[0], 0);
1209
1210 if (XVECLEN (operands[0], 0) == 1)
1211 return \"lg\\t%1,0(%2)\";
1212
1213 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1214 return \"lmg\\t%1,%0,%2\";
1215 }"
1216 [(set_attr "op_type" "RXE")
1217 (set_attr "atype" "mem")])
1218
1219 (define_insn "*load_multiple_si"
1220 [(match_parallel 0 "load_multiple_operation"
1221 [(set (match_operand:SI 1 "register_operand" "=r")
1222 (match_operand:SI 2 "s_operand" "oQ"))])]
1223 ""
1224 "*
1225 {
1226 int words = XVECLEN (operands[0], 0);
1227
1228 if (XVECLEN (operands[0], 0) == 1)
1229 return \"l\\t%1,0(%2)\";
1230
1231 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1232 return \"lm\\t%1,%0,%2\";
1233 }"
1234 [(set_attr "op_type" "RXE")
1235 (set_attr "atype" "mem")])
1236
1237 ;
1238 ; store multiple pattern(s).
1239 ;
1240
1241 (define_expand "store_multiple"
1242 [(match_par_dup 3 [(set (match_operand 0 "" "")
1243 (match_operand 1 "" ""))
1244 (use (match_operand 2 "" ""))])]
1245 ""
1246 "
1247 {
1248 int regno;
1249 int count;
1250 rtx to;
1251 int i;
1252
1253 /* Support only storing a constant number of fixed-point registers to
1254 memory and only bother with this if more than two. */
1255 if (GET_CODE (operands[2]) != CONST_INT
1256 || INTVAL (operands[2]) <= 2
1257 || INTVAL (operands[2]) > 16
1258 || GET_CODE (operands[0]) != MEM
1259 || GET_CODE (operands[1]) != REG
1260 || REGNO (operands[1]) >= 16)
1261 FAIL;
1262
1263 count = INTVAL (operands[2]);
1264 regno = REGNO (operands[1]);
1265
1266 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1267 to = force_reg (Pmode, XEXP (operands[0], 0));
1268
1269 for (i = 0; i < count; i++)
1270 XVECEXP (operands[3], 0, i)
1271 = gen_rtx_SET (VOIDmode,
1272 change_address (operands[0], Pmode,
1273 plus_constant (to, i * 4)),
1274 gen_rtx_REG (Pmode, regno + i));
1275 }")
1276
1277 (define_insn "*store_multiple_di"
1278 [(match_parallel 0 "store_multiple_operation"
1279 [(set (match_operand:DI 1 "s_operand" "=oQ")
1280 (match_operand:DI 2 "register_operand" "r"))])]
1281 ""
1282 "*
1283 {
1284 int words = XVECLEN (operands[0], 0);
1285
1286 if (XVECLEN (operands[0], 0) == 1)
1287 return \"stg\\t%1,0(%2)\";
1288
1289 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1290 return \"stmg\\t%2,%0,%1\";
1291 }"
1292 [(set_attr "op_type" "RXE")
1293 (set_attr "atype" "mem")
1294 (set_attr "type" "other")])
1295
1296
1297 (define_insn "*store_multiple_si"
1298 [(match_parallel 0 "store_multiple_operation"
1299 [(set (match_operand:SI 1 "s_operand" "=oQ")
1300 (match_operand:SI 2 "register_operand" "r"))])]
1301 ""
1302 "*
1303 {
1304 int words = XVECLEN (operands[0], 0);
1305
1306 if (XVECLEN (operands[0], 0) == 1)
1307 return \"st\\t%1,0(%2)\";
1308
1309 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1310 return \"stm\\t%2,%0,%1\";
1311 }"
1312 [(set_attr "op_type" "RXE")
1313 (set_attr "atype" "mem")
1314 (set_attr "type" "other")])
1315
1316 ;;
1317 ;; String instructions.
1318 ;;
1319
1320 ;
1321 ; movstrdi instruction pattern(s).
1322 ;
1323
1324 (define_expand "movstrdi"
1325 [(set (match_operand:BLK 0 "general_operand" "")
1326 (match_operand:BLK 1 "general_operand" ""))
1327 (use (match_operand:DI 2 "general_operand" ""))
1328 (match_operand 3 "" "")]
1329 "TARGET_64BIT"
1330 "
1331 {
1332 rtx addr0, addr1;
1333
1334 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1335 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1336
1337 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1338 {
1339 operands[0] = change_address (operands[0], VOIDmode, addr0);
1340 operands[1] = change_address (operands[1], VOIDmode, addr1);
1341 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1342
1343 emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1344 DONE;
1345 }
1346 else
1347 {
1348 if (TARGET_MVCLE)
1349 {
1350 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1351 rtx reg0 = gen_reg_rtx (TImode);
1352 rtx reg1 = gen_reg_rtx (TImode);
1353 rtx len = operands[2];
1354
1355 if (! CONSTANT_P (len))
1356 len = force_reg (DImode, len);
1357
1358 /* Load up the address+length pairs. */
1359
1360 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 0), addr0);
1361 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 8), len);
1362
1363 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 0), addr1);
1364 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 8), len);
1365
1366 /* MOVE */
1367 emit_insn (gen_movstrdi_64 (reg0, reg1));
1368 DONE;
1369 }
1370 else
1371 {
1372 rtx label = gen_label_rtx ();
1373 rtx reg0, reg1, len;
1374
1375 reg0 = gen_reg_rtx (DImode);
1376 reg1 = gen_reg_rtx (DImode);
1377 len = gen_reg_rtx (DImode);
1378
1379 emit_move_insn (len, operands[2]);
1380 emit_insn (gen_cmpdi (len, const0_rtx));
1381 emit_jump_insn (gen_beq (label));
1382 emit_move_insn (reg0, addr0);
1383 emit_move_insn (reg1, addr1);
1384 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1385 emit_insn (gen_movstrdix_64 (reg0, reg1, len));
1386 emit_label (label);
1387 DONE;
1388 }
1389 }
1390 }")
1391
1392 ;
1393 ; movstrsi instruction pattern(s).
1394 ;
1395
1396 (define_expand "movstrsi"
1397 [(set (match_operand:BLK 0 "general_operand" "")
1398 (match_operand:BLK 1 "general_operand" ""))
1399 (use (match_operand:SI 2 "general_operand" ""))
1400 (match_operand 3 "" "")]
1401 ""
1402 "
1403 {
1404 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1405 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1406
1407 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1408 {
1409 operands[0] = change_address (operands[0], VOIDmode, addr0);
1410 operands[1] = change_address (operands[1], VOIDmode, addr1);
1411 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1412
1413 emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1414 DONE;
1415 }
1416 else
1417 {
1418 if (TARGET_64BIT)
1419 FAIL;
1420
1421 if (TARGET_MVCLE)
1422 {
1423 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1424 rtx reg0 = gen_reg_rtx (DImode);
1425 rtx reg1 = gen_reg_rtx (DImode);
1426 rtx len = operands[2];
1427
1428
1429 if (! CONSTANT_P (len))
1430 len = force_reg (SImode, len);
1431
1432 /* Load up the address+length pairs. */
1433
1434 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 0), addr0);
1435 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 4), len);
1436
1437 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0), addr1);
1438 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 4), len);
1439
1440 /* MOVE */
1441 emit_insn (gen_movstrsi_31 (reg0, reg1));
1442 DONE;
1443 }
1444 else
1445 {
1446 rtx label = gen_label_rtx ();
1447 rtx reg0, reg1, len;
1448
1449 reg0 = gen_reg_rtx (SImode);
1450 reg1 = gen_reg_rtx (SImode);
1451 len = gen_reg_rtx (SImode);
1452
1453 emit_move_insn (len, operands[2]);
1454 emit_insn (gen_cmpsi (len, const0_rtx));
1455 emit_jump_insn (gen_beq (label));
1456 emit_move_insn (reg0, addr0);
1457 emit_move_insn (reg1, addr1);
1458 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1459 emit_insn (gen_movstrsix_31 (reg0, reg1, len));
1460 emit_label (label);
1461 DONE;
1462 }
1463 }
1464 }")
1465
1466 ; Move a block that is less than 256 bytes in length.
1467
1468 (define_insn "movstrsico"
1469 [(set (match_operand:BLK 0 "s_operand" "=oQ")
1470 (match_operand:BLK 1 "s_operand" "oQ"))
1471 (use (match_operand 2 "const_int_operand" "I"))]
1472 "((unsigned) INTVAL (operands[2]) < 256)"
1473 "mvc\\t%O0(%c2+1,%R0),%1"
1474 [(set_attr "op_type" "SS")
1475 (set_attr "atype" "mem")])
1476
1477 ; Move a block that is more than 256 bytes in lenght or length in register
1478
1479 (define_insn "movstrdix_64"
1480 [(set (mem:BLK (match_operand:DI 0 "register_operand" "a"))
1481 (mem:BLK (match_operand:DI 1 "register_operand" "a")))
1482 (use (match_operand:DI 2 "register_operand" "a"))
1483 (clobber (match_dup 0))
1484 (clobber (match_dup 1))
1485 (clobber (match_scratch:DI 3 "=&a"))
1486 (clobber (reg:CC 33))]
1487 ""
1488 "*
1489 {
1490 rtx xop[4];
1491 xop[0] = gen_label_rtx ();
1492 xop[1] = gen_label_rtx ();
1493 xop[2] = gen_label_rtx ();
1494 xop[3] = operands[3];
1495 output_asm_insn (\"srag\\t%3,%2,8\",operands);
1496 output_asm_insn (\"jz\\t%l1\",xop);
1497 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1498 CODE_LABEL_NUMBER (xop[0]));
1499 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\",operands);
1500 output_asm_insn (\"la\\t%0,256(%0)\",operands);
1501 output_asm_insn (\"la\\t%1,256(%1)\",operands);
1502 xop[3] = operands[3];
1503 output_asm_insn (\"brct\\t%3,%l0\",xop);
1504 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1505 CODE_LABEL_NUMBER (xop[1]));
1506 xop[3] = operands[3];
1507 output_asm_insn (\"bras\\t%3,%l2\",xop);
1508 output_asm_insn (\"mvc\\t0(1,%0),0(%1)\",operands);
1509 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1510 CODE_LABEL_NUMBER (xop[2]));
1511 return \"ex\\t%2,0(%3)\";
1512 }"
1513 [(set_attr "op_type" "NN")
1514 (set_attr "atype" "mem")
1515 (set_attr "length" "44")])
1516
1517 (define_insn "movstrsix_31"
1518 [(set (mem:BLK (match_operand:SI 0 "register_operand" "a"))
1519 (mem:BLK (match_operand:SI 1 "register_operand" "a")))
1520 (use (match_operand:SI 2 "register_operand" "a"))
1521 (clobber (match_dup 0))
1522 (clobber (match_dup 1))
1523 (clobber (match_scratch:SI 3 "=&a"))
1524 (clobber (reg:CC 33))]
1525 ""
1526 "*
1527 {
1528 rtx xop[4];
1529 xop[0] = gen_label_rtx ();
1530 xop[1] = gen_label_rtx ();
1531 xop[2] = gen_label_rtx ();
1532 xop[3] = operands[3];
1533 output_asm_insn (\"lr\\t%3,%2\",operands);
1534 output_asm_insn (\"sra\\t%3,8\",operands);
1535 output_asm_insn (\"jz\\t%l1\",xop);
1536 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1537 CODE_LABEL_NUMBER (xop[0]));
1538 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\",operands);
1539 output_asm_insn (\"la\\t%0,256(%0)\",operands);
1540 output_asm_insn (\"la\\t%1,256(%1)\",operands);
1541 xop[3] = operands[3];
1542 output_asm_insn (\"brct\\t%3,%l0\",xop);
1543 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1544 CODE_LABEL_NUMBER (xop[1]));
1545 xop[3] = operands[3];
1546 output_asm_insn (\"bras\\t%3,%l2\",xop);
1547 output_asm_insn (\"mvc\\t0(1,%0),0(%1)\",operands);
1548 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1549 CODE_LABEL_NUMBER (xop[2]));
1550 return \"ex\\t%2,0(%3)\";
1551 }"
1552 [(set_attr "op_type" "NN")
1553 (set_attr "length" "42")
1554 (set_attr "atype" "mem")])
1555
1556 ; Move a block that is larger than 255 bytes in length.
1557
1558 (define_insn "movstrdi_64"
1559 [(set (mem:BLK (subreg:DI (match_operand:TI 0 "register_operand" "d") 0))
1560 (mem:BLK (subreg:DI (match_operand:TI 1 "register_operand" "d") 0)))
1561 (clobber (match_dup 0))
1562 (clobber (match_dup 1))
1563 (clobber (reg:CC 33))]
1564 ""
1565 "mvcle\\t%0,%1,0\;jo\\t.-4"
1566 [(set_attr "op_type" "NN")
1567 (set_attr "atype" "mem")
1568 (set_attr "length" "8")])
1569
1570 (define_insn "movstrsi_31"
1571 [(set (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "d") 0))
1572 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "d") 0)))
1573 (clobber (match_dup 0))
1574 (clobber (match_dup 1))
1575 (clobber (reg:CC 33))]
1576 ""
1577 "mvcle\\t%0,%1,0\;jo\\t.-4"
1578 [(set_attr "op_type" "NN")
1579 (set_attr "atype" "mem")
1580 (set_attr "length" "8")])
1581
1582 ;
1583 ; clrstrdi instruction pattern(s).
1584 ;
1585
1586 (define_expand "clrstrdi"
1587 [(set (match_operand:BLK 0 "general_operand" "")
1588 (const_int 0))
1589 (use (match_operand:DI 1 "general_operand" ""))
1590 (match_operand 2 "" "")]
1591 "TARGET_64BIT"
1592 "
1593 {
1594 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1595
1596 operands[0] = change_address (operands[0], VOIDmode, addr);
1597
1598 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1599 {
1600 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1601 DONE;
1602 }
1603 else
1604 {
1605 rtx reg0 = gen_reg_rtx (TImode);
1606 rtx reg1 = gen_reg_rtx (TImode);
1607 rtx len = operands[1];
1608
1609 if (! CONSTANT_P (len))
1610 len = force_reg (DImode, len);
1611
1612 /* Load up the address+length pairs. */
1613
1614 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 0), addr);
1615 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 8), len);
1616
1617 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 8), const0_rtx);
1618
1619 /* Clear! */
1620 emit_insn (gen_clrstrsi_64 (reg0, reg1));
1621 DONE;
1622 }
1623 }")
1624
1625 ;
1626 ; clrstrsi instruction pattern(s).
1627 ;
1628
1629 (define_expand "clrstrsi"
1630 [(set (match_operand:BLK 0 "general_operand" "")
1631 (const_int 0))
1632 (use (match_operand:SI 1 "general_operand" ""))
1633 (match_operand 2 "" "")]
1634 "!TARGET_64BIT"
1635 "
1636 {
1637 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1638
1639 operands[0] = change_address (operands[0], VOIDmode, addr);
1640
1641 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1642 {
1643 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1644 DONE;
1645 }
1646 else
1647 {
1648 rtx reg0 = gen_reg_rtx (DImode);
1649 rtx reg1 = gen_reg_rtx (DImode);
1650 rtx len = operands[1];
1651
1652 if (! CONSTANT_P (len))
1653 len = force_reg (SImode, len);
1654
1655 /* Load up the address+length pairs. */
1656
1657 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 0), addr);
1658 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 4), len);
1659
1660 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 4), const0_rtx);
1661
1662 /* CLear! */
1663 emit_insn (gen_clrstrsi_31 (reg0, reg1));
1664 DONE;
1665 }
1666 }")
1667
1668 ; Clear memory with length less than 256 bytes
1669
1670 (define_insn "clrstrsico"
1671 [(set (match_operand:BLK 0 "s_operand" "=Qo")
1672 (const_int 0))
1673 (use (match_operand 1 "immediate_operand" "I"))
1674 (clobber (reg:CC 33))]
1675 ""
1676 "xc\\t%O0(%1,%R0),%0"
1677 [(set_attr "op_type" "RS")
1678 (set_attr "atype" "mem")])
1679
1680 ; Clear memory with length greater 256 bytes or lenght not constant
1681
1682 (define_insn "clrstrsi_64"
1683 [(set (mem:BLK (subreg:DI (match_operand:TI 0 "register_operand" "d") 0))
1684 (const_int 0))
1685 (use (match_operand:TI 1 "register_operand" "d"))
1686 (clobber (match_dup 0))
1687 (clobber (match_dup 1))
1688 (clobber (reg:CC 33))]
1689 "TARGET_64BIT"
1690 "mvcle\\t%0,%1,0\;jo\\t.-4"
1691 [(set_attr "op_type" "NN")
1692 (set_attr "atype" "mem")
1693 (set_attr "type" "other")
1694 (set_attr "length" "8")])
1695
1696 (define_insn "clrstrsi_31"
1697 [(set (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "d") 0))
1698 (const_int 0))
1699 (use (match_operand:DI 1 "register_operand" "d"))
1700 (clobber (match_dup 0))
1701 (clobber (match_dup 1))
1702 (clobber (reg:CC 33))]
1703 "!TARGET_64BIT"
1704 "mvcle\\t%0,%1,0\;jo\\t.-4"
1705 [(set_attr "op_type" "NN")
1706 (set_attr "atype" "mem")
1707 (set_attr "type" "other")
1708 (set_attr "length" "8")])
1709
1710 ;
1711 ; cmpstrdi instruction pattern(s).
1712 ;
1713
1714 (define_expand "cmpstrdi"
1715 [(set (match_operand:DI 0 "register_operand" "")
1716 (compare:DI (match_operand:BLK 1 "s_operand" "")
1717 (match_operand:BLK 2 "s_operand" "") ) )
1718 (use (match_operand:DI 3 "general_operand" ""))
1719 (use (match_operand:DI 4 "" ""))]
1720 "TARGET_64BIT"
1721 "
1722 {
1723 rtx addr0, addr1;
1724
1725 /* for pre/post increment */
1726 operands[1] = protect_from_queue (operands[1], 0);
1727 operands[2] = protect_from_queue (operands[2], 0);
1728 operands[3] = protect_from_queue (operands[3], 0);
1729
1730 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1731 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1732
1733 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1734 {
1735 if (INTVAL (operands[3]) == 0) {
1736 emit_move_insn (operands[0], operands[3]);
1737 DONE;
1738 }
1739
1740 operands[1] = change_address (operands[1], VOIDmode, addr0);
1741 operands[2] = change_address (operands[2], VOIDmode, addr1);
1742
1743 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1744 emit_insn (gen_cmpint_di (operands[0]));
1745 DONE;
1746 }
1747 else
1748 {
1749 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1750 rtx reg0 = gen_reg_rtx (TImode);
1751 rtx reg1 = gen_reg_rtx (TImode);
1752 rtx len = operands[3];
1753
1754 if (! CONSTANT_P (len))
1755 len = force_reg (DImode, len);
1756
1757 /* Load up the address+length pairs. */
1758 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 0), addr0);
1759 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 8), len);
1760
1761 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 0), addr1);
1762 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 8), len);
1763
1764 /* Compare! */
1765 emit_insn (gen_cmpstr_64 (reg0, reg1));
1766 emit_insn (gen_cmpint_di (operands[0]));
1767 DONE;
1768 }
1769 }")
1770
1771 ;
1772 ; cmpstrsi instruction pattern(s).
1773 ;
1774
1775 (define_expand "cmpstrsi"
1776 [(set (match_operand:SI 0 "register_operand" "")
1777 (compare:SI (match_operand:BLK 1 "s_operand" "")
1778 (match_operand:BLK 2 "s_operand" "") ) )
1779 (use (match_operand:SI 3 "general_operand" ""))
1780 (use (match_operand:SI 4 "" ""))]
1781 ""
1782 "
1783 {
1784 rtx addr0, addr1;
1785
1786 /* for pre/post increment */
1787 operands[1] = protect_from_queue (operands[1], 0);
1788 operands[2] = protect_from_queue (operands[2], 0);
1789 operands[3] = protect_from_queue (operands[3], 0);
1790
1791 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1792 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1793
1794 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1795 {
1796 if (INTVAL (operands[3]) == 0) {
1797 emit_move_insn (operands[0], operands[3]);
1798 DONE;
1799 }
1800
1801 operands[1] = change_address (operands[1], VOIDmode, addr0);
1802 operands[2] = change_address (operands[2], VOIDmode, addr1);
1803
1804 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1805 emit_insn (gen_cmpint_si (operands[0]));
1806 DONE;
1807 }
1808 else
1809 {
1810 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1811 rtx reg0, reg1;
1812 rtx len = operands[3];
1813
1814 if (TARGET_64BIT)
1815 {
1816 reg0 = gen_reg_rtx (TImode);
1817 reg1 = gen_reg_rtx (TImode);
1818 }
1819 else
1820 {
1821 reg0 = gen_reg_rtx (DImode);
1822 reg1 = gen_reg_rtx (DImode);
1823 }
1824
1825 if (! CONSTANT_P (len))
1826 len = force_reg (Pmode, len);
1827
1828 /* Load up the address+length pairs. */
1829 emit_move_insn (gen_rtx_SUBREG (Pmode, reg0, 0), addr0);
1830 emit_move_insn (gen_rtx_SUBREG (Pmode, reg0,
1831 GET_MODE_SIZE (Pmode)), len);
1832
1833 emit_move_insn (gen_rtx_SUBREG (Pmode, reg1, 0), addr1);
1834 emit_move_insn (gen_rtx_SUBREG (Pmode, reg1,
1835 GET_MODE_SIZE (Pmode)), len);
1836
1837 /* Compare! */
1838 if (TARGET_64BIT)
1839 emit_insn (gen_cmpstr_64 (reg0, reg1));
1840 else
1841 emit_insn (gen_cmpstr_31 (reg0, reg1));
1842
1843 emit_insn (gen_cmpint_si (operands[0]));
1844 DONE;
1845 }
1846 }")
1847
1848 ; Compare a block that is less than 256 bytes in length.
1849
1850 (define_insn "cmpstr_const"
1851 [(set (reg:CCS 33)
1852 (compare:CCS (match_operand:BLK 0 "s_operand" "oQ")
1853 (match_operand:BLK 1 "s_operand" "oQ")))
1854 (use (match_operand 2 "immediate_operand" "I"))]
1855 "(unsigned) INTVAL (operands[2]) < 256"
1856 "clc\\t%O0(%c2,%R0),%1"
1857 [(set_attr "op_type" "SS")
1858 (set_attr "atype" "mem")
1859 (set_attr "type" "other")])
1860
1861 ; Compare a block that is larger than 255 bytes in length.
1862
1863 (define_insn "cmpstr_64"
1864 [(set (reg:CCS 33)
1865 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 0 "register_operand" "d") 0))
1866 (mem:BLK (subreg:DI (match_operand:TI 1 "register_operand" "d") 0))))
1867 (clobber (subreg:DI (match_dup 0) 0))
1868 (clobber (subreg:DI (match_dup 0) 8))
1869 (clobber (subreg:DI (match_dup 1) 0))
1870 (clobber (subreg:DI (match_dup 1) 8))]
1871 "TARGET_64BIT"
1872 "clcl\\t%0,%1"
1873 [(set_attr "op_type" "RR")
1874 (set_attr "atype" "mem")
1875 (set_attr "type" "other")])
1876
1877 (define_insn "cmpstr_31"
1878 [(set (reg:CCS 33)
1879 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "d") 0))
1880 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "d") 0))))
1881 (clobber (subreg:SI (match_dup 0) 0))
1882 (clobber (subreg:SI (match_dup 0) 4))
1883 (clobber (subreg:SI (match_dup 1) 0))
1884 (clobber (subreg:SI (match_dup 1) 4))]
1885 "!TARGET_64BIT"
1886 "clcl\\t%0,%1"
1887 [(set_attr "op_type" "RR")
1888 (set_attr "atype" "mem")
1889 (set_attr "type" "other")])
1890
1891 ; Convert condition code to integer in range (-1, 0, 1)
1892
1893 (define_insn "cmpint_si"
1894 [(set (match_operand:SI 0 "register_operand" "=d")
1895 (compare:SI (reg:CCS 33) (const_int 0)))]
1896 ""
1897 "*
1898 {
1899 output_asm_insn (\"lhi\\t%0,1\", operands);
1900 output_asm_insn (\"jh\\t.+12\", operands);
1901 output_asm_insn (\"jl\\t.+6\", operands);
1902 output_asm_insn (\"sr\\t%0,%0\", operands);
1903 return \"lcr\\t%0,%0\";
1904 }"
1905 [(set_attr "op_type" "NN")
1906 (set_attr "length" "16")
1907 (set_attr "atype" "reg")
1908 (set_attr "type" "other")])
1909
1910 (define_insn "cmpint_di"
1911 [(set (match_operand:DI 0 "register_operand" "=d")
1912 (compare:DI (reg:CCS 33) (const_int 0)))]
1913 "TARGET_64BIT"
1914 "*
1915 {
1916 output_asm_insn (\"lghi\\t%0,1\", operands);
1917 output_asm_insn (\"jh\\t.+12\", operands);
1918 output_asm_insn (\"jl\\t.+6\", operands);
1919 output_asm_insn (\"sgr\\t%0,%0\", operands);
1920 return \"lcgr\\t%0,%0\";
1921 }"
1922 [(set_attr "op_type" "NN")
1923 (set_attr "length" "22")
1924 (set_attr "atype" "reg")
1925 (set_attr "type" "other")])
1926
1927 ;;
1928 ;;- Conversion instructions.
1929 ;;
1930
1931 ;
1932 ; extendsidi2 instruction pattern(s).
1933 ;
1934
1935 (define_insn "extendsidi2"
1936 [(set (match_operand:DI 0 "register_operand" "=d,d")
1937 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
1938 "TARGET_64BIT"
1939 "@
1940 lgfr\\t%0,%1
1941 lgf\\t%0,%1"
1942 [(set_attr "op_type" "RRE,RXE")
1943 (set_attr "atype" "reg,mem")])
1944
1945
1946 ;
1947 ; extendhidi2 instruction pattern(s).
1948 ;
1949
1950 (define_insn "extendhidi2"
1951 [(set (match_operand:DI 0 "register_operand" "=d")
1952 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))
1953 (clobber (reg:CC 33))]
1954 "TARGET_64BIT"
1955 "sllg\\t%0,%1,48\;srag\\t%0,%0,48"
1956 [(set_attr "op_type" "NN")
1957 (set_attr "length" "12")
1958 (set_attr "type" "o2")])
1959
1960 ;
1961 ; extendqidi2 instruction pattern(s).
1962 ;
1963
1964 (define_insn "extendqidi2"
1965 [(set (match_operand:DI 0 "register_operand" "=d")
1966 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))
1967 (clobber (reg:CC 33))]
1968 "TARGET_64BIT"
1969 "sllg\\t%0,%1,56\;srag\\t%0,%0,56"
1970 [(set_attr "op_type" "NN")
1971 (set_attr "length" "12")
1972 (set_attr "type" "o2")])
1973
1974 ;
1975 ; extendhisi2 instruction pattern(s).
1976 ;
1977
1978 (define_insn "extendhisi2"
1979 [(set (match_operand:SI 0 "register_operand" "=d,!d,d")
1980 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,d,m")))
1981 (clobber (reg:CC 33))]
1982 ""
1983 "@
1984 sll\\t%1,16\;sra\\t%1,16
1985 lr\\t%0,%1\;sll\\t%0,16\;sra\\t%0,16
1986 lh\\t%0,%1"
1987 [(set_attr "op_type" "NN,NN,RX")
1988 (set_attr "type" "o2,o3,integer")
1989 (set_attr "atype" "reg,reg,mem")
1990 (set_attr "length" "8,10,*")])
1991
1992
1993 ;
1994 ; extendqisi2 instruction pattern(s).
1995 ;
1996
1997 (define_insn "extendqisi2"
1998 [(set (match_operand:SI 0 "register_operand" "=d,d")
1999 (sign_extend:SI (match_operand:QI 1 "r_or_s_operand" "0,Q")))
2000 (clobber (reg:CC 33))]
2001 ""
2002 "@
2003 sll\\t%0,24\;sra\\t%0,24
2004 icm\\t%0,8,%1\;sra\\t%0,24"
2005 [(set_attr "op_type" "NN,NN")
2006 (set_attr "type" "o2")
2007 (set_attr "atype" "reg,mem")
2008 (set_attr "length" "8,8")])
2009
2010
2011 ;
2012 ; extendqihi2 instruction pattern(s).
2013 ;
2014
2015 (define_insn "extendqihi2"
2016 [(set (match_operand:HI 0 "register_operand" "=d,d")
2017 (sign_extend:HI (match_operand:QI 1 "r_or_s_operand" "0,Q")))
2018 (clobber (reg:CC 33))]
2019 ""
2020 "@
2021 sll\\t%0,24\;sra\\t%0,24
2022 icm\\t%0,8,%1\;sra\\t%0,24"
2023 [(set_attr "op_type" "NN,NN")
2024 (set_attr "type" "o2")
2025 (set_attr "atype" "reg,mem")
2026 (set_attr "length" "8,8")])
2027
2028
2029 ;
2030 ; zero_extendsidi2 instruction pattern(s).
2031 ;
2032
2033 (define_insn "zero_extendsidi2"
2034 [(set (match_operand:DI 0 "register_operand" "=d,d")
2035 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2036 "TARGET_64BIT"
2037 "@
2038 llgfr\\t%0,%1
2039 llgf\\t%0,%1"
2040 [(set_attr "op_type" "RRE,RXE")
2041 (set_attr "atype" "reg,mem")])
2042
2043
2044 ;
2045 ; zero_extendhidi2 instruction pattern(s).
2046 ;
2047
2048 (define_insn "zero_extendhidi2"
2049 [(set (match_operand:DI 0 "register_operand" "=!d,d")
2050 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2051 "TARGET_64BIT"
2052 "@
2053 llgfr\\t%0,%1\;iilh\\t%0,0
2054 llgh\\t%0,%1"
2055 [(set_attr "op_type" "NN,RXE")
2056 (set_attr "type" "o2,integer")
2057 (set_attr "atype" "reg,mem")
2058 (set_attr "length" "12,*")])
2059
2060 ;
2061 ; zero_extendqidi2 instruction pattern(s)
2062 ;
2063
2064 (define_insn "zero_extendqidi2"
2065 [(set (match_operand:DI 0 "register_operand" "=!d,d")
2066 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))
2067 (clobber (reg:CC 33))]
2068 "TARGET_64BIT"
2069 "@
2070 sllg\\t%0,%1,56\;srlg\\t%0,%0,56
2071 llgc\\t%0,%1"
2072 [(set_attr "op_type" "NN,RXE")
2073 (set_attr "type" "o2,integer")
2074 (set_attr "atype" "reg,mem")
2075 (set_attr "length" "12,*")])
2076
2077
2078 ;
2079 ; zero_extendhisi2 instruction pattern(s).
2080 ;
2081
2082 (define_expand "zero_extendhisi2"
2083 [(set (match_operand:SI 0 "register_operand" "")
2084 (zero_extend:SI (match_operand:HI 1 "r_or_s_operand" "")))]
2085 ""
2086 "
2087 {
2088 if (!TARGET_64BIT)
2089 {
2090 emit_insn (gen_zero_extendhisi2_31 (operands[0], operands[1],
2091 force_const_mem (SImode, const0_rtx)));
2092 DONE;
2093 }
2094 }")
2095
2096 (define_insn "*zero_extendhisi2_64"
2097 [(set (match_operand:SI 0 "register_operand" "=d,d")
2098 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,m")))]
2099 "TARGET_64BIT"
2100 "@
2101 iilh\\t%0,0
2102 llgh\\t%0,%1"
2103 [(set_attr "op_type" "RI,RXE")
2104 (set_attr "atype" "reg,mem")])
2105
2106 (define_insn "zero_extendhisi2_31"
2107 [(set (match_operand:SI 0 "register_operand" "=d,d")
2108 (zero_extend:SI (match_operand:HI 1 "r_or_s_operand" "0,Q")))
2109 (use (match_operand:SI 2 "memory_operand" "m,m"))
2110 (clobber (reg:CC 33))]
2111 ""
2112 "@
2113 icm\\t%0,12,%2
2114 icm\\t%0,12,%1\;srl\\t%0,16"
2115 [(set_attr "op_type" "RX,NN")
2116 (set_attr "type" "integer,o2")
2117 (set_attr "atype" "reg,mem")
2118 (set_attr "length" "*,8")])
2119
2120
2121 ;
2122 ; zero_extendqisi2 instruction pattern(s).
2123 ;
2124
2125 (define_insn "*zero_extendqisi2_mem_31"
2126 [(set (match_operand:SI 0 "register_operand" "=&d")
2127 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))
2128 (use (match_operand:SI 2 "memory_operand" "m" ))
2129 (clobber (reg:CC 33))]
2130 ""
2131 "sr\\t%0,%0\;ic\\t%0,%1"
2132 [(set_attr "op_type" "NN")
2133 (set_attr "type" "o2")
2134 (set_attr "atype" "mem")
2135 (set_attr "length" "6")])
2136
2137 (define_insn "zero_extendqisi2_reg_31"
2138 [(set (match_operand:SI 0 "register_operand" "=d")
2139 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))
2140 (use (match_operand:SI 2 "memory_operand" "m" ))
2141 (clobber (reg:CC 33))]
2142 ""
2143 "icm\\t%0,14,%2"
2144 [(set_attr "op_type" "RX")
2145 (set_attr "atype" "mem")])
2146
2147 (define_insn "*zero_extendqisi2_64"
2148 [(set (match_operand:SI 0 "register_operand" "=!d,d")
2149 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2150 "TARGET_64BIT"
2151 "@
2152 sllg\\t%0,%1,56\;srlg\\t%0,%0,56
2153 llgc\\t%0,%1"
2154 [(set_attr "op_type" "NN,RXE")
2155 (set_attr "type" "o2,integer")
2156 (set_attr "atype" "reg,mem")
2157 (set_attr "length" "12,*")])
2158
2159 (define_expand "zero_extendqisi2"
2160 [(set (match_operand:SI 0 "register_operand" "")
2161 (zero_extend:SI (match_operand:QI 1 "r_or_s_operand" "")))]
2162 ""
2163 "
2164 {
2165 if (!TARGET_64BIT)
2166 {
2167 emit_insn (gen_zero_extendqisi2_reg_31 (operands[0], operands[1],
2168 force_const_mem (SImode, const0_rtx)));
2169 DONE;
2170 }
2171 }")
2172
2173
2174 ;
2175 ; zero_extendqihi2 instruction pattern(s).
2176 ;
2177
2178 (define_insn "zero_extendqihi2_64"
2179 [(set (match_operand:HI 0 "register_operand" "=d,d")
2180 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))
2181 (clobber (reg:CC 33))]
2182 "TARGET_64BIT"
2183 "@
2184 nill\\t%0,0x00FF
2185 llgc\\t%0,%1"
2186 [(set_attr "op_type" "RI,RXE")
2187 (set_attr "atype" "reg,mem")])
2188
2189 (define_insn "zero_extendqihi2_31"
2190 [(set (match_operand:HI 0 "register_operand" "=d,&d")
2191 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))
2192 (use (match_operand:SI 2 "memory_operand" "m,m"))
2193 (clobber (reg:CC 33))]
2194 ""
2195 "@
2196 icm\\t%0,14,%2
2197 sr\\t%0,%0\;ic\\t%0,%1"
2198 [(set_attr "op_type" "RX,NN")
2199 (set_attr "atype" "reg,mem")
2200 (set_attr "length" "*,8")])
2201
2202 (define_expand "zero_extendqihi2"
2203 [(set (match_operand:HI 0 "register_operand" "")
2204 (zero_extend:HI (match_operand:QI 1 "general_operand" "")))]
2205 ""
2206 "
2207 {
2208 if (!TARGET_64BIT)
2209 {
2210 emit_insn (gen_zero_extendqihi2_31 (operands[0], operands[1],
2211 force_const_mem (SImode, const0_rtx)));
2212 DONE;
2213 }
2214 else
2215 {
2216 emit_insn (gen_zero_extendqihi2_64 (operands[0], operands[1]));
2217 DONE;
2218 }
2219 }")
2220
2221
2222 ;
2223 ; truncdisi2 instruction pattern(s).
2224 ;
2225
2226 (define_insn "truncdisi2"
2227 [(set (match_operand:SI 0 "register_operand" "=d")
2228 (truncate:SI (match_operand:DI 1 "register_operand" "d")))]
2229 "TARGET_64BIT"
2230 "llgfr\\t%0,%1"
2231 [(set_attr "op_type" "RRE")])
2232
2233
2234 ;
2235 ; truncdihi2 instruction pattern(s).
2236 ;
2237
2238 (define_insn "truncdihi2"
2239 [(set (match_operand:HI 0 "register_operand" "=d")
2240 (truncate:HI (match_operand:DI 1 "register_operand" "d")))]
2241 "TARGET_64BIT"
2242 "llgfr\\t%0,%1\;iilh\\t%0,0"
2243 [(set_attr "op_type" "NN")
2244 (set_attr "length" "10")])
2245
2246
2247 ;
2248 ; truncdiqi2 instruction pattern(s).
2249 ;
2250
2251 (define_insn "truncdiqi2"
2252 [(set (match_operand:QI 0 "register_operand" "=d")
2253 (truncate:QI (match_operand:DI 1 "register_operand" "d")))
2254 (clobber (reg:CC 33))]
2255 "TARGET_64BIT"
2256 "sllg\\t%0,%1,56\;srlg\\t%0,%0,56"
2257 [(set_attr "op_type" "NN")
2258 (set_attr "type" "o2")
2259 (set_attr "length" "12")])
2260
2261
2262 ;
2263 ; truncsihi2 instruction pattern(s).
2264 ;
2265
2266 (define_expand "truncsihi2"
2267 [(set (match_operand:HI 0 "register_operand" "")
2268 (truncate:HI (match_operand:SI 1 "register_operand" "")))]
2269 ""
2270 "
2271 {
2272 if (!TARGET_64BIT)
2273 {
2274 emit_insn (gen_do_truncsihi2 (operands[0], operands[1],
2275 force_const_mem (SImode, const0_rtx)));
2276 DONE;
2277 }
2278 }")
2279
2280
2281 (define_insn "do_truncsihi2"
2282 [(set (match_operand:HI 0 "register_operand" "=d")
2283 (truncate:HI (match_operand:SI 1 "register_operand" "0")))
2284 (use (match_operand:SI 2 "memory_operand" "m"))
2285 (clobber (reg:CC 33))]
2286 ""
2287 "icm\\t%0,12,%2"
2288 [(set_attr "op_type" "RX")])
2289
2290 (define_insn "*truncsihi2_64"
2291 [(set (match_operand:HI 0 "register_operand" "=d")
2292 (truncate:HI (match_operand:SI 1 "register_operand" "0")))]
2293 "TARGET_64BIT"
2294 "iilh\\t%0,0"
2295 [(set_attr "op_type" "RI")])
2296
2297
2298 ;
2299 ; truncsiqi2 instruction pattern(s).
2300 ;
2301
2302 (define_insn "truncsiqi2"
2303 [(set (match_operand:QI 0 "register_operand" "=d")
2304 (truncate:QI (match_operand:SI 1 "register_operand" "0")))
2305 (clobber (reg:CC 33))]
2306 "TARGET_64BIT"
2307 "iilh\\t%0,0\;nill\\t%0,0x00FF"
2308 [(set_attr "op_type" "NN")
2309 (set_attr "type" "o2")
2310 (set_attr "length" "8")])
2311
2312
2313 ;
2314 ; trunchiqi2 instruction pattern(s).
2315 ;
2316
2317 (define_insn "trunchiqi2"
2318 [(set (match_operand:QI 0 "register_operand" "=d")
2319 (truncate:QI (match_operand:HI 1 "register_operand" "0")))
2320 (clobber (reg:CC 33))]
2321 "TARGET_64BIT"
2322 "nill\\t%0,0x00FF"
2323 [(set_attr "op_type" "RI")])
2324
2325
2326 ;
2327 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2328 ;
2329
2330 (define_expand "fixuns_truncdfdi2"
2331 [(set (match_operand:DI 0 "register_operand" "")
2332 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2333 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2334 "
2335 {
2336 rtx label1 = gen_label_rtx ();
2337 rtx label2 = gen_label_rtx ();
2338 rtx temp = gen_reg_rtx (DFmode);
2339 operands[1] = force_reg (DFmode, operands[1]);
2340
2341 emit_insn (gen_cmpdf (operands[1], force_const_mem (DFmode,
2342 CONST_DOUBLE_FROM_REAL_VALUE (0x8000000000000000ULL, DFmode))));
2343 emit_jump_insn (gen_blt (label1));
2344
2345 emit_insn (gen_subdf3 (temp, operands[1], force_const_mem (DFmode,
2346 CONST_DOUBLE_FROM_REAL_VALUE (0x10000000000000000ULL, DFmode))));
2347 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2348 emit_jump (label2);
2349
2350 emit_label (label1);
2351 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2352 emit_label (label2);
2353 DONE;
2354 }")
2355
2356 (define_expand "fix_truncdfdi2"
2357 [(set (match_operand:DI 0 "register_operand" "")
2358 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2359 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2360 "
2361 {
2362 operands[1] = force_reg (DFmode, operands[1]);
2363 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2364 DONE;
2365 }")
2366
2367 (define_insn "fix_truncdfdi2_ieee"
2368 [(set (match_operand:DI 0 "register_operand" "=d")
2369 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2370 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2371 (clobber (reg:CC 33))]
2372 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2373 "cgdbr\\t%0,%h2,%1"
2374 [(set_attr "op_type" "RRE")
2375 (set_attr "type" "other")])
2376
2377 ;
2378 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2379 ;
2380
2381 (define_expand "fixuns_truncdfsi2"
2382 [(set (match_operand:SI 0 "register_operand" "")
2383 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2384 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2385 "
2386 {
2387 rtx label1 = gen_label_rtx ();
2388 rtx label2 = gen_label_rtx ();
2389 rtx temp = gen_reg_rtx (DFmode);
2390
2391 operands[1] = force_reg (DFmode,operands[1]);
2392 emit_insn (gen_cmpdf (operands[1], force_const_mem (DFmode,
2393 CONST_DOUBLE_FROM_REAL_VALUE (0x80000000ULL, DFmode))));
2394 emit_jump_insn (gen_blt (label1));
2395 emit_insn (gen_subdf3 (temp, operands[1], force_const_mem (DFmode,
2396 CONST_DOUBLE_FROM_REAL_VALUE (0x100000000ULL, DFmode))));
2397 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2398 emit_jump (label2);
2399
2400 emit_label (label1);
2401 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2402 emit_label (label2);
2403 DONE;
2404 }")
2405
2406 (define_expand "fix_truncdfsi2"
2407 [(set (match_operand:SI 0 "register_operand" "")
2408 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2409 "TARGET_HARD_FLOAT"
2410 "
2411 {
2412 if (TARGET_IBM_FLOAT)
2413 {
2414 /* This is the algorithm from POP chapter A.5.7.2. */
2415
2416 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2417 rtx two31r = force_const_mem (DFmode,
2418 gen_rtx (CONST_DOUBLE, VOIDmode, cc0_rtx,
2419 0x08000000, 0x4F000000));
2420 rtx two32 = force_const_mem (DFmode,
2421 gen_rtx (CONST_DOUBLE, VOIDmode, cc0_rtx,
2422 0x0, 0x4E000001));
2423
2424 operands[1] = force_reg (DFmode, operands[1]);
2425 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2426 two31r, two32, temp));
2427 }
2428 else
2429 {
2430 operands[1] = force_reg (DFmode, operands[1]);
2431 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2432 }
2433
2434 DONE;
2435 }")
2436
2437 (define_insn "fix_truncdfsi2_ieee"
2438 [(set (match_operand:SI 0 "register_operand" "=d")
2439 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2440 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2441 (clobber (reg:CC 33))]
2442 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2443 "cfdbr\\t%0,%h2,%1"
2444 [(set_attr "op_type" "RRE")
2445 (set_attr "type" "other" )])
2446
2447 (define_insn "fix_truncdfsi2_ibm"
2448 [(set (match_operand:SI 0 "register_operand" "=d")
2449 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2450 (use (match_operand:DF 2 "memory_operand" "m"))
2451 (use (match_operand:DF 3 "memory_operand" "m"))
2452 (use (match_operand:BLK 4 "memory_operand" "m"))
2453 (clobber (reg:CC 33))]
2454 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2455 "*
2456 {
2457 output_asm_insn (\"sd\\t%1,%2\", operands);
2458 output_asm_insn (\"aw\\t%1,%3\", operands);
2459 output_asm_insn (\"std\\t%1,%4\", operands);
2460 output_asm_insn (\"xi\\t%N4,128\", operands);
2461 return \"l\\t%0,%N4\";
2462 }"
2463 [(set_attr "op_type" "NN")
2464 (set_attr "type" "other")
2465 (set_attr "length" "20")])
2466
2467 ;
2468 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2469 ;
2470
2471 (define_expand "fixuns_truncsfdi2"
2472 [(set (match_operand:DI 0 "register_operand" "")
2473 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2474 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2475 "
2476 {
2477 rtx label1 = gen_label_rtx ();
2478 rtx label2 = gen_label_rtx ();
2479 rtx temp = gen_reg_rtx (SFmode);
2480
2481 operands[1] = force_reg (SFmode, operands[1]);
2482 emit_insn (gen_cmpsf (operands[1], force_const_mem (SFmode,
2483 CONST_DOUBLE_FROM_REAL_VALUE (0x8000000000000000ULL, SFmode))));
2484 emit_jump_insn (gen_blt (label1));
2485
2486 emit_insn (gen_subsf3 (temp, operands[1], force_const_mem (SFmode,
2487 CONST_DOUBLE_FROM_REAL_VALUE (0x10000000000000000ULL, SFmode))));
2488 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2489 emit_jump (label2);
2490
2491 emit_label (label1);
2492 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2493 emit_label (label2);
2494 DONE;
2495 }")
2496
2497 (define_expand "fix_truncsfdi2"
2498 [(set (match_operand:DI 0 "register_operand" "")
2499 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2500 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2501 "
2502 {
2503 operands[1] = force_reg (SFmode, operands[1]);
2504 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2505 DONE;
2506 }")
2507
2508 (define_insn "fix_truncsfdi2_ieee"
2509 [(set (match_operand:DI 0 "register_operand" "=d")
2510 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2511 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2512 (clobber (reg:CC 33))]
2513 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2514 "cgebr\\t%0,%h2,%1"
2515 [(set_attr "op_type" "RRE")
2516 (set_attr "type" "other")])
2517
2518 ;
2519 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2520 ;
2521
2522 (define_expand "fixuns_truncsfsi2"
2523 [(set (match_operand:SI 0 "register_operand" "")
2524 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2525 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2526 "
2527 {
2528 rtx label1 = gen_label_rtx ();
2529 rtx label2 = gen_label_rtx ();
2530 rtx temp = gen_reg_rtx (SFmode);
2531
2532 operands[1] = force_reg (SFmode, operands[1]);
2533 emit_insn (gen_cmpsf (operands[1], force_const_mem (SFmode,
2534 CONST_DOUBLE_FROM_REAL_VALUE (0x80000000ULL, SFmode))));
2535 emit_jump_insn (gen_blt (label1));
2536 emit_insn (gen_subsf3 (temp, operands[1], force_const_mem (SFmode,
2537 CONST_DOUBLE_FROM_REAL_VALUE (0x100000000ULL, SFmode))));
2538 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2539 emit_jump (label2);
2540
2541 emit_label (label1);
2542 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2543 emit_label (label2);
2544 DONE;
2545 }")
2546
2547 (define_expand "fix_truncsfsi2"
2548 [(set (match_operand:SI 0 "register_operand" "")
2549 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2550 "TARGET_HARD_FLOAT"
2551 "
2552 {
2553 if (TARGET_IBM_FLOAT)
2554 {
2555 /* Convert to DFmode and then use the POP algorithm. */
2556 rtx temp = gen_reg_rtx (DFmode);
2557 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2558 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2559 }
2560 else
2561 {
2562 operands[1] = force_reg (SFmode, operands[1]);
2563 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2564 }
2565
2566 DONE;
2567 }")
2568
2569 (define_insn "fix_truncsfsi2_ieee"
2570 [(set (match_operand:SI 0 "register_operand" "=d")
2571 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2572 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2573 (clobber (reg:CC 33))]
2574 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2575 "cfebr\\t%0,%h2,%1"
2576 [(set_attr "op_type" "RRE")
2577 (set_attr "type" "other")])
2578
2579 ;
2580 ; floatdidf2 instruction pattern(s).
2581 ;
2582
2583 (define_insn "floatdidf2"
2584 [(set (match_operand:DF 0 "register_operand" "=f")
2585 (float:DF (match_operand:DI 1 "register_operand" "d")))]
2586 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2587 "cdgbr\\t%0,%1"
2588 [(set_attr "op_type" "RRE")
2589 (set_attr "type" "other" )])
2590
2591 ;
2592 ; floatdisf2 instruction pattern(s).
2593 ;
2594
2595 (define_insn "floatdisf2"
2596 [(set (match_operand:SF 0 "register_operand" "=f")
2597 (float:SF (match_operand:DI 1 "register_operand" "d")))]
2598 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2599 "cegbr\\t%0,%1"
2600 [(set_attr "op_type" "RRE")
2601 (set_attr "type" "other" )])
2602
2603 ;
2604 ; floatsidf2 instruction pattern(s).
2605 ;
2606
2607 (define_expand "floatsidf2"
2608 [(set (match_operand:DF 0 "register_operand" "")
2609 (float:DF (match_operand:SI 1 "register_operand" "")))]
2610 "TARGET_HARD_FLOAT"
2611 "
2612 {
2613 if (TARGET_IBM_FLOAT)
2614 {
2615 /* This is the algorithm from POP chapter A.5.7.1. */
2616
2617 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2618 rtx two31 = force_const_mem (DFmode,
2619 gen_rtx (CONST_DOUBLE, VOIDmode, cc0_rtx,
2620 0x80000000U, 0x4E000000U));
2621
2622 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2623 DONE;
2624 }
2625 }")
2626
2627 (define_insn "floatsidf2_ieee"
2628 [(set (match_operand:DF 0 "register_operand" "=f")
2629 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2630 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2631 "cdfbr\\t%0,%1"
2632 [(set_attr "op_type" "RRE")
2633 (set_attr "type" "other" )])
2634
2635 (define_insn "floatsidf2_ibm"
2636 [(set (match_operand:DF 0 "register_operand" "=f")
2637 (float:DF (match_operand:SI 1 "register_operand" "d")))
2638 (use (match_operand:DF 2 "memory_operand" "m"))
2639 (use (match_operand:BLK 3 "memory_operand" "m"))
2640 (clobber (reg:CC 33))]
2641 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2642 "*
2643 {
2644 output_asm_insn (\"st\\t%0,%N3\", operands);
2645 output_asm_insn (\"xi\\t%N3,128\", operands);
2646 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2647 output_asm_insn (\"ld\\t%0,%3\", operands);
2648 return \"sd\\t%0,%2\";
2649 }"
2650 [(set_attr "op_type" "NN")
2651 (set_attr "type" "other" )
2652 (set_attr "length" "20")])
2653
2654 ;
2655 ; floatsisf2 instruction pattern(s).
2656 ;
2657
2658 (define_expand "floatsisf2"
2659 [(set (match_operand:SF 0 "register_operand" "")
2660 (float:SF (match_operand:SI 1 "register_operand" "")))]
2661 "TARGET_HARD_FLOAT"
2662 "
2663 {
2664 if (TARGET_IBM_FLOAT)
2665 {
2666 /* Use the POP algorithm to convert to DFmode and then truncate. */
2667 rtx temp = gen_reg_rtx (DFmode);
2668 emit_insn (gen_floatsidf2 (temp, operands[1]));
2669 emit_insn (gen_truncdfsf2 (operands[0], temp));
2670 DONE;
2671 }
2672 }")
2673
2674 (define_insn "floatsisf2_ieee"
2675 [(set (match_operand:SF 0 "register_operand" "=f")
2676 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2677 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2678 "cefbr\\t%0,%1"
2679 [(set_attr "op_type" "RRE")
2680 (set_attr "type" "other" )])
2681
2682 ;
2683 ; truncdfsf2 instruction pattern(s).
2684 ;
2685
2686 (define_expand "truncdfsf2"
2687 [(set (match_operand:SF 0 "register_operand" "")
2688 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2689 "TARGET_HARD_FLOAT"
2690 "
2691 {
2692 if (CONSTANT_P(operands[1]))
2693 operands[1] = force_const_mem (DFmode, operands[1]);
2694 }")
2695
2696 (define_insn "truncdfsf2_ieee"
2697 [(set (match_operand:SF 0 "register_operand" "=f")
2698 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f")))]
2699 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2700 "ledbr\\t%0,%1"
2701 [(set_attr "op_type" "RR")])
2702
2703 (define_insn "truncdfsf2_ibm"
2704 [(set (match_operand:SF 0 "register_operand" "=f,f")
2705 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,m")))]
2706 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2707 "@
2708 lrer\\t%0,%1
2709 le\\t%0,%1"
2710 [(set_attr "op_type" "RR,RX")])
2711
2712 ;
2713 ; extendsfdf2 instruction pattern(s).
2714 ;
2715
2716 (define_expand "extendsfdf2"
2717 [(set (match_operand:DF 0 "register_operand" "")
2718 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2719 "TARGET_HARD_FLOAT"
2720 "
2721 {
2722 if (TARGET_IBM_FLOAT)
2723 {
2724 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2725 DONE;
2726 }
2727 }")
2728
2729 (define_insn "extendsfdf2_ieee"
2730 [(set (match_operand:DF 0 "register_operand" "=f,f")
2731 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2732 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2733 "@
2734 ldebr\\t%0,%1
2735 ldeb\\t%0,%1"
2736 [(set_attr "op_type" "RRE,RXE")])
2737
2738 (define_insn "extendsfdf2_ibm"
2739 [(set (match_operand:DF 0 "register_operand" "=f,f")
2740 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2741 (clobber (reg:CC 33))]
2742 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2743 "@
2744 sdr\\t%0,%0\;ler\\t%0,%1
2745 sdr\\t%0,%0\;le\\t%0,%1"
2746 [(set_attr "op_type" "RRE,RXE")])
2747
2748
2749 ;;
2750 ;; ARITHMETRIC OPERATIONS
2751 ;;
2752 ; arithmetric operations set the ConditionCode,
2753 ; because of unpredictable Bits in Register for Halfword and Byte
2754 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2755
2756 ;;
2757 ;;- Add instructions.
2758 ;;
2759
2760 ;
2761 ; adddi3 instruction pattern(s).
2762 ;
2763
2764 (define_insn "addaddr_esame"
2765 [(set (match_operand:DI 0 "register_operand" "=a,a")
2766 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
2767 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
2768 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
2769 (REGNO (operands[1]) == BASE_REGISTER)) &&
2770 (GET_CODE (operands[2]) == REG ||
2771 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
2772 "@
2773 la\\t%0,%c2(,%1)
2774 la\\t%0,0(%1,%2)"
2775 [(set_attr "op_type" "RX")
2776 (set_attr "atype" "mem")
2777 (set_attr "type" "la")])
2778
2779 (define_insn "adddi3_64"
2780 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2781 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
2782 (match_operand:DI 2 "general_operand" "d,K,m") ) )
2783 (clobber (reg:CC 33))]
2784 "TARGET_64BIT"
2785 "@
2786 agr\\t%0,%2
2787 aghi\\t%0,%h2
2788 ag\\t%0,%2"
2789 [(set_attr "op_type" "RRE,RI,RXE")
2790 (set_attr "atype" "reg,reg,mem")])
2791
2792 ;
2793 ; For weakness of reload, need (set (reg x) (plus (reg y) (reg x)))
2794 ;
2795
2796 (define_insn "adddi3_inv_64"
2797 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2798 (plus:DI (match_operand:DI 1 "general_operand" "%d,K,m")
2799 (match_operand:DI 2 "register_operand" "0,0,0") ) )
2800 (clobber (reg:CC 33))]
2801 "TARGET_64BIT"
2802 "@
2803 agr\\t%0,%1
2804 aghi\\t%0,%h1
2805 ag\\t%0,%1"
2806 [(set_attr "op_type" "RRE,RI,RXE")
2807 (set_attr "atype" "reg,reg,mem")])
2808
2809 (define_insn "adddi3_31"
2810 [(set (match_operand:DI 0 "register_operand" "=d,d")
2811 (plus:DI (match_operand:DI 1 "register_operand" "0,0")
2812 (match_operand:DI 2 "general_operand" "d,m") ) )
2813 (clobber (reg:CC 33))]
2814 "!TARGET_64BIT"
2815 "*
2816 {
2817 switch(which_alternative)
2818 {
2819 case 0: /* d <- d */
2820 output_asm_insn (\"ar\\t%0,%2\", operands);
2821 output_asm_insn (\"alr\\t%N0,%N2\", operands);
2822 break;
2823
2824 case 1: /* d <- m */
2825 output_asm_insn (\"a\\t%0,%2\", operands);
2826 output_asm_insn (\"al\\t%N0,%N2\", operands);
2827 break;
2828 }
2829
2830 output_asm_insn (\"brc\\t12,.+8\", operands);
2831 return \"ahi\\t%0,1\";
2832 }"
2833 [(set_attr "op_type" "NN,NN")
2834 (set_attr "atype" "reg,mem")
2835 (set_attr "length" "12,16")])
2836
2837 (define_expand "adddi3"
2838 [(set (match_operand:DI 0 "register_operand" "")
2839 (plus:DI (match_operand:DI 1 "register_operand" "")
2840 (match_operand:DI 2 "general_operand" "")))]
2841 ""
2842 "
2843 {
2844 if (TARGET_64BIT)
2845 emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2]));
2846 else
2847 emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2]));
2848 DONE;
2849 }")
2850
2851 (define_insn "reload_load_address"
2852 [(set (match_operand:DI 0 "register_operand" "=a")
2853 (match_operand:QI 1 "address_operand" "p"))]
2854 "TARGET_64BIT"
2855 "la\\t%0,%a1"
2856 [(set_attr "op_type" "RX")
2857 (set_attr "atype" "mem")
2858 (set_attr "type" "la")])
2859
2860 (define_insn "*reload_load_address_reg_0"
2861 [(set (match_operand:DI 0 "register_operand" "=d")
2862 (plus:DI (match_operand:DI 1 "register_operand" "%0")
2863 (match_operand:DI 2 "register_operand" "d")))]
2864 "TARGET_64BIT"
2865 "brxlg\\t%0,%2,.+6"
2866 [(set_attr "op_type" "RIE")
2867 (set_attr "atype" "reg")])
2868
2869 (define_insn "*reload_la_64"
2870 [(set (match_operand:DI 0 "register_operand" "=d")
2871 (plus:DI (match_operand:DI 1 "general_operand" "g")
2872 (match_operand:DI 2 "general_operand" "g")))]
2873 "TARGET_64BIT && reload_in_progress"
2874 "#")
2875
2876 (define_split
2877 [(set (match_operand:DI 0 "register_operand" "")
2878 (plus:DI (match_operand:DI 1 "general_operand" "")
2879 (match_operand:DI 2 "register_operand" "")))]
2880 "TARGET_64BIT && reload_completed
2881 && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
2882 && !rtx_equal_p (operands[0], operands[1])
2883 && !rtx_equal_p (operands[0], operands[2])"
2884 [(set (match_dup 0) (match_dup 1))
2885 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
2886 "")
2887
2888 (define_split
2889 [(set (match_operand:DI 0 "register_operand" "")
2890 (plus:DI (match_operand:DI 1 "register_operand" "")
2891 (match_operand:DI 2 "general_operand" "")))]
2892 "TARGET_64BIT && reload_completed
2893 && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
2894 && !rtx_equal_p (operands[0], operands[1])
2895 && !rtx_equal_p (operands[0], operands[2])"
2896 [(set (match_dup 0) (match_dup 2))
2897 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))]
2898 "")
2899
2900 ;
2901 ; addsi3 instruction pattern(s).
2902 ;
2903 ; The following insn is used when it is known that operand one is the stack pointer,
2904 ; and operand two is small enough to fit in the displacement field
2905 ; In this case, the result will be an address
2906 ;
2907
2908 (define_insn "addaddr"
2909 [(set (match_operand:SI 0 "register_operand" "=d,d")
2910 (plus:SI (match_operand:SI 1 "register_operand" "%a,a")
2911 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
2912 "(((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
2913 (REGNO (operands[1]) == BASE_REGISTER)) &&
2914 (GET_CODE (operands[2]) == REG ||
2915 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
2916 "@
2917 la\\t%0,%c2(,%1)
2918 la\\t%0,0(%1,%2)"
2919 [(set_attr "op_type" "RX")
2920 (set_attr "atype" "mem")
2921 (set_attr "type" "la")])
2922
2923 (define_insn "*addsi3_cc"
2924 [(set (reg 33)
2925 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
2926 (match_operand:SI 2 "nonimmediate_operand" "d,m"))
2927 (const_int 0)))
2928 (set (match_operand:SI 0 "register_operand" "=d,d")
2929 (plus:SI (match_dup 1) (match_dup 2)))]
2930 "s390_match_ccmode(insn, CCLmode)"
2931 "@
2932 alr\\t%0,%2
2933 al\\t%0,%2"
2934 [(set_attr "op_type" "RR,RX")
2935 (set_attr "atype" "reg,mem")])
2936
2937 (define_insn "*addsi3_cconly"
2938 [(set (reg 33)
2939 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
2940 (match_operand:SI 2 "general_operand" "d,m"))
2941 (const_int 0)))
2942 (clobber (match_scratch:SI 0 "=d,d"))]
2943 "s390_match_ccmode(insn, CCLmode)"
2944 "@
2945 alr\\t%0,%2
2946 al\\t%0,%2"
2947 [(set_attr "op_type" "RR,RX")
2948 (set_attr "atype" "reg,mem")])
2949
2950 (define_insn "*addsi3_cconly2"
2951 [(set (reg 33)
2952 (compare (match_operand:SI 1 "register_operand" "%0,0")
2953 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
2954 (clobber (match_scratch:SI 0 "=d,d"))]
2955 "s390_match_ccmode(insn, CCLmode)"
2956 "@
2957 alr\\t%0,%2
2958 al\\t%0,%2"
2959 [(set_attr "op_type" "RR,RX")
2960 (set_attr "atype" "reg,mem")])
2961
2962 (define_insn "addsi3"
2963 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2964 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
2965 (match_operand:SI 2 "general_operand" "d,K,m")))
2966 (clobber (reg:CC 33))]
2967 ""
2968 "@
2969 ar\\t%0,%2
2970 ahi\\t%0,%h2
2971 a\\t%0,%2"
2972 [(set_attr "op_type" "RR,RI,RX")
2973 (set_attr "atype" "reg,reg,mem")])
2974
2975 (define_insn "*do_la"
2976 [(set (match_operand:SI 0 "register_operand" "=a")
2977 (match_operand:QI 1 "address_operand" "p"))]
2978 "reload_in_progress || reload_completed
2979 || legitimate_la_operand_p (operands[1])"
2980 "la\\t%0,%a1"
2981 [(set_attr "op_type" "RX")
2982 (set_attr "atype" "mem")
2983 (set_attr "type" "la")])
2984
2985 (define_insn "*do_la_reg_0"
2986 [(set (match_operand:SI 0 "register_operand" "=d")
2987 (plus:SI (match_operand:SI 1 "register_operand" "%0")
2988 (match_operand:SI 2 "register_operand" "d")))]
2989 "reload_in_progress || reload_completed"
2990 "brxle\\t%0,%2,.+4"
2991 [(set_attr "op_type" "RSI")
2992 (set_attr "atype" "reg")])
2993
2994 (define_insn "*reload_la_31"
2995 [(set (match_operand:SI 0 "register_operand" "=d")
2996 (plus:SI (match_operand:SI 1 "general_operand" "g")
2997 (match_operand:SI 2 "general_operand" "g")))]
2998 "reload_in_progress"
2999 "#")
3000
3001 (define_split
3002 [(set (match_operand:SI 0 "register_operand" "")
3003 (plus:SI (match_operand:SI 1 "general_operand" "")
3004 (match_operand:SI 2 "register_operand" "")))]
3005 "reload_completed
3006 && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3007 && !rtx_equal_p (operands[0], operands[1])
3008 && !rtx_equal_p (operands[0], operands[2])"
3009 [(set (match_dup 0) (match_dup 1))
3010 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3011 "")
3012
3013 (define_split
3014 [(set (match_operand:SI 0 "register_operand" "")
3015 (plus:SI (match_operand:SI 1 "register_operand" "")
3016 (match_operand:SI 2 "general_operand" "")))]
3017 "reload_completed
3018 && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3019 && !rtx_equal_p (operands[0], operands[1])
3020 && !rtx_equal_p (operands[0], operands[2])"
3021 [(set (match_dup 0) (match_dup 2))
3022 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
3023 "")
3024
3025 (define_insn "addsi_64"
3026 [(set (match_operand:SI 0 "register_operand" "=d,d")
3027 (plus:SI (match_operand:SI 1 "register_operand" "%a,a")
3028 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
3029 "TARGET_64BIT"
3030 "@
3031 la\\t%0,%c2(,%1)
3032 la\\t%0,0(%1,%2)"
3033 [(set_attr "op_type" "RX")
3034 (set_attr "atype" "mem")
3035 (set_attr "type" "la")])
3036
3037 ;
3038 ; addhi3 instruction pattern(s).
3039 ;
3040
3041 (define_insn "addhi3"
3042 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3043 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
3044 (match_operand:HI 2 "general_operand" "d,K,m")))
3045 (clobber (reg:CC 33))]
3046 ""
3047 "@
3048 ar\\t%0,%2
3049 ahi\\t%0,%h2
3050 ah\\t%0,%2"
3051 [(set_attr "op_type" "RR,RI,RX")
3052 (set_attr "atype" "reg,reg,mem")])
3053
3054
3055 ;
3056 ; addqi3 instruction pattern(s).
3057 ;
3058
3059 (define_insn "addqi3"
3060 [(set (match_operand:QI 0 "register_operand" "=d,d")
3061 (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
3062 (match_operand:QI 2 "general_operand" "a,n")))
3063 (clobber (reg:CC 33))]
3064 ""
3065 "@
3066 ar\\t%0,%2
3067 ahi\\t%0,%h2"
3068 [(set_attr "op_type" "RX,RX")
3069 (set_attr "atype" "reg,mem")])
3070
3071
3072 ;
3073 ; adddf3 instruction pattern(s).
3074 ;
3075
3076 (define_expand "adddf3"
3077 [(parallel
3078 [(set (match_operand:DF 0 "register_operand" "=f,f")
3079 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3080 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3081 (clobber (reg:CC 33))])]
3082 "TARGET_HARD_FLOAT"
3083 "")
3084
3085 (define_insn "*adddf3"
3086 [(set (match_operand:DF 0 "register_operand" "=f,f")
3087 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3088 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3089 (clobber (reg:CC 33))]
3090 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3091 "@
3092 adbr\\t%0,%2
3093 adb\\t%0,%2"
3094 [(set_attr "op_type" "RR,RX")
3095 (set_attr "atype" "reg,mem")])
3096
3097 (define_insn "*adddf3_ibm"
3098 [(set (match_operand:DF 0 "register_operand" "=f,f")
3099 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3100 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3101 (clobber (reg:CC 33))]
3102 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3103 "@
3104 adr\\t%0,%2
3105 ad\\t%0,%2"
3106 [(set_attr "op_type" "RR,RX")
3107 (set_attr "atype" "reg,mem")])
3108
3109 ;
3110 ; addsf3 instruction pattern(s).
3111 ;
3112
3113 (define_expand "addsf3"
3114 [(parallel
3115 [(set (match_operand:SF 0 "register_operand" "=f,f")
3116 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3117 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3118 (clobber (reg:CC 33))])]
3119 "TARGET_HARD_FLOAT"
3120 "")
3121
3122 (define_insn "*addsf3"
3123 [(set (match_operand:SF 0 "register_operand" "=f,f")
3124 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3125 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3126 (clobber (reg:CC 33))]
3127 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3128 "@
3129 aebr\\t%0,%2
3130 aeb\\t%0,%2"
3131 [(set_attr "op_type" "RR,RX")
3132 (set_attr "atype" "reg,mem")])
3133
3134 (define_insn "*addsf3"
3135 [(set (match_operand:SF 0 "register_operand" "=f,f")
3136 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3137 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3138 (clobber (reg:CC 33))]
3139 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3140 "@
3141 aer\\t%0,%2
3142 ae\\t%0,%2"
3143 [(set_attr "op_type" "RR,RX")
3144 (set_attr "atype" "reg,mem")])
3145
3146
3147 ;;
3148 ;;- Subtract instructions.
3149 ;;
3150
3151 ;
3152 ; subdi3 instruction pattern(s).
3153 ;
3154
3155 (define_insn "*subdi3_64"
3156 [(set (match_operand:DI 0 "register_operand" "=d,d")
3157 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3158 (match_operand:DI 2 "general_operand" "d,m") ) )
3159 (clobber (reg:CC 33))]
3160 "TARGET_64BIT"
3161 "@
3162 sgr\\t%0,%2
3163 sg\\t%0,%2"
3164 [(set_attr "op_type" "RRE,RRE")
3165 (set_attr "atype" "reg,mem")])
3166
3167 (define_insn "subdi3"
3168 [(set (match_operand:DI 0 "register_operand" "=d,d")
3169 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3170 (match_operand:DI 2 "nonimmediate_operand" "d,m")))
3171 (clobber (reg:CC 33))]
3172 ""
3173 "*
3174 {
3175 switch (which_alternative)
3176 {
3177 case 0: /* d <- d */
3178 output_asm_insn (\"sr\\t%0,%2\", operands);
3179 output_asm_insn (\"slr\\t%N0,%N2\", operands);
3180 break;
3181 case 1: /* d <- m */
3182 output_asm_insn (\"s\\t%0,%2\", operands);
3183 output_asm_insn (\"sl\\t%N0,%N2\", operands);
3184 break;
3185 }
3186
3187 output_asm_insn (\"brc\\t11,.+8\", operands);
3188 return \"ahi\\t%0,-1\";
3189 }"
3190 [(set_attr "op_type" "NN,NN")
3191 (set_attr "atype" "reg,mem")
3192 (set_attr "length" "12,16")])
3193
3194 ;
3195 ; subsi3 instruction pattern(s).
3196 ;
3197
3198 (define_insn "*subsi3_cc"
3199 [(set (reg 33)
3200 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3201 (match_operand:SI 2 "general_operand" "d,m"))
3202 (const_int 0)))
3203 (set (match_operand:SI 0 "register_operand" "=d,d")
3204 (minus:SI (match_dup 1) (match_dup 2)))]
3205 "s390_match_ccmode(insn, CCLmode)"
3206 "@
3207 slr\\t%0,%2
3208 sl\\t%0,%2"
3209 [(set_attr "op_type" "RR,RX")
3210 (set_attr "atype" "reg,mem")])
3211
3212 (define_insn "*subsi3_cconly"
3213 [(set (reg 33)
3214 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3215 (match_operand:SI 2 "general_operand" "d,m"))
3216 (const_int 0)))
3217 (clobber (match_scratch:SI 0 "=d,d"))]
3218 "s390_match_ccmode(insn, CCLmode)"
3219 "@
3220 slr\\t%0,%2
3221 sl\\t%0,%2"
3222 [(set_attr "op_type" "RR,RX")
3223 (set_attr "atype" "reg,mem")])
3224
3225 (define_insn "subsi3"
3226 [(set (match_operand:SI 0 "register_operand" "=d,d")
3227 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3228 (match_operand:SI 2 "general_operand" "d,m")))
3229 (clobber (reg:CC 33))]
3230 ""
3231 "@
3232 sr\\t%0,%2
3233 s\\t%0,%2"
3234 [(set_attr "op_type" "RR,RX")
3235 (set_attr "atype" "reg,mem")])
3236
3237 ;
3238 ; subhi3 instruction pattern(s).
3239 ;
3240
3241 (define_insn "subhi3"
3242 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3243 (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
3244 (match_operand:HI 2 "nonimmediate_operand" "d,K,m")))
3245 (clobber (reg:CC 33))]
3246 ""
3247 "@
3248 sr\\t%0,%2
3249 ahi\\t%0,-%h2
3250 sh\\t%0,%2"
3251 [(set_attr "op_type" "RR,RI,RX")
3252 (set_attr "atype" "reg,reg,mem")])
3253
3254 ;
3255 ; subqi3 instruction pattern(s).
3256 ;
3257
3258 (define_insn "subqi3"
3259 [(set (match_operand:QI 0 "register_operand" "=d")
3260 (minus:QI (match_operand:QI 1 "register_operand" "0")
3261 (match_operand:QI 2 "register_operand" "d")))
3262 (clobber (reg:CC 33))]
3263 ""
3264 "sr\\t%0,%2"
3265 [(set_attr "op_type" "RR")])
3266
3267 ;
3268 ; subdf3 instruction pattern(s).
3269 ;
3270
3271 (define_expand "subdf3"
3272 [(parallel
3273 [(set (match_operand:DF 0 "register_operand" "=f,f")
3274 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3275 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3276 (clobber (reg:CC 33))])]
3277 "TARGET_HARD_FLOAT"
3278 "")
3279
3280 (define_insn "*subdf3"
3281 [(set (match_operand:DF 0 "register_operand" "=f,f")
3282 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3283 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3284 (clobber (reg:CC 33))]
3285 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3286 "@
3287 sdbr\\t%0,%2
3288 sdb\\t%0,%2"
3289 [(set_attr "op_type" "RR,RX")
3290 (set_attr "atype" "reg,mem")])
3291
3292 (define_insn "*subdf3_ibm"
3293 [(set (match_operand:DF 0 "register_operand" "=f,f")
3294 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3295 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3296 (clobber (reg:CC 33))]
3297 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3298 "@
3299 sdr\\t%0,%2
3300 sd\\t%0,%2"
3301 [(set_attr "op_type" "RR,RX")
3302 (set_attr "atype" "reg,mem")])
3303
3304 ;
3305 ; subsf3 instruction pattern(s).
3306 ;
3307
3308 (define_expand "subsf3"
3309 [(parallel
3310 [(set (match_operand:SF 0 "register_operand" "=f,f")
3311 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3312 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3313 (clobber (reg:CC 33))])]
3314 "TARGET_HARD_FLOAT"
3315 "")
3316
3317 (define_insn "*subsf3"
3318 [(set (match_operand:SF 0 "register_operand" "=f,f")
3319 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3320 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3321 (clobber (reg:CC 33))]
3322 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3323 "@
3324 sebr\\t%0,%2
3325 seb\\t%0,%2"
3326 [(set_attr "op_type" "RR,RX")
3327 (set_attr "atype" "reg,mem")])
3328
3329 (define_insn "*subsf3_ibm"
3330 [(set (match_operand:SF 0 "register_operand" "=f,f")
3331 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3332 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3333 (clobber (reg:CC 33))]
3334 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3335 "@
3336 ser\\t%0,%2
3337 se\\t%0,%2"
3338 [(set_attr "op_type" "RR,RX")
3339 (set_attr "atype" "reg,mem")])
3340
3341
3342 ;;
3343 ;;- Multiply instructions.
3344 ;;
3345
3346 (define_expand "muldi3"
3347 [(parallel
3348 [(set (match_operand:DI 0 "register_operand" "")
3349 (mult:DI (match_operand:DI 1 "register_operand" "")
3350 (match_operand:DI 2 "register_operand" "")))
3351 (clobber (reg:CC 33))])]
3352 ""
3353 "
3354 {
3355 if (!TARGET_64BIT)
3356 {
3357 rtx label1 = gen_label_rtx ();
3358 rtx label2 = gen_label_rtx ();
3359 rtx op0_0 = operand_subword (operands[0], 0 ,1, DImode);
3360 rtx op0_1 = operand_subword (operands[0], 1 ,1, DImode);
3361 rtx temp1_0 = gen_reg_rtx (SImode);
3362 rtx temp1_1 = gen_reg_rtx (SImode);
3363 rtx temp2_0 = gen_reg_rtx (SImode);
3364 rtx temp2_1 = gen_reg_rtx (SImode);
3365
3366 emit_move_insn (temp1_0, operand_subword (operands[1], 0 ,1, DImode));
3367 emit_move_insn (temp1_1, operand_subword (operands[1], 1 ,1, DImode));
3368 emit_move_insn (temp2_0, operand_subword (operands[2], 0 ,1, DImode));
3369 emit_move_insn (temp2_1, operand_subword (operands[2], 1 ,1, DImode));
3370 emit_move_insn (op0_1, temp1_1);
3371 emit_insn (gen_mulsi_6432 (operands[0], operands[0], temp2_1));
3372
3373 emit_insn (gen_cmpsi (temp1_1, const0_rtx));
3374 emit_jump_insn (gen_bge (label1));
3375 emit_insn (gen_addsi3 (op0_0, op0_0, temp2_1));
3376 emit_label (label1);
3377 emit_insn (gen_cmpsi (temp2_1, const0_rtx));
3378 emit_jump_insn (gen_bge (label2));
3379 emit_insn (gen_addsi3 (op0_0, op0_0, temp1_1));
3380 emit_label (label2);
3381
3382 emit_insn (gen_mulsi3 (temp2_1, temp2_1, temp1_0));
3383 emit_insn (gen_addsi3 (op0_0, op0_0, temp2_1));
3384
3385 emit_insn (gen_mulsi3 (temp1_1, temp1_1, temp2_0));
3386 emit_insn (gen_addsi3 (op0_0, op0_0, temp1_1));
3387
3388 DONE;
3389 }
3390 }")
3391
3392 (define_insn "*muldi3_64"
3393 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3394 (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3395 (match_operand:DI 2 "general_operand" "d,K,m")))
3396 (clobber (reg:CC 33))]
3397 "TARGET_64BIT"
3398 "@
3399 msgr\\t%0,%2
3400 mghi\\t%0,%h2
3401 msg\\t%0,%2"
3402 [(set_attr "op_type" "RRE,RI,RX")
3403 (set_attr "atype" "reg,reg,mem")
3404 (set_attr "type" "imul")])
3405
3406 ;
3407 ; mulsidi3 instruction pattern(s).
3408 ;
3409
3410 ;(define_expand "mulsidi3"
3411 ; [(set (match_operand:DI 0 "register_operand" "")
3412 ; (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3413 ; (sign_extend:DI (match_operand:SI 2 "general_operand" ""))))]
3414 ; ""
3415 ; "
3416 ;{
3417 ; emit_insn (gen_extendsidi2 (operands[0], operands[1]));
3418 ; emit_insn (gen_muldisidi3 (operands[0], operands[0], operands[2]));
3419 ; DONE;
3420 ;}")
3421
3422 ;(define_insn "muldisidi3"
3423 ; [(set (match_operand:DI 0 "register_operand" "=d,d")
3424 ; (mult:DI (match_operand:DI 1 "register_operand" "0,0")
3425 ; (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3426 ; (clobber (reg:CC 33))]
3427 ; "!TARGET_64BIT"
3428 ; "@
3429 ; mr\\t%0,%2
3430 ; m\\t%0,%2"
3431 ; [(set_attr "op_type" "RR,RX")
3432 ; (set_attr "atype" "reg,mem")
3433 ; (set_attr "type" "imul")])
3434
3435 ;
3436 ; mulsi3 instruction pattern(s).
3437 ;
3438
3439 (define_insn "mulsi3"
3440 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3441 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3442 (match_operand:SI 2 "general_operand" "d,K,m")))
3443 (clobber (reg:CC 33))]
3444 ""
3445 "@
3446 msr\\t%0,%2
3447 mhi\\t%0,%h2
3448 ms\\t%0,%2"
3449 [(set_attr "op_type" "RRE,RI,RX")
3450 (set_attr "atype" "reg,reg,mem")
3451 (set_attr "type" "imul")])
3452
3453 (define_insn "mulsi_6432"
3454 [(set (match_operand:DI 0 "register_operand" "=d,d")
3455 (mult:DI (sign_extend:DI
3456 (subreg:SI (match_operand:DI 1 "register_operand" "0,0") 4))
3457 (sign_extend:DI
3458 (match_operand:SI 2 "general_operand" "d,m"))))
3459 (clobber (reg:CC 33))]
3460 "!TARGET_64BIT"
3461 "@
3462 mr\\t%0,%2
3463 m\\t%0,%2"
3464 [(set_attr "op_type" "RR,RX")
3465 (set_attr "atype" "reg,mem")
3466 (set_attr "type" "imul")])
3467
3468
3469 ;
3470 ; muldf3 instruction pattern(s).
3471 ;
3472
3473 (define_expand "muldf3"
3474 [(parallel
3475 [(set (match_operand:DF 0 "register_operand" "=f,f")
3476 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3477 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3478 (clobber (reg:CC 33))])]
3479 "TARGET_HARD_FLOAT"
3480 "")
3481
3482 (define_insn "*muldf3"
3483 [(set (match_operand:DF 0 "register_operand" "=f,f")
3484 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3485 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3486 (clobber (reg:CC 33))]
3487 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3488 "@
3489 mdbr\\t%0,%2
3490 mdb\\t%0,%2"
3491 [(set_attr "op_type" "RR,RX")
3492 (set_attr "type" "fmul")
3493 (set_attr "atype" "reg,mem")])
3494
3495 (define_insn "*muldf3_ibm"
3496 [(set (match_operand:DF 0 "register_operand" "=f,f")
3497 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3498 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3499 (clobber (reg:CC 33))]
3500 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3501 "@
3502 mdr\\t%0,%2
3503 md\\t%0,%2"
3504 [(set_attr "op_type" "RR,RX")
3505 (set_attr "type" "fmul")
3506 (set_attr "atype" "reg,mem")])
3507
3508 ;
3509 ; mulsf3 instruction pattern(s).
3510 ;
3511
3512 (define_expand "mulsf3"
3513 [(parallel
3514 [(set (match_operand:SF 0 "register_operand" "=f,f")
3515 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3516 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3517 (clobber (reg:CC 33))])]
3518 "TARGET_HARD_FLOAT"
3519 "")
3520
3521 (define_insn "*mulsf3"
3522 [(set (match_operand:SF 0 "register_operand" "=f,f")
3523 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3524 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3525 (clobber (reg:CC 33))]
3526 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3527 "@
3528 meebr\\t%0,%2
3529 meeb\\t%0,%2"
3530 [(set_attr "op_type" "RR,RX")
3531 (set_attr "type" "fmul")
3532 (set_attr "atype" "reg,mem")])
3533
3534 (define_insn "*mulsf3_ibm"
3535 [(set (match_operand:SF 0 "register_operand" "=f,f")
3536 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3537 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3538 (clobber (reg:CC 33))]
3539 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3540 "@
3541 mer\\t%0,%2
3542 me\\t%0,%2"
3543 [(set_attr "op_type" "RR,RX")
3544 (set_attr "type" "fmul")
3545 (set_attr "atype" "reg,mem")])
3546
3547
3548 ;;
3549 ;;- Divide and modulo instructions.
3550 ;;
3551
3552 ;
3553 ; divdi3 and moddi3 instruction pattern(s).
3554 ;
3555
3556 (define_expand "divdi3"
3557 [(set (match_operand:DI 0 "register_operand" "=d")
3558 (div:DI (match_operand:DI 1 "register_operand" "d")
3559 (match_operand:DI 2 "general_operand" "")))]
3560 "TARGET_64BIT"
3561 "
3562 {
3563 rtx op3 = gen_reg_rtx (TImode);
3564
3565 if (CONSTANT_P (operands[2]))
3566 operands[2] = force_const_mem (DImode, operands[2]);
3567
3568 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3569 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3570 emit_insn (gen_divmodtidi3 (op3, op3, operands[2]));
3571 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 8));
3572 DONE;
3573 }")
3574
3575 (define_expand "moddi3"
3576 [(set (match_operand:DI 0 "register_operand" "=d")
3577 (mod:DI (match_operand:DI 1 "register_operand" "d")
3578 (match_operand:DI 2 "general_operand" "")))]
3579 "TARGET_64BIT"
3580 "
3581 {
3582 rtx op3 = gen_reg_rtx (TImode);
3583
3584 if (CONSTANT_P (operands[2]))
3585 operands[2] = force_const_mem (DImode, operands[2]);
3586
3587 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3588 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3589 emit_insn (gen_divmodtidi3 (op3, op3, operands[2]));
3590 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 0));
3591 DONE;
3592 }")
3593
3594 (define_insn "divmodtidi3"
3595 [(set (subreg:DI (match_operand:TI 0 "register_operand" "=d,d") 0)
3596 (truncate:DI
3597 (mod:TI (match_operand:TI 1 "register_operand" "0,0")
3598 (sign_extend:TI
3599 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3600 (set (subreg:DI (match_dup 0) 8)
3601 (truncate:DI (div:TI (match_dup 1) (sign_extend:TI (match_dup 2)))))
3602 (clobber (reg:CC 33))]
3603 "TARGET_64BIT"
3604 "@
3605 dsgr\\t%0,%2
3606 dsg\\t%0,%2"
3607 [(set_attr "op_type" "RRE,RXE")
3608 (set_attr "type" "idiv")
3609 (set_attr "atype" "reg,mem")])
3610
3611 ;
3612 ; udivdi3 and umoddi3 instruction pattern(s).
3613 ;
3614
3615 (define_expand "udivdi3"
3616 [(set (match_operand:DI 0 "register_operand" "=d")
3617 (udiv:DI (match_operand:DI 1 "register_operand" "d")
3618 (match_operand:DI 2 "general_operand" "")))]
3619 "TARGET_64BIT"
3620 "
3621 {
3622 rtx op3 = gen_reg_rtx(TImode);
3623
3624 if (CONSTANT_P (operands[2]))
3625 operands[2] = force_const_mem (DImode, operands[2]);
3626
3627 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3628 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3629 emit_insn (gen_udivmodtidi3 (op3, op3, operands[2]));
3630 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 8));
3631 DONE;
3632 }")
3633
3634 (define_expand "umoddi3"
3635 [(set (match_operand:DI 0 "register_operand" "=d")
3636 (umod:DI (match_operand:DI 1 "register_operand" "d")
3637 (match_operand:DI 2 "general_operand" "")))]
3638 "TARGET_64BIT"
3639 "
3640 {
3641 rtx op3 = gen_reg_rtx (TImode);
3642
3643 if (CONSTANT_P (operands[2]))
3644 operands[2] = force_const_mem (DImode, operands[2]);
3645
3646 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3647 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3648 emit_insn (gen_udivmodtidi3 (op3, op3, operands[2]));
3649 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 0));
3650 DONE;
3651 }")
3652
3653 (define_insn "udivmodtidi3"
3654 [(set (subreg:DI (match_operand:TI 0 "register_operand" "=d,d") 0)
3655 (truncate:DI
3656 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
3657 (zero_extend:TI
3658 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3659 (set (subreg:DI (match_dup 0) 8)
3660 (truncate:DI (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3661 (clobber (reg:CC 33))]
3662 "TARGET_64BIT"
3663 "@
3664 dlgr\\t%0,%2
3665 dlg\\t%0,%2"
3666 [(set_attr "op_type" "RRE,RXE")
3667 (set_attr "type" "idiv")
3668 (set_attr "atype" "reg,mem")])
3669
3670 ;
3671 ; divsi3 and modsi3 instruction pattern(s).
3672 ;
3673
3674 (define_expand "divsi3"
3675 [(set (match_operand:SI 0 "register_operand" "=d")
3676 (div:SI (match_operand:SI 1 "register_operand" "d")
3677 (match_operand:SI 2 "nonimmediate_operand" "")))]
3678 "!TARGET_64BIT"
3679 "
3680 {
3681 rtx tmp = gen_reg_rtx (DImode);
3682
3683 if (CONSTANT_P (operands[2]))
3684 operands[2] = force_const_mem (SImode, operands[2]);
3685 else
3686 operands[2] = force_reg (SImode, operands[2]);
3687
3688 emit_insn (gen_rtx_CLOBBER (SImode, gen_rtx_SUBREG (SImode, tmp, 4)));
3689 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), operands[1]);
3690 emit_insn (gen_ashrdi3 (tmp, tmp, GEN_INT (32)));
3691 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3692 emit_move_insn (operands[0], gen_rtx_SUBREG (SImode, tmp, 4));
3693 DONE;
3694 }")
3695
3696 (define_expand "modsi3"
3697 [(set (match_operand:SI 0 "register_operand" "=d")
3698 (mod:SI (match_operand:SI 1 "register_operand" "d")
3699 (match_operand:SI 2 "nonimmediate_operand" "")))]
3700 "!TARGET_64BIT"
3701 "
3702 {
3703 rtx tmp = gen_reg_rtx (DImode);
3704
3705 if (CONSTANT_P (operands[2]))
3706 operands[2] = force_const_mem (SImode, operands[2]);
3707 else
3708 operands[2] = force_reg (SImode, operands[2]);
3709
3710 emit_insn (gen_rtx_CLOBBER (SImode, gen_rtx_SUBREG (SImode, tmp, 4)));
3711 emit_insn (gen_movsi (gen_rtx_SUBREG (SImode, tmp, 0), operands[1]));
3712 emit_insn (gen_ashrdi3 (tmp, tmp, GEN_INT (32)));
3713 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3714 emit_move_insn (operands[0], gen_rtx_SUBREG (SImode, tmp, 0));
3715 DONE;
3716 }")
3717
3718 (define_insn "divmoddisi3"
3719 [(set (subreg:SI (match_operand:DI 0 "register_operand" "=d,d") 0)
3720 (truncate:SI
3721 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
3722 (sign_extend:DI
3723 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3724 (set (subreg:SI (match_dup 0) 4)
3725 (truncate:SI (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))
3726 (clobber (reg:CC 33))]
3727 "!TARGET_64BIT"
3728 "@
3729 dr\\t%0,%2
3730 d\\t%0,%2"
3731 [(set_attr "op_type" "RR,RX")
3732 (set_attr "type" "idiv")
3733 (set_attr "atype" "reg,mem")])
3734
3735 ;
3736 ; udivsi3 and umodsi3 instruction pattern(s).
3737 ;
3738
3739 (define_expand "udivsi3"
3740 [(set (match_operand:SI 0 "register_operand" "=d")
3741 (udiv:SI (match_operand:SI 1 "general_operand" "")
3742 (match_operand:SI 2 "general_operand" "")))]
3743 "!TARGET_64BIT"
3744 "
3745 {
3746 rtx dr_0, dr_1, tmp;
3747
3748 tmp = gen_reg_rtx (DImode);
3749 dr_0 = gen_rtx_SUBREG (SImode, tmp, 0);
3750 dr_1 = gen_rtx_SUBREG (SImode, tmp, 4);
3751
3752 if (CONSTANT_P (operands[2]))
3753 {
3754 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3755 {
3756 rtx label1 = gen_label_rtx ();
3757
3758 emit_move_insn (dr_0, operands[1]);
3759 emit_move_insn (dr_1, const0_rtx);
3760 emit_insn (gen_cmpsi (dr_0, operands[2]));
3761 emit_jump_insn (gen_bltu (label1));
3762 emit_move_insn (dr_1, const1_rtx);
3763 emit_label (label1);
3764 }
3765 else
3766 {
3767 operands[2] = force_const_mem (SImode, operands[2]);
3768 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3769 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3770 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3771 }
3772 }
3773 else
3774 {
3775 rtx label1 = gen_label_rtx ();
3776 rtx label2 = gen_label_rtx ();
3777 rtx label3 = gen_label_rtx ();
3778
3779 operands[1] = force_reg (SImode, operands[1]);
3780 operands[2] = force_reg (SImode, operands[2]);
3781
3782 emit_move_insn (dr_1, const0_rtx);
3783 emit_insn (gen_cmpsi (operands[2], operands[1]));
3784 emit_jump_insn (gen_bgtu (label3));
3785 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3786 emit_jump_insn (gen_blt (label2));
3787 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3788 emit_jump_insn (gen_beq (label1));
3789 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3790 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3791 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3792 emit_jump (label3);
3793 emit_label (label1);
3794 emit_move_insn (dr_1, operands[1]);
3795 emit_jump (label3);
3796 emit_label (label2);
3797 emit_move_insn (dr_1, const1_rtx);
3798 emit_label (label3);
3799 }
3800
3801 emit_move_insn (operands[0], dr_1);
3802 DONE;
3803 }")
3804
3805 (define_expand "umodsi3"
3806 [(set (match_operand:SI 0 "register_operand" "=d")
3807 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
3808 (match_operand:SI 2 "nonimmediate_operand" "")))]
3809 "!TARGET_64BIT"
3810 "
3811 {
3812 rtx dr_0, dr_1, tmp;
3813
3814 tmp = gen_reg_rtx (DImode);
3815 dr_0 = gen_rtx_SUBREG (SImode, tmp, 0);
3816 dr_1 = gen_rtx_SUBREG (SImode, tmp, 4);
3817
3818 if (CONSTANT_P (operands[2]))
3819 {
3820 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
3821 {
3822 rtx label1 = gen_label_rtx ();
3823
3824 emit_move_insn (dr_0, operands[1]);
3825 emit_insn (gen_cmpsi (dr_0, operands[2]));
3826 emit_jump_insn (gen_bltu (label1));
3827 emit_insn (gen_abssi2 (dr_0, operands[2]));
3828 emit_insn (gen_addsi3 (dr_0,dr_0, operands[1]));
3829 emit_label (label1);
3830 }
3831 else
3832 {
3833 operands[2] = force_const_mem (SImode, operands[2]);
3834 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3835 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3836 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3837 }
3838 }
3839 else
3840 {
3841 rtx label1 = gen_label_rtx ();
3842 rtx label2 = gen_label_rtx ();
3843 rtx label3 = gen_label_rtx ();
3844
3845 operands[1] = force_reg (SImode, operands[1]);
3846 operands[2] = force_reg (SImode, operands[2]);
3847
3848 emit_move_insn(dr_0, operands[1]);
3849 emit_insn (gen_cmpsi (operands[2], dr_0));
3850 emit_jump_insn (gen_bgtu (label3));
3851 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3852 emit_jump_insn (gen_blt (label2));
3853 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3854 emit_jump_insn (gen_beq (label1));
3855 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3856 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3857 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3858 emit_jump (label3);
3859 emit_label (label1);
3860 emit_move_insn (dr_0, const0_rtx);
3861 emit_jump (label3);
3862 emit_label (label2);
3863 emit_insn (gen_subsi3 (dr_0, dr_0, operands[2]));
3864 emit_label (label3);
3865 }
3866
3867 emit_move_insn (operands[0], dr_0);
3868 DONE;
3869 }")
3870
3871 ;
3872 ; divdf3 instruction pattern(s).
3873 ;
3874
3875 (define_expand "divdf3"
3876 [(parallel
3877 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
3878 (div:DF (match_operand:DF 1 "general_operand" "0,0")
3879 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3880 (clobber (reg:CC 33))])]
3881 "TARGET_HARD_FLOAT"
3882 "")
3883
3884 (define_insn "*divdf3"
3885 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
3886 (div:DF (match_operand:DF 1 "general_operand" "0,0")
3887 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3888 (clobber (reg:CC 33))]
3889 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3890 "@
3891 ddbr\\t%0,%2
3892 ddb\\t%0,%2"
3893 [(set_attr "op_type" "RR,RX")
3894 (set_attr "type" "fdiv")
3895 (set_attr "atype" "reg,mem")])
3896
3897 (define_insn "*divdf3_ibm"
3898 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
3899 (div:DF (match_operand:DF 1 "general_operand" "0,0")
3900 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3901 (clobber (reg:CC 33))]
3902 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3903 "@
3904 ddr\\t%0,%2
3905 dd\\t%0,%2"
3906 [(set_attr "op_type" "RR,RX")
3907 (set_attr "type" "fdiv")
3908 (set_attr "atype" "reg,mem")])
3909
3910 ;
3911 ; divsf3 instruction pattern(s).
3912 ;
3913
3914 (define_expand "divsf3"
3915 [(parallel
3916 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f")
3917 (div:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
3918 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3919 (clobber (reg:CC 33))])]
3920 "TARGET_HARD_FLOAT"
3921 "")
3922
3923 (define_insn "*divsf3"
3924 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f")
3925 (div:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
3926 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3927 (clobber (reg:CC 33))]
3928 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3929 "@
3930 debr\\t%0,%2
3931 deb\\t%0,%2"
3932 [(set_attr "op_type" "RR,RX")
3933 (set_attr "type" "fdiv")
3934 (set_attr "atype" "reg,mem")])
3935
3936 (define_insn "*divsf3"
3937 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f")
3938 (div:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
3939 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3940 (clobber (reg:CC 33))]
3941 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3942 "@
3943 der\\t%0,%2
3944 de\\t%0,%2"
3945 [(set_attr "op_type" "RR,RX")
3946 (set_attr "type" "fdiv")
3947 (set_attr "atype" "reg,mem")])
3948
3949
3950 ;;
3951 ;;- And instructions.
3952 ;;
3953
3954 ;
3955 ; anddi3 instruction pattern(s).
3956 ;
3957
3958 (define_insn "*anddi3_cc"
3959 [(set (reg 33)
3960 (compare (and:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0")
3961 (match_operand:DI 2 "r_or_s_operand" "d,m,Q"))
3962 (const_int 0)))
3963 (set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q")
3964 (and:DI (match_dup 1) (match_dup 2)))]
3965 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
3966 "@
3967 ngr\\t%0,%2
3968 ng\\t%0,%2
3969 nc\\t%O0(8,%R0),%2"
3970 [(set_attr "op_type" "RR,RX,SS")
3971 (set_attr "atype" "reg,mem,mem")])
3972
3973 (define_insn "*anddi3_cconly"
3974 [(set (reg 33)
3975 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
3976 (match_operand:DI 2 "r_or_s_operand" "d,m"))
3977 (const_int 0)))
3978 (clobber (match_scratch:DI 0 "=d,d"))]
3979 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
3980 "@
3981 ngr\\t%0,%2
3982 ng\\t%0,%2"
3983 [(set_attr "op_type" "RR,RX")
3984 (set_attr "atype" "reg,mem")])
3985
3986 (define_insn "anddi3"
3987 [(set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q")
3988 (and:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0")
3989 (match_operand:DI 2 "r_or_s_operand" "d,m,Q")))
3990 (clobber (reg:CC 33))]
3991 "TARGET_64BIT"
3992 "@
3993 ngr\\t%0,%2
3994 ng\\t%0,%2
3995 nc\\t%O0(8,%R0),%2"
3996 [(set_attr "op_type" "RR,RX,SS")
3997 (set_attr "atype" "reg,mem,mem")])
3998
3999 ;
4000 ; andsi3 instruction pattern(s).
4001 ;
4002
4003 (define_insn "*andsi3_cc"
4004 [(set (reg 33)
4005 (compare (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4006 (match_operand:SI 2 "r_or_s_operand" "d,m,Q"))
4007 (const_int 0)))
4008 (set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4009 (and:SI (match_dup 1) (match_dup 2)))]
4010 "s390_match_ccmode(insn, CCTmode)"
4011 "@
4012 nr\\t%0,%2
4013 n\\t%0,%2
4014 nc\\t%O0(4,%R0),%2"
4015 [(set_attr "op_type" "RR,RX,SS")
4016 (set_attr "atype" "reg,mem,mem")])
4017
4018 (define_insn "*andsi3_cconly"
4019 [(set (reg 33)
4020 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4021 (match_operand:SI 2 "r_or_s_operand" "d,m"))
4022 (const_int 0)))
4023 (clobber (match_scratch:SI 0 "=d,d"))]
4024 "s390_match_ccmode(insn, CCTmode)"
4025 "@
4026 nr\\t%0,%2
4027 n\\t%0,%2"
4028 [(set_attr "op_type" "RR,RX")
4029 (set_attr "atype" "reg,mem")])
4030
4031 (define_insn "andsi3"
4032 [(set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4033 (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4034 (match_operand:SI 2 "r_or_s_operand" "d,m,Q")))
4035 (clobber (reg:CC 33))]
4036 ""
4037 "@
4038 nr\\t%0,%2
4039 n\\t%0,%2
4040 nc\\t%O0(4,%R0),%2"
4041 [(set_attr "op_type" "RR,RX,SS")
4042 (set_attr "atype" "reg,mem,mem")])
4043
4044 ;
4045 ; andhi3 instruction pattern(s).
4046 ;
4047
4048 (define_expand "andhi3"
4049 [(parallel
4050 [(set (match_operand:HI 0 "r_or_s_operand" "")
4051 (and:HI (match_operand:HI 1 "r_or_s_operand" "")
4052 (match_operand:HI 2 "r_or_s_operand" "")))
4053 (clobber (reg:CC 33))])]
4054 ""
4055 "
4056 {
4057 if (CONSTANT_P (operands[2]))
4058 operands[2] = force_const_mem (HImode, operands[2]);
4059 }")
4060
4061 (define_insn "*andhi3"
4062 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4063 (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
4064 (match_operand:HI 2 "r_or_s_operand" "d,Q")))
4065 (clobber (reg:CC 33))]
4066 ""
4067 "@
4068 nr\\t%0,%2
4069 nc\\t%O0(2,%R0),%2"
4070 [(set_attr "op_type" "RR,SS")
4071 (set_attr "atype" "reg,mem")])
4072
4073 ;
4074 ; andqi3 instruction pattern(s).
4075 ;
4076
4077 (define_insn "andqi3"
4078 [(set (match_operand:QI 0 "r_or_s_operand" "=d,Q,Q")
4079 (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0,0")
4080 (match_operand:QI 2 "r_or_s_or_im8_operand" "d,n,Q")))
4081 (clobber (reg:CC 33))]
4082 ""
4083 "@
4084 nr\\t%0,%2
4085 ni\\t%0,%b2
4086 nc\\t%O0(1,%R0),%2"
4087 [(set_attr "op_type" "RR,SI,SS")
4088 (set_attr "atype" "reg,mem,mem")])
4089
4090
4091 ;;
4092 ;;- Bit set (inclusive or) instructions.
4093 ;;
4094
4095 ;
4096 ; iordi3 instruction pattern(s).
4097 ;
4098
4099 (define_insn "iordi3"
4100 [(set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q,d")
4101 (ior:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0,0")
4102 (match_operand:DI 2 "r_or_s_operand" "d,m,Q,L")))
4103 (clobber (reg:CC 33))]
4104 "TARGET_64BIT"
4105 "@
4106 ogr\\t%0,%2
4107 og\\t%0,%2
4108 oc\\t%O0(8,%R0),%2
4109 oill\\t%0,%2"
4110 [(set_attr "op_type" "RRE,RXE,SS,RI")
4111 (set_attr "atype" "reg,mem,mem,reg")])
4112
4113 ;
4114 ; iorsi3 instruction pattern(s).
4115 ;
4116
4117 (define_expand "iorsi3"
4118 [(parallel
4119 [(set (match_operand:SI 0 "r_or_s_operand" "")
4120 (ior:SI (match_operand:SI 1 "r_or_s_operand" "")
4121 (match_operand:SI 2 "r_or_s_operand" "")))
4122 (clobber (reg:CC 33))])]
4123 ""
4124 "
4125 {
4126 if (CONSTANT_P (operands[2]))
4127 operands[2] = force_const_mem (SImode, operands[2]);
4128 }")
4129
4130 (define_insn "*iorsi3"
4131 [(set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4132 (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4133 (match_operand:SI 2 "r_or_s_operand" "d,m,Q")))
4134 (clobber (reg:CC 33))]
4135 ""
4136 "@
4137 or\\t%0,%2
4138 o\\t%0,%2
4139 oc\\t%O0(4,%R0),%2"
4140 [(set_attr "op_type" "RR,RX,SS")
4141 (set_attr "atype" "reg,mem,mem")])
4142
4143 ;
4144 ; iorhi3 instruction pattern(s).
4145 ;
4146
4147 (define_expand "iorhi3"
4148 [(parallel
4149 [(set (match_operand:HI 0 "r_or_s_operand" "")
4150 (ior:HI (match_operand:HI 1 "r_or_s_operand" "")
4151 (match_operand:HI 2 "r_or_s_operand" "")))
4152 (clobber (reg:CC 33))])]
4153 ""
4154 "
4155 {
4156 if (CONSTANT_P (operands[2]))
4157 operands[2] = force_const_mem (HImode, operands[2]);
4158 }")
4159
4160 (define_insn "*iorhi3"
4161 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4162 (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
4163 (match_operand:HI 2 "r_or_s_operand" "d,Q")))
4164 (clobber (reg:CC 33))]
4165 ""
4166 "@
4167 or\\t%0,%2
4168 oc\\t%O0(2,%R0),%2"
4169 [(set_attr "op_type" "RR,SS")
4170 (set_attr "atype" "reg,mem")])
4171
4172 ;
4173 ; iorqi3 instruction pattern(s).
4174 ;
4175
4176 (define_insn "iorqi3"
4177 [(set (match_operand:QI 0 "r_or_s_operand" "=d,Q,Q")
4178 (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0,0")
4179 (match_operand:QI 2 "r_or_s_or_im8_operand" "d,n,Q")))
4180 (clobber (reg:CC 33))]
4181 ""
4182 "@
4183 or\\t%0,%2
4184 oi\\t%0,%b2
4185 oc\\t%O0(1,%R0),%2"
4186 [(set_attr "op_type" "RR,SI,SS")
4187 (set_attr "atype" "reg,mem,mem")])
4188
4189
4190 ;;
4191 ;;- Xor instructions.
4192 ;;
4193
4194 ;
4195 ; xordi3 instruction pattern(s).
4196 ;
4197
4198 (define_insn "xordi3"
4199 [(set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q")
4200 (xor:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0")
4201 (match_operand:DI 2 "r_or_s_operand" "d,m,Q")))
4202 (clobber (reg:CC 33))]
4203 "TARGET_64BIT"
4204 "@
4205 xgr\\t%0,%2
4206 xg\\t%0,%2
4207 xc\\t%O0(8,%R0),%2"
4208 [(set_attr "op_type" "RRE,RXE,SS")
4209 (set_attr "atype" "reg,mem,mem")])
4210
4211 ;
4212 ; xorsi3 instruction pattern(s).
4213 ;
4214
4215 (define_expand "xorsi3"
4216 [(parallel
4217 [(set (match_operand:SI 0 "r_or_s_operand" "")
4218 (xor:SI (match_operand:SI 1 "r_or_s_operand" "")
4219 (match_operand:SI 2 "r_or_s_operand" "")))
4220 (clobber (reg:CC 33))])]
4221 ""
4222 "
4223 {
4224 if (CONSTANT_P (operands[2]))
4225 operands[2] = force_const_mem (SImode, operands[2]);
4226 }")
4227
4228 (define_insn "*xorsi3"
4229 [(set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4230 (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4231 (match_operand:SI 2 "r_or_s_operand" "d,m,Q")))
4232 (clobber (reg:CC 33))]
4233 ""
4234 "@
4235 xr\\t%0,%2
4236 x\\t%0,%2
4237 xc\\t%O0(4,%R0),%2"
4238 [(set_attr "op_type" "RR,RX,SS")
4239 (set_attr "atype" "reg,mem,mem")])
4240
4241 ;
4242 ; xorhi3 instruction pattern(s).
4243 ;
4244
4245 (define_expand "xorhi3"
4246 [(parallel
4247 [(set (match_operand:HI 0 "r_or_s_operand" "")
4248 (xor:HI (match_operand:HI 1 "r_or_s_operand" "")
4249 (match_operand:HI 2 "r_or_s_operand" "")))
4250 (clobber (reg:CC 33))])]
4251 ""
4252 "
4253 {
4254 if (CONSTANT_P (operands[2]))
4255 operands[2] = force_const_mem (HImode, operands[2]);
4256 }")
4257
4258 (define_insn "*xorhi3"
4259 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4260 (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
4261 (match_operand:HI 2 "r_or_s_operand" "d,Q")))
4262 (clobber (reg:CC 33))]
4263 ""
4264 "@
4265 xr\\t%0,%2
4266 xc\\t%O0(2,%R0),%2"
4267 [(set_attr "op_type" "RR,SS")
4268 (set_attr "atype" "reg,mem")])
4269
4270 ;
4271 ; xorqi3 instruction pattern(s).
4272 ;
4273
4274 (define_insn "xorqi3"
4275 [(set (match_operand:QI 0 "r_or_s_operand" "=d,Q,Q")
4276 (xor:QI (match_operand:QI 1 "r_or_s_operand" "0,0,0")
4277 (match_operand:QI 2 "r_or_s_or_im8_operand" "d,n,Q")))
4278 (clobber (reg:CC 33))]
4279 ""
4280 "@
4281 xr\\t%0,%2
4282 xi\\t%0,%b2
4283 xc\\t%O0(1,%R0),%2"
4284 [(set_attr "op_type" "RR,SI,SS")
4285 (set_attr "atype" "reg,mem,mem")])
4286
4287
4288 ;;
4289 ;;- Negate instructions.
4290 ;;
4291
4292 ;
4293 ; negdi2 instruction pattern(s).
4294 ;
4295
4296 (define_expand "negdi2"
4297 [(parallel
4298 [(set (match_operand:DI 0 "register_operand" "=d")
4299 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4300 (clobber (reg:CC 33))])]
4301 ""
4302 "")
4303
4304 (define_insn "*negdi2_64"
4305 [(set (match_operand:DI 0 "register_operand" "=d")
4306 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4307 (clobber (reg:CC 33))]
4308 "TARGET_64BIT"
4309 "lcgr\\t%0,%1"
4310 [(set_attr "op_type" "RR")])
4311
4312 (define_insn "*negdi2_31"
4313 [(set (match_operand:DI 0 "register_operand" "=d")
4314 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4315 (clobber (reg:CC 33))]
4316 "!TARGET_64BIT"
4317 "*
4318 {
4319 rtx xop[1];
4320 xop[0] = gen_label_rtx ();
4321 output_asm_insn (\"lcr\\t%0,%1\", operands);
4322 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
4323 output_asm_insn (\"je\\t%l0\", xop);
4324 output_asm_insn (\"bctr\\t%0,0\", operands);
4325 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4326 CODE_LABEL_NUMBER (xop[0]));
4327 return \"\";
4328 }"
4329 [(set_attr "op_type" "NN")
4330 (set_attr "length" "10")])
4331
4332 ;
4333 ; negsi2 instruction pattern(s).
4334 ;
4335
4336 (define_insn "negsi2"
4337 [(set (match_operand:SI 0 "register_operand" "=d")
4338 (neg:SI (match_operand:SI 1 "register_operand" "d")))
4339 (clobber (reg:CC 33))]
4340 ""
4341 "lcr\\t%0,%1"
4342 [(set_attr "op_type" "RR")])
4343
4344 ;
4345 ; negdf2 instruction pattern(s).
4346 ;
4347
4348 (define_expand "negdf2"
4349 [(parallel
4350 [(set (match_operand:DF 0 "register_operand" "=f")
4351 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4352 (clobber (reg:CC 33))])]
4353 "TARGET_HARD_FLOAT"
4354 "")
4355
4356 (define_insn "*negdf2"
4357 [(set (match_operand:DF 0 "register_operand" "=f")
4358 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4359 (clobber (reg:CC 33))]
4360 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4361 "lcdbr\\t%0,%1"
4362 [(set_attr "op_type" "RR")])
4363
4364 (define_insn "*negdf2_ibm"
4365 [(set (match_operand:DF 0 "register_operand" "=f")
4366 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4367 (clobber (reg:CC 33))]
4368 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4369 "lcdr\\t%0,%1"
4370 [(set_attr "op_type" "RR")])
4371
4372 ;
4373 ; negsf2 instruction pattern(s).
4374 ;
4375
4376 (define_expand "negsf2"
4377 [(parallel
4378 [(set (match_operand:SF 0 "register_operand" "=f")
4379 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4380 (clobber (reg:CC 33))])]
4381 "TARGET_HARD_FLOAT"
4382 "")
4383
4384 (define_insn "*negsf2"
4385 [(set (match_operand:SF 0 "register_operand" "=f")
4386 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4387 (clobber (reg:CC 33))]
4388 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4389 "lcebr\\t%0,%1"
4390 [(set_attr "op_type" "RR")])
4391
4392 (define_insn "*negsf2"
4393 [(set (match_operand:SF 0 "register_operand" "=f")
4394 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4395 (clobber (reg:CC 33))]
4396 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4397 "lcer\\t%0,%1"
4398 [(set_attr "op_type" "RR")])
4399
4400
4401 ;;
4402 ;;- Absolute value instructions.
4403 ;;
4404
4405 ;
4406 ; absdi2 instruction pattern(s).
4407 ;
4408
4409 (define_insn "absdi2"
4410 [(set (match_operand:DI 0 "register_operand" "=d")
4411 (abs:DI (match_operand:DI 1 "register_operand" "d")))
4412 (clobber (reg:CC 33))]
4413 "TARGET_64BIT"
4414 "lpgr\\t%0,%1"
4415 [(set_attr "op_type" "RRE")])
4416
4417 ;
4418 ; abssi2 instruction pattern(s).
4419 ;
4420
4421 (define_insn "abssi2"
4422 [(set (match_operand:SI 0 "register_operand" "=d")
4423 (abs:SI (match_operand:SI 1 "register_operand" "d")))
4424 (clobber (reg:CC 33))]
4425 ""
4426 "lpr\\t%0,%1"
4427 [(set_attr "op_type" "RR")])
4428
4429 ;
4430 ; abshi2 instruction pattern(s).
4431 ;
4432
4433 (define_insn "abshi2"
4434 [(set (match_operand:HI 0 "register_operand" "=d")
4435 (abs:HI (match_operand:HI 1 "register_operand" "d")))
4436 (clobber (reg:CC 33))]
4437 ""
4438 "sll\\t%1,16\;sra\\t%1,16\;lpr\\t%0,%1"
4439 [(set_attr "op_type" "NN")
4440 (set_attr "type" "o3")
4441 (set_attr "length" "10")])
4442
4443 ;
4444 ; absdf2 instruction pattern(s).
4445 ;
4446
4447 (define_expand "absdf2"
4448 [(parallel
4449 [(set (match_operand:DF 0 "register_operand" "=f")
4450 (abs:DF (match_operand:DF 1 "register_operand" "f")))
4451 (clobber (reg:CC 33))])]
4452 "TARGET_HARD_FLOAT"
4453 "")
4454
4455 (define_insn "*absdf2"
4456 [(set (match_operand:DF 0 "register_operand" "=f")
4457 (abs:DF (match_operand:DF 1 "register_operand" "f")))
4458 (clobber (reg:CC 33))]
4459 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4460 "lpdbr\\t%0,%1"
4461 [(set_attr "op_type" "RR")])
4462
4463 (define_insn "*absdf2_ibm"
4464 [(set (match_operand:DF 0 "register_operand" "=f")
4465 (abs:DF (match_operand:DF 1 "register_operand" "f")))
4466 (clobber (reg:CC 33))]
4467 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4468 "lpdr\\t%0,%1"
4469 [(set_attr "op_type" "RR")])
4470
4471 ;
4472 ; abssf2 instruction pattern(s).
4473 ;
4474
4475 (define_expand "abssf2"
4476 [(parallel
4477 [(set (match_operand:SF 0 "register_operand" "=f")
4478 (abs:SF (match_operand:SF 1 "register_operand" "f")))
4479 (clobber (reg:CC 33))])]
4480 "TARGET_HARD_FLOAT"
4481 "")
4482
4483 (define_insn "*abssf2"
4484 [(set (match_operand:SF 0 "register_operand" "=f")
4485 (abs:SF (match_operand:SF 1 "register_operand" "f")))
4486 (clobber (reg:CC 33))]
4487 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4488 "lpebr\\t%0,%1"
4489 [(set_attr "op_type" "RR")])
4490
4491 (define_insn "*abssf2_ibm"
4492 [(set (match_operand:SF 0 "register_operand" "=f")
4493 (abs:SF (match_operand:SF 1 "register_operand" "f")))
4494 (clobber (reg:CC 33))]
4495 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4496 "lper\\t%0,%1"
4497 [(set_attr "op_type" "RR")])
4498
4499
4500 ;;
4501 ;;- One complement instructions.
4502 ;;
4503
4504 ;
4505 ; one_cmpldi2 instruction pattern(s).
4506 ;
4507
4508 (define_expand "one_cmpldi2"
4509 [(parallel
4510 [(set (match_operand:DI 0 "r_or_s_operand" "=d")
4511 (not:DI (match_operand:DI 1 "r_or_s_operand" "0")))
4512 (use (match_dup 2))
4513 (clobber (reg:CC 33))])]
4514 "TARGET_64BIT"
4515 "{ operands[2] = force_const_mem (DImode, constm1_rtx); }")
4516
4517 (define_insn "*one_cmpldi2"
4518 [(set (match_operand:DI 0 "r_or_s_operand" "=d,Q")
4519 (not:DI (match_operand:DI 1 "r_or_s_operand" "0,0")))
4520 (use (match_operand:DI 2 "memory_operand" "m,m"))
4521 (clobber (reg:CC 33))]
4522 ""
4523 "@
4524 xg\\t%0,%2
4525 xc\\t%O0(8,%R0),%2"
4526 [(set_attr "op_type" "RR,SS")
4527 (set_attr "atype" "mem")])
4528
4529 ;
4530 ; one_cmplsi2 instruction pattern(s).
4531 ;
4532
4533 (define_expand "one_cmplsi2"
4534 [(parallel
4535 [(set (match_operand:SI 0 "r_or_s_operand" "=d")
4536 (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))
4537 (use (match_dup 2))
4538 (clobber (reg:CC 33))])]
4539 ""
4540 "{ operands[2] = force_const_mem (SImode, constm1_rtx); }")
4541
4542 (define_insn "*one_cmplsi2"
4543 [(set (match_operand:SI 0 "r_or_s_operand" "=d,Q")
4544 (not:SI (match_operand:SI 1 "r_or_s_operand" "0,0")))
4545 (use (match_operand:SI 2 "memory_operand" "m,m"))
4546 (clobber (reg:CC 33))]
4547 ""
4548 "@
4549 x\\t%0,%2
4550 xc\\t%O0(4,%R0),%2"
4551 [(set_attr "op_type" "RR,SS")
4552 (set_attr "atype" "mem")])
4553
4554 ;
4555 ; one_cmplhi2 instruction pattern(s).
4556 ;
4557
4558 (define_expand "one_cmplhi2"
4559 [(parallel
4560 [(set (match_operand:HI 0 "r_or_s_operand" "=d")
4561 (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))
4562 (use (match_dup 2))
4563 (clobber (reg:CC 33))])]
4564 ""
4565 "{ operands[2] = force_const_mem (SImode, constm1_rtx); }")
4566
4567 (define_insn "*one_cmplhi2"
4568 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4569 (not:HI (match_operand:HI 1 "r_or_s_operand" "0,0")))
4570 (use (match_operand:SI 2 "memory_operand" "m,m"))
4571 (clobber (reg:CC 33))]
4572 ""
4573 "@
4574 x\\t%0,%2
4575 xc\\t%O0(2,%R0),%2"
4576 [(set_attr "op_type" "RX,SS")
4577 (set_attr "atype" "mem")])
4578
4579 ;
4580 ; one_cmplqi2 instruction pattern(s).
4581 ;
4582
4583 (define_insn "one_cmpqi2"
4584 [(set (match_operand:QI 0 "memory_operand" "=Q")
4585 (not:QI (match_operand:QI 1 "memory_operand" "0")))
4586 (clobber (reg:CC 33))]
4587 ""
4588 "xi\\t%0,255"
4589 [(set_attr "op_type" "SI")])
4590
4591
4592 ;;
4593 ;;- Rotate instructions.
4594 ;;
4595
4596 ;
4597 ; rotldi3 instruction pattern(s).
4598 ;
4599
4600 (define_insn "rotldi3"
4601 [(set (match_operand:DI 0 "register_operand" "=d,d")
4602 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
4603 (match_operand:DI 2 "nonmemory_operand" "J,a")))
4604 (clobber (reg:CC 33))]
4605 "TARGET_64BIT"
4606 "@
4607 rllg\\t%0,%1,%c2
4608 rllg\\t%0,%1,0(%2)"
4609 [(set_attr "op_type" "RSE")])
4610
4611 ;
4612 ; rotlsi3 instruction pattern(s).
4613 ;
4614
4615 (define_insn "rotlsi3"
4616 [(set (match_operand:SI 0 "register_operand" "=d,d")
4617 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
4618 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4619 (clobber (reg:CC 33))]
4620 "TARGET_64BIT"
4621 "@
4622 rll\\t%0,%1,%c2
4623 rll\\t%0,%1,0(%2)"
4624 [(set_attr "op_type" "RSE")])
4625
4626
4627 ;;
4628 ;;- Arithmetic shift instructions.
4629 ;;
4630 ;; for left shifts always setal shifts are used (ANSI-C)
4631
4632 ;
4633 ; ashldi3 instruction pattern(s).
4634 ;
4635
4636 (define_expand "ashldi3"
4637 [(parallel
4638 [(set (match_operand:DI 0 "register_operand" "")
4639 (ashift:DI (match_operand:DI 1 "register_operand" "")
4640 (match_operand:SI 2 "nonmemory_operand" "")))
4641 (clobber (reg:CC 33))])]
4642 ""
4643 "")
4644
4645 (define_insn "*ashldi3_31"
4646 [(set (match_operand:DI 0 "register_operand" "=d,d")
4647 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
4648 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4649 (clobber (reg:CC 33))]
4650 "!TARGET_64BIT"
4651 "@
4652 sldl\\t%0,%c2
4653 sldl\\t%0,0(%2)"
4654 [(set_attr "op_type" "RS")])
4655
4656 (define_insn "*ashldi3_64"
4657 [(set (match_operand:DI 0 "register_operand" "=d,d")
4658 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
4659 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4660 (clobber (reg:CC 33))]
4661 "TARGET_64BIT"
4662 "@
4663 sllg\\t%0,%1,%2
4664 sllg\\t%0,%1,0(%2)"
4665 [(set_attr "op_type" "RSE")])
4666
4667 ;
4668 ; ashrdi3 instruction pattern(s).
4669 ;
4670
4671 (define_expand "ashrdi3"
4672 [(parallel
4673 [(set (match_operand:DI 0 "register_operand" "")
4674 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4675 (match_operand:SI 2 "nonmemory_operand" "")))
4676 (clobber (reg:CC 33))])]
4677 ""
4678 "")
4679
4680 (define_insn "*ashrdi3_31"
4681 [(set (match_operand:DI 0 "register_operand" "=d,d")
4682 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4683 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4684 (clobber (reg:CC 33))]
4685 "!TARGET_64BIT"
4686 "@
4687 srda\\t%0,%c2
4688 srda\\t%0,0(%2)"
4689 [(set_attr "op_type" "RS")])
4690
4691 (define_insn "*ashrdi3_64"
4692 [(set (match_operand:DI 0 "register_operand" "=d,d")
4693 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
4694 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4695 (clobber (reg:CC 33))]
4696 "TARGET_64BIT"
4697 "@
4698 srag\\t%0,%1,%c2
4699 srag\\t%0,%1,0(%2)"
4700 [(set_attr "op_type" "RSE")])
4701
4702 ;
4703 ; ashlsi3 instruction pattern(s).
4704 ;
4705 ; all 32 bits has to be shifted (testcase co750c)
4706
4707 (define_insn "ashlsi3"
4708 [(set (match_operand:SI 0 "register_operand" "=d,d")
4709 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
4710 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4711 (clobber (reg:CC 33))]
4712 ""
4713 "@
4714 sll\\t%0,%c2
4715 sll\\t%0,0(%2)"
4716 [(set_attr "op_type" "RS")])
4717
4718 ;
4719 ; ashrsi3 instruction pattern(s).
4720 ;
4721
4722 (define_insn "ashrsi3"
4723 [(set (match_operand:SI 0 "register_operand" "=d,d")
4724 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
4725 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4726 (clobber (reg:CC 33))]
4727 ""
4728 "@
4729 sra\\t%0,%c2
4730 sra\\t%0,0(%2)"
4731 [(set_attr "op_type" "RS")])
4732
4733 ;
4734 ; ashlhi3 instruction pattern(s).
4735 ;
4736
4737 (define_insn "ashlhi3"
4738 [(set (match_operand:HI 0 "register_operand" "=d,d")
4739 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
4740 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4741 (clobber (reg:CC 33))]
4742 ""
4743 "@
4744 sll\\t%0,%c2
4745 sll\\t%0,0(%2)"
4746 [(set_attr "op_type" "RS,RS")])
4747
4748 ;
4749 ; ashrhi3 instruction pattern(s).
4750 ;
4751
4752 (define_insn "ashrhi3"
4753 [(set (match_operand:HI 0 "register_operand" "=d,d")
4754 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
4755 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4756 (clobber (reg:CC 33))]
4757 ""
4758 "@
4759 sll\\t%0,16\;sra\\t%0,16+%c2
4760 sll\\t%0,16\;sra\\t%0,16(%2)"
4761 [(set_attr "op_type" "NN,NN")
4762 (set_attr "length" "8,8")])
4763
4764
4765 ;;
4766 ;;- logical shift instructions.
4767 ;;
4768
4769 ;
4770 ; lshrdi3 instruction pattern(s).
4771 ;
4772
4773 (define_expand "lshrdi3"
4774 [(parallel
4775 [(set (match_operand:DI 0 "register_operand" "")
4776 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4777 (match_operand:SI 2 "nonmemory_operand" "")))
4778 (clobber (reg:CC 33))])]
4779 ""
4780 "")
4781
4782 (define_insn "*lshrdi3_31"
4783 [(set (match_operand:DI 0 "register_operand" "=d,d")
4784 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4785 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4786 (clobber (reg:CC 33))]
4787 "!TARGET_64BIT"
4788 "@
4789 srdl\\t%0,%c2
4790 srdl\\t%0,0(%2)"
4791 [(set_attr "op_type" "RS,RS")])
4792
4793 (define_insn "*lshrdi3_64"
4794 [(set (match_operand:DI 0 "register_operand" "=d,d")
4795 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
4796 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4797 (clobber (reg:CC 33))]
4798 "TARGET_64BIT"
4799 "@
4800 srlg\\t%0,%1,%c2
4801 srlg\\t%0,%1,0(%2)"
4802 [(set_attr "op_type" "RS,RS")])
4803
4804 ;
4805 ; lshrsi3 instruction pattern(s).
4806 ;
4807
4808 (define_insn "lshrsi3"
4809 [(set (match_operand:SI 0 "register_operand" "=d,d")
4810 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
4811 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4812 (clobber (reg:CC 33))]
4813 ""
4814 "@
4815 srl\\t%0,%c2
4816 srl\\t%0,0(%2)"
4817 [(set_attr "op_type" "RS")])
4818
4819 ;
4820 ; lshrhi3 instruction pattern(s).
4821 ;
4822
4823 (define_insn "lshrhi3"
4824 [(set (match_operand:HI 0 "register_operand" "=d,d")
4825 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
4826 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4827 (clobber (reg:CC 33))]
4828 ""
4829 "@
4830 sll\\t%0,16\;srl\\t%0,16+%c2
4831 sll\\t%0,16\;srl\\t%0,16(%2)"
4832 [(set_attr "op_type" "NN,NN")
4833 (set_attr "length" "8,8")])
4834
4835
4836 ;;
4837 ;; Branch instruction patterns.
4838 ;;
4839
4840 (define_expand "beq"
4841 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
4842 (set (pc)
4843 (if_then_else (eq (reg:CCZ 33) (const_int 0))
4844 (label_ref (match_operand 0 "" ""))
4845 (pc)))]
4846 ""
4847 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4848
4849 (define_expand "bne"
4850 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
4851 (set (pc)
4852 (if_then_else (ne (reg:CCZ 33) (const_int 0))
4853 (label_ref (match_operand 0 "" ""))
4854 (pc)))]
4855 ""
4856 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4857
4858 (define_expand "bgt"
4859 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4860 (set (pc)
4861 (if_then_else (gt (reg:CCS 33) (const_int 0))
4862 (label_ref (match_operand 0 "" ""))
4863 (pc)))]
4864 ""
4865 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4866
4867 (define_expand "bgtu"
4868 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
4869 (set (pc)
4870 (if_then_else (gtu (reg:CCU 33) (const_int 0))
4871 (label_ref (match_operand 0 "" ""))
4872 (pc)))]
4873 ""
4874 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4875
4876 (define_expand "blt"
4877 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4878 (set (pc)
4879 (if_then_else (lt (reg:CCS 33) (const_int 0))
4880 (label_ref (match_operand 0 "" ""))
4881 (pc)))]
4882 ""
4883 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4884
4885 (define_expand "bltu"
4886 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
4887 (set (pc)
4888 (if_then_else (ltu (reg:CCU 33) (const_int 0))
4889 (label_ref (match_operand 0 "" ""))
4890 (pc)))]
4891 ""
4892 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4893
4894 (define_expand "bge"
4895 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4896 (set (pc)
4897 (if_then_else (ge (reg:CCS 33) (const_int 0))
4898 (label_ref (match_operand 0 "" ""))
4899 (pc)))]
4900 ""
4901 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4902
4903 (define_expand "bgeu"
4904 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
4905 (set (pc)
4906 (if_then_else (geu (reg:CCU 33) (const_int 0))
4907 (label_ref (match_operand 0 "" ""))
4908 (pc)))]
4909 ""
4910 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4911
4912 (define_expand "ble"
4913 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4914 (set (pc)
4915 (if_then_else (le (reg:CCS 33) (const_int 0))
4916 (label_ref (match_operand 0 "" ""))
4917 (pc)))]
4918 ""
4919 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4920
4921 (define_expand "bleu"
4922 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
4923 (set (pc)
4924 (if_then_else (leu (reg:CCU 33) (const_int 0))
4925 (label_ref (match_operand 0 "" ""))
4926 (pc)))]
4927 ""
4928 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4929
4930 (define_expand "bunordered"
4931 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4932 (set (pc)
4933 (if_then_else (unordered (reg:CCS 33) (const_int 0))
4934 (label_ref (match_operand 0 "" ""))
4935 (pc)))]
4936 ""
4937 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4938
4939 (define_expand "bordered"
4940 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4941 (set (pc)
4942 (if_then_else (ordered (reg:CCS 33) (const_int 0))
4943 (label_ref (match_operand 0 "" ""))
4944 (pc)))]
4945 ""
4946 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4947
4948 (define_expand "buneq"
4949 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4950 (set (pc)
4951 (if_then_else (uneq (reg:CCS 33) (const_int 0))
4952 (label_ref (match_operand 0 "" ""))
4953 (pc)))]
4954 ""
4955 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4956
4957 (define_expand "bungt"
4958 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4959 (set (pc)
4960 (if_then_else (ungt (reg:CCS 33) (const_int 0))
4961 (label_ref (match_operand 0 "" ""))
4962 (pc)))]
4963 ""
4964 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4965
4966 (define_expand "bunlt"
4967 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4968 (set (pc)
4969 (if_then_else (unlt (reg:CCS 33) (const_int 0))
4970 (label_ref (match_operand 0 "" ""))
4971 (pc)))]
4972 ""
4973 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4974
4975 (define_expand "bunge"
4976 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4977 (set (pc)
4978 (if_then_else (unge (reg:CCS 33) (const_int 0))
4979 (label_ref (match_operand 0 "" ""))
4980 (pc)))]
4981 ""
4982 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4983
4984 (define_expand "bunle"
4985 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4986 (set (pc)
4987 (if_then_else (unle (reg:CCS 33) (const_int 0))
4988 (label_ref (match_operand 0 "" ""))
4989 (pc)))]
4990 ""
4991 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4992
4993 (define_expand "bltgt"
4994 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4995 (set (pc)
4996 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
4997 (label_ref (match_operand 0 "" ""))
4998 (pc)))]
4999 ""
5000 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5001
5002
5003 ;;
5004 ;;- Conditional jump instructions.
5005 ;;
5006
5007 (define_insn "cjump"
5008 [(set (pc)
5009 (if_then_else
5010 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5011 (label_ref (match_operand 0 "" ""))
5012 (pc)))]
5013 ""
5014 "*
5015 {
5016 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5017 return \"j%C1\\t%l0\";
5018 else
5019 return \"jg%C1\\t%l0\";
5020 }"
5021 [(set_attr "op_type" "RI")
5022 (set (attr "length") (if_then_else
5023 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5024 (const_int 4) (const_int 6)))])
5025
5026 (define_insn "*cjump_long"
5027 [(set (pc)
5028 (if_then_else
5029 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5030 (match_operand 0 "address_operand" "p")
5031 (pc)))]
5032 ""
5033 "*
5034 {
5035 if (get_attr_op_type (insn) == OP_TYPE_RR)
5036 return \"b%C1r\\t%0\";
5037 else
5038 return \"b%C1\\t%a0\";
5039 }"
5040 [(set (attr "op_type")
5041 (if_then_else (match_operand 0 "register_operand" "")
5042 (const_string "RR") (const_string "RX")))
5043 (set_attr "atype" "mem")])
5044
5045
5046 ;;
5047 ;;- Negated conditional jump instructions.
5048 ;;
5049
5050 (define_insn "icjump"
5051 [(set (pc)
5052 (if_then_else
5053 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5054 (pc)
5055 (label_ref (match_operand 0 "" ""))))]
5056 ""
5057 "*
5058 {
5059 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5060 return \"j%D1\\t%l0\";
5061 else
5062 return \"jg%D1\\t%l0\";
5063 }"
5064 [(set_attr "op_type" "RI")
5065 (set (attr "length") (if_then_else
5066 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5067 (const_int 4) (const_int 6)))])
5068
5069 (define_insn "*icjump_long"
5070 [(set (pc)
5071 (if_then_else
5072 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5073 (pc)
5074 (match_operand 0 "address_operand" "p")))]
5075 ""
5076 "*
5077 {
5078 if (get_attr_op_type (insn) == OP_TYPE_RR)
5079 return \"b%D1r\\t%0\";
5080 else
5081 return \"b%D1\\t%a0\";
5082 }"
5083 [(set (attr "op_type")
5084 (if_then_else (match_operand 0 "register_operand" "")
5085 (const_string "RR") (const_string "RX")))
5086 (set_attr "atype" "mem")])
5087
5088
5089 ;;
5090 ;;- Subtract one and jump if not zero.
5091 ;;
5092
5093 ;(define_expand "decrement_and_branch_on_count"
5094 ; [(use (match_operand 0 "register_operand" ""))
5095 ; (use (label_ref (match_operand 1 "" "")))]
5096 ; ""
5097 ; "
5098 ;{
5099 ;/* if (TARGET_64BIT)
5100 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5101 ; else */
5102 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5103 ; DONE;
5104 ;}")
5105 ;
5106 ;(define_insn "brctsi"
5107 ; [(set (pc)
5108 ; (if_then_else
5109 ; (ne (match_operand:SI 0 "register_operand" "+a")
5110 ; (const_int 1))
5111 ; (label_ref (match_operand 1 "" ""))
5112 ; (pc)))
5113 ; (set (match_dup 0)
5114 ; (plus:SI (match_dup 0) (const_int -1)))]
5115 ; ""
5116 ; "brct\\t%0,%l1"
5117 ; [(set_attr "op_type" "RI")
5118 ; (set_attr "type" "branch")]
5119 ;)
5120 ;
5121 ;(define_insn "ibrctsi"
5122 ; [(set (pc)
5123 ; (if_then_else
5124 ; (eq (match_operand:SI 0 "register_operand" "+a")
5125 ; (const_int 1))
5126 ; (pc)
5127 ; (label_ref (match_operand 1 "" ""))))
5128 ; (set (match_dup 0)
5129 ; (plus:SI (match_dup 0) (const_int -1)))]
5130 ; ""
5131 ; "brct\\t%0,%l1"
5132 ; [(set_attr "op_type" "RI")
5133 ; (set_attr "type" "branch")]
5134 ;)
5135
5136
5137 ;;
5138 ;;- Unconditional jump instructions.
5139 ;;
5140
5141 ;
5142 ; jump instruction pattern(s).
5143 ;
5144
5145 (define_insn "jump"
5146 [(set (pc) (label_ref (match_operand 0 "" "")))]
5147 ""
5148 "*
5149 {
5150 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5151 return \"j\\t%l0\";
5152 else
5153 return \"jg\\t%l0\";
5154 }"
5155 [(set_attr "op_type" "RI")
5156 (set (attr "length") (if_then_else
5157 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5158 (const_int 4) (const_int 6)))])
5159
5160 ;
5161 ; indirect-jump instruction pattern(s).
5162 ;
5163
5164 (define_insn "indirect_jump"
5165 [(set (pc) (match_operand 0 "address_operand" "p"))]
5166 ""
5167 "*
5168 {
5169 if (get_attr_op_type (insn) == OP_TYPE_RR)
5170 return \"br\\t%0\";
5171 else
5172 return \"b\\t%a0\";
5173 }"
5174 [(set (attr "op_type")
5175 (if_then_else (match_operand 0 "register_operand" "")
5176 (const_string "RR") (const_string "RX")))
5177 (set_attr "atype" "mem")])
5178
5179 ;
5180 ; casesi instruction pattern(s).
5181 ;
5182
5183 (define_insn "casesi_jump"
5184 [(set (pc) (match_operand 0 "address_operand" "p"))
5185 (use (label_ref (match_operand 1 "" "")))]
5186 ""
5187 "*
5188 {
5189 if (get_attr_op_type (insn) == OP_TYPE_RR)
5190 return \"br\\t%0\";
5191 else
5192 return \"b\\t%a0\";
5193 }"
5194 [(set (attr "op_type")
5195 (if_then_else (match_operand 0 "register_operand" "")
5196 (const_string "RR") (const_string "RX")))
5197 (set_attr "atype" "mem")])
5198
5199 (define_expand "casesi"
5200 [(match_operand:SI 0 "general_operand" "")
5201 (match_operand:SI 1 "general_operand" "")
5202 (match_operand:SI 2 "general_operand" "")
5203 (label_ref (match_operand 3 "" ""))
5204 (label_ref (match_operand 4 "" ""))]
5205 ""
5206 "
5207 {
5208 rtx index = gen_reg_rtx (SImode);
5209 rtx base = gen_reg_rtx (Pmode);
5210 rtx target = gen_reg_rtx (Pmode);
5211
5212 emit_move_insn (index, operands[0]);
5213 emit_insn (gen_subsi3 (index, index, operands[1]));
5214 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
5215 0, operands[4]);
5216
5217 if (Pmode != SImode)
5218 index = convert_to_mode (Pmode, index, 1);
5219 if (GET_CODE (index) != REG)
5220 index = copy_to_mode_reg (Pmode, index);
5221
5222 if (TARGET_64BIT)
5223 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
5224 else
5225 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
5226
5227 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
5228
5229 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
5230 emit_move_insn (target, index);
5231
5232 if (flag_pic)
5233 target = gen_rtx_PLUS (Pmode, base, target);
5234 emit_jump_insn (gen_casesi_jump (target, operands[3]));
5235
5236 DONE;
5237 }")
5238
5239
5240 ;;
5241 ;;- Jump to subroutine.
5242 ;;
5243 ;;
5244
5245 ;
5246 ; untyped call instruction pattern(s).
5247 ;
5248
5249 ;; Call subroutine returning any type.
5250 (define_expand "untyped_call"
5251 [(parallel [(call (match_operand 0 "" "")
5252 (const_int 0))
5253 (match_operand 1 "" "")
5254 (match_operand 2 "" "")])]
5255 ""
5256 "
5257 {
5258 int i;
5259
5260 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
5261
5262 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5263 {
5264 rtx set = XVECEXP (operands[2], 0, i);
5265 emit_move_insn (SET_DEST (set), SET_SRC (set));
5266 }
5267
5268 /* The optimizer does not know that the call sets the function value
5269 registers we stored in the result block. We avoid problems by
5270 claiming that all hard registers are used and clobbered at this
5271 point. */
5272 emit_insn (gen_blockage ());
5273
5274 DONE;
5275 }")
5276
5277 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5278 ;; all of memory. This blocks insns from being moved across this point.
5279
5280 (define_insn "blockage"
5281 [(unspec_volatile [(const_int 0)] 0)]
5282 ""
5283 "")
5284
5285
5286 ;
5287 ; call instruction pattern(s).
5288 ;
5289
5290 (define_expand "call"
5291 [(parallel [(call (match_operand 0 "" "")
5292 (match_operand 1 "" ""))
5293 (clobber (match_operand 2 "" ""))])]
5294 ""
5295 "
5296 {
5297 /* Abuse operand 2 to hold the return register. */
5298 operands[2] = gen_rtx_REG (Pmode, RETURN_REGNUM);
5299
5300 /* In 31-bit, we must load the GOT register even if the
5301 compiler doesn't know about it, because the PLT glue
5302 code uses it. In 64-bit, this is not necessary. */
5303 if (flag_pic && !TARGET_64BIT)
5304 current_function_uses_pic_offset_table = 1;
5305
5306 /* Direct function calls need special treatment. */
5307 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5308 {
5309 rtx sym = XEXP (operands[0], 0);
5310
5311 /* When calling a global routine in PIC mode, we must
5312 replace the symbol itself with the PLT stub. */
5313 if (flag_pic && !SYMBOL_REF_FLAG(sym))
5314 {
5315 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5316 sym = gen_rtx_CONST (Pmode, sym);
5317 }
5318
5319 /* Unless we can use the bras(l) insn, force the
5320 routine address into a register. */
5321 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5322 {
5323 rtx target = gen_reg_rtx (Pmode);
5324 emit_move_insn (target, sym);
5325 sym = target;
5326 }
5327
5328 operands[0] = gen_rtx_MEM (QImode, sym);
5329 }
5330 }")
5331
5332 (define_insn "brasl"
5333 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
5334 (match_operand:SI 1 "const_int_operand" "n"))
5335 (clobber (match_operand:DI 2 "register_operand" "=r"))]
5336 "TARGET_64BIT"
5337 "brasl\\t%2,%0"
5338 [(set_attr "op_type" "RIL")
5339 (set_attr "type" "jsr")])
5340
5341 (define_insn "bras"
5342 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
5343 (match_operand:SI 1 "const_int_operand" "n"))
5344 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5345 "TARGET_SMALL_EXEC"
5346 "bras\\t%2,%0"
5347 [(set_attr "op_type" "RI")
5348 (set_attr "type" "jsr")])
5349
5350 (define_insn "basr_64"
5351 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
5352 (match_operand:SI 1 "const_int_operand" "n"))
5353 (clobber (match_operand:DI 2 "register_operand" "=r"))]
5354 "TARGET_64BIT"
5355 "basr\\t%2,%0"
5356 [(set_attr "op_type" "RR")
5357 (set_attr "type" "jsr")
5358 (set_attr "atype" "mem")])
5359
5360 (define_insn "basr_31"
5361 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
5362 (match_operand:SI 1 "const_int_operand" "n"))
5363 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5364 "!TARGET_64BIT"
5365 "basr\\t%2,%0"
5366 [(set_attr "op_type" "RR")
5367 (set_attr "type" "jsr")
5368 (set_attr "atype" "mem")])
5369
5370 (define_insn "bas_64"
5371 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
5372 (match_operand:SI 1 "const_int_operand" "n"))
5373 (clobber (match_operand:DI 2 "register_operand" "=r"))]
5374 "TARGET_64BIT"
5375 "bas\\t%2,%a0"
5376 [(set_attr "op_type" "RX")
5377 (set_attr "type" "jsr")
5378 (set_attr "atype" "mem")])
5379
5380 (define_insn "bas_31"
5381 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
5382 (match_operand:SI 1 "const_int_operand" "n"))
5383 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5384 "!TARGET_64BIT"
5385 "bas\\t%2,%a0"
5386 [(set_attr "op_type" "RX")
5387 (set_attr "type" "jsr")
5388 (set_attr "atype" "mem")])
5389
5390
5391 ;
5392 ; call_value instruction pattern(s).
5393 ;
5394
5395 (define_expand "call_value"
5396 [(parallel [(set (match_operand 0 "" "")
5397 (call (match_operand 1 "" "")
5398 (match_operand 2 "" "")))
5399 (clobber (match_operand 3 "" ""))])]
5400 ""
5401 "
5402 {
5403 /* Abuse operand 3 to hold the return register. */
5404 operands[3] = gen_rtx_REG (Pmode, RETURN_REGNUM);
5405
5406 /* In 31-bit, we must load the GOT register even if the
5407 compiler doesn't know about it, because the PLT glue
5408 code uses it. In 64-bit, this is not necessary. */
5409 if (flag_pic && !TARGET_64BIT)
5410 current_function_uses_pic_offset_table = 1;
5411
5412 /* Direct function calls need special treatment. */
5413 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
5414 {
5415 rtx sym = XEXP (operands[1], 0);
5416
5417 /* When calling a global routine in PIC mode, we must
5418 replace the symbol itself with the PLT stub. */
5419 if (flag_pic && !SYMBOL_REF_FLAG(sym))
5420 {
5421 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5422 sym = gen_rtx_CONST (Pmode, sym);
5423 }
5424
5425 /* Unless we can use the bras(l) insn, force the
5426 routine address into a register. */
5427 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5428 {
5429 rtx target = gen_reg_rtx (Pmode);
5430 emit_move_insn (target, sym);
5431 sym = target;
5432 }
5433
5434 operands[1] = gen_rtx_MEM (QImode, sym);
5435 }
5436 }")
5437
5438 (define_insn "brasl_r"
5439 [(set (match_operand 0 "register_operand" "=df")
5440 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
5441 (match_operand:SI 2 "const_int_operand" "n")))
5442 (clobber (match_operand:DI 3 "register_operand" "=r"))]
5443 "TARGET_64BIT"
5444 "brasl\\t%3,%1"
5445 [(set_attr "op_type" "RIL")
5446 (set_attr "type" "jsr")])
5447
5448 (define_insn "bras_r"
5449 [(set (match_operand 0 "register_operand" "=df")
5450 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
5451 (match_operand:SI 2 "const_int_operand" "n")))
5452 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5453 "TARGET_SMALL_EXEC"
5454 "bras\\t%3,%1"
5455 [(set_attr "op_type" "RI")
5456 (set_attr "type" "jsr")])
5457
5458 (define_insn "basr_r_64"
5459 [(set (match_operand 0 "register_operand" "=df")
5460 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
5461 (match_operand:SI 2 "const_int_operand" "n")))
5462 (clobber (match_operand:DI 3 "register_operand" "=r"))]
5463 "TARGET_64BIT"
5464 "basr\\t%3,%1"
5465 [(set_attr "op_type" "RR")
5466 (set_attr "type" "jsr")])
5467
5468 (define_insn "basr_r_31"
5469 [(set (match_operand 0 "register_operand" "=df")
5470 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
5471 (match_operand:SI 2 "const_int_operand" "n")))
5472 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5473 "!TARGET_64BIT"
5474 "basr\\t%3,%1"
5475 [(set_attr "op_type" "RR")
5476 (set_attr "type" "jsr")
5477 (set_attr "atype" "mem")])
5478
5479 (define_insn "bas_r_64"
5480 [(set (match_operand 0 "register_operand" "=df")
5481 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
5482 (match_operand:SI 2 "const_int_operand" "n")))
5483 (clobber (match_operand:DI 3 "register_operand" "=r"))]
5484 "TARGET_64BIT"
5485 "bas\\t%3,%a1"
5486 [(set_attr "op_type" "RX")
5487 (set_attr "type" "jsr")
5488 (set_attr "atype" "mem")])
5489
5490 (define_insn "bas_r_31"
5491 [(set (match_operand 0 "register_operand" "=df")
5492 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
5493 (match_operand:SI 2 "const_int_operand" "n")))
5494 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5495 "!TARGET_64BIT"
5496 "bas\\t%3,%a1"
5497 [(set_attr "op_type" "RX")
5498 (set_attr "type" "jsr")
5499 (set_attr "atype" "mem")])
5500
5501
5502 ;;
5503 ;;- Miscellaneous instructions.
5504 ;;
5505
5506 ;
5507 ; allocate stack instruction pattern(s).
5508 ;
5509
5510 (define_expand "allocate_stack"
5511 [(set (reg 15)
5512 (plus (reg 15) (match_operand 1 "general_operand" "")))
5513 (set (match_operand 0 "general_operand" "")
5514 (reg 15))]
5515 ""
5516 "
5517 {
5518 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
5519 rtx chain = gen_rtx (MEM, Pmode, stack);
5520 rtx temp = gen_reg_rtx (Pmode);
5521
5522 emit_move_insn (temp, chain);
5523
5524 if (TARGET_64BIT)
5525 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
5526 else
5527 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
5528
5529 emit_move_insn (chain, temp);
5530
5531 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5532 DONE;
5533 }")
5534
5535
5536 ;
5537 ; setjmp/longjmp instruction pattern(s).
5538 ;
5539
5540 (define_expand "builtin_setjmp_setup"
5541 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
5542 ""
5543 "
5544 {
5545 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
5546 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
5547
5548 emit_move_insn (base, basereg);
5549 DONE;
5550 }")
5551
5552 (define_expand "builtin_setjmp_receiver"
5553 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5554 "flag_pic"
5555 "
5556 {
5557 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
5558 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
5559 SYMBOL_REF_FLAG (got) = 1;
5560
5561 emit_move_insn (gotreg, got);
5562 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
5563 DONE;
5564 }")
5565
5566 (define_expand "builtin_longjmp"
5567 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
5568 ""
5569 "
5570 {
5571 /* The elements of the buffer are, in order: */
5572 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5573 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
5574 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
5575 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
5576 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
5577 rtx jmp = gen_rtx_REG (Pmode, 14);
5578
5579 emit_move_insn (jmp, lab);
5580 emit_move_insn (basereg, base);
5581 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5582 emit_move_insn (hard_frame_pointer_rtx, fp);
5583
5584 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5585 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5586 emit_insn (gen_rtx_USE (VOIDmode, basereg));
5587 emit_indirect_jump (jmp);
5588 DONE;
5589 }")
5590
5591
5592 ;; These patterns say how to save and restore the stack pointer. We need not
5593 ;; save the stack pointer at function level since we are careful to
5594 ;; preserve the backchain. At block level, we have to restore the backchain
5595 ;; when we restore the stack pointer.
5596 ;;
5597 ;; For nonlocal gotos, we must save both the stack pointer and its
5598 ;; backchain and restore both. Note that in the nonlocal case, the
5599 ;; save area is a memory location.
5600
5601 (define_expand "save_stack_function"
5602 [(match_operand 0 "general_operand" "")
5603 (match_operand 1 "general_operand" "")]
5604 ""
5605 "DONE;")
5606
5607 (define_expand "restore_stack_function"
5608 [(match_operand 0 "general_operand" "")
5609 (match_operand 1 "general_operand" "")]
5610 ""
5611 "DONE;")
5612
5613 (define_expand "restore_stack_block"
5614 [(use (match_operand 0 "register_operand" ""))
5615 (set (match_dup 2) (match_dup 3))
5616 (set (match_dup 0) (match_operand 1 "register_operand" ""))
5617 (set (match_dup 3) (match_dup 2))]
5618 ""
5619 "
5620 {
5621 operands[2] = gen_reg_rtx (Pmode);
5622 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
5623 }")
5624
5625 (define_expand "save_stack_nonlocal"
5626 [(match_operand 0 "memory_operand" "")
5627 (match_operand 1 "register_operand" "")]
5628 ""
5629 "
5630 {
5631 rtx temp = gen_reg_rtx (Pmode);
5632
5633 /* Copy the backchain to the first word, sp to the second. */
5634 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
5635 emit_move_insn (operand_subword (operands[0], 0, 0,
5636 TARGET_64BIT ? TImode : DImode),
5637 temp);
5638 emit_move_insn (operand_subword (operands[0], 1, 0,
5639 TARGET_64BIT ? TImode : DImode),
5640 operands[1]);
5641 DONE;
5642 }")
5643
5644 (define_expand "restore_stack_nonlocal"
5645 [(match_operand 0 "register_operand" "")
5646 (match_operand 1 "memory_operand" "")]
5647 ""
5648 "
5649 {
5650 rtx temp = gen_reg_rtx (Pmode);
5651
5652 /* Restore the backchain from the first word, sp from the second. */
5653 emit_move_insn (temp,
5654 operand_subword (operands[1], 0, 0,
5655 TARGET_64BIT ? TImode : DImode));
5656 emit_move_insn (operands[0],
5657 operand_subword (operands[1], 1, 0,
5658 TARGET_64BIT ? TImode : DImode));
5659 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
5660 DONE;
5661 }")
5662
5663
5664 ;
5665 ; nop instruction pattern(s).
5666 ;
5667
5668 (define_insn "nop"
5669 [(const_int 0)]
5670 ""
5671 "lr\\t0,0"
5672 [(set_attr "op_type" "RR")])
5673
5674
5675 ;
5676 ; Special literal pool access instruction pattern(s).
5677 ;
5678
5679 (define_insn "reload_base"
5680 [(parallel [(set (reg 13) (pc))
5681 (use (label_ref (match_operand 0 "" "")))])]
5682 ""
5683 "*
5684 {
5685 if (TARGET_64BIT)
5686 return \"larl\\t13,%y0\";
5687 else
5688 return \"basr\\t13,0\;ahi\\t13,%Y0\";
5689 }"
5690 [(set_attr "op_type" "NN")
5691 (set_attr "type" "o2")
5692 (set_attr "length" "8")])
5693
5694 (define_insn "ltorg"
5695 [(parallel [(set (reg 13) (pc))
5696 (use (match_operand:SI 0 "const_int_operand" ""))])]
5697 ""
5698 "*
5699 {
5700 s390_dump_literal_pool (insn, operands[0]);
5701 return \"0:\";
5702 }"
5703 [(set_attr "op_type" "NN")
5704 (set_attr "type" "branch")
5705 (set_attr "length" "4096")])
5706
5707
5708 ;;
5709 ;; Peephole optimization patterns.
5710 ;;
5711
5712 (define_peephole
5713 [(set (match_operand:SI 0 "memory_operand" "m")
5714 (match_operand:SI 1 "register_operand" "d"))
5715 (set (match_dup 1)
5716 (match_dup 0))]
5717 ""
5718 "st\\t%1,%0")
5719
5720 (define_peephole
5721 [(set (match_operand:SI 0 "memory_operand" "m")
5722 (match_operand:SI 1 "register_operand" "d"))
5723 (set (match_dup 0)
5724 (match_dup 1))]
5725 ""
5726 "st\\t%1,%0")
5727
5728 (define_peephole
5729 [(set (match_operand:SI 0 "register_operand" "")
5730 (match_operand:SI 1 "register_operand" ""))
5731 (parallel
5732 [(set (match_dup 0)
5733 (plus:SI (match_dup 0)
5734 (match_operand:SI 2 "immediate_operand" "")))
5735 (clobber (reg:CC 33))])]
5736 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
5737 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
5738 REGNO (operands[0]) == BASE_REGISTER ||
5739 REGNO (operands[1]) == BASE_REGISTER) &&
5740 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
5741 "la\\t%0,%c2(%1)")
5742
5743 ;
5744 ; peepholes for fast char instructions
5745 ;
5746
5747 ;(define_peephole
5748 ; [(set (match_operand:QI 0 "register_operand" "d")
5749 ; (match_operand:QI 1 "s_operand" "Q"))
5750 ; (set (match_operand:SI 2 "register_operand" "0")
5751 ; (zero_extend:SI (match_dup 0)))]
5752 ; "REGNO(operands[0]) == REGNO(operands[2])"
5753 ; "icm\\t%0,8,%1\;srl\\t%0,24")
5754
5755 ;(define_peephole
5756 ; [(set (match_operand:QI 0 "register_operand" "d")
5757 ; (match_operand:QI 1 "s_operand" "Q"))
5758 ; (set (match_operand:SI 2 "register_operand" "0")
5759 ; (sign_extend:SI (match_dup 0)))]
5760 ; "REGNO(operands[0]) == REGNO(operands[2])"
5761 ; "icm\\t%0,8,%1\;sra\\t%0,24")
5762
5763 (define_peephole
5764 [(set (match_operand:QI 0 "register_operand" "d")
5765 (match_operand:QI 1 "immediate_operand" "J"))
5766 (set (match_operand:SI 2 "register_operand" "0" )
5767 (sign_extend:SI (match_dup 0) ) )]
5768 "REGNO(operands[0]) == REGNO(operands[2])"
5769 "lhi\\t%0,%h1")
5770
5771 ;
5772 ; peepholes for fast short instructions
5773 ;
5774
5775 ;(define_peephole
5776 ; [(set (match_operand:HI 0 "register_operand" "d")
5777 ; (match_operand:HI 1 "s_operand" "Q"))
5778 ; (set (match_operand:SI 2 "register_operand" "0" )
5779 ; (zero_extend:SI (match_dup 0)))]
5780 ; "REGNO(operands[0]) == REGNO(operands[2])"
5781 ; "icm\\t%0,12,%1\;srl\\t%0,16")
5782
5783 (define_peephole
5784 [(set (match_operand:HI 0 "register_operand" "d")
5785 (match_operand:HI 1 "memory_operand" "m"))
5786 (set (match_operand:SI 2 "register_operand" "0" )
5787 (sign_extend:SI (match_dup 0)))]
5788 "REGNO(operands[0]) == REGNO(operands[2])"
5789 "lh\\t%0,%1")
5790
5791 (define_peephole
5792 [(set (match_operand:HI 0 "register_operand" "d")
5793 (match_operand:HI 1 "immediate_operand" "K"))
5794 (set (match_operand:SI 2 "register_operand" "0" )
5795 (sign_extend:SI (match_dup 0) ) )]
5796 "REGNO(operands[0]) == REGNO(operands[2])"
5797 "lhi\\t%0,%h1")
5798
5799 ;
5800 ; peepholes for divide instructions
5801 ;
5802
5803 (define_peephole
5804 [(set (match_operand:DI 0 "register_operand" "d")
5805 (match_operand:DI 1 "memory_operand" "m"))
5806 (set (match_dup 0)
5807 (lshiftrt:DI (match_dup 0)
5808 (match_operand:SI 2 "immediate_operand" "J")))
5809 (set (match_dup 0)
5810 (div:SI (match_dup 0)
5811 (match_operand:SI 3 "nonimmediate_operand" "g")))
5812 (set (match_dup 1)
5813 (match_dup 0))]
5814 ""
5815 "*
5816 {
5817 output_asm_insn (\"l\\t%0,%1\", operands);
5818 output_asm_insn (\"srdl\\t%0,%b2\", operands);
5819
5820 if (REG_P (operands[3]))
5821 output_asm_insn (\"dr\\t%0,%3\", operands);
5822 else
5823 output_asm_insn (\"d\\t%0,%3\", operands);
5824
5825 return \"st\\t%N0,%N1\";
5826 }")
5827
5828 (define_peephole
5829 [(set (match_operand:DI 0 "register_operand" "d")
5830 (match_operand:DI 1 "memory_operand" "m"))
5831 (set (match_dup 0)
5832 (lshiftrt:DI (match_dup 0)
5833 (match_operand:SI 2 "immediate_operand" "J")))
5834 (set (match_dup 0)
5835 (mod:SI (match_dup 0)
5836 (match_operand:SI 3 "nonimmediate_operand" "g")))
5837 (set (match_dup 1)
5838 (match_dup 0))]
5839 ""
5840 "*
5841 {
5842 output_asm_insn (\"l\\t%0,%1\", operands);
5843 output_asm_insn (\"srdl\\t%0,%b2\", operands);
5844
5845 if (REG_P (operands[3]))
5846 output_asm_insn (\"dr\\t%0,%3\", operands);
5847 else
5848 output_asm_insn (\"d\\t%0,%3\", operands);
5849
5850 return \"st\\t%0,%1\";
5851 }")
5852