gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999-2015 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com) and
   5 ;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify it under
  10 ;; the terms of the GNU General Public License as published by the Free
  11 ;; Software Foundation; either version 3, or (at your option) any later
  12 ;; version.
  13
  14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 ;; for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;;
  24 ;; See constraints.md for a description of constraints specific to s390.
  25 ;;
  26
  27 ;; Special formats used for outputting 390 instructions.
  28 ;;
  29 ;;     %C: print opcode suffix for branch condition.
  30 ;;     %D: print opcode suffix for inverse branch condition.
  31 ;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
  32 ;;     %G: print the size of the operand in bytes.
  33 ;;     %O: print only the displacement of a memory reference.
  34 ;;     %R: print only the base register of a memory reference.
  35 ;;     %S: print S-type memory reference (base+displacement).
  36 ;;     %N: print the second word of a DImode operand.
  37 ;;     %M: print the second word of a TImode operand.
  38 ;;     %Y: print shift count operand.
  39 ;;
  40 ;;     %b: print integer X as if it's an unsigned byte.
  41 ;;     %c: print integer X as if it's an signed byte.
  42 ;;     %x: print integer X as if it's an unsigned halfword.
  43 ;;     %h: print integer X as if it's a signed halfword.
  44 ;;     %i: print the first nonzero HImode part of X.
  45 ;;     %j: print the first HImode part unequal to -1 of X.
  46 ;;     %k: print the first nonzero SImode part of X.
  47 ;;     %m: print the first SImode part unequal to -1 of X.
  48 ;;     %o: print integer X as if it's an unsigned 32bit word.
  49 ;;
  50 ;; We have a special constraint for pattern matching.
  51 ;;
  52 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  53 ;;
  54
  55 ;;
  56 ;; UNSPEC usage
  57 ;;
  58
  59 (define_c_enum "unspec" [
  60    ; Miscellaneous
  61    UNSPEC_ROUND
  62    UNSPEC_ICM
  63    UNSPEC_TIE
  64
  65    ; Convert CC into a str comparison result and copy it into an
  66    ; integer register
  67    ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
  68    UNSPEC_STRCMPCC_TO_INT
  69
  70    ; Copy CC as is into the lower 2 bits of an integer register
  71    UNSPEC_CC_TO_INT
  72
  73    ; The right hand side of an setmem
  74    UNSPEC_REPLICATE_BYTE
  75
  76    ; GOT/PLT and lt-relative accesses
  77    UNSPEC_LTREL_OFFSET
  78    UNSPEC_LTREL_BASE
  79    UNSPEC_POOL_OFFSET
  80    UNSPEC_GOTENT
  81    UNSPEC_GOT
  82    UNSPEC_GOTOFF
  83    UNSPEC_PLT
  84    UNSPEC_PLTOFF
  85
  86    ; Literal pool
  87    UNSPEC_RELOAD_BASE
  88    UNSPEC_MAIN_BASE
  89    UNSPEC_LTREF
  90    UNSPEC_INSN
  91    UNSPEC_EXECUTE
  92
  93    ; Atomic Support
  94    UNSPEC_MB
  95    UNSPEC_MOVA
  96
  97    ; TLS relocation specifiers
  98    UNSPEC_TLSGD
  99    UNSPEC_TLSLDM
 100    UNSPEC_NTPOFF
 101    UNSPEC_DTPOFF
 102    UNSPEC_GOTNTPOFF
 103    UNSPEC_INDNTPOFF
 104
 105    ; TLS support
 106    UNSPEC_TLSLDM_NTPOFF
 107    UNSPEC_TLS_LOAD
 108
 109    ; String Functions
 110    UNSPEC_SRST
 111    UNSPEC_MVST
 112
 113    ; Stack Smashing Protector
 114    UNSPEC_SP_SET
 115    UNSPEC_SP_TEST
 116
 117    ; Test Data Class (TDC)
 118    UNSPEC_TDC_INSN
 119
 120    ; Population Count
 121    UNSPEC_POPCNT
 122    UNSPEC_COPYSIGN
 123
 124    ; Load FP Integer
 125    UNSPEC_FPINT_FLOOR
 126    UNSPEC_FPINT_BTRUNC
 127    UNSPEC_FPINT_ROUND
 128    UNSPEC_FPINT_CEIL
 129    UNSPEC_FPINT_NEARBYINT
 130    UNSPEC_FPINT_RINT
 131
 132    UNSPEC_LCBB
 133
 134    ; Vector
 135    UNSPEC_VEC_SMULT_HI
 136    UNSPEC_VEC_UMULT_HI
 137    UNSPEC_VEC_SMULT_LO
 138    UNSPEC_VEC_SMULT_EVEN
 139    UNSPEC_VEC_UMULT_EVEN
 140    UNSPEC_VEC_SMULT_ODD
 141    UNSPEC_VEC_UMULT_ODD
 142
 143    UNSPEC_VEC_VMAL
 144    UNSPEC_VEC_VMAH
 145    UNSPEC_VEC_VMALH
 146    UNSPEC_VEC_VMAE
 147    UNSPEC_VEC_VMALE
 148    UNSPEC_VEC_VMAO
 149    UNSPEC_VEC_VMALO
 150
 151    UNSPEC_VEC_GATHER
 152    UNSPEC_VEC_EXTRACT
 153    UNSPEC_VEC_INSERT_AND_ZERO
 154    UNSPEC_VEC_LOAD_BNDRY
 155    UNSPEC_VEC_LOAD_LEN
 156    UNSPEC_VEC_MERGEH
 157    UNSPEC_VEC_MERGEL
 158    UNSPEC_VEC_PACK
 159    UNSPEC_VEC_PACK_SATURATE
 160    UNSPEC_VEC_PACK_SATURATE_CC
 161    UNSPEC_VEC_PACK_SATURATE_GENCC
 162    UNSPEC_VEC_PACK_UNSIGNED_SATURATE
 163    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
 164    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
 165    UNSPEC_VEC_PERM
 166    UNSPEC_VEC_PERMI
 167    UNSPEC_VEC_EXTEND
 168    UNSPEC_VEC_STORE_LEN
 169    UNSPEC_VEC_UNPACKH
 170    UNSPEC_VEC_UNPACKH_L
 171    UNSPEC_VEC_UNPACKL
 172    UNSPEC_VEC_UNPACKL_L
 173    UNSPEC_VEC_ADDC
 174    UNSPEC_VEC_ADDC_U128
 175    UNSPEC_VEC_ADDE_U128
 176    UNSPEC_VEC_ADDEC_U128
 177    UNSPEC_VEC_AVG
 178    UNSPEC_VEC_AVGU
 179    UNSPEC_VEC_CHECKSUM
 180    UNSPEC_VEC_GFMSUM
 181    UNSPEC_VEC_GFMSUM_128
 182    UNSPEC_VEC_GFMSUM_ACCUM
 183    UNSPEC_VEC_GFMSUM_ACCUM_128
 184    UNSPEC_VEC_SET
 185
 186    UNSPEC_VEC_VSUMG
 187    UNSPEC_VEC_VSUMQ
 188    UNSPEC_VEC_VSUM
 189    UNSPEC_VEC_RL_MASK
 190    UNSPEC_VEC_SLL
 191    UNSPEC_VEC_SLB
 192    UNSPEC_VEC_SLDB
 193    UNSPEC_VEC_SRAL
 194    UNSPEC_VEC_SRAB
 195    UNSPEC_VEC_SRL
 196    UNSPEC_VEC_SRLB
 197
 198    UNSPEC_VEC_SUB_U128
 199    UNSPEC_VEC_SUBC
 200    UNSPEC_VEC_SUBC_U128
 201    UNSPEC_VEC_SUBE_U128
 202    UNSPEC_VEC_SUBEC_U128
 203
 204    UNSPEC_VEC_TEST_MASK
 205
 206    UNSPEC_VEC_VFAE
 207    UNSPEC_VEC_VFAECC
 208
 209    UNSPEC_VEC_VFEE
 210    UNSPEC_VEC_VFEECC
 211    UNSPEC_VEC_VFENE
 212    UNSPEC_VEC_VFENECC
 213
 214    UNSPEC_VEC_VISTR
 215    UNSPEC_VEC_VISTRCC
 216
 217    UNSPEC_VEC_VSTRC
 218    UNSPEC_VEC_VSTRCCC
 219
 220    UNSPEC_VEC_VCDGB
 221    UNSPEC_VEC_VCDLGB
 222
 223    UNSPEC_VEC_VCGDB
 224    UNSPEC_VEC_VCLGDB
 225
 226    UNSPEC_VEC_VFIDB
 227
 228    UNSPEC_VEC_VLDEB
 229    UNSPEC_VEC_VLEDB
 230
 231    UNSPEC_VEC_VFTCIDB
 232    UNSPEC_VEC_VFTCIDBCC
 233 ])
 234
 235 ;;
 236 ;; UNSPEC_VOLATILE usage
 237 ;;
 238
 239 (define_c_enum "unspecv" [
 240    ; Blockage
 241    UNSPECV_BLOCKAGE
 242
 243    ; TPF Support
 244    UNSPECV_TPF_PROLOGUE
 245    UNSPECV_TPF_EPILOGUE
 246
 247    ; Literal pool
 248    UNSPECV_POOL
 249    UNSPECV_POOL_SECTION
 250    UNSPECV_POOL_ALIGN
 251    UNSPECV_POOL_ENTRY
 252    UNSPECV_MAIN_POOL
 253
 254    ; TLS support
 255    UNSPECV_SET_TP
 256
 257    ; Atomic Support
 258    UNSPECV_CAS
 259    UNSPECV_ATOMIC_OP
 260
 261    ; Hotpatching (unremovable NOPs)
 262    UNSPECV_NOP_2_BYTE
 263    UNSPECV_NOP_4_BYTE
 264    UNSPECV_NOP_6_BYTE
 265
 266    ; Transactional Execution support
 267    UNSPECV_TBEGIN
 268    UNSPECV_TBEGIN_TDB
 269    UNSPECV_TBEGINC
 270    UNSPECV_TEND
 271    UNSPECV_TABORT
 272    UNSPECV_ETND
 273    UNSPECV_NTSTG
 274    UNSPECV_PPA
 275
 276    ; Set and get floating point control register
 277    UNSPECV_SFPC
 278    UNSPECV_EFPC
 279   ])
 280
 281 ;;
 282 ;; Registers
 283 ;;
 284
 285 ; Registers with special meaning
 286
 287 (define_constants
 288   [
 289    ; Sibling call register.
 290    (SIBCALL_REGNUM               1)
 291    ; Literal pool base register.
 292    (BASE_REGNUM                 13)
 293    ; Return address register.
 294    (RETURN_REGNUM               14)
 295    ; Condition code register.
 296    (CC_REGNUM                   33)
 297    ; Thread local storage pointer register.
 298    (TP_REGNUM                   36)
 299   ])
 300
 301 ; Hardware register names
 302
 303 (define_constants
 304   [
 305    ; General purpose registers
 306    (GPR0_REGNUM                  0)
 307    (GPR1_REGNUM                  1)
 308    ; Floating point registers.
 309    (FPR0_REGNUM                 16)
 310    (FPR1_REGNUM                 20)
 311    (FPR2_REGNUM                 17)
 312    (FPR3_REGNUM                 21)
 313    (FPR4_REGNUM                 18)
 314    (FPR5_REGNUM                 22)
 315    (FPR6_REGNUM                 19)
 316    (FPR7_REGNUM                 23)
 317    (FPR8_REGNUM                 24)
 318    (FPR9_REGNUM                 28)
 319    (FPR10_REGNUM                25)
 320    (FPR11_REGNUM                29)
 321    (FPR12_REGNUM                26)
 322    (FPR13_REGNUM                30)
 323    (FPR14_REGNUM                27)
 324    (FPR15_REGNUM                31)
 325    (VR0_REGNUM                  16)
 326    (VR16_REGNUM                 38)
 327    (VR23_REGNUM                 45)
 328    (VR24_REGNUM                 46)
 329    (VR31_REGNUM                 53)
 330   ])
 331
 332 ;;
 333 ;; PFPO GPR0 argument format
 334 ;;
 335
 336 (define_constants
 337   [
 338    ; PFPO operation type
 339    (PFPO_CONVERT          0x1000000)
 340    ; PFPO operand types
 341    (PFPO_OP_TYPE_SF             0x5)
 342    (PFPO_OP_TYPE_DF             0x6)
 343    (PFPO_OP_TYPE_TF             0x7)
 344    (PFPO_OP_TYPE_SD             0x8)
 345    (PFPO_OP_TYPE_DD             0x9)
 346    (PFPO_OP_TYPE_TD             0xa)
 347    ; Bitposition of operand types
 348    (PFPO_OP0_TYPE_SHIFT          16)
 349    (PFPO_OP1_TYPE_SHIFT           8)
 350   ])
 351
 352 ; Immediate operands for tbegin and tbeginc
 353 (define_constants [(TBEGIN_MASK  65292)]) ; 0xff0c
 354 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
 355
 356 ;; Instruction operand type as used in the Principles of Operation.
 357 ;; Used to determine defaults for length and other attribute values.
 358
 359 (define_attr "op_type"
 360   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
 361   (const_string "NN"))
 362
 363 ;; Instruction type attribute used for scheduling.
 364
 365 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 366                      cs,vs,store,sem,idiv,
 367                      imulhi,imulsi,imuldi,
 368                      branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 369                      floadtf,floaddf,floadsf,fstoredf,fstoresf,
 370                      fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 371                      ftoi,fsqrttf,fsqrtdf,fsqrtsf,
 372                      fmadddf,fmaddsf,
 373                      ftrunctf,ftruncdf, ftruncsd, ftruncdd,
 374                      itoftf, itofdf, itofsf, itofdd, itoftd,
 375                      fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
 376                      fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
 377                      ftoidfp, other"
 378   (cond [(eq_attr "op_type" "NN")  (const_string "other")
 379          (eq_attr "op_type" "SS")  (const_string "cs")]
 380     (const_string "integer")))
 381
 382 ;; Another attribute used for scheduling purposes:
 383 ;;   agen: Instruction uses the address generation unit
 384 ;;   reg: Instruction does not use the agen unit
 385
 386 (define_attr "atype" "agen,reg"
 387   (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
 388                 (const_string "reg")
 389                 (const_string "agen")))
 390
 391 ;; Properties concerning Z10 execution grouping and value forwarding.
 392 ;; z10_super: instruction is superscalar.
 393 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
 394 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
 395 ;;   target register.  It can forward this value to a second instruction that reads
 396 ;;   the same register if that second instruction is issued in the same group.
 397 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
 398 ;;   instruction in the S pipe writes to the register, then the T instruction
 399 ;;   can immediately read the new value.
 400 ;; z10_fr: union of Z10_fwd and z10_rec.
 401 ;; z10_c: second operand of instruction is a register and read with complemented bits.
 402 ;;
 403 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
 404
 405
 406 (define_attr "z10prop" "none,
 407                         z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
 408                         z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
 409                         z10_rec,
 410                         z10_fr, z10_fr_A3, z10_fr_E1,
 411                         z10_c"
 412              (const_string "none"))
 413
 414 ;; Properties concerning Z196 decoding
 415 ;; z196_alone: must group alone
 416 ;; z196_end: ends a group
 417 ;; z196_cracked: instruction is cracked or expanded
 418 (define_attr "z196prop" "none,
 419                          z196_alone, z196_ends,
 420                          z196_cracked"
 421              (const_string "none"))
 422
 423 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
 424
 425 ;; Length in bytes.
 426
 427 (define_attr "length" ""
 428   (cond [(eq_attr "op_type" "E,RR")                           (const_int 2)
 429          (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR")  (const_int 4)]
 430     (const_int 6)))
 431
 432
 433 ;; Processor type.  This attribute must exactly match the processor_type
 434 ;; enumeration in s390.h.  The current machine description does not
 435 ;; distinguish between g5 and g6, but there are differences between the two
 436 ;; CPUs could in theory be modeled.
 437
 438 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
 439   (const (symbol_ref "s390_tune_attr")))
 440
 441 (define_attr "cpu_facility"
 442   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
 443   (const_string "standard"))
 444
 445 (define_attr "enabled" ""
 446   (cond [(eq_attr "cpu_facility" "standard")
 447          (const_int 1)
 448
 449          (and (eq_attr "cpu_facility" "ieee")
 450               (match_test "TARGET_CPU_IEEE_FLOAT"))
 451          (const_int 1)
 452
 453          (and (eq_attr "cpu_facility" "zarch")
 454               (match_test "TARGET_ZARCH"))
 455          (const_int 1)
 456
 457          (and (eq_attr "cpu_facility" "longdisp")
 458               (match_test "TARGET_LONG_DISPLACEMENT"))
 459          (const_int 1)
 460
 461          (and (eq_attr "cpu_facility" "extimm")
 462               (match_test "TARGET_EXTIMM"))
 463          (const_int 1)
 464
 465          (and (eq_attr "cpu_facility" "dfp")
 466               (match_test "TARGET_DFP"))
 467          (const_int 1)
 468
 469          (and (eq_attr "cpu_facility" "cpu_zarch")
 470               (match_test "TARGET_CPU_ZARCH"))
 471          (const_int 1)
 472
 473          (and (eq_attr "cpu_facility" "z10")
 474               (match_test "TARGET_Z10"))
 475          (const_int 1)
 476
 477          (and (eq_attr "cpu_facility" "z196")
 478               (match_test "TARGET_Z196"))
 479          (const_int 1)
 480
 481          (and (eq_attr "cpu_facility" "zEC12")
 482               (match_test "TARGET_ZEC12"))
 483          (const_int 1)
 484
 485          (and (eq_attr "cpu_facility" "vec")
 486               (match_test "TARGET_VX"))
 487          (const_int 1)]
 488         (const_int 0)))
 489
 490 ;; Pipeline description for z900.  For lack of anything better,
 491 ;; this description is also used for the g5 and g6.
 492 (include "2064.md")
 493
 494 ;; Pipeline description for z990, z9-109 and z9-ec.
 495 (include "2084.md")
 496
 497 ;; Pipeline description for z10
 498 (include "2097.md")
 499
 500 ;; Pipeline description for z196
 501 (include "2817.md")
 502
 503 ;; Pipeline description for zEC12
 504 (include "2827.md")
 505
 506 ;; Predicates
 507 (include "predicates.md")
 508
 509 ;; Constraint definitions
 510 (include "constraints.md")
 511
 512 ;; Other includes
 513 (include "tpf.md")
 514
 515 ;; Iterators
 516
 517 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
 518
 519 ;; These mode iterators allow floating point patterns to be generated from the
 520 ;; same template.
 521 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
 522                               (SD "TARGET_HARD_DFP")])
 523 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
 524 (define_mode_iterator BFP [TF DF SF])
 525 (define_mode_iterator DFP [TD DD])
 526 (define_mode_iterator DFP_ALL [TD DD SD])
 527 (define_mode_iterator DSF [DF SF])
 528 (define_mode_iterator SD_SF [SF SD])
 529 (define_mode_iterator DD_DF [DF DD])
 530 (define_mode_iterator TD_TF [TF TD])
 531
 532 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 533 ;; from the same template.
 534 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
 535 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
 536 (define_mode_iterator DSI [DI SI])
 537 (define_mode_iterator TDI [TI DI])
 538
 539 ;; These mode iterators allow :P to be used for patterns that operate on
 540 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 541 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 542
 543 ;; These macros refer to the actual word_mode of the configuration.
 544 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
 545 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
 546 (define_mode_iterator W  [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
 547
 548 ;; Used by the umul pattern to express modes having half the size.
 549 (define_mode_attr DWH [(TI "DI") (DI "SI")])
 550 (define_mode_attr dwh [(TI "di") (DI "si")])
 551
 552 ;; This mode iterator allows the QI and HI patterns to be defined from
 553 ;; the same template.
 554 (define_mode_iterator HQI [HI QI])
 555
 556 ;; This mode iterator allows the integer patterns to be defined from the
 557 ;; same template.
 558 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
 559 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
 560
 561 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 562 ;; the same template.
 563 (define_code_iterator SHIFT [ashift lshiftrt])
 564
 565 ;; This iterator allows r[ox]sbg to be defined with the same template
 566 (define_code_iterator IXOR [ior xor])
 567
 568 ;; This iterator is used to expand the patterns for the nearest
 569 ;; integer functions.
 570 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
 571                             UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
 572                             UNSPEC_FPINT_NEARBYINT])
 573 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
 574                              (UNSPEC_FPINT_BTRUNC "btrunc")
 575                              (UNSPEC_FPINT_ROUND "round")
 576                              (UNSPEC_FPINT_CEIL "ceil")
 577                              (UNSPEC_FPINT_NEARBYINT "nearbyint")])
 578 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
 579                                      (UNSPEC_FPINT_BTRUNC "5")
 580                                      (UNSPEC_FPINT_ROUND "1")
 581                                      (UNSPEC_FPINT_CEIL "6")
 582                                      (UNSPEC_FPINT_NEARBYINT "0")])
 583
 584 ;; This iterator and attribute allow to combine most atomic operations.
 585 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 586 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
 587 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
 588                           (plus "add") (minus "sub") (mult "nand")])
 589 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
 590
 591 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
 592 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
 593 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
 594
 595 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
 596 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
 597 ;; SDmode.
 598 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
 599
 600 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 601 ;; Likewise for "<RXe>".
 602 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 603 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 604
 605 ;; The decimal floating point variants of add, sub, div and mul support 3
 606 ;; fp register operands.  The following attributes allow to merge the bfp and
 607 ;; dfp variants in a single insn definition.
 608
 609 ;; This attribute is used to set op_type accordingly.
 610 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
 611                         (DD "RRR") (SD "RRR")])
 612
 613 ;; This attribute is used in the operand constraint list in order to have the
 614 ;; first and the second operand match for bfp modes.
 615 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
 616
 617 ;; This attribute is used to merge the scalar vector instructions into
 618 ;; the FP patterns.  For non-supported modes (all but DF) it expands
 619 ;; to constraints which are supposed to be matched by an earlier
 620 ;; variant.
 621 (define_mode_attr v0      [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")])
 622 (define_mode_attr vf      [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")])
 623 (define_mode_attr vd      [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")])
 624
 625 ;; This attribute is used in the operand list of the instruction to have an
 626 ;; additional operand for the dfp instructions.
 627 (define_mode_attr op1 [(TF "") (DF "") (SF "")
 628                        (TD "%1,") (DD "%1,") (SD "%1,")])
 629
 630
 631 ;; This attribute is used in the operand constraint list
 632 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
 633 ;; TFmode values are represented by a fp register pair.  Since the
 634 ;; sign bit instructions only handle single source and target fp registers
 635 ;; these instructions can only be used for TFmode values if the source and
 636 ;; target operand uses the same fp register.
 637 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 638
 639 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
 640 ;; This is used to disable the memory alternative in TFmode patterns.
 641 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
 642
 643 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 644 ;; within instruction mnemonics.
 645 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 646
 647 ;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
 648 ;; modes and to an empty string for bfp modes.
 649 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 650
 651 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 652 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
 653 ;; version only operates on one register.
 654 (define_mode_attr d0 [(DI "d") (SI "0")])
 655
 656 ;; In combination with d0 this allows to combine instructions of which the 31bit
 657 ;; version only operates on one register. The DImode version needs an additional
 658 ;; register for the assembler output.
 659 (define_mode_attr 1 [(DI "%1,") (SI "")])
 660
 661 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 662 ;; 'ashift' and "srdl" in 'lshiftrt'.
 663 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 664
 665 ;; In SHIFT templates, this attribute holds the correct standard name for the
 666 ;; pattern itself and the corresponding function calls.
 667 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 668
 669 ;; This attribute handles differences in the instruction 'type' and will result
 670 ;; in "RRE" for DImode and "RR" for SImode.
 671 (define_mode_attr E [(DI "E") (SI "")])
 672
 673 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
 674 ;; to result in "RXY" for DImode and "RX" for SImode.
 675 (define_mode_attr Y [(DI "Y") (SI "")])
 676
 677 ;; This attribute handles differences in the instruction 'type' and will result
 678 ;; in "RSE" for TImode and "RS" for DImode.
 679 (define_mode_attr TE [(TI "E") (DI "")])
 680
 681 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
 682 ;; and "lcr" in SImode.
 683 (define_mode_attr g [(DI "g") (SI "")])
 684
 685 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
 686 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
 687 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
 688 ;; variant for long displacements.
 689 (define_mode_attr y [(DI "g") (SI "y")])
 690
 691 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
 692 ;; and "cds" in DImode.
 693 (define_mode_attr tg [(TI "g") (DI "")])
 694
 695 ;; In TDI templates, a string like "c<d>sg".
 696 (define_mode_attr td [(TI "d") (DI "")])
 697
 698 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
 699 ;; and "cfdbr" in SImode.
 700 (define_mode_attr gf [(DI "g") (SI "f")])
 701
 702 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
 703 ;; and sllk for SI.  This way it is possible to merge the new z196 SI
 704 ;; 3 operands shift instructions into the existing patterns.
 705 (define_mode_attr gk [(DI "g") (SI "k")])
 706
 707 ;; ICM mask required to load MODE value into the lowest subreg
 708 ;; of a SImode register.
 709 (define_mode_attr icm_lo [(HI "3") (QI "1")])
 710
 711 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
 712 ;; HImode and "llgc" in QImode.
 713 (define_mode_attr hc [(HI "h") (QI "c")])
 714
 715 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
 716 ;; in SImode.
 717 (define_mode_attr DBL [(DI "TI") (SI "DI")])
 718
 719 ;; This attribute expands to DF for TFmode and to DD for TDmode .  It is
 720 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
 721 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
 722
 723 ;; Maximum unsigned integer that fits in MODE.
 724 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 725
 726 ;; Start and end field computations for RISBG et al.
 727 (define_mode_attr bfstart [(DI "s") (SI "t")])
 728 (define_mode_attr bfend   [(DI "e") (SI "f")])
 729
 730 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 731 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
 732
 733 ;; In place of GET_MODE_SIZE (<MODE>mode)
 734 (define_mode_attr modesize [(DI "8") (SI "4")])
 735
 736 ;; Allow return and simple_return to be defined from a single template.
 737 (define_code_iterator ANY_RETURN [return simple_return])
 738
 739
 740
 741 ; Condition code modes generated by vector fp comparisons.  These will
 742 ; be used also in single element mode.
 743 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
 744 ; Used with VFCMP to expand part of the mnemonic
 745 ; For fp we have a mismatch: eq in the insn name - e in asm
 746 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 747 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
 748
 749
 750 (include "vector.md")
 751
 752 ;;
 753 ;;- Compare instructions.
 754 ;;
 755
 756 ; Test-under-Mask instructions
 757
 758 (define_insn "*tmqi_mem"
 759   [(set (reg CC_REGNUM)
 760         (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
 761                          (match_operand:QI 1 "immediate_operand" "n,n"))
 762                  (match_operand:QI 2 "immediate_operand" "n,n")))]
 763   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
 764   "@
 765    tm\t%S0,%b1
 766    tmy\t%S0,%b1"
 767   [(set_attr "op_type" "SI,SIY")
 768    (set_attr "z10prop" "z10_super,z10_super")])
 769
 770 (define_insn "*tmdi_reg"
 771   [(set (reg CC_REGNUM)
 772         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
 773                          (match_operand:DI 1 "immediate_operand"
 774                                              "N0HD0,N1HD0,N2HD0,N3HD0"))
 775                  (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
 776   "TARGET_ZARCH
 777    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 778    && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
 779   "@
 780    tmhh\t%0,%i1
 781    tmhl\t%0,%i1
 782    tmlh\t%0,%i1
 783    tmll\t%0,%i1"
 784   [(set_attr "op_type" "RI")
 785    (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 786
 787 (define_insn "*tmsi_reg"
 788   [(set (reg CC_REGNUM)
 789         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
 790                          (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
 791                  (match_operand:SI 2 "immediate_operand" "n,n")))]
 792   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 793    && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
 794   "@
 795    tmh\t%0,%i1
 796    tml\t%0,%i1"
 797   [(set_attr "op_type" "RI")
 798    (set_attr "z10prop" "z10_super,z10_super")])
 799
 800 (define_insn "*tm<mode>_full"
 801   [(set (reg CC_REGNUM)
 802         (compare (match_operand:HQI 0 "register_operand" "d")
 803                  (match_operand:HQI 1 "immediate_operand" "n")))]
 804   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
 805   "tml\t%0,<max_uint>"
 806   [(set_attr "op_type" "RI")
 807    (set_attr "z10prop" "z10_super")])
 808
 809
 810 ;
 811 ; Load-and-Test instructions
 812 ;
 813
 814 ; tst(di|si) instruction pattern(s).
 815
 816 (define_insn "*tstdi_sign"
 817   [(set (reg CC_REGNUM)
 818         (compare
 819           (ashiftrt:DI
 820             (ashift:DI
 821               (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
 822               (const_int 32)) (const_int 32))
 823           (match_operand:DI 1 "const0_operand" "")))
 824    (set (match_operand:DI 2 "register_operand" "=d,d")
 825         (sign_extend:DI (match_dup 0)))]
 826   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
 827   "ltgfr\t%2,%0
 828    ltgf\t%2,%0"
 829   [(set_attr "op_type"      "RRE,RXY")
 830    (set_attr "cpu_facility" "*,z10")
 831    (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 832
 833 ; ltr, lt, ltgr, ltg
 834 (define_insn "*tst<mode>_extimm"
 835   [(set (reg CC_REGNUM)
 836         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 837                  (match_operand:GPR 1 "const0_operand" "")))
 838    (set (match_operand:GPR 2 "register_operand" "=d,d")
 839         (match_dup 0))]
 840   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 841   "@
 842    lt<g>r\t%2,%0
 843    lt<g>\t%2,%0"
 844   [(set_attr "op_type" "RR<E>,RXY")
 845    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 846
 847 ; ltr, lt, ltgr, ltg
 848 (define_insn "*tst<mode>_cconly_extimm"
 849   [(set (reg CC_REGNUM)
 850         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 851                  (match_operand:GPR 1 "const0_operand" "")))
 852    (clobber (match_scratch:GPR 2 "=X,d"))]
 853   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 854   "@
 855    lt<g>r\t%0,%0
 856    lt<g>\t%2,%0"
 857   [(set_attr "op_type" "RR<E>,RXY")
 858    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 859
 860 (define_insn "*tstdi"
 861   [(set (reg CC_REGNUM)
 862         (compare (match_operand:DI 0 "register_operand" "d")
 863                  (match_operand:DI 1 "const0_operand" "")))
 864    (set (match_operand:DI 2 "register_operand" "=d")
 865         (match_dup 0))]
 866   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
 867   "ltgr\t%2,%0"
 868   [(set_attr "op_type" "RRE")
 869    (set_attr "z10prop" "z10_fr_E1")])
 870
 871 (define_insn "*tstsi"
 872   [(set (reg CC_REGNUM)
 873         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 874                  (match_operand:SI 1 "const0_operand" "")))
 875    (set (match_operand:SI 2 "register_operand" "=d,d,d")
 876         (match_dup 0))]
 877   "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
 878   "@
 879    ltr\t%2,%0
 880    icm\t%2,15,%S0
 881    icmy\t%2,15,%S0"
 882   [(set_attr "op_type" "RR,RS,RSY")
 883    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 884
 885 (define_insn "*tstsi_cconly"
 886   [(set (reg CC_REGNUM)
 887         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 888                  (match_operand:SI 1 "const0_operand" "")))
 889    (clobber (match_scratch:SI 2 "=X,d,d"))]
 890   "s390_match_ccmode(insn, CCSmode)"
 891   "@
 892    ltr\t%0,%0
 893    icm\t%2,15,%S0
 894    icmy\t%2,15,%S0"
 895   [(set_attr "op_type" "RR,RS,RSY")
 896    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 897
 898 (define_insn "*tstdi_cconly_31"
 899   [(set (reg CC_REGNUM)
 900         (compare (match_operand:DI 0 "register_operand" "d")
 901                  (match_operand:DI 1 "const0_operand" "")))]
 902   "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
 903   "srda\t%0,0"
 904   [(set_attr "op_type" "RS")
 905    (set_attr "atype"   "reg")])
 906
 907 ; ltr, ltgr
 908 (define_insn "*tst<mode>_cconly2"
 909   [(set (reg CC_REGNUM)
 910         (compare (match_operand:GPR 0 "register_operand" "d")
 911                  (match_operand:GPR 1 "const0_operand" "")))]
 912   "s390_match_ccmode(insn, CCSmode)"
 913   "lt<g>r\t%0,%0"
 914   [(set_attr "op_type" "RR<E>")
 915    (set_attr "z10prop" "z10_fr_E1")])
 916
 917 ; tst(hi|qi) instruction pattern(s).
 918
 919 (define_insn "*tst<mode>CCT"
 920   [(set (reg CC_REGNUM)
 921         (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
 922                  (match_operand:HQI 1 "const0_operand" "")))
 923    (set (match_operand:HQI 2 "register_operand" "=d,d,0")
 924         (match_dup 0))]
 925   "s390_match_ccmode(insn, CCTmode)"
 926   "@
 927    icm\t%2,<icm_lo>,%S0
 928    icmy\t%2,<icm_lo>,%S0
 929    tml\t%0,<max_uint>"
 930   [(set_attr "op_type" "RS,RSY,RI")
 931    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 932
 933 (define_insn "*tsthiCCT_cconly"
 934   [(set (reg CC_REGNUM)
 935         (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
 936                  (match_operand:HI 1 "const0_operand" "")))
 937    (clobber (match_scratch:HI 2 "=d,d,X"))]
 938   "s390_match_ccmode(insn, CCTmode)"
 939   "@
 940    icm\t%2,3,%S0
 941    icmy\t%2,3,%S0
 942    tml\t%0,65535"
 943   [(set_attr "op_type" "RS,RSY,RI")
 944    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 945
 946 (define_insn "*tstqiCCT_cconly"
 947   [(set (reg CC_REGNUM)
 948         (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
 949                  (match_operand:QI 1 "const0_operand" "")))]
 950   "s390_match_ccmode(insn, CCTmode)"
 951   "@
 952    cli\t%S0,0
 953    cliy\t%S0,0
 954    tml\t%0,255"
 955   [(set_attr "op_type" "SI,SIY,RI")
 956    (set_attr "z10prop" "z10_super,z10_super,z10_super")])
 957
 958 (define_insn "*tst<mode>"
 959   [(set (reg CC_REGNUM)
 960         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 961                  (match_operand:HQI 1 "const0_operand" "")))
 962    (set (match_operand:HQI 2 "register_operand" "=d,d")
 963         (match_dup 0))]
 964   "s390_match_ccmode(insn, CCSmode)"
 965   "@
 966    icm\t%2,<icm_lo>,%S0
 967    icmy\t%2,<icm_lo>,%S0"
 968   [(set_attr "op_type" "RS,RSY")
 969    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 970
 971 (define_insn "*tst<mode>_cconly"
 972   [(set (reg CC_REGNUM)
 973         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 974                  (match_operand:HQI 1 "const0_operand" "")))
 975    (clobber (match_scratch:HQI 2 "=d,d"))]
 976   "s390_match_ccmode(insn, CCSmode)"
 977   "@
 978    icm\t%2,<icm_lo>,%S0
 979    icmy\t%2,<icm_lo>,%S0"
 980   [(set_attr "op_type" "RS,RSY")
 981    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 982
 983
 984 ; Compare (equality) instructions
 985
 986 (define_insn "*cmpdi_cct"
 987   [(set (reg CC_REGNUM)
 988         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
 989                  (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
 990   "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
 991   "@
 992    cgr\t%0,%1
 993    cghi\t%0,%h1
 994    cgfi\t%0,%1
 995    cg\t%0,%1
 996    #"
 997   [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
 998    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
 999
1000 (define_insn "*cmpsi_cct"
1001   [(set (reg CC_REGNUM)
1002         (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1003                  (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1004   "s390_match_ccmode (insn, CCTmode)"
1005   "@
1006    cr\t%0,%1
1007    chi\t%0,%h1
1008    cfi\t%0,%1
1009    c\t%0,%1
1010    cy\t%0,%1
1011    #"
1012   [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1013    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1014
1015 ; Compare (signed) instructions
1016
1017 (define_insn "*cmpdi_ccs_sign"
1018   [(set (reg CC_REGNUM)
1019         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1020                                                      "d,RT,b"))
1021                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1022   "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1023   "@
1024    cgfr\t%0,%1
1025    cgf\t%0,%1
1026    cgfrl\t%0,%1"
1027   [(set_attr "op_type"      "RRE,RXY,RIL")
1028    (set_attr "z10prop" "z10_c,*,*")
1029    (set_attr "type"         "*,*,larl")])
1030
1031
1032
1033 (define_insn "*cmpsi_ccs_sign"
1034   [(set (reg CC_REGNUM)
1035         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1036                  (match_operand:SI 0 "register_operand" "d,d,d")))]
1037   "s390_match_ccmode(insn, CCSRmode)"
1038   "@
1039    ch\t%0,%1
1040    chy\t%0,%1
1041    chrl\t%0,%1"
1042   [(set_attr "op_type"      "RX,RXY,RIL")
1043    (set_attr "cpu_facility" "*,*,z10")
1044    (set_attr "type"         "*,*,larl")
1045    (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1046
1047 (define_insn "*cmphi_ccs_z10"
1048   [(set (reg CC_REGNUM)
1049         (compare (match_operand:HI 0 "s_operand"         "Q")
1050                  (match_operand:HI 1 "immediate_operand" "K")))]
1051   "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1052   "chhsi\t%0,%1"
1053   [(set_attr "op_type" "SIL")
1054    (set_attr "z196prop" "z196_cracked")])
1055
1056 (define_insn "*cmpdi_ccs_signhi_rl"
1057   [(set (reg CC_REGNUM)
1058         (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
1059                  (match_operand:GPR 0 "register_operand"  "d,d")))]
1060   "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1061   "@
1062    cgh\t%0,%1
1063    cghrl\t%0,%1"
1064   [(set_attr "op_type" "RXY,RIL")
1065    (set_attr "type"    "*,larl")])
1066
1067 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1068 (define_insn "*cmp<mode>_ccs"
1069   [(set (reg CC_REGNUM)
1070         (compare (match_operand:GPR 0 "nonimmediate_operand"
1071                                       "d,d,Q, d,d,d,d")
1072                  (match_operand:GPR 1 "general_operand"
1073                                       "d,K,K,Os,R,T,b")))]
1074   "s390_match_ccmode(insn, CCSmode)"
1075   "@
1076    c<g>r\t%0,%1
1077    c<g>hi\t%0,%h1
1078    c<g>hsi\t%0,%h1
1079    c<g>fi\t%0,%1
1080    c<g>\t%0,%1
1081    c<y>\t%0,%1
1082    c<g>rl\t%0,%1"
1083   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1084    (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
1085    (set_attr "type" "*,*,*,*,*,*,larl")
1086    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1087
1088
1089 ; Compare (unsigned) instructions
1090
1091 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1092   [(set (reg CC_REGNUM)
1093         (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1094                                           "larl_operand" "X")))
1095                  (match_operand:SI 0 "register_operand" "d")))]
1096   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1097   "clhrl\t%0,%1"
1098   [(set_attr "op_type" "RIL")
1099    (set_attr "type"    "larl")
1100    (set_attr "z10prop" "z10_super")])
1101
1102 ; clhrl, clghrl
1103 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1104   [(set (reg CC_REGNUM)
1105         (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1106                                           "larl_operand" "X")))
1107                  (match_operand:GPR 0 "register_operand" "d")))]
1108   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1109   "cl<g>hrl\t%0,%1"
1110   [(set_attr "op_type" "RIL")
1111    (set_attr "type"    "larl")
1112    (set_attr "z10prop" "z10_super")])
1113
1114 (define_insn "*cmpdi_ccu_zero"
1115   [(set (reg CC_REGNUM)
1116         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1117                                                         "d,RT,b"))
1118                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1119   "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1120   "@
1121    clgfr\t%0,%1
1122    clgf\t%0,%1
1123    clgfrl\t%0,%1"
1124   [(set_attr "op_type"      "RRE,RXY,RIL")
1125    (set_attr "cpu_facility" "*,*,z10")
1126    (set_attr "type"         "*,*,larl")
1127    (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1128
1129 (define_insn "*cmpdi_ccu"
1130   [(set (reg CC_REGNUM)
1131         (compare (match_operand:DI 0 "nonimmediate_operand"
1132                                      "d, d,d,Q, d, Q,BQ")
1133                  (match_operand:DI 1 "general_operand"
1134                                      "d,Op,b,D,RT,BQ,Q")))]
1135   "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1136   "@
1137    clgr\t%0,%1
1138    clgfi\t%0,%1
1139    clgrl\t%0,%1
1140    clghsi\t%0,%x1
1141    clg\t%0,%1
1142    #
1143    #"
1144   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1145    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1146    (set_attr "type"         "*,*,larl,*,*,*,*")
1147    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1148
1149 (define_insn "*cmpsi_ccu"
1150   [(set (reg CC_REGNUM)
1151         (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1152                  (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
1153   "s390_match_ccmode (insn, CCUmode)"
1154   "@
1155    clr\t%0,%1
1156    clfi\t%0,%o1
1157    clrl\t%0,%1
1158    clfhsi\t%0,%x1
1159    cl\t%0,%1
1160    cly\t%0,%1
1161    #
1162    #"
1163   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1164    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1165    (set_attr "type"         "*,*,larl,*,*,*,*,*")
1166    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1167
1168 (define_insn "*cmphi_ccu"
1169   [(set (reg CC_REGNUM)
1170         (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1171                  (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
1172   "s390_match_ccmode (insn, CCUmode)
1173    && !register_operand (operands[1], HImode)"
1174   "@
1175    clm\t%0,3,%S1
1176    clmy\t%0,3,%S1
1177    clhhsi\t%0,%1
1178    #
1179    #"
1180   [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1181    (set_attr "cpu_facility" "*,*,z10,*,*")
1182    (set_attr "z10prop" "*,*,z10_super,*,*")])
1183
1184 (define_insn "*cmpqi_ccu"
1185   [(set (reg CC_REGNUM)
1186         (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1187                  (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1188   "s390_match_ccmode (insn, CCUmode)
1189    && !register_operand (operands[1], QImode)"
1190   "@
1191    clm\t%0,1,%S1
1192    clmy\t%0,1,%S1
1193    cli\t%S0,%b1
1194    cliy\t%S0,%b1
1195    #
1196    #"
1197   [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1198    (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1199
1200
1201 ; Block compare (CLC) instruction patterns.
1202
1203 (define_insn "*clc"
1204   [(set (reg CC_REGNUM)
1205         (compare (match_operand:BLK 0 "memory_operand" "Q")
1206                  (match_operand:BLK 1 "memory_operand" "Q")))
1207    (use (match_operand 2 "const_int_operand" "n"))]
1208   "s390_match_ccmode (insn, CCUmode)
1209    && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1210   "clc\t%O0(%2,%R0),%S1"
1211   [(set_attr "op_type" "SS")])
1212
1213 (define_split
1214   [(set (reg CC_REGNUM)
1215         (compare (match_operand 0 "memory_operand" "")
1216                  (match_operand 1 "memory_operand" "")))]
1217   "reload_completed
1218    && s390_match_ccmode (insn, CCUmode)
1219    && GET_MODE (operands[0]) == GET_MODE (operands[1])
1220    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1221   [(parallel
1222     [(set (match_dup 0) (match_dup 1))
1223      (use (match_dup 2))])]
1224 {
1225   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1226   operands[0] = adjust_address (operands[0], BLKmode, 0);
1227   operands[1] = adjust_address (operands[1], BLKmode, 0);
1228
1229   operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1230                                  operands[0], operands[1]);
1231   operands[0] = SET_DEST (PATTERN (curr_insn));
1232 })
1233
1234
1235 ; (TF|DF|SF|TD|DD|SD) instructions
1236
1237 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1238 (define_insn "*cmp<mode>_ccs_0"
1239   [(set (reg CC_REGNUM)
1240         (compare (match_operand:FP 0 "register_operand" "f")
1241                  (match_operand:FP 1 "const0_operand"   "")))]
1242   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1243   "lt<xde><bt>r\t%0,%0"
1244    [(set_attr "op_type" "RRE")
1245     (set_attr "type"  "fsimp<mode>")])
1246
1247 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1248 (define_insn "*cmp<mode>_ccs"
1249   [(set (reg CC_REGNUM)
1250         (compare (match_operand:FP 0 "register_operand" "f,f")
1251                  (match_operand:FP 1 "general_operand"  "f,<Rf>")))]
1252   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1253   "@
1254    c<xde><bt>r\t%0,%1
1255    c<xde>b\t%0,%1"
1256    [(set_attr "op_type" "RRE,RXE")
1257     (set_attr "type"  "fsimp<mode>")])
1258
1259 ; wfcedbs, wfchdbs, wfchedbs
1260 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1261   [(set (reg:VFCMP CC_REGNUM)
1262         (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1263                        (match_operand:DF 1 "register_operand" "v")))
1264    (clobber (match_scratch:V2DI 2 "=v"))]
1265   "TARGET_Z13 && TARGET_HARD_FLOAT"
1266   "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1267   [(set_attr "op_type" "VRR")])
1268
1269 ; Compare and Branch instructions
1270
1271 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1272 ; The following instructions do a complementary access of their second
1273 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1274 (define_insn "*cmp_and_br_signed_<mode>"
1275   [(set (pc)
1276         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1277                         [(match_operand:GPR 1 "register_operand"  "d,d")
1278                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1279                       (label_ref (match_operand 3 "" ""))
1280                       (pc)))
1281    (clobber (reg:CC CC_REGNUM))]
1282   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1283 {
1284   if (get_attr_length (insn) == 6)
1285     return which_alternative ?
1286       "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1287   else
1288     return which_alternative ?
1289       "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1290 }
1291   [(set_attr "op_type" "RIE")
1292    (set_attr "type"    "branch")
1293    (set_attr "z10prop" "z10_super_c,z10_super")
1294    (set (attr "length")
1295         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1296                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1297                                                        ; 10 byte for cgr/jg
1298
1299 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1300 ; The following instructions do a complementary access of their second
1301 ; operand (z10 only): clrj, clgrj, clr, clgr
1302 (define_insn "*cmp_and_br_unsigned_<mode>"
1303   [(set (pc)
1304         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1305                         [(match_operand:GPR 1 "register_operand"  "d,d")
1306                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1307                       (label_ref (match_operand 3 "" ""))
1308                       (pc)))
1309    (clobber (reg:CC CC_REGNUM))]
1310   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1311 {
1312   if (get_attr_length (insn) == 6)
1313     return which_alternative ?
1314       "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1315   else
1316     return which_alternative ?
1317       "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1318 }
1319   [(set_attr "op_type" "RIE")
1320    (set_attr "type"    "branch")
1321    (set_attr "z10prop" "z10_super_c,z10_super")
1322    (set (attr "length")
1323         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1324                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1325                                                        ; 10 byte for clgr/jg
1326
1327 ; And now the same two patterns as above but with a negated CC mask.
1328
1329 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1330 ; The following instructions do a complementary access of their second
1331 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1332 (define_insn "*icmp_and_br_signed_<mode>"
1333   [(set (pc)
1334         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1335                         [(match_operand:GPR 1 "register_operand"  "d,d")
1336                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1337                       (pc)
1338                       (label_ref (match_operand 3 "" ""))))
1339    (clobber (reg:CC CC_REGNUM))]
1340   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1341 {
1342   if (get_attr_length (insn) == 6)
1343     return which_alternative ?
1344       "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1345   else
1346     return which_alternative ?
1347       "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1348 }
1349   [(set_attr "op_type" "RIE")
1350    (set_attr "type"    "branch")
1351    (set_attr "z10prop" "z10_super_c,z10_super")
1352    (set (attr "length")
1353         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1354                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1355                                                        ; 10 byte for cgr/jg
1356
1357 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1358 ; The following instructions do a complementary access of their second
1359 ; operand (z10 only): clrj, clgrj, clr, clgr
1360 (define_insn "*icmp_and_br_unsigned_<mode>"
1361   [(set (pc)
1362         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1363                         [(match_operand:GPR 1 "register_operand"  "d,d")
1364                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1365                       (pc)
1366                       (label_ref (match_operand 3 "" ""))))
1367    (clobber (reg:CC CC_REGNUM))]
1368   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1369 {
1370   if (get_attr_length (insn) == 6)
1371     return which_alternative ?
1372       "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1373   else
1374     return which_alternative ?
1375       "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1376 }
1377   [(set_attr "op_type" "RIE")
1378    (set_attr "type"    "branch")
1379    (set_attr "z10prop" "z10_super_c,z10_super")
1380    (set (attr "length")
1381         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1382                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1383                                                        ; 10 byte for clgr/jg
1384
1385 ;;
1386 ;;- Move instructions.
1387 ;;
1388
1389 ;
1390 ; movti instruction pattern(s).
1391 ;
1392
1393 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1394 ; for TImode (use double-int for the calculations)
1395 (define_insn "movti"
1396   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v,  v,  v,v,d, v,QR,   d,o")
1397         (match_operand:TI 1 "general_operand"      "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1398   "TARGET_ZARCH"
1399   "@
1400    lmg\t%0,%N0,%S1
1401    stmg\t%1,%N1,%S0
1402    vlr\t%v0,%v1
1403    vzero\t%v0
1404    vone\t%v0
1405    vlvgp\t%v0,%1,%N1
1406    #
1407    vl\t%v0,%1
1408    vst\t%v1,%0
1409    #
1410    #"
1411   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1412    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1413    (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1414
1415 (define_split
1416   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1417         (match_operand:TI 1 "general_operand" ""))]
1418   "TARGET_ZARCH && reload_completed
1419    && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1420   [(set (match_dup 2) (match_dup 4))
1421    (set (match_dup 3) (match_dup 5))]
1422 {
1423   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1424   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1425   operands[4] = operand_subword (operands[1], 0, 0, TImode);
1426   operands[5] = operand_subword (operands[1], 1, 0, TImode);
1427 })
1428
1429 (define_split
1430   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1431         (match_operand:TI 1 "general_operand" ""))]
1432   "TARGET_ZARCH && reload_completed
1433    && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1434   [(set (match_dup 2) (match_dup 4))
1435    (set (match_dup 3) (match_dup 5))]
1436 {
1437   operands[2] = operand_subword (operands[0], 1, 0, TImode);
1438   operands[3] = operand_subword (operands[0], 0, 0, TImode);
1439   operands[4] = operand_subword (operands[1], 1, 0, TImode);
1440   operands[5] = operand_subword (operands[1], 0, 0, TImode);
1441 })
1442
1443 ; Use part of the TImode target reg to perform the address
1444 ; calculation.  If the TImode value is supposed to be copied into a VR
1445 ; this splitter is not necessary.
1446 (define_split
1447   [(set (match_operand:TI 0 "register_operand" "")
1448         (match_operand:TI 1 "memory_operand" ""))]
1449   "TARGET_ZARCH && reload_completed
1450    && !VECTOR_REG_P (operands[0])
1451    && !s_operand (operands[1], VOIDmode)"
1452   [(set (match_dup 0) (match_dup 1))]
1453 {
1454   rtx addr = operand_subword (operands[0], 1, 0, TImode);
1455   addr = gen_lowpart (Pmode, addr);
1456   s390_load_address (addr, XEXP (operands[1], 0));
1457   operands[1] = replace_equiv_address (operands[1], addr);
1458 })
1459
1460
1461 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1462 ; For the higher order bits we do simply a DImode move while the
1463 ; second part is done via vec extract.  Both will end up as vlgvg.
1464 (define_split
1465   [(set (match_operand:TI 0 "register_operand" "")
1466         (match_operand:TI 1 "register_operand" ""))]
1467   "TARGET_VX && reload_completed
1468    && GENERAL_REG_P (operands[0])
1469    && VECTOR_REG_P (operands[1])"
1470   [(set (match_dup 2) (match_dup 4))
1471    (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1472                                  UNSPEC_VEC_EXTRACT))]
1473 {
1474   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1475   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1476   operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1477   operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1478 })
1479
1480 ;
1481 ; Patterns used for secondary reloads
1482 ;
1483
1484 ; z10 provides move instructions accepting larl memory operands.
1485 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1486 ; These patterns are also used for unaligned SI and DI accesses.
1487
1488 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1489   [(parallel [(match_operand:ALL 0 "memory_operand"   "")
1490               (match_operand:ALL 1 "register_operand" "=d")
1491               (match_operand:P   2 "register_operand" "=&a")])]
1492   "TARGET_Z10"
1493 {
1494   s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1495   DONE;
1496 })
1497
1498 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1499   [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1500               (match_operand:ALL 1 "memory_operand"   "")
1501               (match_operand:P   2 "register_operand" "=a")])]
1502   "TARGET_Z10"
1503 {
1504   s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1505   DONE;
1506 })
1507
1508 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1509   [(parallel [(match_operand:P 0 "register_operand" "=d")
1510               (match_operand:P 1 "larl_operand"     "")
1511               (match_operand:P 2 "register_operand" "=a")])]
1512   "TARGET_Z10"
1513 {
1514   s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1515   DONE;
1516 })
1517
1518 ; Handles loading a PLUS (load address) expression
1519
1520 (define_expand "reload<mode>_plus"
1521   [(parallel [(match_operand:P 0 "register_operand"  "=a")
1522               (match_operand:P 1 "s390_plus_operand" "")
1523               (match_operand:P 2 "register_operand"  "=&a")])]
1524   ""
1525 {
1526   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1527   DONE;
1528 })
1529
1530 ; Not all the indirect memory access instructions support the full
1531 ; format (long disp + index + base).  So whenever a move from/to such
1532 ; an address is required and the instruction cannot deal with it we do
1533 ; a load address into a scratch register first and use this as the new
1534 ; base register.
1535 ; This in particular is used for:
1536 ; - non-offsetable memory accesses for multiword moves
1537 ; - full vector reg moves with long displacements
1538
1539 (define_expand "reload<mode>_la_in"
1540   [(parallel [(match_operand 0   "register_operand" "")
1541               (match_operand 1   "" "")
1542               (match_operand:P 2 "register_operand" "=&a")])]
1543   ""
1544 {
1545   gcc_assert (MEM_P (operands[1]));
1546   s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1547   operands[1] = replace_equiv_address (operands[1], operands[2]);
1548   emit_move_insn (operands[0], operands[1]);
1549   DONE;
1550 })
1551
1552 (define_expand "reload<mode>_la_out"
1553   [(parallel [(match_operand   0 "" "")
1554               (match_operand   1 "register_operand" "")
1555               (match_operand:P 2 "register_operand" "=&a")])]
1556   ""
1557 {
1558   gcc_assert (MEM_P (operands[0]));
1559   s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1560   operands[0] = replace_equiv_address (operands[0], operands[2]);
1561   emit_move_insn (operands[0], operands[1]);
1562   DONE;
1563 })
1564
1565 (define_expand "reload<mode>_PIC_addr"
1566   [(parallel [(match_operand   0 "register_operand" "=d")
1567               (match_operand   1 "larl_operand"     "")
1568               (match_operand:P 2 "register_operand" "=a")])]
1569   ""
1570 {
1571   rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1572   emit_move_insn (operands[0], new_rtx);
1573 })
1574
1575 ;
1576 ; movdi instruction pattern(s).
1577 ;
1578
1579 (define_expand "movdi"
1580   [(set (match_operand:DI 0 "general_operand" "")
1581         (match_operand:DI 1 "general_operand" ""))]
1582   ""
1583 {
1584   /* Handle symbolic constants.  */
1585   if (TARGET_64BIT
1586       && (SYMBOLIC_CONST (operands[1])
1587           || (GET_CODE (operands[1]) == PLUS
1588               && XEXP (operands[1], 0) == pic_offset_table_rtx
1589               && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1590     emit_symbolic_move (operands);
1591 })
1592
1593 (define_insn "*movdi_larl"
1594   [(set (match_operand:DI 0 "register_operand" "=d")
1595         (match_operand:DI 1 "larl_operand" "X"))]
1596   "TARGET_64BIT
1597    && !FP_REG_P (operands[0])"
1598   "larl\t%0,%1"
1599    [(set_attr "op_type" "RIL")
1600     (set_attr "type"    "larl")
1601     (set_attr "z10prop" "z10_super_A1")])
1602
1603 (define_insn "*movdi_64"
1604   [(set (match_operand:DI 0 "nonimmediate_operand"
1605          "=d,    d,    d,    d,    d, d,    d,    d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1606         (match_operand:DI 1 "general_operand"
1607          " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f,  R,  T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1608   "TARGET_ZARCH"
1609   "@
1610    lghi\t%0,%h1
1611    llihh\t%0,%i1
1612    llihl\t%0,%i1
1613    llilh\t%0,%i1
1614    llill\t%0,%i1
1615    lgfi\t%0,%1
1616    llihf\t%0,%k1
1617    llilf\t%0,%k1
1618    ldgr\t%0,%1
1619    lgdr\t%0,%1
1620    lay\t%0,%a1
1621    lgrl\t%0,%1
1622    lgr\t%0,%1
1623    lg\t%0,%1
1624    stg\t%1,%0
1625    ldr\t%0,%1
1626    ld\t%0,%1
1627    ldy\t%0,%1
1628    std\t%1,%0
1629    stdy\t%1,%0
1630    stgrl\t%1,%0
1631    mvghi\t%0,%1
1632    #
1633    #
1634    stam\t%1,%N1,%S0
1635    lam\t%0,%N0,%S1
1636    vleig\t%v0,%h1,0
1637    vlr\t%v0,%v1
1638    vlvgg\t%v0,%1,0
1639    vlgvg\t%0,%v1,0
1640    vleg\t%v0,%1,0
1641    vsteg\t%v1,%0,0"
1642   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1643                         RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1644    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1645                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1646                      *,*,*,*,*,*,*")
1647    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1648                              z10,*,*,*,*,*,longdisp,*,longdisp,
1649                              z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1650    (set_attr "z10prop" "z10_fwd_A1,
1651                         z10_fwd_E1,
1652                         z10_fwd_E1,
1653                         z10_fwd_E1,
1654                         z10_fwd_E1,
1655                         z10_fwd_A1,
1656                         z10_fwd_E1,
1657                         z10_fwd_E1,
1658                         *,
1659                         *,
1660                         z10_fwd_A1,
1661                         z10_fwd_A3,
1662                         z10_fr_E1,
1663                         z10_fwd_A3,
1664                         z10_rec,
1665                         *,
1666                         *,
1667                         *,
1668                         *,
1669                         *,
1670                         z10_rec,
1671                         z10_super,
1672                         *,
1673                         *,
1674                         *,
1675                         *,*,*,*,*,*,*")
1676 ])
1677
1678 (define_split
1679   [(set (match_operand:DI 0 "register_operand" "")
1680         (match_operand:DI 1 "register_operand" ""))]
1681   "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1682   [(set (match_dup 2) (match_dup 3))
1683    (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1684    (set (strict_low_part (match_dup 2)) (match_dup 4))]
1685   "operands[2] = gen_lowpart (SImode, operands[0]);
1686    s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1687
1688 (define_split
1689   [(set (match_operand:DI 0 "register_operand" "")
1690         (match_operand:DI 1 "register_operand" ""))]
1691   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1692    && dead_or_set_p (insn, operands[1])"
1693   [(set (match_dup 3) (match_dup 2))
1694    (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1695    (set (match_dup 4) (match_dup 2))]
1696   "operands[2] = gen_lowpart (SImode, operands[1]);
1697    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1698
1699 (define_split
1700   [(set (match_operand:DI 0 "register_operand" "")
1701         (match_operand:DI 1 "register_operand" ""))]
1702   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1703    && !dead_or_set_p (insn, operands[1])"
1704   [(set (match_dup 3) (match_dup 2))
1705    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1706    (set (match_dup 4) (match_dup 2))
1707    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1708   "operands[2] = gen_lowpart (SImode, operands[1]);
1709    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1710
1711 (define_insn "*movdi_31"
1712   [(set (match_operand:DI 0 "nonimmediate_operand"
1713                             "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,d")
1714         (match_operand:DI 1 "general_operand"
1715                             " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,b"))]
1716   "!TARGET_ZARCH"
1717   "@
1718    lm\t%0,%N0,%S1
1719    lmy\t%0,%N0,%S1
1720    stm\t%1,%N1,%S0
1721    stmy\t%1,%N1,%S0
1722    #
1723    #
1724    ldr\t%0,%1
1725    ld\t%0,%1
1726    ldy\t%0,%1
1727    std\t%1,%0
1728    stdy\t%1,%0
1729    #"
1730   [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1731    (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1732    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1733
1734 ; For a load from a symbol ref we can use one of the target registers
1735 ; together with larl to load the address.
1736 (define_split
1737   [(set (match_operand:DI 0 "register_operand" "")
1738         (match_operand:DI 1 "memory_operand" ""))]
1739   "!TARGET_ZARCH && reload_completed && TARGET_Z10
1740    && larl_operand (XEXP (operands[1], 0), SImode)"
1741   [(set (match_dup 2) (match_dup 3))
1742    (set (match_dup 0) (match_dup 1))]
1743 {
1744   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1745   operands[3] = XEXP (operands[1], 0);
1746   operands[1] = replace_equiv_address (operands[1], operands[2]);
1747 })
1748
1749 (define_split
1750   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1751         (match_operand:DI 1 "general_operand" ""))]
1752   "!TARGET_ZARCH && reload_completed
1753    && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1754   [(set (match_dup 2) (match_dup 4))
1755    (set (match_dup 3) (match_dup 5))]
1756 {
1757   operands[2] = operand_subword (operands[0], 0, 0, DImode);
1758   operands[3] = operand_subword (operands[0], 1, 0, DImode);
1759   operands[4] = operand_subword (operands[1], 0, 0, DImode);
1760   operands[5] = operand_subword (operands[1], 1, 0, DImode);
1761 })
1762
1763 (define_split
1764   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1765         (match_operand:DI 1 "general_operand" ""))]
1766   "!TARGET_ZARCH && reload_completed
1767    && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1768   [(set (match_dup 2) (match_dup 4))
1769    (set (match_dup 3) (match_dup 5))]
1770 {
1771   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1772   operands[3] = operand_subword (operands[0], 0, 0, DImode);
1773   operands[4] = operand_subword (operands[1], 1, 0, DImode);
1774   operands[5] = operand_subword (operands[1], 0, 0, DImode);
1775 })
1776
1777 (define_split
1778   [(set (match_operand:DI 0 "register_operand" "")
1779         (match_operand:DI 1 "memory_operand" ""))]
1780   "!TARGET_ZARCH && reload_completed
1781    && !FP_REG_P (operands[0])
1782    && !s_operand (operands[1], VOIDmode)"
1783   [(set (match_dup 0) (match_dup 1))]
1784 {
1785   rtx addr = operand_subword (operands[0], 1, 0, DImode);
1786   s390_load_address (addr, XEXP (operands[1], 0));
1787   operands[1] = replace_equiv_address (operands[1], addr);
1788 })
1789
1790 (define_peephole2
1791   [(set (match_operand:DI 0 "register_operand" "")
1792         (mem:DI (match_operand 1 "address_operand" "")))]
1793   "TARGET_ZARCH
1794    && !FP_REG_P (operands[0])
1795    && GET_CODE (operands[1]) == SYMBOL_REF
1796    && CONSTANT_POOL_ADDRESS_P (operands[1])
1797    && get_pool_mode (operands[1]) == DImode
1798    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1799   [(set (match_dup 0) (match_dup 2))]
1800   "operands[2] = get_pool_constant (operands[1]);")
1801
1802 (define_insn "*la_64"
1803   [(set (match_operand:DI 0 "register_operand" "=d,d")
1804         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1805   "TARGET_64BIT"
1806   "@
1807    la\t%0,%a1
1808    lay\t%0,%a1"
1809   [(set_attr "op_type" "RX,RXY")
1810    (set_attr "type"    "la")
1811    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1812
1813 (define_peephole2
1814   [(parallel
1815     [(set (match_operand:DI 0 "register_operand" "")
1816           (match_operand:QI 1 "address_operand" ""))
1817      (clobber (reg:CC CC_REGNUM))])]
1818   "TARGET_64BIT
1819    && preferred_la_operand_p (operands[1], const0_rtx)"
1820   [(set (match_dup 0) (match_dup 1))]
1821   "")
1822
1823 (define_peephole2
1824   [(set (match_operand:DI 0 "register_operand" "")
1825         (match_operand:DI 1 "register_operand" ""))
1826    (parallel
1827     [(set (match_dup 0)
1828           (plus:DI (match_dup 0)
1829                    (match_operand:DI 2 "nonmemory_operand" "")))
1830      (clobber (reg:CC CC_REGNUM))])]
1831   "TARGET_64BIT
1832    && !reg_overlap_mentioned_p (operands[0], operands[2])
1833    && preferred_la_operand_p (operands[1], operands[2])"
1834   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1835   "")
1836
1837 ;
1838 ; movsi instruction pattern(s).
1839 ;
1840
1841 (define_expand "movsi"
1842   [(set (match_operand:SI 0 "general_operand" "")
1843         (match_operand:SI 1 "general_operand" ""))]
1844   ""
1845 {
1846   /* Handle symbolic constants.  */
1847   if (!TARGET_64BIT
1848       && (SYMBOLIC_CONST (operands[1])
1849           || (GET_CODE (operands[1]) == PLUS
1850               && XEXP (operands[1], 0) == pic_offset_table_rtx
1851               && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1852     emit_symbolic_move (operands);
1853 })
1854
1855 (define_insn "*movsi_larl"
1856   [(set (match_operand:SI 0 "register_operand" "=d")
1857         (match_operand:SI 1 "larl_operand" "X"))]
1858   "!TARGET_64BIT && TARGET_CPU_ZARCH
1859    && !FP_REG_P (operands[0])"
1860   "larl\t%0,%1"
1861    [(set_attr "op_type" "RIL")
1862     (set_attr "type"    "larl")
1863     (set_attr "z10prop" "z10_fwd_A1")])
1864
1865 (define_insn "*movsi_zarch"
1866   [(set (match_operand:SI 0 "nonimmediate_operand"
1867          "=d,    d,    d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1868         (match_operand:SI 1 "general_operand"
1869          " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f,  R,  R,  T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1870   "TARGET_ZARCH"
1871   "@
1872    lhi\t%0,%h1
1873    llilh\t%0,%i1
1874    llill\t%0,%i1
1875    iilf\t%0,%o1
1876    lay\t%0,%a1
1877    lrl\t%0,%1
1878    lr\t%0,%1
1879    l\t%0,%1
1880    ly\t%0,%1
1881    st\t%1,%0
1882    sty\t%1,%0
1883    lder\t%0,%1
1884    ler\t%0,%1
1885    lde\t%0,%1
1886    le\t%0,%1
1887    ley\t%0,%1
1888    ste\t%1,%0
1889    stey\t%1,%0
1890    ear\t%0,%1
1891    sar\t%0,%1
1892    stam\t%1,%1,%S0
1893    strl\t%1,%0
1894    mvhi\t%0,%1
1895    lam\t%0,%0,%S1
1896    vleif\t%v0,%h1,0
1897    vlr\t%v0,%v1
1898    vlvgf\t%v0,%1,0
1899    vlgvf\t%0,%v1,0
1900    vlef\t%v0,%1,0
1901    vstef\t%v1,%0,0"
1902   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1903                         RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1904    (set_attr "type" "*,
1905                      *,
1906                      *,
1907                      *,
1908                      la,
1909                      larl,
1910                      lr,
1911                      load,
1912                      load,
1913                      store,
1914                      store,
1915                      floadsf,
1916                      floadsf,
1917                      floadsf,
1918                      floadsf,
1919                      floadsf,
1920                      fstoresf,
1921                      fstoresf,
1922                      *,
1923                      *,
1924                      *,
1925                      larl,
1926                      *,
1927                      *,*,*,*,*,*,*")
1928    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1929                              vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1930    (set_attr "z10prop" "z10_fwd_A1,
1931                         z10_fwd_E1,
1932                         z10_fwd_E1,
1933                         z10_fwd_A1,
1934                         z10_fwd_A1,
1935                         z10_fwd_A3,
1936                         z10_fr_E1,
1937                         z10_fwd_A3,
1938                         z10_fwd_A3,
1939                         z10_rec,
1940                         z10_rec,
1941                         *,
1942                         *,
1943                         *,
1944                         *,
1945                         *,
1946                         *,
1947                         *,
1948                         z10_super_E1,
1949                         z10_super,
1950                         *,
1951                         z10_rec,
1952                         z10_super,
1953                         *,*,*,*,*,*,*")])
1954
1955 (define_insn "*movsi_esa"
1956   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1957         (match_operand:SI 1 "general_operand"       "K,d,R,d, *f, *f,  R,  R,*f,t,d,t,Q"))]
1958   "!TARGET_ZARCH"
1959   "@
1960    lhi\t%0,%h1
1961    lr\t%0,%1
1962    l\t%0,%1
1963    st\t%1,%0
1964    lder\t%0,%1
1965    ler\t%0,%1
1966    lde\t%0,%1
1967    le\t%0,%1
1968    ste\t%1,%0
1969    ear\t%0,%1
1970    sar\t%0,%1
1971    stam\t%1,%1,%S0
1972    lam\t%0,%0,%S1"
1973   [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1974    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1975    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1976                         z10_super,*,*")
1977    (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1978 ])
1979
1980 (define_peephole2
1981   [(set (match_operand:SI 0 "register_operand" "")
1982         (mem:SI (match_operand 1 "address_operand" "")))]
1983   "!FP_REG_P (operands[0])
1984    && GET_CODE (operands[1]) == SYMBOL_REF
1985    && CONSTANT_POOL_ADDRESS_P (operands[1])
1986    && get_pool_mode (operands[1]) == SImode
1987    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1988   [(set (match_dup 0) (match_dup 2))]
1989   "operands[2] = get_pool_constant (operands[1]);")
1990
1991 (define_insn "*la_31"
1992   [(set (match_operand:SI 0 "register_operand" "=d,d")
1993         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1994   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1995   "@
1996    la\t%0,%a1
1997    lay\t%0,%a1"
1998   [(set_attr "op_type"  "RX,RXY")
1999    (set_attr "type"     "la")
2000    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2001
2002 (define_peephole2
2003   [(parallel
2004     [(set (match_operand:SI 0 "register_operand" "")
2005           (match_operand:QI 1 "address_operand" ""))
2006      (clobber (reg:CC CC_REGNUM))])]
2007   "!TARGET_64BIT
2008    && preferred_la_operand_p (operands[1], const0_rtx)"
2009   [(set (match_dup 0) (match_dup 1))]
2010   "")
2011
2012 (define_peephole2
2013   [(set (match_operand:SI 0 "register_operand" "")
2014         (match_operand:SI 1 "register_operand" ""))
2015    (parallel
2016     [(set (match_dup 0)
2017           (plus:SI (match_dup 0)
2018                    (match_operand:SI 2 "nonmemory_operand" "")))
2019      (clobber (reg:CC CC_REGNUM))])]
2020   "!TARGET_64BIT
2021    && !reg_overlap_mentioned_p (operands[0], operands[2])
2022    && preferred_la_operand_p (operands[1], operands[2])"
2023   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2024   "")
2025
2026 (define_insn "*la_31_and"
2027   [(set (match_operand:SI 0 "register_operand" "=d,d")
2028         (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
2029                 (const_int 2147483647)))]
2030   "!TARGET_64BIT"
2031   "@
2032    la\t%0,%a1
2033    lay\t%0,%a1"
2034   [(set_attr "op_type"  "RX,RXY")
2035    (set_attr "type"     "la")
2036    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2037
2038 (define_insn_and_split "*la_31_and_cc"
2039   [(set (match_operand:SI 0 "register_operand" "=d")
2040         (and:SI (match_operand:QI 1 "address_operand" "p")
2041                 (const_int 2147483647)))
2042    (clobber (reg:CC CC_REGNUM))]
2043   "!TARGET_64BIT"
2044   "#"
2045   "&& reload_completed"
2046   [(set (match_dup 0)
2047         (and:SI (match_dup 1) (const_int 2147483647)))]
2048   ""
2049   [(set_attr "op_type"  "RX")
2050    (set_attr "type"     "la")])
2051
2052 (define_insn "force_la_31"
2053   [(set (match_operand:SI 0 "register_operand" "=d,d")
2054         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
2055    (use (const_int 0))]
2056   "!TARGET_64BIT"
2057   "@
2058    la\t%0,%a1
2059    lay\t%0,%a1"
2060   [(set_attr "op_type"  "RX")
2061    (set_attr "type"     "la")
2062    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2063
2064 ;
2065 ; movhi instruction pattern(s).
2066 ;
2067
2068 (define_expand "movhi"
2069   [(set (match_operand:HI 0 "nonimmediate_operand" "")
2070         (match_operand:HI 1 "general_operand" ""))]
2071   ""
2072 {
2073   /* Make it explicit that loading a register from memory
2074      always sign-extends (at least) to SImode.  */
2075   if (optimize && can_create_pseudo_p ()
2076       && register_operand (operands[0], VOIDmode)
2077       && GET_CODE (operands[1]) == MEM)
2078     {
2079       rtx tmp = gen_reg_rtx (SImode);
2080       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2081       emit_insn (gen_rtx_SET (tmp, ext));
2082       operands[1] = gen_lowpart (HImode, tmp);
2083     }
2084 })
2085
2086 (define_insn "*movhi"
2087   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
2088         (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
2089   ""
2090   "@
2091    lr\t%0,%1
2092    lhi\t%0,%h1
2093    lh\t%0,%1
2094    lhy\t%0,%1
2095    lhrl\t%0,%1
2096    sth\t%1,%0
2097    sthy\t%1,%0
2098    sthrl\t%1,%0
2099    mvhhi\t%0,%1
2100    vleih\t%v0,%h1,0
2101    vlr\t%v0,%v1
2102    vlvgh\t%v0,%1,0
2103    vlgvh\t%0,%v1,0
2104    vleh\t%v0,%1,0
2105    vsteh\t%v1,%0,0"
2106   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2107    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2108    (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
2109    (set_attr "z10prop" "z10_fr_E1,
2110                        z10_fwd_A1,
2111                        z10_super_E1,
2112                        z10_super_E1,
2113                        z10_super_E1,
2114                        z10_rec,
2115                        z10_rec,
2116                        z10_rec,
2117                        z10_super,*,*,*,*,*,*")])
2118
2119 (define_peephole2
2120   [(set (match_operand:HI 0 "register_operand" "")
2121         (mem:HI (match_operand 1 "address_operand" "")))]
2122   "GET_CODE (operands[1]) == SYMBOL_REF
2123    && CONSTANT_POOL_ADDRESS_P (operands[1])
2124    && get_pool_mode (operands[1]) == HImode
2125    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2126   [(set (match_dup 0) (match_dup 2))]
2127   "operands[2] = get_pool_constant (operands[1]);")
2128
2129 ;
2130 ; movqi instruction pattern(s).
2131 ;
2132
2133 (define_expand "movqi"
2134   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2135         (match_operand:QI 1 "general_operand" ""))]
2136   ""
2137 {
2138   /* On z/Architecture, zero-extending from memory to register
2139      is just as fast as a QImode load.  */
2140   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2141       && register_operand (operands[0], VOIDmode)
2142       && GET_CODE (operands[1]) == MEM)
2143     {
2144       rtx tmp = gen_reg_rtx (DImode);
2145       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2146       emit_insn (gen_rtx_SET (tmp, ext));
2147       operands[1] = gen_lowpart (QImode, tmp);
2148     }
2149 })
2150
2151 (define_insn "*movqi"
2152   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2153         (match_operand:QI 1 "general_operand"      " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2154   ""
2155   "@
2156    lr\t%0,%1
2157    lhi\t%0,%b1
2158    ic\t%0,%1
2159    icy\t%0,%1
2160    stc\t%1,%0
2161    stcy\t%1,%0
2162    mvi\t%S0,%b1
2163    mviy\t%S0,%b1
2164    #
2165    vleib\t%v0,%b1,0
2166    vlr\t%v0,%v1
2167    vlvgb\t%v0,%1,0
2168    vlgvb\t%0,%v1,0
2169    vleb\t%v0,%1,0
2170    vsteb\t%v1,%0,0"
2171   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2172    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2173    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2174    (set_attr "z10prop" "z10_fr_E1,
2175                         z10_fwd_A1,
2176                         z10_super_E1,
2177                         z10_super_E1,
2178                         z10_rec,
2179                         z10_rec,
2180                         z10_super,
2181                         z10_super,
2182                         *,*,*,*,*,*,*")])
2183
2184 (define_peephole2
2185   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2186         (mem:QI (match_operand 1 "address_operand" "")))]
2187   "GET_CODE (operands[1]) == SYMBOL_REF
2188    && CONSTANT_POOL_ADDRESS_P (operands[1])
2189    && get_pool_mode (operands[1]) == QImode
2190    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2191   [(set (match_dup 0) (match_dup 2))]
2192   "operands[2] = get_pool_constant (operands[1]);")
2193
2194 ;
2195 ; movstrictqi instruction pattern(s).
2196 ;
2197
2198 (define_insn "*movstrictqi"
2199   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2200                          (match_operand:QI 1 "memory_operand" "R,T"))]
2201   ""
2202   "@
2203    ic\t%0,%1
2204    icy\t%0,%1"
2205   [(set_attr "op_type"  "RX,RXY")
2206    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2207
2208 ;
2209 ; movstricthi instruction pattern(s).
2210 ;
2211
2212 (define_insn "*movstricthi"
2213   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2214                          (match_operand:HI 1 "memory_operand" "Q,S"))
2215    (clobber (reg:CC CC_REGNUM))]
2216   ""
2217   "@
2218    icm\t%0,3,%S1
2219    icmy\t%0,3,%S1"
2220   [(set_attr "op_type" "RS,RSY")
2221    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2222
2223 ;
2224 ; movstrictsi instruction pattern(s).
2225 ;
2226
2227 (define_insn "movstrictsi"
2228   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2229                          (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2230   "TARGET_ZARCH"
2231   "@
2232    lr\t%0,%1
2233    l\t%0,%1
2234    ly\t%0,%1
2235    ear\t%0,%1"
2236   [(set_attr "op_type" "RR,RX,RXY,RRE")
2237    (set_attr "type" "lr,load,load,*")
2238    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2239
2240 ;
2241 ; mov(tf|td) instruction pattern(s).
2242 ;
2243
2244 (define_expand "mov<mode>"
2245   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2246         (match_operand:TD_TF 1 "general_operand"      ""))]
2247   ""
2248   "")
2249
2250 (define_insn "*mov<mode>_64"
2251   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS,  d,o")
2252         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d"))]
2253   "TARGET_ZARCH"
2254   "@
2255    lzxr\t%0
2256    lxr\t%0,%1
2257    #
2258    #
2259    lmg\t%0,%N0,%S1
2260    stmg\t%1,%N1,%S0
2261    #
2262    #"
2263   [(set_attr "op_type"      "RRE,RRE,*,*,RSY,RSY,*,*")
2264    (set_attr "type"         "fsimptf,fsimptf,*,*,lm,stm,*,*")
2265    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2266
2267 (define_insn "*mov<mode>_31"
2268   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2269         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
2270   "!TARGET_ZARCH"
2271   "@
2272    lzxr\t%0
2273    lxr\t%0,%1
2274    #
2275    #"
2276   [(set_attr "op_type"      "RRE,RRE,*,*")
2277    (set_attr "type"         "fsimptf,fsimptf,*,*")
2278    (set_attr "cpu_facility" "z196,*,*,*")])
2279
2280 ; TFmode in GPRs splitters
2281
2282 (define_split
2283   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2284         (match_operand:TD_TF 1 "general_operand"      ""))]
2285   "TARGET_ZARCH && reload_completed
2286    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2287   [(set (match_dup 2) (match_dup 4))
2288    (set (match_dup 3) (match_dup 5))]
2289 {
2290   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2291   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2292   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2293   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2294 })
2295
2296 (define_split
2297   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2298         (match_operand:TD_TF 1 "general_operand"      ""))]
2299   "TARGET_ZARCH && reload_completed
2300    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2301   [(set (match_dup 2) (match_dup 4))
2302    (set (match_dup 3) (match_dup 5))]
2303 {
2304   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2305   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2306   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2307   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2308 })
2309
2310 (define_split
2311   [(set (match_operand:TD_TF 0 "register_operand" "")
2312         (match_operand:TD_TF 1 "memory_operand"   ""))]
2313   "TARGET_ZARCH && reload_completed
2314    && GENERAL_REG_P (operands[0])
2315    && !s_operand (operands[1], VOIDmode)"
2316   [(set (match_dup 0) (match_dup 1))]
2317 {
2318   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2319   addr = gen_lowpart (Pmode, addr);
2320   s390_load_address (addr, XEXP (operands[1], 0));
2321   operands[1] = replace_equiv_address (operands[1], addr);
2322 })
2323
2324 ; TFmode in BFPs splitters
2325
2326 (define_split
2327   [(set (match_operand:TD_TF 0 "register_operand" "")
2328         (match_operand:TD_TF 1 "memory_operand" ""))]
2329   "reload_completed && offsettable_memref_p (operands[1])
2330    && FP_REG_P (operands[0])"
2331   [(set (match_dup 2) (match_dup 4))
2332    (set (match_dup 3) (match_dup 5))]
2333 {
2334   operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2335                                      <MODE>mode, 0);
2336   operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2337                                      <MODE>mode, 8);
2338   operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2339   operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2340 })
2341
2342 (define_split
2343   [(set (match_operand:TD_TF 0 "memory_operand" "")
2344         (match_operand:TD_TF 1 "register_operand" ""))]
2345   "reload_completed && offsettable_memref_p (operands[0])
2346    && FP_REG_P (operands[1])"
2347   [(set (match_dup 2) (match_dup 4))
2348    (set (match_dup 3) (match_dup 5))]
2349 {
2350   operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2351   operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2352   operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2353                                      <MODE>mode, 0);
2354   operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2355                                      <MODE>mode, 8);
2356 })
2357
2358 ;
2359 ; mov(df|dd) instruction pattern(s).
2360 ;
2361
2362 (define_expand "mov<mode>"
2363   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2364         (match_operand:DD_DF 1 "general_operand"  ""))]
2365   ""
2366   "")
2367
2368 (define_insn "*mov<mode>_64dfp"
2369   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2370                                "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2371         (match_operand:DD_DF 1 "general_operand"
2372                                " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2373   "TARGET_DFP"
2374   "@
2375    lzdr\t%0
2376    ldr\t%0,%1
2377    ldgr\t%0,%1
2378    lgdr\t%0,%1
2379    ld\t%0,%1
2380    ldy\t%0,%1
2381    std\t%1,%0
2382    stdy\t%1,%0
2383    lghi\t%0,0
2384    lgr\t%0,%1
2385    lgrl\t%0,%1
2386    lg\t%0,%1
2387    stgrl\t%1,%0
2388    stg\t%1,%0
2389    vlr\t%v0,%v1
2390    vlvgg\t%v0,%1,0
2391    vlgvg\t%0,%v1,0
2392    vleg\t%0,%1,0
2393    vsteg\t%1,%0,0"
2394   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2395    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2396                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2397    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2398    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2399
2400 (define_insn "*mov<mode>_64"
2401   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2402         (match_operand:DD_DF 1 "general_operand"      " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2403   "TARGET_ZARCH"
2404   "@
2405    lzdr\t%0
2406    ldr\t%0,%1
2407    ld\t%0,%1
2408    ldy\t%0,%1
2409    std\t%1,%0
2410    stdy\t%1,%0
2411    lghi\t%0,0
2412    lgr\t%0,%1
2413    lgrl\t%0,%1
2414    lg\t%0,%1
2415    stgrl\t%1,%0
2416    stg\t%1,%0
2417    vlr\t%v0,%v1
2418    vleg\t%v0,%1,0
2419    vsteg\t%v1,%0,0"
2420   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2421    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2422                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2423    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2424    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2425
2426 (define_insn "*mov<mode>_31"
2427   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2428                                "=f,f,f,f,R,T,d,d,Q,S,   d,o")
2429         (match_operand:DD_DF 1 "general_operand"
2430                                " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2431   "!TARGET_ZARCH"
2432   "@
2433    lzdr\t%0
2434    ldr\t%0,%1
2435    ld\t%0,%1
2436    ldy\t%0,%1
2437    std\t%1,%0
2438    stdy\t%1,%0
2439    lm\t%0,%N0,%S1
2440    lmy\t%0,%N0,%S1
2441    stm\t%1,%N1,%S0
2442    stmy\t%1,%N1,%S0
2443    #
2444    #"
2445   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2446    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2447                         fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2448    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2449
2450 (define_split
2451   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2452         (match_operand:DD_DF 1 "general_operand" ""))]
2453   "!TARGET_ZARCH && reload_completed
2454    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2455   [(set (match_dup 2) (match_dup 4))
2456    (set (match_dup 3) (match_dup 5))]
2457 {
2458   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2459   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2460   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2461   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2462 })
2463
2464 (define_split
2465   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2466         (match_operand:DD_DF 1 "general_operand" ""))]
2467   "!TARGET_ZARCH && reload_completed
2468    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2469   [(set (match_dup 2) (match_dup 4))
2470    (set (match_dup 3) (match_dup 5))]
2471 {
2472   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2473   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2474   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2475   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2476 })
2477
2478 (define_split
2479   [(set (match_operand:DD_DF 0 "register_operand" "")
2480         (match_operand:DD_DF 1 "memory_operand" ""))]
2481   "!TARGET_ZARCH && reload_completed
2482    && !FP_REG_P (operands[0])
2483    && !s_operand (operands[1], VOIDmode)"
2484   [(set (match_dup 0) (match_dup 1))]
2485 {
2486   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2487   s390_load_address (addr, XEXP (operands[1], 0));
2488   operands[1] = replace_equiv_address (operands[1], addr);
2489 })
2490
2491 ;
2492 ; mov(sf|sd) instruction pattern(s).
2493 ;
2494
2495 (define_insn "mov<mode>"
2496   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2497                                "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2498         (match_operand:SD_SF 1 "general_operand"
2499                                " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2500   ""
2501   "@
2502    lzer\t%0
2503    lder\t%0,%1
2504    ler\t%0,%1
2505    lde\t%0,%1
2506    le\t%0,%1
2507    ley\t%0,%1
2508    ste\t%1,%0
2509    stey\t%1,%0
2510    lhi\t%0,0
2511    lr\t%0,%1
2512    lrl\t%0,%1
2513    l\t%0,%1
2514    ly\t%0,%1
2515    strl\t%1,%0
2516    st\t%1,%0
2517    sty\t%1,%0
2518    vlr\t%v0,%v1
2519    vleif\t%v0,0
2520    vlvgf\t%v0,%1,0
2521    vlgvf\t%0,%v1,0
2522    vleg\t%0,%1,0
2523    vsteg\t%1,%0,0"
2524   [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2525    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2526                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2527    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2528    (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2529
2530 ;
2531 ; movcc instruction pattern
2532 ;
2533
2534 (define_insn "movcc"
2535   [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2536         (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2537   ""
2538   "@
2539    lr\t%0,%1
2540    tmh\t%1,12288
2541    ipm\t%0
2542    l\t%0,%1
2543    ly\t%0,%1
2544    st\t%1,%0
2545    sty\t%1,%0"
2546   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2547    (set_attr "type" "lr,*,*,load,load,store,store")
2548    (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2549    (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2550
2551 ;
2552 ; Block move (MVC) patterns.
2553 ;
2554
2555 (define_insn "*mvc"
2556   [(set (match_operand:BLK 0 "memory_operand" "=Q")
2557         (match_operand:BLK 1 "memory_operand" "Q"))
2558    (use (match_operand 2 "const_int_operand" "n"))]
2559   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2560   "mvc\t%O0(%2,%R0),%S1"
2561   [(set_attr "op_type" "SS")])
2562
2563 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2564 ; order to have it implemented with mvc.
2565
2566 (define_split
2567   [(set (match_operand:QI 0 "memory_operand" "")
2568         (match_operand:QI 1 "memory_operand" ""))]
2569   "reload_completed"
2570   [(parallel
2571     [(set (match_dup 0) (match_dup 1))
2572      (use (const_int 1))])]
2573 {
2574   operands[0] = adjust_address (operands[0], BLKmode, 0);
2575   operands[1] = adjust_address (operands[1], BLKmode, 0);
2576 })
2577
2578
2579 (define_peephole2
2580   [(parallel
2581     [(set (match_operand:BLK 0 "memory_operand" "")
2582           (match_operand:BLK 1 "memory_operand" ""))
2583      (use (match_operand 2 "const_int_operand" ""))])
2584    (parallel
2585     [(set (match_operand:BLK 3 "memory_operand" "")
2586           (match_operand:BLK 4 "memory_operand" ""))
2587      (use (match_operand 5 "const_int_operand" ""))])]
2588   "s390_offset_p (operands[0], operands[3], operands[2])
2589    && s390_offset_p (operands[1], operands[4], operands[2])
2590    && !s390_overlap_p (operands[0], operands[1],
2591                        INTVAL (operands[2]) + INTVAL (operands[5]))
2592    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2593   [(parallel
2594     [(set (match_dup 6) (match_dup 7))
2595      (use (match_dup 8))])]
2596   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2597    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2598    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2599
2600
2601 ;
2602 ; load_multiple pattern(s).
2603 ;
2604 ; ??? Due to reload problems with replacing registers inside match_parallel
2605 ; we currently support load_multiple/store_multiple only after reload.
2606 ;
2607
2608 (define_expand "load_multiple"
2609   [(match_par_dup 3 [(set (match_operand 0 "" "")
2610                           (match_operand 1 "" ""))
2611                      (use (match_operand 2 "" ""))])]
2612   "reload_completed"
2613 {
2614   machine_mode mode;
2615   int regno;
2616   int count;
2617   rtx from;
2618   int i, off;
2619
2620   /* Support only loading a constant number of fixed-point registers from
2621      memory and only bother with this if more than two */
2622   if (GET_CODE (operands[2]) != CONST_INT
2623       || INTVAL (operands[2]) < 2
2624       || INTVAL (operands[2]) > 16
2625       || GET_CODE (operands[1]) != MEM
2626       || GET_CODE (operands[0]) != REG
2627       || REGNO (operands[0]) >= 16)
2628     FAIL;
2629
2630   count = INTVAL (operands[2]);
2631   regno = REGNO (operands[0]);
2632   mode = GET_MODE (operands[0]);
2633   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2634     FAIL;
2635
2636   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2637   if (!can_create_pseudo_p ())
2638     {
2639       if (GET_CODE (XEXP (operands[1], 0)) == REG)
2640         {
2641           from = XEXP (operands[1], 0);
2642           off = 0;
2643         }
2644       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2645                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2646                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2647         {
2648           from = XEXP (XEXP (operands[1], 0), 0);
2649           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2650         }
2651       else
2652         FAIL;
2653     }
2654   else
2655     {
2656       from = force_reg (Pmode, XEXP (operands[1], 0));
2657       off = 0;
2658     }
2659
2660   for (i = 0; i < count; i++)
2661     XVECEXP (operands[3], 0, i)
2662       = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2663                      change_address (operands[1], mode,
2664                        plus_constant (Pmode, from,
2665                                       off + i * GET_MODE_SIZE (mode))));
2666 })
2667
2668 (define_insn "*load_multiple_di"
2669   [(match_parallel 0 "load_multiple_operation"
2670                    [(set (match_operand:DI 1 "register_operand" "=r")
2671                          (match_operand:DI 2 "s_operand" "QS"))])]
2672   "reload_completed && TARGET_ZARCH"
2673 {
2674   int words = XVECLEN (operands[0], 0);
2675   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2676   return "lmg\t%1,%0,%S2";
2677 }
2678    [(set_attr "op_type" "RSY")
2679     (set_attr "type"    "lm")])
2680
2681 (define_insn "*load_multiple_si"
2682   [(match_parallel 0 "load_multiple_operation"
2683                    [(set (match_operand:SI 1 "register_operand" "=r,r")
2684                          (match_operand:SI 2 "s_operand" "Q,S"))])]
2685   "reload_completed"
2686 {
2687   int words = XVECLEN (operands[0], 0);
2688   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2689   return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2690 }
2691    [(set_attr "op_type" "RS,RSY")
2692     (set_attr "type"    "lm")])
2693
2694 ;
2695 ; store multiple pattern(s).
2696 ;
2697
2698 (define_expand "store_multiple"
2699   [(match_par_dup 3 [(set (match_operand 0 "" "")
2700                           (match_operand 1 "" ""))
2701                      (use (match_operand 2 "" ""))])]
2702   "reload_completed"
2703 {
2704   machine_mode mode;
2705   int regno;
2706   int count;
2707   rtx to;
2708   int i, off;
2709
2710   /* Support only storing a constant number of fixed-point registers to
2711      memory and only bother with this if more than two.  */
2712   if (GET_CODE (operands[2]) != CONST_INT
2713       || INTVAL (operands[2]) < 2
2714       || INTVAL (operands[2]) > 16
2715       || GET_CODE (operands[0]) != MEM
2716       || GET_CODE (operands[1]) != REG
2717       || REGNO (operands[1]) >= 16)
2718     FAIL;
2719
2720   count = INTVAL (operands[2]);
2721   regno = REGNO (operands[1]);
2722   mode = GET_MODE (operands[1]);
2723   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2724     FAIL;
2725
2726   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2727
2728   if (!can_create_pseudo_p ())
2729     {
2730       if (GET_CODE (XEXP (operands[0], 0)) == REG)
2731         {
2732           to = XEXP (operands[0], 0);
2733           off = 0;
2734         }
2735       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2736                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2737                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2738         {
2739           to = XEXP (XEXP (operands[0], 0), 0);
2740           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2741         }
2742       else
2743         FAIL;
2744     }
2745   else
2746     {
2747       to = force_reg (Pmode, XEXP (operands[0], 0));
2748       off = 0;
2749     }
2750
2751   for (i = 0; i < count; i++)
2752     XVECEXP (operands[3], 0, i)
2753       = gen_rtx_SET (change_address (operands[0], mode,
2754                        plus_constant (Pmode, to,
2755                                       off + i * GET_MODE_SIZE (mode))),
2756                      gen_rtx_REG (mode, regno + i));
2757 })
2758
2759 (define_insn "*store_multiple_di"
2760   [(match_parallel 0 "store_multiple_operation"
2761                    [(set (match_operand:DI 1 "s_operand" "=QS")
2762                          (match_operand:DI 2 "register_operand" "r"))])]
2763   "reload_completed && TARGET_ZARCH"
2764 {
2765   int words = XVECLEN (operands[0], 0);
2766   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2767   return "stmg\t%2,%0,%S1";
2768 }
2769    [(set_attr "op_type" "RSY")
2770     (set_attr "type"    "stm")])
2771
2772
2773 (define_insn "*store_multiple_si"
2774   [(match_parallel 0 "store_multiple_operation"
2775                    [(set (match_operand:SI 1 "s_operand" "=Q,S")
2776                          (match_operand:SI 2 "register_operand" "r,r"))])]
2777   "reload_completed"
2778 {
2779   int words = XVECLEN (operands[0], 0);
2780   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2781   return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2782 }
2783    [(set_attr "op_type" "RS,RSY")
2784     (set_attr "type"    "stm")])
2785
2786 ;;
2787 ;; String instructions.
2788 ;;
2789
2790 (define_insn "*execute_rl"
2791   [(match_parallel 0 "execute_operation"
2792     [(unspec [(match_operand 1    "register_operand" "a")
2793               (match_operand 2    "" "")
2794               (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2795   "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2796    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2797   "exrl\t%1,%3"
2798   [(set_attr "op_type" "RIL")
2799    (set_attr "type"    "cs")])
2800
2801 (define_insn "*execute"
2802   [(match_parallel 0 "execute_operation"
2803     [(unspec [(match_operand 1 "register_operand" "a")
2804               (match_operand:BLK 2 "memory_operand" "R")
2805               (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2806   "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2807    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2808   "ex\t%1,%2"
2809   [(set_attr "op_type" "RX")
2810    (set_attr "type" "cs")])
2811
2812
2813 ;
2814 ; strlenM instruction pattern(s).
2815 ;
2816
2817 (define_expand "strlen<mode>"
2818   [(match_operand:P   0 "register_operand" "")  ; result
2819    (match_operand:BLK 1 "memory_operand" "")    ; input string
2820    (match_operand:SI  2 "immediate_operand" "") ; search character
2821    (match_operand:SI  3 "immediate_operand" "")] ; known alignment
2822   ""
2823 {
2824   if (!TARGET_VX || operands[2] != const0_rtx)
2825     emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2826                                       operands[2], operands[3]));
2827   else
2828     s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2829
2830   DONE;
2831 })
2832
2833 (define_expand "strlen_srst<mode>"
2834   [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2835    (parallel
2836     [(set (match_dup 4)
2837           (unspec:P [(const_int 0)
2838                       (match_operand:BLK 1 "memory_operand" "")
2839                       (reg:SI 0)
2840                       (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2841      (clobber (scratch:P))
2842      (clobber (reg:CC CC_REGNUM))])
2843    (parallel
2844     [(set (match_operand:P 0 "register_operand" "")
2845           (minus:P (match_dup 4) (match_dup 5)))
2846      (clobber (reg:CC CC_REGNUM))])]
2847   ""
2848 {
2849   operands[4] = gen_reg_rtx (Pmode);
2850   operands[5] = gen_reg_rtx (Pmode);
2851   emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2852   operands[1] = replace_equiv_address (operands[1], operands[5]);
2853 })
2854
2855 (define_insn "*strlen<mode>"
2856   [(set (match_operand:P 0 "register_operand" "=a")
2857         (unspec:P [(match_operand:P 2 "general_operand" "0")
2858                     (mem:BLK (match_operand:P 3 "register_operand" "1"))
2859                     (reg:SI 0)
2860                     (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2861    (clobber (match_scratch:P 1 "=a"))
2862    (clobber (reg:CC CC_REGNUM))]
2863   ""
2864   "srst\t%0,%1\;jo\t.-4"
2865   [(set_attr "length" "8")
2866    (set_attr "type" "vs")])
2867
2868 ;
2869 ; cmpstrM instruction pattern(s).
2870 ;
2871
2872 (define_expand "cmpstrsi"
2873   [(set (reg:SI 0) (const_int 0))
2874    (parallel
2875     [(clobber (match_operand 3 "" ""))
2876      (clobber (match_dup 4))
2877      (set (reg:CCU CC_REGNUM)
2878           (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2879                        (match_operand:BLK 2 "memory_operand" "")))
2880      (use (reg:SI 0))])
2881    (parallel
2882     [(set (match_operand:SI 0 "register_operand" "=d")
2883           (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2884      (clobber (reg:CC CC_REGNUM))])]
2885   ""
2886 {
2887   /* As the result of CMPINT is inverted compared to what we need,
2888      we have to swap the operands.  */
2889   rtx op1 = operands[2];
2890   rtx op2 = operands[1];
2891   rtx addr1 = gen_reg_rtx (Pmode);
2892   rtx addr2 = gen_reg_rtx (Pmode);
2893
2894   emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2895   emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2896   operands[1] = replace_equiv_address_nv (op1, addr1);
2897   operands[2] = replace_equiv_address_nv (op2, addr2);
2898   operands[3] = addr1;
2899   operands[4] = addr2;
2900 })
2901
2902 (define_insn "*cmpstr<mode>"
2903   [(clobber (match_operand:P 0 "register_operand" "=d"))
2904    (clobber (match_operand:P 1 "register_operand" "=d"))
2905    (set (reg:CCU CC_REGNUM)
2906         (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2907                      (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2908    (use (reg:SI 0))]
2909   ""
2910   "clst\t%0,%1\;jo\t.-4"
2911   [(set_attr "length" "8")
2912    (set_attr "type" "vs")])
2913
2914 ;
2915 ; movstr instruction pattern.
2916 ;
2917
2918 (define_expand "movstr"
2919   [(match_operand 0 "register_operand" "")
2920    (match_operand 1 "memory_operand" "")
2921    (match_operand 2 "memory_operand" "")]
2922   ""
2923 {
2924   if (TARGET_64BIT)
2925     emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2926   else
2927     emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2928   DONE;
2929 })
2930
2931 (define_expand "movstr<P:mode>"
2932   [(set (reg:SI 0) (const_int 0))
2933    (parallel
2934     [(clobber (match_dup 3))
2935      (set (match_operand:BLK 1 "memory_operand" "")
2936           (match_operand:BLK 2 "memory_operand" ""))
2937      (set (match_operand:P 0 "register_operand" "")
2938           (unspec:P [(match_dup 1)
2939                    (match_dup 2)
2940                    (reg:SI 0)] UNSPEC_MVST))
2941      (clobber (reg:CC CC_REGNUM))])]
2942   ""
2943 {
2944   rtx addr1 = gen_reg_rtx (Pmode);
2945   rtx addr2 = gen_reg_rtx (Pmode);
2946
2947   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2948   emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2949   operands[1] = replace_equiv_address_nv (operands[1], addr1);
2950   operands[2] = replace_equiv_address_nv (operands[2], addr2);
2951   operands[3] = addr2;
2952 })
2953
2954 (define_insn "*movstr"
2955   [(clobber (match_operand:P 2 "register_operand" "=d"))
2956    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2957         (mem:BLK (match_operand:P 3 "register_operand" "2")))
2958    (set (match_operand:P 0 "register_operand" "=d")
2959         (unspec:P [(mem:BLK (match_dup 1))
2960                  (mem:BLK (match_dup 3))
2961                  (reg:SI 0)] UNSPEC_MVST))
2962    (clobber (reg:CC CC_REGNUM))]
2963   ""
2964   "mvst\t%1,%2\;jo\t.-4"
2965   [(set_attr "length" "8")
2966    (set_attr "type" "vs")])
2967
2968
2969 ;
2970 ; movmemM instruction pattern(s).
2971 ;
2972
2973 (define_expand "movmem<mode>"
2974   [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
2975         (match_operand:BLK 1 "memory_operand" ""))  ; source
2976    (use (match_operand:GPR 2 "general_operand" "")) ; count
2977    (match_operand 3 "" "")]
2978   ""
2979 {
2980   if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2981     DONE;
2982   else
2983     FAIL;
2984 })
2985
2986 ; Move a block that is up to 256 bytes in length.
2987 ; The block length is taken as (operands[2] % 256) + 1.
2988
2989 (define_expand "movmem_short"
2990   [(parallel
2991     [(set (match_operand:BLK 0 "memory_operand" "")
2992           (match_operand:BLK 1 "memory_operand" ""))
2993      (use (match_operand 2 "nonmemory_operand" ""))
2994      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2995      (clobber (match_dup 3))])]
2996   ""
2997   "operands[3] = gen_rtx_SCRATCH (Pmode);")
2998
2999 (define_insn "*movmem_short"
3000   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3001         (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3002    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3003    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3004    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3005   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3006   "#"
3007   [(set_attr "type"         "cs")
3008    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3009
3010 (define_split
3011   [(set (match_operand:BLK 0 "memory_operand" "")
3012         (match_operand:BLK 1 "memory_operand" ""))
3013    (use (match_operand 2 "const_int_operand" ""))
3014    (use (match_operand 3 "immediate_operand" ""))
3015    (clobber (scratch))]
3016   "reload_completed"
3017   [(parallel
3018     [(set (match_dup 0) (match_dup 1))
3019      (use (match_dup 2))])]
3020   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3021
3022 (define_split
3023   [(set (match_operand:BLK 0 "memory_operand" "")
3024         (match_operand:BLK 1 "memory_operand" ""))
3025    (use (match_operand 2 "register_operand" ""))
3026    (use (match_operand 3 "memory_operand" ""))
3027    (clobber (scratch))]
3028   "reload_completed"
3029   [(parallel
3030     [(unspec [(match_dup 2) (match_dup 3)
3031               (const_int 0)] UNSPEC_EXECUTE)
3032      (set (match_dup 0) (match_dup 1))
3033      (use (const_int 1))])]
3034   "")
3035
3036 (define_split
3037   [(set (match_operand:BLK 0 "memory_operand" "")
3038         (match_operand:BLK 1 "memory_operand" ""))
3039    (use (match_operand 2 "register_operand" ""))
3040    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3041    (clobber (scratch))]
3042   "TARGET_Z10 && reload_completed"
3043   [(parallel
3044     [(unspec [(match_dup 2) (const_int 0)
3045               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3046      (set (match_dup 0) (match_dup 1))
3047      (use (const_int 1))])]
3048   "operands[3] = gen_label_rtx ();")
3049
3050 (define_split
3051   [(set (match_operand:BLK 0 "memory_operand" "")
3052         (match_operand:BLK 1 "memory_operand" ""))
3053    (use (match_operand 2 "register_operand" ""))
3054    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3055    (clobber (match_operand 3 "register_operand" ""))]
3056   "reload_completed && TARGET_CPU_ZARCH"
3057   [(set (match_dup 3) (label_ref (match_dup 4)))
3058    (parallel
3059     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3060               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3061      (set (match_dup 0) (match_dup 1))
3062      (use (const_int 1))])]
3063   "operands[4] = gen_label_rtx ();")
3064
3065 ; Move a block of arbitrary length.
3066
3067 (define_expand "movmem_long"
3068   [(parallel
3069     [(clobber (match_dup 2))
3070      (clobber (match_dup 3))
3071      (set (match_operand:BLK 0 "memory_operand" "")
3072           (match_operand:BLK 1 "memory_operand" ""))
3073      (use (match_operand 2 "general_operand" ""))
3074      (use (match_dup 3))
3075      (clobber (reg:CC CC_REGNUM))])]
3076   ""
3077 {
3078   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3079   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3080   rtx reg0 = gen_reg_rtx (dreg_mode);
3081   rtx reg1 = gen_reg_rtx (dreg_mode);
3082   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3083   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3084   rtx len0 = gen_lowpart (Pmode, reg0);
3085   rtx len1 = gen_lowpart (Pmode, reg1);
3086
3087   emit_clobber (reg0);
3088   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3089   emit_move_insn (len0, operands[2]);
3090
3091   emit_clobber (reg1);
3092   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3093   emit_move_insn (len1, operands[2]);
3094
3095   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3096   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3097   operands[2] = reg0;
3098   operands[3] = reg1;
3099 })
3100
3101 (define_insn "*movmem_long"
3102   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3103    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3104    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3105         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3106    (use (match_dup 2))
3107    (use (match_dup 3))
3108    (clobber (reg:CC CC_REGNUM))]
3109   "TARGET_64BIT || !TARGET_ZARCH"
3110   "mvcle\t%0,%1,0\;jo\t.-4"
3111   [(set_attr "length" "8")
3112    (set_attr "type" "vs")])
3113
3114 (define_insn "*movmem_long_31z"
3115   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3116    (clobber (match_operand:TI 1 "register_operand" "=d"))
3117    (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3118         (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3119    (use (match_dup 2))
3120    (use (match_dup 3))
3121    (clobber (reg:CC CC_REGNUM))]
3122   "!TARGET_64BIT && TARGET_ZARCH"
3123   "mvcle\t%0,%1,0\;jo\t.-4"
3124   [(set_attr "length" "8")
3125    (set_attr "type" "vs")])
3126
3127
3128 ;
3129 ; Test data class.
3130 ;
3131
3132 (define_expand "signbit<mode>2"
3133   [(set (reg:CCZ CC_REGNUM)
3134         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3135                      (match_dup 2)]
3136                      UNSPEC_TDC_INSN))
3137    (set (match_operand:SI 0 "register_operand" "=d")
3138         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3139   "TARGET_HARD_FLOAT"
3140 {
3141   operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3142 })
3143
3144 (define_expand "isinf<mode>2"
3145   [(set (reg:CCZ CC_REGNUM)
3146         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3147                      (match_dup 2)]
3148                      UNSPEC_TDC_INSN))
3149    (set (match_operand:SI 0 "register_operand" "=d")
3150         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3151   "TARGET_HARD_FLOAT"
3152 {
3153   operands[2] = GEN_INT (S390_TDC_INFINITY);
3154 })
3155
3156 ; This extracts CC into a GPR properly shifted.  The actual IPM
3157 ; instruction will be issued by reload.  The constraint of operand 1
3158 ; forces reload to use a GPR.  So reload will issue a movcc insn for
3159 ; copying CC into a GPR first.
3160 (define_insn_and_split "*cc_to_int"
3161   [(set (match_operand:SI 0 "nonimmediate_operand"     "=d")
3162         (unspec:SI [(match_operand 1 "register_operand" "0")]
3163                    UNSPEC_CC_TO_INT))]
3164   "operands != NULL"
3165   "#"
3166   "reload_completed"
3167   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3168
3169 ; This insn is used to generate all variants of the Test Data Class
3170 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
3171 ; is the register to be tested and the second one is the bit mask
3172 ; specifying the required test(s).
3173 ;
3174 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3175 (define_insn "*TDC_insn_<mode>"
3176   [(set (reg:CCZ CC_REGNUM)
3177         (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3178                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3179   "TARGET_HARD_FLOAT"
3180   "t<_d>c<xde><bt>\t%0,%1"
3181    [(set_attr "op_type" "RXE")
3182     (set_attr "type"  "fsimp<mode>")])
3183
3184
3185
3186 ;
3187 ; setmemM instruction pattern(s).
3188 ;
3189
3190 (define_expand "setmem<mode>"
3191   [(set (match_operand:BLK 0 "memory_operand" "")
3192         (match_operand:QI 2 "general_operand" ""))
3193    (use (match_operand:GPR 1 "general_operand" ""))
3194    (match_operand 3 "" "")]
3195   ""
3196   "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3197
3198 ; Clear a block that is up to 256 bytes in length.
3199 ; The block length is taken as (operands[1] % 256) + 1.
3200
3201 (define_expand "clrmem_short"
3202   [(parallel
3203     [(set (match_operand:BLK 0 "memory_operand" "")
3204           (const_int 0))
3205      (use (match_operand 1 "nonmemory_operand" ""))
3206      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3207      (clobber (match_dup 2))
3208      (clobber (reg:CC CC_REGNUM))])]
3209   ""
3210   "operands[2] = gen_rtx_SCRATCH (Pmode);")
3211
3212 (define_insn "*clrmem_short"
3213   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3214         (const_int 0))
3215    (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3216    (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3217    (clobber (match_scratch:P 3 "=X,X,X,&a"))
3218    (clobber (reg:CC CC_REGNUM))]
3219   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3220   "#"
3221   [(set_attr "type" "cs")
3222    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3223
3224 (define_split
3225   [(set (match_operand:BLK 0 "memory_operand" "")
3226         (const_int 0))
3227    (use (match_operand 1 "const_int_operand" ""))
3228    (use (match_operand 2 "immediate_operand" ""))
3229    (clobber (scratch))
3230    (clobber (reg:CC CC_REGNUM))]
3231   "reload_completed"
3232   [(parallel
3233     [(set (match_dup 0) (const_int 0))
3234      (use (match_dup 1))
3235      (clobber (reg:CC CC_REGNUM))])]
3236   "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3237
3238 (define_split
3239   [(set (match_operand:BLK 0 "memory_operand" "")
3240         (const_int 0))
3241    (use (match_operand 1 "register_operand" ""))
3242    (use (match_operand 2 "memory_operand" ""))
3243    (clobber (scratch))
3244    (clobber (reg:CC CC_REGNUM))]
3245   "reload_completed"
3246   [(parallel
3247     [(unspec [(match_dup 1) (match_dup 2)
3248               (const_int 0)] UNSPEC_EXECUTE)
3249      (set (match_dup 0) (const_int 0))
3250      (use (const_int 1))
3251      (clobber (reg:CC CC_REGNUM))])]
3252   "")
3253
3254 (define_split
3255   [(set (match_operand:BLK 0 "memory_operand" "")
3256         (const_int 0))
3257    (use (match_operand 1 "register_operand" ""))
3258    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3259    (clobber (scratch))
3260    (clobber (reg:CC CC_REGNUM))]
3261   "TARGET_Z10 && reload_completed"
3262   [(parallel
3263     [(unspec [(match_dup 1) (const_int 0)
3264               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3265      (set (match_dup 0) (const_int 0))
3266      (use (const_int 1))
3267      (clobber (reg:CC CC_REGNUM))])]
3268   "operands[3] = gen_label_rtx ();")
3269
3270 (define_split
3271   [(set (match_operand:BLK 0 "memory_operand" "")
3272         (const_int 0))
3273    (use (match_operand 1 "register_operand" ""))
3274    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3275    (clobber (match_operand 2 "register_operand" ""))
3276    (clobber (reg:CC CC_REGNUM))]
3277   "reload_completed && TARGET_CPU_ZARCH"
3278   [(set (match_dup 2) (label_ref (match_dup 3)))
3279    (parallel
3280     [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3281               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3282      (set (match_dup 0) (const_int 0))
3283      (use (const_int 1))
3284      (clobber (reg:CC CC_REGNUM))])]
3285   "operands[3] = gen_label_rtx ();")
3286
3287 ; Initialize a block of arbitrary length with (operands[2] % 256).
3288
3289 (define_expand "setmem_long_<P:mode>"
3290   [(parallel
3291     [(clobber (match_dup 1))
3292      (set (match_operand:BLK 0 "memory_operand" "")
3293           (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "")
3294                       (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3295      (use (match_dup 3))
3296      (clobber (reg:CC CC_REGNUM))])]
3297   ""
3298 {
3299   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3300   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3301   rtx reg0 = gen_reg_rtx (dreg_mode);
3302   rtx reg1 = gen_reg_rtx (dreg_mode);
3303   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3304   rtx len0 = gen_lowpart (Pmode, reg0);
3305
3306   emit_clobber (reg0);
3307   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3308   emit_move_insn (len0, operands[1]);
3309
3310   emit_move_insn (reg1, const0_rtx);
3311
3312   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3313   operands[1] = reg0;
3314   operands[3] = reg1;
3315   operands[4] = gen_lowpart (Pmode, operands[1]);
3316 })
3317
3318 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3319
3320 (define_insn "*setmem_long"
3321   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3322    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3323         (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y")
3324                      (subreg:P (match_dup 3) <modesize>)]
3325                      UNSPEC_REPLICATE_BYTE))
3326    (use (match_operand:<DBL> 1 "register_operand" "d"))
3327    (clobber (reg:CC CC_REGNUM))]
3328   "TARGET_64BIT || !TARGET_ZARCH"
3329   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3330   [(set_attr "length" "8")
3331    (set_attr "type" "vs")])
3332
3333 (define_insn "*setmem_long_and"
3334   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3335    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3336         (unspec:BLK [(and:P
3337                       (match_operand:P 2 "shift_count_or_setmem_operand" "Y")
3338                       (match_operand:P 4 "const_int_operand"             "n"))
3339                     (subreg:P (match_dup 3) <modesize>)]
3340                     UNSPEC_REPLICATE_BYTE))
3341    (use (match_operand:<DBL> 1 "register_operand" "d"))
3342    (clobber (reg:CC CC_REGNUM))]
3343   "(TARGET_64BIT || !TARGET_ZARCH) &&
3344    (INTVAL (operands[4]) & 255) == 255"
3345   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3346   [(set_attr "length" "8")
3347    (set_attr "type" "vs")])
3348
3349 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3350 ; of the SImode subregs.
3351
3352 (define_insn "*setmem_long_31z"
3353   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3354    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3355         (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
3356                      (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3357    (use (match_operand:TI 1 "register_operand" "d"))
3358    (clobber (reg:CC CC_REGNUM))]
3359   "!TARGET_64BIT && TARGET_ZARCH"
3360   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3361   [(set_attr "length" "8")
3362    (set_attr "type" "vs")])
3363
3364 (define_insn "*setmem_long_and_31z"
3365   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3366    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3367         (unspec:BLK [(and:SI
3368                       (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
3369                       (match_operand:SI 4 "const_int_operand"             "n"))
3370                     (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3371    (use (match_operand:TI 1 "register_operand" "d"))
3372    (clobber (reg:CC CC_REGNUM))]
3373   "(!TARGET_64BIT && TARGET_ZARCH) &&
3374    (INTVAL (operands[4]) & 255) == 255"
3375   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3376   [(set_attr "length" "8")
3377    (set_attr "type" "vs")])
3378
3379 ;
3380 ; cmpmemM instruction pattern(s).
3381 ;
3382
3383 (define_expand "cmpmemsi"
3384   [(set (match_operand:SI 0 "register_operand" "")
3385         (compare:SI (match_operand:BLK 1 "memory_operand" "")
3386                     (match_operand:BLK 2 "memory_operand" "") ) )
3387    (use (match_operand:SI 3 "general_operand" ""))
3388    (use (match_operand:SI 4 "" ""))]
3389   ""
3390 {
3391   if (s390_expand_cmpmem (operands[0], operands[1],
3392                           operands[2], operands[3]))
3393     DONE;
3394   else
3395     FAIL;
3396 })
3397
3398 ; Compare a block that is up to 256 bytes in length.
3399 ; The block length is taken as (operands[2] % 256) + 1.
3400
3401 (define_expand "cmpmem_short"
3402   [(parallel
3403     [(set (reg:CCU CC_REGNUM)
3404           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3405                        (match_operand:BLK 1 "memory_operand" "")))
3406      (use (match_operand 2 "nonmemory_operand" ""))
3407      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3408      (clobber (match_dup 3))])]
3409   ""
3410   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3411
3412 (define_insn "*cmpmem_short"
3413   [(set (reg:CCU CC_REGNUM)
3414         (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3415                      (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3416    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3417    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3418    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3419   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3420   "#"
3421   [(set_attr "type" "cs")
3422    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3423
3424 (define_split
3425   [(set (reg:CCU CC_REGNUM)
3426         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3427                      (match_operand:BLK 1 "memory_operand" "")))
3428    (use (match_operand 2 "const_int_operand" ""))
3429    (use (match_operand 3 "immediate_operand" ""))
3430    (clobber (scratch))]
3431   "reload_completed"
3432   [(parallel
3433     [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3434      (use (match_dup 2))])]
3435   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3436
3437 (define_split
3438   [(set (reg:CCU CC_REGNUM)
3439         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3440                      (match_operand:BLK 1 "memory_operand" "")))
3441    (use (match_operand 2 "register_operand" ""))
3442    (use (match_operand 3 "memory_operand" ""))
3443    (clobber (scratch))]
3444   "reload_completed"
3445   [(parallel
3446     [(unspec [(match_dup 2) (match_dup 3)
3447               (const_int 0)] UNSPEC_EXECUTE)
3448      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3449      (use (const_int 1))])]
3450   "")
3451
3452 (define_split
3453   [(set (reg:CCU CC_REGNUM)
3454         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3455                      (match_operand:BLK 1 "memory_operand" "")))
3456    (use (match_operand 2 "register_operand" ""))
3457    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3458    (clobber (scratch))]
3459   "TARGET_Z10 && reload_completed"
3460   [(parallel
3461     [(unspec [(match_dup 2) (const_int 0)
3462               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3463      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3464      (use (const_int 1))])]
3465   "operands[4] = gen_label_rtx ();")
3466
3467 (define_split
3468   [(set (reg:CCU CC_REGNUM)
3469         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3470                      (match_operand:BLK 1 "memory_operand" "")))
3471    (use (match_operand 2 "register_operand" ""))
3472    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3473    (clobber (match_operand 3 "register_operand" ""))]
3474   "reload_completed && TARGET_CPU_ZARCH"
3475   [(set (match_dup 3) (label_ref (match_dup 4)))
3476    (parallel
3477     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3478               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3479      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3480      (use (const_int 1))])]
3481   "operands[4] = gen_label_rtx ();")
3482
3483 ; Compare a block of arbitrary length.
3484
3485 (define_expand "cmpmem_long"
3486   [(parallel
3487     [(clobber (match_dup 2))
3488      (clobber (match_dup 3))
3489      (set (reg:CCU CC_REGNUM)
3490           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3491                        (match_operand:BLK 1 "memory_operand" "")))
3492      (use (match_operand 2 "general_operand" ""))
3493      (use (match_dup 3))])]
3494   ""
3495 {
3496   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3497   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3498   rtx reg0 = gen_reg_rtx (dreg_mode);
3499   rtx reg1 = gen_reg_rtx (dreg_mode);
3500   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3501   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3502   rtx len0 = gen_lowpart (Pmode, reg0);
3503   rtx len1 = gen_lowpart (Pmode, reg1);
3504
3505   emit_clobber (reg0);
3506   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3507   emit_move_insn (len0, operands[2]);
3508
3509   emit_clobber (reg1);
3510   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3511   emit_move_insn (len1, operands[2]);
3512
3513   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3514   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3515   operands[2] = reg0;
3516   operands[3] = reg1;
3517 })
3518
3519 (define_insn "*cmpmem_long"
3520   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3521    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3522    (set (reg:CCU CC_REGNUM)
3523         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3524                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3525    (use (match_dup 2))
3526    (use (match_dup 3))]
3527   "TARGET_64BIT || !TARGET_ZARCH"
3528   "clcle\t%0,%1,0\;jo\t.-4"
3529   [(set_attr "length" "8")
3530    (set_attr "type" "vs")])
3531
3532 (define_insn "*cmpmem_long_31z"
3533   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3534    (clobber (match_operand:TI 1 "register_operand" "=d"))
3535    (set (reg:CCU CC_REGNUM)
3536         (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3537                      (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3538    (use (match_dup 2))
3539    (use (match_dup 3))]
3540   "!TARGET_64BIT && TARGET_ZARCH"
3541   "clcle\t%0,%1,0\;jo\t.-4"
3542   [(set_attr "op_type" "NN")
3543    (set_attr "type"    "vs")
3544    (set_attr "length"  "8")])
3545
3546 ; Convert CCUmode condition code to integer.
3547 ; Result is zero if EQ, positive if LTU, negative if GTU.
3548
3549 (define_insn_and_split "cmpint"
3550   [(set (match_operand:SI 0 "register_operand" "=d")
3551         (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3552                    UNSPEC_STRCMPCC_TO_INT))
3553    (clobber (reg:CC CC_REGNUM))]
3554   ""
3555   "#"
3556   "reload_completed"
3557   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3558    (parallel
3559     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3560      (clobber (reg:CC CC_REGNUM))])])
3561
3562 (define_insn_and_split "*cmpint_cc"
3563   [(set (reg CC_REGNUM)
3564         (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3565                             UNSPEC_STRCMPCC_TO_INT)
3566                  (const_int 0)))
3567    (set (match_operand:SI 0 "register_operand" "=d")
3568         (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3569   "s390_match_ccmode (insn, CCSmode)"
3570   "#"
3571   "&& reload_completed"
3572   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3573    (parallel
3574     [(set (match_dup 2) (match_dup 3))
3575      (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3576 {
3577   rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3578   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3579   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3580 })
3581
3582 (define_insn_and_split "*cmpint_sign"
3583   [(set (match_operand:DI 0 "register_operand" "=d")
3584         (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3585                                    UNSPEC_STRCMPCC_TO_INT)))
3586    (clobber (reg:CC CC_REGNUM))]
3587   "TARGET_ZARCH"
3588   "#"
3589   "&& reload_completed"
3590   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3591    (parallel
3592     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3593      (clobber (reg:CC CC_REGNUM))])])
3594
3595 (define_insn_and_split "*cmpint_sign_cc"
3596   [(set (reg CC_REGNUM)
3597         (compare (ashiftrt:DI (ashift:DI (subreg:DI
3598                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3599                               UNSPEC_STRCMPCC_TO_INT) 0)
3600                    (const_int 32)) (const_int 32))
3601                  (const_int 0)))
3602    (set (match_operand:DI 0 "register_operand" "=d")
3603         (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3604   "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3605   "#"
3606   "&& reload_completed"
3607   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3608    (parallel
3609     [(set (match_dup 2) (match_dup 3))
3610      (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3611 {
3612   rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3613   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3614   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3615 })
3616
3617
3618 ;;
3619 ;;- Conversion instructions.
3620 ;;
3621
3622 (define_insn "*sethighpartsi"
3623   [(set (match_operand:SI 0 "register_operand" "=d,d")
3624         (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3625                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3626    (clobber (reg:CC CC_REGNUM))]
3627   ""
3628   "@
3629    icm\t%0,%2,%S1
3630    icmy\t%0,%2,%S1"
3631   [(set_attr "op_type" "RS,RSY")
3632    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3633
3634 (define_insn "*sethighpartdi_64"
3635   [(set (match_operand:DI 0 "register_operand" "=d")
3636         (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3637                     (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3638    (clobber (reg:CC CC_REGNUM))]
3639   "TARGET_ZARCH"
3640   "icmh\t%0,%2,%S1"
3641   [(set_attr "op_type" "RSY")
3642    (set_attr "z10prop" "z10_super")])
3643
3644 (define_insn "*sethighpartdi_31"
3645   [(set (match_operand:DI 0 "register_operand" "=d,d")
3646         (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3647                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3648    (clobber (reg:CC CC_REGNUM))]
3649   "!TARGET_ZARCH"
3650   "@
3651    icm\t%0,%2,%S1
3652    icmy\t%0,%2,%S1"
3653   [(set_attr "op_type" "RS,RSY")
3654    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3655
3656 ;
3657 ; extv instruction patterns
3658 ;
3659
3660 ; FIXME: This expander needs to be converted from DI to GPR as well
3661 ; after resolving some issues with it.
3662
3663 (define_expand "extzv"
3664   [(parallel
3665     [(set (match_operand:DI 0 "register_operand" "=d")
3666         (zero_extract:DI
3667          (match_operand:DI 1 "register_operand" "d")
3668          (match_operand 2 "const_int_operand" "")   ; size
3669          (match_operand 3 "const_int_operand" ""))) ; start
3670      (clobber (reg:CC CC_REGNUM))])]
3671   "TARGET_Z10"
3672 {
3673   /* Starting with zEC12 there is risbgn not clobbering CC.  */
3674   if (TARGET_ZEC12)
3675     {
3676       emit_move_insn (operands[0],
3677                     gen_rtx_ZERO_EXTRACT (DImode,
3678                                           operands[1],
3679                                           operands[2],
3680                                           operands[3]));
3681       DONE;
3682     }
3683 })
3684
3685 (define_insn "*extzv<mode>_zEC12"
3686   [(set (match_operand:GPR 0 "register_operand" "=d")
3687       (zero_extract:GPR
3688         (match_operand:GPR 1 "register_operand" "d")
3689         (match_operand 2 "const_int_operand" "")   ; size
3690         (match_operand 3 "const_int_operand" "")))] ; start]
3691   "TARGET_ZEC12"
3692   "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3693   [(set_attr "op_type" "RIE")])
3694
3695 (define_insn "*extzv<mode>_z10"
3696   [(set (match_operand:GPR 0 "register_operand" "=d")
3697       (zero_extract:GPR
3698        (match_operand:GPR 1 "register_operand" "d")
3699        (match_operand 2 "const_int_operand" "")   ; size
3700        (match_operand 3 "const_int_operand" ""))) ; start
3701    (clobber (reg:CC CC_REGNUM))]
3702   "TARGET_Z10"
3703   "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3704   [(set_attr "op_type" "RIE")
3705    (set_attr "z10prop" "z10_super_E1")])
3706
3707 (define_insn_and_split "*pre_z10_extzv<mode>"
3708   [(set (match_operand:GPR 0 "register_operand" "=d")
3709         (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3710                           (match_operand 2 "nonzero_shift_count_operand" "")
3711                           (const_int 0)))
3712    (clobber (reg:CC CC_REGNUM))]
3713   "!TARGET_Z10"
3714   "#"
3715   "&& reload_completed"
3716   [(parallel
3717     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3718      (clobber (reg:CC CC_REGNUM))])
3719    (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3720 {
3721   int bitsize = INTVAL (operands[2]);
3722   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3723   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3724
3725   operands[1] = adjust_address (operands[1], BLKmode, 0);
3726   set_mem_size (operands[1], size);
3727   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3728   operands[3] = GEN_INT (mask);
3729 })
3730
3731 (define_insn_and_split "*pre_z10_extv<mode>"
3732   [(set (match_operand:GPR 0 "register_operand" "=d")
3733         (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3734                           (match_operand 2 "nonzero_shift_count_operand" "")
3735                           (const_int 0)))
3736    (clobber (reg:CC CC_REGNUM))]
3737   ""
3738   "#"
3739   "&& reload_completed"
3740   [(parallel
3741     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3742      (clobber (reg:CC CC_REGNUM))])
3743    (parallel
3744     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3745      (clobber (reg:CC CC_REGNUM))])]
3746 {
3747   int bitsize = INTVAL (operands[2]);
3748   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3749   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3750
3751   operands[1] = adjust_address (operands[1], BLKmode, 0);
3752   set_mem_size (operands[1], size);
3753   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3754   operands[3] = GEN_INT (mask);
3755 })
3756
3757 ;
3758 ; insv instruction patterns
3759 ;
3760
3761 (define_expand "insv"
3762   [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3763                       (match_operand 1 "const_int_operand" "")
3764                       (match_operand 2 "const_int_operand" ""))
3765         (match_operand 3 "general_operand" ""))]
3766   ""
3767 {
3768   if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3769     DONE;
3770   FAIL;
3771 })
3772
3773
3774 ; The normal RTL expansion will never generate a zero_extract where
3775 ; the location operand isn't word mode.  However, we do this in the
3776 ; back-end when generating atomic operations. See s390_two_part_insv.
3777 (define_insn "*insv<mode>_zEC12"
3778   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3779                           (match_operand 1 "const_int_operand"    "I")  ; size
3780                           (match_operand 2 "const_int_operand"    "I")) ; pos
3781         (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3782   "TARGET_ZEC12
3783    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3784   "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3785   [(set_attr "op_type" "RIE")])
3786
3787 (define_insn "*insv<mode>_z10"
3788   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3789                           (match_operand 1 "const_int_operand"    "I")  ; size
3790                           (match_operand 2 "const_int_operand"    "I")) ; pos
3791         (match_operand:GPR 3 "nonimmediate_operand" "d"))
3792    (clobber (reg:CC CC_REGNUM))]
3793   "TARGET_Z10
3794    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3795   "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3796   [(set_attr "op_type" "RIE")
3797    (set_attr "z10prop" "z10_super_E1")])
3798
3799 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3800 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3801 (define_insn "*insv<mode>_zEC12_noshift"
3802   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3803         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3804                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3805                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3806                           (match_operand:GPR 4 "const_int_operand" ""))))]
3807   "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3808   "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3809   [(set_attr "op_type" "RIE")])
3810
3811 (define_insn "*insv<mode>_z10_noshift"
3812   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3813         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3814                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3815                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3816                           (match_operand:GPR 4 "const_int_operand" ""))))
3817    (clobber (reg:CC CC_REGNUM))]
3818   "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3819   "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3820   [(set_attr "op_type" "RIE")
3821    (set_attr "z10prop" "z10_super_E1")])
3822
3823 ; Implement appending Y on the left of S bits of X
3824 ; x = (y << s) | (x & ((1 << s) - 1))
3825 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3826   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3827         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3828                           (match_operand:GPR 2 "immediate_operand" ""))
3829                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3830                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3831   "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3832   "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3833   [(set_attr "op_type" "RIE")
3834    (set_attr "z10prop" "z10_super_E1")])
3835
3836 (define_insn "*insv<mode>_z10_appendbitsleft"
3837   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3838         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3839                           (match_operand:GPR 2 "immediate_operand" ""))
3840                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3841                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3842    (clobber (reg:CC CC_REGNUM))]
3843   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3844   "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3845   [(set_attr "op_type" "RIE")
3846    (set_attr "z10prop" "z10_super_E1")])
3847
3848 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3849 ;  -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3850 ;  -> z = y >> d; z = risbg;
3851
3852 (define_split
3853   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3854         (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3855                                (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3856                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3857                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3858   "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3859   [(set (match_dup 0)
3860         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3861    (set (match_dup 0)
3862         (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3863                  (ashift:GPR (match_dup 3) (match_dup 4))))]
3864 {
3865   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3866 })
3867
3868 (define_split
3869   [(parallel
3870     [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3871           (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3872                                  (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3873                    (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3874                                (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3875      (clobber (reg:CC CC_REGNUM))])]
3876   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3877   [(set (match_dup 0)
3878         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3879    (parallel
3880     [(set (match_dup 0)
3881           (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
3882                    (ashift:GPR (match_dup 3) (match_dup 4))))
3883      (clobber (reg:CC CC_REGNUM))])]
3884 {
3885   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3886 })
3887
3888 (define_insn "*r<noxa>sbg_<mode>_noshift"
3889   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3890         (IXOR:GPR
3891           (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3892                    (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3893           (match_operand:GPR 3 "nonimmediate_operand" "0")))
3894    (clobber (reg:CC CC_REGNUM))]
3895   "TARGET_Z10"
3896   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3897   [(set_attr "op_type" "RIE")])
3898
3899 (define_insn "*r<noxa>sbg_di_rotl"
3900   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3901         (IXOR:DI
3902           (and:DI
3903             (rotate:DI
3904               (match_operand:DI 1 "nonimmediate_operand" "d")
3905               (match_operand:DI 3 "const_int_operand" ""))
3906             (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3907           (match_operand:DI 4 "nonimmediate_operand" "0")))
3908    (clobber (reg:CC CC_REGNUM))]
3909   "TARGET_Z10"
3910   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3911   [(set_attr "op_type" "RIE")])
3912
3913 (define_insn "*r<noxa>sbg_<mode>_srl"
3914   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3915         (IXOR:GPR
3916           (and:GPR
3917             (lshiftrt:GPR
3918               (match_operand:GPR 1 "nonimmediate_operand" "d")
3919               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3920             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3921           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3922    (clobber (reg:CC CC_REGNUM))]
3923   "TARGET_Z10
3924    && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3925                            INTVAL (operands[2]))"
3926   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3927   [(set_attr "op_type" "RIE")])
3928
3929 (define_insn "*r<noxa>sbg_<mode>_sll"
3930   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3931         (IXOR:GPR
3932           (and:GPR
3933             (ashift:GPR
3934               (match_operand:GPR 1 "nonimmediate_operand" "d")
3935               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3936             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3937           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3938    (clobber (reg:CC CC_REGNUM))]
3939   "TARGET_Z10
3940    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3941                            INTVAL (operands[2]))"
3942   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3943   [(set_attr "op_type" "RIE")])
3944
3945 ;; These two are generated by combine for s.bf &= val.
3946 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3947 ;; shifts and ands, which results in some truly awful patterns
3948 ;; including subregs of operations.  Rather unnecessisarily, IMO.
3949 ;; Instead of
3950 ;;
3951 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3952 ;;        (const_int 24 [0x18])
3953 ;;        (const_int 0 [0]))
3954 ;;    (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3955 ;;                    (const_int 40 [0x28])) 4)
3956 ;;            (reg:SI 4 %r4 [ y+4 ])) 0))
3957 ;;
3958 ;; we should instead generate
3959 ;;
3960 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3961 ;;        (const_int 24 [0x18])
3962 ;;        (const_int 0 [0]))
3963 ;;    (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3964 ;;                    (const_int 40 [0x28]))
3965 ;;            (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3966 ;;
3967 ;; by noticing that we can push down the outer paradoxical subreg
3968 ;; into the operation.
3969
3970 (define_insn "*insv_rnsbg_noshift"
3971   [(set (zero_extract:DI
3972           (match_operand:DI 0 "nonimmediate_operand" "+d")
3973           (match_operand 1 "const_int_operand" "")
3974           (match_operand 2 "const_int_operand" ""))
3975         (and:DI
3976           (match_dup 0)
3977           (match_operand:DI 3 "nonimmediate_operand" "d")))
3978    (clobber (reg:CC CC_REGNUM))]
3979   "TARGET_Z10
3980    && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3981   "rnsbg\t%0,%3,%2,63,0"
3982   [(set_attr "op_type" "RIE")])
3983
3984 (define_insn "*insv_rnsbg_srl"
3985   [(set (zero_extract:DI
3986           (match_operand:DI 0 "nonimmediate_operand" "+d")
3987           (match_operand 1 "const_int_operand" "")
3988           (match_operand 2 "const_int_operand" ""))
3989         (and:DI
3990           (lshiftrt:DI
3991             (match_dup 0)
3992             (match_operand 3 "const_int_operand" ""))
3993           (match_operand:DI 4 "nonimmediate_operand" "d")))
3994    (clobber (reg:CC CC_REGNUM))]
3995   "TARGET_Z10
3996    && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3997   "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3998   [(set_attr "op_type" "RIE")])
3999
4000 (define_insn "*insv<mode>_mem_reg"
4001   [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4002                         (match_operand 1 "const_int_operand" "n,n")
4003                         (const_int 0))
4004         (match_operand:W 2 "register_operand" "d,d"))]
4005   "INTVAL (operands[1]) > 0
4006    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4007    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4008 {
4009     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4010
4011     operands[1] = GEN_INT ((1ul << size) - 1);
4012     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4013                                     : "stcmy\t%2,%1,%S0";
4014 }
4015   [(set_attr "op_type" "RS,RSY")
4016    (set_attr "z10prop" "z10_super,z10_super")])
4017
4018 (define_insn "*insvdi_mem_reghigh"
4019   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
4020                          (match_operand 1 "const_int_operand" "n")
4021                          (const_int 0))
4022         (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4023                      (const_int 32)))]
4024   "TARGET_ZARCH
4025    && INTVAL (operands[1]) > 0
4026    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4027    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4028 {
4029     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4030
4031     operands[1] = GEN_INT ((1ul << size) - 1);
4032     return "stcmh\t%2,%1,%S0";
4033 }
4034 [(set_attr "op_type" "RSY")
4035  (set_attr "z10prop" "z10_super")])
4036
4037 (define_insn "*insvdi_reg_imm"
4038   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4039                          (const_int 16)
4040                          (match_operand 1 "const_int_operand" "n"))
4041         (match_operand:DI 2 "const_int_operand" "n"))]
4042   "TARGET_ZARCH
4043    && INTVAL (operands[1]) >= 0
4044    && INTVAL (operands[1]) < BITS_PER_WORD
4045    && INTVAL (operands[1]) % 16 == 0"
4046 {
4047   switch (BITS_PER_WORD - INTVAL (operands[1]))
4048     {
4049       case 64: return "iihh\t%0,%x2"; break;
4050       case 48: return "iihl\t%0,%x2"; break;
4051       case 32: return "iilh\t%0,%x2"; break;
4052       case 16: return "iill\t%0,%x2"; break;
4053       default: gcc_unreachable();
4054     }
4055 }
4056   [(set_attr "op_type" "RI")
4057    (set_attr "z10prop" "z10_super_E1")])
4058
4059 ; Update the left-most 32 bit of a DI.
4060 (define_insn "*insv_h_di_reg_extimm"
4061   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4062                          (const_int 32)
4063                          (const_int 0))
4064         (match_operand:DI 1 "const_int_operand" "n"))]
4065   "TARGET_EXTIMM"
4066   "iihf\t%0,%o1"
4067   [(set_attr "op_type" "RIL")
4068    (set_attr "z10prop" "z10_fwd_E1")])
4069
4070 ; Update the right-most 32 bit of a DI.
4071 (define_insn "*insv_l_di_reg_extimm"
4072   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4073                          (const_int 32)
4074                          (const_int 32))
4075         (match_operand:DI 1 "const_int_operand" "n"))]
4076   "TARGET_EXTIMM"
4077   "iilf\t%0,%o1"
4078   [(set_attr "op_type" "RIL")
4079    (set_attr "z10prop" "z10_fwd_A1")])
4080
4081 ;
4082 ; extendsidi2 instruction pattern(s).
4083 ;
4084
4085 (define_expand "extendsidi2"
4086   [(set (match_operand:DI 0 "register_operand" "")
4087         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4088   ""
4089 {
4090   if (!TARGET_ZARCH)
4091     {
4092       emit_clobber (operands[0]);
4093       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4094       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4095       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4096       DONE;
4097     }
4098 })
4099
4100 (define_insn "*extendsidi2"
4101   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4102         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4103   "TARGET_ZARCH"
4104   "@
4105    lgfr\t%0,%1
4106    lgf\t%0,%1
4107    lgfrl\t%0,%1"
4108   [(set_attr "op_type"      "RRE,RXY,RIL")
4109    (set_attr "type"         "*,*,larl")
4110    (set_attr "cpu_facility" "*,*,z10")
4111    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4112
4113 ;
4114 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4115 ;
4116
4117 (define_expand "extend<HQI:mode><DSI:mode>2"
4118   [(set (match_operand:DSI 0 "register_operand" "")
4119         (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4120   ""
4121 {
4122   if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4123     {
4124       rtx tmp = gen_reg_rtx (SImode);
4125       emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4126       emit_insn (gen_extendsidi2 (operands[0], tmp));
4127       DONE;
4128     }
4129   else if (!TARGET_EXTIMM)
4130     {
4131       rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4132
4133       operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4134       emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4135       emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4136       DONE;
4137     }
4138 })
4139
4140 ;
4141 ; extendhidi2 instruction pattern(s).
4142 ;
4143
4144 (define_insn "*extendhidi2_extimm"
4145   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4146         (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
4147   "TARGET_ZARCH && TARGET_EXTIMM"
4148   "@
4149    lghr\t%0,%1
4150    lgh\t%0,%1
4151    lghrl\t%0,%1"
4152   [(set_attr "op_type"      "RRE,RXY,RIL")
4153    (set_attr "type"         "*,*,larl")
4154    (set_attr "cpu_facility" "extimm,extimm,z10")
4155    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4156
4157 (define_insn "*extendhidi2"
4158   [(set (match_operand:DI 0 "register_operand" "=d")
4159         (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
4160   "TARGET_ZARCH"
4161   "lgh\t%0,%1"
4162   [(set_attr "op_type" "RXY")
4163    (set_attr "z10prop" "z10_super_E1")])
4164
4165 ;
4166 ; extendhisi2 instruction pattern(s).
4167 ;
4168
4169 (define_insn "*extendhisi2_extimm"
4170   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4171         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4172   "TARGET_EXTIMM"
4173   "@
4174    lhr\t%0,%1
4175    lh\t%0,%1
4176    lhy\t%0,%1
4177    lhrl\t%0,%1"
4178   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
4179    (set_attr "type"         "*,*,*,larl")
4180    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4181    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4182
4183 (define_insn "*extendhisi2"
4184   [(set (match_operand:SI 0 "register_operand" "=d,d")
4185         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4186   "!TARGET_EXTIMM"
4187   "@
4188    lh\t%0,%1
4189    lhy\t%0,%1"
4190   [(set_attr "op_type" "RX,RXY")
4191    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4192
4193 ;
4194 ; extendqi(si|di)2 instruction pattern(s).
4195 ;
4196
4197 ; lbr, lgbr, lb, lgb
4198 (define_insn "*extendqi<mode>2_extimm"
4199   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4200         (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
4201   "TARGET_EXTIMM"
4202   "@
4203    l<g>br\t%0,%1
4204    l<g>b\t%0,%1"
4205   [(set_attr "op_type" "RRE,RXY")
4206    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4207
4208 ; lb, lgb
4209 (define_insn "*extendqi<mode>2"
4210   [(set (match_operand:GPR 0 "register_operand" "=d")
4211         (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
4212   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4213   "l<g>b\t%0,%1"
4214   [(set_attr "op_type" "RXY")
4215    (set_attr "z10prop" "z10_super_E1")])
4216
4217 (define_insn_and_split "*extendqi<mode>2_short_displ"
4218   [(set (match_operand:GPR 0 "register_operand" "=d")
4219         (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4220    (clobber (reg:CC CC_REGNUM))]
4221   "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4222   "#"
4223   "&& reload_completed"
4224   [(parallel
4225     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4226      (clobber (reg:CC CC_REGNUM))])
4227    (parallel
4228     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4229      (clobber (reg:CC CC_REGNUM))])]
4230 {
4231   operands[1] = adjust_address (operands[1], BLKmode, 0);
4232   set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4233   operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4234 })
4235
4236 ;
4237 ; zero_extendsidi2 instruction pattern(s).
4238 ;
4239
4240 (define_expand "zero_extendsidi2"
4241   [(set (match_operand:DI 0 "register_operand" "")
4242         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4243   ""
4244 {
4245   if (!TARGET_ZARCH)
4246     {
4247       emit_clobber (operands[0]);
4248       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4249       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4250       DONE;
4251     }
4252 })
4253
4254 (define_insn "*zero_extendsidi2"
4255   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4256         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4257   "TARGET_ZARCH"
4258   "@
4259    llgfr\t%0,%1
4260    llgf\t%0,%1
4261    llgfrl\t%0,%1"
4262   [(set_attr "op_type"      "RRE,RXY,RIL")
4263    (set_attr "type"         "*,*,larl")
4264    (set_attr "cpu_facility" "*,*,z10")
4265    (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4266
4267 ;
4268 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4269 ;
4270
4271 (define_insn "*llgt_sidi"
4272   [(set (match_operand:DI 0 "register_operand" "=d")
4273         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4274                 (const_int 2147483647)))]
4275   "TARGET_ZARCH"
4276   "llgt\t%0,%1"
4277   [(set_attr "op_type"  "RXE")
4278    (set_attr "z10prop" "z10_super_E1")])
4279
4280 (define_insn_and_split "*llgt_sidi_split"
4281   [(set (match_operand:DI 0 "register_operand" "=d")
4282         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4283                 (const_int 2147483647)))
4284    (clobber (reg:CC CC_REGNUM))]
4285   "TARGET_ZARCH"
4286   "#"
4287   "&& reload_completed"
4288   [(set (match_dup 0)
4289         (and:DI (subreg:DI (match_dup 1) 0)
4290                 (const_int 2147483647)))]
4291   "")
4292
4293 (define_insn "*llgt_sisi"
4294   [(set (match_operand:SI 0 "register_operand" "=d,d")
4295         (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4296                 (const_int 2147483647)))]
4297   "TARGET_ZARCH"
4298   "@
4299    llgtr\t%0,%1
4300    llgt\t%0,%1"
4301   [(set_attr "op_type"  "RRE,RXE")
4302    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4303
4304 (define_insn "*llgt_didi"
4305   [(set (match_operand:DI 0 "register_operand" "=d,d")
4306         (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4307                 (const_int 2147483647)))]
4308   "TARGET_ZARCH"
4309   "@
4310    llgtr\t%0,%1
4311    llgt\t%0,%N1"
4312   [(set_attr "op_type"  "RRE,RXE")
4313    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4314
4315 (define_split
4316   [(set (match_operand:DSI 0 "register_operand" "")
4317         (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4318                  (const_int 2147483647)))
4319    (clobber (reg:CC CC_REGNUM))]
4320   "TARGET_ZARCH && reload_completed"
4321   [(set (match_dup 0)
4322         (and:DSI (match_dup 1)
4323                  (const_int 2147483647)))]
4324   "")
4325
4326 ;
4327 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4328 ;
4329
4330 (define_expand "zero_extend<mode>di2"
4331   [(set (match_operand:DI 0 "register_operand" "")
4332         (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4333   ""
4334 {
4335   if (!TARGET_ZARCH)
4336     {
4337       rtx tmp = gen_reg_rtx (SImode);
4338       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4339       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4340       DONE;
4341     }
4342   else if (!TARGET_EXTIMM)
4343     {
4344       rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4345       operands[1] = gen_lowpart (DImode, operands[1]);
4346       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4347       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4348       DONE;
4349     }
4350 })
4351
4352 (define_expand "zero_extend<mode>si2"
4353   [(set (match_operand:SI 0 "register_operand" "")
4354         (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4355   ""
4356 {
4357   if (!TARGET_EXTIMM)
4358     {
4359       operands[1] = gen_lowpart (SImode, operands[1]);
4360       emit_insn (gen_andsi3 (operands[0], operands[1],
4361                              GEN_INT ((1 << <HQI:bitsize>) - 1)));
4362       DONE;
4363     }
4364 })
4365
4366 ; llhrl, llghrl
4367 (define_insn "*zero_extendhi<mode>2_z10"
4368   [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4369         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4370   "TARGET_Z10"
4371   "@
4372    ll<g>hr\t%0,%1
4373    ll<g>h\t%0,%1
4374    ll<g>hrl\t%0,%1"
4375   [(set_attr "op_type"      "RXY,RRE,RIL")
4376    (set_attr "type"         "*,*,larl")
4377    (set_attr "cpu_facility" "*,*,z10")
4378    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4379
4380 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4381 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4382   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4383         (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4384   "TARGET_EXTIMM"
4385   "@
4386    ll<g><hc>r\t%0,%1
4387    ll<g><hc>\t%0,%1"
4388   [(set_attr "op_type" "RRE,RXY")
4389    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4390
4391 ; llgh, llgc
4392 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4393   [(set (match_operand:GPR 0 "register_operand" "=d")
4394         (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4395   "TARGET_ZARCH && !TARGET_EXTIMM"
4396   "llg<hc>\t%0,%1"
4397   [(set_attr "op_type" "RXY")
4398    (set_attr "z10prop" "z10_fwd_A3")])
4399
4400 (define_insn_and_split "*zero_extendhisi2_31"
4401   [(set (match_operand:SI 0 "register_operand" "=&d")
4402         (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4403    (clobber (reg:CC CC_REGNUM))]
4404   "!TARGET_ZARCH"
4405   "#"
4406   "&& reload_completed"
4407   [(set (match_dup 0) (const_int 0))
4408    (parallel
4409     [(set (strict_low_part (match_dup 2)) (match_dup 1))
4410      (clobber (reg:CC CC_REGNUM))])]
4411   "operands[2] = gen_lowpart (HImode, operands[0]);")
4412
4413 (define_insn_and_split "*zero_extendqisi2_31"
4414   [(set (match_operand:SI 0 "register_operand" "=&d")
4415         (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4416   "!TARGET_ZARCH"
4417   "#"
4418   "&& reload_completed"
4419   [(set (match_dup 0) (const_int 0))
4420    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4421   "operands[2] = gen_lowpart (QImode, operands[0]);")
4422
4423 ;
4424 ; zero_extendqihi2 instruction pattern(s).
4425 ;
4426
4427 (define_expand "zero_extendqihi2"
4428   [(set (match_operand:HI 0 "register_operand" "")
4429         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4430   "TARGET_ZARCH && !TARGET_EXTIMM"
4431 {
4432   operands[1] = gen_lowpart (HImode, operands[1]);
4433   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4434   DONE;
4435 })
4436
4437 (define_insn "*zero_extendqihi2_64"
4438   [(set (match_operand:HI 0 "register_operand" "=d")
4439         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4440   "TARGET_ZARCH && !TARGET_EXTIMM"
4441   "llgc\t%0,%1"
4442   [(set_attr "op_type" "RXY")
4443    (set_attr "z10prop" "z10_fwd_A3")])
4444
4445 (define_insn_and_split "*zero_extendqihi2_31"
4446   [(set (match_operand:HI 0 "register_operand" "=&d")
4447         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4448   "!TARGET_ZARCH"
4449   "#"
4450   "&& reload_completed"
4451   [(set (match_dup 0) (const_int 0))
4452    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4453   "operands[2] = gen_lowpart (QImode, operands[0]);")
4454
4455 ;
4456 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4457 ;
4458
4459 (define_expand "fixuns_truncdddi2"
4460   [(parallel
4461     [(set (match_operand:DI 0 "register_operand" "")
4462           (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4463      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4464      (clobber (reg:CC CC_REGNUM))])]
4465
4466   "TARGET_HARD_DFP"
4467 {
4468   if (!TARGET_Z196)
4469     {
4470       rtx_code_label *label1 = gen_label_rtx ();
4471       rtx_code_label *label2 = gen_label_rtx ();
4472       rtx temp = gen_reg_rtx (TDmode);
4473       REAL_VALUE_TYPE cmp, sub;
4474
4475       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4476       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4477
4478       /* 2^63 can't be represented as 64bit DFP number with full precision.  The
4479          solution is doing the check and the subtraction in TD mode and using a
4480          TD -> DI convert afterwards.  */
4481       emit_insn (gen_extendddtd2 (temp, operands[1]));
4482       temp = force_reg (TDmode, temp);
4483       emit_cmp_and_jump_insns (temp,
4484             const_double_from_real_value (cmp, TDmode),
4485             LT, NULL_RTX, VOIDmode, 0, label1);
4486       emit_insn (gen_subtd3 (temp, temp,
4487             const_double_from_real_value (sub, TDmode)));
4488       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4489       emit_jump (label2);
4490
4491       emit_label (label1);
4492       emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4493       emit_label (label2);
4494       DONE;
4495     }
4496 })
4497
4498 (define_expand "fixuns_trunctddi2"
4499   [(parallel
4500     [(set (match_operand:DI 0 "register_operand" "")
4501           (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4502      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4503      (clobber (reg:CC CC_REGNUM))])]
4504
4505   "TARGET_HARD_DFP"
4506 {
4507   if (!TARGET_Z196)
4508     {
4509       rtx_code_label *label1 = gen_label_rtx ();
4510       rtx_code_label *label2 = gen_label_rtx ();
4511       rtx temp = gen_reg_rtx (TDmode);
4512       REAL_VALUE_TYPE cmp, sub;
4513
4514       operands[1] = force_reg (TDmode, operands[1]);
4515       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4516       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4517
4518       emit_cmp_and_jump_insns (operands[1],
4519             const_double_from_real_value (cmp, TDmode),
4520             LT, NULL_RTX, VOIDmode, 0, label1);
4521       emit_insn (gen_subtd3 (temp, operands[1],
4522             const_double_from_real_value (sub, TDmode)));
4523       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4524       emit_jump (label2);
4525
4526       emit_label (label1);
4527       emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4528       emit_label (label2);
4529       DONE;
4530     }
4531 })
4532
4533 ;
4534 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4535 ; instruction pattern(s).
4536 ;
4537
4538 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4539   [(parallel
4540     [(set (match_operand:GPR 0 "register_operand" "")
4541           (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4542      (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4543      (clobber (reg:CC CC_REGNUM))])]
4544   "TARGET_HARD_FLOAT"
4545 {
4546   if (!TARGET_Z196)
4547     {
4548       rtx_code_label *label1 = gen_label_rtx ();
4549       rtx_code_label *label2 = gen_label_rtx ();
4550       rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4551       REAL_VALUE_TYPE cmp, sub;
4552
4553       operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4554       real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4555       real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4556
4557       emit_cmp_and_jump_insns (operands[1],
4558             const_double_from_real_value (cmp, <BFP:MODE>mode),
4559             LT, NULL_RTX, VOIDmode, 0, label1);
4560       emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4561             const_double_from_real_value (sub, <BFP:MODE>mode)));
4562       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4563             GEN_INT (7)));
4564       emit_jump (label2);
4565
4566       emit_label (label1);
4567       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4568             operands[1], GEN_INT (5)));
4569       emit_label (label2);
4570       DONE;
4571     }
4572 })
4573
4574 ; fixuns_trunc(td|dd)si2 expander
4575 (define_expand "fixuns_trunc<mode>si2"
4576   [(parallel
4577     [(set (match_operand:SI 0 "register_operand" "")
4578           (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4579      (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4580      (clobber (reg:CC CC_REGNUM))])]
4581   "TARGET_Z196 && TARGET_HARD_DFP"
4582   "")
4583
4584 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4585
4586 (define_insn "*fixuns_truncdfdi2_z13"
4587   [(set (match_operand:DI                  0 "register_operand" "=d,v")
4588         (unsigned_fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4589    (unspec:DI [(match_operand:DI           2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4590    (clobber (reg:CC CC_REGNUM))]
4591    "TARGET_Z13 && TARGET_HARD_FLOAT"
4592    "@
4593     clgdbr\t%0,%h2,%1,0
4594     wclgdb\t%v0,%v1,0,%h2"
4595    [(set_attr "op_type" "RRF,VRR")
4596     (set_attr "type"    "ftoi")])
4597
4598 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4599 ;         clfdtr, clfxtr,         clgdtr, clgxtr
4600 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4601   [(set (match_operand:GPR                  0 "register_operand" "=d")
4602         (unsigned_fix:GPR (match_operand:FP 1 "register_operand"  "f")))
4603    (unspec:GPR [(match_operand:GPR          2 "immediate_operand" "K")] UNSPEC_ROUND)
4604    (clobber (reg:CC CC_REGNUM))]
4605    "TARGET_Z196 && TARGET_HARD_FLOAT
4606     && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4607    "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4608    [(set_attr "op_type" "RRF")
4609     (set_attr "type"    "ftoi")])
4610
4611 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4612   [(set (match_operand:GPR 0 "register_operand" "")
4613         (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4614   "TARGET_HARD_FLOAT"
4615 {
4616   emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4617              GEN_INT (5)));
4618   DONE;
4619 })
4620
4621 (define_insn "*fix_truncdfdi2_bfp_z13"
4622   [(set (match_operand:DI         0 "register_operand" "=d,v")
4623         (fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4624    (unspec:DI [(match_operand:DI  2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4625    (clobber (reg:CC CC_REGNUM))]
4626   "TARGET_Z13 && TARGET_HARD_FLOAT"
4627   "@
4628    cgdbr\t%0,%h2,%1
4629    wcgdb\t%v0,%v1,0,%h2"
4630   [(set_attr "op_type" "RRE,VRR")
4631    (set_attr "type"    "ftoi")])
4632
4633 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4634 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4635   [(set (match_operand:GPR          0 "register_operand" "=d")
4636         (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4637    (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4638    (clobber (reg:CC CC_REGNUM))]
4639   "TARGET_HARD_FLOAT
4640     && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4641   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4642   [(set_attr "op_type" "RRE")
4643    (set_attr "type"    "ftoi")])
4644
4645 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4646   [(parallel
4647     [(set (match_operand:GPR          0 "register_operand" "=d")
4648           (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4649      (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4650      (clobber (reg:CC CC_REGNUM))])]
4651   "TARGET_HARD_FLOAT")
4652 ;
4653 ; fix_trunc(td|dd)di2 instruction pattern(s).
4654 ;
4655
4656 (define_expand "fix_trunc<mode>di2"
4657   [(set (match_operand:DI 0 "register_operand" "")
4658         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4659   "TARGET_ZARCH && TARGET_HARD_DFP"
4660 {
4661   operands[1] = force_reg (<MODE>mode, operands[1]);
4662   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4663       GEN_INT (9)));
4664   DONE;
4665 })
4666
4667 ; cgxtr, cgdtr
4668 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4669   [(set (match_operand:DI 0 "register_operand" "=d")
4670         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4671    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4672    (clobber (reg:CC CC_REGNUM))]
4673   "TARGET_ZARCH && TARGET_HARD_DFP"
4674   "cg<DFP:xde>tr\t%0,%h2,%1"
4675   [(set_attr "op_type" "RRF")
4676    (set_attr "type"    "ftoidfp")])
4677
4678
4679 ;
4680 ; fix_trunctf(si|di)2 instruction pattern(s).
4681 ;
4682
4683 (define_expand "fix_trunctf<mode>2"
4684   [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4685                    (fix:GPR (match_operand:TF 1 "register_operand" "")))
4686               (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4687               (clobber (reg:CC CC_REGNUM))])]
4688   "TARGET_HARD_FLOAT"
4689   "")
4690
4691
4692 ;
4693 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4694 ;
4695
4696 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4697 (define_insn "floatdi<mode>2"
4698   [(set (match_operand:FP           0 "register_operand" "=f,<vf>")
4699         (float:FP (match_operand:DI 1 "register_operand"  "d,<vd>")))]
4700   "TARGET_ZARCH && TARGET_HARD_FLOAT"
4701   "@
4702    c<xde>g<bt>r\t%0,%1
4703    wcdgb\t%v0,%v1,0,0"
4704   [(set_attr "op_type"      "RRE,VRR")
4705    (set_attr "type"         "itof<mode>" )
4706    (set_attr "cpu_facility" "*,vec")])
4707
4708 ; cxfbr, cdfbr, cefbr
4709 (define_insn "floatsi<mode>2"
4710   [(set (match_operand:BFP 0 "register_operand" "=f")
4711         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4712   "TARGET_HARD_FLOAT"
4713   "c<xde>fbr\t%0,%1"
4714   [(set_attr "op_type" "RRE")
4715    (set_attr "type"   "itof<mode>" )])
4716
4717 ; cxftr, cdftr
4718 (define_insn "floatsi<mode>2"
4719   [(set (match_operand:DFP 0 "register_operand" "=f")
4720         (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4721   "TARGET_Z196 && TARGET_HARD_FLOAT"
4722   "c<xde>ftr\t%0,0,%1,0"
4723   [(set_attr "op_type" "RRE")
4724    (set_attr "type"   "itof<mode>" )])
4725
4726 ;
4727 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4728 ;
4729
4730 (define_insn "*floatunsdidf2_z13"
4731   [(set (match_operand:DF                    0 "register_operand" "=f,v")
4732         (unsigned_float:DF (match_operand:DI 1 "register_operand"  "d,v")))]
4733   "TARGET_Z13 && TARGET_HARD_FLOAT"
4734   "@
4735    cdlgbr\t%0,0,%1,0
4736    wcdlgb\t%v0,%v1,0,0"
4737   [(set_attr "op_type" "RRE,VRR")
4738    (set_attr "type"    "itofdf")])
4739
4740 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4741 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4742 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4743   [(set (match_operand:FP                     0 "register_operand" "=f")
4744         (unsigned_float:FP (match_operand:GPR 1 "register_operand"  "d")))]
4745   "TARGET_Z196 && TARGET_HARD_FLOAT
4746    && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4747   "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4748   [(set_attr "op_type" "RRE")
4749    (set_attr "type"    "itof<FP:mode>")])
4750
4751 (define_expand "floatuns<GPR:mode><FP:mode>2"
4752   [(set (match_operand:FP                     0 "register_operand" "")
4753         (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4754   "TARGET_Z196 && TARGET_HARD_FLOAT")
4755
4756 ;
4757 ; truncdfsf2 instruction pattern(s).
4758 ;
4759
4760 (define_insn "truncdfsf2"
4761   [(set (match_operand:SF                    0 "register_operand" "=f,v")
4762         (float_truncate:SF (match_operand:DF 1 "register_operand"  "f,v")))]
4763   "TARGET_HARD_FLOAT"
4764   "@
4765    ledbr\t%0,%1
4766    wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4767                        ; According to BFP rounding mode
4768   [(set_attr "op_type"      "RRE,VRR")
4769    (set_attr "type"         "ftruncdf")
4770    (set_attr "cpu_facility" "*,vec")])
4771
4772 ;
4773 ; trunctf(df|sf)2 instruction pattern(s).
4774 ;
4775
4776 ; ldxbr, lexbr
4777 (define_insn "trunctf<mode>2"
4778   [(set (match_operand:DSF 0 "register_operand" "=f")
4779         (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4780    (clobber (match_scratch:TF 2 "=f"))]
4781   "TARGET_HARD_FLOAT"
4782   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4783   [(set_attr "length" "6")
4784    (set_attr "type"   "ftrunctf")])
4785
4786 ;
4787 ; trunctddd2 and truncddsd2 instruction pattern(s).
4788 ;
4789
4790 (define_insn "trunctddd2"
4791   [(set (match_operand:DD 0 "register_operand" "=f")
4792         (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4793    (clobber (match_scratch:TD 2 "=f"))]
4794   "TARGET_HARD_DFP"
4795   "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4796   [(set_attr "length"  "6")
4797    (set_attr "type"    "ftruncdd")])
4798
4799 (define_insn "truncddsd2"
4800   [(set (match_operand:SD 0 "register_operand" "=f")
4801         (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4802   "TARGET_HARD_DFP"
4803   "ledtr\t%0,0,%1,0"
4804   [(set_attr "op_type" "RRF")
4805    (set_attr "type"    "ftruncsd")])
4806
4807 (define_expand "trunctdsd2"
4808   [(parallel
4809     [(set (match_dup 3)
4810           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4811      (clobber (match_scratch:TD 2 ""))])
4812    (set (match_operand:SD 0 "register_operand" "")
4813         (float_truncate:SD (match_dup 3)))]
4814   "TARGET_HARD_DFP"
4815 {
4816   operands[3] = gen_reg_rtx (DDmode);
4817 })
4818
4819 ;
4820 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4821 ;
4822
4823 (define_insn "*extendsfdf2_z13"
4824   [(set (match_operand:DF                  0 "register_operand"     "=f,f,v")
4825         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R,v")))]
4826   "TARGET_Z13 && TARGET_HARD_FLOAT"
4827   "@
4828    ldebr\t%0,%1
4829    ldeb\t%0,%1
4830    wldeb\t%v0,%v1"
4831   [(set_attr "op_type" "RRE,RXE,VRR")
4832    (set_attr "type"    "fsimpdf, floaddf,fsimpdf")])
4833
4834 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4835 (define_insn "*extend<DSF:mode><BFP:mode>2"
4836   [(set (match_operand:BFP                   0 "register_operand"     "=f,f")
4837         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
4838   "TARGET_HARD_FLOAT
4839    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4840    && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4841   "@
4842    l<BFP:xde><DSF:xde>br\t%0,%1
4843    l<BFP:xde><DSF:xde>b\t%0,%1"
4844   [(set_attr "op_type" "RRE,RXE")
4845    (set_attr "type"    "fsimp<BFP:mode>, fload<BFP:mode>")])
4846
4847 (define_expand "extend<DSF:mode><BFP:mode>2"
4848   [(set (match_operand:BFP                   0 "register_operand"     "")
4849         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4850   "TARGET_HARD_FLOAT
4851    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4852
4853 ;
4854 ; extendddtd2 and extendsddd2 instruction pattern(s).
4855 ;
4856
4857 (define_insn "extendddtd2"
4858   [(set (match_operand:TD 0 "register_operand" "=f")
4859         (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4860   "TARGET_HARD_DFP"
4861   "lxdtr\t%0,%1,0"
4862   [(set_attr "op_type" "RRF")
4863    (set_attr "type"    "fsimptf")])
4864
4865 (define_insn "extendsddd2"
4866   [(set (match_operand:DD 0 "register_operand" "=f")
4867         (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4868   "TARGET_HARD_DFP"
4869   "ldetr\t%0,%1,0"
4870   [(set_attr "op_type" "RRF")
4871    (set_attr "type"    "fsimptf")])
4872
4873 (define_expand "extendsdtd2"
4874   [(set (match_dup 2)
4875         (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4876    (set (match_operand:TD 0 "register_operand" "")
4877         (float_extend:TD (match_dup 2)))]
4878   "TARGET_HARD_DFP"
4879 {
4880   operands[2] = gen_reg_rtx (DDmode);
4881 })
4882
4883 ; Binary Floating Point - load fp integer
4884
4885 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4886 ; For all of them the inexact exceptions are suppressed.
4887
4888 ; fiebra, fidbra, fixbra
4889 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4890   [(set (match_operand:BFP 0 "register_operand" "=f")
4891         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4892                     FPINT))]
4893   "TARGET_Z196"
4894   "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4895   [(set_attr "op_type"   "RRF")
4896    (set_attr "type"      "fsimp<BFP:mode>")])
4897
4898 ; rint is supposed to raise an inexact exception so we can use the
4899 ; older instructions.
4900
4901 ; fiebr, fidbr, fixbr
4902 (define_insn "rint<BFP:mode>2"
4903   [(set (match_operand:BFP 0 "register_operand" "=f")
4904         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4905                     UNSPEC_FPINT_RINT))]
4906   ""
4907   "fi<BFP:xde>br\t%0,0,%1"
4908   [(set_attr "op_type"   "RRF")
4909    (set_attr "type"      "fsimp<BFP:mode>")])
4910
4911
4912 ; Decimal Floating Point - load fp integer
4913
4914 ; fidtr, fixtr
4915 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4916   [(set (match_operand:DFP 0 "register_operand" "=f")
4917         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4918                     FPINT))]
4919   "TARGET_HARD_DFP"
4920   "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4921   [(set_attr "op_type"   "RRF")
4922    (set_attr "type"      "fsimp<DFP:mode>")])
4923
4924 ; fidtr, fixtr
4925 (define_insn "rint<DFP:mode>2"
4926   [(set (match_operand:DFP 0 "register_operand" "=f")
4927         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4928                     UNSPEC_FPINT_RINT))]
4929   "TARGET_HARD_DFP"
4930   "fi<DFP:xde>tr\t%0,0,%1,0"
4931   [(set_attr "op_type"   "RRF")
4932    (set_attr "type"      "fsimp<DFP:mode>")])
4933
4934 ;
4935 ; Binary <-> Decimal floating point trunc patterns
4936 ;
4937
4938 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4939   [(set (reg:DFP_ALL FPR0_REGNUM)
4940         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4941    (use (reg:SI GPR0_REGNUM))
4942    (clobber (reg:CC CC_REGNUM))
4943    (clobber (reg:SI GPR1_REGNUM))]
4944   "TARGET_HARD_DFP"
4945   "pfpo")
4946
4947 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4948   [(set (reg:BFP FPR0_REGNUM)
4949         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4950    (use (reg:SI GPR0_REGNUM))
4951    (clobber (reg:CC CC_REGNUM))
4952    (clobber (reg:SI GPR1_REGNUM))]
4953   "TARGET_HARD_DFP"
4954   "pfpo")
4955
4956 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4957   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4958    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4959    (parallel
4960     [(set (reg:DFP_ALL FPR0_REGNUM)
4961           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4962      (use (reg:SI GPR0_REGNUM))
4963      (clobber (reg:CC CC_REGNUM))
4964      (clobber (reg:SI GPR1_REGNUM))])
4965    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4966         (reg:DFP_ALL FPR0_REGNUM))]
4967   "TARGET_HARD_DFP
4968    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4969 {
4970   HOST_WIDE_INT flags;
4971
4972   flags = (PFPO_CONVERT |
4973            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4974            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4975
4976   operands[2] = GEN_INT (flags);
4977 })
4978
4979 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4980   [(set (reg:DFP_ALL FPR4_REGNUM)
4981         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4982    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4983    (parallel
4984     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4985      (use (reg:SI GPR0_REGNUM))
4986      (clobber (reg:CC CC_REGNUM))
4987      (clobber (reg:SI GPR1_REGNUM))])
4988    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4989   "TARGET_HARD_DFP
4990    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4991 {
4992   HOST_WIDE_INT flags;
4993
4994   flags = (PFPO_CONVERT |
4995            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4996            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4997
4998   operands[2] = GEN_INT (flags);
4999 })
5000
5001 ;
5002 ; Binary <-> Decimal floating point extend patterns
5003 ;
5004
5005 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5006   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5007    (use (reg:SI GPR0_REGNUM))
5008    (clobber (reg:CC CC_REGNUM))
5009    (clobber (reg:SI GPR1_REGNUM))]
5010   "TARGET_HARD_DFP"
5011   "pfpo")
5012
5013 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5014   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5015    (use (reg:SI GPR0_REGNUM))
5016    (clobber (reg:CC CC_REGNUM))
5017    (clobber (reg:SI GPR1_REGNUM))]
5018   "TARGET_HARD_DFP"
5019   "pfpo")
5020
5021 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5022   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5023    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5024    (parallel
5025     [(set (reg:DFP_ALL FPR0_REGNUM)
5026           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5027      (use (reg:SI GPR0_REGNUM))
5028      (clobber (reg:CC CC_REGNUM))
5029      (clobber (reg:SI GPR1_REGNUM))])
5030    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5031         (reg:DFP_ALL FPR0_REGNUM))]
5032   "TARGET_HARD_DFP
5033    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5034 {
5035   HOST_WIDE_INT flags;
5036
5037   flags = (PFPO_CONVERT |
5038            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5039            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5040
5041   operands[2] = GEN_INT (flags);
5042 })
5043
5044 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5045   [(set (reg:DFP_ALL FPR4_REGNUM)
5046         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5047    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5048    (parallel
5049     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5050      (use (reg:SI GPR0_REGNUM))
5051      (clobber (reg:CC CC_REGNUM))
5052      (clobber (reg:SI GPR1_REGNUM))])
5053    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5054   "TARGET_HARD_DFP
5055    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5056 {
5057   HOST_WIDE_INT flags;
5058
5059   flags = (PFPO_CONVERT |
5060            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5061            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5062
5063   operands[2] = GEN_INT (flags);
5064 })
5065
5066
5067 ;;
5068 ;; ARITHMETIC OPERATIONS
5069 ;;
5070 ;  arithmetic operations set the ConditionCode,
5071 ;  because of unpredictable Bits in Register for Halfword and Byte
5072 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
5073
5074 ;;
5075 ;;- Add instructions.
5076 ;;
5077
5078 ;
5079 ; addti3 instruction pattern(s).
5080 ;
5081
5082 (define_expand "addti3"
5083   [(parallel
5084     [(set (match_operand:TI          0 "register_operand"     "")
5085           (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5086                    (match_operand:TI 2 "general_operand"      "") ) )
5087      (clobber (reg:CC CC_REGNUM))])]
5088   "TARGET_ZARCH"
5089 {
5090   /* For z13 we have vaq which doesn't set CC.  */
5091   if (TARGET_VX)
5092     {
5093       emit_insn (gen_rtx_SET (operands[0],
5094                               gen_rtx_PLUS (TImode,
5095                                             copy_to_mode_reg (TImode, operands[1]),
5096                                             copy_to_mode_reg (TImode, operands[2]))));
5097       DONE;
5098     }
5099 })
5100
5101 (define_insn_and_split "*addti3"
5102   [(set (match_operand:TI          0 "register_operand"    "=&d")
5103         (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5104                  (match_operand:TI 2 "general_operand"      "do") ) )
5105    (clobber (reg:CC CC_REGNUM))]
5106   "TARGET_ZARCH"
5107   "#"
5108   "&& reload_completed"
5109   [(parallel
5110     [(set (reg:CCL1 CC_REGNUM)
5111           (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5112                         (match_dup 7)))
5113      (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5114    (parallel
5115     [(set (match_dup 3) (plus:DI
5116                           (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5117                                    (match_dup 4)) (match_dup 5)))
5118      (clobber (reg:CC CC_REGNUM))])]
5119   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5120    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5121    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5122    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5123    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5124    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5125   [(set_attr "op_type"  "*")
5126    (set_attr "cpu_facility" "*")])
5127
5128 ;
5129 ; adddi3 instruction pattern(s).
5130 ;
5131
5132 (define_expand "adddi3"
5133   [(parallel
5134     [(set (match_operand:DI 0 "nonimmediate_operand" "")
5135           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5136                    (match_operand:DI 2 "general_operand" "")))
5137      (clobber (reg:CC CC_REGNUM))])]
5138   ""
5139   "")
5140
5141 (define_insn "*adddi3_sign"
5142   [(set (match_operand:DI 0 "register_operand" "=d,d")
5143         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5144                  (match_operand:DI 1 "register_operand" "0,0")))
5145    (clobber (reg:CC CC_REGNUM))]
5146   "TARGET_ZARCH"
5147   "@
5148    agfr\t%0,%2
5149    agf\t%0,%2"
5150   [(set_attr "op_type"  "RRE,RXY")
5151    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5152
5153 (define_insn "*adddi3_zero_cc"
5154   [(set (reg CC_REGNUM)
5155         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5156                           (match_operand:DI 1 "register_operand" "0,0"))
5157                  (const_int 0)))
5158    (set (match_operand:DI 0 "register_operand" "=d,d")
5159         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5160   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5161   "@
5162    algfr\t%0,%2
5163    algf\t%0,%2"
5164   [(set_attr "op_type"  "RRE,RXY")
5165    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5166
5167 (define_insn "*adddi3_zero_cconly"
5168   [(set (reg CC_REGNUM)
5169         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5170                           (match_operand:DI 1 "register_operand" "0,0"))
5171                  (const_int 0)))
5172    (clobber (match_scratch:DI 0 "=d,d"))]
5173   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5174   "@
5175    algfr\t%0,%2
5176    algf\t%0,%2"
5177   [(set_attr "op_type"  "RRE,RXY")
5178    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5179
5180 (define_insn "*adddi3_zero"
5181   [(set (match_operand:DI 0 "register_operand" "=d,d")
5182         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5183                  (match_operand:DI 1 "register_operand" "0,0")))
5184    (clobber (reg:CC CC_REGNUM))]
5185   "TARGET_ZARCH"
5186   "@
5187    algfr\t%0,%2
5188    algf\t%0,%2"
5189   [(set_attr "op_type"  "RRE,RXY")
5190    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5191
5192 (define_insn_and_split "*adddi3_31z"
5193   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5194         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5195                  (match_operand:DI 2 "general_operand" "do") ) )
5196    (clobber (reg:CC CC_REGNUM))]
5197   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5198   "#"
5199   "&& reload_completed"
5200   [(parallel
5201     [(set (reg:CCL1 CC_REGNUM)
5202           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5203                         (match_dup 7)))
5204      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5205    (parallel
5206     [(set (match_dup 3) (plus:SI
5207                           (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5208                                    (match_dup 4)) (match_dup 5)))
5209      (clobber (reg:CC CC_REGNUM))])]
5210   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5211    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5212    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5213    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5214    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5215    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5216
5217 (define_insn_and_split "*adddi3_31"
5218   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5219         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5220                  (match_operand:DI 2 "general_operand" "do") ) )
5221    (clobber (reg:CC CC_REGNUM))]
5222   "!TARGET_CPU_ZARCH"
5223   "#"
5224   "&& reload_completed"
5225   [(parallel
5226     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5227      (clobber (reg:CC CC_REGNUM))])
5228    (parallel
5229     [(set (reg:CCL1 CC_REGNUM)
5230           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5231                         (match_dup 7)))
5232      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5233    (set (pc)
5234         (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5235                       (pc)
5236                       (label_ref (match_dup 9))))
5237    (parallel
5238     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5239      (clobber (reg:CC CC_REGNUM))])
5240    (match_dup 9)]
5241   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5242    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5243    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5244    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5245    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5246    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5247    operands[9] = gen_label_rtx ();")
5248
5249 ;
5250 ; addsi3 instruction pattern(s).
5251 ;
5252
5253 (define_expand "addsi3"
5254   [(parallel
5255     [(set (match_operand:SI 0 "nonimmediate_operand" "")
5256           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5257                    (match_operand:SI 2 "general_operand" "")))
5258      (clobber (reg:CC CC_REGNUM))])]
5259   ""
5260   "")
5261
5262 (define_insn "*addsi3_sign"
5263   [(set (match_operand:SI 0 "register_operand" "=d,d")
5264         (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5265                  (match_operand:SI 1 "register_operand" "0,0")))
5266    (clobber (reg:CC CC_REGNUM))]
5267   ""
5268   "@
5269    ah\t%0,%2
5270    ahy\t%0,%2"
5271   [(set_attr "op_type"  "RX,RXY")
5272    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5273
5274 ;
5275 ; add(di|si)3 instruction pattern(s).
5276 ;
5277
5278 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5279 (define_insn "*add<mode>3"
5280   [(set (match_operand:GPR 0 "nonimmediate_operand"           "=d,d,d,d, d, d,d,d,QS")
5281         (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
5282                   (match_operand:GPR 2 "general_operand"      " d,d,K,K,Op,On,R,T, C") ) )
5283    (clobber (reg:CC CC_REGNUM))]
5284   ""
5285   "@
5286    a<g>r\t%0,%2
5287    a<g>rk\t%0,%1,%2
5288    a<g>hi\t%0,%h2
5289    a<g>hik\t%0,%1,%h2
5290    al<g>fi\t%0,%2
5291    sl<g>fi\t%0,%n2
5292    a<g>\t%0,%2
5293    a<y>\t%0,%2
5294    a<g>si\t%0,%c2"
5295   [(set_attr "op_type"  "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5296    (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
5297    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5298                         z10_super_E1,z10_super_E1,z10_super_E1")])
5299
5300 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5301 (define_insn "*add<mode>3_carry1_cc"
5302   [(set (reg CC_REGNUM)
5303         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5304                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5305                  (match_dup 1)))
5306    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,d")
5307         (plus:GPR (match_dup 1) (match_dup 2)))]
5308   "s390_match_ccmode (insn, CCL1mode)"
5309   "@
5310    al<g>r\t%0,%2
5311    al<g>rk\t%0,%1,%2
5312    al<g>fi\t%0,%2
5313    sl<g>fi\t%0,%n2
5314    al<g>hsik\t%0,%1,%h2
5315    al<g>\t%0,%2
5316    al<y>\t%0,%2
5317    al<g>si\t%0,%c2"
5318   [(set_attr "op_type"      "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5319    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5320    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5321                         z10_super_E1,z10_super_E1,z10_super_E1")])
5322
5323 ; alr, al, aly, algr, alg, alrk, algrk
5324 (define_insn "*add<mode>3_carry1_cconly"
5325   [(set (reg CC_REGNUM)
5326         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5327                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5328                  (match_dup 1)))
5329    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5330   "s390_match_ccmode (insn, CCL1mode)"
5331   "@
5332    al<g>r\t%0,%2
5333    al<g>rk\t%0,%1,%2
5334    al<g>\t%0,%2
5335    al<y>\t%0,%2"
5336   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5337    (set_attr "cpu_facility" "*,z196,*,*")
5338    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5339
5340 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5341 (define_insn "*add<mode>3_carry2_cc"
5342   [(set (reg CC_REGNUM)
5343         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5344                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5345                  (match_dup 2)))
5346    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5347         (plus:GPR (match_dup 1) (match_dup 2)))]
5348   "s390_match_ccmode (insn, CCL1mode)"
5349   "@
5350    al<g>r\t%0,%2
5351    al<g>rk\t%0,%1,%2
5352    al<g>fi\t%0,%2
5353    sl<g>fi\t%0,%n2
5354    al<g>hsik\t%0,%1,%h2
5355    al<g>\t%0,%2
5356    al<y>\t%0,%2
5357    al<g>si\t%0,%c2"
5358   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5359    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5360    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5361                         z10_super_E1,z10_super_E1,z10_super_E1")])
5362
5363 ; alr, al, aly, algr, alg, alrk, algrk
5364 (define_insn "*add<mode>3_carry2_cconly"
5365   [(set (reg CC_REGNUM)
5366         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5367                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5368                  (match_dup 2)))
5369    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5370   "s390_match_ccmode (insn, CCL1mode)"
5371   "@
5372    al<g>r\t%0,%2
5373    al<g>rk\t%0,%1,%2
5374    al<g>\t%0,%2
5375    al<y>\t%0,%2"
5376   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5377    (set_attr "cpu_facility" "*,z196,*,*")
5378    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5379
5380 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5381 (define_insn "*add<mode>3_cc"
5382   [(set (reg CC_REGNUM)
5383         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5384                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5385                  (const_int 0)))
5386    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5387         (plus:GPR (match_dup 1) (match_dup 2)))]
5388   "s390_match_ccmode (insn, CCLmode)"
5389   "@
5390    al<g>r\t%0,%2
5391    al<g>rk\t%0,%1,%2
5392    al<g>fi\t%0,%2
5393    sl<g>fi\t%0,%n2
5394    al<g>hsik\t%0,%1,%h2
5395    al<g>\t%0,%2
5396    al<y>\t%0,%2
5397    al<g>si\t%0,%c2"
5398   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5399    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5400    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5401                         *,z10_super_E1,z10_super_E1,z10_super_E1")])
5402
5403 ; alr, al, aly, algr, alg, alrk, algrk
5404 (define_insn "*add<mode>3_cconly"
5405   [(set (reg CC_REGNUM)
5406         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5407                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5408                  (const_int 0)))
5409    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5410   "s390_match_ccmode (insn, CCLmode)"
5411   "@
5412    al<g>r\t%0,%2
5413    al<g>rk\t%0,%1,%2
5414    al<g>\t%0,%2
5415    al<y>\t%0,%2"
5416   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5417    (set_attr "cpu_facility" "*,z196,*,*")
5418    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5419
5420 ; alr, al, aly, algr, alg, alrk, algrk
5421 (define_insn "*add<mode>3_cconly2"
5422   [(set (reg CC_REGNUM)
5423         (compare (match_operand:GPR 1 "nonimmediate_operand"    "%0,d,0,0")
5424                  (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5425    (clobber (match_scratch:GPR 0                                "=d,d,d,d"))]
5426   "s390_match_ccmode(insn, CCLmode)"
5427   "@
5428    al<g>r\t%0,%2
5429    al<g>rk\t%0,%1,%2
5430    al<g>\t%0,%2
5431    al<y>\t%0,%2"
5432   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5433    (set_attr "cpu_facility" "*,z196,*,*")
5434    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5435
5436 ; ahi, afi, aghi, agfi, asi, agsi
5437 (define_insn "*add<mode>3_imm_cc"
5438   [(set (reg CC_REGNUM)
5439         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5440                            (match_operand:GPR 2 "const_int_operand"    " K, K,Os, C"))
5441                  (const_int 0)))
5442    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d, d,d,QS")
5443         (plus:GPR (match_dup 1) (match_dup 2)))]
5444   "s390_match_ccmode (insn, CCAmode)
5445    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5446        || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5447            /* Avoid INT32_MIN on 32 bit.  */
5448            && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5449   "@
5450    a<g>hi\t%0,%h2
5451    a<g>hik\t%0,%1,%h2
5452    a<g>fi\t%0,%2
5453    a<g>si\t%0,%c2"
5454   [(set_attr "op_type"      "RI,RIE,RIL,SIY")
5455    (set_attr "cpu_facility" "*,z196,extimm,z10")
5456    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5457
5458 ;
5459 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5460 ;
5461
5462 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5463 ; FIXME: wfadb does not clobber cc
5464 (define_insn "add<mode>3"
5465   [(set (match_operand:FP 0 "register_operand"                 "=f,   f,<vf>")
5466         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
5467                  (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))
5468    (clobber (reg:CC CC_REGNUM))]
5469   "TARGET_HARD_FLOAT"
5470   "@
5471    a<xde><bt>r\t%0,<op1>%2
5472    a<xde>b\t%0,%2
5473    wfadb\t%v0,%v1,%v2"
5474   [(set_attr "op_type"      "<RRer>,RXE,VRR")
5475    (set_attr "type"         "fsimp<mode>")
5476    (set_attr "cpu_facility" "*,*,vec")])
5477
5478 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5479 (define_insn "*add<mode>3_cc"
5480   [(set (reg CC_REGNUM)
5481         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5482                           (match_operand:FP 2 "general_operand"      " f,<Rf>"))
5483                  (match_operand:FP 3 "const0_operand" "")))
5484    (set (match_operand:FP 0 "register_operand" "=f,f")
5485         (plus:FP (match_dup 1) (match_dup 2)))]
5486   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5487   "@
5488    a<xde><bt>r\t%0,<op1>%2
5489    a<xde>b\t%0,%2"
5490   [(set_attr "op_type"  "<RRer>,RXE")
5491    (set_attr "type"     "fsimp<mode>")])
5492
5493 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5494 (define_insn "*add<mode>3_cconly"
5495   [(set (reg CC_REGNUM)
5496         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5497                            (match_operand:FP 2 "general_operand"      " f,<Rf>"))
5498                  (match_operand:FP 3 "const0_operand" "")))
5499    (clobber (match_scratch:FP 0 "=f,f"))]
5500   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5501   "@
5502    a<xde><bt>r\t%0,<op1>%2
5503    a<xde>b\t%0,%2"
5504   [(set_attr "op_type"  "<RRer>,RXE")
5505    (set_attr "type"     "fsimp<mode>")])
5506
5507 ;
5508 ; Pointer add instruction patterns
5509 ;
5510
5511 ; This will match "*la_64"
5512 (define_expand "addptrdi3"
5513   [(set (match_operand:DI 0 "register_operand" "")
5514         (plus:DI (match_operand:DI 1 "register_operand" "")
5515                  (match_operand:DI 2 "nonmemory_operand" "")))]
5516   "TARGET_64BIT"
5517 {
5518   if (GET_CODE (operands[2]) == CONST_INT)
5519     {
5520       HOST_WIDE_INT c = INTVAL (operands[2]);
5521
5522       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5523           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5524         {
5525           operands[2] = force_const_mem (DImode, operands[2]);
5526           operands[2] = force_reg (DImode, operands[2]);
5527         }
5528       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5529         operands[2] = force_reg (DImode, operands[2]);
5530     }
5531 })
5532
5533 ; For 31 bit we have to prevent the generated pattern from matching
5534 ; normal ADDs since la only does a 31 bit add.  This is supposed to
5535 ; match "force_la_31".
5536 (define_expand "addptrsi3"
5537   [(parallel
5538     [(set (match_operand:SI 0 "register_operand" "")
5539           (plus:SI (match_operand:SI 1 "register_operand" "")
5540                    (match_operand:SI 2 "nonmemory_operand" "")))
5541                    (use (const_int 0))])]
5542   "!TARGET_64BIT"
5543 {
5544   if (GET_CODE (operands[2]) == CONST_INT)
5545     {
5546       HOST_WIDE_INT c = INTVAL (operands[2]);
5547
5548       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5549           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5550         {
5551           operands[2] = force_const_mem (SImode, operands[2]);
5552           operands[2] = force_reg (SImode, operands[2]);
5553         }
5554       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5555         operands[2] = force_reg (SImode, operands[2]);
5556     }
5557 })
5558
5559 ;;
5560 ;;- Subtract instructions.
5561 ;;
5562
5563 ;
5564 ; subti3 instruction pattern(s).
5565 ;
5566
5567 (define_expand "subti3"
5568   [(parallel
5569     [(set (match_operand:TI           0 "register_operand" "")
5570           (minus:TI (match_operand:TI 1 "register_operand" "")
5571                     (match_operand:TI 2 "general_operand"  "") ) )
5572      (clobber (reg:CC CC_REGNUM))])]
5573   "TARGET_ZARCH"
5574 {
5575   /* For z13 we have vaq which doesn't set CC.  */
5576   if (TARGET_VX)
5577     {
5578       emit_insn (gen_rtx_SET (operands[0],
5579                               gen_rtx_MINUS (TImode,
5580                                             operands[1],
5581                                             copy_to_mode_reg (TImode, operands[2]))));
5582       DONE;
5583     }
5584 })
5585
5586 (define_insn_and_split "*subti3"
5587   [(set (match_operand:TI           0 "register_operand" "=&d")
5588         (minus:TI (match_operand:TI 1 "register_operand"   "0")
5589                   (match_operand:TI 2 "general_operand"   "do") ) )
5590    (clobber (reg:CC CC_REGNUM))]
5591   "TARGET_ZARCH"
5592   "#"
5593   "&& reload_completed"
5594   [(parallel
5595     [(set (reg:CCL2 CC_REGNUM)
5596           (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5597                         (match_dup 7)))
5598      (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5599    (parallel
5600     [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5601                                   (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5602      (clobber (reg:CC CC_REGNUM))])]
5603   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5604    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5605    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5606    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5607    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5608    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5609   [(set_attr "op_type"      "*")
5610    (set_attr "cpu_facility" "*")])
5611
5612 ;
5613 ; subdi3 instruction pattern(s).
5614 ;
5615
5616 (define_expand "subdi3"
5617   [(parallel
5618     [(set (match_operand:DI 0 "register_operand" "")
5619           (minus:DI (match_operand:DI 1 "register_operand" "")
5620                     (match_operand:DI 2 "general_operand" "")))
5621      (clobber (reg:CC CC_REGNUM))])]
5622   ""
5623   "")
5624
5625 (define_insn "*subdi3_sign"
5626   [(set (match_operand:DI 0 "register_operand" "=d,d")
5627         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5628                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5629    (clobber (reg:CC CC_REGNUM))]
5630   "TARGET_ZARCH"
5631   "@
5632    sgfr\t%0,%2
5633    sgf\t%0,%2"
5634   [(set_attr "op_type"  "RRE,RXY")
5635    (set_attr "z10prop" "z10_c,*")
5636    (set_attr "z196prop" "z196_cracked")])
5637
5638 (define_insn "*subdi3_zero_cc"
5639   [(set (reg CC_REGNUM)
5640         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5641                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5642                  (const_int 0)))
5643    (set (match_operand:DI 0 "register_operand" "=d,d")
5644         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5645   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5646   "@
5647    slgfr\t%0,%2
5648    slgf\t%0,%2"
5649   [(set_attr "op_type"  "RRE,RXY")
5650    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5651
5652 (define_insn "*subdi3_zero_cconly"
5653   [(set (reg CC_REGNUM)
5654         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5655                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5656                  (const_int 0)))
5657    (clobber (match_scratch:DI 0 "=d,d"))]
5658   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5659   "@
5660    slgfr\t%0,%2
5661    slgf\t%0,%2"
5662   [(set_attr "op_type"  "RRE,RXY")
5663    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5664
5665 (define_insn "*subdi3_zero"
5666   [(set (match_operand:DI 0 "register_operand" "=d,d")
5667         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5668                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5669    (clobber (reg:CC CC_REGNUM))]
5670   "TARGET_ZARCH"
5671   "@
5672    slgfr\t%0,%2
5673    slgf\t%0,%2"
5674   [(set_attr "op_type"  "RRE,RXY")
5675    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5676
5677 (define_insn_and_split "*subdi3_31z"
5678   [(set (match_operand:DI 0 "register_operand" "=&d")
5679         (minus:DI (match_operand:DI 1 "register_operand" "0")
5680                   (match_operand:DI 2 "general_operand" "do") ) )
5681    (clobber (reg:CC CC_REGNUM))]
5682   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5683   "#"
5684   "&& reload_completed"
5685   [(parallel
5686     [(set (reg:CCL2 CC_REGNUM)
5687           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5688                         (match_dup 7)))
5689      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5690    (parallel
5691     [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5692                                   (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5693      (clobber (reg:CC CC_REGNUM))])]
5694   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5695    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5696    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5697    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5698    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5699    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5700
5701 (define_insn_and_split "*subdi3_31"
5702   [(set (match_operand:DI 0 "register_operand" "=&d")
5703         (minus:DI (match_operand:DI 1 "register_operand" "0")
5704                   (match_operand:DI 2 "general_operand" "do") ) )
5705    (clobber (reg:CC CC_REGNUM))]
5706   "!TARGET_CPU_ZARCH"
5707   "#"
5708   "&& reload_completed"
5709   [(parallel
5710     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5711      (clobber (reg:CC CC_REGNUM))])
5712    (parallel
5713     [(set (reg:CCL2 CC_REGNUM)
5714           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5715                         (match_dup 7)))
5716      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5717    (set (pc)
5718         (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5719                       (pc)
5720                       (label_ref (match_dup 9))))
5721    (parallel
5722     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5723      (clobber (reg:CC CC_REGNUM))])
5724    (match_dup 9)]
5725   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5726    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5727    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5728    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5729    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5730    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5731    operands[9] = gen_label_rtx ();")
5732
5733 ;
5734 ; subsi3 instruction pattern(s).
5735 ;
5736
5737 (define_expand "subsi3"
5738   [(parallel
5739     [(set (match_operand:SI 0 "register_operand" "")
5740           (minus:SI (match_operand:SI 1 "register_operand" "")
5741                     (match_operand:SI 2 "general_operand" "")))
5742      (clobber (reg:CC CC_REGNUM))])]
5743   ""
5744   "")
5745
5746 (define_insn "*subsi3_sign"
5747   [(set (match_operand:SI 0 "register_operand" "=d,d")
5748         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5749                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5750    (clobber (reg:CC CC_REGNUM))]
5751   ""
5752   "@
5753    sh\t%0,%2
5754    shy\t%0,%2"
5755   [(set_attr "op_type"  "RX,RXY")
5756    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5757
5758 ;
5759 ; sub(di|si)3 instruction pattern(s).
5760 ;
5761
5762 ; sr, s, sy, sgr, sg, srk, sgrk
5763 (define_insn "*sub<mode>3"
5764   [(set (match_operand:GPR 0 "register_operand"           "=d,d,d,d")
5765         (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5766                    (match_operand:GPR 2 "general_operand"  "d,d,R,T") ) )
5767    (clobber (reg:CC CC_REGNUM))]
5768   ""
5769   "@
5770    s<g>r\t%0,%2
5771    s<g>rk\t%0,%1,%2
5772    s<g>\t%0,%2
5773    s<y>\t%0,%2"
5774   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5775    (set_attr "cpu_facility" "*,z196,*,*")
5776    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5777
5778 ; slr, sl, sly, slgr, slg, slrk, slgrk
5779 (define_insn "*sub<mode>3_borrow_cc"
5780   [(set (reg CC_REGNUM)
5781         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5782                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5783                  (match_dup 1)))
5784    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5785         (minus:GPR (match_dup 1) (match_dup 2)))]
5786   "s390_match_ccmode (insn, CCL2mode)"
5787   "@
5788    sl<g>r\t%0,%2
5789    sl<g>rk\t%0,%1,%2
5790    sl<g>\t%0,%2
5791    sl<y>\t%0,%2"
5792   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5793    (set_attr "cpu_facility" "*,z196,*,*")
5794    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5795
5796 ; slr, sl, sly, slgr, slg, slrk, slgrk
5797 (define_insn "*sub<mode>3_borrow_cconly"
5798   [(set (reg CC_REGNUM)
5799         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5800                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5801                  (match_dup 1)))
5802    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5803   "s390_match_ccmode (insn, CCL2mode)"
5804   "@
5805    sl<g>r\t%0,%2
5806    sl<g>rk\t%0,%1,%2
5807    sl<g>\t%0,%2
5808    sl<y>\t%0,%2"
5809   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5810    (set_attr "cpu_facility" "*,z196,*,*")
5811    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5812
5813 ; slr, sl, sly, slgr, slg, slrk, slgrk
5814 (define_insn "*sub<mode>3_cc"
5815   [(set (reg CC_REGNUM)
5816         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5817                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5818                  (const_int 0)))
5819    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5820         (minus:GPR (match_dup 1) (match_dup 2)))]
5821   "s390_match_ccmode (insn, CCLmode)"
5822   "@
5823    sl<g>r\t%0,%2
5824    sl<g>rk\t%0,%1,%2
5825    sl<g>\t%0,%2
5826    sl<y>\t%0,%2"
5827   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5828    (set_attr "cpu_facility" "*,z196,*,*")
5829    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5830
5831 ; slr, sl, sly, slgr, slg, slrk, slgrk
5832 (define_insn "*sub<mode>3_cc2"
5833   [(set (reg CC_REGNUM)
5834         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5835                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5836    (set (match_operand:GPR 0 "register_operand"         "=d,d,d,d")
5837         (minus:GPR (match_dup 1) (match_dup 2)))]
5838   "s390_match_ccmode (insn, CCL3mode)"
5839   "@
5840    sl<g>r\t%0,%2
5841    sl<g>rk\t%0,%1,%2
5842    sl<g>\t%0,%2
5843    sl<y>\t%0,%2"
5844   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5845    (set_attr "cpu_facility" "*,z196,*,*")
5846    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5847
5848 ; slr, sl, sly, slgr, slg, slrk, slgrk
5849 (define_insn "*sub<mode>3_cconly"
5850   [(set (reg CC_REGNUM)
5851         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5852                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5853                  (const_int 0)))
5854    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5855   "s390_match_ccmode (insn, CCLmode)"
5856   "@
5857    sl<g>r\t%0,%2
5858    sl<g>rk\t%0,%1,%2
5859    sl<g>\t%0,%2
5860    sl<y>\t%0,%2"
5861   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5862    (set_attr "cpu_facility" "*,z196,*,*")
5863    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5864
5865
5866 ; slr, sl, sly, slgr, slg, slrk, slgrk
5867 (define_insn "*sub<mode>3_cconly2"
5868   [(set (reg CC_REGNUM)
5869         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5870                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5871    (clobber (match_scratch:GPR 0                        "=d,d,d,d"))]
5872   "s390_match_ccmode (insn, CCL3mode)"
5873   "@
5874    sl<g>r\t%0,%2
5875    sl<g>rk\t%0,%1,%2
5876    sl<g>\t%0,%2
5877    sl<y>\t%0,%2"
5878   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5879    (set_attr "cpu_facility" "*,z196,*,*")
5880    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5881
5882
5883 ;
5884 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5885 ;
5886
5887 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5888 (define_insn "sub<mode>3"
5889   [(set (match_operand:FP           0 "register_operand"   "=f,   f,<vf>")
5890         (minus:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
5891                   (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))
5892    (clobber (reg:CC CC_REGNUM))]
5893   "TARGET_HARD_FLOAT"
5894   "@
5895    s<xde><bt>r\t%0,<op1>%2
5896    s<xde>b\t%0,%2
5897    wfsdb\t%v0,%v1,%v2"
5898   [(set_attr "op_type"      "<RRer>,RXE,VRR")
5899    (set_attr "type"         "fsimp<mode>")
5900    (set_attr "cpu_facility" "*,*,vec")])
5901
5902 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5903 (define_insn "*sub<mode>3_cc"
5904   [(set (reg CC_REGNUM)
5905         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5906                            (match_operand:FP 2 "general_operand"      "f,<Rf>"))
5907                  (match_operand:FP 3 "const0_operand" "")))
5908    (set (match_operand:FP 0 "register_operand" "=f,f")
5909         (minus:FP (match_dup 1) (match_dup 2)))]
5910   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5911   "@
5912    s<xde><bt>r\t%0,<op1>%2
5913    s<xde>b\t%0,%2"
5914   [(set_attr "op_type"  "<RRer>,RXE")
5915    (set_attr "type"     "fsimp<mode>")])
5916
5917 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5918 (define_insn "*sub<mode>3_cconly"
5919   [(set (reg CC_REGNUM)
5920         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5921                            (match_operand:FP 2 "general_operand"      "f,<Rf>"))
5922                  (match_operand:FP 3 "const0_operand" "")))
5923    (clobber (match_scratch:FP 0 "=f,f"))]
5924   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5925   "@
5926    s<xde><bt>r\t%0,<op1>%2
5927    s<xde>b\t%0,%2"
5928   [(set_attr "op_type"  "<RRer>,RXE")
5929    (set_attr "type"     "fsimp<mode>")])
5930
5931
5932 ;;
5933 ;;- Conditional add/subtract instructions.
5934 ;;
5935
5936 ;
5937 ; add(di|si)cc instruction pattern(s).
5938 ;
5939
5940 ; the following 4 patterns are used when the result of an add with
5941 ; carry is checked for an overflow condition
5942
5943 ; op1 + op2 + c < op1
5944
5945 ; alcr, alc, alcgr, alcg
5946 (define_insn "*add<mode>3_alc_carry1_cc"
5947   [(set (reg CC_REGNUM)
5948         (compare
5949           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5950                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5951                     (match_operand:GPR 2 "general_operand" "d,RT"))
5952           (match_dup 1)))
5953    (set (match_operand:GPR 0 "register_operand" "=d,d")
5954         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5955   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5956   "@
5957    alc<g>r\t%0,%2
5958    alc<g>\t%0,%2"
5959   [(set_attr "op_type"  "RRE,RXY")
5960    (set_attr "z196prop" "z196_alone,z196_alone")])
5961
5962 ; alcr, alc, alcgr, alcg
5963 (define_insn "*add<mode>3_alc_carry1_cconly"
5964   [(set (reg CC_REGNUM)
5965         (compare
5966           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5967                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5968                     (match_operand:GPR 2 "general_operand" "d,RT"))
5969           (match_dup 1)))
5970    (clobber (match_scratch:GPR 0 "=d,d"))]
5971   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5972   "@
5973    alc<g>r\t%0,%2
5974    alc<g>\t%0,%2"
5975   [(set_attr "op_type"  "RRE,RXY")
5976    (set_attr "z196prop" "z196_alone,z196_alone")])
5977
5978 ; op1 + op2 + c < op2
5979
5980 ; alcr, alc, alcgr, alcg
5981 (define_insn "*add<mode>3_alc_carry2_cc"
5982   [(set (reg CC_REGNUM)
5983         (compare
5984           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5985                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5986                     (match_operand:GPR 2 "general_operand" "d,RT"))
5987           (match_dup 2)))
5988    (set (match_operand:GPR 0 "register_operand" "=d,d")
5989         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5990   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5991   "@
5992    alc<g>r\t%0,%2
5993    alc<g>\t%0,%2"
5994   [(set_attr "op_type"  "RRE,RXY")])
5995
5996 ; alcr, alc, alcgr, alcg
5997 (define_insn "*add<mode>3_alc_carry2_cconly"
5998   [(set (reg CC_REGNUM)
5999         (compare
6000           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6001                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6002                     (match_operand:GPR 2 "general_operand" "d,RT"))
6003           (match_dup 2)))
6004    (clobber (match_scratch:GPR 0 "=d,d"))]
6005   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6006   "@
6007    alc<g>r\t%0,%2
6008    alc<g>\t%0,%2"
6009   [(set_attr "op_type"  "RRE,RXY")])
6010
6011 ; alcr, alc, alcgr, alcg
6012 (define_insn "*add<mode>3_alc_cc"
6013   [(set (reg CC_REGNUM)
6014         (compare
6015           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6016                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6017                     (match_operand:GPR 2 "general_operand" "d,RT"))
6018           (const_int 0)))
6019    (set (match_operand:GPR 0 "register_operand" "=d,d")
6020         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6021   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6022   "@
6023    alc<g>r\t%0,%2
6024    alc<g>\t%0,%2"
6025   [(set_attr "op_type"  "RRE,RXY")])
6026
6027 ; alcr, alc, alcgr, alcg
6028 (define_insn "*add<mode>3_alc"
6029   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6030         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6031                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6032                   (match_operand:GPR 2 "general_operand" "d,RT")))
6033    (clobber (reg:CC CC_REGNUM))]
6034   "TARGET_CPU_ZARCH"
6035   "@
6036    alc<g>r\t%0,%2
6037    alc<g>\t%0,%2"
6038   [(set_attr "op_type"  "RRE,RXY")])
6039
6040 ; slbr, slb, slbgr, slbg
6041 (define_insn "*sub<mode>3_slb_cc"
6042   [(set (reg CC_REGNUM)
6043         (compare
6044           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6045                                 (match_operand:GPR 2 "general_operand" "d,RT"))
6046                      (match_operand:GPR 3 "s390_slb_comparison" ""))
6047           (const_int 0)))
6048    (set (match_operand:GPR 0 "register_operand" "=d,d")
6049         (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6050   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6051   "@
6052    slb<g>r\t%0,%2
6053    slb<g>\t%0,%2"
6054   [(set_attr "op_type"  "RRE,RXY")
6055    (set_attr "z10prop" "z10_c,*")])
6056
6057 ; slbr, slb, slbgr, slbg
6058 (define_insn "*sub<mode>3_slb"
6059   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6060         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6061                               (match_operand:GPR 2 "general_operand" "d,RT"))
6062                    (match_operand:GPR 3 "s390_slb_comparison" "")))
6063    (clobber (reg:CC CC_REGNUM))]
6064   "TARGET_CPU_ZARCH"
6065   "@
6066    slb<g>r\t%0,%2
6067    slb<g>\t%0,%2"
6068   [(set_attr "op_type"  "RRE,RXY")
6069    (set_attr "z10prop" "z10_c,*")])
6070
6071 (define_expand "add<mode>cc"
6072   [(match_operand:GPR 0 "register_operand" "")
6073    (match_operand 1 "comparison_operator" "")
6074    (match_operand:GPR 2 "register_operand" "")
6075    (match_operand:GPR 3 "const_int_operand" "")]
6076   "TARGET_CPU_ZARCH"
6077   "if (!s390_expand_addcc (GET_CODE (operands[1]),
6078                            XEXP (operands[1], 0), XEXP (operands[1], 1),
6079                            operands[0], operands[2],
6080                            operands[3])) FAIL; DONE;")
6081
6082 ;
6083 ; scond instruction pattern(s).
6084 ;
6085
6086 (define_insn_and_split "*scond<mode>"
6087   [(set (match_operand:GPR 0 "register_operand" "=&d")
6088         (match_operand:GPR 1 "s390_alc_comparison" ""))
6089    (clobber (reg:CC CC_REGNUM))]
6090   "TARGET_CPU_ZARCH"
6091   "#"
6092   "&& reload_completed"
6093   [(set (match_dup 0) (const_int 0))
6094    (parallel
6095     [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6096                                   (match_dup 0)))
6097      (clobber (reg:CC CC_REGNUM))])]
6098   "")
6099
6100 (define_insn_and_split "*scond<mode>_neg"
6101   [(set (match_operand:GPR 0 "register_operand" "=&d")
6102         (match_operand:GPR 1 "s390_slb_comparison" ""))
6103    (clobber (reg:CC CC_REGNUM))]
6104   "TARGET_CPU_ZARCH"
6105   "#"
6106   "&& reload_completed"
6107   [(set (match_dup 0) (const_int 0))
6108    (parallel
6109     [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6110                                    (match_dup 1)))
6111      (clobber (reg:CC CC_REGNUM))])
6112    (parallel
6113     [(set (match_dup 0) (neg:GPR (match_dup 0)))
6114      (clobber (reg:CC CC_REGNUM))])]
6115   "")
6116
6117
6118 (define_expand "cstore<mode>4"
6119   [(set (match_operand:SI 0 "register_operand" "")
6120         (match_operator:SI 1 "s390_scond_operator"
6121          [(match_operand:GPR 2 "register_operand" "")
6122           (match_operand:GPR 3 "general_operand" "")]))]
6123   "TARGET_CPU_ZARCH"
6124   "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6125                            operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6126
6127 (define_expand "cstorecc4"
6128   [(parallel
6129     [(set (match_operand:SI 0 "register_operand" "")
6130           (match_operator:SI 1 "s390_eqne_operator"
6131            [(match_operand:CCZ1 2 "register_operand")
6132             (match_operand 3 "const0_operand")]))
6133      (clobber (reg:CC CC_REGNUM))])]
6134   ""
6135   "emit_insn (gen_sne (operands[0], operands[2]));
6136    if (GET_CODE (operands[1]) == EQ)
6137      emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6138    DONE;")
6139
6140 (define_insn_and_split "sne"
6141   [(set (match_operand:SI 0 "register_operand" "=d")
6142         (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6143                (const_int 0)))
6144    (clobber (reg:CC CC_REGNUM))]
6145   ""
6146   "#"
6147   "reload_completed"
6148   [(parallel
6149     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6150      (clobber (reg:CC CC_REGNUM))])])
6151
6152
6153 ;;
6154 ;; - Conditional move instructions (introduced with z196)
6155 ;;
6156
6157 (define_expand "mov<mode>cc"
6158   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6159         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6160                           (match_operand:GPR 2 "nonimmediate_operand" "")
6161                           (match_operand:GPR 3 "nonimmediate_operand" "")))]
6162   "TARGET_Z196"
6163 {
6164   /* Emit the comparison insn in case we do not already have a comparison result.  */
6165   if (!s390_comparison (operands[1], VOIDmode))
6166     operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6167                                      XEXP (operands[1], 0),
6168                                      XEXP (operands[1], 1));
6169 })
6170
6171 ; locr, loc, stoc, locgr, locg, stocg
6172 (define_insn_and_split "*mov<mode>cc"
6173   [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d, d, d,QS,QS,&d")
6174         (if_then_else:GPR
6175           (match_operator 1 "s390_comparison"
6176             [(match_operand 2 "cc_reg_operand"        " c,c, c, c, c, c, c")
6177              (match_operand 5 "const_int_operand"     "")])
6178           (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
6179           (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
6180   "TARGET_Z196"
6181   "@
6182    loc<g>r%C1\t%0,%3
6183    loc<g>r%D1\t%0,%4
6184    loc<g>%C1\t%0,%3
6185    loc<g>%D1\t%0,%4
6186    stoc<g>%C1\t%3,%0
6187    stoc<g>%D1\t%4,%0
6188    #"
6189   "&& reload_completed
6190    && MEM_P (operands[3]) && MEM_P (operands[4])"
6191   [(set (match_dup 0)
6192         (if_then_else:GPR
6193          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6194          (match_dup 3)
6195          (match_dup 0)))
6196    (set (match_dup 0)
6197         (if_then_else:GPR
6198          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6199          (match_dup 0)
6200          (match_dup 4)))]
6201   ""
6202   [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
6203
6204 ;;
6205 ;;- Multiply instructions.
6206 ;;
6207
6208 ;
6209 ; muldi3 instruction pattern(s).
6210 ;
6211
6212 (define_insn "*muldi3_sign"
6213   [(set (match_operand:DI 0 "register_operand" "=d,d")
6214         (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
6215                  (match_operand:DI 1 "register_operand" "0,0")))]
6216   "TARGET_ZARCH"
6217   "@
6218    msgfr\t%0,%2
6219    msgf\t%0,%2"
6220   [(set_attr "op_type"      "RRE,RXY")
6221    (set_attr "type"         "imuldi")])
6222
6223 (define_insn "muldi3"
6224   [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6225         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6226                  (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
6227   "TARGET_ZARCH"
6228   "@
6229    msgr\t%0,%2
6230    mghi\t%0,%h2
6231    msg\t%0,%2
6232    msgfi\t%0,%2"
6233   [(set_attr "op_type"      "RRE,RI,RXY,RIL")
6234    (set_attr "type"         "imuldi")
6235    (set_attr "cpu_facility" "*,*,*,z10")])
6236
6237 ;
6238 ; mulsi3 instruction pattern(s).
6239 ;
6240
6241 (define_insn "*mulsi3_sign"
6242   [(set (match_operand:SI 0 "register_operand" "=d,d")
6243         (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6244                  (match_operand:SI 1 "register_operand" "0,0")))]
6245   ""
6246   "@
6247    mh\t%0,%2
6248    mhy\t%0,%2"
6249   [(set_attr "op_type"      "RX,RXY")
6250    (set_attr "type"         "imulhi")
6251    (set_attr "cpu_facility" "*,z10")])
6252
6253 (define_insn "mulsi3"
6254   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6255         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6256                   (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6257   ""
6258   "@
6259    msr\t%0,%2
6260    mhi\t%0,%h2
6261    ms\t%0,%2
6262    msy\t%0,%2
6263    msfi\t%0,%2"
6264   [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
6265    (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
6266    (set_attr "cpu_facility" "*,*,*,*,z10")])
6267
6268 ;
6269 ; mulsidi3 instruction pattern(s).
6270 ;
6271
6272 (define_insn "mulsidi3"
6273   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6274         (mult:DI (sign_extend:DI
6275                    (match_operand:SI 1 "register_operand" "%0,0,0"))
6276                  (sign_extend:DI
6277                    (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6278   "!TARGET_ZARCH"
6279   "@
6280    mr\t%0,%2
6281    m\t%0,%2
6282    mfy\t%0,%2"
6283   [(set_attr "op_type"      "RR,RX,RXY")
6284    (set_attr "type"         "imulsi")
6285    (set_attr "cpu_facility" "*,*,z10")])
6286
6287 ;
6288 ; umul instruction pattern(s).
6289 ;
6290
6291 ; mlr, ml, mlgr, mlg
6292 (define_insn "umul<dwh><mode>3"
6293   [(set (match_operand:DW 0 "register_operand"                   "=d, d")
6294         (mult:DW (zero_extend:DW
6295                    (match_operand:<DWH> 1 "register_operand"     "%0, 0"))
6296                  (zero_extend:DW
6297                    (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
6298   "TARGET_CPU_ZARCH"
6299   "@
6300    ml<tg>r\t%0,%2
6301    ml<tg>\t%0,%2"
6302   [(set_attr "op_type"  "RRE,RXY")
6303    (set_attr "type"     "imul<dwh>")])
6304
6305 ;
6306 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6307 ;
6308
6309 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6310 (define_insn "mul<mode>3"
6311   [(set (match_operand:FP          0 "register_operand"        "=f,   f,<vf>")
6312         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
6313                  (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))]
6314   "TARGET_HARD_FLOAT"
6315   "@
6316    m<xdee><bt>r\t%0,<op1>%2
6317    m<xdee>b\t%0,%2
6318    wfmdb\t%v0,%v1,%v2"
6319   [(set_attr "op_type"      "<RRer>,RXE,VRR")
6320    (set_attr "type"         "fmul<mode>")
6321    (set_attr "cpu_facility" "*,*,vec")])
6322
6323 ; madbr, maebr, maxb, madb, maeb
6324 (define_insn "fma<mode>4"
6325   [(set (match_operand:DSF          0 "register_operand"     "=f,f,<vf>")
6326         (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
6327                  (match_operand:DSF 2 "nonimmediate_operand"  "f,R,<vf>")
6328                  (match_operand:DSF 3 "register_operand"      "0,0,<v0>")))]
6329   "TARGET_HARD_FLOAT"
6330   "@
6331    ma<xde>br\t%0,%1,%2
6332    ma<xde>b\t%0,%1,%2
6333    wfmadb\t%v0,%v1,%v2,%v3"
6334   [(set_attr "op_type"      "RRE,RXE,VRR")
6335    (set_attr "type"         "fmadd<mode>")
6336    (set_attr "cpu_facility" "*,*,vec")])
6337
6338 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6339 (define_insn "fms<mode>4"
6340   [(set (match_operand:DSF                   0 "register_operand"     "=f,f,<vf>")
6341         (fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,<vf>")
6342                  (match_operand:DSF          2 "nonimmediate_operand"  "f,R,<vf>")
6343                  (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,<v0>"))))]
6344   "TARGET_HARD_FLOAT"
6345   "@
6346    ms<xde>br\t%0,%1,%2
6347    ms<xde>b\t%0,%1,%2
6348    wfmsdb\t%v0,%v1,%v2,%v3"
6349   [(set_attr "op_type"      "RRE,RXE,VRR")
6350    (set_attr "type"         "fmadd<mode>")
6351    (set_attr "cpu_facility" "*,*,vec")])
6352
6353 ;;
6354 ;;- Divide and modulo instructions.
6355 ;;
6356
6357 ;
6358 ; divmoddi4 instruction pattern(s).
6359 ;
6360
6361 (define_expand "divmoddi4"
6362   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6363                    (div:DI (match_operand:DI 1 "register_operand" "")
6364                            (match_operand:DI 2 "general_operand" "")))
6365               (set (match_operand:DI 3 "general_operand" "")
6366                    (mod:DI (match_dup 1) (match_dup 2)))])
6367    (clobber (match_dup 4))]
6368   "TARGET_ZARCH"
6369 {
6370   rtx insn, div_equal, mod_equal;
6371
6372   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6373   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6374
6375   operands[4] = gen_reg_rtx(TImode);
6376   emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6377
6378   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6379   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6380
6381   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6382   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6383
6384   DONE;
6385 })
6386
6387 (define_insn "divmodtidi3"
6388   [(set (match_operand:TI 0 "register_operand" "=d,d")
6389         (ior:TI
6390           (ashift:TI
6391             (zero_extend:TI
6392               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6393                       (match_operand:DI 2 "general_operand" "d,RT")))
6394             (const_int 64))
6395           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6396   "TARGET_ZARCH"
6397   "@
6398    dsgr\t%0,%2
6399    dsg\t%0,%2"
6400   [(set_attr "op_type"  "RRE,RXY")
6401    (set_attr "type"     "idiv")])
6402
6403 (define_insn "divmodtisi3"
6404   [(set (match_operand:TI 0 "register_operand" "=d,d")
6405         (ior:TI
6406           (ashift:TI
6407             (zero_extend:TI
6408               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6409                       (sign_extend:DI
6410                         (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6411             (const_int 64))
6412           (zero_extend:TI
6413             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6414   "TARGET_ZARCH"
6415   "@
6416    dsgfr\t%0,%2
6417    dsgf\t%0,%2"
6418   [(set_attr "op_type"  "RRE,RXY")
6419    (set_attr "type"     "idiv")])
6420
6421 ;
6422 ; udivmoddi4 instruction pattern(s).
6423 ;
6424
6425 (define_expand "udivmoddi4"
6426   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6427                    (udiv:DI (match_operand:DI 1 "general_operand" "")
6428                             (match_operand:DI 2 "nonimmediate_operand" "")))
6429               (set (match_operand:DI 3 "general_operand" "")
6430                    (umod:DI (match_dup 1) (match_dup 2)))])
6431    (clobber (match_dup 4))]
6432   "TARGET_ZARCH"
6433 {
6434   rtx insn, div_equal, mod_equal, equal;
6435
6436   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6437   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6438   equal = gen_rtx_IOR (TImode,
6439                        gen_rtx_ASHIFT (TImode,
6440                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6441                                        GEN_INT (64)),
6442                        gen_rtx_ZERO_EXTEND (TImode, div_equal));
6443
6444   operands[4] = gen_reg_rtx(TImode);
6445   emit_clobber (operands[4]);
6446   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6447   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6448
6449   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6450   set_unique_reg_note (insn, REG_EQUAL, equal);
6451
6452   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6453   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6454
6455   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6456   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6457
6458   DONE;
6459 })
6460
6461 (define_insn "udivmodtidi3"
6462   [(set (match_operand:TI 0 "register_operand" "=d,d")
6463         (ior:TI
6464           (ashift:TI
6465             (zero_extend:TI
6466               (truncate:DI
6467                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6468                          (zero_extend:TI
6469                            (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6470             (const_int 64))
6471           (zero_extend:TI
6472             (truncate:DI
6473               (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6474   "TARGET_ZARCH"
6475   "@
6476    dlgr\t%0,%2
6477    dlg\t%0,%2"
6478   [(set_attr "op_type"  "RRE,RXY")
6479    (set_attr "type"     "idiv")])
6480
6481 ;
6482 ; divmodsi4 instruction pattern(s).
6483 ;
6484
6485 (define_expand "divmodsi4"
6486   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6487                    (div:SI (match_operand:SI 1 "general_operand" "")
6488                            (match_operand:SI 2 "nonimmediate_operand" "")))
6489               (set (match_operand:SI 3 "general_operand" "")
6490                    (mod:SI (match_dup 1) (match_dup 2)))])
6491    (clobber (match_dup 4))]
6492   "!TARGET_ZARCH"
6493 {
6494   rtx insn, div_equal, mod_equal, equal;
6495
6496   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6497   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6498   equal = gen_rtx_IOR (DImode,
6499                        gen_rtx_ASHIFT (DImode,
6500                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6501                                        GEN_INT (32)),
6502                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6503
6504   operands[4] = gen_reg_rtx(DImode);
6505   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6506
6507   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6508   set_unique_reg_note (insn, REG_EQUAL, equal);
6509
6510   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6511   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6512
6513   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6514   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6515
6516   DONE;
6517 })
6518
6519 (define_insn "divmoddisi3"
6520   [(set (match_operand:DI 0 "register_operand" "=d,d")
6521         (ior:DI
6522           (ashift:DI
6523             (zero_extend:DI
6524               (truncate:SI
6525                 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6526                         (sign_extend:DI
6527                           (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6528             (const_int 32))
6529           (zero_extend:DI
6530             (truncate:SI
6531               (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6532   "!TARGET_ZARCH"
6533   "@
6534    dr\t%0,%2
6535    d\t%0,%2"
6536   [(set_attr "op_type"  "RR,RX")
6537    (set_attr "type"     "idiv")])
6538
6539 ;
6540 ; udivsi3 and umodsi3 instruction pattern(s).
6541 ;
6542
6543 (define_expand "udivmodsi4"
6544   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6545                    (udiv:SI (match_operand:SI 1 "general_operand" "")
6546                             (match_operand:SI 2 "nonimmediate_operand" "")))
6547               (set (match_operand:SI 3 "general_operand" "")
6548                    (umod:SI (match_dup 1) (match_dup 2)))])
6549    (clobber (match_dup 4))]
6550   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6551 {
6552   rtx insn, div_equal, mod_equal, equal;
6553
6554   div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6555   mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6556   equal = gen_rtx_IOR (DImode,
6557                        gen_rtx_ASHIFT (DImode,
6558                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6559                                        GEN_INT (32)),
6560                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6561
6562   operands[4] = gen_reg_rtx(DImode);
6563   emit_clobber (operands[4]);
6564   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6565   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6566
6567   insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6568   set_unique_reg_note (insn, REG_EQUAL, equal);
6569
6570   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6571   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6572
6573   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6574   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6575
6576   DONE;
6577 })
6578
6579 (define_insn "udivmoddisi3"
6580   [(set (match_operand:DI 0 "register_operand" "=d,d")
6581         (ior:DI
6582           (ashift:DI
6583             (zero_extend:DI
6584               (truncate:SI
6585                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6586                          (zero_extend:DI
6587                            (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6588             (const_int 32))
6589           (zero_extend:DI
6590             (truncate:SI
6591               (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6592   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6593   "@
6594    dlr\t%0,%2
6595    dl\t%0,%2"
6596   [(set_attr "op_type"  "RRE,RXY")
6597    (set_attr "type"     "idiv")])
6598
6599 (define_expand "udivsi3"
6600   [(set (match_operand:SI 0 "register_operand" "=d")
6601         (udiv:SI (match_operand:SI 1 "general_operand" "")
6602                  (match_operand:SI 2 "general_operand" "")))
6603    (clobber (match_dup 3))]
6604   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6605 {
6606   rtx insn, udiv_equal, umod_equal, equal;
6607
6608   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6609   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6610   equal = gen_rtx_IOR (DImode,
6611                        gen_rtx_ASHIFT (DImode,
6612                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6613                                        GEN_INT (32)),
6614                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6615
6616   operands[3] = gen_reg_rtx (DImode);
6617
6618   if (CONSTANT_P (operands[2]))
6619     {
6620       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6621         {
6622           rtx_code_label *label1 = gen_label_rtx ();
6623
6624           operands[1] = make_safe_from (operands[1], operands[0]);
6625           emit_move_insn (operands[0], const0_rtx);
6626           emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6627                                    SImode, 1, label1);
6628           emit_move_insn (operands[0], const1_rtx);
6629           emit_label (label1);
6630         }
6631       else
6632         {
6633           operands[2] = force_reg (SImode, operands[2]);
6634           operands[2] = make_safe_from (operands[2], operands[0]);
6635
6636           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6637           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6638                                              operands[2]));
6639           set_unique_reg_note (insn, REG_EQUAL, equal);
6640
6641           insn = emit_move_insn (operands[0],
6642                                  gen_lowpart (SImode, operands[3]));
6643           set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6644         }
6645     }
6646   else
6647     {
6648       rtx_code_label *label1 = gen_label_rtx ();
6649       rtx_code_label *label2 = gen_label_rtx ();
6650       rtx_code_label *label3 = gen_label_rtx ();
6651
6652       operands[1] = force_reg (SImode, operands[1]);
6653       operands[1] = make_safe_from (operands[1], operands[0]);
6654       operands[2] = force_reg (SImode, operands[2]);
6655       operands[2] = make_safe_from (operands[2], operands[0]);
6656
6657       emit_move_insn (operands[0], const0_rtx);
6658       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6659                                SImode, 1, label3);
6660       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6661                                SImode, 0, label2);
6662       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6663                                SImode, 0, label1);
6664       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6665       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6666                                          operands[2]));
6667       set_unique_reg_note (insn, REG_EQUAL, equal);
6668
6669       insn = emit_move_insn (operands[0],
6670                              gen_lowpart (SImode, operands[3]));
6671       set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6672
6673       emit_jump (label3);
6674       emit_label (label1);
6675       emit_move_insn (operands[0], operands[1]);
6676       emit_jump (label3);
6677       emit_label (label2);
6678       emit_move_insn (operands[0], const1_rtx);
6679       emit_label (label3);
6680     }
6681   emit_move_insn (operands[0], operands[0]);
6682   DONE;
6683 })
6684
6685 (define_expand "umodsi3"
6686   [(set (match_operand:SI 0 "register_operand" "=d")
6687         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6688                  (match_operand:SI 2 "nonimmediate_operand" "")))
6689    (clobber (match_dup 3))]
6690   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6691 {
6692   rtx insn, udiv_equal, umod_equal, equal;
6693
6694   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6695   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6696   equal = gen_rtx_IOR (DImode,
6697                        gen_rtx_ASHIFT (DImode,
6698                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6699                                        GEN_INT (32)),
6700                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6701
6702   operands[3] = gen_reg_rtx (DImode);
6703
6704   if (CONSTANT_P (operands[2]))
6705     {
6706       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6707         {
6708           rtx_code_label *label1 = gen_label_rtx ();
6709
6710           operands[1] = make_safe_from (operands[1], operands[0]);
6711           emit_move_insn (operands[0], operands[1]);
6712           emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6713                                    SImode, 1, label1);
6714           emit_insn (gen_abssi2 (operands[0], operands[2]));
6715           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6716           emit_label (label1);
6717         }
6718       else
6719         {
6720           operands[2] = force_reg (SImode, operands[2]);
6721           operands[2] = make_safe_from (operands[2], operands[0]);
6722
6723           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6724           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6725                                              operands[2]));
6726           set_unique_reg_note (insn, REG_EQUAL, equal);
6727
6728           insn = emit_move_insn (operands[0],
6729                                  gen_highpart (SImode, operands[3]));
6730           set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6731         }
6732     }
6733   else
6734     {
6735       rtx_code_label *label1 = gen_label_rtx ();
6736       rtx_code_label *label2 = gen_label_rtx ();
6737       rtx_code_label *label3 = gen_label_rtx ();
6738
6739       operands[1] = force_reg (SImode, operands[1]);
6740       operands[1] = make_safe_from (operands[1], operands[0]);
6741       operands[2] = force_reg (SImode, operands[2]);
6742       operands[2] = make_safe_from (operands[2], operands[0]);
6743
6744       emit_move_insn(operands[0], operands[1]);
6745       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6746                                SImode, 1, label3);
6747       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6748                                SImode, 0, label2);
6749       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6750                                SImode, 0, label1);
6751       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6752       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6753                                          operands[2]));
6754       set_unique_reg_note (insn, REG_EQUAL, equal);
6755
6756       insn = emit_move_insn (operands[0],
6757                              gen_highpart (SImode, operands[3]));
6758       set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6759
6760       emit_jump (label3);
6761       emit_label (label1);
6762       emit_move_insn (operands[0], const0_rtx);
6763       emit_jump (label3);
6764       emit_label (label2);
6765       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6766       emit_label (label3);
6767     }
6768   DONE;
6769 })
6770
6771 ;
6772 ; div(df|sf)3 instruction pattern(s).
6773 ;
6774
6775 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6776 (define_insn "div<mode>3"
6777   [(set (match_operand:FP         0 "register_operand"   "=f,   f,<vf>")
6778         (div:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
6779                 (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))]
6780   "TARGET_HARD_FLOAT"
6781   "@
6782    d<xde><bt>r\t%0,<op1>%2
6783    d<xde>b\t%0,%2
6784    wfddb\t%v0,%v1,%v2"
6785   [(set_attr "op_type"      "<RRer>,RXE,VRR")
6786    (set_attr "type"         "fdiv<mode>")
6787    (set_attr "cpu_facility" "*,*,vec")])
6788
6789
6790 ;;
6791 ;;- And instructions.
6792 ;;
6793
6794 (define_expand "and<mode>3"
6795   [(set (match_operand:INT 0 "nonimmediate_operand" "")
6796         (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6797                  (match_operand:INT 2 "general_operand" "")))
6798    (clobber (reg:CC CC_REGNUM))]
6799   ""
6800   "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6801
6802 ;
6803 ; anddi3 instruction pattern(s).
6804 ;
6805
6806 (define_insn "*anddi3_cc"
6807   [(set (reg CC_REGNUM)
6808         (compare
6809           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6810                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6811           (const_int 0)))
6812    (set (match_operand:DI 0 "register_operand"               "=d,d, d,    d")
6813         (and:DI (match_dup 1) (match_dup 2)))]
6814   "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6815   "@
6816    ngr\t%0,%2
6817    ngrk\t%0,%1,%2
6818    ng\t%0,%2
6819    risbg\t%0,%1,%s2,128+%e2,0"
6820   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6821    (set_attr "cpu_facility" "*,z196,*,z10")
6822    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6823
6824 (define_insn "*anddi3_cconly"
6825   [(set (reg CC_REGNUM)
6826         (compare
6827           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6828                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6829                  (const_int 0)))
6830    (clobber (match_scratch:DI 0                              "=d,d, d,    d"))]
6831   "TARGET_ZARCH
6832    && s390_match_ccmode(insn, CCTmode)
6833    /* Do not steal TM patterns.  */
6834    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6835   "@
6836    ngr\t%0,%2
6837    ngrk\t%0,%1,%2
6838    ng\t%0,%2
6839    risbg\t%0,%1,%s2,128+%e2,0"
6840   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6841    (set_attr "cpu_facility" "*,z196,*,z10")
6842    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6843
6844 (define_insn "*anddi3"
6845   [(set (match_operand:DI 0 "nonimmediate_operand"
6846             "=d,d,    d,    d,    d,    d,    d,    d,d,d, d,    d,   AQ,Q")
6847         (and:DI
6848           (match_operand:DI 1 "nonimmediate_operand"
6849             "%d,o,    0,    0,    0,    0,    0,    0,0,d, 0,    d,    0,0")
6850           (match_operand:DI 2 "general_operand"
6851             "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6852    (clobber (reg:CC CC_REGNUM))]
6853   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6854   "@
6855    #
6856    #
6857    nihh\t%0,%j2
6858    nihl\t%0,%j2
6859    nilh\t%0,%j2
6860    nill\t%0,%j2
6861    nihf\t%0,%m2
6862    nilf\t%0,%m2
6863    ngr\t%0,%2
6864    ngrk\t%0,%1,%2
6865    ng\t%0,%2
6866    risbg\t%0,%1,%s2,128+%e2,0
6867    #
6868    #"
6869   [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6870    (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6871    (set_attr "z10prop" "*,
6872                         *,
6873                         z10_super_E1,
6874                         z10_super_E1,
6875                         z10_super_E1,
6876                         z10_super_E1,
6877                         z10_super_E1,
6878                         z10_super_E1,
6879                         z10_super_E1,
6880                         *,
6881                         z10_super_E1,
6882                         z10_super_E1,
6883                         *,
6884                         *")])
6885
6886 (define_split
6887   [(set (match_operand:DI 0 "s_operand" "")
6888         (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6889    (clobber (reg:CC CC_REGNUM))]
6890   "reload_completed"
6891   [(parallel
6892     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6893      (clobber (reg:CC CC_REGNUM))])]
6894   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6895
6896 ;; These two are what combine generates for (ashift (zero_extract)).
6897 (define_insn "*extzv_<mode>_srl"
6898   [(set (match_operand:GPR 0 "register_operand" "=d")
6899         (and:GPR (lshiftrt:GPR
6900                    (match_operand:GPR 1 "register_operand" "d")
6901                    (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6902                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6903    (clobber (reg:CC CC_REGNUM))]
6904   "TARGET_Z10
6905    /* Note that even for the SImode pattern, the rotate is always DImode.  */
6906    && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6907                            INTVAL (operands[3]))"
6908   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6909   [(set_attr "op_type" "RIE")
6910    (set_attr "z10prop" "z10_super_E1")])
6911
6912 (define_insn "*extzv_<mode>_sll"
6913   [(set (match_operand:GPR 0 "register_operand" "=d")
6914         (and:GPR (ashift:GPR
6915                   (match_operand:GPR 1 "register_operand" "d")
6916                   (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6917                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6918    (clobber (reg:CC CC_REGNUM))]
6919   "TARGET_Z10
6920    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6921                            INTVAL (operands[3]))"
6922   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6923   [(set_attr "op_type" "RIE")
6924    (set_attr "z10prop" "z10_super_E1")])
6925
6926
6927 ;
6928 ; andsi3 instruction pattern(s).
6929 ;
6930
6931 (define_insn "*andsi3_cc"
6932   [(set (reg CC_REGNUM)
6933         (compare
6934           (and:SI
6935             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6936             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6937           (const_int 0)))
6938    (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
6939         (and:SI (match_dup 1) (match_dup 2)))]
6940   "s390_match_ccmode(insn, CCTmode)"
6941   "@
6942    nilf\t%0,%o2
6943    nr\t%0,%2
6944    nrk\t%0,%1,%2
6945    n\t%0,%2
6946    ny\t%0,%2
6947    risbg\t%0,%1,%t2,128+%f2,0"
6948   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6949    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6950    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6951                         z10_super_E1,z10_super_E1,z10_super_E1")])
6952
6953 (define_insn "*andsi3_cconly"
6954   [(set (reg CC_REGNUM)
6955         (compare
6956           (and:SI
6957             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6958             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6959           (const_int 0)))
6960    (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
6961   "s390_match_ccmode(insn, CCTmode)
6962    /* Do not steal TM patterns.  */
6963    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6964   "@
6965    nilf\t%0,%o2
6966    nr\t%0,%2
6967    nrk\t%0,%1,%2
6968    n\t%0,%2
6969    ny\t%0,%2
6970    risbg\t%0,%1,%t2,128+%f2,0"
6971   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6972    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6973    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6974                         z10_super_E1,z10_super_E1,z10_super_E1")])
6975
6976 (define_insn "*andsi3_zarch"
6977   [(set (match_operand:SI 0 "nonimmediate_operand"
6978                             "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
6979         (and:SI (match_operand:SI 1 "nonimmediate_operand"
6980                             "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
6981                 (match_operand:SI 2 "general_operand"
6982                             " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6983    (clobber (reg:CC CC_REGNUM))]
6984   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6985   "@
6986    #
6987    #
6988    nilh\t%0,%j2
6989    nill\t%0,%j2
6990    nilf\t%0,%o2
6991    nr\t%0,%2
6992    nrk\t%0,%1,%2
6993    n\t%0,%2
6994    ny\t%0,%2
6995    risbg\t%0,%1,%t2,128+%f2,0
6996    #
6997    #"
6998   [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6999    (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
7000    (set_attr "z10prop" "*,
7001                         *,
7002                         z10_super_E1,
7003                         z10_super_E1,
7004                         z10_super_E1,
7005                         z10_super_E1,
7006                         *,
7007                         z10_super_E1,
7008                         z10_super_E1,
7009                         z10_super_E1,
7010                         *,
7011                         *")])
7012
7013 (define_insn "*andsi3_esa"
7014   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,   AQ,Q")
7015         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,    0,0")
7016                 (match_operand:SI 2 "general_operand"      " d,R,NxQSF,Q")))
7017    (clobber (reg:CC CC_REGNUM))]
7018   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7019   "@
7020    nr\t%0,%2
7021    n\t%0,%2
7022    #
7023    #"
7024   [(set_attr "op_type"  "RR,RX,SI,SS")
7025    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7026
7027
7028 (define_split
7029   [(set (match_operand:SI 0 "s_operand" "")
7030         (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7031    (clobber (reg:CC CC_REGNUM))]
7032   "reload_completed"
7033   [(parallel
7034     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7035      (clobber (reg:CC CC_REGNUM))])]
7036   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7037
7038 ;
7039 ; andhi3 instruction pattern(s).
7040 ;
7041
7042 (define_insn "*andhi3_zarch"
7043   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7044         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7045                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQHF,Q")))
7046    (clobber (reg:CC CC_REGNUM))]
7047   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7048   "@
7049    nr\t%0,%2
7050    nrk\t%0,%1,%2
7051    nill\t%0,%x2
7052    #
7053    #"
7054   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7055    (set_attr "cpu_facility" "*,z196,*,*,*")
7056    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7057 ])
7058
7059 (define_insn "*andhi3_esa"
7060   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7061         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7062                 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7063    (clobber (reg:CC CC_REGNUM))]
7064   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7065   "@
7066    nr\t%0,%2
7067    #
7068    #"
7069   [(set_attr "op_type"  "RR,SI,SS")
7070    (set_attr "z10prop" "z10_super_E1,*,*")
7071 ])
7072
7073 (define_split
7074   [(set (match_operand:HI 0 "s_operand" "")
7075         (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7076    (clobber (reg:CC CC_REGNUM))]
7077   "reload_completed"
7078   [(parallel
7079     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7080      (clobber (reg:CC CC_REGNUM))])]
7081   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7082
7083 ;
7084 ; andqi3 instruction pattern(s).
7085 ;
7086
7087 (define_insn "*andqi3_zarch"
7088   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7089         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7090                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7091    (clobber (reg:CC CC_REGNUM))]
7092   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7093   "@
7094    nr\t%0,%2
7095    nrk\t%0,%1,%2
7096    nill\t%0,%b2
7097    ni\t%S0,%b2
7098    niy\t%S0,%b2
7099    #"
7100   [(set_attr "op_type"  "RR,RRF,RI,SI,SIY,SS")
7101    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7102    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7103
7104 (define_insn "*andqi3_esa"
7105   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7106         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7107                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7108    (clobber (reg:CC CC_REGNUM))]
7109   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7110   "@
7111    nr\t%0,%2
7112    ni\t%S0,%b2
7113    #"
7114   [(set_attr "op_type"  "RR,SI,SS")
7115    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7116
7117 ;
7118 ; Block and (NC) patterns.
7119 ;
7120
7121 (define_insn "*nc"
7122   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7123         (and:BLK (match_dup 0)
7124                  (match_operand:BLK 1 "memory_operand" "Q")))
7125    (use (match_operand 2 "const_int_operand" "n"))
7126    (clobber (reg:CC CC_REGNUM))]
7127   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7128   "nc\t%O0(%2,%R0),%S1"
7129   [(set_attr "op_type" "SS")
7130    (set_attr "z196prop" "z196_cracked")])
7131
7132 (define_split
7133   [(set (match_operand 0 "memory_operand" "")
7134         (and (match_dup 0)
7135              (match_operand 1 "memory_operand" "")))
7136    (clobber (reg:CC CC_REGNUM))]
7137   "reload_completed
7138    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7139    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7140   [(parallel
7141     [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7142      (use (match_dup 2))
7143      (clobber (reg:CC CC_REGNUM))])]
7144 {
7145   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7146   operands[0] = adjust_address (operands[0], BLKmode, 0);
7147   operands[1] = adjust_address (operands[1], BLKmode, 0);
7148 })
7149
7150 (define_peephole2
7151   [(parallel
7152     [(set (match_operand:BLK 0 "memory_operand" "")
7153           (and:BLK (match_dup 0)
7154                    (match_operand:BLK 1 "memory_operand" "")))
7155      (use (match_operand 2 "const_int_operand" ""))
7156      (clobber (reg:CC CC_REGNUM))])
7157    (parallel
7158     [(set (match_operand:BLK 3 "memory_operand" "")
7159           (and:BLK (match_dup 3)
7160                    (match_operand:BLK 4 "memory_operand" "")))
7161      (use (match_operand 5 "const_int_operand" ""))
7162      (clobber (reg:CC CC_REGNUM))])]
7163   "s390_offset_p (operands[0], operands[3], operands[2])
7164    && s390_offset_p (operands[1], operands[4], operands[2])
7165    && !s390_overlap_p (operands[0], operands[1],
7166                        INTVAL (operands[2]) + INTVAL (operands[5]))
7167    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7168   [(parallel
7169     [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7170      (use (match_dup 8))
7171      (clobber (reg:CC CC_REGNUM))])]
7172   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7173    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7174    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7175
7176
7177 ;;
7178 ;;- Bit set (inclusive or) instructions.
7179 ;;
7180
7181 (define_expand "ior<mode>3"
7182   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7183         (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7184                  (match_operand:INT 2 "general_operand" "")))
7185    (clobber (reg:CC CC_REGNUM))]
7186   ""
7187   "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7188
7189 ;
7190 ; iordi3 instruction pattern(s).
7191 ;
7192
7193 (define_insn "*iordi3_cc"
7194   [(set (reg CC_REGNUM)
7195         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7196                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7197                  (const_int 0)))
7198    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7199         (ior:DI (match_dup 1) (match_dup 2)))]
7200   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7201   "@
7202    ogr\t%0,%2
7203    ogrk\t%0,%1,%2
7204    og\t%0,%2"
7205   [(set_attr "op_type"  "RRE,RRF,RXY")
7206    (set_attr "cpu_facility" "*,z196,*")
7207    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7208
7209 (define_insn "*iordi3_cconly"
7210   [(set (reg CC_REGNUM)
7211         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7212                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7213                  (const_int 0)))
7214    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7215   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7216   "@
7217    ogr\t%0,%2
7218    ogrk\t%0,%1,%2
7219    og\t%0,%2"
7220   [(set_attr "op_type"  "RRE,RRF,RXY")
7221    (set_attr "cpu_facility" "*,z196,*")
7222    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7223
7224 (define_insn "*iordi3"
7225   [(set (match_operand:DI 0 "nonimmediate_operand"
7226                                "=d,    d,    d,    d,    d,    d,d,d, d,   AQ,Q")
7227         (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7228                             "   %0,    0,    0,    0,    0,    0,0,d, 0,    0,0")
7229                 (match_operand:DI 2 "general_operand"
7230                             "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7231    (clobber (reg:CC CC_REGNUM))]
7232   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7233   "@
7234    oihh\t%0,%i2
7235    oihl\t%0,%i2
7236    oilh\t%0,%i2
7237    oill\t%0,%i2
7238    oihf\t%0,%k2
7239    oilf\t%0,%k2
7240    ogr\t%0,%2
7241    ogrk\t%0,%1,%2
7242    og\t%0,%2
7243    #
7244    #"
7245   [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7246    (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7247    (set_attr "z10prop" "z10_super_E1,
7248                         z10_super_E1,
7249                         z10_super_E1,
7250                         z10_super_E1,
7251                         z10_super_E1,
7252                         z10_super_E1,
7253                         z10_super_E1,
7254                         *,
7255                         z10_super_E1,
7256                         *,
7257                         *")])
7258
7259 (define_split
7260   [(set (match_operand:DI 0 "s_operand" "")
7261         (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7262    (clobber (reg:CC CC_REGNUM))]
7263   "reload_completed"
7264   [(parallel
7265     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7266      (clobber (reg:CC CC_REGNUM))])]
7267   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7268
7269 ;
7270 ; iorsi3 instruction pattern(s).
7271 ;
7272
7273 (define_insn "*iorsi3_cc"
7274   [(set (reg CC_REGNUM)
7275         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7276                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7277                  (const_int 0)))
7278    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7279         (ior:SI (match_dup 1) (match_dup 2)))]
7280   "s390_match_ccmode(insn, CCTmode)"
7281   "@
7282    oilf\t%0,%o2
7283    or\t%0,%2
7284    ork\t%0,%1,%2
7285    o\t%0,%2
7286    oy\t%0,%2"
7287   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7288    (set_attr "cpu_facility" "*,*,z196,*,*")
7289    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7290
7291 (define_insn "*iorsi3_cconly"
7292   [(set (reg CC_REGNUM)
7293         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7294                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7295                  (const_int 0)))
7296    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7297   "s390_match_ccmode(insn, CCTmode)"
7298   "@
7299    oilf\t%0,%o2
7300    or\t%0,%2
7301    ork\t%0,%1,%2
7302    o\t%0,%2
7303    oy\t%0,%2"
7304   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7305    (set_attr "cpu_facility" "*,*,z196,*,*")
7306    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7307
7308 (define_insn "*iorsi3_zarch"
7309   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,    d, d,d,d,d,d,   AQ,Q")
7310         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,    0, 0,0,d,0,0,    0,0")
7311                 (match_operand:SI 2 "general_operand"   "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7312    (clobber (reg:CC CC_REGNUM))]
7313   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7314   "@
7315    oilh\t%0,%i2
7316    oill\t%0,%i2
7317    oilf\t%0,%o2
7318    or\t%0,%2
7319    ork\t%0,%1,%2
7320    o\t%0,%2
7321    oy\t%0,%2
7322    #
7323    #"
7324   [(set_attr "op_type"  "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7325    (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7326    (set_attr "z10prop" "z10_super_E1,
7327                         z10_super_E1,
7328                         z10_super_E1,
7329                         z10_super_E1,
7330                         *,
7331                         z10_super_E1,
7332                         z10_super_E1,
7333                         *,
7334                         *")])
7335
7336 (define_insn "*iorsi3_esa"
7337   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7338         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7339                 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7340    (clobber (reg:CC CC_REGNUM))]
7341   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7342   "@
7343    or\t%0,%2
7344    o\t%0,%2
7345    #
7346    #"
7347   [(set_attr "op_type"  "RR,RX,SI,SS")
7348    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7349
7350 (define_split
7351   [(set (match_operand:SI 0 "s_operand" "")
7352         (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7353    (clobber (reg:CC CC_REGNUM))]
7354   "reload_completed"
7355   [(parallel
7356     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7357      (clobber (reg:CC CC_REGNUM))])]
7358   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7359
7360 ;
7361 ; iorhi3 instruction pattern(s).
7362 ;
7363
7364 (define_insn "*iorhi3_zarch"
7365   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7366         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7367                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQH0,Q")))
7368    (clobber (reg:CC CC_REGNUM))]
7369   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7370   "@
7371    or\t%0,%2
7372    ork\t%0,%1,%2
7373    oill\t%0,%x2
7374    #
7375    #"
7376   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7377    (set_attr "cpu_facility" "*,z196,*,*,*")
7378    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7379
7380 (define_insn "*iorhi3_esa"
7381   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7382         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7383                 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7384    (clobber (reg:CC CC_REGNUM))]
7385   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7386   "@
7387    or\t%0,%2
7388    #
7389    #"
7390   [(set_attr "op_type"  "RR,SI,SS")
7391    (set_attr "z10prop" "z10_super_E1,*,*")])
7392
7393 (define_split
7394   [(set (match_operand:HI 0 "s_operand" "")
7395         (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7396    (clobber (reg:CC CC_REGNUM))]
7397   "reload_completed"
7398   [(parallel
7399     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7400      (clobber (reg:CC CC_REGNUM))])]
7401   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7402
7403 ;
7404 ; iorqi3 instruction pattern(s).
7405 ;
7406
7407 (define_insn "*iorqi3_zarch"
7408   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7409         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7410                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7411    (clobber (reg:CC CC_REGNUM))]
7412   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7413   "@
7414    or\t%0,%2
7415    ork\t%0,%1,%2
7416    oill\t%0,%b2
7417    oi\t%S0,%b2
7418    oiy\t%S0,%b2
7419    #"
7420   [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7421    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7422    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7423                         z10_super,z10_super,*")])
7424
7425 (define_insn "*iorqi3_esa"
7426   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7427         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7428                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7429    (clobber (reg:CC CC_REGNUM))]
7430   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7431   "@
7432    or\t%0,%2
7433    oi\t%S0,%b2
7434    #"
7435   [(set_attr "op_type"  "RR,SI,SS")
7436    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7437
7438 ;
7439 ; Block inclusive or (OC) patterns.
7440 ;
7441
7442 (define_insn "*oc"
7443   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7444         (ior:BLK (match_dup 0)
7445                  (match_operand:BLK 1 "memory_operand" "Q")))
7446    (use (match_operand 2 "const_int_operand" "n"))
7447    (clobber (reg:CC CC_REGNUM))]
7448   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7449   "oc\t%O0(%2,%R0),%S1"
7450   [(set_attr "op_type" "SS")
7451    (set_attr "z196prop" "z196_cracked")])
7452
7453 (define_split
7454   [(set (match_operand 0 "memory_operand" "")
7455         (ior (match_dup 0)
7456              (match_operand 1 "memory_operand" "")))
7457    (clobber (reg:CC CC_REGNUM))]
7458   "reload_completed
7459    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7460    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7461   [(parallel
7462     [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7463      (use (match_dup 2))
7464      (clobber (reg:CC CC_REGNUM))])]
7465 {
7466   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7467   operands[0] = adjust_address (operands[0], BLKmode, 0);
7468   operands[1] = adjust_address (operands[1], BLKmode, 0);
7469 })
7470
7471 (define_peephole2
7472   [(parallel
7473     [(set (match_operand:BLK 0 "memory_operand" "")
7474           (ior:BLK (match_dup 0)
7475                    (match_operand:BLK 1 "memory_operand" "")))
7476      (use (match_operand 2 "const_int_operand" ""))
7477      (clobber (reg:CC CC_REGNUM))])
7478    (parallel
7479     [(set (match_operand:BLK 3 "memory_operand" "")
7480           (ior:BLK (match_dup 3)
7481                    (match_operand:BLK 4 "memory_operand" "")))
7482      (use (match_operand 5 "const_int_operand" ""))
7483      (clobber (reg:CC CC_REGNUM))])]
7484   "s390_offset_p (operands[0], operands[3], operands[2])
7485    && s390_offset_p (operands[1], operands[4], operands[2])
7486    && !s390_overlap_p (operands[0], operands[1],
7487                        INTVAL (operands[2]) + INTVAL (operands[5]))
7488    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7489   [(parallel
7490     [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7491      (use (match_dup 8))
7492      (clobber (reg:CC CC_REGNUM))])]
7493   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7494    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7495    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7496
7497
7498 ;;
7499 ;;- Xor instructions.
7500 ;;
7501
7502 (define_expand "xor<mode>3"
7503   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7504         (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7505                  (match_operand:INT 2 "general_operand" "")))
7506    (clobber (reg:CC CC_REGNUM))]
7507   ""
7508   "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7509
7510 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7511 ; simplifications.  So its better to have something matching.
7512 (define_split
7513   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7514         (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7515   ""
7516   [(parallel
7517     [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7518      (clobber (reg:CC CC_REGNUM))])]
7519 {
7520   operands[2] = constm1_rtx;
7521   if (!s390_logical_operator_ok_p (operands))
7522     FAIL;
7523 })
7524
7525 ;
7526 ; xordi3 instruction pattern(s).
7527 ;
7528
7529 (define_insn "*xordi3_cc"
7530   [(set (reg CC_REGNUM)
7531         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7532                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7533                  (const_int 0)))
7534    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7535         (xor:DI (match_dup 1) (match_dup 2)))]
7536   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7537   "@
7538    xgr\t%0,%2
7539    xgrk\t%0,%1,%2
7540    xg\t%0,%2"
7541   [(set_attr "op_type" "RRE,RRF,RXY")
7542    (set_attr "cpu_facility" "*,z196,*")
7543    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7544
7545 (define_insn "*xordi3_cconly"
7546   [(set (reg CC_REGNUM)
7547         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7548                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7549                  (const_int 0)))
7550    (clobber (match_scratch:DI 0                                     "=d,d, d"))]
7551   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7552   "@
7553    xgr\t%0,%2
7554    xgrk\t%0,%1,%2
7555    xg\t%0,%2"
7556   [(set_attr "op_type" "RRE,RRF,RXY")
7557    (set_attr "cpu_facility" "*,z196,*")
7558    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7559
7560 (define_insn "*xordi3"
7561   [(set (match_operand:DI 0 "nonimmediate_operand"         "=d,    d,d,d, d,   AQ,Q")
7562         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,    0,0,d, 0,    0,0")
7563                 (match_operand:DI 2 "general_operand"   "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7564    (clobber (reg:CC CC_REGNUM))]
7565   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7566   "@
7567    xihf\t%0,%k2
7568    xilf\t%0,%k2
7569    xgr\t%0,%2
7570    xgrk\t%0,%1,%2
7571    xg\t%0,%2
7572    #
7573    #"
7574   [(set_attr "op_type"  "RIL,RIL,RRE,RRF,RXY,SI,SS")
7575    (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7576    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7577                         *,z10_super_E1,*,*")])
7578
7579 (define_split
7580   [(set (match_operand:DI 0 "s_operand" "")
7581         (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7582    (clobber (reg:CC CC_REGNUM))]
7583   "reload_completed"
7584   [(parallel
7585     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7586      (clobber (reg:CC CC_REGNUM))])]
7587   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7588
7589 ;
7590 ; xorsi3 instruction pattern(s).
7591 ;
7592
7593 (define_insn "*xorsi3_cc"
7594   [(set (reg CC_REGNUM)
7595         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7596                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7597                  (const_int 0)))
7598    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7599         (xor:SI (match_dup 1) (match_dup 2)))]
7600   "s390_match_ccmode(insn, CCTmode)"
7601   "@
7602    xilf\t%0,%o2
7603    xr\t%0,%2
7604    xrk\t%0,%1,%2
7605    x\t%0,%2
7606    xy\t%0,%2"
7607   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7608    (set_attr "cpu_facility" "*,*,z196,*,*")
7609    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7610                         z10_super_E1,z10_super_E1")])
7611
7612 (define_insn "*xorsi3_cconly"
7613   [(set (reg CC_REGNUM)
7614         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7615                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7616                  (const_int 0)))
7617    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7618   "s390_match_ccmode(insn, CCTmode)"
7619   "@
7620    xilf\t%0,%o2
7621    xr\t%0,%2
7622    xrk\t%0,%1,%2
7623    x\t%0,%2
7624    xy\t%0,%2"
7625   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7626    (set_attr "cpu_facility" "*,*,z196,*,*")
7627    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7628                         z10_super_E1,z10_super_E1")])
7629
7630 (define_insn "*xorsi3"
7631   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,d,d,d,   AQ,Q")
7632         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    0,0")
7633                 (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxQS0,Q")))
7634    (clobber (reg:CC CC_REGNUM))]
7635   "s390_logical_operator_ok_p (operands)"
7636   "@
7637    xilf\t%0,%o2
7638    xr\t%0,%2
7639    xrk\t%0,%1,%2
7640    x\t%0,%2
7641    xy\t%0,%2
7642    #
7643    #"
7644   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,SI,SS")
7645    (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7646    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7647                         z10_super_E1,z10_super_E1,*,*")])
7648
7649 (define_split
7650   [(set (match_operand:SI 0 "s_operand" "")
7651         (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7652    (clobber (reg:CC CC_REGNUM))]
7653   "reload_completed"
7654   [(parallel
7655     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7656      (clobber (reg:CC CC_REGNUM))])]
7657   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7658
7659 ;
7660 ; xorhi3 instruction pattern(s).
7661 ;
7662
7663 (define_insn "*xorhi3"
7664   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7665         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d,    0,0")
7666                 (match_operand:HI 2 "general_operand"      "Os,d,d,NxQH0,Q")))
7667    (clobber (reg:CC CC_REGNUM))]
7668   "s390_logical_operator_ok_p (operands)"
7669   "@
7670    xilf\t%0,%x2
7671    xr\t%0,%2
7672    xrk\t%0,%1,%2
7673    #
7674    #"
7675   [(set_attr "op_type"  "RIL,RR,RRF,SI,SS")
7676    (set_attr "cpu_facility" "*,*,z196,*,*")
7677    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7678
7679 (define_split
7680   [(set (match_operand:HI 0 "s_operand" "")
7681         (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7682    (clobber (reg:CC CC_REGNUM))]
7683   "reload_completed"
7684   [(parallel
7685     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7686      (clobber (reg:CC CC_REGNUM))])]
7687   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7688
7689 ;
7690 ; xorqi3 instruction pattern(s).
7691 ;
7692
7693 (define_insn "*xorqi3"
7694   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7695         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7696                 (match_operand:QI 2 "general_operand"      "Os,d,d,n,n,Q")))
7697    (clobber (reg:CC CC_REGNUM))]
7698   "s390_logical_operator_ok_p (operands)"
7699   "@
7700    xilf\t%0,%b2
7701    xr\t%0,%2
7702    xrk\t%0,%1,%2
7703    xi\t%S0,%b2
7704    xiy\t%S0,%b2
7705    #"
7706   [(set_attr "op_type"  "RIL,RR,RRF,SI,SIY,SS")
7707    (set_attr "cpu_facility" "*,*,z196,*,*,*")
7708    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7709
7710
7711 ;
7712 ; Block exclusive or (XC) patterns.
7713 ;
7714
7715 (define_insn "*xc"
7716   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7717         (xor:BLK (match_dup 0)
7718                  (match_operand:BLK 1 "memory_operand" "Q")))
7719    (use (match_operand 2 "const_int_operand" "n"))
7720    (clobber (reg:CC CC_REGNUM))]
7721   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7722   "xc\t%O0(%2,%R0),%S1"
7723   [(set_attr "op_type" "SS")])
7724
7725 (define_split
7726   [(set (match_operand 0 "memory_operand" "")
7727         (xor (match_dup 0)
7728              (match_operand 1 "memory_operand" "")))
7729    (clobber (reg:CC CC_REGNUM))]
7730   "reload_completed
7731    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7732    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7733   [(parallel
7734     [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7735      (use (match_dup 2))
7736      (clobber (reg:CC CC_REGNUM))])]
7737 {
7738   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7739   operands[0] = adjust_address (operands[0], BLKmode, 0);
7740   operands[1] = adjust_address (operands[1], BLKmode, 0);
7741 })
7742
7743 (define_peephole2
7744   [(parallel
7745     [(set (match_operand:BLK 0 "memory_operand" "")
7746           (xor:BLK (match_dup 0)
7747                    (match_operand:BLK 1 "memory_operand" "")))
7748      (use (match_operand 2 "const_int_operand" ""))
7749      (clobber (reg:CC CC_REGNUM))])
7750    (parallel
7751     [(set (match_operand:BLK 3 "memory_operand" "")
7752           (xor:BLK (match_dup 3)
7753                    (match_operand:BLK 4 "memory_operand" "")))
7754      (use (match_operand 5 "const_int_operand" ""))
7755      (clobber (reg:CC CC_REGNUM))])]
7756   "s390_offset_p (operands[0], operands[3], operands[2])
7757    && s390_offset_p (operands[1], operands[4], operands[2])
7758    && !s390_overlap_p (operands[0], operands[1],
7759                        INTVAL (operands[2]) + INTVAL (operands[5]))
7760    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7761   [(parallel
7762     [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7763      (use (match_dup 8))
7764      (clobber (reg:CC CC_REGNUM))])]
7765   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7766    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7767    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7768
7769 ;
7770 ; Block xor (XC) patterns with src == dest.
7771 ;
7772
7773 (define_insn "*xc_zero"
7774   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7775         (const_int 0))
7776    (use (match_operand 1 "const_int_operand" "n"))
7777    (clobber (reg:CC CC_REGNUM))]
7778   "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7779   "xc\t%O0(%1,%R0),%S0"
7780   [(set_attr "op_type" "SS")
7781    (set_attr "z196prop" "z196_cracked")])
7782
7783 (define_peephole2
7784   [(parallel
7785     [(set (match_operand:BLK 0 "memory_operand" "")
7786           (const_int 0))
7787      (use (match_operand 1 "const_int_operand" ""))
7788      (clobber (reg:CC CC_REGNUM))])
7789    (parallel
7790     [(set (match_operand:BLK 2 "memory_operand" "")
7791           (const_int 0))
7792      (use (match_operand 3 "const_int_operand" ""))
7793      (clobber (reg:CC CC_REGNUM))])]
7794   "s390_offset_p (operands[0], operands[2], operands[1])
7795    && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7796   [(parallel
7797     [(set (match_dup 4) (const_int 0))
7798      (use (match_dup 5))
7799      (clobber (reg:CC CC_REGNUM))])]
7800   "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7801    operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7802
7803
7804 ;;
7805 ;;- Negate instructions.
7806 ;;
7807
7808 ;
7809 ; neg(di|si)2 instruction pattern(s).
7810 ;
7811
7812 (define_expand "neg<mode>2"
7813   [(parallel
7814     [(set (match_operand:DSI 0 "register_operand" "=d")
7815           (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7816      (clobber (reg:CC CC_REGNUM))])]
7817   ""
7818   "")
7819
7820 (define_insn "*negdi2_sign_cc"
7821   [(set (reg CC_REGNUM)
7822         (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7823                            (match_operand:SI 1 "register_operand" "d") 0)
7824                            (const_int 32)) (const_int 32)))
7825                  (const_int 0)))
7826    (set (match_operand:DI 0 "register_operand" "=d")
7827         (neg:DI (sign_extend:DI (match_dup 1))))]
7828   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7829   "lcgfr\t%0,%1"
7830   [(set_attr "op_type"  "RRE")
7831    (set_attr "z10prop" "z10_c")])
7832
7833 (define_insn "*negdi2_sign"
7834   [(set (match_operand:DI 0 "register_operand" "=d")
7835         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7836    (clobber (reg:CC CC_REGNUM))]
7837   "TARGET_ZARCH"
7838   "lcgfr\t%0,%1"
7839   [(set_attr "op_type"  "RRE")
7840    (set_attr "z10prop" "z10_c")])
7841
7842 ; lcr, lcgr
7843 (define_insn "*neg<mode>2_cc"
7844   [(set (reg CC_REGNUM)
7845         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7846                  (const_int 0)))
7847    (set (match_operand:GPR 0 "register_operand" "=d")
7848         (neg:GPR (match_dup 1)))]
7849   "s390_match_ccmode (insn, CCAmode)"
7850   "lc<g>r\t%0,%1"
7851   [(set_attr "op_type"  "RR<E>")
7852    (set_attr "z10prop" "z10_super_c_E1")])
7853
7854 ; lcr, lcgr
7855 (define_insn "*neg<mode>2_cconly"
7856   [(set (reg CC_REGNUM)
7857         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7858                  (const_int 0)))
7859    (clobber (match_scratch:GPR 0 "=d"))]
7860   "s390_match_ccmode (insn, CCAmode)"
7861   "lc<g>r\t%0,%1"
7862   [(set_attr "op_type"  "RR<E>")
7863    (set_attr "z10prop" "z10_super_c_E1")])
7864
7865 ; lcr, lcgr
7866 (define_insn "*neg<mode>2"
7867   [(set (match_operand:GPR 0 "register_operand" "=d")
7868         (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7869    (clobber (reg:CC CC_REGNUM))]
7870   ""
7871   "lc<g>r\t%0,%1"
7872   [(set_attr "op_type"  "RR<E>")
7873    (set_attr "z10prop" "z10_super_c_E1")])
7874
7875 (define_insn "*negdi2_31"
7876   [(set (match_operand:DI 0 "register_operand" "=d")
7877         (neg:DI (match_operand:DI 1 "register_operand" "d")))
7878    (clobber (reg:CC CC_REGNUM))]
7879   "!TARGET_ZARCH"
7880   "#")
7881
7882 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7883
7884 ; Doing the twos complement separately on the SImode parts does an
7885 ; unwanted +1 on the high part which needs to be subtracted afterwards
7886 ; ... unless the +1 on the low part created an overflow.
7887
7888 (define_split
7889   [(set (match_operand:DI 0 "register_operand" "")
7890         (neg:DI (match_operand:DI 1 "register_operand" "")))
7891    (clobber (reg:CC CC_REGNUM))]
7892   "!TARGET_ZARCH
7893    && (REGNO (operands[0]) == REGNO (operands[1])
7894       || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7895    && reload_completed"
7896   [(parallel
7897     [(set (match_dup 2) (neg:SI (match_dup 3)))
7898      (clobber (reg:CC CC_REGNUM))])
7899    (parallel
7900     [(set (reg:CCAP CC_REGNUM)
7901           (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7902      (set (match_dup 4) (neg:SI (match_dup 5)))])
7903    (set (pc)
7904         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7905                       (pc)
7906                       (label_ref (match_dup 6))))
7907    (parallel
7908     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7909      (clobber (reg:CC CC_REGNUM))])
7910    (match_dup 6)]
7911   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7912    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7913    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7914    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7915    operands[6] = gen_label_rtx ();")
7916
7917 ; Like above but first make a copy of the low part of the src operand
7918 ; since it might overlap with the high part of the destination.
7919
7920 (define_split
7921   [(set (match_operand:DI 0 "register_operand" "")
7922         (neg:DI (match_operand:DI 1 "register_operand" "")))
7923    (clobber (reg:CC CC_REGNUM))]
7924   "!TARGET_ZARCH
7925    && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7926    && reload_completed"
7927   [; Make a backup of op5 first
7928    (set (match_dup 4) (match_dup 5))
7929    ; Setting op2 here might clobber op5
7930    (parallel
7931     [(set (match_dup 2) (neg:SI (match_dup 3)))
7932      (clobber (reg:CC CC_REGNUM))])
7933    (parallel
7934     [(set (reg:CCAP CC_REGNUM)
7935           (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7936      (set (match_dup 4) (neg:SI (match_dup 4)))])
7937    (set (pc)
7938         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7939                       (pc)
7940                       (label_ref (match_dup 6))))
7941    (parallel
7942     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7943      (clobber (reg:CC CC_REGNUM))])
7944    (match_dup 6)]
7945   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7946    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7947    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7948    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7949    operands[6] = gen_label_rtx ();")
7950
7951 ;
7952 ; neg(df|sf)2 instruction pattern(s).
7953 ;
7954
7955 (define_expand "neg<mode>2"
7956   [(parallel
7957     [(set (match_operand:BFP 0 "register_operand" "=f")
7958           (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7959      (clobber (reg:CC CC_REGNUM))])]
7960   "TARGET_HARD_FLOAT"
7961   "")
7962
7963 ; lcxbr, lcdbr, lcebr
7964 (define_insn "*neg<mode>2_cc"
7965   [(set (reg CC_REGNUM)
7966         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7967                  (match_operand:BFP 2 "const0_operand" "")))
7968    (set (match_operand:BFP 0 "register_operand" "=f")
7969         (neg:BFP (match_dup 1)))]
7970   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7971   "lc<xde>br\t%0,%1"
7972   [(set_attr "op_type"  "RRE")
7973    (set_attr "type"     "fsimp<mode>")])
7974
7975 ; lcxbr, lcdbr, lcebr
7976 (define_insn "*neg<mode>2_cconly"
7977   [(set (reg CC_REGNUM)
7978         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7979                  (match_operand:BFP 2 "const0_operand" "")))
7980    (clobber (match_scratch:BFP 0 "=f"))]
7981   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7982   "lc<xde>br\t%0,%1"
7983   [(set_attr "op_type"  "RRE")
7984    (set_attr "type"     "fsimp<mode>")])
7985
7986 ; lcdfr
7987 (define_insn "*neg<mode>2_nocc"
7988   [(set (match_operand:FP 0 "register_operand"         "=f")
7989         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7990   "TARGET_DFP"
7991   "lcdfr\t%0,%1"
7992   [(set_attr "op_type"  "RRE")
7993    (set_attr "type"     "fsimp<mode>")])
7994
7995 ; lcxbr, lcdbr, lcebr
7996 ; FIXME: wflcdb does not clobber cc
7997 (define_insn "*neg<mode>2"
7998   [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
7999         (neg:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
8000    (clobber (reg:CC CC_REGNUM))]
8001   "TARGET_HARD_FLOAT"
8002   "@
8003    lc<xde>br\t%0,%1
8004    wflcdb\t%0,%1"
8005   [(set_attr "op_type"      "RRE,VRR")
8006    (set_attr "cpu_facility" "*,vec")
8007    (set_attr "type"         "fsimp<mode>,*")])
8008
8009
8010 ;;
8011 ;;- Absolute value instructions.
8012 ;;
8013
8014 ;
8015 ; abs(di|si)2 instruction pattern(s).
8016 ;
8017
8018 (define_insn "*absdi2_sign_cc"
8019   [(set (reg CC_REGNUM)
8020         (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8021                            (match_operand:SI 1 "register_operand" "d") 0)
8022                            (const_int 32)) (const_int 32)))
8023                  (const_int 0)))
8024    (set (match_operand:DI 0 "register_operand" "=d")
8025         (abs:DI (sign_extend:DI (match_dup 1))))]
8026   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8027   "lpgfr\t%0,%1"
8028   [(set_attr "op_type"  "RRE")
8029    (set_attr "z10prop" "z10_c")])
8030
8031 (define_insn "*absdi2_sign"
8032   [(set (match_operand:DI 0 "register_operand" "=d")
8033         (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8034    (clobber (reg:CC CC_REGNUM))]
8035   "TARGET_ZARCH"
8036   "lpgfr\t%0,%1"
8037   [(set_attr "op_type"  "RRE")
8038    (set_attr "z10prop" "z10_c")])
8039
8040 ; lpr, lpgr
8041 (define_insn "*abs<mode>2_cc"
8042   [(set (reg CC_REGNUM)
8043         (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8044                  (const_int 0)))
8045    (set (match_operand:GPR 0 "register_operand" "=d")
8046         (abs:GPR (match_dup 1)))]
8047   "s390_match_ccmode (insn, CCAmode)"
8048   "lp<g>r\t%0,%1"
8049   [(set_attr "op_type"  "RR<E>")
8050    (set_attr "z10prop" "z10_c")])
8051
8052 ; lpr, lpgr
8053 (define_insn "*abs<mode>2_cconly"
8054   [(set (reg CC_REGNUM)
8055         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8056                  (const_int 0)))
8057    (clobber (match_scratch:GPR 0 "=d"))]
8058   "s390_match_ccmode (insn, CCAmode)"
8059   "lp<g>r\t%0,%1"
8060   [(set_attr "op_type"  "RR<E>")
8061    (set_attr "z10prop" "z10_c")])
8062
8063 ; lpr, lpgr
8064 (define_insn "abs<mode>2"
8065   [(set (match_operand:GPR 0 "register_operand" "=d")
8066         (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8067    (clobber (reg:CC CC_REGNUM))]
8068   ""
8069   "lp<g>r\t%0,%1"
8070   [(set_attr "op_type"  "RR<E>")
8071    (set_attr "z10prop" "z10_c")])
8072
8073 ;
8074 ; abs(df|sf)2 instruction pattern(s).
8075 ;
8076
8077 (define_expand "abs<mode>2"
8078   [(parallel
8079     [(set (match_operand:BFP 0 "register_operand" "=f")
8080           (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8081      (clobber (reg:CC CC_REGNUM))])]
8082   "TARGET_HARD_FLOAT"
8083   "")
8084
8085 ; lpxbr, lpdbr, lpebr
8086 (define_insn "*abs<mode>2_cc"
8087   [(set (reg CC_REGNUM)
8088         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8089                  (match_operand:BFP 2 "const0_operand" "")))
8090    (set (match_operand:BFP 0 "register_operand" "=f")
8091         (abs:BFP (match_dup 1)))]
8092   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8093   "lp<xde>br\t%0,%1"
8094   [(set_attr "op_type"  "RRE")
8095    (set_attr "type"     "fsimp<mode>")])
8096
8097 ; lpxbr, lpdbr, lpebr
8098 (define_insn "*abs<mode>2_cconly"
8099   [(set (reg CC_REGNUM)
8100         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8101                  (match_operand:BFP 2 "const0_operand" "")))
8102    (clobber (match_scratch:BFP 0 "=f"))]
8103   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8104   "lp<xde>br\t%0,%1"
8105   [(set_attr "op_type"  "RRE")
8106    (set_attr "type"     "fsimp<mode>")])
8107
8108 ; lpdfr
8109 (define_insn "*abs<mode>2_nocc"
8110   [(set (match_operand:FP 0 "register_operand"         "=f")
8111         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8112   "TARGET_DFP"
8113   "lpdfr\t%0,%1"
8114   [(set_attr "op_type"  "RRE")
8115    (set_attr "type"     "fsimp<mode>")])
8116
8117 ; lpxbr, lpdbr, lpebr
8118 ; FIXME: wflpdb does not clobber cc
8119 (define_insn "*abs<mode>2"
8120   [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
8121         (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
8122    (clobber (reg:CC CC_REGNUM))]
8123   "TARGET_HARD_FLOAT"
8124   "@
8125     lp<xde>br\t%0,%1
8126     wflpdb\t%0,%1"
8127   [(set_attr "op_type"      "RRE,VRR")
8128    (set_attr "cpu_facility" "*,vec")
8129    (set_attr "type"         "fsimp<mode>,*")])
8130
8131
8132 ;;
8133 ;;- Negated absolute value instructions
8134 ;;
8135
8136 ;
8137 ; Integer
8138 ;
8139
8140 (define_insn "*negabsdi2_sign_cc"
8141   [(set (reg CC_REGNUM)
8142         (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8143                            (match_operand:SI 1 "register_operand" "d") 0)
8144                            (const_int 32)) (const_int 32))))
8145                  (const_int 0)))
8146    (set (match_operand:DI 0 "register_operand" "=d")
8147         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8148   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8149   "lngfr\t%0,%1"
8150   [(set_attr "op_type"  "RRE")
8151    (set_attr "z10prop" "z10_c")])
8152
8153 (define_insn "*negabsdi2_sign"
8154   [(set (match_operand:DI 0 "register_operand" "=d")
8155         (neg:DI (abs:DI (sign_extend:DI
8156                           (match_operand:SI 1 "register_operand" "d")))))
8157    (clobber (reg:CC CC_REGNUM))]
8158   "TARGET_ZARCH"
8159   "lngfr\t%0,%1"
8160   [(set_attr "op_type" "RRE")
8161    (set_attr "z10prop" "z10_c")])
8162
8163 ; lnr, lngr
8164 (define_insn "*negabs<mode>2_cc"
8165   [(set (reg CC_REGNUM)
8166         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8167                  (const_int 0)))
8168    (set (match_operand:GPR 0 "register_operand" "=d")
8169         (neg:GPR (abs:GPR (match_dup 1))))]
8170   "s390_match_ccmode (insn, CCAmode)"
8171   "ln<g>r\t%0,%1"
8172   [(set_attr "op_type"  "RR<E>")
8173    (set_attr "z10prop" "z10_c")])
8174
8175 ; lnr, lngr
8176 (define_insn "*negabs<mode>2_cconly"
8177   [(set (reg CC_REGNUM)
8178         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8179                  (const_int 0)))
8180    (clobber (match_scratch:GPR 0 "=d"))]
8181   "s390_match_ccmode (insn, CCAmode)"
8182   "ln<g>r\t%0,%1"
8183   [(set_attr "op_type"  "RR<E>")
8184    (set_attr "z10prop" "z10_c")])
8185
8186 ; lnr, lngr
8187 (define_insn "*negabs<mode>2"
8188   [(set (match_operand:GPR 0 "register_operand" "=d")
8189         (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8190    (clobber (reg:CC CC_REGNUM))]
8191   ""
8192   "ln<g>r\t%0,%1"
8193   [(set_attr "op_type" "RR<E>")
8194    (set_attr "z10prop" "z10_c")])
8195
8196 ;
8197 ; Floating point
8198 ;
8199
8200 ; lnxbr, lndbr, lnebr
8201 (define_insn "*negabs<mode>2_cc"
8202   [(set (reg CC_REGNUM)
8203         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8204                  (match_operand:BFP 2 "const0_operand" "")))
8205    (set (match_operand:BFP 0 "register_operand" "=f")
8206         (neg:BFP (abs:BFP (match_dup 1))))]
8207   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8208   "ln<xde>br\t%0,%1"
8209   [(set_attr "op_type"  "RRE")
8210    (set_attr "type"     "fsimp<mode>")])
8211
8212 ; lnxbr, lndbr, lnebr
8213 (define_insn "*negabs<mode>2_cconly"
8214   [(set (reg CC_REGNUM)
8215         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8216                  (match_operand:BFP 2 "const0_operand" "")))
8217    (clobber (match_scratch:BFP 0 "=f"))]
8218   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8219   "ln<xde>br\t%0,%1"
8220   [(set_attr "op_type"  "RRE")
8221    (set_attr "type"     "fsimp<mode>")])
8222
8223 ; lndfr
8224 (define_insn "*negabs<mode>2_nocc"
8225   [(set (match_operand:FP 0 "register_operand"                  "=f")
8226         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8227   "TARGET_DFP"
8228   "lndfr\t%0,%1"
8229   [(set_attr "op_type"  "RRE")
8230    (set_attr "type"     "fsimp<mode>")])
8231
8232 ; lnxbr, lndbr, lnebr
8233 ; FIXME: wflndb does not clobber cc
8234 (define_insn "*negabs<mode>2"
8235   [(set (match_operand:BFP                   0 "register_operand" "=f,<vf>")
8236         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>"))))
8237    (clobber (reg:CC CC_REGNUM))]
8238   "TARGET_HARD_FLOAT"
8239   "@
8240    ln<xde>br\t%0,%1
8241    wflndb\t%0,%1"
8242   [(set_attr "op_type"      "RRE,VRR")
8243    (set_attr "cpu_facility" "*,vec")
8244    (set_attr "type"         "fsimp<mode>,*")])
8245
8246 ;;
8247 ;;- Square root instructions.
8248 ;;
8249
8250 ;
8251 ; sqrt(df|sf)2 instruction pattern(s).
8252 ;
8253
8254 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8255 (define_insn "sqrt<mode>2"
8256   [(set (match_operand:BFP           0 "register_operand" "=f,   f,<vf>")
8257         (sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,<Rf>,<vf>")))]
8258   "TARGET_HARD_FLOAT"
8259   "@
8260    sq<xde>br\t%0,%1
8261    sq<xde>b\t%0,%1
8262    wfsqdb\t%v0,%v1"
8263   [(set_attr "op_type"      "RRE,RXE,VRR")
8264    (set_attr "type"         "fsqrt<mode>")
8265    (set_attr "cpu_facility" "*,*,vec")])
8266
8267
8268 ;;
8269 ;;- One complement instructions.
8270 ;;
8271
8272 ;
8273 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8274 ;
8275
8276 (define_expand "one_cmpl<mode>2"
8277   [(parallel
8278     [(set (match_operand:INT 0 "register_operand" "")
8279           (xor:INT (match_operand:INT 1 "register_operand" "")
8280                    (const_int -1)))
8281      (clobber (reg:CC CC_REGNUM))])]
8282   ""
8283   "")
8284
8285
8286 ;;
8287 ;; Find leftmost bit instructions.
8288 ;;
8289
8290 (define_expand "clzdi2"
8291   [(set (match_operand:DI 0 "register_operand" "=d")
8292         (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8293   "TARGET_EXTIMM && TARGET_ZARCH"
8294 {
8295   rtx insn, clz_equal;
8296   rtx wide_reg = gen_reg_rtx (TImode);
8297   rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8298
8299   clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8300
8301   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8302
8303   insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8304   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8305
8306   DONE;
8307 })
8308
8309 (define_insn "clztidi2"
8310   [(set (match_operand:TI 0 "register_operand" "=d")
8311         (ior:TI
8312           (ashift:TI
8313             (zero_extend:TI
8314               (xor:DI (match_operand:DI 1 "register_operand" "d")
8315                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8316                                 (subreg:SI (clz:DI (match_dup 1)) 4))))
8317
8318             (const_int 64))
8319           (zero_extend:TI (clz:DI (match_dup 1)))))
8320    (clobber (reg:CC CC_REGNUM))]
8321   "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8322    == (unsigned HOST_WIDE_INT) 1 << 63
8323    && TARGET_EXTIMM && TARGET_ZARCH"
8324   "flogr\t%0,%1"
8325   [(set_attr "op_type"  "RRE")])
8326
8327
8328 ;;
8329 ;;- Rotate instructions.
8330 ;;
8331
8332 ;
8333 ; rotl(di|si)3 instruction pattern(s).
8334 ;
8335
8336 ; rll, rllg
8337 (define_insn "rotl<mode>3"
8338   [(set (match_operand:GPR 0 "register_operand" "=d")
8339         (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8340                     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8341   "TARGET_CPU_ZARCH"
8342   "rll<g>\t%0,%1,%Y2"
8343   [(set_attr "op_type"  "RSE")
8344    (set_attr "atype"    "reg")
8345    (set_attr "z10prop" "z10_super_E1")])
8346
8347 ; rll, rllg
8348 (define_insn "*rotl<mode>3_and"
8349   [(set (match_operand:GPR 0 "register_operand" "=d")
8350         (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8351                     (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8352                             (match_operand:SI 3 "const_int_operand"   "n"))))]
8353   "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8354   "rll<g>\t%0,%1,%Y2"
8355   [(set_attr "op_type"  "RSE")
8356    (set_attr "atype"    "reg")
8357    (set_attr "z10prop" "z10_super_E1")])
8358
8359
8360 ;;
8361 ;;- Shift instructions.
8362 ;;
8363
8364 ;
8365 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8366 ; Left shifts and logical right shifts
8367
8368 (define_expand "<shift><mode>3"
8369   [(set (match_operand:DSI 0 "register_operand" "")
8370         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8371                    (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
8372   ""
8373   "")
8374
8375 ; sldl, srdl
8376 (define_insn "*<shift>di3_31"
8377   [(set (match_operand:DI 0 "register_operand" "=d")
8378         (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8379                   (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
8380   "!TARGET_ZARCH"
8381   "s<lr>dl\t%0,%Y2"
8382   [(set_attr "op_type"  "RS")
8383    (set_attr "atype"    "reg")
8384    (set_attr "z196prop" "z196_cracked")])
8385
8386 ; sll, srl, sllg, srlg, sllk, srlk
8387 (define_insn "*<shift><mode>3"
8388   [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
8389         (SHIFT:GPR (match_operand:GPR 1 "register_operand"             "<d0>,d")
8390                    (match_operand:SI 2 "shift_count_or_setmem_operand"    "Y,Y")))]
8391   ""
8392   "@
8393    s<lr>l<g>\t%0,<1>%Y2
8394    s<lr>l<gk>\t%0,%1,%Y2"
8395   [(set_attr "op_type"  "RS<E>,RSY")
8396    (set_attr "atype"    "reg,reg")
8397    (set_attr "cpu_facility" "*,z196")
8398    (set_attr "z10prop" "z10_super_E1,*")])
8399
8400 ; sldl, srdl
8401 (define_insn "*<shift>di3_31_and"
8402   [(set (match_operand:DI 0 "register_operand" "=d")
8403         (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8404                   (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8405                           (match_operand:SI 3 "const_int_operand"   "n"))))]
8406   "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8407   "s<lr>dl\t%0,%Y2"
8408   [(set_attr "op_type"  "RS")
8409    (set_attr "atype"    "reg")])
8410
8411 ; sll, srl, sllg, srlg, sllk, srlk
8412 (define_insn "*<shift><mode>3_and"
8413   [(set (match_operand:GPR 0 "register_operand"                                 "=d,d")
8414         (SHIFT:GPR (match_operand:GPR 1 "register_operand"                    "<d0>,d")
8415                    (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand"   "Y,Y")
8416                            (match_operand:SI 3 "const_int_operand"               "n,n"))))]
8417   "(INTVAL (operands[3]) & 63) == 63"
8418   "@
8419    s<lr>l<g>\t%0,<1>%Y2
8420    s<lr>l<gk>\t%0,%1,%Y2"
8421   [(set_attr "op_type"  "RS<E>,RSY")
8422    (set_attr "atype"    "reg,reg")
8423    (set_attr "cpu_facility" "*,z196")
8424    (set_attr "z10prop" "z10_super_E1,*")])
8425
8426 ;
8427 ; ashr(di|si)3 instruction pattern(s).
8428 ; Arithmetic right shifts
8429
8430 (define_expand "ashr<mode>3"
8431   [(parallel
8432     [(set (match_operand:DSI 0 "register_operand" "")
8433           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8434                         (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
8435      (clobber (reg:CC CC_REGNUM))])]
8436   ""
8437   "")
8438
8439 (define_insn "*ashrdi3_cc_31"
8440   [(set (reg CC_REGNUM)
8441         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8442                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8443                  (const_int 0)))
8444    (set (match_operand:DI 0 "register_operand" "=d")
8445         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8446   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8447   "srda\t%0,%Y2"
8448   [(set_attr "op_type"  "RS")
8449    (set_attr "atype"    "reg")])
8450
8451 (define_insn "*ashrdi3_cconly_31"
8452   [(set (reg CC_REGNUM)
8453         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8454                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
8455                  (const_int 0)))
8456    (clobber (match_scratch:DI 0 "=d"))]
8457   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
8458   "srda\t%0,%Y2"
8459   [(set_attr "op_type"  "RS")
8460    (set_attr "atype"    "reg")])
8461
8462 (define_insn "*ashrdi3_31"
8463   [(set (match_operand:DI 0 "register_operand" "=d")
8464         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8465                      (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
8466    (clobber (reg:CC CC_REGNUM))]
8467   "!TARGET_ZARCH"
8468   "srda\t%0,%Y2"
8469   [(set_attr "op_type"  "RS")
8470    (set_attr "atype"    "reg")])
8471
8472 ; sra, srag, srak
8473 (define_insn "*ashr<mode>3_cc"
8474   [(set (reg CC_REGNUM)
8475         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8476                                (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8477                  (const_int 0)))
8478    (set (match_operand:GPR 0 "register_operand"                                   "=d,d")
8479         (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
8480   "s390_match_ccmode(insn, CCSmode)"
8481   "@
8482    sra<g>\t%0,<1>%Y2
8483    sra<gk>\t%0,%1,%Y2"
8484   [(set_attr "op_type"  "RS<E>,RSY")
8485    (set_attr "atype"    "reg,reg")
8486    (set_attr "cpu_facility" "*,z196")
8487    (set_attr "z10prop" "z10_super_E1,*")])
8488
8489 ; sra, srag, srak
8490 (define_insn "*ashr<mode>3_cconly"
8491   [(set (reg CC_REGNUM)
8492         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8493                                (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8494                  (const_int 0)))
8495    (clobber (match_scratch:GPR 0                                                  "=d,d"))]
8496   "s390_match_ccmode(insn, CCSmode)"
8497   "@
8498    sra<g>\t%0,<1>%Y2
8499    sra<gk>\t%0,%1,%Y2"
8500   [(set_attr "op_type"  "RS<E>,RSY")
8501    (set_attr "atype"    "reg,reg")
8502    (set_attr "cpu_facility" "*,z196")
8503    (set_attr "z10prop" "z10_super_E1,*")])
8504
8505 ; sra, srag
8506 (define_insn "*ashr<mode>3"
8507   [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
8508         (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
8509                       (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8510    (clobber (reg:CC CC_REGNUM))]
8511   ""
8512   "@
8513    sra<g>\t%0,<1>%Y2
8514    sra<gk>\t%0,%1,%Y2"
8515   [(set_attr "op_type"  "RS<E>,RSY")
8516    (set_attr "atype"    "reg,reg")
8517    (set_attr "cpu_facility" "*,z196")
8518    (set_attr "z10prop" "z10_super_E1,*")])
8519
8520
8521 ; shift pattern with implicit ANDs
8522
8523 (define_insn "*ashrdi3_cc_31_and"
8524   [(set (reg CC_REGNUM)
8525         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8526                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8527                                       (match_operand:SI 3 "const_int_operand"   "n")))
8528                  (const_int 0)))
8529    (set (match_operand:DI 0 "register_operand" "=d")
8530         (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8531   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8532    && (INTVAL (operands[3]) & 63) == 63"
8533   "srda\t%0,%Y2"
8534   [(set_attr "op_type"  "RS")
8535    (set_attr "atype"    "reg")])
8536
8537 (define_insn "*ashrdi3_cconly_31_and"
8538   [(set (reg CC_REGNUM)
8539         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8540                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8541                                       (match_operand:SI 3 "const_int_operand"   "n")))
8542                  (const_int 0)))
8543    (clobber (match_scratch:DI 0 "=d"))]
8544   "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8545    && (INTVAL (operands[3]) & 63) == 63"
8546   "srda\t%0,%Y2"
8547   [(set_attr "op_type"  "RS")
8548    (set_attr "atype"    "reg")])
8549
8550 (define_insn "*ashrdi3_31_and"
8551   [(set (match_operand:DI 0 "register_operand" "=d")
8552         (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8553                      (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8554                              (match_operand:SI 3 "const_int_operand"   "n"))))
8555    (clobber (reg:CC CC_REGNUM))]
8556   "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8557   "srda\t%0,%Y2"
8558   [(set_attr "op_type"  "RS")
8559    (set_attr "atype"    "reg")])
8560
8561 ; sra, srag, srak
8562 (define_insn "*ashr<mode>3_cc_and"
8563   [(set (reg CC_REGNUM)
8564         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8565                                (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8566                                        (match_operand:SI 3 "const_int_operand"             "n,n")))
8567                  (const_int 0)))
8568    (set (match_operand:GPR 0 "register_operand"                                           "=d,d")
8569         (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8570   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8571   "@
8572    sra<g>\t%0,<1>%Y2
8573    sra<gk>\t%0,%1,%Y2"
8574   [(set_attr "op_type"  "RS<E>,RSY")
8575    (set_attr "atype"    "reg,reg")
8576    (set_attr "cpu_facility" "*,z196")
8577    (set_attr "z10prop" "z10_super_E1,*")])
8578
8579 ; sra, srag, srak
8580 (define_insn "*ashr<mode>3_cconly_and"
8581   [(set (reg CC_REGNUM)
8582         (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8583                                (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8584                                        (match_operand:SI 3 "const_int_operand"             "n,n")))
8585                  (const_int 0)))
8586    (clobber (match_scratch:GPR 0                                                          "=d,d"))]
8587   "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8588   "@
8589    sra<g>\t%0,<1>%Y2
8590    sra<gk>\t%0,%1,%Y2"
8591   [(set_attr "op_type"  "RS<E>,RSY")
8592    (set_attr "atype"    "reg,reg")
8593    (set_attr "cpu_facility" "*,z196")
8594    (set_attr "z10prop" "z10_super_E1,*")])
8595
8596 ; sra, srag, srak
8597 (define_insn "*ashr<mode>3_and"
8598   [(set (match_operand:GPR 0 "register_operand"                                  "=d,d")
8599         (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
8600                       (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8601                               (match_operand:SI 3 "const_int_operand"             "n,n"))))
8602    (clobber (reg:CC CC_REGNUM))]
8603   "(INTVAL (operands[3]) & 63) == 63"
8604   "@
8605    sra<g>\t%0,<1>%Y2
8606    sra<gk>\t%0,%1,%Y2"
8607   [(set_attr "op_type"  "RS<E>,RSY")
8608    (set_attr "atype"    "reg,reg")
8609    (set_attr "cpu_facility" "*,z196")
8610    (set_attr "z10prop" "z10_super_E1,*")])
8611
8612
8613 ;;
8614 ;; Branch instruction patterns.
8615 ;;
8616
8617 (define_expand "cbranch<mode>4"
8618   [(set (pc)
8619         (if_then_else (match_operator 0 "comparison_operator"
8620                        [(match_operand:GPR 1 "register_operand" "")
8621                         (match_operand:GPR 2 "general_operand" "")])
8622                       (label_ref (match_operand 3 "" ""))
8623                       (pc)))]
8624   ""
8625   "s390_emit_jump (operands[3],
8626     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8627    DONE;")
8628
8629 (define_expand "cbranch<mode>4"
8630   [(set (pc)
8631         (if_then_else (match_operator 0 "comparison_operator"
8632                        [(match_operand:FP 1 "register_operand" "")
8633                         (match_operand:FP 2 "general_operand" "")])
8634                       (label_ref (match_operand 3 "" ""))
8635                       (pc)))]
8636   "TARGET_HARD_FLOAT"
8637   "s390_emit_jump (operands[3],
8638     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8639    DONE;")
8640
8641 (define_expand "cbranchcc4"
8642   [(set (pc)
8643         (if_then_else (match_operator 0 "s390_comparison"
8644                        [(match_operand 1 "cc_reg_operand" "")
8645                         (match_operand 2 "const_int_operand" "")])
8646                       (label_ref (match_operand 3 "" ""))
8647                       (pc)))]
8648   ""
8649   "")
8650
8651
8652 ;;
8653 ;;- Conditional jump instructions.
8654 ;;
8655
8656 (define_insn "*cjump_64"
8657   [(set (pc)
8658         (if_then_else
8659           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8660                                                (match_operand 2 "const_int_operand" "")])
8661           (label_ref (match_operand 0 "" ""))
8662           (pc)))]
8663   "TARGET_CPU_ZARCH"
8664 {
8665   if (get_attr_length (insn) == 4)
8666     return "j%C1\t%l0";
8667   else
8668     return "jg%C1\t%l0";
8669 }
8670   [(set_attr "op_type" "RI")
8671    (set_attr "type"    "branch")
8672    (set (attr "length")
8673         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8674                       (const_int 4) (const_int 6)))])
8675
8676 (define_insn "*cjump_31"
8677   [(set (pc)
8678         (if_then_else
8679           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8680                                                (match_operand 2 "const_int_operand" "")])
8681           (label_ref (match_operand 0 "" ""))
8682           (pc)))]
8683   "!TARGET_CPU_ZARCH"
8684 {
8685   gcc_assert (get_attr_length (insn) == 4);
8686   return "j%C1\t%l0";
8687 }
8688   [(set_attr "op_type" "RI")
8689    (set_attr "type"    "branch")
8690    (set (attr "length")
8691         (if_then_else (not (match_test "flag_pic"))
8692           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8693                         (const_int 4) (const_int 6))
8694           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8695                         (const_int 4) (const_int 8))))])
8696
8697 (define_insn "*cjump_long"
8698   [(set (pc)
8699         (if_then_else
8700           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8701           (match_operand 0 "address_operand" "ZQZR")
8702           (pc)))]
8703   ""
8704 {
8705   if (get_attr_op_type (insn) == OP_TYPE_RR)
8706     return "b%C1r\t%0";
8707   else
8708     return "b%C1\t%a0";
8709 }
8710   [(set (attr "op_type")
8711         (if_then_else (match_operand 0 "register_operand" "")
8712                       (const_string "RR") (const_string "RX")))
8713    (set_attr "type"  "branch")
8714    (set_attr "atype" "agen")])
8715
8716 ;; A conditional return instruction.
8717 (define_insn "*c<code>"
8718   [(set (pc)
8719         (if_then_else
8720           (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8721           (ANY_RETURN)
8722           (pc)))]
8723   "s390_can_use_<code>_insn ()"
8724   "b%C0r\t%%r14"
8725   [(set_attr "op_type" "RR")
8726    (set_attr "type"  "jsr")
8727    (set_attr "atype" "agen")])
8728
8729 ;;
8730 ;;- Negated conditional jump instructions.
8731 ;;
8732
8733 (define_insn "*icjump_64"
8734   [(set (pc)
8735         (if_then_else
8736           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8737           (pc)
8738           (label_ref (match_operand 0 "" ""))))]
8739   "TARGET_CPU_ZARCH"
8740 {
8741   if (get_attr_length (insn) == 4)
8742     return "j%D1\t%l0";
8743   else
8744     return "jg%D1\t%l0";
8745 }
8746   [(set_attr "op_type" "RI")
8747    (set_attr "type"    "branch")
8748    (set (attr "length")
8749         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8750                       (const_int 4) (const_int 6)))])
8751
8752 (define_insn "*icjump_31"
8753   [(set (pc)
8754         (if_then_else
8755           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8756           (pc)
8757           (label_ref (match_operand 0 "" ""))))]
8758   "!TARGET_CPU_ZARCH"
8759 {
8760   gcc_assert (get_attr_length (insn) == 4);
8761   return "j%D1\t%l0";
8762 }
8763   [(set_attr "op_type" "RI")
8764    (set_attr "type"    "branch")
8765    (set (attr "length")
8766         (if_then_else (not (match_test "flag_pic"))
8767           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8768                         (const_int 4) (const_int 6))
8769           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8770                         (const_int 4) (const_int 8))))])
8771
8772 (define_insn "*icjump_long"
8773   [(set (pc)
8774         (if_then_else
8775           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8776           (pc)
8777           (match_operand 0 "address_operand" "ZQZR")))]
8778   ""
8779 {
8780   if (get_attr_op_type (insn) == OP_TYPE_RR)
8781     return "b%D1r\t%0";
8782   else
8783     return "b%D1\t%a0";
8784 }
8785   [(set (attr "op_type")
8786         (if_then_else (match_operand 0 "register_operand" "")
8787                       (const_string "RR") (const_string "RX")))
8788    (set_attr "type"  "branch")
8789    (set_attr "atype" "agen")])
8790
8791 ;;
8792 ;;- Trap instructions.
8793 ;;
8794
8795 (define_insn "trap"
8796   [(trap_if (const_int 1) (const_int 0))]
8797   ""
8798   "j\t.+2"
8799   [(set_attr "op_type" "RI")
8800    (set_attr "type"  "branch")])
8801
8802 (define_expand "ctrap<mode>4"
8803   [(trap_if (match_operator 0 "comparison_operator"
8804              [(match_operand:GPR 1 "register_operand" "")
8805               (match_operand:GPR 2 "general_operand" "")])
8806              (match_operand 3 "const0_operand" ""))]
8807   ""
8808   {
8809     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8810                                   operands[1], operands[2]);
8811     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8812     DONE;
8813   })
8814
8815 (define_expand "ctrap<mode>4"
8816   [(trap_if (match_operator 0 "comparison_operator"
8817              [(match_operand:FP 1 "register_operand" "")
8818               (match_operand:FP 2 "general_operand" "")])
8819              (match_operand 3 "const0_operand" ""))]
8820   ""
8821   {
8822     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8823                                   operands[1], operands[2]);
8824     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8825     DONE;
8826   })
8827
8828 (define_insn "condtrap"
8829   [(trap_if (match_operator 0 "s390_comparison"
8830              [(match_operand 1 "cc_reg_operand" "c")
8831               (const_int 0)])
8832             (const_int 0))]
8833   ""
8834   "j%C0\t.+2";
8835   [(set_attr "op_type" "RI")
8836    (set_attr "type"  "branch")])
8837
8838 ; crt, cgrt, cit, cgit
8839 (define_insn "*cmp_and_trap_signed_int<mode>"
8840   [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8841                [(match_operand:GPR 1 "register_operand"  "d,d")
8842                 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8843             (const_int 0))]
8844   "TARGET_Z10"
8845   "@
8846    c<g>rt%C0\t%1,%2
8847    c<g>it%C0\t%1,%h2"
8848   [(set_attr "op_type" "RRF,RIE")
8849    (set_attr "type"    "branch")
8850    (set_attr "z10prop" "z10_super_c,z10_super")])
8851
8852 ; clrt, clgrt, clfit, clgit, clt, clgt
8853 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8854   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8855                [(match_operand:GPR 1 "register_operand" "d,d, d")
8856                 (match_operand:GPR 2 "general_operand"  "d,D,RT")])
8857             (const_int 0))]
8858   "TARGET_Z10"
8859   "@
8860    cl<g>rt%C0\t%1,%2
8861    cl<gf>it%C0\t%1,%x2
8862    cl<g>t%C0\t%1,%2"
8863   [(set_attr "op_type"      "RRF,RIE,RSY")
8864    (set_attr "type"         "branch")
8865    (set_attr "z10prop"      "z10_super_c,z10_super,*")
8866    (set_attr "cpu_facility" "z10,z10,zEC12")])
8867
8868 ; lat, lgat
8869 (define_insn "*load_and_trap<mode>"
8870   [(trap_if (eq (match_operand:GPR 0 "memory_operand"  "RT")
8871                 (const_int 0))
8872             (const_int 0))
8873    (set (match_operand:GPR 1 "register_operand" "=d")
8874         (match_dup 0))]
8875   "TARGET_ZEC12"
8876   "l<g>at\t%1,%0"
8877   [(set_attr "op_type" "RXY")])
8878
8879
8880 ;;
8881 ;;- Loop instructions.
8882 ;;
8883 ;;  This is all complicated by the fact that since this is a jump insn
8884 ;;  we must handle our own output reloads.
8885
8886 ;; branch on index
8887
8888 ; This splitter will be matched by combine and has to add the 2 moves
8889 ; necessary to load the compare and the increment values into a
8890 ; register pair as needed by brxle.
8891
8892 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8893   [(set (pc)
8894         (if_then_else
8895          (match_operator 6 "s390_brx_operator"
8896             [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8897                        (match_operand:GPR 2 "general_operand"  ""))
8898              (match_operand:GPR 3 "register_operand" "")])
8899          (label_ref (match_operand 0 "" ""))
8900          (pc)))
8901    (set (match_operand:GPR 4 "nonimmediate_operand" "")
8902         (plus:GPR (match_dup 1) (match_dup 2)))
8903    (clobber (match_scratch:GPR 5 ""))]
8904   "TARGET_CPU_ZARCH"
8905   "#"
8906   "!reload_completed && !reload_in_progress"
8907   [(set (match_dup 7) (match_dup 2)) ; the increment
8908    (set (match_dup 8) (match_dup 3)) ; the comparison value
8909    (parallel [(set (pc)
8910                    (if_then_else
8911                     (match_op_dup 6
8912                        [(plus:GPR (match_dup 1) (match_dup 7))
8913                         (match_dup 8)])
8914                     (label_ref (match_dup 0))
8915                     (pc)))
8916               (set (match_dup 4)
8917                    (plus:GPR (match_dup 1) (match_dup 7)))
8918               (clobber (match_dup 5))
8919               (clobber (reg:CC CC_REGNUM))])]
8920   {
8921     rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8922     operands[7] = gen_lowpart (<GPR:MODE>mode,
8923                                gen_highpart (word_mode, dreg));
8924     operands[8] = gen_lowpart (<GPR:MODE>mode,
8925                                gen_lowpart (word_mode, dreg));
8926   })
8927
8928 ; brxlg, brxhg
8929
8930 (define_insn_and_split "*brxg_64bit"
8931   [(set (pc)
8932         (if_then_else
8933           (match_operator 5 "s390_brx_operator"
8934              [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8935                        (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8936               (subreg:DI (match_dup 2) 8)])
8937           (label_ref (match_operand 0 "" ""))
8938           (pc)))
8939    (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8940         (plus:DI (match_dup 1)
8941                  (subreg:DI (match_dup 2) 0)))
8942    (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8943    (clobber (reg:CC CC_REGNUM))]
8944   "TARGET_ZARCH"
8945 {
8946   if (which_alternative != 0)
8947     return "#";
8948   else if (get_attr_length (insn) == 6)
8949     return "brx%E5g\t%1,%2,%l0";
8950   else
8951     return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8952 }
8953   "&& reload_completed
8954    && (!REG_P (operands[3])
8955        || !rtx_equal_p (operands[1], operands[3]))"
8956   [(set (match_dup 4) (match_dup 1))
8957    (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8958               (clobber (reg:CC CC_REGNUM))])
8959    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8960    (set (match_dup 3) (match_dup 4))
8961    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8962                            (label_ref (match_dup 0))
8963                            (pc)))]
8964   ""
8965   [(set_attr "op_type"  "RIE")
8966    (set_attr "type"  "branch")
8967    (set (attr "length")
8968         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8969                       (const_int 6) (const_int 16)))])
8970
8971 ; brxle, brxh
8972
8973 (define_insn_and_split "*brx_64bit"
8974   [(set (pc)
8975         (if_then_else
8976           (match_operator 5 "s390_brx_operator"
8977              [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8978                        (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8979               (subreg:SI (match_dup 2) 12)])
8980           (label_ref (match_operand 0 "" ""))
8981           (pc)))
8982    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8983         (plus:SI (match_dup 1)
8984                  (subreg:SI (match_dup 2) 4)))
8985    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8986    (clobber (reg:CC CC_REGNUM))]
8987   "TARGET_ZARCH"
8988 {
8989   if (which_alternative != 0)
8990     return "#";
8991   else if (get_attr_length (insn) == 6)
8992     return "brx%C5\t%1,%2,%l0";
8993   else
8994     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8995 }
8996   "&& reload_completed
8997    && (!REG_P (operands[3])
8998        || !rtx_equal_p (operands[1], operands[3]))"
8999   [(set (match_dup 4) (match_dup 1))
9000    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9001               (clobber (reg:CC CC_REGNUM))])
9002    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9003    (set (match_dup 3) (match_dup 4))
9004    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9005                            (label_ref (match_dup 0))
9006                            (pc)))]
9007   ""
9008   [(set_attr "op_type"  "RSI")
9009    (set_attr "type"  "branch")
9010    (set (attr "length")
9011         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9012                       (const_int 6) (const_int 14)))])
9013
9014 ; brxle, brxh
9015
9016 (define_insn_and_split "*brx_31bit"
9017   [(set (pc)
9018         (if_then_else
9019           (match_operator 5 "s390_brx_operator"
9020             [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9021                       (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9022              (subreg:SI (match_dup 2) 4)])
9023           (label_ref (match_operand 0 "" ""))
9024           (pc)))
9025    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9026         (plus:SI (match_dup 1)
9027                  (subreg:SI (match_dup 2) 0)))
9028    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9029    (clobber (reg:CC CC_REGNUM))]
9030   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9031 {
9032   if (which_alternative != 0)
9033     return "#";
9034   else if (get_attr_length (insn) == 6)
9035     return "brx%C5\t%1,%2,%l0";
9036   else
9037     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9038 }
9039   "&& reload_completed
9040    && (!REG_P (operands[3])
9041        || !rtx_equal_p (operands[1], operands[3]))"
9042   [(set (match_dup 4) (match_dup 1))
9043    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9044               (clobber (reg:CC CC_REGNUM))])
9045    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9046    (set (match_dup 3) (match_dup 4))
9047    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9048                            (label_ref (match_dup 0))
9049                            (pc)))]
9050   ""
9051   [(set_attr "op_type"  "RSI")
9052    (set_attr "type"  "branch")
9053    (set (attr "length")
9054         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9055                       (const_int 6) (const_int 14)))])
9056
9057
9058 ;; branch on count
9059
9060 (define_expand "doloop_end"
9061   [(use (match_operand 0 "" ""))        ; loop pseudo
9062    (use (match_operand 1 "" ""))]       ; label
9063   ""
9064 {
9065   if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9066     emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9067   else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9068     emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9069   else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9070     emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9071   else
9072     FAIL;
9073
9074   DONE;
9075 })
9076
9077 (define_insn_and_split "doloop_si64"
9078   [(set (pc)
9079         (if_then_else
9080           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9081               (const_int 1))
9082           (label_ref (match_operand 0 "" ""))
9083           (pc)))
9084    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9085         (plus:SI (match_dup 1) (const_int -1)))
9086    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9087    (clobber (reg:CC CC_REGNUM))]
9088   "TARGET_CPU_ZARCH"
9089 {
9090   if (which_alternative != 0)
9091     return "#";
9092   else if (get_attr_length (insn) == 4)
9093     return "brct\t%1,%l0";
9094   else
9095     return "ahi\t%1,-1\;jgne\t%l0";
9096 }
9097   "&& reload_completed
9098    && (! REG_P (operands[2])
9099        || ! rtx_equal_p (operands[1], operands[2]))"
9100   [(set (match_dup 3) (match_dup 1))
9101    (parallel [(set (reg:CCAN CC_REGNUM)
9102                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9103                                  (const_int 0)))
9104               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9105    (set (match_dup 2) (match_dup 3))
9106    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9107                            (label_ref (match_dup 0))
9108                            (pc)))]
9109   ""
9110   [(set_attr "op_type"  "RI")
9111    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9112    ; hurt us in the (rare) case of ahi.
9113    (set_attr "z10prop"  "z10_super_E1")
9114    (set_attr "type"  "branch")
9115    (set (attr "length")
9116         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9117                       (const_int 4) (const_int 10)))])
9118
9119 (define_insn_and_split "doloop_si31"
9120   [(set (pc)
9121         (if_then_else
9122           (ne (match_operand:SI 1 "register_operand" "d,d,d")
9123               (const_int 1))
9124           (label_ref (match_operand 0 "" ""))
9125           (pc)))
9126    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9127         (plus:SI (match_dup 1) (const_int -1)))
9128    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9129    (clobber (reg:CC CC_REGNUM))]
9130   "!TARGET_CPU_ZARCH"
9131 {
9132   if (which_alternative != 0)
9133     return "#";
9134   else if (get_attr_length (insn) == 4)
9135     return "brct\t%1,%l0";
9136   else
9137     gcc_unreachable ();
9138 }
9139   "&& reload_completed
9140    && (! REG_P (operands[2])
9141        || ! rtx_equal_p (operands[1], operands[2]))"
9142   [(set (match_dup 3) (match_dup 1))
9143    (parallel [(set (reg:CCAN CC_REGNUM)
9144                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9145                                  (const_int 0)))
9146               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9147    (set (match_dup 2) (match_dup 3))
9148    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9149                            (label_ref (match_dup 0))
9150                            (pc)))]
9151   ""
9152   [(set_attr "op_type"  "RI")
9153    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9154    ; hurt us in the (rare) case of ahi.
9155    (set_attr "z10prop"  "z10_super_E1")
9156    (set_attr "type"  "branch")
9157    (set (attr "length")
9158         (if_then_else (not (match_test "flag_pic"))
9159           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9160                         (const_int 4) (const_int 6))
9161           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9162                         (const_int 4) (const_int 8))))])
9163
9164 (define_insn "*doloop_si_long"
9165   [(set (pc)
9166         (if_then_else
9167           (ne (match_operand:SI 1 "register_operand" "d")
9168               (const_int 1))
9169           (match_operand 0 "address_operand" "ZQZR")
9170           (pc)))
9171    (set (match_operand:SI 2 "register_operand" "=1")
9172         (plus:SI (match_dup 1) (const_int -1)))
9173    (clobber (match_scratch:SI 3 "=X"))
9174    (clobber (reg:CC CC_REGNUM))]
9175   "!TARGET_CPU_ZARCH"
9176 {
9177   if (get_attr_op_type (insn) == OP_TYPE_RR)
9178     return "bctr\t%1,%0";
9179   else
9180     return "bct\t%1,%a0";
9181 }
9182   [(set (attr "op_type")
9183         (if_then_else (match_operand 0 "register_operand" "")
9184                       (const_string "RR") (const_string "RX")))
9185    (set_attr "type"  "branch")
9186    (set_attr "atype" "agen")
9187    (set_attr "z10prop"  "z10_c")
9188    (set_attr "z196prop" "z196_cracked")])
9189
9190 (define_insn_and_split "doloop_di"
9191   [(set (pc)
9192         (if_then_else
9193           (ne (match_operand:DI 1 "register_operand" "d,d,d")
9194               (const_int 1))
9195           (label_ref (match_operand 0 "" ""))
9196           (pc)))
9197    (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9198         (plus:DI (match_dup 1) (const_int -1)))
9199    (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9200    (clobber (reg:CC CC_REGNUM))]
9201   "TARGET_ZARCH"
9202 {
9203   if (which_alternative != 0)
9204     return "#";
9205   else if (get_attr_length (insn) == 4)
9206     return "brctg\t%1,%l0";
9207   else
9208     return "aghi\t%1,-1\;jgne\t%l0";
9209 }
9210   "&& reload_completed
9211    && (! REG_P (operands[2])
9212        || ! rtx_equal_p (operands[1], operands[2]))"
9213   [(set (match_dup 3) (match_dup 1))
9214    (parallel [(set (reg:CCAN CC_REGNUM)
9215                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9216                                  (const_int 0)))
9217               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9218    (set (match_dup 2) (match_dup 3))
9219    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9220                            (label_ref (match_dup 0))
9221                            (pc)))]
9222   ""
9223   [(set_attr "op_type"  "RI")
9224    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9225    ; hurt us in the (rare) case of ahi.
9226    (set_attr "z10prop"  "z10_super_E1")
9227    (set_attr "type"  "branch")
9228    (set (attr "length")
9229         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9230                       (const_int 4) (const_int 10)))])
9231
9232 ;;
9233 ;;- Unconditional jump instructions.
9234 ;;
9235
9236 ;
9237 ; jump instruction pattern(s).
9238 ;
9239
9240 (define_expand "jump"
9241   [(match_operand 0 "" "")]
9242   ""
9243   "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9244
9245 (define_insn "*jump64"
9246   [(set (pc) (label_ref (match_operand 0 "" "")))]
9247   "TARGET_CPU_ZARCH"
9248 {
9249   if (get_attr_length (insn) == 4)
9250     return "j\t%l0";
9251   else
9252     return "jg\t%l0";
9253 }
9254   [(set_attr "op_type" "RI")
9255    (set_attr "type"  "branch")
9256    (set (attr "length")
9257         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9258                       (const_int 4) (const_int 6)))])
9259
9260 (define_insn "*jump31"
9261   [(set (pc) (label_ref (match_operand 0 "" "")))]
9262   "!TARGET_CPU_ZARCH"
9263 {
9264   gcc_assert (get_attr_length (insn) == 4);
9265   return "j\t%l0";
9266 }
9267   [(set_attr "op_type" "RI")
9268    (set_attr "type"  "branch")
9269    (set (attr "length")
9270         (if_then_else (not (match_test "flag_pic"))
9271           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9272                         (const_int 4) (const_int 6))
9273           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9274                         (const_int 4) (const_int 8))))])
9275
9276 ;
9277 ; indirect-jump instruction pattern(s).
9278 ;
9279
9280 (define_insn "indirect_jump"
9281  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
9282   ""
9283 {
9284   if (get_attr_op_type (insn) == OP_TYPE_RR)
9285     return "br\t%0";
9286   else
9287     return "b\t%a0";
9288 }
9289   [(set (attr "op_type")
9290         (if_then_else (match_operand 0 "register_operand" "")
9291                       (const_string "RR") (const_string "RX")))
9292    (set_attr "type"  "branch")
9293    (set_attr "atype" "agen")])
9294
9295 ;
9296 ; casesi instruction pattern(s).
9297 ;
9298
9299 (define_insn "casesi_jump"
9300  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
9301    (use (label_ref (match_operand 1 "" "")))]
9302   ""
9303 {
9304   if (get_attr_op_type (insn) == OP_TYPE_RR)
9305     return "br\t%0";
9306   else
9307     return "b\t%a0";
9308 }
9309   [(set (attr "op_type")
9310         (if_then_else (match_operand 0 "register_operand" "")
9311                       (const_string "RR") (const_string "RX")))
9312    (set_attr "type"  "branch")
9313    (set_attr "atype" "agen")])
9314
9315 (define_expand "casesi"
9316   [(match_operand:SI 0 "general_operand" "")
9317    (match_operand:SI 1 "general_operand" "")
9318    (match_operand:SI 2 "general_operand" "")
9319    (label_ref (match_operand 3 "" ""))
9320    (label_ref (match_operand 4 "" ""))]
9321   ""
9322 {
9323    rtx index  = gen_reg_rtx (SImode);
9324    rtx base   = gen_reg_rtx (Pmode);
9325    rtx target = gen_reg_rtx (Pmode);
9326
9327    emit_move_insn (index, operands[0]);
9328    emit_insn (gen_subsi3 (index, index, operands[1]));
9329    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9330                             operands[4]);
9331
9332    if (Pmode != SImode)
9333      index = convert_to_mode (Pmode, index, 1);
9334    if (GET_CODE (index) != REG)
9335      index = copy_to_mode_reg (Pmode, index);
9336
9337    if (TARGET_64BIT)
9338        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9339    else
9340        emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9341
9342    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9343
9344    index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9345    emit_move_insn (target, index);
9346
9347    if (flag_pic)
9348      target = gen_rtx_PLUS (Pmode, base, target);
9349    emit_jump_insn (gen_casesi_jump (target, operands[3]));
9350
9351    DONE;
9352 })
9353
9354
9355 ;;
9356 ;;- Jump to subroutine.
9357 ;;
9358 ;;
9359
9360 ;
9361 ; untyped call instruction pattern(s).
9362 ;
9363
9364 ;; Call subroutine returning any type.
9365 (define_expand "untyped_call"
9366   [(parallel [(call (match_operand 0 "" "")
9367                     (const_int 0))
9368               (match_operand 1 "" "")
9369               (match_operand 2 "" "")])]
9370   ""
9371 {
9372   int i;
9373
9374   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9375
9376   for (i = 0; i < XVECLEN (operands[2], 0); i++)
9377     {
9378       rtx set = XVECEXP (operands[2], 0, i);
9379       emit_move_insn (SET_DEST (set), SET_SRC (set));
9380     }
9381
9382   /* The optimizer does not know that the call sets the function value
9383      registers we stored in the result block.  We avoid problems by
9384      claiming that all hard registers are used and clobbered at this
9385      point.  */
9386   emit_insn (gen_blockage ());
9387
9388   DONE;
9389 })
9390
9391 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9392 ;; all of memory.  This blocks insns from being moved across this point.
9393
9394 (define_insn "blockage"
9395   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9396   ""
9397   ""
9398   [(set_attr "type"    "none")
9399    (set_attr "length"  "0")])
9400
9401 ;
9402 ; sibcall patterns
9403 ;
9404
9405 (define_expand "sibcall"
9406   [(call (match_operand 0 "" "")
9407          (match_operand 1 "" ""))]
9408   ""
9409 {
9410   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9411   DONE;
9412 })
9413
9414 (define_insn "*sibcall_br"
9415   [(call (mem:QI (reg SIBCALL_REGNUM))
9416          (match_operand 0 "const_int_operand" "n"))]
9417   "SIBLING_CALL_P (insn)
9418    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9419   "br\t%%r1"
9420   [(set_attr "op_type" "RR")
9421    (set_attr "type"  "branch")
9422    (set_attr "atype" "agen")])
9423
9424 (define_insn "*sibcall_brc"
9425   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9426          (match_operand 1 "const_int_operand" "n"))]
9427   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9428   "j\t%0"
9429   [(set_attr "op_type" "RI")
9430    (set_attr "type"    "branch")])
9431
9432 (define_insn "*sibcall_brcl"
9433   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9434          (match_operand 1 "const_int_operand" "n"))]
9435   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9436   "jg\t%0"
9437   [(set_attr "op_type" "RIL")
9438    (set_attr "type"    "branch")])
9439
9440 ;
9441 ; sibcall_value patterns
9442 ;
9443
9444 (define_expand "sibcall_value"
9445   [(set (match_operand 0 "" "")
9446         (call (match_operand 1 "" "")
9447               (match_operand 2 "" "")))]
9448   ""
9449 {
9450   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9451   DONE;
9452 })
9453
9454 (define_insn "*sibcall_value_br"
9455   [(set (match_operand 0 "" "")
9456         (call (mem:QI (reg SIBCALL_REGNUM))
9457               (match_operand 1 "const_int_operand" "n")))]
9458   "SIBLING_CALL_P (insn)
9459    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9460   "br\t%%r1"
9461   [(set_attr "op_type" "RR")
9462    (set_attr "type"  "branch")
9463    (set_attr "atype" "agen")])
9464
9465 (define_insn "*sibcall_value_brc"
9466   [(set (match_operand 0 "" "")
9467         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9468               (match_operand 2 "const_int_operand" "n")))]
9469   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9470   "j\t%1"
9471   [(set_attr "op_type" "RI")
9472    (set_attr "type"    "branch")])
9473
9474 (define_insn "*sibcall_value_brcl"
9475   [(set (match_operand 0 "" "")
9476         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9477               (match_operand 2 "const_int_operand" "n")))]
9478   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9479   "jg\t%1"
9480   [(set_attr "op_type" "RIL")
9481    (set_attr "type"    "branch")])
9482
9483
9484 ;
9485 ; call instruction pattern(s).
9486 ;
9487
9488 (define_expand "call"
9489   [(call (match_operand 0 "" "")
9490          (match_operand 1 "" ""))
9491    (use (match_operand 2 "" ""))]
9492   ""
9493 {
9494   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9495                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9496   DONE;
9497 })
9498
9499 (define_insn "*bras"
9500   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9501          (match_operand 1 "const_int_operand" "n"))
9502    (clobber (match_operand 2 "register_operand" "=r"))]
9503   "!SIBLING_CALL_P (insn)
9504    && TARGET_SMALL_EXEC
9505    && GET_MODE (operands[2]) == Pmode"
9506   "bras\t%2,%0"
9507   [(set_attr "op_type" "RI")
9508    (set_attr "type"    "jsr")
9509    (set_attr "z196prop" "z196_cracked")])
9510
9511 (define_insn "*brasl"
9512   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9513          (match_operand 1 "const_int_operand" "n"))
9514    (clobber (match_operand 2 "register_operand" "=r"))]
9515   "!SIBLING_CALL_P (insn)
9516    && TARGET_CPU_ZARCH
9517    && GET_MODE (operands[2]) == Pmode"
9518   "brasl\t%2,%0"
9519   [(set_attr "op_type" "RIL")
9520    (set_attr "type"    "jsr")
9521    (set_attr "z196prop" "z196_cracked")])
9522
9523 (define_insn "*basr"
9524   [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9525          (match_operand 1 "const_int_operand" "n"))
9526    (clobber (match_operand 2 "register_operand" "=r"))]
9527   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9528 {
9529   if (get_attr_op_type (insn) == OP_TYPE_RR)
9530     return "basr\t%2,%0";
9531   else
9532     return "bas\t%2,%a0";
9533 }
9534   [(set (attr "op_type")
9535         (if_then_else (match_operand 0 "register_operand" "")
9536                       (const_string "RR") (const_string "RX")))
9537    (set_attr "type"  "jsr")
9538    (set_attr "atype" "agen")
9539    (set_attr "z196prop" "z196_cracked")])
9540
9541 ;
9542 ; call_value instruction pattern(s).
9543 ;
9544
9545 (define_expand "call_value"
9546   [(set (match_operand 0 "" "")
9547         (call (match_operand 1 "" "")
9548               (match_operand 2 "" "")))
9549    (use (match_operand 3 "" ""))]
9550   ""
9551 {
9552   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9553                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9554   DONE;
9555 })
9556
9557 (define_insn "*bras_r"
9558   [(set (match_operand 0 "" "")
9559         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9560               (match_operand:SI 2 "const_int_operand" "n")))
9561    (clobber (match_operand 3 "register_operand" "=r"))]
9562   "!SIBLING_CALL_P (insn)
9563    && TARGET_SMALL_EXEC
9564    && GET_MODE (operands[3]) == Pmode"
9565   "bras\t%3,%1"
9566   [(set_attr "op_type" "RI")
9567    (set_attr "type"    "jsr")
9568    (set_attr "z196prop" "z196_cracked")])
9569
9570 (define_insn "*brasl_r"
9571   [(set (match_operand 0 "" "")
9572         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9573               (match_operand 2 "const_int_operand" "n")))
9574    (clobber (match_operand 3 "register_operand" "=r"))]
9575   "!SIBLING_CALL_P (insn)
9576    && TARGET_CPU_ZARCH
9577    && GET_MODE (operands[3]) == Pmode"
9578   "brasl\t%3,%1"
9579   [(set_attr "op_type" "RIL")
9580    (set_attr "type"    "jsr")
9581    (set_attr "z196prop" "z196_cracked")])
9582
9583 (define_insn "*basr_r"
9584   [(set (match_operand 0 "" "")
9585         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9586               (match_operand 2 "const_int_operand" "n")))
9587    (clobber (match_operand 3 "register_operand" "=r"))]
9588   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9589 {
9590   if (get_attr_op_type (insn) == OP_TYPE_RR)
9591     return "basr\t%3,%1";
9592   else
9593     return "bas\t%3,%a1";
9594 }
9595   [(set (attr "op_type")
9596         (if_then_else (match_operand 1 "register_operand" "")
9597                       (const_string "RR") (const_string "RX")))
9598    (set_attr "type"  "jsr")
9599    (set_attr "atype" "agen")
9600    (set_attr "z196prop" "z196_cracked")])
9601
9602 ;;
9603 ;;- Thread-local storage support.
9604 ;;
9605
9606 (define_expand "get_thread_pointer<mode>"
9607   [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9608   ""
9609   "")
9610
9611 (define_expand "set_thread_pointer<mode>"
9612   [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9613    (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9614   ""
9615   "")
9616
9617 (define_insn "*set_tp"
9618   [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9619   ""
9620   ""
9621   [(set_attr "type" "none")
9622    (set_attr "length" "0")])
9623
9624 (define_insn "*tls_load_64"
9625   [(set (match_operand:DI 0 "register_operand" "=d")
9626         (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9627                     (match_operand:DI 2 "" "")]
9628                    UNSPEC_TLS_LOAD))]
9629   "TARGET_64BIT"
9630   "lg\t%0,%1%J2"
9631   [(set_attr "op_type" "RXE")
9632    (set_attr "z10prop" "z10_fwd_A3")])
9633
9634 (define_insn "*tls_load_31"
9635   [(set (match_operand:SI 0 "register_operand" "=d,d")
9636         (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9637                     (match_operand:SI 2 "" "")]
9638                    UNSPEC_TLS_LOAD))]
9639   "!TARGET_64BIT"
9640   "@
9641    l\t%0,%1%J2
9642    ly\t%0,%1%J2"
9643   [(set_attr "op_type" "RX,RXY")
9644    (set_attr "type" "load")
9645    (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9646
9647 (define_insn "*bras_tls"
9648   [(set (match_operand 0 "" "")
9649         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9650               (match_operand 2 "const_int_operand" "n")))
9651    (clobber (match_operand 3 "register_operand" "=r"))
9652    (use (match_operand 4 "" ""))]
9653   "!SIBLING_CALL_P (insn)
9654    && TARGET_SMALL_EXEC
9655    && GET_MODE (operands[3]) == Pmode"
9656   "bras\t%3,%1%J4"
9657   [(set_attr "op_type" "RI")
9658    (set_attr "type"    "jsr")
9659    (set_attr "z196prop" "z196_cracked")])
9660
9661 (define_insn "*brasl_tls"
9662   [(set (match_operand 0 "" "")
9663         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9664               (match_operand 2 "const_int_operand" "n")))
9665    (clobber (match_operand 3 "register_operand" "=r"))
9666    (use (match_operand 4 "" ""))]
9667   "!SIBLING_CALL_P (insn)
9668    && TARGET_CPU_ZARCH
9669    && GET_MODE (operands[3]) == Pmode"
9670   "brasl\t%3,%1%J4"
9671   [(set_attr "op_type" "RIL")
9672    (set_attr "type"    "jsr")
9673    (set_attr "z196prop" "z196_cracked")])
9674
9675 (define_insn "*basr_tls"
9676   [(set (match_operand 0 "" "")
9677         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9678               (match_operand 2 "const_int_operand" "n")))
9679    (clobber (match_operand 3 "register_operand" "=r"))
9680    (use (match_operand 4 "" ""))]
9681   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9682 {
9683   if (get_attr_op_type (insn) == OP_TYPE_RR)
9684     return "basr\t%3,%1%J4";
9685   else
9686     return "bas\t%3,%a1%J4";
9687 }
9688   [(set (attr "op_type")
9689         (if_then_else (match_operand 1 "register_operand" "")
9690                       (const_string "RR") (const_string "RX")))
9691    (set_attr "type"  "jsr")
9692    (set_attr "atype" "agen")
9693    (set_attr "z196prop" "z196_cracked")])
9694
9695 ;;
9696 ;;- Atomic operations
9697 ;;
9698
9699 ;
9700 ; memory barrier patterns.
9701 ;
9702
9703 (define_expand "mem_signal_fence"
9704   [(match_operand:SI 0 "const_int_operand")]            ;; model
9705   ""
9706 {
9707   /* The s390 memory model is strong enough not to require any
9708      barrier in order to synchronize a thread with itself.  */
9709   DONE;
9710 })
9711
9712 (define_expand "mem_thread_fence"
9713   [(match_operand:SI 0 "const_int_operand")]            ;; model
9714   ""
9715 {
9716   /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9717      enough not to require barriers of any kind.  */
9718   if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9719     {
9720       rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9721       MEM_VOLATILE_P (mem) = 1;
9722       emit_insn (gen_mem_thread_fence_1 (mem));
9723     }
9724   DONE;
9725 })
9726
9727 ; Although bcr is superscalar on Z10, this variant will never
9728 ; become part of an execution group.
9729 ; With z196 we can make use of the fast-BCR-serialization facility.
9730 ; This allows for a slightly faster sync which is sufficient for our
9731 ; purposes.
9732 (define_insn "mem_thread_fence_1"
9733   [(set (match_operand:BLK 0 "" "")
9734         (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9735   ""
9736 {
9737   if (TARGET_Z196)
9738     return "bcr\t14,0";
9739   else
9740     return "bcr\t15,0";
9741 }
9742   [(set_attr "op_type" "RR")
9743    (set_attr "mnemonic" "bcr_flush")
9744    (set_attr "z196prop" "z196_alone")])
9745
9746 ;
9747 ; atomic load/store operations
9748 ;
9749
9750 ; Atomic loads need not examine the memory model at all.
9751 (define_expand "atomic_load<mode>"
9752   [(match_operand:DINT 0 "register_operand")    ;; output
9753    (match_operand:DINT 1 "memory_operand")      ;; memory
9754    (match_operand:SI 2 "const_int_operand")]    ;; model
9755   ""
9756 {
9757   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9758     FAIL;
9759
9760   if (<MODE>mode == TImode)
9761     emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9762   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9763     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9764   else
9765     emit_move_insn (operands[0], operands[1]);
9766   DONE;
9767 })
9768
9769 ; Different from movdi_31 in that we want no splitters.
9770 (define_insn "atomic_loaddi_1"
9771   [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9772         (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9773                    UNSPEC_MOVA))]
9774   "!TARGET_ZARCH"
9775   "@
9776    lm\t%0,%M0,%S1
9777    lmy\t%0,%M0,%S1
9778    ld\t%0,%1
9779    ldy\t%0,%1"
9780   [(set_attr "op_type" "RS,RSY,RS,RSY")
9781    (set_attr "type" "lm,lm,floaddf,floaddf")])
9782
9783 (define_insn "atomic_loadti_1"
9784   [(set (match_operand:TI 0 "register_operand" "=r")
9785         (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9786                    UNSPEC_MOVA))]
9787   "TARGET_ZARCH"
9788   "lpq\t%0,%1"
9789   [(set_attr "op_type" "RXY")
9790    (set_attr "type" "other")])
9791
9792 ; Atomic stores must(?) enforce sequential consistency.
9793 (define_expand "atomic_store<mode>"
9794   [(match_operand:DINT 0 "memory_operand")      ;; memory
9795    (match_operand:DINT 1 "register_operand")    ;; input
9796    (match_operand:SI 2 "const_int_operand")]    ;; model
9797   ""
9798 {
9799   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9800
9801   if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9802     FAIL;
9803
9804   if (<MODE>mode == TImode)
9805     emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9806   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9807     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9808   else
9809     emit_move_insn (operands[0], operands[1]);
9810   if (is_mm_seq_cst (model))
9811     emit_insn (gen_mem_thread_fence (operands[2]));
9812   DONE;
9813 })
9814
9815 ; Different from movdi_31 in that we want no splitters.
9816 (define_insn "atomic_storedi_1"
9817   [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9818         (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9819                    UNSPEC_MOVA))]
9820   "!TARGET_ZARCH"
9821   "@
9822    stm\t%1,%N1,%S0
9823    stmy\t%1,%N1,%S0
9824    std %1,%0
9825    stdy %1,%0"
9826   [(set_attr "op_type" "RS,RSY,RS,RSY")
9827    (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9828
9829 (define_insn "atomic_storeti_1"
9830   [(set (match_operand:TI 0 "memory_operand" "=RT")
9831         (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9832                    UNSPEC_MOVA))]
9833   "TARGET_ZARCH"
9834   "stpq\t%1,%0"
9835   [(set_attr "op_type" "RXY")
9836    (set_attr "type" "other")])
9837
9838 ;
9839 ; compare and swap patterns.
9840 ;
9841
9842 (define_expand "atomic_compare_and_swap<mode>"
9843   [(match_operand:SI 0 "register_operand")      ;; bool success output
9844    (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9845    (match_operand:DGPR 2 "memory_operand")      ;; memory
9846    (match_operand:DGPR 3 "register_operand")    ;; expected intput
9847    (match_operand:DGPR 4 "register_operand")    ;; newval intput
9848    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9849    (match_operand:SI 6 "const_int_operand")     ;; success model
9850    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9851   ""
9852 {
9853   rtx cc, cmp, output = operands[1];
9854
9855   if (!register_operand (output, <MODE>mode))
9856     output = gen_reg_rtx (<MODE>mode);
9857
9858   if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9859     FAIL;
9860
9861   emit_insn (gen_atomic_compare_and_swap<mode>_internal
9862              (output, operands[2], operands[3], operands[4]));
9863
9864   /* We deliberately accept non-register operands in the predicate
9865      to ensure the write back to the output operand happens *before*
9866      the store-flags code below.  This makes it easier for combine
9867      to merge the store-flags code with a potential test-and-branch
9868      pattern following (immediately!) afterwards.  */
9869   if (output != operands[1])
9870     emit_move_insn (operands[1], output);
9871
9872   cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9873   cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9874   emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9875   DONE;
9876 })
9877
9878 (define_expand "atomic_compare_and_swap<mode>"
9879   [(match_operand:SI 0 "register_operand")      ;; bool success output
9880    (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9881    (match_operand:HQI 2 "memory_operand")       ;; memory
9882    (match_operand:HQI 3 "general_operand")      ;; expected intput
9883    (match_operand:HQI 4 "general_operand")      ;; newval intput
9884    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9885    (match_operand:SI 6 "const_int_operand")     ;; success model
9886    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9887   ""
9888 {
9889   s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9890                       operands[3], operands[4], INTVAL (operands[5]));
9891   DONE;
9892 })
9893
9894 (define_expand "atomic_compare_and_swap<mode>_internal"
9895   [(parallel
9896      [(set (match_operand:DGPR 0 "register_operand")
9897            (match_operand:DGPR 1 "memory_operand"))
9898       (set (match_dup 1)
9899            (unspec_volatile:DGPR
9900              [(match_dup 1)
9901               (match_operand:DGPR 2 "register_operand")
9902               (match_operand:DGPR 3 "register_operand")]
9903              UNSPECV_CAS))
9904       (set (reg:CCZ1 CC_REGNUM)
9905            (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9906   "")
9907
9908 ; cdsg, csg
9909 (define_insn "*atomic_compare_and_swap<mode>_1"
9910   [(set (match_operand:TDI 0 "register_operand" "=r")
9911         (match_operand:TDI 1 "memory_operand" "+QS"))
9912    (set (match_dup 1)
9913         (unspec_volatile:TDI
9914           [(match_dup 1)
9915            (match_operand:TDI 2 "register_operand" "0")
9916            (match_operand:TDI 3 "register_operand" "r")]
9917           UNSPECV_CAS))
9918    (set (reg:CCZ1 CC_REGNUM)
9919         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9920   "TARGET_ZARCH"
9921   "c<td>sg\t%0,%3,%S1"
9922   [(set_attr "op_type" "RSY")
9923    (set_attr "type"   "sem")])
9924
9925 ; cds, cdsy
9926 (define_insn "*atomic_compare_and_swapdi_2"
9927   [(set (match_operand:DI 0 "register_operand" "=r,r")
9928         (match_operand:DI 1 "memory_operand" "+Q,S"))
9929    (set (match_dup 1)
9930         (unspec_volatile:DI
9931           [(match_dup 1)
9932            (match_operand:DI 2 "register_operand" "0,0")
9933            (match_operand:DI 3 "register_operand" "r,r")]
9934           UNSPECV_CAS))
9935    (set (reg:CCZ1 CC_REGNUM)
9936         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9937   "!TARGET_ZARCH"
9938   "@
9939    cds\t%0,%3,%S1
9940    cdsy\t%0,%3,%S1"
9941   [(set_attr "op_type" "RS,RSY")
9942    (set_attr "type" "sem")])
9943
9944 ; cs, csy
9945 (define_insn "*atomic_compare_and_swapsi_3"
9946   [(set (match_operand:SI 0 "register_operand" "=r,r")
9947         (match_operand:SI 1 "memory_operand" "+Q,S"))
9948    (set (match_dup 1)
9949         (unspec_volatile:SI
9950           [(match_dup 1)
9951            (match_operand:SI 2 "register_operand" "0,0")
9952            (match_operand:SI 3 "register_operand" "r,r")]
9953           UNSPECV_CAS))
9954    (set (reg:CCZ1 CC_REGNUM)
9955         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9956   ""
9957   "@
9958    cs\t%0,%3,%S1
9959    csy\t%0,%3,%S1"
9960   [(set_attr "op_type" "RS,RSY")
9961    (set_attr "type"   "sem")])
9962
9963 ;
9964 ; Other atomic instruction patterns.
9965 ;
9966
9967 ; z196 load and add, xor, or and and instructions
9968
9969 (define_expand "atomic_fetch_<atomic><mode>"
9970   [(match_operand:GPR 0 "register_operand")             ;; val out
9971    (ATOMIC_Z196:GPR
9972      (match_operand:GPR 1 "memory_operand")             ;; memory
9973      (match_operand:GPR 2 "register_operand"))          ;; val in
9974    (match_operand:SI 3 "const_int_operand")]            ;; model
9975   "TARGET_Z196"
9976 {
9977   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9978     FAIL;
9979
9980   emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9981              (operands[0], operands[1], operands[2]));
9982   DONE;
9983 })
9984
9985 ; lan, lang, lao, laog, lax, laxg, laa, laag
9986 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9987   [(set (match_operand:GPR 0 "register_operand" "=d")
9988         (match_operand:GPR 1 "memory_operand" "+QS"))
9989    (set (match_dup 1)
9990         (unspec_volatile:GPR
9991          [(ATOMIC_Z196:GPR (match_dup 1)
9992                            (match_operand:GPR 2 "general_operand" "d"))]
9993          UNSPECV_ATOMIC_OP))
9994    (clobber (reg:CC CC_REGNUM))]
9995   "TARGET_Z196"
9996   "la<noxa><g>\t%0,%2,%1"
9997   [(set_attr "op_type" "RSY")
9998    (set_attr "type" "sem")])
9999
10000 ;; For SImode and larger, the optabs.c code will do just fine in
10001 ;; expanding a compare-and-swap loop.  For QI/HImode, we can do
10002 ;; better by expanding our own loop.
10003
10004 (define_expand "atomic_<atomic><mode>"
10005   [(ATOMIC:HQI
10006      (match_operand:HQI 0 "memory_operand")             ;; memory
10007      (match_operand:HQI 1 "general_operand"))           ;; val in
10008    (match_operand:SI 2 "const_int_operand")]            ;; model
10009   ""
10010 {
10011   s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10012                        operands[1], false);
10013   DONE;
10014 })
10015
10016 (define_expand "atomic_fetch_<atomic><mode>"
10017   [(match_operand:HQI 0 "register_operand")             ;; val out
10018    (ATOMIC:HQI
10019      (match_operand:HQI 1 "memory_operand")             ;; memory
10020      (match_operand:HQI 2 "general_operand"))           ;; val in
10021    (match_operand:SI 3 "const_int_operand")]            ;; model
10022   ""
10023 {
10024   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10025                       operands[2], false);
10026   DONE;
10027 })
10028
10029 (define_expand "atomic_<atomic>_fetch<mode>"
10030   [(match_operand:HQI 0 "register_operand")             ;; val out
10031    (ATOMIC:HQI
10032      (match_operand:HQI 1 "memory_operand")             ;; memory
10033      (match_operand:HQI 2 "general_operand"))           ;; val in
10034    (match_operand:SI 3 "const_int_operand")]            ;; model
10035   ""
10036 {
10037   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10038                       operands[2], true);
10039   DONE;
10040 })
10041
10042 (define_expand "atomic_exchange<mode>"
10043   [(match_operand:HQI 0 "register_operand")             ;; val out
10044    (match_operand:HQI 1 "memory_operand")               ;; memory
10045    (match_operand:HQI 2 "general_operand")              ;; val in
10046    (match_operand:SI 3 "const_int_operand")]            ;; model
10047   ""
10048 {
10049   s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10050                       operands[2], false);
10051   DONE;
10052 })
10053
10054 ;;
10055 ;;- Miscellaneous instructions.
10056 ;;
10057
10058 ;
10059 ; allocate stack instruction pattern(s).
10060 ;
10061
10062 (define_expand "allocate_stack"
10063   [(match_operand 0 "general_operand" "")
10064    (match_operand 1 "general_operand" "")]
10065  "TARGET_BACKCHAIN"
10066 {
10067   rtx temp = gen_reg_rtx (Pmode);
10068
10069   emit_move_insn (temp, s390_back_chain_rtx ());
10070   anti_adjust_stack (operands[1]);
10071   emit_move_insn (s390_back_chain_rtx (), temp);
10072
10073   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10074   DONE;
10075 })
10076
10077
10078 ;
10079 ; setjmp instruction pattern.
10080 ;
10081
10082 (define_expand "builtin_setjmp_receiver"
10083   [(match_operand 0 "" "")]
10084   "flag_pic"
10085 {
10086   emit_insn (s390_load_got ());
10087   emit_use (pic_offset_table_rtx);
10088   DONE;
10089 })
10090
10091 ;; These patterns say how to save and restore the stack pointer.  We need not
10092 ;; save the stack pointer at function level since we are careful to
10093 ;; preserve the backchain.  At block level, we have to restore the backchain
10094 ;; when we restore the stack pointer.
10095 ;;
10096 ;; For nonlocal gotos, we must save both the stack pointer and its
10097 ;; backchain and restore both.  Note that in the nonlocal case, the
10098 ;; save area is a memory location.
10099
10100 (define_expand "save_stack_function"
10101   [(match_operand 0 "general_operand" "")
10102    (match_operand 1 "general_operand" "")]
10103   ""
10104   "DONE;")
10105
10106 (define_expand "restore_stack_function"
10107   [(match_operand 0 "general_operand" "")
10108    (match_operand 1 "general_operand" "")]
10109   ""
10110   "DONE;")
10111
10112 (define_expand "restore_stack_block"
10113   [(match_operand 0 "register_operand" "")
10114    (match_operand 1 "register_operand" "")]
10115   "TARGET_BACKCHAIN"
10116 {
10117   rtx temp = gen_reg_rtx (Pmode);
10118
10119   emit_move_insn (temp, s390_back_chain_rtx ());
10120   emit_move_insn (operands[0], operands[1]);
10121   emit_move_insn (s390_back_chain_rtx (), temp);
10122
10123   DONE;
10124 })
10125
10126 (define_expand "save_stack_nonlocal"
10127   [(match_operand 0 "memory_operand" "")
10128    (match_operand 1 "register_operand" "")]
10129   ""
10130 {
10131   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10132
10133   /* Copy the backchain to the first word, sp to the second and the
10134      literal pool base to the third.  */
10135
10136   rtx save_bc = adjust_address (operands[0], Pmode, 0);
10137   rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10138   rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10139
10140   if (TARGET_BACKCHAIN)
10141     emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10142
10143   emit_move_insn (save_sp, operands[1]);
10144   emit_move_insn (save_bp, base);
10145
10146   DONE;
10147 })
10148
10149 (define_expand "restore_stack_nonlocal"
10150   [(match_operand 0 "register_operand" "")
10151    (match_operand 1 "memory_operand" "")]
10152   ""
10153 {
10154   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10155   rtx temp = NULL_RTX;
10156
10157   /* Restore the backchain from the first word, sp from the second and the
10158      literal pool base from the third.  */
10159
10160   rtx save_bc = adjust_address (operands[1], Pmode, 0);
10161   rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10162   rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10163
10164   if (TARGET_BACKCHAIN)
10165     temp = force_reg (Pmode, save_bc);
10166
10167   emit_move_insn (base, save_bp);
10168   emit_move_insn (operands[0], save_sp);
10169
10170   if (temp)
10171     emit_move_insn (s390_back_chain_rtx (), temp);
10172
10173   emit_use (base);
10174   DONE;
10175 })
10176
10177 (define_expand "exception_receiver"
10178   [(const_int 0)]
10179   ""
10180 {
10181   s390_set_has_landing_pad_p (true);
10182   DONE;
10183 })
10184
10185 ;
10186 ; nop instruction pattern(s).
10187 ;
10188
10189 (define_insn "nop"
10190   [(const_int 0)]
10191   ""
10192   "lr\t0,0"
10193   [(set_attr "op_type" "RR")
10194    (set_attr "z10prop"  "z10_fr_E1")])
10195
10196 (define_insn "nop1"
10197   [(const_int 1)]
10198   ""
10199   "lr\t1,1"
10200   [(set_attr "op_type" "RR")])
10201
10202 ;;- Undeletable nops (used for hotpatching)
10203
10204 (define_insn "nop_2_byte"
10205   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10206   ""
10207   "nopr\t%%r7"
10208   [(set_attr "op_type" "RR")])
10209
10210 (define_insn "nop_4_byte"
10211   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10212   ""
10213   "nop\t0"
10214   [(set_attr "op_type" "RX")])
10215
10216 (define_insn "nop_6_byte"
10217   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10218   "TARGET_CPU_ZARCH"
10219   "brcl\t0, 0"
10220   [(set_attr "op_type" "RIL")])
10221
10222
10223 ;
10224 ; Special literal pool access instruction pattern(s).
10225 ;
10226
10227 (define_insn "*pool_entry"
10228   [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10229                     UNSPECV_POOL_ENTRY)]
10230   ""
10231 {
10232   machine_mode mode = GET_MODE (PATTERN (insn));
10233   unsigned int align = GET_MODE_BITSIZE (mode);
10234   s390_output_pool_entry (operands[0], mode, align);
10235   return "";
10236 }
10237   [(set (attr "length")
10238         (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10239
10240 (define_insn "pool_align"
10241   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10242                     UNSPECV_POOL_ALIGN)]
10243   ""
10244   ".align\t%0"
10245   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10246
10247 (define_insn "pool_section_start"
10248   [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10249   ""
10250   ".section\t.rodata"
10251   [(set_attr "length" "0")])
10252
10253 (define_insn "pool_section_end"
10254   [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10255   ""
10256   ".previous"
10257   [(set_attr "length" "0")])
10258
10259 (define_insn "main_base_31_small"
10260   [(set (match_operand 0 "register_operand" "=a")
10261         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10262   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10263   "basr\t%0,0"
10264   [(set_attr "op_type" "RR")
10265    (set_attr "type"    "la")
10266    (set_attr "z196prop" "z196_cracked")])
10267
10268 (define_insn "main_base_31_large"
10269   [(set (match_operand 0 "register_operand" "=a")
10270         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10271    (set (pc) (label_ref (match_operand 2 "" "")))]
10272   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10273   "bras\t%0,%2"
10274   [(set_attr "op_type" "RI")
10275    (set_attr "z196prop" "z196_cracked")])
10276
10277 (define_insn "main_base_64"
10278   [(set (match_operand 0 "register_operand" "=a")
10279         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10280   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10281   "larl\t%0,%1"
10282   [(set_attr "op_type" "RIL")
10283    (set_attr "type"    "larl")
10284    (set_attr "z10prop" "z10_fwd_A1")])
10285
10286 (define_insn "main_pool"
10287   [(set (match_operand 0 "register_operand" "=a")
10288         (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10289   "GET_MODE (operands[0]) == Pmode"
10290 {
10291   gcc_unreachable ();
10292 }
10293   [(set (attr "type")
10294         (if_then_else (match_test "TARGET_CPU_ZARCH")
10295                       (const_string "larl") (const_string "la")))])
10296
10297 (define_insn "reload_base_31"
10298   [(set (match_operand 0 "register_operand" "=a")
10299         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10300   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10301   "basr\t%0,0\;la\t%0,%1-.(%0)"
10302   [(set_attr "length" "6")
10303    (set_attr "type" "la")
10304    (set_attr "z196prop" "z196_cracked")])
10305
10306 (define_insn "reload_base_64"
10307   [(set (match_operand 0 "register_operand" "=a")
10308         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10309   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10310   "larl\t%0,%1"
10311   [(set_attr "op_type" "RIL")
10312    (set_attr "type"    "larl")
10313    (set_attr "z10prop" "z10_fwd_A1")])
10314
10315 (define_insn "pool"
10316   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10317   ""
10318 {
10319   gcc_unreachable ();
10320 }
10321   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10322
10323 ;;
10324 ;; Insns related to generating the function prologue and epilogue.
10325 ;;
10326
10327
10328 (define_expand "prologue"
10329   [(use (const_int 0))]
10330   ""
10331   "s390_emit_prologue (); DONE;")
10332
10333 (define_expand "epilogue"
10334   [(use (const_int 1))]
10335   ""
10336   "s390_emit_epilogue (false); DONE;")
10337
10338 (define_expand "sibcall_epilogue"
10339   [(use (const_int 0))]
10340   ""
10341   "s390_emit_epilogue (true); DONE;")
10342
10343 ;; A direct return instruction, without using an epilogue.
10344 (define_insn "<code>"
10345   [(ANY_RETURN)]
10346   "s390_can_use_<code>_insn ()"
10347   "br\t%%r14"
10348   [(set_attr "op_type" "RR")
10349    (set_attr "type"    "jsr")
10350    (set_attr "atype"   "agen")])
10351
10352 (define_insn "*return"
10353   [(return)
10354    (use (match_operand 0 "register_operand" "a"))]
10355   "GET_MODE (operands[0]) == Pmode"
10356   "br\t%0"
10357   [(set_attr "op_type" "RR")
10358    (set_attr "type"    "jsr")
10359    (set_attr "atype"   "agen")])
10360
10361
10362 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10363 ;; pointer. This is used for compatibility.
10364
10365 (define_expand "ptr_extend"
10366   [(set (match_operand:DI 0 "register_operand" "=r")
10367         (match_operand:SI 1 "register_operand" "r"))]
10368   "TARGET_64BIT"
10369 {
10370   emit_insn (gen_anddi3 (operands[0],
10371                          gen_lowpart (DImode, operands[1]),
10372                          GEN_INT (0x7fffffff)));
10373   DONE;
10374 })
10375
10376 ;; Instruction definition to expand eh_return macro to support
10377 ;; swapping in special linkage return addresses.
10378
10379 (define_expand "eh_return"
10380   [(use (match_operand 0 "register_operand" ""))]
10381   "TARGET_TPF"
10382 {
10383   s390_emit_tpf_eh_return (operands[0]);
10384   DONE;
10385 })
10386
10387 ;
10388 ; Stack Protector Patterns
10389 ;
10390
10391 (define_expand "stack_protect_set"
10392   [(set (match_operand 0 "memory_operand" "")
10393         (match_operand 1 "memory_operand" ""))]
10394   ""
10395 {
10396 #ifdef TARGET_THREAD_SSP_OFFSET
10397   operands[1]
10398     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10399                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10400 #endif
10401   if (TARGET_64BIT)
10402     emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10403   else
10404     emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10405
10406   DONE;
10407 })
10408
10409 (define_insn "stack_protect_set<mode>"
10410   [(set (match_operand:DSI 0 "memory_operand" "=Q")
10411         (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10412   ""
10413   "mvc\t%O0(%G0,%R0),%S1"
10414   [(set_attr "op_type" "SS")])
10415
10416 (define_expand "stack_protect_test"
10417   [(set (reg:CC CC_REGNUM)
10418         (compare (match_operand 0 "memory_operand" "")
10419                  (match_operand 1 "memory_operand" "")))
10420    (match_operand 2 "" "")]
10421   ""
10422 {
10423   rtx cc_reg, test;
10424 #ifdef TARGET_THREAD_SSP_OFFSET
10425   operands[1]
10426     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10427                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10428 #endif
10429   if (TARGET_64BIT)
10430     emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10431   else
10432     emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10433
10434   cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10435   test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10436   emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10437   DONE;
10438 })
10439
10440 (define_insn "stack_protect_test<mode>"
10441   [(set (reg:CCZ CC_REGNUM)
10442         (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10443                      (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10444   ""
10445   "clc\t%O0(%G0,%R0),%S1"
10446   [(set_attr "op_type" "SS")])
10447
10448 ; This is used in s390_emit_prologue in order to prevent insns
10449 ; adjusting the stack pointer to be moved over insns writing stack
10450 ; slots using a copy of the stack pointer in a different register.
10451 (define_insn "stack_tie"
10452   [(set (match_operand:BLK 0 "memory_operand" "+m")
10453         (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10454   ""
10455   ""
10456   [(set_attr "length" "0")])
10457
10458
10459 ;
10460 ; Data prefetch patterns
10461 ;
10462
10463 (define_insn "prefetch"
10464   [(prefetch (match_operand 0    "address_operand"   "ZQZRZSZT,X")
10465              (match_operand:SI 1 "const_int_operand" "       n,n")
10466              (match_operand:SI 2 "const_int_operand" "       n,n"))]
10467   "TARGET_Z10"
10468 {
10469   switch (which_alternative)
10470     {
10471       case 0:
10472         return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10473       case 1:
10474         if (larl_operand (operands[0], Pmode))
10475           return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10476       default:
10477
10478         /* This might be reached for symbolic operands with an odd
10479            addend.  We simply omit the prefetch for such rare cases.  */
10480
10481         return "";
10482      }
10483 }
10484   [(set_attr "type" "load,larl")
10485    (set_attr "op_type" "RXY,RIL")
10486    (set_attr "z10prop" "z10_super")
10487    (set_attr "z196prop" "z196_alone")])
10488
10489
10490 ;
10491 ; Byte swap instructions
10492 ;
10493
10494 ; FIXME: There is also mvcin but we cannot use it since src and target
10495 ; may overlap.
10496 (define_insn "bswap<mode>2"
10497   [(set (match_operand:GPR 0            "nonimmediate_operand" "=d, d,RT")
10498         (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))]
10499   "TARGET_CPU_ZARCH"
10500   "@
10501    lrv<g>r\t%0,%1
10502    lrv<g>\t%0,%1
10503    strv<g>\t%1,%0"
10504   [(set_attr "type" "*,load,store")
10505    (set_attr "op_type" "RRE,RXY,RXY")
10506    (set_attr "z10prop" "z10_super")])
10507
10508 (define_insn "bswaphi2"
10509   [(set (match_operand:HI 0           "nonimmediate_operand" "=d, d,RT")
10510         (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))]
10511   "TARGET_CPU_ZARCH"
10512   "@
10513    #
10514    lrvh\t%0,%1
10515    strvh\t%1,%0"
10516   [(set_attr "type" "*,load,store")
10517    (set_attr "op_type" "RRE,RXY,RXY")
10518    (set_attr "z10prop" "z10_super")])
10519
10520 (define_split
10521   [(set (match_operand:HI 0           "register_operand" "")
10522         (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10523   "TARGET_CPU_ZARCH"
10524   [(set (match_dup 2) (bswap:SI (match_dup 3)))
10525    (set (match_dup 2) (lshiftrt:SI (match_dup 2)
10526                                    (const_int 16)))
10527    (set (match_dup 0) (subreg:HI (match_dup 2) 2))]
10528 {
10529   operands[2] = gen_reg_rtx (SImode);
10530   operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10531 })
10532
10533
10534 ;
10535 ; Population count instruction
10536 ;
10537
10538 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10539 ; portions and stores the result in the corresponding bytes in op0.
10540 (define_insn "*popcount<mode>"
10541   [(set (match_operand:INT 0 "register_operand" "=d")
10542         (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10543    (clobber (reg:CC CC_REGNUM))]
10544   "TARGET_Z196"
10545   "popcnt\t%0,%1"
10546   [(set_attr "op_type" "RRE")])
10547
10548 (define_expand "popcountdi2"
10549   [; popcnt op0, op1
10550    (parallel [(set (match_operand:DI 0 "register_operand" "")
10551                    (unspec:DI [(match_operand:DI 1 "register_operand")]
10552                               UNSPEC_POPCNT))
10553               (clobber (reg:CC CC_REGNUM))])
10554    ; sllg op2, op0, 32
10555    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10556    ; agr op0, op2
10557    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10558               (clobber (reg:CC CC_REGNUM))])
10559    ; sllg op2, op0, 16
10560    (set (match_dup 2)
10561         (ashift:DI (match_dup 0) (const_int 16)))
10562    ; agr op0, op2
10563    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10564               (clobber (reg:CC CC_REGNUM))])
10565    ; sllg op2, op0, 8
10566    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10567    ; agr op0, op2
10568    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10569               (clobber (reg:CC CC_REGNUM))])
10570    ; srlg op0, op0, 56
10571    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10572   "TARGET_Z196 && TARGET_64BIT"
10573   "operands[2] = gen_reg_rtx (DImode);")
10574
10575 (define_expand "popcountsi2"
10576   [; popcnt op0, op1
10577    (parallel [(set (match_operand:SI 0 "register_operand" "")
10578                    (unspec:SI [(match_operand:SI 1 "register_operand")]
10579                               UNSPEC_POPCNT))
10580               (clobber (reg:CC CC_REGNUM))])
10581    ; sllk op2, op0, 16
10582    (set (match_dup 2)
10583         (ashift:SI (match_dup 0) (const_int 16)))
10584    ; ar op0, op2
10585    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10586               (clobber (reg:CC CC_REGNUM))])
10587    ; sllk op2, op0, 8
10588    (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10589    ; ar op0, op2
10590    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10591               (clobber (reg:CC CC_REGNUM))])
10592    ; srl op0, op0, 24
10593    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10594   "TARGET_Z196"
10595   "operands[2] = gen_reg_rtx (SImode);")
10596
10597 (define_expand "popcounthi2"
10598   [; popcnt op0, op1
10599    (parallel [(set (match_operand:HI 0 "register_operand" "")
10600                    (unspec:HI [(match_operand:HI 1 "register_operand")]
10601                               UNSPEC_POPCNT))
10602               (clobber (reg:CC CC_REGNUM))])
10603    ; sllk op2, op0, 8
10604    (set (match_dup 2)
10605         (ashift:SI (match_dup 0) (const_int 8)))
10606    ; ar op0, op2
10607    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10608               (clobber (reg:CC CC_REGNUM))])
10609    ; srl op0, op0, 8
10610    (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10611   "TARGET_Z196"
10612   "operands[2] = gen_reg_rtx (SImode);")
10613
10614 (define_expand "popcountqi2"
10615   [; popcnt op0, op1
10616    (parallel [(set (match_operand:QI 0 "register_operand" "")
10617                    (unspec:QI [(match_operand:QI 1 "register_operand")]
10618                               UNSPEC_POPCNT))
10619               (clobber (reg:CC CC_REGNUM))])]
10620   "TARGET_Z196"
10621   "")
10622
10623 ;;
10624 ;;- Copy sign instructions
10625 ;;
10626
10627 (define_insn "copysign<mode>3"
10628   [(set (match_operand:FP 0 "register_operand" "=f")
10629       (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10630                   (match_operand:FP 2 "register_operand" "f")]
10631                   UNSPEC_COPYSIGN))]
10632   "TARGET_Z196"
10633   "cpsdr\t%0,%2,%1"
10634   [(set_attr "op_type"  "RRF")
10635    (set_attr "type"     "fsimp<mode>")])
10636
10637
10638 ;;
10639 ;;- Transactional execution instructions
10640 ;;
10641
10642 ; This splitter helps combine to make use of CC directly when
10643 ; comparing the integer result of a tbegin builtin with a constant.
10644 ; The unspec is already removed by canonicalize_comparison. So this
10645 ; splitters only job is to turn the PARALLEL into separate insns
10646 ; again.  Unfortunately this only works with the very first cc/int
10647 ; compare since combine is not able to deal with data flow across
10648 ; basic block boundaries.
10649
10650 ; It needs to be an insn pattern as well since combine does not apply
10651 ; the splitter directly.  Combine would only use it if it actually
10652 ; would reduce the number of instructions.
10653 (define_insn_and_split "*ccraw_to_int"
10654   [(set (pc)
10655         (if_then_else
10656          (match_operator 0 "s390_eqne_operator"
10657                          [(reg:CCRAW CC_REGNUM)
10658                           (match_operand 1 "const_int_operand" "")])
10659          (label_ref (match_operand 2 "" ""))
10660          (pc)))
10661    (set (match_operand:SI 3 "register_operand" "=d")
10662         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10663   ""
10664   "#"
10665   ""
10666   [(set (match_dup 3)
10667         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10668    (set (pc)
10669         (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10670                       (label_ref (match_dup 2))
10671                       (pc)))]
10672   "")
10673
10674 ; Non-constrained transaction begin
10675
10676 (define_expand "tbegin"
10677   [(match_operand:SI 0 "register_operand" "")
10678    (match_operand:BLK 1 "memory_operand" "")]
10679   "TARGET_HTM"
10680 {
10681   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10682   DONE;
10683 })
10684
10685 (define_expand "tbegin_nofloat"
10686   [(match_operand:SI 0 "register_operand" "")
10687    (match_operand:BLK 1 "memory_operand" "")]
10688   "TARGET_HTM"
10689 {
10690   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10691   DONE;
10692 })
10693
10694 (define_expand "tbegin_retry"
10695   [(match_operand:SI 0 "register_operand" "")
10696    (match_operand:BLK 1 "memory_operand" "")
10697    (match_operand:SI 2 "general_operand" "")]
10698   "TARGET_HTM"
10699 {
10700   s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10701   DONE;
10702 })
10703
10704 (define_expand "tbegin_retry_nofloat"
10705   [(match_operand:SI 0 "register_operand" "")
10706    (match_operand:BLK 1 "memory_operand" "")
10707    (match_operand:SI 2 "general_operand" "")]
10708   "TARGET_HTM"
10709 {
10710   s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10711   DONE;
10712 })
10713
10714 ; Clobber VRs since they don't get restored
10715 (define_insn "tbegin_1_z13"
10716   [(set (reg:CCRAW CC_REGNUM)
10717         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10718                                UNSPECV_TBEGIN))
10719    (set (match_operand:BLK 1 "memory_operand" "=Q")
10720         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10721    (clobber (reg:TI 16)) (clobber (reg:TI 38))
10722    (clobber (reg:TI 17)) (clobber (reg:TI 39))
10723    (clobber (reg:TI 18)) (clobber (reg:TI 40))
10724    (clobber (reg:TI 19)) (clobber (reg:TI 41))
10725    (clobber (reg:TI 20)) (clobber (reg:TI 42))
10726    (clobber (reg:TI 21)) (clobber (reg:TI 43))
10727    (clobber (reg:TI 22)) (clobber (reg:TI 44))
10728    (clobber (reg:TI 23)) (clobber (reg:TI 45))
10729    (clobber (reg:TI 24)) (clobber (reg:TI 46))
10730    (clobber (reg:TI 25)) (clobber (reg:TI 47))
10731    (clobber (reg:TI 26)) (clobber (reg:TI 48))
10732    (clobber (reg:TI 27)) (clobber (reg:TI 49))
10733    (clobber (reg:TI 28)) (clobber (reg:TI 50))
10734    (clobber (reg:TI 29)) (clobber (reg:TI 51))
10735    (clobber (reg:TI 30)) (clobber (reg:TI 52))
10736    (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10737 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10738 ; not supposed to be used for immediates (see genpreds.c).
10739   "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10740   "tbegin\t%1,%x0"
10741   [(set_attr "op_type" "SIL")])
10742
10743 (define_insn "tbegin_1"
10744   [(set (reg:CCRAW CC_REGNUM)
10745         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10746                                UNSPECV_TBEGIN))
10747    (set (match_operand:BLK 1 "memory_operand" "=Q")
10748         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10749    (clobber (reg:DF 16))
10750    (clobber (reg:DF 17))
10751    (clobber (reg:DF 18))
10752    (clobber (reg:DF 19))
10753    (clobber (reg:DF 20))
10754    (clobber (reg:DF 21))
10755    (clobber (reg:DF 22))
10756    (clobber (reg:DF 23))
10757    (clobber (reg:DF 24))
10758    (clobber (reg:DF 25))
10759    (clobber (reg:DF 26))
10760    (clobber (reg:DF 27))
10761    (clobber (reg:DF 28))
10762    (clobber (reg:DF 29))
10763    (clobber (reg:DF 30))
10764    (clobber (reg:DF 31))]
10765 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10766 ; not supposed to be used for immediates (see genpreds.c).
10767   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10768   "tbegin\t%1,%x0"
10769   [(set_attr "op_type" "SIL")])
10770
10771 ; Same as above but without the FPR clobbers
10772 (define_insn "tbegin_nofloat_1"
10773   [(set (reg:CCRAW CC_REGNUM)
10774         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10775                                UNSPECV_TBEGIN))
10776    (set (match_operand:BLK 1 "memory_operand" "=Q")
10777         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10778   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10779   "tbegin\t%1,%x0"
10780   [(set_attr "op_type" "SIL")])
10781
10782
10783 ; Constrained transaction begin
10784
10785 (define_expand "tbeginc"
10786   [(set (reg:CCRAW CC_REGNUM)
10787         (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10788                                UNSPECV_TBEGINC))]
10789   "TARGET_HTM"
10790   "")
10791
10792 (define_insn "*tbeginc_1"
10793   [(set (reg:CCRAW CC_REGNUM)
10794         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10795                                UNSPECV_TBEGINC))]
10796   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10797   "tbeginc\t0,%x0"
10798   [(set_attr "op_type" "SIL")])
10799
10800 ; Transaction end
10801
10802 (define_expand "tend"
10803   [(set (reg:CCRAW CC_REGNUM)
10804         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10805    (set (match_operand:SI 0 "register_operand" "")
10806         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10807   "TARGET_HTM"
10808   "")
10809
10810 (define_insn "*tend_1"
10811   [(set (reg:CCRAW CC_REGNUM)
10812         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10813   "TARGET_HTM"
10814   "tend"
10815   [(set_attr "op_type" "S")])
10816
10817 ; Transaction abort
10818
10819 (define_expand "tabort"
10820   [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10821                     UNSPECV_TABORT)]
10822   "TARGET_HTM && operands != NULL"
10823 {
10824   if (CONST_INT_P (operands[0])
10825       && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10826     {
10827       error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10828              ".  Values in range 0 through 255 are reserved.",
10829              INTVAL (operands[0]));
10830       FAIL;
10831     }
10832 })
10833
10834 (define_insn "*tabort_1"
10835   [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10836                     UNSPECV_TABORT)]
10837   "TARGET_HTM && operands != NULL"
10838   "tabort\t%Y0"
10839   [(set_attr "op_type" "S")])
10840
10841 ; Transaction extract nesting depth
10842
10843 (define_insn "etnd"
10844   [(set (match_operand:SI 0 "register_operand" "=d")
10845         (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10846   "TARGET_HTM"
10847   "etnd\t%0"
10848   [(set_attr "op_type" "RRE")])
10849
10850 ; Non-transactional store
10851
10852 (define_insn "ntstg"
10853   [(set (match_operand:DI 0 "memory_operand" "=RT")
10854         (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10855                             UNSPECV_NTSTG))]
10856   "TARGET_HTM"
10857   "ntstg\t%1,%0"
10858   [(set_attr "op_type" "RXY")])
10859
10860 ; Transaction perform processor assist
10861
10862 (define_expand "tx_assist"
10863   [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10864                      (reg:SI GPR0_REGNUM)
10865                      (const_int 1)]
10866                     UNSPECV_PPA)]
10867   "TARGET_HTM"
10868   "")
10869
10870 (define_insn "*ppa"
10871   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10872                      (match_operand:SI 1 "register_operand" "d")
10873                      (match_operand 2 "const_int_operand" "I")]
10874                     UNSPECV_PPA)]
10875   "TARGET_HTM && INTVAL (operands[2]) < 16"
10876   "ppa\t%0,%1,%2"
10877   [(set_attr "op_type" "RRF")])
10878
10879
10880 ; Set and get floating point control register
10881
10882 (define_insn "sfpc"
10883   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10884                     UNSPECV_SFPC)]
10885   "TARGET_HARD_FLOAT"
10886   "sfpc\t%0")
10887
10888 (define_insn "efpc"
10889   [(set (match_operand:SI 0 "register_operand" "=d")
10890         (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10891   "TARGET_HARD_FLOAT"
10892   "efpc\t%0")
10893
10894
10895 ; Load count to block boundary
10896
10897 (define_insn "lcbb"
10898   [(set (match_operand:SI             0 "register_operand"  "=d")
10899         (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR")
10900                     (match_operand:SI 2 "immediate_operand"  "C")] UNSPEC_LCBB))
10901    (clobber (reg:CC CC_REGNUM))]
10902   "TARGET_Z13"
10903   "lcbb\t%0,%1,%b2"
10904   [(set_attr "op_type" "VRX")])