gcc/config/s390/s390.md

   1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
   2 ;;  Copyright (C) 1999-2016 Free Software Foundation, Inc.
   3 ;;  Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                 Ulrich Weigand (uweigand@de.ibm.com) and
   5 ;;                 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify it under
  10 ;; the terms of the GNU General Public License as published by the Free
  11 ;; Software Foundation; either version 3, or (at your option) any later
  12 ;; version.
  13
  14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 ;; for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;;
  24 ;; See constraints.md for a description of constraints specific to s390.
  25 ;;
  26
  27 ;; Special formats used for outputting 390 instructions.
  28 ;;
  29 ;;     %C: print opcode suffix for branch condition.
  30 ;;     %D: print opcode suffix for inverse branch condition.
  31 ;;     %J: print tls_load/tls_gdcall/tls_ldcall suffix
  32 ;;     %G: print the size of the operand in bytes.
  33 ;;     %O: print only the displacement of a memory reference.
  34 ;;     %R: print only the base register of a memory reference.
  35 ;;     %S: print S-type memory reference (base+displacement).
  36 ;;     %N: print the second word of a DImode operand.
  37 ;;     %M: print the second word of a TImode operand.
  38 ;;     %Y: print shift count operand.
  39 ;;
  40 ;;     %b: print integer X as if it's an unsigned byte.
  41 ;;     %c: print integer X as if it's an signed byte.
  42 ;;     %x: print integer X as if it's an unsigned halfword.
  43 ;;     %h: print integer X as if it's a signed halfword.
  44 ;;     %i: print the first nonzero HImode part of X.
  45 ;;     %j: print the first HImode part unequal to -1 of X.
  46 ;;     %k: print the first nonzero SImode part of X.
  47 ;;     %m: print the first SImode part unequal to -1 of X.
  48 ;;     %o: print integer X as if it's an unsigned 32bit word.
  49 ;;
  50 ;; We have a special constraint for pattern matching.
  51 ;;
  52 ;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
  53 ;;
  54
  55 ;;
  56 ;; UNSPEC usage
  57 ;;
  58
  59 (define_c_enum "unspec" [
  60    ; Miscellaneous
  61    UNSPEC_ROUND
  62    UNSPEC_ICM
  63    UNSPEC_TIE
  64
  65    ; Convert CC into a str comparison result and copy it into an
  66    ; integer register
  67    ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
  68    UNSPEC_STRCMPCC_TO_INT
  69
  70    ; Copy CC as is into the lower 2 bits of an integer register
  71    UNSPEC_CC_TO_INT
  72
  73    ; The right hand side of an setmem
  74    UNSPEC_REPLICATE_BYTE
  75
  76    ; GOT/PLT and lt-relative accesses
  77    UNSPEC_LTREL_OFFSET
  78    UNSPEC_LTREL_BASE
  79    UNSPEC_POOL_OFFSET
  80    UNSPEC_GOTENT
  81    UNSPEC_GOT
  82    UNSPEC_GOTOFF
  83    UNSPEC_PLT
  84    UNSPEC_PLTOFF
  85
  86    ; Literal pool
  87    UNSPEC_RELOAD_BASE
  88    UNSPEC_MAIN_BASE
  89    UNSPEC_LTREF
  90    UNSPEC_INSN
  91    UNSPEC_EXECUTE
  92
  93    ; Atomic Support
  94    UNSPEC_MB
  95    UNSPEC_MOVA
  96
  97    ; TLS relocation specifiers
  98    UNSPEC_TLSGD
  99    UNSPEC_TLSLDM
 100    UNSPEC_NTPOFF
 101    UNSPEC_DTPOFF
 102    UNSPEC_GOTNTPOFF
 103    UNSPEC_INDNTPOFF
 104
 105    ; TLS support
 106    UNSPEC_TLSLDM_NTPOFF
 107    UNSPEC_TLS_LOAD
 108
 109    ; String Functions
 110    UNSPEC_SRST
 111    UNSPEC_MVST
 112
 113    ; Stack Smashing Protector
 114    UNSPEC_SP_SET
 115    UNSPEC_SP_TEST
 116
 117    ; Split stack support
 118    UNSPEC_STACK_CHECK
 119
 120    ; Test Data Class (TDC)
 121    UNSPEC_TDC_INSN
 122
 123    ; Population Count
 124    UNSPEC_POPCNT
 125    UNSPEC_COPYSIGN
 126
 127    ; Load FP Integer
 128    UNSPEC_FPINT_FLOOR
 129    UNSPEC_FPINT_BTRUNC
 130    UNSPEC_FPINT_ROUND
 131    UNSPEC_FPINT_CEIL
 132    UNSPEC_FPINT_NEARBYINT
 133    UNSPEC_FPINT_RINT
 134
 135    UNSPEC_LCBB
 136
 137    ; Vector
 138    UNSPEC_VEC_SMULT_HI
 139    UNSPEC_VEC_UMULT_HI
 140    UNSPEC_VEC_SMULT_LO
 141    UNSPEC_VEC_SMULT_EVEN
 142    UNSPEC_VEC_UMULT_EVEN
 143    UNSPEC_VEC_SMULT_ODD
 144    UNSPEC_VEC_UMULT_ODD
 145
 146    UNSPEC_VEC_VMAL
 147    UNSPEC_VEC_VMAH
 148    UNSPEC_VEC_VMALH
 149    UNSPEC_VEC_VMAE
 150    UNSPEC_VEC_VMALE
 151    UNSPEC_VEC_VMAO
 152    UNSPEC_VEC_VMALO
 153
 154    UNSPEC_VEC_GATHER
 155    UNSPEC_VEC_EXTRACT
 156    UNSPEC_VEC_INSERT_AND_ZERO
 157    UNSPEC_VEC_LOAD_BNDRY
 158    UNSPEC_VEC_LOAD_LEN
 159    UNSPEC_VEC_MERGEH
 160    UNSPEC_VEC_MERGEL
 161    UNSPEC_VEC_PACK
 162    UNSPEC_VEC_PACK_SATURATE
 163    UNSPEC_VEC_PACK_SATURATE_CC
 164    UNSPEC_VEC_PACK_SATURATE_GENCC
 165    UNSPEC_VEC_PACK_UNSIGNED_SATURATE
 166    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
 167    UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
 168    UNSPEC_VEC_PERM
 169    UNSPEC_VEC_PERMI
 170    UNSPEC_VEC_EXTEND
 171    UNSPEC_VEC_STORE_LEN
 172    UNSPEC_VEC_UNPACKH
 173    UNSPEC_VEC_UNPACKH_L
 174    UNSPEC_VEC_UNPACKL
 175    UNSPEC_VEC_UNPACKL_L
 176    UNSPEC_VEC_ADDC
 177    UNSPEC_VEC_ADDC_U128
 178    UNSPEC_VEC_ADDE_U128
 179    UNSPEC_VEC_ADDEC_U128
 180    UNSPEC_VEC_AVG
 181    UNSPEC_VEC_AVGU
 182    UNSPEC_VEC_CHECKSUM
 183    UNSPEC_VEC_GFMSUM
 184    UNSPEC_VEC_GFMSUM_128
 185    UNSPEC_VEC_GFMSUM_ACCUM
 186    UNSPEC_VEC_GFMSUM_ACCUM_128
 187    UNSPEC_VEC_SET
 188
 189    UNSPEC_VEC_VSUMG
 190    UNSPEC_VEC_VSUMQ
 191    UNSPEC_VEC_VSUM
 192    UNSPEC_VEC_RL_MASK
 193    UNSPEC_VEC_SLL
 194    UNSPEC_VEC_SLB
 195    UNSPEC_VEC_SLDB
 196    UNSPEC_VEC_SRAL
 197    UNSPEC_VEC_SRAB
 198    UNSPEC_VEC_SRL
 199    UNSPEC_VEC_SRLB
 200
 201    UNSPEC_VEC_SUB_U128
 202    UNSPEC_VEC_SUBC
 203    UNSPEC_VEC_SUBC_U128
 204    UNSPEC_VEC_SUBE_U128
 205    UNSPEC_VEC_SUBEC_U128
 206
 207    UNSPEC_VEC_TEST_MASK
 208
 209    UNSPEC_VEC_VFAE
 210    UNSPEC_VEC_VFAECC
 211
 212    UNSPEC_VEC_VFEE
 213    UNSPEC_VEC_VFEECC
 214    UNSPEC_VEC_VFENE
 215    UNSPEC_VEC_VFENECC
 216
 217    UNSPEC_VEC_VISTR
 218    UNSPEC_VEC_VISTRCC
 219
 220    UNSPEC_VEC_VSTRC
 221    UNSPEC_VEC_VSTRCCC
 222
 223    UNSPEC_VEC_VCDGB
 224    UNSPEC_VEC_VCDLGB
 225
 226    UNSPEC_VEC_VCGDB
 227    UNSPEC_VEC_VCLGDB
 228
 229    UNSPEC_VEC_VFIDB
 230
 231    UNSPEC_VEC_VLDEB
 232    UNSPEC_VEC_VLEDB
 233
 234    UNSPEC_VEC_VFTCIDB
 235    UNSPEC_VEC_VFTCIDBCC
 236 ])
 237
 238 ;;
 239 ;; UNSPEC_VOLATILE usage
 240 ;;
 241
 242 (define_c_enum "unspecv" [
 243    ; Blockage
 244    UNSPECV_BLOCKAGE
 245
 246    ; TPF Support
 247    UNSPECV_TPF_PROLOGUE
 248    UNSPECV_TPF_EPILOGUE
 249
 250    ; Literal pool
 251    UNSPECV_POOL
 252    UNSPECV_POOL_SECTION
 253    UNSPECV_POOL_ALIGN
 254    UNSPECV_POOL_ENTRY
 255    UNSPECV_MAIN_POOL
 256
 257    ; TLS support
 258    UNSPECV_SET_TP
 259
 260    ; Atomic Support
 261    UNSPECV_CAS
 262    UNSPECV_ATOMIC_OP
 263
 264    ; Hotpatching (unremovable NOPs)
 265    UNSPECV_NOP_2_BYTE
 266    UNSPECV_NOP_4_BYTE
 267    UNSPECV_NOP_6_BYTE
 268
 269    ; Transactional Execution support
 270    UNSPECV_TBEGIN
 271    UNSPECV_TBEGIN_TDB
 272    UNSPECV_TBEGINC
 273    UNSPECV_TEND
 274    UNSPECV_TABORT
 275    UNSPECV_ETND
 276    UNSPECV_NTSTG
 277    UNSPECV_PPA
 278
 279    ; Set and get floating point control register
 280    UNSPECV_SFPC
 281    UNSPECV_EFPC
 282
 283    ; Split stack support
 284    UNSPECV_SPLIT_STACK_CALL
 285    UNSPECV_SPLIT_STACK_DATA
 286   ])
 287
 288 ;;
 289 ;; Registers
 290 ;;
 291
 292 ; Registers with special meaning
 293
 294 (define_constants
 295   [
 296    ; Sibling call register.
 297    (SIBCALL_REGNUM               1)
 298    ; Literal pool base register.
 299    (BASE_REGNUM                 13)
 300    ; Return address register.
 301    (RETURN_REGNUM               14)
 302    ; Condition code register.
 303    (CC_REGNUM                   33)
 304    ; Thread local storage pointer register.
 305    (TP_REGNUM                   36)
 306   ])
 307
 308 ; Hardware register names
 309
 310 (define_constants
 311   [
 312    ; General purpose registers
 313    (GPR0_REGNUM                  0)
 314    (GPR1_REGNUM                  1)
 315    (GPR2_REGNUM                  2)
 316    (GPR6_REGNUM                  6)
 317    ; Floating point registers.
 318    (FPR0_REGNUM                 16)
 319    (FPR1_REGNUM                 20)
 320    (FPR2_REGNUM                 17)
 321    (FPR3_REGNUM                 21)
 322    (FPR4_REGNUM                 18)
 323    (FPR5_REGNUM                 22)
 324    (FPR6_REGNUM                 19)
 325    (FPR7_REGNUM                 23)
 326    (FPR8_REGNUM                 24)
 327    (FPR9_REGNUM                 28)
 328    (FPR10_REGNUM                25)
 329    (FPR11_REGNUM                29)
 330    (FPR12_REGNUM                26)
 331    (FPR13_REGNUM                30)
 332    (FPR14_REGNUM                27)
 333    (FPR15_REGNUM                31)
 334    (VR0_REGNUM                  16)
 335    (VR16_REGNUM                 38)
 336    (VR23_REGNUM                 45)
 337    (VR24_REGNUM                 46)
 338    (VR31_REGNUM                 53)
 339   ])
 340
 341 ;;
 342 ;; PFPO GPR0 argument format
 343 ;;
 344
 345 (define_constants
 346   [
 347    ; PFPO operation type
 348    (PFPO_CONVERT          0x1000000)
 349    ; PFPO operand types
 350    (PFPO_OP_TYPE_SF             0x5)
 351    (PFPO_OP_TYPE_DF             0x6)
 352    (PFPO_OP_TYPE_TF             0x7)
 353    (PFPO_OP_TYPE_SD             0x8)
 354    (PFPO_OP_TYPE_DD             0x9)
 355    (PFPO_OP_TYPE_TD             0xa)
 356    ; Bitposition of operand types
 357    (PFPO_OP0_TYPE_SHIFT          16)
 358    (PFPO_OP1_TYPE_SHIFT           8)
 359   ])
 360
 361 ; Immediate operands for tbegin and tbeginc
 362 (define_constants [(TBEGIN_MASK  65292)]) ; 0xff0c
 363 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
 364
 365 ;; Instruction operand type as used in the Principles of Operation.
 366 ;; Used to determine defaults for length and other attribute values.
 367
 368 (define_attr "op_type"
 369   "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
 370   (const_string "NN"))
 371
 372 ;; Instruction type attribute used for scheduling.
 373
 374 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
 375                      cs,vs,store,sem,idiv,
 376                      imulhi,imulsi,imuldi,
 377                      branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
 378                      floadtf,floaddf,floadsf,fstoredf,fstoresf,
 379                      fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
 380                      ftoi,fsqrttf,fsqrtdf,fsqrtsf,
 381                      fmadddf,fmaddsf,
 382                      ftrunctf,ftruncdf, ftruncsd, ftruncdd,
 383                      itoftf, itofdf, itofsf, itofdd, itoftd,
 384                      fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
 385                      fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
 386                      ftoidfp, other"
 387   (cond [(eq_attr "op_type" "NN")  (const_string "other")
 388          (eq_attr "op_type" "SS")  (const_string "cs")]
 389     (const_string "integer")))
 390
 391 ;; Another attribute used for scheduling purposes:
 392 ;;   agen: Instruction uses the address generation unit
 393 ;;   reg: Instruction does not use the agen unit
 394
 395 (define_attr "atype" "agen,reg"
 396   (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
 397                 (const_string "reg")
 398                 (const_string "agen")))
 399
 400 ;; Properties concerning Z10 execution grouping and value forwarding.
 401 ;; z10_super: instruction is superscalar.
 402 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
 403 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
 404 ;;   target register.  It can forward this value to a second instruction that reads
 405 ;;   the same register if that second instruction is issued in the same group.
 406 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
 407 ;;   instruction in the S pipe writes to the register, then the T instruction
 408 ;;   can immediately read the new value.
 409 ;; z10_fr: union of Z10_fwd and z10_rec.
 410 ;; z10_c: second operand of instruction is a register and read with complemented bits.
 411 ;;
 412 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
 413
 414
 415 (define_attr "z10prop" "none,
 416                         z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
 417                         z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
 418                         z10_rec,
 419                         z10_fr, z10_fr_A3, z10_fr_E1,
 420                         z10_c"
 421              (const_string "none"))
 422
 423 ;; Properties concerning Z196 decoding
 424 ;; z196_alone: must group alone
 425 ;; z196_end: ends a group
 426 ;; z196_cracked: instruction is cracked or expanded
 427 (define_attr "z196prop" "none,
 428                          z196_alone, z196_ends,
 429                          z196_cracked"
 430              (const_string "none"))
 431
 432 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
 433
 434 ;; Length in bytes.
 435
 436 (define_attr "length" ""
 437   (cond [(eq_attr "op_type" "E,RR")                       (const_int 2)
 438          (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF")  (const_int 4)]
 439     (const_int 6)))
 440
 441
 442 ;; Processor type.  This attribute must exactly match the processor_type
 443 ;; enumeration in s390.h.  The current machine description does not
 444 ;; distinguish between g5 and g6, but there are differences between the two
 445 ;; CPUs could in theory be modeled.
 446
 447 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
 448   (const (symbol_ref "s390_tune_attr")))
 449
 450 (define_attr "cpu_facility"
 451   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
 452   (const_string "standard"))
 453
 454 (define_attr "enabled" ""
 455   (cond [(eq_attr "cpu_facility" "standard")
 456          (const_int 1)
 457
 458          (and (eq_attr "cpu_facility" "ieee")
 459               (match_test "TARGET_CPU_IEEE_FLOAT"))
 460          (const_int 1)
 461
 462          (and (eq_attr "cpu_facility" "zarch")
 463               (match_test "TARGET_ZARCH"))
 464          (const_int 1)
 465
 466          (and (eq_attr "cpu_facility" "longdisp")
 467               (match_test "TARGET_LONG_DISPLACEMENT"))
 468          (const_int 1)
 469
 470          (and (eq_attr "cpu_facility" "extimm")
 471               (match_test "TARGET_EXTIMM"))
 472          (const_int 1)
 473
 474          (and (eq_attr "cpu_facility" "dfp")
 475               (match_test "TARGET_DFP"))
 476          (const_int 1)
 477
 478          (and (eq_attr "cpu_facility" "cpu_zarch")
 479               (match_test "TARGET_CPU_ZARCH"))
 480          (const_int 1)
 481
 482          (and (eq_attr "cpu_facility" "z10")
 483               (match_test "TARGET_Z10"))
 484          (const_int 1)
 485
 486          (and (eq_attr "cpu_facility" "z196")
 487               (match_test "TARGET_Z196"))
 488          (const_int 1)
 489
 490          (and (eq_attr "cpu_facility" "zEC12")
 491               (match_test "TARGET_ZEC12"))
 492          (const_int 1)
 493
 494          (and (eq_attr "cpu_facility" "vec")
 495               (match_test "TARGET_VX"))
 496          (const_int 1)]
 497         (const_int 0)))
 498
 499 ;; Pipeline description for z900.  For lack of anything better,
 500 ;; this description is also used for the g5 and g6.
 501 (include "2064.md")
 502
 503 ;; Pipeline description for z990, z9-109 and z9-ec.
 504 (include "2084.md")
 505
 506 ;; Pipeline description for z10
 507 (include "2097.md")
 508
 509 ;; Pipeline description for z196
 510 (include "2817.md")
 511
 512 ;; Pipeline description for zEC12
 513 (include "2827.md")
 514
 515 ;; Pipeline description for z13
 516 (include "2964.md")
 517
 518 ;; Predicates
 519 (include "predicates.md")
 520
 521 ;; Constraint definitions
 522 (include "constraints.md")
 523
 524 ;; Other includes
 525 (include "tpf.md")
 526
 527 ;; Iterators
 528
 529 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
 530
 531 ;; These mode iterators allow floating point patterns to be generated from the
 532 ;; same template.
 533 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
 534                               (SD "TARGET_HARD_DFP")])
 535 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
 536 (define_mode_iterator BFP [TF DF SF])
 537 (define_mode_iterator DFP [TD DD])
 538 (define_mode_iterator DFP_ALL [TD DD SD])
 539 (define_mode_iterator DSF [DF SF])
 540 (define_mode_iterator SD_SF [SF SD])
 541 (define_mode_iterator DD_DF [DF DD])
 542 (define_mode_iterator TD_TF [TF TD])
 543
 544 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 545 ;; from the same template.
 546 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
 547 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
 548 (define_mode_iterator DSI [DI SI])
 549 (define_mode_iterator TDI [TI DI])
 550
 551 ;; These mode iterators allow :P to be used for patterns that operate on
 552 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 553 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 554
 555 ;; These macros refer to the actual word_mode of the configuration.
 556 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
 557 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
 558 (define_mode_iterator W  [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
 559
 560 ;; Used by the umul pattern to express modes having half the size.
 561 (define_mode_attr DWH [(TI "DI") (DI "SI")])
 562 (define_mode_attr dwh [(TI "di") (DI "si")])
 563
 564 ;; This mode iterator allows the QI and HI patterns to be defined from
 565 ;; the same template.
 566 (define_mode_iterator HQI [HI QI])
 567
 568 ;; This mode iterator allows the integer patterns to be defined from the
 569 ;; same template.
 570 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
 571 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
 572
 573 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 574 ;; the same template.
 575 (define_code_iterator SHIFT [ashift lshiftrt])
 576
 577 ;; This iterator allows r[ox]sbg to be defined with the same template
 578 (define_code_iterator IXOR [ior xor])
 579
 580 ;; This iterator is used to expand the patterns for the nearest
 581 ;; integer functions.
 582 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
 583                             UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
 584                             UNSPEC_FPINT_NEARBYINT])
 585 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
 586                              (UNSPEC_FPINT_BTRUNC "btrunc")
 587                              (UNSPEC_FPINT_ROUND "round")
 588                              (UNSPEC_FPINT_CEIL "ceil")
 589                              (UNSPEC_FPINT_NEARBYINT "nearbyint")])
 590 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
 591                                      (UNSPEC_FPINT_BTRUNC "5")
 592                                      (UNSPEC_FPINT_ROUND "1")
 593                                      (UNSPEC_FPINT_CEIL "6")
 594                                      (UNSPEC_FPINT_NEARBYINT "0")])
 595
 596 ;; This iterator and attribute allow to combine most atomic operations.
 597 (define_code_iterator ATOMIC [and ior xor plus minus mult])
 598 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
 599 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
 600                           (plus "add") (minus "sub") (mult "nand")])
 601 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
 602
 603 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
 604 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
 605 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
 606
 607 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
 608 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
 609 ;; SDmode.
 610 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
 611
 612 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 613 ;; Likewise for "<RXe>".
 614 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 615 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 616
 617 ;; The decimal floating point variants of add, sub, div and mul support 3
 618 ;; fp register operands.  The following attributes allow to merge the bfp and
 619 ;; dfp variants in a single insn definition.
 620
 621 ;; These mode attributes are supposed to be used in the `enabled' insn
 622 ;; attribute to disable certain alternatives for certain modes.
 623 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
 624 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
 625 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
 626 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
 627                         (TD "0") (DD "0") (DD "0")
 628                         (TI "0") (DI "*") (SI "0")])
 629
 630 ;; This attribute is used in the operand constraint list
 631 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
 632 ;; TFmode values are represented by a fp register pair.  Since the
 633 ;; sign bit instructions only handle single source and target fp registers
 634 ;; these instructions can only be used for TFmode values if the source and
 635 ;; target operand uses the same fp register.
 636 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 637
 638 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 639 ;; within instruction mnemonics.
 640 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 641
 642 ;; This attribute is used within instruction mnemonics.  It evaluates to d for dfp
 643 ;; modes and to an empty string for bfp modes.
 644 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
 645
 646 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
 647 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
 648 ;; version only operates on one register.
 649 (define_mode_attr d0 [(DI "d") (SI "0")])
 650
 651 ;; In combination with d0 this allows to combine instructions of which the 31bit
 652 ;; version only operates on one register. The DImode version needs an additional
 653 ;; register for the assembler output.
 654 (define_mode_attr 1 [(DI "%1,") (SI "")])
 655
 656 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
 657 ;; 'ashift' and "srdl" in 'lshiftrt'.
 658 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
 659
 660 ;; In SHIFT templates, this attribute holds the correct standard name for the
 661 ;; pattern itself and the corresponding function calls.
 662 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
 663
 664 ;; This attribute handles differences in the instruction 'type' and will result
 665 ;; in "RRE" for DImode and "RR" for SImode.
 666 (define_mode_attr E [(DI "E") (SI "")])
 667
 668 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
 669 ;; to result in "RXY" for DImode and "RX" for SImode.
 670 (define_mode_attr Y [(DI "Y") (SI "")])
 671
 672 ;; This attribute handles differences in the instruction 'type' and will result
 673 ;; in "RSE" for TImode and "RS" for DImode.
 674 (define_mode_attr TE [(TI "E") (DI "")])
 675
 676 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
 677 ;; and "lcr" in SImode.
 678 (define_mode_attr g [(DI "g") (SI "")])
 679
 680 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
 681 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
 682 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
 683 ;; variant for long displacements.
 684 (define_mode_attr y [(DI "g") (SI "y")])
 685
 686 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
 687 ;; and "cds" in DImode.
 688 (define_mode_attr tg [(TI "g") (DI "")])
 689
 690 ;; In TDI templates, a string like "c<d>sg".
 691 (define_mode_attr td [(TI "d") (DI "")])
 692
 693 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
 694 ;; and "cfdbr" in SImode.
 695 (define_mode_attr gf [(DI "g") (SI "f")])
 696
 697 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
 698 ;; and sllk for SI.  This way it is possible to merge the new z196 SI
 699 ;; 3 operands shift instructions into the existing patterns.
 700 (define_mode_attr gk [(DI "g") (SI "k")])
 701
 702 ;; ICM mask required to load MODE value into the lowest subreg
 703 ;; of a SImode register.
 704 (define_mode_attr icm_lo [(HI "3") (QI "1")])
 705
 706 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
 707 ;; HImode and "llgc" in QImode.
 708 (define_mode_attr hc [(HI "h") (QI "c")])
 709
 710 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
 711 ;; in SImode.
 712 (define_mode_attr DBL [(DI "TI") (SI "DI")])
 713
 714 ;; This attribute expands to DF for TFmode and to DD for TDmode .  It is
 715 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
 716 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
 717
 718 ;; Maximum unsigned integer that fits in MODE.
 719 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 720
 721 ;; Start and end field computations for RISBG et al.
 722 (define_mode_attr bfstart [(DI "s") (SI "t")])
 723 (define_mode_attr bfend   [(DI "e") (SI "f")])
 724
 725 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 726 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
 727
 728 ;; In place of GET_MODE_SIZE (<MODE>mode)
 729 (define_mode_attr modesize [(DI "8") (SI "4")])
 730
 731 ;; Allow return and simple_return to be defined from a single template.
 732 (define_code_iterator ANY_RETURN [return simple_return])
 733
 734
 735
 736 ; Condition code modes generated by vector fp comparisons.  These will
 737 ; be used also in single element mode.
 738 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
 739 ; Used with VFCMP to expand part of the mnemonic
 740 ; For fp we have a mismatch: eq in the insn name - e in asm
 741 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 742 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
 743
 744 ;; Subst pattern definitions
 745 (include "subst.md")
 746
 747 (include "vector.md")
 748
 749 ;;
 750 ;;- Compare instructions.
 751 ;;
 752
 753 ; Test-under-Mask instructions
 754
 755 (define_insn "*tmqi_mem"
 756   [(set (reg CC_REGNUM)
 757         (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
 758                          (match_operand:QI 1 "immediate_operand" "n,n"))
 759                  (match_operand:QI 2 "immediate_operand" "n,n")))]
 760   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
 761   "@
 762    tm\t%S0,%b1
 763    tmy\t%S0,%b1"
 764   [(set_attr "op_type" "SI,SIY")
 765    (set_attr "z10prop" "z10_super,z10_super")])
 766
 767 (define_insn "*tmdi_reg"
 768   [(set (reg CC_REGNUM)
 769         (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
 770                          (match_operand:DI 1 "immediate_operand"
 771                                              "N0HD0,N1HD0,N2HD0,N3HD0"))
 772                  (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
 773   "TARGET_ZARCH
 774    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 775    && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
 776   "@
 777    tmhh\t%0,%i1
 778    tmhl\t%0,%i1
 779    tmlh\t%0,%i1
 780    tmll\t%0,%i1"
 781   [(set_attr "op_type" "RI")
 782    (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
 783
 784 (define_insn "*tmsi_reg"
 785   [(set (reg CC_REGNUM)
 786         (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
 787                          (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
 788                  (match_operand:SI 2 "immediate_operand" "n,n")))]
 789   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
 790    && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
 791   "@
 792    tmh\t%0,%i1
 793    tml\t%0,%i1"
 794   [(set_attr "op_type" "RI")
 795    (set_attr "z10prop" "z10_super,z10_super")])
 796
 797 (define_insn "*tm<mode>_full"
 798   [(set (reg CC_REGNUM)
 799         (compare (match_operand:HQI 0 "register_operand" "d")
 800                  (match_operand:HQI 1 "immediate_operand" "n")))]
 801   "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
 802   "tml\t%0,<max_uint>"
 803   [(set_attr "op_type" "RI")
 804    (set_attr "z10prop" "z10_super")])
 805
 806
 807 ;
 808 ; Load-and-Test instructions
 809 ;
 810
 811 ; tst(di|si) instruction pattern(s).
 812
 813 (define_insn "*tstdi_sign"
 814   [(set (reg CC_REGNUM)
 815         (compare
 816           (ashiftrt:DI
 817             (ashift:DI
 818               (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
 819               (const_int 32)) (const_int 32))
 820           (match_operand:DI 1 "const0_operand" "")))
 821    (set (match_operand:DI 2 "register_operand" "=d,d")
 822         (sign_extend:DI (match_dup 0)))]
 823   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
 824   "ltgfr\t%2,%0
 825    ltgf\t%2,%0"
 826   [(set_attr "op_type"      "RRE,RXY")
 827    (set_attr "cpu_facility" "*,z10")
 828    (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
 829
 830 ; ltr, lt, ltgr, ltg
 831 (define_insn "*tst<mode>_extimm"
 832   [(set (reg CC_REGNUM)
 833         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 834                  (match_operand:GPR 1 "const0_operand" "")))
 835    (set (match_operand:GPR 2 "register_operand" "=d,d")
 836         (match_dup 0))]
 837   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 838   "@
 839    lt<g>r\t%2,%0
 840    lt<g>\t%2,%0"
 841   [(set_attr "op_type" "RR<E>,RXY")
 842    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
 843
 844 ; ltr, lt, ltgr, ltg
 845 (define_insn "*tst<mode>_cconly_extimm"
 846   [(set (reg CC_REGNUM)
 847         (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
 848                  (match_operand:GPR 1 "const0_operand" "")))
 849    (clobber (match_scratch:GPR 2 "=X,d"))]
 850   "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
 851   "@
 852    lt<g>r\t%0,%0
 853    lt<g>\t%2,%0"
 854   [(set_attr "op_type" "RR<E>,RXY")
 855    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
 856
 857 (define_insn "*tstdi"
 858   [(set (reg CC_REGNUM)
 859         (compare (match_operand:DI 0 "register_operand" "d")
 860                  (match_operand:DI 1 "const0_operand" "")))
 861    (set (match_operand:DI 2 "register_operand" "=d")
 862         (match_dup 0))]
 863   "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
 864   "ltgr\t%2,%0"
 865   [(set_attr "op_type" "RRE")
 866    (set_attr "z10prop" "z10_fr_E1")])
 867
 868 (define_insn "*tstsi"
 869   [(set (reg CC_REGNUM)
 870         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 871                  (match_operand:SI 1 "const0_operand" "")))
 872    (set (match_operand:SI 2 "register_operand" "=d,d,d")
 873         (match_dup 0))]
 874   "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
 875   "@
 876    ltr\t%2,%0
 877    icm\t%2,15,%S0
 878    icmy\t%2,15,%S0"
 879   [(set_attr "op_type" "RR,RS,RSY")
 880    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 881
 882 (define_insn "*tstsi_cconly"
 883   [(set (reg CC_REGNUM)
 884         (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
 885                  (match_operand:SI 1 "const0_operand" "")))
 886    (clobber (match_scratch:SI 2 "=X,d,d"))]
 887   "s390_match_ccmode(insn, CCSmode)"
 888   "@
 889    ltr\t%0,%0
 890    icm\t%2,15,%S0
 891    icmy\t%2,15,%S0"
 892   [(set_attr "op_type" "RR,RS,RSY")
 893    (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
 894
 895 (define_insn "*tstdi_cconly_31"
 896   [(set (reg CC_REGNUM)
 897         (compare (match_operand:DI 0 "register_operand" "d")
 898                  (match_operand:DI 1 "const0_operand" "")))]
 899   "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
 900   "srda\t%0,0"
 901   [(set_attr "op_type" "RS")
 902    (set_attr "atype"   "reg")])
 903
 904 ; ltr, ltgr
 905 (define_insn "*tst<mode>_cconly2"
 906   [(set (reg CC_REGNUM)
 907         (compare (match_operand:GPR 0 "register_operand" "d")
 908                  (match_operand:GPR 1 "const0_operand" "")))]
 909   "s390_match_ccmode(insn, CCSmode)"
 910   "lt<g>r\t%0,%0"
 911   [(set_attr "op_type" "RR<E>")
 912    (set_attr "z10prop" "z10_fr_E1")])
 913
 914 ; tst(hi|qi) instruction pattern(s).
 915
 916 (define_insn "*tst<mode>CCT"
 917   [(set (reg CC_REGNUM)
 918         (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
 919                  (match_operand:HQI 1 "const0_operand" "")))
 920    (set (match_operand:HQI 2 "register_operand" "=d,d,0")
 921         (match_dup 0))]
 922   "s390_match_ccmode(insn, CCTmode)"
 923   "@
 924    icm\t%2,<icm_lo>,%S0
 925    icmy\t%2,<icm_lo>,%S0
 926    tml\t%0,<max_uint>"
 927   [(set_attr "op_type" "RS,RSY,RI")
 928    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 929
 930 (define_insn "*tsthiCCT_cconly"
 931   [(set (reg CC_REGNUM)
 932         (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
 933                  (match_operand:HI 1 "const0_operand" "")))
 934    (clobber (match_scratch:HI 2 "=d,d,X"))]
 935   "s390_match_ccmode(insn, CCTmode)"
 936   "@
 937    icm\t%2,3,%S0
 938    icmy\t%2,3,%S0
 939    tml\t%0,65535"
 940   [(set_attr "op_type" "RS,RSY,RI")
 941    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
 942
 943 (define_insn "*tstqiCCT_cconly"
 944   [(set (reg CC_REGNUM)
 945         (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
 946                  (match_operand:QI 1 "const0_operand" "")))]
 947   "s390_match_ccmode(insn, CCTmode)"
 948   "@
 949    cli\t%S0,0
 950    cliy\t%S0,0
 951    tml\t%0,255"
 952   [(set_attr "op_type" "SI,SIY,RI")
 953    (set_attr "z10prop" "z10_super,z10_super,z10_super")])
 954
 955 (define_insn "*tst<mode>"
 956   [(set (reg CC_REGNUM)
 957         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 958                  (match_operand:HQI 1 "const0_operand" "")))
 959    (set (match_operand:HQI 2 "register_operand" "=d,d")
 960         (match_dup 0))]
 961   "s390_match_ccmode(insn, CCSmode)"
 962   "@
 963    icm\t%2,<icm_lo>,%S0
 964    icmy\t%2,<icm_lo>,%S0"
 965   [(set_attr "op_type" "RS,RSY")
 966    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 967
 968 (define_insn "*tst<mode>_cconly"
 969   [(set (reg CC_REGNUM)
 970         (compare (match_operand:HQI 0 "s_operand" "Q,S")
 971                  (match_operand:HQI 1 "const0_operand" "")))
 972    (clobber (match_scratch:HQI 2 "=d,d"))]
 973   "s390_match_ccmode(insn, CCSmode)"
 974   "@
 975    icm\t%2,<icm_lo>,%S0
 976    icmy\t%2,<icm_lo>,%S0"
 977   [(set_attr "op_type" "RS,RSY")
 978    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
 979
 980
 981 ; Compare (equality) instructions
 982
 983 (define_insn "*cmpdi_cct"
 984   [(set (reg CC_REGNUM)
 985         (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
 986                  (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
 987   "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
 988   "@
 989    cgr\t%0,%1
 990    cghi\t%0,%h1
 991    cgfi\t%0,%1
 992    cg\t%0,%1
 993    #"
 994   [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
 995    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
 996
 997 (define_insn "*cmpsi_cct"
 998   [(set (reg CC_REGNUM)
 999         (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1000                  (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1001   "s390_match_ccmode (insn, CCTmode)"
1002   "@
1003    cr\t%0,%1
1004    chi\t%0,%h1
1005    cfi\t%0,%1
1006    c\t%0,%1
1007    cy\t%0,%1
1008    #"
1009   [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1010    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1011
1012 ; Compare (signed) instructions
1013
1014 (define_insn "*cmpdi_ccs_sign"
1015   [(set (reg CC_REGNUM)
1016         (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1017                                                      "d,RT,b"))
1018                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1019   "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1020   "@
1021    cgfr\t%0,%1
1022    cgf\t%0,%1
1023    cgfrl\t%0,%1"
1024   [(set_attr "op_type"      "RRE,RXY,RIL")
1025    (set_attr "z10prop" "z10_c,*,*")
1026    (set_attr "type"         "*,*,larl")])
1027
1028
1029
1030 (define_insn "*cmpsi_ccs_sign"
1031   [(set (reg CC_REGNUM)
1032         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1033                  (match_operand:SI 0 "register_operand" "d,d,d")))]
1034   "s390_match_ccmode(insn, CCSRmode)"
1035   "@
1036    ch\t%0,%1
1037    chy\t%0,%1
1038    chrl\t%0,%1"
1039   [(set_attr "op_type"      "RX,RXY,RIL")
1040    (set_attr "cpu_facility" "*,*,z10")
1041    (set_attr "type"         "*,*,larl")
1042    (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1043
1044 (define_insn "*cmphi_ccs_z10"
1045   [(set (reg CC_REGNUM)
1046         (compare (match_operand:HI 0 "s_operand"         "Q")
1047                  (match_operand:HI 1 "immediate_operand" "K")))]
1048   "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1049   "chhsi\t%0,%1"
1050   [(set_attr "op_type" "SIL")
1051    (set_attr "z196prop" "z196_cracked")])
1052
1053 (define_insn "*cmpdi_ccs_signhi_rl"
1054   [(set (reg CC_REGNUM)
1055         (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
1056                  (match_operand:GPR 0 "register_operand"  "d,d")))]
1057   "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1058   "@
1059    cgh\t%0,%1
1060    cghrl\t%0,%1"
1061   [(set_attr "op_type" "RXY,RIL")
1062    (set_attr "type"    "*,larl")])
1063
1064 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1065 (define_insn "*cmp<mode>_ccs"
1066   [(set (reg CC_REGNUM)
1067         (compare (match_operand:GPR 0 "nonimmediate_operand"
1068                                       "d,d,Q, d,d,d,d")
1069                  (match_operand:GPR 1 "general_operand"
1070                                       "d,K,K,Os,R,T,b")))]
1071   "s390_match_ccmode(insn, CCSmode)"
1072   "@
1073    c<g>r\t%0,%1
1074    c<g>hi\t%0,%h1
1075    c<g>hsi\t%0,%h1
1076    c<g>fi\t%0,%1
1077    c<g>\t%0,%1
1078    c<y>\t%0,%1
1079    c<g>rl\t%0,%1"
1080   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1081    (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
1082    (set_attr "type" "*,*,*,*,*,*,larl")
1083    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1084
1085
1086 ; Compare (unsigned) instructions
1087
1088 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1089   [(set (reg CC_REGNUM)
1090         (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1091                                           "larl_operand" "X")))
1092                  (match_operand:SI 0 "register_operand" "d")))]
1093   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1094   "clhrl\t%0,%1"
1095   [(set_attr "op_type" "RIL")
1096    (set_attr "type"    "larl")
1097    (set_attr "z10prop" "z10_super")])
1098
1099 ; clhrl, clghrl
1100 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1101   [(set (reg CC_REGNUM)
1102         (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1103                                           "larl_operand" "X")))
1104                  (match_operand:GPR 0 "register_operand" "d")))]
1105   "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1106   "cl<g>hrl\t%0,%1"
1107   [(set_attr "op_type" "RIL")
1108    (set_attr "type"    "larl")
1109    (set_attr "z10prop" "z10_super")])
1110
1111 (define_insn "*cmpdi_ccu_zero"
1112   [(set (reg CC_REGNUM)
1113         (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1114                                                         "d,RT,b"))
1115                  (match_operand:DI 0 "register_operand" "d, d,d")))]
1116   "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1117   "@
1118    clgfr\t%0,%1
1119    clgf\t%0,%1
1120    clgfrl\t%0,%1"
1121   [(set_attr "op_type"      "RRE,RXY,RIL")
1122    (set_attr "cpu_facility" "*,*,z10")
1123    (set_attr "type"         "*,*,larl")
1124    (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1125
1126 (define_insn "*cmpdi_ccu"
1127   [(set (reg CC_REGNUM)
1128         (compare (match_operand:DI 0 "nonimmediate_operand"
1129                                      "d, d,d,Q, d, Q,BQ")
1130                  (match_operand:DI 1 "general_operand"
1131                                      "d,Op,b,D,RT,BQ,Q")))]
1132   "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1133   "@
1134    clgr\t%0,%1
1135    clgfi\t%0,%1
1136    clgrl\t%0,%1
1137    clghsi\t%0,%x1
1138    clg\t%0,%1
1139    #
1140    #"
1141   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1142    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1143    (set_attr "type"         "*,*,larl,*,*,*,*")
1144    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1145
1146 (define_insn "*cmpsi_ccu"
1147   [(set (reg CC_REGNUM)
1148         (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1149                  (match_operand:SI 1 "general_operand"      "d,Os,b,D,R,T,BQ, Q")))]
1150   "s390_match_ccmode (insn, CCUmode)"
1151   "@
1152    clr\t%0,%1
1153    clfi\t%0,%o1
1154    clrl\t%0,%1
1155    clfhsi\t%0,%x1
1156    cl\t%0,%1
1157    cly\t%0,%1
1158    #
1159    #"
1160   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1161    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1162    (set_attr "type"         "*,*,larl,*,*,*,*,*")
1163    (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1164
1165 (define_insn "*cmphi_ccu"
1166   [(set (reg CC_REGNUM)
1167         (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1168                  (match_operand:HI 1 "general_operand"      "Q,S,D,BQ,Q")))]
1169   "s390_match_ccmode (insn, CCUmode)
1170    && !register_operand (operands[1], HImode)"
1171   "@
1172    clm\t%0,3,%S1
1173    clmy\t%0,3,%S1
1174    clhhsi\t%0,%1
1175    #
1176    #"
1177   [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1178    (set_attr "cpu_facility" "*,*,z10,*,*")
1179    (set_attr "z10prop" "*,*,z10_super,*,*")])
1180
1181 (define_insn "*cmpqi_ccu"
1182   [(set (reg CC_REGNUM)
1183         (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1184                  (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1185   "s390_match_ccmode (insn, CCUmode)
1186    && !register_operand (operands[1], QImode)"
1187   "@
1188    clm\t%0,1,%S1
1189    clmy\t%0,1,%S1
1190    cli\t%S0,%b1
1191    cliy\t%S0,%b1
1192    #
1193    #"
1194   [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1195    (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1196
1197
1198 ; Block compare (CLC) instruction patterns.
1199
1200 (define_insn "*clc"
1201   [(set (reg CC_REGNUM)
1202         (compare (match_operand:BLK 0 "memory_operand" "Q")
1203                  (match_operand:BLK 1 "memory_operand" "Q")))
1204    (use (match_operand 2 "const_int_operand" "n"))]
1205   "s390_match_ccmode (insn, CCUmode)
1206    && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1207   "clc\t%O0(%2,%R0),%S1"
1208   [(set_attr "op_type" "SS")])
1209
1210 (define_split
1211   [(set (reg CC_REGNUM)
1212         (compare (match_operand 0 "memory_operand" "")
1213                  (match_operand 1 "memory_operand" "")))]
1214   "reload_completed
1215    && s390_match_ccmode (insn, CCUmode)
1216    && GET_MODE (operands[0]) == GET_MODE (operands[1])
1217    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1218   [(parallel
1219     [(set (match_dup 0) (match_dup 1))
1220      (use (match_dup 2))])]
1221 {
1222   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1223   operands[0] = adjust_address (operands[0], BLKmode, 0);
1224   operands[1] = adjust_address (operands[1], BLKmode, 0);
1225
1226   operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1227                                  operands[0], operands[1]);
1228   operands[0] = SET_DEST (PATTERN (curr_insn));
1229 })
1230
1231
1232 ; (TF|DF|SF|TD|DD|SD) instructions
1233
1234 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1235 (define_insn "*cmp<mode>_ccs_0"
1236   [(set (reg CC_REGNUM)
1237         (compare (match_operand:FP 0 "register_operand" "f")
1238                  (match_operand:FP 1 "const0_operand"   "")))]
1239   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1240   "lt<xde><bt>r\t%0,%0"
1241    [(set_attr "op_type" "RRE")
1242     (set_attr "type"  "fsimp<mode>")])
1243
1244 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1245 (define_insn "*cmp<mode>_ccs"
1246   [(set (reg CC_REGNUM)
1247         (compare (match_operand:FP 0 "register_operand" "f,f")
1248                  (match_operand:FP 1 "general_operand"  "f,R")))]
1249   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1250   "@
1251    c<xde><bt>r\t%0,%1
1252    c<xde>b\t%0,%1"
1253    [(set_attr "op_type" "RRE,RXE")
1254     (set_attr "type"  "fsimp<mode>")
1255     (set_attr "enabled" "*,<DSF>")])
1256
1257 ; wfcedbs, wfchdbs, wfchedbs
1258 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1259   [(set (reg:VFCMP CC_REGNUM)
1260         (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1261                        (match_operand:DF 1 "register_operand" "v")))
1262    (clobber (match_scratch:V2DI 2 "=v"))]
1263   "TARGET_Z13 && TARGET_HARD_FLOAT"
1264   "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1265   [(set_attr "op_type" "VRR")])
1266
1267 ; Compare and Branch instructions
1268
1269 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1270 ; The following instructions do a complementary access of their second
1271 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1272 (define_insn "*cmp_and_br_signed_<mode>"
1273   [(set (pc)
1274         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1275                         [(match_operand:GPR 1 "register_operand"  "d,d")
1276                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1277                       (label_ref (match_operand 3 "" ""))
1278                       (pc)))
1279    (clobber (reg:CC CC_REGNUM))]
1280   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1281 {
1282   if (get_attr_length (insn) == 6)
1283     return which_alternative ?
1284       "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1285   else
1286     return which_alternative ?
1287       "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1288 }
1289   [(set_attr "op_type" "RIE")
1290    (set_attr "type"    "branch")
1291    (set_attr "z10prop" "z10_super_c,z10_super")
1292    (set (attr "length")
1293         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1294                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1295                                                        ; 10 byte for cgr/jg
1296
1297 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1298 ; The following instructions do a complementary access of their second
1299 ; operand (z10 only): clrj, clgrj, clr, clgr
1300 (define_insn "*cmp_and_br_unsigned_<mode>"
1301   [(set (pc)
1302         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1303                         [(match_operand:GPR 1 "register_operand"  "d,d")
1304                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1305                       (label_ref (match_operand 3 "" ""))
1306                       (pc)))
1307    (clobber (reg:CC CC_REGNUM))]
1308   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1309 {
1310   if (get_attr_length (insn) == 6)
1311     return which_alternative ?
1312       "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1313   else
1314     return which_alternative ?
1315       "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1316 }
1317   [(set_attr "op_type" "RIE")
1318    (set_attr "type"    "branch")
1319    (set_attr "z10prop" "z10_super_c,z10_super")
1320    (set (attr "length")
1321         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1322                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1323                                                        ; 10 byte for clgr/jg
1324
1325 ; And now the same two patterns as above but with a negated CC mask.
1326
1327 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1328 ; The following instructions do a complementary access of their second
1329 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1330 (define_insn "*icmp_and_br_signed_<mode>"
1331   [(set (pc)
1332         (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1333                         [(match_operand:GPR 1 "register_operand"  "d,d")
1334                          (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1335                       (pc)
1336                       (label_ref (match_operand 3 "" ""))))
1337    (clobber (reg:CC CC_REGNUM))]
1338   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1339 {
1340   if (get_attr_length (insn) == 6)
1341     return which_alternative ?
1342       "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1343   else
1344     return which_alternative ?
1345       "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1346 }
1347   [(set_attr "op_type" "RIE")
1348    (set_attr "type"    "branch")
1349    (set_attr "z10prop" "z10_super_c,z10_super")
1350    (set (attr "length")
1351         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1352                       (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1353                                                        ; 10 byte for cgr/jg
1354
1355 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1356 ; The following instructions do a complementary access of their second
1357 ; operand (z10 only): clrj, clgrj, clr, clgr
1358 (define_insn "*icmp_and_br_unsigned_<mode>"
1359   [(set (pc)
1360         (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1361                         [(match_operand:GPR 1 "register_operand"  "d,d")
1362                          (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1363                       (pc)
1364                       (label_ref (match_operand 3 "" ""))))
1365    (clobber (reg:CC CC_REGNUM))]
1366   "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1367 {
1368   if (get_attr_length (insn) == 6)
1369     return which_alternative ?
1370       "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1371   else
1372     return which_alternative ?
1373       "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1374 }
1375   [(set_attr "op_type" "RIE")
1376    (set_attr "type"    "branch")
1377    (set_attr "z10prop" "z10_super_c,z10_super")
1378    (set (attr "length")
1379         (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1380                       (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1381                                                        ; 10 byte for clgr/jg
1382
1383 ;;
1384 ;;- Move instructions.
1385 ;;
1386
1387 ;
1388 ; movti instruction pattern(s).
1389 ;
1390
1391 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1392 ; for TImode (use double-int for the calculations)
1393 (define_insn "movti"
1394   [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v,  v,  v,v,d, v,QR,   d,o")
1395         (match_operand:TI 1 "general_operand"      "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
1396   "TARGET_ZARCH"
1397   "@
1398    lmg\t%0,%N0,%S1
1399    stmg\t%1,%N1,%S0
1400    vlr\t%v0,%v1
1401    vzero\t%v0
1402    vone\t%v0
1403    vlvgp\t%v0,%1,%N1
1404    #
1405    vl\t%v0,%1
1406    vst\t%v1,%0
1407    #
1408    #"
1409   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1410    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1411    (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1412
1413 (define_split
1414   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1415         (match_operand:TI 1 "general_operand" ""))]
1416   "TARGET_ZARCH && reload_completed
1417    && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1418   [(set (match_dup 2) (match_dup 4))
1419    (set (match_dup 3) (match_dup 5))]
1420 {
1421   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1422   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1423   operands[4] = operand_subword (operands[1], 0, 0, TImode);
1424   operands[5] = operand_subword (operands[1], 1, 0, TImode);
1425 })
1426
1427 (define_split
1428   [(set (match_operand:TI 0 "nonimmediate_operand" "")
1429         (match_operand:TI 1 "general_operand" ""))]
1430   "TARGET_ZARCH && reload_completed
1431    && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1432   [(set (match_dup 2) (match_dup 4))
1433    (set (match_dup 3) (match_dup 5))]
1434 {
1435   operands[2] = operand_subword (operands[0], 1, 0, TImode);
1436   operands[3] = operand_subword (operands[0], 0, 0, TImode);
1437   operands[4] = operand_subword (operands[1], 1, 0, TImode);
1438   operands[5] = operand_subword (operands[1], 0, 0, TImode);
1439 })
1440
1441 ; Use part of the TImode target reg to perform the address
1442 ; calculation.  If the TImode value is supposed to be copied into a VR
1443 ; this splitter is not necessary.
1444 (define_split
1445   [(set (match_operand:TI 0 "register_operand" "")
1446         (match_operand:TI 1 "memory_operand" ""))]
1447   "TARGET_ZARCH && reload_completed
1448    && !VECTOR_REG_P (operands[0])
1449    && !s_operand (operands[1], VOIDmode)"
1450   [(set (match_dup 0) (match_dup 1))]
1451 {
1452   rtx addr = operand_subword (operands[0], 1, 0, TImode);
1453   addr = gen_lowpart (Pmode, addr);
1454   s390_load_address (addr, XEXP (operands[1], 0));
1455   operands[1] = replace_equiv_address (operands[1], addr);
1456 })
1457
1458
1459 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1460 ; For the higher order bits we do simply a DImode move while the
1461 ; second part is done via vec extract.  Both will end up as vlgvg.
1462 (define_split
1463   [(set (match_operand:TI 0 "register_operand" "")
1464         (match_operand:TI 1 "register_operand" ""))]
1465   "TARGET_VX && reload_completed
1466    && GENERAL_REG_P (operands[0])
1467    && VECTOR_REG_P (operands[1])"
1468   [(set (match_dup 2) (match_dup 4))
1469    (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1470                                  UNSPEC_VEC_EXTRACT))]
1471 {
1472   operands[2] = operand_subword (operands[0], 0, 0, TImode);
1473   operands[3] = operand_subword (operands[0], 1, 0, TImode);
1474   operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1475   operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1476 })
1477
1478 ;
1479 ; Patterns used for secondary reloads
1480 ;
1481
1482 ; z10 provides move instructions accepting larl memory operands.
1483 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1484 ; These patterns are also used for unaligned SI and DI accesses.
1485
1486 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1487   [(parallel [(match_operand:ALL 0 "memory_operand"   "")
1488               (match_operand:ALL 1 "register_operand" "=d")
1489               (match_operand:P   2 "register_operand" "=&a")])]
1490   "TARGET_Z10"
1491 {
1492   s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1493   DONE;
1494 })
1495
1496 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1497   [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1498               (match_operand:ALL 1 "memory_operand"   "")
1499               (match_operand:P   2 "register_operand" "=a")])]
1500   "TARGET_Z10"
1501 {
1502   s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1503   DONE;
1504 })
1505
1506 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1507   [(parallel [(match_operand:P 0 "register_operand" "=d")
1508               (match_operand:P 1 "larl_operand"     "")
1509               (match_operand:P 2 "register_operand" "=a")])]
1510   "TARGET_Z10"
1511 {
1512   s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1513   DONE;
1514 })
1515
1516 ; Handles loading a PLUS (load address) expression
1517
1518 (define_expand "reload<mode>_plus"
1519   [(parallel [(match_operand:P 0 "register_operand"  "=a")
1520               (match_operand:P 1 "s390_plus_operand" "")
1521               (match_operand:P 2 "register_operand"  "=&a")])]
1522   ""
1523 {
1524   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1525   DONE;
1526 })
1527
1528 ; Not all the indirect memory access instructions support the full
1529 ; format (long disp + index + base).  So whenever a move from/to such
1530 ; an address is required and the instruction cannot deal with it we do
1531 ; a load address into a scratch register first and use this as the new
1532 ; base register.
1533 ; This in particular is used for:
1534 ; - non-offsetable memory accesses for multiword moves
1535 ; - full vector reg moves with long displacements
1536
1537 (define_expand "reload<mode>_la_in"
1538   [(parallel [(match_operand 0   "register_operand" "")
1539               (match_operand 1   "" "")
1540               (match_operand:P 2 "register_operand" "=&a")])]
1541   ""
1542 {
1543   gcc_assert (MEM_P (operands[1]));
1544   s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1545   operands[1] = replace_equiv_address (operands[1], operands[2]);
1546   emit_move_insn (operands[0], operands[1]);
1547   DONE;
1548 })
1549
1550 (define_expand "reload<mode>_la_out"
1551   [(parallel [(match_operand   0 "" "")
1552               (match_operand   1 "register_operand" "")
1553               (match_operand:P 2 "register_operand" "=&a")])]
1554   ""
1555 {
1556   gcc_assert (MEM_P (operands[0]));
1557   s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1558   operands[0] = replace_equiv_address (operands[0], operands[2]);
1559   emit_move_insn (operands[0], operands[1]);
1560   DONE;
1561 })
1562
1563 (define_expand "reload<mode>_PIC_addr"
1564   [(parallel [(match_operand   0 "register_operand" "=d")
1565               (match_operand   1 "larl_operand"     "")
1566               (match_operand:P 2 "register_operand" "=a")])]
1567   ""
1568 {
1569   rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1570   emit_move_insn (operands[0], new_rtx);
1571 })
1572
1573 ;
1574 ; movdi instruction pattern(s).
1575 ;
1576
1577 (define_expand "movdi"
1578   [(set (match_operand:DI 0 "general_operand" "")
1579         (match_operand:DI 1 "general_operand" ""))]
1580   ""
1581 {
1582   /* Handle symbolic constants.  */
1583   if (TARGET_64BIT
1584       && (SYMBOLIC_CONST (operands[1])
1585           || (GET_CODE (operands[1]) == PLUS
1586               && XEXP (operands[1], 0) == pic_offset_table_rtx
1587               && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1588     emit_symbolic_move (operands);
1589 })
1590
1591 (define_insn "*movdi_larl"
1592   [(set (match_operand:DI 0 "register_operand" "=d")
1593         (match_operand:DI 1 "larl_operand" "X"))]
1594   "TARGET_64BIT
1595    && !FP_REG_P (operands[0])"
1596   "larl\t%0,%1"
1597    [(set_attr "op_type" "RIL")
1598     (set_attr "type"    "larl")
1599     (set_attr "z10prop" "z10_super_A1")])
1600
1601 (define_insn "*movdi_64"
1602   [(set (match_operand:DI 0 "nonimmediate_operand"
1603          "=d,    d,    d,    d,    d, d,    d,    d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
1604         (match_operand:DI 1 "general_operand"
1605          " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f,  R,  T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
1606   "TARGET_ZARCH"
1607   "@
1608    lghi\t%0,%h1
1609    llihh\t%0,%i1
1610    llihl\t%0,%i1
1611    llilh\t%0,%i1
1612    llill\t%0,%i1
1613    lgfi\t%0,%1
1614    llihf\t%0,%k1
1615    llilf\t%0,%k1
1616    ldgr\t%0,%1
1617    lgdr\t%0,%1
1618    lay\t%0,%a1
1619    lgrl\t%0,%1
1620    lgr\t%0,%1
1621    lg\t%0,%1
1622    stg\t%1,%0
1623    ldr\t%0,%1
1624    ld\t%0,%1
1625    ldy\t%0,%1
1626    std\t%1,%0
1627    stdy\t%1,%0
1628    stgrl\t%1,%0
1629    mvghi\t%0,%1
1630    #
1631    #
1632    stam\t%1,%N1,%S0
1633    lam\t%0,%N0,%S1
1634    vleig\t%v0,%h1,0
1635    vlr\t%v0,%v1
1636    vlvgg\t%v0,%1,0
1637    vlgvg\t%0,%v1,0
1638    vleg\t%v0,%1,0
1639    vsteg\t%v1,%0,0"
1640   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1641                         RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1642    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1643                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1644                      *,*,*,*,*,*,*")
1645    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1646                              z10,*,*,*,*,*,longdisp,*,longdisp,
1647                              z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1648    (set_attr "z10prop" "z10_fwd_A1,
1649                         z10_fwd_E1,
1650                         z10_fwd_E1,
1651                         z10_fwd_E1,
1652                         z10_fwd_E1,
1653                         z10_fwd_A1,
1654                         z10_fwd_E1,
1655                         z10_fwd_E1,
1656                         *,
1657                         *,
1658                         z10_fwd_A1,
1659                         z10_fwd_A3,
1660                         z10_fr_E1,
1661                         z10_fwd_A3,
1662                         z10_rec,
1663                         *,
1664                         *,
1665                         *,
1666                         *,
1667                         *,
1668                         z10_rec,
1669                         z10_super,
1670                         *,
1671                         *,
1672                         *,
1673                         *,*,*,*,*,*,*")
1674 ])
1675
1676 (define_split
1677   [(set (match_operand:DI 0 "register_operand" "")
1678         (match_operand:DI 1 "register_operand" ""))]
1679   "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1680   [(set (match_dup 2) (match_dup 3))
1681    (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1682    (set (strict_low_part (match_dup 2)) (match_dup 4))]
1683   "operands[2] = gen_lowpart (SImode, operands[0]);
1684    s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1685
1686 (define_split
1687   [(set (match_operand:DI 0 "register_operand" "")
1688         (match_operand:DI 1 "register_operand" ""))]
1689   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1690    && dead_or_set_p (insn, operands[1])"
1691   [(set (match_dup 3) (match_dup 2))
1692    (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1693    (set (match_dup 4) (match_dup 2))]
1694   "operands[2] = gen_lowpart (SImode, operands[1]);
1695    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1696
1697 (define_split
1698   [(set (match_operand:DI 0 "register_operand" "")
1699         (match_operand:DI 1 "register_operand" ""))]
1700   "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1701    && !dead_or_set_p (insn, operands[1])"
1702   [(set (match_dup 3) (match_dup 2))
1703    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1704    (set (match_dup 4) (match_dup 2))
1705    (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1706   "operands[2] = gen_lowpart (SImode, operands[1]);
1707    s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1708
1709 (define_insn "*movdi_31"
1710   [(set (match_operand:DI 0 "nonimmediate_operand"
1711                             "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,d")
1712         (match_operand:DI 1 "general_operand"
1713                             " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,b"))]
1714   "!TARGET_ZARCH"
1715   "@
1716    lm\t%0,%N0,%S1
1717    lmy\t%0,%N0,%S1
1718    stm\t%1,%N1,%S0
1719    stmy\t%1,%N1,%S0
1720    #
1721    #
1722    ldr\t%0,%1
1723    ld\t%0,%1
1724    ldy\t%0,%1
1725    std\t%1,%0
1726    stdy\t%1,%0
1727    #"
1728   [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1729    (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1730    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1731
1732 ; For a load from a symbol ref we can use one of the target registers
1733 ; together with larl to load the address.
1734 (define_split
1735   [(set (match_operand:DI 0 "register_operand" "")
1736         (match_operand:DI 1 "memory_operand" ""))]
1737   "!TARGET_ZARCH && reload_completed && TARGET_Z10
1738    && larl_operand (XEXP (operands[1], 0), SImode)"
1739   [(set (match_dup 2) (match_dup 3))
1740    (set (match_dup 0) (match_dup 1))]
1741 {
1742   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1743   operands[3] = XEXP (operands[1], 0);
1744   operands[1] = replace_equiv_address (operands[1], operands[2]);
1745 })
1746
1747 (define_split
1748   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1749         (match_operand:DI 1 "general_operand" ""))]
1750   "!TARGET_ZARCH && reload_completed
1751    && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1752   [(set (match_dup 2) (match_dup 4))
1753    (set (match_dup 3) (match_dup 5))]
1754 {
1755   operands[2] = operand_subword (operands[0], 0, 0, DImode);
1756   operands[3] = operand_subword (operands[0], 1, 0, DImode);
1757   operands[4] = operand_subword (operands[1], 0, 0, DImode);
1758   operands[5] = operand_subword (operands[1], 1, 0, DImode);
1759 })
1760
1761 (define_split
1762   [(set (match_operand:DI 0 "nonimmediate_operand" "")
1763         (match_operand:DI 1 "general_operand" ""))]
1764   "!TARGET_ZARCH && reload_completed
1765    && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1766   [(set (match_dup 2) (match_dup 4))
1767    (set (match_dup 3) (match_dup 5))]
1768 {
1769   operands[2] = operand_subword (operands[0], 1, 0, DImode);
1770   operands[3] = operand_subword (operands[0], 0, 0, DImode);
1771   operands[4] = operand_subword (operands[1], 1, 0, DImode);
1772   operands[5] = operand_subword (operands[1], 0, 0, DImode);
1773 })
1774
1775 (define_split
1776   [(set (match_operand:DI 0 "register_operand" "")
1777         (match_operand:DI 1 "memory_operand" ""))]
1778   "!TARGET_ZARCH && reload_completed
1779    && !FP_REG_P (operands[0])
1780    && !s_operand (operands[1], VOIDmode)"
1781   [(set (match_dup 0) (match_dup 1))]
1782 {
1783   rtx addr = operand_subword (operands[0], 1, 0, DImode);
1784   s390_load_address (addr, XEXP (operands[1], 0));
1785   operands[1] = replace_equiv_address (operands[1], addr);
1786 })
1787
1788 (define_peephole2
1789   [(set (match_operand:DI 0 "register_operand" "")
1790         (mem:DI (match_operand 1 "address_operand" "")))]
1791   "TARGET_ZARCH
1792    && !FP_REG_P (operands[0])
1793    && GET_CODE (operands[1]) == SYMBOL_REF
1794    && CONSTANT_POOL_ADDRESS_P (operands[1])
1795    && get_pool_mode (operands[1]) == DImode
1796    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1797   [(set (match_dup 0) (match_dup 2))]
1798   "operands[2] = get_pool_constant (operands[1]);")
1799
1800 (define_insn "*la_64"
1801   [(set (match_operand:DI 0 "register_operand" "=d,d")
1802         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1803   "TARGET_64BIT"
1804   "@
1805    la\t%0,%a1
1806    lay\t%0,%a1"
1807   [(set_attr "op_type" "RX,RXY")
1808    (set_attr "type"    "la")
1809    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1810
1811 (define_peephole2
1812   [(parallel
1813     [(set (match_operand:DI 0 "register_operand" "")
1814           (match_operand:QI 1 "address_operand" ""))
1815      (clobber (reg:CC CC_REGNUM))])]
1816   "TARGET_64BIT
1817    && preferred_la_operand_p (operands[1], const0_rtx)"
1818   [(set (match_dup 0) (match_dup 1))]
1819   "")
1820
1821 (define_peephole2
1822   [(set (match_operand:DI 0 "register_operand" "")
1823         (match_operand:DI 1 "register_operand" ""))
1824    (parallel
1825     [(set (match_dup 0)
1826           (plus:DI (match_dup 0)
1827                    (match_operand:DI 2 "nonmemory_operand" "")))
1828      (clobber (reg:CC CC_REGNUM))])]
1829   "TARGET_64BIT
1830    && !reg_overlap_mentioned_p (operands[0], operands[2])
1831    && preferred_la_operand_p (operands[1], operands[2])"
1832   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1833   "")
1834
1835 ;
1836 ; movsi instruction pattern(s).
1837 ;
1838
1839 (define_expand "movsi"
1840   [(set (match_operand:SI 0 "general_operand" "")
1841         (match_operand:SI 1 "general_operand" ""))]
1842   ""
1843 {
1844   /* Handle symbolic constants.  */
1845   if (!TARGET_64BIT
1846       && (SYMBOLIC_CONST (operands[1])
1847           || (GET_CODE (operands[1]) == PLUS
1848               && XEXP (operands[1], 0) == pic_offset_table_rtx
1849               && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1850     emit_symbolic_move (operands);
1851 })
1852
1853 (define_insn "*movsi_larl"
1854   [(set (match_operand:SI 0 "register_operand" "=d")
1855         (match_operand:SI 1 "larl_operand" "X"))]
1856   "!TARGET_64BIT && TARGET_CPU_ZARCH
1857    && !FP_REG_P (operands[0])"
1858   "larl\t%0,%1"
1859    [(set_attr "op_type" "RIL")
1860     (set_attr "type"    "larl")
1861     (set_attr "z10prop" "z10_fwd_A1")])
1862
1863 (define_insn "*movsi_zarch"
1864   [(set (match_operand:SI 0 "nonimmediate_operand"
1865          "=d,    d,    d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
1866         (match_operand:SI 1 "general_operand"
1867          " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f,  R,  R,  T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
1868   "TARGET_ZARCH"
1869   "@
1870    lhi\t%0,%h1
1871    llilh\t%0,%i1
1872    llill\t%0,%i1
1873    iilf\t%0,%o1
1874    lay\t%0,%a1
1875    lrl\t%0,%1
1876    lr\t%0,%1
1877    l\t%0,%1
1878    ly\t%0,%1
1879    st\t%1,%0
1880    sty\t%1,%0
1881    lder\t%0,%1
1882    ler\t%0,%1
1883    lde\t%0,%1
1884    le\t%0,%1
1885    ley\t%0,%1
1886    ste\t%1,%0
1887    stey\t%1,%0
1888    ear\t%0,%1
1889    sar\t%0,%1
1890    stam\t%1,%1,%S0
1891    strl\t%1,%0
1892    mvhi\t%0,%1
1893    lam\t%0,%0,%S1
1894    vleif\t%v0,%h1,0
1895    vlr\t%v0,%v1
1896    vlvgf\t%v0,%1,0
1897    vlgvf\t%0,%v1,0
1898    vlef\t%v0,%1,0
1899    vstef\t%v1,%0,0"
1900   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1901                         RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1902    (set_attr "type" "*,
1903                      *,
1904                      *,
1905                      *,
1906                      la,
1907                      larl,
1908                      lr,
1909                      load,
1910                      load,
1911                      store,
1912                      store,
1913                      floadsf,
1914                      floadsf,
1915                      floadsf,
1916                      floadsf,
1917                      floadsf,
1918                      fstoresf,
1919                      fstoresf,
1920                      *,
1921                      *,
1922                      *,
1923                      larl,
1924                      *,
1925                      *,*,*,*,*,*,*")
1926    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1927                              vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1928    (set_attr "z10prop" "z10_fwd_A1,
1929                         z10_fwd_E1,
1930                         z10_fwd_E1,
1931                         z10_fwd_A1,
1932                         z10_fwd_A1,
1933                         z10_fwd_A3,
1934                         z10_fr_E1,
1935                         z10_fwd_A3,
1936                         z10_fwd_A3,
1937                         z10_rec,
1938                         z10_rec,
1939                         *,
1940                         *,
1941                         *,
1942                         *,
1943                         *,
1944                         *,
1945                         *,
1946                         z10_super_E1,
1947                         z10_super,
1948                         *,
1949                         z10_rec,
1950                         z10_super,
1951                         *,*,*,*,*,*,*")])
1952
1953 (define_insn "*movsi_esa"
1954   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
1955         (match_operand:SI 1 "general_operand"       "K,d,R,d, *f, *f,  R,  R,*f,t,d,t,Q"))]
1956   "!TARGET_ZARCH"
1957   "@
1958    lhi\t%0,%h1
1959    lr\t%0,%1
1960    l\t%0,%1
1961    st\t%1,%0
1962    lder\t%0,%1
1963    ler\t%0,%1
1964    lde\t%0,%1
1965    le\t%0,%1
1966    ste\t%1,%0
1967    ear\t%0,%1
1968    sar\t%0,%1
1969    stam\t%1,%1,%S0
1970    lam\t%0,%0,%S1"
1971   [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
1972    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
1973    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
1974                         z10_super,*,*")
1975    (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
1976 ])
1977
1978 (define_peephole2
1979   [(set (match_operand:SI 0 "register_operand" "")
1980         (mem:SI (match_operand 1 "address_operand" "")))]
1981   "!FP_REG_P (operands[0])
1982    && GET_CODE (operands[1]) == SYMBOL_REF
1983    && CONSTANT_POOL_ADDRESS_P (operands[1])
1984    && get_pool_mode (operands[1]) == SImode
1985    && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1986   [(set (match_dup 0) (match_dup 2))]
1987   "operands[2] = get_pool_constant (operands[1]);")
1988
1989 (define_insn "*la_31"
1990   [(set (match_operand:SI 0 "register_operand" "=d,d")
1991         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1992   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1993   "@
1994    la\t%0,%a1
1995    lay\t%0,%a1"
1996   [(set_attr "op_type"  "RX,RXY")
1997    (set_attr "type"     "la")
1998    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1999
2000 (define_peephole2
2001   [(parallel
2002     [(set (match_operand:SI 0 "register_operand" "")
2003           (match_operand:QI 1 "address_operand" ""))
2004      (clobber (reg:CC CC_REGNUM))])]
2005   "!TARGET_64BIT
2006    && preferred_la_operand_p (operands[1], const0_rtx)"
2007   [(set (match_dup 0) (match_dup 1))]
2008   "")
2009
2010 (define_peephole2
2011   [(set (match_operand:SI 0 "register_operand" "")
2012         (match_operand:SI 1 "register_operand" ""))
2013    (parallel
2014     [(set (match_dup 0)
2015           (plus:SI (match_dup 0)
2016                    (match_operand:SI 2 "nonmemory_operand" "")))
2017      (clobber (reg:CC CC_REGNUM))])]
2018   "!TARGET_64BIT
2019    && !reg_overlap_mentioned_p (operands[0], operands[2])
2020    && preferred_la_operand_p (operands[1], operands[2])"
2021   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2022   "")
2023
2024 (define_insn "*la_31_and"
2025   [(set (match_operand:SI 0 "register_operand" "=d,d")
2026         (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
2027                 (const_int 2147483647)))]
2028   "!TARGET_64BIT"
2029   "@
2030    la\t%0,%a1
2031    lay\t%0,%a1"
2032   [(set_attr "op_type"  "RX,RXY")
2033    (set_attr "type"     "la")
2034    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2035
2036 (define_insn_and_split "*la_31_and_cc"
2037   [(set (match_operand:SI 0 "register_operand" "=d")
2038         (and:SI (match_operand:QI 1 "address_operand" "p")
2039                 (const_int 2147483647)))
2040    (clobber (reg:CC CC_REGNUM))]
2041   "!TARGET_64BIT"
2042   "#"
2043   "&& reload_completed"
2044   [(set (match_dup 0)
2045         (and:SI (match_dup 1) (const_int 2147483647)))]
2046   ""
2047   [(set_attr "op_type"  "RX")
2048    (set_attr "type"     "la")])
2049
2050 (define_insn "force_la_31"
2051   [(set (match_operand:SI 0 "register_operand" "=d,d")
2052         (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
2053    (use (const_int 0))]
2054   "!TARGET_64BIT"
2055   "@
2056    la\t%0,%a1
2057    lay\t%0,%a1"
2058   [(set_attr "op_type"  "RX")
2059    (set_attr "type"     "la")
2060    (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2061
2062 ;
2063 ; movhi instruction pattern(s).
2064 ;
2065
2066 (define_expand "movhi"
2067   [(set (match_operand:HI 0 "nonimmediate_operand" "")
2068         (match_operand:HI 1 "general_operand" ""))]
2069   ""
2070 {
2071   /* Make it explicit that loading a register from memory
2072      always sign-extends (at least) to SImode.  */
2073   if (optimize && can_create_pseudo_p ()
2074       && register_operand (operands[0], VOIDmode)
2075       && GET_CODE (operands[1]) == MEM)
2076     {
2077       rtx tmp = gen_reg_rtx (SImode);
2078       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2079       emit_insn (gen_rtx_SET (tmp, ext));
2080       operands[1] = gen_lowpart (HImode, tmp);
2081     }
2082 })
2083
2084 (define_insn "*movhi"
2085   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
2086         (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
2087   ""
2088   "@
2089    lr\t%0,%1
2090    lhi\t%0,%h1
2091    lh\t%0,%1
2092    lhy\t%0,%1
2093    lhrl\t%0,%1
2094    sth\t%1,%0
2095    sthy\t%1,%0
2096    sthrl\t%1,%0
2097    mvhhi\t%0,%1
2098    vleih\t%v0,%h1,0
2099    vlr\t%v0,%v1
2100    vlvgh\t%v0,%1,0
2101    vlgvh\t%0,%v1,0
2102    vleh\t%v0,%1,0
2103    vsteh\t%v1,%0,0"
2104   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2105    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2106    (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
2107    (set_attr "z10prop" "z10_fr_E1,
2108                        z10_fwd_A1,
2109                        z10_super_E1,
2110                        z10_super_E1,
2111                        z10_super_E1,
2112                        z10_rec,
2113                        z10_rec,
2114                        z10_rec,
2115                        z10_super,*,*,*,*,*,*")])
2116
2117 (define_peephole2
2118   [(set (match_operand:HI 0 "register_operand" "")
2119         (mem:HI (match_operand 1 "address_operand" "")))]
2120   "GET_CODE (operands[1]) == SYMBOL_REF
2121    && CONSTANT_POOL_ADDRESS_P (operands[1])
2122    && get_pool_mode (operands[1]) == HImode
2123    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2124   [(set (match_dup 0) (match_dup 2))]
2125   "operands[2] = get_pool_constant (operands[1]);")
2126
2127 ;
2128 ; movqi instruction pattern(s).
2129 ;
2130
2131 (define_expand "movqi"
2132   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2133         (match_operand:QI 1 "general_operand" ""))]
2134   ""
2135 {
2136   /* On z/Architecture, zero-extending from memory to register
2137      is just as fast as a QImode load.  */
2138   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2139       && register_operand (operands[0], VOIDmode)
2140       && GET_CODE (operands[1]) == MEM)
2141     {
2142       rtx tmp = gen_reg_rtx (DImode);
2143       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2144       emit_insn (gen_rtx_SET (tmp, ext));
2145       operands[1] = gen_lowpart (QImode, tmp);
2146     }
2147 })
2148
2149 (define_insn "*movqi"
2150   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
2151         (match_operand:QI 1 "general_operand"      " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
2152   ""
2153   "@
2154    lr\t%0,%1
2155    lhi\t%0,%b1
2156    ic\t%0,%1
2157    icy\t%0,%1
2158    stc\t%1,%0
2159    stcy\t%1,%0
2160    mvi\t%S0,%b1
2161    mviy\t%S0,%b1
2162    #
2163    vleib\t%v0,%b1,0
2164    vlr\t%v0,%v1
2165    vlvgb\t%v0,%1,0
2166    vlgvb\t%0,%v1,0
2167    vleb\t%v0,%1,0
2168    vsteb\t%v1,%0,0"
2169   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2170    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2171    (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
2172    (set_attr "z10prop" "z10_fr_E1,
2173                         z10_fwd_A1,
2174                         z10_super_E1,
2175                         z10_super_E1,
2176                         z10_rec,
2177                         z10_rec,
2178                         z10_super,
2179                         z10_super,
2180                         *,*,*,*,*,*,*")])
2181
2182 (define_peephole2
2183   [(set (match_operand:QI 0 "nonimmediate_operand" "")
2184         (mem:QI (match_operand 1 "address_operand" "")))]
2185   "GET_CODE (operands[1]) == SYMBOL_REF
2186    && CONSTANT_POOL_ADDRESS_P (operands[1])
2187    && get_pool_mode (operands[1]) == QImode
2188    && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2189   [(set (match_dup 0) (match_dup 2))]
2190   "operands[2] = get_pool_constant (operands[1]);")
2191
2192 ;
2193 ; movstrictqi instruction pattern(s).
2194 ;
2195
2196 (define_insn "*movstrictqi"
2197   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2198                          (match_operand:QI 1 "memory_operand" "R,T"))]
2199   ""
2200   "@
2201    ic\t%0,%1
2202    icy\t%0,%1"
2203   [(set_attr "op_type"  "RX,RXY")
2204    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2205
2206 ;
2207 ; movstricthi instruction pattern(s).
2208 ;
2209
2210 (define_insn "*movstricthi"
2211   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2212                          (match_operand:HI 1 "memory_operand" "Q,S"))
2213    (clobber (reg:CC CC_REGNUM))]
2214   ""
2215   "@
2216    icm\t%0,3,%S1
2217    icmy\t%0,3,%S1"
2218   [(set_attr "op_type" "RS,RSY")
2219    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2220
2221 ;
2222 ; movstrictsi instruction pattern(s).
2223 ;
2224
2225 (define_insn "movstrictsi"
2226   [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2227                          (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2228   "TARGET_ZARCH"
2229   "@
2230    lr\t%0,%1
2231    l\t%0,%1
2232    ly\t%0,%1
2233    ear\t%0,%1"
2234   [(set_attr "op_type" "RR,RX,RXY,RRE")
2235    (set_attr "type" "lr,load,load,*")
2236    (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2237
2238 ;
2239 ; mov(tf|td) instruction pattern(s).
2240 ;
2241
2242 (define_expand "mov<mode>"
2243   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2244         (match_operand:TD_TF 1 "general_operand"      ""))]
2245   ""
2246   "")
2247
2248 (define_insn "*mov<mode>_64"
2249   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS,  d,o")
2250         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d"))]
2251   "TARGET_ZARCH"
2252   "@
2253    lzxr\t%0
2254    lxr\t%0,%1
2255    #
2256    #
2257    lmg\t%0,%N0,%S1
2258    stmg\t%1,%N1,%S0
2259    #
2260    #"
2261   [(set_attr "op_type"      "RRE,RRE,*,*,RSY,RSY,*,*")
2262    (set_attr "type"         "fsimptf,fsimptf,*,*,lm,stm,*,*")
2263    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2264
2265 (define_insn "*mov<mode>_31"
2266   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2267         (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
2268   "!TARGET_ZARCH"
2269   "@
2270    lzxr\t%0
2271    lxr\t%0,%1
2272    #
2273    #"
2274   [(set_attr "op_type"      "RRE,RRE,*,*")
2275    (set_attr "type"         "fsimptf,fsimptf,*,*")
2276    (set_attr "cpu_facility" "z196,*,*,*")])
2277
2278 ; TFmode in GPRs splitters
2279
2280 (define_split
2281   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2282         (match_operand:TD_TF 1 "general_operand"      ""))]
2283   "TARGET_ZARCH && reload_completed
2284    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2285   [(set (match_dup 2) (match_dup 4))
2286    (set (match_dup 3) (match_dup 5))]
2287 {
2288   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2289   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2290   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2291   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2292 })
2293
2294 (define_split
2295   [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2296         (match_operand:TD_TF 1 "general_operand"      ""))]
2297   "TARGET_ZARCH && reload_completed
2298    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2299   [(set (match_dup 2) (match_dup 4))
2300    (set (match_dup 3) (match_dup 5))]
2301 {
2302   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2303   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2304   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2305   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2306 })
2307
2308 (define_split
2309   [(set (match_operand:TD_TF 0 "register_operand" "")
2310         (match_operand:TD_TF 1 "memory_operand"   ""))]
2311   "TARGET_ZARCH && reload_completed
2312    && GENERAL_REG_P (operands[0])
2313    && !s_operand (operands[1], VOIDmode)"
2314   [(set (match_dup 0) (match_dup 1))]
2315 {
2316   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2317   addr = gen_lowpart (Pmode, addr);
2318   s390_load_address (addr, XEXP (operands[1], 0));
2319   operands[1] = replace_equiv_address (operands[1], addr);
2320 })
2321
2322 ; TFmode in BFPs splitters
2323
2324 (define_split
2325   [(set (match_operand:TD_TF 0 "register_operand" "")
2326         (match_operand:TD_TF 1 "memory_operand" ""))]
2327   "reload_completed && offsettable_memref_p (operands[1])
2328    && FP_REG_P (operands[0])"
2329   [(set (match_dup 2) (match_dup 4))
2330    (set (match_dup 3) (match_dup 5))]
2331 {
2332   operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2333                                      <MODE>mode, 0);
2334   operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2335                                      <MODE>mode, 8);
2336   operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2337   operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2338 })
2339
2340 (define_split
2341   [(set (match_operand:TD_TF 0 "memory_operand" "")
2342         (match_operand:TD_TF 1 "register_operand" ""))]
2343   "reload_completed && offsettable_memref_p (operands[0])
2344    && FP_REG_P (operands[1])"
2345   [(set (match_dup 2) (match_dup 4))
2346    (set (match_dup 3) (match_dup 5))]
2347 {
2348   operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2349   operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2350   operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2351                                      <MODE>mode, 0);
2352   operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2353                                      <MODE>mode, 8);
2354 })
2355
2356 ;
2357 ; mov(df|dd) instruction pattern(s).
2358 ;
2359
2360 (define_expand "mov<mode>"
2361   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2362         (match_operand:DD_DF 1 "general_operand"  ""))]
2363   ""
2364   "")
2365
2366 (define_insn "*mov<mode>_64dfp"
2367   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2368                                "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
2369         (match_operand:DD_DF 1 "general_operand"
2370                                " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
2371   "TARGET_DFP"
2372   "@
2373    lzdr\t%0
2374    ldr\t%0,%1
2375    ldgr\t%0,%1
2376    lgdr\t%0,%1
2377    ld\t%0,%1
2378    ldy\t%0,%1
2379    std\t%1,%0
2380    stdy\t%1,%0
2381    lghi\t%0,0
2382    lgr\t%0,%1
2383    lgrl\t%0,%1
2384    lg\t%0,%1
2385    stgrl\t%1,%0
2386    stg\t%1,%0
2387    vlr\t%v0,%v1
2388    vlvgg\t%v0,%1,0
2389    vlgvg\t%0,%v1,0
2390    vleg\t%0,%1,0
2391    vsteg\t%1,%0,0"
2392   [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2393    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2394                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2395    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2396    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2397
2398 (define_insn "*mov<mode>_64"
2399   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
2400         (match_operand:DD_DF 1 "general_operand"      " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
2401   "TARGET_ZARCH"
2402   "@
2403    lzdr\t%0
2404    ldr\t%0,%1
2405    ld\t%0,%1
2406    ldy\t%0,%1
2407    std\t%1,%0
2408    stdy\t%1,%0
2409    lghi\t%0,0
2410    lgr\t%0,%1
2411    lgrl\t%0,%1
2412    lg\t%0,%1
2413    stgrl\t%1,%0
2414    stg\t%1,%0
2415    vlr\t%v0,%v1
2416    vleg\t%v0,%1,0
2417    vsteg\t%v1,%0,0"
2418   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2419    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2420                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2421    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2422    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
2423
2424 (define_insn "*mov<mode>_31"
2425   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2426                                "=f,f,f,f,R,T,d,d,Q,S,   d,o")
2427         (match_operand:DD_DF 1 "general_operand"
2428                                " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2429   "!TARGET_ZARCH"
2430   "@
2431    lzdr\t%0
2432    ldr\t%0,%1
2433    ld\t%0,%1
2434    ldy\t%0,%1
2435    std\t%1,%0
2436    stdy\t%1,%0
2437    lm\t%0,%N0,%S1
2438    lmy\t%0,%N0,%S1
2439    stm\t%1,%N1,%S0
2440    stmy\t%1,%N1,%S0
2441    #
2442    #"
2443   [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2444    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2445                         fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2446    (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2447
2448 (define_split
2449   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2450         (match_operand:DD_DF 1 "general_operand" ""))]
2451   "!TARGET_ZARCH && reload_completed
2452    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2453   [(set (match_dup 2) (match_dup 4))
2454    (set (match_dup 3) (match_dup 5))]
2455 {
2456   operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2457   operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2458   operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2459   operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2460 })
2461
2462 (define_split
2463   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2464         (match_operand:DD_DF 1 "general_operand" ""))]
2465   "!TARGET_ZARCH && reload_completed
2466    && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2467   [(set (match_dup 2) (match_dup 4))
2468    (set (match_dup 3) (match_dup 5))]
2469 {
2470   operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2471   operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2472   operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2473   operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2474 })
2475
2476 (define_split
2477   [(set (match_operand:DD_DF 0 "register_operand" "")
2478         (match_operand:DD_DF 1 "memory_operand" ""))]
2479   "!TARGET_ZARCH && reload_completed
2480    && !FP_REG_P (operands[0])
2481    && !s_operand (operands[1], VOIDmode)"
2482   [(set (match_dup 0) (match_dup 1))]
2483 {
2484   rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2485   s390_load_address (addr, XEXP (operands[1], 0));
2486   operands[1] = replace_equiv_address (operands[1], addr);
2487 })
2488
2489 ;
2490 ; mov(sf|sd) instruction pattern(s).
2491 ;
2492
2493 (define_insn "mov<mode>"
2494   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2495                                "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
2496         (match_operand:SD_SF 1 "general_operand"
2497                                " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
2498   ""
2499   "@
2500    lzer\t%0
2501    lder\t%0,%1
2502    ler\t%0,%1
2503    lde\t%0,%1
2504    le\t%0,%1
2505    ley\t%0,%1
2506    ste\t%1,%0
2507    stey\t%1,%0
2508    lhi\t%0,0
2509    lr\t%0,%1
2510    lrl\t%0,%1
2511    l\t%0,%1
2512    ly\t%0,%1
2513    strl\t%1,%0
2514    st\t%1,%0
2515    sty\t%1,%0
2516    vlr\t%v0,%v1
2517    vleif\t%v0,0
2518    vlvgf\t%v0,%1,0
2519    vlgvf\t%0,%v1,0
2520    vleg\t%0,%1,0
2521    vsteg\t%1,%0,0"
2522   [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2523    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2524                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2525    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2526    (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
2527
2528 ;
2529 ; movcc instruction pattern
2530 ;
2531
2532 (define_insn "movcc"
2533   [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2534         (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2535   ""
2536   "@
2537    lr\t%0,%1
2538    tmh\t%1,12288
2539    ipm\t%0
2540    l\t%0,%1
2541    ly\t%0,%1
2542    st\t%1,%0
2543    sty\t%1,%0"
2544   [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2545    (set_attr "type" "lr,*,*,load,load,store,store")
2546    (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2547    (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2548
2549 ;
2550 ; Block move (MVC) patterns.
2551 ;
2552
2553 (define_insn "*mvc"
2554   [(set (match_operand:BLK 0 "memory_operand" "=Q")
2555         (match_operand:BLK 1 "memory_operand" "Q"))
2556    (use (match_operand 2 "const_int_operand" "n"))]
2557   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2558   "mvc\t%O0(%2,%R0),%S1"
2559   [(set_attr "op_type" "SS")])
2560
2561 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2562 ; order to have it implemented with mvc.
2563
2564 (define_split
2565   [(set (match_operand:QI 0 "memory_operand" "")
2566         (match_operand:QI 1 "memory_operand" ""))]
2567   "reload_completed"
2568   [(parallel
2569     [(set (match_dup 0) (match_dup 1))
2570      (use (const_int 1))])]
2571 {
2572   operands[0] = adjust_address (operands[0], BLKmode, 0);
2573   operands[1] = adjust_address (operands[1], BLKmode, 0);
2574 })
2575
2576
2577 (define_peephole2
2578   [(parallel
2579     [(set (match_operand:BLK 0 "memory_operand" "")
2580           (match_operand:BLK 1 "memory_operand" ""))
2581      (use (match_operand 2 "const_int_operand" ""))])
2582    (parallel
2583     [(set (match_operand:BLK 3 "memory_operand" "")
2584           (match_operand:BLK 4 "memory_operand" ""))
2585      (use (match_operand 5 "const_int_operand" ""))])]
2586   "s390_offset_p (operands[0], operands[3], operands[2])
2587    && s390_offset_p (operands[1], operands[4], operands[2])
2588    && !s390_overlap_p (operands[0], operands[1],
2589                        INTVAL (operands[2]) + INTVAL (operands[5]))
2590    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2591   [(parallel
2592     [(set (match_dup 6) (match_dup 7))
2593      (use (match_dup 8))])]
2594   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2595    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2596    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2597
2598
2599 ;
2600 ; load_multiple pattern(s).
2601 ;
2602 ; ??? Due to reload problems with replacing registers inside match_parallel
2603 ; we currently support load_multiple/store_multiple only after reload.
2604 ;
2605
2606 (define_expand "load_multiple"
2607   [(match_par_dup 3 [(set (match_operand 0 "" "")
2608                           (match_operand 1 "" ""))
2609                      (use (match_operand 2 "" ""))])]
2610   "reload_completed"
2611 {
2612   machine_mode mode;
2613   int regno;
2614   int count;
2615   rtx from;
2616   int i, off;
2617
2618   /* Support only loading a constant number of fixed-point registers from
2619      memory and only bother with this if more than two */
2620   if (GET_CODE (operands[2]) != CONST_INT
2621       || INTVAL (operands[2]) < 2
2622       || INTVAL (operands[2]) > 16
2623       || GET_CODE (operands[1]) != MEM
2624       || GET_CODE (operands[0]) != REG
2625       || REGNO (operands[0]) >= 16)
2626     FAIL;
2627
2628   count = INTVAL (operands[2]);
2629   regno = REGNO (operands[0]);
2630   mode = GET_MODE (operands[0]);
2631   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2632     FAIL;
2633
2634   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2635   if (!can_create_pseudo_p ())
2636     {
2637       if (GET_CODE (XEXP (operands[1], 0)) == REG)
2638         {
2639           from = XEXP (operands[1], 0);
2640           off = 0;
2641         }
2642       else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2643                && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2644                && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2645         {
2646           from = XEXP (XEXP (operands[1], 0), 0);
2647           off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2648         }
2649       else
2650         FAIL;
2651     }
2652   else
2653     {
2654       from = force_reg (Pmode, XEXP (operands[1], 0));
2655       off = 0;
2656     }
2657
2658   for (i = 0; i < count; i++)
2659     XVECEXP (operands[3], 0, i)
2660       = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2661                      change_address (operands[1], mode,
2662                        plus_constant (Pmode, from,
2663                                       off + i * GET_MODE_SIZE (mode))));
2664 })
2665
2666 (define_insn "*load_multiple_di"
2667   [(match_parallel 0 "load_multiple_operation"
2668                    [(set (match_operand:DI 1 "register_operand" "=r")
2669                          (match_operand:DI 2 "s_operand" "QS"))])]
2670   "reload_completed && TARGET_ZARCH"
2671 {
2672   int words = XVECLEN (operands[0], 0);
2673   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2674   return "lmg\t%1,%0,%S2";
2675 }
2676    [(set_attr "op_type" "RSY")
2677     (set_attr "type"    "lm")])
2678
2679 (define_insn "*load_multiple_si"
2680   [(match_parallel 0 "load_multiple_operation"
2681                    [(set (match_operand:SI 1 "register_operand" "=r,r")
2682                          (match_operand:SI 2 "s_operand" "Q,S"))])]
2683   "reload_completed"
2684 {
2685   int words = XVECLEN (operands[0], 0);
2686   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2687   return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2688 }
2689    [(set_attr "op_type" "RS,RSY")
2690     (set_attr "type"    "lm")])
2691
2692 ;
2693 ; store multiple pattern(s).
2694 ;
2695
2696 (define_expand "store_multiple"
2697   [(match_par_dup 3 [(set (match_operand 0 "" "")
2698                           (match_operand 1 "" ""))
2699                      (use (match_operand 2 "" ""))])]
2700   "reload_completed"
2701 {
2702   machine_mode mode;
2703   int regno;
2704   int count;
2705   rtx to;
2706   int i, off;
2707
2708   /* Support only storing a constant number of fixed-point registers to
2709      memory and only bother with this if more than two.  */
2710   if (GET_CODE (operands[2]) != CONST_INT
2711       || INTVAL (operands[2]) < 2
2712       || INTVAL (operands[2]) > 16
2713       || GET_CODE (operands[0]) != MEM
2714       || GET_CODE (operands[1]) != REG
2715       || REGNO (operands[1]) >= 16)
2716     FAIL;
2717
2718   count = INTVAL (operands[2]);
2719   regno = REGNO (operands[1]);
2720   mode = GET_MODE (operands[1]);
2721   if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2722     FAIL;
2723
2724   operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2725
2726   if (!can_create_pseudo_p ())
2727     {
2728       if (GET_CODE (XEXP (operands[0], 0)) == REG)
2729         {
2730           to = XEXP (operands[0], 0);
2731           off = 0;
2732         }
2733       else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2734                && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2735                && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2736         {
2737           to = XEXP (XEXP (operands[0], 0), 0);
2738           off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2739         }
2740       else
2741         FAIL;
2742     }
2743   else
2744     {
2745       to = force_reg (Pmode, XEXP (operands[0], 0));
2746       off = 0;
2747     }
2748
2749   for (i = 0; i < count; i++)
2750     XVECEXP (operands[3], 0, i)
2751       = gen_rtx_SET (change_address (operands[0], mode,
2752                        plus_constant (Pmode, to,
2753                                       off + i * GET_MODE_SIZE (mode))),
2754                      gen_rtx_REG (mode, regno + i));
2755 })
2756
2757 (define_insn "*store_multiple_di"
2758   [(match_parallel 0 "store_multiple_operation"
2759                    [(set (match_operand:DI 1 "s_operand" "=QS")
2760                          (match_operand:DI 2 "register_operand" "r"))])]
2761   "reload_completed && TARGET_ZARCH"
2762 {
2763   int words = XVECLEN (operands[0], 0);
2764   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2765   return "stmg\t%2,%0,%S1";
2766 }
2767    [(set_attr "op_type" "RSY")
2768     (set_attr "type"    "stm")])
2769
2770
2771 (define_insn "*store_multiple_si"
2772   [(match_parallel 0 "store_multiple_operation"
2773                    [(set (match_operand:SI 1 "s_operand" "=Q,S")
2774                          (match_operand:SI 2 "register_operand" "r,r"))])]
2775   "reload_completed"
2776 {
2777   int words = XVECLEN (operands[0], 0);
2778   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2779   return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2780 }
2781    [(set_attr "op_type" "RS,RSY")
2782     (set_attr "type"    "stm")])
2783
2784 ;;
2785 ;; String instructions.
2786 ;;
2787
2788 (define_insn "*execute_rl"
2789   [(match_parallel 0 "execute_operation"
2790     [(unspec [(match_operand 1    "register_operand" "a")
2791               (match_operand 2    "" "")
2792               (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2793   "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2794    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2795   "exrl\t%1,%3"
2796   [(set_attr "op_type" "RIL")
2797    (set_attr "type"    "cs")])
2798
2799 (define_insn "*execute"
2800   [(match_parallel 0 "execute_operation"
2801     [(unspec [(match_operand 1 "register_operand" "a")
2802               (match_operand:BLK 2 "memory_operand" "R")
2803               (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2804   "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2805    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2806   "ex\t%1,%2"
2807   [(set_attr "op_type" "RX")
2808    (set_attr "type" "cs")])
2809
2810
2811 ;
2812 ; strlenM instruction pattern(s).
2813 ;
2814
2815 (define_expand "strlen<mode>"
2816   [(match_operand:P   0 "register_operand" "")  ; result
2817    (match_operand:BLK 1 "memory_operand" "")    ; input string
2818    (match_operand:SI  2 "immediate_operand" "") ; search character
2819    (match_operand:SI  3 "immediate_operand" "")] ; known alignment
2820   ""
2821 {
2822   if (!TARGET_VX || operands[2] != const0_rtx)
2823     emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2824                                       operands[2], operands[3]));
2825   else
2826     s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2827
2828   DONE;
2829 })
2830
2831 (define_expand "strlen_srst<mode>"
2832   [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2833    (parallel
2834     [(set (match_dup 4)
2835           (unspec:P [(const_int 0)
2836                       (match_operand:BLK 1 "memory_operand" "")
2837                       (reg:SI 0)
2838                       (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2839      (clobber (scratch:P))
2840      (clobber (reg:CC CC_REGNUM))])
2841    (parallel
2842     [(set (match_operand:P 0 "register_operand" "")
2843           (minus:P (match_dup 4) (match_dup 5)))
2844      (clobber (reg:CC CC_REGNUM))])]
2845   ""
2846 {
2847   operands[4] = gen_reg_rtx (Pmode);
2848   operands[5] = gen_reg_rtx (Pmode);
2849   emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2850   operands[1] = replace_equiv_address (operands[1], operands[5]);
2851 })
2852
2853 (define_insn "*strlen<mode>"
2854   [(set (match_operand:P 0 "register_operand" "=a")
2855         (unspec:P [(match_operand:P 2 "general_operand" "0")
2856                     (mem:BLK (match_operand:P 3 "register_operand" "1"))
2857                     (reg:SI 0)
2858                     (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2859    (clobber (match_scratch:P 1 "=a"))
2860    (clobber (reg:CC CC_REGNUM))]
2861   ""
2862   "srst\t%0,%1\;jo\t.-4"
2863   [(set_attr "length" "8")
2864    (set_attr "type" "vs")])
2865
2866 ;
2867 ; cmpstrM instruction pattern(s).
2868 ;
2869
2870 (define_expand "cmpstrsi"
2871   [(set (reg:SI 0) (const_int 0))
2872    (parallel
2873     [(clobber (match_operand 3 "" ""))
2874      (clobber (match_dup 4))
2875      (set (reg:CCU CC_REGNUM)
2876           (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2877                        (match_operand:BLK 2 "memory_operand" "")))
2878      (use (reg:SI 0))])
2879    (parallel
2880     [(set (match_operand:SI 0 "register_operand" "=d")
2881           (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2882      (clobber (reg:CC CC_REGNUM))])]
2883   ""
2884 {
2885   /* As the result of CMPINT is inverted compared to what we need,
2886      we have to swap the operands.  */
2887   rtx op1 = operands[2];
2888   rtx op2 = operands[1];
2889   rtx addr1 = gen_reg_rtx (Pmode);
2890   rtx addr2 = gen_reg_rtx (Pmode);
2891
2892   emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2893   emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2894   operands[1] = replace_equiv_address_nv (op1, addr1);
2895   operands[2] = replace_equiv_address_nv (op2, addr2);
2896   operands[3] = addr1;
2897   operands[4] = addr2;
2898 })
2899
2900 (define_insn "*cmpstr<mode>"
2901   [(clobber (match_operand:P 0 "register_operand" "=d"))
2902    (clobber (match_operand:P 1 "register_operand" "=d"))
2903    (set (reg:CCU CC_REGNUM)
2904         (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2905                      (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2906    (use (reg:SI 0))]
2907   ""
2908   "clst\t%0,%1\;jo\t.-4"
2909   [(set_attr "length" "8")
2910    (set_attr "type" "vs")])
2911
2912 ;
2913 ; movstr instruction pattern.
2914 ;
2915
2916 (define_expand "movstr"
2917   [(match_operand 0 "register_operand" "")
2918    (match_operand 1 "memory_operand" "")
2919    (match_operand 2 "memory_operand" "")]
2920   ""
2921 {
2922   if (TARGET_64BIT)
2923     emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2924   else
2925     emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2926   DONE;
2927 })
2928
2929 (define_expand "movstr<P:mode>"
2930   [(set (reg:SI 0) (const_int 0))
2931    (parallel
2932     [(clobber (match_dup 3))
2933      (set (match_operand:BLK 1 "memory_operand" "")
2934           (match_operand:BLK 2 "memory_operand" ""))
2935      (set (match_operand:P 0 "register_operand" "")
2936           (unspec:P [(match_dup 1)
2937                    (match_dup 2)
2938                    (reg:SI 0)] UNSPEC_MVST))
2939      (clobber (reg:CC CC_REGNUM))])]
2940   ""
2941 {
2942   rtx addr1, addr2;
2943
2944   if (TARGET_VX && optimize_function_for_speed_p (cfun))
2945     {
2946       s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
2947       DONE;
2948     }
2949
2950   addr1 = gen_reg_rtx (Pmode);
2951   addr2 = gen_reg_rtx (Pmode);
2952
2953   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2954   emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2955   operands[1] = replace_equiv_address_nv (operands[1], addr1);
2956   operands[2] = replace_equiv_address_nv (operands[2], addr2);
2957   operands[3] = addr2;
2958 })
2959
2960 (define_insn "*movstr"
2961   [(clobber (match_operand:P 2 "register_operand" "=d"))
2962    (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2963         (mem:BLK (match_operand:P 3 "register_operand" "2")))
2964    (set (match_operand:P 0 "register_operand" "=d")
2965         (unspec:P [(mem:BLK (match_dup 1))
2966                  (mem:BLK (match_dup 3))
2967                  (reg:SI 0)] UNSPEC_MVST))
2968    (clobber (reg:CC CC_REGNUM))]
2969   ""
2970   "mvst\t%1,%2\;jo\t.-4"
2971   [(set_attr "length" "8")
2972    (set_attr "type" "vs")])
2973
2974
2975 ;
2976 ; movmemM instruction pattern(s).
2977 ;
2978
2979 (define_expand "movmem<mode>"
2980   [(set (match_operand:BLK 0 "memory_operand" "")   ; destination
2981         (match_operand:BLK 1 "memory_operand" ""))  ; source
2982    (use (match_operand:GPR 2 "general_operand" "")) ; count
2983    (match_operand 3 "" "")]
2984   ""
2985 {
2986   if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2987     DONE;
2988   else
2989     FAIL;
2990 })
2991
2992 ; Move a block that is up to 256 bytes in length.
2993 ; The block length is taken as (operands[2] % 256) + 1.
2994
2995 (define_expand "movmem_short"
2996   [(parallel
2997     [(set (match_operand:BLK 0 "memory_operand" "")
2998           (match_operand:BLK 1 "memory_operand" ""))
2999      (use (match_operand 2 "nonmemory_operand" ""))
3000      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3001      (clobber (match_dup 3))])]
3002   ""
3003   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3004
3005 (define_insn "*movmem_short"
3006   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3007         (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3008    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3009    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3010    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3011   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3012   "#"
3013   [(set_attr "type"         "cs")
3014    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3015
3016 (define_split
3017   [(set (match_operand:BLK 0 "memory_operand" "")
3018         (match_operand:BLK 1 "memory_operand" ""))
3019    (use (match_operand 2 "const_int_operand" ""))
3020    (use (match_operand 3 "immediate_operand" ""))
3021    (clobber (scratch))]
3022   "reload_completed"
3023   [(parallel
3024     [(set (match_dup 0) (match_dup 1))
3025      (use (match_dup 2))])]
3026   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3027
3028 (define_split
3029   [(set (match_operand:BLK 0 "memory_operand" "")
3030         (match_operand:BLK 1 "memory_operand" ""))
3031    (use (match_operand 2 "register_operand" ""))
3032    (use (match_operand 3 "memory_operand" ""))
3033    (clobber (scratch))]
3034   "reload_completed"
3035   [(parallel
3036     [(unspec [(match_dup 2) (match_dup 3)
3037               (const_int 0)] UNSPEC_EXECUTE)
3038      (set (match_dup 0) (match_dup 1))
3039      (use (const_int 1))])]
3040   "")
3041
3042 (define_split
3043   [(set (match_operand:BLK 0 "memory_operand" "")
3044         (match_operand:BLK 1 "memory_operand" ""))
3045    (use (match_operand 2 "register_operand" ""))
3046    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3047    (clobber (scratch))]
3048   "TARGET_Z10 && reload_completed"
3049   [(parallel
3050     [(unspec [(match_dup 2) (const_int 0)
3051               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3052      (set (match_dup 0) (match_dup 1))
3053      (use (const_int 1))])]
3054   "operands[3] = gen_label_rtx ();")
3055
3056 (define_split
3057   [(set (match_operand:BLK 0 "memory_operand" "")
3058         (match_operand:BLK 1 "memory_operand" ""))
3059    (use (match_operand 2 "register_operand" ""))
3060    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3061    (clobber (match_operand 3 "register_operand" ""))]
3062   "reload_completed && TARGET_CPU_ZARCH"
3063   [(set (match_dup 3) (label_ref (match_dup 4)))
3064    (parallel
3065     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3066               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3067      (set (match_dup 0) (match_dup 1))
3068      (use (const_int 1))])]
3069   "operands[4] = gen_label_rtx ();")
3070
3071 ; Move a block of arbitrary length.
3072
3073 (define_expand "movmem_long"
3074   [(parallel
3075     [(clobber (match_dup 2))
3076      (clobber (match_dup 3))
3077      (set (match_operand:BLK 0 "memory_operand" "")
3078           (match_operand:BLK 1 "memory_operand" ""))
3079      (use (match_operand 2 "general_operand" ""))
3080      (use (match_dup 3))
3081      (clobber (reg:CC CC_REGNUM))])]
3082   ""
3083 {
3084   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3085   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3086   rtx reg0 = gen_reg_rtx (dreg_mode);
3087   rtx reg1 = gen_reg_rtx (dreg_mode);
3088   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3089   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3090   rtx len0 = gen_lowpart (Pmode, reg0);
3091   rtx len1 = gen_lowpart (Pmode, reg1);
3092
3093   emit_clobber (reg0);
3094   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3095   emit_move_insn (len0, operands[2]);
3096
3097   emit_clobber (reg1);
3098   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3099   emit_move_insn (len1, operands[2]);
3100
3101   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3102   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3103   operands[2] = reg0;
3104   operands[3] = reg1;
3105 })
3106
3107 (define_insn "*movmem_long"
3108   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3109    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3110    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3111         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3112    (use (match_dup 2))
3113    (use (match_dup 3))
3114    (clobber (reg:CC CC_REGNUM))]
3115   "TARGET_64BIT || !TARGET_ZARCH"
3116   "mvcle\t%0,%1,0\;jo\t.-4"
3117   [(set_attr "length" "8")
3118    (set_attr "type" "vs")])
3119
3120 (define_insn "*movmem_long_31z"
3121   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3122    (clobber (match_operand:TI 1 "register_operand" "=d"))
3123    (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3124         (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3125    (use (match_dup 2))
3126    (use (match_dup 3))
3127    (clobber (reg:CC CC_REGNUM))]
3128   "!TARGET_64BIT && TARGET_ZARCH"
3129   "mvcle\t%0,%1,0\;jo\t.-4"
3130   [(set_attr "length" "8")
3131    (set_attr "type" "vs")])
3132
3133
3134 ;
3135 ; Test data class.
3136 ;
3137
3138 (define_expand "signbit<mode>2"
3139   [(set (reg:CCZ CC_REGNUM)
3140         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3141                      (match_dup 2)]
3142                      UNSPEC_TDC_INSN))
3143    (set (match_operand:SI 0 "register_operand" "=d")
3144         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3145   "TARGET_HARD_FLOAT"
3146 {
3147   operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3148 })
3149
3150 (define_expand "isinf<mode>2"
3151   [(set (reg:CCZ CC_REGNUM)
3152         (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3153                      (match_dup 2)]
3154                      UNSPEC_TDC_INSN))
3155    (set (match_operand:SI 0 "register_operand" "=d")
3156         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3157   "TARGET_HARD_FLOAT"
3158 {
3159   operands[2] = GEN_INT (S390_TDC_INFINITY);
3160 })
3161
3162 ; This extracts CC into a GPR properly shifted.  The actual IPM
3163 ; instruction will be issued by reload.  The constraint of operand 1
3164 ; forces reload to use a GPR.  So reload will issue a movcc insn for
3165 ; copying CC into a GPR first.
3166 (define_insn_and_split "*cc_to_int"
3167   [(set (match_operand:SI 0 "nonimmediate_operand"     "=d")
3168         (unspec:SI [(match_operand 1 "register_operand" "0")]
3169                    UNSPEC_CC_TO_INT))]
3170   "operands != NULL"
3171   "#"
3172   "reload_completed"
3173   [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3174
3175 ; This insn is used to generate all variants of the Test Data Class
3176 ; instruction, namely tcxb, tcdb, and tceb.  The insn's first operand
3177 ; is the register to be tested and the second one is the bit mask
3178 ; specifying the required test(s).
3179 ;
3180 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3181 (define_insn "*TDC_insn_<mode>"
3182   [(set (reg:CCZ CC_REGNUM)
3183         (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3184                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3185   "TARGET_HARD_FLOAT"
3186   "t<_d>c<xde><bt>\t%0,%1"
3187    [(set_attr "op_type" "RXE")
3188     (set_attr "type"  "fsimp<mode>")])
3189
3190
3191
3192 ;
3193 ; setmemM instruction pattern(s).
3194 ;
3195
3196 (define_expand "setmem<mode>"
3197   [(set (match_operand:BLK 0 "memory_operand" "")
3198         (match_operand:QI 2 "general_operand" ""))
3199    (use (match_operand:GPR 1 "general_operand" ""))
3200    (match_operand 3 "" "")]
3201   ""
3202   "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3203
3204 ; Clear a block that is up to 256 bytes in length.
3205 ; The block length is taken as (operands[1] % 256) + 1.
3206
3207 (define_expand "clrmem_short"
3208   [(parallel
3209     [(set (match_operand:BLK 0 "memory_operand" "")
3210           (const_int 0))
3211      (use (match_operand 1 "nonmemory_operand" ""))
3212      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3213      (clobber (match_dup 2))
3214      (clobber (reg:CC CC_REGNUM))])]
3215   ""
3216   "operands[2] = gen_rtx_SCRATCH (Pmode);")
3217
3218 (define_insn "*clrmem_short"
3219   [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3220         (const_int 0))
3221    (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3222    (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3223    (clobber (match_scratch:P 3 "=X,X,X,&a"))
3224    (clobber (reg:CC CC_REGNUM))]
3225   "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3226   "#"
3227   [(set_attr "type" "cs")
3228    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3229
3230 (define_split
3231   [(set (match_operand:BLK 0 "memory_operand" "")
3232         (const_int 0))
3233    (use (match_operand 1 "const_int_operand" ""))
3234    (use (match_operand 2 "immediate_operand" ""))
3235    (clobber (scratch))
3236    (clobber (reg:CC CC_REGNUM))]
3237   "reload_completed"
3238   [(parallel
3239     [(set (match_dup 0) (const_int 0))
3240      (use (match_dup 1))
3241      (clobber (reg:CC CC_REGNUM))])]
3242   "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3243
3244 (define_split
3245   [(set (match_operand:BLK 0 "memory_operand" "")
3246         (const_int 0))
3247    (use (match_operand 1 "register_operand" ""))
3248    (use (match_operand 2 "memory_operand" ""))
3249    (clobber (scratch))
3250    (clobber (reg:CC CC_REGNUM))]
3251   "reload_completed"
3252   [(parallel
3253     [(unspec [(match_dup 1) (match_dup 2)
3254               (const_int 0)] UNSPEC_EXECUTE)
3255      (set (match_dup 0) (const_int 0))
3256      (use (const_int 1))
3257      (clobber (reg:CC CC_REGNUM))])]
3258   "")
3259
3260 (define_split
3261   [(set (match_operand:BLK 0 "memory_operand" "")
3262         (const_int 0))
3263    (use (match_operand 1 "register_operand" ""))
3264    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3265    (clobber (scratch))
3266    (clobber (reg:CC CC_REGNUM))]
3267   "TARGET_Z10 && reload_completed"
3268   [(parallel
3269     [(unspec [(match_dup 1) (const_int 0)
3270               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3271      (set (match_dup 0) (const_int 0))
3272      (use (const_int 1))
3273      (clobber (reg:CC CC_REGNUM))])]
3274   "operands[3] = gen_label_rtx ();")
3275
3276 (define_split
3277   [(set (match_operand:BLK 0 "memory_operand" "")
3278         (const_int 0))
3279    (use (match_operand 1 "register_operand" ""))
3280    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3281    (clobber (match_operand 2 "register_operand" ""))
3282    (clobber (reg:CC CC_REGNUM))]
3283   "reload_completed && TARGET_CPU_ZARCH"
3284   [(set (match_dup 2) (label_ref (match_dup 3)))
3285    (parallel
3286     [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3287               (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3288      (set (match_dup 0) (const_int 0))
3289      (use (const_int 1))
3290      (clobber (reg:CC CC_REGNUM))])]
3291   "operands[3] = gen_label_rtx ();")
3292
3293 ; Initialize a block of arbitrary length with (operands[2] % 256).
3294
3295 (define_expand "setmem_long_<P:mode>"
3296   [(parallel
3297     [(clobber (match_dup 1))
3298      (set (match_operand:BLK 0 "memory_operand" "")
3299           (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "")
3300                       (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3301      (use (match_dup 3))
3302      (clobber (reg:CC CC_REGNUM))])]
3303   ""
3304 {
3305   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3306   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3307   rtx reg0 = gen_reg_rtx (dreg_mode);
3308   rtx reg1 = gen_reg_rtx (dreg_mode);
3309   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3310   rtx len0 = gen_lowpart (Pmode, reg0);
3311
3312   emit_clobber (reg0);
3313   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3314   emit_move_insn (len0, operands[1]);
3315
3316   emit_move_insn (reg1, const0_rtx);
3317
3318   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3319   operands[1] = reg0;
3320   operands[3] = reg1;
3321   operands[4] = gen_lowpart (Pmode, operands[1]);
3322 })
3323
3324 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3325
3326 (define_insn "*setmem_long"
3327   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3328    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3329         (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y")
3330                      (subreg:P (match_dup 3) <modesize>)]
3331                      UNSPEC_REPLICATE_BYTE))
3332    (use (match_operand:<DBL> 1 "register_operand" "d"))
3333    (clobber (reg:CC CC_REGNUM))]
3334   "TARGET_64BIT || !TARGET_ZARCH"
3335   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3336   [(set_attr "length" "8")
3337    (set_attr "type" "vs")])
3338
3339 (define_insn "*setmem_long_and"
3340   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3341    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3342         (unspec:BLK [(and:P
3343                       (match_operand:P 2 "shift_count_or_setmem_operand" "Y")
3344                       (match_operand:P 4 "const_int_operand"             "n"))
3345                     (subreg:P (match_dup 3) <modesize>)]
3346                     UNSPEC_REPLICATE_BYTE))
3347    (use (match_operand:<DBL> 1 "register_operand" "d"))
3348    (clobber (reg:CC CC_REGNUM))]
3349   "(TARGET_64BIT || !TARGET_ZARCH) &&
3350    (INTVAL (operands[4]) & 255) == 255"
3351   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3352   [(set_attr "length" "8")
3353    (set_attr "type" "vs")])
3354
3355 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3356 ; of the SImode subregs.
3357
3358 (define_insn "*setmem_long_31z"
3359   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3360    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3361         (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
3362                      (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3363    (use (match_operand:TI 1 "register_operand" "d"))
3364    (clobber (reg:CC CC_REGNUM))]
3365   "!TARGET_64BIT && TARGET_ZARCH"
3366   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3367   [(set_attr "length" "8")
3368    (set_attr "type" "vs")])
3369
3370 (define_insn "*setmem_long_and_31z"
3371   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3372    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3373         (unspec:BLK [(and:SI
3374                       (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
3375                       (match_operand:SI 4 "const_int_operand"             "n"))
3376                     (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3377    (use (match_operand:TI 1 "register_operand" "d"))
3378    (clobber (reg:CC CC_REGNUM))]
3379   "(!TARGET_64BIT && TARGET_ZARCH) &&
3380    (INTVAL (operands[4]) & 255) == 255"
3381   "mvcle\t%0,%1,%Y2\;jo\t.-4"
3382   [(set_attr "length" "8")
3383    (set_attr "type" "vs")])
3384
3385 ;
3386 ; cmpmemM instruction pattern(s).
3387 ;
3388
3389 (define_expand "cmpmemsi"
3390   [(set (match_operand:SI 0 "register_operand" "")
3391         (compare:SI (match_operand:BLK 1 "memory_operand" "")
3392                     (match_operand:BLK 2 "memory_operand" "") ) )
3393    (use (match_operand:SI 3 "general_operand" ""))
3394    (use (match_operand:SI 4 "" ""))]
3395   ""
3396 {
3397   if (s390_expand_cmpmem (operands[0], operands[1],
3398                           operands[2], operands[3]))
3399     DONE;
3400   else
3401     FAIL;
3402 })
3403
3404 ; Compare a block that is up to 256 bytes in length.
3405 ; The block length is taken as (operands[2] % 256) + 1.
3406
3407 (define_expand "cmpmem_short"
3408   [(parallel
3409     [(set (reg:CCU CC_REGNUM)
3410           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3411                        (match_operand:BLK 1 "memory_operand" "")))
3412      (use (match_operand 2 "nonmemory_operand" ""))
3413      (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3414      (clobber (match_dup 3))])]
3415   ""
3416   "operands[3] = gen_rtx_SCRATCH (Pmode);")
3417
3418 (define_insn "*cmpmem_short"
3419   [(set (reg:CCU CC_REGNUM)
3420         (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3421                      (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3422    (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3423    (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3424    (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3425   "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3426   "#"
3427   [(set_attr "type" "cs")
3428    (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3429
3430 (define_split
3431   [(set (reg:CCU CC_REGNUM)
3432         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3433                      (match_operand:BLK 1 "memory_operand" "")))
3434    (use (match_operand 2 "const_int_operand" ""))
3435    (use (match_operand 3 "immediate_operand" ""))
3436    (clobber (scratch))]
3437   "reload_completed"
3438   [(parallel
3439     [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3440      (use (match_dup 2))])]
3441   "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3442
3443 (define_split
3444   [(set (reg:CCU CC_REGNUM)
3445         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3446                      (match_operand:BLK 1 "memory_operand" "")))
3447    (use (match_operand 2 "register_operand" ""))
3448    (use (match_operand 3 "memory_operand" ""))
3449    (clobber (scratch))]
3450   "reload_completed"
3451   [(parallel
3452     [(unspec [(match_dup 2) (match_dup 3)
3453               (const_int 0)] UNSPEC_EXECUTE)
3454      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3455      (use (const_int 1))])]
3456   "")
3457
3458 (define_split
3459   [(set (reg:CCU CC_REGNUM)
3460         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3461                      (match_operand:BLK 1 "memory_operand" "")))
3462    (use (match_operand 2 "register_operand" ""))
3463    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3464    (clobber (scratch))]
3465   "TARGET_Z10 && reload_completed"
3466   [(parallel
3467     [(unspec [(match_dup 2) (const_int 0)
3468               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3469      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3470      (use (const_int 1))])]
3471   "operands[4] = gen_label_rtx ();")
3472
3473 (define_split
3474   [(set (reg:CCU CC_REGNUM)
3475         (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3476                      (match_operand:BLK 1 "memory_operand" "")))
3477    (use (match_operand 2 "register_operand" ""))
3478    (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3479    (clobber (match_operand 3 "register_operand" ""))]
3480   "reload_completed && TARGET_CPU_ZARCH"
3481   [(set (match_dup 3) (label_ref (match_dup 4)))
3482    (parallel
3483     [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3484               (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3485      (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3486      (use (const_int 1))])]
3487   "operands[4] = gen_label_rtx ();")
3488
3489 ; Compare a block of arbitrary length.
3490
3491 (define_expand "cmpmem_long"
3492   [(parallel
3493     [(clobber (match_dup 2))
3494      (clobber (match_dup 3))
3495      (set (reg:CCU CC_REGNUM)
3496           (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3497                        (match_operand:BLK 1 "memory_operand" "")))
3498      (use (match_operand 2 "general_operand" ""))
3499      (use (match_dup 3))])]
3500   ""
3501 {
3502   machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3503   machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3504   rtx reg0 = gen_reg_rtx (dreg_mode);
3505   rtx reg1 = gen_reg_rtx (dreg_mode);
3506   rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3507   rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3508   rtx len0 = gen_lowpart (Pmode, reg0);
3509   rtx len1 = gen_lowpart (Pmode, reg1);
3510
3511   emit_clobber (reg0);
3512   emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3513   emit_move_insn (len0, operands[2]);
3514
3515   emit_clobber (reg1);
3516   emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3517   emit_move_insn (len1, operands[2]);
3518
3519   operands[0] = replace_equiv_address_nv (operands[0], addr0);
3520   operands[1] = replace_equiv_address_nv (operands[1], addr1);
3521   operands[2] = reg0;
3522   operands[3] = reg1;
3523 })
3524
3525 (define_insn "*cmpmem_long"
3526   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3527    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3528    (set (reg:CCU CC_REGNUM)
3529         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3530                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3531    (use (match_dup 2))
3532    (use (match_dup 3))]
3533   "TARGET_64BIT || !TARGET_ZARCH"
3534   "clcle\t%0,%1,0\;jo\t.-4"
3535   [(set_attr "length" "8")
3536    (set_attr "type" "vs")])
3537
3538 (define_insn "*cmpmem_long_31z"
3539   [(clobber (match_operand:TI 0 "register_operand" "=d"))
3540    (clobber (match_operand:TI 1 "register_operand" "=d"))
3541    (set (reg:CCU CC_REGNUM)
3542         (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3543                      (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3544    (use (match_dup 2))
3545    (use (match_dup 3))]
3546   "!TARGET_64BIT && TARGET_ZARCH"
3547   "clcle\t%0,%1,0\;jo\t.-4"
3548   [(set_attr "op_type" "NN")
3549    (set_attr "type"    "vs")
3550    (set_attr "length"  "8")])
3551
3552 ; Convert CCUmode condition code to integer.
3553 ; Result is zero if EQ, positive if LTU, negative if GTU.
3554
3555 (define_insn_and_split "cmpint"
3556   [(set (match_operand:SI 0 "register_operand" "=d")
3557         (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3558                    UNSPEC_STRCMPCC_TO_INT))
3559    (clobber (reg:CC CC_REGNUM))]
3560   ""
3561   "#"
3562   "reload_completed"
3563   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3564    (parallel
3565     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3566      (clobber (reg:CC CC_REGNUM))])])
3567
3568 (define_insn_and_split "*cmpint_cc"
3569   [(set (reg CC_REGNUM)
3570         (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3571                             UNSPEC_STRCMPCC_TO_INT)
3572                  (const_int 0)))
3573    (set (match_operand:SI 0 "register_operand" "=d")
3574         (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3575   "s390_match_ccmode (insn, CCSmode)"
3576   "#"
3577   "&& reload_completed"
3578   [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3579    (parallel
3580     [(set (match_dup 2) (match_dup 3))
3581      (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3582 {
3583   rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3584   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3585   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3586 })
3587
3588 (define_insn_and_split "*cmpint_sign"
3589   [(set (match_operand:DI 0 "register_operand" "=d")
3590         (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3591                                    UNSPEC_STRCMPCC_TO_INT)))
3592    (clobber (reg:CC CC_REGNUM))]
3593   "TARGET_ZARCH"
3594   "#"
3595   "&& reload_completed"
3596   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3597    (parallel
3598     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3599      (clobber (reg:CC CC_REGNUM))])])
3600
3601 (define_insn_and_split "*cmpint_sign_cc"
3602   [(set (reg CC_REGNUM)
3603         (compare (ashiftrt:DI (ashift:DI (subreg:DI
3604                    (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3605                               UNSPEC_STRCMPCC_TO_INT) 0)
3606                    (const_int 32)) (const_int 32))
3607                  (const_int 0)))
3608    (set (match_operand:DI 0 "register_operand" "=d")
3609         (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3610   "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3611   "#"
3612   "&& reload_completed"
3613   [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3614    (parallel
3615     [(set (match_dup 2) (match_dup 3))
3616      (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3617 {
3618   rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3619   operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3620   operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3621 })
3622
3623
3624 ;;
3625 ;;- Conversion instructions.
3626 ;;
3627
3628 (define_insn "*sethighpartsi"
3629   [(set (match_operand:SI 0 "register_operand" "=d,d")
3630         (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3631                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3632    (clobber (reg:CC CC_REGNUM))]
3633   ""
3634   "@
3635    icm\t%0,%2,%S1
3636    icmy\t%0,%2,%S1"
3637   [(set_attr "op_type" "RS,RSY")
3638    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3639
3640 (define_insn "*sethighpartdi_64"
3641   [(set (match_operand:DI 0 "register_operand" "=d")
3642         (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3643                     (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3644    (clobber (reg:CC CC_REGNUM))]
3645   "TARGET_ZARCH"
3646   "icmh\t%0,%2,%S1"
3647   [(set_attr "op_type" "RSY")
3648    (set_attr "z10prop" "z10_super")])
3649
3650 (define_insn "*sethighpartdi_31"
3651   [(set (match_operand:DI 0 "register_operand" "=d,d")
3652         (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3653                     (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3654    (clobber (reg:CC CC_REGNUM))]
3655   "!TARGET_ZARCH"
3656   "@
3657    icm\t%0,%2,%S1
3658    icmy\t%0,%2,%S1"
3659   [(set_attr "op_type" "RS,RSY")
3660    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3661
3662 ;
3663 ; extv instruction patterns
3664 ;
3665
3666 ; FIXME: This expander needs to be converted from DI to GPR as well
3667 ; after resolving some issues with it.
3668
3669 (define_expand "extzv"
3670   [(parallel
3671     [(set (match_operand:DI 0 "register_operand" "=d")
3672         (zero_extract:DI
3673          (match_operand:DI 1 "register_operand" "d")
3674          (match_operand 2 "const_int_operand" "")   ; size
3675          (match_operand 3 "const_int_operand" ""))) ; start
3676      (clobber (reg:CC CC_REGNUM))])]
3677   "TARGET_Z10"
3678 {
3679   /* Starting with zEC12 there is risbgn not clobbering CC.  */
3680   if (TARGET_ZEC12)
3681     {
3682       emit_move_insn (operands[0],
3683                     gen_rtx_ZERO_EXTRACT (DImode,
3684                                           operands[1],
3685                                           operands[2],
3686                                           operands[3]));
3687       DONE;
3688     }
3689 })
3690
3691 (define_insn "*extzv<mode>_zEC12"
3692   [(set (match_operand:GPR 0 "register_operand" "=d")
3693       (zero_extract:GPR
3694         (match_operand:GPR 1 "register_operand" "d")
3695         (match_operand 2 "const_int_operand" "")   ; size
3696         (match_operand 3 "const_int_operand" "")))] ; start]
3697   "TARGET_ZEC12"
3698   "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3699   [(set_attr "op_type" "RIE")])
3700
3701 (define_insn "*extzv<mode>_z10"
3702   [(set (match_operand:GPR 0 "register_operand" "=d")
3703       (zero_extract:GPR
3704        (match_operand:GPR 1 "register_operand" "d")
3705        (match_operand 2 "const_int_operand" "")   ; size
3706        (match_operand 3 "const_int_operand" ""))) ; start
3707    (clobber (reg:CC CC_REGNUM))]
3708   "TARGET_Z10"
3709   "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3710   [(set_attr "op_type" "RIE")
3711    (set_attr "z10prop" "z10_super_E1")])
3712
3713 (define_insn_and_split "*pre_z10_extzv<mode>"
3714   [(set (match_operand:GPR 0 "register_operand" "=d")
3715         (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3716                           (match_operand 2 "nonzero_shift_count_operand" "")
3717                           (const_int 0)))
3718    (clobber (reg:CC CC_REGNUM))]
3719   "!TARGET_Z10"
3720   "#"
3721   "&& reload_completed"
3722   [(parallel
3723     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3724      (clobber (reg:CC CC_REGNUM))])
3725    (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3726 {
3727   int bitsize = INTVAL (operands[2]);
3728   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3729   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3730
3731   operands[1] = adjust_address (operands[1], BLKmode, 0);
3732   set_mem_size (operands[1], size);
3733   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3734   operands[3] = GEN_INT (mask);
3735 })
3736
3737 (define_insn_and_split "*pre_z10_extv<mode>"
3738   [(set (match_operand:GPR 0 "register_operand" "=d")
3739         (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3740                           (match_operand 2 "nonzero_shift_count_operand" "")
3741                           (const_int 0)))
3742    (clobber (reg:CC CC_REGNUM))]
3743   ""
3744   "#"
3745   "&& reload_completed"
3746   [(parallel
3747     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3748      (clobber (reg:CC CC_REGNUM))])
3749    (parallel
3750     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3751      (clobber (reg:CC CC_REGNUM))])]
3752 {
3753   int bitsize = INTVAL (operands[2]);
3754   int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3755   int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3756
3757   operands[1] = adjust_address (operands[1], BLKmode, 0);
3758   set_mem_size (operands[1], size);
3759   operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3760   operands[3] = GEN_INT (mask);
3761 })
3762
3763 ;
3764 ; insv instruction patterns
3765 ;
3766
3767 (define_expand "insv"
3768   [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3769                       (match_operand 1 "const_int_operand" "")
3770                       (match_operand 2 "const_int_operand" ""))
3771         (match_operand 3 "general_operand" ""))]
3772   ""
3773 {
3774   if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3775     DONE;
3776   FAIL;
3777 })
3778
3779
3780 ; The normal RTL expansion will never generate a zero_extract where
3781 ; the location operand isn't word mode.  However, we do this in the
3782 ; back-end when generating atomic operations. See s390_two_part_insv.
3783 (define_insn "*insv<mode>_zEC12"
3784   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3785                           (match_operand 1 "const_int_operand"    "I")  ; size
3786                           (match_operand 2 "const_int_operand"    "I")) ; pos
3787         (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3788   "TARGET_ZEC12
3789    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3790   "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3791   [(set_attr "op_type" "RIE")])
3792
3793 (define_insn "*insv<mode>_z10"
3794   [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3795                           (match_operand 1 "const_int_operand"    "I")  ; size
3796                           (match_operand 2 "const_int_operand"    "I")) ; pos
3797         (match_operand:GPR 3 "nonimmediate_operand" "d"))
3798    (clobber (reg:CC CC_REGNUM))]
3799   "TARGET_Z10
3800    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3801   "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3802   [(set_attr "op_type" "RIE")
3803    (set_attr "z10prop" "z10_super_E1")])
3804
3805 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3806 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3807 (define_insn "*insv<mode>_zEC12_noshift"
3808   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3809         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3810                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3811                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3812                           (match_operand:GPR 4 "const_int_operand" ""))))]
3813   "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3814   "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3815   [(set_attr "op_type" "RIE")])
3816
3817 (define_insn "*insv<mode>_z10_noshift"
3818   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3819         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3820                           (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3821                  (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3822                           (match_operand:GPR 4 "const_int_operand" ""))))
3823    (clobber (reg:CC CC_REGNUM))]
3824   "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3825   "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3826   [(set_attr "op_type" "RIE")
3827    (set_attr "z10prop" "z10_super_E1")])
3828
3829 ; Implement appending Y on the left of S bits of X
3830 ; x = (y << s) | (x & ((1 << s) - 1))
3831 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3832   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3833         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3834                           (match_operand:GPR 2 "immediate_operand" ""))
3835                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3836                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3837   "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3838   "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3839   [(set_attr "op_type" "RIE")
3840    (set_attr "z10prop" "z10_super_E1")])
3841
3842 (define_insn "*insv<mode>_z10_appendbitsleft"
3843   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3844         (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3845                           (match_operand:GPR 2 "immediate_operand" ""))
3846                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3847                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3848    (clobber (reg:CC CC_REGNUM))]
3849   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3850   "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3851   [(set_attr "op_type" "RIE")
3852    (set_attr "z10prop" "z10_super_E1")])
3853
3854 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3855 ;  -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3856 ;  -> z = y >> d; z = risbg;
3857
3858 (define_split
3859   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3860         (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3861                                (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3862                  (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3863                              (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3864   "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3865   [(set (match_dup 6)
3866         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3867    (set (match_dup 0)
3868         (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3869                  (ashift:GPR (match_dup 3) (match_dup 4))))]
3870 {
3871   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3872   if (rtx_equal_p (operands[0], operands[3]))
3873     {
3874       if (!can_create_pseudo_p ())
3875         FAIL;
3876       operands[6] = gen_reg_rtx (<MODE>mode);
3877     }
3878   else
3879     operands[6] = operands[0];
3880 })
3881
3882 (define_split
3883   [(parallel
3884     [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3885           (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3886                                  (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3887                    (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3888                                (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3889      (clobber (reg:CC CC_REGNUM))])]
3890   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3891   [(set (match_dup 6)
3892         (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3893    (parallel
3894     [(set (match_dup 0)
3895           (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3896                    (ashift:GPR (match_dup 3) (match_dup 4))))
3897      (clobber (reg:CC CC_REGNUM))])]
3898 {
3899   operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3900   if (rtx_equal_p (operands[0], operands[3]))
3901     {
3902       if (!can_create_pseudo_p ())
3903         FAIL;
3904       operands[6] = gen_reg_rtx (<MODE>mode);
3905     }
3906   else
3907     operands[6] = operands[0];
3908 })
3909
3910 (define_insn "*r<noxa>sbg_<mode>_noshift"
3911   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3912         (IXOR:GPR
3913           (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3914                    (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3915           (match_operand:GPR 3 "nonimmediate_operand" "0")))
3916    (clobber (reg:CC CC_REGNUM))]
3917   "TARGET_Z10"
3918   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3919   [(set_attr "op_type" "RIE")])
3920
3921 (define_insn "*r<noxa>sbg_di_rotl"
3922   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3923         (IXOR:DI
3924           (and:DI
3925             (rotate:DI
3926               (match_operand:DI 1 "nonimmediate_operand" "d")
3927               (match_operand:DI 3 "const_int_operand" ""))
3928             (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3929           (match_operand:DI 4 "nonimmediate_operand" "0")))
3930    (clobber (reg:CC CC_REGNUM))]
3931   "TARGET_Z10"
3932   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3933   [(set_attr "op_type" "RIE")])
3934
3935 (define_insn "*r<noxa>sbg_<mode>_srl"
3936   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3937         (IXOR:GPR
3938           (and:GPR
3939             (lshiftrt:GPR
3940               (match_operand:GPR 1 "nonimmediate_operand" "d")
3941               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3942             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3943           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3944    (clobber (reg:CC CC_REGNUM))]
3945   "TARGET_Z10
3946    && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3947                            INTVAL (operands[2]))"
3948   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3949   [(set_attr "op_type" "RIE")])
3950
3951 (define_insn "*r<noxa>sbg_<mode>_sll"
3952   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3953         (IXOR:GPR
3954           (and:GPR
3955             (ashift:GPR
3956               (match_operand:GPR 1 "nonimmediate_operand" "d")
3957               (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3958             (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3959           (match_operand:GPR 4 "nonimmediate_operand" "0")))
3960    (clobber (reg:CC CC_REGNUM))]
3961   "TARGET_Z10
3962    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3963                            INTVAL (operands[2]))"
3964   "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3965   [(set_attr "op_type" "RIE")])
3966
3967 ;; These two are generated by combine for s.bf &= val.
3968 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3969 ;; shifts and ands, which results in some truly awful patterns
3970 ;; including subregs of operations.  Rather unnecessisarily, IMO.
3971 ;; Instead of
3972 ;;
3973 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3974 ;;        (const_int 24 [0x18])
3975 ;;        (const_int 0 [0]))
3976 ;;    (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3977 ;;                    (const_int 40 [0x28])) 4)
3978 ;;            (reg:SI 4 %r4 [ y+4 ])) 0))
3979 ;;
3980 ;; we should instead generate
3981 ;;
3982 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3983 ;;        (const_int 24 [0x18])
3984 ;;        (const_int 0 [0]))
3985 ;;    (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3986 ;;                    (const_int 40 [0x28]))
3987 ;;            (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3988 ;;
3989 ;; by noticing that we can push down the outer paradoxical subreg
3990 ;; into the operation.
3991
3992 (define_insn "*insv_rnsbg_noshift"
3993   [(set (zero_extract:DI
3994           (match_operand:DI 0 "nonimmediate_operand" "+d")
3995           (match_operand 1 "const_int_operand" "")
3996           (match_operand 2 "const_int_operand" ""))
3997         (and:DI
3998           (match_dup 0)
3999           (match_operand:DI 3 "nonimmediate_operand" "d")))
4000    (clobber (reg:CC CC_REGNUM))]
4001   "TARGET_Z10
4002    && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4003   "rnsbg\t%0,%3,%2,63,0"
4004   [(set_attr "op_type" "RIE")])
4005
4006 (define_insn "*insv_rnsbg_srl"
4007   [(set (zero_extract:DI
4008           (match_operand:DI 0 "nonimmediate_operand" "+d")
4009           (match_operand 1 "const_int_operand" "")
4010           (match_operand 2 "const_int_operand" ""))
4011         (and:DI
4012           (lshiftrt:DI
4013             (match_dup 0)
4014             (match_operand 3 "const_int_operand" ""))
4015           (match_operand:DI 4 "nonimmediate_operand" "d")))
4016    (clobber (reg:CC CC_REGNUM))]
4017   "TARGET_Z10
4018    && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4019   "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4020   [(set_attr "op_type" "RIE")])
4021
4022 (define_insn "*insv<mode>_mem_reg"
4023   [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4024                         (match_operand 1 "const_int_operand" "n,n")
4025                         (const_int 0))
4026         (match_operand:W 2 "register_operand" "d,d"))]
4027   "INTVAL (operands[1]) > 0
4028    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4029    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4030 {
4031     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4032
4033     operands[1] = GEN_INT ((1ul << size) - 1);
4034     return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4035                                     : "stcmy\t%2,%1,%S0";
4036 }
4037   [(set_attr "op_type" "RS,RSY")
4038    (set_attr "z10prop" "z10_super,z10_super")])
4039
4040 (define_insn "*insvdi_mem_reghigh"
4041   [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
4042                          (match_operand 1 "const_int_operand" "n")
4043                          (const_int 0))
4044         (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4045                      (const_int 32)))]
4046   "TARGET_ZARCH
4047    && INTVAL (operands[1]) > 0
4048    && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4049    && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4050 {
4051     int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4052
4053     operands[1] = GEN_INT ((1ul << size) - 1);
4054     return "stcmh\t%2,%1,%S0";
4055 }
4056 [(set_attr "op_type" "RSY")
4057  (set_attr "z10prop" "z10_super")])
4058
4059 (define_insn "*insvdi_reg_imm"
4060   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4061                          (const_int 16)
4062                          (match_operand 1 "const_int_operand" "n"))
4063         (match_operand:DI 2 "const_int_operand" "n"))]
4064   "TARGET_ZARCH
4065    && INTVAL (operands[1]) >= 0
4066    && INTVAL (operands[1]) < BITS_PER_WORD
4067    && INTVAL (operands[1]) % 16 == 0"
4068 {
4069   switch (BITS_PER_WORD - INTVAL (operands[1]))
4070     {
4071       case 64: return "iihh\t%0,%x2"; break;
4072       case 48: return "iihl\t%0,%x2"; break;
4073       case 32: return "iilh\t%0,%x2"; break;
4074       case 16: return "iill\t%0,%x2"; break;
4075       default: gcc_unreachable();
4076     }
4077 }
4078   [(set_attr "op_type" "RI")
4079    (set_attr "z10prop" "z10_super_E1")])
4080
4081 ; Update the left-most 32 bit of a DI.
4082 (define_insn "*insv_h_di_reg_extimm"
4083   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4084                          (const_int 32)
4085                          (const_int 0))
4086         (match_operand:DI 1 "const_int_operand" "n"))]
4087   "TARGET_EXTIMM"
4088   "iihf\t%0,%o1"
4089   [(set_attr "op_type" "RIL")
4090    (set_attr "z10prop" "z10_fwd_E1")])
4091
4092 ; Update the right-most 32 bit of a DI.
4093 (define_insn "*insv_l_di_reg_extimm"
4094   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4095                          (const_int 32)
4096                          (const_int 32))
4097         (match_operand:DI 1 "const_int_operand" "n"))]
4098   "TARGET_EXTIMM"
4099   "iilf\t%0,%o1"
4100   [(set_attr "op_type" "RIL")
4101    (set_attr "z10prop" "z10_fwd_A1")])
4102
4103 ;
4104 ; extendsidi2 instruction pattern(s).
4105 ;
4106
4107 (define_expand "extendsidi2"
4108   [(set (match_operand:DI 0 "register_operand" "")
4109         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4110   ""
4111 {
4112   if (!TARGET_ZARCH)
4113     {
4114       emit_clobber (operands[0]);
4115       emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4116       emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4117       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4118       DONE;
4119     }
4120 })
4121
4122 (define_insn "*extendsidi2"
4123   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4124         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4125   "TARGET_ZARCH"
4126   "@
4127    lgfr\t%0,%1
4128    lgf\t%0,%1
4129    lgfrl\t%0,%1"
4130   [(set_attr "op_type"      "RRE,RXY,RIL")
4131    (set_attr "type"         "*,*,larl")
4132    (set_attr "cpu_facility" "*,*,z10")
4133    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4134
4135 ;
4136 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4137 ;
4138
4139 (define_expand "extend<HQI:mode><DSI:mode>2"
4140   [(set (match_operand:DSI 0 "register_operand" "")
4141         (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4142   ""
4143 {
4144   if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4145     {
4146       rtx tmp = gen_reg_rtx (SImode);
4147       emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4148       emit_insn (gen_extendsidi2 (operands[0], tmp));
4149       DONE;
4150     }
4151   else if (!TARGET_EXTIMM)
4152     {
4153       rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4154
4155       operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4156       emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4157       emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4158       DONE;
4159     }
4160 })
4161
4162 ;
4163 ; extendhidi2 instruction pattern(s).
4164 ;
4165
4166 (define_insn "*extendhidi2_extimm"
4167   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4168         (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
4169   "TARGET_ZARCH && TARGET_EXTIMM"
4170   "@
4171    lghr\t%0,%1
4172    lgh\t%0,%1
4173    lghrl\t%0,%1"
4174   [(set_attr "op_type"      "RRE,RXY,RIL")
4175    (set_attr "type"         "*,*,larl")
4176    (set_attr "cpu_facility" "extimm,extimm,z10")
4177    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4178
4179 (define_insn "*extendhidi2"
4180   [(set (match_operand:DI 0 "register_operand" "=d")
4181         (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
4182   "TARGET_ZARCH"
4183   "lgh\t%0,%1"
4184   [(set_attr "op_type" "RXY")
4185    (set_attr "z10prop" "z10_super_E1")])
4186
4187 ;
4188 ; extendhisi2 instruction pattern(s).
4189 ;
4190
4191 (define_insn "*extendhisi2_extimm"
4192   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4193         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4194   "TARGET_EXTIMM"
4195   "@
4196    lhr\t%0,%1
4197    lh\t%0,%1
4198    lhy\t%0,%1
4199    lhrl\t%0,%1"
4200   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
4201    (set_attr "type"         "*,*,*,larl")
4202    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4203    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4204
4205 (define_insn "*extendhisi2"
4206   [(set (match_operand:SI 0 "register_operand" "=d,d")
4207         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4208   "!TARGET_EXTIMM"
4209   "@
4210    lh\t%0,%1
4211    lhy\t%0,%1"
4212   [(set_attr "op_type" "RX,RXY")
4213    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4214
4215 ;
4216 ; extendqi(si|di)2 instruction pattern(s).
4217 ;
4218
4219 ; lbr, lgbr, lb, lgb
4220 (define_insn "*extendqi<mode>2_extimm"
4221   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4222         (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
4223   "TARGET_EXTIMM"
4224   "@
4225    l<g>br\t%0,%1
4226    l<g>b\t%0,%1"
4227   [(set_attr "op_type" "RRE,RXY")
4228    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4229
4230 ; lb, lgb
4231 (define_insn "*extendqi<mode>2"
4232   [(set (match_operand:GPR 0 "register_operand" "=d")
4233         (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
4234   "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4235   "l<g>b\t%0,%1"
4236   [(set_attr "op_type" "RXY")
4237    (set_attr "z10prop" "z10_super_E1")])
4238
4239 (define_insn_and_split "*extendqi<mode>2_short_displ"
4240   [(set (match_operand:GPR 0 "register_operand" "=d")
4241         (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4242    (clobber (reg:CC CC_REGNUM))]
4243   "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4244   "#"
4245   "&& reload_completed"
4246   [(parallel
4247     [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4248      (clobber (reg:CC CC_REGNUM))])
4249    (parallel
4250     [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4251      (clobber (reg:CC CC_REGNUM))])]
4252 {
4253   operands[1] = adjust_address (operands[1], BLKmode, 0);
4254   set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4255   operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4256 })
4257
4258 ;
4259 ; zero_extendsidi2 instruction pattern(s).
4260 ;
4261
4262 (define_expand "zero_extendsidi2"
4263   [(set (match_operand:DI 0 "register_operand" "")
4264         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4265   ""
4266 {
4267   if (!TARGET_ZARCH)
4268     {
4269       emit_clobber (operands[0]);
4270       emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4271       emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4272       DONE;
4273     }
4274 })
4275
4276 (define_insn "*zero_extendsidi2"
4277   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4278         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
4279   "TARGET_ZARCH"
4280   "@
4281    llgfr\t%0,%1
4282    llgf\t%0,%1
4283    llgfrl\t%0,%1"
4284   [(set_attr "op_type"      "RRE,RXY,RIL")
4285    (set_attr "type"         "*,*,larl")
4286    (set_attr "cpu_facility" "*,*,z10")
4287    (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4288
4289 ;
4290 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4291 ;
4292
4293 (define_insn "*llgt_sidi"
4294   [(set (match_operand:DI 0 "register_operand" "=d")
4295         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4296                 (const_int 2147483647)))]
4297   "TARGET_ZARCH"
4298   "llgt\t%0,%1"
4299   [(set_attr "op_type"  "RXE")
4300    (set_attr "z10prop" "z10_super_E1")])
4301
4302 (define_insn_and_split "*llgt_sidi_split"
4303   [(set (match_operand:DI 0 "register_operand" "=d")
4304         (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
4305                 (const_int 2147483647)))
4306    (clobber (reg:CC CC_REGNUM))]
4307   "TARGET_ZARCH"
4308   "#"
4309   "&& reload_completed"
4310   [(set (match_dup 0)
4311         (and:DI (subreg:DI (match_dup 1) 0)
4312                 (const_int 2147483647)))]
4313   "")
4314
4315 (define_insn "*llgt_sisi"
4316   [(set (match_operand:SI 0 "register_operand" "=d,d")
4317         (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
4318                 (const_int 2147483647)))]
4319   "TARGET_ZARCH"
4320   "@
4321    llgtr\t%0,%1
4322    llgt\t%0,%1"
4323   [(set_attr "op_type"  "RRE,RXE")
4324    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4325
4326 (define_insn "*llgt_didi"
4327   [(set (match_operand:DI 0 "register_operand" "=d,d")
4328         (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4329                 (const_int 2147483647)))]
4330   "TARGET_ZARCH"
4331   "@
4332    llgtr\t%0,%1
4333    llgt\t%0,%N1"
4334   [(set_attr "op_type"  "RRE,RXE")
4335    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4336
4337 (define_split
4338   [(set (match_operand:DSI 0 "register_operand" "")
4339         (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4340                  (const_int 2147483647)))
4341    (clobber (reg:CC CC_REGNUM))]
4342   "TARGET_ZARCH && reload_completed"
4343   [(set (match_dup 0)
4344         (and:DSI (match_dup 1)
4345                  (const_int 2147483647)))]
4346   "")
4347
4348 ;
4349 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4350 ;
4351
4352 (define_expand "zero_extend<mode>di2"
4353   [(set (match_operand:DI 0 "register_operand" "")
4354         (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4355   ""
4356 {
4357   if (!TARGET_ZARCH)
4358     {
4359       rtx tmp = gen_reg_rtx (SImode);
4360       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4361       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4362       DONE;
4363     }
4364   else if (!TARGET_EXTIMM)
4365     {
4366       rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4367       operands[1] = gen_lowpart (DImode, operands[1]);
4368       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4369       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4370       DONE;
4371     }
4372 })
4373
4374 (define_expand "zero_extend<mode>si2"
4375   [(set (match_operand:SI 0 "register_operand" "")
4376         (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4377   ""
4378 {
4379   if (!TARGET_EXTIMM)
4380     {
4381       operands[1] = gen_lowpart (SImode, operands[1]);
4382       emit_insn (gen_andsi3 (operands[0], operands[1],
4383                              GEN_INT ((1 << <HQI:bitsize>) - 1)));
4384       DONE;
4385     }
4386 })
4387
4388 ; llhrl, llghrl
4389 (define_insn "*zero_extendhi<mode>2_z10"
4390   [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4391         (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4392   "TARGET_Z10"
4393   "@
4394    ll<g>hr\t%0,%1
4395    ll<g>h\t%0,%1
4396    ll<g>hrl\t%0,%1"
4397   [(set_attr "op_type"      "RXY,RRE,RIL")
4398    (set_attr "type"         "*,*,larl")
4399    (set_attr "cpu_facility" "*,*,z10")
4400    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4401
4402 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4403 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4404   [(set (match_operand:GPR 0 "register_operand" "=d,d")
4405         (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4406   "TARGET_EXTIMM"
4407   "@
4408    ll<g><hc>r\t%0,%1
4409    ll<g><hc>\t%0,%1"
4410   [(set_attr "op_type" "RRE,RXY")
4411    (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4412
4413 ; llgh, llgc
4414 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4415   [(set (match_operand:GPR 0 "register_operand" "=d")
4416         (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4417   "TARGET_ZARCH && !TARGET_EXTIMM"
4418   "llg<hc>\t%0,%1"
4419   [(set_attr "op_type" "RXY")
4420    (set_attr "z10prop" "z10_fwd_A3")])
4421
4422 (define_insn_and_split "*zero_extendhisi2_31"
4423   [(set (match_operand:SI 0 "register_operand" "=&d")
4424         (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4425    (clobber (reg:CC CC_REGNUM))]
4426   "!TARGET_ZARCH"
4427   "#"
4428   "&& reload_completed"
4429   [(set (match_dup 0) (const_int 0))
4430    (parallel
4431     [(set (strict_low_part (match_dup 2)) (match_dup 1))
4432      (clobber (reg:CC CC_REGNUM))])]
4433   "operands[2] = gen_lowpart (HImode, operands[0]);")
4434
4435 (define_insn_and_split "*zero_extendqisi2_31"
4436   [(set (match_operand:SI 0 "register_operand" "=&d")
4437         (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4438   "!TARGET_ZARCH"
4439   "#"
4440   "&& reload_completed"
4441   [(set (match_dup 0) (const_int 0))
4442    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4443   "operands[2] = gen_lowpart (QImode, operands[0]);")
4444
4445 ;
4446 ; zero_extendqihi2 instruction pattern(s).
4447 ;
4448
4449 (define_expand "zero_extendqihi2"
4450   [(set (match_operand:HI 0 "register_operand" "")
4451         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4452   "TARGET_ZARCH && !TARGET_EXTIMM"
4453 {
4454   operands[1] = gen_lowpart (HImode, operands[1]);
4455   emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4456   DONE;
4457 })
4458
4459 (define_insn "*zero_extendqihi2_64"
4460   [(set (match_operand:HI 0 "register_operand" "=d")
4461         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4462   "TARGET_ZARCH && !TARGET_EXTIMM"
4463   "llgc\t%0,%1"
4464   [(set_attr "op_type" "RXY")
4465    (set_attr "z10prop" "z10_fwd_A3")])
4466
4467 (define_insn_and_split "*zero_extendqihi2_31"
4468   [(set (match_operand:HI 0 "register_operand" "=&d")
4469         (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4470   "!TARGET_ZARCH"
4471   "#"
4472   "&& reload_completed"
4473   [(set (match_dup 0) (const_int 0))
4474    (set (strict_low_part (match_dup 2)) (match_dup 1))]
4475   "operands[2] = gen_lowpart (QImode, operands[0]);")
4476
4477 ;
4478 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4479 ;
4480
4481 (define_expand "fixuns_truncdddi2"
4482   [(parallel
4483     [(set (match_operand:DI 0 "register_operand" "")
4484           (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4485      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4486      (clobber (reg:CC CC_REGNUM))])]
4487
4488   "TARGET_HARD_DFP"
4489 {
4490   if (!TARGET_Z196)
4491     {
4492       rtx_code_label *label1 = gen_label_rtx ();
4493       rtx_code_label *label2 = gen_label_rtx ();
4494       rtx temp = gen_reg_rtx (TDmode);
4495       REAL_VALUE_TYPE cmp, sub;
4496
4497       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4498       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4499
4500       /* 2^63 can't be represented as 64bit DFP number with full precision.  The
4501          solution is doing the check and the subtraction in TD mode and using a
4502          TD -> DI convert afterwards.  */
4503       emit_insn (gen_extendddtd2 (temp, operands[1]));
4504       temp = force_reg (TDmode, temp);
4505       emit_cmp_and_jump_insns (temp,
4506             const_double_from_real_value (cmp, TDmode),
4507             LT, NULL_RTX, VOIDmode, 0, label1);
4508       emit_insn (gen_subtd3 (temp, temp,
4509             const_double_from_real_value (sub, TDmode)));
4510       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4511       emit_jump (label2);
4512
4513       emit_label (label1);
4514       emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4515       emit_label (label2);
4516       DONE;
4517     }
4518 })
4519
4520 (define_expand "fixuns_trunctddi2"
4521   [(parallel
4522     [(set (match_operand:DI 0 "register_operand" "")
4523           (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4524      (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4525      (clobber (reg:CC CC_REGNUM))])]
4526
4527   "TARGET_HARD_DFP"
4528 {
4529   if (!TARGET_Z196)
4530     {
4531       rtx_code_label *label1 = gen_label_rtx ();
4532       rtx_code_label *label2 = gen_label_rtx ();
4533       rtx temp = gen_reg_rtx (TDmode);
4534       REAL_VALUE_TYPE cmp, sub;
4535
4536       operands[1] = force_reg (TDmode, operands[1]);
4537       decimal_real_from_string (&cmp, "9223372036854775808.0");  /* 2^63 */
4538       decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4539
4540       emit_cmp_and_jump_insns (operands[1],
4541             const_double_from_real_value (cmp, TDmode),
4542             LT, NULL_RTX, VOIDmode, 0, label1);
4543       emit_insn (gen_subtd3 (temp, operands[1],
4544             const_double_from_real_value (sub, TDmode)));
4545       emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4546       emit_jump (label2);
4547
4548       emit_label (label1);
4549       emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4550       emit_label (label2);
4551       DONE;
4552     }
4553 })
4554
4555 ;
4556 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4557 ; instruction pattern(s).
4558 ;
4559
4560 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4561   [(parallel
4562     [(set (match_operand:GPR 0 "register_operand" "")
4563           (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4564      (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4565      (clobber (reg:CC CC_REGNUM))])]
4566   "TARGET_HARD_FLOAT"
4567 {
4568   if (!TARGET_Z196)
4569     {
4570       rtx_code_label *label1 = gen_label_rtx ();
4571       rtx_code_label *label2 = gen_label_rtx ();
4572       rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4573       REAL_VALUE_TYPE cmp, sub;
4574
4575       operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4576       real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4577       real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4578
4579       emit_cmp_and_jump_insns (operands[1],
4580             const_double_from_real_value (cmp, <BFP:MODE>mode),
4581             LT, NULL_RTX, VOIDmode, 0, label1);
4582       emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4583             const_double_from_real_value (sub, <BFP:MODE>mode)));
4584       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4585             GEN_INT (7)));
4586       emit_jump (label2);
4587
4588       emit_label (label1);
4589       emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4590             operands[1], GEN_INT (5)));
4591       emit_label (label2);
4592       DONE;
4593     }
4594 })
4595
4596 ; fixuns_trunc(td|dd)si2 expander
4597 (define_expand "fixuns_trunc<mode>si2"
4598   [(parallel
4599     [(set (match_operand:SI 0 "register_operand" "")
4600           (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4601      (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4602      (clobber (reg:CC CC_REGNUM))])]
4603   "TARGET_Z196 && TARGET_HARD_DFP"
4604   "")
4605
4606 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4607
4608 (define_insn "*fixuns_truncdfdi2_z13"
4609   [(set (match_operand:DI                  0 "register_operand" "=d,v")
4610         (unsigned_fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4611    (unspec:DI [(match_operand:DI           2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4612    (clobber (reg:CC CC_REGNUM))]
4613    "TARGET_Z13 && TARGET_HARD_FLOAT"
4614    "@
4615     clgdbr\t%0,%h2,%1,0
4616     wclgdb\t%v0,%v1,0,%h2"
4617    [(set_attr "op_type" "RRF,VRR")
4618     (set_attr "type"    "ftoi")])
4619
4620 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4621 ;         clfdtr, clfxtr,         clgdtr, clgxtr
4622 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4623   [(set (match_operand:GPR                  0 "register_operand" "=d")
4624         (unsigned_fix:GPR (match_operand:FP 1 "register_operand"  "f")))
4625    (unspec:GPR [(match_operand:GPR          2 "immediate_operand" "K")] UNSPEC_ROUND)
4626    (clobber (reg:CC CC_REGNUM))]
4627    "TARGET_Z196 && TARGET_HARD_FLOAT
4628     && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4629    "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4630    [(set_attr "op_type" "RRF")
4631     (set_attr "type"    "ftoi")])
4632
4633 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4634   [(set (match_operand:GPR 0 "register_operand" "")
4635         (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4636   "TARGET_HARD_FLOAT"
4637 {
4638   emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4639              GEN_INT (5)));
4640   DONE;
4641 })
4642
4643 (define_insn "*fix_truncdfdi2_bfp_z13"
4644   [(set (match_operand:DI         0 "register_operand" "=d,v")
4645         (fix:DI (match_operand:DF 1 "register_operand"  "f,v")))
4646    (unspec:DI [(match_operand:DI  2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4647    (clobber (reg:CC CC_REGNUM))]
4648   "TARGET_Z13 && TARGET_HARD_FLOAT"
4649   "@
4650    cgdbr\t%0,%h2,%1
4651    wcgdb\t%v0,%v1,0,%h2"
4652   [(set_attr "op_type" "RRE,VRR")
4653    (set_attr "type"    "ftoi")])
4654
4655 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4656 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4657   [(set (match_operand:GPR          0 "register_operand" "=d")
4658         (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4659    (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4660    (clobber (reg:CC CC_REGNUM))]
4661   "TARGET_HARD_FLOAT
4662     && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4663   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4664   [(set_attr "op_type" "RRE")
4665    (set_attr "type"    "ftoi")])
4666
4667 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4668   [(parallel
4669     [(set (match_operand:GPR          0 "register_operand" "=d")
4670           (fix:GPR (match_operand:BFP 1 "register_operand"  "f")))
4671      (unspec:GPR [(match_operand:GPR  2 "immediate_operand" "K")] UNSPEC_ROUND)
4672      (clobber (reg:CC CC_REGNUM))])]
4673   "TARGET_HARD_FLOAT")
4674 ;
4675 ; fix_trunc(td|dd)di2 instruction pattern(s).
4676 ;
4677
4678 (define_expand "fix_trunc<mode>di2"
4679   [(set (match_operand:DI 0 "register_operand" "")
4680         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4681   "TARGET_ZARCH && TARGET_HARD_DFP"
4682 {
4683   operands[1] = force_reg (<MODE>mode, operands[1]);
4684   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4685       GEN_INT (9)));
4686   DONE;
4687 })
4688
4689 ; cgxtr, cgdtr
4690 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4691   [(set (match_operand:DI 0 "register_operand" "=d")
4692         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4693    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4694    (clobber (reg:CC CC_REGNUM))]
4695   "TARGET_ZARCH && TARGET_HARD_DFP"
4696   "cg<DFP:xde>tr\t%0,%h2,%1"
4697   [(set_attr "op_type" "RRF")
4698    (set_attr "type"    "ftoidfp")])
4699
4700
4701 ;
4702 ; fix_trunctf(si|di)2 instruction pattern(s).
4703 ;
4704
4705 (define_expand "fix_trunctf<mode>2"
4706   [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4707                    (fix:GPR (match_operand:TF 1 "register_operand" "")))
4708               (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4709               (clobber (reg:CC CC_REGNUM))])]
4710   "TARGET_HARD_FLOAT"
4711   "")
4712
4713
4714 ;
4715 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4716 ;
4717
4718 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4719 (define_insn "floatdi<mode>2"
4720   [(set (match_operand:FP           0 "register_operand" "=f,v")
4721         (float:FP (match_operand:DI 1 "register_operand"  "d,v")))]
4722   "TARGET_ZARCH && TARGET_HARD_FLOAT"
4723   "@
4724    c<xde>g<bt>r\t%0,%1
4725    wcdgb\t%v0,%v1,0,0"
4726   [(set_attr "op_type"      "RRE,VRR")
4727    (set_attr "type"         "itof<mode>" )
4728    (set_attr "cpu_facility" "*,vec")
4729    (set_attr "enabled"      "*,<DFDI>")])
4730
4731 ; cxfbr, cdfbr, cefbr
4732 (define_insn "floatsi<mode>2"
4733   [(set (match_operand:BFP 0 "register_operand" "=f")
4734         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4735   "TARGET_HARD_FLOAT"
4736   "c<xde>fbr\t%0,%1"
4737   [(set_attr "op_type" "RRE")
4738    (set_attr "type"   "itof<mode>" )])
4739
4740 ; cxftr, cdftr
4741 (define_insn "floatsi<mode>2"
4742   [(set (match_operand:DFP 0 "register_operand" "=f")
4743         (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4744   "TARGET_Z196 && TARGET_HARD_FLOAT"
4745   "c<xde>ftr\t%0,0,%1,0"
4746   [(set_attr "op_type" "RRE")
4747    (set_attr "type"   "itof<mode>" )])
4748
4749 ;
4750 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4751 ;
4752
4753 (define_insn "*floatunsdidf2_z13"
4754   [(set (match_operand:DF                    0 "register_operand" "=f,v")
4755         (unsigned_float:DF (match_operand:DI 1 "register_operand"  "d,v")))]
4756   "TARGET_Z13 && TARGET_HARD_FLOAT"
4757   "@
4758    cdlgbr\t%0,0,%1,0
4759    wcdlgb\t%v0,%v1,0,0"
4760   [(set_attr "op_type" "RRE,VRR")
4761    (set_attr "type"    "itofdf")])
4762
4763 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4764 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4765 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4766   [(set (match_operand:FP                     0 "register_operand" "=f")
4767         (unsigned_float:FP (match_operand:GPR 1 "register_operand"  "d")))]
4768   "TARGET_Z196 && TARGET_HARD_FLOAT
4769    && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4770   "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4771   [(set_attr "op_type" "RRE")
4772    (set_attr "type"    "itof<FP:mode>")])
4773
4774 (define_expand "floatuns<GPR:mode><FP:mode>2"
4775   [(set (match_operand:FP                     0 "register_operand" "")
4776         (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4777   "TARGET_Z196 && TARGET_HARD_FLOAT")
4778
4779 ;
4780 ; truncdfsf2 instruction pattern(s).
4781 ;
4782
4783 (define_insn "truncdfsf2"
4784   [(set (match_operand:SF                    0 "register_operand" "=f,v")
4785         (float_truncate:SF (match_operand:DF 1 "register_operand"  "f,v")))]
4786   "TARGET_HARD_FLOAT"
4787   "@
4788    ledbr\t%0,%1
4789    wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4790                        ; According to BFP rounding mode
4791   [(set_attr "op_type"      "RRE,VRR")
4792    (set_attr "type"         "ftruncdf")
4793    (set_attr "cpu_facility" "*,vec")])
4794
4795 ;
4796 ; trunctf(df|sf)2 instruction pattern(s).
4797 ;
4798
4799 ; ldxbr, lexbr
4800 (define_insn "trunctf<mode>2"
4801   [(set (match_operand:DSF 0 "register_operand" "=f")
4802         (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4803    (clobber (match_scratch:TF 2 "=f"))]
4804   "TARGET_HARD_FLOAT"
4805   "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4806   [(set_attr "length" "6")
4807    (set_attr "type"   "ftrunctf")])
4808
4809 ;
4810 ; trunctddd2 and truncddsd2 instruction pattern(s).
4811 ;
4812
4813 (define_insn "trunctddd2"
4814   [(set (match_operand:DD 0 "register_operand" "=f")
4815         (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4816    (clobber (match_scratch:TD 2 "=f"))]
4817   "TARGET_HARD_DFP"
4818   "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4819   [(set_attr "length"  "6")
4820    (set_attr "type"    "ftruncdd")])
4821
4822 (define_insn "truncddsd2"
4823   [(set (match_operand:SD 0 "register_operand" "=f")
4824         (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4825   "TARGET_HARD_DFP"
4826   "ledtr\t%0,0,%1,0"
4827   [(set_attr "op_type" "RRF")
4828    (set_attr "type"    "ftruncsd")])
4829
4830 (define_expand "trunctdsd2"
4831   [(parallel
4832     [(set (match_dup 3)
4833           (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4834      (clobber (match_scratch:TD 2 ""))])
4835    (set (match_operand:SD 0 "register_operand" "")
4836         (float_truncate:SD (match_dup 3)))]
4837   "TARGET_HARD_DFP"
4838 {
4839   operands[3] = gen_reg_rtx (DDmode);
4840 })
4841
4842 ;
4843 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4844 ;
4845
4846 (define_insn "*extendsfdf2_z13"
4847   [(set (match_operand:DF                  0 "register_operand"     "=f,f,v")
4848         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R,v")))]
4849   "TARGET_Z13 && TARGET_HARD_FLOAT"
4850   "@
4851    ldebr\t%0,%1
4852    ldeb\t%0,%1
4853    wldeb\t%v0,%v1"
4854   [(set_attr "op_type" "RRE,RXE,VRR")
4855    (set_attr "type"    "fsimpdf, floaddf,fsimpdf")])
4856
4857 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4858 (define_insn "*extend<DSF:mode><BFP:mode>2"
4859   [(set (match_operand:BFP                   0 "register_operand"     "=f,f")
4860         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
4861   "TARGET_HARD_FLOAT
4862    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4863    && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4864   "@
4865    l<BFP:xde><DSF:xde>br\t%0,%1
4866    l<BFP:xde><DSF:xde>b\t%0,%1"
4867   [(set_attr "op_type" "RRE,RXE")
4868    (set_attr "type"    "fsimp<BFP:mode>, fload<BFP:mode>")])
4869
4870 (define_expand "extend<DSF:mode><BFP:mode>2"
4871   [(set (match_operand:BFP                   0 "register_operand"     "")
4872         (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4873   "TARGET_HARD_FLOAT
4874    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4875
4876 ;
4877 ; extendddtd2 and extendsddd2 instruction pattern(s).
4878 ;
4879
4880 (define_insn "extendddtd2"
4881   [(set (match_operand:TD 0 "register_operand" "=f")
4882         (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4883   "TARGET_HARD_DFP"
4884   "lxdtr\t%0,%1,0"
4885   [(set_attr "op_type" "RRF")
4886    (set_attr "type"    "fsimptf")])
4887
4888 (define_insn "extendsddd2"
4889   [(set (match_operand:DD 0 "register_operand" "=f")
4890         (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4891   "TARGET_HARD_DFP"
4892   "ldetr\t%0,%1,0"
4893   [(set_attr "op_type" "RRF")
4894    (set_attr "type"    "fsimptf")])
4895
4896 (define_expand "extendsdtd2"
4897   [(set (match_dup 2)
4898         (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4899    (set (match_operand:TD 0 "register_operand" "")
4900         (float_extend:TD (match_dup 2)))]
4901   "TARGET_HARD_DFP"
4902 {
4903   operands[2] = gen_reg_rtx (DDmode);
4904 })
4905
4906 ; Binary Floating Point - load fp integer
4907
4908 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4909 ; For all of them the inexact exceptions are suppressed.
4910
4911 ; fiebra, fidbra, fixbra
4912 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4913   [(set (match_operand:BFP 0 "register_operand" "=f")
4914         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4915                     FPINT))]
4916   "TARGET_Z196"
4917   "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4918   [(set_attr "op_type"   "RRF")
4919    (set_attr "type"      "fsimp<BFP:mode>")])
4920
4921 ; rint is supposed to raise an inexact exception so we can use the
4922 ; older instructions.
4923
4924 ; fiebr, fidbr, fixbr
4925 (define_insn "rint<BFP:mode>2"
4926   [(set (match_operand:BFP 0 "register_operand" "=f")
4927         (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4928                     UNSPEC_FPINT_RINT))]
4929   ""
4930   "fi<BFP:xde>br\t%0,0,%1"
4931   [(set_attr "op_type"   "RRF")
4932    (set_attr "type"      "fsimp<BFP:mode>")])
4933
4934
4935 ; Decimal Floating Point - load fp integer
4936
4937 ; fidtr, fixtr
4938 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4939   [(set (match_operand:DFP 0 "register_operand" "=f")
4940         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4941                     FPINT))]
4942   "TARGET_HARD_DFP"
4943   "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4944   [(set_attr "op_type"   "RRF")
4945    (set_attr "type"      "fsimp<DFP:mode>")])
4946
4947 ; fidtr, fixtr
4948 (define_insn "rint<DFP:mode>2"
4949   [(set (match_operand:DFP 0 "register_operand" "=f")
4950         (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4951                     UNSPEC_FPINT_RINT))]
4952   "TARGET_HARD_DFP"
4953   "fi<DFP:xde>tr\t%0,0,%1,0"
4954   [(set_attr "op_type"   "RRF")
4955    (set_attr "type"      "fsimp<DFP:mode>")])
4956
4957 ;
4958 ; Binary <-> Decimal floating point trunc patterns
4959 ;
4960
4961 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4962   [(set (reg:DFP_ALL FPR0_REGNUM)
4963         (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4964    (use (reg:SI GPR0_REGNUM))
4965    (clobber (reg:CC CC_REGNUM))
4966    (clobber (reg:SI GPR1_REGNUM))]
4967   "TARGET_HARD_DFP"
4968   "pfpo")
4969
4970 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4971   [(set (reg:BFP FPR0_REGNUM)
4972         (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4973    (use (reg:SI GPR0_REGNUM))
4974    (clobber (reg:CC CC_REGNUM))
4975    (clobber (reg:SI GPR1_REGNUM))]
4976   "TARGET_HARD_DFP"
4977   "pfpo")
4978
4979 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4980   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4981    (set (reg:SI GPR0_REGNUM) (match_dup 2))
4982    (parallel
4983     [(set (reg:DFP_ALL FPR0_REGNUM)
4984           (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4985      (use (reg:SI GPR0_REGNUM))
4986      (clobber (reg:CC CC_REGNUM))
4987      (clobber (reg:SI GPR1_REGNUM))])
4988    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4989         (reg:DFP_ALL FPR0_REGNUM))]
4990   "TARGET_HARD_DFP
4991    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4992 {
4993   HOST_WIDE_INT flags;
4994
4995   flags = (PFPO_CONVERT |
4996            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4997            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4998
4999   operands[2] = GEN_INT (flags);
5000 })
5001
5002 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5003   [(set (reg:DFP_ALL FPR4_REGNUM)
5004         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5005    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5006    (parallel
5007     [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5008      (use (reg:SI GPR0_REGNUM))
5009      (clobber (reg:CC CC_REGNUM))
5010      (clobber (reg:SI GPR1_REGNUM))])
5011    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5012   "TARGET_HARD_DFP
5013    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5014 {
5015   HOST_WIDE_INT flags;
5016
5017   flags = (PFPO_CONVERT |
5018            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5019            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5020
5021   operands[2] = GEN_INT (flags);
5022 })
5023
5024 ;
5025 ; Binary <-> Decimal floating point extend patterns
5026 ;
5027
5028 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5029   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5030    (use (reg:SI GPR0_REGNUM))
5031    (clobber (reg:CC CC_REGNUM))
5032    (clobber (reg:SI GPR1_REGNUM))]
5033   "TARGET_HARD_DFP"
5034   "pfpo")
5035
5036 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5037   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5038    (use (reg:SI GPR0_REGNUM))
5039    (clobber (reg:CC CC_REGNUM))
5040    (clobber (reg:SI GPR1_REGNUM))]
5041   "TARGET_HARD_DFP"
5042   "pfpo")
5043
5044 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5045   [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5046    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5047    (parallel
5048     [(set (reg:DFP_ALL FPR0_REGNUM)
5049           (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5050      (use (reg:SI GPR0_REGNUM))
5051      (clobber (reg:CC CC_REGNUM))
5052      (clobber (reg:SI GPR1_REGNUM))])
5053    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5054         (reg:DFP_ALL FPR0_REGNUM))]
5055   "TARGET_HARD_DFP
5056    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5057 {
5058   HOST_WIDE_INT flags;
5059
5060   flags = (PFPO_CONVERT |
5061            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5062            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5063
5064   operands[2] = GEN_INT (flags);
5065 })
5066
5067 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5068   [(set (reg:DFP_ALL FPR4_REGNUM)
5069         (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5070    (set (reg:SI GPR0_REGNUM) (match_dup 2))
5071    (parallel
5072     [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5073      (use (reg:SI GPR0_REGNUM))
5074      (clobber (reg:CC CC_REGNUM))
5075      (clobber (reg:SI GPR1_REGNUM))])
5076    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5077   "TARGET_HARD_DFP
5078    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5079 {
5080   HOST_WIDE_INT flags;
5081
5082   flags = (PFPO_CONVERT |
5083            PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5084            PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5085
5086   operands[2] = GEN_INT (flags);
5087 })
5088
5089
5090 ;;
5091 ;; ARITHMETIC OPERATIONS
5092 ;;
5093 ;  arithmetic operations set the ConditionCode,
5094 ;  because of unpredictable Bits in Register for Halfword and Byte
5095 ;  the ConditionCode can be set wrong in operations for Halfword and Byte
5096
5097 ;;
5098 ;;- Add instructions.
5099 ;;
5100
5101 ;
5102 ; addti3 instruction pattern(s).
5103 ;
5104
5105 (define_expand "addti3"
5106   [(parallel
5107     [(set (match_operand:TI          0 "register_operand"     "")
5108           (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5109                    (match_operand:TI 2 "general_operand"      "") ) )
5110      (clobber (reg:CC CC_REGNUM))])]
5111   "TARGET_ZARCH"
5112 {
5113   /* For z13 we have vaq which doesn't set CC.  */
5114   if (TARGET_VX)
5115     {
5116       emit_insn (gen_rtx_SET (operands[0],
5117                               gen_rtx_PLUS (TImode,
5118                                             copy_to_mode_reg (TImode, operands[1]),
5119                                             copy_to_mode_reg (TImode, operands[2]))));
5120       DONE;
5121     }
5122 })
5123
5124 (define_insn_and_split "*addti3"
5125   [(set (match_operand:TI          0 "register_operand"    "=&d")
5126         (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5127                  (match_operand:TI 2 "general_operand"      "do") ) )
5128    (clobber (reg:CC CC_REGNUM))]
5129   "TARGET_ZARCH"
5130   "#"
5131   "&& reload_completed"
5132   [(parallel
5133     [(set (reg:CCL1 CC_REGNUM)
5134           (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5135                         (match_dup 7)))
5136      (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5137    (parallel
5138     [(set (match_dup 3) (plus:DI
5139                           (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5140                                    (match_dup 4)) (match_dup 5)))
5141      (clobber (reg:CC CC_REGNUM))])]
5142   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5143    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5144    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5145    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5146    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5147    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5148   [(set_attr "op_type"  "*")
5149    (set_attr "cpu_facility" "*")])
5150
5151 ;
5152 ; adddi3 instruction pattern(s).
5153 ;
5154
5155 (define_expand "adddi3"
5156   [(parallel
5157     [(set (match_operand:DI 0 "nonimmediate_operand" "")
5158           (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5159                    (match_operand:DI 2 "general_operand" "")))
5160      (clobber (reg:CC CC_REGNUM))])]
5161   ""
5162   "")
5163
5164 (define_insn "*adddi3_sign"
5165   [(set (match_operand:DI 0 "register_operand" "=d,d")
5166         (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5167                  (match_operand:DI 1 "register_operand" "0,0")))
5168    (clobber (reg:CC CC_REGNUM))]
5169   "TARGET_ZARCH"
5170   "@
5171    agfr\t%0,%2
5172    agf\t%0,%2"
5173   [(set_attr "op_type"  "RRE,RXY")
5174    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5175
5176 (define_insn "*adddi3_zero_cc"
5177   [(set (reg CC_REGNUM)
5178         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5179                           (match_operand:DI 1 "register_operand" "0,0"))
5180                  (const_int 0)))
5181    (set (match_operand:DI 0 "register_operand" "=d,d")
5182         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5183   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5184   "@
5185    algfr\t%0,%2
5186    algf\t%0,%2"
5187   [(set_attr "op_type"  "RRE,RXY")
5188    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5189
5190 (define_insn "*adddi3_zero_cconly"
5191   [(set (reg CC_REGNUM)
5192         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5193                           (match_operand:DI 1 "register_operand" "0,0"))
5194                  (const_int 0)))
5195    (clobber (match_scratch:DI 0 "=d,d"))]
5196   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5197   "@
5198    algfr\t%0,%2
5199    algf\t%0,%2"
5200   [(set_attr "op_type"  "RRE,RXY")
5201    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5202
5203 (define_insn "*adddi3_zero"
5204   [(set (match_operand:DI 0 "register_operand" "=d,d")
5205         (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5206                  (match_operand:DI 1 "register_operand" "0,0")))
5207    (clobber (reg:CC CC_REGNUM))]
5208   "TARGET_ZARCH"
5209   "@
5210    algfr\t%0,%2
5211    algf\t%0,%2"
5212   [(set_attr "op_type"  "RRE,RXY")
5213    (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5214
5215 (define_insn_and_split "*adddi3_31z"
5216   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5217         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5218                  (match_operand:DI 2 "general_operand" "do") ) )
5219    (clobber (reg:CC CC_REGNUM))]
5220   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5221   "#"
5222   "&& reload_completed"
5223   [(parallel
5224     [(set (reg:CCL1 CC_REGNUM)
5225           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5226                         (match_dup 7)))
5227      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5228    (parallel
5229     [(set (match_dup 3) (plus:SI
5230                           (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5231                                    (match_dup 4)) (match_dup 5)))
5232      (clobber (reg:CC CC_REGNUM))])]
5233   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5234    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5235    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5236    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5237    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5238    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5239
5240 (define_insn_and_split "*adddi3_31"
5241   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5242         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5243                  (match_operand:DI 2 "general_operand" "do") ) )
5244    (clobber (reg:CC CC_REGNUM))]
5245   "!TARGET_CPU_ZARCH"
5246   "#"
5247   "&& reload_completed"
5248   [(parallel
5249     [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5250      (clobber (reg:CC CC_REGNUM))])
5251    (parallel
5252     [(set (reg:CCL1 CC_REGNUM)
5253           (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5254                         (match_dup 7)))
5255      (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5256    (set (pc)
5257         (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5258                       (pc)
5259                       (label_ref (match_dup 9))))
5260    (parallel
5261     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5262      (clobber (reg:CC CC_REGNUM))])
5263    (match_dup 9)]
5264   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5265    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5266    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5267    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5268    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5269    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5270    operands[9] = gen_label_rtx ();")
5271
5272 ;
5273 ; addsi3 instruction pattern(s).
5274 ;
5275
5276 (define_expand "addsi3"
5277   [(parallel
5278     [(set (match_operand:SI 0 "nonimmediate_operand" "")
5279           (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5280                    (match_operand:SI 2 "general_operand" "")))
5281      (clobber (reg:CC CC_REGNUM))])]
5282   ""
5283   "")
5284
5285 (define_insn "*addsi3_sign"
5286   [(set (match_operand:SI 0 "register_operand" "=d,d")
5287         (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5288                  (match_operand:SI 1 "register_operand" "0,0")))
5289    (clobber (reg:CC CC_REGNUM))]
5290   ""
5291   "@
5292    ah\t%0,%2
5293    ahy\t%0,%2"
5294   [(set_attr "op_type"  "RX,RXY")
5295    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5296
5297 ;
5298 ; add(di|si)3 instruction pattern(s).
5299 ;
5300
5301 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5302 (define_insn "*add<mode>3"
5303   [(set (match_operand:GPR 0 "nonimmediate_operand"           "=d,d,d,d, d, d,d,d,QS")
5304         (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
5305                   (match_operand:GPR 2 "general_operand"      " d,d,K,K,Op,On,R,T, C") ) )
5306    (clobber (reg:CC CC_REGNUM))]
5307   ""
5308   "@
5309    a<g>r\t%0,%2
5310    a<g>rk\t%0,%1,%2
5311    a<g>hi\t%0,%h2
5312    a<g>hik\t%0,%1,%h2
5313    al<g>fi\t%0,%2
5314    sl<g>fi\t%0,%n2
5315    a<g>\t%0,%2
5316    a<y>\t%0,%2
5317    a<g>si\t%0,%c2"
5318   [(set_attr "op_type"  "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5319    (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
5320    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5321                         z10_super_E1,z10_super_E1,z10_super_E1")])
5322
5323 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5324 (define_insn "*add<mode>3_carry1_cc"
5325   [(set (reg CC_REGNUM)
5326         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5327                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T,C"))
5328                  (match_dup 1)))
5329    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,d")
5330         (plus:GPR (match_dup 1) (match_dup 2)))]
5331   "s390_match_ccmode (insn, CCL1mode)"
5332   "@
5333    al<g>r\t%0,%2
5334    al<g>rk\t%0,%1,%2
5335    al<g>fi\t%0,%2
5336    sl<g>fi\t%0,%n2
5337    al<g>hsik\t%0,%1,%h2
5338    al<g>\t%0,%2
5339    al<y>\t%0,%2
5340    al<g>si\t%0,%c2"
5341   [(set_attr "op_type"      "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5342    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5343    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5344                         z10_super_E1,z10_super_E1,z10_super_E1")])
5345
5346 ; alr, al, aly, algr, alg, alrk, algrk
5347 (define_insn "*add<mode>3_carry1_cconly"
5348   [(set (reg CC_REGNUM)
5349         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5350                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5351                  (match_dup 1)))
5352    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5353   "s390_match_ccmode (insn, CCL1mode)"
5354   "@
5355    al<g>r\t%0,%2
5356    al<g>rk\t%0,%1,%2
5357    al<g>\t%0,%2
5358    al<y>\t%0,%2"
5359   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5360    (set_attr "cpu_facility" "*,z196,*,*")
5361    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5362
5363 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5364 (define_insn "*add<mode>3_carry2_cc"
5365   [(set (reg CC_REGNUM)
5366         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5367                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5368                  (match_dup 2)))
5369    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5370         (plus:GPR (match_dup 1) (match_dup 2)))]
5371   "s390_match_ccmode (insn, CCL1mode)"
5372   "@
5373    al<g>r\t%0,%2
5374    al<g>rk\t%0,%1,%2
5375    al<g>fi\t%0,%2
5376    sl<g>fi\t%0,%n2
5377    al<g>hsik\t%0,%1,%h2
5378    al<g>\t%0,%2
5379    al<y>\t%0,%2
5380    al<g>si\t%0,%c2"
5381   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5382    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5383    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5384                         z10_super_E1,z10_super_E1,z10_super_E1")])
5385
5386 ; alr, al, aly, algr, alg, alrk, algrk
5387 (define_insn "*add<mode>3_carry2_cconly"
5388   [(set (reg CC_REGNUM)
5389         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5390                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5391                  (match_dup 2)))
5392    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5393   "s390_match_ccmode (insn, CCL1mode)"
5394   "@
5395    al<g>r\t%0,%2
5396    al<g>rk\t%0,%1,%2
5397    al<g>\t%0,%2
5398    al<y>\t%0,%2"
5399   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5400    (set_attr "cpu_facility" "*,z196,*,*")
5401    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5402
5403 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5404 (define_insn "*add<mode>3_cc"
5405   [(set (reg CC_REGNUM)
5406         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
5407                            (match_operand:GPR 2 "general_operand"      " d,d,Op,On,K,R,T, C"))
5408                  (const_int 0)))
5409    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d,d, d, d,d,d,d,RS")
5410         (plus:GPR (match_dup 1) (match_dup 2)))]
5411   "s390_match_ccmode (insn, CCLmode)"
5412   "@
5413    al<g>r\t%0,%2
5414    al<g>rk\t%0,%1,%2
5415    al<g>fi\t%0,%2
5416    sl<g>fi\t%0,%n2
5417    al<g>hsik\t%0,%1,%h2
5418    al<g>\t%0,%2
5419    al<y>\t%0,%2
5420    al<g>si\t%0,%c2"
5421   [(set_attr "op_type"  "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5422    (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
5423    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5424                         *,z10_super_E1,z10_super_E1,z10_super_E1")])
5425
5426 ; alr, al, aly, algr, alg, alrk, algrk
5427 (define_insn "*add<mode>3_cconly"
5428   [(set (reg CC_REGNUM)
5429         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5430                            (match_operand:GPR 2 "general_operand"       "d,d,R,T"))
5431                  (const_int 0)))
5432    (clobber (match_scratch:GPR 0                                       "=d,d,d,d"))]
5433   "s390_match_ccmode (insn, CCLmode)"
5434   "@
5435    al<g>r\t%0,%2
5436    al<g>rk\t%0,%1,%2
5437    al<g>\t%0,%2
5438    al<y>\t%0,%2"
5439   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5440    (set_attr "cpu_facility" "*,z196,*,*")
5441    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5442
5443 ; alr, al, aly, algr, alg, alrk, algrk
5444 (define_insn "*add<mode>3_cconly2"
5445   [(set (reg CC_REGNUM)
5446         (compare (match_operand:GPR 1 "nonimmediate_operand"    "%0,d,0,0")
5447                  (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5448    (clobber (match_scratch:GPR 0                                "=d,d,d,d"))]
5449   "s390_match_ccmode(insn, CCLmode)"
5450   "@
5451    al<g>r\t%0,%2
5452    al<g>rk\t%0,%1,%2
5453    al<g>\t%0,%2
5454    al<y>\t%0,%2"
5455   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5456    (set_attr "cpu_facility" "*,z196,*,*")
5457    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5458
5459 ; ahi, afi, aghi, agfi, asi, agsi
5460 (define_insn "*add<mode>3_imm_cc"
5461   [(set (reg CC_REGNUM)
5462         (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5463                            (match_operand:GPR 2 "const_int_operand"    " K, K,Os, C"))
5464                  (const_int 0)))
5465    (set (match_operand:GPR 0 "nonimmediate_operand"                    "=d, d,d,QS")
5466         (plus:GPR (match_dup 1) (match_dup 2)))]
5467   "s390_match_ccmode (insn, CCAmode)
5468    && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5469        || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5470            /* Avoid INT32_MIN on 32 bit.  */
5471            && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5472   "@
5473    a<g>hi\t%0,%h2
5474    a<g>hik\t%0,%1,%h2
5475    a<g>fi\t%0,%2
5476    a<g>si\t%0,%c2"
5477   [(set_attr "op_type"      "RI,RIE,RIL,SIY")
5478    (set_attr "cpu_facility" "*,z196,extimm,z10")
5479    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5480
5481 ;
5482 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5483 ;
5484
5485 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5486 ; FIXME: wfadb does not clobber cc
5487 (define_insn "add<mode>3"
5488   [(set (match_operand:FP 0 "register_operand"              "=f,f,f,v")
5489         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5490                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))
5491    (clobber (reg:CC CC_REGNUM))]
5492   "TARGET_HARD_FLOAT"
5493   "@
5494    a<xde>tr\t%0,%1,%2
5495    a<xde>br\t%0,%2
5496    a<xde>b\t%0,%2
5497    wfadb\t%v0,%v1,%v2"
5498   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
5499    (set_attr "type"         "fsimp<mode>")
5500    (set_attr "cpu_facility" "*,*,*,vec")
5501    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5502
5503 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5504 (define_insn "*add<mode>3_cc"
5505   [(set (reg CC_REGNUM)
5506         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5507                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5508                  (match_operand:FP 3 "const0_operand" "")))
5509    (set (match_operand:FP 0 "register_operand" "=f,f,f")
5510         (plus:FP (match_dup 1) (match_dup 2)))]
5511   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5512   "@
5513    a<xde>tr\t%0,%1,%2
5514    a<xde>br\t%0,%2
5515    a<xde>b\t%0,%2"
5516   [(set_attr "op_type"  "RRF,RRE,RXE")
5517    (set_attr "type"     "fsimp<mode>")
5518    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5519
5520 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5521 (define_insn "*add<mode>3_cconly"
5522   [(set (reg CC_REGNUM)
5523         (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5524                           (match_operand:FP 2 "general_operand"       "f,f,R"))
5525                  (match_operand:FP 3 "const0_operand" "")))
5526    (clobber (match_scratch:FP 0 "=f,f,f"))]
5527   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5528   "@
5529    a<xde>tr\t%0,%1,%2
5530    a<xde>br\t%0,%2
5531    a<xde>b\t%0,%2"
5532   [(set_attr "op_type"  "RRF,RRE,RXE")
5533    (set_attr "type"     "fsimp<mode>")
5534    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5535
5536 ;
5537 ; Pointer add instruction patterns
5538 ;
5539
5540 ; This will match "*la_64"
5541 (define_expand "addptrdi3"
5542   [(set (match_operand:DI 0 "register_operand" "")
5543         (plus:DI (match_operand:DI 1 "register_operand" "")
5544                  (match_operand:DI 2 "nonmemory_operand" "")))]
5545   "TARGET_64BIT"
5546 {
5547   if (GET_CODE (operands[2]) == CONST_INT)
5548     {
5549       HOST_WIDE_INT c = INTVAL (operands[2]);
5550
5551       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5552           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5553         {
5554           operands[2] = force_const_mem (DImode, operands[2]);
5555           operands[2] = force_reg (DImode, operands[2]);
5556         }
5557       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5558         operands[2] = force_reg (DImode, operands[2]);
5559     }
5560 })
5561
5562 ; For 31 bit we have to prevent the generated pattern from matching
5563 ; normal ADDs since la only does a 31 bit add.  This is supposed to
5564 ; match "force_la_31".
5565 (define_expand "addptrsi3"
5566   [(parallel
5567     [(set (match_operand:SI 0 "register_operand" "")
5568           (plus:SI (match_operand:SI 1 "register_operand" "")
5569                    (match_operand:SI 2 "nonmemory_operand" "")))
5570                    (use (const_int 0))])]
5571   "!TARGET_64BIT"
5572 {
5573   if (GET_CODE (operands[2]) == CONST_INT)
5574     {
5575       HOST_WIDE_INT c = INTVAL (operands[2]);
5576
5577       if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5578           && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5579         {
5580           operands[2] = force_const_mem (SImode, operands[2]);
5581           operands[2] = force_reg (SImode, operands[2]);
5582         }
5583       else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5584         operands[2] = force_reg (SImode, operands[2]);
5585     }
5586 })
5587
5588 ;;
5589 ;;- Subtract instructions.
5590 ;;
5591
5592 ;
5593 ; subti3 instruction pattern(s).
5594 ;
5595
5596 (define_expand "subti3"
5597   [(parallel
5598     [(set (match_operand:TI           0 "register_operand" "")
5599           (minus:TI (match_operand:TI 1 "register_operand" "")
5600                     (match_operand:TI 2 "general_operand"  "") ) )
5601      (clobber (reg:CC CC_REGNUM))])]
5602   "TARGET_ZARCH"
5603 {
5604   /* For z13 we have vaq which doesn't set CC.  */
5605   if (TARGET_VX)
5606     {
5607       emit_insn (gen_rtx_SET (operands[0],
5608                               gen_rtx_MINUS (TImode,
5609                                             operands[1],
5610                                             copy_to_mode_reg (TImode, operands[2]))));
5611       DONE;
5612     }
5613 })
5614
5615 (define_insn_and_split "*subti3"
5616   [(set (match_operand:TI           0 "register_operand" "=&d")
5617         (minus:TI (match_operand:TI 1 "register_operand"   "0")
5618                   (match_operand:TI 2 "general_operand"   "do") ) )
5619    (clobber (reg:CC CC_REGNUM))]
5620   "TARGET_ZARCH"
5621   "#"
5622   "&& reload_completed"
5623   [(parallel
5624     [(set (reg:CCL2 CC_REGNUM)
5625           (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5626                         (match_dup 7)))
5627      (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5628    (parallel
5629     [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5630                                   (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5631      (clobber (reg:CC CC_REGNUM))])]
5632   "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5633    operands[4] = operand_subword (operands[1], 0, 0, TImode);
5634    operands[5] = operand_subword (operands[2], 0, 0, TImode);
5635    operands[6] = operand_subword (operands[0], 1, 0, TImode);
5636    operands[7] = operand_subword (operands[1], 1, 0, TImode);
5637    operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5638   [(set_attr "op_type"      "*")
5639    (set_attr "cpu_facility" "*")])
5640
5641 ;
5642 ; subdi3 instruction pattern(s).
5643 ;
5644
5645 (define_expand "subdi3"
5646   [(parallel
5647     [(set (match_operand:DI 0 "register_operand" "")
5648           (minus:DI (match_operand:DI 1 "register_operand" "")
5649                     (match_operand:DI 2 "general_operand" "")))
5650      (clobber (reg:CC CC_REGNUM))])]
5651   ""
5652   "")
5653
5654 (define_insn "*subdi3_sign"
5655   [(set (match_operand:DI 0 "register_operand" "=d,d")
5656         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5657                   (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5658    (clobber (reg:CC CC_REGNUM))]
5659   "TARGET_ZARCH"
5660   "@
5661    sgfr\t%0,%2
5662    sgf\t%0,%2"
5663   [(set_attr "op_type"  "RRE,RXY")
5664    (set_attr "z10prop" "z10_c,*")
5665    (set_attr "z196prop" "z196_cracked")])
5666
5667 (define_insn "*subdi3_zero_cc"
5668   [(set (reg CC_REGNUM)
5669         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5670                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5671                  (const_int 0)))
5672    (set (match_operand:DI 0 "register_operand" "=d,d")
5673         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5674   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5675   "@
5676    slgfr\t%0,%2
5677    slgf\t%0,%2"
5678   [(set_attr "op_type"  "RRE,RXY")
5679    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5680
5681 (define_insn "*subdi3_zero_cconly"
5682   [(set (reg CC_REGNUM)
5683         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5684                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5685                  (const_int 0)))
5686    (clobber (match_scratch:DI 0 "=d,d"))]
5687   "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5688   "@
5689    slgfr\t%0,%2
5690    slgf\t%0,%2"
5691   [(set_attr "op_type"  "RRE,RXY")
5692    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5693
5694 (define_insn "*subdi3_zero"
5695   [(set (match_operand:DI 0 "register_operand" "=d,d")
5696         (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5697                   (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5698    (clobber (reg:CC CC_REGNUM))]
5699   "TARGET_ZARCH"
5700   "@
5701    slgfr\t%0,%2
5702    slgf\t%0,%2"
5703   [(set_attr "op_type"  "RRE,RXY")
5704    (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5705
5706 (define_insn_and_split "*subdi3_31z"
5707   [(set (match_operand:DI 0 "register_operand" "=&d")
5708         (minus:DI (match_operand:DI 1 "register_operand" "0")
5709                   (match_operand:DI 2 "general_operand" "do") ) )
5710    (clobber (reg:CC CC_REGNUM))]
5711   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5712   "#"
5713   "&& reload_completed"
5714   [(parallel
5715     [(set (reg:CCL2 CC_REGNUM)
5716           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5717                         (match_dup 7)))
5718      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5719    (parallel
5720     [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5721                                   (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5722      (clobber (reg:CC CC_REGNUM))])]
5723   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5724    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5725    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5726    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5727    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5728    operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5729
5730 (define_insn_and_split "*subdi3_31"
5731   [(set (match_operand:DI 0 "register_operand" "=&d")
5732         (minus:DI (match_operand:DI 1 "register_operand" "0")
5733                   (match_operand:DI 2 "general_operand" "do") ) )
5734    (clobber (reg:CC CC_REGNUM))]
5735   "!TARGET_CPU_ZARCH"
5736   "#"
5737   "&& reload_completed"
5738   [(parallel
5739     [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5740      (clobber (reg:CC CC_REGNUM))])
5741    (parallel
5742     [(set (reg:CCL2 CC_REGNUM)
5743           (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5744                         (match_dup 7)))
5745      (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5746    (set (pc)
5747         (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5748                       (pc)
5749                       (label_ref (match_dup 9))))
5750    (parallel
5751     [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5752      (clobber (reg:CC CC_REGNUM))])
5753    (match_dup 9)]
5754   "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5755    operands[4] = operand_subword (operands[1], 0, 0, DImode);
5756    operands[5] = operand_subword (operands[2], 0, 0, DImode);
5757    operands[6] = operand_subword (operands[0], 1, 0, DImode);
5758    operands[7] = operand_subword (operands[1], 1, 0, DImode);
5759    operands[8] = operand_subword (operands[2], 1, 0, DImode);
5760    operands[9] = gen_label_rtx ();")
5761
5762 ;
5763 ; subsi3 instruction pattern(s).
5764 ;
5765
5766 (define_expand "subsi3"
5767   [(parallel
5768     [(set (match_operand:SI 0 "register_operand" "")
5769           (minus:SI (match_operand:SI 1 "register_operand" "")
5770                     (match_operand:SI 2 "general_operand" "")))
5771      (clobber (reg:CC CC_REGNUM))])]
5772   ""
5773   "")
5774
5775 (define_insn "*subsi3_sign"
5776   [(set (match_operand:SI 0 "register_operand" "=d,d")
5777         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5778                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5779    (clobber (reg:CC CC_REGNUM))]
5780   ""
5781   "@
5782    sh\t%0,%2
5783    shy\t%0,%2"
5784   [(set_attr "op_type"  "RX,RXY")
5785    (set_attr "z196prop" "z196_cracked,z196_cracked")])
5786
5787 ;
5788 ; sub(di|si)3 instruction pattern(s).
5789 ;
5790
5791 ; sr, s, sy, sgr, sg, srk, sgrk
5792 (define_insn "*sub<mode>3"
5793   [(set (match_operand:GPR 0 "register_operand"           "=d,d,d,d")
5794         (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5795                    (match_operand:GPR 2 "general_operand"  "d,d,R,T") ) )
5796    (clobber (reg:CC CC_REGNUM))]
5797   ""
5798   "@
5799    s<g>r\t%0,%2
5800    s<g>rk\t%0,%1,%2
5801    s<g>\t%0,%2
5802    s<y>\t%0,%2"
5803   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5804    (set_attr "cpu_facility" "*,z196,*,*")
5805    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5806
5807 ; slr, sl, sly, slgr, slg, slrk, slgrk
5808 (define_insn "*sub<mode>3_borrow_cc"
5809   [(set (reg CC_REGNUM)
5810         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5811                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5812                  (match_dup 1)))
5813    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5814         (minus:GPR (match_dup 1) (match_dup 2)))]
5815   "s390_match_ccmode (insn, CCL2mode)"
5816   "@
5817    sl<g>r\t%0,%2
5818    sl<g>rk\t%0,%1,%2
5819    sl<g>\t%0,%2
5820    sl<y>\t%0,%2"
5821   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5822    (set_attr "cpu_facility" "*,z196,*,*")
5823    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5824
5825 ; slr, sl, sly, slgr, slg, slrk, slgrk
5826 (define_insn "*sub<mode>3_borrow_cconly"
5827   [(set (reg CC_REGNUM)
5828         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5829                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5830                  (match_dup 1)))
5831    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5832   "s390_match_ccmode (insn, CCL2mode)"
5833   "@
5834    sl<g>r\t%0,%2
5835    sl<g>rk\t%0,%1,%2
5836    sl<g>\t%0,%2
5837    sl<y>\t%0,%2"
5838   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5839    (set_attr "cpu_facility" "*,z196,*,*")
5840    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5841
5842 ; slr, sl, sly, slgr, slg, slrk, slgrk
5843 (define_insn "*sub<mode>3_cc"
5844   [(set (reg CC_REGNUM)
5845         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5846                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5847                  (const_int 0)))
5848    (set (match_operand:GPR 0 "register_operand"                    "=d,d,d,d")
5849         (minus:GPR (match_dup 1) (match_dup 2)))]
5850   "s390_match_ccmode (insn, CCLmode)"
5851   "@
5852    sl<g>r\t%0,%2
5853    sl<g>rk\t%0,%1,%2
5854    sl<g>\t%0,%2
5855    sl<y>\t%0,%2"
5856   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5857    (set_attr "cpu_facility" "*,z196,*,*")
5858    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5859
5860 ; slr, sl, sly, slgr, slg, slrk, slgrk
5861 (define_insn "*sub<mode>3_cc2"
5862   [(set (reg CC_REGNUM)
5863         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5864                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5865    (set (match_operand:GPR 0 "register_operand"         "=d,d,d,d")
5866         (minus:GPR (match_dup 1) (match_dup 2)))]
5867   "s390_match_ccmode (insn, CCL3mode)"
5868   "@
5869    sl<g>r\t%0,%2
5870    sl<g>rk\t%0,%1,%2
5871    sl<g>\t%0,%2
5872    sl<y>\t%0,%2"
5873   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5874    (set_attr "cpu_facility" "*,z196,*,*")
5875    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5876
5877 ; slr, sl, sly, slgr, slg, slrk, slgrk
5878 (define_insn "*sub<mode>3_cconly"
5879   [(set (reg CC_REGNUM)
5880         (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5881                             (match_operand:GPR 2 "general_operand"  "d,d,R,T"))
5882                  (const_int 0)))
5883    (clobber (match_scratch:GPR 0                                   "=d,d,d,d"))]
5884   "s390_match_ccmode (insn, CCLmode)"
5885   "@
5886    sl<g>r\t%0,%2
5887    sl<g>rk\t%0,%1,%2
5888    sl<g>\t%0,%2
5889    sl<y>\t%0,%2"
5890   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5891    (set_attr "cpu_facility" "*,z196,*,*")
5892    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5893
5894
5895 ; slr, sl, sly, slgr, slg, slrk, slgrk
5896 (define_insn "*sub<mode>3_cconly2"
5897   [(set (reg CC_REGNUM)
5898         (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5899                  (match_operand:GPR 2 "general_operand"  "d,d,R,T")))
5900    (clobber (match_scratch:GPR 0                        "=d,d,d,d"))]
5901   "s390_match_ccmode (insn, CCL3mode)"
5902   "@
5903    sl<g>r\t%0,%2
5904    sl<g>rk\t%0,%1,%2
5905    sl<g>\t%0,%2
5906    sl<y>\t%0,%2"
5907   [(set_attr "op_type"  "RR<E>,RRF,RX<Y>,RXY")
5908    (set_attr "cpu_facility" "*,z196,*,*")
5909    (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5910
5911
5912 ;
5913 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5914 ;
5915
5916 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5917 (define_insn "sub<mode>3"
5918   [(set (match_operand:FP           0 "register_operand" "=f,f,f,v")
5919         (minus:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
5920                   (match_operand:FP 2 "general_operand"   "f,f,R,v")))
5921    (clobber (reg:CC CC_REGNUM))]
5922   "TARGET_HARD_FLOAT"
5923   "@
5924    s<xde>tr\t%0,%1,%2
5925    s<xde>br\t%0,%2
5926    s<xde>b\t%0,%2
5927    wfsdb\t%v0,%v1,%v2"
5928   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
5929    (set_attr "type"         "fsimp<mode>")
5930    (set_attr "cpu_facility" "*,*,*,vec")
5931    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5932
5933 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5934 (define_insn "*sub<mode>3_cc"
5935   [(set (reg CC_REGNUM)
5936         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
5937                            (match_operand:FP 2 "general_operand"      "f,f,R"))
5938                  (match_operand:FP 3 "const0_operand" "")))
5939    (set (match_operand:FP 0 "register_operand" "=f,f,f")
5940         (minus:FP (match_dup 1) (match_dup 2)))]
5941   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5942   "@
5943    s<xde>tr\t%0,%1,%2
5944    s<xde>br\t%0,%2
5945    s<xde>b\t%0,%2"
5946   [(set_attr "op_type"  "RRF,RRE,RXE")
5947    (set_attr "type"     "fsimp<mode>")
5948    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5949
5950 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5951 (define_insn "*sub<mode>3_cconly"
5952   [(set (reg CC_REGNUM)
5953         (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
5954                            (match_operand:FP 2 "general_operand"      "f,f,R"))
5955                  (match_operand:FP 3 "const0_operand" "")))
5956    (clobber (match_scratch:FP 0 "=f,f,f"))]
5957   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5958   "@
5959    s<xde>tr\t%0,%1,%2
5960    s<xde>br\t%0,%2
5961    s<xde>b\t%0,%2"
5962   [(set_attr "op_type"  "RRF,RRE,RXE")
5963    (set_attr "type"     "fsimp<mode>")
5964    (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
5965
5966
5967 ;;
5968 ;;- Conditional add/subtract instructions.
5969 ;;
5970
5971 ;
5972 ; add(di|si)cc instruction pattern(s).
5973 ;
5974
5975 ; the following 4 patterns are used when the result of an add with
5976 ; carry is checked for an overflow condition
5977
5978 ; op1 + op2 + c < op1
5979
5980 ; alcr, alc, alcgr, alcg
5981 (define_insn "*add<mode>3_alc_carry1_cc"
5982   [(set (reg CC_REGNUM)
5983         (compare
5984           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5985                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5986                     (match_operand:GPR 2 "general_operand" "d,RT"))
5987           (match_dup 1)))
5988    (set (match_operand:GPR 0 "register_operand" "=d,d")
5989         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5990   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5991   "@
5992    alc<g>r\t%0,%2
5993    alc<g>\t%0,%2"
5994   [(set_attr "op_type"  "RRE,RXY")
5995    (set_attr "z196prop" "z196_alone,z196_alone")])
5996
5997 ; alcr, alc, alcgr, alcg
5998 (define_insn "*add<mode>3_alc_carry1_cconly"
5999   [(set (reg CC_REGNUM)
6000         (compare
6001           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6002                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6003                     (match_operand:GPR 2 "general_operand" "d,RT"))
6004           (match_dup 1)))
6005    (clobber (match_scratch:GPR 0 "=d,d"))]
6006   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6007   "@
6008    alc<g>r\t%0,%2
6009    alc<g>\t%0,%2"
6010   [(set_attr "op_type"  "RRE,RXY")
6011    (set_attr "z196prop" "z196_alone,z196_alone")])
6012
6013 ; op1 + op2 + c < op2
6014
6015 ; alcr, alc, alcgr, alcg
6016 (define_insn "*add<mode>3_alc_carry2_cc"
6017   [(set (reg CC_REGNUM)
6018         (compare
6019           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6020                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6021                     (match_operand:GPR 2 "general_operand" "d,RT"))
6022           (match_dup 2)))
6023    (set (match_operand:GPR 0 "register_operand" "=d,d")
6024         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6025   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6026   "@
6027    alc<g>r\t%0,%2
6028    alc<g>\t%0,%2"
6029   [(set_attr "op_type"  "RRE,RXY")])
6030
6031 ; alcr, alc, alcgr, alcg
6032 (define_insn "*add<mode>3_alc_carry2_cconly"
6033   [(set (reg CC_REGNUM)
6034         (compare
6035           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6036                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6037                     (match_operand:GPR 2 "general_operand" "d,RT"))
6038           (match_dup 2)))
6039    (clobber (match_scratch:GPR 0 "=d,d"))]
6040   "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6041   "@
6042    alc<g>r\t%0,%2
6043    alc<g>\t%0,%2"
6044   [(set_attr "op_type"  "RRE,RXY")])
6045
6046 ; alcr, alc, alcgr, alcg
6047 (define_insn "*add<mode>3_alc_cc"
6048   [(set (reg CC_REGNUM)
6049         (compare
6050           (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6051                               (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6052                     (match_operand:GPR 2 "general_operand" "d,RT"))
6053           (const_int 0)))
6054    (set (match_operand:GPR 0 "register_operand" "=d,d")
6055         (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6056   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6057   "@
6058    alc<g>r\t%0,%2
6059    alc<g>\t%0,%2"
6060   [(set_attr "op_type"  "RRE,RXY")])
6061
6062 ; alcr, alc, alcgr, alcg
6063 (define_insn "*add<mode>3_alc"
6064   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6065         (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6066                             (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6067                   (match_operand:GPR 2 "general_operand" "d,RT")))
6068    (clobber (reg:CC CC_REGNUM))]
6069   "TARGET_CPU_ZARCH"
6070   "@
6071    alc<g>r\t%0,%2
6072    alc<g>\t%0,%2"
6073   [(set_attr "op_type"  "RRE,RXY")])
6074
6075 ; slbr, slb, slbgr, slbg
6076 (define_insn "*sub<mode>3_slb_cc"
6077   [(set (reg CC_REGNUM)
6078         (compare
6079           (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6080                                 (match_operand:GPR 2 "general_operand" "d,RT"))
6081                      (match_operand:GPR 3 "s390_slb_comparison" ""))
6082           (const_int 0)))
6083    (set (match_operand:GPR 0 "register_operand" "=d,d")
6084         (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6085   "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6086   "@
6087    slb<g>r\t%0,%2
6088    slb<g>\t%0,%2"
6089   [(set_attr "op_type"  "RRE,RXY")
6090    (set_attr "z10prop" "z10_c,*")])
6091
6092 ; slbr, slb, slbgr, slbg
6093 (define_insn "*sub<mode>3_slb"
6094   [(set (match_operand:GPR 0 "register_operand" "=d,d")
6095         (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6096                               (match_operand:GPR 2 "general_operand" "d,RT"))
6097                    (match_operand:GPR 3 "s390_slb_comparison" "")))
6098    (clobber (reg:CC CC_REGNUM))]
6099   "TARGET_CPU_ZARCH"
6100   "@
6101    slb<g>r\t%0,%2
6102    slb<g>\t%0,%2"
6103   [(set_attr "op_type"  "RRE,RXY")
6104    (set_attr "z10prop" "z10_c,*")])
6105
6106 (define_expand "add<mode>cc"
6107   [(match_operand:GPR 0 "register_operand" "")
6108    (match_operand 1 "comparison_operator" "")
6109    (match_operand:GPR 2 "register_operand" "")
6110    (match_operand:GPR 3 "const_int_operand" "")]
6111   "TARGET_CPU_ZARCH"
6112   "if (!s390_expand_addcc (GET_CODE (operands[1]),
6113                            XEXP (operands[1], 0), XEXP (operands[1], 1),
6114                            operands[0], operands[2],
6115                            operands[3])) FAIL; DONE;")
6116
6117 ;
6118 ; scond instruction pattern(s).
6119 ;
6120
6121 (define_insn_and_split "*scond<mode>"
6122   [(set (match_operand:GPR 0 "register_operand" "=&d")
6123         (match_operand:GPR 1 "s390_alc_comparison" ""))
6124    (clobber (reg:CC CC_REGNUM))]
6125   "TARGET_CPU_ZARCH"
6126   "#"
6127   "&& reload_completed"
6128   [(set (match_dup 0) (const_int 0))
6129    (parallel
6130     [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6131                                   (match_dup 0)))
6132      (clobber (reg:CC CC_REGNUM))])]
6133   "")
6134
6135 (define_insn_and_split "*scond<mode>_neg"
6136   [(set (match_operand:GPR 0 "register_operand" "=&d")
6137         (match_operand:GPR 1 "s390_slb_comparison" ""))
6138    (clobber (reg:CC CC_REGNUM))]
6139   "TARGET_CPU_ZARCH"
6140   "#"
6141   "&& reload_completed"
6142   [(set (match_dup 0) (const_int 0))
6143    (parallel
6144     [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6145                                    (match_dup 1)))
6146      (clobber (reg:CC CC_REGNUM))])
6147    (parallel
6148     [(set (match_dup 0) (neg:GPR (match_dup 0)))
6149      (clobber (reg:CC CC_REGNUM))])]
6150   "")
6151
6152
6153 (define_expand "cstore<mode>4"
6154   [(set (match_operand:SI 0 "register_operand" "")
6155         (match_operator:SI 1 "s390_scond_operator"
6156          [(match_operand:GPR 2 "register_operand" "")
6157           (match_operand:GPR 3 "general_operand" "")]))]
6158   "TARGET_CPU_ZARCH"
6159   "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6160                            operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6161
6162 (define_expand "cstorecc4"
6163   [(parallel
6164     [(set (match_operand:SI 0 "register_operand" "")
6165           (match_operator:SI 1 "s390_eqne_operator"
6166            [(match_operand:CCZ1 2 "register_operand")
6167             (match_operand 3 "const0_operand")]))
6168      (clobber (reg:CC CC_REGNUM))])]
6169   ""
6170   "emit_insn (gen_sne (operands[0], operands[2]));
6171    if (GET_CODE (operands[1]) == EQ)
6172      emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6173    DONE;")
6174
6175 (define_insn_and_split "sne"
6176   [(set (match_operand:SI 0 "register_operand" "=d")
6177         (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6178                (const_int 0)))
6179    (clobber (reg:CC CC_REGNUM))]
6180   ""
6181   "#"
6182   "reload_completed"
6183   [(parallel
6184     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6185      (clobber (reg:CC CC_REGNUM))])])
6186
6187
6188 ;;
6189 ;; - Conditional move instructions (introduced with z196)
6190 ;;
6191
6192 (define_expand "mov<mode>cc"
6193   [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6194         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6195                           (match_operand:GPR 2 "nonimmediate_operand" "")
6196                           (match_operand:GPR 3 "nonimmediate_operand" "")))]
6197   "TARGET_Z196"
6198 {
6199   /* Emit the comparison insn in case we do not already have a comparison result.  */
6200   if (!s390_comparison (operands[1], VOIDmode))
6201     operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6202                                      XEXP (operands[1], 0),
6203                                      XEXP (operands[1], 1));
6204 })
6205
6206 ; locr, loc, stoc, locgr, locg, stocg
6207 (define_insn_and_split "*mov<mode>cc"
6208   [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d, d, d,QS,QS,&d")
6209         (if_then_else:GPR
6210           (match_operator 1 "s390_comparison"
6211             [(match_operand 2 "cc_reg_operand"        " c,c, c, c, c, c, c")
6212              (match_operand 5 "const_int_operand"     "")])
6213           (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
6214           (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
6215   "TARGET_Z196"
6216   "@
6217    loc<g>r%C1\t%0,%3
6218    loc<g>r%D1\t%0,%4
6219    loc<g>%C1\t%0,%3
6220    loc<g>%D1\t%0,%4
6221    stoc<g>%C1\t%3,%0
6222    stoc<g>%D1\t%4,%0
6223    #"
6224   "&& reload_completed
6225    && MEM_P (operands[3]) && MEM_P (operands[4])"
6226   [(set (match_dup 0)
6227         (if_then_else:GPR
6228          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6229          (match_dup 3)
6230          (match_dup 0)))
6231    (set (match_dup 0)
6232         (if_then_else:GPR
6233          (match_op_dup 1 [(match_dup 2) (const_int 0)])
6234          (match_dup 0)
6235          (match_dup 4)))]
6236   ""
6237   [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
6238
6239 ;;
6240 ;;- Multiply instructions.
6241 ;;
6242
6243 ;
6244 ; muldi3 instruction pattern(s).
6245 ;
6246
6247 (define_insn "*muldi3_sign"
6248   [(set (match_operand:DI 0 "register_operand" "=d,d")
6249         (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
6250                  (match_operand:DI 1 "register_operand" "0,0")))]
6251   "TARGET_ZARCH"
6252   "@
6253    msgfr\t%0,%2
6254    msgf\t%0,%2"
6255   [(set_attr "op_type"      "RRE,RXY")
6256    (set_attr "type"         "imuldi")])
6257
6258 (define_insn "muldi3"
6259   [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6260         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6261                  (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
6262   "TARGET_ZARCH"
6263   "@
6264    msgr\t%0,%2
6265    mghi\t%0,%h2
6266    msg\t%0,%2
6267    msgfi\t%0,%2"
6268   [(set_attr "op_type"      "RRE,RI,RXY,RIL")
6269    (set_attr "type"         "imuldi")
6270    (set_attr "cpu_facility" "*,*,*,z10")])
6271
6272 ;
6273 ; mulsi3 instruction pattern(s).
6274 ;
6275
6276 (define_insn "*mulsi3_sign"
6277   [(set (match_operand:SI 0 "register_operand" "=d,d")
6278         (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6279                  (match_operand:SI 1 "register_operand" "0,0")))]
6280   ""
6281   "@
6282    mh\t%0,%2
6283    mhy\t%0,%2"
6284   [(set_attr "op_type"      "RX,RXY")
6285    (set_attr "type"         "imulhi")
6286    (set_attr "cpu_facility" "*,z10")])
6287
6288 (define_insn "mulsi3"
6289   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6290         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6291                   (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6292   ""
6293   "@
6294    msr\t%0,%2
6295    mhi\t%0,%h2
6296    ms\t%0,%2
6297    msy\t%0,%2
6298    msfi\t%0,%2"
6299   [(set_attr "op_type"      "RRE,RI,RX,RXY,RIL")
6300    (set_attr "type"         "imulsi,imulhi,imulsi,imulsi,imulsi")
6301    (set_attr "cpu_facility" "*,*,*,*,z10")])
6302
6303 ;
6304 ; mulsidi3 instruction pattern(s).
6305 ;
6306
6307 (define_insn "mulsidi3"
6308   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6309         (mult:DI (sign_extend:DI
6310                    (match_operand:SI 1 "register_operand" "%0,0,0"))
6311                  (sign_extend:DI
6312                    (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6313   "!TARGET_ZARCH"
6314   "@
6315    mr\t%0,%2
6316    m\t%0,%2
6317    mfy\t%0,%2"
6318   [(set_attr "op_type"      "RR,RX,RXY")
6319    (set_attr "type"         "imulsi")
6320    (set_attr "cpu_facility" "*,*,z10")])
6321
6322 ;
6323 ; umul instruction pattern(s).
6324 ;
6325
6326 ; mlr, ml, mlgr, mlg
6327 (define_insn "umul<dwh><mode>3"
6328   [(set (match_operand:DW 0 "register_operand"                   "=d, d")
6329         (mult:DW (zero_extend:DW
6330                    (match_operand:<DWH> 1 "register_operand"     "%0, 0"))
6331                  (zero_extend:DW
6332                    (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
6333   "TARGET_CPU_ZARCH"
6334   "@
6335    ml<tg>r\t%0,%2
6336    ml<tg>\t%0,%2"
6337   [(set_attr "op_type"  "RRE,RXY")
6338    (set_attr "type"     "imul<dwh>")])
6339
6340 ;
6341 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6342 ;
6343
6344 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6345 (define_insn "mul<mode>3"
6346   [(set (match_operand:FP          0 "register_operand"     "=f,f,f,v")
6347         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6348                  (match_operand:FP 2 "general_operand"       "f,f,R,v")))]
6349   "TARGET_HARD_FLOAT"
6350   "@
6351    m<xdee>tr\t%0,%1,%2
6352    m<xdee>br\t%0,%2
6353    m<xdee>b\t%0,%2
6354    wfmdb\t%v0,%v1,%v2"
6355   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6356    (set_attr "type"         "fmul<mode>")
6357    (set_attr "cpu_facility" "*,*,*,vec")
6358    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6359
6360 ; madbr, maebr, maxb, madb, maeb
6361 (define_insn "fma<mode>4"
6362   [(set (match_operand:DSF          0 "register_operand"     "=f,f,v")
6363         (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6364                  (match_operand:DSF 2 "nonimmediate_operand"  "f,R,v")
6365                  (match_operand:DSF 3 "register_operand"      "0,0,v")))]
6366   "TARGET_HARD_FLOAT"
6367   "@
6368    ma<xde>br\t%0,%1,%2
6369    ma<xde>b\t%0,%1,%2
6370    wfmadb\t%v0,%v1,%v2,%v3"
6371   [(set_attr "op_type"      "RRE,RXE,VRR")
6372    (set_attr "type"         "fmadd<mode>")
6373    (set_attr "cpu_facility" "*,*,vec")
6374    (set_attr "enabled"      "*,*,<DFDI>")])
6375
6376 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6377 (define_insn "fms<mode>4"
6378   [(set (match_operand:DSF                   0 "register_operand"     "=f,f,v")
6379         (fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,v")
6380                  (match_operand:DSF          2 "nonimmediate_operand"  "f,R,v")
6381                  (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,v"))))]
6382   "TARGET_HARD_FLOAT"
6383   "@
6384    ms<xde>br\t%0,%1,%2
6385    ms<xde>b\t%0,%1,%2
6386    wfmsdb\t%v0,%v1,%v2,%v3"
6387   [(set_attr "op_type"      "RRE,RXE,VRR")
6388    (set_attr "type"         "fmadd<mode>")
6389    (set_attr "cpu_facility" "*,*,vec")
6390    (set_attr "enabled"      "*,*,<DFDI>")])
6391
6392 ;;
6393 ;;- Divide and modulo instructions.
6394 ;;
6395
6396 ;
6397 ; divmoddi4 instruction pattern(s).
6398 ;
6399
6400 (define_expand "divmoddi4"
6401   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6402                    (div:DI (match_operand:DI 1 "register_operand" "")
6403                            (match_operand:DI 2 "general_operand" "")))
6404               (set (match_operand:DI 3 "general_operand" "")
6405                    (mod:DI (match_dup 1) (match_dup 2)))])
6406    (clobber (match_dup 4))]
6407   "TARGET_ZARCH"
6408 {
6409   rtx insn, div_equal, mod_equal;
6410
6411   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6412   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6413
6414   operands[4] = gen_reg_rtx(TImode);
6415   emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6416
6417   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6418   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6419
6420   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6421   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6422
6423   DONE;
6424 })
6425
6426 (define_insn "divmodtidi3"
6427   [(set (match_operand:TI 0 "register_operand" "=d,d")
6428         (ior:TI
6429           (ashift:TI
6430             (zero_extend:TI
6431               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6432                       (match_operand:DI 2 "general_operand" "d,RT")))
6433             (const_int 64))
6434           (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6435   "TARGET_ZARCH"
6436   "@
6437    dsgr\t%0,%2
6438    dsg\t%0,%2"
6439   [(set_attr "op_type"  "RRE,RXY")
6440    (set_attr "type"     "idiv")])
6441
6442 (define_insn "divmodtisi3"
6443   [(set (match_operand:TI 0 "register_operand" "=d,d")
6444         (ior:TI
6445           (ashift:TI
6446             (zero_extend:TI
6447               (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6448                       (sign_extend:DI
6449                         (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
6450             (const_int 64))
6451           (zero_extend:TI
6452             (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6453   "TARGET_ZARCH"
6454   "@
6455    dsgfr\t%0,%2
6456    dsgf\t%0,%2"
6457   [(set_attr "op_type"  "RRE,RXY")
6458    (set_attr "type"     "idiv")])
6459
6460 ;
6461 ; udivmoddi4 instruction pattern(s).
6462 ;
6463
6464 (define_expand "udivmoddi4"
6465   [(parallel [(set (match_operand:DI 0 "general_operand" "")
6466                    (udiv:DI (match_operand:DI 1 "general_operand" "")
6467                             (match_operand:DI 2 "nonimmediate_operand" "")))
6468               (set (match_operand:DI 3 "general_operand" "")
6469                    (umod:DI (match_dup 1) (match_dup 2)))])
6470    (clobber (match_dup 4))]
6471   "TARGET_ZARCH"
6472 {
6473   rtx insn, div_equal, mod_equal, equal;
6474
6475   div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6476   mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6477   equal = gen_rtx_IOR (TImode,
6478                        gen_rtx_ASHIFT (TImode,
6479                                        gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6480                                        GEN_INT (64)),
6481                        gen_rtx_ZERO_EXTEND (TImode, div_equal));
6482
6483   operands[4] = gen_reg_rtx(TImode);
6484   emit_clobber (operands[4]);
6485   emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6486   emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6487
6488   insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6489   set_unique_reg_note (insn, REG_EQUAL, equal);
6490
6491   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6492   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6493
6494   insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6495   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6496
6497   DONE;
6498 })
6499
6500 (define_insn "udivmodtidi3"
6501   [(set (match_operand:TI 0 "register_operand" "=d,d")
6502         (ior:TI
6503           (ashift:TI
6504             (zero_extend:TI
6505               (truncate:DI
6506                 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6507                          (zero_extend:TI
6508                            (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6509             (const_int 64))
6510           (zero_extend:TI
6511             (truncate:DI
6512               (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6513   "TARGET_ZARCH"
6514   "@
6515    dlgr\t%0,%2
6516    dlg\t%0,%2"
6517   [(set_attr "op_type"  "RRE,RXY")
6518    (set_attr "type"     "idiv")])
6519
6520 ;
6521 ; divmodsi4 instruction pattern(s).
6522 ;
6523
6524 (define_expand "divmodsi4"
6525   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6526                    (div:SI (match_operand:SI 1 "general_operand" "")
6527                            (match_operand:SI 2 "nonimmediate_operand" "")))
6528               (set (match_operand:SI 3 "general_operand" "")
6529                    (mod:SI (match_dup 1) (match_dup 2)))])
6530    (clobber (match_dup 4))]
6531   "!TARGET_ZARCH"
6532 {
6533   rtx insn, div_equal, mod_equal, equal;
6534
6535   div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6536   mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6537   equal = gen_rtx_IOR (DImode,
6538                        gen_rtx_ASHIFT (DImode,
6539                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6540                                        GEN_INT (32)),
6541                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6542
6543   operands[4] = gen_reg_rtx(DImode);
6544   emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6545
6546   insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6547   set_unique_reg_note (insn, REG_EQUAL, equal);
6548
6549   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6550   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6551
6552   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6553   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6554
6555   DONE;
6556 })
6557
6558 (define_insn "divmoddisi3"
6559   [(set (match_operand:DI 0 "register_operand" "=d,d")
6560         (ior:DI
6561           (ashift:DI
6562             (zero_extend:DI
6563               (truncate:SI
6564                 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6565                         (sign_extend:DI
6566                           (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6567             (const_int 32))
6568           (zero_extend:DI
6569             (truncate:SI
6570               (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6571   "!TARGET_ZARCH"
6572   "@
6573    dr\t%0,%2
6574    d\t%0,%2"
6575   [(set_attr "op_type"  "RR,RX")
6576    (set_attr "type"     "idiv")])
6577
6578 ;
6579 ; udivsi3 and umodsi3 instruction pattern(s).
6580 ;
6581
6582 (define_expand "udivmodsi4"
6583   [(parallel [(set (match_operand:SI 0 "general_operand" "")
6584                    (udiv:SI (match_operand:SI 1 "general_operand" "")
6585                             (match_operand:SI 2 "nonimmediate_operand" "")))
6586               (set (match_operand:SI 3 "general_operand" "")
6587                    (umod:SI (match_dup 1) (match_dup 2)))])
6588    (clobber (match_dup 4))]
6589   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6590 {
6591   rtx insn, div_equal, mod_equal, equal;
6592
6593   div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6594   mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6595   equal = gen_rtx_IOR (DImode,
6596                        gen_rtx_ASHIFT (DImode,
6597                                        gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6598                                        GEN_INT (32)),
6599                        gen_rtx_ZERO_EXTEND (DImode, div_equal));
6600
6601   operands[4] = gen_reg_rtx(DImode);
6602   emit_clobber (operands[4]);
6603   emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6604   emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6605
6606   insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6607   set_unique_reg_note (insn, REG_EQUAL, equal);
6608
6609   insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6610   set_unique_reg_note (insn, REG_EQUAL, div_equal);
6611
6612   insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6613   set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6614
6615   DONE;
6616 })
6617
6618 (define_insn "udivmoddisi3"
6619   [(set (match_operand:DI 0 "register_operand" "=d,d")
6620         (ior:DI
6621           (ashift:DI
6622             (zero_extend:DI
6623               (truncate:SI
6624                 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6625                          (zero_extend:DI
6626                            (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6627             (const_int 32))
6628           (zero_extend:DI
6629             (truncate:SI
6630               (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6631   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6632   "@
6633    dlr\t%0,%2
6634    dl\t%0,%2"
6635   [(set_attr "op_type"  "RRE,RXY")
6636    (set_attr "type"     "idiv")])
6637
6638 (define_expand "udivsi3"
6639   [(set (match_operand:SI 0 "register_operand" "=d")
6640         (udiv:SI (match_operand:SI 1 "general_operand" "")
6641                  (match_operand:SI 2 "general_operand" "")))
6642    (clobber (match_dup 3))]
6643   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6644 {
6645   rtx insn, udiv_equal, umod_equal, equal;
6646
6647   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6648   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6649   equal = gen_rtx_IOR (DImode,
6650                        gen_rtx_ASHIFT (DImode,
6651                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6652                                        GEN_INT (32)),
6653                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6654
6655   operands[3] = gen_reg_rtx (DImode);
6656
6657   if (CONSTANT_P (operands[2]))
6658     {
6659       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6660         {
6661           rtx_code_label *label1 = gen_label_rtx ();
6662
6663           operands[1] = make_safe_from (operands[1], operands[0]);
6664           emit_move_insn (operands[0], const0_rtx);
6665           emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6666                                    SImode, 1, label1);
6667           emit_move_insn (operands[0], const1_rtx);
6668           emit_label (label1);
6669         }
6670       else
6671         {
6672           operands[2] = force_reg (SImode, operands[2]);
6673           operands[2] = make_safe_from (operands[2], operands[0]);
6674
6675           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6676           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6677                                              operands[2]));
6678           set_unique_reg_note (insn, REG_EQUAL, equal);
6679
6680           insn = emit_move_insn (operands[0],
6681                                  gen_lowpart (SImode, operands[3]));
6682           set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6683         }
6684     }
6685   else
6686     {
6687       rtx_code_label *label1 = gen_label_rtx ();
6688       rtx_code_label *label2 = gen_label_rtx ();
6689       rtx_code_label *label3 = gen_label_rtx ();
6690
6691       operands[1] = force_reg (SImode, operands[1]);
6692       operands[1] = make_safe_from (operands[1], operands[0]);
6693       operands[2] = force_reg (SImode, operands[2]);
6694       operands[2] = make_safe_from (operands[2], operands[0]);
6695
6696       emit_move_insn (operands[0], const0_rtx);
6697       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6698                                SImode, 1, label3);
6699       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6700                                SImode, 0, label2);
6701       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6702                                SImode, 0, label1);
6703       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6704       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6705                                          operands[2]));
6706       set_unique_reg_note (insn, REG_EQUAL, equal);
6707
6708       insn = emit_move_insn (operands[0],
6709                              gen_lowpart (SImode, operands[3]));
6710       set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6711
6712       emit_jump (label3);
6713       emit_label (label1);
6714       emit_move_insn (operands[0], operands[1]);
6715       emit_jump (label3);
6716       emit_label (label2);
6717       emit_move_insn (operands[0], const1_rtx);
6718       emit_label (label3);
6719     }
6720   emit_move_insn (operands[0], operands[0]);
6721   DONE;
6722 })
6723
6724 (define_expand "umodsi3"
6725   [(set (match_operand:SI 0 "register_operand" "=d")
6726         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6727                  (match_operand:SI 2 "nonimmediate_operand" "")))
6728    (clobber (match_dup 3))]
6729   "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6730 {
6731   rtx insn, udiv_equal, umod_equal, equal;
6732
6733   udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6734   umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6735   equal = gen_rtx_IOR (DImode,
6736                        gen_rtx_ASHIFT (DImode,
6737                                        gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6738                                        GEN_INT (32)),
6739                        gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6740
6741   operands[3] = gen_reg_rtx (DImode);
6742
6743   if (CONSTANT_P (operands[2]))
6744     {
6745       if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6746         {
6747           rtx_code_label *label1 = gen_label_rtx ();
6748
6749           operands[1] = make_safe_from (operands[1], operands[0]);
6750           emit_move_insn (operands[0], operands[1]);
6751           emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6752                                    SImode, 1, label1);
6753           emit_insn (gen_abssi2 (operands[0], operands[2]));
6754           emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6755           emit_label (label1);
6756         }
6757       else
6758         {
6759           operands[2] = force_reg (SImode, operands[2]);
6760           operands[2] = make_safe_from (operands[2], operands[0]);
6761
6762           emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6763           insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6764                                              operands[2]));
6765           set_unique_reg_note (insn, REG_EQUAL, equal);
6766
6767           insn = emit_move_insn (operands[0],
6768                                  gen_highpart (SImode, operands[3]));
6769           set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6770         }
6771     }
6772   else
6773     {
6774       rtx_code_label *label1 = gen_label_rtx ();
6775       rtx_code_label *label2 = gen_label_rtx ();
6776       rtx_code_label *label3 = gen_label_rtx ();
6777
6778       operands[1] = force_reg (SImode, operands[1]);
6779       operands[1] = make_safe_from (operands[1], operands[0]);
6780       operands[2] = force_reg (SImode, operands[2]);
6781       operands[2] = make_safe_from (operands[2], operands[0]);
6782
6783       emit_move_insn(operands[0], operands[1]);
6784       emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6785                                SImode, 1, label3);
6786       emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6787                                SImode, 0, label2);
6788       emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6789                                SImode, 0, label1);
6790       emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6791       insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6792                                          operands[2]));
6793       set_unique_reg_note (insn, REG_EQUAL, equal);
6794
6795       insn = emit_move_insn (operands[0],
6796                              gen_highpart (SImode, operands[3]));
6797       set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6798
6799       emit_jump (label3);
6800       emit_label (label1);
6801       emit_move_insn (operands[0], const0_rtx);
6802       emit_jump (label3);
6803       emit_label (label2);
6804       emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6805       emit_label (label3);
6806     }
6807   DONE;
6808 })
6809
6810 ;
6811 ; div(df|sf)3 instruction pattern(s).
6812 ;
6813
6814 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6815 (define_insn "div<mode>3"
6816   [(set (match_operand:FP         0 "register_operand" "=f,f,f,v")
6817         (div:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
6818                 (match_operand:FP 2 "general_operand"   "f,f,R,v")))]
6819   "TARGET_HARD_FLOAT"
6820   "@
6821    d<xde>tr\t%0,%1,%2
6822    d<xde>br\t%0,%2
6823    d<xde>b\t%0,%2
6824    wfddb\t%v0,%v1,%v2"
6825   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
6826    (set_attr "type"         "fdiv<mode>")
6827    (set_attr "cpu_facility" "*,*,*,vec")
6828    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6829
6830
6831 ;;
6832 ;;- And instructions.
6833 ;;
6834
6835 (define_expand "and<mode>3"
6836   [(set (match_operand:INT 0 "nonimmediate_operand" "")
6837         (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6838                  (match_operand:INT 2 "general_operand" "")))
6839    (clobber (reg:CC CC_REGNUM))]
6840   ""
6841   "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6842
6843 ;
6844 ; anddi3 instruction pattern(s).
6845 ;
6846
6847 (define_insn "*anddi3_cc"
6848   [(set (reg CC_REGNUM)
6849         (compare
6850           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6851                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6852           (const_int 0)))
6853    (set (match_operand:DI 0 "register_operand"               "=d,d, d,    d")
6854         (and:DI (match_dup 1) (match_dup 2)))]
6855   "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6856   "@
6857    ngr\t%0,%2
6858    ngrk\t%0,%1,%2
6859    ng\t%0,%2
6860    risbg\t%0,%1,%s2,128+%e2,0"
6861   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6862    (set_attr "cpu_facility" "*,z196,*,z10")
6863    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6864
6865 (define_insn "*anddi3_cconly"
6866   [(set (reg CC_REGNUM)
6867         (compare
6868           (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
6869                   (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
6870                  (const_int 0)))
6871    (clobber (match_scratch:DI 0                              "=d,d, d,    d"))]
6872   "TARGET_ZARCH
6873    && s390_match_ccmode(insn, CCTmode)
6874    /* Do not steal TM patterns.  */
6875    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6876   "@
6877    ngr\t%0,%2
6878    ngrk\t%0,%1,%2
6879    ng\t%0,%2
6880    risbg\t%0,%1,%s2,128+%e2,0"
6881   [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
6882    (set_attr "cpu_facility" "*,z196,*,z10")
6883    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6884
6885 (define_insn "*anddi3"
6886   [(set (match_operand:DI 0 "nonimmediate_operand"
6887             "=d,d,    d,    d,    d,    d,    d,    d,d,d, d,    d,   AQ,Q")
6888         (and:DI
6889           (match_operand:DI 1 "nonimmediate_operand"
6890             "%d,o,    0,    0,    0,    0,    0,    0,0,d, 0,    d,    0,0")
6891           (match_operand:DI 2 "general_operand"
6892             "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6893    (clobber (reg:CC CC_REGNUM))]
6894   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6895   "@
6896    #
6897    #
6898    nihh\t%0,%j2
6899    nihl\t%0,%j2
6900    nilh\t%0,%j2
6901    nill\t%0,%j2
6902    nihf\t%0,%m2
6903    nilf\t%0,%m2
6904    ngr\t%0,%2
6905    ngrk\t%0,%1,%2
6906    ng\t%0,%2
6907    risbg\t%0,%1,%s2,128+%e2,0
6908    #
6909    #"
6910   [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6911    (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6912    (set_attr "z10prop" "*,
6913                         *,
6914                         z10_super_E1,
6915                         z10_super_E1,
6916                         z10_super_E1,
6917                         z10_super_E1,
6918                         z10_super_E1,
6919                         z10_super_E1,
6920                         z10_super_E1,
6921                         *,
6922                         z10_super_E1,
6923                         z10_super_E1,
6924                         *,
6925                         *")])
6926
6927 (define_split
6928   [(set (match_operand:DI 0 "s_operand" "")
6929         (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6930    (clobber (reg:CC CC_REGNUM))]
6931   "reload_completed"
6932   [(parallel
6933     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6934      (clobber (reg:CC CC_REGNUM))])]
6935   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6936
6937 ;; These two are what combine generates for (ashift (zero_extract)).
6938 (define_insn "*extzv_<mode>_srl"
6939   [(set (match_operand:GPR 0 "register_operand" "=d")
6940         (and:GPR (lshiftrt:GPR
6941                    (match_operand:GPR 1 "register_operand" "d")
6942                    (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6943                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6944    (clobber (reg:CC CC_REGNUM))]
6945   "TARGET_Z10
6946    /* Note that even for the SImode pattern, the rotate is always DImode.  */
6947    && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6948                            INTVAL (operands[3]))"
6949   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6950   [(set_attr "op_type" "RIE")
6951    (set_attr "z10prop" "z10_super_E1")])
6952
6953 (define_insn "*extzv_<mode>_sll"
6954   [(set (match_operand:GPR 0 "register_operand" "=d")
6955         (and:GPR (ashift:GPR
6956                   (match_operand:GPR 1 "register_operand" "d")
6957                   (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6958                 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6959    (clobber (reg:CC CC_REGNUM))]
6960   "TARGET_Z10
6961    && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6962                            INTVAL (operands[3]))"
6963   "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6964   [(set_attr "op_type" "RIE")
6965    (set_attr "z10prop" "z10_super_E1")])
6966
6967
6968 ;
6969 ; andsi3 instruction pattern(s).
6970 ;
6971
6972 (define_insn "*andsi3_cc"
6973   [(set (reg CC_REGNUM)
6974         (compare
6975           (and:SI
6976             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6977             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
6978           (const_int 0)))
6979    (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
6980         (and:SI (match_dup 1) (match_dup 2)))]
6981   "s390_match_ccmode(insn, CCTmode)"
6982   "@
6983    nilf\t%0,%o2
6984    nr\t%0,%2
6985    nrk\t%0,%1,%2
6986    n\t%0,%2
6987    ny\t%0,%2
6988    risbg\t%0,%1,%t2,128+%f2,0"
6989   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
6990    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6991    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6992                         z10_super_E1,z10_super_E1,z10_super_E1")])
6993
6994 (define_insn "*andsi3_cconly"
6995   [(set (reg CC_REGNUM)
6996         (compare
6997           (and:SI
6998             (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
6999             (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
7000           (const_int 0)))
7001    (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
7002   "s390_match_ccmode(insn, CCTmode)
7003    /* Do not steal TM patterns.  */
7004    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7005   "@
7006    nilf\t%0,%o2
7007    nr\t%0,%2
7008    nrk\t%0,%1,%2
7009    n\t%0,%2
7010    ny\t%0,%2
7011    risbg\t%0,%1,%t2,128+%f2,0"
7012   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
7013    (set_attr "cpu_facility" "*,*,z196,*,*,z10")
7014    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7015                         z10_super_E1,z10_super_E1,z10_super_E1")])
7016
7017 (define_insn "*andsi3_zarch"
7018   [(set (match_operand:SI 0 "nonimmediate_operand"
7019                             "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
7020         (and:SI (match_operand:SI 1 "nonimmediate_operand"
7021                             "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
7022                 (match_operand:SI 2 "general_operand"
7023                             " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
7024    (clobber (reg:CC CC_REGNUM))]
7025   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7026   "@
7027    #
7028    #
7029    nilh\t%0,%j2
7030    nill\t%0,%j2
7031    nilf\t%0,%o2
7032    nr\t%0,%2
7033    nrk\t%0,%1,%2
7034    n\t%0,%2
7035    ny\t%0,%2
7036    risbg\t%0,%1,%t2,128+%f2,0
7037    #
7038    #"
7039   [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7040    (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
7041    (set_attr "z10prop" "*,
7042                         *,
7043                         z10_super_E1,
7044                         z10_super_E1,
7045                         z10_super_E1,
7046                         z10_super_E1,
7047                         *,
7048                         z10_super_E1,
7049                         z10_super_E1,
7050                         z10_super_E1,
7051                         *,
7052                         *")])
7053
7054 (define_insn "*andsi3_esa"
7055   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,   AQ,Q")
7056         (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,    0,0")
7057                 (match_operand:SI 2 "general_operand"      " d,R,NxQSF,Q")))
7058    (clobber (reg:CC CC_REGNUM))]
7059   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7060   "@
7061    nr\t%0,%2
7062    n\t%0,%2
7063    #
7064    #"
7065   [(set_attr "op_type"  "RR,RX,SI,SS")
7066    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7067
7068
7069 (define_split
7070   [(set (match_operand:SI 0 "s_operand" "")
7071         (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7072    (clobber (reg:CC CC_REGNUM))]
7073   "reload_completed"
7074   [(parallel
7075     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7076      (clobber (reg:CC CC_REGNUM))])]
7077   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7078
7079 ;
7080 ; andhi3 instruction pattern(s).
7081 ;
7082
7083 (define_insn "*andhi3_zarch"
7084   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7085         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7086                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQHF,Q")))
7087    (clobber (reg:CC CC_REGNUM))]
7088   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7089   "@
7090    nr\t%0,%2
7091    nrk\t%0,%1,%2
7092    nill\t%0,%x2
7093    #
7094    #"
7095   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7096    (set_attr "cpu_facility" "*,z196,*,*,*")
7097    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7098 ])
7099
7100 (define_insn "*andhi3_esa"
7101   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7102         (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7103                 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7104    (clobber (reg:CC CC_REGNUM))]
7105   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7106   "@
7107    nr\t%0,%2
7108    #
7109    #"
7110   [(set_attr "op_type"  "RR,SI,SS")
7111    (set_attr "z10prop" "z10_super_E1,*,*")
7112 ])
7113
7114 (define_split
7115   [(set (match_operand:HI 0 "s_operand" "")
7116         (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7117    (clobber (reg:CC CC_REGNUM))]
7118   "reload_completed"
7119   [(parallel
7120     [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7121      (clobber (reg:CC CC_REGNUM))])]
7122   "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7123
7124 ;
7125 ; andqi3 instruction pattern(s).
7126 ;
7127
7128 (define_insn "*andqi3_zarch"
7129   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7130         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7131                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7132    (clobber (reg:CC CC_REGNUM))]
7133   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7134   "@
7135    nr\t%0,%2
7136    nrk\t%0,%1,%2
7137    nill\t%0,%b2
7138    ni\t%S0,%b2
7139    niy\t%S0,%b2
7140    #"
7141   [(set_attr "op_type"  "RR,RRF,RI,SI,SIY,SS")
7142    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7143    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7144
7145 (define_insn "*andqi3_esa"
7146   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7147         (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7148                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7149    (clobber (reg:CC CC_REGNUM))]
7150   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7151   "@
7152    nr\t%0,%2
7153    ni\t%S0,%b2
7154    #"
7155   [(set_attr "op_type"  "RR,SI,SS")
7156    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7157
7158 ;
7159 ; Block and (NC) patterns.
7160 ;
7161
7162 (define_insn "*nc"
7163   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7164         (and:BLK (match_dup 0)
7165                  (match_operand:BLK 1 "memory_operand" "Q")))
7166    (use (match_operand 2 "const_int_operand" "n"))
7167    (clobber (reg:CC CC_REGNUM))]
7168   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7169   "nc\t%O0(%2,%R0),%S1"
7170   [(set_attr "op_type" "SS")
7171    (set_attr "z196prop" "z196_cracked")])
7172
7173 (define_split
7174   [(set (match_operand 0 "memory_operand" "")
7175         (and (match_dup 0)
7176              (match_operand 1 "memory_operand" "")))
7177    (clobber (reg:CC CC_REGNUM))]
7178   "reload_completed
7179    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7180    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7181   [(parallel
7182     [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7183      (use (match_dup 2))
7184      (clobber (reg:CC CC_REGNUM))])]
7185 {
7186   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7187   operands[0] = adjust_address (operands[0], BLKmode, 0);
7188   operands[1] = adjust_address (operands[1], BLKmode, 0);
7189 })
7190
7191 (define_peephole2
7192   [(parallel
7193     [(set (match_operand:BLK 0 "memory_operand" "")
7194           (and:BLK (match_dup 0)
7195                    (match_operand:BLK 1 "memory_operand" "")))
7196      (use (match_operand 2 "const_int_operand" ""))
7197      (clobber (reg:CC CC_REGNUM))])
7198    (parallel
7199     [(set (match_operand:BLK 3 "memory_operand" "")
7200           (and:BLK (match_dup 3)
7201                    (match_operand:BLK 4 "memory_operand" "")))
7202      (use (match_operand 5 "const_int_operand" ""))
7203      (clobber (reg:CC CC_REGNUM))])]
7204   "s390_offset_p (operands[0], operands[3], operands[2])
7205    && s390_offset_p (operands[1], operands[4], operands[2])
7206    && !s390_overlap_p (operands[0], operands[1],
7207                        INTVAL (operands[2]) + INTVAL (operands[5]))
7208    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7209   [(parallel
7210     [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7211      (use (match_dup 8))
7212      (clobber (reg:CC CC_REGNUM))])]
7213   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7214    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7215    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7216
7217
7218 ;;
7219 ;;- Bit set (inclusive or) instructions.
7220 ;;
7221
7222 (define_expand "ior<mode>3"
7223   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7224         (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7225                  (match_operand:INT 2 "general_operand" "")))
7226    (clobber (reg:CC CC_REGNUM))]
7227   ""
7228   "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7229
7230 ;
7231 ; iordi3 instruction pattern(s).
7232 ;
7233
7234 (define_insn "*iordi3_cc"
7235   [(set (reg CC_REGNUM)
7236         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7237                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7238                  (const_int 0)))
7239    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7240         (ior:DI (match_dup 1) (match_dup 2)))]
7241   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7242   "@
7243    ogr\t%0,%2
7244    ogrk\t%0,%1,%2
7245    og\t%0,%2"
7246   [(set_attr "op_type"  "RRE,RRF,RXY")
7247    (set_attr "cpu_facility" "*,z196,*")
7248    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7249
7250 (define_insn "*iordi3_cconly"
7251   [(set (reg CC_REGNUM)
7252         (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7253                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7254                  (const_int 0)))
7255    (clobber (match_scratch:DI 0                                     "=d,d,d"))]
7256   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7257   "@
7258    ogr\t%0,%2
7259    ogrk\t%0,%1,%2
7260    og\t%0,%2"
7261   [(set_attr "op_type"  "RRE,RRF,RXY")
7262    (set_attr "cpu_facility" "*,z196,*")
7263    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7264
7265 (define_insn "*iordi3"
7266   [(set (match_operand:DI 0 "nonimmediate_operand"
7267                                "=d,    d,    d,    d,    d,    d,d,d, d,   AQ,Q")
7268         (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7269                             "   %0,    0,    0,    0,    0,    0,0,d, 0,    0,0")
7270                 (match_operand:DI 2 "general_operand"
7271                             "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7272    (clobber (reg:CC CC_REGNUM))]
7273   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7274   "@
7275    oihh\t%0,%i2
7276    oihl\t%0,%i2
7277    oilh\t%0,%i2
7278    oill\t%0,%i2
7279    oihf\t%0,%k2
7280    oilf\t%0,%k2
7281    ogr\t%0,%2
7282    ogrk\t%0,%1,%2
7283    og\t%0,%2
7284    #
7285    #"
7286   [(set_attr "op_type"  "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7287    (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7288    (set_attr "z10prop" "z10_super_E1,
7289                         z10_super_E1,
7290                         z10_super_E1,
7291                         z10_super_E1,
7292                         z10_super_E1,
7293                         z10_super_E1,
7294                         z10_super_E1,
7295                         *,
7296                         z10_super_E1,
7297                         *,
7298                         *")])
7299
7300 (define_split
7301   [(set (match_operand:DI 0 "s_operand" "")
7302         (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7303    (clobber (reg:CC CC_REGNUM))]
7304   "reload_completed"
7305   [(parallel
7306     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7307      (clobber (reg:CC CC_REGNUM))])]
7308   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7309
7310 ;
7311 ; iorsi3 instruction pattern(s).
7312 ;
7313
7314 (define_insn "*iorsi3_cc"
7315   [(set (reg CC_REGNUM)
7316         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7317                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7318                  (const_int 0)))
7319    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7320         (ior:SI (match_dup 1) (match_dup 2)))]
7321   "s390_match_ccmode(insn, CCTmode)"
7322   "@
7323    oilf\t%0,%o2
7324    or\t%0,%2
7325    ork\t%0,%1,%2
7326    o\t%0,%2
7327    oy\t%0,%2"
7328   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7329    (set_attr "cpu_facility" "*,*,z196,*,*")
7330    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7331
7332 (define_insn "*iorsi3_cconly"
7333   [(set (reg CC_REGNUM)
7334         (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7335                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7336                  (const_int 0)))
7337    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7338   "s390_match_ccmode(insn, CCTmode)"
7339   "@
7340    oilf\t%0,%o2
7341    or\t%0,%2
7342    ork\t%0,%1,%2
7343    o\t%0,%2
7344    oy\t%0,%2"
7345   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
7346    (set_attr "cpu_facility" "*,*,z196,*,*")
7347    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7348
7349 (define_insn "*iorsi3_zarch"
7350   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,    d, d,d,d,d,d,   AQ,Q")
7351         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,    0, 0,0,d,0,0,    0,0")
7352                 (match_operand:SI 2 "general_operand"   "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7353    (clobber (reg:CC CC_REGNUM))]
7354   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7355   "@
7356    oilh\t%0,%i2
7357    oill\t%0,%i2
7358    oilf\t%0,%o2
7359    or\t%0,%2
7360    ork\t%0,%1,%2
7361    o\t%0,%2
7362    oy\t%0,%2
7363    #
7364    #"
7365   [(set_attr "op_type"  "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7366    (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
7367    (set_attr "z10prop" "z10_super_E1,
7368                         z10_super_E1,
7369                         z10_super_E1,
7370                         z10_super_E1,
7371                         *,
7372                         z10_super_E1,
7373                         z10_super_E1,
7374                         *,
7375                         *")])
7376
7377 (define_insn "*iorsi3_esa"
7378   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7379         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7380                 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7381    (clobber (reg:CC CC_REGNUM))]
7382   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7383   "@
7384    or\t%0,%2
7385    o\t%0,%2
7386    #
7387    #"
7388   [(set_attr "op_type"  "RR,RX,SI,SS")
7389    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7390
7391 (define_split
7392   [(set (match_operand:SI 0 "s_operand" "")
7393         (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7394    (clobber (reg:CC CC_REGNUM))]
7395   "reload_completed"
7396   [(parallel
7397     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7398      (clobber (reg:CC CC_REGNUM))])]
7399   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7400
7401 ;
7402 ; iorhi3 instruction pattern(s).
7403 ;
7404
7405 (define_insn "*iorhi3_zarch"
7406   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7407         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0,    0,0")
7408                 (match_operand:HI 2 "general_operand"      " d,d,n,NxQH0,Q")))
7409    (clobber (reg:CC CC_REGNUM))]
7410   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7411   "@
7412    or\t%0,%2
7413    ork\t%0,%1,%2
7414    oill\t%0,%x2
7415    #
7416    #"
7417   [(set_attr "op_type"  "RR,RRF,RI,SI,SS")
7418    (set_attr "cpu_facility" "*,z196,*,*,*")
7419    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7420
7421 (define_insn "*iorhi3_esa"
7422   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7423         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7424                 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7425    (clobber (reg:CC CC_REGNUM))]
7426   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7427   "@
7428    or\t%0,%2
7429    #
7430    #"
7431   [(set_attr "op_type"  "RR,SI,SS")
7432    (set_attr "z10prop" "z10_super_E1,*,*")])
7433
7434 (define_split
7435   [(set (match_operand:HI 0 "s_operand" "")
7436         (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7437    (clobber (reg:CC CC_REGNUM))]
7438   "reload_completed"
7439   [(parallel
7440     [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7441      (clobber (reg:CC CC_REGNUM))])]
7442   "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7443
7444 ;
7445 ; iorqi3 instruction pattern(s).
7446 ;
7447
7448 (define_insn "*iorqi3_zarch"
7449   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7450         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7451                 (match_operand:QI 2 "general_operand"      " d,d,n,n,n,Q")))
7452    (clobber (reg:CC CC_REGNUM))]
7453   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7454   "@
7455    or\t%0,%2
7456    ork\t%0,%1,%2
7457    oill\t%0,%b2
7458    oi\t%S0,%b2
7459    oiy\t%S0,%b2
7460    #"
7461   [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7462    (set_attr "cpu_facility" "*,z196,*,*,*,*")
7463    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7464                         z10_super,z10_super,*")])
7465
7466 (define_insn "*iorqi3_esa"
7467   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7468         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7469                 (match_operand:QI 2 "general_operand" "d,n,Q")))
7470    (clobber (reg:CC CC_REGNUM))]
7471   "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7472   "@
7473    or\t%0,%2
7474    oi\t%S0,%b2
7475    #"
7476   [(set_attr "op_type"  "RR,SI,SS")
7477    (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7478
7479 ;
7480 ; Block inclusive or (OC) patterns.
7481 ;
7482
7483 (define_insn "*oc"
7484   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7485         (ior:BLK (match_dup 0)
7486                  (match_operand:BLK 1 "memory_operand" "Q")))
7487    (use (match_operand 2 "const_int_operand" "n"))
7488    (clobber (reg:CC CC_REGNUM))]
7489   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7490   "oc\t%O0(%2,%R0),%S1"
7491   [(set_attr "op_type" "SS")
7492    (set_attr "z196prop" "z196_cracked")])
7493
7494 (define_split
7495   [(set (match_operand 0 "memory_operand" "")
7496         (ior (match_dup 0)
7497              (match_operand 1 "memory_operand" "")))
7498    (clobber (reg:CC CC_REGNUM))]
7499   "reload_completed
7500    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7501    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7502   [(parallel
7503     [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7504      (use (match_dup 2))
7505      (clobber (reg:CC CC_REGNUM))])]
7506 {
7507   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7508   operands[0] = adjust_address (operands[0], BLKmode, 0);
7509   operands[1] = adjust_address (operands[1], BLKmode, 0);
7510 })
7511
7512 (define_peephole2
7513   [(parallel
7514     [(set (match_operand:BLK 0 "memory_operand" "")
7515           (ior:BLK (match_dup 0)
7516                    (match_operand:BLK 1 "memory_operand" "")))
7517      (use (match_operand 2 "const_int_operand" ""))
7518      (clobber (reg:CC CC_REGNUM))])
7519    (parallel
7520     [(set (match_operand:BLK 3 "memory_operand" "")
7521           (ior:BLK (match_dup 3)
7522                    (match_operand:BLK 4 "memory_operand" "")))
7523      (use (match_operand 5 "const_int_operand" ""))
7524      (clobber (reg:CC CC_REGNUM))])]
7525   "s390_offset_p (operands[0], operands[3], operands[2])
7526    && s390_offset_p (operands[1], operands[4], operands[2])
7527    && !s390_overlap_p (operands[0], operands[1],
7528                        INTVAL (operands[2]) + INTVAL (operands[5]))
7529    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7530   [(parallel
7531     [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7532      (use (match_dup 8))
7533      (clobber (reg:CC CC_REGNUM))])]
7534   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7535    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7536    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7537
7538
7539 ;;
7540 ;;- Xor instructions.
7541 ;;
7542
7543 (define_expand "xor<mode>3"
7544   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7545         (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7546                  (match_operand:INT 2 "general_operand" "")))
7547    (clobber (reg:CC CC_REGNUM))]
7548   ""
7549   "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7550
7551 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7552 ; simplifications.  So its better to have something matching.
7553 (define_split
7554   [(set (match_operand:INT 0 "nonimmediate_operand" "")
7555         (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7556   ""
7557   [(parallel
7558     [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7559      (clobber (reg:CC CC_REGNUM))])]
7560 {
7561   operands[2] = constm1_rtx;
7562   if (!s390_logical_operator_ok_p (operands))
7563     FAIL;
7564 })
7565
7566 ;
7567 ; xordi3 instruction pattern(s).
7568 ;
7569
7570 (define_insn "*xordi3_cc"
7571   [(set (reg CC_REGNUM)
7572         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7573                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7574                  (const_int 0)))
7575    (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
7576         (xor:DI (match_dup 1) (match_dup 2)))]
7577   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7578   "@
7579    xgr\t%0,%2
7580    xgrk\t%0,%1,%2
7581    xg\t%0,%2"
7582   [(set_attr "op_type" "RRE,RRF,RXY")
7583    (set_attr "cpu_facility" "*,z196,*")
7584    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7585
7586 (define_insn "*xordi3_cconly"
7587   [(set (reg CC_REGNUM)
7588         (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7589                          (match_operand:DI 2 "general_operand"      " d,d,RT"))
7590                  (const_int 0)))
7591    (clobber (match_scratch:DI 0                                     "=d,d, d"))]
7592   "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7593   "@
7594    xgr\t%0,%2
7595    xgrk\t%0,%1,%2
7596    xg\t%0,%2"
7597   [(set_attr "op_type" "RRE,RRF,RXY")
7598    (set_attr "cpu_facility" "*,z196,*")
7599    (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7600
7601 (define_insn "*xordi3"
7602   [(set (match_operand:DI 0 "nonimmediate_operand"         "=d,    d,d,d, d,   AQ,Q")
7603         (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,    0,0,d, 0,    0,0")
7604                 (match_operand:DI 2 "general_operand"   "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7605    (clobber (reg:CC CC_REGNUM))]
7606   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7607   "@
7608    xihf\t%0,%k2
7609    xilf\t%0,%k2
7610    xgr\t%0,%2
7611    xgrk\t%0,%1,%2
7612    xg\t%0,%2
7613    #
7614    #"
7615   [(set_attr "op_type"  "RIL,RIL,RRE,RRF,RXY,SI,SS")
7616    (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7617    (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7618                         *,z10_super_E1,*,*")])
7619
7620 (define_split
7621   [(set (match_operand:DI 0 "s_operand" "")
7622         (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7623    (clobber (reg:CC CC_REGNUM))]
7624   "reload_completed"
7625   [(parallel
7626     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7627      (clobber (reg:CC CC_REGNUM))])]
7628   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7629
7630 ;
7631 ; xorsi3 instruction pattern(s).
7632 ;
7633
7634 (define_insn "*xorsi3_cc"
7635   [(set (reg CC_REGNUM)
7636         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7637                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7638                  (const_int 0)))
7639    (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
7640         (xor:SI (match_dup 1) (match_dup 2)))]
7641   "s390_match_ccmode(insn, CCTmode)"
7642   "@
7643    xilf\t%0,%o2
7644    xr\t%0,%2
7645    xrk\t%0,%1,%2
7646    x\t%0,%2
7647    xy\t%0,%2"
7648   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7649    (set_attr "cpu_facility" "*,*,z196,*,*")
7650    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7651                         z10_super_E1,z10_super_E1")])
7652
7653 (define_insn "*xorsi3_cconly"
7654   [(set (reg CC_REGNUM)
7655         (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7656                          (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
7657                  (const_int 0)))
7658    (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
7659   "s390_match_ccmode(insn, CCTmode)"
7660   "@
7661    xilf\t%0,%o2
7662    xr\t%0,%2
7663    xrk\t%0,%1,%2
7664    x\t%0,%2
7665    xy\t%0,%2"
7666   [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7667    (set_attr "cpu_facility" "*,*,z196,*,*")
7668    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7669                         z10_super_E1,z10_super_E1")])
7670
7671 (define_insn "*xorsi3"
7672   [(set (match_operand:SI 0 "nonimmediate_operand"         "=d,d,d,d,d,   AQ,Q")
7673         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    0,0")
7674                 (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxQS0,Q")))
7675    (clobber (reg:CC CC_REGNUM))]
7676   "s390_logical_operator_ok_p (operands)"
7677   "@
7678    xilf\t%0,%o2
7679    xr\t%0,%2
7680    xrk\t%0,%1,%2
7681    x\t%0,%2
7682    xy\t%0,%2
7683    #
7684    #"
7685   [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,SI,SS")
7686    (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7687    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7688                         z10_super_E1,z10_super_E1,*,*")])
7689
7690 (define_split
7691   [(set (match_operand:SI 0 "s_operand" "")
7692         (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7693    (clobber (reg:CC CC_REGNUM))]
7694   "reload_completed"
7695   [(parallel
7696     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7697      (clobber (reg:CC CC_REGNUM))])]
7698   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7699
7700 ;
7701 ; xorhi3 instruction pattern(s).
7702 ;
7703
7704 (define_insn "*xorhi3"
7705   [(set (match_operand:HI 0 "nonimmediate_operand"         "=d,d,d,   AQ,Q")
7706         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d,    0,0")
7707                 (match_operand:HI 2 "general_operand"      "Os,d,d,NxQH0,Q")))
7708    (clobber (reg:CC CC_REGNUM))]
7709   "s390_logical_operator_ok_p (operands)"
7710   "@
7711    xilf\t%0,%x2
7712    xr\t%0,%2
7713    xrk\t%0,%1,%2
7714    #
7715    #"
7716   [(set_attr "op_type"  "RIL,RR,RRF,SI,SS")
7717    (set_attr "cpu_facility" "*,*,z196,*,*")
7718    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7719
7720 (define_split
7721   [(set (match_operand:HI 0 "s_operand" "")
7722         (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7723    (clobber (reg:CC CC_REGNUM))]
7724   "reload_completed"
7725   [(parallel
7726     [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7727      (clobber (reg:CC CC_REGNUM))])]
7728   "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7729
7730 ;
7731 ; xorqi3 instruction pattern(s).
7732 ;
7733
7734 (define_insn "*xorqi3"
7735   [(set (match_operand:QI 0 "nonimmediate_operand"         "=d,d,d,Q,S,Q")
7736         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7737                 (match_operand:QI 2 "general_operand"      "Os,d,d,n,n,Q")))
7738    (clobber (reg:CC CC_REGNUM))]
7739   "s390_logical_operator_ok_p (operands)"
7740   "@
7741    xilf\t%0,%b2
7742    xr\t%0,%2
7743    xrk\t%0,%1,%2
7744    xi\t%S0,%b2
7745    xiy\t%S0,%b2
7746    #"
7747   [(set_attr "op_type"  "RIL,RR,RRF,SI,SIY,SS")
7748    (set_attr "cpu_facility" "*,*,z196,*,*,*")
7749    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7750
7751
7752 ;
7753 ; Block exclusive or (XC) patterns.
7754 ;
7755
7756 (define_insn "*xc"
7757   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7758         (xor:BLK (match_dup 0)
7759                  (match_operand:BLK 1 "memory_operand" "Q")))
7760    (use (match_operand 2 "const_int_operand" "n"))
7761    (clobber (reg:CC CC_REGNUM))]
7762   "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7763   "xc\t%O0(%2,%R0),%S1"
7764   [(set_attr "op_type" "SS")])
7765
7766 (define_split
7767   [(set (match_operand 0 "memory_operand" "")
7768         (xor (match_dup 0)
7769              (match_operand 1 "memory_operand" "")))
7770    (clobber (reg:CC CC_REGNUM))]
7771   "reload_completed
7772    && GET_MODE (operands[0]) == GET_MODE (operands[1])
7773    && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7774   [(parallel
7775     [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7776      (use (match_dup 2))
7777      (clobber (reg:CC CC_REGNUM))])]
7778 {
7779   operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7780   operands[0] = adjust_address (operands[0], BLKmode, 0);
7781   operands[1] = adjust_address (operands[1], BLKmode, 0);
7782 })
7783
7784 (define_peephole2
7785   [(parallel
7786     [(set (match_operand:BLK 0 "memory_operand" "")
7787           (xor:BLK (match_dup 0)
7788                    (match_operand:BLK 1 "memory_operand" "")))
7789      (use (match_operand 2 "const_int_operand" ""))
7790      (clobber (reg:CC CC_REGNUM))])
7791    (parallel
7792     [(set (match_operand:BLK 3 "memory_operand" "")
7793           (xor:BLK (match_dup 3)
7794                    (match_operand:BLK 4 "memory_operand" "")))
7795      (use (match_operand 5 "const_int_operand" ""))
7796      (clobber (reg:CC CC_REGNUM))])]
7797   "s390_offset_p (operands[0], operands[3], operands[2])
7798    && s390_offset_p (operands[1], operands[4], operands[2])
7799    && !s390_overlap_p (operands[0], operands[1],
7800                        INTVAL (operands[2]) + INTVAL (operands[5]))
7801    && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7802   [(parallel
7803     [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7804      (use (match_dup 8))
7805      (clobber (reg:CC CC_REGNUM))])]
7806   "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7807    operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7808    operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7809
7810 ;
7811 ; Block xor (XC) patterns with src == dest.
7812 ;
7813
7814 (define_insn "*xc_zero"
7815   [(set (match_operand:BLK 0 "memory_operand" "=Q")
7816         (const_int 0))
7817    (use (match_operand 1 "const_int_operand" "n"))
7818    (clobber (reg:CC CC_REGNUM))]
7819   "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7820   "xc\t%O0(%1,%R0),%S0"
7821   [(set_attr "op_type" "SS")
7822    (set_attr "z196prop" "z196_cracked")])
7823
7824 (define_peephole2
7825   [(parallel
7826     [(set (match_operand:BLK 0 "memory_operand" "")
7827           (const_int 0))
7828      (use (match_operand 1 "const_int_operand" ""))
7829      (clobber (reg:CC CC_REGNUM))])
7830    (parallel
7831     [(set (match_operand:BLK 2 "memory_operand" "")
7832           (const_int 0))
7833      (use (match_operand 3 "const_int_operand" ""))
7834      (clobber (reg:CC CC_REGNUM))])]
7835   "s390_offset_p (operands[0], operands[2], operands[1])
7836    && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7837   [(parallel
7838     [(set (match_dup 4) (const_int 0))
7839      (use (match_dup 5))
7840      (clobber (reg:CC CC_REGNUM))])]
7841   "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7842    operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7843
7844
7845 ;;
7846 ;;- Negate instructions.
7847 ;;
7848
7849 ;
7850 ; neg(di|si)2 instruction pattern(s).
7851 ;
7852
7853 (define_expand "neg<mode>2"
7854   [(parallel
7855     [(set (match_operand:DSI 0 "register_operand" "=d")
7856           (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7857      (clobber (reg:CC CC_REGNUM))])]
7858   ""
7859   "")
7860
7861 (define_insn "*negdi2_sign_cc"
7862   [(set (reg CC_REGNUM)
7863         (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7864                            (match_operand:SI 1 "register_operand" "d") 0)
7865                            (const_int 32)) (const_int 32)))
7866                  (const_int 0)))
7867    (set (match_operand:DI 0 "register_operand" "=d")
7868         (neg:DI (sign_extend:DI (match_dup 1))))]
7869   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7870   "lcgfr\t%0,%1"
7871   [(set_attr "op_type"  "RRE")
7872    (set_attr "z10prop" "z10_c")])
7873
7874 (define_insn "*negdi2_sign"
7875   [(set (match_operand:DI 0 "register_operand" "=d")
7876         (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7877    (clobber (reg:CC CC_REGNUM))]
7878   "TARGET_ZARCH"
7879   "lcgfr\t%0,%1"
7880   [(set_attr "op_type"  "RRE")
7881    (set_attr "z10prop" "z10_c")])
7882
7883 ; lcr, lcgr
7884 (define_insn "*neg<mode>2_cc"
7885   [(set (reg CC_REGNUM)
7886         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7887                  (const_int 0)))
7888    (set (match_operand:GPR 0 "register_operand" "=d")
7889         (neg:GPR (match_dup 1)))]
7890   "s390_match_ccmode (insn, CCAmode)"
7891   "lc<g>r\t%0,%1"
7892   [(set_attr "op_type"  "RR<E>")
7893    (set_attr "z10prop" "z10_super_c_E1")])
7894
7895 ; lcr, lcgr
7896 (define_insn "*neg<mode>2_cconly"
7897   [(set (reg CC_REGNUM)
7898         (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7899                  (const_int 0)))
7900    (clobber (match_scratch:GPR 0 "=d"))]
7901   "s390_match_ccmode (insn, CCAmode)"
7902   "lc<g>r\t%0,%1"
7903   [(set_attr "op_type"  "RR<E>")
7904    (set_attr "z10prop" "z10_super_c_E1")])
7905
7906 ; lcr, lcgr
7907 (define_insn "*neg<mode>2"
7908   [(set (match_operand:GPR 0 "register_operand" "=d")
7909         (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7910    (clobber (reg:CC CC_REGNUM))]
7911   ""
7912   "lc<g>r\t%0,%1"
7913   [(set_attr "op_type"  "RR<E>")
7914    (set_attr "z10prop" "z10_super_c_E1")])
7915
7916 (define_insn "*negdi2_31"
7917   [(set (match_operand:DI 0 "register_operand" "=d")
7918         (neg:DI (match_operand:DI 1 "register_operand" "d")))
7919    (clobber (reg:CC CC_REGNUM))]
7920   "!TARGET_ZARCH"
7921   "#")
7922
7923 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7924
7925 ; Doing the twos complement separately on the SImode parts does an
7926 ; unwanted +1 on the high part which needs to be subtracted afterwards
7927 ; ... unless the +1 on the low part created an overflow.
7928
7929 (define_split
7930   [(set (match_operand:DI 0 "register_operand" "")
7931         (neg:DI (match_operand:DI 1 "register_operand" "")))
7932    (clobber (reg:CC CC_REGNUM))]
7933   "!TARGET_ZARCH
7934    && (REGNO (operands[0]) == REGNO (operands[1])
7935       || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7936    && reload_completed"
7937   [(parallel
7938     [(set (match_dup 2) (neg:SI (match_dup 3)))
7939      (clobber (reg:CC CC_REGNUM))])
7940    (parallel
7941     [(set (reg:CCAP CC_REGNUM)
7942           (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7943      (set (match_dup 4) (neg:SI (match_dup 5)))])
7944    (set (pc)
7945         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7946                       (pc)
7947                       (label_ref (match_dup 6))))
7948    (parallel
7949     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7950      (clobber (reg:CC CC_REGNUM))])
7951    (match_dup 6)]
7952   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7953    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7954    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7955    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7956    operands[6] = gen_label_rtx ();")
7957
7958 ; Like above but first make a copy of the low part of the src operand
7959 ; since it might overlap with the high part of the destination.
7960
7961 (define_split
7962   [(set (match_operand:DI 0 "register_operand" "")
7963         (neg:DI (match_operand:DI 1 "register_operand" "")))
7964    (clobber (reg:CC CC_REGNUM))]
7965   "!TARGET_ZARCH
7966    && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7967    && reload_completed"
7968   [; Make a backup of op5 first
7969    (set (match_dup 4) (match_dup 5))
7970    ; Setting op2 here might clobber op5
7971    (parallel
7972     [(set (match_dup 2) (neg:SI (match_dup 3)))
7973      (clobber (reg:CC CC_REGNUM))])
7974    (parallel
7975     [(set (reg:CCAP CC_REGNUM)
7976           (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7977      (set (match_dup 4) (neg:SI (match_dup 4)))])
7978    (set (pc)
7979         (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7980                       (pc)
7981                       (label_ref (match_dup 6))))
7982    (parallel
7983     [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7984      (clobber (reg:CC CC_REGNUM))])
7985    (match_dup 6)]
7986   "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7987    operands[3] = operand_subword (operands[1], 0, 0, DImode);
7988    operands[4] = operand_subword (operands[0], 1, 0, DImode);
7989    operands[5] = operand_subword (operands[1], 1, 0, DImode);
7990    operands[6] = gen_label_rtx ();")
7991
7992 ;
7993 ; neg(df|sf)2 instruction pattern(s).
7994 ;
7995
7996 (define_expand "neg<mode>2"
7997   [(parallel
7998     [(set (match_operand:BFP 0 "register_operand" "=f")
7999           (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
8000      (clobber (reg:CC CC_REGNUM))])]
8001   "TARGET_HARD_FLOAT"
8002   "")
8003
8004 ; lcxbr, lcdbr, lcebr
8005 (define_insn "*neg<mode>2_cc"
8006   [(set (reg CC_REGNUM)
8007         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8008                  (match_operand:BFP 2 "const0_operand" "")))
8009    (set (match_operand:BFP 0 "register_operand" "=f")
8010         (neg:BFP (match_dup 1)))]
8011   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8012   "lc<xde>br\t%0,%1"
8013   [(set_attr "op_type"  "RRE")
8014    (set_attr "type"     "fsimp<mode>")])
8015
8016 ; lcxbr, lcdbr, lcebr
8017 (define_insn "*neg<mode>2_cconly"
8018   [(set (reg CC_REGNUM)
8019         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8020                  (match_operand:BFP 2 "const0_operand" "")))
8021    (clobber (match_scratch:BFP 0 "=f"))]
8022   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8023   "lc<xde>br\t%0,%1"
8024   [(set_attr "op_type"  "RRE")
8025    (set_attr "type"     "fsimp<mode>")])
8026
8027 ; lcdfr
8028 (define_insn "*neg<mode>2_nocc"
8029   [(set (match_operand:FP 0 "register_operand"         "=f")
8030         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8031   "TARGET_DFP"
8032   "lcdfr\t%0,%1"
8033   [(set_attr "op_type"  "RRE")
8034    (set_attr "type"     "fsimp<mode>")])
8035
8036 ; lcxbr, lcdbr, lcebr
8037 ; FIXME: wflcdb does not clobber cc
8038 (define_insn "*neg<mode>2"
8039   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8040         (neg:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8041    (clobber (reg:CC CC_REGNUM))]
8042   "TARGET_HARD_FLOAT"
8043   "@
8044    lc<xde>br\t%0,%1
8045    wflcdb\t%0,%1"
8046   [(set_attr "op_type"      "RRE,VRR")
8047    (set_attr "cpu_facility" "*,vec")
8048    (set_attr "type"         "fsimp<mode>,*")
8049    (set_attr "enabled"      "*,<DFDI>")])
8050
8051
8052 ;;
8053 ;;- Absolute value instructions.
8054 ;;
8055
8056 ;
8057 ; abs(di|si)2 instruction pattern(s).
8058 ;
8059
8060 (define_insn "*absdi2_sign_cc"
8061   [(set (reg CC_REGNUM)
8062         (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8063                            (match_operand:SI 1 "register_operand" "d") 0)
8064                            (const_int 32)) (const_int 32)))
8065                  (const_int 0)))
8066    (set (match_operand:DI 0 "register_operand" "=d")
8067         (abs:DI (sign_extend:DI (match_dup 1))))]
8068   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8069   "lpgfr\t%0,%1"
8070   [(set_attr "op_type"  "RRE")
8071    (set_attr "z10prop" "z10_c")])
8072
8073 (define_insn "*absdi2_sign"
8074   [(set (match_operand:DI 0 "register_operand" "=d")
8075         (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8076    (clobber (reg:CC CC_REGNUM))]
8077   "TARGET_ZARCH"
8078   "lpgfr\t%0,%1"
8079   [(set_attr "op_type"  "RRE")
8080    (set_attr "z10prop" "z10_c")])
8081
8082 ; lpr, lpgr
8083 (define_insn "*abs<mode>2_cc"
8084   [(set (reg CC_REGNUM)
8085         (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8086                  (const_int 0)))
8087    (set (match_operand:GPR 0 "register_operand" "=d")
8088         (abs:GPR (match_dup 1)))]
8089   "s390_match_ccmode (insn, CCAmode)"
8090   "lp<g>r\t%0,%1"
8091   [(set_attr "op_type"  "RR<E>")
8092    (set_attr "z10prop" "z10_c")])
8093
8094 ; lpr, lpgr
8095 (define_insn "*abs<mode>2_cconly"
8096   [(set (reg CC_REGNUM)
8097         (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8098                  (const_int 0)))
8099    (clobber (match_scratch:GPR 0 "=d"))]
8100   "s390_match_ccmode (insn, CCAmode)"
8101   "lp<g>r\t%0,%1"
8102   [(set_attr "op_type"  "RR<E>")
8103    (set_attr "z10prop" "z10_c")])
8104
8105 ; lpr, lpgr
8106 (define_insn "abs<mode>2"
8107   [(set (match_operand:GPR 0 "register_operand" "=d")
8108         (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8109    (clobber (reg:CC CC_REGNUM))]
8110   ""
8111   "lp<g>r\t%0,%1"
8112   [(set_attr "op_type"  "RR<E>")
8113    (set_attr "z10prop" "z10_c")])
8114
8115 ;
8116 ; abs(df|sf)2 instruction pattern(s).
8117 ;
8118
8119 (define_expand "abs<mode>2"
8120   [(parallel
8121     [(set (match_operand:BFP 0 "register_operand" "=f")
8122           (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8123      (clobber (reg:CC CC_REGNUM))])]
8124   "TARGET_HARD_FLOAT"
8125   "")
8126
8127 ; lpxbr, lpdbr, lpebr
8128 (define_insn "*abs<mode>2_cc"
8129   [(set (reg CC_REGNUM)
8130         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8131                  (match_operand:BFP 2 "const0_operand" "")))
8132    (set (match_operand:BFP 0 "register_operand" "=f")
8133         (abs:BFP (match_dup 1)))]
8134   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8135   "lp<xde>br\t%0,%1"
8136   [(set_attr "op_type"  "RRE")
8137    (set_attr "type"     "fsimp<mode>")])
8138
8139 ; lpxbr, lpdbr, lpebr
8140 (define_insn "*abs<mode>2_cconly"
8141   [(set (reg CC_REGNUM)
8142         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8143                  (match_operand:BFP 2 "const0_operand" "")))
8144    (clobber (match_scratch:BFP 0 "=f"))]
8145   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8146   "lp<xde>br\t%0,%1"
8147   [(set_attr "op_type"  "RRE")
8148    (set_attr "type"     "fsimp<mode>")])
8149
8150 ; lpdfr
8151 (define_insn "*abs<mode>2_nocc"
8152   [(set (match_operand:FP 0 "register_operand"         "=f")
8153         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8154   "TARGET_DFP"
8155   "lpdfr\t%0,%1"
8156   [(set_attr "op_type"  "RRE")
8157    (set_attr "type"     "fsimp<mode>")])
8158
8159 ; lpxbr, lpdbr, lpebr
8160 ; FIXME: wflpdb does not clobber cc
8161 (define_insn "*abs<mode>2"
8162   [(set (match_operand:BFP          0 "register_operand" "=f,v")
8163         (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
8164    (clobber (reg:CC CC_REGNUM))]
8165   "TARGET_HARD_FLOAT"
8166   "@
8167     lp<xde>br\t%0,%1
8168     wflpdb\t%0,%1"
8169   [(set_attr "op_type"      "RRE,VRR")
8170    (set_attr "cpu_facility" "*,vec")
8171    (set_attr "type"         "fsimp<mode>,*")
8172    (set_attr "enabled"      "*,<DFDI>")])
8173
8174
8175 ;;
8176 ;;- Negated absolute value instructions
8177 ;;
8178
8179 ;
8180 ; Integer
8181 ;
8182
8183 (define_insn "*negabsdi2_sign_cc"
8184   [(set (reg CC_REGNUM)
8185         (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8186                            (match_operand:SI 1 "register_operand" "d") 0)
8187                            (const_int 32)) (const_int 32))))
8188                  (const_int 0)))
8189    (set (match_operand:DI 0 "register_operand" "=d")
8190         (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8191   "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8192   "lngfr\t%0,%1"
8193   [(set_attr "op_type"  "RRE")
8194    (set_attr "z10prop" "z10_c")])
8195
8196 (define_insn "*negabsdi2_sign"
8197   [(set (match_operand:DI 0 "register_operand" "=d")
8198         (neg:DI (abs:DI (sign_extend:DI
8199                           (match_operand:SI 1 "register_operand" "d")))))
8200    (clobber (reg:CC CC_REGNUM))]
8201   "TARGET_ZARCH"
8202   "lngfr\t%0,%1"
8203   [(set_attr "op_type" "RRE")
8204    (set_attr "z10prop" "z10_c")])
8205
8206 ; lnr, lngr
8207 (define_insn "*negabs<mode>2_cc"
8208   [(set (reg CC_REGNUM)
8209         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8210                  (const_int 0)))
8211    (set (match_operand:GPR 0 "register_operand" "=d")
8212         (neg:GPR (abs:GPR (match_dup 1))))]
8213   "s390_match_ccmode (insn, CCAmode)"
8214   "ln<g>r\t%0,%1"
8215   [(set_attr "op_type"  "RR<E>")
8216    (set_attr "z10prop" "z10_c")])
8217
8218 ; lnr, lngr
8219 (define_insn "*negabs<mode>2_cconly"
8220   [(set (reg CC_REGNUM)
8221         (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8222                  (const_int 0)))
8223    (clobber (match_scratch:GPR 0 "=d"))]
8224   "s390_match_ccmode (insn, CCAmode)"
8225   "ln<g>r\t%0,%1"
8226   [(set_attr "op_type"  "RR<E>")
8227    (set_attr "z10prop" "z10_c")])
8228
8229 ; lnr, lngr
8230 (define_insn "*negabs<mode>2"
8231   [(set (match_operand:GPR 0 "register_operand" "=d")
8232         (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8233    (clobber (reg:CC CC_REGNUM))]
8234   ""
8235   "ln<g>r\t%0,%1"
8236   [(set_attr "op_type" "RR<E>")
8237    (set_attr "z10prop" "z10_c")])
8238
8239 ;
8240 ; Floating point
8241 ;
8242
8243 ; lnxbr, lndbr, lnebr
8244 (define_insn "*negabs<mode>2_cc"
8245   [(set (reg CC_REGNUM)
8246         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8247                  (match_operand:BFP 2 "const0_operand" "")))
8248    (set (match_operand:BFP 0 "register_operand" "=f")
8249         (neg:BFP (abs:BFP (match_dup 1))))]
8250   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8251   "ln<xde>br\t%0,%1"
8252   [(set_attr "op_type"  "RRE")
8253    (set_attr "type"     "fsimp<mode>")])
8254
8255 ; lnxbr, lndbr, lnebr
8256 (define_insn "*negabs<mode>2_cconly"
8257   [(set (reg CC_REGNUM)
8258         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8259                  (match_operand:BFP 2 "const0_operand" "")))
8260    (clobber (match_scratch:BFP 0 "=f"))]
8261   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8262   "ln<xde>br\t%0,%1"
8263   [(set_attr "op_type"  "RRE")
8264    (set_attr "type"     "fsimp<mode>")])
8265
8266 ; lndfr
8267 (define_insn "*negabs<mode>2_nocc"
8268   [(set (match_operand:FP 0 "register_operand"                  "=f")
8269         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8270   "TARGET_DFP"
8271   "lndfr\t%0,%1"
8272   [(set_attr "op_type"  "RRE")
8273    (set_attr "type"     "fsimp<mode>")])
8274
8275 ; lnxbr, lndbr, lnebr
8276 ; FIXME: wflndb does not clobber cc
8277 (define_insn "*negabs<mode>2"
8278   [(set (match_operand:BFP                   0 "register_operand" "=f,v")
8279         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v"))))
8280    (clobber (reg:CC CC_REGNUM))]
8281   "TARGET_HARD_FLOAT"
8282   "@
8283    ln<xde>br\t%0,%1
8284    wflndb\t%0,%1"
8285   [(set_attr "op_type"      "RRE,VRR")
8286    (set_attr "cpu_facility" "*,vec")
8287    (set_attr "type"         "fsimp<mode>,*")
8288    (set_attr "enabled"      "*,<DFDI>")])
8289
8290 ;;
8291 ;;- Square root instructions.
8292 ;;
8293
8294 ;
8295 ; sqrt(df|sf)2 instruction pattern(s).
8296 ;
8297
8298 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8299 (define_insn "sqrt<mode>2"
8300   [(set (match_operand:BFP           0 "register_operand" "=f,f,v")
8301         (sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,R,v")))]
8302   "TARGET_HARD_FLOAT"
8303   "@
8304    sq<xde>br\t%0,%1
8305    sq<xde>b\t%0,%1
8306    wfsqdb\t%v0,%v1"
8307   [(set_attr "op_type"      "RRE,RXE,VRR")
8308    (set_attr "type"         "fsqrt<mode>")
8309    (set_attr "cpu_facility" "*,*,vec")
8310    (set_attr "enabled"      "*,<DSF>,<DFDI>")])
8311
8312
8313 ;;
8314 ;;- One complement instructions.
8315 ;;
8316
8317 ;
8318 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8319 ;
8320
8321 (define_expand "one_cmpl<mode>2"
8322   [(parallel
8323     [(set (match_operand:INT 0 "register_operand" "")
8324           (xor:INT (match_operand:INT 1 "register_operand" "")
8325                    (const_int -1)))
8326      (clobber (reg:CC CC_REGNUM))])]
8327   ""
8328   "")
8329
8330
8331 ;;
8332 ;; Find leftmost bit instructions.
8333 ;;
8334
8335 (define_expand "clzdi2"
8336   [(set (match_operand:DI 0 "register_operand" "=d")
8337         (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8338   "TARGET_EXTIMM && TARGET_ZARCH"
8339 {
8340   rtx insn, clz_equal;
8341   rtx wide_reg = gen_reg_rtx (TImode);
8342   rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8343
8344   clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8345
8346   emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8347
8348   insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8349   set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8350
8351   DONE;
8352 })
8353
8354 (define_insn "clztidi2"
8355   [(set (match_operand:TI 0 "register_operand" "=d")
8356         (ior:TI
8357           (ashift:TI
8358             (zero_extend:TI
8359               (xor:DI (match_operand:DI 1 "register_operand" "d")
8360                       (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8361                                 (subreg:SI (clz:DI (match_dup 1)) 4))))
8362
8363             (const_int 64))
8364           (zero_extend:TI (clz:DI (match_dup 1)))))
8365    (clobber (reg:CC CC_REGNUM))]
8366   "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8367    == (unsigned HOST_WIDE_INT) 1 << 63
8368    && TARGET_EXTIMM && TARGET_ZARCH"
8369   "flogr\t%0,%1"
8370   [(set_attr "op_type"  "RRE")])
8371
8372
8373 ;;
8374 ;;- Rotate instructions.
8375 ;;
8376
8377 ;
8378 ; rotl(di|si)3 instruction pattern(s).
8379 ;
8380
8381 (define_expand "rotl<mode>3"
8382   [(set (match_operand:GPR 0 "register_operand" "")
8383         (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8384                     (match_operand:SI 2 "nonmemory_operand" "")))]
8385   "TARGET_CPU_ZARCH"
8386   "")
8387
8388 ; rll, rllg
8389 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8390   [(set (match_operand:GPR             0 "register_operand"  "=d")
8391         (rotate:GPR (match_operand:GPR 1 "register_operand"   "d")
8392                     (match_operand:SI  2 "nonmemory_operand" "an")))]
8393   "TARGET_CPU_ZARCH"
8394   "rll<g>\t%0,%1,<addr_style_op_ops>"
8395   [(set_attr "op_type"  "RSE")
8396    (set_attr "atype"    "reg")
8397    (set_attr "z10prop"  "z10_super_E1")])
8398
8399
8400 ;;
8401 ;;- Shift instructions.
8402 ;;
8403
8404 ;
8405 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8406 ; Left shifts and logical right shifts
8407
8408 (define_expand "<shift><mode>3"
8409   [(set (match_operand:DSI 0 "register_operand" "")
8410         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8411                    (match_operand:SI 2 "nonmemory_operand" "")))]
8412   ""
8413   "")
8414
8415 ; ESA 64 bit register pair shift with reg or imm shift count
8416 ; sldl, srdl
8417 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8418   [(set (match_operand:DI 0 "register_operand"            "=d")
8419         (SHIFT:DI (match_operand:DI 1 "register_operand"   "0")
8420                   (match_operand:SI 2 "nonmemory_operand" "an")))]
8421   "!TARGET_ZARCH"
8422   "s<lr>dl\t%0,<addr_style_op_ops>"
8423   [(set_attr "op_type"  "RS")
8424    (set_attr "atype"    "reg")
8425    (set_attr "z196prop" "z196_cracked")])
8426
8427
8428 ; 64 bit register shift with reg or imm shift count
8429 ; sll, srl, sllg, srlg, sllk, srlk
8430 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8431   [(set (match_operand:GPR 0 "register_operand"              "=d, d")
8432         (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8433                    (match_operand:SI 2 "nonmemory_operand"   "an,an")))]
8434   ""
8435   "@
8436    s<lr>l<g>\t%0,<1><addr_style_op_ops>
8437    s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8438   [(set_attr "op_type"  "RS<E>,RSY")
8439    (set_attr "atype"    "reg,reg")
8440    (set_attr "cpu_facility" "*,z196")
8441    (set_attr "z10prop"  "z10_super_E1,*")])
8442
8443 ;
8444 ; ashr(di|si)3 instruction pattern(s).
8445 ; Arithmetic right shifts
8446
8447 (define_expand "ashr<mode>3"
8448   [(parallel
8449     [(set (match_operand:DSI 0 "register_operand" "")
8450           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8451                         (match_operand:SI 2 "nonmemory_operand" "")))
8452      (clobber (reg:CC CC_REGNUM))])]
8453   ""
8454   "")
8455
8456 ; FIXME: The number of alternatives is doubled here to match the fix
8457 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8458 ; The right fix should be to support match_scratch in the output
8459 ; pattern of a define_subst.
8460 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8461   [(set (match_operand:DI 0 "register_operand"               "=d, d")
8462         (ashiftrt:DI (match_operand:DI 1 "register_operand"   "0, 0")
8463                      (match_operand:SI 2 "nonmemory_operand" "an,an")))
8464    (clobber (reg:CC CC_REGNUM))]
8465   "!TARGET_ZARCH"
8466   "@
8467    srda\t%0,<addr_style_op_cc_ops>
8468    srda\t%0,<addr_style_op_cc_ops>"
8469   [(set_attr "op_type" "RS")
8470    (set_attr "atype"   "reg")])
8471
8472
8473 ; sra, srag
8474 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8475   [(set (match_operand:GPR 0 "register_operand"                 "=d, d")
8476         (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8477                       (match_operand:SI 2 "nonmemory_operand"   "an,an")))
8478    (clobber (reg:CC CC_REGNUM))]
8479   ""
8480   "@
8481    sra<g>\t%0,<1><addr_style_op_cc_ops>
8482    sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8483   [(set_attr "op_type"  "RS<E>,RSY")
8484    (set_attr "atype"    "reg")
8485    (set_attr "cpu_facility" "*,z196")
8486    (set_attr "z10prop" "z10_super_E1,*")])
8487
8488
8489 ;;
8490 ;; Branch instruction patterns.
8491 ;;
8492
8493 (define_expand "cbranch<mode>4"
8494   [(set (pc)
8495         (if_then_else (match_operator 0 "comparison_operator"
8496                        [(match_operand:GPR 1 "register_operand" "")
8497                         (match_operand:GPR 2 "general_operand" "")])
8498                       (label_ref (match_operand 3 "" ""))
8499                       (pc)))]
8500   ""
8501   "s390_emit_jump (operands[3],
8502     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8503    DONE;")
8504
8505 (define_expand "cbranch<mode>4"
8506   [(set (pc)
8507         (if_then_else (match_operator 0 "comparison_operator"
8508                        [(match_operand:FP 1 "register_operand" "")
8509                         (match_operand:FP 2 "general_operand" "")])
8510                       (label_ref (match_operand 3 "" ""))
8511                       (pc)))]
8512   "TARGET_HARD_FLOAT"
8513   "s390_emit_jump (operands[3],
8514     s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8515    DONE;")
8516
8517 (define_expand "cbranchcc4"
8518   [(set (pc)
8519         (if_then_else (match_operator 0 "s390_comparison"
8520                        [(match_operand 1 "cc_reg_operand" "")
8521                         (match_operand 2 "const_int_operand" "")])
8522                       (label_ref (match_operand 3 "" ""))
8523                       (pc)))]
8524   ""
8525   "")
8526
8527
8528 ;;
8529 ;;- Conditional jump instructions.
8530 ;;
8531
8532 (define_insn "*cjump_64"
8533   [(set (pc)
8534         (if_then_else
8535           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8536                                                (match_operand 2 "const_int_operand" "")])
8537           (label_ref (match_operand 0 "" ""))
8538           (pc)))]
8539   "TARGET_CPU_ZARCH"
8540 {
8541   if (get_attr_length (insn) == 4)
8542     return "j%C1\t%l0";
8543   else
8544     return "jg%C1\t%l0";
8545 }
8546   [(set_attr "op_type" "RI")
8547    (set_attr "type"    "branch")
8548    (set (attr "length")
8549         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8550                       (const_int 4) (const_int 6)))])
8551
8552 (define_insn "*cjump_31"
8553   [(set (pc)
8554         (if_then_else
8555           (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8556                                                (match_operand 2 "const_int_operand" "")])
8557           (label_ref (match_operand 0 "" ""))
8558           (pc)))]
8559   "!TARGET_CPU_ZARCH"
8560 {
8561   gcc_assert (get_attr_length (insn) == 4);
8562   return "j%C1\t%l0";
8563 }
8564   [(set_attr "op_type" "RI")
8565    (set_attr "type"    "branch")
8566    (set (attr "length")
8567         (if_then_else (not (match_test "flag_pic"))
8568           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8569                         (const_int 4) (const_int 6))
8570           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8571                         (const_int 4) (const_int 8))))])
8572
8573 (define_insn "*cjump_long"
8574   [(set (pc)
8575         (if_then_else
8576           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8577           (match_operand 0 "address_operand" "ZQZR")
8578           (pc)))]
8579   ""
8580 {
8581   if (get_attr_op_type (insn) == OP_TYPE_RR)
8582     return "b%C1r\t%0";
8583   else
8584     return "b%C1\t%a0";
8585 }
8586   [(set (attr "op_type")
8587         (if_then_else (match_operand 0 "register_operand" "")
8588                       (const_string "RR") (const_string "RX")))
8589    (set_attr "type"  "branch")
8590    (set_attr "atype" "agen")])
8591
8592 ;; A conditional return instruction.
8593 (define_insn "*c<code>"
8594   [(set (pc)
8595         (if_then_else
8596           (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8597           (ANY_RETURN)
8598           (pc)))]
8599   "s390_can_use_<code>_insn ()"
8600   "b%C0r\t%%r14"
8601   [(set_attr "op_type" "RR")
8602    (set_attr "type"  "jsr")
8603    (set_attr "atype" "agen")])
8604
8605 ;;
8606 ;;- Negated conditional jump instructions.
8607 ;;
8608
8609 (define_insn "*icjump_64"
8610   [(set (pc)
8611         (if_then_else
8612           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8613           (pc)
8614           (label_ref (match_operand 0 "" ""))))]
8615   "TARGET_CPU_ZARCH"
8616 {
8617   if (get_attr_length (insn) == 4)
8618     return "j%D1\t%l0";
8619   else
8620     return "jg%D1\t%l0";
8621 }
8622   [(set_attr "op_type" "RI")
8623    (set_attr "type"    "branch")
8624    (set (attr "length")
8625         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8626                       (const_int 4) (const_int 6)))])
8627
8628 (define_insn "*icjump_31"
8629   [(set (pc)
8630         (if_then_else
8631           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8632           (pc)
8633           (label_ref (match_operand 0 "" ""))))]
8634   "!TARGET_CPU_ZARCH"
8635 {
8636   gcc_assert (get_attr_length (insn) == 4);
8637   return "j%D1\t%l0";
8638 }
8639   [(set_attr "op_type" "RI")
8640    (set_attr "type"    "branch")
8641    (set (attr "length")
8642         (if_then_else (not (match_test "flag_pic"))
8643           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8644                         (const_int 4) (const_int 6))
8645           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8646                         (const_int 4) (const_int 8))))])
8647
8648 (define_insn "*icjump_long"
8649   [(set (pc)
8650         (if_then_else
8651           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8652           (pc)
8653           (match_operand 0 "address_operand" "ZQZR")))]
8654   ""
8655 {
8656   if (get_attr_op_type (insn) == OP_TYPE_RR)
8657     return "b%D1r\t%0";
8658   else
8659     return "b%D1\t%a0";
8660 }
8661   [(set (attr "op_type")
8662         (if_then_else (match_operand 0 "register_operand" "")
8663                       (const_string "RR") (const_string "RX")))
8664    (set_attr "type"  "branch")
8665    (set_attr "atype" "agen")])
8666
8667 ;;
8668 ;;- Trap instructions.
8669 ;;
8670
8671 (define_insn "trap"
8672   [(trap_if (const_int 1) (const_int 0))]
8673   ""
8674   "j\t.+2"
8675   [(set_attr "op_type" "RI")
8676    (set_attr "type"  "branch")])
8677
8678 (define_expand "ctrap<mode>4"
8679   [(trap_if (match_operator 0 "comparison_operator"
8680              [(match_operand:GPR 1 "register_operand" "")
8681               (match_operand:GPR 2 "general_operand" "")])
8682              (match_operand 3 "const0_operand" ""))]
8683   ""
8684   {
8685     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8686                                   operands[1], operands[2]);
8687     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8688     DONE;
8689   })
8690
8691 (define_expand "ctrap<mode>4"
8692   [(trap_if (match_operator 0 "comparison_operator"
8693              [(match_operand:FP 1 "register_operand" "")
8694               (match_operand:FP 2 "general_operand" "")])
8695              (match_operand 3 "const0_operand" ""))]
8696   ""
8697   {
8698     rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8699                                   operands[1], operands[2]);
8700     emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8701     DONE;
8702   })
8703
8704 (define_insn "condtrap"
8705   [(trap_if (match_operator 0 "s390_comparison"
8706              [(match_operand 1 "cc_reg_operand" "c")
8707               (const_int 0)])
8708             (const_int 0))]
8709   ""
8710   "j%C0\t.+2";
8711   [(set_attr "op_type" "RI")
8712    (set_attr "type"  "branch")])
8713
8714 ; crt, cgrt, cit, cgit
8715 (define_insn "*cmp_and_trap_signed_int<mode>"
8716   [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8717                [(match_operand:GPR 1 "register_operand"  "d,d")
8718                 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8719             (const_int 0))]
8720   "TARGET_Z10"
8721   "@
8722    c<g>rt%C0\t%1,%2
8723    c<g>it%C0\t%1,%h2"
8724   [(set_attr "op_type" "RRF,RIE")
8725    (set_attr "type"    "branch")
8726    (set_attr "z10prop" "z10_super_c,z10_super")])
8727
8728 ; clrt, clgrt, clfit, clgit, clt, clgt
8729 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8730   [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8731                [(match_operand:GPR 1 "register_operand" "d,d, d")
8732                 (match_operand:GPR 2 "general_operand"  "d,D,RT")])
8733             (const_int 0))]
8734   "TARGET_Z10"
8735   "@
8736    cl<g>rt%C0\t%1,%2
8737    cl<gf>it%C0\t%1,%x2
8738    cl<g>t%C0\t%1,%2"
8739   [(set_attr "op_type"      "RRF,RIE,RSY")
8740    (set_attr "type"         "branch")
8741    (set_attr "z10prop"      "z10_super_c,z10_super,*")
8742    (set_attr "cpu_facility" "z10,z10,zEC12")])
8743
8744 ; lat, lgat
8745 (define_insn "*load_and_trap<mode>"
8746   [(trap_if (eq (match_operand:GPR 0 "memory_operand"  "RT")
8747                 (const_int 0))
8748             (const_int 0))
8749    (set (match_operand:GPR 1 "register_operand" "=d")
8750         (match_dup 0))]
8751   "TARGET_ZEC12"
8752   "l<g>at\t%1,%0"
8753   [(set_attr "op_type" "RXY")])
8754
8755
8756 ;;
8757 ;;- Loop instructions.
8758 ;;
8759 ;;  This is all complicated by the fact that since this is a jump insn
8760 ;;  we must handle our own output reloads.
8761
8762 ;; branch on index
8763
8764 ; This splitter will be matched by combine and has to add the 2 moves
8765 ; necessary to load the compare and the increment values into a
8766 ; register pair as needed by brxle.
8767
8768 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8769   [(set (pc)
8770         (if_then_else
8771          (match_operator 6 "s390_brx_operator"
8772             [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8773                        (match_operand:GPR 2 "general_operand"  ""))
8774              (match_operand:GPR 3 "register_operand" "")])
8775          (label_ref (match_operand 0 "" ""))
8776          (pc)))
8777    (set (match_operand:GPR 4 "nonimmediate_operand" "")
8778         (plus:GPR (match_dup 1) (match_dup 2)))
8779    (clobber (match_scratch:GPR 5 ""))]
8780   "TARGET_CPU_ZARCH"
8781   "#"
8782   "!reload_completed && !reload_in_progress"
8783   [(set (match_dup 7) (match_dup 2)) ; the increment
8784    (set (match_dup 8) (match_dup 3)) ; the comparison value
8785    (parallel [(set (pc)
8786                    (if_then_else
8787                     (match_op_dup 6
8788                        [(plus:GPR (match_dup 1) (match_dup 7))
8789                         (match_dup 8)])
8790                     (label_ref (match_dup 0))
8791                     (pc)))
8792               (set (match_dup 4)
8793                    (plus:GPR (match_dup 1) (match_dup 7)))
8794               (clobber (match_dup 5))
8795               (clobber (reg:CC CC_REGNUM))])]
8796   {
8797     rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8798     operands[7] = gen_lowpart (<GPR:MODE>mode,
8799                                gen_highpart (word_mode, dreg));
8800     operands[8] = gen_lowpart (<GPR:MODE>mode,
8801                                gen_lowpart (word_mode, dreg));
8802   })
8803
8804 ; brxlg, brxhg
8805
8806 (define_insn_and_split "*brxg_64bit"
8807   [(set (pc)
8808         (if_then_else
8809           (match_operator 5 "s390_brx_operator"
8810              [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8811                        (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8812               (subreg:DI (match_dup 2) 8)])
8813           (label_ref (match_operand 0 "" ""))
8814           (pc)))
8815    (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8816         (plus:DI (match_dup 1)
8817                  (subreg:DI (match_dup 2) 0)))
8818    (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8819    (clobber (reg:CC CC_REGNUM))]
8820   "TARGET_ZARCH"
8821 {
8822   if (which_alternative != 0)
8823     return "#";
8824   else if (get_attr_length (insn) == 6)
8825     return "brx%E5g\t%1,%2,%l0";
8826   else
8827     return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8828 }
8829   "&& reload_completed
8830    && (!REG_P (operands[3])
8831        || !rtx_equal_p (operands[1], operands[3]))"
8832   [(set (match_dup 4) (match_dup 1))
8833    (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8834               (clobber (reg:CC CC_REGNUM))])
8835    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8836    (set (match_dup 3) (match_dup 4))
8837    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8838                            (label_ref (match_dup 0))
8839                            (pc)))]
8840   ""
8841   [(set_attr "op_type"  "RIE")
8842    (set_attr "type"  "branch")
8843    (set (attr "length")
8844         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8845                       (const_int 6) (const_int 16)))])
8846
8847 ; brxle, brxh
8848
8849 (define_insn_and_split "*brx_64bit"
8850   [(set (pc)
8851         (if_then_else
8852           (match_operator 5 "s390_brx_operator"
8853              [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8854                        (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8855               (subreg:SI (match_dup 2) 12)])
8856           (label_ref (match_operand 0 "" ""))
8857           (pc)))
8858    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8859         (plus:SI (match_dup 1)
8860                  (subreg:SI (match_dup 2) 4)))
8861    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8862    (clobber (reg:CC CC_REGNUM))]
8863   "TARGET_ZARCH"
8864 {
8865   if (which_alternative != 0)
8866     return "#";
8867   else if (get_attr_length (insn) == 6)
8868     return "brx%C5\t%1,%2,%l0";
8869   else
8870     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8871 }
8872   "&& reload_completed
8873    && (!REG_P (operands[3])
8874        || !rtx_equal_p (operands[1], operands[3]))"
8875   [(set (match_dup 4) (match_dup 1))
8876    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8877               (clobber (reg:CC CC_REGNUM))])
8878    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8879    (set (match_dup 3) (match_dup 4))
8880    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8881                            (label_ref (match_dup 0))
8882                            (pc)))]
8883   ""
8884   [(set_attr "op_type"  "RSI")
8885    (set_attr "type"  "branch")
8886    (set (attr "length")
8887         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8888                       (const_int 6) (const_int 14)))])
8889
8890 ; brxle, brxh
8891
8892 (define_insn_and_split "*brx_31bit"
8893   [(set (pc)
8894         (if_then_else
8895           (match_operator 5 "s390_brx_operator"
8896             [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8897                       (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8898              (subreg:SI (match_dup 2) 4)])
8899           (label_ref (match_operand 0 "" ""))
8900           (pc)))
8901    (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8902         (plus:SI (match_dup 1)
8903                  (subreg:SI (match_dup 2) 0)))
8904    (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8905    (clobber (reg:CC CC_REGNUM))]
8906   "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8907 {
8908   if (which_alternative != 0)
8909     return "#";
8910   else if (get_attr_length (insn) == 6)
8911     return "brx%C5\t%1,%2,%l0";
8912   else
8913     return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8914 }
8915   "&& reload_completed
8916    && (!REG_P (operands[3])
8917        || !rtx_equal_p (operands[1], operands[3]))"
8918   [(set (match_dup 4) (match_dup 1))
8919    (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8920               (clobber (reg:CC CC_REGNUM))])
8921    (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8922    (set (match_dup 3) (match_dup 4))
8923    (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8924                            (label_ref (match_dup 0))
8925                            (pc)))]
8926   ""
8927   [(set_attr "op_type"  "RSI")
8928    (set_attr "type"  "branch")
8929    (set (attr "length")
8930         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8931                       (const_int 6) (const_int 14)))])
8932
8933
8934 ;; branch on count
8935
8936 (define_expand "doloop_end"
8937   [(use (match_operand 0 "" ""))        ; loop pseudo
8938    (use (match_operand 1 "" ""))]       ; label
8939   ""
8940 {
8941   if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8942     emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8943   else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8944     emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8945   else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8946     emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8947   else
8948     FAIL;
8949
8950   DONE;
8951 })
8952
8953 (define_insn_and_split "doloop_si64"
8954   [(set (pc)
8955         (if_then_else
8956           (ne (match_operand:SI 1 "register_operand" "d,d,d")
8957               (const_int 1))
8958           (label_ref (match_operand 0 "" ""))
8959           (pc)))
8960    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8961         (plus:SI (match_dup 1) (const_int -1)))
8962    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8963    (clobber (reg:CC CC_REGNUM))]
8964   "TARGET_CPU_ZARCH"
8965 {
8966   if (which_alternative != 0)
8967     return "#";
8968   else if (get_attr_length (insn) == 4)
8969     return "brct\t%1,%l0";
8970   else
8971     return "ahi\t%1,-1\;jgne\t%l0";
8972 }
8973   "&& reload_completed
8974    && (! REG_P (operands[2])
8975        || ! rtx_equal_p (operands[1], operands[2]))"
8976   [(set (match_dup 3) (match_dup 1))
8977    (parallel [(set (reg:CCAN CC_REGNUM)
8978                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8979                                  (const_int 0)))
8980               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8981    (set (match_dup 2) (match_dup 3))
8982    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8983                            (label_ref (match_dup 0))
8984                            (pc)))]
8985   ""
8986   [(set_attr "op_type"  "RI")
8987    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8988    ; hurt us in the (rare) case of ahi.
8989    (set_attr "z10prop"  "z10_super_E1")
8990    (set_attr "type"  "branch")
8991    (set (attr "length")
8992         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8993                       (const_int 4) (const_int 10)))])
8994
8995 (define_insn_and_split "doloop_si31"
8996   [(set (pc)
8997         (if_then_else
8998           (ne (match_operand:SI 1 "register_operand" "d,d,d")
8999               (const_int 1))
9000           (label_ref (match_operand 0 "" ""))
9001           (pc)))
9002    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9003         (plus:SI (match_dup 1) (const_int -1)))
9004    (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9005    (clobber (reg:CC CC_REGNUM))]
9006   "!TARGET_CPU_ZARCH"
9007 {
9008   if (which_alternative != 0)
9009     return "#";
9010   else if (get_attr_length (insn) == 4)
9011     return "brct\t%1,%l0";
9012   else
9013     gcc_unreachable ();
9014 }
9015   "&& reload_completed
9016    && (! REG_P (operands[2])
9017        || ! rtx_equal_p (operands[1], operands[2]))"
9018   [(set (match_dup 3) (match_dup 1))
9019    (parallel [(set (reg:CCAN CC_REGNUM)
9020                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9021                                  (const_int 0)))
9022               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9023    (set (match_dup 2) (match_dup 3))
9024    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9025                            (label_ref (match_dup 0))
9026                            (pc)))]
9027   ""
9028   [(set_attr "op_type"  "RI")
9029    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9030    ; hurt us in the (rare) case of ahi.
9031    (set_attr "z10prop"  "z10_super_E1")
9032    (set_attr "type"  "branch")
9033    (set (attr "length")
9034         (if_then_else (not (match_test "flag_pic"))
9035           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9036                         (const_int 4) (const_int 6))
9037           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9038                         (const_int 4) (const_int 8))))])
9039
9040 (define_insn "*doloop_si_long"
9041   [(set (pc)
9042         (if_then_else
9043           (ne (match_operand:SI 1 "register_operand" "d")
9044               (const_int 1))
9045           (match_operand 0 "address_operand" "ZQZR")
9046           (pc)))
9047    (set (match_operand:SI 2 "register_operand" "=1")
9048         (plus:SI (match_dup 1) (const_int -1)))
9049    (clobber (match_scratch:SI 3 "=X"))
9050    (clobber (reg:CC CC_REGNUM))]
9051   "!TARGET_CPU_ZARCH"
9052 {
9053   if (get_attr_op_type (insn) == OP_TYPE_RR)
9054     return "bctr\t%1,%0";
9055   else
9056     return "bct\t%1,%a0";
9057 }
9058   [(set (attr "op_type")
9059         (if_then_else (match_operand 0 "register_operand" "")
9060                       (const_string "RR") (const_string "RX")))
9061    (set_attr "type"  "branch")
9062    (set_attr "atype" "agen")
9063    (set_attr "z10prop"  "z10_c")
9064    (set_attr "z196prop" "z196_cracked")])
9065
9066 (define_insn_and_split "doloop_di"
9067   [(set (pc)
9068         (if_then_else
9069           (ne (match_operand:DI 1 "register_operand" "d,d,d")
9070               (const_int 1))
9071           (label_ref (match_operand 0 "" ""))
9072           (pc)))
9073    (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9074         (plus:DI (match_dup 1) (const_int -1)))
9075    (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9076    (clobber (reg:CC CC_REGNUM))]
9077   "TARGET_ZARCH"
9078 {
9079   if (which_alternative != 0)
9080     return "#";
9081   else if (get_attr_length (insn) == 4)
9082     return "brctg\t%1,%l0";
9083   else
9084     return "aghi\t%1,-1\;jgne\t%l0";
9085 }
9086   "&& reload_completed
9087    && (! REG_P (operands[2])
9088        || ! rtx_equal_p (operands[1], operands[2]))"
9089   [(set (match_dup 3) (match_dup 1))
9090    (parallel [(set (reg:CCAN CC_REGNUM)
9091                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9092                                  (const_int 0)))
9093               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9094    (set (match_dup 2) (match_dup 3))
9095    (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9096                            (label_ref (match_dup 0))
9097                            (pc)))]
9098   ""
9099   [(set_attr "op_type"  "RI")
9100    ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9101    ; hurt us in the (rare) case of ahi.
9102    (set_attr "z10prop"  "z10_super_E1")
9103    (set_attr "type"  "branch")
9104    (set (attr "length")
9105         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9106                       (const_int 4) (const_int 10)))])
9107
9108 ;;
9109 ;;- Unconditional jump instructions.
9110 ;;
9111
9112 ;
9113 ; jump instruction pattern(s).
9114 ;
9115
9116 (define_expand "jump"
9117   [(match_operand 0 "" "")]
9118   ""
9119   "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9120
9121 (define_insn "*jump64"
9122   [(set (pc) (label_ref (match_operand 0 "" "")))]
9123   "TARGET_CPU_ZARCH"
9124 {
9125   if (get_attr_length (insn) == 4)
9126     return "j\t%l0";
9127   else
9128     return "jg\t%l0";
9129 }
9130   [(set_attr "op_type" "RI")
9131    (set_attr "type"  "branch")
9132    (set (attr "length")
9133         (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9134                       (const_int 4) (const_int 6)))])
9135
9136 (define_insn "*jump31"
9137   [(set (pc) (label_ref (match_operand 0 "" "")))]
9138   "!TARGET_CPU_ZARCH"
9139 {
9140   gcc_assert (get_attr_length (insn) == 4);
9141   return "j\t%l0";
9142 }
9143   [(set_attr "op_type" "RI")
9144    (set_attr "type"  "branch")
9145    (set (attr "length")
9146         (if_then_else (not (match_test "flag_pic"))
9147           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9148                         (const_int 4) (const_int 6))
9149           (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9150                         (const_int 4) (const_int 8))))])
9151
9152 ;
9153 ; indirect-jump instruction pattern(s).
9154 ;
9155
9156 (define_insn "indirect_jump"
9157  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
9158   ""
9159 {
9160   if (get_attr_op_type (insn) == OP_TYPE_RR)
9161     return "br\t%0";
9162   else
9163     return "b\t%a0";
9164 }
9165   [(set (attr "op_type")
9166         (if_then_else (match_operand 0 "register_operand" "")
9167                       (const_string "RR") (const_string "RX")))
9168    (set_attr "type"  "branch")
9169    (set_attr "atype" "agen")])
9170
9171 ;
9172 ; casesi instruction pattern(s).
9173 ;
9174
9175 (define_insn "casesi_jump"
9176  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
9177    (use (label_ref (match_operand 1 "" "")))]
9178   ""
9179 {
9180   if (get_attr_op_type (insn) == OP_TYPE_RR)
9181     return "br\t%0";
9182   else
9183     return "b\t%a0";
9184 }
9185   [(set (attr "op_type")
9186         (if_then_else (match_operand 0 "register_operand" "")
9187                       (const_string "RR") (const_string "RX")))
9188    (set_attr "type"  "branch")
9189    (set_attr "atype" "agen")])
9190
9191 (define_expand "casesi"
9192   [(match_operand:SI 0 "general_operand" "")
9193    (match_operand:SI 1 "general_operand" "")
9194    (match_operand:SI 2 "general_operand" "")
9195    (label_ref (match_operand 3 "" ""))
9196    (label_ref (match_operand 4 "" ""))]
9197   ""
9198 {
9199    rtx index  = gen_reg_rtx (SImode);
9200    rtx base   = gen_reg_rtx (Pmode);
9201    rtx target = gen_reg_rtx (Pmode);
9202
9203    emit_move_insn (index, operands[0]);
9204    emit_insn (gen_subsi3 (index, index, operands[1]));
9205    emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9206                             operands[4]);
9207
9208    if (Pmode != SImode)
9209      index = convert_to_mode (Pmode, index, 1);
9210    if (GET_CODE (index) != REG)
9211      index = copy_to_mode_reg (Pmode, index);
9212
9213    if (TARGET_64BIT)
9214        emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9215    else
9216        emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9217
9218    emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9219
9220    index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9221    emit_move_insn (target, index);
9222
9223    if (flag_pic)
9224      target = gen_rtx_PLUS (Pmode, base, target);
9225    emit_jump_insn (gen_casesi_jump (target, operands[3]));
9226
9227    DONE;
9228 })
9229
9230
9231 ;;
9232 ;;- Jump to subroutine.
9233 ;;
9234 ;;
9235
9236 ;
9237 ; untyped call instruction pattern(s).
9238 ;
9239
9240 ;; Call subroutine returning any type.
9241 (define_expand "untyped_call"
9242   [(parallel [(call (match_operand 0 "" "")
9243                     (const_int 0))
9244               (match_operand 1 "" "")
9245               (match_operand 2 "" "")])]
9246   ""
9247 {
9248   int i;
9249
9250   emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9251
9252   for (i = 0; i < XVECLEN (operands[2], 0); i++)
9253     {
9254       rtx set = XVECEXP (operands[2], 0, i);
9255       emit_move_insn (SET_DEST (set), SET_SRC (set));
9256     }
9257
9258   /* The optimizer does not know that the call sets the function value
9259      registers we stored in the result block.  We avoid problems by
9260      claiming that all hard registers are used and clobbered at this
9261      point.  */
9262   emit_insn (gen_blockage ());
9263
9264   DONE;
9265 })
9266
9267 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9268 ;; all of memory.  This blocks insns from being moved across this point.
9269
9270 (define_insn "blockage"
9271   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9272   ""
9273   ""
9274   [(set_attr "type"    "none")
9275    (set_attr "length"  "0")])
9276
9277 ;
9278 ; sibcall patterns
9279 ;
9280
9281 (define_expand "sibcall"
9282   [(call (match_operand 0 "" "")
9283          (match_operand 1 "" ""))]
9284   ""
9285 {
9286   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9287   DONE;
9288 })
9289
9290 (define_insn "*sibcall_br"
9291   [(call (mem:QI (reg SIBCALL_REGNUM))
9292          (match_operand 0 "const_int_operand" "n"))]
9293   "SIBLING_CALL_P (insn)
9294    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9295   "br\t%%r1"
9296   [(set_attr "op_type" "RR")
9297    (set_attr "type"  "branch")
9298    (set_attr "atype" "agen")])
9299
9300 (define_insn "*sibcall_brc"
9301   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9302          (match_operand 1 "const_int_operand" "n"))]
9303   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9304   "j\t%0"
9305   [(set_attr "op_type" "RI")
9306    (set_attr "type"    "branch")])
9307
9308 (define_insn "*sibcall_brcl"
9309   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9310          (match_operand 1 "const_int_operand" "n"))]
9311   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9312   "jg\t%0"
9313   [(set_attr "op_type" "RIL")
9314    (set_attr "type"    "branch")])
9315
9316 ;
9317 ; sibcall_value patterns
9318 ;
9319
9320 (define_expand "sibcall_value"
9321   [(set (match_operand 0 "" "")
9322         (call (match_operand 1 "" "")
9323               (match_operand 2 "" "")))]
9324   ""
9325 {
9326   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9327   DONE;
9328 })
9329
9330 (define_insn "*sibcall_value_br"
9331   [(set (match_operand 0 "" "")
9332         (call (mem:QI (reg SIBCALL_REGNUM))
9333               (match_operand 1 "const_int_operand" "n")))]
9334   "SIBLING_CALL_P (insn)
9335    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9336   "br\t%%r1"
9337   [(set_attr "op_type" "RR")
9338    (set_attr "type"  "branch")
9339    (set_attr "atype" "agen")])
9340
9341 (define_insn "*sibcall_value_brc"
9342   [(set (match_operand 0 "" "")
9343         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9344               (match_operand 2 "const_int_operand" "n")))]
9345   "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9346   "j\t%1"
9347   [(set_attr "op_type" "RI")
9348    (set_attr "type"    "branch")])
9349
9350 (define_insn "*sibcall_value_brcl"
9351   [(set (match_operand 0 "" "")
9352         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9353               (match_operand 2 "const_int_operand" "n")))]
9354   "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9355   "jg\t%1"
9356   [(set_attr "op_type" "RIL")
9357    (set_attr "type"    "branch")])
9358
9359
9360 ;
9361 ; call instruction pattern(s).
9362 ;
9363
9364 (define_expand "call"
9365   [(call (match_operand 0 "" "")
9366          (match_operand 1 "" ""))
9367    (use (match_operand 2 "" ""))]
9368   ""
9369 {
9370   s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9371                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9372   DONE;
9373 })
9374
9375 (define_insn "*bras"
9376   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9377          (match_operand 1 "const_int_operand" "n"))
9378    (clobber (match_operand 2 "register_operand" "=r"))]
9379   "!SIBLING_CALL_P (insn)
9380    && TARGET_SMALL_EXEC
9381    && GET_MODE (operands[2]) == Pmode"
9382   "bras\t%2,%0"
9383   [(set_attr "op_type" "RI")
9384    (set_attr "type"    "jsr")
9385    (set_attr "z196prop" "z196_cracked")])
9386
9387 (define_insn "*brasl"
9388   [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9389          (match_operand 1 "const_int_operand" "n"))
9390    (clobber (match_operand 2 "register_operand" "=r"))]
9391   "!SIBLING_CALL_P (insn)
9392    && TARGET_CPU_ZARCH
9393    && GET_MODE (operands[2]) == Pmode"
9394   "brasl\t%2,%0"
9395   [(set_attr "op_type" "RIL")
9396    (set_attr "type"    "jsr")
9397    (set_attr "z196prop" "z196_cracked")])
9398
9399 (define_insn "*basr"
9400   [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9401          (match_operand 1 "const_int_operand" "n"))
9402    (clobber (match_operand 2 "register_operand" "=r"))]
9403   "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9404 {
9405   if (get_attr_op_type (insn) == OP_TYPE_RR)
9406     return "basr\t%2,%0";
9407   else
9408     return "bas\t%2,%a0";
9409 }
9410   [(set (attr "op_type")
9411         (if_then_else (match_operand 0 "register_operand" "")
9412                       (const_string "RR") (const_string "RX")))
9413    (set_attr "type"  "jsr")
9414    (set_attr "atype" "agen")
9415    (set_attr "z196prop" "z196_cracked")])
9416
9417 ;
9418 ; call_value instruction pattern(s).
9419 ;
9420
9421 (define_expand "call_value"
9422   [(set (match_operand 0 "" "")
9423         (call (match_operand 1 "" "")
9424               (match_operand 2 "" "")))
9425    (use (match_operand 3 "" ""))]
9426   ""
9427 {
9428   s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9429                   gen_rtx_REG (Pmode, RETURN_REGNUM));
9430   DONE;
9431 })
9432
9433 (define_insn "*bras_r"
9434   [(set (match_operand 0 "" "")
9435         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9436               (match_operand:SI 2 "const_int_operand" "n")))
9437    (clobber (match_operand 3 "register_operand" "=r"))]
9438   "!SIBLING_CALL_P (insn)
9439    && TARGET_SMALL_EXEC
9440    && GET_MODE (operands[3]) == Pmode"
9441   "bras\t%3,%1"
9442   [(set_attr "op_type" "RI")
9443    (set_attr "type"    "jsr")
9444    (set_attr "z196prop" "z196_cracked")])
9445
9446 (define_insn "*brasl_r"
9447   [(set (match_operand 0 "" "")
9448         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9449               (match_operand 2 "const_int_operand" "n")))
9450    (clobber (match_operand 3 "register_operand" "=r"))]
9451   "!SIBLING_CALL_P (insn)
9452    && TARGET_CPU_ZARCH
9453    && GET_MODE (operands[3]) == Pmode"
9454   "brasl\t%3,%1"
9455   [(set_attr "op_type" "RIL")
9456    (set_attr "type"    "jsr")
9457    (set_attr "z196prop" "z196_cracked")])
9458
9459 (define_insn "*basr_r"
9460   [(set (match_operand 0 "" "")
9461         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9462               (match_operand 2 "const_int_operand" "n")))
9463    (clobber (match_operand 3 "register_operand" "=r"))]
9464   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9465 {
9466   if (get_attr_op_type (insn) == OP_TYPE_RR)
9467     return "basr\t%3,%1";
9468   else
9469     return "bas\t%3,%a1";
9470 }
9471   [(set (attr "op_type")
9472         (if_then_else (match_operand 1 "register_operand" "")
9473                       (const_string "RR") (const_string "RX")))
9474    (set_attr "type"  "jsr")
9475    (set_attr "atype" "agen")
9476    (set_attr "z196prop" "z196_cracked")])
9477
9478 ;;
9479 ;;- Thread-local storage support.
9480 ;;
9481
9482 (define_expand "get_thread_pointer<mode>"
9483   [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9484   ""
9485   "")
9486
9487 (define_expand "set_thread_pointer<mode>"
9488   [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9489    (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9490   ""
9491   "")
9492
9493 (define_insn "*set_tp"
9494   [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9495   ""
9496   ""
9497   [(set_attr "type" "none")
9498    (set_attr "length" "0")])
9499
9500 (define_insn "*tls_load_64"
9501   [(set (match_operand:DI 0 "register_operand" "=d")
9502         (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9503                     (match_operand:DI 2 "" "")]
9504                    UNSPEC_TLS_LOAD))]
9505   "TARGET_64BIT"
9506   "lg\t%0,%1%J2"
9507   [(set_attr "op_type" "RXE")
9508    (set_attr "z10prop" "z10_fwd_A3")])
9509
9510 (define_insn "*tls_load_31"
9511   [(set (match_operand:SI 0 "register_operand" "=d,d")
9512         (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9513                     (match_operand:SI 2 "" "")]
9514                    UNSPEC_TLS_LOAD))]
9515   "!TARGET_64BIT"
9516   "@
9517    l\t%0,%1%J2
9518    ly\t%0,%1%J2"
9519   [(set_attr "op_type" "RX,RXY")
9520    (set_attr "type" "load")
9521    (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9522
9523 (define_insn "*bras_tls"
9524   [(set (match_operand 0 "" "")
9525         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9526               (match_operand 2 "const_int_operand" "n")))
9527    (clobber (match_operand 3 "register_operand" "=r"))
9528    (use (match_operand 4 "" ""))]
9529   "!SIBLING_CALL_P (insn)
9530    && TARGET_SMALL_EXEC
9531    && GET_MODE (operands[3]) == Pmode"
9532   "bras\t%3,%1%J4"
9533   [(set_attr "op_type" "RI")
9534    (set_attr "type"    "jsr")
9535    (set_attr "z196prop" "z196_cracked")])
9536
9537 (define_insn "*brasl_tls"
9538   [(set (match_operand 0 "" "")
9539         (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9540               (match_operand 2 "const_int_operand" "n")))
9541    (clobber (match_operand 3 "register_operand" "=r"))
9542    (use (match_operand 4 "" ""))]
9543   "!SIBLING_CALL_P (insn)
9544    && TARGET_CPU_ZARCH
9545    && GET_MODE (operands[3]) == Pmode"
9546   "brasl\t%3,%1%J4"
9547   [(set_attr "op_type" "RIL")
9548    (set_attr "type"    "jsr")
9549    (set_attr "z196prop" "z196_cracked")])
9550
9551 (define_insn "*basr_tls"
9552   [(set (match_operand 0 "" "")
9553         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9554               (match_operand 2 "const_int_operand" "n")))
9555    (clobber (match_operand 3 "register_operand" "=r"))
9556    (use (match_operand 4 "" ""))]
9557   "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9558 {
9559   if (get_attr_op_type (insn) == OP_TYPE_RR)
9560     return "basr\t%3,%1%J4";
9561   else
9562     return "bas\t%3,%a1%J4";
9563 }
9564   [(set (attr "op_type")
9565         (if_then_else (match_operand 1 "register_operand" "")
9566                       (const_string "RR") (const_string "RX")))
9567    (set_attr "type"  "jsr")
9568    (set_attr "atype" "agen")
9569    (set_attr "z196prop" "z196_cracked")])
9570
9571 ;;
9572 ;;- Atomic operations
9573 ;;
9574
9575 ;
9576 ; memory barrier patterns.
9577 ;
9578
9579 (define_expand "mem_signal_fence"
9580   [(match_operand:SI 0 "const_int_operand")]            ;; model
9581   ""
9582 {
9583   /* The s390 memory model is strong enough not to require any
9584      barrier in order to synchronize a thread with itself.  */
9585   DONE;
9586 })
9587
9588 (define_expand "mem_thread_fence"
9589   [(match_operand:SI 0 "const_int_operand")]            ;; model
9590   ""
9591 {
9592   /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9593      enough not to require barriers of any kind.  */
9594   if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9595     {
9596       rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9597       MEM_VOLATILE_P (mem) = 1;
9598       emit_insn (gen_mem_thread_fence_1 (mem));
9599     }
9600   DONE;
9601 })
9602
9603 ; Although bcr is superscalar on Z10, this variant will never
9604 ; become part of an execution group.
9605 ; With z196 we can make use of the fast-BCR-serialization facility.
9606 ; This allows for a slightly faster sync which is sufficient for our
9607 ; purposes.
9608 (define_insn "mem_thread_fence_1"
9609   [(set (match_operand:BLK 0 "" "")
9610         (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9611   ""
9612 {
9613   if (TARGET_Z196)
9614     return "bcr\t14,0";
9615   else
9616     return "bcr\t15,0";
9617 }
9618   [(set_attr "op_type" "RR")
9619    (set_attr "mnemonic" "bcr_flush")
9620    (set_attr "z196prop" "z196_alone")])
9621
9622 ;
9623 ; atomic load/store operations
9624 ;
9625
9626 ; Atomic loads need not examine the memory model at all.
9627 (define_expand "atomic_load<mode>"
9628   [(match_operand:DINT 0 "register_operand")    ;; output
9629    (match_operand:DINT 1 "memory_operand")      ;; memory
9630    (match_operand:SI 2 "const_int_operand")]    ;; model
9631   ""
9632 {
9633   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9634     FAIL;
9635
9636   if (<MODE>mode == TImode)
9637     emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9638   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9639     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9640   else
9641     emit_move_insn (operands[0], operands[1]);
9642   DONE;
9643 })
9644
9645 ; Different from movdi_31 in that we want no splitters.
9646 (define_insn "atomic_loaddi_1"
9647   [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9648         (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9649                    UNSPEC_MOVA))]
9650   "!TARGET_ZARCH"
9651   "@
9652    lm\t%0,%M0,%S1
9653    lmy\t%0,%M0,%S1
9654    ld\t%0,%1
9655    ldy\t%0,%1"
9656   [(set_attr "op_type" "RS,RSY,RS,RSY")
9657    (set_attr "type" "lm,lm,floaddf,floaddf")])
9658
9659 (define_insn "atomic_loadti_1"
9660   [(set (match_operand:TI 0 "register_operand" "=r")
9661         (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9662                    UNSPEC_MOVA))]
9663   "TARGET_ZARCH"
9664   "lpq\t%0,%1"
9665   [(set_attr "op_type" "RXY")
9666    (set_attr "type" "other")])
9667
9668 ; Atomic stores must(?) enforce sequential consistency.
9669 (define_expand "atomic_store<mode>"
9670   [(match_operand:DINT 0 "memory_operand")      ;; memory
9671    (match_operand:DINT 1 "register_operand")    ;; input
9672    (match_operand:SI 2 "const_int_operand")]    ;; model
9673   ""
9674 {
9675   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9676
9677   if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9678     FAIL;
9679
9680   if (<MODE>mode == TImode)
9681     emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9682   else if (<MODE>mode == DImode && !TARGET_ZARCH)
9683     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9684   else
9685     emit_move_insn (operands[0], operands[1]);
9686   if (is_mm_seq_cst (model))
9687     emit_insn (gen_mem_thread_fence (operands[2]));
9688   DONE;
9689 })
9690
9691 ; Different from movdi_31 in that we want no splitters.
9692 (define_insn "atomic_storedi_1"
9693   [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9694         (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9695                    UNSPEC_MOVA))]
9696   "!TARGET_ZARCH"
9697   "@
9698    stm\t%1,%N1,%S0
9699    stmy\t%1,%N1,%S0
9700    std %1,%0
9701    stdy %1,%0"
9702   [(set_attr "op_type" "RS,RSY,RS,RSY")
9703    (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9704
9705 (define_insn "atomic_storeti_1"
9706   [(set (match_operand:TI 0 "memory_operand" "=RT")
9707         (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9708                    UNSPEC_MOVA))]
9709   "TARGET_ZARCH"
9710   "stpq\t%1,%0"
9711   [(set_attr "op_type" "RXY")
9712    (set_attr "type" "other")])
9713
9714 ;
9715 ; compare and swap patterns.
9716 ;
9717
9718 (define_expand "atomic_compare_and_swap<mode>"
9719   [(match_operand:SI 0 "register_operand")      ;; bool success output
9720    (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9721    (match_operand:DGPR 2 "memory_operand")      ;; memory
9722    (match_operand:DGPR 3 "register_operand")    ;; expected intput
9723    (match_operand:DGPR 4 "register_operand")    ;; newval intput
9724    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9725    (match_operand:SI 6 "const_int_operand")     ;; success model
9726    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9727   ""
9728 {
9729   rtx cc, cmp, output = operands[1];
9730
9731   if (!register_operand (output, <MODE>mode))
9732     output = gen_reg_rtx (<MODE>mode);
9733
9734   if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9735     FAIL;
9736
9737   emit_insn (gen_atomic_compare_and_swap<mode>_internal
9738              (output, operands[2], operands[3], operands[4]));
9739
9740   /* We deliberately accept non-register operands in the predicate
9741      to ensure the write back to the output operand happens *before*
9742      the store-flags code below.  This makes it easier for combine
9743      to merge the store-flags code with a potential test-and-branch
9744      pattern following (immediately!) afterwards.  */
9745   if (output != operands[1])
9746     emit_move_insn (operands[1], output);
9747
9748   cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9749   cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9750   emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9751   DONE;
9752 })
9753
9754 (define_expand "atomic_compare_and_swap<mode>"
9755   [(match_operand:SI 0 "register_operand")      ;; bool success output
9756    (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9757    (match_operand:HQI 2 "memory_operand")       ;; memory
9758    (match_operand:HQI 3 "general_operand")      ;; expected intput
9759    (match_operand:HQI 4 "general_operand")      ;; newval intput
9760    (match_operand:SI 5 "const_int_operand")     ;; is_weak
9761    (match_operand:SI 6 "const_int_operand")     ;; success model
9762    (match_operand:SI 7 "const_int_operand")]    ;; failure model
9763   ""
9764 {
9765   s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9766                       operands[3], operands[4], INTVAL (operands[5]));
9767   DONE;
9768 })
9769
9770 (define_expand "atomic_compare_and_swap<mode>_internal"
9771   [(parallel
9772      [(set (match_operand:DGPR 0 "register_operand")
9773            (match_operand:DGPR 1 "memory_operand"))
9774       (set (match_dup 1)
9775            (unspec_volatile:DGPR
9776              [(match_dup 1)
9777               (match_operand:DGPR 2 "register_operand")
9778               (match_operand:DGPR 3 "register_operand")]
9779              UNSPECV_CAS))
9780       (set (reg:CCZ1 CC_REGNUM)
9781            (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9782   "")
9783
9784 ; cdsg, csg
9785 (define_insn "*atomic_compare_and_swap<mode>_1"
9786   [(set (match_operand:TDI 0 "register_operand" "=r")
9787         (match_operand:TDI 1 "memory_operand" "+QS"))
9788    (set (match_dup 1)
9789         (unspec_volatile:TDI
9790           [(match_dup 1)
9791            (match_operand:TDI 2 "register_operand" "0")
9792            (match_operand:TDI 3 "register_operand" "r")]
9793           UNSPECV_CAS))
9794    (set (reg:CCZ1 CC_REGNUM)
9795         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9796   "TARGET_ZARCH"
9797   "c<td>sg\t%0,%3,%S1"
9798   [(set_attr "op_type" "RSY")
9799    (set_attr "type"   "sem")])
9800
9801 ; cds, cdsy
9802 (define_insn "*atomic_compare_and_swapdi_2"
9803   [(set (match_operand:DI 0 "register_operand" "=r,r")
9804         (match_operand:DI 1 "memory_operand" "+Q,S"))
9805    (set (match_dup 1)
9806         (unspec_volatile:DI
9807           [(match_dup 1)
9808            (match_operand:DI 2 "register_operand" "0,0")
9809            (match_operand:DI 3 "register_operand" "r,r")]
9810           UNSPECV_CAS))
9811    (set (reg:CCZ1 CC_REGNUM)
9812         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9813   "!TARGET_ZARCH"
9814   "@
9815    cds\t%0,%3,%S1
9816    cdsy\t%0,%3,%S1"
9817   [(set_attr "op_type" "RS,RSY")
9818    (set_attr "type" "sem")])
9819
9820 ; cs, csy
9821 (define_insn "*atomic_compare_and_swapsi_3"
9822   [(set (match_operand:SI 0 "register_operand" "=r,r")
9823         (match_operand:SI 1 "memory_operand" "+Q,S"))
9824    (set (match_dup 1)
9825         (unspec_volatile:SI
9826           [(match_dup 1)
9827            (match_operand:SI 2 "register_operand" "0,0")
9828            (match_operand:SI 3 "register_operand" "r,r")]
9829           UNSPECV_CAS))
9830    (set (reg:CCZ1 CC_REGNUM)
9831         (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9832   ""
9833   "@
9834    cs\t%0,%3,%S1
9835    csy\t%0,%3,%S1"
9836   [(set_attr "op_type" "RS,RSY")
9837    (set_attr "type"   "sem")])
9838
9839 ;
9840 ; Other atomic instruction patterns.
9841 ;
9842
9843 ; z196 load and add, xor, or and and instructions
9844
9845 (define_expand "atomic_fetch_<atomic><mode>"
9846   [(match_operand:GPR 0 "register_operand")             ;; val out
9847    (ATOMIC_Z196:GPR
9848      (match_operand:GPR 1 "memory_operand")             ;; memory
9849      (match_operand:GPR 2 "register_operand"))          ;; val in
9850    (match_operand:SI 3 "const_int_operand")]            ;; model
9851   "TARGET_Z196"
9852 {
9853   if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9854     FAIL;
9855
9856   emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9857              (operands[0], operands[1], operands[2]));
9858   DONE;
9859 })
9860
9861 ; lan, lang, lao, laog, lax, laxg, laa, laag
9862 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9863   [(set (match_operand:GPR 0 "register_operand" "=d")
9864         (match_operand:GPR 1 "memory_operand" "+QS"))
9865    (set (match_dup 1)
9866         (unspec_volatile:GPR
9867          [(ATOMIC_Z196:GPR (match_dup 1)
9868                            (match_operand:GPR 2 "general_operand" "d"))]
9869          UNSPECV_ATOMIC_OP))
9870    (clobber (reg:CC CC_REGNUM))]
9871   "TARGET_Z196"
9872   "la<noxa><g>\t%0,%2,%1"
9873   [(set_attr "op_type" "RSY")
9874    (set_attr "type" "sem")])
9875
9876 ;; For SImode and larger, the optabs.c code will do just fine in
9877 ;; expanding a compare-and-swap loop.  For QI/HImode, we can do
9878 ;; better by expanding our own loop.
9879
9880 (define_expand "atomic_<atomic><mode>"
9881   [(ATOMIC:HQI
9882      (match_operand:HQI 0 "memory_operand")             ;; memory
9883      (match_operand:HQI 1 "general_operand"))           ;; val in
9884    (match_operand:SI 2 "const_int_operand")]            ;; model
9885   ""
9886 {
9887   s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9888                        operands[1], false);
9889   DONE;
9890 })
9891
9892 (define_expand "atomic_fetch_<atomic><mode>"
9893   [(match_operand:HQI 0 "register_operand")             ;; val out
9894    (ATOMIC:HQI
9895      (match_operand:HQI 1 "memory_operand")             ;; memory
9896      (match_operand:HQI 2 "general_operand"))           ;; val in
9897    (match_operand:SI 3 "const_int_operand")]            ;; model
9898   ""
9899 {
9900   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9901                       operands[2], false);
9902   DONE;
9903 })
9904
9905 (define_expand "atomic_<atomic>_fetch<mode>"
9906   [(match_operand:HQI 0 "register_operand")             ;; val out
9907    (ATOMIC:HQI
9908      (match_operand:HQI 1 "memory_operand")             ;; memory
9909      (match_operand:HQI 2 "general_operand"))           ;; val in
9910    (match_operand:SI 3 "const_int_operand")]            ;; model
9911   ""
9912 {
9913   s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9914                       operands[2], true);
9915   DONE;
9916 })
9917
9918 (define_expand "atomic_exchange<mode>"
9919   [(match_operand:HQI 0 "register_operand")             ;; val out
9920    (match_operand:HQI 1 "memory_operand")               ;; memory
9921    (match_operand:HQI 2 "general_operand")              ;; val in
9922    (match_operand:SI 3 "const_int_operand")]            ;; model
9923   ""
9924 {
9925   s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9926                       operands[2], false);
9927   DONE;
9928 })
9929
9930 ;;
9931 ;;- Miscellaneous instructions.
9932 ;;
9933
9934 ;
9935 ; allocate stack instruction pattern(s).
9936 ;
9937
9938 (define_expand "allocate_stack"
9939   [(match_operand 0 "general_operand" "")
9940    (match_operand 1 "general_operand" "")]
9941  "TARGET_BACKCHAIN"
9942 {
9943   rtx temp = gen_reg_rtx (Pmode);
9944
9945   emit_move_insn (temp, s390_back_chain_rtx ());
9946   anti_adjust_stack (operands[1]);
9947   emit_move_insn (s390_back_chain_rtx (), temp);
9948
9949   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9950   DONE;
9951 })
9952
9953
9954 ;
9955 ; setjmp instruction pattern.
9956 ;
9957
9958 (define_expand "builtin_setjmp_receiver"
9959   [(match_operand 0 "" "")]
9960   "flag_pic"
9961 {
9962   emit_insn (s390_load_got ());
9963   emit_use (pic_offset_table_rtx);
9964   DONE;
9965 })
9966
9967 ;; These patterns say how to save and restore the stack pointer.  We need not
9968 ;; save the stack pointer at function level since we are careful to
9969 ;; preserve the backchain.  At block level, we have to restore the backchain
9970 ;; when we restore the stack pointer.
9971 ;;
9972 ;; For nonlocal gotos, we must save both the stack pointer and its
9973 ;; backchain and restore both.  Note that in the nonlocal case, the
9974 ;; save area is a memory location.
9975
9976 (define_expand "save_stack_function"
9977   [(match_operand 0 "general_operand" "")
9978    (match_operand 1 "general_operand" "")]
9979   ""
9980   "DONE;")
9981
9982 (define_expand "restore_stack_function"
9983   [(match_operand 0 "general_operand" "")
9984    (match_operand 1 "general_operand" "")]
9985   ""
9986   "DONE;")
9987
9988 (define_expand "restore_stack_block"
9989   [(match_operand 0 "register_operand" "")
9990    (match_operand 1 "register_operand" "")]
9991   "TARGET_BACKCHAIN"
9992 {
9993   rtx temp = gen_reg_rtx (Pmode);
9994
9995   emit_move_insn (temp, s390_back_chain_rtx ());
9996   emit_move_insn (operands[0], operands[1]);
9997   emit_move_insn (s390_back_chain_rtx (), temp);
9998
9999   DONE;
10000 })
10001
10002 (define_expand "save_stack_nonlocal"
10003   [(match_operand 0 "memory_operand" "")
10004    (match_operand 1 "register_operand" "")]
10005   ""
10006 {
10007   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10008
10009   /* Copy the backchain to the first word, sp to the second and the
10010      literal pool base to the third.  */
10011
10012   rtx save_bc = adjust_address (operands[0], Pmode, 0);
10013   rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10014   rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10015
10016   if (TARGET_BACKCHAIN)
10017     emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10018
10019   emit_move_insn (save_sp, operands[1]);
10020   emit_move_insn (save_bp, base);
10021
10022   DONE;
10023 })
10024
10025 (define_expand "restore_stack_nonlocal"
10026   [(match_operand 0 "register_operand" "")
10027    (match_operand 1 "memory_operand" "")]
10028   ""
10029 {
10030   rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10031   rtx temp = NULL_RTX;
10032
10033   /* Restore the backchain from the first word, sp from the second and the
10034      literal pool base from the third.  */
10035
10036   rtx save_bc = adjust_address (operands[1], Pmode, 0);
10037   rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10038   rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10039
10040   if (TARGET_BACKCHAIN)
10041     temp = force_reg (Pmode, save_bc);
10042
10043   emit_move_insn (base, save_bp);
10044   emit_move_insn (operands[0], save_sp);
10045
10046   if (temp)
10047     emit_move_insn (s390_back_chain_rtx (), temp);
10048
10049   emit_use (base);
10050   DONE;
10051 })
10052
10053 (define_expand "exception_receiver"
10054   [(const_int 0)]
10055   ""
10056 {
10057   s390_set_has_landing_pad_p (true);
10058   DONE;
10059 })
10060
10061 ;
10062 ; nop instruction pattern(s).
10063 ;
10064
10065 (define_insn "nop"
10066   [(const_int 0)]
10067   ""
10068   "lr\t0,0"
10069   [(set_attr "op_type" "RR")
10070    (set_attr "z10prop"  "z10_fr_E1")])
10071
10072 (define_insn "nop1"
10073   [(const_int 1)]
10074   ""
10075   "lr\t1,1"
10076   [(set_attr "op_type" "RR")])
10077
10078 ;;- Undeletable nops (used for hotpatching)
10079
10080 (define_insn "nop_2_byte"
10081   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10082   ""
10083   "nopr\t%%r7"
10084   [(set_attr "op_type" "RR")])
10085
10086 (define_insn "nop_4_byte"
10087   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10088   ""
10089   "nop\t0"
10090   [(set_attr "op_type" "RX")])
10091
10092 (define_insn "nop_6_byte"
10093   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10094   "TARGET_CPU_ZARCH"
10095   "brcl\t0, 0"
10096   [(set_attr "op_type" "RIL")])
10097
10098
10099 ;
10100 ; Special literal pool access instruction pattern(s).
10101 ;
10102
10103 (define_insn "*pool_entry"
10104   [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10105                     UNSPECV_POOL_ENTRY)]
10106   ""
10107 {
10108   machine_mode mode = GET_MODE (PATTERN (insn));
10109   unsigned int align = GET_MODE_BITSIZE (mode);
10110   s390_output_pool_entry (operands[0], mode, align);
10111   return "";
10112 }
10113   [(set (attr "length")
10114         (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10115
10116 (define_insn "pool_align"
10117   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10118                     UNSPECV_POOL_ALIGN)]
10119   ""
10120   ".align\t%0"
10121   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10122
10123 (define_insn "pool_section_start"
10124   [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10125   ""
10126 {
10127   switch_to_section (targetm.asm_out.function_rodata_section
10128                  (current_function_decl));
10129   return "";
10130 }
10131   [(set_attr "length" "0")])
10132
10133 (define_insn "pool_section_end"
10134   [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10135   ""
10136 {
10137   switch_to_section (current_function_section ());
10138   return "";
10139 }
10140   [(set_attr "length" "0")])
10141
10142 (define_insn "main_base_31_small"
10143   [(set (match_operand 0 "register_operand" "=a")
10144         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10145   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10146   "basr\t%0,0"
10147   [(set_attr "op_type" "RR")
10148    (set_attr "type"    "la")
10149    (set_attr "z196prop" "z196_cracked")])
10150
10151 (define_insn "main_base_31_large"
10152   [(set (match_operand 0 "register_operand" "=a")
10153         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10154    (set (pc) (label_ref (match_operand 2 "" "")))]
10155   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10156   "bras\t%0,%2"
10157   [(set_attr "op_type" "RI")
10158    (set_attr "z196prop" "z196_cracked")])
10159
10160 (define_insn "main_base_64"
10161   [(set (match_operand 0 "register_operand" "=a")
10162         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10163   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10164   "larl\t%0,%1"
10165   [(set_attr "op_type" "RIL")
10166    (set_attr "type"    "larl")
10167    (set_attr "z10prop" "z10_fwd_A1")])
10168
10169 (define_insn "main_pool"
10170   [(set (match_operand 0 "register_operand" "=a")
10171         (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10172   "GET_MODE (operands[0]) == Pmode"
10173 {
10174   gcc_unreachable ();
10175 }
10176   [(set (attr "type")
10177         (if_then_else (match_test "TARGET_CPU_ZARCH")
10178                       (const_string "larl") (const_string "la")))])
10179
10180 (define_insn "reload_base_31"
10181   [(set (match_operand 0 "register_operand" "=a")
10182         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10183   "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10184   "basr\t%0,0\;la\t%0,%1-.(%0)"
10185   [(set_attr "length" "6")
10186    (set_attr "type" "la")
10187    (set_attr "z196prop" "z196_cracked")])
10188
10189 (define_insn "reload_base_64"
10190   [(set (match_operand 0 "register_operand" "=a")
10191         (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10192   "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10193   "larl\t%0,%1"
10194   [(set_attr "op_type" "RIL")
10195    (set_attr "type"    "larl")
10196    (set_attr "z10prop" "z10_fwd_A1")])
10197
10198 (define_insn "pool"
10199   [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10200   ""
10201 {
10202   gcc_unreachable ();
10203 }
10204   [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10205
10206 ;;
10207 ;; Insns related to generating the function prologue and epilogue.
10208 ;;
10209
10210
10211 (define_expand "prologue"
10212   [(use (const_int 0))]
10213   ""
10214   "s390_emit_prologue (); DONE;")
10215
10216 (define_expand "epilogue"
10217   [(use (const_int 1))]
10218   ""
10219   "s390_emit_epilogue (false); DONE;")
10220
10221 (define_expand "sibcall_epilogue"
10222   [(use (const_int 0))]
10223   ""
10224   "s390_emit_epilogue (true); DONE;")
10225
10226 ;; A direct return instruction, without using an epilogue.
10227 (define_insn "<code>"
10228   [(ANY_RETURN)]
10229   "s390_can_use_<code>_insn ()"
10230   "br\t%%r14"
10231   [(set_attr "op_type" "RR")
10232    (set_attr "type"    "jsr")
10233    (set_attr "atype"   "agen")])
10234
10235 (define_insn "*return"
10236   [(return)
10237    (use (match_operand 0 "register_operand" "a"))]
10238   "GET_MODE (operands[0]) == Pmode"
10239   "br\t%0"
10240   [(set_attr "op_type" "RR")
10241    (set_attr "type"    "jsr")
10242    (set_attr "atype"   "agen")])
10243
10244
10245 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10246 ;; pointer. This is used for compatibility.
10247
10248 (define_expand "ptr_extend"
10249   [(set (match_operand:DI 0 "register_operand" "=r")
10250         (match_operand:SI 1 "register_operand" "r"))]
10251   "TARGET_64BIT"
10252 {
10253   emit_insn (gen_anddi3 (operands[0],
10254                          gen_lowpart (DImode, operands[1]),
10255                          GEN_INT (0x7fffffff)));
10256   DONE;
10257 })
10258
10259 ;; Instruction definition to expand eh_return macro to support
10260 ;; swapping in special linkage return addresses.
10261
10262 (define_expand "eh_return"
10263   [(use (match_operand 0 "register_operand" ""))]
10264   "TARGET_TPF"
10265 {
10266   s390_emit_tpf_eh_return (operands[0]);
10267   DONE;
10268 })
10269
10270 ;
10271 ; Stack Protector Patterns
10272 ;
10273
10274 (define_expand "stack_protect_set"
10275   [(set (match_operand 0 "memory_operand" "")
10276         (match_operand 1 "memory_operand" ""))]
10277   ""
10278 {
10279 #ifdef TARGET_THREAD_SSP_OFFSET
10280   operands[1]
10281     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10282                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10283 #endif
10284   if (TARGET_64BIT)
10285     emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10286   else
10287     emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10288
10289   DONE;
10290 })
10291
10292 (define_insn "stack_protect_set<mode>"
10293   [(set (match_operand:DSI 0 "memory_operand" "=Q")
10294         (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10295   ""
10296   "mvc\t%O0(%G0,%R0),%S1"
10297   [(set_attr "op_type" "SS")])
10298
10299 (define_expand "stack_protect_test"
10300   [(set (reg:CC CC_REGNUM)
10301         (compare (match_operand 0 "memory_operand" "")
10302                  (match_operand 1 "memory_operand" "")))
10303    (match_operand 2 "" "")]
10304   ""
10305 {
10306   rtx cc_reg, test;
10307 #ifdef TARGET_THREAD_SSP_OFFSET
10308   operands[1]
10309     = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10310                                         GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10311 #endif
10312   if (TARGET_64BIT)
10313     emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10314   else
10315     emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10316
10317   cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10318   test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10319   emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10320   DONE;
10321 })
10322
10323 (define_insn "stack_protect_test<mode>"
10324   [(set (reg:CCZ CC_REGNUM)
10325         (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10326                      (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10327   ""
10328   "clc\t%O0(%G0,%R0),%S1"
10329   [(set_attr "op_type" "SS")])
10330
10331 ; This is used in s390_emit_prologue in order to prevent insns
10332 ; adjusting the stack pointer to be moved over insns writing stack
10333 ; slots using a copy of the stack pointer in a different register.
10334 (define_insn "stack_tie"
10335   [(set (match_operand:BLK 0 "memory_operand" "+m")
10336         (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10337   ""
10338   ""
10339   [(set_attr "length" "0")])
10340
10341
10342 ;
10343 ; Data prefetch patterns
10344 ;
10345
10346 (define_insn "prefetch"
10347   [(prefetch (match_operand 0    "address_operand"   "ZQZRZSZT,X")
10348              (match_operand:SI 1 "const_int_operand" "       n,n")
10349              (match_operand:SI 2 "const_int_operand" "       n,n"))]
10350   "TARGET_Z10"
10351 {
10352   switch (which_alternative)
10353     {
10354       case 0:
10355         return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10356       case 1:
10357         if (larl_operand (operands[0], Pmode))
10358           return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10359       default:
10360
10361         /* This might be reached for symbolic operands with an odd
10362            addend.  We simply omit the prefetch for such rare cases.  */
10363
10364         return "";
10365      }
10366 }
10367   [(set_attr "type" "load,larl")
10368    (set_attr "op_type" "RXY,RIL")
10369    (set_attr "z10prop" "z10_super")
10370    (set_attr "z196prop" "z196_alone")])
10371
10372
10373 ;
10374 ; Byte swap instructions
10375 ;
10376
10377 ; FIXME: There is also mvcin but we cannot use it since src and target
10378 ; may overlap.
10379 (define_insn "bswap<mode>2"
10380   [(set (match_operand:GPR 0            "nonimmediate_operand" "=d, d,RT")
10381         (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))]
10382   "TARGET_CPU_ZARCH"
10383   "@
10384    lrv<g>r\t%0,%1
10385    lrv<g>\t%0,%1
10386    strv<g>\t%1,%0"
10387   [(set_attr "type" "*,load,store")
10388    (set_attr "op_type" "RRE,RXY,RXY")
10389    (set_attr "z10prop" "z10_super")])
10390
10391 (define_insn "bswaphi2"
10392   [(set (match_operand:HI 0           "nonimmediate_operand" "=d, d,RT")
10393         (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))]
10394   "TARGET_CPU_ZARCH"
10395   "@
10396    #
10397    lrvh\t%0,%1
10398    strvh\t%1,%0"
10399   [(set_attr "type" "*,load,store")
10400    (set_attr "op_type" "RRE,RXY,RXY")
10401    (set_attr "z10prop" "z10_super")])
10402
10403 (define_split
10404   [(set (match_operand:HI 0           "register_operand" "")
10405         (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10406   "TARGET_CPU_ZARCH"
10407   [(set (match_dup 2) (bswap:SI (match_dup 3)))
10408    (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10409 {
10410   operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10411   operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10412 })
10413
10414
10415 ;
10416 ; Population count instruction
10417 ;
10418
10419 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10420 ; portions and stores the result in the corresponding bytes in op0.
10421 (define_insn "*popcount<mode>"
10422   [(set (match_operand:INT 0 "register_operand" "=d")
10423         (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10424    (clobber (reg:CC CC_REGNUM))]
10425   "TARGET_Z196"
10426   "popcnt\t%0,%1"
10427   [(set_attr "op_type" "RRE")])
10428
10429 (define_expand "popcountdi2"
10430   [; popcnt op0, op1
10431    (parallel [(set (match_operand:DI 0 "register_operand" "")
10432                    (unspec:DI [(match_operand:DI 1 "register_operand")]
10433                               UNSPEC_POPCNT))
10434               (clobber (reg:CC CC_REGNUM))])
10435    ; sllg op2, op0, 32
10436    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10437    ; agr op0, op2
10438    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10439               (clobber (reg:CC CC_REGNUM))])
10440    ; sllg op2, op0, 16
10441    (set (match_dup 2)
10442         (ashift:DI (match_dup 0) (const_int 16)))
10443    ; agr op0, op2
10444    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10445               (clobber (reg:CC CC_REGNUM))])
10446    ; sllg op2, op0, 8
10447    (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10448    ; agr op0, op2
10449    (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10450               (clobber (reg:CC CC_REGNUM))])
10451    ; srlg op0, op0, 56
10452    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10453   "TARGET_Z196 && TARGET_64BIT"
10454   "operands[2] = gen_reg_rtx (DImode);")
10455
10456 (define_expand "popcountsi2"
10457   [; popcnt op0, op1
10458    (parallel [(set (match_operand:SI 0 "register_operand" "")
10459                    (unspec:SI [(match_operand:SI 1 "register_operand")]
10460                               UNSPEC_POPCNT))
10461               (clobber (reg:CC CC_REGNUM))])
10462    ; sllk op2, op0, 16
10463    (set (match_dup 2)
10464         (ashift:SI (match_dup 0) (const_int 16)))
10465    ; ar op0, op2
10466    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10467               (clobber (reg:CC CC_REGNUM))])
10468    ; sllk op2, op0, 8
10469    (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10470    ; ar op0, op2
10471    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10472               (clobber (reg:CC CC_REGNUM))])
10473    ; srl op0, op0, 24
10474    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10475   "TARGET_Z196"
10476   "operands[2] = gen_reg_rtx (SImode);")
10477
10478 (define_expand "popcounthi2"
10479   [; popcnt op0, op1
10480    (parallel [(set (match_operand:HI 0 "register_operand" "")
10481                    (unspec:HI [(match_operand:HI 1 "register_operand")]
10482                               UNSPEC_POPCNT))
10483               (clobber (reg:CC CC_REGNUM))])
10484    ; sllk op2, op0, 8
10485    (set (match_dup 2)
10486         (ashift:SI (match_dup 0) (const_int 8)))
10487    ; ar op0, op2
10488    (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10489               (clobber (reg:CC CC_REGNUM))])
10490    ; srl op0, op0, 8
10491    (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10492   "TARGET_Z196"
10493   "operands[2] = gen_reg_rtx (SImode);")
10494
10495 (define_expand "popcountqi2"
10496   [; popcnt op0, op1
10497    (parallel [(set (match_operand:QI 0 "register_operand" "")
10498                    (unspec:QI [(match_operand:QI 1 "register_operand")]
10499                               UNSPEC_POPCNT))
10500               (clobber (reg:CC CC_REGNUM))])]
10501   "TARGET_Z196"
10502   "")
10503
10504 ;;
10505 ;;- Copy sign instructions
10506 ;;
10507
10508 (define_insn "copysign<mode>3"
10509   [(set (match_operand:FP 0 "register_operand" "=f")
10510       (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10511                   (match_operand:FP 2 "register_operand" "f")]
10512                   UNSPEC_COPYSIGN))]
10513   "TARGET_Z196"
10514   "cpsdr\t%0,%2,%1"
10515   [(set_attr "op_type"  "RRF")
10516    (set_attr "type"     "fsimp<mode>")])
10517
10518
10519 ;;
10520 ;;- Transactional execution instructions
10521 ;;
10522
10523 ; This splitter helps combine to make use of CC directly when
10524 ; comparing the integer result of a tbegin builtin with a constant.
10525 ; The unspec is already removed by canonicalize_comparison. So this
10526 ; splitters only job is to turn the PARALLEL into separate insns
10527 ; again.  Unfortunately this only works with the very first cc/int
10528 ; compare since combine is not able to deal with data flow across
10529 ; basic block boundaries.
10530
10531 ; It needs to be an insn pattern as well since combine does not apply
10532 ; the splitter directly.  Combine would only use it if it actually
10533 ; would reduce the number of instructions.
10534 (define_insn_and_split "*ccraw_to_int"
10535   [(set (pc)
10536         (if_then_else
10537          (match_operator 0 "s390_eqne_operator"
10538                          [(reg:CCRAW CC_REGNUM)
10539                           (match_operand 1 "const_int_operand" "")])
10540          (label_ref (match_operand 2 "" ""))
10541          (pc)))
10542    (set (match_operand:SI 3 "register_operand" "=d")
10543         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10544   ""
10545   "#"
10546   ""
10547   [(set (match_dup 3)
10548         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10549    (set (pc)
10550         (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10551                       (label_ref (match_dup 2))
10552                       (pc)))]
10553   "")
10554
10555 ; Non-constrained transaction begin
10556
10557 (define_expand "tbegin"
10558   [(match_operand:SI 0 "register_operand" "")
10559    (match_operand:BLK 1 "memory_operand" "")]
10560   "TARGET_HTM"
10561 {
10562   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10563   DONE;
10564 })
10565
10566 (define_expand "tbegin_nofloat"
10567   [(match_operand:SI 0 "register_operand" "")
10568    (match_operand:BLK 1 "memory_operand" "")]
10569   "TARGET_HTM"
10570 {
10571   s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10572   DONE;
10573 })
10574
10575 (define_expand "tbegin_retry"
10576   [(match_operand:SI 0 "register_operand" "")
10577    (match_operand:BLK 1 "memory_operand" "")
10578    (match_operand:SI 2 "general_operand" "")]
10579   "TARGET_HTM"
10580 {
10581   s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10582   DONE;
10583 })
10584
10585 (define_expand "tbegin_retry_nofloat"
10586   [(match_operand:SI 0 "register_operand" "")
10587    (match_operand:BLK 1 "memory_operand" "")
10588    (match_operand:SI 2 "general_operand" "")]
10589   "TARGET_HTM"
10590 {
10591   s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10592   DONE;
10593 })
10594
10595 ; Clobber VRs since they don't get restored
10596 (define_insn "tbegin_1_z13"
10597   [(set (reg:CCRAW CC_REGNUM)
10598         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10599                                UNSPECV_TBEGIN))
10600    (set (match_operand:BLK 1 "memory_operand" "=Q")
10601         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10602    (clobber (reg:TI 16)) (clobber (reg:TI 38))
10603    (clobber (reg:TI 17)) (clobber (reg:TI 39))
10604    (clobber (reg:TI 18)) (clobber (reg:TI 40))
10605    (clobber (reg:TI 19)) (clobber (reg:TI 41))
10606    (clobber (reg:TI 20)) (clobber (reg:TI 42))
10607    (clobber (reg:TI 21)) (clobber (reg:TI 43))
10608    (clobber (reg:TI 22)) (clobber (reg:TI 44))
10609    (clobber (reg:TI 23)) (clobber (reg:TI 45))
10610    (clobber (reg:TI 24)) (clobber (reg:TI 46))
10611    (clobber (reg:TI 25)) (clobber (reg:TI 47))
10612    (clobber (reg:TI 26)) (clobber (reg:TI 48))
10613    (clobber (reg:TI 27)) (clobber (reg:TI 49))
10614    (clobber (reg:TI 28)) (clobber (reg:TI 50))
10615    (clobber (reg:TI 29)) (clobber (reg:TI 51))
10616    (clobber (reg:TI 30)) (clobber (reg:TI 52))
10617    (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10618 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10619 ; not supposed to be used for immediates (see genpreds.c).
10620   "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10621   "tbegin\t%1,%x0"
10622   [(set_attr "op_type" "SIL")])
10623
10624 (define_insn "tbegin_1"
10625   [(set (reg:CCRAW CC_REGNUM)
10626         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10627                                UNSPECV_TBEGIN))
10628    (set (match_operand:BLK 1 "memory_operand" "=Q")
10629         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10630    (clobber (reg:DF 16))
10631    (clobber (reg:DF 17))
10632    (clobber (reg:DF 18))
10633    (clobber (reg:DF 19))
10634    (clobber (reg:DF 20))
10635    (clobber (reg:DF 21))
10636    (clobber (reg:DF 22))
10637    (clobber (reg:DF 23))
10638    (clobber (reg:DF 24))
10639    (clobber (reg:DF 25))
10640    (clobber (reg:DF 26))
10641    (clobber (reg:DF 27))
10642    (clobber (reg:DF 28))
10643    (clobber (reg:DF 29))
10644    (clobber (reg:DF 30))
10645    (clobber (reg:DF 31))]
10646 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10647 ; not supposed to be used for immediates (see genpreds.c).
10648   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10649   "tbegin\t%1,%x0"
10650   [(set_attr "op_type" "SIL")])
10651
10652 ; Same as above but without the FPR clobbers
10653 (define_insn "tbegin_nofloat_1"
10654   [(set (reg:CCRAW CC_REGNUM)
10655         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10656                                UNSPECV_TBEGIN))
10657    (set (match_operand:BLK 1 "memory_operand" "=Q")
10658         (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10659   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10660   "tbegin\t%1,%x0"
10661   [(set_attr "op_type" "SIL")])
10662
10663
10664 ; Constrained transaction begin
10665
10666 (define_expand "tbeginc"
10667   [(set (reg:CCRAW CC_REGNUM)
10668         (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10669                                UNSPECV_TBEGINC))]
10670   "TARGET_HTM"
10671   "")
10672
10673 (define_insn "*tbeginc_1"
10674   [(set (reg:CCRAW CC_REGNUM)
10675         (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10676                                UNSPECV_TBEGINC))]
10677   "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10678   "tbeginc\t0,%x0"
10679   [(set_attr "op_type" "SIL")])
10680
10681 ; Transaction end
10682
10683 (define_expand "tend"
10684   [(set (reg:CCRAW CC_REGNUM)
10685         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10686    (set (match_operand:SI 0 "register_operand" "")
10687         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10688   "TARGET_HTM"
10689   "")
10690
10691 (define_insn "*tend_1"
10692   [(set (reg:CCRAW CC_REGNUM)
10693         (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10694   "TARGET_HTM"
10695   "tend"
10696   [(set_attr "op_type" "S")])
10697
10698 ; Transaction abort
10699
10700 (define_expand "tabort"
10701   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
10702                     UNSPECV_TABORT)]
10703   "TARGET_HTM && operands != NULL"
10704 {
10705   if (CONST_INT_P (operands[0])
10706       && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10707     {
10708       error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10709              ".  Values in range 0 through 255 are reserved.",
10710              INTVAL (operands[0]));
10711       FAIL;
10712     }
10713 })
10714
10715 (define_insn "*tabort_1"
10716   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
10717                     UNSPECV_TABORT)]
10718   "TARGET_HTM && operands != NULL"
10719   "tabort\t%Y0"
10720   [(set_attr "op_type" "S")])
10721
10722 (define_insn "*tabort_1_plus"
10723   [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand"  "a")
10724                               (match_operand:SI 1 "const_int_operand" "J"))]
10725                     UNSPECV_TABORT)]
10726   "TARGET_HTM && operands != NULL
10727    && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
10728   "tabort\t%1(%0)"
10729   [(set_attr "op_type" "S")])
10730
10731 ; Transaction extract nesting depth
10732
10733 (define_insn "etnd"
10734   [(set (match_operand:SI 0 "register_operand" "=d")
10735         (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10736   "TARGET_HTM"
10737   "etnd\t%0"
10738   [(set_attr "op_type" "RRE")])
10739
10740 ; Non-transactional store
10741
10742 (define_insn "ntstg"
10743   [(set (match_operand:DI 0 "memory_operand" "=RT")
10744         (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10745                             UNSPECV_NTSTG))]
10746   "TARGET_HTM"
10747   "ntstg\t%1,%0"
10748   [(set_attr "op_type" "RXY")])
10749
10750 ; Transaction perform processor assist
10751
10752 (define_expand "tx_assist"
10753   [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10754                      (reg:SI GPR0_REGNUM)
10755                      (const_int 1)]
10756                     UNSPECV_PPA)]
10757   "TARGET_HTM"
10758   "")
10759
10760 (define_insn "*ppa"
10761   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10762                      (match_operand:SI 1 "register_operand" "d")
10763                      (match_operand 2 "const_int_operand" "I")]
10764                     UNSPECV_PPA)]
10765   "TARGET_HTM && INTVAL (operands[2]) < 16"
10766   "ppa\t%0,%1,%2"
10767   [(set_attr "op_type" "RRF")])
10768
10769
10770 ; Set and get floating point control register
10771
10772 (define_insn "sfpc"
10773   [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10774                     UNSPECV_SFPC)]
10775   "TARGET_HARD_FLOAT"
10776   "sfpc\t%0")
10777
10778 (define_insn "efpc"
10779   [(set (match_operand:SI 0 "register_operand" "=d")
10780         (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10781   "TARGET_HARD_FLOAT"
10782   "efpc\t%0")
10783
10784
10785 ; Load count to block boundary
10786
10787 (define_insn "lcbb"
10788   [(set (match_operand:SI             0 "register_operand"  "=d")
10789         (unspec:SI [(match_operand    1 "address_operand" "ZQZR")
10790                     (match_operand:SI 2 "immediate_operand"  "C")] UNSPEC_LCBB))
10791    (clobber (reg:CC CC_REGNUM))]
10792   "TARGET_Z13"
10793   "lcbb\t%0,%a1,%b2"
10794   [(set_attr "op_type" "VRX")])
10795
10796 ; Handle -fsplit-stack.
10797
10798 (define_expand "split_stack_prologue"
10799   [(const_int 0)]
10800   ""
10801 {
10802   s390_expand_split_stack_prologue ();
10803   DONE;
10804 })
10805
10806 ;; If there are operand 0 bytes available on the stack, jump to
10807 ;; operand 1.
10808
10809 (define_expand "split_stack_space_check"
10810   [(set (pc) (if_then_else
10811               (ltu (minus (reg 15)
10812                           (match_operand 0 "register_operand"))
10813                    (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
10814               (label_ref (match_operand 1))
10815               (pc)))]
10816   ""
10817 {
10818   /* Offset from thread pointer to __private_ss.  */
10819   int psso = TARGET_64BIT ? 0x38 : 0x20;
10820   rtx tp = s390_get_thread_pointer ();
10821   rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
10822   rtx reg = gen_reg_rtx (Pmode);
10823   rtx cc;
10824   if (TARGET_64BIT)
10825     emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
10826   else
10827     emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
10828   cc = s390_emit_compare (GT, reg, guard);
10829   s390_emit_jump (operands[1], cc);
10830
10831   DONE;
10832 })
10833
10834 ;; __morestack parameter block for split stack prologue.  Parameters are:
10835 ;; parameter block label, label to be called by __morestack, frame size,
10836 ;; stack parameter size.
10837
10838 (define_insn "split_stack_data"
10839   [(unspec_volatile [(match_operand 0 "" "X")
10840                      (match_operand 1 "" "X")
10841                      (match_operand 2 "const_int_operand" "X")
10842                      (match_operand 3 "const_int_operand" "X")]
10843                     UNSPECV_SPLIT_STACK_DATA)]
10844   "TARGET_CPU_ZARCH"
10845 {
10846   switch_to_section (targetm.asm_out.function_rodata_section
10847                  (current_function_decl));
10848
10849   if (TARGET_64BIT)
10850     output_asm_insn (".align\t8", operands);
10851   else
10852     output_asm_insn (".align\t4", operands);
10853   (*targetm.asm_out.internal_label) (asm_out_file, "L",
10854                                      CODE_LABEL_NUMBER (operands[0]));
10855   if (TARGET_64BIT)
10856     {
10857       output_asm_insn (".quad\t%2", operands);
10858       output_asm_insn (".quad\t%3", operands);
10859       output_asm_insn (".quad\t%1-%0", operands);
10860     }
10861   else
10862     {
10863       output_asm_insn (".long\t%2", operands);
10864       output_asm_insn (".long\t%3", operands);
10865       output_asm_insn (".long\t%1-%0", operands);
10866     }
10867
10868   switch_to_section (current_function_section ());
10869   return "";
10870 }
10871   [(set_attr "length" "0")])
10872
10873
10874 ;; A jg with minimal fuss for use in split stack prologue.
10875
10876 (define_expand "split_stack_call"
10877   [(match_operand 0 "bras_sym_operand" "X")
10878    (match_operand 1 "" "")]
10879   "TARGET_CPU_ZARCH"
10880 {
10881   if (TARGET_64BIT)
10882     emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
10883   else
10884     emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
10885   DONE;
10886 })
10887
10888 (define_insn "split_stack_call_<mode>"
10889   [(set (pc) (label_ref (match_operand 1 "" "")))
10890    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
10891                                     (reg:P 1)]
10892                                    UNSPECV_SPLIT_STACK_CALL))]
10893   "TARGET_CPU_ZARCH"
10894   "jg\t%0"
10895   [(set_attr "op_type" "RIL")
10896    (set_attr "type"  "branch")])
10897
10898 ;; Also a conditional one.
10899
10900 (define_expand "split_stack_cond_call"
10901   [(match_operand 0 "bras_sym_operand" "X")
10902    (match_operand 1 "" "")
10903    (match_operand 2 "" "")]
10904   "TARGET_CPU_ZARCH"
10905 {
10906   if (TARGET_64BIT)
10907     emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
10908   else
10909     emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
10910   DONE;
10911 })
10912
10913 (define_insn "split_stack_cond_call_<mode>"
10914   [(set (pc)
10915         (if_then_else
10916           (match_operand 1 "" "")
10917           (label_ref (match_operand 2 "" ""))
10918           (pc)))
10919    (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
10920                                     (reg:P 1)]
10921                                    UNSPECV_SPLIT_STACK_CALL))]
10922   "TARGET_CPU_ZARCH"
10923   "jg%C1\t%0"
10924   [(set_attr "op_type" "RIL")
10925    (set_attr "type"  "branch")])