1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2016 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; The right hand side of an setmem
76 ; GOT/PLT and lt-relative accesses
97 ; TLS relocation specifiers
113 ; Stack Smashing Protector
117 ; Split stack support
120 ; Test Data Class (TDC)
132 UNSPEC_FPINT_NEARBYINT
141 UNSPEC_VEC_SMULT_EVEN
142 UNSPEC_VEC_UMULT_EVEN
156 UNSPEC_VEC_INSERT_AND_ZERO
157 UNSPEC_VEC_LOAD_BNDRY
162 UNSPEC_VEC_PACK_SATURATE
163 UNSPEC_VEC_PACK_SATURATE_CC
164 UNSPEC_VEC_PACK_SATURATE_GENCC
165 UNSPEC_VEC_PACK_UNSIGNED_SATURATE
166 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
178 UNSPEC_VEC_ADDEC_U128
183 UNSPEC_VEC_GFMSUM_128
184 UNSPEC_VEC_GFMSUM_ACCUM
185 UNSPEC_VEC_GFMSUM_ACCUM_128
202 UNSPEC_VEC_SUBEC_U128
236 ;; UNSPEC_VOLATILE usage
239 (define_c_enum "unspecv" [
261 ; Hotpatching (unremovable NOPs)
266 ; Transactional Execution support
276 ; Set and get floating point control register
280 ; Split stack support
281 UNSPECV_SPLIT_STACK_CALL
282 UNSPECV_SPLIT_STACK_DATA
289 ; Registers with special meaning
293 ; Sibling call register.
295 ; Literal pool base register.
297 ; Return address register.
299 ; Stack pointer register.
301 ; Condition code register.
303 ; Thread local storage pointer register.
307 ; Hardware register names
311 ; General purpose registers
316 ; Floating point registers.
340 ; Rounding modes for binary floating point numbers
343 (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
344 (BFP_RND_PREP_FOR_SHORT_PREC 3)
345 (BFP_RND_NEAREST_TIE_TO_EVEN 4)
347 (BFP_RND_TOWARD_INF 6)
348 (BFP_RND_TOWARD_MINF 7)])
350 ; Rounding modes for decimal floating point numbers
351 ; 1-7 were introduced with the floating point extension facility
352 ; available with z196
353 ; With these rounding modes (1-7) a quantum exception might occur
354 ; which is suppressed for the other modes.
357 (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
358 (DFP_RND_CURRENT_QUANTEXC 2)
359 (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3)
360 (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4)
361 (DFP_RND_TOWARD_0_QUANTEXC 5)
362 (DFP_RND_TOWARD_INF_QUANTEXC 6)
363 (DFP_RND_TOWARD_MINF_QUANTEXC 7)
364 (DFP_RND_NEAREST_TIE_TO_EVEN 8)
366 (DFP_RND_TOWARD_INF 10)
367 (DFP_RND_TOWARD_MINF 11)
368 (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12)
369 (DFP_RND_NEAREST_TIE_TO_0 13)
370 (DFP_RND_AWAY_FROM_0 14)
371 (DFP_RND_PREP_FOR_SHORT_PREC 15)])
374 ;; PFPO GPR0 argument format
379 ; PFPO operation type
380 (PFPO_CONVERT 0x1000000)
382 (PFPO_OP_TYPE_SF 0x5)
383 (PFPO_OP_TYPE_DF 0x6)
384 (PFPO_OP_TYPE_TF 0x7)
385 (PFPO_OP_TYPE_SD 0x8)
386 (PFPO_OP_TYPE_DD 0x9)
387 (PFPO_OP_TYPE_TD 0xa)
388 ; Bitposition of operand types
389 (PFPO_OP0_TYPE_SHIFT 16)
390 (PFPO_OP1_TYPE_SHIFT 8)
393 ; Immediate operands for tbegin and tbeginc
394 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
395 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
397 ;; Instruction operand type as used in the Principles of Operation.
398 ;; Used to determine defaults for length and other attribute values.
400 (define_attr "op_type"
401 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
404 ;; Instruction type attribute used for scheduling.
406 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
407 cs,vs,store,sem,idiv,
408 imulhi,imulsi,imuldi,
409 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
410 floadtf,floaddf,floadsf,fstoredf,fstoresf,
411 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
412 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
414 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
415 itoftf, itofdf, itofsf, itofdd, itoftd,
416 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
417 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
419 (cond [(eq_attr "op_type" "NN") (const_string "other")
420 (eq_attr "op_type" "SS") (const_string "cs")]
421 (const_string "integer")))
423 ;; Another attribute used for scheduling purposes:
424 ;; agen: Instruction uses the address generation unit
425 ;; reg: Instruction does not use the agen unit
427 (define_attr "atype" "agen,reg"
428 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
430 (const_string "agen")))
432 ;; Properties concerning Z10 execution grouping and value forwarding.
433 ;; z10_super: instruction is superscalar.
434 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
435 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
436 ;; target register. It can forward this value to a second instruction that reads
437 ;; the same register if that second instruction is issued in the same group.
438 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
439 ;; instruction in the S pipe writes to the register, then the T instruction
440 ;; can immediately read the new value.
441 ;; z10_fr: union of Z10_fwd and z10_rec.
442 ;; z10_c: second operand of instruction is a register and read with complemented bits.
444 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
447 (define_attr "z10prop" "none,
448 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
449 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
451 z10_fr, z10_fr_A3, z10_fr_E1,
453 (const_string "none"))
455 ;; Properties concerning Z196 decoding
456 ;; z196_alone: must group alone
457 ;; z196_end: ends a group
458 ;; z196_cracked: instruction is cracked or expanded
459 (define_attr "z196prop" "none,
460 z196_alone, z196_ends,
462 (const_string "none"))
464 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
468 (define_attr "length" ""
469 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
470 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
474 ;; Processor type. This attribute must exactly match the processor_type
475 ;; enumeration in s390.h. The current machine description does not
476 ;; distinguish between g5 and g6, but there are differences between the two
477 ;; CPUs could in theory be modeled.
479 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
480 (const (symbol_ref "s390_tune_attr")))
482 (define_attr "cpu_facility"
483 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec,z13"
484 (const_string "standard"))
486 (define_attr "enabled" ""
487 (cond [(eq_attr "cpu_facility" "standard")
490 (and (eq_attr "cpu_facility" "ieee")
491 (match_test "TARGET_CPU_IEEE_FLOAT"))
494 (and (eq_attr "cpu_facility" "zarch")
495 (match_test "TARGET_ZARCH"))
498 (and (eq_attr "cpu_facility" "longdisp")
499 (match_test "TARGET_LONG_DISPLACEMENT"))
502 (and (eq_attr "cpu_facility" "extimm")
503 (match_test "TARGET_EXTIMM"))
506 (and (eq_attr "cpu_facility" "dfp")
507 (match_test "TARGET_DFP"))
510 (and (eq_attr "cpu_facility" "cpu_zarch")
511 (match_test "TARGET_CPU_ZARCH"))
514 (and (eq_attr "cpu_facility" "z10")
515 (match_test "TARGET_Z10"))
518 (and (eq_attr "cpu_facility" "z196")
519 (match_test "TARGET_Z196"))
522 (and (eq_attr "cpu_facility" "zEC12")
523 (match_test "TARGET_ZEC12"))
526 (and (eq_attr "cpu_facility" "vec")
527 (match_test "TARGET_VX"))
530 (and (eq_attr "cpu_facility" "z13")
531 (match_test "TARGET_Z13"))
536 ;; Pipeline description for z900. For lack of anything better,
537 ;; this description is also used for the g5 and g6.
540 ;; Pipeline description for z990, z9-109 and z9-ec.
543 ;; Pipeline description for z10
546 ;; Pipeline description for z196
549 ;; Pipeline description for zEC12
552 ;; Pipeline description for z13
556 (include "predicates.md")
558 ;; Constraint definitions
559 (include "constraints.md")
566 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
568 ;; These mode iterators allow floating point patterns to be generated from the
570 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
571 (SD "TARGET_HARD_DFP")])
572 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
573 (define_mode_iterator BFP [TF DF SF])
574 (define_mode_iterator DFP [TD DD])
575 (define_mode_iterator DFP_ALL [TD DD SD])
576 (define_mode_iterator DSF [DF SF])
577 (define_mode_iterator SD_SF [SF SD])
578 (define_mode_iterator DD_DF [DF DD])
579 (define_mode_iterator TD_TF [TF TD])
581 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
582 ;; from the same template.
583 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
584 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
585 (define_mode_iterator DSI [DI SI])
586 (define_mode_iterator TDI [TI DI])
588 ;; These mode iterators allow :P to be used for patterns that operate on
589 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
590 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
592 ;; These macros refer to the actual word_mode of the configuration.
593 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
594 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
595 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
597 ;; Used by the umul pattern to express modes having half the size.
598 (define_mode_attr DWH [(TI "DI") (DI "SI")])
599 (define_mode_attr dwh [(TI "di") (DI "si")])
601 ;; This mode iterator allows the QI and HI patterns to be defined from
602 ;; the same template.
603 (define_mode_iterator HQI [HI QI])
605 ;; This mode iterator allows the integer patterns to be defined from the
607 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
608 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
610 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
611 ;; the same template.
612 (define_code_iterator SHIFT [ashift lshiftrt])
614 ;; This iterator allows r[ox]sbg to be defined with the same template
615 (define_code_iterator IXOR [ior xor])
617 ;; This iterator is used to expand the patterns for the nearest
618 ;; integer functions.
619 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
620 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
621 UNSPEC_FPINT_NEARBYINT])
622 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
623 (UNSPEC_FPINT_BTRUNC "btrunc")
624 (UNSPEC_FPINT_ROUND "round")
625 (UNSPEC_FPINT_CEIL "ceil")
626 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
627 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
628 (UNSPEC_FPINT_BTRUNC "5")
629 (UNSPEC_FPINT_ROUND "1")
630 (UNSPEC_FPINT_CEIL "6")
631 (UNSPEC_FPINT_NEARBYINT "0")])
633 ;; This iterator and attribute allow to combine most atomic operations.
634 (define_code_iterator ATOMIC [and ior xor plus minus mult])
635 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
636 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
637 (plus "add") (minus "sub") (mult "nand")])
638 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
640 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
641 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
642 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
644 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
645 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
647 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
649 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
650 ;; Likewise for "<RXe>".
651 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
652 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
654 ;; The decimal floating point variants of add, sub, div and mul support 3
655 ;; fp register operands. The following attributes allow to merge the bfp and
656 ;; dfp variants in a single insn definition.
658 ;; These mode attributes are supposed to be used in the `enabled' insn
659 ;; attribute to disable certain alternatives for certain modes.
660 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
661 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
662 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
663 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
664 (TD "0") (DD "0") (DD "0")
665 (TI "0") (DI "*") (SI "0")])
667 ;; This attribute is used in the operand constraint list
668 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
669 ;; TFmode values are represented by a fp register pair. Since the
670 ;; sign bit instructions only handle single source and target fp registers
671 ;; these instructions can only be used for TFmode values if the source and
672 ;; target operand uses the same fp register.
673 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
675 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
676 ;; within instruction mnemonics.
677 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
679 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
680 ;; modes and to an empty string for bfp modes.
681 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
683 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
684 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
685 ;; version only operates on one register.
686 (define_mode_attr d0 [(DI "d") (SI "0")])
688 ;; In combination with d0 this allows to combine instructions of which the 31bit
689 ;; version only operates on one register. The DImode version needs an additional
690 ;; register for the assembler output.
691 (define_mode_attr 1 [(DI "%1,") (SI "")])
693 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
694 ;; 'ashift' and "srdl" in 'lshiftrt'.
695 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
697 ;; In SHIFT templates, this attribute holds the correct standard name for the
698 ;; pattern itself and the corresponding function calls.
699 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
701 ;; This attribute handles differences in the instruction 'type' and will result
702 ;; in "RRE" for DImode and "RR" for SImode.
703 (define_mode_attr E [(DI "E") (SI "")])
705 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
706 ;; to result in "RXY" for DImode and "RX" for SImode.
707 (define_mode_attr Y [(DI "Y") (SI "")])
709 ;; This attribute handles differences in the instruction 'type' and will result
710 ;; in "RSE" for TImode and "RS" for DImode.
711 (define_mode_attr TE [(TI "E") (DI "")])
713 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
714 ;; and "lcr" in SImode.
715 (define_mode_attr g [(DI "g") (SI "")])
717 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
718 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
719 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
720 ;; variant for long displacements.
721 (define_mode_attr y [(DI "g") (SI "y")])
723 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
724 ;; and "cds" in DImode.
725 (define_mode_attr tg [(TI "g") (DI "")])
727 ;; In TDI templates, a string like "c<d>sg".
728 (define_mode_attr td [(TI "d") (DI "")])
730 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
731 ;; and "cfdbr" in SImode.
732 (define_mode_attr gf [(DI "g") (SI "f")])
734 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
735 ;; and sllk for SI. This way it is possible to merge the new z196 SI
736 ;; 3 operands shift instructions into the existing patterns.
737 (define_mode_attr gk [(DI "g") (SI "k")])
739 ;; ICM mask required to load MODE value into the lowest subreg
740 ;; of a SImode register.
741 (define_mode_attr icm_lo [(HI "3") (QI "1")])
743 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
744 ;; HImode and "llgc" in QImode.
745 (define_mode_attr hc [(HI "h") (QI "c")])
747 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
749 (define_mode_attr DBL [(DI "TI") (SI "DI")])
751 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
752 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
753 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
755 ;; Maximum unsigned integer that fits in MODE.
756 (define_mode_attr max_uint [(HI "65535") (QI "255")])
758 ;; Start and end field computations for RISBG et al.
759 (define_mode_attr bfstart [(DI "s") (SI "t")])
760 (define_mode_attr bfend [(DI "e") (SI "f")])
762 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
763 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
765 ;; In place of GET_MODE_SIZE (<MODE>mode)
766 (define_mode_attr modesize [(DI "8") (SI "4")])
768 ;; Allow return and simple_return to be defined from a single template.
769 (define_code_iterator ANY_RETURN [return simple_return])
773 ; Condition code modes generated by vector fp comparisons. These will
774 ; be used also in single element mode.
775 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
776 ; Used with VFCMP to expand part of the mnemonic
777 ; For fp we have a mismatch: eq in the insn name - e in asm
778 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
779 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
781 ;; Subst pattern definitions
784 (include "vector.md")
787 ;;- Compare instructions.
790 ; Test-under-Mask instructions
792 (define_insn "*tmqi_mem"
793 [(set (reg CC_REGNUM)
794 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
795 (match_operand:QI 1 "immediate_operand" "n,n"))
796 (match_operand:QI 2 "immediate_operand" "n,n")))]
797 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
801 [(set_attr "op_type" "SI,SIY")
802 (set_attr "cpu_facility" "*,longdisp")
803 (set_attr "z10prop" "z10_super,z10_super")])
805 (define_insn "*tmdi_reg"
806 [(set (reg CC_REGNUM)
807 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
808 (match_operand:DI 1 "immediate_operand"
809 "N0HD0,N1HD0,N2HD0,N3HD0"))
810 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
812 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
813 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
819 [(set_attr "op_type" "RI")
820 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
822 (define_insn "*tmsi_reg"
823 [(set (reg CC_REGNUM)
824 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
825 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
826 (match_operand:SI 2 "immediate_operand" "n,n")))]
827 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
828 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
832 [(set_attr "op_type" "RI")
833 (set_attr "z10prop" "z10_super,z10_super")])
835 (define_insn "*tm<mode>_full"
836 [(set (reg CC_REGNUM)
837 (compare (match_operand:HQI 0 "register_operand" "d")
838 (match_operand:HQI 1 "immediate_operand" "n")))]
839 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
841 [(set_attr "op_type" "RI")
842 (set_attr "z10prop" "z10_super")])
846 ; Load-and-Test instructions
849 ; tst(di|si) instruction pattern(s).
851 (define_insn "*tstdi_sign"
852 [(set (reg CC_REGNUM)
856 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
857 (const_int 32)) (const_int 32))
858 (match_operand:DI 1 "const0_operand" "")))
859 (set (match_operand:DI 2 "register_operand" "=d,d")
860 (sign_extend:DI (match_dup 0)))]
861 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
864 [(set_attr "op_type" "RRE,RXY")
865 (set_attr "cpu_facility" "*,z10")
866 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
869 (define_insn "*tst<mode>_extimm"
870 [(set (reg CC_REGNUM)
871 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
872 (match_operand:GPR 1 "const0_operand" "")))
873 (set (match_operand:GPR 2 "register_operand" "=d,d")
875 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
879 [(set_attr "op_type" "RR<E>,RXY")
880 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
883 (define_insn "*tst<mode>_cconly_extimm"
884 [(set (reg CC_REGNUM)
885 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
886 (match_operand:GPR 1 "const0_operand" "")))
887 (clobber (match_scratch:GPR 2 "=X,d"))]
888 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
892 [(set_attr "op_type" "RR<E>,RXY")
893 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
895 (define_insn "*tstdi"
896 [(set (reg CC_REGNUM)
897 (compare (match_operand:DI 0 "register_operand" "d")
898 (match_operand:DI 1 "const0_operand" "")))
899 (set (match_operand:DI 2 "register_operand" "=d")
901 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
903 [(set_attr "op_type" "RRE")
904 (set_attr "z10prop" "z10_fr_E1")])
906 (define_insn "*tstsi"
907 [(set (reg CC_REGNUM)
908 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
909 (match_operand:SI 1 "const0_operand" "")))
910 (set (match_operand:SI 2 "register_operand" "=d,d,d")
912 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
917 [(set_attr "op_type" "RR,RS,RSY")
918 (set_attr "cpu_facility" "*,*,longdisp")
919 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
921 (define_insn "*tstsi_cconly"
922 [(set (reg CC_REGNUM)
923 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
924 (match_operand:SI 1 "const0_operand" "")))
925 (clobber (match_scratch:SI 2 "=X,d,d"))]
926 "s390_match_ccmode(insn, CCSmode)"
931 [(set_attr "op_type" "RR,RS,RSY")
932 (set_attr "cpu_facility" "*,*,longdisp")
933 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
935 (define_insn "*tstdi_cconly_31"
936 [(set (reg CC_REGNUM)
937 (compare (match_operand:DI 0 "register_operand" "d")
938 (match_operand:DI 1 "const0_operand" "")))]
939 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
941 [(set_attr "op_type" "RS")
942 (set_attr "atype" "reg")])
945 (define_insn "*tst<mode>_cconly2"
946 [(set (reg CC_REGNUM)
947 (compare (match_operand:GPR 0 "register_operand" "d")
948 (match_operand:GPR 1 "const0_operand" "")))]
949 "s390_match_ccmode(insn, CCSmode)"
951 [(set_attr "op_type" "RR<E>")
952 (set_attr "z10prop" "z10_fr_E1")])
954 ; tst(hi|qi) instruction pattern(s).
956 (define_insn "*tst<mode>CCT"
957 [(set (reg CC_REGNUM)
958 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
959 (match_operand:HQI 1 "const0_operand" "")))
960 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
962 "s390_match_ccmode(insn, CCTmode)"
965 icmy\t%2,<icm_lo>,%S0
967 [(set_attr "op_type" "RS,RSY,RI")
968 (set_attr "cpu_facility" "*,longdisp,*")
969 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
971 (define_insn "*tsthiCCT_cconly"
972 [(set (reg CC_REGNUM)
973 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
974 (match_operand:HI 1 "const0_operand" "")))
975 (clobber (match_scratch:HI 2 "=d,d,X"))]
976 "s390_match_ccmode(insn, CCTmode)"
981 [(set_attr "op_type" "RS,RSY,RI")
982 (set_attr "cpu_facility" "*,longdisp,*")
983 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
985 (define_insn "*tstqiCCT_cconly"
986 [(set (reg CC_REGNUM)
987 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
988 (match_operand:QI 1 "const0_operand" "")))]
989 "s390_match_ccmode(insn, CCTmode)"
994 [(set_attr "op_type" "SI,SIY,RI")
995 (set_attr "cpu_facility" "*,longdisp,*")
996 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
998 (define_insn "*tst<mode>"
999 [(set (reg CC_REGNUM)
1000 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1001 (match_operand:HQI 1 "const0_operand" "")))
1002 (set (match_operand:HQI 2 "register_operand" "=d,d")
1004 "s390_match_ccmode(insn, CCSmode)"
1006 icm\t%2,<icm_lo>,%S0
1007 icmy\t%2,<icm_lo>,%S0"
1008 [(set_attr "op_type" "RS,RSY")
1009 (set_attr "cpu_facility" "*,longdisp")
1010 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1012 (define_insn "*tst<mode>_cconly"
1013 [(set (reg CC_REGNUM)
1014 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1015 (match_operand:HQI 1 "const0_operand" "")))
1016 (clobber (match_scratch:HQI 2 "=d,d"))]
1017 "s390_match_ccmode(insn, CCSmode)"
1019 icm\t%2,<icm_lo>,%S0
1020 icmy\t%2,<icm_lo>,%S0"
1021 [(set_attr "op_type" "RS,RSY")
1022 (set_attr "cpu_facility" "*,longdisp")
1023 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1026 ; Compare (equality) instructions
1028 (define_insn "*cmpdi_cct"
1029 [(set (reg CC_REGNUM)
1030 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
1031 (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
1032 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
1039 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
1040 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
1042 (define_insn "*cmpsi_cct"
1043 [(set (reg CC_REGNUM)
1044 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1045 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1046 "s390_match_ccmode (insn, CCTmode)"
1054 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1055 (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
1056 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1058 ; Compare (signed) instructions
1060 (define_insn "*cmpdi_ccs_sign"
1061 [(set (reg CC_REGNUM)
1062 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1064 (match_operand:DI 0 "register_operand" "d, d,d")))]
1065 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1070 [(set_attr "op_type" "RRE,RXY,RIL")
1071 (set_attr "z10prop" "z10_c,*,*")
1072 (set_attr "type" "*,*,larl")])
1076 (define_insn "*cmpsi_ccs_sign"
1077 [(set (reg CC_REGNUM)
1078 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1079 (match_operand:SI 0 "register_operand" "d,d,d")))]
1080 "s390_match_ccmode(insn, CCSRmode)"
1085 [(set_attr "op_type" "RX,RXY,RIL")
1086 (set_attr "cpu_facility" "*,longdisp,z10")
1087 (set_attr "type" "*,*,larl")
1088 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1090 (define_insn "*cmphi_ccs_z10"
1091 [(set (reg CC_REGNUM)
1092 (compare (match_operand:HI 0 "s_operand" "Q")
1093 (match_operand:HI 1 "immediate_operand" "K")))]
1094 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1096 [(set_attr "op_type" "SIL")
1097 (set_attr "z196prop" "z196_cracked")])
1099 (define_insn "*cmpdi_ccs_signhi_rl"
1100 [(set (reg CC_REGNUM)
1101 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
1102 (match_operand:GPR 0 "register_operand" "d,d")))]
1103 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1107 [(set_attr "op_type" "RXY,RIL")
1108 (set_attr "type" "*,larl")])
1110 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1111 (define_insn "*cmp<mode>_ccs"
1112 [(set (reg CC_REGNUM)
1113 (compare (match_operand:GPR 0 "nonimmediate_operand"
1115 (match_operand:GPR 1 "general_operand"
1116 "d,K,K,Os,R,T,b")))]
1117 "s390_match_ccmode(insn, CCSmode)"
1126 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1127 (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
1128 (set_attr "type" "*,*,*,*,*,*,larl")
1129 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1132 ; Compare (unsigned) instructions
1134 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1135 [(set (reg CC_REGNUM)
1136 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1137 "larl_operand" "X")))
1138 (match_operand:SI 0 "register_operand" "d")))]
1139 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1141 [(set_attr "op_type" "RIL")
1142 (set_attr "type" "larl")
1143 (set_attr "z10prop" "z10_super")])
1146 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1147 [(set (reg CC_REGNUM)
1148 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1149 "larl_operand" "X")))
1150 (match_operand:GPR 0 "register_operand" "d")))]
1151 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1153 [(set_attr "op_type" "RIL")
1154 (set_attr "type" "larl")
1155 (set_attr "z10prop" "z10_super")])
1157 (define_insn "*cmpdi_ccu_zero"
1158 [(set (reg CC_REGNUM)
1159 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1161 (match_operand:DI 0 "register_operand" "d,d,d")))]
1162 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1167 [(set_attr "op_type" "RRE,RXY,RIL")
1168 (set_attr "cpu_facility" "*,*,z10")
1169 (set_attr "type" "*,*,larl")
1170 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1172 (define_insn "*cmpdi_ccu"
1173 [(set (reg CC_REGNUM)
1174 (compare (match_operand:DI 0 "nonimmediate_operand"
1176 (match_operand:DI 1 "general_operand"
1177 "d,Op,b,D,T,BQ,Q")))]
1178 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1187 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1188 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1189 (set_attr "type" "*,*,larl,*,*,*,*")
1190 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1192 (define_insn "*cmpsi_ccu"
1193 [(set (reg CC_REGNUM)
1194 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1195 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1196 "s390_match_ccmode (insn, CCUmode)"
1206 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1207 (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
1208 (set_attr "type" "*,*,larl,*,*,*,*,*")
1209 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1211 (define_insn "*cmphi_ccu"
1212 [(set (reg CC_REGNUM)
1213 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1214 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1215 "s390_match_ccmode (insn, CCUmode)
1216 && !register_operand (operands[1], HImode)"
1223 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1224 (set_attr "cpu_facility" "*,longdisp,z10,*,*")
1225 (set_attr "z10prop" "*,*,z10_super,*,*")])
1227 (define_insn "*cmpqi_ccu"
1228 [(set (reg CC_REGNUM)
1229 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1230 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1231 "s390_match_ccmode (insn, CCUmode)
1232 && !register_operand (operands[1], QImode)"
1240 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1241 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
1242 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1245 ; Block compare (CLC) instruction patterns.
1248 [(set (reg CC_REGNUM)
1249 (compare (match_operand:BLK 0 "memory_operand" "Q")
1250 (match_operand:BLK 1 "memory_operand" "Q")))
1251 (use (match_operand 2 "const_int_operand" "n"))]
1252 "s390_match_ccmode (insn, CCUmode)
1253 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1254 "clc\t%O0(%2,%R0),%S1"
1255 [(set_attr "op_type" "SS")])
1258 [(set (reg CC_REGNUM)
1259 (compare (match_operand 0 "memory_operand" "")
1260 (match_operand 1 "memory_operand" "")))]
1262 && s390_match_ccmode (insn, CCUmode)
1263 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1264 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1266 [(set (match_dup 0) (match_dup 1))
1267 (use (match_dup 2))])]
1269 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1270 operands[0] = adjust_address (operands[0], BLKmode, 0);
1271 operands[1] = adjust_address (operands[1], BLKmode, 0);
1273 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1274 operands[0], operands[1]);
1275 operands[0] = SET_DEST (PATTERN (curr_insn));
1279 ; (TF|DF|SF|TD|DD|SD) instructions
1281 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1282 (define_insn "*cmp<mode>_ccs_0"
1283 [(set (reg CC_REGNUM)
1284 (compare (match_operand:FP 0 "register_operand" "f")
1285 (match_operand:FP 1 "const0_operand" "")))]
1286 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1287 "lt<xde><bt>r\t%0,%0"
1288 [(set_attr "op_type" "RRE")
1289 (set_attr "type" "fsimp<mode>")])
1291 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1292 (define_insn "*cmp<mode>_ccs"
1293 [(set (reg CC_REGNUM)
1294 (compare (match_operand:FP 0 "register_operand" "f,f")
1295 (match_operand:FP 1 "general_operand" "f,R")))]
1296 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1300 [(set_attr "op_type" "RRE,RXE")
1301 (set_attr "type" "fsimp<mode>")
1302 (set_attr "enabled" "*,<DSF>")])
1304 ; wfcedbs, wfchdbs, wfchedbs
1305 (define_insn "*vec_cmp<insn_cmp>df_cconly"
1306 [(set (reg:VFCMP CC_REGNUM)
1307 (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
1308 (match_operand:DF 1 "register_operand" "v")))
1309 (clobber (match_scratch:V2DI 2 "=v"))]
1310 "TARGET_VX && TARGET_HARD_FLOAT"
1311 "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1312 [(set_attr "op_type" "VRR")])
1314 ; Compare and Branch instructions
1316 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1317 ; The following instructions do a complementary access of their second
1318 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1319 (define_insn "*cmp_and_br_signed_<mode>"
1321 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1322 [(match_operand:GPR 1 "register_operand" "d,d")
1323 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1324 (label_ref (match_operand 3 "" ""))
1326 (clobber (reg:CC CC_REGNUM))]
1327 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1329 if (get_attr_length (insn) == 6)
1330 return which_alternative ?
1331 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1333 return which_alternative ?
1334 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1336 [(set_attr "op_type" "RIE")
1337 (set_attr "type" "branch")
1338 (set_attr "z10prop" "z10_super_c,z10_super")
1339 (set (attr "length")
1340 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1341 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1342 ; 10 byte for cgr/jg
1344 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1345 ; The following instructions do a complementary access of their second
1346 ; operand (z10 only): clrj, clgrj, clr, clgr
1347 (define_insn "*cmp_and_br_unsigned_<mode>"
1349 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1350 [(match_operand:GPR 1 "register_operand" "d,d")
1351 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1352 (label_ref (match_operand 3 "" ""))
1354 (clobber (reg:CC CC_REGNUM))]
1355 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1357 if (get_attr_length (insn) == 6)
1358 return which_alternative ?
1359 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1361 return which_alternative ?
1362 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1364 [(set_attr "op_type" "RIE")
1365 (set_attr "type" "branch")
1366 (set_attr "z10prop" "z10_super_c,z10_super")
1367 (set (attr "length")
1368 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1369 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1370 ; 10 byte for clgr/jg
1372 ; And now the same two patterns as above but with a negated CC mask.
1374 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1375 ; The following instructions do a complementary access of their second
1376 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1377 (define_insn "*icmp_and_br_signed_<mode>"
1379 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1380 [(match_operand:GPR 1 "register_operand" "d,d")
1381 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1383 (label_ref (match_operand 3 "" ""))))
1384 (clobber (reg:CC CC_REGNUM))]
1385 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1387 if (get_attr_length (insn) == 6)
1388 return which_alternative ?
1389 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1391 return which_alternative ?
1392 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1394 [(set_attr "op_type" "RIE")
1395 (set_attr "type" "branch")
1396 (set_attr "z10prop" "z10_super_c,z10_super")
1397 (set (attr "length")
1398 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1399 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1400 ; 10 byte for cgr/jg
1402 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1403 ; The following instructions do a complementary access of their second
1404 ; operand (z10 only): clrj, clgrj, clr, clgr
1405 (define_insn "*icmp_and_br_unsigned_<mode>"
1407 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1408 [(match_operand:GPR 1 "register_operand" "d,d")
1409 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1411 (label_ref (match_operand 3 "" ""))))
1412 (clobber (reg:CC CC_REGNUM))]
1413 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1415 if (get_attr_length (insn) == 6)
1416 return which_alternative ?
1417 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1419 return which_alternative ?
1420 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1422 [(set_attr "op_type" "RIE")
1423 (set_attr "type" "branch")
1424 (set_attr "z10prop" "z10_super_c,z10_super")
1425 (set (attr "length")
1426 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1427 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1428 ; 10 byte for clgr/jg
1431 ;;- Move instructions.
1435 ; movti instruction pattern(s).
1438 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1439 ; for TImode (use double-int for the calculations)
1440 (define_insn "movti"
1441 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o")
1442 (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))]
1456 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1457 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1458 (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
1461 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1462 (match_operand:TI 1 "general_operand" ""))]
1463 "TARGET_ZARCH && reload_completed
1464 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1465 [(set (match_dup 2) (match_dup 4))
1466 (set (match_dup 3) (match_dup 5))]
1468 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1469 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1470 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1471 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1475 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1476 (match_operand:TI 1 "general_operand" ""))]
1477 "TARGET_ZARCH && reload_completed
1478 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1479 [(set (match_dup 2) (match_dup 4))
1480 (set (match_dup 3) (match_dup 5))]
1482 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1483 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1484 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1485 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1488 ; Use part of the TImode target reg to perform the address
1489 ; calculation. If the TImode value is supposed to be copied into a VR
1490 ; this splitter is not necessary.
1492 [(set (match_operand:TI 0 "register_operand" "")
1493 (match_operand:TI 1 "memory_operand" ""))]
1494 "TARGET_ZARCH && reload_completed
1495 && !VECTOR_REG_P (operands[0])
1496 && !s_operand (operands[1], VOIDmode)"
1497 [(set (match_dup 0) (match_dup 1))]
1499 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1500 addr = gen_lowpart (Pmode, addr);
1501 s390_load_address (addr, XEXP (operands[1], 0));
1502 operands[1] = replace_equiv_address (operands[1], addr);
1506 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1507 ; For the higher order bits we do simply a DImode move while the
1508 ; second part is done via vec extract. Both will end up as vlgvg.
1510 [(set (match_operand:TI 0 "register_operand" "")
1511 (match_operand:TI 1 "register_operand" ""))]
1512 "TARGET_VX && reload_completed
1513 && GENERAL_REG_P (operands[0])
1514 && VECTOR_REG_P (operands[1])"
1515 [(set (match_dup 2) (match_dup 4))
1516 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1517 UNSPEC_VEC_EXTRACT))]
1519 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1520 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1521 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1522 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1526 ; Patterns used for secondary reloads
1529 ; z10 provides move instructions accepting larl memory operands.
1530 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1531 ; These patterns are also used for unaligned SI and DI accesses.
1533 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1534 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1535 (match_operand:ALL 1 "register_operand" "=d")
1536 (match_operand:P 2 "register_operand" "=&a")])]
1539 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1543 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1544 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1545 (match_operand:ALL 1 "memory_operand" "")
1546 (match_operand:P 2 "register_operand" "=a")])]
1549 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1553 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1554 [(parallel [(match_operand:P 0 "register_operand" "=d")
1555 (match_operand:P 1 "larl_operand" "")
1556 (match_operand:P 2 "register_operand" "=a")])]
1559 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1563 ; Handles loading a PLUS (load address) expression
1565 (define_expand "reload<mode>_plus"
1566 [(parallel [(match_operand:P 0 "register_operand" "=a")
1567 (match_operand:P 1 "s390_plus_operand" "")
1568 (match_operand:P 2 "register_operand" "=&a")])]
1571 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1575 ; Not all the indirect memory access instructions support the full
1576 ; format (long disp + index + base). So whenever a move from/to such
1577 ; an address is required and the instruction cannot deal with it we do
1578 ; a load address into a scratch register first and use this as the new
1580 ; This in particular is used for:
1581 ; - non-offsetable memory accesses for multiword moves
1582 ; - full vector reg moves with long displacements
1584 (define_expand "reload<mode>_la_in"
1585 [(parallel [(match_operand 0 "register_operand" "")
1586 (match_operand 1 "" "")
1587 (match_operand:P 2 "register_operand" "=&a")])]
1590 gcc_assert (MEM_P (operands[1]));
1591 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1592 operands[1] = replace_equiv_address (operands[1], operands[2]);
1593 emit_move_insn (operands[0], operands[1]);
1597 (define_expand "reload<mode>_la_out"
1598 [(parallel [(match_operand 0 "" "")
1599 (match_operand 1 "register_operand" "")
1600 (match_operand:P 2 "register_operand" "=&a")])]
1603 gcc_assert (MEM_P (operands[0]));
1604 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1605 operands[0] = replace_equiv_address (operands[0], operands[2]);
1606 emit_move_insn (operands[0], operands[1]);
1610 (define_expand "reload<mode>_PIC_addr"
1611 [(parallel [(match_operand 0 "register_operand" "=d")
1612 (match_operand 1 "larl_operand" "")
1613 (match_operand:P 2 "register_operand" "=a")])]
1616 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1617 emit_move_insn (operands[0], new_rtx);
1621 ; movdi instruction pattern(s).
1624 (define_expand "movdi"
1625 [(set (match_operand:DI 0 "general_operand" "")
1626 (match_operand:DI 1 "general_operand" ""))]
1629 /* Handle symbolic constants. */
1631 && (SYMBOLIC_CONST (operands[1])
1632 || (GET_CODE (operands[1]) == PLUS
1633 && XEXP (operands[1], 0) == pic_offset_table_rtx
1634 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1635 emit_symbolic_move (operands);
1638 (define_insn "*movdi_larl"
1639 [(set (match_operand:DI 0 "register_operand" "=d")
1640 (match_operand:DI 1 "larl_operand" "X"))]
1642 && !FP_REG_P (operands[0])"
1644 [(set_attr "op_type" "RIL")
1645 (set_attr "type" "larl")
1646 (set_attr "z10prop" "z10_super_A1")])
1648 (define_insn "*movdi_64"
1649 [(set (match_operand:DI 0 "nonimmediate_operand"
1650 "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
1651 (match_operand:DI 1 "general_operand"
1652 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
1687 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1688 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1689 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1690 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1692 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1693 z10,*,*,*,*,*,longdisp,*,longdisp,
1694 z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
1695 (set_attr "z10prop" "z10_fwd_A1,
1724 [(set (match_operand:DI 0 "register_operand" "")
1725 (match_operand:DI 1 "register_operand" ""))]
1726 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1727 [(set (match_dup 2) (match_dup 3))
1728 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1729 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1730 "operands[2] = gen_lowpart (SImode, operands[0]);
1731 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1734 [(set (match_operand:DI 0 "register_operand" "")
1735 (match_operand:DI 1 "register_operand" ""))]
1736 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1737 && dead_or_set_p (insn, operands[1])"
1738 [(set (match_dup 3) (match_dup 2))
1739 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1740 (set (match_dup 4) (match_dup 2))]
1741 "operands[2] = gen_lowpart (SImode, operands[1]);
1742 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1745 [(set (match_operand:DI 0 "register_operand" "")
1746 (match_operand:DI 1 "register_operand" ""))]
1747 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1748 && !dead_or_set_p (insn, operands[1])"
1749 [(set (match_dup 3) (match_dup 2))
1750 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1751 (set (match_dup 4) (match_dup 2))
1752 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1753 "operands[2] = gen_lowpart (SImode, operands[1]);
1754 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1756 (define_insn "*movdi_31"
1757 [(set (match_operand:DI 0 "nonimmediate_operand"
1758 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1759 (match_operand:DI 1 "general_operand"
1760 " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
1775 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1776 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1777 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
1779 ; For a load from a symbol ref we can use one of the target registers
1780 ; together with larl to load the address.
1782 [(set (match_operand:DI 0 "register_operand" "")
1783 (match_operand:DI 1 "memory_operand" ""))]
1784 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1785 && larl_operand (XEXP (operands[1], 0), SImode)"
1786 [(set (match_dup 2) (match_dup 3))
1787 (set (match_dup 0) (match_dup 1))]
1789 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1790 operands[3] = XEXP (operands[1], 0);
1791 operands[1] = replace_equiv_address (operands[1], operands[2]);
1795 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1796 (match_operand:DI 1 "general_operand" ""))]
1797 "!TARGET_ZARCH && reload_completed
1798 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1799 [(set (match_dup 2) (match_dup 4))
1800 (set (match_dup 3) (match_dup 5))]
1802 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1803 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1804 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1805 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1809 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1810 (match_operand:DI 1 "general_operand" ""))]
1811 "!TARGET_ZARCH && reload_completed
1812 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1813 [(set (match_dup 2) (match_dup 4))
1814 (set (match_dup 3) (match_dup 5))]
1816 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1817 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1818 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1819 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1823 [(set (match_operand:DI 0 "register_operand" "")
1824 (match_operand:DI 1 "memory_operand" ""))]
1825 "!TARGET_ZARCH && reload_completed
1826 && !FP_REG_P (operands[0])
1827 && !s_operand (operands[1], VOIDmode)"
1828 [(set (match_dup 0) (match_dup 1))]
1830 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1831 s390_load_address (addr, XEXP (operands[1], 0));
1832 operands[1] = replace_equiv_address (operands[1], addr);
1836 [(set (match_operand:DI 0 "register_operand" "")
1837 (mem:DI (match_operand 1 "address_operand" "")))]
1839 && !FP_REG_P (operands[0])
1840 && GET_CODE (operands[1]) == SYMBOL_REF
1841 && CONSTANT_POOL_ADDRESS_P (operands[1])
1842 && get_pool_mode (operands[1]) == DImode
1843 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1844 [(set (match_dup 0) (match_dup 2))]
1845 "operands[2] = get_pool_constant (operands[1]);")
1847 (define_insn "*la_64"
1848 [(set (match_operand:DI 0 "register_operand" "=d,d")
1849 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
1854 [(set_attr "op_type" "RX,RXY")
1855 (set_attr "type" "la")
1856 (set_attr "cpu_facility" "*,longdisp")
1857 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1861 [(set (match_operand:DI 0 "register_operand" "")
1862 (match_operand:QI 1 "address_operand" ""))
1863 (clobber (reg:CC CC_REGNUM))])]
1865 && preferred_la_operand_p (operands[1], const0_rtx)"
1866 [(set (match_dup 0) (match_dup 1))]
1870 [(set (match_operand:DI 0 "register_operand" "")
1871 (match_operand:DI 1 "register_operand" ""))
1874 (plus:DI (match_dup 0)
1875 (match_operand:DI 2 "nonmemory_operand" "")))
1876 (clobber (reg:CC CC_REGNUM))])]
1878 && !reg_overlap_mentioned_p (operands[0], operands[2])
1879 && preferred_la_operand_p (operands[1], operands[2])"
1880 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1884 ; movsi instruction pattern(s).
1887 (define_expand "movsi"
1888 [(set (match_operand:SI 0 "general_operand" "")
1889 (match_operand:SI 1 "general_operand" ""))]
1892 /* Handle symbolic constants. */
1894 && (SYMBOLIC_CONST (operands[1])
1895 || (GET_CODE (operands[1]) == PLUS
1896 && XEXP (operands[1], 0) == pic_offset_table_rtx
1897 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1898 emit_symbolic_move (operands);
1901 (define_insn "*movsi_larl"
1902 [(set (match_operand:SI 0 "register_operand" "=d")
1903 (match_operand:SI 1 "larl_operand" "X"))]
1904 "!TARGET_64BIT && TARGET_CPU_ZARCH
1905 && !FP_REG_P (operands[0])"
1907 [(set_attr "op_type" "RIL")
1908 (set_attr "type" "larl")
1909 (set_attr "z10prop" "z10_fwd_A1")])
1911 (define_insn "*movsi_zarch"
1912 [(set (match_operand:SI 0 "nonimmediate_operand"
1913 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
1914 (match_operand:SI 1 "general_operand"
1915 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
1948 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1949 RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1950 (set_attr "type" "*,
1974 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1975 vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
1976 (set_attr "z10prop" "z10_fwd_A1,
2001 (define_insn "*movsi_esa"
2002 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
2003 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
2019 [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
2020 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
2021 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
2023 (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
2027 [(set (match_operand:SI 0 "register_operand" "")
2028 (mem:SI (match_operand 1 "address_operand" "")))]
2029 "!FP_REG_P (operands[0])
2030 && GET_CODE (operands[1]) == SYMBOL_REF
2031 && CONSTANT_POOL_ADDRESS_P (operands[1])
2032 && get_pool_mode (operands[1]) == SImode
2033 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
2034 [(set (match_dup 0) (match_dup 2))]
2035 "operands[2] = get_pool_constant (operands[1]);")
2037 (define_insn "*la_31"
2038 [(set (match_operand:SI 0 "register_operand" "=d,d")
2039 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
2040 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
2044 [(set_attr "op_type" "RX,RXY")
2045 (set_attr "type" "la")
2046 (set_attr "cpu_facility" "*,longdisp")
2047 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2051 [(set (match_operand:SI 0 "register_operand" "")
2052 (match_operand:QI 1 "address_operand" ""))
2053 (clobber (reg:CC CC_REGNUM))])]
2055 && preferred_la_operand_p (operands[1], const0_rtx)"
2056 [(set (match_dup 0) (match_dup 1))]
2060 [(set (match_operand:SI 0 "register_operand" "")
2061 (match_operand:SI 1 "register_operand" ""))
2064 (plus:SI (match_dup 0)
2065 (match_operand:SI 2 "nonmemory_operand" "")))
2066 (clobber (reg:CC CC_REGNUM))])]
2068 && !reg_overlap_mentioned_p (operands[0], operands[2])
2069 && preferred_la_operand_p (operands[1], operands[2])"
2070 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2073 (define_insn "*la_31_and"
2074 [(set (match_operand:SI 0 "register_operand" "=d,d")
2075 (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
2076 (const_int 2147483647)))]
2081 [(set_attr "op_type" "RX,RXY")
2082 (set_attr "type" "la")
2083 (set_attr "cpu_facility" "*,longdisp")
2084 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2086 (define_insn_and_split "*la_31_and_cc"
2087 [(set (match_operand:SI 0 "register_operand" "=d")
2088 (and:SI (match_operand:QI 1 "address_operand" "p")
2089 (const_int 2147483647)))
2090 (clobber (reg:CC CC_REGNUM))]
2093 "&& reload_completed"
2095 (and:SI (match_dup 1) (const_int 2147483647)))]
2097 [(set_attr "op_type" "RX")
2098 (set_attr "type" "la")])
2100 (define_insn "force_la_31"
2101 [(set (match_operand:SI 0 "register_operand" "=d,d")
2102 (match_operand:QI 1 "address_operand" "ZR,ZT"))
2103 (use (const_int 0))]
2108 [(set_attr "op_type" "RX")
2109 (set_attr "type" "la")
2110 (set_attr "cpu_facility" "*,longdisp")
2111 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2114 ; movhi instruction pattern(s).
2117 (define_expand "movhi"
2118 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2119 (match_operand:HI 1 "general_operand" ""))]
2122 /* Make it explicit that loading a register from memory
2123 always sign-extends (at least) to SImode. */
2124 if (optimize && can_create_pseudo_p ()
2125 && register_operand (operands[0], VOIDmode)
2126 && GET_CODE (operands[1]) == MEM)
2128 rtx tmp = gen_reg_rtx (SImode);
2129 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2130 emit_insn (gen_rtx_SET (tmp, ext));
2131 operands[1] = gen_lowpart (HImode, tmp);
2135 (define_insn "*movhi"
2136 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
2137 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
2155 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2156 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2157 (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vec,vec,vec,vec,vec,vec")
2158 (set_attr "z10prop" "z10_fr_E1,
2166 z10_super,*,*,*,*,*,*")])
2169 [(set (match_operand:HI 0 "register_operand" "")
2170 (mem:HI (match_operand 1 "address_operand" "")))]
2171 "GET_CODE (operands[1]) == SYMBOL_REF
2172 && CONSTANT_POOL_ADDRESS_P (operands[1])
2173 && get_pool_mode (operands[1]) == HImode
2174 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2175 [(set (match_dup 0) (match_dup 2))]
2176 "operands[2] = get_pool_constant (operands[1]);")
2179 ; movqi instruction pattern(s).
2182 (define_expand "movqi"
2183 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2184 (match_operand:QI 1 "general_operand" ""))]
2187 /* On z/Architecture, zero-extending from memory to register
2188 is just as fast as a QImode load. */
2189 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2190 && register_operand (operands[0], VOIDmode)
2191 && GET_CODE (operands[1]) == MEM)
2193 rtx tmp = gen_reg_rtx (DImode);
2194 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2195 emit_insn (gen_rtx_SET (tmp, ext));
2196 operands[1] = gen_lowpart (QImode, tmp);
2200 (define_insn "*movqi"
2201 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
2202 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
2220 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2221 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2222 (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vec,vec,vec,vec,vec,vec")
2223 (set_attr "z10prop" "z10_fr_E1,
2234 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2235 (mem:QI (match_operand 1 "address_operand" "")))]
2236 "GET_CODE (operands[1]) == SYMBOL_REF
2237 && CONSTANT_POOL_ADDRESS_P (operands[1])
2238 && get_pool_mode (operands[1]) == QImode
2239 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2240 [(set (match_dup 0) (match_dup 2))]
2241 "operands[2] = get_pool_constant (operands[1]);")
2244 ; movstrictqi instruction pattern(s).
2247 (define_insn "*movstrictqi"
2248 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2249 (match_operand:QI 1 "memory_operand" "R,T"))]
2254 [(set_attr "op_type" "RX,RXY")
2255 (set_attr "cpu_facility" "*,longdisp")
2256 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2259 ; movstricthi instruction pattern(s).
2262 (define_insn "*movstricthi"
2263 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2264 (match_operand:HI 1 "memory_operand" "Q,S"))
2265 (clobber (reg:CC CC_REGNUM))]
2270 [(set_attr "op_type" "RS,RSY")
2271 (set_attr "cpu_facility" "*,longdisp")
2272 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2275 ; movstrictsi instruction pattern(s).
2278 (define_insn "movstrictsi"
2279 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2280 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2287 [(set_attr "op_type" "RR,RX,RXY,RRE")
2288 (set_attr "type" "lr,load,load,*")
2289 (set_attr "cpu_facility" "*,*,longdisp,*")
2290 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2293 ; mov(tf|td) instruction pattern(s).
2296 (define_expand "mov<mode>"
2297 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2298 (match_operand:TD_TF 1 "general_operand" ""))]
2302 (define_insn "*mov<mode>_64"
2303 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
2304 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
2315 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2316 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2317 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2319 (define_insn "*mov<mode>_31"
2320 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2321 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2328 [(set_attr "op_type" "RRE,RRE,*,*")
2329 (set_attr "type" "fsimptf,fsimptf,*,*")
2330 (set_attr "cpu_facility" "z196,*,*,*")])
2332 ; TFmode in GPRs splitters
2335 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2336 (match_operand:TD_TF 1 "general_operand" ""))]
2337 "TARGET_ZARCH && reload_completed
2338 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2339 [(set (match_dup 2) (match_dup 4))
2340 (set (match_dup 3) (match_dup 5))]
2342 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2343 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2344 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2345 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2349 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2350 (match_operand:TD_TF 1 "general_operand" ""))]
2351 "TARGET_ZARCH && reload_completed
2352 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2353 [(set (match_dup 2) (match_dup 4))
2354 (set (match_dup 3) (match_dup 5))]
2356 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2357 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2358 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2359 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2363 [(set (match_operand:TD_TF 0 "register_operand" "")
2364 (match_operand:TD_TF 1 "memory_operand" ""))]
2365 "TARGET_ZARCH && reload_completed
2366 && GENERAL_REG_P (operands[0])
2367 && !s_operand (operands[1], VOIDmode)"
2368 [(set (match_dup 0) (match_dup 1))]
2370 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2371 addr = gen_lowpart (Pmode, addr);
2372 s390_load_address (addr, XEXP (operands[1], 0));
2373 operands[1] = replace_equiv_address (operands[1], addr);
2376 ; TFmode in BFPs splitters
2379 [(set (match_operand:TD_TF 0 "register_operand" "")
2380 (match_operand:TD_TF 1 "memory_operand" ""))]
2381 "reload_completed && offsettable_memref_p (operands[1])
2382 && FP_REG_P (operands[0])"
2383 [(set (match_dup 2) (match_dup 4))
2384 (set (match_dup 3) (match_dup 5))]
2386 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2388 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2390 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2391 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2395 [(set (match_operand:TD_TF 0 "memory_operand" "")
2396 (match_operand:TD_TF 1 "register_operand" ""))]
2397 "reload_completed && offsettable_memref_p (operands[0])
2398 && FP_REG_P (operands[1])"
2399 [(set (match_dup 2) (match_dup 4))
2400 (set (match_dup 3) (match_dup 5))]
2402 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2403 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2404 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2406 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2411 ; mov(df|dd) instruction pattern(s).
2414 (define_expand "mov<mode>"
2415 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2416 (match_operand:DD_DF 1 "general_operand" ""))]
2420 (define_insn "*mov<mode>_64dfp"
2421 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2422 "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,d,v,R")
2423 (match_operand:DD_DF 1 "general_operand"
2424 " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,d,v,R,v"))]
2446 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
2447 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2448 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
2449 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
2450 (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
2452 (define_insn "*mov<mode>_64"
2453 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R")
2454 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d,v,R,v"))]
2472 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
2473 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2474 fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
2475 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
2476 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec")])
2478 (define_insn "*mov<mode>_31"
2479 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2480 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2481 (match_operand:DD_DF 1 "general_operand"
2482 " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
2497 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2498 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2499 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2500 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
2503 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2504 (match_operand:DD_DF 1 "general_operand" ""))]
2505 "!TARGET_ZARCH && reload_completed
2506 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2507 [(set (match_dup 2) (match_dup 4))
2508 (set (match_dup 3) (match_dup 5))]
2510 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2511 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2512 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2513 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2517 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2518 (match_operand:DD_DF 1 "general_operand" ""))]
2519 "!TARGET_ZARCH && reload_completed
2520 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2521 [(set (match_dup 2) (match_dup 4))
2522 (set (match_dup 3) (match_dup 5))]
2524 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2525 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2526 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2527 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2531 [(set (match_operand:DD_DF 0 "register_operand" "")
2532 (match_operand:DD_DF 1 "memory_operand" ""))]
2533 "!TARGET_ZARCH && reload_completed
2534 && !FP_REG_P (operands[0])
2535 && !s_operand (operands[1], VOIDmode)"
2536 [(set (match_dup 0) (match_dup 1))]
2538 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2539 s390_load_address (addr, XEXP (operands[1], 0));
2540 operands[1] = replace_equiv_address (operands[1], addr);
2544 ; mov(sf|sd) instruction pattern(s).
2547 (define_insn "mov<mode>"
2548 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2549 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
2550 (match_operand:SD_SF 1 "general_operand"
2551 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
2576 [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2577 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2578 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2579 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2580 (set_attr "cpu_facility" "z196,vec,*,vec,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vec,vec,vec,vec,vec,vec")])
2583 ; movcc instruction pattern
2586 (define_insn "movcc"
2587 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2588 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2598 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2599 (set_attr "type" "lr,*,*,load,load,store,store")
2600 (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
2601 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2602 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2605 ; Block move (MVC) patterns.
2609 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2610 (match_operand:BLK 1 "memory_operand" "Q"))
2611 (use (match_operand 2 "const_int_operand" "n"))]
2612 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2613 "mvc\t%O0(%2,%R0),%S1"
2614 [(set_attr "op_type" "SS")])
2616 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2617 ; order to have it implemented with mvc.
2620 [(set (match_operand:QI 0 "memory_operand" "")
2621 (match_operand:QI 1 "memory_operand" ""))]
2624 [(set (match_dup 0) (match_dup 1))
2625 (use (const_int 1))])]
2627 operands[0] = adjust_address (operands[0], BLKmode, 0);
2628 operands[1] = adjust_address (operands[1], BLKmode, 0);
2634 [(set (match_operand:BLK 0 "memory_operand" "")
2635 (match_operand:BLK 1 "memory_operand" ""))
2636 (use (match_operand 2 "const_int_operand" ""))])
2638 [(set (match_operand:BLK 3 "memory_operand" "")
2639 (match_operand:BLK 4 "memory_operand" ""))
2640 (use (match_operand 5 "const_int_operand" ""))])]
2641 "s390_offset_p (operands[0], operands[3], operands[2])
2642 && s390_offset_p (operands[1], operands[4], operands[2])
2643 && !s390_overlap_p (operands[0], operands[1],
2644 INTVAL (operands[2]) + INTVAL (operands[5]))
2645 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2647 [(set (match_dup 6) (match_dup 7))
2648 (use (match_dup 8))])]
2649 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2650 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2651 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2655 ; load_multiple pattern(s).
2657 ; ??? Due to reload problems with replacing registers inside match_parallel
2658 ; we currently support load_multiple/store_multiple only after reload.
2661 (define_expand "load_multiple"
2662 [(match_par_dup 3 [(set (match_operand 0 "" "")
2663 (match_operand 1 "" ""))
2664 (use (match_operand 2 "" ""))])]
2673 /* Support only loading a constant number of fixed-point registers from
2674 memory and only bother with this if more than two */
2675 if (GET_CODE (operands[2]) != CONST_INT
2676 || INTVAL (operands[2]) < 2
2677 || INTVAL (operands[2]) > 16
2678 || GET_CODE (operands[1]) != MEM
2679 || GET_CODE (operands[0]) != REG
2680 || REGNO (operands[0]) >= 16)
2683 count = INTVAL (operands[2]);
2684 regno = REGNO (operands[0]);
2685 mode = GET_MODE (operands[0]);
2686 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2689 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2690 if (!can_create_pseudo_p ())
2692 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2694 from = XEXP (operands[1], 0);
2697 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2698 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2699 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2701 from = XEXP (XEXP (operands[1], 0), 0);
2702 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2709 from = force_reg (Pmode, XEXP (operands[1], 0));
2713 for (i = 0; i < count; i++)
2714 XVECEXP (operands[3], 0, i)
2715 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2716 change_address (operands[1], mode,
2717 plus_constant (Pmode, from,
2718 off + i * GET_MODE_SIZE (mode))));
2721 (define_insn "*load_multiple_di"
2722 [(match_parallel 0 "load_multiple_operation"
2723 [(set (match_operand:DI 1 "register_operand" "=r")
2724 (match_operand:DI 2 "s_operand" "S"))])]
2725 "reload_completed && TARGET_ZARCH"
2727 int words = XVECLEN (operands[0], 0);
2728 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2729 return "lmg\t%1,%0,%S2";
2731 [(set_attr "op_type" "RSY")
2732 (set_attr "type" "lm")])
2734 (define_insn "*load_multiple_si"
2735 [(match_parallel 0 "load_multiple_operation"
2736 [(set (match_operand:SI 1 "register_operand" "=r,r")
2737 (match_operand:SI 2 "s_operand" "Q,S"))])]
2740 int words = XVECLEN (operands[0], 0);
2741 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2742 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2744 [(set_attr "op_type" "RS,RSY")
2745 (set_attr "cpu_facility" "*,longdisp")
2746 (set_attr "type" "lm")])
2749 ; store multiple pattern(s).
2752 (define_expand "store_multiple"
2753 [(match_par_dup 3 [(set (match_operand 0 "" "")
2754 (match_operand 1 "" ""))
2755 (use (match_operand 2 "" ""))])]
2764 /* Support only storing a constant number of fixed-point registers to
2765 memory and only bother with this if more than two. */
2766 if (GET_CODE (operands[2]) != CONST_INT
2767 || INTVAL (operands[2]) < 2
2768 || INTVAL (operands[2]) > 16
2769 || GET_CODE (operands[0]) != MEM
2770 || GET_CODE (operands[1]) != REG
2771 || REGNO (operands[1]) >= 16)
2774 count = INTVAL (operands[2]);
2775 regno = REGNO (operands[1]);
2776 mode = GET_MODE (operands[1]);
2777 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2780 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2782 if (!can_create_pseudo_p ())
2784 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2786 to = XEXP (operands[0], 0);
2789 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2790 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2791 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2793 to = XEXP (XEXP (operands[0], 0), 0);
2794 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2801 to = force_reg (Pmode, XEXP (operands[0], 0));
2805 for (i = 0; i < count; i++)
2806 XVECEXP (operands[3], 0, i)
2807 = gen_rtx_SET (change_address (operands[0], mode,
2808 plus_constant (Pmode, to,
2809 off + i * GET_MODE_SIZE (mode))),
2810 gen_rtx_REG (mode, regno + i));
2813 (define_insn "*store_multiple_di"
2814 [(match_parallel 0 "store_multiple_operation"
2815 [(set (match_operand:DI 1 "s_operand" "=S")
2816 (match_operand:DI 2 "register_operand" "r"))])]
2817 "reload_completed && TARGET_ZARCH"
2819 int words = XVECLEN (operands[0], 0);
2820 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2821 return "stmg\t%2,%0,%S1";
2823 [(set_attr "op_type" "RSY")
2824 (set_attr "type" "stm")])
2827 (define_insn "*store_multiple_si"
2828 [(match_parallel 0 "store_multiple_operation"
2829 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2830 (match_operand:SI 2 "register_operand" "r,r"))])]
2833 int words = XVECLEN (operands[0], 0);
2834 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2835 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2837 [(set_attr "op_type" "RS,RSY")
2838 (set_attr "cpu_facility" "*,longdisp")
2839 (set_attr "type" "stm")])
2842 ;; String instructions.
2845 (define_insn "*execute_rl"
2846 [(match_parallel 0 "execute_operation"
2847 [(unspec [(match_operand 1 "register_operand" "a")
2848 (match_operand 2 "" "")
2849 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2850 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2851 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2853 [(set_attr "op_type" "RIL")
2854 (set_attr "type" "cs")])
2856 (define_insn "*execute"
2857 [(match_parallel 0 "execute_operation"
2858 [(unspec [(match_operand 1 "register_operand" "a")
2859 (match_operand:BLK 2 "memory_operand" "R")
2860 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2861 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2862 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2864 [(set_attr "op_type" "RX")
2865 (set_attr "type" "cs")])
2869 ; strlenM instruction pattern(s).
2872 (define_expand "strlen<mode>"
2873 [(match_operand:P 0 "register_operand" "") ; result
2874 (match_operand:BLK 1 "memory_operand" "") ; input string
2875 (match_operand:SI 2 "immediate_operand" "") ; search character
2876 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2879 if (!TARGET_VX || operands[2] != const0_rtx)
2880 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2881 operands[2], operands[3]));
2883 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2888 (define_expand "strlen_srst<mode>"
2889 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2892 (unspec:P [(const_int 0)
2893 (match_operand:BLK 1 "memory_operand" "")
2895 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2896 (clobber (scratch:P))
2897 (clobber (reg:CC CC_REGNUM))])
2899 [(set (match_operand:P 0 "register_operand" "")
2900 (minus:P (match_dup 4) (match_dup 5)))
2901 (clobber (reg:CC CC_REGNUM))])]
2904 operands[4] = gen_reg_rtx (Pmode);
2905 operands[5] = gen_reg_rtx (Pmode);
2906 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2907 operands[1] = replace_equiv_address (operands[1], operands[5]);
2910 (define_insn "*strlen<mode>"
2911 [(set (match_operand:P 0 "register_operand" "=a")
2912 (unspec:P [(match_operand:P 2 "general_operand" "0")
2913 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2915 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2916 (clobber (match_scratch:P 1 "=a"))
2917 (clobber (reg:CC CC_REGNUM))]
2919 "srst\t%0,%1\;jo\t.-4"
2920 [(set_attr "length" "8")
2921 (set_attr "type" "vs")])
2924 ; cmpstrM instruction pattern(s).
2927 (define_expand "cmpstrsi"
2928 [(set (reg:SI 0) (const_int 0))
2930 [(clobber (match_operand 3 "" ""))
2931 (clobber (match_dup 4))
2932 (set (reg:CCU CC_REGNUM)
2933 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2934 (match_operand:BLK 2 "memory_operand" "")))
2937 [(set (match_operand:SI 0 "register_operand" "=d")
2938 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2939 (clobber (reg:CC CC_REGNUM))])]
2942 /* As the result of CMPINT is inverted compared to what we need,
2943 we have to swap the operands. */
2944 rtx op1 = operands[2];
2945 rtx op2 = operands[1];
2946 rtx addr1 = gen_reg_rtx (Pmode);
2947 rtx addr2 = gen_reg_rtx (Pmode);
2949 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2950 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2951 operands[1] = replace_equiv_address_nv (op1, addr1);
2952 operands[2] = replace_equiv_address_nv (op2, addr2);
2953 operands[3] = addr1;
2954 operands[4] = addr2;
2957 (define_insn "*cmpstr<mode>"
2958 [(clobber (match_operand:P 0 "register_operand" "=d"))
2959 (clobber (match_operand:P 1 "register_operand" "=d"))
2960 (set (reg:CCU CC_REGNUM)
2961 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2962 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2965 "clst\t%0,%1\;jo\t.-4"
2966 [(set_attr "length" "8")
2967 (set_attr "type" "vs")])
2970 ; movstr instruction pattern.
2973 (define_expand "movstr"
2974 [(match_operand 0 "register_operand" "")
2975 (match_operand 1 "memory_operand" "")
2976 (match_operand 2 "memory_operand" "")]
2980 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
2982 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
2986 (define_expand "movstr<P:mode>"
2987 [(set (reg:SI 0) (const_int 0))
2989 [(clobber (match_dup 3))
2990 (set (match_operand:BLK 1 "memory_operand" "")
2991 (match_operand:BLK 2 "memory_operand" ""))
2992 (set (match_operand:P 0 "register_operand" "")
2993 (unspec:P [(match_dup 1)
2995 (reg:SI 0)] UNSPEC_MVST))
2996 (clobber (reg:CC CC_REGNUM))])]
3001 if (TARGET_VX && optimize_function_for_speed_p (cfun))
3003 s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
3007 addr1 = gen_reg_rtx (Pmode);
3008 addr2 = gen_reg_rtx (Pmode);
3010 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3011 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
3012 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3013 operands[2] = replace_equiv_address_nv (operands[2], addr2);
3014 operands[3] = addr2;
3017 (define_insn "*movstr"
3018 [(clobber (match_operand:P 2 "register_operand" "=d"))
3019 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
3020 (mem:BLK (match_operand:P 3 "register_operand" "2")))
3021 (set (match_operand:P 0 "register_operand" "=d")
3022 (unspec:P [(mem:BLK (match_dup 1))
3023 (mem:BLK (match_dup 3))
3024 (reg:SI 0)] UNSPEC_MVST))
3025 (clobber (reg:CC CC_REGNUM))]
3027 "mvst\t%1,%2\;jo\t.-4"
3028 [(set_attr "length" "8")
3029 (set_attr "type" "vs")])
3033 ; movmemM instruction pattern(s).
3036 (define_expand "movmem<mode>"
3037 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
3038 (match_operand:BLK 1 "memory_operand" "")) ; source
3039 (use (match_operand:GPR 2 "general_operand" "")) ; count
3040 (match_operand 3 "" "")]
3043 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
3049 ; Move a block that is up to 256 bytes in length.
3050 ; The block length is taken as (operands[2] % 256) + 1.
3052 (define_expand "movmem_short"
3054 [(set (match_operand:BLK 0 "memory_operand" "")
3055 (match_operand:BLK 1 "memory_operand" ""))
3056 (use (match_operand 2 "nonmemory_operand" ""))
3057 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3058 (clobber (match_dup 3))])]
3060 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3062 (define_insn "*movmem_short"
3063 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3064 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3065 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3066 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3067 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3068 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3070 [(set_attr "type" "cs")
3071 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3074 [(set (match_operand:BLK 0 "memory_operand" "")
3075 (match_operand:BLK 1 "memory_operand" ""))
3076 (use (match_operand 2 "const_int_operand" ""))
3077 (use (match_operand 3 "immediate_operand" ""))
3078 (clobber (scratch))]
3081 [(set (match_dup 0) (match_dup 1))
3082 (use (match_dup 2))])]
3083 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3086 [(set (match_operand:BLK 0 "memory_operand" "")
3087 (match_operand:BLK 1 "memory_operand" ""))
3088 (use (match_operand 2 "register_operand" ""))
3089 (use (match_operand 3 "memory_operand" ""))
3090 (clobber (scratch))]
3093 [(unspec [(match_dup 2) (match_dup 3)
3094 (const_int 0)] UNSPEC_EXECUTE)
3095 (set (match_dup 0) (match_dup 1))
3096 (use (const_int 1))])]
3100 [(set (match_operand:BLK 0 "memory_operand" "")
3101 (match_operand:BLK 1 "memory_operand" ""))
3102 (use (match_operand 2 "register_operand" ""))
3103 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3104 (clobber (scratch))]
3105 "TARGET_Z10 && reload_completed"
3107 [(unspec [(match_dup 2) (const_int 0)
3108 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3109 (set (match_dup 0) (match_dup 1))
3110 (use (const_int 1))])]
3111 "operands[3] = gen_label_rtx ();")
3114 [(set (match_operand:BLK 0 "memory_operand" "")
3115 (match_operand:BLK 1 "memory_operand" ""))
3116 (use (match_operand 2 "register_operand" ""))
3117 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3118 (clobber (match_operand 3 "register_operand" ""))]
3119 "reload_completed && TARGET_CPU_ZARCH"
3120 [(set (match_dup 3) (label_ref (match_dup 4)))
3122 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3123 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3124 (set (match_dup 0) (match_dup 1))
3125 (use (const_int 1))])]
3126 "operands[4] = gen_label_rtx ();")
3128 ; Move a block of arbitrary length.
3130 (define_expand "movmem_long"
3132 [(clobber (match_dup 2))
3133 (clobber (match_dup 3))
3134 (set (match_operand:BLK 0 "memory_operand" "")
3135 (match_operand:BLK 1 "memory_operand" ""))
3136 (use (match_operand 2 "general_operand" ""))
3138 (clobber (reg:CC CC_REGNUM))])]
3141 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3142 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3143 rtx reg0 = gen_reg_rtx (dreg_mode);
3144 rtx reg1 = gen_reg_rtx (dreg_mode);
3145 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3146 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3147 rtx len0 = gen_lowpart (Pmode, reg0);
3148 rtx len1 = gen_lowpart (Pmode, reg1);
3150 emit_clobber (reg0);
3151 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3152 emit_move_insn (len0, operands[2]);
3154 emit_clobber (reg1);
3155 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3156 emit_move_insn (len1, operands[2]);
3158 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3159 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3164 (define_insn "*movmem_long"
3165 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3166 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3167 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3168 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3171 (clobber (reg:CC CC_REGNUM))]
3172 "TARGET_64BIT || !TARGET_ZARCH"
3173 "mvcle\t%0,%1,0\;jo\t.-4"
3174 [(set_attr "length" "8")
3175 (set_attr "type" "vs")])
3177 (define_insn "*movmem_long_31z"
3178 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3179 (clobber (match_operand:TI 1 "register_operand" "=d"))
3180 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3181 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3184 (clobber (reg:CC CC_REGNUM))]
3185 "!TARGET_64BIT && TARGET_ZARCH"
3186 "mvcle\t%0,%1,0\;jo\t.-4"
3187 [(set_attr "length" "8")
3188 (set_attr "type" "vs")])
3195 (define_expand "signbit<mode>2"
3196 [(set (reg:CCZ CC_REGNUM)
3197 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3200 (set (match_operand:SI 0 "register_operand" "=d")
3201 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3204 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3207 (define_expand "isinf<mode>2"
3208 [(set (reg:CCZ CC_REGNUM)
3209 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3212 (set (match_operand:SI 0 "register_operand" "=d")
3213 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3216 operands[2] = GEN_INT (S390_TDC_INFINITY);
3219 ; This extracts CC into a GPR properly shifted. The actual IPM
3220 ; instruction will be issued by reload. The constraint of operand 1
3221 ; forces reload to use a GPR. So reload will issue a movcc insn for
3222 ; copying CC into a GPR first.
3223 (define_insn_and_split "*cc_to_int"
3224 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3225 (unspec:SI [(match_operand 1 "register_operand" "0")]
3230 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3232 ; This insn is used to generate all variants of the Test Data Class
3233 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3234 ; is the register to be tested and the second one is the bit mask
3235 ; specifying the required test(s).
3237 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3238 (define_insn "*TDC_insn_<mode>"
3239 [(set (reg:CCZ CC_REGNUM)
3240 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3241 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3243 "t<_d>c<xde><bt>\t%0,%1"
3244 [(set_attr "op_type" "RXE")
3245 (set_attr "type" "fsimp<mode>")])
3250 ; setmemM instruction pattern(s).
3253 (define_expand "setmem<mode>"
3254 [(set (match_operand:BLK 0 "memory_operand" "")
3255 (match_operand:QI 2 "general_operand" ""))
3256 (use (match_operand:GPR 1 "general_operand" ""))
3257 (match_operand 3 "" "")]
3259 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3261 ; Clear a block that is up to 256 bytes in length.
3262 ; The block length is taken as (operands[1] % 256) + 1.
3264 (define_expand "clrmem_short"
3266 [(set (match_operand:BLK 0 "memory_operand" "")
3268 (use (match_operand 1 "nonmemory_operand" ""))
3269 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3270 (clobber (match_dup 2))
3271 (clobber (reg:CC CC_REGNUM))])]
3273 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3275 (define_insn "*clrmem_short"
3276 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3278 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3279 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3280 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3281 (clobber (reg:CC CC_REGNUM))]
3282 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3284 [(set_attr "type" "cs")
3285 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3288 [(set (match_operand:BLK 0 "memory_operand" "")
3290 (use (match_operand 1 "const_int_operand" ""))
3291 (use (match_operand 2 "immediate_operand" ""))
3293 (clobber (reg:CC CC_REGNUM))]
3296 [(set (match_dup 0) (const_int 0))
3298 (clobber (reg:CC CC_REGNUM))])]
3299 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3302 [(set (match_operand:BLK 0 "memory_operand" "")
3304 (use (match_operand 1 "register_operand" ""))
3305 (use (match_operand 2 "memory_operand" ""))
3307 (clobber (reg:CC CC_REGNUM))]
3310 [(unspec [(match_dup 1) (match_dup 2)
3311 (const_int 0)] UNSPEC_EXECUTE)
3312 (set (match_dup 0) (const_int 0))
3314 (clobber (reg:CC CC_REGNUM))])]
3318 [(set (match_operand:BLK 0 "memory_operand" "")
3320 (use (match_operand 1 "register_operand" ""))
3321 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3323 (clobber (reg:CC CC_REGNUM))]
3324 "TARGET_Z10 && reload_completed"
3326 [(unspec [(match_dup 1) (const_int 0)
3327 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3328 (set (match_dup 0) (const_int 0))
3330 (clobber (reg:CC CC_REGNUM))])]
3331 "operands[3] = gen_label_rtx ();")
3334 [(set (match_operand:BLK 0 "memory_operand" "")
3336 (use (match_operand 1 "register_operand" ""))
3337 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3338 (clobber (match_operand 2 "register_operand" ""))
3339 (clobber (reg:CC CC_REGNUM))]
3340 "reload_completed && TARGET_CPU_ZARCH"
3341 [(set (match_dup 2) (label_ref (match_dup 3)))
3343 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3344 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3345 (set (match_dup 0) (const_int 0))
3347 (clobber (reg:CC CC_REGNUM))])]
3348 "operands[3] = gen_label_rtx ();")
3350 ; Initialize a block of arbitrary length with (operands[2] % 256).
3352 (define_expand "setmem_long_<P:mode>"
3354 [(clobber (match_dup 1))
3355 (set (match_operand:BLK 0 "memory_operand" "")
3356 (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
3357 (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3359 (clobber (reg:CC CC_REGNUM))])]
3362 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3363 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3364 rtx reg0 = gen_reg_rtx (dreg_mode);
3365 rtx reg1 = gen_reg_rtx (dreg_mode);
3366 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3367 rtx len0 = gen_lowpart (Pmode, reg0);
3369 emit_clobber (reg0);
3370 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3371 emit_move_insn (len0, operands[1]);
3373 emit_move_insn (reg1, const0_rtx);
3375 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3378 operands[4] = gen_lowpart (Pmode, operands[1]);
3381 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3383 (define_insn "*setmem_long"
3384 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3385 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3386 (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
3387 (subreg:P (match_dup 3) <modesize>)]
3388 UNSPEC_REPLICATE_BYTE))
3389 (use (match_operand:<DBL> 1 "register_operand" "d"))
3390 (clobber (reg:CC CC_REGNUM))]
3391 "TARGET_64BIT || !TARGET_ZARCH"
3392 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3393 [(set_attr "length" "8")
3394 (set_attr "type" "vs")])
3396 (define_insn "*setmem_long_and"
3397 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3398 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3400 (match_operand:P 2 "setmem_operand" "Y")
3401 (match_operand:P 4 "const_int_operand" "n"))
3402 (subreg:P (match_dup 3) <modesize>)]
3403 UNSPEC_REPLICATE_BYTE))
3404 (use (match_operand:<DBL> 1 "register_operand" "d"))
3405 (clobber (reg:CC CC_REGNUM))]
3406 "(TARGET_64BIT || !TARGET_ZARCH) &&
3407 (INTVAL (operands[4]) & 255) == 255"
3408 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3409 [(set_attr "length" "8")
3410 (set_attr "type" "vs")])
3412 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3413 ; of the SImode subregs.
3415 (define_insn "*setmem_long_31z"
3416 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3417 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3418 (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
3419 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3420 (use (match_operand:TI 1 "register_operand" "d"))
3421 (clobber (reg:CC CC_REGNUM))]
3422 "!TARGET_64BIT && TARGET_ZARCH"
3423 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3424 [(set_attr "length" "8")
3425 (set_attr "type" "vs")])
3427 (define_insn "*setmem_long_and_31z"
3428 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3429 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3430 (unspec:BLK [(and:SI
3431 (match_operand:SI 2 "setmem_operand" "Y")
3432 (match_operand:SI 4 "const_int_operand" "n"))
3433 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3434 (use (match_operand:TI 1 "register_operand" "d"))
3435 (clobber (reg:CC CC_REGNUM))]
3436 "(!TARGET_64BIT && TARGET_ZARCH) &&
3437 (INTVAL (operands[4]) & 255) == 255"
3438 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3439 [(set_attr "length" "8")
3440 (set_attr "type" "vs")])
3443 ; cmpmemM instruction pattern(s).
3446 (define_expand "cmpmemsi"
3447 [(set (match_operand:SI 0 "register_operand" "")
3448 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3449 (match_operand:BLK 2 "memory_operand" "") ) )
3450 (use (match_operand:SI 3 "general_operand" ""))
3451 (use (match_operand:SI 4 "" ""))]
3454 if (s390_expand_cmpmem (operands[0], operands[1],
3455 operands[2], operands[3]))
3461 ; Compare a block that is up to 256 bytes in length.
3462 ; The block length is taken as (operands[2] % 256) + 1.
3464 (define_expand "cmpmem_short"
3466 [(set (reg:CCU CC_REGNUM)
3467 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3468 (match_operand:BLK 1 "memory_operand" "")))
3469 (use (match_operand 2 "nonmemory_operand" ""))
3470 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3471 (clobber (match_dup 3))])]
3473 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3475 (define_insn "*cmpmem_short"
3476 [(set (reg:CCU CC_REGNUM)
3477 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3478 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3479 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3480 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3481 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3482 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3484 [(set_attr "type" "cs")
3485 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3488 [(set (reg:CCU CC_REGNUM)
3489 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3490 (match_operand:BLK 1 "memory_operand" "")))
3491 (use (match_operand 2 "const_int_operand" ""))
3492 (use (match_operand 3 "immediate_operand" ""))
3493 (clobber (scratch))]
3496 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3497 (use (match_dup 2))])]
3498 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3501 [(set (reg:CCU CC_REGNUM)
3502 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3503 (match_operand:BLK 1 "memory_operand" "")))
3504 (use (match_operand 2 "register_operand" ""))
3505 (use (match_operand 3 "memory_operand" ""))
3506 (clobber (scratch))]
3509 [(unspec [(match_dup 2) (match_dup 3)
3510 (const_int 0)] UNSPEC_EXECUTE)
3511 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3512 (use (const_int 1))])]
3516 [(set (reg:CCU CC_REGNUM)
3517 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3518 (match_operand:BLK 1 "memory_operand" "")))
3519 (use (match_operand 2 "register_operand" ""))
3520 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3521 (clobber (scratch))]
3522 "TARGET_Z10 && reload_completed"
3524 [(unspec [(match_dup 2) (const_int 0)
3525 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3526 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3527 (use (const_int 1))])]
3528 "operands[4] = gen_label_rtx ();")
3531 [(set (reg:CCU CC_REGNUM)
3532 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3533 (match_operand:BLK 1 "memory_operand" "")))
3534 (use (match_operand 2 "register_operand" ""))
3535 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3536 (clobber (match_operand 3 "register_operand" ""))]
3537 "reload_completed && TARGET_CPU_ZARCH"
3538 [(set (match_dup 3) (label_ref (match_dup 4)))
3540 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3541 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3542 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3543 (use (const_int 1))])]
3544 "operands[4] = gen_label_rtx ();")
3546 ; Compare a block of arbitrary length.
3548 (define_expand "cmpmem_long"
3550 [(clobber (match_dup 2))
3551 (clobber (match_dup 3))
3552 (set (reg:CCU CC_REGNUM)
3553 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3554 (match_operand:BLK 1 "memory_operand" "")))
3555 (use (match_operand 2 "general_operand" ""))
3556 (use (match_dup 3))])]
3559 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3560 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3561 rtx reg0 = gen_reg_rtx (dreg_mode);
3562 rtx reg1 = gen_reg_rtx (dreg_mode);
3563 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3564 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3565 rtx len0 = gen_lowpart (Pmode, reg0);
3566 rtx len1 = gen_lowpart (Pmode, reg1);
3568 emit_clobber (reg0);
3569 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3570 emit_move_insn (len0, operands[2]);
3572 emit_clobber (reg1);
3573 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3574 emit_move_insn (len1, operands[2]);
3576 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3577 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3582 (define_insn "*cmpmem_long"
3583 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3584 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3585 (set (reg:CCU CC_REGNUM)
3586 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3587 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3589 (use (match_dup 3))]
3590 "TARGET_64BIT || !TARGET_ZARCH"
3591 "clcle\t%0,%1,0\;jo\t.-4"
3592 [(set_attr "length" "8")
3593 (set_attr "type" "vs")])
3595 (define_insn "*cmpmem_long_31z"
3596 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3597 (clobber (match_operand:TI 1 "register_operand" "=d"))
3598 (set (reg:CCU CC_REGNUM)
3599 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3600 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3602 (use (match_dup 3))]
3603 "!TARGET_64BIT && TARGET_ZARCH"
3604 "clcle\t%0,%1,0\;jo\t.-4"
3605 [(set_attr "op_type" "NN")
3606 (set_attr "type" "vs")
3607 (set_attr "length" "8")])
3609 ; Convert CCUmode condition code to integer.
3610 ; Result is zero if EQ, positive if LTU, negative if GTU.
3612 (define_insn_and_split "cmpint"
3613 [(set (match_operand:SI 0 "register_operand" "=d")
3614 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3615 UNSPEC_STRCMPCC_TO_INT))
3616 (clobber (reg:CC CC_REGNUM))]
3620 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3622 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3623 (clobber (reg:CC CC_REGNUM))])])
3625 (define_insn_and_split "*cmpint_cc"
3626 [(set (reg CC_REGNUM)
3627 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3628 UNSPEC_STRCMPCC_TO_INT)
3630 (set (match_operand:SI 0 "register_operand" "=d")
3631 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3632 "s390_match_ccmode (insn, CCSmode)"
3634 "&& reload_completed"
3635 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3637 [(set (match_dup 2) (match_dup 3))
3638 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3640 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3641 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3642 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3645 (define_insn_and_split "*cmpint_sign"
3646 [(set (match_operand:DI 0 "register_operand" "=d")
3647 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3648 UNSPEC_STRCMPCC_TO_INT)))
3649 (clobber (reg:CC CC_REGNUM))]
3652 "&& reload_completed"
3653 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3655 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3656 (clobber (reg:CC CC_REGNUM))])])
3658 (define_insn_and_split "*cmpint_sign_cc"
3659 [(set (reg CC_REGNUM)
3660 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3661 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3662 UNSPEC_STRCMPCC_TO_INT) 0)
3663 (const_int 32)) (const_int 32))
3665 (set (match_operand:DI 0 "register_operand" "=d")
3666 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3667 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3669 "&& reload_completed"
3670 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3672 [(set (match_dup 2) (match_dup 3))
3673 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3675 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3676 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3677 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3682 ;;- Conversion instructions.
3685 (define_insn "*sethighpartsi"
3686 [(set (match_operand:SI 0 "register_operand" "=d,d")
3687 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3688 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3689 (clobber (reg:CC CC_REGNUM))]
3694 [(set_attr "op_type" "RS,RSY")
3695 (set_attr "cpu_facility" "*,longdisp")
3696 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3698 (define_insn "*sethighpartdi_64"
3699 [(set (match_operand:DI 0 "register_operand" "=d")
3700 (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
3701 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3702 (clobber (reg:CC CC_REGNUM))]
3705 [(set_attr "op_type" "RSY")
3706 (set_attr "z10prop" "z10_super")])
3708 (define_insn "*sethighpartdi_31"
3709 [(set (match_operand:DI 0 "register_operand" "=d,d")
3710 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3711 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3712 (clobber (reg:CC CC_REGNUM))]
3717 [(set_attr "op_type" "RS,RSY")
3718 (set_attr "cpu_facility" "*,longdisp")
3719 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3722 ; extv instruction patterns
3725 ; FIXME: This expander needs to be converted from DI to GPR as well
3726 ; after resolving some issues with it.
3728 (define_expand "extzv"
3730 [(set (match_operand:DI 0 "register_operand" "=d")
3732 (match_operand:DI 1 "register_operand" "d")
3733 (match_operand 2 "const_int_operand" "") ; size
3734 (match_operand 3 "const_int_operand" ""))) ; start
3735 (clobber (reg:CC CC_REGNUM))])]
3738 /* Starting with zEC12 there is risbgn not clobbering CC. */
3741 emit_move_insn (operands[0],
3742 gen_rtx_ZERO_EXTRACT (DImode,
3750 (define_insn "*extzv<mode>_zEC12"
3751 [(set (match_operand:GPR 0 "register_operand" "=d")
3753 (match_operand:GPR 1 "register_operand" "d")
3754 (match_operand 2 "const_int_operand" "") ; size
3755 (match_operand 3 "const_int_operand" "")))] ; start]
3757 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3758 [(set_attr "op_type" "RIE")])
3760 (define_insn "*extzv<mode>_z10"
3761 [(set (match_operand:GPR 0 "register_operand" "=d")
3763 (match_operand:GPR 1 "register_operand" "d")
3764 (match_operand 2 "const_int_operand" "") ; size
3765 (match_operand 3 "const_int_operand" ""))) ; start
3766 (clobber (reg:CC CC_REGNUM))]
3768 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3769 [(set_attr "op_type" "RIE")
3770 (set_attr "z10prop" "z10_super_E1")])
3772 (define_insn_and_split "*pre_z10_extzv<mode>"
3773 [(set (match_operand:GPR 0 "register_operand" "=d")
3774 (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
3775 (match_operand 2 "nonzero_shift_count_operand" "")
3777 (clobber (reg:CC CC_REGNUM))]
3780 "&& reload_completed"
3782 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3783 (clobber (reg:CC CC_REGNUM))])
3784 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3786 int bitsize = INTVAL (operands[2]);
3787 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3788 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3790 operands[1] = adjust_address (operands[1], BLKmode, 0);
3791 set_mem_size (operands[1], size);
3792 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3793 operands[3] = GEN_INT (mask);
3796 (define_insn_and_split "*pre_z10_extv<mode>"
3797 [(set (match_operand:GPR 0 "register_operand" "=d")
3798 (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
3799 (match_operand 2 "nonzero_shift_count_operand" "")
3801 (clobber (reg:CC CC_REGNUM))]
3804 "&& reload_completed"
3806 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3807 (clobber (reg:CC CC_REGNUM))])
3809 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3810 (clobber (reg:CC CC_REGNUM))])]
3812 int bitsize = INTVAL (operands[2]);
3813 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3814 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3816 operands[1] = adjust_address (operands[1], BLKmode, 0);
3817 set_mem_size (operands[1], size);
3818 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3819 operands[3] = GEN_INT (mask);
3823 ; insv instruction patterns
3826 (define_expand "insv"
3827 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3828 (match_operand 1 "const_int_operand" "")
3829 (match_operand 2 "const_int_operand" ""))
3830 (match_operand 3 "general_operand" ""))]
3833 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3839 ; The normal RTL expansion will never generate a zero_extract where
3840 ; the location operand isn't word mode. However, we do this in the
3841 ; back-end when generating atomic operations. See s390_two_part_insv.
3842 (define_insn "*insv<mode>_zEC12"
3843 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3844 (match_operand 1 "const_int_operand" "I") ; size
3845 (match_operand 2 "const_int_operand" "I")) ; pos
3846 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3848 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3849 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3850 [(set_attr "op_type" "RIE")])
3852 (define_insn "*insv<mode>_z10"
3853 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3854 (match_operand 1 "const_int_operand" "I") ; size
3855 (match_operand 2 "const_int_operand" "I")) ; pos
3856 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3857 (clobber (reg:CC CC_REGNUM))]
3859 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3860 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3861 [(set_attr "op_type" "RIE")
3862 (set_attr "z10prop" "z10_super_E1")])
3864 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3865 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3866 (define_insn "*insv<mode>_zEC12_noshift"
3867 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3868 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3869 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3870 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3871 (match_operand:GPR 4 "const_int_operand" ""))))]
3872 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3873 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3874 [(set_attr "op_type" "RIE")])
3876 (define_insn "*insv<mode>_z10_noshift"
3877 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3878 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3879 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3880 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3881 (match_operand:GPR 4 "const_int_operand" ""))))
3882 (clobber (reg:CC CC_REGNUM))]
3883 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3884 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3885 [(set_attr "op_type" "RIE")
3886 (set_attr "z10prop" "z10_super_E1")])
3888 ; Implement appending Y on the left of S bits of X
3889 ; x = (y << s) | (x & ((1 << s) - 1))
3890 (define_insn "*insv<mode>_zEC12_appendbitsleft"
3891 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3892 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3893 (match_operand:GPR 2 "immediate_operand" ""))
3894 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3895 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3896 "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3897 "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
3898 [(set_attr "op_type" "RIE")
3899 (set_attr "z10prop" "z10_super_E1")])
3901 (define_insn "*insv<mode>_z10_appendbitsleft"
3902 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3903 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
3904 (match_operand:GPR 2 "immediate_operand" ""))
3905 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
3906 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3907 (clobber (reg:CC CC_REGNUM))]
3908 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
3909 "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
3910 [(set_attr "op_type" "RIE")
3911 (set_attr "z10prop" "z10_super_E1")])
3913 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
3914 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
3915 ; -> z = y >> d; z = risbg;
3918 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3919 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3920 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3921 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3922 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
3923 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3925 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3927 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3928 (ashift:GPR (match_dup 3) (match_dup 4))))]
3930 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3931 if (reg_overlap_mentioned_p (operands[0], operands[3]))
3933 if (!can_create_pseudo_p ())
3935 operands[6] = gen_reg_rtx (<MODE>mode);
3938 operands[6] = operands[0];
3943 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
3944 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3945 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
3946 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
3947 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
3948 (clobber (reg:CC CC_REGNUM))])]
3949 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
3951 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
3954 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
3955 (ashift:GPR (match_dup 3) (match_dup 4))))
3956 (clobber (reg:CC CC_REGNUM))])]
3958 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
3959 if (reg_overlap_mentioned_p (operands[0], operands[3]))
3961 if (!can_create_pseudo_p ())
3963 operands[6] = gen_reg_rtx (<MODE>mode);
3966 operands[6] = operands[0];
3969 (define_insn "*r<noxa>sbg_<mode>_noshift"
3970 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3972 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3973 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3974 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3975 (clobber (reg:CC CC_REGNUM))]
3977 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3978 [(set_attr "op_type" "RIE")])
3980 (define_insn "*r<noxa>sbg_di_rotl"
3981 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3985 (match_operand:DI 1 "nonimmediate_operand" "d")
3986 (match_operand:DI 3 "const_int_operand" ""))
3987 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3988 (match_operand:DI 4 "nonimmediate_operand" "0")))
3989 (clobber (reg:CC CC_REGNUM))]
3991 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3992 [(set_attr "op_type" "RIE")])
3994 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
3995 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3999 (match_operand:GPR 1 "nonimmediate_operand" "d")
4000 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4001 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4002 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4003 (clobber (reg:CC CC_REGNUM))]
4005 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
4006 INTVAL (operands[2]))"
4007 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
4008 [(set_attr "op_type" "RIE")])
4010 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
4011 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4015 (match_operand:GPR 1 "nonimmediate_operand" "d")
4016 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4017 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4018 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4019 (clobber (reg:CC CC_REGNUM))]
4021 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
4022 INTVAL (operands[2]))"
4023 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
4024 [(set_attr "op_type" "RIE")])
4026 ;; unsigned {int,long} a, b
4027 ;; a = a | (b << const_int)
4028 ;; a = a ^ (b << const_int)
4029 (define_insn "*r<noxa>sbg_<mode>_sll"
4030 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4033 (match_operand:GPR 1 "nonimmediate_operand" "d")
4034 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4035 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4036 (clobber (reg:CC CC_REGNUM))]
4038 "r<noxa>sbg\t%0,%1,64-<bitsize>,63-%2,%2"
4039 [(set_attr "op_type" "RIE")])
4041 ;; unsigned {int,long} a, b
4042 ;; a = a | (b >> const_int)
4043 ;; a = a ^ (b >> const_int)
4044 (define_insn "*r<noxa>sbg_<mode>_srl"
4045 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4048 (match_operand:GPR 1 "nonimmediate_operand" "d")
4049 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4050 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4051 (clobber (reg:CC CC_REGNUM))]
4053 "r<noxa>sbg\t%0,%1,64-<bitsize>+%2,63,64-%2"
4054 [(set_attr "op_type" "RIE")])
4056 ;; These two are generated by combine for s.bf &= val.
4057 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
4058 ;; shifts and ands, which results in some truly awful patterns
4059 ;; including subregs of operations. Rather unnecessisarily, IMO.
4062 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4063 ;; (const_int 24 [0x18])
4064 ;; (const_int 0 [0]))
4065 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
4066 ;; (const_int 40 [0x28])) 4)
4067 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
4069 ;; we should instead generate
4071 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4072 ;; (const_int 24 [0x18])
4073 ;; (const_int 0 [0]))
4074 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
4075 ;; (const_int 40 [0x28]))
4076 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
4078 ;; by noticing that we can push down the outer paradoxical subreg
4079 ;; into the operation.
4081 (define_insn "*insv_rnsbg_noshift"
4082 [(set (zero_extract:DI
4083 (match_operand:DI 0 "nonimmediate_operand" "+d")
4084 (match_operand 1 "const_int_operand" "")
4085 (match_operand 2 "const_int_operand" ""))
4088 (match_operand:DI 3 "nonimmediate_operand" "d")))
4089 (clobber (reg:CC CC_REGNUM))]
4091 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4092 "rnsbg\t%0,%3,%2,63,0"
4093 [(set_attr "op_type" "RIE")])
4095 (define_insn "*insv_rnsbg_srl"
4096 [(set (zero_extract:DI
4097 (match_operand:DI 0 "nonimmediate_operand" "+d")
4098 (match_operand 1 "const_int_operand" "")
4099 (match_operand 2 "const_int_operand" ""))
4103 (match_operand 3 "const_int_operand" ""))
4104 (match_operand:DI 4 "nonimmediate_operand" "d")))
4105 (clobber (reg:CC CC_REGNUM))]
4107 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4108 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4109 [(set_attr "op_type" "RIE")])
4111 (define_insn "*insv<mode>_mem_reg"
4112 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4113 (match_operand 1 "const_int_operand" "n,n")
4115 (match_operand:W 2 "register_operand" "d,d"))]
4116 "INTVAL (operands[1]) > 0
4117 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4118 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4120 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4122 operands[1] = GEN_INT ((1ul << size) - 1);
4123 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4124 : "stcmy\t%2,%1,%S0";
4126 [(set_attr "op_type" "RS,RSY")
4127 (set_attr "cpu_facility" "*,longdisp")
4128 (set_attr "z10prop" "z10_super,z10_super")])
4130 (define_insn "*insvdi_mem_reghigh"
4131 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
4132 (match_operand 1 "const_int_operand" "n")
4134 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4137 && INTVAL (operands[1]) > 0
4138 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4139 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4141 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4143 operands[1] = GEN_INT ((1ul << size) - 1);
4144 return "stcmh\t%2,%1,%S0";
4146 [(set_attr "op_type" "RSY")
4147 (set_attr "z10prop" "z10_super")])
4149 (define_insn "*insvdi_reg_imm"
4150 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4152 (match_operand 1 "const_int_operand" "n"))
4153 (match_operand:DI 2 "const_int_operand" "n"))]
4155 && INTVAL (operands[1]) >= 0
4156 && INTVAL (operands[1]) < BITS_PER_WORD
4157 && INTVAL (operands[1]) % 16 == 0"
4159 switch (BITS_PER_WORD - INTVAL (operands[1]))
4161 case 64: return "iihh\t%0,%x2"; break;
4162 case 48: return "iihl\t%0,%x2"; break;
4163 case 32: return "iilh\t%0,%x2"; break;
4164 case 16: return "iill\t%0,%x2"; break;
4165 default: gcc_unreachable();
4168 [(set_attr "op_type" "RI")
4169 (set_attr "z10prop" "z10_super_E1")])
4171 ; Update the left-most 32 bit of a DI.
4172 (define_insn "*insv_h_di_reg_extimm"
4173 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4176 (match_operand:DI 1 "const_int_operand" "n"))]
4179 [(set_attr "op_type" "RIL")
4180 (set_attr "z10prop" "z10_fwd_E1")])
4182 ; Update the right-most 32 bit of a DI.
4183 (define_insn "*insv_l_di_reg_extimm"
4184 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4187 (match_operand:DI 1 "const_int_operand" "n"))]
4190 [(set_attr "op_type" "RIL")
4191 (set_attr "z10prop" "z10_fwd_A1")])
4194 ; extendsidi2 instruction pattern(s).
4197 (define_expand "extendsidi2"
4198 [(set (match_operand:DI 0 "register_operand" "")
4199 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4204 emit_clobber (operands[0]);
4205 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4206 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4207 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4212 (define_insn "*extendsidi2"
4213 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4214 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4220 [(set_attr "op_type" "RRE,RXY,RIL")
4221 (set_attr "type" "*,*,larl")
4222 (set_attr "cpu_facility" "*,*,z10")
4223 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4226 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4229 (define_expand "extend<HQI:mode><DSI:mode>2"
4230 [(set (match_operand:DSI 0 "register_operand" "")
4231 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4234 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4236 rtx tmp = gen_reg_rtx (SImode);
4237 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4238 emit_insn (gen_extendsidi2 (operands[0], tmp));
4241 else if (!TARGET_EXTIMM)
4243 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4245 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4246 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4247 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4253 ; extendhidi2 instruction pattern(s).
4256 (define_insn "*extendhidi2_extimm"
4257 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4258 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
4259 "TARGET_ZARCH && TARGET_EXTIMM"
4264 [(set_attr "op_type" "RRE,RXY,RIL")
4265 (set_attr "type" "*,*,larl")
4266 (set_attr "cpu_facility" "extimm,extimm,z10")
4267 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4269 (define_insn "*extendhidi2"
4270 [(set (match_operand:DI 0 "register_operand" "=d")
4271 (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
4274 [(set_attr "op_type" "RXY")
4275 (set_attr "z10prop" "z10_super_E1")])
4278 ; extendhisi2 instruction pattern(s).
4281 (define_insn "*extendhisi2_extimm"
4282 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4283 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4290 [(set_attr "op_type" "RRE,RX,RXY,RIL")
4291 (set_attr "type" "*,*,*,larl")
4292 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4293 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4295 (define_insn "*extendhisi2"
4296 [(set (match_operand:SI 0 "register_operand" "=d,d")
4297 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4302 [(set_attr "op_type" "RX,RXY")
4303 (set_attr "cpu_facility" "*,longdisp")
4304 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4307 ; extendqi(si|di)2 instruction pattern(s).
4310 ; lbr, lgbr, lb, lgb
4311 (define_insn "*extendqi<mode>2_extimm"
4312 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4313 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
4318 [(set_attr "op_type" "RRE,RXY")
4319 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4322 (define_insn "*extendqi<mode>2"
4323 [(set (match_operand:GPR 0 "register_operand" "=d")
4324 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
4325 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4327 [(set_attr "op_type" "RXY")
4328 (set_attr "z10prop" "z10_super_E1")])
4330 (define_insn_and_split "*extendqi<mode>2_short_displ"
4331 [(set (match_operand:GPR 0 "register_operand" "=d")
4332 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4333 (clobber (reg:CC CC_REGNUM))]
4334 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4336 "&& reload_completed"
4338 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4339 (clobber (reg:CC CC_REGNUM))])
4341 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4342 (clobber (reg:CC CC_REGNUM))])]
4344 operands[1] = adjust_address (operands[1], BLKmode, 0);
4345 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4346 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4350 ; zero_extendsidi2 instruction pattern(s).
4353 (define_expand "zero_extendsidi2"
4354 [(set (match_operand:DI 0 "register_operand" "")
4355 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4360 emit_clobber (operands[0]);
4361 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4362 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4367 (define_insn "*zero_extendsidi2"
4368 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4369 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4375 [(set_attr "op_type" "RRE,RXY,RIL")
4376 (set_attr "type" "*,*,larl")
4377 (set_attr "cpu_facility" "*,*,z10")
4378 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4381 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4384 (define_insn "*llgt_sidi"
4385 [(set (match_operand:DI 0 "register_operand" "=d")
4386 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4387 (const_int 2147483647)))]
4390 [(set_attr "op_type" "RXE")
4391 (set_attr "z10prop" "z10_super_E1")])
4393 (define_insn_and_split "*llgt_sidi_split"
4394 [(set (match_operand:DI 0 "register_operand" "=d")
4395 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4396 (const_int 2147483647)))
4397 (clobber (reg:CC CC_REGNUM))]
4400 "&& reload_completed"
4402 (and:DI (subreg:DI (match_dup 1) 0)
4403 (const_int 2147483647)))]
4406 (define_insn "*llgt_sisi"
4407 [(set (match_operand:SI 0 "register_operand" "=d,d")
4408 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
4409 (const_int 2147483647)))]
4414 [(set_attr "op_type" "RRE,RXE")
4415 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4417 (define_insn "*llgt_didi"
4418 [(set (match_operand:DI 0 "register_operand" "=d,d")
4419 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4420 (const_int 2147483647)))]
4425 [(set_attr "op_type" "RRE,RXE")
4426 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4429 [(set (match_operand:DSI 0 "register_operand" "")
4430 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4431 (const_int 2147483647)))
4432 (clobber (reg:CC CC_REGNUM))]
4433 "TARGET_ZARCH && reload_completed"
4435 (and:DSI (match_dup 1)
4436 (const_int 2147483647)))]
4440 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4443 (define_expand "zero_extend<mode>di2"
4444 [(set (match_operand:DI 0 "register_operand" "")
4445 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4450 rtx tmp = gen_reg_rtx (SImode);
4451 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4452 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4455 else if (!TARGET_EXTIMM)
4457 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4458 operands[1] = gen_lowpart (DImode, operands[1]);
4459 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4460 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4465 (define_expand "zero_extend<mode>si2"
4466 [(set (match_operand:SI 0 "register_operand" "")
4467 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4472 operands[1] = gen_lowpart (SImode, operands[1]);
4473 emit_insn (gen_andsi3 (operands[0], operands[1],
4474 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4480 (define_insn "*zero_extendhi<mode>2_z10"
4481 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4482 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
4488 [(set_attr "op_type" "RXY,RRE,RIL")
4489 (set_attr "type" "*,*,larl")
4490 (set_attr "cpu_facility" "*,*,z10")
4491 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4493 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4494 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4495 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4496 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
4501 [(set_attr "op_type" "RRE,RXY")
4502 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4505 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4506 [(set (match_operand:GPR 0 "register_operand" "=d")
4507 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
4508 "TARGET_ZARCH && !TARGET_EXTIMM"
4510 [(set_attr "op_type" "RXY")
4511 (set_attr "z10prop" "z10_fwd_A3")])
4513 (define_insn_and_split "*zero_extendhisi2_31"
4514 [(set (match_operand:SI 0 "register_operand" "=&d")
4515 (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
4516 (clobber (reg:CC CC_REGNUM))]
4519 "&& reload_completed"
4520 [(set (match_dup 0) (const_int 0))
4522 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4523 (clobber (reg:CC CC_REGNUM))])]
4524 "operands[2] = gen_lowpart (HImode, operands[0]);")
4526 (define_insn_and_split "*zero_extendqisi2_31"
4527 [(set (match_operand:SI 0 "register_operand" "=&d")
4528 (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
4531 "&& reload_completed"
4532 [(set (match_dup 0) (const_int 0))
4533 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4534 "operands[2] = gen_lowpart (QImode, operands[0]);")
4537 ; zero_extendqihi2 instruction pattern(s).
4540 (define_expand "zero_extendqihi2"
4541 [(set (match_operand:HI 0 "register_operand" "")
4542 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4543 "TARGET_ZARCH && !TARGET_EXTIMM"
4545 operands[1] = gen_lowpart (HImode, operands[1]);
4546 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4550 (define_insn "*zero_extendqihi2_64"
4551 [(set (match_operand:HI 0 "register_operand" "=d")
4552 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4553 "TARGET_ZARCH && !TARGET_EXTIMM"
4555 [(set_attr "op_type" "RXY")
4556 (set_attr "z10prop" "z10_fwd_A3")])
4558 (define_insn_and_split "*zero_extendqihi2_31"
4559 [(set (match_operand:HI 0 "register_operand" "=&d")
4560 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4563 "&& reload_completed"
4564 [(set (match_dup 0) (const_int 0))
4565 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4566 "operands[2] = gen_lowpart (QImode, operands[0]);")
4569 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4572 (define_expand "fixuns_truncdddi2"
4574 [(set (match_operand:DI 0 "register_operand" "")
4575 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4576 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4577 (clobber (reg:CC CC_REGNUM))])]
4583 rtx_code_label *label1 = gen_label_rtx ();
4584 rtx_code_label *label2 = gen_label_rtx ();
4585 rtx temp = gen_reg_rtx (TDmode);
4586 REAL_VALUE_TYPE cmp, sub;
4588 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4589 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4591 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4592 solution is doing the check and the subtraction in TD mode and using a
4593 TD -> DI convert afterwards. */
4594 emit_insn (gen_extendddtd2 (temp, operands[1]));
4595 temp = force_reg (TDmode, temp);
4596 emit_cmp_and_jump_insns (temp,
4597 const_double_from_real_value (cmp, TDmode),
4598 LT, NULL_RTX, VOIDmode, 0, label1);
4599 emit_insn (gen_subtd3 (temp, temp,
4600 const_double_from_real_value (sub, TDmode)));
4601 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4602 GEN_INT (DFP_RND_TOWARD_MINF)));
4605 emit_label (label1);
4606 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
4607 GEN_INT (DFP_RND_TOWARD_0)));
4608 emit_label (label2);
4613 (define_expand "fixuns_trunctddi2"
4615 [(set (match_operand:DI 0 "register_operand" "")
4616 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4617 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4618 (clobber (reg:CC CC_REGNUM))])]
4624 rtx_code_label *label1 = gen_label_rtx ();
4625 rtx_code_label *label2 = gen_label_rtx ();
4626 rtx temp = gen_reg_rtx (TDmode);
4627 REAL_VALUE_TYPE cmp, sub;
4629 operands[1] = force_reg (TDmode, operands[1]);
4630 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4631 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4633 emit_cmp_and_jump_insns (operands[1],
4634 const_double_from_real_value (cmp, TDmode),
4635 LT, NULL_RTX, VOIDmode, 0, label1);
4636 emit_insn (gen_subtd3 (temp, operands[1],
4637 const_double_from_real_value (sub, TDmode)));
4638 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4639 GEN_INT (DFP_RND_TOWARD_MINF)));
4642 emit_label (label1);
4643 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
4644 GEN_INT (DFP_RND_TOWARD_0)));
4645 emit_label (label2);
4651 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4652 ; instruction pattern(s).
4655 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4657 [(set (match_operand:GPR 0 "register_operand" "")
4658 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4659 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4660 (clobber (reg:CC CC_REGNUM))])]
4665 rtx_code_label *label1 = gen_label_rtx ();
4666 rtx_code_label *label2 = gen_label_rtx ();
4667 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4668 REAL_VALUE_TYPE cmp, sub;
4670 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4671 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4672 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4674 emit_cmp_and_jump_insns (operands[1],
4675 const_double_from_real_value (cmp, <BFP:MODE>mode),
4676 LT, NULL_RTX, VOIDmode, 0, label1);
4677 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4678 const_double_from_real_value (sub, <BFP:MODE>mode)));
4679 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4680 GEN_INT (BFP_RND_TOWARD_MINF)));
4683 emit_label (label1);
4684 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4685 operands[1], GEN_INT (BFP_RND_TOWARD_0)));
4686 emit_label (label2);
4691 ; fixuns_trunc(td|dd)si2 expander
4692 (define_expand "fixuns_trunc<mode>si2"
4694 [(set (match_operand:SI 0 "register_operand" "")
4695 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4696 (unspec:SI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4697 (clobber (reg:CC CC_REGNUM))])]
4698 "TARGET_Z196 && TARGET_HARD_DFP"
4701 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4703 (define_insn "*fixuns_truncdfdi2_z13"
4704 [(set (match_operand:DI 0 "register_operand" "=d,v")
4705 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4706 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4707 (clobber (reg:CC CC_REGNUM))]
4708 "TARGET_VX && TARGET_HARD_FLOAT"
4711 wclgdb\t%v0,%v1,0,%h2"
4712 [(set_attr "op_type" "RRF,VRR")
4713 (set_attr "type" "ftoi")])
4715 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4716 ; clfdtr, clfxtr, clgdtr, clgxtr
4717 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4718 [(set (match_operand:GPR 0 "register_operand" "=d")
4719 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4720 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4721 (clobber (reg:CC CC_REGNUM))]
4722 "TARGET_Z196 && TARGET_HARD_FLOAT
4723 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4724 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4725 [(set_attr "op_type" "RRF")
4726 (set_attr "type" "ftoi")])
4728 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4729 [(set (match_operand:GPR 0 "register_operand" "")
4730 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4733 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4734 GEN_INT (BFP_RND_TOWARD_0)));
4738 (define_insn "*fix_truncdfdi2_bfp_z13"
4739 [(set (match_operand:DI 0 "register_operand" "=d,v")
4740 (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4741 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4742 (clobber (reg:CC CC_REGNUM))]
4743 "TARGET_VX && TARGET_HARD_FLOAT"
4746 wcgdb\t%v0,%v1,0,%h2"
4747 [(set_attr "op_type" "RRE,VRR")
4748 (set_attr "type" "ftoi")])
4750 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4751 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
4752 [(set (match_operand:GPR 0 "register_operand" "=d")
4753 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4754 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4755 (clobber (reg:CC CC_REGNUM))]
4757 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
4758 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4759 [(set_attr "op_type" "RRE")
4760 (set_attr "type" "ftoi")])
4762 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4764 [(set (match_operand:GPR 0 "register_operand" "=d")
4765 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4766 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4767 (clobber (reg:CC CC_REGNUM))])]
4768 "TARGET_HARD_FLOAT")
4770 ; fix_trunc(td|dd)di2 instruction pattern(s).
4773 (define_expand "fix_trunc<mode>di2"
4774 [(set (match_operand:DI 0 "register_operand" "")
4775 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4776 "TARGET_ZARCH && TARGET_HARD_DFP"
4778 operands[1] = force_reg (<MODE>mode, operands[1]);
4779 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4780 GEN_INT (DFP_RND_TOWARD_0)));
4785 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4786 [(set (match_operand:DI 0 "register_operand" "=d")
4787 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4788 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4789 (clobber (reg:CC CC_REGNUM))]
4790 "TARGET_ZARCH && TARGET_HARD_DFP"
4791 "cg<DFP:xde>tr\t%0,%h2,%1"
4792 [(set_attr "op_type" "RRF")
4793 (set_attr "type" "ftoidfp")])
4797 ; fix_trunctf(si|di)2 instruction pattern(s).
4800 (define_expand "fix_trunctf<mode>2"
4801 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4802 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4803 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4804 (clobber (reg:CC CC_REGNUM))])]
4810 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4813 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4814 (define_insn "floatdi<mode>2"
4815 [(set (match_operand:FP 0 "register_operand" "=f,v")
4816 (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
4817 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4821 [(set_attr "op_type" "RRE,VRR")
4822 (set_attr "type" "itof<mode>" )
4823 (set_attr "cpu_facility" "*,vec")
4824 (set_attr "enabled" "*,<DFDI>")])
4826 ; cxfbr, cdfbr, cefbr
4827 (define_insn "floatsi<mode>2"
4828 [(set (match_operand:BFP 0 "register_operand" "=f")
4829 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4832 [(set_attr "op_type" "RRE")
4833 (set_attr "type" "itof<mode>" )])
4836 (define_insn "floatsi<mode>2"
4837 [(set (match_operand:DFP 0 "register_operand" "=f")
4838 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4839 "TARGET_Z196 && TARGET_HARD_FLOAT"
4840 "c<xde>ftr\t%0,0,%1,0"
4841 [(set_attr "op_type" "RRE")
4842 (set_attr "type" "itof<mode>" )])
4845 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4848 (define_insn "*floatunsdidf2_z13"
4849 [(set (match_operand:DF 0 "register_operand" "=f,v")
4850 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
4851 "TARGET_VX && TARGET_HARD_FLOAT"
4854 wcdlgb\t%v0,%v1,0,0"
4855 [(set_attr "op_type" "RRE,VRR")
4856 (set_attr "type" "itofdf")])
4858 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4859 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4860 (define_insn "*floatuns<GPR:mode><FP:mode>2"
4861 [(set (match_operand:FP 0 "register_operand" "=f")
4862 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4863 "TARGET_Z196 && TARGET_HARD_FLOAT
4864 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
4865 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4866 [(set_attr "op_type" "RRE")
4867 (set_attr "type" "itof<FP:mode>")])
4869 (define_expand "floatuns<GPR:mode><FP:mode>2"
4870 [(set (match_operand:FP 0 "register_operand" "")
4871 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
4872 "TARGET_Z196 && TARGET_HARD_FLOAT")
4875 ; truncdfsf2 instruction pattern(s).
4878 (define_insn "truncdfsf2"
4879 [(set (match_operand:SF 0 "register_operand" "=f,v")
4880 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
4884 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
4885 ; According to BFP rounding mode
4886 [(set_attr "op_type" "RRE,VRR")
4887 (set_attr "type" "ftruncdf")
4888 (set_attr "cpu_facility" "*,vec")])
4891 ; trunctf(df|sf)2 instruction pattern(s).
4895 (define_insn "trunctf<mode>2"
4896 [(set (match_operand:DSF 0 "register_operand" "=f")
4897 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4898 (clobber (match_scratch:TF 2 "=f"))]
4900 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4901 [(set_attr "length" "6")
4902 (set_attr "type" "ftrunctf")])
4905 ; trunctddd2 and truncddsd2 instruction pattern(s).
4909 (define_expand "trunctddd2"
4911 [(set (match_operand:DD 0 "register_operand" "")
4912 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4913 (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
4914 (clobber (scratch:TD))])]
4917 (define_insn "*trunctddd2"
4918 [(set (match_operand:DD 0 "register_operand" "=f")
4919 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4920 (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
4921 (clobber (match_scratch:TD 3 "=f"))]
4923 "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
4924 [(set_attr "length" "6")
4925 (set_attr "type" "ftruncdd")])
4927 (define_insn "truncddsd2"
4928 [(set (match_operand:SD 0 "register_operand" "=f")
4929 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4932 [(set_attr "op_type" "RRF")
4933 (set_attr "type" "ftruncsd")])
4935 (define_expand "trunctdsd2"
4938 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4939 (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
4940 (clobber (match_scratch:TD 2 ""))])
4941 (set (match_operand:SD 0 "register_operand" "")
4942 (float_truncate:SD (match_dup 3)))]
4945 operands[3] = gen_reg_rtx (DDmode);
4949 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4952 (define_insn "*extendsfdf2_z13"
4953 [(set (match_operand:DF 0 "register_operand" "=f,f,v")
4954 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
4955 "TARGET_VX && TARGET_HARD_FLOAT"
4960 [(set_attr "op_type" "RRE,RXE,VRR")
4961 (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
4963 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4964 (define_insn "*extend<DSF:mode><BFP:mode>2"
4965 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4966 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4968 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
4969 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
4971 l<BFP:xde><DSF:xde>br\t%0,%1
4972 l<BFP:xde><DSF:xde>b\t%0,%1"
4973 [(set_attr "op_type" "RRE,RXE")
4974 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4976 (define_expand "extend<DSF:mode><BFP:mode>2"
4977 [(set (match_operand:BFP 0 "register_operand" "")
4978 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
4980 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
4983 ; extendddtd2 and extendsddd2 instruction pattern(s).
4986 (define_insn "extendddtd2"
4987 [(set (match_operand:TD 0 "register_operand" "=f")
4988 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4991 [(set_attr "op_type" "RRF")
4992 (set_attr "type" "fsimptf")])
4994 (define_insn "extendsddd2"
4995 [(set (match_operand:DD 0 "register_operand" "=f")
4996 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4999 [(set_attr "op_type" "RRF")
5000 (set_attr "type" "fsimptf")])
5002 (define_expand "extendsdtd2"
5004 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
5005 (set (match_operand:TD 0 "register_operand" "")
5006 (float_extend:TD (match_dup 2)))]
5009 operands[2] = gen_reg_rtx (DDmode);
5012 ; Binary Floating Point - load fp integer
5014 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
5015 ; For all of them the inexact exceptions are suppressed.
5017 ; fiebra, fidbra, fixbra
5018 (define_insn "<FPINT:fpint_name><BFP:mode>2"
5019 [(set (match_operand:BFP 0 "register_operand" "=f")
5020 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5023 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
5024 [(set_attr "op_type" "RRF")
5025 (set_attr "type" "fsimp<BFP:mode>")])
5027 ; rint is supposed to raise an inexact exception so we can use the
5028 ; older instructions.
5030 ; fiebr, fidbr, fixbr
5031 (define_insn "rint<BFP:mode>2"
5032 [(set (match_operand:BFP 0 "register_operand" "=f")
5033 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5034 UNSPEC_FPINT_RINT))]
5036 "fi<BFP:xde>br\t%0,0,%1"
5037 [(set_attr "op_type" "RRF")
5038 (set_attr "type" "fsimp<BFP:mode>")])
5041 ; Decimal Floating Point - load fp integer
5044 (define_insn "<FPINT:fpint_name><DFP:mode>2"
5045 [(set (match_operand:DFP 0 "register_operand" "=f")
5046 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5049 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
5050 [(set_attr "op_type" "RRF")
5051 (set_attr "type" "fsimp<DFP:mode>")])
5054 (define_insn "rint<DFP:mode>2"
5055 [(set (match_operand:DFP 0 "register_operand" "=f")
5056 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5057 UNSPEC_FPINT_RINT))]
5059 "fi<DFP:xde>tr\t%0,0,%1,0"
5060 [(set_attr "op_type" "RRF")
5061 (set_attr "type" "fsimp<DFP:mode>")])
5064 ; Binary <-> Decimal floating point trunc patterns
5067 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
5068 [(set (reg:DFP_ALL FPR0_REGNUM)
5069 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5070 (use (reg:SI GPR0_REGNUM))
5071 (clobber (reg:CC CC_REGNUM))
5072 (clobber (reg:SI GPR1_REGNUM))]
5076 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
5077 [(set (reg:BFP FPR0_REGNUM)
5078 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5079 (use (reg:SI GPR0_REGNUM))
5080 (clobber (reg:CC CC_REGNUM))
5081 (clobber (reg:SI GPR1_REGNUM))]
5085 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
5086 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5087 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5089 [(set (reg:DFP_ALL FPR0_REGNUM)
5090 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5091 (use (reg:SI GPR0_REGNUM))
5092 (clobber (reg:CC CC_REGNUM))
5093 (clobber (reg:SI GPR1_REGNUM))])
5094 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5095 (reg:DFP_ALL FPR0_REGNUM))]
5097 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5099 HOST_WIDE_INT flags;
5101 flags = (PFPO_CONVERT |
5102 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5103 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5105 operands[2] = GEN_INT (flags);
5108 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5109 [(set (reg:DFP_ALL FPR4_REGNUM)
5110 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5111 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5113 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5114 (use (reg:SI GPR0_REGNUM))
5115 (clobber (reg:CC CC_REGNUM))
5116 (clobber (reg:SI GPR1_REGNUM))])
5117 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5119 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5121 HOST_WIDE_INT flags;
5123 flags = (PFPO_CONVERT |
5124 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5125 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5127 operands[2] = GEN_INT (flags);
5131 ; Binary <-> Decimal floating point extend patterns
5134 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5135 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5136 (use (reg:SI GPR0_REGNUM))
5137 (clobber (reg:CC CC_REGNUM))
5138 (clobber (reg:SI GPR1_REGNUM))]
5142 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5143 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5144 (use (reg:SI GPR0_REGNUM))
5145 (clobber (reg:CC CC_REGNUM))
5146 (clobber (reg:SI GPR1_REGNUM))]
5150 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5151 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5152 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5154 [(set (reg:DFP_ALL FPR0_REGNUM)
5155 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5156 (use (reg:SI GPR0_REGNUM))
5157 (clobber (reg:CC CC_REGNUM))
5158 (clobber (reg:SI GPR1_REGNUM))])
5159 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5160 (reg:DFP_ALL FPR0_REGNUM))]
5162 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5164 HOST_WIDE_INT flags;
5166 flags = (PFPO_CONVERT |
5167 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5168 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5170 operands[2] = GEN_INT (flags);
5173 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5174 [(set (reg:DFP_ALL FPR4_REGNUM)
5175 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5176 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5178 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5179 (use (reg:SI GPR0_REGNUM))
5180 (clobber (reg:CC CC_REGNUM))
5181 (clobber (reg:SI GPR1_REGNUM))])
5182 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5184 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5186 HOST_WIDE_INT flags;
5188 flags = (PFPO_CONVERT |
5189 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5190 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5192 operands[2] = GEN_INT (flags);
5197 ;; ARITHMETIC OPERATIONS
5199 ; arithmetic operations set the ConditionCode,
5200 ; because of unpredictable Bits in Register for Halfword and Byte
5201 ; the ConditionCode can be set wrong in operations for Halfword and Byte
5204 ;;- Add instructions.
5208 ; addti3 instruction pattern(s).
5211 (define_expand "addti3"
5213 [(set (match_operand:TI 0 "register_operand" "")
5214 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5215 (match_operand:TI 2 "general_operand" "") ) )
5216 (clobber (reg:CC CC_REGNUM))])]
5219 /* For z13 we have vaq which doesn't set CC. */
5222 emit_insn (gen_rtx_SET (operands[0],
5223 gen_rtx_PLUS (TImode,
5224 copy_to_mode_reg (TImode, operands[1]),
5225 copy_to_mode_reg (TImode, operands[2]))));
5230 (define_insn_and_split "*addti3"
5231 [(set (match_operand:TI 0 "register_operand" "=&d")
5232 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5233 (match_operand:TI 2 "general_operand" "do") ) )
5234 (clobber (reg:CC CC_REGNUM))]
5237 "&& reload_completed"
5239 [(set (reg:CCL1 CC_REGNUM)
5240 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5242 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5244 [(set (match_dup 3) (plus:DI
5245 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5246 (match_dup 4)) (match_dup 5)))
5247 (clobber (reg:CC CC_REGNUM))])]
5248 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5249 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5250 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5251 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5252 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5253 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5254 [(set_attr "op_type" "*")
5255 (set_attr "cpu_facility" "*")])
5258 ; adddi3 instruction pattern(s).
5261 (define_expand "adddi3"
5263 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5264 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5265 (match_operand:DI 2 "general_operand" "")))
5266 (clobber (reg:CC CC_REGNUM))])]
5270 (define_insn "*adddi3_sign"
5271 [(set (match_operand:DI 0 "register_operand" "=d,d")
5272 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5273 (match_operand:DI 1 "register_operand" "0,0")))
5274 (clobber (reg:CC CC_REGNUM))]
5279 [(set_attr "op_type" "RRE,RXY")
5280 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5282 (define_insn "*adddi3_zero_cc"
5283 [(set (reg CC_REGNUM)
5284 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5285 (match_operand:DI 1 "register_operand" "0,0"))
5287 (set (match_operand:DI 0 "register_operand" "=d,d")
5288 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5289 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5293 [(set_attr "op_type" "RRE,RXY")
5294 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5296 (define_insn "*adddi3_zero_cconly"
5297 [(set (reg CC_REGNUM)
5298 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5299 (match_operand:DI 1 "register_operand" "0,0"))
5301 (clobber (match_scratch:DI 0 "=d,d"))]
5302 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5306 [(set_attr "op_type" "RRE,RXY")
5307 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5309 (define_insn "*adddi3_zero"
5310 [(set (match_operand:DI 0 "register_operand" "=d,d")
5311 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5312 (match_operand:DI 1 "register_operand" "0,0")))
5313 (clobber (reg:CC CC_REGNUM))]
5318 [(set_attr "op_type" "RRE,RXY")
5319 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5321 (define_insn_and_split "*adddi3_31z"
5322 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5323 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5324 (match_operand:DI 2 "general_operand" "do") ) )
5325 (clobber (reg:CC CC_REGNUM))]
5326 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5328 "&& reload_completed"
5330 [(set (reg:CCL1 CC_REGNUM)
5331 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5333 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5335 [(set (match_dup 3) (plus:SI
5336 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5337 (match_dup 4)) (match_dup 5)))
5338 (clobber (reg:CC CC_REGNUM))])]
5339 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5340 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5341 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5342 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5343 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5344 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5346 (define_insn_and_split "*adddi3_31"
5347 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5348 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5349 (match_operand:DI 2 "general_operand" "do") ) )
5350 (clobber (reg:CC CC_REGNUM))]
5353 "&& reload_completed"
5355 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5356 (clobber (reg:CC CC_REGNUM))])
5358 [(set (reg:CCL1 CC_REGNUM)
5359 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5361 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5363 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5365 (label_ref (match_dup 9))))
5367 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5368 (clobber (reg:CC CC_REGNUM))])
5370 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5371 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5372 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5373 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5374 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5375 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5376 operands[9] = gen_label_rtx ();")
5379 ; addsi3 instruction pattern(s).
5382 (define_expand "addsi3"
5384 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5385 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5386 (match_operand:SI 2 "general_operand" "")))
5387 (clobber (reg:CC CC_REGNUM))])]
5391 (define_insn "*addsi3_sign"
5392 [(set (match_operand:SI 0 "register_operand" "=d,d")
5393 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5394 (match_operand:SI 1 "register_operand" "0,0")))
5395 (clobber (reg:CC CC_REGNUM))]
5400 [(set_attr "op_type" "RX,RXY")
5401 (set_attr "cpu_facility" "*,longdisp")
5402 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5405 ; add(di|si)3 instruction pattern(s).
5408 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5409 (define_insn "*add<mode>3"
5410 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
5411 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
5412 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
5413 (clobber (reg:CC CC_REGNUM))]
5425 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5426 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
5427 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5428 z10_super_E1,z10_super_E1,z10_super_E1")])
5430 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5431 (define_insn "*add<mode>3_carry1_cc"
5432 [(set (reg CC_REGNUM)
5433 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5434 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5436 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5437 (plus:GPR (match_dup 1) (match_dup 2)))]
5438 "s390_match_ccmode (insn, CCL1mode)"
5444 al<g>hsik\t%0,%1,%h2
5448 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5449 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5450 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5451 z10_super_E1,z10_super_E1,z10_super_E1")])
5453 ; alr, al, aly, algr, alg, alrk, algrk
5454 (define_insn "*add<mode>3_carry1_cconly"
5455 [(set (reg CC_REGNUM)
5456 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5457 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5459 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5460 "s390_match_ccmode (insn, CCL1mode)"
5466 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5467 (set_attr "cpu_facility" "*,z196,*,longdisp")
5468 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5470 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5471 (define_insn "*add<mode>3_carry2_cc"
5472 [(set (reg CC_REGNUM)
5473 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5474 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5476 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5477 (plus:GPR (match_dup 1) (match_dup 2)))]
5478 "s390_match_ccmode (insn, CCL1mode)"
5484 al<g>hsik\t%0,%1,%h2
5488 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5489 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5490 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5491 z10_super_E1,z10_super_E1,z10_super_E1")])
5493 ; alr, al, aly, algr, alg, alrk, algrk
5494 (define_insn "*add<mode>3_carry2_cconly"
5495 [(set (reg CC_REGNUM)
5496 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5497 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5499 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5500 "s390_match_ccmode (insn, CCL1mode)"
5506 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5507 (set_attr "cpu_facility" "*,z196,*,longdisp")
5508 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5510 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5511 (define_insn "*add<mode>3_cc"
5512 [(set (reg CC_REGNUM)
5513 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5514 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5516 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5517 (plus:GPR (match_dup 1) (match_dup 2)))]
5518 "s390_match_ccmode (insn, CCLmode)"
5524 al<g>hsik\t%0,%1,%h2
5528 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5529 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5530 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5531 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5533 ; alr, al, aly, algr, alg, alrk, algrk
5534 (define_insn "*add<mode>3_cconly"
5535 [(set (reg CC_REGNUM)
5536 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5537 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5539 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5540 "s390_match_ccmode (insn, CCLmode)"
5546 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5547 (set_attr "cpu_facility" "*,z196,*,longdisp")
5548 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5550 ; alr, al, aly, algr, alg, alrk, algrk
5551 (define_insn "*add<mode>3_cconly2"
5552 [(set (reg CC_REGNUM)
5553 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5554 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5555 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5556 "s390_match_ccmode(insn, CCLmode)"
5562 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5563 (set_attr "cpu_facility" "*,z196,*,longdisp")
5564 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5566 ; ahi, afi, aghi, agfi, asi, agsi
5567 (define_insn "*add<mode>3_imm_cc"
5568 [(set (reg CC_REGNUM)
5569 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5570 (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
5572 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
5573 (plus:GPR (match_dup 1) (match_dup 2)))]
5574 "s390_match_ccmode (insn, CCAmode)
5575 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5576 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5577 /* Avoid INT32_MIN on 32 bit. */
5578 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5584 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5585 (set_attr "cpu_facility" "*,z196,extimm,z10")
5586 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5589 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5592 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5593 ; FIXME: wfadb does not clobber cc
5594 (define_insn "add<mode>3"
5595 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
5596 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
5597 (match_operand:FP 2 "general_operand" "f,f,R,v")))
5598 (clobber (reg:CC CC_REGNUM))]
5605 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
5606 (set_attr "type" "fsimp<mode>")
5607 (set_attr "cpu_facility" "*,*,*,vec")
5608 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
5610 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5611 (define_insn "*add<mode>3_cc"
5612 [(set (reg CC_REGNUM)
5613 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5614 (match_operand:FP 2 "general_operand" "f,f,R"))
5615 (match_operand:FP 3 "const0_operand" "")))
5616 (set (match_operand:FP 0 "register_operand" "=f,f,f")
5617 (plus:FP (match_dup 1) (match_dup 2)))]
5618 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5623 [(set_attr "op_type" "RRF,RRE,RXE")
5624 (set_attr "type" "fsimp<mode>")
5625 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5627 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5628 (define_insn "*add<mode>3_cconly"
5629 [(set (reg CC_REGNUM)
5630 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5631 (match_operand:FP 2 "general_operand" "f,f,R"))
5632 (match_operand:FP 3 "const0_operand" "")))
5633 (clobber (match_scratch:FP 0 "=f,f,f"))]
5634 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5639 [(set_attr "op_type" "RRF,RRE,RXE")
5640 (set_attr "type" "fsimp<mode>")
5641 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5644 ; Pointer add instruction patterns
5647 ; This will match "*la_64"
5648 (define_expand "addptrdi3"
5649 [(set (match_operand:DI 0 "register_operand" "")
5650 (plus:DI (match_operand:DI 1 "register_operand" "")
5651 (match_operand:DI 2 "nonmemory_operand" "")))]
5654 if (GET_CODE (operands[2]) == CONST_INT)
5656 HOST_WIDE_INT c = INTVAL (operands[2]);
5658 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5659 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5661 operands[2] = force_const_mem (DImode, operands[2]);
5662 operands[2] = force_reg (DImode, operands[2]);
5664 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5665 operands[2] = force_reg (DImode, operands[2]);
5669 ; For 31 bit we have to prevent the generated pattern from matching
5670 ; normal ADDs since la only does a 31 bit add. This is supposed to
5671 ; match "force_la_31".
5672 (define_expand "addptrsi3"
5674 [(set (match_operand:SI 0 "register_operand" "")
5675 (plus:SI (match_operand:SI 1 "register_operand" "")
5676 (match_operand:SI 2 "nonmemory_operand" "")))
5677 (use (const_int 0))])]
5680 if (GET_CODE (operands[2]) == CONST_INT)
5682 HOST_WIDE_INT c = INTVAL (operands[2]);
5684 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5685 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5687 operands[2] = force_const_mem (SImode, operands[2]);
5688 operands[2] = force_reg (SImode, operands[2]);
5690 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5691 operands[2] = force_reg (SImode, operands[2]);
5696 ;;- Subtract instructions.
5700 ; subti3 instruction pattern(s).
5703 (define_expand "subti3"
5705 [(set (match_operand:TI 0 "register_operand" "")
5706 (minus:TI (match_operand:TI 1 "register_operand" "")
5707 (match_operand:TI 2 "general_operand" "") ) )
5708 (clobber (reg:CC CC_REGNUM))])]
5711 /* For z13 we have vsq which doesn't set CC. */
5714 emit_insn (gen_rtx_SET (operands[0],
5715 gen_rtx_MINUS (TImode,
5717 copy_to_mode_reg (TImode, operands[2]))));
5722 (define_insn_and_split "*subti3"
5723 [(set (match_operand:TI 0 "register_operand" "=&d")
5724 (minus:TI (match_operand:TI 1 "register_operand" "0")
5725 (match_operand:TI 2 "general_operand" "do") ) )
5726 (clobber (reg:CC CC_REGNUM))]
5729 "&& reload_completed"
5731 [(set (reg:CCL2 CC_REGNUM)
5732 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5734 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5736 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5737 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5738 (clobber (reg:CC CC_REGNUM))])]
5739 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5740 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5741 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5742 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5743 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5744 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5745 [(set_attr "op_type" "*")
5746 (set_attr "cpu_facility" "*")])
5749 ; subdi3 instruction pattern(s).
5752 (define_expand "subdi3"
5754 [(set (match_operand:DI 0 "register_operand" "")
5755 (minus:DI (match_operand:DI 1 "register_operand" "")
5756 (match_operand:DI 2 "general_operand" "")))
5757 (clobber (reg:CC CC_REGNUM))])]
5761 (define_insn "*subdi3_sign"
5762 [(set (match_operand:DI 0 "register_operand" "=d,d")
5763 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5764 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5765 (clobber (reg:CC CC_REGNUM))]
5770 [(set_attr "op_type" "RRE,RXY")
5771 (set_attr "z10prop" "z10_c,*")
5772 (set_attr "z196prop" "z196_cracked")])
5774 (define_insn "*subdi3_zero_cc"
5775 [(set (reg CC_REGNUM)
5776 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5777 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5779 (set (match_operand:DI 0 "register_operand" "=d,d")
5780 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5781 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5785 [(set_attr "op_type" "RRE,RXY")
5786 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5788 (define_insn "*subdi3_zero_cconly"
5789 [(set (reg CC_REGNUM)
5790 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5791 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
5793 (clobber (match_scratch:DI 0 "=d,d"))]
5794 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5798 [(set_attr "op_type" "RRE,RXY")
5799 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5801 (define_insn "*subdi3_zero"
5802 [(set (match_operand:DI 0 "register_operand" "=d,d")
5803 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5804 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
5805 (clobber (reg:CC CC_REGNUM))]
5810 [(set_attr "op_type" "RRE,RXY")
5811 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5813 (define_insn_and_split "*subdi3_31z"
5814 [(set (match_operand:DI 0 "register_operand" "=&d")
5815 (minus:DI (match_operand:DI 1 "register_operand" "0")
5816 (match_operand:DI 2 "general_operand" "do") ) )
5817 (clobber (reg:CC CC_REGNUM))]
5818 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5820 "&& reload_completed"
5822 [(set (reg:CCL2 CC_REGNUM)
5823 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5825 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5827 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5828 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5829 (clobber (reg:CC CC_REGNUM))])]
5830 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5831 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5832 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5833 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5834 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5835 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5837 (define_insn_and_split "*subdi3_31"
5838 [(set (match_operand:DI 0 "register_operand" "=&d")
5839 (minus:DI (match_operand:DI 1 "register_operand" "0")
5840 (match_operand:DI 2 "general_operand" "do") ) )
5841 (clobber (reg:CC CC_REGNUM))]
5844 "&& reload_completed"
5846 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5847 (clobber (reg:CC CC_REGNUM))])
5849 [(set (reg:CCL2 CC_REGNUM)
5850 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5852 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5854 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5856 (label_ref (match_dup 9))))
5858 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5859 (clobber (reg:CC CC_REGNUM))])
5861 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5862 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5863 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5864 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5865 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5866 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5867 operands[9] = gen_label_rtx ();")
5870 ; subsi3 instruction pattern(s).
5873 (define_expand "subsi3"
5875 [(set (match_operand:SI 0 "register_operand" "")
5876 (minus:SI (match_operand:SI 1 "register_operand" "")
5877 (match_operand:SI 2 "general_operand" "")))
5878 (clobber (reg:CC CC_REGNUM))])]
5882 (define_insn "*subsi3_sign"
5883 [(set (match_operand:SI 0 "register_operand" "=d,d")
5884 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5885 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5886 (clobber (reg:CC CC_REGNUM))]
5891 [(set_attr "op_type" "RX,RXY")
5892 (set_attr "cpu_facility" "*,longdisp")
5893 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5896 ; sub(di|si)3 instruction pattern(s).
5899 ; sr, s, sy, sgr, sg, srk, sgrk
5900 (define_insn "*sub<mode>3"
5901 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5902 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5903 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5904 (clobber (reg:CC CC_REGNUM))]
5911 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5912 (set_attr "cpu_facility" "*,z196,*,longdisp")
5913 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5915 ; slr, sl, sly, slgr, slg, slrk, slgrk
5916 (define_insn "*sub<mode>3_borrow_cc"
5917 [(set (reg CC_REGNUM)
5918 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5919 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5921 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5922 (minus:GPR (match_dup 1) (match_dup 2)))]
5923 "s390_match_ccmode (insn, CCL2mode)"
5929 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5930 (set_attr "cpu_facility" "*,z196,*,longdisp")
5931 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5933 ; slr, sl, sly, slgr, slg, slrk, slgrk
5934 (define_insn "*sub<mode>3_borrow_cconly"
5935 [(set (reg CC_REGNUM)
5936 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5937 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5939 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5940 "s390_match_ccmode (insn, CCL2mode)"
5946 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5947 (set_attr "cpu_facility" "*,z196,*,longdisp")
5948 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5950 ; slr, sl, sly, slgr, slg, slrk, slgrk
5951 (define_insn "*sub<mode>3_cc"
5952 [(set (reg CC_REGNUM)
5953 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5954 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5956 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5957 (minus:GPR (match_dup 1) (match_dup 2)))]
5958 "s390_match_ccmode (insn, CCLmode)"
5964 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5965 (set_attr "cpu_facility" "*,z196,*,longdisp")
5966 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5968 ; slr, sl, sly, slgr, slg, slrk, slgrk
5969 (define_insn "*sub<mode>3_cc2"
5970 [(set (reg CC_REGNUM)
5971 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5972 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5973 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5974 (minus:GPR (match_dup 1) (match_dup 2)))]
5975 "s390_match_ccmode (insn, CCL3mode)"
5981 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5982 (set_attr "cpu_facility" "*,z196,*,longdisp")
5983 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5985 ; slr, sl, sly, slgr, slg, slrk, slgrk
5986 (define_insn "*sub<mode>3_cconly"
5987 [(set (reg CC_REGNUM)
5988 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5989 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5991 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5992 "s390_match_ccmode (insn, CCLmode)"
5998 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5999 (set_attr "cpu_facility" "*,z196,*,longdisp")
6000 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6003 ; slr, sl, sly, slgr, slg, slrk, slgrk
6004 (define_insn "*sub<mode>3_cconly2"
6005 [(set (reg CC_REGNUM)
6006 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6007 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6008 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6009 "s390_match_ccmode (insn, CCL3mode)"
6015 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6016 (set_attr "cpu_facility" "*,z196,*,longdisp")
6017 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6021 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
6024 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6025 (define_insn "sub<mode>3"
6026 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6027 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
6028 (match_operand:FP 2 "general_operand" "f,f,R,v")))
6029 (clobber (reg:CC CC_REGNUM))]
6036 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6037 (set_attr "type" "fsimp<mode>")
6038 (set_attr "cpu_facility" "*,*,*,vec")
6039 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6041 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6042 (define_insn "*sub<mode>3_cc"
6043 [(set (reg CC_REGNUM)
6044 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6045 (match_operand:FP 2 "general_operand" "f,f,R"))
6046 (match_operand:FP 3 "const0_operand" "")))
6047 (set (match_operand:FP 0 "register_operand" "=f,f,f")
6048 (minus:FP (match_dup 1) (match_dup 2)))]
6049 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6054 [(set_attr "op_type" "RRF,RRE,RXE")
6055 (set_attr "type" "fsimp<mode>")
6056 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6058 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6059 (define_insn "*sub<mode>3_cconly"
6060 [(set (reg CC_REGNUM)
6061 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6062 (match_operand:FP 2 "general_operand" "f,f,R"))
6063 (match_operand:FP 3 "const0_operand" "")))
6064 (clobber (match_scratch:FP 0 "=f,f,f"))]
6065 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6070 [(set_attr "op_type" "RRF,RRE,RXE")
6071 (set_attr "type" "fsimp<mode>")
6072 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6076 ;;- Conditional add/subtract instructions.
6080 ; add(di|si)cc instruction pattern(s).
6083 ; the following 4 patterns are used when the result of an add with
6084 ; carry is checked for an overflow condition
6086 ; op1 + op2 + c < op1
6088 ; alcr, alc, alcgr, alcg
6089 (define_insn "*add<mode>3_alc_carry1_cc"
6090 [(set (reg CC_REGNUM)
6092 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6093 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6094 (match_operand:GPR 2 "general_operand" "d,T"))
6096 (set (match_operand:GPR 0 "register_operand" "=d,d")
6097 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6098 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6102 [(set_attr "op_type" "RRE,RXY")
6103 (set_attr "z196prop" "z196_alone,z196_alone")])
6105 ; alcr, alc, alcgr, alcg
6106 (define_insn "*add<mode>3_alc_carry1_cconly"
6107 [(set (reg CC_REGNUM)
6109 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6110 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6111 (match_operand:GPR 2 "general_operand" "d,T"))
6113 (clobber (match_scratch:GPR 0 "=d,d"))]
6114 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6118 [(set_attr "op_type" "RRE,RXY")
6119 (set_attr "z196prop" "z196_alone,z196_alone")])
6121 ; op1 + op2 + c < op2
6123 ; alcr, alc, alcgr, alcg
6124 (define_insn "*add<mode>3_alc_carry2_cc"
6125 [(set (reg CC_REGNUM)
6127 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6128 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6129 (match_operand:GPR 2 "general_operand" "d,T"))
6131 (set (match_operand:GPR 0 "register_operand" "=d,d")
6132 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6133 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6137 [(set_attr "op_type" "RRE,RXY")])
6139 ; alcr, alc, alcgr, alcg
6140 (define_insn "*add<mode>3_alc_carry2_cconly"
6141 [(set (reg CC_REGNUM)
6143 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6144 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6145 (match_operand:GPR 2 "general_operand" "d,T"))
6147 (clobber (match_scratch:GPR 0 "=d,d"))]
6148 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6152 [(set_attr "op_type" "RRE,RXY")])
6154 ; alcr, alc, alcgr, alcg
6155 (define_insn "*add<mode>3_alc_cc"
6156 [(set (reg CC_REGNUM)
6158 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6159 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6160 (match_operand:GPR 2 "general_operand" "d,T"))
6162 (set (match_operand:GPR 0 "register_operand" "=d,d")
6163 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6164 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6168 [(set_attr "op_type" "RRE,RXY")])
6170 ; alcr, alc, alcgr, alcg
6171 (define_insn "*add<mode>3_alc"
6172 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6173 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6174 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6175 (match_operand:GPR 2 "general_operand" "d,T")))
6176 (clobber (reg:CC CC_REGNUM))]
6181 [(set_attr "op_type" "RRE,RXY")])
6183 ; slbr, slb, slbgr, slbg
6184 (define_insn "*sub<mode>3_slb_cc"
6185 [(set (reg CC_REGNUM)
6187 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6188 (match_operand:GPR 2 "general_operand" "d,T"))
6189 (match_operand:GPR 3 "s390_slb_comparison" ""))
6191 (set (match_operand:GPR 0 "register_operand" "=d,d")
6192 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6193 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6197 [(set_attr "op_type" "RRE,RXY")
6198 (set_attr "z10prop" "z10_c,*")])
6200 ; slbr, slb, slbgr, slbg
6201 (define_insn "*sub<mode>3_slb"
6202 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6203 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6204 (match_operand:GPR 2 "general_operand" "d,T"))
6205 (match_operand:GPR 3 "s390_slb_comparison" "")))
6206 (clobber (reg:CC CC_REGNUM))]
6211 [(set_attr "op_type" "RRE,RXY")
6212 (set_attr "z10prop" "z10_c,*")])
6214 (define_expand "add<mode>cc"
6215 [(match_operand:GPR 0 "register_operand" "")
6216 (match_operand 1 "comparison_operator" "")
6217 (match_operand:GPR 2 "register_operand" "")
6218 (match_operand:GPR 3 "const_int_operand" "")]
6220 "if (!s390_expand_addcc (GET_CODE (operands[1]),
6221 XEXP (operands[1], 0), XEXP (operands[1], 1),
6222 operands[0], operands[2],
6223 operands[3])) FAIL; DONE;")
6226 ; scond instruction pattern(s).
6229 (define_insn_and_split "*scond<mode>"
6230 [(set (match_operand:GPR 0 "register_operand" "=&d")
6231 (match_operand:GPR 1 "s390_alc_comparison" ""))
6232 (clobber (reg:CC CC_REGNUM))]
6235 "&& reload_completed"
6236 [(set (match_dup 0) (const_int 0))
6238 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6240 (clobber (reg:CC CC_REGNUM))])]
6243 (define_insn_and_split "*scond<mode>_neg"
6244 [(set (match_operand:GPR 0 "register_operand" "=&d")
6245 (match_operand:GPR 1 "s390_slb_comparison" ""))
6246 (clobber (reg:CC CC_REGNUM))]
6249 "&& reload_completed"
6250 [(set (match_dup 0) (const_int 0))
6252 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6254 (clobber (reg:CC CC_REGNUM))])
6256 [(set (match_dup 0) (neg:GPR (match_dup 0)))
6257 (clobber (reg:CC CC_REGNUM))])]
6261 (define_expand "cstore<mode>4"
6262 [(set (match_operand:SI 0 "register_operand" "")
6263 (match_operator:SI 1 "s390_scond_operator"
6264 [(match_operand:GPR 2 "register_operand" "")
6265 (match_operand:GPR 3 "general_operand" "")]))]
6267 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6268 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6270 (define_expand "cstorecc4"
6272 [(set (match_operand:SI 0 "register_operand" "")
6273 (match_operator:SI 1 "s390_eqne_operator"
6274 [(match_operand:CCZ1 2 "register_operand")
6275 (match_operand 3 "const0_operand")]))
6276 (clobber (reg:CC CC_REGNUM))])]
6278 "emit_insn (gen_sne (operands[0], operands[2]));
6279 if (GET_CODE (operands[1]) == EQ)
6280 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6283 (define_insn_and_split "sne"
6284 [(set (match_operand:SI 0 "register_operand" "=d")
6285 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6287 (clobber (reg:CC CC_REGNUM))]
6292 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6293 (clobber (reg:CC CC_REGNUM))])])
6297 ;; - Conditional move instructions (introduced with z196)
6300 (define_expand "mov<mode>cc"
6301 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6302 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6303 (match_operand:GPR 2 "nonimmediate_operand" "")
6304 (match_operand:GPR 3 "nonimmediate_operand" "")))]
6307 /* Emit the comparison insn in case we do not already have a comparison result. */
6308 if (!s390_comparison (operands[1], VOIDmode))
6309 operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6310 XEXP (operands[1], 0),
6311 XEXP (operands[1], 1));
6314 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
6315 (define_insn_and_split "*mov<mode>cc"
6316 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S,&d")
6318 (match_operator 1 "s390_comparison"
6319 [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c")
6320 (match_operand 5 "const_int_operand" "")])
6321 (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
6322 (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
6334 "&& reload_completed
6335 && MEM_P (operands[3]) && MEM_P (operands[4])"
6338 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6343 (match_op_dup 1 [(match_dup 2) (const_int 0)])
6347 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
6348 (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
6351 ;;- Multiply instructions.
6355 ; muldi3 instruction pattern(s).
6358 (define_insn "*muldi3_sign"
6359 [(set (match_operand:DI 0 "register_operand" "=d,d")
6360 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
6361 (match_operand:DI 1 "register_operand" "0,0")))]
6366 [(set_attr "op_type" "RRE,RXY")
6367 (set_attr "type" "imuldi")])
6369 (define_insn "muldi3"
6370 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
6371 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
6372 (match_operand:DI 2 "general_operand" "d,K,T,Os")))]
6379 [(set_attr "op_type" "RRE,RI,RXY,RIL")
6380 (set_attr "type" "imuldi")
6381 (set_attr "cpu_facility" "*,*,*,z10")])
6384 ; mulsi3 instruction pattern(s).
6387 (define_insn "*mulsi3_sign"
6388 [(set (match_operand:SI 0 "register_operand" "=d,d")
6389 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6390 (match_operand:SI 1 "register_operand" "0,0")))]
6395 [(set_attr "op_type" "RX,RXY")
6396 (set_attr "type" "imulhi")
6397 (set_attr "cpu_facility" "*,z10")])
6399 (define_insn "mulsi3"
6400 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6401 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
6402 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
6410 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
6411 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
6412 (set_attr "cpu_facility" "*,*,*,longdisp,z10")])
6415 ; mulsidi3 instruction pattern(s).
6418 (define_insn "mulsidi3"
6419 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6420 (mult:DI (sign_extend:DI
6421 (match_operand:SI 1 "register_operand" "%0,0,0"))
6423 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6429 [(set_attr "op_type" "RR,RX,RXY")
6430 (set_attr "type" "imulsi")
6431 (set_attr "cpu_facility" "*,*,z10")])
6434 ; umul instruction pattern(s).
6437 ; mlr, ml, mlgr, mlg
6438 (define_insn "umul<dwh><mode>3"
6439 [(set (match_operand:DW 0 "register_operand" "=d,d")
6440 (mult:DW (zero_extend:DW
6441 (match_operand:<DWH> 1 "register_operand" "%0,0"))
6443 (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
6448 [(set_attr "op_type" "RRE,RXY")
6449 (set_attr "type" "imul<dwh>")])
6452 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6455 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6456 (define_insn "mul<mode>3"
6457 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6458 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
6459 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
6466 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6467 (set_attr "type" "fmul<mode>")
6468 (set_attr "cpu_facility" "*,*,*,vec")
6469 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6471 ; madbr, maebr, maxb, madb, maeb
6472 (define_insn "fma<mode>4"
6473 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6474 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6475 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6476 (match_operand:DSF 3 "register_operand" "0,0,v")))]
6481 wfmadb\t%v0,%v1,%v2,%v3"
6482 [(set_attr "op_type" "RRE,RXE,VRR")
6483 (set_attr "type" "fmadd<mode>")
6484 (set_attr "cpu_facility" "*,*,vec")
6485 (set_attr "enabled" "*,*,<DFDI>")])
6487 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6488 (define_insn "fms<mode>4"
6489 [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
6490 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
6491 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
6492 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))]
6497 wfmsdb\t%v0,%v1,%v2,%v3"
6498 [(set_attr "op_type" "RRE,RXE,VRR")
6499 (set_attr "type" "fmadd<mode>")
6500 (set_attr "cpu_facility" "*,*,vec")
6501 (set_attr "enabled" "*,*,<DFDI>")])
6504 ;;- Divide and modulo instructions.
6508 ; divmoddi4 instruction pattern(s).
6511 (define_expand "divmoddi4"
6512 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6513 (div:DI (match_operand:DI 1 "register_operand" "")
6514 (match_operand:DI 2 "general_operand" "")))
6515 (set (match_operand:DI 3 "general_operand" "")
6516 (mod:DI (match_dup 1) (match_dup 2)))])
6517 (clobber (match_dup 4))]
6520 rtx insn, div_equal, mod_equal;
6522 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6523 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6525 operands[4] = gen_reg_rtx(TImode);
6526 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6528 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6529 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6531 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6532 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6537 (define_insn "divmodtidi3"
6538 [(set (match_operand:TI 0 "register_operand" "=d,d")
6542 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6543 (match_operand:DI 2 "general_operand" "d,T")))
6545 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6550 [(set_attr "op_type" "RRE,RXY")
6551 (set_attr "type" "idiv")])
6553 (define_insn "divmodtisi3"
6554 [(set (match_operand:TI 0 "register_operand" "=d,d")
6558 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6560 (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
6563 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6568 [(set_attr "op_type" "RRE,RXY")
6569 (set_attr "type" "idiv")])
6572 ; udivmoddi4 instruction pattern(s).
6575 (define_expand "udivmoddi4"
6576 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6577 (udiv:DI (match_operand:DI 1 "general_operand" "")
6578 (match_operand:DI 2 "nonimmediate_operand" "")))
6579 (set (match_operand:DI 3 "general_operand" "")
6580 (umod:DI (match_dup 1) (match_dup 2)))])
6581 (clobber (match_dup 4))]
6584 rtx insn, div_equal, mod_equal, equal;
6586 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6587 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6588 equal = gen_rtx_IOR (TImode,
6589 gen_rtx_ASHIFT (TImode,
6590 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6592 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6594 operands[4] = gen_reg_rtx(TImode);
6595 emit_clobber (operands[4]);
6596 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6597 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6599 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6600 set_unique_reg_note (insn, REG_EQUAL, equal);
6602 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6603 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6605 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6606 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6611 (define_insn "udivmodtidi3"
6612 [(set (match_operand:TI 0 "register_operand" "=d,d")
6617 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6619 (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
6623 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6628 [(set_attr "op_type" "RRE,RXY")
6629 (set_attr "type" "idiv")])
6632 ; divmodsi4 instruction pattern(s).
6635 (define_expand "divmodsi4"
6636 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6637 (div:SI (match_operand:SI 1 "general_operand" "")
6638 (match_operand:SI 2 "nonimmediate_operand" "")))
6639 (set (match_operand:SI 3 "general_operand" "")
6640 (mod:SI (match_dup 1) (match_dup 2)))])
6641 (clobber (match_dup 4))]
6644 rtx insn, div_equal, mod_equal, equal;
6646 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6647 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6648 equal = gen_rtx_IOR (DImode,
6649 gen_rtx_ASHIFT (DImode,
6650 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6652 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6654 operands[4] = gen_reg_rtx(DImode);
6655 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6657 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6658 set_unique_reg_note (insn, REG_EQUAL, equal);
6660 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6661 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6663 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6664 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6669 (define_insn "divmoddisi3"
6670 [(set (match_operand:DI 0 "register_operand" "=d,d")
6675 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6677 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6681 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6686 [(set_attr "op_type" "RR,RX")
6687 (set_attr "type" "idiv")])
6690 ; udivsi3 and umodsi3 instruction pattern(s).
6693 (define_expand "udivmodsi4"
6694 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6695 (udiv:SI (match_operand:SI 1 "general_operand" "")
6696 (match_operand:SI 2 "nonimmediate_operand" "")))
6697 (set (match_operand:SI 3 "general_operand" "")
6698 (umod:SI (match_dup 1) (match_dup 2)))])
6699 (clobber (match_dup 4))]
6700 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6702 rtx insn, div_equal, mod_equal, equal;
6704 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6705 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6706 equal = gen_rtx_IOR (DImode,
6707 gen_rtx_ASHIFT (DImode,
6708 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6710 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6712 operands[4] = gen_reg_rtx(DImode);
6713 emit_clobber (operands[4]);
6714 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6715 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6717 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6718 set_unique_reg_note (insn, REG_EQUAL, equal);
6720 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6721 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6723 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6724 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6729 (define_insn "udivmoddisi3"
6730 [(set (match_operand:DI 0 "register_operand" "=d,d")
6735 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6737 (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
6741 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6742 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6746 [(set_attr "op_type" "RRE,RXY")
6747 (set_attr "type" "idiv")])
6749 (define_expand "udivsi3"
6750 [(set (match_operand:SI 0 "register_operand" "=d")
6751 (udiv:SI (match_operand:SI 1 "general_operand" "")
6752 (match_operand:SI 2 "general_operand" "")))
6753 (clobber (match_dup 3))]
6754 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6756 rtx insn, udiv_equal, umod_equal, equal;
6758 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6759 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6760 equal = gen_rtx_IOR (DImode,
6761 gen_rtx_ASHIFT (DImode,
6762 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6764 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6766 operands[3] = gen_reg_rtx (DImode);
6768 if (CONSTANT_P (operands[2]))
6770 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6772 rtx_code_label *label1 = gen_label_rtx ();
6774 operands[1] = make_safe_from (operands[1], operands[0]);
6775 emit_move_insn (operands[0], const0_rtx);
6776 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6778 emit_move_insn (operands[0], const1_rtx);
6779 emit_label (label1);
6783 operands[2] = force_reg (SImode, operands[2]);
6784 operands[2] = make_safe_from (operands[2], operands[0]);
6786 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6787 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6789 set_unique_reg_note (insn, REG_EQUAL, equal);
6791 insn = emit_move_insn (operands[0],
6792 gen_lowpart (SImode, operands[3]));
6793 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6798 rtx_code_label *label1 = gen_label_rtx ();
6799 rtx_code_label *label2 = gen_label_rtx ();
6800 rtx_code_label *label3 = gen_label_rtx ();
6802 operands[1] = force_reg (SImode, operands[1]);
6803 operands[1] = make_safe_from (operands[1], operands[0]);
6804 operands[2] = force_reg (SImode, operands[2]);
6805 operands[2] = make_safe_from (operands[2], operands[0]);
6807 emit_move_insn (operands[0], const0_rtx);
6808 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6810 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6812 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6814 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6815 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6817 set_unique_reg_note (insn, REG_EQUAL, equal);
6819 insn = emit_move_insn (operands[0],
6820 gen_lowpart (SImode, operands[3]));
6821 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6824 emit_label (label1);
6825 emit_move_insn (operands[0], operands[1]);
6827 emit_label (label2);
6828 emit_move_insn (operands[0], const1_rtx);
6829 emit_label (label3);
6831 emit_move_insn (operands[0], operands[0]);
6835 (define_expand "umodsi3"
6836 [(set (match_operand:SI 0 "register_operand" "=d")
6837 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6838 (match_operand:SI 2 "nonimmediate_operand" "")))
6839 (clobber (match_dup 3))]
6840 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6842 rtx insn, udiv_equal, umod_equal, equal;
6844 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6845 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6846 equal = gen_rtx_IOR (DImode,
6847 gen_rtx_ASHIFT (DImode,
6848 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6850 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6852 operands[3] = gen_reg_rtx (DImode);
6854 if (CONSTANT_P (operands[2]))
6856 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6858 rtx_code_label *label1 = gen_label_rtx ();
6860 operands[1] = make_safe_from (operands[1], operands[0]);
6861 emit_move_insn (operands[0], operands[1]);
6862 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6864 emit_insn (gen_abssi2 (operands[0], operands[2]));
6865 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6866 emit_label (label1);
6870 operands[2] = force_reg (SImode, operands[2]);
6871 operands[2] = make_safe_from (operands[2], operands[0]);
6873 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6874 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6876 set_unique_reg_note (insn, REG_EQUAL, equal);
6878 insn = emit_move_insn (operands[0],
6879 gen_highpart (SImode, operands[3]));
6880 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6885 rtx_code_label *label1 = gen_label_rtx ();
6886 rtx_code_label *label2 = gen_label_rtx ();
6887 rtx_code_label *label3 = gen_label_rtx ();
6889 operands[1] = force_reg (SImode, operands[1]);
6890 operands[1] = make_safe_from (operands[1], operands[0]);
6891 operands[2] = force_reg (SImode, operands[2]);
6892 operands[2] = make_safe_from (operands[2], operands[0]);
6894 emit_move_insn(operands[0], operands[1]);
6895 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6897 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6899 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6901 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6902 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6904 set_unique_reg_note (insn, REG_EQUAL, equal);
6906 insn = emit_move_insn (operands[0],
6907 gen_highpart (SImode, operands[3]));
6908 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6911 emit_label (label1);
6912 emit_move_insn (operands[0], const0_rtx);
6914 emit_label (label2);
6915 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6916 emit_label (label3);
6922 ; div(df|sf)3 instruction pattern(s).
6925 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6926 (define_insn "div<mode>3"
6927 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
6928 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
6929 (match_operand:FP 2 "general_operand" "f,f,R,v")))]
6936 [(set_attr "op_type" "RRF,RRE,RXE,VRR")
6937 (set_attr "type" "fdiv<mode>")
6938 (set_attr "cpu_facility" "*,*,*,vec")
6939 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
6943 ;;- And instructions.
6946 (define_expand "and<mode>3"
6947 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6948 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6949 (match_operand:INT 2 "general_operand" "")))
6950 (clobber (reg:CC CC_REGNUM))]
6952 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6955 ; anddi3 instruction pattern(s).
6958 (define_insn "*anddi3_cc"
6959 [(set (reg CC_REGNUM)
6961 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
6962 (match_operand:DI 2 "general_operand" " d,d,T,NxxDq"))
6964 (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
6965 (and:DI (match_dup 1) (match_dup 2)))]
6966 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6971 risbg\t%0,%1,%s2,128+%e2,0"
6972 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6973 (set_attr "cpu_facility" "*,z196,*,z10")
6974 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6976 (define_insn "*anddi3_cconly"
6977 [(set (reg CC_REGNUM)
6979 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
6980 (match_operand:DI 2 "general_operand" " d,d,T,NxxDq"))
6982 (clobber (match_scratch:DI 0 "=d,d,d, d"))]
6984 && s390_match_ccmode(insn, CCTmode)
6985 /* Do not steal TM patterns. */
6986 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6991 risbg\t%0,%1,%s2,128+%e2,0"
6992 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6993 (set_attr "cpu_facility" "*,z196,*,z10")
6994 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6996 (define_insn "*anddi3"
6997 [(set (match_operand:DI 0 "nonimmediate_operand"
6998 "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
7000 (match_operand:DI 1 "nonimmediate_operand"
7001 "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
7002 (match_operand:DI 2 "general_operand"
7003 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDq,NxQDF,Q")))
7004 (clobber (reg:CC CC_REGNUM))]
7005 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7018 risbg\t%0,%1,%s2,128+%e2,0
7021 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7022 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
7023 (set_attr "z10prop" "*,
7039 [(set (match_operand:DI 0 "s_operand" "")
7040 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7041 (clobber (reg:CC CC_REGNUM))]
7044 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7045 (clobber (reg:CC CC_REGNUM))])]
7046 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7048 ;; These two are what combine generates for (ashift (zero_extract)).
7049 (define_insn "*extzv_<mode>_srl"
7050 [(set (match_operand:GPR 0 "register_operand" "=d")
7051 (and:GPR (lshiftrt:GPR
7052 (match_operand:GPR 1 "register_operand" "d")
7053 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7054 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
7055 (clobber (reg:CC CC_REGNUM))]
7057 /* Note that even for the SImode pattern, the rotate is always DImode. */
7058 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
7059 INTVAL (operands[3]))"
7060 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
7061 [(set_attr "op_type" "RIE")
7062 (set_attr "z10prop" "z10_super_E1")])
7064 (define_insn "*extzv_<mode>_sll"
7065 [(set (match_operand:GPR 0 "register_operand" "=d")
7066 (and:GPR (ashift:GPR
7067 (match_operand:GPR 1 "register_operand" "d")
7068 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7069 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
7070 (clobber (reg:CC CC_REGNUM))]
7072 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
7073 INTVAL (operands[3]))"
7074 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
7075 [(set_attr "op_type" "RIE")
7076 (set_attr "z10prop" "z10_super_E1")])
7080 ; andsi3 instruction pattern(s).
7083 (define_insn "*andsi3_cc"
7084 [(set (reg CC_REGNUM)
7087 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7088 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7090 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
7091 (and:SI (match_dup 1) (match_dup 2)))]
7092 "s390_match_ccmode(insn, CCTmode)"
7099 risbg\t%0,%1,%t2,128+%f2,0"
7100 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7101 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7102 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7103 z10_super_E1,z10_super_E1,z10_super_E1")])
7105 (define_insn "*andsi3_cconly"
7106 [(set (reg CC_REGNUM)
7109 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7110 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7112 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
7113 "s390_match_ccmode(insn, CCTmode)
7114 /* Do not steal TM patterns. */
7115 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7122 risbg\t%0,%1,%t2,128+%f2,0"
7123 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7124 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7125 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7126 z10_super_E1,z10_super_E1,z10_super_E1")])
7128 (define_insn "*andsi3_zarch"
7129 [(set (match_operand:SI 0 "nonimmediate_operand"
7130 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
7131 (and:SI (match_operand:SI 1 "nonimmediate_operand"
7132 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
7133 (match_operand:SI 2 "general_operand"
7134 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
7135 (clobber (reg:CC CC_REGNUM))]
7136 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7147 risbg\t%0,%1,%t2,128+%f2,0
7150 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7151 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
7152 (set_attr "z10prop" "*,
7165 (define_insn "*andsi3_esa"
7166 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
7167 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
7168 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
7169 (clobber (reg:CC CC_REGNUM))]
7170 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7176 [(set_attr "op_type" "RR,RX,SI,SS")
7177 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7181 [(set (match_operand:SI 0 "s_operand" "")
7182 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7183 (clobber (reg:CC CC_REGNUM))]
7186 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7187 (clobber (reg:CC CC_REGNUM))])]
7188 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7191 ; andhi3 instruction pattern(s).
7194 (define_insn "*andhi3_zarch"
7195 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7196 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7197 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
7198 (clobber (reg:CC CC_REGNUM))]
7199 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7206 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7207 (set_attr "cpu_facility" "*,z196,*,*,*")
7208 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7211 (define_insn "*andhi3_esa"
7212 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7213 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7214 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7215 (clobber (reg:CC CC_REGNUM))]
7216 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7221 [(set_attr "op_type" "RR,SI,SS")
7222 (set_attr "z10prop" "z10_super_E1,*,*")
7226 [(set (match_operand:HI 0 "s_operand" "")
7227 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7228 (clobber (reg:CC CC_REGNUM))]
7231 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7232 (clobber (reg:CC CC_REGNUM))])]
7233 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7236 ; andqi3 instruction pattern(s).
7239 (define_insn "*andqi3_zarch"
7240 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7241 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7242 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7243 (clobber (reg:CC CC_REGNUM))]
7244 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7252 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7253 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7254 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7256 (define_insn "*andqi3_esa"
7257 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7258 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7259 (match_operand:QI 2 "general_operand" "d,n,Q")))
7260 (clobber (reg:CC CC_REGNUM))]
7261 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7266 [(set_attr "op_type" "RR,SI,SS")
7267 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7270 ; And with complement
7272 ; c = ~b & a = (b & a) ^ a
7274 (define_insn_and_split "*andc_split_<mode>"
7275 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
7276 (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
7277 (match_operand:GPR 2 "general_operand" "")))
7278 (clobber (reg:CC CC_REGNUM))]
7279 "! reload_completed && s390_logical_operator_ok_p (operands)"
7284 [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
7285 (clobber (reg:CC CC_REGNUM))])
7287 [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
7288 (clobber (reg:CC CC_REGNUM))])]
7290 if (reg_overlap_mentioned_p (operands[0], operands[2]))
7291 operands[3] = gen_reg_rtx (<MODE>mode);
7293 operands[3] = operands[0];
7297 ; Block and (NC) patterns.
7301 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7302 (and:BLK (match_dup 0)
7303 (match_operand:BLK 1 "memory_operand" "Q")))
7304 (use (match_operand 2 "const_int_operand" "n"))
7305 (clobber (reg:CC CC_REGNUM))]
7306 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7307 "nc\t%O0(%2,%R0),%S1"
7308 [(set_attr "op_type" "SS")
7309 (set_attr "z196prop" "z196_cracked")])
7312 [(set (match_operand 0 "memory_operand" "")
7314 (match_operand 1 "memory_operand" "")))
7315 (clobber (reg:CC CC_REGNUM))]
7317 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7318 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7320 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7322 (clobber (reg:CC CC_REGNUM))])]
7324 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7325 operands[0] = adjust_address (operands[0], BLKmode, 0);
7326 operands[1] = adjust_address (operands[1], BLKmode, 0);
7331 [(set (match_operand:BLK 0 "memory_operand" "")
7332 (and:BLK (match_dup 0)
7333 (match_operand:BLK 1 "memory_operand" "")))
7334 (use (match_operand 2 "const_int_operand" ""))
7335 (clobber (reg:CC CC_REGNUM))])
7337 [(set (match_operand:BLK 3 "memory_operand" "")
7338 (and:BLK (match_dup 3)
7339 (match_operand:BLK 4 "memory_operand" "")))
7340 (use (match_operand 5 "const_int_operand" ""))
7341 (clobber (reg:CC CC_REGNUM))])]
7342 "s390_offset_p (operands[0], operands[3], operands[2])
7343 && s390_offset_p (operands[1], operands[4], operands[2])
7344 && !s390_overlap_p (operands[0], operands[1],
7345 INTVAL (operands[2]) + INTVAL (operands[5]))
7346 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7348 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7350 (clobber (reg:CC CC_REGNUM))])]
7351 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7352 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7353 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7357 ;;- Bit set (inclusive or) instructions.
7360 (define_expand "ior<mode>3"
7361 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7362 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7363 (match_operand:INT 2 "general_operand" "")))
7364 (clobber (reg:CC CC_REGNUM))]
7366 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7369 ; iordi3 instruction pattern(s).
7372 (define_insn "*iordi3_cc"
7373 [(set (reg CC_REGNUM)
7374 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7375 (match_operand:DI 2 "general_operand" " d,d,T"))
7377 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7378 (ior:DI (match_dup 1) (match_dup 2)))]
7379 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7384 [(set_attr "op_type" "RRE,RRF,RXY")
7385 (set_attr "cpu_facility" "*,z196,*")
7386 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7388 (define_insn "*iordi3_cconly"
7389 [(set (reg CC_REGNUM)
7390 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7391 (match_operand:DI 2 "general_operand" " d,d,T"))
7393 (clobber (match_scratch:DI 0 "=d,d,d"))]
7394 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7399 [(set_attr "op_type" "RRE,RRF,RXY")
7400 (set_attr "cpu_facility" "*,z196,*")
7401 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7403 (define_insn "*iordi3"
7404 [(set (match_operand:DI 0 "nonimmediate_operand"
7405 "=d, d, d, d, d, d,d,d,d, AQ,Q")
7406 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7407 " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
7408 (match_operand:DI 2 "general_operand"
7409 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7410 (clobber (reg:CC CC_REGNUM))]
7411 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7424 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7425 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7426 (set_attr "z10prop" "z10_super_E1,
7439 [(set (match_operand:DI 0 "s_operand" "")
7440 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7441 (clobber (reg:CC CC_REGNUM))]
7444 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7445 (clobber (reg:CC CC_REGNUM))])]
7446 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7449 ; iorsi3 instruction pattern(s).
7452 (define_insn "*iorsi3_cc"
7453 [(set (reg CC_REGNUM)
7454 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7455 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7457 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7458 (ior:SI (match_dup 1) (match_dup 2)))]
7459 "s390_match_ccmode(insn, CCTmode)"
7466 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7467 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7468 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7470 (define_insn "*iorsi3_cconly"
7471 [(set (reg CC_REGNUM)
7472 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7473 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7475 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7476 "s390_match_ccmode(insn, CCTmode)"
7483 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7484 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7485 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7487 (define_insn "*iorsi3_zarch"
7488 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
7489 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
7490 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7491 (clobber (reg:CC CC_REGNUM))]
7492 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7503 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7504 (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
7505 (set_attr "z10prop" "z10_super_E1,
7515 (define_insn "*iorsi3_esa"
7516 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7517 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7518 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7519 (clobber (reg:CC CC_REGNUM))]
7520 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7526 [(set_attr "op_type" "RR,RX,SI,SS")
7527 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7530 [(set (match_operand:SI 0 "s_operand" "")
7531 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7532 (clobber (reg:CC CC_REGNUM))]
7535 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7536 (clobber (reg:CC CC_REGNUM))])]
7537 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7540 ; iorhi3 instruction pattern(s).
7543 (define_insn "*iorhi3_zarch"
7544 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7545 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7546 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7547 (clobber (reg:CC CC_REGNUM))]
7548 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7555 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7556 (set_attr "cpu_facility" "*,z196,*,*,*")
7557 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7559 (define_insn "*iorhi3_esa"
7560 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7561 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7562 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7563 (clobber (reg:CC CC_REGNUM))]
7564 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7569 [(set_attr "op_type" "RR,SI,SS")
7570 (set_attr "z10prop" "z10_super_E1,*,*")])
7573 [(set (match_operand:HI 0 "s_operand" "")
7574 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7575 (clobber (reg:CC CC_REGNUM))]
7578 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7579 (clobber (reg:CC CC_REGNUM))])]
7580 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7583 ; iorqi3 instruction pattern(s).
7586 (define_insn "*iorqi3_zarch"
7587 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7588 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7589 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7590 (clobber (reg:CC CC_REGNUM))]
7591 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7599 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7600 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7601 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7602 z10_super,z10_super,*")])
7604 (define_insn "*iorqi3_esa"
7605 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7606 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7607 (match_operand:QI 2 "general_operand" "d,n,Q")))
7608 (clobber (reg:CC CC_REGNUM))]
7609 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7614 [(set_attr "op_type" "RR,SI,SS")
7615 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7618 ; Block inclusive or (OC) patterns.
7622 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7623 (ior:BLK (match_dup 0)
7624 (match_operand:BLK 1 "memory_operand" "Q")))
7625 (use (match_operand 2 "const_int_operand" "n"))
7626 (clobber (reg:CC CC_REGNUM))]
7627 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7628 "oc\t%O0(%2,%R0),%S1"
7629 [(set_attr "op_type" "SS")
7630 (set_attr "z196prop" "z196_cracked")])
7633 [(set (match_operand 0 "memory_operand" "")
7635 (match_operand 1 "memory_operand" "")))
7636 (clobber (reg:CC CC_REGNUM))]
7638 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7639 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7641 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7643 (clobber (reg:CC CC_REGNUM))])]
7645 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7646 operands[0] = adjust_address (operands[0], BLKmode, 0);
7647 operands[1] = adjust_address (operands[1], BLKmode, 0);
7652 [(set (match_operand:BLK 0 "memory_operand" "")
7653 (ior:BLK (match_dup 0)
7654 (match_operand:BLK 1 "memory_operand" "")))
7655 (use (match_operand 2 "const_int_operand" ""))
7656 (clobber (reg:CC CC_REGNUM))])
7658 [(set (match_operand:BLK 3 "memory_operand" "")
7659 (ior:BLK (match_dup 3)
7660 (match_operand:BLK 4 "memory_operand" "")))
7661 (use (match_operand 5 "const_int_operand" ""))
7662 (clobber (reg:CC CC_REGNUM))])]
7663 "s390_offset_p (operands[0], operands[3], operands[2])
7664 && s390_offset_p (operands[1], operands[4], operands[2])
7665 && !s390_overlap_p (operands[0], operands[1],
7666 INTVAL (operands[2]) + INTVAL (operands[5]))
7667 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7669 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7671 (clobber (reg:CC CC_REGNUM))])]
7672 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7673 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7674 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7678 ;;- Xor instructions.
7681 (define_expand "xor<mode>3"
7682 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7683 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7684 (match_operand:INT 2 "general_operand" "")))
7685 (clobber (reg:CC CC_REGNUM))]
7687 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7689 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7690 ; simplifications. So its better to have something matching.
7692 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7693 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7696 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7697 (clobber (reg:CC CC_REGNUM))])]
7699 operands[2] = constm1_rtx;
7700 if (!s390_logical_operator_ok_p (operands))
7705 ; xordi3 instruction pattern(s).
7708 (define_insn "*xordi3_cc"
7709 [(set (reg CC_REGNUM)
7710 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7711 (match_operand:DI 2 "general_operand" " d,d,T"))
7713 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7714 (xor:DI (match_dup 1) (match_dup 2)))]
7715 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7720 [(set_attr "op_type" "RRE,RRF,RXY")
7721 (set_attr "cpu_facility" "*,z196,*")
7722 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7724 (define_insn "*xordi3_cconly"
7725 [(set (reg CC_REGNUM)
7726 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7727 (match_operand:DI 2 "general_operand" " d,d,T"))
7729 (clobber (match_scratch:DI 0 "=d,d,d"))]
7730 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7735 [(set_attr "op_type" "RRE,RRF,RXY")
7736 (set_attr "cpu_facility" "*,z196,*")
7737 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7739 (define_insn "*xordi3"
7740 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
7741 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
7742 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7743 (clobber (reg:CC CC_REGNUM))]
7744 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7753 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7754 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7755 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7756 *,z10_super_E1,*,*")])
7759 [(set (match_operand:DI 0 "s_operand" "")
7760 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7761 (clobber (reg:CC CC_REGNUM))]
7764 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7765 (clobber (reg:CC CC_REGNUM))])]
7766 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7769 ; xorsi3 instruction pattern(s).
7772 (define_insn "*xorsi3_cc"
7773 [(set (reg CC_REGNUM)
7774 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7775 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7777 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7778 (xor:SI (match_dup 1) (match_dup 2)))]
7779 "s390_match_ccmode(insn, CCTmode)"
7786 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7787 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7788 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7789 z10_super_E1,z10_super_E1")])
7791 (define_insn "*xorsi3_cconly"
7792 [(set (reg CC_REGNUM)
7793 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7794 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7796 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7797 "s390_match_ccmode(insn, CCTmode)"
7804 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7805 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7806 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7807 z10_super_E1,z10_super_E1")])
7809 (define_insn "*xorsi3"
7810 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7811 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7812 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7813 (clobber (reg:CC CC_REGNUM))]
7814 "s390_logical_operator_ok_p (operands)"
7823 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7824 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
7825 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7826 z10_super_E1,z10_super_E1,*,*")])
7829 [(set (match_operand:SI 0 "s_operand" "")
7830 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7831 (clobber (reg:CC CC_REGNUM))]
7834 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7835 (clobber (reg:CC CC_REGNUM))])]
7836 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7839 ; xorhi3 instruction pattern(s).
7842 (define_insn "*xorhi3"
7843 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7844 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7845 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7846 (clobber (reg:CC CC_REGNUM))]
7847 "s390_logical_operator_ok_p (operands)"
7854 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7855 (set_attr "cpu_facility" "*,*,z196,*,*")
7856 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7859 [(set (match_operand:HI 0 "s_operand" "")
7860 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7861 (clobber (reg:CC CC_REGNUM))]
7864 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7865 (clobber (reg:CC CC_REGNUM))])]
7866 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7869 ; xorqi3 instruction pattern(s).
7872 (define_insn "*xorqi3"
7873 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7874 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7875 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7876 (clobber (reg:CC CC_REGNUM))]
7877 "s390_logical_operator_ok_p (operands)"
7885 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7886 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
7887 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7891 ; Block exclusive or (XC) patterns.
7895 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7896 (xor:BLK (match_dup 0)
7897 (match_operand:BLK 1 "memory_operand" "Q")))
7898 (use (match_operand 2 "const_int_operand" "n"))
7899 (clobber (reg:CC CC_REGNUM))]
7900 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7901 "xc\t%O0(%2,%R0),%S1"
7902 [(set_attr "op_type" "SS")])
7905 [(set (match_operand 0 "memory_operand" "")
7907 (match_operand 1 "memory_operand" "")))
7908 (clobber (reg:CC CC_REGNUM))]
7910 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7911 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7913 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7915 (clobber (reg:CC CC_REGNUM))])]
7917 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7918 operands[0] = adjust_address (operands[0], BLKmode, 0);
7919 operands[1] = adjust_address (operands[1], BLKmode, 0);
7924 [(set (match_operand:BLK 0 "memory_operand" "")
7925 (xor:BLK (match_dup 0)
7926 (match_operand:BLK 1 "memory_operand" "")))
7927 (use (match_operand 2 "const_int_operand" ""))
7928 (clobber (reg:CC CC_REGNUM))])
7930 [(set (match_operand:BLK 3 "memory_operand" "")
7931 (xor:BLK (match_dup 3)
7932 (match_operand:BLK 4 "memory_operand" "")))
7933 (use (match_operand 5 "const_int_operand" ""))
7934 (clobber (reg:CC CC_REGNUM))])]
7935 "s390_offset_p (operands[0], operands[3], operands[2])
7936 && s390_offset_p (operands[1], operands[4], operands[2])
7937 && !s390_overlap_p (operands[0], operands[1],
7938 INTVAL (operands[2]) + INTVAL (operands[5]))
7939 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7941 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7943 (clobber (reg:CC CC_REGNUM))])]
7944 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7945 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7946 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7949 ; Block xor (XC) patterns with src == dest.
7952 (define_insn "*xc_zero"
7953 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7955 (use (match_operand 1 "const_int_operand" "n"))
7956 (clobber (reg:CC CC_REGNUM))]
7957 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7958 "xc\t%O0(%1,%R0),%S0"
7959 [(set_attr "op_type" "SS")
7960 (set_attr "z196prop" "z196_cracked")])
7964 [(set (match_operand:BLK 0 "memory_operand" "")
7966 (use (match_operand 1 "const_int_operand" ""))
7967 (clobber (reg:CC CC_REGNUM))])
7969 [(set (match_operand:BLK 2 "memory_operand" "")
7971 (use (match_operand 3 "const_int_operand" ""))
7972 (clobber (reg:CC CC_REGNUM))])]
7973 "s390_offset_p (operands[0], operands[2], operands[1])
7974 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7976 [(set (match_dup 4) (const_int 0))
7978 (clobber (reg:CC CC_REGNUM))])]
7979 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7980 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7984 ;;- Negate instructions.
7988 ; neg(di|si)2 instruction pattern(s).
7991 (define_expand "neg<mode>2"
7993 [(set (match_operand:DSI 0 "register_operand" "=d")
7994 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7995 (clobber (reg:CC CC_REGNUM))])]
7999 (define_insn "*negdi2_sign_cc"
8000 [(set (reg CC_REGNUM)
8001 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
8002 (match_operand:SI 1 "register_operand" "d") 0)
8003 (const_int 32)) (const_int 32)))
8005 (set (match_operand:DI 0 "register_operand" "=d")
8006 (neg:DI (sign_extend:DI (match_dup 1))))]
8007 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8009 [(set_attr "op_type" "RRE")
8010 (set_attr "z10prop" "z10_c")])
8012 (define_insn "*negdi2_sign"
8013 [(set (match_operand:DI 0 "register_operand" "=d")
8014 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8015 (clobber (reg:CC CC_REGNUM))]
8018 [(set_attr "op_type" "RRE")
8019 (set_attr "z10prop" "z10_c")])
8022 (define_insn "*neg<mode>2_cc"
8023 [(set (reg CC_REGNUM)
8024 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8026 (set (match_operand:GPR 0 "register_operand" "=d")
8027 (neg:GPR (match_dup 1)))]
8028 "s390_match_ccmode (insn, CCAmode)"
8030 [(set_attr "op_type" "RR<E>")
8031 (set_attr "z10prop" "z10_super_c_E1")])
8034 (define_insn "*neg<mode>2_cconly"
8035 [(set (reg CC_REGNUM)
8036 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8038 (clobber (match_scratch:GPR 0 "=d"))]
8039 "s390_match_ccmode (insn, CCAmode)"
8041 [(set_attr "op_type" "RR<E>")
8042 (set_attr "z10prop" "z10_super_c_E1")])
8045 (define_insn "*neg<mode>2"
8046 [(set (match_operand:GPR 0 "register_operand" "=d")
8047 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
8048 (clobber (reg:CC CC_REGNUM))]
8051 [(set_attr "op_type" "RR<E>")
8052 (set_attr "z10prop" "z10_super_c_E1")])
8054 (define_insn "*negdi2_31"
8055 [(set (match_operand:DI 0 "register_operand" "=d")
8056 (neg:DI (match_operand:DI 1 "register_operand" "d")))
8057 (clobber (reg:CC CC_REGNUM))]
8061 ; Split a DImode NEG on 31bit into 2 SImode NEGs
8063 ; Doing the twos complement separately on the SImode parts does an
8064 ; unwanted +1 on the high part which needs to be subtracted afterwards
8065 ; ... unless the +1 on the low part created an overflow.
8068 [(set (match_operand:DI 0 "register_operand" "")
8069 (neg:DI (match_operand:DI 1 "register_operand" "")))
8070 (clobber (reg:CC CC_REGNUM))]
8072 && (REGNO (operands[0]) == REGNO (operands[1])
8073 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
8074 && reload_completed"
8076 [(set (match_dup 2) (neg:SI (match_dup 3)))
8077 (clobber (reg:CC CC_REGNUM))])
8079 [(set (reg:CCAP CC_REGNUM)
8080 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
8081 (set (match_dup 4) (neg:SI (match_dup 5)))])
8083 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8085 (label_ref (match_dup 6))))
8087 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8088 (clobber (reg:CC CC_REGNUM))])
8090 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8091 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8092 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8093 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8094 operands[6] = gen_label_rtx ();")
8096 ; Like above but first make a copy of the low part of the src operand
8097 ; since it might overlap with the high part of the destination.
8100 [(set (match_operand:DI 0 "register_operand" "")
8101 (neg:DI (match_operand:DI 1 "register_operand" "")))
8102 (clobber (reg:CC CC_REGNUM))]
8104 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
8105 && reload_completed"
8106 [; Make a backup of op5 first
8107 (set (match_dup 4) (match_dup 5))
8108 ; Setting op2 here might clobber op5
8110 [(set (match_dup 2) (neg:SI (match_dup 3)))
8111 (clobber (reg:CC CC_REGNUM))])
8113 [(set (reg:CCAP CC_REGNUM)
8114 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
8115 (set (match_dup 4) (neg:SI (match_dup 4)))])
8117 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8119 (label_ref (match_dup 6))))
8121 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8122 (clobber (reg:CC CC_REGNUM))])
8124 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8125 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8126 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8127 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8128 operands[6] = gen_label_rtx ();")
8131 ; neg(df|sf)2 instruction pattern(s).
8134 (define_expand "neg<mode>2"
8136 [(set (match_operand:BFP 0 "register_operand" "=f")
8137 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
8138 (clobber (reg:CC CC_REGNUM))])]
8142 ; lcxbr, lcdbr, lcebr
8143 (define_insn "*neg<mode>2_cc"
8144 [(set (reg CC_REGNUM)
8145 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8146 (match_operand:BFP 2 "const0_operand" "")))
8147 (set (match_operand:BFP 0 "register_operand" "=f")
8148 (neg:BFP (match_dup 1)))]
8149 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8151 [(set_attr "op_type" "RRE")
8152 (set_attr "type" "fsimp<mode>")])
8154 ; lcxbr, lcdbr, lcebr
8155 (define_insn "*neg<mode>2_cconly"
8156 [(set (reg CC_REGNUM)
8157 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8158 (match_operand:BFP 2 "const0_operand" "")))
8159 (clobber (match_scratch:BFP 0 "=f"))]
8160 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8162 [(set_attr "op_type" "RRE")
8163 (set_attr "type" "fsimp<mode>")])
8166 (define_insn "*neg<mode>2_nocc"
8167 [(set (match_operand:FP 0 "register_operand" "=f")
8168 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8171 [(set_attr "op_type" "RRE")
8172 (set_attr "type" "fsimp<mode>")])
8174 ; lcxbr, lcdbr, lcebr
8175 ; FIXME: wflcdb does not clobber cc
8176 (define_insn "*neg<mode>2"
8177 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8178 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8179 (clobber (reg:CC CC_REGNUM))]
8184 [(set_attr "op_type" "RRE,VRR")
8185 (set_attr "cpu_facility" "*,vec")
8186 (set_attr "type" "fsimp<mode>,*")
8187 (set_attr "enabled" "*,<DFDI>")])
8191 ;;- Absolute value instructions.
8195 ; abs(di|si)2 instruction pattern(s).
8198 (define_insn "*absdi2_sign_cc"
8199 [(set (reg CC_REGNUM)
8200 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8201 (match_operand:SI 1 "register_operand" "d") 0)
8202 (const_int 32)) (const_int 32)))
8204 (set (match_operand:DI 0 "register_operand" "=d")
8205 (abs:DI (sign_extend:DI (match_dup 1))))]
8206 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8208 [(set_attr "op_type" "RRE")
8209 (set_attr "z10prop" "z10_c")])
8211 (define_insn "*absdi2_sign"
8212 [(set (match_operand:DI 0 "register_operand" "=d")
8213 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8214 (clobber (reg:CC CC_REGNUM))]
8217 [(set_attr "op_type" "RRE")
8218 (set_attr "z10prop" "z10_c")])
8221 (define_insn "*abs<mode>2_cc"
8222 [(set (reg CC_REGNUM)
8223 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8225 (set (match_operand:GPR 0 "register_operand" "=d")
8226 (abs:GPR (match_dup 1)))]
8227 "s390_match_ccmode (insn, CCAmode)"
8229 [(set_attr "op_type" "RR<E>")
8230 (set_attr "z10prop" "z10_c")])
8233 (define_insn "*abs<mode>2_cconly"
8234 [(set (reg CC_REGNUM)
8235 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8237 (clobber (match_scratch:GPR 0 "=d"))]
8238 "s390_match_ccmode (insn, CCAmode)"
8240 [(set_attr "op_type" "RR<E>")
8241 (set_attr "z10prop" "z10_c")])
8244 (define_insn "abs<mode>2"
8245 [(set (match_operand:GPR 0 "register_operand" "=d")
8246 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8247 (clobber (reg:CC CC_REGNUM))]
8250 [(set_attr "op_type" "RR<E>")
8251 (set_attr "z10prop" "z10_c")])
8254 ; abs(df|sf)2 instruction pattern(s).
8257 (define_expand "abs<mode>2"
8259 [(set (match_operand:BFP 0 "register_operand" "=f")
8260 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8261 (clobber (reg:CC CC_REGNUM))])]
8265 ; lpxbr, lpdbr, lpebr
8266 (define_insn "*abs<mode>2_cc"
8267 [(set (reg CC_REGNUM)
8268 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8269 (match_operand:BFP 2 "const0_operand" "")))
8270 (set (match_operand:BFP 0 "register_operand" "=f")
8271 (abs:BFP (match_dup 1)))]
8272 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8274 [(set_attr "op_type" "RRE")
8275 (set_attr "type" "fsimp<mode>")])
8277 ; lpxbr, lpdbr, lpebr
8278 (define_insn "*abs<mode>2_cconly"
8279 [(set (reg CC_REGNUM)
8280 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8281 (match_operand:BFP 2 "const0_operand" "")))
8282 (clobber (match_scratch:BFP 0 "=f"))]
8283 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8285 [(set_attr "op_type" "RRE")
8286 (set_attr "type" "fsimp<mode>")])
8289 (define_insn "*abs<mode>2_nocc"
8290 [(set (match_operand:FP 0 "register_operand" "=f")
8291 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8294 [(set_attr "op_type" "RRE")
8295 (set_attr "type" "fsimp<mode>")])
8297 ; lpxbr, lpdbr, lpebr
8298 ; FIXME: wflpdb does not clobber cc
8299 (define_insn "*abs<mode>2"
8300 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8301 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8302 (clobber (reg:CC CC_REGNUM))]
8307 [(set_attr "op_type" "RRE,VRR")
8308 (set_attr "cpu_facility" "*,vec")
8309 (set_attr "type" "fsimp<mode>,*")
8310 (set_attr "enabled" "*,<DFDI>")])
8314 ;;- Negated absolute value instructions
8321 (define_insn "*negabsdi2_sign_cc"
8322 [(set (reg CC_REGNUM)
8323 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8324 (match_operand:SI 1 "register_operand" "d") 0)
8325 (const_int 32)) (const_int 32))))
8327 (set (match_operand:DI 0 "register_operand" "=d")
8328 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8329 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8331 [(set_attr "op_type" "RRE")
8332 (set_attr "z10prop" "z10_c")])
8334 (define_insn "*negabsdi2_sign"
8335 [(set (match_operand:DI 0 "register_operand" "=d")
8336 (neg:DI (abs:DI (sign_extend:DI
8337 (match_operand:SI 1 "register_operand" "d")))))
8338 (clobber (reg:CC CC_REGNUM))]
8341 [(set_attr "op_type" "RRE")
8342 (set_attr "z10prop" "z10_c")])
8345 (define_insn "*negabs<mode>2_cc"
8346 [(set (reg CC_REGNUM)
8347 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8349 (set (match_operand:GPR 0 "register_operand" "=d")
8350 (neg:GPR (abs:GPR (match_dup 1))))]
8351 "s390_match_ccmode (insn, CCAmode)"
8353 [(set_attr "op_type" "RR<E>")
8354 (set_attr "z10prop" "z10_c")])
8357 (define_insn "*negabs<mode>2_cconly"
8358 [(set (reg CC_REGNUM)
8359 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8361 (clobber (match_scratch:GPR 0 "=d"))]
8362 "s390_match_ccmode (insn, CCAmode)"
8364 [(set_attr "op_type" "RR<E>")
8365 (set_attr "z10prop" "z10_c")])
8368 (define_insn "*negabs<mode>2"
8369 [(set (match_operand:GPR 0 "register_operand" "=d")
8370 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8371 (clobber (reg:CC CC_REGNUM))]
8374 [(set_attr "op_type" "RR<E>")
8375 (set_attr "z10prop" "z10_c")])
8381 ; lnxbr, lndbr, lnebr
8382 (define_insn "*negabs<mode>2_cc"
8383 [(set (reg CC_REGNUM)
8384 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8385 (match_operand:BFP 2 "const0_operand" "")))
8386 (set (match_operand:BFP 0 "register_operand" "=f")
8387 (neg:BFP (abs:BFP (match_dup 1))))]
8388 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8390 [(set_attr "op_type" "RRE")
8391 (set_attr "type" "fsimp<mode>")])
8393 ; lnxbr, lndbr, lnebr
8394 (define_insn "*negabs<mode>2_cconly"
8395 [(set (reg CC_REGNUM)
8396 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8397 (match_operand:BFP 2 "const0_operand" "")))
8398 (clobber (match_scratch:BFP 0 "=f"))]
8399 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8401 [(set_attr "op_type" "RRE")
8402 (set_attr "type" "fsimp<mode>")])
8405 (define_insn "*negabs<mode>2_nocc"
8406 [(set (match_operand:FP 0 "register_operand" "=f")
8407 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8410 [(set_attr "op_type" "RRE")
8411 (set_attr "type" "fsimp<mode>")])
8413 ; lnxbr, lndbr, lnebr
8414 ; FIXME: wflndb does not clobber cc
8415 (define_insn "*negabs<mode>2"
8416 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8417 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
8418 (clobber (reg:CC CC_REGNUM))]
8423 [(set_attr "op_type" "RRE,VRR")
8424 (set_attr "cpu_facility" "*,vec")
8425 (set_attr "type" "fsimp<mode>,*")
8426 (set_attr "enabled" "*,<DFDI>")])
8429 ;;- Square root instructions.
8433 ; sqrt(df|sf)2 instruction pattern(s).
8436 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8437 (define_insn "sqrt<mode>2"
8438 [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
8439 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
8445 [(set_attr "op_type" "RRE,RXE,VRR")
8446 (set_attr "type" "fsqrt<mode>")
8447 (set_attr "cpu_facility" "*,*,vec")
8448 (set_attr "enabled" "*,<DSF>,<DFDI>")])
8452 ;;- One complement instructions.
8456 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8459 (define_expand "one_cmpl<mode>2"
8461 [(set (match_operand:INT 0 "register_operand" "")
8462 (xor:INT (match_operand:INT 1 "register_operand" "")
8464 (clobber (reg:CC CC_REGNUM))])]
8470 ;; Find leftmost bit instructions.
8473 (define_expand "clzdi2"
8474 [(set (match_operand:DI 0 "register_operand" "=d")
8475 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8476 "TARGET_EXTIMM && TARGET_ZARCH"
8478 rtx insn, clz_equal;
8479 rtx wide_reg = gen_reg_rtx (TImode);
8480 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
8482 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8484 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8486 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8487 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8492 (define_insn "clztidi2"
8493 [(set (match_operand:TI 0 "register_operand" "=d")
8497 (xor:DI (match_operand:DI 1 "register_operand" "d")
8498 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8499 (subreg:SI (clz:DI (match_dup 1)) 4))))
8502 (zero_extend:TI (clz:DI (match_dup 1)))))
8503 (clobber (reg:CC CC_REGNUM))]
8504 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
8505 == (unsigned HOST_WIDE_INT) 1 << 63
8506 && TARGET_EXTIMM && TARGET_ZARCH"
8508 [(set_attr "op_type" "RRE")])
8512 ;;- Rotate instructions.
8516 ; rotl(di|si)3 instruction pattern(s).
8519 (define_expand "rotl<mode>3"
8520 [(set (match_operand:GPR 0 "register_operand" "")
8521 (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8522 (match_operand:SI 2 "nonmemory_operand" "")))]
8527 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8528 [(set (match_operand:GPR 0 "register_operand" "=d")
8529 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8530 (match_operand:SI 2 "nonmemory_operand" "an")))]
8532 "rll<g>\t%0,%1,<addr_style_op_ops>"
8533 [(set_attr "op_type" "RSE")
8534 (set_attr "atype" "reg")
8535 (set_attr "z10prop" "z10_super_E1")])
8539 ;;- Shift instructions.
8543 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8544 ; Left shifts and logical right shifts
8546 (define_expand "<shift><mode>3"
8547 [(set (match_operand:DSI 0 "register_operand" "")
8548 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8549 (match_operand:SI 2 "nonmemory_operand" "")))]
8553 ; ESA 64 bit register pair shift with reg or imm shift count
8555 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8556 [(set (match_operand:DI 0 "register_operand" "=d")
8557 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8558 (match_operand:SI 2 "nonmemory_operand" "an")))]
8560 "s<lr>dl\t%0,<addr_style_op_ops>"
8561 [(set_attr "op_type" "RS")
8562 (set_attr "atype" "reg")
8563 (set_attr "z196prop" "z196_cracked")])
8566 ; 64 bit register shift with reg or imm shift count
8567 ; sll, srl, sllg, srlg, sllk, srlk
8568 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8569 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8570 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8571 (match_operand:SI 2 "nonmemory_operand" "an,an")))]
8574 s<lr>l<g>\t%0,<1><addr_style_op_ops>
8575 s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8576 [(set_attr "op_type" "RS<E>,RSY")
8577 (set_attr "atype" "reg,reg")
8578 (set_attr "cpu_facility" "*,z196")
8579 (set_attr "z10prop" "z10_super_E1,*")])
8582 ; ashr(di|si)3 instruction pattern(s).
8583 ; Arithmetic right shifts
8585 (define_expand "ashr<mode>3"
8587 [(set (match_operand:DSI 0 "register_operand" "")
8588 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8589 (match_operand:SI 2 "nonmemory_operand" "")))
8590 (clobber (reg:CC CC_REGNUM))])]
8594 ; FIXME: The number of alternatives is doubled here to match the fix
8595 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8596 ; The right fix should be to support match_scratch in the output
8597 ; pattern of a define_subst.
8598 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8599 [(set (match_operand:DI 0 "register_operand" "=d, d")
8600 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0")
8601 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8602 (clobber (reg:CC CC_REGNUM))]
8605 srda\t%0,<addr_style_op_cc_ops>
8606 srda\t%0,<addr_style_op_cc_ops>"
8607 [(set_attr "op_type" "RS")
8608 (set_attr "atype" "reg")])
8612 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8613 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8614 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8615 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8616 (clobber (reg:CC CC_REGNUM))]
8619 sra<g>\t%0,<1><addr_style_op_cc_ops>
8620 sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8621 [(set_attr "op_type" "RS<E>,RSY")
8622 (set_attr "atype" "reg")
8623 (set_attr "cpu_facility" "*,z196")
8624 (set_attr "z10prop" "z10_super_E1,*")])
8628 ;; Branch instruction patterns.
8631 (define_expand "cbranch<mode>4"
8633 (if_then_else (match_operator 0 "comparison_operator"
8634 [(match_operand:GPR 1 "register_operand" "")
8635 (match_operand:GPR 2 "general_operand" "")])
8636 (label_ref (match_operand 3 "" ""))
8639 "s390_emit_jump (operands[3],
8640 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8643 (define_expand "cbranch<mode>4"
8645 (if_then_else (match_operator 0 "comparison_operator"
8646 [(match_operand:FP 1 "register_operand" "")
8647 (match_operand:FP 2 "general_operand" "")])
8648 (label_ref (match_operand 3 "" ""))
8651 "s390_emit_jump (operands[3],
8652 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8655 (define_expand "cbranchcc4"
8657 (if_then_else (match_operator 0 "s390_comparison"
8658 [(match_operand 1 "cc_reg_operand" "")
8659 (match_operand 2 "const_int_operand" "")])
8660 (label_ref (match_operand 3 "" ""))
8667 ;;- Conditional jump instructions.
8670 (define_insn "*cjump_64"
8673 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8674 (match_operand 2 "const_int_operand" "")])
8675 (label_ref (match_operand 0 "" ""))
8679 if (get_attr_length (insn) == 4)
8682 return "jg%C1\t%l0";
8684 [(set_attr "op_type" "RI")
8685 (set_attr "type" "branch")
8686 (set (attr "length")
8687 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8688 (const_int 4) (const_int 6)))])
8690 (define_insn "*cjump_31"
8693 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8694 (match_operand 2 "const_int_operand" "")])
8695 (label_ref (match_operand 0 "" ""))
8699 gcc_assert (get_attr_length (insn) == 4);
8702 [(set_attr "op_type" "RI")
8703 (set_attr "type" "branch")
8704 (set (attr "length")
8705 (if_then_else (not (match_test "flag_pic"))
8706 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8707 (const_int 4) (const_int 6))
8708 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8709 (const_int 4) (const_int 8))))])
8711 (define_insn "*cjump_long"
8714 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8715 (match_operand 0 "address_operand" "ZQZR")
8719 if (get_attr_op_type (insn) == OP_TYPE_RR)
8724 [(set (attr "op_type")
8725 (if_then_else (match_operand 0 "register_operand" "")
8726 (const_string "RR") (const_string "RX")))
8727 (set_attr "type" "branch")
8728 (set_attr "atype" "agen")])
8730 ;; A conditional return instruction.
8731 (define_insn "*c<code>"
8734 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8737 "s390_can_use_<code>_insn ()"
8739 [(set_attr "op_type" "RR")
8740 (set_attr "type" "jsr")
8741 (set_attr "atype" "agen")])
8744 ;;- Negated conditional jump instructions.
8747 (define_insn "*icjump_64"
8750 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8752 (label_ref (match_operand 0 "" ""))))]
8755 if (get_attr_length (insn) == 4)
8758 return "jg%D1\t%l0";
8760 [(set_attr "op_type" "RI")
8761 (set_attr "type" "branch")
8762 (set (attr "length")
8763 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8764 (const_int 4) (const_int 6)))])
8766 (define_insn "*icjump_31"
8769 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8771 (label_ref (match_operand 0 "" ""))))]
8774 gcc_assert (get_attr_length (insn) == 4);
8777 [(set_attr "op_type" "RI")
8778 (set_attr "type" "branch")
8779 (set (attr "length")
8780 (if_then_else (not (match_test "flag_pic"))
8781 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8782 (const_int 4) (const_int 6))
8783 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8784 (const_int 4) (const_int 8))))])
8786 (define_insn "*icjump_long"
8789 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8791 (match_operand 0 "address_operand" "ZQZR")))]
8794 if (get_attr_op_type (insn) == OP_TYPE_RR)
8799 [(set (attr "op_type")
8800 (if_then_else (match_operand 0 "register_operand" "")
8801 (const_string "RR") (const_string "RX")))
8802 (set_attr "type" "branch")
8803 (set_attr "atype" "agen")])
8806 ;;- Trap instructions.
8810 [(trap_if (const_int 1) (const_int 0))]
8813 [(set_attr "op_type" "RI")
8814 (set_attr "type" "branch")])
8816 (define_expand "ctrap<mode>4"
8817 [(trap_if (match_operator 0 "comparison_operator"
8818 [(match_operand:GPR 1 "register_operand" "")
8819 (match_operand:GPR 2 "general_operand" "")])
8820 (match_operand 3 "const0_operand" ""))]
8823 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8824 operands[1], operands[2]);
8825 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8829 (define_expand "ctrap<mode>4"
8830 [(trap_if (match_operator 0 "comparison_operator"
8831 [(match_operand:FP 1 "register_operand" "")
8832 (match_operand:FP 2 "general_operand" "")])
8833 (match_operand 3 "const0_operand" ""))]
8836 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8837 operands[1], operands[2]);
8838 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8842 (define_insn "condtrap"
8843 [(trap_if (match_operator 0 "s390_comparison"
8844 [(match_operand 1 "cc_reg_operand" "c")
8849 [(set_attr "op_type" "RI")
8850 (set_attr "type" "branch")])
8852 ; crt, cgrt, cit, cgit
8853 (define_insn "*cmp_and_trap_signed_int<mode>"
8854 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8855 [(match_operand:GPR 1 "register_operand" "d,d")
8856 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8862 [(set_attr "op_type" "RRF,RIE")
8863 (set_attr "type" "branch")
8864 (set_attr "z10prop" "z10_super_c,z10_super")])
8866 ; clrt, clgrt, clfit, clgit, clt, clgt
8867 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8868 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8869 [(match_operand:GPR 1 "register_operand" "d,d,d")
8870 (match_operand:GPR 2 "general_operand" "d,D,T")])
8877 [(set_attr "op_type" "RRF,RIE,RSY")
8878 (set_attr "type" "branch")
8879 (set_attr "z10prop" "z10_super_c,z10_super,*")
8880 (set_attr "cpu_facility" "z10,z10,zEC12")])
8883 (define_insn "*load_and_trap<mode>"
8884 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
8887 (set (match_operand:GPR 1 "register_operand" "=d")
8891 [(set_attr "op_type" "RXY")])
8895 ;;- Loop instructions.
8897 ;; This is all complicated by the fact that since this is a jump insn
8898 ;; we must handle our own output reloads.
8902 ; This splitter will be matched by combine and has to add the 2 moves
8903 ; necessary to load the compare and the increment values into a
8904 ; register pair as needed by brxle.
8906 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8909 (match_operator 6 "s390_brx_operator"
8910 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8911 (match_operand:GPR 2 "general_operand" ""))
8912 (match_operand:GPR 3 "register_operand" "")])
8913 (label_ref (match_operand 0 "" ""))
8915 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8916 (plus:GPR (match_dup 1) (match_dup 2)))
8917 (clobber (match_scratch:GPR 5 ""))]
8920 "!reload_completed && !reload_in_progress"
8921 [(set (match_dup 7) (match_dup 2)) ; the increment
8922 (set (match_dup 8) (match_dup 3)) ; the comparison value
8923 (parallel [(set (pc)
8926 [(plus:GPR (match_dup 1) (match_dup 7))
8928 (label_ref (match_dup 0))
8931 (plus:GPR (match_dup 1) (match_dup 7)))
8932 (clobber (match_dup 5))
8933 (clobber (reg:CC CC_REGNUM))])]
8935 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8936 operands[7] = gen_lowpart (<GPR:MODE>mode,
8937 gen_highpart (word_mode, dreg));
8938 operands[8] = gen_lowpart (<GPR:MODE>mode,
8939 gen_lowpart (word_mode, dreg));
8944 (define_insn_and_split "*brxg_64bit"
8947 (match_operator 5 "s390_brx_operator"
8948 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8949 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8950 (subreg:DI (match_dup 2) 8)])
8951 (label_ref (match_operand 0 "" ""))
8953 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8954 (plus:DI (match_dup 1)
8955 (subreg:DI (match_dup 2) 0)))
8956 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8957 (clobber (reg:CC CC_REGNUM))]
8960 if (which_alternative != 0)
8962 else if (get_attr_length (insn) == 6)
8963 return "brx%E5g\t%1,%2,%l0";
8965 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8967 "&& reload_completed
8968 && (!REG_P (operands[3])
8969 || !rtx_equal_p (operands[1], operands[3]))"
8970 [(set (match_dup 4) (match_dup 1))
8971 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8972 (clobber (reg:CC CC_REGNUM))])
8973 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8974 (set (match_dup 3) (match_dup 4))
8975 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8976 (label_ref (match_dup 0))
8979 [(set_attr "op_type" "RIE")
8980 (set_attr "type" "branch")
8981 (set (attr "length")
8982 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8983 (const_int 6) (const_int 16)))])
8987 (define_insn_and_split "*brx_64bit"
8990 (match_operator 5 "s390_brx_operator"
8991 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8992 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8993 (subreg:SI (match_dup 2) 12)])
8994 (label_ref (match_operand 0 "" ""))
8996 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8997 (plus:SI (match_dup 1)
8998 (subreg:SI (match_dup 2) 4)))
8999 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9000 (clobber (reg:CC CC_REGNUM))]
9003 if (which_alternative != 0)
9005 else if (get_attr_length (insn) == 6)
9006 return "brx%C5\t%1,%2,%l0";
9008 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9010 "&& reload_completed
9011 && (!REG_P (operands[3])
9012 || !rtx_equal_p (operands[1], operands[3]))"
9013 [(set (match_dup 4) (match_dup 1))
9014 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9015 (clobber (reg:CC CC_REGNUM))])
9016 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9017 (set (match_dup 3) (match_dup 4))
9018 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9019 (label_ref (match_dup 0))
9022 [(set_attr "op_type" "RSI")
9023 (set_attr "type" "branch")
9024 (set (attr "length")
9025 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9026 (const_int 6) (const_int 14)))])
9030 (define_insn_and_split "*brx_31bit"
9033 (match_operator 5 "s390_brx_operator"
9034 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9035 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9036 (subreg:SI (match_dup 2) 4)])
9037 (label_ref (match_operand 0 "" ""))
9039 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9040 (plus:SI (match_dup 1)
9041 (subreg:SI (match_dup 2) 0)))
9042 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9043 (clobber (reg:CC CC_REGNUM))]
9044 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9046 if (which_alternative != 0)
9048 else if (get_attr_length (insn) == 6)
9049 return "brx%C5\t%1,%2,%l0";
9051 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9053 "&& reload_completed
9054 && (!REG_P (operands[3])
9055 || !rtx_equal_p (operands[1], operands[3]))"
9056 [(set (match_dup 4) (match_dup 1))
9057 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9058 (clobber (reg:CC CC_REGNUM))])
9059 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9060 (set (match_dup 3) (match_dup 4))
9061 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9062 (label_ref (match_dup 0))
9065 [(set_attr "op_type" "RSI")
9066 (set_attr "type" "branch")
9067 (set (attr "length")
9068 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9069 (const_int 6) (const_int 14)))])
9074 (define_expand "doloop_end"
9075 [(use (match_operand 0 "" "")) ; loop pseudo
9076 (use (match_operand 1 "" ""))] ; label
9079 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9080 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9081 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9082 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9083 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9084 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9091 (define_insn_and_split "doloop_si64"
9094 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9096 (label_ref (match_operand 0 "" ""))
9098 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9099 (plus:SI (match_dup 1) (const_int -1)))
9100 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9101 (clobber (reg:CC CC_REGNUM))]
9104 if (which_alternative != 0)
9106 else if (get_attr_length (insn) == 4)
9107 return "brct\t%1,%l0";
9109 return "ahi\t%1,-1\;jgne\t%l0";
9111 "&& reload_completed
9112 && (! REG_P (operands[2])
9113 || ! rtx_equal_p (operands[1], operands[2]))"
9114 [(set (match_dup 3) (match_dup 1))
9115 (parallel [(set (reg:CCAN CC_REGNUM)
9116 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9118 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9119 (set (match_dup 2) (match_dup 3))
9120 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9121 (label_ref (match_dup 0))
9124 [(set_attr "op_type" "RI")
9125 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9126 ; hurt us in the (rare) case of ahi.
9127 (set_attr "z10prop" "z10_super_E1")
9128 (set_attr "type" "branch")
9129 (set (attr "length")
9130 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9131 (const_int 4) (const_int 10)))])
9133 (define_insn_and_split "doloop_si31"
9136 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9138 (label_ref (match_operand 0 "" ""))
9140 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9141 (plus:SI (match_dup 1) (const_int -1)))
9142 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9143 (clobber (reg:CC CC_REGNUM))]
9146 if (which_alternative != 0)
9148 else if (get_attr_length (insn) == 4)
9149 return "brct\t%1,%l0";
9153 "&& reload_completed
9154 && (! REG_P (operands[2])
9155 || ! rtx_equal_p (operands[1], operands[2]))"
9156 [(set (match_dup 3) (match_dup 1))
9157 (parallel [(set (reg:CCAN CC_REGNUM)
9158 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9160 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9161 (set (match_dup 2) (match_dup 3))
9162 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9163 (label_ref (match_dup 0))
9166 [(set_attr "op_type" "RI")
9167 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9168 ; hurt us in the (rare) case of ahi.
9169 (set_attr "z10prop" "z10_super_E1")
9170 (set_attr "type" "branch")
9171 (set (attr "length")
9172 (if_then_else (not (match_test "flag_pic"))
9173 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9174 (const_int 4) (const_int 6))
9175 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9176 (const_int 4) (const_int 8))))])
9178 (define_insn "*doloop_si_long"
9181 (ne (match_operand:SI 1 "register_operand" "d")
9183 (match_operand 0 "address_operand" "ZR")
9185 (set (match_operand:SI 2 "register_operand" "=1")
9186 (plus:SI (match_dup 1) (const_int -1)))
9187 (clobber (match_scratch:SI 3 "=X"))
9188 (clobber (reg:CC CC_REGNUM))]
9191 if (get_attr_op_type (insn) == OP_TYPE_RR)
9192 return "bctr\t%1,%0";
9194 return "bct\t%1,%a0";
9196 [(set (attr "op_type")
9197 (if_then_else (match_operand 0 "register_operand" "")
9198 (const_string "RR") (const_string "RX")))
9199 (set_attr "type" "branch")
9200 (set_attr "atype" "agen")
9201 (set_attr "z10prop" "z10_c")
9202 (set_attr "z196prop" "z196_cracked")])
9204 (define_insn_and_split "doloop_di"
9207 (ne (match_operand:DI 1 "register_operand" "d,d,d")
9209 (label_ref (match_operand 0 "" ""))
9211 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9212 (plus:DI (match_dup 1) (const_int -1)))
9213 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9214 (clobber (reg:CC CC_REGNUM))]
9217 if (which_alternative != 0)
9219 else if (get_attr_length (insn) == 4)
9220 return "brctg\t%1,%l0";
9222 return "aghi\t%1,-1\;jgne\t%l0";
9224 "&& reload_completed
9225 && (! REG_P (operands[2])
9226 || ! rtx_equal_p (operands[1], operands[2]))"
9227 [(set (match_dup 3) (match_dup 1))
9228 (parallel [(set (reg:CCAN CC_REGNUM)
9229 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9231 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9232 (set (match_dup 2) (match_dup 3))
9233 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9234 (label_ref (match_dup 0))
9237 [(set_attr "op_type" "RI")
9238 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9239 ; hurt us in the (rare) case of ahi.
9240 (set_attr "z10prop" "z10_super_E1")
9241 (set_attr "type" "branch")
9242 (set (attr "length")
9243 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9244 (const_int 4) (const_int 10)))])
9247 ;;- Unconditional jump instructions.
9251 ; jump instruction pattern(s).
9254 (define_expand "jump"
9255 [(match_operand 0 "" "")]
9257 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9259 (define_insn "*jump64"
9260 [(set (pc) (label_ref (match_operand 0 "" "")))]
9263 if (get_attr_length (insn) == 4)
9268 [(set_attr "op_type" "RI")
9269 (set_attr "type" "branch")
9270 (set (attr "length")
9271 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9272 (const_int 4) (const_int 6)))])
9274 (define_insn "*jump31"
9275 [(set (pc) (label_ref (match_operand 0 "" "")))]
9278 gcc_assert (get_attr_length (insn) == 4);
9281 [(set_attr "op_type" "RI")
9282 (set_attr "type" "branch")
9283 (set (attr "length")
9284 (if_then_else (not (match_test "flag_pic"))
9285 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9286 (const_int 4) (const_int 6))
9287 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9288 (const_int 4) (const_int 8))))])
9291 ; indirect-jump instruction pattern(s).
9294 (define_insn "indirect_jump"
9295 [(set (pc) (match_operand 0 "address_operand" "ZR"))]
9298 if (get_attr_op_type (insn) == OP_TYPE_RR)
9303 [(set (attr "op_type")
9304 (if_then_else (match_operand 0 "register_operand" "")
9305 (const_string "RR") (const_string "RX")))
9306 (set_attr "type" "branch")
9307 (set_attr "atype" "agen")])
9310 ; casesi instruction pattern(s).
9313 (define_insn "casesi_jump"
9314 [(set (pc) (match_operand 0 "address_operand" "ZR"))
9315 (use (label_ref (match_operand 1 "" "")))]
9318 if (get_attr_op_type (insn) == OP_TYPE_RR)
9323 [(set (attr "op_type")
9324 (if_then_else (match_operand 0 "register_operand" "")
9325 (const_string "RR") (const_string "RX")))
9326 (set_attr "type" "branch")
9327 (set_attr "atype" "agen")])
9329 (define_expand "casesi"
9330 [(match_operand:SI 0 "general_operand" "")
9331 (match_operand:SI 1 "general_operand" "")
9332 (match_operand:SI 2 "general_operand" "")
9333 (label_ref (match_operand 3 "" ""))
9334 (label_ref (match_operand 4 "" ""))]
9337 rtx index = gen_reg_rtx (SImode);
9338 rtx base = gen_reg_rtx (Pmode);
9339 rtx target = gen_reg_rtx (Pmode);
9341 emit_move_insn (index, operands[0]);
9342 emit_insn (gen_subsi3 (index, index, operands[1]));
9343 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9346 if (Pmode != SImode)
9347 index = convert_to_mode (Pmode, index, 1);
9348 if (GET_CODE (index) != REG)
9349 index = copy_to_mode_reg (Pmode, index);
9352 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9354 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9356 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9358 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9359 emit_move_insn (target, index);
9362 target = gen_rtx_PLUS (Pmode, base, target);
9363 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9370 ;;- Jump to subroutine.
9375 ; untyped call instruction pattern(s).
9378 ;; Call subroutine returning any type.
9379 (define_expand "untyped_call"
9380 [(parallel [(call (match_operand 0 "" "")
9382 (match_operand 1 "" "")
9383 (match_operand 2 "" "")])]
9388 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9390 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9392 rtx set = XVECEXP (operands[2], 0, i);
9393 emit_move_insn (SET_DEST (set), SET_SRC (set));
9396 /* The optimizer does not know that the call sets the function value
9397 registers we stored in the result block. We avoid problems by
9398 claiming that all hard registers are used and clobbered at this
9400 emit_insn (gen_blockage ());
9405 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9406 ;; all of memory. This blocks insns from being moved across this point.
9408 (define_insn "blockage"
9409 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9412 [(set_attr "type" "none")
9413 (set_attr "length" "0")])
9419 (define_expand "sibcall"
9420 [(call (match_operand 0 "" "")
9421 (match_operand 1 "" ""))]
9424 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9428 (define_insn "*sibcall_br"
9429 [(call (mem:QI (reg SIBCALL_REGNUM))
9430 (match_operand 0 "const_int_operand" "n"))]
9431 "SIBLING_CALL_P (insn)
9432 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9434 [(set_attr "op_type" "RR")
9435 (set_attr "type" "branch")
9436 (set_attr "atype" "agen")])
9438 (define_insn "*sibcall_brc"
9439 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9440 (match_operand 1 "const_int_operand" "n"))]
9441 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9443 [(set_attr "op_type" "RI")
9444 (set_attr "type" "branch")])
9446 (define_insn "*sibcall_brcl"
9447 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9448 (match_operand 1 "const_int_operand" "n"))]
9449 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9451 [(set_attr "op_type" "RIL")
9452 (set_attr "type" "branch")])
9455 ; sibcall_value patterns
9458 (define_expand "sibcall_value"
9459 [(set (match_operand 0 "" "")
9460 (call (match_operand 1 "" "")
9461 (match_operand 2 "" "")))]
9464 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9468 (define_insn "*sibcall_value_br"
9469 [(set (match_operand 0 "" "")
9470 (call (mem:QI (reg SIBCALL_REGNUM))
9471 (match_operand 1 "const_int_operand" "n")))]
9472 "SIBLING_CALL_P (insn)
9473 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9475 [(set_attr "op_type" "RR")
9476 (set_attr "type" "branch")
9477 (set_attr "atype" "agen")])
9479 (define_insn "*sibcall_value_brc"
9480 [(set (match_operand 0 "" "")
9481 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9482 (match_operand 2 "const_int_operand" "n")))]
9483 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9485 [(set_attr "op_type" "RI")
9486 (set_attr "type" "branch")])
9488 (define_insn "*sibcall_value_brcl"
9489 [(set (match_operand 0 "" "")
9490 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9491 (match_operand 2 "const_int_operand" "n")))]
9492 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9494 [(set_attr "op_type" "RIL")
9495 (set_attr "type" "branch")])
9499 ; call instruction pattern(s).
9502 (define_expand "call"
9503 [(call (match_operand 0 "" "")
9504 (match_operand 1 "" ""))
9505 (use (match_operand 2 "" ""))]
9508 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9509 gen_rtx_REG (Pmode, RETURN_REGNUM));
9513 (define_insn "*bras"
9514 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9515 (match_operand 1 "const_int_operand" "n"))
9516 (clobber (match_operand 2 "register_operand" "=r"))]
9517 "!SIBLING_CALL_P (insn)
9518 && TARGET_SMALL_EXEC
9519 && GET_MODE (operands[2]) == Pmode"
9521 [(set_attr "op_type" "RI")
9522 (set_attr "type" "jsr")
9523 (set_attr "z196prop" "z196_cracked")])
9525 (define_insn "*brasl"
9526 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9527 (match_operand 1 "const_int_operand" "n"))
9528 (clobber (match_operand 2 "register_operand" "=r"))]
9529 "!SIBLING_CALL_P (insn)
9531 && GET_MODE (operands[2]) == Pmode"
9533 [(set_attr "op_type" "RIL")
9534 (set_attr "type" "jsr")
9535 (set_attr "z196prop" "z196_cracked")])
9537 (define_insn "*basr"
9538 [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
9539 (match_operand 1 "const_int_operand" "n"))
9540 (clobber (match_operand 2 "register_operand" "=r"))]
9541 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9543 if (get_attr_op_type (insn) == OP_TYPE_RR)
9544 return "basr\t%2,%0";
9546 return "bas\t%2,%a0";
9548 [(set (attr "op_type")
9549 (if_then_else (match_operand 0 "register_operand" "")
9550 (const_string "RR") (const_string "RX")))
9551 (set_attr "type" "jsr")
9552 (set_attr "atype" "agen")
9553 (set_attr "z196prop" "z196_cracked")])
9556 ; call_value instruction pattern(s).
9559 (define_expand "call_value"
9560 [(set (match_operand 0 "" "")
9561 (call (match_operand 1 "" "")
9562 (match_operand 2 "" "")))
9563 (use (match_operand 3 "" ""))]
9566 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9567 gen_rtx_REG (Pmode, RETURN_REGNUM));
9571 (define_insn "*bras_r"
9572 [(set (match_operand 0 "" "")
9573 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9574 (match_operand:SI 2 "const_int_operand" "n")))
9575 (clobber (match_operand 3 "register_operand" "=r"))]
9576 "!SIBLING_CALL_P (insn)
9577 && TARGET_SMALL_EXEC
9578 && GET_MODE (operands[3]) == Pmode"
9580 [(set_attr "op_type" "RI")
9581 (set_attr "type" "jsr")
9582 (set_attr "z196prop" "z196_cracked")])
9584 (define_insn "*brasl_r"
9585 [(set (match_operand 0 "" "")
9586 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9587 (match_operand 2 "const_int_operand" "n")))
9588 (clobber (match_operand 3 "register_operand" "=r"))]
9589 "!SIBLING_CALL_P (insn)
9591 && GET_MODE (operands[3]) == Pmode"
9593 [(set_attr "op_type" "RIL")
9594 (set_attr "type" "jsr")
9595 (set_attr "z196prop" "z196_cracked")])
9597 (define_insn "*basr_r"
9598 [(set (match_operand 0 "" "")
9599 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9600 (match_operand 2 "const_int_operand" "n")))
9601 (clobber (match_operand 3 "register_operand" "=r"))]
9602 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9604 if (get_attr_op_type (insn) == OP_TYPE_RR)
9605 return "basr\t%3,%1";
9607 return "bas\t%3,%a1";
9609 [(set (attr "op_type")
9610 (if_then_else (match_operand 1 "register_operand" "")
9611 (const_string "RR") (const_string "RX")))
9612 (set_attr "type" "jsr")
9613 (set_attr "atype" "agen")
9614 (set_attr "z196prop" "z196_cracked")])
9617 ;;- Thread-local storage support.
9620 (define_expand "get_thread_pointer<mode>"
9621 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9625 (define_expand "set_thread_pointer<mode>"
9626 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9627 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9631 (define_insn "*set_tp"
9632 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9635 [(set_attr "type" "none")
9636 (set_attr "length" "0")])
9638 (define_insn "*tls_load_64"
9639 [(set (match_operand:DI 0 "register_operand" "=d")
9640 (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
9641 (match_operand:DI 2 "" "")]
9645 [(set_attr "op_type" "RXE")
9646 (set_attr "z10prop" "z10_fwd_A3")])
9648 (define_insn "*tls_load_31"
9649 [(set (match_operand:SI 0 "register_operand" "=d,d")
9650 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9651 (match_operand:SI 2 "" "")]
9657 [(set_attr "op_type" "RX,RXY")
9658 (set_attr "type" "load")
9659 (set_attr "cpu_facility" "*,longdisp")
9660 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9662 (define_insn "*bras_tls"
9663 [(set (match_operand 0 "" "")
9664 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9665 (match_operand 2 "const_int_operand" "n")))
9666 (clobber (match_operand 3 "register_operand" "=r"))
9667 (use (match_operand 4 "" ""))]
9668 "!SIBLING_CALL_P (insn)
9669 && TARGET_SMALL_EXEC
9670 && GET_MODE (operands[3]) == Pmode"
9672 [(set_attr "op_type" "RI")
9673 (set_attr "type" "jsr")
9674 (set_attr "z196prop" "z196_cracked")])
9676 (define_insn "*brasl_tls"
9677 [(set (match_operand 0 "" "")
9678 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9679 (match_operand 2 "const_int_operand" "n")))
9680 (clobber (match_operand 3 "register_operand" "=r"))
9681 (use (match_operand 4 "" ""))]
9682 "!SIBLING_CALL_P (insn)
9684 && GET_MODE (operands[3]) == Pmode"
9686 [(set_attr "op_type" "RIL")
9687 (set_attr "type" "jsr")
9688 (set_attr "z196prop" "z196_cracked")])
9690 (define_insn "*basr_tls"
9691 [(set (match_operand 0 "" "")
9692 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9693 (match_operand 2 "const_int_operand" "n")))
9694 (clobber (match_operand 3 "register_operand" "=r"))
9695 (use (match_operand 4 "" ""))]
9696 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9698 if (get_attr_op_type (insn) == OP_TYPE_RR)
9699 return "basr\t%3,%1%J4";
9701 return "bas\t%3,%a1%J4";
9703 [(set (attr "op_type")
9704 (if_then_else (match_operand 1 "register_operand" "")
9705 (const_string "RR") (const_string "RX")))
9706 (set_attr "type" "jsr")
9707 (set_attr "atype" "agen")
9708 (set_attr "z196prop" "z196_cracked")])
9711 ;;- Atomic operations
9715 ; memory barrier patterns.
9718 (define_expand "mem_signal_fence"
9719 [(match_operand:SI 0 "const_int_operand")] ;; model
9722 /* The s390 memory model is strong enough not to require any
9723 barrier in order to synchronize a thread with itself. */
9727 (define_expand "mem_thread_fence"
9728 [(match_operand:SI 0 "const_int_operand")] ;; model
9731 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9732 enough not to require barriers of any kind. */
9733 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
9735 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9736 MEM_VOLATILE_P (mem) = 1;
9737 emit_insn (gen_mem_thread_fence_1 (mem));
9742 ; Although bcr is superscalar on Z10, this variant will never
9743 ; become part of an execution group.
9744 ; With z196 we can make use of the fast-BCR-serialization facility.
9745 ; This allows for a slightly faster sync which is sufficient for our
9747 (define_insn "mem_thread_fence_1"
9748 [(set (match_operand:BLK 0 "" "")
9749 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9757 [(set_attr "op_type" "RR")
9758 (set_attr "mnemonic" "bcr_flush")
9759 (set_attr "z196prop" "z196_alone")])
9762 ; atomic load/store operations
9765 ; Atomic loads need not examine the memory model at all.
9766 (define_expand "atomic_load<mode>"
9767 [(match_operand:DINT 0 "register_operand") ;; output
9768 (match_operand:DINT 1 "memory_operand") ;; memory
9769 (match_operand:SI 2 "const_int_operand")] ;; model
9772 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9775 if (<MODE>mode == TImode)
9776 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9777 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9778 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9780 emit_move_insn (operands[0], operands[1]);
9784 ; Different from movdi_31 in that we want no splitters.
9785 (define_insn "atomic_loaddi_1"
9786 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9787 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9795 [(set_attr "op_type" "RS,RSY,RS,RSY")
9796 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
9797 (set_attr "type" "lm,lm,floaddf,floaddf")])
9799 (define_insn "atomic_loadti_1"
9800 [(set (match_operand:TI 0 "register_operand" "=r")
9801 (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
9805 [(set_attr "op_type" "RXY")
9806 (set_attr "type" "other")])
9808 ; Atomic stores must(?) enforce sequential consistency.
9809 (define_expand "atomic_store<mode>"
9810 [(match_operand:DINT 0 "memory_operand") ;; memory
9811 (match_operand:DINT 1 "register_operand") ;; input
9812 (match_operand:SI 2 "const_int_operand")] ;; model
9815 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
9817 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9820 if (<MODE>mode == TImode)
9821 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9822 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9823 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9825 emit_move_insn (operands[0], operands[1]);
9826 if (is_mm_seq_cst (model))
9827 emit_insn (gen_mem_thread_fence (operands[2]));
9831 ; Different from movdi_31 in that we want no splitters.
9832 (define_insn "atomic_storedi_1"
9833 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9834 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9842 [(set_attr "op_type" "RS,RSY,RS,RSY")
9843 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
9844 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9846 (define_insn "atomic_storeti_1"
9847 [(set (match_operand:TI 0 "memory_operand" "=T")
9848 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9852 [(set_attr "op_type" "RXY")
9853 (set_attr "type" "other")])
9856 ; compare and swap patterns.
9859 (define_expand "atomic_compare_and_swap<mode>"
9860 [(match_operand:SI 0 "register_operand") ;; bool success output
9861 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9862 (match_operand:DGPR 2 "memory_operand") ;; memory
9863 (match_operand:DGPR 3 "register_operand") ;; expected intput
9864 (match_operand:DGPR 4 "register_operand") ;; newval intput
9865 (match_operand:SI 5 "const_int_operand") ;; is_weak
9866 (match_operand:SI 6 "const_int_operand") ;; success model
9867 (match_operand:SI 7 "const_int_operand")] ;; failure model
9870 rtx cc, cmp, output = operands[1];
9872 if (!register_operand (output, <MODE>mode))
9873 output = gen_reg_rtx (<MODE>mode);
9875 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9878 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9879 (output, operands[2], operands[3], operands[4]));
9881 /* We deliberately accept non-register operands in the predicate
9882 to ensure the write back to the output operand happens *before*
9883 the store-flags code below. This makes it easier for combine
9884 to merge the store-flags code with a potential test-and-branch
9885 pattern following (immediately!) afterwards. */
9886 if (output != operands[1])
9887 emit_move_insn (operands[1], output);
9889 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9890 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9891 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9895 (define_expand "atomic_compare_and_swap<mode>"
9896 [(match_operand:SI 0 "register_operand") ;; bool success output
9897 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9898 (match_operand:HQI 2 "memory_operand") ;; memory
9899 (match_operand:HQI 3 "general_operand") ;; expected intput
9900 (match_operand:HQI 4 "general_operand") ;; newval intput
9901 (match_operand:SI 5 "const_int_operand") ;; is_weak
9902 (match_operand:SI 6 "const_int_operand") ;; success model
9903 (match_operand:SI 7 "const_int_operand")] ;; failure model
9906 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9907 operands[3], operands[4], INTVAL (operands[5]));
9911 (define_expand "atomic_compare_and_swap<mode>_internal"
9913 [(set (match_operand:DGPR 0 "register_operand")
9914 (match_operand:DGPR 1 "memory_operand"))
9916 (unspec_volatile:DGPR
9918 (match_operand:DGPR 2 "register_operand")
9919 (match_operand:DGPR 3 "register_operand")]
9921 (set (reg:CCZ1 CC_REGNUM)
9922 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9926 (define_insn "*atomic_compare_and_swap<mode>_1"
9927 [(set (match_operand:TDI 0 "register_operand" "=r")
9928 (match_operand:TDI 1 "memory_operand" "+S"))
9930 (unspec_volatile:TDI
9932 (match_operand:TDI 2 "register_operand" "0")
9933 (match_operand:TDI 3 "register_operand" "r")]
9935 (set (reg:CCZ1 CC_REGNUM)
9936 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9938 "c<td>sg\t%0,%3,%S1"
9939 [(set_attr "op_type" "RSY")
9940 (set_attr "type" "sem")])
9943 (define_insn "*atomic_compare_and_swapdi_2"
9944 [(set (match_operand:DI 0 "register_operand" "=r,r")
9945 (match_operand:DI 1 "memory_operand" "+Q,S"))
9949 (match_operand:DI 2 "register_operand" "0,0")
9950 (match_operand:DI 3 "register_operand" "r,r")]
9952 (set (reg:CCZ1 CC_REGNUM)
9953 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9958 [(set_attr "op_type" "RS,RSY")
9959 (set_attr "cpu_facility" "*,longdisp")
9960 (set_attr "type" "sem")])
9963 (define_insn "*atomic_compare_and_swapsi_3"
9964 [(set (match_operand:SI 0 "register_operand" "=r,r")
9965 (match_operand:SI 1 "memory_operand" "+Q,S"))
9969 (match_operand:SI 2 "register_operand" "0,0")
9970 (match_operand:SI 3 "register_operand" "r,r")]
9972 (set (reg:CCZ1 CC_REGNUM)
9973 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9978 [(set_attr "op_type" "RS,RSY")
9979 (set_attr "cpu_facility" "*,longdisp")
9980 (set_attr "type" "sem")])
9983 ; Other atomic instruction patterns.
9986 ; z196 load and add, xor, or and and instructions
9988 (define_expand "atomic_fetch_<atomic><mode>"
9989 [(match_operand:GPR 0 "register_operand") ;; val out
9991 (match_operand:GPR 1 "memory_operand") ;; memory
9992 (match_operand:GPR 2 "register_operand")) ;; val in
9993 (match_operand:SI 3 "const_int_operand")] ;; model
9996 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9999 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
10000 (operands[0], operands[1], operands[2]));
10004 ; lan, lang, lao, laog, lax, laxg, laa, laag
10005 (define_insn "atomic_fetch_<atomic><mode>_iaf"
10006 [(set (match_operand:GPR 0 "register_operand" "=d")
10007 (match_operand:GPR 1 "memory_operand" "+S"))
10009 (unspec_volatile:GPR
10010 [(ATOMIC_Z196:GPR (match_dup 1)
10011 (match_operand:GPR 2 "general_operand" "d"))]
10012 UNSPECV_ATOMIC_OP))
10013 (clobber (reg:CC CC_REGNUM))]
10015 "la<noxa><g>\t%0,%2,%1"
10016 [(set_attr "op_type" "RSY")
10017 (set_attr "type" "sem")])
10019 ;; For SImode and larger, the optabs.c code will do just fine in
10020 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
10021 ;; better by expanding our own loop.
10023 (define_expand "atomic_<atomic><mode>"
10025 (match_operand:HQI 0 "memory_operand") ;; memory
10026 (match_operand:HQI 1 "general_operand")) ;; val in
10027 (match_operand:SI 2 "const_int_operand")] ;; model
10030 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10031 operands[1], false);
10035 (define_expand "atomic_fetch_<atomic><mode>"
10036 [(match_operand:HQI 0 "register_operand") ;; val out
10038 (match_operand:HQI 1 "memory_operand") ;; memory
10039 (match_operand:HQI 2 "general_operand")) ;; val in
10040 (match_operand:SI 3 "const_int_operand")] ;; model
10043 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10044 operands[2], false);
10048 (define_expand "atomic_<atomic>_fetch<mode>"
10049 [(match_operand:HQI 0 "register_operand") ;; val out
10051 (match_operand:HQI 1 "memory_operand") ;; memory
10052 (match_operand:HQI 2 "general_operand")) ;; val in
10053 (match_operand:SI 3 "const_int_operand")] ;; model
10056 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10057 operands[2], true);
10061 (define_expand "atomic_exchange<mode>"
10062 [(match_operand:HQI 0 "register_operand") ;; val out
10063 (match_operand:HQI 1 "memory_operand") ;; memory
10064 (match_operand:HQI 2 "general_operand") ;; val in
10065 (match_operand:SI 3 "const_int_operand")] ;; model
10068 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
10069 operands[2], false);
10074 ;;- Miscellaneous instructions.
10078 ; allocate stack instruction pattern(s).
10081 (define_expand "allocate_stack"
10082 [(match_operand 0 "general_operand" "")
10083 (match_operand 1 "general_operand" "")]
10086 rtx temp = gen_reg_rtx (Pmode);
10088 emit_move_insn (temp, s390_back_chain_rtx ());
10089 anti_adjust_stack (operands[1]);
10090 emit_move_insn (s390_back_chain_rtx (), temp);
10092 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10098 ; setjmp instruction pattern.
10101 (define_expand "builtin_setjmp_receiver"
10102 [(match_operand 0 "" "")]
10105 emit_insn (s390_load_got ());
10106 emit_use (pic_offset_table_rtx);
10110 ;; These patterns say how to save and restore the stack pointer. We need not
10111 ;; save the stack pointer at function level since we are careful to
10112 ;; preserve the backchain. At block level, we have to restore the backchain
10113 ;; when we restore the stack pointer.
10115 ;; For nonlocal gotos, we must save both the stack pointer and its
10116 ;; backchain and restore both. Note that in the nonlocal case, the
10117 ;; save area is a memory location.
10119 (define_expand "save_stack_function"
10120 [(match_operand 0 "general_operand" "")
10121 (match_operand 1 "general_operand" "")]
10125 (define_expand "restore_stack_function"
10126 [(match_operand 0 "general_operand" "")
10127 (match_operand 1 "general_operand" "")]
10131 (define_expand "restore_stack_block"
10132 [(match_operand 0 "register_operand" "")
10133 (match_operand 1 "register_operand" "")]
10136 rtx temp = gen_reg_rtx (Pmode);
10138 emit_move_insn (temp, s390_back_chain_rtx ());
10139 emit_move_insn (operands[0], operands[1]);
10140 emit_move_insn (s390_back_chain_rtx (), temp);
10145 (define_expand "save_stack_nonlocal"
10146 [(match_operand 0 "memory_operand" "")
10147 (match_operand 1 "register_operand" "")]
10150 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10152 /* Copy the backchain to the first word, sp to the second and the
10153 literal pool base to the third. */
10155 rtx save_bc = adjust_address (operands[0], Pmode, 0);
10156 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10157 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10159 if (TARGET_BACKCHAIN)
10160 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10162 emit_move_insn (save_sp, operands[1]);
10163 emit_move_insn (save_bp, base);
10168 (define_expand "restore_stack_nonlocal"
10169 [(match_operand 0 "register_operand" "")
10170 (match_operand 1 "memory_operand" "")]
10173 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10174 rtx temp = NULL_RTX;
10176 /* Restore the backchain from the first word, sp from the second and the
10177 literal pool base from the third. */
10179 rtx save_bc = adjust_address (operands[1], Pmode, 0);
10180 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10181 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10183 if (TARGET_BACKCHAIN)
10184 temp = force_reg (Pmode, save_bc);
10186 emit_move_insn (base, save_bp);
10187 emit_move_insn (operands[0], save_sp);
10190 emit_move_insn (s390_back_chain_rtx (), temp);
10196 (define_expand "exception_receiver"
10200 s390_set_has_landing_pad_p (true);
10205 ; nop instruction pattern(s).
10212 [(set_attr "op_type" "RR")
10213 (set_attr "z10prop" "z10_fr_E1")])
10215 (define_insn "nop1"
10219 [(set_attr "op_type" "RR")])
10221 ;;- Undeletable nops (used for hotpatching)
10223 (define_insn "nop_2_byte"
10224 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10227 [(set_attr "op_type" "RR")])
10229 (define_insn "nop_4_byte"
10230 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10233 [(set_attr "op_type" "RX")])
10235 (define_insn "nop_6_byte"
10236 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10239 [(set_attr "op_type" "RIL")])
10243 ; Special literal pool access instruction pattern(s).
10246 (define_insn "*pool_entry"
10247 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10248 UNSPECV_POOL_ENTRY)]
10251 machine_mode mode = GET_MODE (PATTERN (insn));
10252 unsigned int align = GET_MODE_BITSIZE (mode);
10253 s390_output_pool_entry (operands[0], mode, align);
10256 [(set (attr "length")
10257 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10259 (define_insn "pool_align"
10260 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10261 UNSPECV_POOL_ALIGN)]
10264 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10266 (define_insn "pool_section_start"
10267 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10270 switch_to_section (targetm.asm_out.function_rodata_section
10271 (current_function_decl));
10274 [(set_attr "length" "0")])
10276 (define_insn "pool_section_end"
10277 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10280 switch_to_section (current_function_section ());
10283 [(set_attr "length" "0")])
10285 (define_insn "main_base_31_small"
10286 [(set (match_operand 0 "register_operand" "=a")
10287 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10288 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10290 [(set_attr "op_type" "RR")
10291 (set_attr "type" "la")
10292 (set_attr "z196prop" "z196_cracked")])
10294 (define_insn "main_base_31_large"
10295 [(set (match_operand 0 "register_operand" "=a")
10296 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10297 (set (pc) (label_ref (match_operand 2 "" "")))]
10298 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10300 [(set_attr "op_type" "RI")
10301 (set_attr "z196prop" "z196_cracked")])
10303 (define_insn "main_base_64"
10304 [(set (match_operand 0 "register_operand" "=a")
10305 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10306 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10308 [(set_attr "op_type" "RIL")
10309 (set_attr "type" "larl")
10310 (set_attr "z10prop" "z10_fwd_A1")])
10312 (define_insn "main_pool"
10313 [(set (match_operand 0 "register_operand" "=a")
10314 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10315 "GET_MODE (operands[0]) == Pmode"
10317 gcc_unreachable ();
10319 [(set (attr "type")
10320 (if_then_else (match_test "TARGET_CPU_ZARCH")
10321 (const_string "larl") (const_string "la")))])
10323 (define_insn "reload_base_31"
10324 [(set (match_operand 0 "register_operand" "=a")
10325 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10326 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10327 "basr\t%0,0\;la\t%0,%1-.(%0)"
10328 [(set_attr "length" "6")
10329 (set_attr "type" "la")
10330 (set_attr "z196prop" "z196_cracked")])
10332 (define_insn "reload_base_64"
10333 [(set (match_operand 0 "register_operand" "=a")
10334 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10335 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10337 [(set_attr "op_type" "RIL")
10338 (set_attr "type" "larl")
10339 (set_attr "z10prop" "z10_fwd_A1")])
10341 (define_insn "pool"
10342 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10345 gcc_unreachable ();
10347 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10350 ;; Insns related to generating the function prologue and epilogue.
10354 (define_expand "prologue"
10355 [(use (const_int 0))]
10357 "s390_emit_prologue (); DONE;")
10359 (define_expand "epilogue"
10360 [(use (const_int 1))]
10362 "s390_emit_epilogue (false); DONE;")
10364 (define_expand "sibcall_epilogue"
10365 [(use (const_int 0))]
10367 "s390_emit_epilogue (true); DONE;")
10369 ;; A direct return instruction, without using an epilogue.
10370 (define_insn "<code>"
10372 "s390_can_use_<code>_insn ()"
10374 [(set_attr "op_type" "RR")
10375 (set_attr "type" "jsr")
10376 (set_attr "atype" "agen")])
10378 (define_insn "*return"
10380 (use (match_operand 0 "register_operand" "a"))]
10381 "GET_MODE (operands[0]) == Pmode"
10383 [(set_attr "op_type" "RR")
10384 (set_attr "type" "jsr")
10385 (set_attr "atype" "agen")])
10388 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10389 ;; pointer. This is used for compatibility.
10391 (define_expand "ptr_extend"
10392 [(set (match_operand:DI 0 "register_operand" "=r")
10393 (match_operand:SI 1 "register_operand" "r"))]
10396 emit_insn (gen_anddi3 (operands[0],
10397 gen_lowpart (DImode, operands[1]),
10398 GEN_INT (0x7fffffff)));
10402 ;; Instruction definition to expand eh_return macro to support
10403 ;; swapping in special linkage return addresses.
10405 (define_expand "eh_return"
10406 [(use (match_operand 0 "register_operand" ""))]
10409 s390_emit_tpf_eh_return (operands[0]);
10414 ; Stack Protector Patterns
10417 (define_expand "stack_protect_set"
10418 [(set (match_operand 0 "memory_operand" "")
10419 (match_operand 1 "memory_operand" ""))]
10422 #ifdef TARGET_THREAD_SSP_OFFSET
10424 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10425 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10428 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10430 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10435 (define_insn "stack_protect_set<mode>"
10436 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10437 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10439 "mvc\t%O0(%G0,%R0),%S1"
10440 [(set_attr "op_type" "SS")])
10442 (define_expand "stack_protect_test"
10443 [(set (reg:CC CC_REGNUM)
10444 (compare (match_operand 0 "memory_operand" "")
10445 (match_operand 1 "memory_operand" "")))
10446 (match_operand 2 "" "")]
10450 #ifdef TARGET_THREAD_SSP_OFFSET
10452 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10453 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10456 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10458 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10460 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10461 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10462 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10466 (define_insn "stack_protect_test<mode>"
10467 [(set (reg:CCZ CC_REGNUM)
10468 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10469 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10471 "clc\t%O0(%G0,%R0),%S1"
10472 [(set_attr "op_type" "SS")])
10474 ; This is used in s390_emit_prologue in order to prevent insns
10475 ; adjusting the stack pointer to be moved over insns writing stack
10476 ; slots using a copy of the stack pointer in a different register.
10477 (define_insn "stack_tie"
10478 [(set (match_operand:BLK 0 "memory_operand" "+m")
10479 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10482 [(set_attr "length" "0")])
10485 (define_insn "stack_restore_from_fpr"
10486 [(set (reg:DI STACK_REGNUM)
10487 (match_operand:DI 0 "register_operand" "f"))
10488 (clobber (mem:BLK (scratch)))]
10491 [(set_attr "op_type" "RRE")])
10494 ; Data prefetch patterns
10497 (define_insn "prefetch"
10498 [(prefetch (match_operand 0 "address_operand" "ZT,X")
10499 (match_operand:SI 1 "const_int_operand" " n,n")
10500 (match_operand:SI 2 "const_int_operand" " n,n"))]
10503 switch (which_alternative)
10506 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10508 if (larl_operand (operands[0], Pmode))
10509 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10512 /* This might be reached for symbolic operands with an odd
10513 addend. We simply omit the prefetch for such rare cases. */
10518 [(set_attr "type" "load,larl")
10519 (set_attr "op_type" "RXY,RIL")
10520 (set_attr "z10prop" "z10_super")
10521 (set_attr "z196prop" "z196_alone")])
10525 ; Byte swap instructions
10528 ; FIXME: There is also mvcin but we cannot use it since src and target
10530 (define_insn "bswap<mode>2"
10531 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
10532 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
10538 [(set_attr "type" "*,load,store")
10539 (set_attr "op_type" "RRE,RXY,RXY")
10540 (set_attr "z10prop" "z10_super")])
10542 (define_insn "bswaphi2"
10543 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
10544 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
10550 [(set_attr "type" "*,load,store")
10551 (set_attr "op_type" "RRE,RXY,RXY")
10552 (set_attr "z10prop" "z10_super")])
10555 [(set (match_operand:HI 0 "register_operand" "")
10556 (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10558 [(set (match_dup 2) (bswap:SI (match_dup 3)))
10559 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10561 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10562 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10567 ; Population count instruction
10570 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10571 ; portions and stores the result in the corresponding bytes in op0.
10572 (define_insn "*popcount<mode>"
10573 [(set (match_operand:INT 0 "register_operand" "=d")
10574 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10575 (clobber (reg:CC CC_REGNUM))]
10578 [(set_attr "op_type" "RRE")])
10580 (define_expand "popcountdi2"
10582 (parallel [(set (match_operand:DI 0 "register_operand" "")
10583 (unspec:DI [(match_operand:DI 1 "register_operand")]
10585 (clobber (reg:CC CC_REGNUM))])
10586 ; sllg op2, op0, 32
10587 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10589 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10590 (clobber (reg:CC CC_REGNUM))])
10591 ; sllg op2, op0, 16
10593 (ashift:DI (match_dup 0) (const_int 16)))
10595 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10596 (clobber (reg:CC CC_REGNUM))])
10598 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10600 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10601 (clobber (reg:CC CC_REGNUM))])
10602 ; srlg op0, op0, 56
10603 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10604 "TARGET_Z196 && TARGET_64BIT"
10605 "operands[2] = gen_reg_rtx (DImode);")
10607 (define_expand "popcountsi2"
10609 (parallel [(set (match_operand:SI 0 "register_operand" "")
10610 (unspec:SI [(match_operand:SI 1 "register_operand")]
10612 (clobber (reg:CC CC_REGNUM))])
10613 ; sllk op2, op0, 16
10615 (ashift:SI (match_dup 0) (const_int 16)))
10617 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10618 (clobber (reg:CC CC_REGNUM))])
10620 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10622 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10623 (clobber (reg:CC CC_REGNUM))])
10625 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10627 "operands[2] = gen_reg_rtx (SImode);")
10629 (define_expand "popcounthi2"
10631 (parallel [(set (match_operand:HI 0 "register_operand" "")
10632 (unspec:HI [(match_operand:HI 1 "register_operand")]
10634 (clobber (reg:CC CC_REGNUM))])
10637 (ashift:SI (match_dup 0) (const_int 8)))
10639 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10640 (clobber (reg:CC CC_REGNUM))])
10642 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10644 "operands[2] = gen_reg_rtx (SImode);")
10646 (define_expand "popcountqi2"
10648 (parallel [(set (match_operand:QI 0 "register_operand" "")
10649 (unspec:QI [(match_operand:QI 1 "register_operand")]
10651 (clobber (reg:CC CC_REGNUM))])]
10656 ;;- Copy sign instructions
10659 (define_insn "copysign<mode>3"
10660 [(set (match_operand:FP 0 "register_operand" "=f")
10661 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10662 (match_operand:FP 2 "register_operand" "f")]
10666 [(set_attr "op_type" "RRF")
10667 (set_attr "type" "fsimp<mode>")])
10671 ;;- Transactional execution instructions
10674 ; This splitter helps combine to make use of CC directly when
10675 ; comparing the integer result of a tbegin builtin with a constant.
10676 ; The unspec is already removed by canonicalize_comparison. So this
10677 ; splitters only job is to turn the PARALLEL into separate insns
10678 ; again. Unfortunately this only works with the very first cc/int
10679 ; compare since combine is not able to deal with data flow across
10680 ; basic block boundaries.
10682 ; It needs to be an insn pattern as well since combine does not apply
10683 ; the splitter directly. Combine would only use it if it actually
10684 ; would reduce the number of instructions.
10685 (define_insn_and_split "*ccraw_to_int"
10688 (match_operator 0 "s390_eqne_operator"
10689 [(reg:CCRAW CC_REGNUM)
10690 (match_operand 1 "const_int_operand" "")])
10691 (label_ref (match_operand 2 "" ""))
10693 (set (match_operand:SI 3 "register_operand" "=d")
10694 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10698 [(set (match_dup 3)
10699 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10701 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10702 (label_ref (match_dup 2))
10706 ; Non-constrained transaction begin
10708 (define_expand "tbegin"
10709 [(match_operand:SI 0 "register_operand" "")
10710 (match_operand:BLK 1 "memory_operand" "")]
10713 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10717 (define_expand "tbegin_nofloat"
10718 [(match_operand:SI 0 "register_operand" "")
10719 (match_operand:BLK 1 "memory_operand" "")]
10722 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10726 (define_expand "tbegin_retry"
10727 [(match_operand:SI 0 "register_operand" "")
10728 (match_operand:BLK 1 "memory_operand" "")
10729 (match_operand:SI 2 "general_operand" "")]
10732 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10736 (define_expand "tbegin_retry_nofloat"
10737 [(match_operand:SI 0 "register_operand" "")
10738 (match_operand:BLK 1 "memory_operand" "")
10739 (match_operand:SI 2 "general_operand" "")]
10742 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10746 ; Clobber VRs since they don't get restored
10747 (define_insn "tbegin_1_z13"
10748 [(set (reg:CCRAW CC_REGNUM)
10749 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10751 (set (match_operand:BLK 1 "memory_operand" "=Q")
10752 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10753 (clobber (reg:TI 16)) (clobber (reg:TI 38))
10754 (clobber (reg:TI 17)) (clobber (reg:TI 39))
10755 (clobber (reg:TI 18)) (clobber (reg:TI 40))
10756 (clobber (reg:TI 19)) (clobber (reg:TI 41))
10757 (clobber (reg:TI 20)) (clobber (reg:TI 42))
10758 (clobber (reg:TI 21)) (clobber (reg:TI 43))
10759 (clobber (reg:TI 22)) (clobber (reg:TI 44))
10760 (clobber (reg:TI 23)) (clobber (reg:TI 45))
10761 (clobber (reg:TI 24)) (clobber (reg:TI 46))
10762 (clobber (reg:TI 25)) (clobber (reg:TI 47))
10763 (clobber (reg:TI 26)) (clobber (reg:TI 48))
10764 (clobber (reg:TI 27)) (clobber (reg:TI 49))
10765 (clobber (reg:TI 28)) (clobber (reg:TI 50))
10766 (clobber (reg:TI 29)) (clobber (reg:TI 51))
10767 (clobber (reg:TI 30)) (clobber (reg:TI 52))
10768 (clobber (reg:TI 31)) (clobber (reg:TI 53))]
10769 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10770 ; not supposed to be used for immediates (see genpreds.c).
10771 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10773 [(set_attr "op_type" "SIL")])
10775 (define_insn "tbegin_1"
10776 [(set (reg:CCRAW CC_REGNUM)
10777 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10779 (set (match_operand:BLK 1 "memory_operand" "=Q")
10780 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10781 (clobber (reg:DF 16))
10782 (clobber (reg:DF 17))
10783 (clobber (reg:DF 18))
10784 (clobber (reg:DF 19))
10785 (clobber (reg:DF 20))
10786 (clobber (reg:DF 21))
10787 (clobber (reg:DF 22))
10788 (clobber (reg:DF 23))
10789 (clobber (reg:DF 24))
10790 (clobber (reg:DF 25))
10791 (clobber (reg:DF 26))
10792 (clobber (reg:DF 27))
10793 (clobber (reg:DF 28))
10794 (clobber (reg:DF 29))
10795 (clobber (reg:DF 30))
10796 (clobber (reg:DF 31))]
10797 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10798 ; not supposed to be used for immediates (see genpreds.c).
10799 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10801 [(set_attr "op_type" "SIL")])
10803 ; Same as above but without the FPR clobbers
10804 (define_insn "tbegin_nofloat_1"
10805 [(set (reg:CCRAW CC_REGNUM)
10806 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10808 (set (match_operand:BLK 1 "memory_operand" "=Q")
10809 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10810 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10812 [(set_attr "op_type" "SIL")])
10815 ; Constrained transaction begin
10817 (define_expand "tbeginc"
10818 [(set (reg:CCRAW CC_REGNUM)
10819 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10824 (define_insn "*tbeginc_1"
10825 [(set (reg:CCRAW CC_REGNUM)
10826 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10828 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10830 [(set_attr "op_type" "SIL")])
10834 (define_expand "tend"
10835 [(set (reg:CCRAW CC_REGNUM)
10836 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10837 (set (match_operand:SI 0 "register_operand" "")
10838 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10842 (define_insn "*tend_1"
10843 [(set (reg:CCRAW CC_REGNUM)
10844 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10847 [(set_attr "op_type" "S")])
10849 ; Transaction abort
10851 (define_expand "tabort"
10852 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
10854 "TARGET_HTM && operands != NULL"
10856 if (CONST_INT_P (operands[0])
10857 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10859 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10860 ". Values in range 0 through 255 are reserved.",
10861 INTVAL (operands[0]));
10866 (define_insn "*tabort_1"
10867 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
10869 "TARGET_HTM && operands != NULL"
10871 [(set_attr "op_type" "S")])
10873 (define_insn "*tabort_1_plus"
10874 [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a")
10875 (match_operand:SI 1 "const_int_operand" "J"))]
10877 "TARGET_HTM && operands != NULL
10878 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
10880 [(set_attr "op_type" "S")])
10882 ; Transaction extract nesting depth
10884 (define_insn "etnd"
10885 [(set (match_operand:SI 0 "register_operand" "=d")
10886 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10889 [(set_attr "op_type" "RRE")])
10891 ; Non-transactional store
10893 (define_insn "ntstg"
10894 [(set (match_operand:DI 0 "memory_operand" "=T")
10895 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10899 [(set_attr "op_type" "RXY")])
10901 ; Transaction perform processor assist
10903 (define_expand "tx_assist"
10904 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10905 (reg:SI GPR0_REGNUM)
10911 (define_insn "*ppa"
10912 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10913 (match_operand:SI 1 "register_operand" "d")
10914 (match_operand 2 "const_int_operand" "I")]
10916 "TARGET_HTM && INTVAL (operands[2]) < 16"
10918 [(set_attr "op_type" "RRF")])
10921 ; Set and get floating point control register
10923 (define_insn "sfpc"
10924 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10926 "TARGET_HARD_FLOAT"
10929 (define_insn "efpc"
10930 [(set (match_operand:SI 0 "register_operand" "=d")
10931 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10932 "TARGET_HARD_FLOAT"
10936 ; Load count to block boundary
10938 (define_insn "lcbb"
10939 [(set (match_operand:SI 0 "register_operand" "=d")
10940 (unspec:SI [(match_operand 1 "address_operand" "ZR")
10941 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
10942 (clobber (reg:CC CC_REGNUM))]
10945 [(set_attr "op_type" "VRX")])
10947 ; Handle -fsplit-stack.
10949 (define_expand "split_stack_prologue"
10953 s390_expand_split_stack_prologue ();
10957 ;; If there are operand 0 bytes available on the stack, jump to
10960 (define_expand "split_stack_space_check"
10961 [(set (pc) (if_then_else
10962 (ltu (minus (reg 15)
10963 (match_operand 0 "register_operand"))
10964 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
10965 (label_ref (match_operand 1))
10969 /* Offset from thread pointer to __private_ss. */
10970 int psso = TARGET_64BIT ? 0x38 : 0x20;
10971 rtx tp = s390_get_thread_pointer ();
10972 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
10973 rtx reg = gen_reg_rtx (Pmode);
10976 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
10978 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
10979 cc = s390_emit_compare (GT, reg, guard);
10980 s390_emit_jump (operands[1], cc);
10985 ;; __morestack parameter block for split stack prologue. Parameters are:
10986 ;; parameter block label, label to be called by __morestack, frame size,
10987 ;; stack parameter size.
10989 (define_insn "split_stack_data"
10990 [(unspec_volatile [(match_operand 0 "" "X")
10991 (match_operand 1 "" "X")
10992 (match_operand 2 "const_int_operand" "X")
10993 (match_operand 3 "const_int_operand" "X")]
10994 UNSPECV_SPLIT_STACK_DATA)]
10997 switch_to_section (targetm.asm_out.function_rodata_section
10998 (current_function_decl));
11001 output_asm_insn (".align\t8", operands);
11003 output_asm_insn (".align\t4", operands);
11004 (*targetm.asm_out.internal_label) (asm_out_file, "L",
11005 CODE_LABEL_NUMBER (operands[0]));
11008 output_asm_insn (".quad\t%2", operands);
11009 output_asm_insn (".quad\t%3", operands);
11010 output_asm_insn (".quad\t%1-%0", operands);
11014 output_asm_insn (".long\t%2", operands);
11015 output_asm_insn (".long\t%3", operands);
11016 output_asm_insn (".long\t%1-%0", operands);
11019 switch_to_section (current_function_section ());
11022 [(set_attr "length" "0")])
11025 ;; A jg with minimal fuss for use in split stack prologue.
11027 (define_expand "split_stack_call"
11028 [(match_operand 0 "bras_sym_operand" "X")
11029 (match_operand 1 "" "")]
11033 emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11035 emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11039 (define_insn "split_stack_call_<mode>"
11040 [(set (pc) (label_ref (match_operand 1 "" "")))
11041 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11043 UNSPECV_SPLIT_STACK_CALL))]
11046 [(set_attr "op_type" "RIL")
11047 (set_attr "type" "branch")])
11049 ;; Also a conditional one.
11051 (define_expand "split_stack_cond_call"
11052 [(match_operand 0 "bras_sym_operand" "X")
11053 (match_operand 1 "" "")
11054 (match_operand 2 "" "")]
11058 emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11060 emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11064 (define_insn "split_stack_cond_call_<mode>"
11067 (match_operand 1 "" "")
11068 (label_ref (match_operand 2 "" ""))
11070 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11072 UNSPECV_SPLIT_STACK_CALL))]
11075 [(set_attr "op_type" "RIL")
11076 (set_attr "type" "branch")])