1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
48 ;; Define an insn type attribute. This is used in function unit delay
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
58 (define_attr "atype" "reg,mem"
61 ;; Generic pipeline function unit.
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
117 ;; Operand type. Used to default length attribute values
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
143 ;; Define attributes for `asm' insns.
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
159 ; CCZ1 -> CCA/CCU/CCS/CCT
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
167 ;;- Compare instructions.
170 (define_expand "cmpdi"
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
182 (define_expand "cmpsi"
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
194 ;(define_expand "cmphi"
196 ; (compare:CC (match_operand:HI 0 "register_operand" "")
197 ; (match_operand:HI 1 "general_operand" "")))]
201 ; s390_compare_op0 = operands[0];
202 ; s390_compare_op1 = operands[1];
206 ;(define_expand "cmpqi"
208 ; (compare:CC (match_operand:QI 0 "register_operand" "")
209 ; (match_operand:QI 1 "general_operand" "")))]
213 ; s390_compare_op0 = operands[0];
214 ; s390_compare_op1 = operands[1];
218 (define_expand "cmpdf"
220 (compare:CC (match_operand:DF 0 "register_operand" "")
221 (match_operand:DF 1 "general_operand" "")))]
225 s390_compare_op0 = operands[0];
226 s390_compare_op1 = operands[1];
230 (define_expand "cmpsf"
232 (compare:CC (match_operand:SF 0 "register_operand" "")
233 (match_operand:SF 1 "general_operand" "")))]
237 s390_compare_op0 = operands[0];
238 s390_compare_op1 = operands[1];
245 (define_insn "*cmpdi_tm2"
247 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
248 (match_operand:DI 1 "const_int_operand" "n")
249 (match_operand:DI 2 "const_int_operand" "n"))
251 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
252 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
253 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
254 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
255 == INTVAL (operands[2]) >> 4"
258 int part = INTVAL (operands[2]) >> 4;
259 int block = (1 << INTVAL (operands[1])) - 1;
260 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
262 operands[2] = GEN_INT (block << shift);
266 case 0: return \"tmhh\\t%0,%x2\";
267 case 1: return \"tmhl\\t%0,%x2\";
268 case 2: return \"tmlh\\t%0,%x2\";
269 case 3: return \"tmll\\t%0,%x2\";
273 [(set_attr "op_type" "RI")])
275 (define_insn "*cmpdi_tm_reg"
277 (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
278 (match_operand:DI 1 "immediate_operand" "n"))
280 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
281 && s390_single_hi (operands[1], DImode, 0) >= 0"
284 int part = s390_single_hi (operands[1], DImode, 0);
285 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
289 case 0: return \"tmhh\\t%0,%x1\";
290 case 1: return \"tmhl\\t%0,%x1\";
291 case 2: return \"tmlh\\t%0,%x1\";
292 case 3: return \"tmll\\t%0,%x1\";
296 [(set_attr "op_type" "RI")])
298 (define_insn "*cmpdi_tm_mem"
300 (compare (and:DI (match_operand:DI 0 "s_operand" "%Qo")
301 (match_operand:DI 1 "immediate_operand" "n"))
303 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
304 && s390_single_qi (operands[1], DImode, 0) >= 0"
307 int part = s390_single_qi (operands[1], DImode, 0);
308 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
310 operands[0] = gen_rtx_MEM (QImode,
311 plus_constant (XEXP (operands[0], 0), part));
312 return \"tm\\t%0,%b1\";
314 [(set_attr "op_type" "SI")
315 (set_attr "atype" "mem")])
319 (compare (match_operand:DI 0 "register_operand" "d")
320 (match_operand:DI 1 "const0_operand" "")))
321 (set (match_operand:DI 2 "register_operand" "=d")
323 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
325 [(set_attr "op_type" "RRE")])
327 (define_insn "*cmpdi_ccs_0_64"
329 (compare (match_operand:DI 0 "register_operand" "d")
330 (match_operand:DI 1 "const0_operand" "")))]
331 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
333 [(set_attr "op_type" "RRE")])
335 (define_insn "*cmpdi_ccs_0_31"
337 (compare (match_operand:DI 0 "register_operand" "d")
338 (match_operand:DI 1 "const0_operand" "")))]
339 "s390_match_ccmode(insn, CCSmode)"
341 [(set_attr "op_type" "RS")])
343 (define_insn "*cmpdi_ccs"
345 (compare (match_operand:DI 0 "register_operand" "d,d,d")
346 (match_operand:DI 1 "general_operand" "d,K,m")))]
347 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
352 [(set_attr "op_type" "RRE,RI,RXE")
353 (set_attr "atype" "reg,reg,mem")])
355 (define_insn "*cmpdi_ccu"
357 (compare (match_operand:DI 0 "register_operand" "d,d")
358 (match_operand:DI 1 "general_operand" "d,m")))]
359 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
363 [(set_attr "op_type" "RRE,RXE")
364 (set_attr "atype" "reg,mem")])
366 (define_insn "*cmpdi_ccu_mem"
368 (compare (match_operand:DI 0 "s_operand" "oQ")
369 (match_operand:DI 1 "s_imm_operand" "oQ")))]
370 "s390_match_ccmode(insn, CCUmode)"
371 "clc\\t%O0(8,%R0),%1"
372 [(set_attr "op_type" "SS")
373 (set_attr "atype" "mem")])
377 (define_insn "*cmpsi_tm2"
379 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
380 (match_operand:SI 1 "const_int_operand" "n")
381 (match_operand:SI 2 "const_int_operand" "n"))
383 "s390_match_ccmode(insn, CCTmode)
384 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
385 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
386 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
387 == INTVAL (operands[2]) >> 4"
390 int part = INTVAL (operands[2]) >> 4;
391 int block = (1 << INTVAL (operands[1])) - 1;
392 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
394 operands[2] = GEN_INT (block << shift);
398 case 0: return \"tmh\\t%0,%x2\";
399 case 1: return \"tml\\t%0,%x2\";
403 [(set_attr "op_type" "RI")])
405 (define_insn "*cmpsi_tm_reg"
407 (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
408 (match_operand:SI 1 "immediate_operand" "n"))
410 "s390_match_ccmode(insn, CCTmode)
411 && s390_single_hi (operands[1], SImode, 0) >= 0"
414 int part = s390_single_hi (operands[1], SImode, 0);
415 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
419 case 0: return \"tmh\\t%0,%x1\";
420 case 1: return \"tml\\t%0,%x1\";
424 [(set_attr "op_type" "RI")])
426 (define_insn "*cmpsi_tm_mem"
428 (compare (and:SI (match_operand:SI 0 "s_operand" "%Qo")
429 (match_operand:SI 1 "immediate_operand" "n"))
431 "s390_match_ccmode(insn, CCTmode)
432 && s390_single_qi (operands[1], SImode, 0) >= 0"
435 int part = s390_single_qi (operands[1], SImode, 0);
436 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
438 operands[0] = gen_rtx_MEM (QImode,
439 plus_constant (XEXP (operands[0], 0), part));
440 return \"tm\\t%0,%b1\";
442 [(set_attr "op_type" "SI")
443 (set_attr "atype" "mem")])
447 (compare (match_operand:SI 0 "register_operand" "d")
448 (match_operand:SI 1 "const0_operand" "")))
449 (set (match_operand:SI 2 "register_operand" "=d")
451 "s390_match_ccmode(insn, CCSmode)"
453 [(set_attr "op_type" "RR")])
455 (define_insn "*icm15"
457 (compare (match_operand:SI 0 "s_operand" "Qo")
458 (match_operand:SI 1 "const0_operand" "")))
459 (set (match_operand:SI 2 "register_operand" "=d")
461 "s390_match_ccmode(insn, CCSmode)"
463 [(set_attr "op_type" "RS")
464 (set_attr "atype" "mem")])
466 (define_insn "*icm15_cconly"
468 (compare (match_operand:SI 0 "s_operand" "Qo")
469 (match_operand:SI 1 "const0_operand" "")))
470 (clobber (match_scratch:SI 2 "=d"))]
471 "s390_match_ccmode(insn, CCSmode)"
473 [(set_attr "op_type" "RS")
474 (set_attr "atype" "mem")])
476 (define_insn "*cmpsi_ccs_0"
478 (compare (match_operand:SI 0 "register_operand" "d")
479 (match_operand:SI 1 "const0_operand" "")))]
480 "s390_match_ccmode(insn, CCSmode)"
482 [(set_attr "op_type" "RR")])
484 (define_insn "*cmpsidi_ccs"
486 (compare (match_operand:SI 0 "register_operand" "d")
487 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
488 "s390_match_ccmode(insn, CCSmode)"
490 [(set_attr "op_type" "RR")
491 (set_attr "atype" "mem")])
493 (define_insn "*cmpsi_ccs"
495 (compare (match_operand:SI 0 "register_operand" "d,d,d")
496 (match_operand:SI 1 "general_operand" "d,K,m")))]
497 "s390_match_ccmode(insn, CCSmode)"
502 [(set_attr "op_type" "RR,RI,RX")
503 (set_attr "atype" "reg,reg,mem")])
505 (define_insn "*cmpsi_ccu"
507 (compare (match_operand:SI 0 "register_operand" "d,d")
508 (match_operand:SI 1 "general_operand" "d,m")))]
509 "s390_match_ccmode(insn, CCUmode)"
513 [(set_attr "op_type" "RR,RX")
514 (set_attr "atype" "reg,mem")])
516 (define_insn "*cmpsi_ccu_mem"
518 (compare (match_operand:SI 0 "s_operand" "oQ")
519 (match_operand:SI 1 "s_imm_operand" "oQ")))]
520 "s390_match_ccmode(insn, CCUmode)"
521 "clc\\t%O0(4,%R0),%1"
522 [(set_attr "op_type" "SS")
523 (set_attr "atype" "mem")])
528 (define_insn "*cmphi_tm_sub"
530 (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0)
531 (match_operand:SI 1 "immediate_operand" "n"))
533 "s390_match_ccmode(insn, CCTmode)
534 && s390_single_qi (operands[1], HImode, 0) >= 0"
537 int part = s390_single_qi (operands[1], HImode, 0);
538 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
540 operands[0] = gen_rtx_MEM (QImode,
541 plus_constant (XEXP (operands[0], 0), part));
542 return \"tm\\t%0,%b1\";
544 [(set_attr "op_type" "SI")
545 (set_attr "atype" "mem")])
549 (compare (match_operand:HI 0 "s_operand" "Qo")
550 (match_operand:HI 1 "const0_operand" "")))
551 (set (match_operand:HI 2 "register_operand" "=d")
553 "s390_match_ccmode(insn, CCSmode)"
555 [(set_attr "op_type" "RS")
556 (set_attr "atype" "mem")])
558 (define_insn "*cmphi_cct_0"
560 (compare (match_operand:HI 0 "register_operand" "d")
561 (match_operand:HI 1 "const0_operand" "")))]
562 "s390_match_ccmode(insn, CCTmode)"
564 [(set_attr "op_type" "RX")])
566 (define_insn "*cmphi_ccs_0"
568 (compare (match_operand:HI 0 "s_operand" "Qo")
569 (match_operand:HI 1 "const0_operand" "")))
570 (clobber (match_scratch:HI 2 "=d"))]
571 "s390_match_ccmode(insn, CCSmode)"
573 [(set_attr "op_type" "RS")
574 (set_attr "atype" "mem")])
576 (define_insn "*cmphi_ccu"
578 (compare (match_operand:HI 0 "register_operand" "d")
579 (match_operand:HI 1 "s_imm_operand" "Qo")))]
580 "s390_match_ccmode(insn, CCUmode)"
582 [(set_attr "op_type" "RS")
583 (set_attr "atype" "mem")])
585 (define_insn "*cmphi_ccu_mem"
587 (compare (match_operand:HI 0 "s_operand" "oQ")
588 (match_operand:HI 1 "s_imm_operand" "oQ")))]
589 "s390_match_ccmode(insn, CCUmode)"
590 "clc\\t%O0(2,%R0),%1"
591 [(set_attr "op_type" "SS")
592 (set_attr "atype" "mem")])
597 (define_insn "*cmpqi_tm2"
599 (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo")
600 (match_operand:SI 1 "const_int_operand" "n")
601 (match_operand:SI 2 "const_int_operand" "n"))
603 "s390_match_ccmode(insn, CCTmode)
604 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
605 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
608 int block = (1 << INTVAL (operands[1])) - 1;
609 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
611 operands[2] = GEN_INT (block << shift);
612 return \"tm\\t%0,%b2\";
614 [(set_attr "op_type" "SI")
615 (set_attr "atype" "mem")])
617 (define_insn "*cmpqi_tm"
619 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q")
620 (match_operand:QI 1 "immediate_operand" "n,n"))
622 "s390_match_ccmode(insn, CCTmode)"
626 [(set_attr "op_type" "RI,SI")
627 (set_attr "atype" "reg,mem")])
629 (define_insn "*cmpqi_tm_sub"
631 (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0)
632 (match_operand:SI 1 "immediate_operand" "n"))
634 "s390_match_ccmode(insn, CCTmode)"
636 [(set_attr "op_type" "SI")
637 (set_attr "atype" "mem")])
641 (compare (match_operand:QI 0 "s_operand" "Qo")
642 (match_operand:QI 1 "const0_operand" "")))
643 (set (match_operand:QI 2 "register_operand" "=d")
645 "s390_match_ccmode(insn, CCSmode)"
647 [(set_attr "op_type" "RS")
648 (set_attr "atype" "mem")])
652 (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
653 (match_operand:QI 1 "immediate_operand" "")))
655 "s390_match_ccmode(insn, CCTmode) &&
656 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
658 [(set_attr "op_type" "RI")
659 (set_attr "atype" "mem")])
661 (define_insn "*cmpqi_cct_0"
663 (compare (match_operand:QI 0 "register_operand" "d")
664 (match_operand:QI 1 "const0_operand" "")))]
665 "s390_match_ccmode(insn, CCTmode)"
667 [(set_attr "op_type" "RI")])
669 (define_insn "*cmpqi_ccs_0"
671 (compare (match_operand:QI 0 "s_operand" "Qo")
672 (match_operand:QI 1 "const0_operand" "")))
673 (clobber (match_scratch:QI 2 "=d"))]
674 "s390_match_ccmode(insn, CCSmode)"
676 [(set_attr "op_type" "RS")
677 (set_attr "atype" "mem")])
679 (define_insn "*cmpqi_ccu_0"
681 (compare (match_operand:QI 0 "s_operand" "Qo")
682 (match_operand:QI 1 "const0_operand" "")))]
683 "s390_match_ccmode(insn, CCUmode)"
685 [(set_attr "op_type" "SI")
686 (set_attr "atype" "mem")])
688 (define_insn "*cmpqi_ccu"
690 (compare (match_operand:QI 0 "register_operand" "d")
691 (match_operand:QI 1 "s_imm_operand" "Qo")))]
692 "s390_match_ccmode(insn, CCUmode)"
694 [(set_attr "op_type" "RS")
695 (set_attr "atype" "mem")])
697 (define_insn "*cmpqi_ccu_immed"
699 (compare (match_operand:QI 0 "s_operand" "Qo")
700 (match_operand:QI 1 "const_int_operand" "n")))]
701 "s390_match_ccmode(insn, CCUmode) &&
702 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
704 [(set_attr "op_type" "SI")
705 (set_attr "atype" "mem")])
707 (define_insn "*cmpqi_ccu_mem"
709 (compare (match_operand:QI 0 "s_operand" "oQ")
710 (match_operand:QI 1 "s_imm_operand" "oQ")))]
711 "s390_match_ccmode(insn, CCUmode)"
712 "clc\\t%O0(1,%R0),%1"
713 [(set_attr "op_type" "SS")
714 (set_attr "atype" "mem")])
719 (define_insn "*cmpdf_ccs_0"
721 (compare (match_operand:DF 0 "register_operand" "f")
722 (match_operand:DF 1 "const0_operand" "")))]
723 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
725 [(set_attr "op_type" "RRE")])
727 (define_insn "*cmpdf_ccs_0_ibm"
729 (compare (match_operand:DF 0 "register_operand" "f")
730 (match_operand:DF 1 "const0_operand" "")))]
731 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
733 [(set_attr "op_type" "RR")])
735 (define_insn "*cmpdf_ccs"
737 (compare (match_operand:DF 0 "register_operand" "f,f")
738 (match_operand:DF 1 "general_operand" "f,m")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
743 [(set_attr "op_type" "RRE,RXE")
744 (set_attr "atype" "reg,mem")])
746 (define_insn "*cmpdf_ccs_ibm"
748 (compare (match_operand:DF 0 "register_operand" "f,f")
749 (match_operand:DF 1 "general_operand" "f,m")))]
750 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
754 [(set_attr "op_type" "RR,RX")
755 (set_attr "atype" "reg,mem")])
760 (define_insn "*cmpsf_ccs_0"
762 (compare (match_operand:SF 0 "register_operand" "f")
763 (match_operand:SF 1 "const0_operand" "")))]
764 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
766 [(set_attr "op_type" "RRE")])
768 (define_insn "*cmpsf_ccs_0_ibm"
770 (compare (match_operand:SF 0 "register_operand" "f")
771 (match_operand:SF 1 "const0_operand" "")))]
772 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
774 [(set_attr "op_type" "RR")])
776 (define_insn "*cmpsf_ccs"
778 (compare (match_operand:SF 0 "register_operand" "f,f")
779 (match_operand:SF 1 "general_operand" "f,m")))]
780 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
784 [(set_attr "op_type" "RRE,RXE")
785 (set_attr "atype" "reg,mem")])
787 (define_insn "*cmpsf_ccs"
789 (compare (match_operand:SF 0 "register_operand" "f,f")
790 (match_operand:SF 1 "general_operand" "f,m")))]
791 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
795 [(set_attr "op_type" "RR,RX")
796 (set_attr "atype" "reg,mem")])
800 ;;- Move instructions.
804 ; movti instruction pattern(s).
807 (define_insn "*movti_ss"
808 [(set (match_operand:TI 0 "s_operand" "=Qo")
809 (match_operand:TI 1 "s_imm_operand" "Qo"))]
811 "mvc\\t%O0(16,%R0),%1"
812 [(set_attr "op_type" "SS")
813 (set_attr "atype" "mem")])
816 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m")
817 (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))]
824 [(set_attr "op_type" "RSE,RSE,NN,NN")
825 (set_attr "atype" "mem")])
828 [(set (match_operand:TI 0 "nonimmediate_operand" "")
829 (match_operand:TI 1 "general_operand" ""))]
830 "TARGET_64BIT && reload_completed
831 && !s_operand (operands[0], VOIDmode)
832 && !s_operand (operands[1], VOIDmode)
833 && (register_operand (operands[0], VOIDmode)
834 || register_operand (operands[1], VOIDmode))
835 && (!register_operand (operands[0], VOIDmode)
836 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
838 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
840 [(set (match_dup 2) (match_dup 4))
841 (set (match_dup 3) (match_dup 5))]
844 if (!register_operand (operands[0], VOIDmode)
845 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
848 operands[2] = operand_subword (operands[0], 0, 0, TImode);
849 operands[3] = operand_subword (operands[0], 1, 0, TImode);
850 operands[4] = operand_subword (operands[1], 0, 0, TImode);
851 operands[5] = operand_subword (operands[1], 1, 0, TImode);
855 operands[2] = operand_subword (operands[0], 1, 0, TImode);
856 operands[3] = operand_subword (operands[0], 0, 0, TImode);
857 operands[4] = operand_subword (operands[1], 1, 0, TImode);
858 operands[5] = operand_subword (operands[1], 0, 0, TImode);
863 [(set (match_operand:TI 0 "register_operand" "")
864 (match_operand:TI 1 "memory_operand" ""))]
865 "TARGET_64BIT && reload_completed
866 && !s_operand (operands[1], VOIDmode)"
867 [(set (match_dup 2) (match_dup 3))
868 (set (match_dup 0) (mem:TI (match_dup 2)))]
869 "operands[2] = operand_subword (operands[0], 1, 0, TImode);
870 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
873 ; movdi instruction pattern(s).
876 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
877 ;; move to get the address of the symbolic object from the GOT.
879 (define_expand "movdi"
880 [(set (match_operand:DI 0 "general_operand" "")
881 (match_operand:DI 1 "general_operand" ""))]
885 /* Handle PIC symbolic constants. */
886 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
887 emit_pic_move (operands, DImode);
889 /* During and after reload, we need to force constants
890 to the literal pool ourselves, if necessary. */
891 if ((reload_in_progress || reload_completed)
892 && CONSTANT_P (operands[1])
893 && (!legitimate_reload_constant_p (operands[1])
894 || fp_operand (operands[0], VOIDmode)))
895 operands[1] = force_const_mem (DImode, operands[1]);
898 (define_insn "*movdi_lhi"
899 [(set (match_operand:DI 0 "register_operand" "=d")
900 (match_operand:DI 1 "immediate_operand" "K"))]
902 && GET_CODE (operands[1]) == CONST_INT
903 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
904 && !fp_operand (operands[0], VOIDmode)"
906 [(set_attr "op_type" "RI")
907 (set_attr "atype" "reg")])
909 (define_insn "*movdi_lli"
910 [(set (match_operand:DI 0 "register_operand" "=d")
911 (match_operand:DI 1 "immediate_operand" "n"))]
912 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
913 && !fp_operand (operands[0], VOIDmode)"
916 int part = s390_single_hi (operands[1], DImode, 0);
917 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
921 case 0: return \"llihh\\t%0,%x1\";
922 case 1: return \"llihl\\t%0,%x1\";
923 case 2: return \"llilh\\t%0,%x1\";
924 case 3: return \"llill\\t%0,%x1\";
928 [(set_attr "op_type" "RI")
929 (set_attr "atype" "reg")])
931 (define_insn "*movdi_larl"
932 [(set (match_operand:DI 0 "register_operand" "=d")
933 (match_operand:DI 1 "larl_operand" "X"))]
935 && !fp_operand (operands[0], VOIDmode)"
937 [(set_attr "op_type" "RIL")
938 (set_attr "atype" "reg")
939 (set_attr "type" "la")])
941 (define_insn "*movdi_ss"
942 [(set (match_operand:DI 0 "s_operand" "=Qo")
943 (match_operand:DI 1 "s_imm_operand" "Qo"))]
945 "mvc\\t%O0(8,%R0),%1"
946 [(set_attr "op_type" "SS")
947 (set_attr "atype" "mem")])
949 (define_insn "*movdi_64"
950 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m")
951 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f"))]
960 [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX")
961 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
963 (define_insn "*movdi_31"
964 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m")
965 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f"))]
975 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX")
976 (set_attr "atype" "mem,mem,*,*,reg,mem,mem")])
979 [(set (match_operand:DI 0 "nonimmediate_operand" "")
980 (match_operand:DI 1 "general_operand" ""))]
981 "!TARGET_64BIT && reload_completed
982 && !fp_operand (operands[0], VOIDmode)
983 && !fp_operand (operands[1], VOIDmode)
984 && !s_operand (operands[0], VOIDmode)
985 && !s_operand (operands[1], VOIDmode)
986 && (register_operand (operands[0], VOIDmode)
987 || register_operand (operands[1], VOIDmode))
988 && (!register_operand (operands[0], VOIDmode)
989 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
991 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
993 [(set (match_dup 2) (match_dup 4))
994 (set (match_dup 3) (match_dup 5))]
997 if (!register_operand (operands[0], VOIDmode)
998 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1001 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1002 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1003 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1004 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1008 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1009 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1010 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1011 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1016 [(set (match_operand:DI 0 "register_operand" "")
1017 (match_operand:DI 1 "memory_operand" ""))]
1018 "!TARGET_64BIT && reload_completed
1019 && !fp_operand (operands[0], VOIDmode)
1020 && !fp_operand (operands[1], VOIDmode)
1021 && !s_operand (operands[1], VOIDmode)"
1022 [(set (match_dup 2) (match_dup 3))
1023 (set (match_dup 0) (mem:DI (match_dup 2)))]
1024 "operands[2] = operand_subword (operands[0], 1, 0, DImode);
1025 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1028 ; movsi instruction pattern(s).
1031 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1032 ;; move to get the address of the symbolic object from the GOT.
1034 (define_expand "movsi"
1035 [(set (match_operand:SI 0 "general_operand" "")
1036 (match_operand:SI 1 "general_operand" ""))]
1040 /* Handle PIC symbolic constants. */
1041 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1042 emit_pic_move (operands, SImode);
1044 /* expr.c tries to load an effective address using
1045 force_reg. This fails because we don't have a
1046 generic load_address pattern. Convert the move
1047 to a proper arithmetic operation instead, unless
1048 it is guaranteed to be OK. */
1049 if (GET_CODE (operands[1]) == PLUS
1050 && !legitimate_la_operand_p (operands[1]))
1052 operands[1] = force_operand (operands[1], operands[0]);
1053 if (operands[1] == operands[0])
1057 /* During and after reload, we need to force constants
1058 to the literal pool ourselves, if necessary. */
1059 if ((reload_in_progress || reload_completed)
1060 && CONSTANT_P (operands[1])
1061 && (!legitimate_reload_constant_p (operands[1])
1062 || fp_operand (operands[0], VOIDmode)))
1063 operands[1] = force_const_mem (SImode, operands[1]);
1066 (define_insn "*movsi_lhi"
1067 [(set (match_operand:SI 0 "register_operand" "=d")
1068 (match_operand:SI 1 "immediate_operand" "K"))]
1069 "GET_CODE (operands[1]) == CONST_INT
1070 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1071 && !fp_operand (operands[0], VOIDmode)"
1073 [(set_attr "op_type" "RI")])
1075 (define_insn "*movsi_lli"
1076 [(set (match_operand:SI 0 "register_operand" "=d")
1077 (match_operand:SI 1 "immediate_operand" "n"))]
1078 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1079 && !fp_operand (operands[0], VOIDmode)"
1082 int part = s390_single_hi (operands[1], SImode, 0);
1083 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1087 case 0: return \"llilh\\t%0,%x1\";
1088 case 1: return \"llill\\t%0,%x1\";
1092 [(set_attr "op_type" "RI")])
1094 (define_insn "*movsi_ss"
1095 [(set (match_operand:SI 0 "s_operand" "=Qo")
1096 (match_operand:SI 1 "s_imm_operand" "Qo"))]
1098 "mvc\\t%O0(4,%R0),%1"
1099 [(set_attr "op_type" "SS")
1100 (set_attr "atype" "mem")])
1102 (define_insn "*movsi"
1103 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m")
1104 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f"))]
1113 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1114 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1118 ; movhi instruction pattern(s).
1121 (define_insn "movhi"
1122 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
1123 (match_operand:HI 1 "general_operand" "d,n,m,d"))]
1130 [(set_attr "op_type" "RR,RI,RX,RX")
1131 (set_attr "atype" "reg,reg,mem,mem")])
1135 ; movqi instruction pattern(s).
1138 (define_insn "movqi_64"
1139 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1140 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1148 [(set_attr "op_type" "RR,RI,RXE,RX,SI")
1149 (set_attr "atype" "reg,reg,mem,mem,mem")])
1152 (define_insn "movqi"
1153 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1154 (match_operand:QI 1 "general_operand" "d,n,m,d,n"))]
1162 [(set_attr "op_type" "RR,RI,RX,RX,SI")
1163 (set_attr "atype" "reg,reg,mem,mem,mem")])
1167 ; moveqstrictqi instruction pattern(s).
1170 (define_insn "*movstrictqi"
1171 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1172 (match_operand:QI 1 "memory_operand" "m"))]
1175 [(set_attr "op_type" "RX")
1176 (set_attr "atype" "mem")])
1179 ; movstricthi instruction pattern(s).
1182 (define_insn "*movstricthi"
1183 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1184 (match_operand:HI 1 "s_imm_operand" "Qo"))
1185 (clobber (reg:CC 33))]
1188 [(set_attr "op_type" "RS")
1189 (set_attr "atype" "mem")])
1193 ; movstrictsi instruction pattern(s).
1196 (define_insn "movestrictsi"
1197 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1198 (match_operand:SI 1 "general_operand" "d,m"))]
1203 [(set_attr "op_type" "RR,RS")
1204 (set_attr "atype" "reg,mem")])
1208 ; movdf instruction pattern(s).
1211 (define_expand "movdf"
1212 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1213 (match_operand:DF 1 "general_operand" ""))]
1217 /* During and after reload, we need to force constants
1218 to the literal pool ourselves, if necessary. */
1219 if ((reload_in_progress || reload_completed)
1220 && CONSTANT_P (operands[1]))
1221 operands[1] = force_const_mem (DFmode, operands[1]);
1224 (define_insn "*movdf_ss"
1225 [(set (match_operand:DF 0 "s_operand" "=Qo")
1226 (match_operand:DF 1 "s_imm_operand" "Qo"))]
1228 "mvc\\t%O0(8,%R0),%1"
1229 [(set_attr "op_type" "SS")
1230 (set_attr "atype" "mem")])
1232 (define_insn "*movdf_64"
1233 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1234 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d"))]
1243 [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE")
1244 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1246 (define_insn "*movdf_31"
1247 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m")
1248 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d"))]
1258 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN")
1259 (set_attr "atype" "reg,mem,mem,mem,mem,*,*")])
1262 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1263 (match_operand:DF 1 "general_operand" ""))]
1264 "!TARGET_64BIT && reload_completed
1265 && !fp_operand (operands[0], VOIDmode)
1266 && !fp_operand (operands[1], VOIDmode)
1267 && !s_operand (operands[0], VOIDmode)
1268 && !s_operand (operands[1], VOIDmode)
1269 && (register_operand (operands[0], VOIDmode)
1270 || register_operand (operands[1], VOIDmode))
1271 && (!register_operand (operands[0], VOIDmode)
1272 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1274 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1276 [(set (match_dup 2) (match_dup 4))
1277 (set (match_dup 3) (match_dup 5))]
1280 if (!register_operand (operands[0], VOIDmode)
1281 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1284 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1285 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1286 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1287 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1291 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1292 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1293 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1294 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1299 [(set (match_operand:DF 0 "register_operand" "")
1300 (match_operand:DF 1 "memory_operand" ""))]
1301 "!TARGET_64BIT && reload_completed
1302 && !fp_operand (operands[0], VOIDmode)
1303 && !fp_operand (operands[1], VOIDmode)
1304 && !s_operand (operands[1], VOIDmode)"
1305 [(set (match_dup 2) (match_dup 3))
1306 (set (match_dup 0) (mem:DI (match_dup 2)))]
1307 "operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1308 operands[3] = legitimize_la_operand (XEXP (operands[1], 0));")
1311 ; movsf instruction pattern(s).
1314 (define_expand "movsf"
1315 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1316 (match_operand:SF 1 "general_operand" ""))]
1320 /* During and after reload, we need to force constants
1321 to the literal pool ourselves, if necessary. */
1322 if ((reload_in_progress || reload_completed)
1323 && CONSTANT_P (operands[1]))
1324 operands[1] = force_const_mem (SFmode, operands[1]);
1327 (define_insn "*movsf_ss"
1328 [(set (match_operand:SF 0 "s_operand" "=Qo")
1329 (match_operand:SF 1 "s_imm_operand" "Qo"))]
1331 "mvc\\t%O0(4,%R0),%1"
1332 [(set_attr "op_type" "SS")
1333 (set_attr "atype" "mem")])
1335 (define_insn "*movsf"
1336 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m")
1337 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d"))]
1346 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX")
1347 (set_attr "atype" "reg,mem,mem,reg,mem,mem")])
1350 ; load_multiple pattern(s).
1353 (define_expand "load_multiple"
1354 [(match_par_dup 3 [(set (match_operand 0 "" "")
1355 (match_operand 1 "" ""))
1356 (use (match_operand 2 "" ""))])]
1365 /* Support only loading a constant number of fixed-point registers from
1366 memory and only bother with this if more than two */
1367 if (GET_CODE (operands[2]) != CONST_INT
1368 || INTVAL (operands[2]) < 2
1369 || INTVAL (operands[2]) > 16
1370 || GET_CODE (operands[1]) != MEM
1371 || GET_CODE (operands[0]) != REG
1372 || REGNO (operands[0]) >= 16)
1375 count = INTVAL (operands[2]);
1376 regno = REGNO (operands[0]);
1378 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1381 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1383 from = XEXP (operands[1], 0);
1386 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1387 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1388 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1390 from = XEXP (XEXP (operands[1], 0), 0);
1391 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1396 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1401 from = force_reg (Pmode, XEXP (operands[1], 0));
1405 for (i = 0; i < count; i++)
1406 XVECEXP (operands[3], 0, i)
1407 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1408 change_address (operands[1], Pmode,
1409 plus_constant (from,
1410 off + i * UNITS_PER_WORD)));
1413 (define_insn "*load_multiple_di"
1414 [(match_parallel 0 "load_multiple_operation"
1415 [(set (match_operand:DI 1 "register_operand" "=r")
1416 (match_operand:DI 2 "s_operand" "oQ"))])]
1420 int words = XVECLEN (operands[0], 0);
1422 if (XVECLEN (operands[0], 0) == 1)
1423 return \"lg\\t%1,0(%2)\";
1425 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1426 return \"lmg\\t%1,%0,%2\";
1428 [(set_attr "op_type" "RXE")
1429 (set_attr "atype" "mem")
1430 (set_attr "type" "lm")])
1432 (define_insn "*load_multiple_si"
1433 [(match_parallel 0 "load_multiple_operation"
1434 [(set (match_operand:SI 1 "register_operand" "=r")
1435 (match_operand:SI 2 "s_operand" "oQ"))])]
1439 int words = XVECLEN (operands[0], 0);
1441 if (XVECLEN (operands[0], 0) == 1)
1442 return \"l\\t%1,0(%2)\";
1444 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1445 return \"lm\\t%1,%0,%2\";
1447 [(set_attr "op_type" "RXE")
1448 (set_attr "atype" "mem")
1449 (set_attr "type" "lm")])
1452 ; store multiple pattern(s).
1455 (define_expand "store_multiple"
1456 [(match_par_dup 3 [(set (match_operand 0 "" "")
1457 (match_operand 1 "" ""))
1458 (use (match_operand 2 "" ""))])]
1467 /* Support only storing a constant number of fixed-point registers to
1468 memory and only bother with this if more than two. */
1469 if (GET_CODE (operands[2]) != CONST_INT
1470 || INTVAL (operands[2]) < 2
1471 || INTVAL (operands[2]) > 16
1472 || GET_CODE (operands[0]) != MEM
1473 || GET_CODE (operands[1]) != REG
1474 || REGNO (operands[1]) >= 16)
1477 count = INTVAL (operands[2]);
1478 regno = REGNO (operands[1]);
1480 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1484 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1486 to = XEXP (operands[0], 0);
1489 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1490 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1491 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1493 to = XEXP (XEXP (operands[0], 0), 0);
1494 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1499 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1504 to = force_reg (Pmode, XEXP (operands[0], 0));
1508 for (i = 0; i < count; i++)
1509 XVECEXP (operands[3], 0, i)
1510 = gen_rtx_SET (VOIDmode,
1511 change_address (operands[0], Pmode,
1513 off + i * UNITS_PER_WORD)),
1514 gen_rtx_REG (Pmode, regno + i));
1517 (define_insn "*store_multiple_di"
1518 [(match_parallel 0 "store_multiple_operation"
1519 [(set (match_operand:DI 1 "s_operand" "=oQ")
1520 (match_operand:DI 2 "register_operand" "r"))])]
1524 int words = XVECLEN (operands[0], 0);
1526 if (XVECLEN (operands[0], 0) == 1)
1527 return \"stg\\t%1,0(%2)\";
1529 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1530 return \"stmg\\t%2,%0,%1\";
1532 [(set_attr "op_type" "RXE")
1533 (set_attr "atype" "mem")
1534 (set_attr "type" "stm")])
1537 (define_insn "*store_multiple_si"
1538 [(match_parallel 0 "store_multiple_operation"
1539 [(set (match_operand:SI 1 "s_operand" "=oQ")
1540 (match_operand:SI 2 "register_operand" "r"))])]
1544 int words = XVECLEN (operands[0], 0);
1546 if (XVECLEN (operands[0], 0) == 1)
1547 return \"st\\t%1,0(%2)\";
1549 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1550 return \"stm\\t%2,%0,%1\";
1552 [(set_attr "op_type" "RXE")
1553 (set_attr "atype" "mem")
1554 (set_attr "type" "stm")])
1557 ;; String instructions.
1561 ; movstrdi instruction pattern(s).
1564 (define_expand "movstrdi"
1565 [(set (match_operand:BLK 0 "general_operand" "")
1566 (match_operand:BLK 1 "general_operand" ""))
1567 (use (match_operand:DI 2 "general_operand" ""))
1568 (match_operand 3 "" "")]
1574 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1575 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1577 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1579 operands[0] = change_address (operands[0], VOIDmode, addr0);
1580 operands[1] = change_address (operands[1], VOIDmode, addr1);
1581 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1583 emit_insn (gen_movstrdi_short (operands[0], operands[1], operands[2]));
1590 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1591 rtx reg0 = gen_reg_rtx (TImode);
1592 rtx reg1 = gen_reg_rtx (TImode);
1593 rtx len = operands[2];
1595 if (! CONSTANT_P (len))
1596 len = force_reg (DImode, len);
1598 /* Load up the address+length pairs. */
1600 emit_move_insn (gen_highpart (DImode, reg0), addr0);
1601 emit_move_insn (gen_lowpart (DImode, reg0), len);
1603 emit_move_insn (gen_highpart (DImode, reg1), addr1);
1604 emit_move_insn (gen_lowpart (DImode, reg1), len);
1607 emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1));
1612 rtx label1 = gen_label_rtx ();
1613 rtx label2 = gen_label_rtx ();
1614 rtx reg0, reg1, len, blocks;
1616 reg0 = gen_reg_rtx (DImode);
1617 reg1 = gen_reg_rtx (DImode);
1618 len = gen_reg_rtx (DImode);
1619 blocks = gen_reg_rtx (DImode);
1621 emit_move_insn (len, operands[2]);
1622 emit_insn (gen_cmpdi (len, const0_rtx));
1623 emit_jump_insn (gen_beq (label1));
1624 emit_move_insn (reg0, addr0);
1625 emit_move_insn (reg1, addr1);
1626 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1627 emit_insn (gen_ashrdi3 (blocks, len, GEN_INT (8)));
1628 emit_insn (gen_cmpdi (blocks, const0_rtx));
1629 emit_jump_insn (gen_beq (label2));
1630 emit_insn (gen_movstrdi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1631 emit_label (label2);
1632 operands[0] = change_address (operands[0], VOIDmode, reg0);
1633 operands[1] = change_address (operands[1], VOIDmode, reg1);
1634 emit_insn (gen_movstrdi_short (operands[0], operands[1], len));
1635 emit_label (label1);
1642 ; movstrsi instruction pattern(s).
1645 (define_expand "movstrsi"
1646 [(set (match_operand:BLK 0 "general_operand" "")
1647 (match_operand:BLK 1 "general_operand" ""))
1648 (use (match_operand:SI 2 "general_operand" ""))
1649 (match_operand 3 "" "")]
1653 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1654 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1656 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1658 operands[0] = change_address (operands[0], VOIDmode, addr0);
1659 operands[1] = change_address (operands[1], VOIDmode, addr1);
1660 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1662 emit_insn (gen_movstrsi_short (operands[0], operands[1], operands[2]));
1669 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1670 rtx reg0 = gen_reg_rtx (DImode);
1671 rtx reg1 = gen_reg_rtx (DImode);
1672 rtx len = operands[2];
1675 if (! CONSTANT_P (len))
1676 len = force_reg (SImode, len);
1678 /* Load up the address+length pairs. */
1680 emit_move_insn (gen_highpart (SImode, reg0), addr0);
1681 emit_move_insn (gen_lowpart (SImode, reg0), len);
1683 emit_move_insn (gen_highpart (SImode, reg1), addr1);
1684 emit_move_insn (gen_lowpart (SImode, reg1), len);
1687 emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1));
1692 rtx label1 = gen_label_rtx ();
1693 rtx label2 = gen_label_rtx ();
1694 rtx reg0, reg1, len, blocks;
1696 reg0 = gen_reg_rtx (SImode);
1697 reg1 = gen_reg_rtx (SImode);
1698 len = gen_reg_rtx (SImode);
1699 blocks = gen_reg_rtx (SImode);
1701 emit_move_insn (len, operands[2]);
1702 emit_insn (gen_cmpsi (len, const0_rtx));
1703 emit_jump_insn (gen_beq (label1));
1704 emit_move_insn (reg0, addr0);
1705 emit_move_insn (reg1, addr1);
1706 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1707 emit_insn (gen_ashrsi3 (blocks, len, GEN_INT (8)));
1708 emit_insn (gen_cmpsi (blocks, const0_rtx));
1709 emit_jump_insn (gen_beq (label2));
1710 emit_insn (gen_movstrsi_long (reg0, reg1, reg0, reg1, blocks, blocks));
1711 emit_label (label2);
1712 operands[0] = change_address (operands[0], VOIDmode, reg0);
1713 operands[1] = change_address (operands[1], VOIDmode, reg1);
1714 emit_insn (gen_movstrsi_short (operands[0], operands[1], len));
1715 emit_label (label1);
1721 ; Move a block that is up to 256 bytes in length.
1722 ; The block length is taken as (operands[2] % 256) + 1.
1724 (define_insn "movstrdi_short"
1725 [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
1726 (match_operand:BLK 1 "s_operand" "oQ,oQ"))
1727 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1728 (clobber (match_scratch:DI 3 "=X,&a"))]
1732 switch (which_alternative)
1735 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1738 output_asm_insn (\"bras\\t%3,.+10\", operands);
1739 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1740 return \"ex\\t%2,0(%3)\";
1746 [(set_attr "op_type" "SS,NN")
1747 (set_attr "atype" "mem,mem")
1748 (set_attr "length" "*,14")])
1750 (define_insn "movstrsi_short"
1751 [(set (match_operand:BLK 0 "s_operand" "=oQ,oQ")
1752 (match_operand:BLK 1 "s_operand" "oQ,oQ"))
1753 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1754 (clobber (match_scratch:SI 3 "=X,&a"))]
1758 switch (which_alternative)
1761 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1764 output_asm_insn (\"bras\\t%3,.+10\", operands);
1765 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1766 return \"ex\\t%2,0(%3)\";
1772 [(set_attr "op_type" "SS,NN")
1773 (set_attr "atype" "mem,mem")
1774 (set_attr "length" "*,14")])
1776 ; Move a block that is a multiple of 256 bytes in length
1778 (define_insn "movstrdi_long"
1779 [(set (match_operand:DI 4 "register_operand" "=d")
1781 (set (match_operand:DI 0 "register_operand" "=a")
1782 (plus:DI (match_operand:DI 2 "register_operand" "0")
1783 (ashift:DI (match_operand:DI 5 "register_operand" "4")
1785 (set (match_operand:DI 1 "register_operand" "=a")
1786 (plus:DI (match_operand:DI 3 "register_operand" "1")
1787 (ashift:DI (match_dup 5) (const_int 8))))
1788 (set (mem:BLK (match_dup 2))
1789 (mem:BLK (match_dup 3)))
1790 (use (match_dup 5))]
1794 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1795 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1796 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1797 return \"brct\\t%4,.-14\";
1799 [(set_attr "op_type" "NN")
1800 (set_attr "atype" "mem")
1801 (set_attr "length" "18")])
1803 (define_insn "movstrsi_long"
1804 [(set (match_operand:SI 4 "register_operand" "=d")
1806 (set (match_operand:SI 0 "register_operand" "=a")
1807 (plus:SI (match_operand:SI 2 "register_operand" "0")
1808 (ashift:SI (match_operand:SI 5 "register_operand" "4")
1810 (set (match_operand:SI 1 "register_operand" "=a")
1811 (plus:SI (match_operand:SI 3 "register_operand" "1")
1812 (ashift:SI (match_dup 5) (const_int 8))))
1813 (set (mem:BLK (match_dup 2))
1814 (mem:BLK (match_dup 3)))
1815 (use (match_dup 5))]
1819 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands);
1820 output_asm_insn (\"la\\t%0,256(%0)\", operands);
1821 output_asm_insn (\"la\\t%1,256(%1)\", operands);
1822 return \"brct\\t%4,.-14\";
1824 [(set_attr "op_type" "NN")
1825 (set_attr "atype" "mem")
1826 (set_attr "length" "18")])
1828 ; Move a block that is larger than 255 bytes in length.
1830 (define_insn "movstrdi_64"
1831 [(set (match_operand:TI 0 "register_operand" "=d")
1832 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1833 (lshiftrt:TI (match_dup 2) (const_int 64)))
1835 (set (match_operand:TI 1 "register_operand" "=d")
1836 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1837 (lshiftrt:TI (match_dup 3) (const_int 64)))
1839 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1840 (mem:BLK (subreg:DI (match_dup 3) 0)))
1841 (clobber (reg:CC 33))]
1843 "mvcle\\t%0,%1,0\;jo\\t.-4"
1844 [(set_attr "op_type" "NN")
1845 (set_attr "atype" "mem")
1846 (set_attr "length" "8")])
1848 (define_insn "movstrsi_31"
1849 [(set (match_operand:DI 0 "register_operand" "=d")
1850 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1851 (lshiftrt:DI (match_dup 2) (const_int 32)))
1853 (set (match_operand:DI 1 "register_operand" "=d")
1854 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1855 (lshiftrt:DI (match_dup 3) (const_int 32)))
1857 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1858 (mem:BLK (subreg:SI (match_dup 3) 0)))
1859 (clobber (reg:CC 33))]
1861 "mvcle\\t%0,%1,0\;jo\\t.-4"
1862 [(set_attr "op_type" "NN")
1863 (set_attr "atype" "mem")
1864 (set_attr "length" "8")])
1867 ; clrstrdi instruction pattern(s).
1870 (define_expand "clrstrdi"
1871 [(set (match_operand:BLK 0 "general_operand" "")
1873 (use (match_operand:DI 1 "general_operand" ""))
1874 (match_operand 2 "" "")]
1878 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1880 operands[0] = change_address (operands[0], VOIDmode, addr);
1882 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1884 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1889 rtx reg0 = gen_reg_rtx (TImode);
1890 rtx reg1 = gen_reg_rtx (TImode);
1891 rtx len = operands[1];
1893 if (! CONSTANT_P (len))
1894 len = force_reg (DImode, len);
1896 /* Load up the address+length pairs. */
1898 emit_move_insn (gen_highpart (DImode, reg0), addr);
1899 emit_move_insn (gen_lowpart (DImode, reg0), len);
1901 emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx);
1904 emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0));
1910 ; clrstrsi instruction pattern(s).
1913 (define_expand "clrstrsi"
1914 [(set (match_operand:BLK 0 "general_operand" "")
1916 (use (match_operand:SI 1 "general_operand" ""))
1917 (match_operand 2 "" "")]
1921 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1923 operands[0] = change_address (operands[0], VOIDmode, addr);
1925 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1927 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1932 rtx reg0 = gen_reg_rtx (DImode);
1933 rtx reg1 = gen_reg_rtx (DImode);
1934 rtx len = operands[1];
1936 if (! CONSTANT_P (len))
1937 len = force_reg (SImode, len);
1939 /* Load up the address+length pairs. */
1941 emit_move_insn (gen_highpart (SImode, reg0), addr);
1942 emit_move_insn (gen_lowpart (SImode, reg0), len);
1944 emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx);
1947 emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0));
1952 ; Clear memory with length less than 256 bytes
1954 (define_insn "clrstrsico"
1955 [(set (match_operand:BLK 0 "s_operand" "=Qo")
1957 (use (match_operand 1 "immediate_operand" "I"))
1958 (clobber (reg:CC 33))]
1960 "xc\\t%O0(%1,%R0),%0"
1961 [(set_attr "op_type" "RS")
1962 (set_attr "type" "cs")
1963 (set_attr "atype" "mem")])
1965 ; Clear memory with length greater 256 bytes or lenght not constant
1967 (define_insn "clrstrsi_64"
1968 [(set (match_operand:TI 0 "register_operand" "=d")
1969 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1970 (lshiftrt:TI (match_dup 2) (const_int 64)))
1972 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1974 (use (match_operand:TI 1 "register_operand" "d"))
1975 (clobber (reg:CC 33))]
1977 "mvcle\\t%0,%1,0\;jo\\t.-4"
1978 [(set_attr "op_type" "NN")
1979 (set_attr "atype" "mem")
1980 (set_attr "type" "vs")
1981 (set_attr "length" "8")])
1983 (define_insn "clrstrsi_31"
1984 [(set (match_operand:DI 0 "register_operand" "=d")
1985 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1986 (lshiftrt:DI (match_dup 2) (const_int 32)))
1988 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1990 (use (match_operand:DI 1 "register_operand" "d"))
1991 (clobber (reg:CC 33))]
1993 "mvcle\\t%0,%1,0\;jo\\t.-4"
1994 [(set_attr "op_type" "NN")
1995 (set_attr "atype" "mem")
1996 (set_attr "type" "vs")
1997 (set_attr "length" "8")])
2000 ; cmpstrdi instruction pattern(s).
2003 (define_expand "cmpstrdi"
2004 [(set (match_operand:DI 0 "register_operand" "")
2005 (compare:DI (match_operand:BLK 1 "s_operand" "")
2006 (match_operand:BLK 2 "s_operand" "") ) )
2007 (use (match_operand:DI 3 "general_operand" ""))
2008 (use (match_operand:DI 4 "" ""))]
2014 /* for pre/post increment */
2015 operands[1] = protect_from_queue (operands[1], 0);
2016 operands[2] = protect_from_queue (operands[2], 0);
2017 operands[3] = protect_from_queue (operands[3], 0);
2019 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2020 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2022 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2024 if (INTVAL (operands[3]) == 0) {
2025 emit_move_insn (operands[0], operands[3]);
2029 operands[1] = change_address (operands[1], VOIDmode, addr0);
2030 operands[2] = change_address (operands[2], VOIDmode, addr1);
2032 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2033 emit_insn (gen_cmpint_di (operands[0]));
2038 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2039 rtx reg0 = gen_reg_rtx (TImode);
2040 rtx reg1 = gen_reg_rtx (TImode);
2041 rtx len = operands[3];
2043 if (! CONSTANT_P (len))
2044 len = force_reg (DImode, len);
2046 /* Load up the address+length pairs. */
2047 emit_move_insn (gen_highpart (DImode, reg0), addr0);
2048 emit_move_insn (gen_lowpart (DImode, reg0), len);
2050 emit_move_insn (gen_highpart (DImode, reg1), addr1);
2051 emit_move_insn (gen_lowpart (DImode, reg1), len);
2054 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2055 emit_insn (gen_cmpint_di (operands[0]));
2061 ; cmpstrsi instruction pattern(s).
2064 (define_expand "cmpstrsi"
2065 [(set (match_operand:SI 0 "register_operand" "")
2066 (compare:SI (match_operand:BLK 1 "s_operand" "")
2067 (match_operand:BLK 2 "s_operand" "") ) )
2068 (use (match_operand:SI 3 "general_operand" ""))
2069 (use (match_operand:SI 4 "" ""))]
2075 /* for pre/post increment */
2076 operands[1] = protect_from_queue (operands[1], 0);
2077 operands[2] = protect_from_queue (operands[2], 0);
2078 operands[3] = protect_from_queue (operands[3], 0);
2080 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
2081 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
2083 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
2085 if (INTVAL (operands[3]) == 0) {
2086 emit_move_insn (operands[0], operands[3]);
2090 operands[1] = change_address (operands[1], VOIDmode, addr0);
2091 operands[2] = change_address (operands[2], VOIDmode, addr1);
2093 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
2094 emit_insn (gen_cmpint_si (operands[0]));
2099 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
2101 rtx len = operands[3];
2105 reg0 = gen_reg_rtx (TImode);
2106 reg1 = gen_reg_rtx (TImode);
2110 reg0 = gen_reg_rtx (DImode);
2111 reg1 = gen_reg_rtx (DImode);
2114 if (! CONSTANT_P (len))
2115 len = force_reg (Pmode, len);
2117 /* Load up the address+length pairs. */
2118 emit_move_insn (gen_highpart (Pmode, reg0), addr0);
2119 emit_move_insn (gen_lowpart (Pmode, reg0), len);
2121 emit_move_insn (gen_highpart (Pmode, reg1), addr1);
2122 emit_move_insn (gen_lowpart (Pmode, reg1), len);
2126 emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1));
2128 emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1));
2130 emit_insn (gen_cmpint_si (operands[0]));
2135 ; Compare a block that is less than 256 bytes in length.
2137 (define_insn "cmpstr_const"
2139 (compare:CCS (match_operand:BLK 0 "s_operand" "oQ")
2140 (match_operand:BLK 1 "s_operand" "oQ")))
2141 (use (match_operand 2 "immediate_operand" "I"))]
2142 "(unsigned) INTVAL (operands[2]) < 256"
2143 "clc\\t%O0(%c2,%R0),%1"
2144 [(set_attr "op_type" "SS")
2145 (set_attr "atype" "mem")
2146 (set_attr "type" "cs")])
2148 ; Compare a block that is larger than 255 bytes in length.
2150 (define_insn "cmpstr_64"
2151 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2152 (clobber (match_operand:TI 1 "register_operand" "=d"))
2154 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2155 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2157 (use (match_dup 3))]
2160 [(set_attr "op_type" "RR")
2161 (set_attr "atype" "mem")
2162 (set_attr "type" "vs")])
2164 (define_insn "cmpstr_31"
2165 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2166 (clobber (match_operand:DI 1 "register_operand" "=d"))
2168 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2169 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2171 (use (match_dup 3))]
2174 [(set_attr "op_type" "RR")
2175 (set_attr "atype" "mem")
2176 (set_attr "type" "vs")])
2178 ; Convert condition code to integer in range (-1, 0, 1)
2180 (define_insn "cmpint_si"
2181 [(set (match_operand:SI 0 "register_operand" "=d")
2182 (compare:SI (reg:CCS 33) (const_int 0)))]
2186 output_asm_insn (\"lhi\\t%0,1\", operands);
2187 output_asm_insn (\"jh\\t.+12\", operands);
2188 output_asm_insn (\"jl\\t.+6\", operands);
2189 output_asm_insn (\"sr\\t%0,%0\", operands);
2190 return \"lcr\\t%0,%0\";
2192 [(set_attr "op_type" "NN")
2193 (set_attr "length" "16")
2194 (set_attr "atype" "reg")
2195 (set_attr "type" "other")])
2197 (define_insn "cmpint_di"
2198 [(set (match_operand:DI 0 "register_operand" "=d")
2199 (compare:DI (reg:CCS 33) (const_int 0)))]
2203 output_asm_insn (\"lghi\\t%0,1\", operands);
2204 output_asm_insn (\"jh\\t.+12\", operands);
2205 output_asm_insn (\"jl\\t.+6\", operands);
2206 output_asm_insn (\"sgr\\t%0,%0\", operands);
2207 return \"lcgr\\t%0,%0\";
2209 [(set_attr "op_type" "NN")
2210 (set_attr "length" "22")
2211 (set_attr "atype" "reg")
2212 (set_attr "type" "other")])
2216 ;;- Conversion instructions.
2219 (define_insn "*sethighqisi"
2220 [(set (match_operand:SI 0 "register_operand" "=d")
2221 (unspec:SI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2222 (clobber (reg:CC 33))]
2225 [(set_attr "op_type" "RS")
2226 (set_attr "atype" "mem")])
2228 (define_insn "*sethighhisi"
2229 [(set (match_operand:SI 0 "register_operand" "=d")
2230 (unspec:SI [(match_operand:HI 1 "s_operand" "Qo")] 10))
2231 (clobber (reg:CC 33))]
2234 [(set_attr "op_type" "RS")
2235 (set_attr "atype" "mem")])
2237 (define_insn "*sethighqidi_64"
2238 [(set (match_operand:DI 0 "register_operand" "=d")
2239 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2240 (clobber (reg:CC 33))]
2243 [(set_attr "op_type" "RSE")
2244 (set_attr "atype" "mem")])
2246 (define_insn "*sethighqidi_31"
2247 [(set (match_operand:DI 0 "register_operand" "=d")
2248 (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10))
2249 (clobber (reg:CC 33))]
2252 [(set_attr "op_type" "RS")
2253 (set_attr "atype" "mem")])
2256 [(set (match_operand:SI 0 "register_operand" "")
2257 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2258 (match_operand 2 "const_int_operand" "")
2260 "!TARGET_64BIT && !reload_completed
2261 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2263 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2264 (clobber (reg:CC 33))])
2265 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2268 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2269 operands[1] = change_address (operands[1], QImode, 0);
2273 [(set (match_operand:SI 0 "register_operand" "")
2274 (zero_extract:SI (match_operand:QI 1 "s_operand" "")
2275 (match_operand 2 "const_int_operand" "")
2277 "!TARGET_64BIT && !reload_completed
2278 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2280 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2281 (clobber (reg:CC 33))])
2282 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2285 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2286 operands[1] = change_address (operands[1], HImode, 0);
2290 ; extendsidi2 instruction pattern(s).
2293 (define_expand "extendsidi2"
2294 [(set (match_operand:DI 0 "register_operand" "")
2295 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2301 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2302 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2303 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2304 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2310 (define_insn "*extendsidi2"
2311 [(set (match_operand:DI 0 "register_operand" "=d,d")
2312 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2317 [(set_attr "op_type" "RRE,RXE")
2318 (set_attr "atype" "reg,mem")])
2321 ; extendhidi2 instruction pattern(s).
2324 (define_expand "extendhidi2"
2325 [(set (match_operand:DI 0 "register_operand" "")
2326 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2332 rtx tmp = gen_reg_rtx (SImode);
2333 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2334 emit_insn (gen_extendsidi2 (operands[0], tmp));
2339 operands[1] = gen_lowpart (DImode, operands[1]);
2340 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2341 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2347 (define_insn "*extendhidi2"
2348 [(set (match_operand:DI 0 "register_operand" "=d")
2349 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2352 [(set_attr "op_type" "RXE")
2353 (set_attr "atype" "mem")])
2356 ; extendqidi2 instruction pattern(s).
2359 (define_expand "extendqidi2"
2360 [(set (match_operand:DI 0 "register_operand" "")
2361 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2367 rtx tmp = gen_reg_rtx (SImode);
2368 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2369 emit_insn (gen_extendsidi2 (operands[0], tmp));
2374 operands[1] = gen_lowpart (DImode, operands[1]);
2375 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2376 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2383 [(set (match_operand:DI 0 "register_operand" "")
2384 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2385 "TARGET_64BIT && !reload_completed"
2387 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2388 (clobber (reg:CC 33))])
2390 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2391 (clobber (reg:CC 33))])]
2395 ; extendhisi2 instruction pattern(s).
2398 (define_expand "extendhisi2"
2399 [(set (match_operand:SI 0 "register_operand" "")
2400 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2404 operands[1] = gen_lowpart (SImode, operands[1]);
2405 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2406 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2411 (define_insn "*extendhisi2"
2412 [(set (match_operand:SI 0 "register_operand" "=d")
2413 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2416 [(set_attr "op_type" "RX")
2417 (set_attr "atype" "mem")])
2420 ; extendqisi2 instruction pattern(s).
2423 (define_expand "extendqisi2"
2424 [(set (match_operand:SI 0 "register_operand" "")
2425 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2429 operands[1] = gen_lowpart (SImode, operands[1]);
2430 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2431 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2437 [(set (match_operand:SI 0 "register_operand" "")
2438 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2441 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2442 (clobber (reg:CC 33))])
2444 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2445 (clobber (reg:CC 33))])]
2449 ; extendqihi2 instruction pattern(s).
2454 ; zero_extendsidi2 instruction pattern(s).
2457 (define_expand "zero_extendsidi2"
2458 [(set (match_operand:DI 0 "register_operand" "")
2459 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2465 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2466 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2467 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2473 (define_insn "*zero_extendsidi2"
2474 [(set (match_operand:DI 0 "register_operand" "=d,d")
2475 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2480 [(set_attr "op_type" "RRE,RXE")
2481 (set_attr "atype" "reg,mem")])
2484 ; zero_extendhidi2 instruction pattern(s).
2487 (define_expand "zero_extendhidi2"
2488 [(set (match_operand:DI 0 "register_operand" "")
2489 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2495 rtx tmp = gen_reg_rtx (SImode);
2496 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2497 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2502 operands[1] = gen_lowpart (DImode, operands[1]);
2503 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2504 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2510 (define_insn "*zero_extendhidi2"
2511 [(set (match_operand:DI 0 "register_operand" "=d")
2512 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2515 [(set_attr "op_type" "RXE")
2516 (set_attr "atype" "mem")])
2519 ; zero_extendqidi2 instruction pattern(s)
2522 (define_expand "zero_extendqidi2"
2523 [(set (match_operand:DI 0 "register_operand" "")
2524 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2530 rtx tmp = gen_reg_rtx (SImode);
2531 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2532 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2537 operands[1] = gen_lowpart (DImode, operands[1]);
2538 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2539 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2545 (define_insn "*zero_extendqidi2"
2546 [(set (match_operand:DI 0 "register_operand" "=d")
2547 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2550 [(set_attr "op_type" "RXE")
2551 (set_attr "atype" "mem")])
2554 ; zero_extendhisi2 instruction pattern(s).
2557 (define_expand "zero_extendhisi2"
2558 [(set (match_operand:SI 0 "register_operand" "")
2559 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2563 operands[1] = gen_lowpart (SImode, operands[1]);
2564 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2569 (define_insn "*zero_extendhisi2_64"
2570 [(set (match_operand:SI 0 "register_operand" "=d")
2571 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2574 [(set_attr "op_type" "RXE")
2575 (set_attr "atype" "mem")])
2578 ; zero_extendqisi2 instruction pattern(s).
2581 (define_expand "zero_extendqisi2"
2582 [(set (match_operand:SI 0 "register_operand" "")
2583 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2587 operands[1] = gen_lowpart (SImode, operands[1]);
2588 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2593 (define_insn "*zero_extendqisi2_64"
2594 [(set (match_operand:SI 0 "register_operand" "=d")
2595 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2598 [(set_attr "op_type" "RXE")
2599 (set_attr "atype" "mem")])
2602 ; zero_extendqihi2 instruction pattern(s).
2605 (define_expand "zero_extendqihi2"
2606 [(set (match_operand:HI 0 "register_operand" "")
2607 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2611 operands[1] = gen_lowpart (HImode, operands[1]);
2612 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2617 (define_insn "*zero_extendqihi2_64"
2618 [(set (match_operand:HI 0 "register_operand" "=d")
2619 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
2620 (clobber (reg:CC 33))]
2623 [(set_attr "op_type" "RXE")
2624 (set_attr "atype" "mem")])
2627 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2630 (define_expand "fixuns_truncdfdi2"
2631 [(set (match_operand:DI 0 "register_operand" "")
2632 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2633 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2636 rtx label1 = gen_label_rtx ();
2637 rtx label2 = gen_label_rtx ();
2638 rtx temp = gen_reg_rtx (DFmode);
2639 operands[1] = force_reg (DFmode, operands[1]);
2641 emit_insn (gen_cmpdf (operands[1],
2642 CONST_DOUBLE_FROM_REAL_VALUE (
2643 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2644 emit_jump_insn (gen_blt (label1));
2645 emit_insn (gen_subdf3 (temp, operands[1],
2646 CONST_DOUBLE_FROM_REAL_VALUE (
2647 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2648 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2651 emit_label (label1);
2652 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2653 emit_label (label2);
2657 (define_expand "fix_truncdfdi2"
2658 [(set (match_operand:DI 0 "register_operand" "")
2659 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2660 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2663 operands[1] = force_reg (DFmode, operands[1]);
2664 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2668 (define_insn "fix_truncdfdi2_ieee"
2669 [(set (match_operand:DI 0 "register_operand" "=d")
2670 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2671 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2672 (clobber (reg:CC 33))]
2673 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2675 [(set_attr "op_type" "RRE")
2676 (set_attr "type" "other")])
2679 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2682 (define_expand "fixuns_truncdfsi2"
2683 [(set (match_operand:SI 0 "register_operand" "")
2684 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2685 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2688 rtx label1 = gen_label_rtx ();
2689 rtx label2 = gen_label_rtx ();
2690 rtx temp = gen_reg_rtx (DFmode);
2692 operands[1] = force_reg (DFmode,operands[1]);
2693 emit_insn (gen_cmpdf (operands[1],
2694 CONST_DOUBLE_FROM_REAL_VALUE (
2695 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2696 emit_jump_insn (gen_blt (label1));
2697 emit_insn (gen_subdf3 (temp, operands[1],
2698 CONST_DOUBLE_FROM_REAL_VALUE (
2699 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2700 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2703 emit_label (label1);
2704 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2705 emit_label (label2);
2709 (define_expand "fix_truncdfsi2"
2710 [(set (match_operand:SI 0 "register_operand" "")
2711 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2715 if (TARGET_IBM_FLOAT)
2717 /* This is the algorithm from POP chapter A.5.7.2. */
2719 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2720 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2721 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2723 operands[1] = force_reg (DFmode, operands[1]);
2724 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2725 two31r, two32, temp));
2729 operands[1] = force_reg (DFmode, operands[1]);
2730 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2736 (define_insn "fix_truncdfsi2_ieee"
2737 [(set (match_operand:SI 0 "register_operand" "=d")
2738 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2739 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2740 (clobber (reg:CC 33))]
2741 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2743 [(set_attr "op_type" "RRE")
2744 (set_attr "type" "other" )])
2746 (define_insn "fix_truncdfsi2_ibm"
2747 [(set (match_operand:SI 0 "register_operand" "=d")
2748 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2749 (use (match_operand:DI 2 "immediate_operand" "m"))
2750 (use (match_operand:DI 3 "immediate_operand" "m"))
2751 (use (match_operand:BLK 4 "memory_operand" "m"))
2752 (clobber (reg:CC 33))]
2753 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2756 output_asm_insn (\"sd\\t%1,%2\", operands);
2757 output_asm_insn (\"aw\\t%1,%3\", operands);
2758 output_asm_insn (\"std\\t%1,%4\", operands);
2759 output_asm_insn (\"xi\\t%N4,128\", operands);
2760 return \"l\\t%0,%N4\";
2762 [(set_attr "op_type" "NN")
2763 (set_attr "type" "other")
2764 (set_attr "length" "20")])
2767 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2770 (define_expand "fixuns_truncsfdi2"
2771 [(set (match_operand:DI 0 "register_operand" "")
2772 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2773 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2776 rtx label1 = gen_label_rtx ();
2777 rtx label2 = gen_label_rtx ();
2778 rtx temp = gen_reg_rtx (SFmode);
2780 operands[1] = force_reg (SFmode, operands[1]);
2781 emit_insn (gen_cmpsf (operands[1],
2782 CONST_DOUBLE_FROM_REAL_VALUE (
2783 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2784 emit_jump_insn (gen_blt (label1));
2786 emit_insn (gen_subsf3 (temp, operands[1],
2787 CONST_DOUBLE_FROM_REAL_VALUE (
2788 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2789 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2792 emit_label (label1);
2793 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2794 emit_label (label2);
2798 (define_expand "fix_truncsfdi2"
2799 [(set (match_operand:DI 0 "register_operand" "")
2800 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2801 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2804 operands[1] = force_reg (SFmode, operands[1]);
2805 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2809 (define_insn "fix_truncsfdi2_ieee"
2810 [(set (match_operand:DI 0 "register_operand" "=d")
2811 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2812 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2813 (clobber (reg:CC 33))]
2814 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2816 [(set_attr "op_type" "RRE")
2817 (set_attr "type" "other")])
2820 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2823 (define_expand "fixuns_truncsfsi2"
2824 [(set (match_operand:SI 0 "register_operand" "")
2825 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2826 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2829 rtx label1 = gen_label_rtx ();
2830 rtx label2 = gen_label_rtx ();
2831 rtx temp = gen_reg_rtx (SFmode);
2833 operands[1] = force_reg (SFmode, operands[1]);
2834 emit_insn (gen_cmpsf (operands[1],
2835 CONST_DOUBLE_FROM_REAL_VALUE (
2836 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2837 emit_jump_insn (gen_blt (label1));
2838 emit_insn (gen_subsf3 (temp, operands[1],
2839 CONST_DOUBLE_FROM_REAL_VALUE (
2840 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2841 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2844 emit_label (label1);
2845 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2846 emit_label (label2);
2850 (define_expand "fix_truncsfsi2"
2851 [(set (match_operand:SI 0 "register_operand" "")
2852 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2856 if (TARGET_IBM_FLOAT)
2858 /* Convert to DFmode and then use the POP algorithm. */
2859 rtx temp = gen_reg_rtx (DFmode);
2860 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2861 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2865 operands[1] = force_reg (SFmode, operands[1]);
2866 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2872 (define_insn "fix_truncsfsi2_ieee"
2873 [(set (match_operand:SI 0 "register_operand" "=d")
2874 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2875 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2876 (clobber (reg:CC 33))]
2877 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2879 [(set_attr "op_type" "RRE")
2880 (set_attr "type" "other")])
2883 ; floatdidf2 instruction pattern(s).
2886 (define_insn "floatdidf2"
2887 [(set (match_operand:DF 0 "register_operand" "=f")
2888 (float:DF (match_operand:DI 1 "register_operand" "d")))
2889 (clobber (reg:CC 33))]
2890 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2892 [(set_attr "op_type" "RRE")
2893 (set_attr "type" "other" )])
2896 ; floatdisf2 instruction pattern(s).
2899 (define_insn "floatdisf2"
2900 [(set (match_operand:SF 0 "register_operand" "=f")
2901 (float:SF (match_operand:DI 1 "register_operand" "d")))
2902 (clobber (reg:CC 33))]
2903 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2905 [(set_attr "op_type" "RRE")
2906 (set_attr "type" "other" )])
2909 ; floatsidf2 instruction pattern(s).
2912 (define_expand "floatsidf2"
2914 [(set (match_operand:DF 0 "register_operand" "")
2915 (float:DF (match_operand:SI 1 "register_operand" "")))
2916 (clobber (reg:CC 33))])]
2920 if (TARGET_IBM_FLOAT)
2922 /* This is the algorithm from POP chapter A.5.7.1. */
2924 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2925 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2927 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2932 (define_insn "floatsidf2_ieee"
2933 [(set (match_operand:DF 0 "register_operand" "=f")
2934 (float:DF (match_operand:SI 1 "register_operand" "d")))
2935 (clobber (reg:CC 33))]
2936 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2938 [(set_attr "op_type" "RRE")
2939 (set_attr "type" "other" )])
2941 (define_insn "floatsidf2_ibm"
2942 [(set (match_operand:DF 0 "register_operand" "=f")
2943 (float:DF (match_operand:SI 1 "register_operand" "d")))
2944 (use (match_operand:DI 2 "immediate_operand" "m"))
2945 (use (match_operand:BLK 3 "memory_operand" "m"))
2946 (clobber (reg:CC 33))]
2947 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2950 output_asm_insn (\"st\\t%1,%N3\", operands);
2951 output_asm_insn (\"xi\\t%N3,128\", operands);
2952 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2953 output_asm_insn (\"ld\\t%0,%3\", operands);
2954 return \"sd\\t%0,%2\";
2956 [(set_attr "op_type" "NN")
2957 (set_attr "type" "other" )
2958 (set_attr "length" "20")])
2961 ; floatsisf2 instruction pattern(s).
2964 (define_expand "floatsisf2"
2966 [(set (match_operand:SF 0 "register_operand" "")
2967 (float:SF (match_operand:SI 1 "register_operand" "")))
2968 (clobber (reg:CC 33))])]
2972 if (TARGET_IBM_FLOAT)
2974 /* Use the POP algorithm to convert to DFmode and then truncate. */
2975 rtx temp = gen_reg_rtx (DFmode);
2976 emit_insn (gen_floatsidf2 (temp, operands[1]));
2977 emit_insn (gen_truncdfsf2 (operands[0], temp));
2982 (define_insn "floatsisf2_ieee"
2983 [(set (match_operand:SF 0 "register_operand" "=f")
2984 (float:SF (match_operand:SI 1 "register_operand" "d")))
2985 (clobber (reg:CC 33))]
2986 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2988 [(set_attr "op_type" "RRE")
2989 (set_attr "type" "other" )])
2992 ; truncdfsf2 instruction pattern(s).
2995 (define_expand "truncdfsf2"
2996 [(set (match_operand:SF 0 "register_operand" "")
2997 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
3001 (define_insn "truncdfsf2_ieee"
3002 [(set (match_operand:SF 0 "register_operand" "=f")
3003 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
3004 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3006 [(set_attr "op_type" "RRE")])
3008 (define_insn "truncdfsf2_ibm"
3009 [(set (match_operand:SF 0 "register_operand" "=f,f")
3010 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
3011 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3015 [(set_attr "op_type" "RR,RX")
3016 (set_attr "atype" "reg,mem")])
3019 ; extendsfdf2 instruction pattern(s).
3022 (define_expand "extendsfdf2"
3023 [(set (match_operand:DF 0 "register_operand" "")
3024 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3028 if (TARGET_IBM_FLOAT)
3030 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3035 (define_insn "extendsfdf2_ieee"
3036 [(set (match_operand:DF 0 "register_operand" "=f,f")
3037 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
3038 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3042 [(set_attr "op_type" "RRE,RXE")])
3044 (define_insn "extendsfdf2_ibm"
3045 [(set (match_operand:DF 0 "register_operand" "=f,f")
3046 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
3047 (clobber (reg:CC 33))]
3048 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3050 sdr\\t%0,%0\;ler\\t%0,%1
3051 sdr\\t%0,%0\;le\\t%0,%1"
3052 [(set_attr "op_type" "RRE,RXE")
3053 (set_attr "atype" "reg,mem")
3054 (set_attr "type" "o2,o2")])
3058 ;; ARITHMETRIC OPERATIONS
3060 ; arithmetric operations set the ConditionCode,
3061 ; because of unpredictable Bits in Register for Halfword and Byte
3062 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3065 ;;- Add instructions.
3069 ; adddi3 instruction pattern(s).
3072 (define_insn "addaddr_esame"
3073 [(set (match_operand:DI 0 "register_operand" "=a,a")
3074 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
3075 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
3076 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
3077 (REGNO (operands[1]) == BASE_REGISTER)) &&
3078 (GET_CODE (operands[2]) == REG ||
3079 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
3083 [(set_attr "op_type" "RX")
3084 (set_attr "atype" "mem")
3085 (set_attr "type" "la")])
3087 (define_insn "adddi3_64"
3088 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3089 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3090 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3091 (clobber (reg:CC 33))]
3097 [(set_attr "op_type" "RRE,RI,RXE")
3098 (set_attr "atype" "reg,reg,mem")])
3100 (define_insn "adddi3_31"
3101 [(set (match_operand:DI 0 "register_operand" "=d,d")
3102 (plus:DI (match_operand:DI 1 "register_operand" "0,0")
3103 (match_operand:DI 2 "general_operand" "d,m") ) )
3104 (clobber (reg:CC 33))]
3108 switch (which_alternative)
3110 case 0: /* d <- d */
3111 output_asm_insn (\"ar\\t%0,%2\", operands);
3112 output_asm_insn (\"alr\\t%N0,%N2\", operands);
3115 case 1: /* d <- m */
3116 output_asm_insn (\"a\\t%0,%2\", operands);
3117 output_asm_insn (\"al\\t%N0,%N2\", operands);
3124 output_asm_insn (\"brc\\t12,.+8\", operands);
3125 return \"ahi\\t%0,1\";
3127 [(set_attr "op_type" "NN,NN")
3128 (set_attr "atype" "reg,mem")
3129 (set_attr "type" "o2,o2")
3130 (set_attr "length" "12,16")])
3132 (define_expand "adddi3"
3133 [(set (match_operand:DI 0 "register_operand" "")
3134 (plus:DI (match_operand:DI 1 "register_operand" "")
3135 (match_operand:DI 2 "general_operand" "")))]
3140 emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2]));
3142 emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2]));
3146 (define_insn "*la_64"
3147 [(set (match_operand:DI 0 "register_operand" "=d")
3148 (match_operand:QI 1 "address_operand" "p"))]
3151 [(set_attr "op_type" "RX")
3152 (set_attr "atype" "mem")
3153 (set_attr "type" "la")])
3155 (define_expand "reload_indi"
3156 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3157 (match_operand:DI 1 "s390_plus_operand" "")
3158 (match_operand:TI 2 "register_operand" "=&a")])]
3162 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3168 ; addsi3 instruction pattern(s).
3171 (define_insn "*la_ccclobber"
3172 [(set (match_operand:SI 0 "register_operand" "=d")
3173 (match_operand:QI 1 "address_operand" "p"))
3174 (clobber (reg:CC 33))]
3175 "legitimate_la_operand_p (operands[1])"
3177 [(set_attr "op_type" "RX")
3178 (set_attr "atype" "mem")
3179 (set_attr "type" "la")])
3181 (define_insn "*addsi3_cc"
3183 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3184 (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3186 (set (match_operand:SI 0 "register_operand" "=d,d")
3187 (plus:SI (match_dup 1) (match_dup 2)))]
3188 "s390_match_ccmode(insn, CCLmode)"
3192 [(set_attr "op_type" "RR,RX")
3193 (set_attr "atype" "reg,mem")])
3195 (define_insn "*addsi3_cconly"
3197 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
3198 (match_operand:SI 2 "general_operand" "d,m"))
3200 (clobber (match_scratch:SI 0 "=d,d"))]
3201 "s390_match_ccmode(insn, CCLmode)"
3205 [(set_attr "op_type" "RR,RX")
3206 (set_attr "atype" "reg,mem")])
3208 (define_insn "*addsi3_cconly2"
3210 (compare (match_operand:SI 1 "register_operand" "%0,0")
3211 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3212 (clobber (match_scratch:SI 0 "=d,d"))]
3213 "s390_match_ccmode(insn, CCLmode)"
3217 [(set_attr "op_type" "RR,RX")
3218 (set_attr "atype" "reg,mem")])
3220 (define_insn "addsi3"
3221 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3222 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3223 (match_operand:SI 2 "general_operand" "d,K,m")))
3224 (clobber (reg:CC 33))]
3230 [(set_attr "op_type" "RR,RI,RX")
3231 (set_attr "atype" "reg,reg,mem")])
3233 (define_insn "*la_31"
3234 [(set (match_operand:SI 0 "register_operand" "=d")
3235 (match_operand:QI 1 "address_operand" "p"))]
3236 "legitimate_la_operand_p (operands[1])"
3238 [(set_attr "op_type" "RX")
3239 (set_attr "atype" "mem")
3240 (set_attr "type" "la")])
3242 (define_expand "reload_insi"
3243 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3244 (match_operand:SI 1 "s390_plus_operand" "")
3245 (match_operand:DI 2 "register_operand" "=&a")])]
3249 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3255 ; addhi3 instruction pattern(s).
3258 (define_insn "addhi3"
3259 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3260 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
3261 (match_operand:HI 2 "general_operand" "d,K,m")))
3262 (clobber (reg:CC 33))]
3268 [(set_attr "op_type" "RR,RI,RX")
3269 (set_attr "atype" "reg,reg,mem")])
3273 ; addqi3 instruction pattern(s).
3276 (define_insn "addqi3"
3277 [(set (match_operand:QI 0 "register_operand" "=d,d")
3278 (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
3279 (match_operand:QI 2 "general_operand" "a,n")))
3280 (clobber (reg:CC 33))]
3285 [(set_attr "op_type" "RX,RX")
3286 (set_attr "atype" "reg,mem")])
3290 ; adddf3 instruction pattern(s).
3293 (define_expand "adddf3"
3295 [(set (match_operand:DF 0 "register_operand" "=f,f")
3296 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3297 (match_operand:DF 2 "general_operand" "f,m")))
3298 (clobber (reg:CC 33))])]
3302 (define_insn "*adddf3"
3303 [(set (match_operand:DF 0 "register_operand" "=f,f")
3304 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3305 (match_operand:DF 2 "general_operand" "f,m")))
3306 (clobber (reg:CC 33))]
3307 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3311 [(set_attr "op_type" "RRE,RXE")
3312 (set_attr "atype" "reg,mem")])
3314 (define_insn "*adddf3_ibm"
3315 [(set (match_operand:DF 0 "register_operand" "=f,f")
3316 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3317 (match_operand:DF 2 "general_operand" "f,m")))
3318 (clobber (reg:CC 33))]
3319 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3323 [(set_attr "op_type" "RR,RX")
3324 (set_attr "atype" "reg,mem")])
3327 ; addsf3 instruction pattern(s).
3330 (define_expand "addsf3"
3332 [(set (match_operand:SF 0 "register_operand" "=f,f")
3333 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3334 (match_operand:SF 2 "general_operand" "f,m")))
3335 (clobber (reg:CC 33))])]
3339 (define_insn "*addsf3"
3340 [(set (match_operand:SF 0 "register_operand" "=f,f")
3341 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3342 (match_operand:SF 2 "general_operand" "f,m")))
3343 (clobber (reg:CC 33))]
3344 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3348 [(set_attr "op_type" "RRE,RXE")
3349 (set_attr "atype" "reg,mem")])
3351 (define_insn "*addsf3"
3352 [(set (match_operand:SF 0 "register_operand" "=f,f")
3353 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3354 (match_operand:SF 2 "general_operand" "f,m")))
3355 (clobber (reg:CC 33))]
3356 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3360 [(set_attr "op_type" "RR,RX")
3361 (set_attr "atype" "reg,mem")])
3365 ;;- Subtract instructions.
3369 ; subdi3 instruction pattern(s).
3372 (define_insn "*subdi3_64"
3373 [(set (match_operand:DI 0 "register_operand" "=d,d")
3374 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3375 (match_operand:DI 2 "general_operand" "d,m") ) )
3376 (clobber (reg:CC 33))]
3381 [(set_attr "op_type" "RRE,RRE")
3382 (set_attr "atype" "reg,mem")])
3384 (define_insn "subdi3"
3385 [(set (match_operand:DI 0 "register_operand" "=d,d")
3386 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3387 (match_operand:DI 2 "general_operand" "d,m")))
3388 (clobber (reg:CC 33))]
3392 switch (which_alternative)
3394 case 0: /* d <- d */
3395 output_asm_insn (\"sr\\t%0,%2\", operands);
3396 output_asm_insn (\"slr\\t%N0,%N2\", operands);
3398 case 1: /* d <- m */
3399 output_asm_insn (\"s\\t%0,%2\", operands);
3400 output_asm_insn (\"sl\\t%N0,%N2\", operands);
3407 output_asm_insn (\"brc\\t11,.+8\", operands);
3408 return \"ahi\\t%0,-1\";
3410 [(set_attr "op_type" "NN,NN")
3411 (set_attr "atype" "reg,mem")
3412 (set_attr "type" "other,other")
3413 (set_attr "length" "12,16")])
3416 ; subsi3 instruction pattern(s).
3419 (define_insn "*subsi3_cc"
3421 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3422 (match_operand:SI 2 "general_operand" "d,m"))
3424 (set (match_operand:SI 0 "register_operand" "=d,d")
3425 (minus:SI (match_dup 1) (match_dup 2)))]
3426 "s390_match_ccmode(insn, CCLmode)"
3430 [(set_attr "op_type" "RR,RX")
3431 (set_attr "atype" "reg,mem")])
3433 (define_insn "*subsi3_cconly"
3435 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3436 (match_operand:SI 2 "general_operand" "d,m"))
3438 (clobber (match_scratch:SI 0 "=d,d"))]
3439 "s390_match_ccmode(insn, CCLmode)"
3443 [(set_attr "op_type" "RR,RX")
3444 (set_attr "atype" "reg,mem")])
3446 (define_insn "subsi3"
3447 [(set (match_operand:SI 0 "register_operand" "=d,d")
3448 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3449 (match_operand:SI 2 "general_operand" "d,m")))
3450 (clobber (reg:CC 33))]
3455 [(set_attr "op_type" "RR,RX")
3456 (set_attr "atype" "reg,mem")])
3459 ; subhi3 instruction pattern(s).
3462 (define_insn "subhi3"
3463 [(set (match_operand:HI 0 "register_operand" "=d,d")
3464 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
3465 (match_operand:HI 2 "general_operand" "d,m")))
3466 (clobber (reg:CC 33))]
3471 [(set_attr "op_type" "RR,RX")
3472 (set_attr "atype" "reg,mem")])
3475 ; subqi3 instruction pattern(s).
3478 (define_insn "subqi3"
3479 [(set (match_operand:QI 0 "register_operand" "=d")
3480 (minus:QI (match_operand:QI 1 "register_operand" "0")
3481 (match_operand:QI 2 "register_operand" "d")))
3482 (clobber (reg:CC 33))]
3485 [(set_attr "op_type" "RR")])
3488 ; subdf3 instruction pattern(s).
3491 (define_expand "subdf3"
3493 [(set (match_operand:DF 0 "register_operand" "=f,f")
3494 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3495 (match_operand:DF 2 "general_operand" "f,m")))
3496 (clobber (reg:CC 33))])]
3500 (define_insn "*subdf3"
3501 [(set (match_operand:DF 0 "register_operand" "=f,f")
3502 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3503 (match_operand:DF 2 "general_operand" "f,m")))
3504 (clobber (reg:CC 33))]
3505 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3509 [(set_attr "op_type" "RRE,RXE")
3510 (set_attr "atype" "reg,mem")])
3512 (define_insn "*subdf3_ibm"
3513 [(set (match_operand:DF 0 "register_operand" "=f,f")
3514 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3515 (match_operand:DF 2 "general_operand" "f,m")))
3516 (clobber (reg:CC 33))]
3517 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3521 [(set_attr "op_type" "RR,RX")
3522 (set_attr "atype" "reg,mem")])
3525 ; subsf3 instruction pattern(s).
3528 (define_expand "subsf3"
3530 [(set (match_operand:SF 0 "register_operand" "=f,f")
3531 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3532 (match_operand:SF 2 "general_operand" "f,m")))
3533 (clobber (reg:CC 33))])]
3537 (define_insn "*subsf3"
3538 [(set (match_operand:SF 0 "register_operand" "=f,f")
3539 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3540 (match_operand:SF 2 "general_operand" "f,m")))
3541 (clobber (reg:CC 33))]
3542 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3546 [(set_attr "op_type" "RRE,RXE")
3547 (set_attr "atype" "reg,mem")])
3549 (define_insn "*subsf3_ibm"
3550 [(set (match_operand:SF 0 "register_operand" "=f,f")
3551 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3552 (match_operand:SF 2 "general_operand" "f,m")))
3553 (clobber (reg:CC 33))]
3554 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3558 [(set_attr "op_type" "RR,RX")
3559 (set_attr "atype" "reg,mem")])
3563 ;;- Multiply instructions.
3567 ; muldi3 instruction pattern(s).
3570 (define_insn "muldi3"
3571 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3572 (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3573 (match_operand:DI 2 "general_operand" "d,K,m")))
3574 (clobber (reg:CC 33))]
3580 [(set_attr "op_type" "RRE,RI,RX")
3581 (set_attr "atype" "reg,reg,mem")
3582 (set_attr "type" "imul")])
3585 ; mulsi3 instruction pattern(s).
3588 (define_insn "mulsi3"
3589 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3590 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3591 (match_operand:SI 2 "general_operand" "d,K,m")))
3592 (clobber (reg:CC 33))]
3598 [(set_attr "op_type" "RRE,RI,RX")
3599 (set_attr "atype" "reg,reg,mem")
3600 (set_attr "type" "imul")])
3603 ; mulsidi3 instruction pattern(s).
3606 (define_expand "mulsidi3"
3607 [(set (match_operand:DI 0 "register_operand" "")
3608 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3609 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3615 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3616 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3619 gen_rtx_EXPR_LIST (REG_EQUAL,
3620 gen_rtx_MULT (DImode,
3621 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3622 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3627 (define_insn "mulsi_6432"
3628 [(set (match_operand:DI 0 "register_operand" "=d,d")
3629 (mult:DI (sign_extend:DI
3630 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3632 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3633 (clobber (reg:CC 33))]
3638 [(set_attr "op_type" "RR,RX")
3639 (set_attr "atype" "reg,mem")
3640 (set_attr "type" "imul")])
3643 ; muldf3 instruction pattern(s).
3646 (define_expand "muldf3"
3648 [(set (match_operand:DF 0 "register_operand" "=f,f")
3649 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3650 (match_operand:DF 2 "general_operand" "f,m")))
3651 (clobber (reg:CC 33))])]
3655 (define_insn "*muldf3"
3656 [(set (match_operand:DF 0 "register_operand" "=f,f")
3657 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3658 (match_operand:DF 2 "general_operand" "f,m")))
3659 (clobber (reg:CC 33))]
3660 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3664 [(set_attr "op_type" "RRE,RXE")
3665 (set_attr "type" "fmul")
3666 (set_attr "atype" "reg,mem")])
3668 (define_insn "*muldf3_ibm"
3669 [(set (match_operand:DF 0 "register_operand" "=f,f")
3670 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3671 (match_operand:DF 2 "general_operand" "f,m")))
3672 (clobber (reg:CC 33))]
3673 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3677 [(set_attr "op_type" "RR,RX")
3678 (set_attr "type" "fmul")
3679 (set_attr "atype" "reg,mem")])
3682 ; mulsf3 instruction pattern(s).
3685 (define_expand "mulsf3"
3687 [(set (match_operand:SF 0 "register_operand" "=f,f")
3688 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3689 (match_operand:SF 2 "general_operand" "f,m")))
3690 (clobber (reg:CC 33))])]
3694 (define_insn "*mulsf3"
3695 [(set (match_operand:SF 0 "register_operand" "=f,f")
3696 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3697 (match_operand:SF 2 "general_operand" "f,m")))
3698 (clobber (reg:CC 33))]
3699 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3703 [(set_attr "op_type" "RRE,RXE")
3704 (set_attr "type" "fmul")
3705 (set_attr "atype" "reg,mem")])
3707 (define_insn "*mulsf3_ibm"
3708 [(set (match_operand:SF 0 "register_operand" "=f,f")
3709 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3710 (match_operand:SF 2 "general_operand" "f,m")))
3711 (clobber (reg:CC 33))]
3712 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3716 [(set_attr "op_type" "RR,RX")
3717 (set_attr "type" "fmul")
3718 (set_attr "atype" "reg,mem")])
3722 ;;- Divide and modulo instructions.
3726 ; divmoddi4 instruction pattern(s).
3729 (define_expand "divmoddi4"
3730 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3731 (div:DI (match_operand:DI 1 "general_operand" "")
3732 (match_operand:DI 2 "general_operand" "")))
3733 (set (match_operand:DI 3 "general_operand" "")
3734 (mod:DI (match_dup 1) (match_dup 2)))])
3735 (clobber (match_dup 4))]
3739 rtx insn, div_equal, mod_equal, equal;
3741 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3742 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3743 equal = gen_rtx_IOR (TImode,
3744 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3745 gen_rtx_ASHIFT (TImode,
3746 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3749 operands[4] = gen_reg_rtx(TImode);
3750 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3751 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3752 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3753 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3755 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3757 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3759 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3761 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3763 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3768 (define_insn "divmodtidi3"
3769 [(set (match_operand:TI 0 "register_operand" "=d,d")
3772 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3773 (match_operand:DI 2 "general_operand" "d,m")))
3776 (mod:DI (truncate:DI (match_dup 1))
3783 [(set_attr "op_type" "RRE,RXE")
3784 (set_attr "type" "idiv")
3785 (set_attr "atype" "reg,mem")])
3787 (define_insn "divmodtisi3"
3788 [(set (match_operand:TI 0 "register_operand" "=d,d")
3791 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3792 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3795 (mod:DI (truncate:DI (match_dup 1))
3796 (sign_extend:DI (match_dup 2))))
3802 [(set_attr "op_type" "RRE,RXE")
3803 (set_attr "type" "idiv")
3804 (set_attr "atype" "reg,mem")])
3807 ; udivmoddi4 instruction pattern(s).
3810 (define_expand "udivmoddi4"
3811 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3812 (udiv:DI (match_operand:DI 1 "general_operand" "")
3813 (match_operand:DI 2 "nonimmediate_operand" "")))
3814 (set (match_operand:DI 3 "general_operand" "")
3815 (umod:DI (match_dup 1) (match_dup 2)))])
3816 (clobber (match_dup 4))]
3820 rtx insn, div_equal, mod_equal, equal;
3822 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3823 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3824 equal = gen_rtx_IOR (TImode,
3825 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3826 gen_rtx_ASHIFT (TImode,
3827 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3830 operands[4] = gen_reg_rtx(TImode);
3831 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3832 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3833 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3834 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3836 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3838 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3840 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3842 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3844 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3849 (define_insn "udivmodtidi3"
3850 [(set (match_operand:TI 0 "register_operand" "=d,d")
3851 (ior:TI (zero_extend:TI
3853 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3855 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3859 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3865 [(set_attr "op_type" "RRE,RXE")
3866 (set_attr "type" "idiv")
3867 (set_attr "atype" "reg,mem")])
3870 ; divmodsi4 instruction pattern(s).
3873 (define_expand "divmodsi4"
3874 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3875 (div:SI (match_operand:SI 1 "general_operand" "")
3876 (match_operand:SI 2 "nonimmediate_operand" "")))
3877 (set (match_operand:SI 3 "general_operand" "")
3878 (mod:SI (match_dup 1) (match_dup 2)))])
3879 (clobber (match_dup 4))]
3883 rtx insn, div_equal, mod_equal, equal;
3885 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3886 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3887 equal = gen_rtx_IOR (DImode,
3888 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3889 gen_rtx_ASHIFT (DImode,
3890 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3893 operands[4] = gen_reg_rtx(DImode);
3894 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3895 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3897 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3899 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3901 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3903 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3905 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3910 (define_insn "divmoddisi3"
3911 [(set (match_operand:DI 0 "register_operand" "=d,d")
3912 (ior:DI (zero_extend:DI
3914 (div:DI (match_operand:DI 1 "register_operand" "0,0")
3916 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3920 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
3926 [(set_attr "op_type" "RR,RX")
3927 (set_attr "type" "idiv")
3928 (set_attr "atype" "reg,mem")])
3931 ; udivsi3 and umodsi3 instruction pattern(s).
3935 (define_expand "udivsi3"
3936 [(set (match_operand:SI 0 "register_operand" "=d")
3937 (udiv:SI (match_operand:SI 1 "general_operand" "")
3938 (match_operand:SI 2 "general_operand" "")))
3939 (clobber (match_dup 3))]
3943 rtx insn, udiv_equal, umod_equal, equal;
3945 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
3946 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
3947 equal = gen_rtx_IOR (DImode,
3948 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
3949 gen_rtx_ASHIFT (DImode,
3950 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
3953 operands[3] = gen_reg_rtx (DImode);
3955 if (CONSTANT_P (operands[2]))
3957 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3959 rtx label1 = gen_label_rtx ();
3961 operands[1] = make_safe_from (operands[1], operands[0]);
3962 emit_move_insn (operands[0], const0_rtx);
3963 emit_insn (gen_cmpsi (operands[1], operands[2]));
3964 emit_jump_insn (gen_bltu (label1));
3965 emit_move_insn (operands[0], const1_rtx);
3966 emit_label (label1);
3970 operands[2] = force_reg (SImode, operands[2]);
3971 operands[2] = make_safe_from (operands[2], operands[0]);
3973 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
3974 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
3977 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3979 insn = emit_move_insn (operands[0],
3980 gen_lowpart (SImode, operands[3]));
3982 gen_rtx_EXPR_LIST (REG_EQUAL,
3983 udiv_equal, REG_NOTES (insn));
3988 rtx label1 = gen_label_rtx ();
3989 rtx label2 = gen_label_rtx ();
3990 rtx label3 = gen_label_rtx ();
3992 operands[1] = force_reg (SImode, operands[1]);
3993 operands[1] = make_safe_from (operands[1], operands[0]);
3994 operands[2] = force_reg (SImode, operands[2]);
3995 operands[2] = make_safe_from (operands[2], operands[0]);
3997 emit_move_insn (operands[0], const0_rtx);
3998 emit_insn (gen_cmpsi (operands[2], operands[1]));
3999 emit_jump_insn (gen_bgtu (label3));
4000 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4001 emit_jump_insn (gen_blt (label2));
4002 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4003 emit_jump_insn (gen_beq (label1));
4004 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4005 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4008 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4010 insn = emit_move_insn (operands[0],
4011 gen_lowpart (SImode, operands[3]));
4013 gen_rtx_EXPR_LIST (REG_EQUAL,
4014 udiv_equal, REG_NOTES (insn));
4016 emit_label (label1);
4017 emit_move_insn (operands[0], operands[1]);
4019 emit_label (label2);
4020 emit_move_insn (operands[0], const1_rtx);
4021 emit_label (label3);
4023 emit_move_insn (operands[0], operands[0]);
4027 (define_expand "umodsi3"
4028 [(set (match_operand:SI 0 "register_operand" "=d")
4029 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4030 (match_operand:SI 2 "nonimmediate_operand" "")))
4031 (clobber (match_dup 3))]
4035 rtx insn, udiv_equal, umod_equal, equal;
4037 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4038 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4039 equal = gen_rtx_IOR (DImode,
4040 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4041 gen_rtx_ASHIFT (DImode,
4042 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4045 operands[3] = gen_reg_rtx (DImode);
4047 if (CONSTANT_P (operands[2]))
4049 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4051 rtx label1 = gen_label_rtx ();
4053 operands[1] = make_safe_from (operands[1], operands[0]);
4054 emit_move_insn (operands[0], operands[1]);
4055 emit_insn (gen_cmpsi (operands[0], operands[2]));
4056 emit_jump_insn (gen_bltu (label1));
4057 emit_insn (gen_abssi2 (operands[0], operands[2]));
4058 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4059 emit_label (label1);
4063 operands[2] = force_reg (SImode, operands[2]);
4064 operands[2] = make_safe_from (operands[2], operands[0]);
4066 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4067 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4070 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4072 insn = emit_move_insn (operands[0],
4073 gen_highpart (SImode, operands[3]));
4075 gen_rtx_EXPR_LIST (REG_EQUAL,
4076 umod_equal, REG_NOTES (insn));
4081 rtx label1 = gen_label_rtx ();
4082 rtx label2 = gen_label_rtx ();
4083 rtx label3 = gen_label_rtx ();
4085 operands[1] = force_reg (SImode, operands[1]);
4086 operands[1] = make_safe_from (operands[1], operands[0]);
4087 operands[2] = force_reg (SImode, operands[2]);
4088 operands[2] = make_safe_from (operands[2], operands[0]);
4090 emit_move_insn(operands[0], operands[1]);
4091 emit_insn (gen_cmpsi (operands[2], operands[1]));
4092 emit_jump_insn (gen_bgtu (label3));
4093 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4094 emit_jump_insn (gen_blt (label2));
4095 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4096 emit_jump_insn (gen_beq (label1));
4097 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4098 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4101 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4103 insn = emit_move_insn (operands[0],
4104 gen_highpart (SImode, operands[3]));
4106 gen_rtx_EXPR_LIST (REG_EQUAL,
4107 umod_equal, REG_NOTES (insn));
4109 emit_label (label1);
4110 emit_move_insn (operands[0], const0_rtx);
4112 emit_label (label2);
4113 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4114 emit_label (label3);
4120 ; divdf3 instruction pattern(s).
4123 (define_expand "divdf3"
4125 [(set (match_operand:DF 0 "register_operand" "=f,f")
4126 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4127 (match_operand:DF 2 "general_operand" "f,m")))
4128 (clobber (reg:CC 33))])]
4132 (define_insn "*divdf3"
4133 [(set (match_operand:DF 0 "register_operand" "=f,f")
4134 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4135 (match_operand:DF 2 "general_operand" "f,m")))
4136 (clobber (reg:CC 33))]
4137 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4141 [(set_attr "op_type" "RRE,RXE")
4142 (set_attr "type" "fdiv")
4143 (set_attr "atype" "reg,mem")])
4145 (define_insn "*divdf3_ibm"
4146 [(set (match_operand:DF 0 "register_operand" "=f,f")
4147 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4148 (match_operand:DF 2 "general_operand" "f,m")))
4149 (clobber (reg:CC 33))]
4150 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4154 [(set_attr "op_type" "RR,RX")
4155 (set_attr "type" "fdiv")
4156 (set_attr "atype" "reg,mem")])
4159 ; divsf3 instruction pattern(s).
4162 (define_expand "divsf3"
4164 [(set (match_operand:SF 0 "register_operand" "=f,f")
4165 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4166 (match_operand:SF 2 "general_operand" "f,m")))
4167 (clobber (reg:CC 33))])]
4171 (define_insn "*divsf3"
4172 [(set (match_operand:SF 0 "register_operand" "=f,f")
4173 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4174 (match_operand:SF 2 "general_operand" "f,m")))
4175 (clobber (reg:CC 33))]
4176 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4180 [(set_attr "op_type" "RRE,RXE")
4181 (set_attr "type" "fdiv")
4182 (set_attr "atype" "reg,mem")])
4184 (define_insn "*divsf3"
4185 [(set (match_operand:SF 0 "register_operand" "=f,f")
4186 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4187 (match_operand:SF 2 "general_operand" "f,m")))
4188 (clobber (reg:CC 33))]
4189 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4193 [(set_attr "op_type" "RR,RX")
4194 (set_attr "type" "fdiv")
4195 (set_attr "atype" "reg,mem")])
4199 ;;- And instructions.
4203 ; anddi3 instruction pattern(s).
4206 (define_insn "*anddi3_cc"
4208 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4209 (match_operand:DI 2 "general_operand" "d,m"))
4211 (set (match_operand:DI 0 "register_operand" "=d,d")
4212 (and:DI (match_dup 1) (match_dup 2)))]
4213 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4217 [(set_attr "op_type" "RRE,RXE")
4218 (set_attr "atype" "reg,mem")])
4220 (define_insn "*anddi3_cconly"
4222 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4223 (match_operand:DI 2 "general_operand" "d,m"))
4225 (clobber (match_scratch:DI 0 "=d,d"))]
4226 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4230 [(set_attr "op_type" "RRE,RXE")
4231 (set_attr "atype" "reg,mem")])
4233 (define_insn "*anddi3_ni"
4234 [(set (match_operand:DI 0 "register_operand" "=d")
4235 (and:DI (match_operand:DI 1 "register_operand" "%0")
4236 (match_operand:DI 2 "immediate_operand" "n")))
4237 (clobber (reg:CC 33))]
4238 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4241 int part = s390_single_hi (operands[2], DImode, -1);
4242 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4246 case 0: return \"nihh\\t%0,%x2\";
4247 case 1: return \"nihl\\t%0,%x2\";
4248 case 2: return \"nilh\\t%0,%x2\";
4249 case 3: return \"nill\\t%0,%x2\";
4253 [(set_attr "op_type" "RI")
4254 (set_attr "atype" "reg")])
4256 (define_insn "anddi3"
4257 [(set (match_operand:DI 0 "register_operand" "=d,d")
4258 (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4259 (match_operand:DI 2 "general_operand" "d,m")))
4260 (clobber (reg:CC 33))]
4265 [(set_attr "op_type" "RRE,RXE")
4266 (set_attr "atype" "reg,mem")])
4268 (define_insn "*anddi3_ss"
4269 [(set (match_operand:DI 0 "s_operand" "=Qo")
4270 (and:DI (match_dup 0)
4271 (match_operand:DI 1 "s_imm_operand" "Qo")))
4272 (clobber (reg:CC 33))]
4274 "nc\\t%O0(8,%R0),%1"
4275 [(set_attr "op_type" "SS")
4276 (set_attr "atype" "mem")])
4278 (define_insn "*anddi3_ss_inv"
4279 [(set (match_operand:DI 0 "s_operand" "=Qo")
4280 (and:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4282 (clobber (reg:CC 33))]
4284 "nc\\t%O0(8,%R0),%1"
4285 [(set_attr "op_type" "SS")
4286 (set_attr "atype" "mem")])
4289 ; andsi3 instruction pattern(s).
4292 (define_insn "*andsi3_cc"
4294 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4295 (match_operand:SI 2 "general_operand" "d,m"))
4297 (set (match_operand:SI 0 "register_operand" "=d,d")
4298 (and:SI (match_dup 1) (match_dup 2)))]
4299 "s390_match_ccmode(insn, CCTmode)"
4303 [(set_attr "op_type" "RR,RX")
4304 (set_attr "atype" "reg,mem")])
4306 (define_insn "*andsi3_cconly"
4308 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4309 (match_operand:SI 2 "general_operand" "d,m"))
4311 (clobber (match_scratch:SI 0 "=d,d"))]
4312 "s390_match_ccmode(insn, CCTmode)"
4316 [(set_attr "op_type" "RR,RX")
4317 (set_attr "atype" "reg,mem")])
4319 (define_insn "*andsi3_ni"
4320 [(set (match_operand:SI 0 "register_operand" "=d")
4321 (and:SI (match_operand:SI 1 "register_operand" "%0")
4322 (match_operand:SI 2 "immediate_operand" "n")))
4323 (clobber (reg:CC 33))]
4324 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4327 int part = s390_single_hi (operands[2], SImode, -1);
4328 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4332 case 0: return \"nilh\\t%0,%x2\";
4333 case 1: return \"nill\\t%0,%x2\";
4337 [(set_attr "op_type" "RI")
4338 (set_attr "atype" "reg")])
4340 (define_insn "andsi3"
4341 [(set (match_operand:SI 0 "register_operand" "=d,d")
4342 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4343 (match_operand:SI 2 "general_operand" "d,m")))
4344 (clobber (reg:CC 33))]
4349 [(set_attr "op_type" "RR,RX")
4350 (set_attr "atype" "reg,mem")])
4352 (define_insn "*andsi3_ss"
4353 [(set (match_operand:SI 0 "s_operand" "=Qo")
4354 (and:SI (match_dup 0)
4355 (match_operand:SI 1 "s_imm_operand" "Qo")))
4356 (clobber (reg:CC 33))]
4358 "nc\\t%O0(4,%R0),%1"
4359 [(set_attr "op_type" "SS")
4360 (set_attr "atype" "mem")])
4362 (define_insn "*andsi3_ss_inv"
4363 [(set (match_operand:SI 0 "s_operand" "=Qo")
4364 (and:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4366 (clobber (reg:CC 33))]
4368 "nc\\t%O0(4,%R0),%1"
4369 [(set_attr "op_type" "SS")
4370 (set_attr "atype" "mem")])
4373 ; andhi3 instruction pattern(s).
4376 (define_insn "*andhi3_ni"
4377 [(set (match_operand:HI 0 "register_operand" "=d,d")
4378 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4379 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4380 (clobber (reg:CC 33))]
4385 [(set_attr "op_type" "RR,RI")
4386 (set_attr "atype" "reg")])
4388 (define_insn "andhi3"
4389 [(set (match_operand:HI 0 "register_operand" "=d")
4390 (and:HI (match_operand:HI 1 "register_operand" "%0")
4391 (match_operand:HI 2 "nonmemory_operand" "d")))
4392 (clobber (reg:CC 33))]
4395 [(set_attr "op_type" "RR")
4396 (set_attr "atype" "reg")])
4398 (define_insn "*andhi3_ss"
4399 [(set (match_operand:HI 0 "s_operand" "=Qo")
4400 (and:HI (match_dup 0)
4401 (match_operand:HI 1 "s_imm_operand" "Qo")))
4402 (clobber (reg:CC 33))]
4404 "nc\\t%O0(2,%R0),%1"
4405 [(set_attr "op_type" "SS")
4406 (set_attr "atype" "mem")])
4408 (define_insn "*andhi3_ss_inv"
4409 [(set (match_operand:HI 0 "s_operand" "=Qo")
4410 (and:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4412 (clobber (reg:CC 33))]
4414 "nc\\t%O0(2,%R0),%1"
4415 [(set_attr "op_type" "SS")
4416 (set_attr "atype" "mem")])
4419 ; andqi3 instruction pattern(s).
4422 (define_insn "*andqi3_ni"
4423 [(set (match_operand:QI 0 "register_operand" "=d,d")
4424 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4425 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4426 (clobber (reg:CC 33))]
4431 [(set_attr "op_type" "RR,RI")
4432 (set_attr "atype" "reg")])
4434 (define_insn "andqi3"
4435 [(set (match_operand:QI 0 "register_operand" "=d")
4436 (and:QI (match_operand:QI 1 "register_operand" "%0")
4437 (match_operand:QI 2 "nonmemory_operand" "d")))
4438 (clobber (reg:CC 33))]
4441 [(set_attr "op_type" "RR")
4442 (set_attr "atype" "reg")])
4444 (define_insn "*andqi3_ss"
4445 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4446 (and:QI (match_dup 0)
4447 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4448 (clobber (reg:CC 33))]
4453 [(set_attr "op_type" "SI,SS")
4454 (set_attr "atype" "mem")])
4456 (define_insn "*andqi3_ss_inv"
4457 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4458 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4460 (clobber (reg:CC 33))]
4465 [(set_attr "op_type" "SI,SS")
4466 (set_attr "atype" "mem")])
4470 ;;- Bit set (inclusive or) instructions.
4474 ; iordi3 instruction pattern(s).
4477 (define_insn "*iordi3_cc"
4479 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4480 (match_operand:DI 2 "general_operand" "d,m"))
4482 (set (match_operand:DI 0 "register_operand" "=d,d")
4483 (ior:DI (match_dup 1) (match_dup 2)))]
4484 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4488 [(set_attr "op_type" "RRE,RXE")
4489 (set_attr "atype" "reg,mem")])
4491 (define_insn "*iordi3_cconly"
4493 (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4494 (match_operand:DI 2 "general_operand" "d,m"))
4496 (clobber (match_scratch:DI 0 "=d,d"))]
4497 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4501 [(set_attr "op_type" "RRE,RXE")
4502 (set_attr "atype" "reg,mem")])
4504 (define_insn "*iordi3_oi"
4505 [(set (match_operand:DI 0 "register_operand" "=d")
4506 (ior:DI (match_operand:DI 1 "register_operand" "%0")
4507 (match_operand:DI 2 "immediate_operand" "n")))
4508 (clobber (reg:CC 33))]
4509 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4512 int part = s390_single_hi (operands[2], DImode, 0);
4513 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4517 case 0: return \"oihh\\t%0,%x2\";
4518 case 1: return \"oihl\\t%0,%x2\";
4519 case 2: return \"oilh\\t%0,%x2\";
4520 case 3: return \"oill\\t%0,%x2\";
4524 [(set_attr "op_type" "RI")
4525 (set_attr "atype" "reg")])
4527 (define_insn "iordi3"
4528 [(set (match_operand:DI 0 "register_operand" "=d,d")
4529 (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
4530 (match_operand:DI 2 "general_operand" "d,m")))
4531 (clobber (reg:CC 33))]
4536 [(set_attr "op_type" "RRE,RXE")
4537 (set_attr "atype" "reg,mem")])
4539 (define_insn "*iordi3_ss"
4540 [(set (match_operand:DI 0 "s_operand" "=Qo")
4541 (ior:DI (match_dup 0)
4542 (match_operand:DI 1 "s_imm_operand" "Qo")))
4543 (clobber (reg:CC 33))]
4545 "oc\\t%O0(8,%R0),%1"
4546 [(set_attr "op_type" "SS")
4547 (set_attr "atype" "mem")])
4549 (define_insn "*iordi3_ss_inv"
4550 [(set (match_operand:DI 0 "s_operand" "=Qo")
4551 (ior:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4553 (clobber (reg:CC 33))]
4555 "oc\\t%O0(8,%R0),%1"
4556 [(set_attr "op_type" "SS")
4557 (set_attr "atype" "mem")])
4560 ; iorsi3 instruction pattern(s).
4563 (define_insn "*iorsi3_cc"
4565 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4566 (match_operand:SI 2 "general_operand" "d,m"))
4568 (set (match_operand:SI 0 "register_operand" "=d,d")
4569 (ior:SI (match_dup 1) (match_dup 2)))]
4570 "s390_match_ccmode(insn, CCTmode)"
4574 [(set_attr "op_type" "RR,RX")
4575 (set_attr "atype" "reg,mem")])
4577 (define_insn "*iorsi3_cconly"
4579 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4580 (match_operand:SI 2 "general_operand" "d,m"))
4582 (clobber (match_scratch:SI 0 "=d,d"))]
4583 "s390_match_ccmode(insn, CCTmode)"
4587 [(set_attr "op_type" "RR,RX")
4588 (set_attr "atype" "reg,mem")])
4590 (define_insn "*iorsi3_oi"
4591 [(set (match_operand:SI 0 "register_operand" "=d")
4592 (ior:SI (match_operand:SI 1 "register_operand" "%0")
4593 (match_operand:SI 2 "immediate_operand" "n")))
4594 (clobber (reg:CC 33))]
4595 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4598 int part = s390_single_hi (operands[2], SImode, 0);
4599 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4603 case 0: return \"oilh\\t%0,%x2\";
4604 case 1: return \"oill\\t%0,%x2\";
4608 [(set_attr "op_type" "RI")
4609 (set_attr "atype" "reg")])
4611 (define_insn "iorsi3"
4612 [(set (match_operand:SI 0 "register_operand" "=d,d")
4613 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
4614 (match_operand:SI 2 "general_operand" "d,m")))
4615 (clobber (reg:CC 33))]
4620 [(set_attr "op_type" "RR,RX")
4621 (set_attr "atype" "reg,mem")])
4623 (define_insn "*iorsi3_ss"
4624 [(set (match_operand:SI 0 "s_operand" "=Qo")
4625 (ior:SI (match_dup 0)
4626 (match_operand:SI 1 "s_imm_operand" "Qo")))
4627 (clobber (reg:CC 33))]
4629 "oc\\t%O0(4,%R0),%1"
4630 [(set_attr "op_type" "SS")
4631 (set_attr "atype" "mem")])
4633 (define_insn "*iorsi3_ss_inv"
4634 [(set (match_operand:SI 0 "s_operand" "=Qo")
4635 (ior:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4637 (clobber (reg:CC 33))]
4639 "oc\\t%O0(4,%R0),%1"
4640 [(set_attr "op_type" "SS")
4641 (set_attr "atype" "mem")])
4644 ; iorhi3 instruction pattern(s).
4647 (define_insn "*iorhi3_oi"
4648 [(set (match_operand:HI 0 "register_operand" "=d,d")
4649 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4650 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4651 (clobber (reg:CC 33))]
4656 [(set_attr "op_type" "RR,RI")
4657 (set_attr "atype" "reg")])
4659 (define_insn "iorhi3"
4660 [(set (match_operand:HI 0 "register_operand" "=d")
4661 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4662 (match_operand:HI 2 "nonmemory_operand" "d")))
4663 (clobber (reg:CC 33))]
4666 [(set_attr "op_type" "RR")
4667 (set_attr "atype" "reg")])
4669 (define_insn "*iorhi3_ss"
4670 [(set (match_operand:HI 0 "s_operand" "=Qo")
4671 (ior:HI (match_dup 0)
4672 (match_operand:HI 1 "s_imm_operand" "Qo")))
4673 (clobber (reg:CC 33))]
4675 "oc\\t%O0(2,%R0),%1"
4676 [(set_attr "op_type" "SS")
4677 (set_attr "atype" "mem")])
4679 (define_insn "*iorhi3_ss_inv"
4680 [(set (match_operand:HI 0 "s_operand" "=Qo")
4681 (ior:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4683 (clobber (reg:CC 33))]
4685 "oc\\t%O0(2,%R0),%1"
4686 [(set_attr "op_type" "SS")
4687 (set_attr "atype" "mem")])
4690 ; iorqi3 instruction pattern(s).
4693 (define_insn "*iorqi3_oi"
4694 [(set (match_operand:QI 0 "register_operand" "=d,d")
4695 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4696 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4697 (clobber (reg:CC 33))]
4702 [(set_attr "op_type" "RR,RI")
4703 (set_attr "atype" "reg")])
4705 (define_insn "iorqi3"
4706 [(set (match_operand:QI 0 "register_operand" "=d")
4707 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4708 (match_operand:QI 2 "nonmemory_operand" "d")))
4709 (clobber (reg:CC 33))]
4712 [(set_attr "op_type" "RR")
4713 (set_attr "atype" "reg")])
4715 (define_insn "*iorqi3_ss"
4716 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4717 (ior:QI (match_dup 0)
4718 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4719 (clobber (reg:CC 33))]
4724 [(set_attr "op_type" "SI,SS")
4725 (set_attr "atype" "reg,mem")])
4727 (define_insn "*iorqi3_ss_inv"
4728 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4729 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4731 (clobber (reg:CC 33))]
4736 [(set_attr "op_type" "SI,SS")
4737 (set_attr "atype" "reg,mem")])
4741 ;;- Xor instructions.
4745 ; xordi3 instruction pattern(s).
4748 (define_insn "*xordi3_cc"
4750 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4751 (match_operand:DI 2 "general_operand" "d,m"))
4753 (set (match_operand:DI 0 "register_operand" "=d,d")
4754 (xor:DI (match_dup 1) (match_dup 2)))]
4755 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4759 [(set_attr "op_type" "RRE,RXE")
4760 (set_attr "atype" "reg,mem")])
4762 (define_insn "*xordi3_cconly"
4764 (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4765 (match_operand:DI 2 "general_operand" "d,m"))
4767 (clobber (match_scratch:DI 0 "=d,d"))]
4768 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4772 [(set_attr "op_type" "RRE,RXE")
4773 (set_attr "atype" "reg,mem")])
4775 (define_insn "xordi3"
4776 [(set (match_operand:DI 0 "register_operand" "=d,d")
4777 (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
4778 (match_operand:DI 2 "general_operand" "d,m")))
4779 (clobber (reg:CC 33))]
4784 [(set_attr "op_type" "RRE,RXE")
4785 (set_attr "atype" "reg,mem")])
4787 (define_insn "*xordi3_ss"
4788 [(set (match_operand:DI 0 "s_operand" "=Qo")
4789 (xor:DI (match_dup 0)
4790 (match_operand:DI 1 "s_imm_operand" "Qo")))
4791 (clobber (reg:CC 33))]
4793 "xc\\t%O0(8,%R0),%1"
4794 [(set_attr "op_type" "SS")
4795 (set_attr "atype" "mem")])
4797 (define_insn "*xordi3_ss_inv"
4798 [(set (match_operand:DI 0 "s_operand" "=Qo")
4799 (xor:DI (match_operand:DI 1 "s_imm_operand" "Qo")
4801 (clobber (reg:CC 33))]
4803 "xc\\t%O0(8,%R0),%1"
4804 [(set_attr "op_type" "SS")
4805 (set_attr "atype" "mem")])
4808 ; xorsi3 instruction pattern(s).
4811 (define_insn "*xorsi3_cc"
4813 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4814 (match_operand:SI 2 "general_operand" "d,m"))
4816 (set (match_operand:SI 0 "register_operand" "=d,d")
4817 (xor:SI (match_dup 1) (match_dup 2)))]
4818 "s390_match_ccmode(insn, CCTmode)"
4822 [(set_attr "op_type" "RR,RX")
4823 (set_attr "atype" "reg,mem")])
4825 (define_insn "*xorsi3_cconly"
4827 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4828 (match_operand:SI 2 "general_operand" "d,m"))
4830 (clobber (match_scratch:SI 0 "=d,d"))]
4831 "s390_match_ccmode(insn, CCTmode)"
4835 [(set_attr "op_type" "RR,RX")
4836 (set_attr "atype" "reg,mem")])
4838 (define_insn "xorsi3"
4839 [(set (match_operand:SI 0 "register_operand" "=d,d")
4840 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
4841 (match_operand:SI 2 "general_operand" "d,m")))
4842 (clobber (reg:CC 33))]
4847 [(set_attr "op_type" "RR,RX")
4848 (set_attr "atype" "reg,mem")])
4850 (define_insn "*xorsi3_ss"
4851 [(set (match_operand:SI 0 "s_operand" "=Qo")
4852 (xor:SI (match_dup 0)
4853 (match_operand:SI 1 "s_imm_operand" "Qo")))
4854 (clobber (reg:CC 33))]
4856 "xc\\t%O0(4,%R0),%1"
4857 [(set_attr "op_type" "SS")
4858 (set_attr "atype" "mem")])
4860 (define_insn "*xorsi3_ss_inv"
4861 [(set (match_operand:SI 0 "s_operand" "=Qo")
4862 (xor:SI (match_operand:SI 1 "s_imm_operand" "Qo")
4864 (clobber (reg:CC 33))]
4866 "xc\\t%O0(4,%R0),%1"
4867 [(set_attr "op_type" "SS")
4868 (set_attr "atype" "mem")])
4871 ; xorhi3 instruction pattern(s).
4874 (define_insn "xorhi3"
4875 [(set (match_operand:HI 0 "register_operand" "=d")
4876 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4877 (match_operand:HI 2 "nonmemory_operand" "d")))
4878 (clobber (reg:CC 33))]
4881 [(set_attr "op_type" "RR")
4882 (set_attr "atype" "reg")])
4884 (define_insn "*xorhi3_ss"
4885 [(set (match_operand:HI 0 "s_operand" "=Qo")
4886 (xor:HI (match_dup 0)
4887 (match_operand:HI 1 "s_imm_operand" "Qo")))
4888 (clobber (reg:CC 33))]
4890 "xc\\t%O0(2,%R0),%1"
4891 [(set_attr "op_type" "SS")
4892 (set_attr "atype" "mem")])
4894 (define_insn "*xorhi3_ss_inv"
4895 [(set (match_operand:HI 0 "s_operand" "=Qo")
4896 (xor:HI (match_operand:HI 1 "s_imm_operand" "Qo")
4898 (clobber (reg:CC 33))]
4900 "xc\\t%O0(2,%R0),%1"
4901 [(set_attr "op_type" "SS")
4902 (set_attr "atype" "mem")])
4905 ; xorqi3 instruction pattern(s).
4908 (define_insn "xorqi3"
4909 [(set (match_operand:QI 0 "register_operand" "=d")
4910 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4911 (match_operand:QI 2 "nonmemory_operand" "d")))
4912 (clobber (reg:CC 33))]
4915 [(set_attr "op_type" "RR")
4916 (set_attr "atype" "reg")])
4918 (define_insn "*xorqi3_ss"
4919 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4920 (xor:QI (match_dup 0)
4921 (match_operand:QI 1 "s_imm_operand" "n,Qo")))
4922 (clobber (reg:CC 33))]
4927 [(set_attr "op_type" "SI,SS")
4928 (set_attr "atype" "mem")])
4930 (define_insn "*xorqi3_ss_inv"
4931 [(set (match_operand:QI 0 "s_operand" "=Qo,Qo")
4932 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Qo")
4934 (clobber (reg:CC 33))]
4939 [(set_attr "op_type" "SI,SS")
4940 (set_attr "atype" "mem")])
4944 ;;- Negate instructions.
4948 ; negdi2 instruction pattern(s).
4951 (define_expand "negdi2"
4953 [(set (match_operand:DI 0 "register_operand" "=d")
4954 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4955 (clobber (reg:CC 33))])]
4959 (define_insn "*negdi2_64"
4960 [(set (match_operand:DI 0 "register_operand" "=d")
4961 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4962 (clobber (reg:CC 33))]
4965 [(set_attr "op_type" "RR")])
4967 (define_insn "*negdi2_31"
4968 [(set (match_operand:DI 0 "register_operand" "=d")
4969 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4970 (clobber (reg:CC 33))]
4975 xop[0] = gen_label_rtx ();
4976 output_asm_insn (\"lcr\\t%0,%1\", operands);
4977 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
4978 output_asm_insn (\"je\\t%l0\", xop);
4979 output_asm_insn (\"bctr\\t%0,0\", operands);
4980 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4981 CODE_LABEL_NUMBER (xop[0]));
4984 [(set_attr "op_type" "NN")
4985 (set_attr "type" "other")
4986 (set_attr "length" "10")])
4989 ; negsi2 instruction pattern(s).
4992 (define_insn "negsi2"
4993 [(set (match_operand:SI 0 "register_operand" "=d")
4994 (neg:SI (match_operand:SI 1 "register_operand" "d")))
4995 (clobber (reg:CC 33))]
4998 [(set_attr "op_type" "RR")])
5001 ; negdf2 instruction pattern(s).
5004 (define_expand "negdf2"
5006 [(set (match_operand:DF 0 "register_operand" "=f")
5007 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5008 (clobber (reg:CC 33))])]
5012 (define_insn "*negdf2"
5013 [(set (match_operand:DF 0 "register_operand" "=f")
5014 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5015 (clobber (reg:CC 33))]
5016 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5018 [(set_attr "op_type" "RRE")])
5020 (define_insn "*negdf2_ibm"
5021 [(set (match_operand:DF 0 "register_operand" "=f")
5022 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5023 (clobber (reg:CC 33))]
5024 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5026 [(set_attr "op_type" "RR")])
5029 ; negsf2 instruction pattern(s).
5032 (define_expand "negsf2"
5034 [(set (match_operand:SF 0 "register_operand" "=f")
5035 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5036 (clobber (reg:CC 33))])]
5040 (define_insn "*negsf2"
5041 [(set (match_operand:SF 0 "register_operand" "=f")
5042 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5043 (clobber (reg:CC 33))]
5044 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5046 [(set_attr "op_type" "RRE")])
5048 (define_insn "*negsf2"
5049 [(set (match_operand:SF 0 "register_operand" "=f")
5050 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5051 (clobber (reg:CC 33))]
5052 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5054 [(set_attr "op_type" "RR")])
5058 ;;- Absolute value instructions.
5062 ; absdi2 instruction pattern(s).
5065 (define_insn "absdi2"
5066 [(set (match_operand:DI 0 "register_operand" "=d")
5067 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5068 (clobber (reg:CC 33))]
5071 [(set_attr "op_type" "RRE")])
5074 ; abssi2 instruction pattern(s).
5077 (define_insn "abssi2"
5078 [(set (match_operand:SI 0 "register_operand" "=d")
5079 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5080 (clobber (reg:CC 33))]
5083 [(set_attr "op_type" "RR")])
5086 ; absdf2 instruction pattern(s).
5089 (define_expand "absdf2"
5091 [(set (match_operand:DF 0 "register_operand" "=f")
5092 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5093 (clobber (reg:CC 33))])]
5097 (define_insn "*absdf2"
5098 [(set (match_operand:DF 0 "register_operand" "=f")
5099 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5100 (clobber (reg:CC 33))]
5101 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5103 [(set_attr "op_type" "RRE")])
5105 (define_insn "*absdf2_ibm"
5106 [(set (match_operand:DF 0 "register_operand" "=f")
5107 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5108 (clobber (reg:CC 33))]
5109 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5111 [(set_attr "op_type" "RR")])
5114 ; abssf2 instruction pattern(s).
5117 (define_expand "abssf2"
5119 [(set (match_operand:SF 0 "register_operand" "=f")
5120 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5121 (clobber (reg:CC 33))])]
5125 (define_insn "*abssf2"
5126 [(set (match_operand:SF 0 "register_operand" "=f")
5127 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5128 (clobber (reg:CC 33))]
5129 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5131 [(set_attr "op_type" "RRE")])
5133 (define_insn "*abssf2_ibm"
5134 [(set (match_operand:SF 0 "register_operand" "=f")
5135 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5136 (clobber (reg:CC 33))]
5137 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5139 [(set_attr "op_type" "RR")])
5142 ;;- Square root instructions.
5146 ; sqrtdf2 instruction pattern(s).
5149 (define_insn "sqrtdf2"
5150 [(set (match_operand:DF 0 "register_operand" "=f,f")
5151 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5152 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5156 [(set_attr "op_type" "RRE,RSE")])
5159 ; sqrtsf2 instruction pattern(s).
5162 (define_insn "sqrtsf2"
5163 [(set (match_operand:SF 0 "register_operand" "=f,f")
5164 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5165 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5169 [(set_attr "op_type" "RRE,RSE")])
5172 ;;- One complement instructions.
5176 ; one_cmpldi2 instruction pattern(s).
5179 (define_expand "one_cmpldi2"
5181 [(set (match_operand:DI 0 "register_operand" "")
5182 (xor:DI (match_operand:DI 1 "register_operand" "")
5184 (clobber (reg:CC 33))])]
5189 ; one_cmplsi2 instruction pattern(s).
5192 (define_expand "one_cmplsi2"
5194 [(set (match_operand:SI 0 "register_operand" "")
5195 (xor:SI (match_operand:SI 1 "register_operand" "")
5197 (clobber (reg:CC 33))])]
5202 ; one_cmplhi2 instruction pattern(s).
5205 (define_expand "one_cmplhi2"
5207 [(set (match_operand:HI 0 "register_operand" "")
5208 (xor:HI (match_operand:HI 1 "register_operand" "")
5210 (clobber (reg:CC 33))])]
5215 ; one_cmplqi2 instruction pattern(s).
5218 (define_expand "one_cmplqi2"
5220 [(set (match_operand:QI 0 "register_operand" "")
5221 (xor:QI (match_operand:QI 1 "register_operand" "")
5223 (clobber (reg:CC 33))])]
5229 ;;- Rotate instructions.
5233 ; rotldi3 instruction pattern(s).
5236 (define_insn "rotldi3"
5237 [(set (match_operand:DI 0 "register_operand" "=d,d")
5238 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5239 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5244 [(set_attr "op_type" "RSE")])
5247 ; rotlsi3 instruction pattern(s).
5250 (define_insn "rotlsi3"
5251 [(set (match_operand:SI 0 "register_operand" "=d,d")
5252 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5253 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5258 [(set_attr "op_type" "RSE")])
5262 ;;- Arithmetic shift instructions.
5266 ; ashldi3 instruction pattern(s).
5269 (define_expand "ashldi3"
5270 [(set (match_operand:DI 0 "register_operand" "")
5271 (ashift:DI (match_operand:DI 1 "register_operand" "")
5272 (match_operand:SI 2 "nonmemory_operand" "")))]
5276 (define_insn "*ashldi3_31"
5277 [(set (match_operand:DI 0 "register_operand" "=d,d")
5278 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5279 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5284 [(set_attr "op_type" "RS")])
5286 (define_insn "*ashldi3_64"
5287 [(set (match_operand:DI 0 "register_operand" "=d,d")
5288 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5289 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5294 [(set_attr "op_type" "RSE")])
5297 ; ashrdi3 instruction pattern(s).
5300 (define_expand "ashrdi3"
5302 [(set (match_operand:DI 0 "register_operand" "")
5303 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5304 (match_operand:SI 2 "nonmemory_operand" "")))
5305 (clobber (reg:CC 33))])]
5309 (define_insn "*ashrdi3_cc_31"
5311 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5312 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5314 (set (match_operand:DI 0 "register_operand" "=d,d")
5315 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5316 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5320 [(set_attr "op_type" "RS")])
5322 (define_insn "*ashrdi3_cconly_31"
5324 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5325 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5327 (clobber (match_scratch:DI 0 "=d,d"))]
5328 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5332 [(set_attr "op_type" "RS")])
5334 (define_insn "*ashrdi3_31"
5335 [(set (match_operand:DI 0 "register_operand" "=d,d")
5336 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5337 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5338 (clobber (reg:CC 33))]
5343 [(set_attr "op_type" "RS")])
5345 (define_insn "*ashrdi3_cc_64"
5347 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5348 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5350 (set (match_operand:DI 0 "register_operand" "=d,d")
5351 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5352 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5356 [(set_attr "op_type" "RSE")])
5358 (define_insn "*ashrdi3_cconly_64"
5360 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5361 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5363 (clobber (match_scratch:DI 0 "=d,d"))]
5364 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5368 [(set_attr "op_type" "RSE")])
5370 (define_insn "*ashrdi3_64"
5371 [(set (match_operand:DI 0 "register_operand" "=d,d")
5372 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5373 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5374 (clobber (reg:CC 33))]
5379 [(set_attr "op_type" "RSE")])
5382 ; ashlsi3 instruction pattern(s).
5385 (define_insn "ashlsi3"
5386 [(set (match_operand:SI 0 "register_operand" "=d,d")
5387 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5388 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5393 [(set_attr "op_type" "RS")])
5396 ; ashrsi3 instruction pattern(s).
5399 (define_insn "*ashrsi3_cc"
5401 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5402 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5404 (set (match_operand:SI 0 "register_operand" "=d,d")
5405 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5406 "s390_match_ccmode(insn, CCSmode)"
5410 [(set_attr "op_type" "RS")])
5412 (define_insn "*ashrsi3_cconly"
5414 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5415 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5417 (clobber (match_scratch:SI 0 "=d,d"))]
5418 "s390_match_ccmode(insn, CCSmode)"
5422 [(set_attr "op_type" "RS")])
5424 (define_insn "ashrsi3"
5425 [(set (match_operand:SI 0 "register_operand" "=d,d")
5426 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5427 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5428 (clobber (reg:CC 33))]
5433 [(set_attr "op_type" "RS")])
5437 ;;- logical shift instructions.
5441 ; lshrdi3 instruction pattern(s).
5444 (define_expand "lshrdi3"
5445 [(set (match_operand:DI 0 "register_operand" "")
5446 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5447 (match_operand:SI 2 "nonmemory_operand" "")))]
5451 (define_insn "*lshrdi3_31"
5452 [(set (match_operand:DI 0 "register_operand" "=d,d")
5453 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5454 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5459 [(set_attr "op_type" "RS,RS")])
5461 (define_insn "*lshrdi3_64"
5462 [(set (match_operand:DI 0 "register_operand" "=d,d")
5463 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5464 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5469 [(set_attr "op_type" "RS,RS")])
5472 ; lshrsi3 instruction pattern(s).
5475 (define_insn "lshrsi3"
5476 [(set (match_operand:SI 0 "register_operand" "=d,d")
5477 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5478 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5483 [(set_attr "op_type" "RS")])
5487 ;; Branch instruction patterns.
5490 (define_expand "beq"
5491 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5493 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5494 (label_ref (match_operand 0 "" ""))
5497 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5499 (define_expand "bne"
5500 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5502 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5503 (label_ref (match_operand 0 "" ""))
5506 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5508 (define_expand "bgt"
5509 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5511 (if_then_else (gt (reg:CCS 33) (const_int 0))
5512 (label_ref (match_operand 0 "" ""))
5515 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5517 (define_expand "bgtu"
5518 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5520 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5521 (label_ref (match_operand 0 "" ""))
5524 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5526 (define_expand "blt"
5527 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5529 (if_then_else (lt (reg:CCS 33) (const_int 0))
5530 (label_ref (match_operand 0 "" ""))
5533 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5535 (define_expand "bltu"
5536 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5538 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5539 (label_ref (match_operand 0 "" ""))
5542 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5544 (define_expand "bge"
5545 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5547 (if_then_else (ge (reg:CCS 33) (const_int 0))
5548 (label_ref (match_operand 0 "" ""))
5551 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5553 (define_expand "bgeu"
5554 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5556 (if_then_else (geu (reg:CCU 33) (const_int 0))
5557 (label_ref (match_operand 0 "" ""))
5560 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5562 (define_expand "ble"
5563 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5565 (if_then_else (le (reg:CCS 33) (const_int 0))
5566 (label_ref (match_operand 0 "" ""))
5569 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5571 (define_expand "bleu"
5572 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5574 (if_then_else (leu (reg:CCU 33) (const_int 0))
5575 (label_ref (match_operand 0 "" ""))
5578 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5580 (define_expand "bunordered"
5581 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5583 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5584 (label_ref (match_operand 0 "" ""))
5587 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5589 (define_expand "bordered"
5590 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5592 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5593 (label_ref (match_operand 0 "" ""))
5596 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5598 (define_expand "buneq"
5599 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5601 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5602 (label_ref (match_operand 0 "" ""))
5605 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5607 (define_expand "bungt"
5608 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5610 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5611 (label_ref (match_operand 0 "" ""))
5614 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5616 (define_expand "bunlt"
5617 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5619 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5620 (label_ref (match_operand 0 "" ""))
5623 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5625 (define_expand "bunge"
5626 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5628 (if_then_else (unge (reg:CCS 33) (const_int 0))
5629 (label_ref (match_operand 0 "" ""))
5632 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5634 (define_expand "bunle"
5635 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5637 (if_then_else (unle (reg:CCS 33) (const_int 0))
5638 (label_ref (match_operand 0 "" ""))
5641 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5643 (define_expand "bltgt"
5644 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5646 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5647 (label_ref (match_operand 0 "" ""))
5650 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5654 ;;- Conditional jump instructions.
5657 (define_insn "cjump"
5660 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5661 (label_ref (match_operand 0 "" ""))
5666 if (get_attr_length (insn) == 4)
5667 return \"j%C1\\t%l0\";
5668 else if (TARGET_64BIT)
5669 return \"jg%C1\\t%l0\";
5673 [(set_attr "op_type" "RI")
5674 (set (attr "length")
5675 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5677 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5679 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5680 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5681 (const_int 12) (const_int 14))
5682 (eq (symbol_ref "flag_pic") (const_int 0))
5683 (const_int 6)] (const_int 8)))])
5685 (define_insn "*cjump_long"
5688 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5689 (match_operand 0 "address_operand" "p")
5694 if (get_attr_op_type (insn) == OP_TYPE_RR)
5695 return \"b%C1r\\t%0\";
5697 return \"b%C1\\t%a0\";
5699 [(set (attr "op_type")
5700 (if_then_else (match_operand 0 "register_operand" "")
5701 (const_string "RR") (const_string "RX")))
5702 (set_attr "atype" "mem")])
5706 ;;- Negated conditional jump instructions.
5709 (define_insn "icjump"
5712 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5714 (label_ref (match_operand 0 "" ""))))]
5718 if (get_attr_length (insn) == 4)
5719 return \"j%D1\\t%l0\";
5720 else if (TARGET_64BIT)
5721 return \"jg%D1\\t%l0\";
5725 [(set_attr "op_type" "RI")
5726 (set (attr "length")
5727 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5729 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5731 (ne (symbol_ref "s390_pool_overflow") (const_int 0))
5732 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5733 (const_int 12) (const_int 14))
5734 (eq (symbol_ref "flag_pic") (const_int 0))
5735 (const_int 6)] (const_int 8)))])
5737 (define_insn "*icjump_long"
5740 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5742 (match_operand 0 "address_operand" "p")))]
5746 if (get_attr_op_type (insn) == OP_TYPE_RR)
5747 return \"b%D1r\\t%0\";
5749 return \"b%D1\\t%a0\";
5751 [(set (attr "op_type")
5752 (if_then_else (match_operand 0 "register_operand" "")
5753 (const_string "RR") (const_string "RX")))
5754 (set_attr "atype" "mem")])
5758 ;;- Subtract one and jump if not zero.
5761 ;(define_expand "decrement_and_branch_on_count"
5762 ; [(use (match_operand 0 "register_operand" ""))
5763 ; (use (label_ref (match_operand 1 "" "")))]
5767 ;/* if (TARGET_64BIT)
5768 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5770 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5774 ;(define_insn "brctsi"
5777 ; (ne (match_operand:SI 0 "register_operand" "+a")
5779 ; (label_ref (match_operand 1 "" ""))
5781 ; (set (match_dup 0)
5782 ; (plus:SI (match_dup 0) (const_int -1)))]
5785 ; [(set_attr "op_type" "RI")
5786 ; (set_attr "type" "branch")]
5789 ;(define_insn "ibrctsi"
5792 ; (eq (match_operand:SI 0 "register_operand" "+a")
5795 ; (label_ref (match_operand 1 "" ""))))
5796 ; (set (match_dup 0)
5797 ; (plus:SI (match_dup 0) (const_int -1)))]
5800 ; [(set_attr "op_type" "RI")
5801 ; (set_attr "type" "branch")]
5806 ;;- Unconditional jump instructions.
5810 ; jump instruction pattern(s).
5814 [(set (pc) (label_ref (match_operand 0 "" "")))]
5818 if (get_attr_length (insn) == 4)
5820 else if (TARGET_64BIT)
5821 return \"jg\\t%l0\";
5825 [(set_attr "op_type" "RI")
5826 (set (attr "length")
5827 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5829 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5831 (eq (symbol_ref "flag_pic") (const_int 0))
5832 (const_int 6)] (const_int 8)))])
5835 ; indirect-jump instruction pattern(s).
5838 (define_insn "indirect_jump"
5839 [(set (pc) (match_operand 0 "address_operand" "p"))]
5843 if (get_attr_op_type (insn) == OP_TYPE_RR)
5848 [(set (attr "op_type")
5849 (if_then_else (match_operand 0 "register_operand" "")
5850 (const_string "RR") (const_string "RX")))
5851 (set_attr "atype" "mem")])
5854 ; casesi instruction pattern(s).
5857 (define_insn "casesi_jump"
5858 [(set (pc) (match_operand 0 "address_operand" "p"))
5859 (use (label_ref (match_operand 1 "" "")))]
5863 if (get_attr_op_type (insn) == OP_TYPE_RR)
5868 [(set (attr "op_type")
5869 (if_then_else (match_operand 0 "register_operand" "")
5870 (const_string "RR") (const_string "RX")))
5871 (set_attr "atype" "mem")])
5873 (define_expand "casesi"
5874 [(match_operand:SI 0 "general_operand" "")
5875 (match_operand:SI 1 "general_operand" "")
5876 (match_operand:SI 2 "general_operand" "")
5877 (label_ref (match_operand 3 "" ""))
5878 (label_ref (match_operand 4 "" ""))]
5882 rtx index = gen_reg_rtx (SImode);
5883 rtx base = gen_reg_rtx (Pmode);
5884 rtx target = gen_reg_rtx (Pmode);
5886 emit_move_insn (index, operands[0]);
5887 emit_insn (gen_subsi3 (index, index, operands[1]));
5888 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
5891 if (Pmode != SImode)
5892 index = convert_to_mode (Pmode, index, 1);
5893 if (GET_CODE (index) != REG)
5894 index = copy_to_mode_reg (Pmode, index);
5897 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
5899 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
5901 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
5903 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
5904 emit_move_insn (target, index);
5907 target = gen_rtx_PLUS (Pmode, base, target);
5908 emit_jump_insn (gen_casesi_jump (target, operands[3]));
5915 ;;- Jump to subroutine.
5920 ; untyped call instruction pattern(s).
5923 ;; Call subroutine returning any type.
5924 (define_expand "untyped_call"
5925 [(parallel [(call (match_operand 0 "" "")
5927 (match_operand 1 "" "")
5928 (match_operand 2 "" "")])]
5934 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
5936 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5938 rtx set = XVECEXP (operands[2], 0, i);
5939 emit_move_insn (SET_DEST (set), SET_SRC (set));
5942 /* The optimizer does not know that the call sets the function value
5943 registers we stored in the result block. We avoid problems by
5944 claiming that all hard registers are used and clobbered at this
5946 emit_insn (gen_blockage ());
5951 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5952 ;; all of memory. This blocks insns from being moved across this point.
5954 (define_insn "blockage"
5955 [(unspec_volatile [(const_int 0)] 0)]
5958 [(set_attr "type" "none")])
5963 ; call instruction pattern(s).
5966 (define_expand "call"
5967 [(call (match_operand 0 "" "")
5968 (match_operand 1 "" ""))
5969 (use (match_operand 2 "" ""))]
5976 /* Direct function calls need special treatment. */
5977 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5979 rtx sym = XEXP (operands[0], 0);
5981 /* When calling a global routine in PIC mode, we must
5982 replace the symbol itself with the PLT stub. */
5983 if (flag_pic && !SYMBOL_REF_FLAG (sym))
5985 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5986 sym = gen_rtx_CONST (Pmode, sym);
5991 /* Unless we can use the bras(l) insn, force the
5992 routine address into a register. */
5993 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5995 rtx target = gen_reg_rtx (Pmode);
5996 emit_move_insn (target, sym);
6000 operands[0] = gen_rtx_MEM (QImode, sym);
6004 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6005 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6007 /* In 31-bit, we must load the GOT register even if the
6008 compiler doesn't know about it, because the PLT glue
6009 code uses it. In 64-bit, this is not necessary. */
6010 if (plt_call && !TARGET_64BIT)
6012 current_function_uses_pic_offset_table = 1;
6013 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6019 (define_expand "call_exp"
6020 [(parallel [(call (match_operand 0 "" "")
6021 (match_operand 1 "" ""))
6022 (clobber (match_operand 2 "" ""))])]
6026 (define_insn "brasl"
6027 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6028 (match_operand:SI 1 "const_int_operand" "n"))
6029 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6032 [(set_attr "op_type" "RIL")
6033 (set_attr "type" "jsr")])
6036 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6037 (match_operand:SI 1 "const_int_operand" "n"))
6038 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6041 [(set_attr "op_type" "RI")
6042 (set_attr "type" "jsr")])
6044 (define_insn "basr_64"
6045 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6046 (match_operand:SI 1 "const_int_operand" "n"))
6047 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6050 [(set_attr "op_type" "RR")
6051 (set_attr "type" "jsr")
6052 (set_attr "atype" "mem")])
6054 (define_insn "basr_31"
6055 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6056 (match_operand:SI 1 "const_int_operand" "n"))
6057 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6060 [(set_attr "op_type" "RR")
6061 (set_attr "type" "jsr")
6062 (set_attr "atype" "mem")])
6064 (define_insn "bas_64"
6065 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6066 (match_operand:SI 1 "const_int_operand" "n"))
6067 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6070 [(set_attr "op_type" "RX")
6071 (set_attr "type" "jsr")
6072 (set_attr "atype" "mem")])
6074 (define_insn "bas_31"
6075 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6076 (match_operand:SI 1 "const_int_operand" "n"))
6077 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6080 [(set_attr "op_type" "RX")
6081 (set_attr "type" "jsr")
6082 (set_attr "atype" "mem")])
6086 ; call_value instruction pattern(s).
6089 (define_expand "call_value"
6090 [(set (match_operand 0 "" "")
6091 (call (match_operand 1 "" "")
6092 (match_operand 2 "" "")))
6093 (use (match_operand 3 "" ""))]
6100 /* Direct function calls need special treatment. */
6101 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6103 rtx sym = XEXP (operands[1], 0);
6105 /* When calling a global routine in PIC mode, we must
6106 replace the symbol itself with the PLT stub. */
6107 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6109 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6110 sym = gen_rtx_CONST (Pmode, sym);
6115 /* Unless we can use the bras(l) insn, force the
6116 routine address into a register. */
6117 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6119 rtx target = gen_reg_rtx (Pmode);
6120 emit_move_insn (target, sym);
6124 operands[1] = gen_rtx_MEM (QImode, sym);
6128 insn = emit_call_insn (
6129 gen_call_value_exp (operands[0], operands[1], operands[2],
6130 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6132 /* In 31-bit, we must load the GOT register even if the
6133 compiler doesn't know about it, because the PLT glue
6134 code uses it. In 64-bit, this is not necessary. */
6135 if (plt_call && !TARGET_64BIT)
6137 current_function_uses_pic_offset_table = 1;
6138 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6144 (define_expand "call_value_exp"
6145 [(parallel [(set (match_operand 0 "" "")
6146 (call (match_operand 1 "" "")
6147 (match_operand 2 "" "")))
6148 (clobber (match_operand 3 "" ""))])]
6152 (define_insn "brasl_r"
6153 [(set (match_operand 0 "register_operand" "=df")
6154 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6155 (match_operand:SI 2 "const_int_operand" "n")))
6156 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6159 [(set_attr "op_type" "RIL")
6160 (set_attr "type" "jsr")])
6162 (define_insn "bras_r"
6163 [(set (match_operand 0 "register_operand" "=df")
6164 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6165 (match_operand:SI 2 "const_int_operand" "n")))
6166 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6169 [(set_attr "op_type" "RI")
6170 (set_attr "type" "jsr")])
6172 (define_insn "basr_r_64"
6173 [(set (match_operand 0 "register_operand" "=df")
6174 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6175 (match_operand:SI 2 "const_int_operand" "n")))
6176 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6179 [(set_attr "op_type" "RR")
6180 (set_attr "type" "jsr")])
6182 (define_insn "basr_r_31"
6183 [(set (match_operand 0 "register_operand" "=df")
6184 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6185 (match_operand:SI 2 "const_int_operand" "n")))
6186 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6189 [(set_attr "op_type" "RR")
6190 (set_attr "type" "jsr")
6191 (set_attr "atype" "mem")])
6193 (define_insn "bas_r_64"
6194 [(set (match_operand 0 "register_operand" "=df")
6195 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6196 (match_operand:SI 2 "const_int_operand" "n")))
6197 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6200 [(set_attr "op_type" "RX")
6201 (set_attr "type" "jsr")
6202 (set_attr "atype" "mem")])
6204 (define_insn "bas_r_31"
6205 [(set (match_operand 0 "register_operand" "=df")
6206 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6207 (match_operand:SI 2 "const_int_operand" "n")))
6208 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6211 [(set_attr "op_type" "RX")
6212 (set_attr "type" "jsr")
6213 (set_attr "atype" "mem")])
6217 ;;- Miscellaneous instructions.
6221 ; allocate stack instruction pattern(s).
6224 (define_expand "allocate_stack"
6226 (plus (reg 15) (match_operand 1 "general_operand" "")))
6227 (set (match_operand 0 "general_operand" "")
6232 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6233 rtx chain = gen_rtx (MEM, Pmode, stack);
6234 rtx temp = gen_reg_rtx (Pmode);
6236 emit_move_insn (temp, chain);
6239 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6241 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6243 emit_move_insn (chain, temp);
6245 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6251 ; setjmp/longjmp instruction pattern(s).
6254 (define_expand "builtin_setjmp_setup"
6255 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6259 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6260 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6262 emit_move_insn (base, basereg);
6266 (define_expand "builtin_setjmp_receiver"
6267 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6271 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6272 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6273 SYMBOL_REF_FLAG (got) = 1;
6275 emit_move_insn (gotreg, got);
6276 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6280 (define_expand "builtin_longjmp"
6281 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6285 /* The elements of the buffer are, in order: */
6286 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6287 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6288 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6289 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6290 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6291 rtx jmp = gen_rtx_REG (Pmode, 14);
6293 emit_move_insn (jmp, lab);
6294 emit_move_insn (basereg, base);
6295 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6296 emit_move_insn (hard_frame_pointer_rtx, fp);
6298 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6299 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6300 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6301 emit_indirect_jump (jmp);
6306 ;; These patterns say how to save and restore the stack pointer. We need not
6307 ;; save the stack pointer at function level since we are careful to
6308 ;; preserve the backchain. At block level, we have to restore the backchain
6309 ;; when we restore the stack pointer.
6311 ;; For nonlocal gotos, we must save both the stack pointer and its
6312 ;; backchain and restore both. Note that in the nonlocal case, the
6313 ;; save area is a memory location.
6315 (define_expand "save_stack_function"
6316 [(match_operand 0 "general_operand" "")
6317 (match_operand 1 "general_operand" "")]
6321 (define_expand "restore_stack_function"
6322 [(match_operand 0 "general_operand" "")
6323 (match_operand 1 "general_operand" "")]
6327 (define_expand "restore_stack_block"
6328 [(use (match_operand 0 "register_operand" ""))
6329 (set (match_dup 2) (match_dup 3))
6330 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6331 (set (match_dup 3) (match_dup 2))]
6335 operands[2] = gen_reg_rtx (Pmode);
6336 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6339 (define_expand "save_stack_nonlocal"
6340 [(match_operand 0 "memory_operand" "")
6341 (match_operand 1 "register_operand" "")]
6345 rtx temp = gen_reg_rtx (Pmode);
6347 /* Copy the backchain to the first word, sp to the second. */
6348 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6349 emit_move_insn (operand_subword (operands[0], 0, 0,
6350 TARGET_64BIT ? TImode : DImode),
6352 emit_move_insn (operand_subword (operands[0], 1, 0,
6353 TARGET_64BIT ? TImode : DImode),
6358 (define_expand "restore_stack_nonlocal"
6359 [(match_operand 0 "register_operand" "")
6360 (match_operand 1 "memory_operand" "")]
6364 rtx temp = gen_reg_rtx (Pmode);
6366 /* Restore the backchain from the first word, sp from the second. */
6367 emit_move_insn (temp,
6368 operand_subword (operands[1], 0, 0,
6369 TARGET_64BIT ? TImode : DImode));
6370 emit_move_insn (operands[0],
6371 operand_subword (operands[1], 1, 0,
6372 TARGET_64BIT ? TImode : DImode));
6373 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6379 ; nop instruction pattern(s).
6386 [(set_attr "op_type" "RR")])
6390 ; Special literal pool access instruction pattern(s).
6393 (define_insn "consttable_qi"
6394 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6398 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6401 [(set_attr "op_type" "NN")
6402 (set_attr "length" "1")])
6404 (define_insn "consttable_hi"
6405 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6409 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6412 [(set_attr "op_type" "NN")
6413 (set_attr "length" "2")])
6415 (define_insn "consttable_si"
6416 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6420 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6421 return \".long\\t%0\";
6423 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6426 [(set_attr "op_type" "NN")
6427 (set_attr "length" "4")])
6429 (define_insn "consttable_di"
6430 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6434 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6437 [(set_attr "op_type" "NN")
6438 (set_attr "length" "8")])
6440 (define_insn "consttable_sf"
6441 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6447 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6450 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6451 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6454 [(set_attr "op_type" "NN")
6455 (set_attr "length" "4")])
6457 (define_insn "consttable_df"
6458 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6464 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6467 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6468 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6471 [(set_attr "op_type" "NN")
6472 (set_attr "length" "8")])
6474 (define_insn "pool_start_31"
6475 [(unspec_volatile [(const_int 0)] 206)]
6478 [(set_attr "op_type" "NN")
6479 (set_attr "length" "2")])
6481 (define_insn "pool_end_31"
6482 [(unspec_volatile [(const_int 0)] 207)]
6485 [(set_attr "op_type" "NN")
6486 (set_attr "length" "2")])
6488 (define_insn "pool_start_64"
6489 [(unspec_volatile [(const_int 0)] 206)]
6491 ".section\\t.rodata\;.align\\t8"
6492 [(set_attr "op_type" "NN")
6493 (set_attr "length" "0")])
6495 (define_insn "pool_end_64"
6496 [(unspec_volatile [(const_int 0)] 207)]
6499 [(set_attr "op_type" "NN")
6500 (set_attr "length" "0")])
6502 (define_insn "reload_base"
6503 [(set (match_operand:SI 0 "register_operand" "=a")
6504 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6506 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6507 [(set_attr "op_type" "NN")
6508 (set_attr "type" "la")
6509 (set_attr "length" "6")])
6511 (define_insn "reload_base2"
6512 [(set (match_operand:SI 0 "register_operand" "=a")
6513 (unspec:SI [(label_ref (match_operand 1 "" ""))] 211))]
6516 [(set_attr "op_type" "NN")
6517 (set_attr "type" "la")
6518 (set_attr "length" "4")])
6522 ;; Insns related to generating the function prologue and epilogue.
6526 (define_expand "prologue"
6527 [(use (const_int 0))]
6531 s390_emit_prologue ();
6535 (define_expand "epilogue"
6536 [(use (const_int 1))]
6540 s390_emit_epilogue ();
6545 (define_insn "*return_si"
6547 (use (match_operand:SI 0 "register_operand" "a"))]
6550 [(set_attr "op_type" "RR")
6551 (set_attr "type" "jsr")
6552 (set_attr "atype" "mem")])
6554 (define_insn "*return_di"
6556 (use (match_operand:DI 0 "register_operand" "a"))]
6559 [(set_attr "op_type" "RR")
6560 (set_attr "type" "jsr")
6561 (set_attr "atype" "mem")])
6565 [(set (reg 13) (pc))
6566 (unspec_volatile [(const_int 0)] 200)]
6570 s390_output_constant_pool (asm_out_file);
6573 [(set_attr "op_type" "NN")
6574 (set_attr "type" "integer")])
6578 ;; Peephole optimization patterns.
6582 [(set (match_operand:SI 0 "memory_operand" "m")
6583 (match_operand:SI 1 "register_operand" "d"))
6590 [(set (match_operand:SI 0 "memory_operand" "m")
6591 (match_operand:SI 1 "register_operand" "d"))
6598 [(set (match_operand:SI 0 "register_operand" "")
6599 (match_operand:SI 1 "register_operand" ""))
6602 (plus:SI (match_dup 0)
6603 (match_operand:SI 2 "immediate_operand" "")))
6604 (clobber (reg:CC 33))])]
6605 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
6606 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
6607 REGNO (operands[0]) == BASE_REGISTER ||
6608 REGNO (operands[1]) == BASE_REGISTER) &&
6609 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
6613 ; peepholes for fast char instructions
6617 ; [(set (match_operand:QI 0 "register_operand" "d")
6618 ; (match_operand:QI 1 "s_operand" "Q"))
6619 ; (set (match_operand:SI 2 "register_operand" "0")
6620 ; (zero_extend:SI (match_dup 0)))]
6621 ; "REGNO(operands[0]) == REGNO(operands[2])"
6622 ; "icm\\t%0,8,%1\;srl\\t%0,24")
6625 ; [(set (match_operand:QI 0 "register_operand" "d")
6626 ; (match_operand:QI 1 "s_operand" "Q"))
6627 ; (set (match_operand:SI 2 "register_operand" "0")
6628 ; (sign_extend:SI (match_dup 0)))]
6629 ; "REGNO(operands[0]) == REGNO(operands[2])"
6630 ; "icm\\t%0,8,%1\;sra\\t%0,24")
6633 [(set (match_operand:QI 0 "register_operand" "d")
6634 (match_operand:QI 1 "immediate_operand" "J"))
6635 (set (match_operand:SI 2 "register_operand" "0" )
6636 (sign_extend:SI (match_dup 0) ) )]
6637 "REGNO(operands[0]) == REGNO(operands[2])"
6641 ; peepholes for fast short instructions
6645 ; [(set (match_operand:HI 0 "register_operand" "d")
6646 ; (match_operand:HI 1 "s_operand" "Q"))
6647 ; (set (match_operand:SI 2 "register_operand" "0" )
6648 ; (zero_extend:SI (match_dup 0)))]
6649 ; "REGNO(operands[0]) == REGNO(operands[2])"
6650 ; "icm\\t%0,12,%1\;srl\\t%0,16")
6653 [(set (match_operand:HI 0 "register_operand" "d")
6654 (match_operand:HI 1 "memory_operand" "m"))
6655 (set (match_operand:SI 2 "register_operand" "0" )
6656 (sign_extend:SI (match_dup 0)))]
6657 "REGNO(operands[0]) == REGNO(operands[2])"
6661 [(set (match_operand:HI 0 "register_operand" "d")
6662 (match_operand:HI 1 "immediate_operand" "K"))
6663 (set (match_operand:SI 2 "register_operand" "0" )
6664 (sign_extend:SI (match_dup 0) ) )]
6665 "REGNO(operands[0]) == REGNO(operands[2])"
6669 ; peepholes for divide instructions
6673 [(set (match_operand:DI 0 "register_operand" "d")
6674 (match_operand:DI 1 "memory_operand" "m"))
6676 (lshiftrt:DI (match_dup 0)
6677 (match_operand:SI 2 "immediate_operand" "J")))
6679 (div:SI (match_dup 0)
6680 (match_operand:SI 3 "nonimmediate_operand" "g")))
6686 output_asm_insn (\"l\\t%0,%1\", operands);
6687 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6689 if (REG_P (operands[3]))
6690 output_asm_insn (\"dr\\t%0,%3\", operands);
6692 output_asm_insn (\"d\\t%0,%3\", operands);
6694 return \"st\\t%N0,%N1\";
6698 [(set (match_operand:DI 0 "register_operand" "d")
6699 (match_operand:DI 1 "memory_operand" "m"))
6701 (lshiftrt:DI (match_dup 0)
6702 (match_operand:SI 2 "immediate_operand" "J")))
6704 (mod:SI (match_dup 0)
6705 (match_operand:SI 3 "nonimmediate_operand" "g")))
6711 output_asm_insn (\"l\\t%0,%1\", operands);
6712 output_asm_insn (\"srdl\\t%0,%b2\", operands);
6714 if (REG_P (operands[3]))
6715 output_asm_insn (\"dr\\t%0,%3\", operands);
6717 output_asm_insn (\"d\\t%0,%3\", operands);
6719 return \"st\\t%0,%1\";