1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; GOT/PLT and lt-relative accesses
94 ; TLS relocation specifiers
110 ; Stack Smashing Protector
114 ; Test Data Class (TDC)
126 UNSPEC_FPINT_NEARBYINT
131 ;; UNSPEC_VOLATILE usage
134 (define_c_enum "unspecv" [
156 ; Hotpatching (unremovable NOPs)
161 ; Transactional Execution support
171 ; Set and get floating point control register
180 ; Registers with special meaning
184 ; Sibling call register.
186 ; Literal pool base register.
188 ; Return address register.
190 ; Condition code register.
192 ; Thread local storage pointer register.
196 ; Hardware register names
200 ; General purpose registers
202 ; Floating point registers.
222 ;; PFPO GPR0 argument format
227 ; PFPO operation type
228 (PFPO_CONVERT 0x1000000)
230 (PFPO_OP_TYPE_SF 0x5)
231 (PFPO_OP_TYPE_DF 0x6)
232 (PFPO_OP_TYPE_TF 0x7)
233 (PFPO_OP_TYPE_SD 0x8)
234 (PFPO_OP_TYPE_DD 0x9)
235 (PFPO_OP_TYPE_TD 0xa)
236 ; Bitposition of operand types
237 (PFPO_OP0_TYPE_SHIFT 16)
238 (PFPO_OP1_TYPE_SHIFT 8)
241 ; Immediate operands for tbegin and tbeginc
242 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
243 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
245 ;; Instruction operand type as used in the Principles of Operation.
246 ;; Used to determine defaults for length and other attribute values.
248 (define_attr "op_type"
249 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
252 ;; Instruction type attribute used for scheduling.
254 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
255 cs,vs,store,sem,idiv,
256 imulhi,imulsi,imuldi,
257 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
258 floadtf,floaddf,floadsf,fstoredf,fstoresf,
259 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
260 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
262 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
263 itoftf, itofdf, itofsf, itofdd, itoftd,
264 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
265 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
267 (cond [(eq_attr "op_type" "NN") (const_string "other")
268 (eq_attr "op_type" "SS") (const_string "cs")]
269 (const_string "integer")))
271 ;; Another attribute used for scheduling purposes:
272 ;; agen: Instruction uses the address generation unit
273 ;; reg: Instruction does not use the agen unit
275 (define_attr "atype" "agen,reg"
276 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
278 (const_string "agen")))
280 ;; Properties concerning Z10 execution grouping and value forwarding.
281 ;; z10_super: instruction is superscalar.
282 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
283 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
284 ;; target register. It can forward this value to a second instruction that reads
285 ;; the same register if that second instruction is issued in the same group.
286 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
287 ;; instruction in the S pipe writes to the register, then the T instruction
288 ;; can immediately read the new value.
289 ;; z10_fr: union of Z10_fwd and z10_rec.
290 ;; z10_c: second operand of instruction is a register and read with complemented bits.
292 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
295 (define_attr "z10prop" "none,
296 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
297 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
299 z10_fr, z10_fr_A3, z10_fr_E1,
301 (const_string "none"))
303 ;; Properties concerning Z196 decoding
304 ;; z196_alone: must group alone
305 ;; z196_end: ends a group
306 ;; z196_cracked: instruction is cracked or expanded
307 (define_attr "z196prop" "none,
308 z196_alone, z196_ends,
310 (const_string "none"))
312 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
316 (define_attr "length" ""
317 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
318 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
322 ;; Processor type. This attribute must exactly match the processor_type
323 ;; enumeration in s390.h. The current machine description does not
324 ;; distinguish between g5 and g6, but there are differences between the two
325 ;; CPUs could in theory be modeled.
327 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
328 (const (symbol_ref "s390_tune_attr")))
330 (define_attr "cpu_facility"
331 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12"
332 (const_string "standard"))
334 (define_attr "enabled" ""
335 (cond [(eq_attr "cpu_facility" "standard")
338 (and (eq_attr "cpu_facility" "ieee")
339 (match_test "TARGET_CPU_IEEE_FLOAT"))
342 (and (eq_attr "cpu_facility" "zarch")
343 (match_test "TARGET_ZARCH"))
346 (and (eq_attr "cpu_facility" "longdisp")
347 (match_test "TARGET_LONG_DISPLACEMENT"))
350 (and (eq_attr "cpu_facility" "extimm")
351 (match_test "TARGET_EXTIMM"))
354 (and (eq_attr "cpu_facility" "dfp")
355 (match_test "TARGET_DFP"))
358 (and (eq_attr "cpu_facility" "cpu_zarch")
359 (match_test "TARGET_CPU_ZARCH"))
362 (and (eq_attr "cpu_facility" "z10")
363 (match_test "TARGET_Z10"))
366 (and (eq_attr "cpu_facility" "z196")
367 (match_test "TARGET_Z196"))
370 (and (eq_attr "cpu_facility" "zEC12")
371 (match_test "TARGET_ZEC12"))
375 ;; Pipeline description for z900. For lack of anything better,
376 ;; this description is also used for the g5 and g6.
379 ;; Pipeline description for z990, z9-109 and z9-ec.
382 ;; Pipeline description for z10
385 ;; Pipeline description for z196
388 ;; Pipeline description for zEC12
392 (include "predicates.md")
394 ;; Constraint definitions
395 (include "constraints.md")
402 ;; These mode iterators allow floating point patterns to be generated from the
404 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
405 (SD "TARGET_HARD_DFP")])
406 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
407 (define_mode_iterator FPALL [TF DF SF TD DD SD])
408 (define_mode_iterator BFP [TF DF SF])
409 (define_mode_iterator DFP [TD DD])
410 (define_mode_iterator DFP_ALL [TD DD SD])
411 (define_mode_iterator DSF [DF SF])
412 (define_mode_iterator SD_SF [SF SD])
413 (define_mode_iterator DD_DF [DF DD])
414 (define_mode_iterator TD_TF [TF TD])
416 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
417 ;; from the same template.
418 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
419 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
420 (define_mode_iterator DSI [DI SI])
421 (define_mode_iterator TDI [TI DI])
423 ;; These mode iterators allow :P to be used for patterns that operate on
424 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
425 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
427 ;; These macros refer to the actual word_mode of the configuration.
428 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
429 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
430 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
432 ;; Used by the umul pattern to express modes having half the size.
433 (define_mode_attr DWH [(TI "DI") (DI "SI")])
434 (define_mode_attr dwh [(TI "di") (DI "si")])
436 ;; This mode iterator allows the QI and HI patterns to be defined from
437 ;; the same template.
438 (define_mode_iterator HQI [HI QI])
440 ;; This mode iterator allows the integer patterns to be defined from the
442 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
443 (define_mode_iterator INTALL [TI DI SI HI QI])
444 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
446 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
447 ;; the same template.
448 (define_code_iterator SHIFT [ashift lshiftrt])
450 ;; This iterator allows r[ox]sbg to be defined with the same template
451 (define_code_iterator IXOR [ior xor])
453 ;; This iterator is used to expand the patterns for the nearest
454 ;; integer functions.
455 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
456 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
457 UNSPEC_FPINT_NEARBYINT])
458 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
459 (UNSPEC_FPINT_BTRUNC "btrunc")
460 (UNSPEC_FPINT_ROUND "round")
461 (UNSPEC_FPINT_CEIL "ceil")
462 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
463 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
464 (UNSPEC_FPINT_BTRUNC "5")
465 (UNSPEC_FPINT_ROUND "1")
466 (UNSPEC_FPINT_CEIL "6")
467 (UNSPEC_FPINT_NEARBYINT "0")])
469 ;; This iterator and attribute allow to combine most atomic operations.
470 (define_code_iterator ATOMIC [and ior xor plus minus mult])
471 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
472 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
473 (plus "add") (minus "sub") (mult "nand")])
474 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
476 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
477 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
478 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
480 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
481 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
483 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
485 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
486 ;; Likewise for "<RXe>".
487 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
488 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
490 ;; The decimal floating point variants of add, sub, div and mul support 3
491 ;; fp register operands. The following attributes allow to merge the bfp and
492 ;; dfp variants in a single insn definition.
494 ;; This attribute is used to set op_type accordingly.
495 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
496 (DD "RRR") (SD "RRR")])
498 ;; This attribute is used in the operand constraint list in order to have the
499 ;; first and the second operand match for bfp modes.
500 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
502 ;; This attribute is used in the operand list of the instruction to have an
503 ;; additional operand for the dfp instructions.
504 (define_mode_attr op1 [(TF "") (DF "") (SF "")
505 (TD "%1,") (DD "%1,") (SD "%1,")])
508 ;; This attribute is used in the operand constraint list
509 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
510 ;; TFmode values are represented by a fp register pair. Since the
511 ;; sign bit instructions only handle single source and target fp registers
512 ;; these instructions can only be used for TFmode values if the source and
513 ;; target operand uses the same fp register.
514 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
516 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
517 ;; This is used to disable the memory alternative in TFmode patterns.
518 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
520 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
521 ;; within instruction mnemonics.
522 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
524 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
525 ;; modes and to an empty string for bfp modes.
526 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
528 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
529 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
530 ;; version only operates on one register.
531 (define_mode_attr d0 [(DI "d") (SI "0")])
533 ;; In combination with d0 this allows to combine instructions of which the 31bit
534 ;; version only operates on one register. The DImode version needs an additional
535 ;; register for the assembler output.
536 (define_mode_attr 1 [(DI "%1,") (SI "")])
538 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
539 ;; 'ashift' and "srdl" in 'lshiftrt'.
540 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
542 ;; In SHIFT templates, this attribute holds the correct standard name for the
543 ;; pattern itself and the corresponding function calls.
544 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
546 ;; This attribute handles differences in the instruction 'type' and will result
547 ;; in "RRE" for DImode and "RR" for SImode.
548 (define_mode_attr E [(DI "E") (SI "")])
550 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
551 ;; to result in "RXY" for DImode and "RX" for SImode.
552 (define_mode_attr Y [(DI "Y") (SI "")])
554 ;; This attribute handles differences in the instruction 'type' and will result
555 ;; in "RSE" for TImode and "RS" for DImode.
556 (define_mode_attr TE [(TI "E") (DI "")])
558 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
559 ;; and "lcr" in SImode.
560 (define_mode_attr g [(DI "g") (SI "")])
562 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
563 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
564 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
565 ;; variant for long displacements.
566 (define_mode_attr y [(DI "g") (SI "y")])
568 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
569 ;; and "cds" in DImode.
570 (define_mode_attr tg [(TI "g") (DI "")])
572 ;; In TDI templates, a string like "c<d>sg".
573 (define_mode_attr td [(TI "d") (DI "")])
575 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
576 ;; and "cfdbr" in SImode.
577 (define_mode_attr gf [(DI "g") (SI "f")])
579 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
580 ;; and sllk for SI. This way it is possible to merge the new z196 SI
581 ;; 3 operands shift instructions into the existing patterns.
582 (define_mode_attr gk [(DI "g") (SI "k")])
584 ;; ICM mask required to load MODE value into the lowest subreg
585 ;; of a SImode register.
586 (define_mode_attr icm_lo [(HI "3") (QI "1")])
588 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
589 ;; HImode and "llgc" in QImode.
590 (define_mode_attr hc [(HI "h") (QI "c")])
592 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
594 (define_mode_attr DBL [(DI "TI") (SI "DI")])
596 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
597 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
598 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
600 ;; Maximum unsigned integer that fits in MODE.
601 (define_mode_attr max_uint [(HI "65535") (QI "255")])
603 ;; Start and end field computations for RISBG et al.
604 (define_mode_attr bfstart [(DI "s") (SI "t")])
605 (define_mode_attr bfend [(DI "e") (SI "f")])
607 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
608 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
610 ;; Allow return and simple_return to be defined from a single template.
611 (define_code_iterator ANY_RETURN [return simple_return])
614 ;;- Compare instructions.
617 ; Test-under-Mask instructions
619 (define_insn "*tmqi_mem"
620 [(set (reg CC_REGNUM)
621 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
622 (match_operand:QI 1 "immediate_operand" "n,n"))
623 (match_operand:QI 2 "immediate_operand" "n,n")))]
624 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
628 [(set_attr "op_type" "SI,SIY")
629 (set_attr "z10prop" "z10_super,z10_super")])
631 (define_insn "*tmdi_reg"
632 [(set (reg CC_REGNUM)
633 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
634 (match_operand:DI 1 "immediate_operand"
635 "N0HD0,N1HD0,N2HD0,N3HD0"))
636 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
638 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
639 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
645 [(set_attr "op_type" "RI")
646 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
648 (define_insn "*tmsi_reg"
649 [(set (reg CC_REGNUM)
650 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
651 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
652 (match_operand:SI 2 "immediate_operand" "n,n")))]
653 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
654 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
658 [(set_attr "op_type" "RI")
659 (set_attr "z10prop" "z10_super,z10_super")])
661 (define_insn "*tm<mode>_full"
662 [(set (reg CC_REGNUM)
663 (compare (match_operand:HQI 0 "register_operand" "d")
664 (match_operand:HQI 1 "immediate_operand" "n")))]
665 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
667 [(set_attr "op_type" "RI")
668 (set_attr "z10prop" "z10_super")])
672 ; Load-and-Test instructions
675 ; tst(di|si) instruction pattern(s).
677 (define_insn "*tstdi_sign"
678 [(set (reg CC_REGNUM)
682 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
683 (const_int 32)) (const_int 32))
684 (match_operand:DI 1 "const0_operand" "")))
685 (set (match_operand:DI 2 "register_operand" "=d,d")
686 (sign_extend:DI (match_dup 0)))]
687 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
690 [(set_attr "op_type" "RRE,RXY")
691 (set_attr "cpu_facility" "*,z10")
692 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
695 (define_insn "*tst<mode>_extimm"
696 [(set (reg CC_REGNUM)
697 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
698 (match_operand:GPR 1 "const0_operand" "")))
699 (set (match_operand:GPR 2 "register_operand" "=d,d")
701 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
705 [(set_attr "op_type" "RR<E>,RXY")
706 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
709 (define_insn "*tst<mode>_cconly_extimm"
710 [(set (reg CC_REGNUM)
711 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
712 (match_operand:GPR 1 "const0_operand" "")))
713 (clobber (match_scratch:GPR 2 "=X,d"))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
718 [(set_attr "op_type" "RR<E>,RXY")
719 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
721 (define_insn "*tstdi"
722 [(set (reg CC_REGNUM)
723 (compare (match_operand:DI 0 "register_operand" "d")
724 (match_operand:DI 1 "const0_operand" "")))
725 (set (match_operand:DI 2 "register_operand" "=d")
727 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
729 [(set_attr "op_type" "RRE")
730 (set_attr "z10prop" "z10_fr_E1")])
732 (define_insn "*tstsi"
733 [(set (reg CC_REGNUM)
734 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
735 (match_operand:SI 1 "const0_operand" "")))
736 (set (match_operand:SI 2 "register_operand" "=d,d,d")
738 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
743 [(set_attr "op_type" "RR,RS,RSY")
744 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
746 (define_insn "*tstsi_cconly"
747 [(set (reg CC_REGNUM)
748 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
749 (match_operand:SI 1 "const0_operand" "")))
750 (clobber (match_scratch:SI 2 "=X,d,d"))]
751 "s390_match_ccmode(insn, CCSmode)"
756 [(set_attr "op_type" "RR,RS,RSY")
757 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
759 (define_insn "*tstdi_cconly_31"
760 [(set (reg CC_REGNUM)
761 (compare (match_operand:DI 0 "register_operand" "d")
762 (match_operand:DI 1 "const0_operand" "")))]
763 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
765 [(set_attr "op_type" "RS")
766 (set_attr "atype" "reg")])
769 (define_insn "*tst<mode>_cconly2"
770 [(set (reg CC_REGNUM)
771 (compare (match_operand:GPR 0 "register_operand" "d")
772 (match_operand:GPR 1 "const0_operand" "")))]
773 "s390_match_ccmode(insn, CCSmode)"
775 [(set_attr "op_type" "RR<E>")
776 (set_attr "z10prop" "z10_fr_E1")])
778 ; tst(hi|qi) instruction pattern(s).
780 (define_insn "*tst<mode>CCT"
781 [(set (reg CC_REGNUM)
782 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
783 (match_operand:HQI 1 "const0_operand" "")))
784 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
786 "s390_match_ccmode(insn, CCTmode)"
789 icmy\t%2,<icm_lo>,%S0
791 [(set_attr "op_type" "RS,RSY,RI")
792 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
794 (define_insn "*tsthiCCT_cconly"
795 [(set (reg CC_REGNUM)
796 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
797 (match_operand:HI 1 "const0_operand" "")))
798 (clobber (match_scratch:HI 2 "=d,d,X"))]
799 "s390_match_ccmode(insn, CCTmode)"
804 [(set_attr "op_type" "RS,RSY,RI")
805 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
807 (define_insn "*tstqiCCT_cconly"
808 [(set (reg CC_REGNUM)
809 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
810 (match_operand:QI 1 "const0_operand" "")))]
811 "s390_match_ccmode(insn, CCTmode)"
816 [(set_attr "op_type" "SI,SIY,RI")
817 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
819 (define_insn "*tst<mode>"
820 [(set (reg CC_REGNUM)
821 (compare (match_operand:HQI 0 "s_operand" "Q,S")
822 (match_operand:HQI 1 "const0_operand" "")))
823 (set (match_operand:HQI 2 "register_operand" "=d,d")
825 "s390_match_ccmode(insn, CCSmode)"
828 icmy\t%2,<icm_lo>,%S0"
829 [(set_attr "op_type" "RS,RSY")
830 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
832 (define_insn "*tst<mode>_cconly"
833 [(set (reg CC_REGNUM)
834 (compare (match_operand:HQI 0 "s_operand" "Q,S")
835 (match_operand:HQI 1 "const0_operand" "")))
836 (clobber (match_scratch:HQI 2 "=d,d"))]
837 "s390_match_ccmode(insn, CCSmode)"
840 icmy\t%2,<icm_lo>,%S0"
841 [(set_attr "op_type" "RS,RSY")
842 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
845 ; Compare (equality) instructions
847 (define_insn "*cmpdi_cct"
848 [(set (reg CC_REGNUM)
849 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
850 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
851 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
858 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
859 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
861 (define_insn "*cmpsi_cct"
862 [(set (reg CC_REGNUM)
863 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
864 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
865 "s390_match_ccmode (insn, CCTmode)"
873 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
874 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
876 ; Compare (signed) instructions
878 (define_insn "*cmpdi_ccs_sign"
879 [(set (reg CC_REGNUM)
880 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
882 (match_operand:DI 0 "register_operand" "d, d,d")))]
883 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
888 [(set_attr "op_type" "RRE,RXY,RIL")
889 (set_attr "z10prop" "z10_c,*,*")
890 (set_attr "type" "*,*,larl")])
894 (define_insn "*cmpsi_ccs_sign"
895 [(set (reg CC_REGNUM)
896 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
897 (match_operand:SI 0 "register_operand" "d,d,d")))]
898 "s390_match_ccmode(insn, CCSRmode)"
903 [(set_attr "op_type" "RX,RXY,RIL")
904 (set_attr "cpu_facility" "*,*,z10")
905 (set_attr "type" "*,*,larl")
906 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
908 (define_insn "*cmphi_ccs_z10"
909 [(set (reg CC_REGNUM)
910 (compare (match_operand:HI 0 "s_operand" "Q")
911 (match_operand:HI 1 "immediate_operand" "K")))]
912 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
914 [(set_attr "op_type" "SIL")
915 (set_attr "z196prop" "z196_cracked")])
917 (define_insn "*cmpdi_ccs_signhi_rl"
918 [(set (reg CC_REGNUM)
919 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
920 (match_operand:GPR 0 "register_operand" "d,d")))]
921 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
925 [(set_attr "op_type" "RXY,RIL")
926 (set_attr "type" "*,larl")])
928 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
929 (define_insn "*cmp<mode>_ccs"
930 [(set (reg CC_REGNUM)
931 (compare (match_operand:GPR 0 "nonimmediate_operand"
933 (match_operand:GPR 1 "general_operand"
935 "s390_match_ccmode(insn, CCSmode)"
944 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
945 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
946 (set_attr "type" "*,*,*,*,*,*,larl")
947 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
950 ; Compare (unsigned) instructions
952 (define_insn "*cmpsi_ccu_zerohi_rlsi"
953 [(set (reg CC_REGNUM)
954 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
955 "larl_operand" "X")))
956 (match_operand:SI 0 "register_operand" "d")))]
957 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
959 [(set_attr "op_type" "RIL")
960 (set_attr "type" "larl")
961 (set_attr "z10prop" "z10_super")])
964 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
965 [(set (reg CC_REGNUM)
966 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
967 "larl_operand" "X")))
968 (match_operand:GPR 0 "register_operand" "d")))]
969 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
971 [(set_attr "op_type" "RIL")
972 (set_attr "type" "larl")
973 (set_attr "z10prop" "z10_super")])
975 (define_insn "*cmpdi_ccu_zero"
976 [(set (reg CC_REGNUM)
977 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
979 (match_operand:DI 0 "register_operand" "d, d,d")))]
980 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
985 [(set_attr "op_type" "RRE,RXY,RIL")
986 (set_attr "cpu_facility" "*,*,z10")
987 (set_attr "type" "*,*,larl")
988 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
990 (define_insn "*cmpdi_ccu"
991 [(set (reg CC_REGNUM)
992 (compare (match_operand:DI 0 "nonimmediate_operand"
994 (match_operand:DI 1 "general_operand"
995 "d,Op,b,D,RT,BQ,Q")))]
996 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1005 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1006 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1007 (set_attr "type" "*,*,larl,*,*,*,*")
1008 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1010 (define_insn "*cmpsi_ccu"
1011 [(set (reg CC_REGNUM)
1012 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1013 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1014 "s390_match_ccmode (insn, CCUmode)"
1024 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1025 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
1026 (set_attr "type" "*,*,larl,*,*,*,*,*")
1027 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1029 (define_insn "*cmphi_ccu"
1030 [(set (reg CC_REGNUM)
1031 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1032 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1033 "s390_match_ccmode (insn, CCUmode)
1034 && !register_operand (operands[1], HImode)"
1041 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1042 (set_attr "cpu_facility" "*,*,z10,*,*")
1043 (set_attr "z10prop" "*,*,z10_super,*,*")])
1045 (define_insn "*cmpqi_ccu"
1046 [(set (reg CC_REGNUM)
1047 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1048 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1049 "s390_match_ccmode (insn, CCUmode)
1050 && !register_operand (operands[1], QImode)"
1058 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1059 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1062 ; Block compare (CLC) instruction patterns.
1065 [(set (reg CC_REGNUM)
1066 (compare (match_operand:BLK 0 "memory_operand" "Q")
1067 (match_operand:BLK 1 "memory_operand" "Q")))
1068 (use (match_operand 2 "const_int_operand" "n"))]
1069 "s390_match_ccmode (insn, CCUmode)
1070 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1071 "clc\t%O0(%2,%R0),%S1"
1072 [(set_attr "op_type" "SS")])
1075 [(set (reg CC_REGNUM)
1076 (compare (match_operand 0 "memory_operand" "")
1077 (match_operand 1 "memory_operand" "")))]
1079 && s390_match_ccmode (insn, CCUmode)
1080 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1081 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1083 [(set (match_dup 0) (match_dup 1))
1084 (use (match_dup 2))])]
1086 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1087 operands[0] = adjust_address (operands[0], BLKmode, 0);
1088 operands[1] = adjust_address (operands[1], BLKmode, 0);
1090 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1091 operands[0], operands[1]);
1092 operands[0] = SET_DEST (PATTERN (curr_insn));
1096 ; (TF|DF|SF|TD|DD|SD) instructions
1098 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1099 (define_insn "*cmp<mode>_ccs_0"
1100 [(set (reg CC_REGNUM)
1101 (compare (match_operand:FP 0 "register_operand" "f")
1102 (match_operand:FP 1 "const0_operand" "")))]
1103 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1104 "lt<xde><bt>r\t%0,%0"
1105 [(set_attr "op_type" "RRE")
1106 (set_attr "type" "fsimp<mode>")])
1108 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1109 (define_insn "*cmp<mode>_ccs"
1110 [(set (reg CC_REGNUM)
1111 (compare (match_operand:FP 0 "register_operand" "f,f")
1112 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1113 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1117 [(set_attr "op_type" "RRE,RXE")
1118 (set_attr "type" "fsimp<mode>")])
1121 ; Compare and Branch instructions
1123 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1124 ; The following instructions do a complementary access of their second
1125 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1126 (define_insn "*cmp_and_br_signed_<mode>"
1128 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1129 [(match_operand:GPR 1 "register_operand" "d,d")
1130 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1131 (label_ref (match_operand 3 "" ""))
1133 (clobber (reg:CC CC_REGNUM))]
1134 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1136 if (get_attr_length (insn) == 6)
1137 return which_alternative ?
1138 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1140 return which_alternative ?
1141 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1143 [(set_attr "op_type" "RIE")
1144 (set_attr "type" "branch")
1145 (set_attr "z10prop" "z10_super_c,z10_super")
1146 (set (attr "length")
1147 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1148 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1149 ; 10 byte for cgr/jg
1151 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1152 ; The following instructions do a complementary access of their second
1153 ; operand (z10 only): clrj, clgrj, clr, clgr
1154 (define_insn "*cmp_and_br_unsigned_<mode>"
1156 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1157 [(match_operand:GPR 1 "register_operand" "d,d")
1158 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1159 (label_ref (match_operand 3 "" ""))
1161 (clobber (reg:CC CC_REGNUM))]
1162 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1164 if (get_attr_length (insn) == 6)
1165 return which_alternative ?
1166 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1168 return which_alternative ?
1169 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1171 [(set_attr "op_type" "RIE")
1172 (set_attr "type" "branch")
1173 (set_attr "z10prop" "z10_super_c,z10_super")
1174 (set (attr "length")
1175 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1176 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1177 ; 10 byte for clgr/jg
1179 ; And now the same two patterns as above but with a negated CC mask.
1181 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1182 ; The following instructions do a complementary access of their second
1183 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1184 (define_insn "*icmp_and_br_signed_<mode>"
1186 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1187 [(match_operand:GPR 1 "register_operand" "d,d")
1188 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1190 (label_ref (match_operand 3 "" ""))))
1191 (clobber (reg:CC CC_REGNUM))]
1192 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1194 if (get_attr_length (insn) == 6)
1195 return which_alternative ?
1196 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1198 return which_alternative ?
1199 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1201 [(set_attr "op_type" "RIE")
1202 (set_attr "type" "branch")
1203 (set_attr "z10prop" "z10_super_c,z10_super")
1204 (set (attr "length")
1205 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1206 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1207 ; 10 byte for cgr/jg
1209 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1210 ; The following instructions do a complementary access of their second
1211 ; operand (z10 only): clrj, clgrj, clr, clgr
1212 (define_insn "*icmp_and_br_unsigned_<mode>"
1214 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1215 [(match_operand:GPR 1 "register_operand" "d,d")
1216 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1218 (label_ref (match_operand 3 "" ""))))
1219 (clobber (reg:CC CC_REGNUM))]
1220 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1222 if (get_attr_length (insn) == 6)
1223 return which_alternative ?
1224 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1226 return which_alternative ?
1227 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1229 [(set_attr "op_type" "RIE")
1230 (set_attr "type" "branch")
1231 (set_attr "z10prop" "z10_super_c,z10_super")
1232 (set (attr "length")
1233 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1234 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1235 ; 10 byte for clgr/jg
1238 ;;- Move instructions.
1242 ; movti instruction pattern(s).
1245 (define_insn "movti"
1246 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1247 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1254 [(set_attr "op_type" "RSY,RSY,*,*")
1255 (set_attr "type" "lm,stm,*,*")])
1258 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1259 (match_operand:TI 1 "general_operand" ""))]
1260 "TARGET_ZARCH && reload_completed
1261 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1262 [(set (match_dup 2) (match_dup 4))
1263 (set (match_dup 3) (match_dup 5))]
1265 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1266 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1267 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1268 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1272 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1273 (match_operand:TI 1 "general_operand" ""))]
1274 "TARGET_ZARCH && reload_completed
1275 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1276 [(set (match_dup 2) (match_dup 4))
1277 (set (match_dup 3) (match_dup 5))]
1279 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1280 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1281 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1282 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1286 [(set (match_operand:TI 0 "register_operand" "")
1287 (match_operand:TI 1 "memory_operand" ""))]
1288 "TARGET_ZARCH && reload_completed
1289 && !s_operand (operands[1], VOIDmode)"
1290 [(set (match_dup 0) (match_dup 1))]
1292 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1293 addr = gen_lowpart (Pmode, addr);
1294 s390_load_address (addr, XEXP (operands[1], 0));
1295 operands[1] = replace_equiv_address (operands[1], addr);
1300 ; Patterns used for secondary reloads
1303 ; z10 provides move instructions accepting larl memory operands.
1304 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1305 ; These patterns are also used for unaligned SI and DI accesses.
1307 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1308 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1309 (match_operand:INTALL 1 "register_operand" "=d")
1310 (match_operand:P 2 "register_operand" "=&a")])]
1313 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1317 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1318 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1319 (match_operand:INTALL 1 "memory_operand" "")
1320 (match_operand:P 2 "register_operand" "=a")])]
1323 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1327 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1328 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1329 (match_operand:FPALL 1 "register_operand" "=d")
1330 (match_operand:P 2 "register_operand" "=&a")])]
1333 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1337 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1338 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1339 (match_operand:FPALL 1 "memory_operand" "")
1340 (match_operand:P 2 "register_operand" "=a")])]
1343 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1347 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1348 [(parallel [(match_operand:P 0 "register_operand" "=d")
1349 (match_operand:P 1 "larl_operand" "")
1350 (match_operand:P 2 "register_operand" "=a")])]
1353 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1357 ; Handles loading a PLUS (load address) expression
1359 (define_expand "reload<mode>_plus"
1360 [(parallel [(match_operand:P 0 "register_operand" "=a")
1361 (match_operand:P 1 "s390_plus_operand" "")
1362 (match_operand:P 2 "register_operand" "=&a")])]
1365 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1369 ; Handles assessing a non-offsetable memory address
1371 (define_expand "reload<mode>_nonoffmem_in"
1372 [(parallel [(match_operand 0 "register_operand" "")
1373 (match_operand 1 "" "")
1374 (match_operand:P 2 "register_operand" "=&a")])]
1377 gcc_assert (MEM_P (operands[1]));
1378 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1379 operands[1] = replace_equiv_address (operands[1], operands[2]);
1380 emit_move_insn (operands[0], operands[1]);
1384 (define_expand "reload<mode>_nonoffmem_out"
1385 [(parallel [(match_operand 0 "" "")
1386 (match_operand 1 "register_operand" "")
1387 (match_operand:P 2 "register_operand" "=&a")])]
1390 gcc_assert (MEM_P (operands[0]));
1391 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1392 operands[0] = replace_equiv_address (operands[0], operands[2]);
1393 emit_move_insn (operands[0], operands[1]);
1397 (define_expand "reload<mode>_PIC_addr"
1398 [(parallel [(match_operand 0 "register_operand" "=d")
1399 (match_operand 1 "larl_operand" "")
1400 (match_operand:P 2 "register_operand" "=a")])]
1403 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1404 emit_move_insn (operands[0], new_rtx);
1408 ; movdi instruction pattern(s).
1411 (define_expand "movdi"
1412 [(set (match_operand:DI 0 "general_operand" "")
1413 (match_operand:DI 1 "general_operand" ""))]
1416 /* Handle symbolic constants. */
1418 && (SYMBOLIC_CONST (operands[1])
1419 || (GET_CODE (operands[1]) == PLUS
1420 && XEXP (operands[1], 0) == pic_offset_table_rtx
1421 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1422 emit_symbolic_move (operands);
1425 (define_insn "*movdi_larl"
1426 [(set (match_operand:DI 0 "register_operand" "=d")
1427 (match_operand:DI 1 "larl_operand" "X"))]
1429 && !FP_REG_P (operands[0])"
1431 [(set_attr "op_type" "RIL")
1432 (set_attr "type" "larl")
1433 (set_attr "z10prop" "z10_super_A1")])
1435 (define_insn "*movdi_64"
1436 [(set (match_operand:DI 0 "nonimmediate_operand"
1437 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1438 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1439 (match_operand:DI 1 "general_operand"
1440 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1441 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1470 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1471 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1472 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1473 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1475 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1476 z10,*,*,*,*,*,longdisp,*,longdisp,
1478 (set_attr "z10prop" "z10_fwd_A1,
1507 [(set (match_operand:DI 0 "register_operand" "")
1508 (match_operand:DI 1 "register_operand" ""))]
1509 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1510 [(set (match_dup 2) (match_dup 3))
1511 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1512 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1513 "operands[2] = gen_lowpart (SImode, operands[0]);
1514 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1517 [(set (match_operand:DI 0 "register_operand" "")
1518 (match_operand:DI 1 "register_operand" ""))]
1519 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1520 && dead_or_set_p (insn, operands[1])"
1521 [(set (match_dup 3) (match_dup 2))
1522 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1523 (set (match_dup 4) (match_dup 2))]
1524 "operands[2] = gen_lowpart (SImode, operands[1]);
1525 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1528 [(set (match_operand:DI 0 "register_operand" "")
1529 (match_operand:DI 1 "register_operand" ""))]
1530 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1531 && !dead_or_set_p (insn, operands[1])"
1532 [(set (match_dup 3) (match_dup 2))
1533 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1534 (set (match_dup 4) (match_dup 2))
1535 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1536 "operands[2] = gen_lowpart (SImode, operands[1]);
1537 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1539 (define_insn "*movdi_31"
1540 [(set (match_operand:DI 0 "nonimmediate_operand"
1541 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1542 (match_operand:DI 1 "general_operand"
1543 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1558 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1559 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1560 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1562 ; For a load from a symbol ref we can use one of the target registers
1563 ; together with larl to load the address.
1565 [(set (match_operand:DI 0 "register_operand" "")
1566 (match_operand:DI 1 "memory_operand" ""))]
1567 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1568 && larl_operand (XEXP (operands[1], 0), SImode)"
1569 [(set (match_dup 2) (match_dup 3))
1570 (set (match_dup 0) (match_dup 1))]
1572 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1573 operands[3] = XEXP (operands[1], 0);
1574 operands[1] = replace_equiv_address (operands[1], operands[2]);
1578 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1579 (match_operand:DI 1 "general_operand" ""))]
1580 "!TARGET_ZARCH && reload_completed
1581 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1582 [(set (match_dup 2) (match_dup 4))
1583 (set (match_dup 3) (match_dup 5))]
1585 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1586 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1587 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1588 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1592 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1593 (match_operand:DI 1 "general_operand" ""))]
1594 "!TARGET_ZARCH && reload_completed
1595 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1596 [(set (match_dup 2) (match_dup 4))
1597 (set (match_dup 3) (match_dup 5))]
1599 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1600 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1601 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1602 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1606 [(set (match_operand:DI 0 "register_operand" "")
1607 (match_operand:DI 1 "memory_operand" ""))]
1608 "!TARGET_ZARCH && reload_completed
1609 && !FP_REG_P (operands[0])
1610 && !s_operand (operands[1], VOIDmode)"
1611 [(set (match_dup 0) (match_dup 1))]
1613 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1614 s390_load_address (addr, XEXP (operands[1], 0));
1615 operands[1] = replace_equiv_address (operands[1], addr);
1619 [(set (match_operand:DI 0 "register_operand" "")
1620 (mem:DI (match_operand 1 "address_operand" "")))]
1622 && !FP_REG_P (operands[0])
1623 && GET_CODE (operands[1]) == SYMBOL_REF
1624 && CONSTANT_POOL_ADDRESS_P (operands[1])
1625 && get_pool_mode (operands[1]) == DImode
1626 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1627 [(set (match_dup 0) (match_dup 2))]
1628 "operands[2] = get_pool_constant (operands[1]);")
1630 (define_insn "*la_64"
1631 [(set (match_operand:DI 0 "register_operand" "=d,d")
1632 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1637 [(set_attr "op_type" "RX,RXY")
1638 (set_attr "type" "la")
1639 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1643 [(set (match_operand:DI 0 "register_operand" "")
1644 (match_operand:QI 1 "address_operand" ""))
1645 (clobber (reg:CC CC_REGNUM))])]
1647 && preferred_la_operand_p (operands[1], const0_rtx)"
1648 [(set (match_dup 0) (match_dup 1))]
1652 [(set (match_operand:DI 0 "register_operand" "")
1653 (match_operand:DI 1 "register_operand" ""))
1656 (plus:DI (match_dup 0)
1657 (match_operand:DI 2 "nonmemory_operand" "")))
1658 (clobber (reg:CC CC_REGNUM))])]
1660 && !reg_overlap_mentioned_p (operands[0], operands[2])
1661 && preferred_la_operand_p (operands[1], operands[2])"
1662 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1666 ; movsi instruction pattern(s).
1669 (define_expand "movsi"
1670 [(set (match_operand:SI 0 "general_operand" "")
1671 (match_operand:SI 1 "general_operand" ""))]
1674 /* Handle symbolic constants. */
1676 && (SYMBOLIC_CONST (operands[1])
1677 || (GET_CODE (operands[1]) == PLUS
1678 && XEXP (operands[1], 0) == pic_offset_table_rtx
1679 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1680 emit_symbolic_move (operands);
1683 (define_insn "*movsi_larl"
1684 [(set (match_operand:SI 0 "register_operand" "=d")
1685 (match_operand:SI 1 "larl_operand" "X"))]
1686 "!TARGET_64BIT && TARGET_CPU_ZARCH
1687 && !FP_REG_P (operands[0])"
1689 [(set_attr "op_type" "RIL")
1690 (set_attr "type" "larl")
1691 (set_attr "z10prop" "z10_fwd_A1")])
1693 (define_insn "*movsi_zarch"
1694 [(set (match_operand:SI 0 "nonimmediate_operand"
1695 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1696 (match_operand:SI 1 "general_operand"
1697 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1722 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1723 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1724 (set_attr "type" "*,
1746 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1747 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1748 (set_attr "z10prop" "z10_fwd_A1,
1771 (define_insn "*movsi_esa"
1772 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1773 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1787 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1788 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1789 (set_attr "z10prop" "z10_fwd_A1,
1803 [(set (match_operand:SI 0 "register_operand" "")
1804 (mem:SI (match_operand 1 "address_operand" "")))]
1805 "!FP_REG_P (operands[0])
1806 && GET_CODE (operands[1]) == SYMBOL_REF
1807 && CONSTANT_POOL_ADDRESS_P (operands[1])
1808 && get_pool_mode (operands[1]) == SImode
1809 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1810 [(set (match_dup 0) (match_dup 2))]
1811 "operands[2] = get_pool_constant (operands[1]);")
1813 (define_insn "*la_31"
1814 [(set (match_operand:SI 0 "register_operand" "=d,d")
1815 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1816 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1820 [(set_attr "op_type" "RX,RXY")
1821 (set_attr "type" "la")
1822 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1826 [(set (match_operand:SI 0 "register_operand" "")
1827 (match_operand:QI 1 "address_operand" ""))
1828 (clobber (reg:CC CC_REGNUM))])]
1830 && preferred_la_operand_p (operands[1], const0_rtx)"
1831 [(set (match_dup 0) (match_dup 1))]
1835 [(set (match_operand:SI 0 "register_operand" "")
1836 (match_operand:SI 1 "register_operand" ""))
1839 (plus:SI (match_dup 0)
1840 (match_operand:SI 2 "nonmemory_operand" "")))
1841 (clobber (reg:CC CC_REGNUM))])]
1843 && !reg_overlap_mentioned_p (operands[0], operands[2])
1844 && preferred_la_operand_p (operands[1], operands[2])"
1845 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1848 (define_insn "*la_31_and"
1849 [(set (match_operand:SI 0 "register_operand" "=d,d")
1850 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1851 (const_int 2147483647)))]
1856 [(set_attr "op_type" "RX,RXY")
1857 (set_attr "type" "la")
1858 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1860 (define_insn_and_split "*la_31_and_cc"
1861 [(set (match_operand:SI 0 "register_operand" "=d")
1862 (and:SI (match_operand:QI 1 "address_operand" "p")
1863 (const_int 2147483647)))
1864 (clobber (reg:CC CC_REGNUM))]
1867 "&& reload_completed"
1869 (and:SI (match_dup 1) (const_int 2147483647)))]
1871 [(set_attr "op_type" "RX")
1872 (set_attr "type" "la")])
1874 (define_insn "force_la_31"
1875 [(set (match_operand:SI 0 "register_operand" "=d,d")
1876 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1877 (use (const_int 0))]
1882 [(set_attr "op_type" "RX")
1883 (set_attr "type" "la")
1884 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1887 ; movhi instruction pattern(s).
1890 (define_expand "movhi"
1891 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1892 (match_operand:HI 1 "general_operand" ""))]
1895 /* Make it explicit that loading a register from memory
1896 always sign-extends (at least) to SImode. */
1897 if (optimize && can_create_pseudo_p ()
1898 && register_operand (operands[0], VOIDmode)
1899 && GET_CODE (operands[1]) == MEM)
1901 rtx tmp = gen_reg_rtx (SImode);
1902 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1903 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1904 operands[1] = gen_lowpart (HImode, tmp);
1908 (define_insn "*movhi"
1909 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1910 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1922 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1923 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1924 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1925 (set_attr "z10prop" "z10_fr_E1,
1936 [(set (match_operand:HI 0 "register_operand" "")
1937 (mem:HI (match_operand 1 "address_operand" "")))]
1938 "GET_CODE (operands[1]) == SYMBOL_REF
1939 && CONSTANT_POOL_ADDRESS_P (operands[1])
1940 && get_pool_mode (operands[1]) == HImode
1941 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1942 [(set (match_dup 0) (match_dup 2))]
1943 "operands[2] = get_pool_constant (operands[1]);")
1946 ; movqi instruction pattern(s).
1949 (define_expand "movqi"
1950 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1951 (match_operand:QI 1 "general_operand" ""))]
1954 /* On z/Architecture, zero-extending from memory to register
1955 is just as fast as a QImode load. */
1956 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1957 && register_operand (operands[0], VOIDmode)
1958 && GET_CODE (operands[1]) == MEM)
1960 rtx tmp = gen_reg_rtx (DImode);
1961 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1962 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1963 operands[1] = gen_lowpart (QImode, tmp);
1967 (define_insn "*movqi"
1968 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1969 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1981 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1982 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1983 (set_attr "z10prop" "z10_fr_E1,
1994 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1995 (mem:QI (match_operand 1 "address_operand" "")))]
1996 "GET_CODE (operands[1]) == SYMBOL_REF
1997 && CONSTANT_POOL_ADDRESS_P (operands[1])
1998 && get_pool_mode (operands[1]) == QImode
1999 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2000 [(set (match_dup 0) (match_dup 2))]
2001 "operands[2] = get_pool_constant (operands[1]);")
2004 ; movstrictqi instruction pattern(s).
2007 (define_insn "*movstrictqi"
2008 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2009 (match_operand:QI 1 "memory_operand" "R,T"))]
2014 [(set_attr "op_type" "RX,RXY")
2015 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2018 ; movstricthi instruction pattern(s).
2021 (define_insn "*movstricthi"
2022 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2023 (match_operand:HI 1 "memory_operand" "Q,S"))
2024 (clobber (reg:CC CC_REGNUM))]
2029 [(set_attr "op_type" "RS,RSY")
2030 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2033 ; movstrictsi instruction pattern(s).
2036 (define_insn "movstrictsi"
2037 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2038 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2045 [(set_attr "op_type" "RR,RX,RXY,RRE")
2046 (set_attr "type" "lr,load,load,*")
2047 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2050 ; mov(tf|td) instruction pattern(s).
2053 (define_expand "mov<mode>"
2054 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2055 (match_operand:TD_TF 1 "general_operand" ""))]
2059 (define_insn "*mov<mode>_64"
2060 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
2061 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
2072 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2073 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2074 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2076 (define_insn "*mov<mode>_31"
2077 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2078 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2085 [(set_attr "op_type" "RRE,RRE,*,*")
2086 (set_attr "type" "fsimptf,fsimptf,*,*")
2087 (set_attr "cpu_facility" "z196,*,*,*")])
2089 ; TFmode in GPRs splitters
2092 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2093 (match_operand:TD_TF 1 "general_operand" ""))]
2094 "TARGET_ZARCH && reload_completed
2095 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2096 [(set (match_dup 2) (match_dup 4))
2097 (set (match_dup 3) (match_dup 5))]
2099 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2100 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2101 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2102 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2106 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2107 (match_operand:TD_TF 1 "general_operand" ""))]
2108 "TARGET_ZARCH && reload_completed
2109 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2110 [(set (match_dup 2) (match_dup 4))
2111 (set (match_dup 3) (match_dup 5))]
2113 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2114 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2115 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2116 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2120 [(set (match_operand:TD_TF 0 "register_operand" "")
2121 (match_operand:TD_TF 1 "memory_operand" ""))]
2122 "TARGET_ZARCH && reload_completed
2123 && !FP_REG_P (operands[0])
2124 && !s_operand (operands[1], VOIDmode)"
2125 [(set (match_dup 0) (match_dup 1))]
2127 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2128 addr = gen_lowpart (Pmode, addr);
2129 s390_load_address (addr, XEXP (operands[1], 0));
2130 operands[1] = replace_equiv_address (operands[1], addr);
2133 ; TFmode in BFPs splitters
2136 [(set (match_operand:TD_TF 0 "register_operand" "")
2137 (match_operand:TD_TF 1 "memory_operand" ""))]
2138 "reload_completed && offsettable_memref_p (operands[1])
2139 && FP_REG_P (operands[0])"
2140 [(set (match_dup 2) (match_dup 4))
2141 (set (match_dup 3) (match_dup 5))]
2143 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2145 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2147 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2148 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2152 [(set (match_operand:TD_TF 0 "memory_operand" "")
2153 (match_operand:TD_TF 1 "register_operand" ""))]
2154 "reload_completed && offsettable_memref_p (operands[0])
2155 && FP_REG_P (operands[1])"
2156 [(set (match_dup 2) (match_dup 4))
2157 (set (match_dup 3) (match_dup 5))]
2159 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2160 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2161 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2163 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2168 ; mov(df|dd) instruction pattern(s).
2171 (define_expand "mov<mode>"
2172 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2173 (match_operand:DD_DF 1 "general_operand" ""))]
2177 (define_insn "*mov<mode>_64dfp"
2178 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2179 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2180 (match_operand:DD_DF 1 "general_operand"
2181 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2196 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2197 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2198 fstoredf,fstoredf,*,lr,load,store")
2199 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2200 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2202 (define_insn "*mov<mode>_64"
2203 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2204 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2217 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2218 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2219 fstore<mode>,fstore<mode>,*,lr,load,store")
2220 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2221 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2223 (define_insn "*mov<mode>_31"
2224 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2225 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2226 (match_operand:DD_DF 1 "general_operand"
2227 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2242 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2243 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2244 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2245 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2248 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2249 (match_operand:DD_DF 1 "general_operand" ""))]
2250 "!TARGET_ZARCH && reload_completed
2251 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2252 [(set (match_dup 2) (match_dup 4))
2253 (set (match_dup 3) (match_dup 5))]
2255 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2256 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2257 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2258 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2262 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2263 (match_operand:DD_DF 1 "general_operand" ""))]
2264 "!TARGET_ZARCH && reload_completed
2265 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2266 [(set (match_dup 2) (match_dup 4))
2267 (set (match_dup 3) (match_dup 5))]
2269 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2270 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2271 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2272 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2276 [(set (match_operand:DD_DF 0 "register_operand" "")
2277 (match_operand:DD_DF 1 "memory_operand" ""))]
2278 "!TARGET_ZARCH && reload_completed
2279 && !FP_REG_P (operands[0])
2280 && !s_operand (operands[1], VOIDmode)"
2281 [(set (match_dup 0) (match_dup 1))]
2283 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2284 s390_load_address (addr, XEXP (operands[1], 0));
2285 operands[1] = replace_equiv_address (operands[1], addr);
2289 ; mov(sf|sd) instruction pattern(s).
2292 (define_insn "mov<mode>"
2293 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2294 "=f,f,f,f,R,T,d,d,d,d,R,T")
2295 (match_operand:SD_SF 1 "general_operand"
2296 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2311 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2312 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2313 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2314 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2315 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2318 ; movcc instruction pattern
2321 (define_insn "movcc"
2322 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2323 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2333 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2334 (set_attr "type" "lr,*,*,load,load,store,store")
2335 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2336 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2339 ; Block move (MVC) patterns.
2343 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2344 (match_operand:BLK 1 "memory_operand" "Q"))
2345 (use (match_operand 2 "const_int_operand" "n"))]
2346 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2347 "mvc\t%O0(%2,%R0),%S1"
2348 [(set_attr "op_type" "SS")])
2350 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2351 ; order to have it implemented with mvc.
2354 [(set (match_operand:QI 0 "memory_operand" "")
2355 (match_operand:QI 1 "memory_operand" ""))]
2358 [(set (match_dup 0) (match_dup 1))
2359 (use (const_int 1))])]
2361 operands[0] = adjust_address (operands[0], BLKmode, 0);
2362 operands[1] = adjust_address (operands[1], BLKmode, 0);
2368 [(set (match_operand:BLK 0 "memory_operand" "")
2369 (match_operand:BLK 1 "memory_operand" ""))
2370 (use (match_operand 2 "const_int_operand" ""))])
2372 [(set (match_operand:BLK 3 "memory_operand" "")
2373 (match_operand:BLK 4 "memory_operand" ""))
2374 (use (match_operand 5 "const_int_operand" ""))])]
2375 "s390_offset_p (operands[0], operands[3], operands[2])
2376 && s390_offset_p (operands[1], operands[4], operands[2])
2377 && !s390_overlap_p (operands[0], operands[1],
2378 INTVAL (operands[2]) + INTVAL (operands[5]))
2379 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2381 [(set (match_dup 6) (match_dup 7))
2382 (use (match_dup 8))])]
2383 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2384 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2385 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2389 ; load_multiple pattern(s).
2391 ; ??? Due to reload problems with replacing registers inside match_parallel
2392 ; we currently support load_multiple/store_multiple only after reload.
2395 (define_expand "load_multiple"
2396 [(match_par_dup 3 [(set (match_operand 0 "" "")
2397 (match_operand 1 "" ""))
2398 (use (match_operand 2 "" ""))])]
2407 /* Support only loading a constant number of fixed-point registers from
2408 memory and only bother with this if more than two */
2409 if (GET_CODE (operands[2]) != CONST_INT
2410 || INTVAL (operands[2]) < 2
2411 || INTVAL (operands[2]) > 16
2412 || GET_CODE (operands[1]) != MEM
2413 || GET_CODE (operands[0]) != REG
2414 || REGNO (operands[0]) >= 16)
2417 count = INTVAL (operands[2]);
2418 regno = REGNO (operands[0]);
2419 mode = GET_MODE (operands[0]);
2420 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2423 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2424 if (!can_create_pseudo_p ())
2426 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2428 from = XEXP (operands[1], 0);
2431 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2432 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2433 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2435 from = XEXP (XEXP (operands[1], 0), 0);
2436 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2443 from = force_reg (Pmode, XEXP (operands[1], 0));
2447 for (i = 0; i < count; i++)
2448 XVECEXP (operands[3], 0, i)
2449 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2450 change_address (operands[1], mode,
2451 plus_constant (Pmode, from,
2452 off + i * GET_MODE_SIZE (mode))));
2455 (define_insn "*load_multiple_di"
2456 [(match_parallel 0 "load_multiple_operation"
2457 [(set (match_operand:DI 1 "register_operand" "=r")
2458 (match_operand:DI 2 "s_operand" "QS"))])]
2459 "reload_completed && TARGET_ZARCH"
2461 int words = XVECLEN (operands[0], 0);
2462 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2463 return "lmg\t%1,%0,%S2";
2465 [(set_attr "op_type" "RSY")
2466 (set_attr "type" "lm")])
2468 (define_insn "*load_multiple_si"
2469 [(match_parallel 0 "load_multiple_operation"
2470 [(set (match_operand:SI 1 "register_operand" "=r,r")
2471 (match_operand:SI 2 "s_operand" "Q,S"))])]
2474 int words = XVECLEN (operands[0], 0);
2475 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2476 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2478 [(set_attr "op_type" "RS,RSY")
2479 (set_attr "type" "lm")])
2482 ; store multiple pattern(s).
2485 (define_expand "store_multiple"
2486 [(match_par_dup 3 [(set (match_operand 0 "" "")
2487 (match_operand 1 "" ""))
2488 (use (match_operand 2 "" ""))])]
2497 /* Support only storing a constant number of fixed-point registers to
2498 memory and only bother with this if more than two. */
2499 if (GET_CODE (operands[2]) != CONST_INT
2500 || INTVAL (operands[2]) < 2
2501 || INTVAL (operands[2]) > 16
2502 || GET_CODE (operands[0]) != MEM
2503 || GET_CODE (operands[1]) != REG
2504 || REGNO (operands[1]) >= 16)
2507 count = INTVAL (operands[2]);
2508 regno = REGNO (operands[1]);
2509 mode = GET_MODE (operands[1]);
2510 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2513 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2515 if (!can_create_pseudo_p ())
2517 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2519 to = XEXP (operands[0], 0);
2522 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2523 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2524 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2526 to = XEXP (XEXP (operands[0], 0), 0);
2527 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2534 to = force_reg (Pmode, XEXP (operands[0], 0));
2538 for (i = 0; i < count; i++)
2539 XVECEXP (operands[3], 0, i)
2540 = gen_rtx_SET (VOIDmode,
2541 change_address (operands[0], mode,
2542 plus_constant (Pmode, to,
2543 off + i * GET_MODE_SIZE (mode))),
2544 gen_rtx_REG (mode, regno + i));
2547 (define_insn "*store_multiple_di"
2548 [(match_parallel 0 "store_multiple_operation"
2549 [(set (match_operand:DI 1 "s_operand" "=QS")
2550 (match_operand:DI 2 "register_operand" "r"))])]
2551 "reload_completed && TARGET_ZARCH"
2553 int words = XVECLEN (operands[0], 0);
2554 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2555 return "stmg\t%2,%0,%S1";
2557 [(set_attr "op_type" "RSY")
2558 (set_attr "type" "stm")])
2561 (define_insn "*store_multiple_si"
2562 [(match_parallel 0 "store_multiple_operation"
2563 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2564 (match_operand:SI 2 "register_operand" "r,r"))])]
2567 int words = XVECLEN (operands[0], 0);
2568 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2569 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2571 [(set_attr "op_type" "RS,RSY")
2572 (set_attr "type" "stm")])
2575 ;; String instructions.
2578 (define_insn "*execute_rl"
2579 [(match_parallel 0 "execute_operation"
2580 [(unspec [(match_operand 1 "register_operand" "a")
2581 (match_operand 2 "" "")
2582 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2583 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2584 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2586 [(set_attr "op_type" "RIL")
2587 (set_attr "type" "cs")])
2589 (define_insn "*execute"
2590 [(match_parallel 0 "execute_operation"
2591 [(unspec [(match_operand 1 "register_operand" "a")
2592 (match_operand:BLK 2 "memory_operand" "R")
2593 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2594 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2595 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2597 [(set_attr "op_type" "RX")
2598 (set_attr "type" "cs")])
2602 ; strlenM instruction pattern(s).
2605 (define_expand "strlen<mode>"
2606 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2609 (unspec:P [(const_int 0)
2610 (match_operand:BLK 1 "memory_operand" "")
2612 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2613 (clobber (scratch:P))
2614 (clobber (reg:CC CC_REGNUM))])
2616 [(set (match_operand:P 0 "register_operand" "")
2617 (minus:P (match_dup 4) (match_dup 5)))
2618 (clobber (reg:CC CC_REGNUM))])]
2621 operands[4] = gen_reg_rtx (Pmode);
2622 operands[5] = gen_reg_rtx (Pmode);
2623 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2624 operands[1] = replace_equiv_address (operands[1], operands[5]);
2627 (define_insn "*strlen<mode>"
2628 [(set (match_operand:P 0 "register_operand" "=a")
2629 (unspec:P [(match_operand:P 2 "general_operand" "0")
2630 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2632 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2633 (clobber (match_scratch:P 1 "=a"))
2634 (clobber (reg:CC CC_REGNUM))]
2636 "srst\t%0,%1\;jo\t.-4"
2637 [(set_attr "length" "8")
2638 (set_attr "type" "vs")])
2641 ; cmpstrM instruction pattern(s).
2644 (define_expand "cmpstrsi"
2645 [(set (reg:SI 0) (const_int 0))
2647 [(clobber (match_operand 3 "" ""))
2648 (clobber (match_dup 4))
2649 (set (reg:CCU CC_REGNUM)
2650 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2651 (match_operand:BLK 2 "memory_operand" "")))
2654 [(set (match_operand:SI 0 "register_operand" "=d")
2655 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
2656 (clobber (reg:CC CC_REGNUM))])]
2659 /* As the result of CMPINT is inverted compared to what we need,
2660 we have to swap the operands. */
2661 rtx op1 = operands[2];
2662 rtx op2 = operands[1];
2663 rtx addr1 = gen_reg_rtx (Pmode);
2664 rtx addr2 = gen_reg_rtx (Pmode);
2666 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2667 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2668 operands[1] = replace_equiv_address_nv (op1, addr1);
2669 operands[2] = replace_equiv_address_nv (op2, addr2);
2670 operands[3] = addr1;
2671 operands[4] = addr2;
2674 (define_insn "*cmpstr<mode>"
2675 [(clobber (match_operand:P 0 "register_operand" "=d"))
2676 (clobber (match_operand:P 1 "register_operand" "=d"))
2677 (set (reg:CCU CC_REGNUM)
2678 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2679 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2682 "clst\t%0,%1\;jo\t.-4"
2683 [(set_attr "length" "8")
2684 (set_attr "type" "vs")])
2687 ; movstr instruction pattern.
2690 (define_expand "movstr"
2691 [(set (reg:SI 0) (const_int 0))
2693 [(clobber (match_dup 3))
2694 (set (match_operand:BLK 1 "memory_operand" "")
2695 (match_operand:BLK 2 "memory_operand" ""))
2696 (set (match_operand 0 "register_operand" "")
2697 (unspec [(match_dup 1)
2699 (reg:SI 0)] UNSPEC_MVST))
2700 (clobber (reg:CC CC_REGNUM))])]
2703 rtx addr1 = gen_reg_rtx (Pmode);
2704 rtx addr2 = gen_reg_rtx (Pmode);
2706 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2707 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2708 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2709 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2710 operands[3] = addr2;
2713 (define_insn "*movstr"
2714 [(clobber (match_operand:P 2 "register_operand" "=d"))
2715 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2716 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2717 (set (match_operand:P 0 "register_operand" "=d")
2718 (unspec [(mem:BLK (match_dup 1))
2719 (mem:BLK (match_dup 3))
2720 (reg:SI 0)] UNSPEC_MVST))
2721 (clobber (reg:CC CC_REGNUM))]
2723 "mvst\t%1,%2\;jo\t.-4"
2724 [(set_attr "length" "8")
2725 (set_attr "type" "vs")])
2729 ; movmemM instruction pattern(s).
2732 (define_expand "movmem<mode>"
2733 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2734 (match_operand:BLK 1 "memory_operand" "")) ; source
2735 (use (match_operand:GPR 2 "general_operand" "")) ; count
2736 (match_operand 3 "" "")]
2739 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2745 ; Move a block that is up to 256 bytes in length.
2746 ; The block length is taken as (operands[2] % 256) + 1.
2748 (define_expand "movmem_short"
2750 [(set (match_operand:BLK 0 "memory_operand" "")
2751 (match_operand:BLK 1 "memory_operand" ""))
2752 (use (match_operand 2 "nonmemory_operand" ""))
2753 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2754 (clobber (match_dup 3))])]
2756 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2758 (define_insn "*movmem_short"
2759 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2760 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2761 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2762 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2763 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2764 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2766 [(set_attr "type" "cs")
2767 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2770 [(set (match_operand:BLK 0 "memory_operand" "")
2771 (match_operand:BLK 1 "memory_operand" ""))
2772 (use (match_operand 2 "const_int_operand" ""))
2773 (use (match_operand 3 "immediate_operand" ""))
2774 (clobber (scratch))]
2777 [(set (match_dup 0) (match_dup 1))
2778 (use (match_dup 2))])]
2779 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2782 [(set (match_operand:BLK 0 "memory_operand" "")
2783 (match_operand:BLK 1 "memory_operand" ""))
2784 (use (match_operand 2 "register_operand" ""))
2785 (use (match_operand 3 "memory_operand" ""))
2786 (clobber (scratch))]
2789 [(unspec [(match_dup 2) (match_dup 3)
2790 (const_int 0)] UNSPEC_EXECUTE)
2791 (set (match_dup 0) (match_dup 1))
2792 (use (const_int 1))])]
2796 [(set (match_operand:BLK 0 "memory_operand" "")
2797 (match_operand:BLK 1 "memory_operand" ""))
2798 (use (match_operand 2 "register_operand" ""))
2799 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2800 (clobber (scratch))]
2801 "TARGET_Z10 && reload_completed"
2803 [(unspec [(match_dup 2) (const_int 0)
2804 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2805 (set (match_dup 0) (match_dup 1))
2806 (use (const_int 1))])]
2807 "operands[3] = gen_label_rtx ();")
2810 [(set (match_operand:BLK 0 "memory_operand" "")
2811 (match_operand:BLK 1 "memory_operand" ""))
2812 (use (match_operand 2 "register_operand" ""))
2813 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2814 (clobber (match_operand 3 "register_operand" ""))]
2815 "reload_completed && TARGET_CPU_ZARCH"
2816 [(set (match_dup 3) (label_ref (match_dup 4)))
2818 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2819 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2820 (set (match_dup 0) (match_dup 1))
2821 (use (const_int 1))])]
2822 "operands[4] = gen_label_rtx ();")
2824 ; Move a block of arbitrary length.
2826 (define_expand "movmem_long"
2828 [(clobber (match_dup 2))
2829 (clobber (match_dup 3))
2830 (set (match_operand:BLK 0 "memory_operand" "")
2831 (match_operand:BLK 1 "memory_operand" ""))
2832 (use (match_operand 2 "general_operand" ""))
2834 (clobber (reg:CC CC_REGNUM))])]
2837 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2838 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2839 rtx reg0 = gen_reg_rtx (dreg_mode);
2840 rtx reg1 = gen_reg_rtx (dreg_mode);
2841 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2842 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2843 rtx len0 = gen_lowpart (Pmode, reg0);
2844 rtx len1 = gen_lowpart (Pmode, reg1);
2846 emit_clobber (reg0);
2847 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2848 emit_move_insn (len0, operands[2]);
2850 emit_clobber (reg1);
2851 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2852 emit_move_insn (len1, operands[2]);
2854 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2855 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2860 (define_insn "*movmem_long"
2861 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2862 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2863 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2864 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2867 (clobber (reg:CC CC_REGNUM))]
2868 "TARGET_64BIT || !TARGET_ZARCH"
2869 "mvcle\t%0,%1,0\;jo\t.-4"
2870 [(set_attr "length" "8")
2871 (set_attr "type" "vs")])
2873 (define_insn "*movmem_long_31z"
2874 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2875 (clobber (match_operand:TI 1 "register_operand" "=d"))
2876 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2877 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2880 (clobber (reg:CC CC_REGNUM))]
2881 "!TARGET_64BIT && TARGET_ZARCH"
2882 "mvcle\t%0,%1,0\;jo\t.-4"
2883 [(set_attr "length" "8")
2884 (set_attr "type" "vs")])
2891 (define_expand "signbit<mode>2"
2892 [(set (reg:CCZ CC_REGNUM)
2893 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2896 (set (match_operand:SI 0 "register_operand" "=d")
2897 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2900 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2903 (define_expand "isinf<mode>2"
2904 [(set (reg:CCZ CC_REGNUM)
2905 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2908 (set (match_operand:SI 0 "register_operand" "=d")
2909 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
2912 operands[2] = GEN_INT (S390_TDC_INFINITY);
2915 (define_insn_and_split "*cc_to_int"
2916 [(set (match_operand:SI 0 "register_operand" "=d")
2917 (unspec:SI [(match_operand 1 "register_operand" "0")]
2922 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2924 ; This insn is used to generate all variants of the Test Data Class
2925 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2926 ; is the register to be tested and the second one is the bit mask
2927 ; specifying the required test(s).
2929 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2930 (define_insn "*TDC_insn_<mode>"
2931 [(set (reg:CCZ CC_REGNUM)
2932 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2933 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2935 "t<_d>c<xde><bt>\t%0,%1"
2936 [(set_attr "op_type" "RXE")
2937 (set_attr "type" "fsimp<mode>")])
2942 ; setmemM instruction pattern(s).
2945 (define_expand "setmem<mode>"
2946 [(set (match_operand:BLK 0 "memory_operand" "")
2947 (match_operand:QI 2 "general_operand" ""))
2948 (use (match_operand:GPR 1 "general_operand" ""))
2949 (match_operand 3 "" "")]
2951 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2953 ; Clear a block that is up to 256 bytes in length.
2954 ; The block length is taken as (operands[1] % 256) + 1.
2956 (define_expand "clrmem_short"
2958 [(set (match_operand:BLK 0 "memory_operand" "")
2960 (use (match_operand 1 "nonmemory_operand" ""))
2961 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2962 (clobber (match_dup 2))
2963 (clobber (reg:CC CC_REGNUM))])]
2965 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2967 (define_insn "*clrmem_short"
2968 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2970 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2971 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2972 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2973 (clobber (reg:CC CC_REGNUM))]
2974 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2976 [(set_attr "type" "cs")
2977 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
2980 [(set (match_operand:BLK 0 "memory_operand" "")
2982 (use (match_operand 1 "const_int_operand" ""))
2983 (use (match_operand 2 "immediate_operand" ""))
2985 (clobber (reg:CC CC_REGNUM))]
2988 [(set (match_dup 0) (const_int 0))
2990 (clobber (reg:CC CC_REGNUM))])]
2991 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2994 [(set (match_operand:BLK 0 "memory_operand" "")
2996 (use (match_operand 1 "register_operand" ""))
2997 (use (match_operand 2 "memory_operand" ""))
2999 (clobber (reg:CC CC_REGNUM))]
3002 [(unspec [(match_dup 1) (match_dup 2)
3003 (const_int 0)] UNSPEC_EXECUTE)
3004 (set (match_dup 0) (const_int 0))
3006 (clobber (reg:CC CC_REGNUM))])]
3010 [(set (match_operand:BLK 0 "memory_operand" "")
3012 (use (match_operand 1 "register_operand" ""))
3013 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3015 (clobber (reg:CC CC_REGNUM))]
3016 "TARGET_Z10 && reload_completed"
3018 [(unspec [(match_dup 1) (const_int 0)
3019 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3020 (set (match_dup 0) (const_int 0))
3022 (clobber (reg:CC CC_REGNUM))])]
3023 "operands[3] = gen_label_rtx ();")
3026 [(set (match_operand:BLK 0 "memory_operand" "")
3028 (use (match_operand 1 "register_operand" ""))
3029 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3030 (clobber (match_operand 2 "register_operand" ""))
3031 (clobber (reg:CC CC_REGNUM))]
3032 "reload_completed && TARGET_CPU_ZARCH"
3033 [(set (match_dup 2) (label_ref (match_dup 3)))
3035 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3036 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3037 (set (match_dup 0) (const_int 0))
3039 (clobber (reg:CC CC_REGNUM))])]
3040 "operands[3] = gen_label_rtx ();")
3042 ; Initialize a block of arbitrary length with (operands[2] % 256).
3044 (define_expand "setmem_long"
3046 [(clobber (match_dup 1))
3047 (set (match_operand:BLK 0 "memory_operand" "")
3048 (match_operand 2 "shift_count_or_setmem_operand" ""))
3049 (use (match_operand 1 "general_operand" ""))
3051 (clobber (reg:CC CC_REGNUM))])]
3054 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3055 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3056 rtx reg0 = gen_reg_rtx (dreg_mode);
3057 rtx reg1 = gen_reg_rtx (dreg_mode);
3058 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3059 rtx len0 = gen_lowpart (Pmode, reg0);
3061 emit_clobber (reg0);
3062 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3063 emit_move_insn (len0, operands[1]);
3065 emit_move_insn (reg1, const0_rtx);
3067 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3072 (define_insn "*setmem_long"
3073 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3074 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3075 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3077 (use (match_operand:<DBL> 1 "register_operand" "d"))
3078 (clobber (reg:CC CC_REGNUM))]
3079 "TARGET_64BIT || !TARGET_ZARCH"
3080 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3081 [(set_attr "length" "8")
3082 (set_attr "type" "vs")])
3084 (define_insn "*setmem_long_and"
3085 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3086 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3087 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3088 (match_operand 4 "const_int_operand" "n")))
3090 (use (match_operand:<DBL> 1 "register_operand" "d"))
3091 (clobber (reg:CC CC_REGNUM))]
3092 "(TARGET_64BIT || !TARGET_ZARCH) &&
3093 (INTVAL (operands[4]) & 255) == 255"
3094 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3095 [(set_attr "length" "8")
3096 (set_attr "type" "vs")])
3098 (define_insn "*setmem_long_31z"
3099 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3100 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3101 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3103 (use (match_operand:TI 1 "register_operand" "d"))
3104 (clobber (reg:CC CC_REGNUM))]
3105 "!TARGET_64BIT && TARGET_ZARCH"
3106 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3107 [(set_attr "length" "8")
3108 (set_attr "type" "vs")])
3111 ; cmpmemM instruction pattern(s).
3114 (define_expand "cmpmemsi"
3115 [(set (match_operand:SI 0 "register_operand" "")
3116 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3117 (match_operand:BLK 2 "memory_operand" "") ) )
3118 (use (match_operand:SI 3 "general_operand" ""))
3119 (use (match_operand:SI 4 "" ""))]
3122 if (s390_expand_cmpmem (operands[0], operands[1],
3123 operands[2], operands[3]))
3129 ; Compare a block that is up to 256 bytes in length.
3130 ; The block length is taken as (operands[2] % 256) + 1.
3132 (define_expand "cmpmem_short"
3134 [(set (reg:CCU CC_REGNUM)
3135 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3136 (match_operand:BLK 1 "memory_operand" "")))
3137 (use (match_operand 2 "nonmemory_operand" ""))
3138 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3139 (clobber (match_dup 3))])]
3141 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3143 (define_insn "*cmpmem_short"
3144 [(set (reg:CCU CC_REGNUM)
3145 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3146 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3147 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3148 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3149 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3150 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3152 [(set_attr "type" "cs")
3153 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3156 [(set (reg:CCU CC_REGNUM)
3157 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3158 (match_operand:BLK 1 "memory_operand" "")))
3159 (use (match_operand 2 "const_int_operand" ""))
3160 (use (match_operand 3 "immediate_operand" ""))
3161 (clobber (scratch))]
3164 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3165 (use (match_dup 2))])]
3166 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3169 [(set (reg:CCU CC_REGNUM)
3170 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3171 (match_operand:BLK 1 "memory_operand" "")))
3172 (use (match_operand 2 "register_operand" ""))
3173 (use (match_operand 3 "memory_operand" ""))
3174 (clobber (scratch))]
3177 [(unspec [(match_dup 2) (match_dup 3)
3178 (const_int 0)] UNSPEC_EXECUTE)
3179 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3180 (use (const_int 1))])]
3184 [(set (reg:CCU CC_REGNUM)
3185 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3186 (match_operand:BLK 1 "memory_operand" "")))
3187 (use (match_operand 2 "register_operand" ""))
3188 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3189 (clobber (scratch))]
3190 "TARGET_Z10 && reload_completed"
3192 [(unspec [(match_dup 2) (const_int 0)
3193 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3194 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3195 (use (const_int 1))])]
3196 "operands[4] = gen_label_rtx ();")
3199 [(set (reg:CCU CC_REGNUM)
3200 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3201 (match_operand:BLK 1 "memory_operand" "")))
3202 (use (match_operand 2 "register_operand" ""))
3203 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3204 (clobber (match_operand 3 "register_operand" ""))]
3205 "reload_completed && TARGET_CPU_ZARCH"
3206 [(set (match_dup 3) (label_ref (match_dup 4)))
3208 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3209 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3210 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3211 (use (const_int 1))])]
3212 "operands[4] = gen_label_rtx ();")
3214 ; Compare a block of arbitrary length.
3216 (define_expand "cmpmem_long"
3218 [(clobber (match_dup 2))
3219 (clobber (match_dup 3))
3220 (set (reg:CCU CC_REGNUM)
3221 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3222 (match_operand:BLK 1 "memory_operand" "")))
3223 (use (match_operand 2 "general_operand" ""))
3224 (use (match_dup 3))])]
3227 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3228 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3229 rtx reg0 = gen_reg_rtx (dreg_mode);
3230 rtx reg1 = gen_reg_rtx (dreg_mode);
3231 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3232 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3233 rtx len0 = gen_lowpart (Pmode, reg0);
3234 rtx len1 = gen_lowpart (Pmode, reg1);
3236 emit_clobber (reg0);
3237 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3238 emit_move_insn (len0, operands[2]);
3240 emit_clobber (reg1);
3241 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3242 emit_move_insn (len1, operands[2]);
3244 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3245 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3250 (define_insn "*cmpmem_long"
3251 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3252 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3253 (set (reg:CCU CC_REGNUM)
3254 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3255 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3257 (use (match_dup 3))]
3258 "TARGET_64BIT || !TARGET_ZARCH"
3259 "clcle\t%0,%1,0\;jo\t.-4"
3260 [(set_attr "length" "8")
3261 (set_attr "type" "vs")])
3263 (define_insn "*cmpmem_long_31z"
3264 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3265 (clobber (match_operand:TI 1 "register_operand" "=d"))
3266 (set (reg:CCU CC_REGNUM)
3267 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3268 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3270 (use (match_dup 3))]
3271 "!TARGET_64BIT && TARGET_ZARCH"
3272 "clcle\t%0,%1,0\;jo\t.-4"
3273 [(set_attr "op_type" "NN")
3274 (set_attr "type" "vs")
3275 (set_attr "length" "8")])
3277 ; Convert CCUmode condition code to integer.
3278 ; Result is zero if EQ, positive if LTU, negative if GTU.
3280 (define_insn_and_split "cmpint"
3281 [(set (match_operand:SI 0 "register_operand" "=d")
3282 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3283 UNSPEC_STRCMPCC_TO_INT))
3284 (clobber (reg:CC CC_REGNUM))]
3288 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3290 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3291 (clobber (reg:CC CC_REGNUM))])])
3293 (define_insn_and_split "*cmpint_cc"
3294 [(set (reg CC_REGNUM)
3295 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3296 UNSPEC_STRCMPCC_TO_INT)
3298 (set (match_operand:SI 0 "register_operand" "=d")
3299 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3300 "s390_match_ccmode (insn, CCSmode)"
3302 "&& reload_completed"
3303 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3305 [(set (match_dup 2) (match_dup 3))
3306 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3308 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3309 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3310 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3313 (define_insn_and_split "*cmpint_sign"
3314 [(set (match_operand:DI 0 "register_operand" "=d")
3315 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3316 UNSPEC_STRCMPCC_TO_INT)))
3317 (clobber (reg:CC CC_REGNUM))]
3320 "&& reload_completed"
3321 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3323 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3324 (clobber (reg:CC CC_REGNUM))])])
3326 (define_insn_and_split "*cmpint_sign_cc"
3327 [(set (reg CC_REGNUM)
3328 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3329 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3330 UNSPEC_STRCMPCC_TO_INT) 0)
3331 (const_int 32)) (const_int 32))
3333 (set (match_operand:DI 0 "register_operand" "=d")
3334 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3335 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3337 "&& reload_completed"
3338 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3340 [(set (match_dup 2) (match_dup 3))
3341 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3343 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3344 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3345 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3350 ;;- Conversion instructions.
3353 (define_insn "*sethighpartsi"
3354 [(set (match_operand:SI 0 "register_operand" "=d,d")
3355 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3356 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3357 (clobber (reg:CC CC_REGNUM))]
3362 [(set_attr "op_type" "RS,RSY")
3363 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3365 (define_insn "*sethighpartdi_64"
3366 [(set (match_operand:DI 0 "register_operand" "=d")
3367 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3368 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3369 (clobber (reg:CC CC_REGNUM))]
3372 [(set_attr "op_type" "RSY")
3373 (set_attr "z10prop" "z10_super")])
3375 (define_insn "*sethighpartdi_31"
3376 [(set (match_operand:DI 0 "register_operand" "=d,d")
3377 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3378 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3379 (clobber (reg:CC CC_REGNUM))]
3384 [(set_attr "op_type" "RS,RSY")
3385 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3388 ; extv instruction patterns
3391 ; FIXME: This expander needs to be converted from DI to GPR as well
3392 ; after resolving some issues with it.
3394 (define_expand "extzv"
3396 [(set (match_operand:DI 0 "register_operand" "=d")
3398 (match_operand:DI 1 "register_operand" "d")
3399 (match_operand 2 "const_int_operand" "") ; size
3400 (match_operand 3 "const_int_operand" ""))) ; start
3401 (clobber (reg:CC CC_REGNUM))])]
3404 /* Starting with zEC12 there is risbgn not clobbering CC. */
3407 emit_move_insn (operands[0],
3408 gen_rtx_ZERO_EXTRACT (DImode,
3416 (define_insn "*extzv<mode>_zEC12"
3417 [(set (match_operand:GPR 0 "register_operand" "=d")
3419 (match_operand:GPR 1 "register_operand" "d")
3420 (match_operand 2 "const_int_operand" "") ; size
3421 (match_operand 3 "const_int_operand" "")))] ; start]
3423 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3424 [(set_attr "op_type" "RIE")])
3426 (define_insn "*extzv<mode>_z10"
3427 [(set (match_operand:GPR 0 "register_operand" "=d")
3429 (match_operand:GPR 1 "register_operand" "d")
3430 (match_operand 2 "const_int_operand" "") ; size
3431 (match_operand 3 "const_int_operand" ""))) ; start
3432 (clobber (reg:CC CC_REGNUM))]
3434 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
3435 [(set_attr "op_type" "RIE")
3436 (set_attr "z10prop" "z10_super_E1")])
3438 (define_insn_and_split "*pre_z10_extzv<mode>"
3439 [(set (match_operand:GPR 0 "register_operand" "=d")
3440 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3441 (match_operand 2 "nonzero_shift_count_operand" "")
3443 (clobber (reg:CC CC_REGNUM))]
3446 "&& reload_completed"
3448 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3449 (clobber (reg:CC CC_REGNUM))])
3450 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3452 int bitsize = INTVAL (operands[2]);
3453 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3454 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3456 operands[1] = adjust_address (operands[1], BLKmode, 0);
3457 set_mem_size (operands[1], size);
3458 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3459 operands[3] = GEN_INT (mask);
3462 (define_insn_and_split "*pre_z10_extv<mode>"
3463 [(set (match_operand:GPR 0 "register_operand" "=d")
3464 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3465 (match_operand 2 "nonzero_shift_count_operand" "")
3467 (clobber (reg:CC CC_REGNUM))]
3470 "&& reload_completed"
3472 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3473 (clobber (reg:CC CC_REGNUM))])
3475 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3476 (clobber (reg:CC CC_REGNUM))])]
3478 int bitsize = INTVAL (operands[2]);
3479 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3480 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3482 operands[1] = adjust_address (operands[1], BLKmode, 0);
3483 set_mem_size (operands[1], size);
3484 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3485 operands[3] = GEN_INT (mask);
3489 ; insv instruction patterns
3492 (define_expand "insv"
3493 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3494 (match_operand 1 "const_int_operand" "")
3495 (match_operand 2 "const_int_operand" ""))
3496 (match_operand 3 "general_operand" ""))]
3499 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3505 ; The normal RTL expansion will never generate a zero_extract where
3506 ; the location operand isn't word mode. However, we do this in the
3507 ; back-end when generating atomic operations. See s390_two_part_insv.
3508 (define_insn "*insv<mode>_zEC12"
3509 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3510 (match_operand 1 "const_int_operand" "I") ; size
3511 (match_operand 2 "const_int_operand" "I")) ; pos
3512 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3514 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3515 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3516 [(set_attr "op_type" "RIE")])
3518 (define_insn "*insv<mode>_z10"
3519 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3520 (match_operand 1 "const_int_operand" "I") ; size
3521 (match_operand 2 "const_int_operand" "I")) ; pos
3522 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3523 (clobber (reg:CC CC_REGNUM))]
3525 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
3526 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
3527 [(set_attr "op_type" "RIE")
3528 (set_attr "z10prop" "z10_super_E1")])
3530 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3531 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3532 (define_insn "*insv<mode>_zEC12_noshift"
3533 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3534 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3535 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3536 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3537 (match_operand:GPR 4 "const_int_operand" ""))))]
3538 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3539 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
3540 [(set_attr "op_type" "RIE")])
3542 (define_insn "*insv<mode>_z10_noshift"
3543 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3544 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3545 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3546 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3547 (match_operand:GPR 4 "const_int_operand" ""))))
3548 (clobber (reg:CC CC_REGNUM))]
3549 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
3550 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3551 [(set_attr "op_type" "RIE")
3552 (set_attr "z10prop" "z10_super_E1")])
3554 (define_insn "*r<noxa>sbg_<mode>_noshift"
3555 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3557 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3558 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3559 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3560 (clobber (reg:CC CC_REGNUM))]
3562 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
3563 [(set_attr "op_type" "RIE")])
3565 (define_insn "*r<noxa>sbg_di_rotl"
3566 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3570 (match_operand:DI 1 "nonimmediate_operand" "d")
3571 (match_operand:DI 3 "const_int_operand" ""))
3572 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
3573 (match_operand:DI 4 "nonimmediate_operand" "0")))
3574 (clobber (reg:CC CC_REGNUM))]
3576 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
3577 [(set_attr "op_type" "RIE")])
3579 (define_insn "*r<noxa>sbg_<mode>_srl"
3580 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3584 (match_operand:GPR 1 "nonimmediate_operand" "d")
3585 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3586 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3587 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3588 (clobber (reg:CC CC_REGNUM))]
3590 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
3591 INTVAL (operands[2]))"
3592 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
3593 [(set_attr "op_type" "RIE")])
3595 (define_insn "*r<noxa>sbg_<mode>_sll"
3596 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3600 (match_operand:GPR 1 "nonimmediate_operand" "d")
3601 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
3602 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
3603 (match_operand:GPR 4 "nonimmediate_operand" "0")))
3604 (clobber (reg:CC CC_REGNUM))]
3606 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
3607 INTVAL (operands[2]))"
3608 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
3609 [(set_attr "op_type" "RIE")])
3611 ;; These two are generated by combine for s.bf &= val.
3612 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
3613 ;; shifts and ands, which results in some truly awful patterns
3614 ;; including subregs of operations. Rather unnecessisarily, IMO.
3617 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3618 ;; (const_int 24 [0x18])
3619 ;; (const_int 0 [0]))
3620 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
3621 ;; (const_int 40 [0x28])) 4)
3622 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
3624 ;; we should instead generate
3626 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
3627 ;; (const_int 24 [0x18])
3628 ;; (const_int 0 [0]))
3629 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
3630 ;; (const_int 40 [0x28]))
3631 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
3633 ;; by noticing that we can push down the outer paradoxical subreg
3634 ;; into the operation.
3636 (define_insn "*insv_rnsbg_noshift"
3637 [(set (zero_extract:DI
3638 (match_operand:DI 0 "nonimmediate_operand" "+d")
3639 (match_operand 1 "const_int_operand" "")
3640 (match_operand 2 "const_int_operand" ""))
3643 (match_operand:DI 3 "nonimmediate_operand" "d")))
3644 (clobber (reg:CC CC_REGNUM))]
3646 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
3647 "rnsbg\t%0,%3,%2,63,0"
3648 [(set_attr "op_type" "RIE")])
3650 (define_insn "*insv_rnsbg_srl"
3651 [(set (zero_extract:DI
3652 (match_operand:DI 0 "nonimmediate_operand" "+d")
3653 (match_operand 1 "const_int_operand" "")
3654 (match_operand 2 "const_int_operand" ""))
3658 (match_operand 3 "const_int_operand" ""))
3659 (match_operand:DI 4 "nonimmediate_operand" "d")))
3660 (clobber (reg:CC CC_REGNUM))]
3662 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
3663 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
3664 [(set_attr "op_type" "RIE")])
3666 (define_insn "*insv<mode>_mem_reg"
3667 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3668 (match_operand 1 "const_int_operand" "n,n")
3670 (match_operand:W 2 "register_operand" "d,d"))]
3671 "INTVAL (operands[1]) > 0
3672 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3673 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3675 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3677 operands[1] = GEN_INT ((1ul << size) - 1);
3678 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3679 : "stcmy\t%2,%1,%S0";
3681 [(set_attr "op_type" "RS,RSY")
3682 (set_attr "z10prop" "z10_super,z10_super")])
3684 (define_insn "*insvdi_mem_reghigh"
3685 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3686 (match_operand 1 "const_int_operand" "n")
3688 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3691 && INTVAL (operands[1]) > 0
3692 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3693 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3695 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3697 operands[1] = GEN_INT ((1ul << size) - 1);
3698 return "stcmh\t%2,%1,%S0";
3700 [(set_attr "op_type" "RSY")
3701 (set_attr "z10prop" "z10_super")])
3703 (define_insn "*insvdi_reg_imm"
3704 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3706 (match_operand 1 "const_int_operand" "n"))
3707 (match_operand:DI 2 "const_int_operand" "n"))]
3709 && INTVAL (operands[1]) >= 0
3710 && INTVAL (operands[1]) < BITS_PER_WORD
3711 && INTVAL (operands[1]) % 16 == 0"
3713 switch (BITS_PER_WORD - INTVAL (operands[1]))
3715 case 64: return "iihh\t%0,%x2"; break;
3716 case 48: return "iihl\t%0,%x2"; break;
3717 case 32: return "iilh\t%0,%x2"; break;
3718 case 16: return "iill\t%0,%x2"; break;
3719 default: gcc_unreachable();
3722 [(set_attr "op_type" "RI")
3723 (set_attr "z10prop" "z10_super_E1")])
3725 ; Update the left-most 32 bit of a DI.
3726 (define_insn "*insv_h_di_reg_extimm"
3727 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3730 (match_operand:DI 1 "const_int_operand" "n"))]
3733 [(set_attr "op_type" "RIL")
3734 (set_attr "z10prop" "z10_fwd_E1")])
3736 ; Update the right-most 32 bit of a DI.
3737 (define_insn "*insv_l_di_reg_extimm"
3738 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3741 (match_operand:DI 1 "const_int_operand" "n"))]
3744 [(set_attr "op_type" "RIL")
3745 (set_attr "z10prop" "z10_fwd_A1")])
3748 ; extendsidi2 instruction pattern(s).
3751 (define_expand "extendsidi2"
3752 [(set (match_operand:DI 0 "register_operand" "")
3753 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3758 emit_clobber (operands[0]);
3759 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3760 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3761 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3766 (define_insn "*extendsidi2"
3767 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3768 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3774 [(set_attr "op_type" "RRE,RXY,RIL")
3775 (set_attr "type" "*,*,larl")
3776 (set_attr "cpu_facility" "*,*,z10")
3777 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3780 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3783 (define_expand "extend<HQI:mode><DSI:mode>2"
3784 [(set (match_operand:DSI 0 "register_operand" "")
3785 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3788 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3790 rtx tmp = gen_reg_rtx (SImode);
3791 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3792 emit_insn (gen_extendsidi2 (operands[0], tmp));
3795 else if (!TARGET_EXTIMM)
3797 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
3799 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3800 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3801 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3807 ; extendhidi2 instruction pattern(s).
3810 (define_insn "*extendhidi2_extimm"
3811 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3812 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3813 "TARGET_ZARCH && TARGET_EXTIMM"
3818 [(set_attr "op_type" "RRE,RXY,RIL")
3819 (set_attr "type" "*,*,larl")
3820 (set_attr "cpu_facility" "extimm,extimm,z10")
3821 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3823 (define_insn "*extendhidi2"
3824 [(set (match_operand:DI 0 "register_operand" "=d")
3825 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3828 [(set_attr "op_type" "RXY")
3829 (set_attr "z10prop" "z10_super_E1")])
3832 ; extendhisi2 instruction pattern(s).
3835 (define_insn "*extendhisi2_extimm"
3836 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3837 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3844 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3845 (set_attr "type" "*,*,*,larl")
3846 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3847 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3849 (define_insn "*extendhisi2"
3850 [(set (match_operand:SI 0 "register_operand" "=d,d")
3851 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3856 [(set_attr "op_type" "RX,RXY")
3857 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3860 ; extendqi(si|di)2 instruction pattern(s).
3863 ; lbr, lgbr, lb, lgb
3864 (define_insn "*extendqi<mode>2_extimm"
3865 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3866 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3871 [(set_attr "op_type" "RRE,RXY")
3872 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3875 (define_insn "*extendqi<mode>2"
3876 [(set (match_operand:GPR 0 "register_operand" "=d")
3877 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3878 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3880 [(set_attr "op_type" "RXY")
3881 (set_attr "z10prop" "z10_super_E1")])
3883 (define_insn_and_split "*extendqi<mode>2_short_displ"
3884 [(set (match_operand:GPR 0 "register_operand" "=d")
3885 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3886 (clobber (reg:CC CC_REGNUM))]
3887 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3889 "&& reload_completed"
3891 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3892 (clobber (reg:CC CC_REGNUM))])
3894 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3895 (clobber (reg:CC CC_REGNUM))])]
3897 operands[1] = adjust_address (operands[1], BLKmode, 0);
3898 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3899 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
3903 ; zero_extendsidi2 instruction pattern(s).
3906 (define_expand "zero_extendsidi2"
3907 [(set (match_operand:DI 0 "register_operand" "")
3908 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3913 emit_clobber (operands[0]);
3914 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3915 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3920 (define_insn "*zero_extendsidi2"
3921 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3922 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3928 [(set_attr "op_type" "RRE,RXY,RIL")
3929 (set_attr "type" "*,*,larl")
3930 (set_attr "cpu_facility" "*,*,z10")
3931 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3934 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3937 (define_insn "*llgt_sidi"
3938 [(set (match_operand:DI 0 "register_operand" "=d")
3939 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3940 (const_int 2147483647)))]
3943 [(set_attr "op_type" "RXE")
3944 (set_attr "z10prop" "z10_super_E1")])
3946 (define_insn_and_split "*llgt_sidi_split"
3947 [(set (match_operand:DI 0 "register_operand" "=d")
3948 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3949 (const_int 2147483647)))
3950 (clobber (reg:CC CC_REGNUM))]
3953 "&& reload_completed"
3955 (and:DI (subreg:DI (match_dup 1) 0)
3956 (const_int 2147483647)))]
3959 (define_insn "*llgt_sisi"
3960 [(set (match_operand:SI 0 "register_operand" "=d,d")
3961 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3962 (const_int 2147483647)))]
3967 [(set_attr "op_type" "RRE,RXE")
3968 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3970 (define_insn "*llgt_didi"
3971 [(set (match_operand:DI 0 "register_operand" "=d,d")
3972 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3973 (const_int 2147483647)))]
3978 [(set_attr "op_type" "RRE,RXE")
3979 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3982 [(set (match_operand:DSI 0 "register_operand" "")
3983 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3984 (const_int 2147483647)))
3985 (clobber (reg:CC CC_REGNUM))]
3986 "TARGET_ZARCH && reload_completed"
3988 (and:DSI (match_dup 1)
3989 (const_int 2147483647)))]
3993 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3996 (define_expand "zero_extend<mode>di2"
3997 [(set (match_operand:DI 0 "register_operand" "")
3998 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4003 rtx tmp = gen_reg_rtx (SImode);
4004 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4005 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4008 else if (!TARGET_EXTIMM)
4010 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4011 operands[1] = gen_lowpart (DImode, operands[1]);
4012 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4013 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4018 (define_expand "zero_extend<mode>si2"
4019 [(set (match_operand:SI 0 "register_operand" "")
4020 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4025 operands[1] = gen_lowpart (SImode, operands[1]);
4026 emit_insn (gen_andsi3 (operands[0], operands[1],
4027 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4033 (define_insn "*zero_extendhi<mode>2_z10"
4034 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4035 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
4041 [(set_attr "op_type" "RXY,RRE,RIL")
4042 (set_attr "type" "*,*,larl")
4043 (set_attr "cpu_facility" "*,*,z10")
4044 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4046 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4047 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4048 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4049 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
4054 [(set_attr "op_type" "RRE,RXY")
4055 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4058 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4059 [(set (match_operand:GPR 0 "register_operand" "=d")
4060 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
4061 "TARGET_ZARCH && !TARGET_EXTIMM"
4063 [(set_attr "op_type" "RXY")
4064 (set_attr "z10prop" "z10_fwd_A3")])
4066 (define_insn_and_split "*zero_extendhisi2_31"
4067 [(set (match_operand:SI 0 "register_operand" "=&d")
4068 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
4069 (clobber (reg:CC CC_REGNUM))]
4072 "&& reload_completed"
4073 [(set (match_dup 0) (const_int 0))
4075 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4076 (clobber (reg:CC CC_REGNUM))])]
4077 "operands[2] = gen_lowpart (HImode, operands[0]);")
4079 (define_insn_and_split "*zero_extendqisi2_31"
4080 [(set (match_operand:SI 0 "register_operand" "=&d")
4081 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
4084 "&& reload_completed"
4085 [(set (match_dup 0) (const_int 0))
4086 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4087 "operands[2] = gen_lowpart (QImode, operands[0]);")
4090 ; zero_extendqihi2 instruction pattern(s).
4093 (define_expand "zero_extendqihi2"
4094 [(set (match_operand:HI 0 "register_operand" "")
4095 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4096 "TARGET_ZARCH && !TARGET_EXTIMM"
4098 operands[1] = gen_lowpart (HImode, operands[1]);
4099 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4103 (define_insn "*zero_extendqihi2_64"
4104 [(set (match_operand:HI 0 "register_operand" "=d")
4105 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4106 "TARGET_ZARCH && !TARGET_EXTIMM"
4108 [(set_attr "op_type" "RXY")
4109 (set_attr "z10prop" "z10_fwd_A3")])
4111 (define_insn_and_split "*zero_extendqihi2_31"
4112 [(set (match_operand:HI 0 "register_operand" "=&d")
4113 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
4116 "&& reload_completed"
4117 [(set (match_dup 0) (const_int 0))
4118 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4119 "operands[2] = gen_lowpart (QImode, operands[0]);")
4122 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
4125 (define_expand "fixuns_truncdddi2"
4127 [(set (match_operand:DI 0 "register_operand" "")
4128 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4129 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4130 (clobber (reg:CC CC_REGNUM))])]
4136 rtx_code_label *label1 = gen_label_rtx ();
4137 rtx_code_label *label2 = gen_label_rtx ();
4138 rtx temp = gen_reg_rtx (TDmode);
4139 REAL_VALUE_TYPE cmp, sub;
4141 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4142 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4144 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4145 solution is doing the check and the subtraction in TD mode and using a
4146 TD -> DI convert afterwards. */
4147 emit_insn (gen_extendddtd2 (temp, operands[1]));
4148 temp = force_reg (TDmode, temp);
4149 emit_cmp_and_jump_insns (temp,
4150 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4151 LT, NULL_RTX, VOIDmode, 0, label1);
4152 emit_insn (gen_subtd3 (temp, temp,
4153 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4154 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4157 emit_label (label1);
4158 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4159 emit_label (label2);
4164 (define_expand "fixuns_trunctddi2"
4166 [(set (match_operand:DI 0 "register_operand" "")
4167 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4168 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4169 (clobber (reg:CC CC_REGNUM))])]
4175 rtx_code_label *label1 = gen_label_rtx ();
4176 rtx_code_label *label2 = gen_label_rtx ();
4177 rtx temp = gen_reg_rtx (TDmode);
4178 REAL_VALUE_TYPE cmp, sub;
4180 operands[1] = force_reg (TDmode, operands[1]);
4181 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4182 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4184 emit_cmp_and_jump_insns (operands[1],
4185 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4186 LT, NULL_RTX, VOIDmode, 0, label1);
4187 emit_insn (gen_subtd3 (temp, operands[1],
4188 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4189 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4192 emit_label (label1);
4193 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4194 emit_label (label2);
4200 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4201 ; instruction pattern(s).
4204 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4206 [(set (match_operand:GPR 0 "register_operand" "")
4207 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4208 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4209 (clobber (reg:CC CC_REGNUM))])]
4214 rtx_code_label *label1 = gen_label_rtx ();
4215 rtx_code_label *label2 = gen_label_rtx ();
4216 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4217 REAL_VALUE_TYPE cmp, sub;
4219 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4220 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4221 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4223 emit_cmp_and_jump_insns (operands[1],
4224 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4225 LT, NULL_RTX, VOIDmode, 0, label1);
4226 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4227 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4228 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4232 emit_label (label1);
4233 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4234 operands[1], GEN_INT (5)));
4235 emit_label (label2);
4240 ; fixuns_trunc(td|dd)si2 expander
4241 (define_expand "fixuns_trunc<mode>si2"
4243 [(set (match_operand:SI 0 "register_operand" "")
4244 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4245 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4246 (clobber (reg:CC CC_REGNUM))])]
4247 "TARGET_Z196 && TARGET_HARD_DFP"
4250 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4252 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4253 ; clfdtr, clfxtr, clgdtr, clgxtr
4254 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4255 [(set (match_operand:GPR 0 "register_operand" "=r")
4256 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4257 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4258 (clobber (reg:CC CC_REGNUM))]
4260 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4261 [(set_attr "op_type" "RRF")
4262 (set_attr "type" "ftoi")])
4264 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4265 [(set (match_operand:GPR 0 "register_operand" "")
4266 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4269 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4274 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4275 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4276 [(set (match_operand:GPR 0 "register_operand" "=d")
4277 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4278 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4279 (clobber (reg:CC CC_REGNUM))]
4281 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4282 [(set_attr "op_type" "RRE")
4283 (set_attr "type" "ftoi")])
4287 ; fix_trunc(td|dd)di2 instruction pattern(s).
4290 (define_expand "fix_trunc<mode>di2"
4291 [(set (match_operand:DI 0 "register_operand" "")
4292 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4293 "TARGET_ZARCH && TARGET_HARD_DFP"
4295 operands[1] = force_reg (<MODE>mode, operands[1]);
4296 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4302 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4303 [(set (match_operand:DI 0 "register_operand" "=d")
4304 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4305 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4306 (clobber (reg:CC CC_REGNUM))]
4307 "TARGET_ZARCH && TARGET_HARD_DFP"
4308 "cg<DFP:xde>tr\t%0,%h2,%1"
4309 [(set_attr "op_type" "RRF")
4310 (set_attr "type" "ftoidfp")])
4314 ; fix_trunctf(si|di)2 instruction pattern(s).
4317 (define_expand "fix_trunctf<mode>2"
4318 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4319 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4320 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4321 (clobber (reg:CC CC_REGNUM))])]
4327 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4330 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4331 (define_insn "floatdi<mode>2"
4332 [(set (match_operand:FP 0 "register_operand" "=f")
4333 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4334 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4335 "c<xde>g<bt>r\t%0,%1"
4336 [(set_attr "op_type" "RRE")
4337 (set_attr "type" "itof<mode>" )])
4339 ; cxfbr, cdfbr, cefbr
4340 (define_insn "floatsi<mode>2"
4341 [(set (match_operand:BFP 0 "register_operand" "=f")
4342 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4345 [(set_attr "op_type" "RRE")
4346 (set_attr "type" "itof<mode>" )])
4349 (define_insn "floatsi<mode>2"
4350 [(set (match_operand:DFP 0 "register_operand" "=f")
4351 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4352 "TARGET_Z196 && TARGET_HARD_FLOAT"
4353 "c<xde>ftr\t%0,0,%1,0"
4354 [(set_attr "op_type" "RRE")
4355 (set_attr "type" "itof<mode>" )])
4358 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4361 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4362 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4363 (define_insn "floatuns<GPR:mode><FP:mode>2"
4364 [(set (match_operand:FP 0 "register_operand" "=f")
4365 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4366 "TARGET_Z196 && TARGET_HARD_FLOAT"
4367 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4368 [(set_attr "op_type" "RRE")
4369 (set_attr "type" "itof<FP:mode>" )])
4372 ; truncdfsf2 instruction pattern(s).
4375 (define_insn "truncdfsf2"
4376 [(set (match_operand:SF 0 "register_operand" "=f")
4377 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4380 [(set_attr "op_type" "RRE")
4381 (set_attr "type" "ftruncdf")])
4384 ; trunctf(df|sf)2 instruction pattern(s).
4388 (define_insn "trunctf<mode>2"
4389 [(set (match_operand:DSF 0 "register_operand" "=f")
4390 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4391 (clobber (match_scratch:TF 2 "=f"))]
4393 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4394 [(set_attr "length" "6")
4395 (set_attr "type" "ftrunctf")])
4398 ; trunctddd2 and truncddsd2 instruction pattern(s).
4401 (define_insn "trunctddd2"
4402 [(set (match_operand:DD 0 "register_operand" "=f")
4403 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4404 (clobber (match_scratch:TD 2 "=f"))]
4406 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4407 [(set_attr "length" "6")
4408 (set_attr "type" "ftruncdd")])
4410 (define_insn "truncddsd2"
4411 [(set (match_operand:SD 0 "register_operand" "=f")
4412 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4415 [(set_attr "op_type" "RRF")
4416 (set_attr "type" "ftruncsd")])
4418 (define_expand "trunctdsd2"
4421 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
4422 (clobber (match_scratch:TD 2 ""))])
4423 (set (match_operand:SD 0 "register_operand" "")
4424 (float_truncate:SD (match_dup 3)))]
4427 operands[3] = gen_reg_rtx (DDmode);
4431 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4434 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4435 (define_insn "extend<DSF:mode><BFP:mode>2"
4436 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4437 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4439 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4441 l<BFP:xde><DSF:xde>br\t%0,%1
4442 l<BFP:xde><DSF:xde>b\t%0,%1"
4443 [(set_attr "op_type" "RRE,RXE")
4444 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4447 ; extendddtd2 and extendsddd2 instruction pattern(s).
4450 (define_insn "extendddtd2"
4451 [(set (match_operand:TD 0 "register_operand" "=f")
4452 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4455 [(set_attr "op_type" "RRF")
4456 (set_attr "type" "fsimptf")])
4458 (define_insn "extendsddd2"
4459 [(set (match_operand:DD 0 "register_operand" "=f")
4460 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4463 [(set_attr "op_type" "RRF")
4464 (set_attr "type" "fsimptf")])
4466 (define_expand "extendsdtd2"
4468 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
4469 (set (match_operand:TD 0 "register_operand" "")
4470 (float_extend:TD (match_dup 2)))]
4473 operands[2] = gen_reg_rtx (DDmode);
4476 ; Binary Floating Point - load fp integer
4478 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
4479 ; For all of them the inexact exceptions are suppressed.
4481 ; fiebra, fidbra, fixbra
4482 (define_insn "<FPINT:fpint_name><BFP:mode>2"
4483 [(set (match_operand:BFP 0 "register_operand" "=f")
4484 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4487 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
4488 [(set_attr "op_type" "RRF")
4489 (set_attr "type" "fsimp<BFP:mode>")])
4491 ; rint is supposed to raise an inexact exception so we can use the
4492 ; older instructions.
4494 ; fiebr, fidbr, fixbr
4495 (define_insn "rint<BFP:mode>2"
4496 [(set (match_operand:BFP 0 "register_operand" "=f")
4497 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
4498 UNSPEC_FPINT_RINT))]
4500 "fi<BFP:xde>br\t%0,0,%1"
4501 [(set_attr "op_type" "RRF")
4502 (set_attr "type" "fsimp<BFP:mode>")])
4505 ; Decimal Floating Point - load fp integer
4508 (define_insn "<FPINT:fpint_name><DFP:mode>2"
4509 [(set (match_operand:DFP 0 "register_operand" "=f")
4510 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4513 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
4514 [(set_attr "op_type" "RRF")
4515 (set_attr "type" "fsimp<DFP:mode>")])
4518 (define_insn "rint<DFP:mode>2"
4519 [(set (match_operand:DFP 0 "register_operand" "=f")
4520 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
4521 UNSPEC_FPINT_RINT))]
4523 "fi<DFP:xde>tr\t%0,0,%1,0"
4524 [(set_attr "op_type" "RRF")
4525 (set_attr "type" "fsimp<DFP:mode>")])
4528 ; Binary <-> Decimal floating point trunc patterns
4531 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4532 [(set (reg:DFP_ALL FPR0_REGNUM)
4533 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4534 (use (reg:SI GPR0_REGNUM))
4535 (clobber (reg:CC CC_REGNUM))]
4539 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4540 [(set (reg:BFP FPR0_REGNUM)
4541 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4542 (use (reg:SI GPR0_REGNUM))
4543 (clobber (reg:CC CC_REGNUM))]
4547 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4548 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4549 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4551 [(set (reg:DFP_ALL FPR0_REGNUM)
4552 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
4553 (use (reg:SI GPR0_REGNUM))
4554 (clobber (reg:CC CC_REGNUM))])
4555 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4556 (reg:DFP_ALL FPR0_REGNUM))]
4558 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4560 HOST_WIDE_INT flags;
4562 flags = (PFPO_CONVERT |
4563 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4564 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4566 operands[2] = GEN_INT (flags);
4569 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4570 [(set (reg:DFP_ALL FPR4_REGNUM)
4571 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4572 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4574 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
4575 (use (reg:SI GPR0_REGNUM))
4576 (clobber (reg:CC CC_REGNUM))])
4577 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4579 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4581 HOST_WIDE_INT flags;
4583 flags = (PFPO_CONVERT |
4584 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4585 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4587 operands[2] = GEN_INT (flags);
4591 ; Binary <-> Decimal floating point extend patterns
4594 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4595 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4596 (use (reg:SI GPR0_REGNUM))
4597 (clobber (reg:CC CC_REGNUM))]
4601 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4602 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4603 (use (reg:SI GPR0_REGNUM))
4604 (clobber (reg:CC CC_REGNUM))]
4608 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4609 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4610 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4612 [(set (reg:DFP_ALL FPR0_REGNUM)
4613 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
4614 (use (reg:SI GPR0_REGNUM))
4615 (clobber (reg:CC CC_REGNUM))])
4616 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4617 (reg:DFP_ALL FPR0_REGNUM))]
4619 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4621 HOST_WIDE_INT flags;
4623 flags = (PFPO_CONVERT |
4624 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4625 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4627 operands[2] = GEN_INT (flags);
4630 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4631 [(set (reg:DFP_ALL FPR4_REGNUM)
4632 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4633 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4635 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
4636 (use (reg:SI GPR0_REGNUM))
4637 (clobber (reg:CC CC_REGNUM))])
4638 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4640 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4642 HOST_WIDE_INT flags;
4644 flags = (PFPO_CONVERT |
4645 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4646 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4648 operands[2] = GEN_INT (flags);
4653 ;; ARITHMETIC OPERATIONS
4655 ; arithmetic operations set the ConditionCode,
4656 ; because of unpredictable Bits in Register for Halfword and Byte
4657 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4660 ;;- Add instructions.
4664 ; addti3 instruction pattern(s).
4667 (define_insn_and_split "addti3"
4668 [(set (match_operand:TI 0 "register_operand" "=&d")
4669 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4670 (match_operand:TI 2 "general_operand" "do") ) )
4671 (clobber (reg:CC CC_REGNUM))]
4674 "&& reload_completed"
4676 [(set (reg:CCL1 CC_REGNUM)
4677 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4679 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4681 [(set (match_dup 3) (plus:DI
4682 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4683 (match_dup 4)) (match_dup 5)))
4684 (clobber (reg:CC CC_REGNUM))])]
4685 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4686 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4687 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4688 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4689 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4690 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4693 ; adddi3 instruction pattern(s).
4696 (define_expand "adddi3"
4698 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4699 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4700 (match_operand:DI 2 "general_operand" "")))
4701 (clobber (reg:CC CC_REGNUM))])]
4705 (define_insn "*adddi3_sign"
4706 [(set (match_operand:DI 0 "register_operand" "=d,d")
4707 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4708 (match_operand:DI 1 "register_operand" "0,0")))
4709 (clobber (reg:CC CC_REGNUM))]
4714 [(set_attr "op_type" "RRE,RXY")
4715 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4717 (define_insn "*adddi3_zero_cc"
4718 [(set (reg CC_REGNUM)
4719 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4720 (match_operand:DI 1 "register_operand" "0,0"))
4722 (set (match_operand:DI 0 "register_operand" "=d,d")
4723 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4724 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4728 [(set_attr "op_type" "RRE,RXY")
4729 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4731 (define_insn "*adddi3_zero_cconly"
4732 [(set (reg CC_REGNUM)
4733 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4734 (match_operand:DI 1 "register_operand" "0,0"))
4736 (clobber (match_scratch:DI 0 "=d,d"))]
4737 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4741 [(set_attr "op_type" "RRE,RXY")
4742 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4744 (define_insn "*adddi3_zero"
4745 [(set (match_operand:DI 0 "register_operand" "=d,d")
4746 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4747 (match_operand:DI 1 "register_operand" "0,0")))
4748 (clobber (reg:CC CC_REGNUM))]
4753 [(set_attr "op_type" "RRE,RXY")
4754 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4756 (define_insn_and_split "*adddi3_31z"
4757 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4758 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4759 (match_operand:DI 2 "general_operand" "do") ) )
4760 (clobber (reg:CC CC_REGNUM))]
4761 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4763 "&& reload_completed"
4765 [(set (reg:CCL1 CC_REGNUM)
4766 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4768 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4770 [(set (match_dup 3) (plus:SI
4771 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4772 (match_dup 4)) (match_dup 5)))
4773 (clobber (reg:CC CC_REGNUM))])]
4774 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4775 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4776 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4777 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4778 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4779 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4781 (define_insn_and_split "*adddi3_31"
4782 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4783 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4784 (match_operand:DI 2 "general_operand" "do") ) )
4785 (clobber (reg:CC CC_REGNUM))]
4788 "&& reload_completed"
4790 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4791 (clobber (reg:CC CC_REGNUM))])
4793 [(set (reg:CCL1 CC_REGNUM)
4794 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4796 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4798 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4800 (label_ref (match_dup 9))))
4802 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4803 (clobber (reg:CC CC_REGNUM))])
4805 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4806 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4807 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4808 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4809 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4810 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4811 operands[9] = gen_label_rtx ();")
4814 ; addsi3 instruction pattern(s).
4817 (define_expand "addsi3"
4819 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4820 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4821 (match_operand:SI 2 "general_operand" "")))
4822 (clobber (reg:CC CC_REGNUM))])]
4826 (define_insn "*addsi3_sign"
4827 [(set (match_operand:SI 0 "register_operand" "=d,d")
4828 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4829 (match_operand:SI 1 "register_operand" "0,0")))
4830 (clobber (reg:CC CC_REGNUM))]
4835 [(set_attr "op_type" "RX,RXY")
4836 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4839 ; add(di|si)3 instruction pattern(s).
4842 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4843 (define_insn "*add<mode>3"
4844 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4845 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4846 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4847 (clobber (reg:CC CC_REGNUM))]
4859 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4860 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4861 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4862 z10_super_E1,z10_super_E1,z10_super_E1")])
4864 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4865 (define_insn "*add<mode>3_carry1_cc"
4866 [(set (reg CC_REGNUM)
4867 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4868 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4870 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4871 (plus:GPR (match_dup 1) (match_dup 2)))]
4872 "s390_match_ccmode (insn, CCL1mode)"
4878 al<g>hsik\t%0,%1,%h2
4882 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4883 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4884 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4885 z10_super_E1,z10_super_E1,z10_super_E1")])
4887 ; alr, al, aly, algr, alg, alrk, algrk
4888 (define_insn "*add<mode>3_carry1_cconly"
4889 [(set (reg CC_REGNUM)
4890 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4891 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4893 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4894 "s390_match_ccmode (insn, CCL1mode)"
4900 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4901 (set_attr "cpu_facility" "*,z196,*,*")
4902 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4904 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4905 (define_insn "*add<mode>3_carry2_cc"
4906 [(set (reg CC_REGNUM)
4907 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4908 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4910 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4911 (plus:GPR (match_dup 1) (match_dup 2)))]
4912 "s390_match_ccmode (insn, CCL1mode)"
4918 al<g>hsik\t%0,%1,%h2
4922 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4923 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4924 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4925 z10_super_E1,z10_super_E1,z10_super_E1")])
4927 ; alr, al, aly, algr, alg, alrk, algrk
4928 (define_insn "*add<mode>3_carry2_cconly"
4929 [(set (reg CC_REGNUM)
4930 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4931 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4933 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4934 "s390_match_ccmode (insn, CCL1mode)"
4940 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4941 (set_attr "cpu_facility" "*,z196,*,*")
4942 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4944 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4945 (define_insn "*add<mode>3_cc"
4946 [(set (reg CC_REGNUM)
4947 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4948 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4950 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4951 (plus:GPR (match_dup 1) (match_dup 2)))]
4952 "s390_match_ccmode (insn, CCLmode)"
4958 al<g>hsik\t%0,%1,%h2
4962 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4963 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4964 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4965 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4967 ; alr, al, aly, algr, alg, alrk, algrk
4968 (define_insn "*add<mode>3_cconly"
4969 [(set (reg CC_REGNUM)
4970 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4971 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4973 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4974 "s390_match_ccmode (insn, CCLmode)"
4980 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4981 (set_attr "cpu_facility" "*,z196,*,*")
4982 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4984 ; alr, al, aly, algr, alg, alrk, algrk
4985 (define_insn "*add<mode>3_cconly2"
4986 [(set (reg CC_REGNUM)
4987 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4988 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4989 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4990 "s390_match_ccmode(insn, CCLmode)"
4996 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4997 (set_attr "cpu_facility" "*,z196,*,*")
4998 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5000 ; ahi, afi, aghi, agfi, asi, agsi
5001 (define_insn "*add<mode>3_imm_cc"
5002 [(set (reg CC_REGNUM)
5003 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5004 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
5006 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
5007 (plus:GPR (match_dup 1) (match_dup 2)))]
5008 "s390_match_ccmode (insn, CCAmode)
5009 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5010 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5011 /* Avoid INT32_MIN on 32 bit. */
5012 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5018 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5019 (set_attr "cpu_facility" "*,z196,extimm,z10")
5020 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5023 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5026 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5027 (define_insn "add<mode>3"
5028 [(set (match_operand:FP 0 "register_operand" "=f, f")
5029 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5030 (match_operand:FP 2 "general_operand" " f,<Rf>")))
5031 (clobber (reg:CC CC_REGNUM))]
5034 a<xde><bt>r\t%0,<op1>%2
5036 [(set_attr "op_type" "<RRer>,RXE")
5037 (set_attr "type" "fsimp<mode>")])
5039 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5040 (define_insn "*add<mode>3_cc"
5041 [(set (reg CC_REGNUM)
5042 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5043 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5044 (match_operand:FP 3 "const0_operand" "")))
5045 (set (match_operand:FP 0 "register_operand" "=f,f")
5046 (plus:FP (match_dup 1) (match_dup 2)))]
5047 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5049 a<xde><bt>r\t%0,<op1>%2
5051 [(set_attr "op_type" "<RRer>,RXE")
5052 (set_attr "type" "fsimp<mode>")])
5054 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5055 (define_insn "*add<mode>3_cconly"
5056 [(set (reg CC_REGNUM)
5057 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5058 (match_operand:FP 2 "general_operand" " f,<Rf>"))
5059 (match_operand:FP 3 "const0_operand" "")))
5060 (clobber (match_scratch:FP 0 "=f,f"))]
5061 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5063 a<xde><bt>r\t%0,<op1>%2
5065 [(set_attr "op_type" "<RRer>,RXE")
5066 (set_attr "type" "fsimp<mode>")])
5069 ; Pointer add instruction patterns
5072 ; This will match "*la_64"
5073 (define_expand "addptrdi3"
5074 [(set (match_operand:DI 0 "register_operand" "")
5075 (plus:DI (match_operand:DI 1 "register_operand" "")
5076 (match_operand:DI 2 "nonmemory_operand" "")))]
5079 if (GET_CODE (operands[2]) == CONST_INT)
5081 HOST_WIDE_INT c = INTVAL (operands[2]);
5083 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5084 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5086 operands[2] = force_const_mem (DImode, operands[2]);
5087 operands[2] = force_reg (DImode, operands[2]);
5089 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5090 operands[2] = force_reg (DImode, operands[2]);
5094 ; For 31 bit we have to prevent the generated pattern from matching
5095 ; normal ADDs since la only does a 31 bit add. This is supposed to
5096 ; match "force_la_31".
5097 (define_expand "addptrsi3"
5099 [(set (match_operand:SI 0 "register_operand" "")
5100 (plus:SI (match_operand:SI 1 "register_operand" "")
5101 (match_operand:SI 2 "nonmemory_operand" "")))
5102 (use (const_int 0))])]
5105 if (GET_CODE (operands[2]) == CONST_INT)
5107 HOST_WIDE_INT c = INTVAL (operands[2]);
5109 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5110 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5112 operands[2] = force_const_mem (SImode, operands[2]);
5113 operands[2] = force_reg (SImode, operands[2]);
5115 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5116 operands[2] = force_reg (SImode, operands[2]);
5121 ;;- Subtract instructions.
5125 ; subti3 instruction pattern(s).
5128 (define_insn_and_split "subti3"
5129 [(set (match_operand:TI 0 "register_operand" "=&d")
5130 (minus:TI (match_operand:TI 1 "register_operand" "0")
5131 (match_operand:TI 2 "general_operand" "do") ) )
5132 (clobber (reg:CC CC_REGNUM))]
5135 "&& reload_completed"
5137 [(set (reg:CCL2 CC_REGNUM)
5138 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5140 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5142 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5143 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5144 (clobber (reg:CC CC_REGNUM))])]
5145 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5146 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5147 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5148 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5149 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5150 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
5153 ; subdi3 instruction pattern(s).
5156 (define_expand "subdi3"
5158 [(set (match_operand:DI 0 "register_operand" "")
5159 (minus:DI (match_operand:DI 1 "register_operand" "")
5160 (match_operand:DI 2 "general_operand" "")))
5161 (clobber (reg:CC CC_REGNUM))])]
5165 (define_insn "*subdi3_sign"
5166 [(set (match_operand:DI 0 "register_operand" "=d,d")
5167 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5168 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5169 (clobber (reg:CC CC_REGNUM))]
5174 [(set_attr "op_type" "RRE,RXY")
5175 (set_attr "z10prop" "z10_c,*")
5176 (set_attr "z196prop" "z196_cracked")])
5178 (define_insn "*subdi3_zero_cc"
5179 [(set (reg CC_REGNUM)
5180 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5181 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5183 (set (match_operand:DI 0 "register_operand" "=d,d")
5184 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
5185 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5189 [(set_attr "op_type" "RRE,RXY")
5190 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5192 (define_insn "*subdi3_zero_cconly"
5193 [(set (reg CC_REGNUM)
5194 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5195 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
5197 (clobber (match_scratch:DI 0 "=d,d"))]
5198 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5202 [(set_attr "op_type" "RRE,RXY")
5203 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5205 (define_insn "*subdi3_zero"
5206 [(set (match_operand:DI 0 "register_operand" "=d,d")
5207 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
5208 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
5209 (clobber (reg:CC CC_REGNUM))]
5214 [(set_attr "op_type" "RRE,RXY")
5215 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
5217 (define_insn_and_split "*subdi3_31z"
5218 [(set (match_operand:DI 0 "register_operand" "=&d")
5219 (minus:DI (match_operand:DI 1 "register_operand" "0")
5220 (match_operand:DI 2 "general_operand" "do") ) )
5221 (clobber (reg:CC CC_REGNUM))]
5222 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5224 "&& reload_completed"
5226 [(set (reg:CCL2 CC_REGNUM)
5227 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5229 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5231 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
5232 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
5233 (clobber (reg:CC CC_REGNUM))])]
5234 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5235 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5236 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5237 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5238 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5239 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5241 (define_insn_and_split "*subdi3_31"
5242 [(set (match_operand:DI 0 "register_operand" "=&d")
5243 (minus:DI (match_operand:DI 1 "register_operand" "0")
5244 (match_operand:DI 2 "general_operand" "do") ) )
5245 (clobber (reg:CC CC_REGNUM))]
5248 "&& reload_completed"
5250 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
5251 (clobber (reg:CC CC_REGNUM))])
5253 [(set (reg:CCL2 CC_REGNUM)
5254 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
5256 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
5258 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
5260 (label_ref (match_dup 9))))
5262 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
5263 (clobber (reg:CC CC_REGNUM))])
5265 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5266 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5267 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5268 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5269 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5270 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5271 operands[9] = gen_label_rtx ();")
5274 ; subsi3 instruction pattern(s).
5277 (define_expand "subsi3"
5279 [(set (match_operand:SI 0 "register_operand" "")
5280 (minus:SI (match_operand:SI 1 "register_operand" "")
5281 (match_operand:SI 2 "general_operand" "")))
5282 (clobber (reg:CC CC_REGNUM))])]
5286 (define_insn "*subsi3_sign"
5287 [(set (match_operand:SI 0 "register_operand" "=d,d")
5288 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5289 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5290 (clobber (reg:CC CC_REGNUM))]
5295 [(set_attr "op_type" "RX,RXY")
5296 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5299 ; sub(di|si)3 instruction pattern(s).
5302 ; sr, s, sy, sgr, sg, srk, sgrk
5303 (define_insn "*sub<mode>3"
5304 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5305 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5306 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5307 (clobber (reg:CC CC_REGNUM))]
5314 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5315 (set_attr "cpu_facility" "*,z196,*,*")
5316 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5318 ; slr, sl, sly, slgr, slg, slrk, slgrk
5319 (define_insn "*sub<mode>3_borrow_cc"
5320 [(set (reg CC_REGNUM)
5321 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5322 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5324 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5325 (minus:GPR (match_dup 1) (match_dup 2)))]
5326 "s390_match_ccmode (insn, CCL2mode)"
5332 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5333 (set_attr "cpu_facility" "*,z196,*,*")
5334 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5336 ; slr, sl, sly, slgr, slg, slrk, slgrk
5337 (define_insn "*sub<mode>3_borrow_cconly"
5338 [(set (reg CC_REGNUM)
5339 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5340 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5342 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5343 "s390_match_ccmode (insn, CCL2mode)"
5349 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5350 (set_attr "cpu_facility" "*,z196,*,*")
5351 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5353 ; slr, sl, sly, slgr, slg, slrk, slgrk
5354 (define_insn "*sub<mode>3_cc"
5355 [(set (reg CC_REGNUM)
5356 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5357 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5359 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5360 (minus:GPR (match_dup 1) (match_dup 2)))]
5361 "s390_match_ccmode (insn, CCLmode)"
5367 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5368 (set_attr "cpu_facility" "*,z196,*,*")
5369 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5371 ; slr, sl, sly, slgr, slg, slrk, slgrk
5372 (define_insn "*sub<mode>3_cc2"
5373 [(set (reg CC_REGNUM)
5374 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5375 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5376 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5377 (minus:GPR (match_dup 1) (match_dup 2)))]
5378 "s390_match_ccmode (insn, CCL3mode)"
5384 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5385 (set_attr "cpu_facility" "*,z196,*,*")
5386 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5388 ; slr, sl, sly, slgr, slg, slrk, slgrk
5389 (define_insn "*sub<mode>3_cconly"
5390 [(set (reg CC_REGNUM)
5391 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5392 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5394 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5395 "s390_match_ccmode (insn, CCLmode)"
5401 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5402 (set_attr "cpu_facility" "*,z196,*,*")
5403 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5406 ; slr, sl, sly, slgr, slg, slrk, slgrk
5407 (define_insn "*sub<mode>3_cconly2"
5408 [(set (reg CC_REGNUM)
5409 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5410 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5411 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5412 "s390_match_ccmode (insn, CCL3mode)"
5418 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5419 (set_attr "cpu_facility" "*,z196,*,*")
5420 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5424 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5427 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5428 (define_insn "sub<mode>3"
5429 [(set (match_operand:FP 0 "register_operand" "=f, f")
5430 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5431 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5432 (clobber (reg:CC CC_REGNUM))]
5435 s<xde><bt>r\t%0,<op1>%2
5437 [(set_attr "op_type" "<RRer>,RXE")
5438 (set_attr "type" "fsimp<mode>")])
5440 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5441 (define_insn "*sub<mode>3_cc"
5442 [(set (reg CC_REGNUM)
5443 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5444 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5445 (match_operand:FP 3 "const0_operand" "")))
5446 (set (match_operand:FP 0 "register_operand" "=f,f")
5447 (minus:FP (match_dup 1) (match_dup 2)))]
5448 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5450 s<xde><bt>r\t%0,<op1>%2
5452 [(set_attr "op_type" "<RRer>,RXE")
5453 (set_attr "type" "fsimp<mode>")])
5455 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5456 (define_insn "*sub<mode>3_cconly"
5457 [(set (reg CC_REGNUM)
5458 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5459 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5460 (match_operand:FP 3 "const0_operand" "")))
5461 (clobber (match_scratch:FP 0 "=f,f"))]
5462 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5464 s<xde><bt>r\t%0,<op1>%2
5466 [(set_attr "op_type" "<RRer>,RXE")
5467 (set_attr "type" "fsimp<mode>")])
5471 ;;- Conditional add/subtract instructions.
5475 ; add(di|si)cc instruction pattern(s).
5478 ; the following 4 patterns are used when the result of an add with
5479 ; carry is checked for an overflow condition
5481 ; op1 + op2 + c < op1
5483 ; alcr, alc, alcgr, alcg
5484 (define_insn "*add<mode>3_alc_carry1_cc"
5485 [(set (reg CC_REGNUM)
5487 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5488 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5489 (match_operand:GPR 2 "general_operand" "d,RT"))
5491 (set (match_operand:GPR 0 "register_operand" "=d,d")
5492 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5493 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5497 [(set_attr "op_type" "RRE,RXY")
5498 (set_attr "z196prop" "z196_alone,z196_alone")])
5500 ; alcr, alc, alcgr, alcg
5501 (define_insn "*add<mode>3_alc_carry1_cconly"
5502 [(set (reg CC_REGNUM)
5504 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5505 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5506 (match_operand:GPR 2 "general_operand" "d,RT"))
5508 (clobber (match_scratch:GPR 0 "=d,d"))]
5509 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5513 [(set_attr "op_type" "RRE,RXY")
5514 (set_attr "z196prop" "z196_alone,z196_alone")])
5516 ; op1 + op2 + c < op2
5518 ; alcr, alc, alcgr, alcg
5519 (define_insn "*add<mode>3_alc_carry2_cc"
5520 [(set (reg CC_REGNUM)
5522 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5523 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5524 (match_operand:GPR 2 "general_operand" "d,RT"))
5526 (set (match_operand:GPR 0 "register_operand" "=d,d")
5527 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5528 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5532 [(set_attr "op_type" "RRE,RXY")])
5534 ; alcr, alc, alcgr, alcg
5535 (define_insn "*add<mode>3_alc_carry2_cconly"
5536 [(set (reg CC_REGNUM)
5538 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5539 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5540 (match_operand:GPR 2 "general_operand" "d,RT"))
5542 (clobber (match_scratch:GPR 0 "=d,d"))]
5543 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5547 [(set_attr "op_type" "RRE,RXY")])
5549 ; alcr, alc, alcgr, alcg
5550 (define_insn "*add<mode>3_alc_cc"
5551 [(set (reg CC_REGNUM)
5553 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5554 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5555 (match_operand:GPR 2 "general_operand" "d,RT"))
5557 (set (match_operand:GPR 0 "register_operand" "=d,d")
5558 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5559 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5563 [(set_attr "op_type" "RRE,RXY")])
5565 ; alcr, alc, alcgr, alcg
5566 (define_insn "*add<mode>3_alc"
5567 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5568 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5569 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5570 (match_operand:GPR 2 "general_operand" "d,RT")))
5571 (clobber (reg:CC CC_REGNUM))]
5576 [(set_attr "op_type" "RRE,RXY")])
5578 ; slbr, slb, slbgr, slbg
5579 (define_insn "*sub<mode>3_slb_cc"
5580 [(set (reg CC_REGNUM)
5582 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5583 (match_operand:GPR 2 "general_operand" "d,RT"))
5584 (match_operand:GPR 3 "s390_slb_comparison" ""))
5586 (set (match_operand:GPR 0 "register_operand" "=d,d")
5587 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5588 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5592 [(set_attr "op_type" "RRE,RXY")
5593 (set_attr "z10prop" "z10_c,*")])
5595 ; slbr, slb, slbgr, slbg
5596 (define_insn "*sub<mode>3_slb"
5597 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5598 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5599 (match_operand:GPR 2 "general_operand" "d,RT"))
5600 (match_operand:GPR 3 "s390_slb_comparison" "")))
5601 (clobber (reg:CC CC_REGNUM))]
5606 [(set_attr "op_type" "RRE,RXY")
5607 (set_attr "z10prop" "z10_c,*")])
5609 (define_expand "add<mode>cc"
5610 [(match_operand:GPR 0 "register_operand" "")
5611 (match_operand 1 "comparison_operator" "")
5612 (match_operand:GPR 2 "register_operand" "")
5613 (match_operand:GPR 3 "const_int_operand" "")]
5615 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5616 XEXP (operands[1], 0), XEXP (operands[1], 1),
5617 operands[0], operands[2],
5618 operands[3])) FAIL; DONE;")
5621 ; scond instruction pattern(s).
5624 (define_insn_and_split "*scond<mode>"
5625 [(set (match_operand:GPR 0 "register_operand" "=&d")
5626 (match_operand:GPR 1 "s390_alc_comparison" ""))
5627 (clobber (reg:CC CC_REGNUM))]
5630 "&& reload_completed"
5631 [(set (match_dup 0) (const_int 0))
5633 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5635 (clobber (reg:CC CC_REGNUM))])]
5638 (define_insn_and_split "*scond<mode>_neg"
5639 [(set (match_operand:GPR 0 "register_operand" "=&d")
5640 (match_operand:GPR 1 "s390_slb_comparison" ""))
5641 (clobber (reg:CC CC_REGNUM))]
5644 "&& reload_completed"
5645 [(set (match_dup 0) (const_int 0))
5647 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5649 (clobber (reg:CC CC_REGNUM))])
5651 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5652 (clobber (reg:CC CC_REGNUM))])]
5656 (define_expand "cstore<mode>4"
5657 [(set (match_operand:SI 0 "register_operand" "")
5658 (match_operator:SI 1 "s390_scond_operator"
5659 [(match_operand:GPR 2 "register_operand" "")
5660 (match_operand:GPR 3 "general_operand" "")]))]
5662 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5663 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5665 (define_expand "cstorecc4"
5667 [(set (match_operand:SI 0 "register_operand" "")
5668 (match_operator:SI 1 "s390_eqne_operator"
5669 [(match_operand:CCZ1 2 "register_operand")
5670 (match_operand 3 "const0_operand")]))
5671 (clobber (reg:CC CC_REGNUM))])]
5673 "emit_insn (gen_sne (operands[0], operands[2]));
5674 if (GET_CODE (operands[1]) == EQ)
5675 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5678 (define_insn_and_split "sne"
5679 [(set (match_operand:SI 0 "register_operand" "=d")
5680 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5682 (clobber (reg:CC CC_REGNUM))]
5687 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5688 (clobber (reg:CC CC_REGNUM))])])
5692 ;; - Conditional move instructions (introduced with z196)
5695 (define_expand "mov<mode>cc"
5696 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5697 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5698 (match_operand:GPR 2 "nonimmediate_operand" "")
5699 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5701 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5702 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5704 ; locr, loc, stoc, locgr, locg, stocg
5705 (define_insn_and_split "*mov<mode>cc"
5706 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5708 (match_operator 1 "s390_comparison"
5709 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5710 (match_operand 5 "const_int_operand" "")])
5711 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5712 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5722 "&& reload_completed
5723 && MEM_P (operands[3]) && MEM_P (operands[4])"
5726 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5731 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5735 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5738 ;;- Multiply instructions.
5742 ; muldi3 instruction pattern(s).
5745 (define_insn "*muldi3_sign"
5746 [(set (match_operand:DI 0 "register_operand" "=d,d")
5747 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5748 (match_operand:DI 1 "register_operand" "0,0")))]
5753 [(set_attr "op_type" "RRE,RXY")
5754 (set_attr "type" "imuldi")])
5756 (define_insn "muldi3"
5757 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5758 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5759 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5766 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5767 (set_attr "type" "imuldi")
5768 (set_attr "cpu_facility" "*,*,*,z10")])
5771 ; mulsi3 instruction pattern(s).
5774 (define_insn "*mulsi3_sign"
5775 [(set (match_operand:SI 0 "register_operand" "=d,d")
5776 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5777 (match_operand:SI 1 "register_operand" "0,0")))]
5782 [(set_attr "op_type" "RX,RXY")
5783 (set_attr "type" "imulhi")
5784 (set_attr "cpu_facility" "*,z10")])
5786 (define_insn "mulsi3"
5787 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5788 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5789 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5797 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5798 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5799 (set_attr "cpu_facility" "*,*,*,*,z10")])
5802 ; mulsidi3 instruction pattern(s).
5805 (define_insn "mulsidi3"
5806 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5807 (mult:DI (sign_extend:DI
5808 (match_operand:SI 1 "register_operand" "%0,0,0"))
5810 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5816 [(set_attr "op_type" "RR,RX,RXY")
5817 (set_attr "type" "imulsi")
5818 (set_attr "cpu_facility" "*,*,z10")])
5821 ; umul instruction pattern(s).
5824 ; mlr, ml, mlgr, mlg
5825 (define_insn "umul<dwh><mode>3"
5826 [(set (match_operand:DW 0 "register_operand" "=d, d")
5827 (mult:DW (zero_extend:DW
5828 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5830 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5835 [(set_attr "op_type" "RRE,RXY")
5836 (set_attr "type" "imul<dwh>")])
5839 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5842 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5843 (define_insn "mul<mode>3"
5844 [(set (match_operand:FP 0 "register_operand" "=f,f")
5845 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5846 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5849 m<xdee><bt>r\t%0,<op1>%2
5851 [(set_attr "op_type" "<RRer>,RXE")
5852 (set_attr "type" "fmul<mode>")])
5854 ; madbr, maebr, maxb, madb, maeb
5855 (define_insn "fma<mode>4"
5856 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5857 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5858 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5859 (match_operand:DSF 3 "register_operand" "0,0")))]
5864 [(set_attr "op_type" "RRE,RXE")
5865 (set_attr "type" "fmadd<mode>")])
5867 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5868 (define_insn "fms<mode>4"
5869 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5870 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5871 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5872 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5877 [(set_attr "op_type" "RRE,RXE")
5878 (set_attr "type" "fmadd<mode>")])
5881 ;;- Divide and modulo instructions.
5885 ; divmoddi4 instruction pattern(s).
5888 (define_expand "divmoddi4"
5889 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5890 (div:DI (match_operand:DI 1 "register_operand" "")
5891 (match_operand:DI 2 "general_operand" "")))
5892 (set (match_operand:DI 3 "general_operand" "")
5893 (mod:DI (match_dup 1) (match_dup 2)))])
5894 (clobber (match_dup 4))]
5897 rtx insn, div_equal, mod_equal;
5899 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5900 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5902 operands[4] = gen_reg_rtx(TImode);
5903 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5905 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5906 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5908 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5909 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5914 (define_insn "divmodtidi3"
5915 [(set (match_operand:TI 0 "register_operand" "=d,d")
5919 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5920 (match_operand:DI 2 "general_operand" "d,RT")))
5922 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5927 [(set_attr "op_type" "RRE,RXY")
5928 (set_attr "type" "idiv")])
5930 (define_insn "divmodtisi3"
5931 [(set (match_operand:TI 0 "register_operand" "=d,d")
5935 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5937 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5940 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5945 [(set_attr "op_type" "RRE,RXY")
5946 (set_attr "type" "idiv")])
5949 ; udivmoddi4 instruction pattern(s).
5952 (define_expand "udivmoddi4"
5953 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5954 (udiv:DI (match_operand:DI 1 "general_operand" "")
5955 (match_operand:DI 2 "nonimmediate_operand" "")))
5956 (set (match_operand:DI 3 "general_operand" "")
5957 (umod:DI (match_dup 1) (match_dup 2)))])
5958 (clobber (match_dup 4))]
5961 rtx insn, div_equal, mod_equal, equal;
5963 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5964 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5965 equal = gen_rtx_IOR (TImode,
5966 gen_rtx_ASHIFT (TImode,
5967 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5969 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5971 operands[4] = gen_reg_rtx(TImode);
5972 emit_clobber (operands[4]);
5973 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5974 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5976 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5977 set_unique_reg_note (insn, REG_EQUAL, equal);
5979 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5980 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5982 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5983 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5988 (define_insn "udivmodtidi3"
5989 [(set (match_operand:TI 0 "register_operand" "=d,d")
5994 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5996 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
6000 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6005 [(set_attr "op_type" "RRE,RXY")
6006 (set_attr "type" "idiv")])
6009 ; divmodsi4 instruction pattern(s).
6012 (define_expand "divmodsi4"
6013 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6014 (div:SI (match_operand:SI 1 "general_operand" "")
6015 (match_operand:SI 2 "nonimmediate_operand" "")))
6016 (set (match_operand:SI 3 "general_operand" "")
6017 (mod:SI (match_dup 1) (match_dup 2)))])
6018 (clobber (match_dup 4))]
6021 rtx insn, div_equal, mod_equal, equal;
6023 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6024 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6025 equal = gen_rtx_IOR (DImode,
6026 gen_rtx_ASHIFT (DImode,
6027 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6029 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6031 operands[4] = gen_reg_rtx(DImode);
6032 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6034 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6035 set_unique_reg_note (insn, REG_EQUAL, equal);
6037 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6038 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6040 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6041 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6046 (define_insn "divmoddisi3"
6047 [(set (match_operand:DI 0 "register_operand" "=d,d")
6052 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6054 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
6058 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
6063 [(set_attr "op_type" "RR,RX")
6064 (set_attr "type" "idiv")])
6067 ; udivsi3 and umodsi3 instruction pattern(s).
6070 (define_expand "udivmodsi4"
6071 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6072 (udiv:SI (match_operand:SI 1 "general_operand" "")
6073 (match_operand:SI 2 "nonimmediate_operand" "")))
6074 (set (match_operand:SI 3 "general_operand" "")
6075 (umod:SI (match_dup 1) (match_dup 2)))])
6076 (clobber (match_dup 4))]
6077 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6079 rtx insn, div_equal, mod_equal, equal;
6081 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6082 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6083 equal = gen_rtx_IOR (DImode,
6084 gen_rtx_ASHIFT (DImode,
6085 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6087 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6089 operands[4] = gen_reg_rtx(DImode);
6090 emit_clobber (operands[4]);
6091 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
6092 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
6094 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
6095 set_unique_reg_note (insn, REG_EQUAL, equal);
6097 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6098 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6100 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6101 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6106 (define_insn "udivmoddisi3"
6107 [(set (match_operand:DI 0 "register_operand" "=d,d")
6112 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
6114 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
6118 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
6119 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6123 [(set_attr "op_type" "RRE,RXY")
6124 (set_attr "type" "idiv")])
6126 (define_expand "udivsi3"
6127 [(set (match_operand:SI 0 "register_operand" "=d")
6128 (udiv:SI (match_operand:SI 1 "general_operand" "")
6129 (match_operand:SI 2 "general_operand" "")))
6130 (clobber (match_dup 3))]
6131 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6133 rtx insn, udiv_equal, umod_equal, equal;
6135 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6136 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6137 equal = gen_rtx_IOR (DImode,
6138 gen_rtx_ASHIFT (DImode,
6139 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6141 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6143 operands[3] = gen_reg_rtx (DImode);
6145 if (CONSTANT_P (operands[2]))
6147 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6149 rtx_code_label *label1 = gen_label_rtx ();
6151 operands[1] = make_safe_from (operands[1], operands[0]);
6152 emit_move_insn (operands[0], const0_rtx);
6153 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
6155 emit_move_insn (operands[0], const1_rtx);
6156 emit_label (label1);
6160 operands[2] = force_reg (SImode, operands[2]);
6161 operands[2] = make_safe_from (operands[2], operands[0]);
6163 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6164 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6166 set_unique_reg_note (insn, REG_EQUAL, equal);
6168 insn = emit_move_insn (operands[0],
6169 gen_lowpart (SImode, operands[3]));
6170 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6175 rtx_code_label *label1 = gen_label_rtx ();
6176 rtx_code_label *label2 = gen_label_rtx ();
6177 rtx_code_label *label3 = gen_label_rtx ();
6179 operands[1] = force_reg (SImode, operands[1]);
6180 operands[1] = make_safe_from (operands[1], operands[0]);
6181 operands[2] = force_reg (SImode, operands[2]);
6182 operands[2] = make_safe_from (operands[2], operands[0]);
6184 emit_move_insn (operands[0], const0_rtx);
6185 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6187 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6189 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6191 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6192 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6194 set_unique_reg_note (insn, REG_EQUAL, equal);
6196 insn = emit_move_insn (operands[0],
6197 gen_lowpart (SImode, operands[3]));
6198 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
6201 emit_label (label1);
6202 emit_move_insn (operands[0], operands[1]);
6204 emit_label (label2);
6205 emit_move_insn (operands[0], const1_rtx);
6206 emit_label (label3);
6208 emit_move_insn (operands[0], operands[0]);
6212 (define_expand "umodsi3"
6213 [(set (match_operand:SI 0 "register_operand" "=d")
6214 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
6215 (match_operand:SI 2 "nonimmediate_operand" "")))
6216 (clobber (match_dup 3))]
6217 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
6219 rtx insn, udiv_equal, umod_equal, equal;
6221 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
6222 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
6223 equal = gen_rtx_IOR (DImode,
6224 gen_rtx_ASHIFT (DImode,
6225 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
6227 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
6229 operands[3] = gen_reg_rtx (DImode);
6231 if (CONSTANT_P (operands[2]))
6233 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
6235 rtx_code_label *label1 = gen_label_rtx ();
6237 operands[1] = make_safe_from (operands[1], operands[0]);
6238 emit_move_insn (operands[0], operands[1]);
6239 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
6241 emit_insn (gen_abssi2 (operands[0], operands[2]));
6242 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
6243 emit_label (label1);
6247 operands[2] = force_reg (SImode, operands[2]);
6248 operands[2] = make_safe_from (operands[2], operands[0]);
6250 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6251 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6253 set_unique_reg_note (insn, REG_EQUAL, equal);
6255 insn = emit_move_insn (operands[0],
6256 gen_highpart (SImode, operands[3]));
6257 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6262 rtx_code_label *label1 = gen_label_rtx ();
6263 rtx_code_label *label2 = gen_label_rtx ();
6264 rtx_code_label *label3 = gen_label_rtx ();
6266 operands[1] = force_reg (SImode, operands[1]);
6267 operands[1] = make_safe_from (operands[1], operands[0]);
6268 operands[2] = force_reg (SImode, operands[2]);
6269 operands[2] = make_safe_from (operands[2], operands[0]);
6271 emit_move_insn(operands[0], operands[1]);
6272 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
6274 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
6276 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
6278 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
6279 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
6281 set_unique_reg_note (insn, REG_EQUAL, equal);
6283 insn = emit_move_insn (operands[0],
6284 gen_highpart (SImode, operands[3]));
6285 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6288 emit_label (label1);
6289 emit_move_insn (operands[0], const0_rtx);
6291 emit_label (label2);
6292 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6293 emit_label (label3);
6299 ; div(df|sf)3 instruction pattern(s).
6302 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6303 (define_insn "div<mode>3"
6304 [(set (match_operand:FP 0 "register_operand" "=f,f")
6305 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6306 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6309 d<xde><bt>r\t%0,<op1>%2
6311 [(set_attr "op_type" "<RRer>,RXE")
6312 (set_attr "type" "fdiv<mode>")])
6316 ;;- And instructions.
6319 (define_expand "and<mode>3"
6320 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6321 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6322 (match_operand:INT 2 "general_operand" "")))
6323 (clobber (reg:CC CC_REGNUM))]
6325 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6328 ; anddi3 instruction pattern(s).
6331 (define_insn "*anddi3_cc"
6332 [(set (reg CC_REGNUM)
6334 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6335 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6337 (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
6338 (and:DI (match_dup 1) (match_dup 2)))]
6339 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
6344 risbg\t%0,%1,%s2,128+%e2,0"
6345 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6346 (set_attr "cpu_facility" "*,z196,*,z10")
6347 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6349 (define_insn "*anddi3_cconly"
6350 [(set (reg CC_REGNUM)
6352 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
6353 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
6355 (clobber (match_scratch:DI 0 "=d,d, d, d"))]
6357 && s390_match_ccmode(insn, CCTmode)
6358 /* Do not steal TM patterns. */
6359 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6364 risbg\t%0,%1,%s2,128+%e2,0"
6365 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
6366 (set_attr "cpu_facility" "*,z196,*,z10")
6367 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
6369 (define_insn "*anddi3"
6370 [(set (match_operand:DI 0 "nonimmediate_operand"
6371 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
6373 (match_operand:DI 1 "nonimmediate_operand"
6374 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
6375 (match_operand:DI 2 "general_operand"
6376 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
6377 (clobber (reg:CC CC_REGNUM))]
6378 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6391 risbg\t%0,%1,%s2,128+%e2,0
6394 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
6395 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
6396 (set_attr "z10prop" "*,
6412 [(set (match_operand:DI 0 "s_operand" "")
6413 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6414 (clobber (reg:CC CC_REGNUM))]
6417 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6418 (clobber (reg:CC CC_REGNUM))])]
6419 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6421 ;; These two are what combine generates for (ashift (zero_extract)).
6422 (define_insn "*extzv_<mode>_srl"
6423 [(set (match_operand:GPR 0 "register_operand" "=d")
6424 (and:GPR (lshiftrt:GPR
6425 (match_operand:GPR 1 "register_operand" "d")
6426 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6427 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6428 (clobber (reg:CC CC_REGNUM))]
6430 /* Note that even for the SImode pattern, the rotate is always DImode. */
6431 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
6432 INTVAL (operands[3]))"
6433 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
6434 [(set_attr "op_type" "RIE")
6435 (set_attr "z10prop" "z10_super_E1")])
6437 (define_insn "*extzv_<mode>_sll"
6438 [(set (match_operand:GPR 0 "register_operand" "=d")
6439 (and:GPR (ashift:GPR
6440 (match_operand:GPR 1 "register_operand" "d")
6441 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
6442 (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
6443 (clobber (reg:CC CC_REGNUM))]
6445 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
6446 INTVAL (operands[3]))"
6447 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
6448 [(set_attr "op_type" "RIE")
6449 (set_attr "z10prop" "z10_super_E1")])
6453 ; andsi3 instruction pattern(s).
6456 (define_insn "*andsi3_cc"
6457 [(set (reg CC_REGNUM)
6460 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6461 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6463 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
6464 (and:SI (match_dup 1) (match_dup 2)))]
6465 "s390_match_ccmode(insn, CCTmode)"
6472 risbg\t%0,%1,%t2,128+%f2,0"
6473 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6474 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6475 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6476 z10_super_E1,z10_super_E1,z10_super_E1")])
6478 (define_insn "*andsi3_cconly"
6479 [(set (reg CC_REGNUM)
6482 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
6483 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
6485 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
6486 "s390_match_ccmode(insn, CCTmode)
6487 /* Do not steal TM patterns. */
6488 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6495 risbg\t%0,%1,%t2,128+%f2,0"
6496 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
6497 (set_attr "cpu_facility" "*,*,z196,*,*,z10")
6498 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6499 z10_super_E1,z10_super_E1,z10_super_E1")])
6501 (define_insn "*andsi3_zarch"
6502 [(set (match_operand:SI 0 "nonimmediate_operand"
6503 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
6504 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6505 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
6506 (match_operand:SI 2 "general_operand"
6507 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
6508 (clobber (reg:CC CC_REGNUM))]
6509 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6520 risbg\t%0,%1,%t2,128+%f2,0
6523 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
6524 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
6525 (set_attr "z10prop" "*,
6538 (define_insn "*andsi3_esa"
6539 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6540 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6541 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6542 (clobber (reg:CC CC_REGNUM))]
6543 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6549 [(set_attr "op_type" "RR,RX,SI,SS")
6550 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6554 [(set (match_operand:SI 0 "s_operand" "")
6555 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6556 (clobber (reg:CC CC_REGNUM))]
6559 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6560 (clobber (reg:CC CC_REGNUM))])]
6561 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6564 ; andhi3 instruction pattern(s).
6567 (define_insn "*andhi3_zarch"
6568 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6569 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6570 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6571 (clobber (reg:CC CC_REGNUM))]
6572 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6579 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6580 (set_attr "cpu_facility" "*,z196,*,*,*")
6581 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6584 (define_insn "*andhi3_esa"
6585 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6586 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6587 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6588 (clobber (reg:CC CC_REGNUM))]
6589 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6594 [(set_attr "op_type" "RR,SI,SS")
6595 (set_attr "z10prop" "z10_super_E1,*,*")
6599 [(set (match_operand:HI 0 "s_operand" "")
6600 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6601 (clobber (reg:CC CC_REGNUM))]
6604 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6605 (clobber (reg:CC CC_REGNUM))])]
6606 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6609 ; andqi3 instruction pattern(s).
6612 (define_insn "*andqi3_zarch"
6613 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6614 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6615 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6616 (clobber (reg:CC CC_REGNUM))]
6617 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6625 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6626 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6627 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6629 (define_insn "*andqi3_esa"
6630 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6631 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6632 (match_operand:QI 2 "general_operand" "d,n,Q")))
6633 (clobber (reg:CC CC_REGNUM))]
6634 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6639 [(set_attr "op_type" "RR,SI,SS")
6640 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6643 ; Block and (NC) patterns.
6647 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6648 (and:BLK (match_dup 0)
6649 (match_operand:BLK 1 "memory_operand" "Q")))
6650 (use (match_operand 2 "const_int_operand" "n"))
6651 (clobber (reg:CC CC_REGNUM))]
6652 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6653 "nc\t%O0(%2,%R0),%S1"
6654 [(set_attr "op_type" "SS")
6655 (set_attr "z196prop" "z196_cracked")])
6658 [(set (match_operand 0 "memory_operand" "")
6660 (match_operand 1 "memory_operand" "")))
6661 (clobber (reg:CC CC_REGNUM))]
6663 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6664 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6666 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6668 (clobber (reg:CC CC_REGNUM))])]
6670 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6671 operands[0] = adjust_address (operands[0], BLKmode, 0);
6672 operands[1] = adjust_address (operands[1], BLKmode, 0);
6677 [(set (match_operand:BLK 0 "memory_operand" "")
6678 (and:BLK (match_dup 0)
6679 (match_operand:BLK 1 "memory_operand" "")))
6680 (use (match_operand 2 "const_int_operand" ""))
6681 (clobber (reg:CC CC_REGNUM))])
6683 [(set (match_operand:BLK 3 "memory_operand" "")
6684 (and:BLK (match_dup 3)
6685 (match_operand:BLK 4 "memory_operand" "")))
6686 (use (match_operand 5 "const_int_operand" ""))
6687 (clobber (reg:CC CC_REGNUM))])]
6688 "s390_offset_p (operands[0], operands[3], operands[2])
6689 && s390_offset_p (operands[1], operands[4], operands[2])
6690 && !s390_overlap_p (operands[0], operands[1],
6691 INTVAL (operands[2]) + INTVAL (operands[5]))
6692 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6694 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6696 (clobber (reg:CC CC_REGNUM))])]
6697 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6698 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6699 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6703 ;;- Bit set (inclusive or) instructions.
6706 (define_expand "ior<mode>3"
6707 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6708 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6709 (match_operand:INT 2 "general_operand" "")))
6710 (clobber (reg:CC CC_REGNUM))]
6712 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6715 ; iordi3 instruction pattern(s).
6718 (define_insn "*iordi3_cc"
6719 [(set (reg CC_REGNUM)
6720 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6721 (match_operand:DI 2 "general_operand" " d,d,RT"))
6723 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6724 (ior:DI (match_dup 1) (match_dup 2)))]
6725 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6730 [(set_attr "op_type" "RRE,RRF,RXY")
6731 (set_attr "cpu_facility" "*,z196,*")
6732 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6734 (define_insn "*iordi3_cconly"
6735 [(set (reg CC_REGNUM)
6736 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6737 (match_operand:DI 2 "general_operand" " d,d,RT"))
6739 (clobber (match_scratch:DI 0 "=d,d,d"))]
6740 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6745 [(set_attr "op_type" "RRE,RRF,RXY")
6746 (set_attr "cpu_facility" "*,z196,*")
6747 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6749 (define_insn "*iordi3"
6750 [(set (match_operand:DI 0 "nonimmediate_operand"
6751 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6752 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6753 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6754 (match_operand:DI 2 "general_operand"
6755 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6756 (clobber (reg:CC CC_REGNUM))]
6757 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6770 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6771 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6772 (set_attr "z10prop" "z10_super_E1,
6785 [(set (match_operand:DI 0 "s_operand" "")
6786 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6787 (clobber (reg:CC CC_REGNUM))]
6790 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6791 (clobber (reg:CC CC_REGNUM))])]
6792 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6795 ; iorsi3 instruction pattern(s).
6798 (define_insn "*iorsi3_cc"
6799 [(set (reg CC_REGNUM)
6800 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6801 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6803 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6804 (ior:SI (match_dup 1) (match_dup 2)))]
6805 "s390_match_ccmode(insn, CCTmode)"
6812 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6813 (set_attr "cpu_facility" "*,*,z196,*,*")
6814 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6816 (define_insn "*iorsi3_cconly"
6817 [(set (reg CC_REGNUM)
6818 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6819 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6821 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6822 "s390_match_ccmode(insn, CCTmode)"
6829 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6830 (set_attr "cpu_facility" "*,*,z196,*,*")
6831 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6833 (define_insn "*iorsi3_zarch"
6834 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6835 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6836 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6837 (clobber (reg:CC CC_REGNUM))]
6838 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6849 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6850 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6851 (set_attr "z10prop" "z10_super_E1,
6861 (define_insn "*iorsi3_esa"
6862 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6863 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6864 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6865 (clobber (reg:CC CC_REGNUM))]
6866 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6872 [(set_attr "op_type" "RR,RX,SI,SS")
6873 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6876 [(set (match_operand:SI 0 "s_operand" "")
6877 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6878 (clobber (reg:CC CC_REGNUM))]
6881 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6882 (clobber (reg:CC CC_REGNUM))])]
6883 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6886 ; iorhi3 instruction pattern(s).
6889 (define_insn "*iorhi3_zarch"
6890 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6891 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6892 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6893 (clobber (reg:CC CC_REGNUM))]
6894 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6901 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6902 (set_attr "cpu_facility" "*,z196,*,*,*")
6903 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6905 (define_insn "*iorhi3_esa"
6906 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6907 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6908 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6909 (clobber (reg:CC CC_REGNUM))]
6910 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6915 [(set_attr "op_type" "RR,SI,SS")
6916 (set_attr "z10prop" "z10_super_E1,*,*")])
6919 [(set (match_operand:HI 0 "s_operand" "")
6920 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6921 (clobber (reg:CC CC_REGNUM))]
6924 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6925 (clobber (reg:CC CC_REGNUM))])]
6926 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6929 ; iorqi3 instruction pattern(s).
6932 (define_insn "*iorqi3_zarch"
6933 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6934 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6935 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6936 (clobber (reg:CC CC_REGNUM))]
6937 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6945 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6946 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6947 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6948 z10_super,z10_super,*")])
6950 (define_insn "*iorqi3_esa"
6951 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6952 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6953 (match_operand:QI 2 "general_operand" "d,n,Q")))
6954 (clobber (reg:CC CC_REGNUM))]
6955 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6960 [(set_attr "op_type" "RR,SI,SS")
6961 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6964 ; Block inclusive or (OC) patterns.
6968 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6969 (ior:BLK (match_dup 0)
6970 (match_operand:BLK 1 "memory_operand" "Q")))
6971 (use (match_operand 2 "const_int_operand" "n"))
6972 (clobber (reg:CC CC_REGNUM))]
6973 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6974 "oc\t%O0(%2,%R0),%S1"
6975 [(set_attr "op_type" "SS")
6976 (set_attr "z196prop" "z196_cracked")])
6979 [(set (match_operand 0 "memory_operand" "")
6981 (match_operand 1 "memory_operand" "")))
6982 (clobber (reg:CC CC_REGNUM))]
6984 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6985 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6987 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6989 (clobber (reg:CC CC_REGNUM))])]
6991 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6992 operands[0] = adjust_address (operands[0], BLKmode, 0);
6993 operands[1] = adjust_address (operands[1], BLKmode, 0);
6998 [(set (match_operand:BLK 0 "memory_operand" "")
6999 (ior:BLK (match_dup 0)
7000 (match_operand:BLK 1 "memory_operand" "")))
7001 (use (match_operand 2 "const_int_operand" ""))
7002 (clobber (reg:CC CC_REGNUM))])
7004 [(set (match_operand:BLK 3 "memory_operand" "")
7005 (ior:BLK (match_dup 3)
7006 (match_operand:BLK 4 "memory_operand" "")))
7007 (use (match_operand 5 "const_int_operand" ""))
7008 (clobber (reg:CC CC_REGNUM))])]
7009 "s390_offset_p (operands[0], operands[3], operands[2])
7010 && s390_offset_p (operands[1], operands[4], operands[2])
7011 && !s390_overlap_p (operands[0], operands[1],
7012 INTVAL (operands[2]) + INTVAL (operands[5]))
7013 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7015 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
7017 (clobber (reg:CC CC_REGNUM))])]
7018 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7019 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7020 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7024 ;;- Xor instructions.
7027 (define_expand "xor<mode>3"
7028 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7029 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
7030 (match_operand:INT 2 "general_operand" "")))
7031 (clobber (reg:CC CC_REGNUM))]
7033 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
7035 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
7036 ; simplifications. So its better to have something matching.
7038 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7039 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
7042 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
7043 (clobber (reg:CC CC_REGNUM))])]
7045 operands[2] = constm1_rtx;
7046 if (!s390_logical_operator_ok_p (operands))
7051 ; xordi3 instruction pattern(s).
7054 (define_insn "*xordi3_cc"
7055 [(set (reg CC_REGNUM)
7056 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7057 (match_operand:DI 2 "general_operand" " d,d,RT"))
7059 (set (match_operand:DI 0 "register_operand" "=d,d, d")
7060 (xor:DI (match_dup 1) (match_dup 2)))]
7061 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7066 [(set_attr "op_type" "RRE,RRF,RXY")
7067 (set_attr "cpu_facility" "*,z196,*")
7068 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7070 (define_insn "*xordi3_cconly"
7071 [(set (reg CC_REGNUM)
7072 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
7073 (match_operand:DI 2 "general_operand" " d,d,RT"))
7075 (clobber (match_scratch:DI 0 "=d,d, d"))]
7076 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7081 [(set_attr "op_type" "RRE,RRF,RXY")
7082 (set_attr "cpu_facility" "*,z196,*")
7083 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7085 (define_insn "*xordi3"
7086 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
7087 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
7088 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
7089 (clobber (reg:CC CC_REGNUM))]
7090 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7099 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
7100 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
7101 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
7102 *,z10_super_E1,*,*")])
7105 [(set (match_operand:DI 0 "s_operand" "")
7106 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7107 (clobber (reg:CC CC_REGNUM))]
7110 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7111 (clobber (reg:CC CC_REGNUM))])]
7112 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7115 ; xorsi3 instruction pattern(s).
7118 (define_insn "*xorsi3_cc"
7119 [(set (reg CC_REGNUM)
7120 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7121 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7123 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7124 (xor:SI (match_dup 1) (match_dup 2)))]
7125 "s390_match_ccmode(insn, CCTmode)"
7132 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7133 (set_attr "cpu_facility" "*,*,z196,*,*")
7134 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7135 z10_super_E1,z10_super_E1")])
7137 (define_insn "*xorsi3_cconly"
7138 [(set (reg CC_REGNUM)
7139 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7140 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7142 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7143 "s390_match_ccmode(insn, CCTmode)"
7150 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7151 (set_attr "cpu_facility" "*,*,z196,*,*")
7152 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7153 z10_super_E1,z10_super_E1")])
7155 (define_insn "*xorsi3"
7156 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
7157 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
7158 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
7159 (clobber (reg:CC CC_REGNUM))]
7160 "s390_logical_operator_ok_p (operands)"
7169 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
7170 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
7171 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7172 z10_super_E1,z10_super_E1,*,*")])
7175 [(set (match_operand:SI 0 "s_operand" "")
7176 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7177 (clobber (reg:CC CC_REGNUM))]
7180 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7181 (clobber (reg:CC CC_REGNUM))])]
7182 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7185 ; xorhi3 instruction pattern(s).
7188 (define_insn "*xorhi3"
7189 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7190 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
7191 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
7192 (clobber (reg:CC CC_REGNUM))]
7193 "s390_logical_operator_ok_p (operands)"
7200 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
7201 (set_attr "cpu_facility" "*,*,z196,*,*")
7202 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
7205 [(set (match_operand:HI 0 "s_operand" "")
7206 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7207 (clobber (reg:CC CC_REGNUM))]
7210 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7211 (clobber (reg:CC CC_REGNUM))])]
7212 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
7215 ; xorqi3 instruction pattern(s).
7218 (define_insn "*xorqi3"
7219 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7220 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
7221 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
7222 (clobber (reg:CC CC_REGNUM))]
7223 "s390_logical_operator_ok_p (operands)"
7231 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
7232 (set_attr "cpu_facility" "*,*,z196,*,*,*")
7233 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
7237 ; Block exclusive or (XC) patterns.
7241 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7242 (xor:BLK (match_dup 0)
7243 (match_operand:BLK 1 "memory_operand" "Q")))
7244 (use (match_operand 2 "const_int_operand" "n"))
7245 (clobber (reg:CC CC_REGNUM))]
7246 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7247 "xc\t%O0(%2,%R0),%S1"
7248 [(set_attr "op_type" "SS")])
7251 [(set (match_operand 0 "memory_operand" "")
7253 (match_operand 1 "memory_operand" "")))
7254 (clobber (reg:CC CC_REGNUM))]
7256 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7257 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7259 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
7261 (clobber (reg:CC CC_REGNUM))])]
7263 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7264 operands[0] = adjust_address (operands[0], BLKmode, 0);
7265 operands[1] = adjust_address (operands[1], BLKmode, 0);
7270 [(set (match_operand:BLK 0 "memory_operand" "")
7271 (xor:BLK (match_dup 0)
7272 (match_operand:BLK 1 "memory_operand" "")))
7273 (use (match_operand 2 "const_int_operand" ""))
7274 (clobber (reg:CC CC_REGNUM))])
7276 [(set (match_operand:BLK 3 "memory_operand" "")
7277 (xor:BLK (match_dup 3)
7278 (match_operand:BLK 4 "memory_operand" "")))
7279 (use (match_operand 5 "const_int_operand" ""))
7280 (clobber (reg:CC CC_REGNUM))])]
7281 "s390_offset_p (operands[0], operands[3], operands[2])
7282 && s390_offset_p (operands[1], operands[4], operands[2])
7283 && !s390_overlap_p (operands[0], operands[1],
7284 INTVAL (operands[2]) + INTVAL (operands[5]))
7285 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7287 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
7289 (clobber (reg:CC CC_REGNUM))])]
7290 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7291 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7292 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7295 ; Block xor (XC) patterns with src == dest.
7298 (define_insn "*xc_zero"
7299 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7301 (use (match_operand 1 "const_int_operand" "n"))
7302 (clobber (reg:CC CC_REGNUM))]
7303 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
7304 "xc\t%O0(%1,%R0),%S0"
7305 [(set_attr "op_type" "SS")
7306 (set_attr "z196prop" "z196_cracked")])
7310 [(set (match_operand:BLK 0 "memory_operand" "")
7312 (use (match_operand 1 "const_int_operand" ""))
7313 (clobber (reg:CC CC_REGNUM))])
7315 [(set (match_operand:BLK 2 "memory_operand" "")
7317 (use (match_operand 3 "const_int_operand" ""))
7318 (clobber (reg:CC CC_REGNUM))])]
7319 "s390_offset_p (operands[0], operands[2], operands[1])
7320 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
7322 [(set (match_dup 4) (const_int 0))
7324 (clobber (reg:CC CC_REGNUM))])]
7325 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7326 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
7330 ;;- Negate instructions.
7334 ; neg(di|si)2 instruction pattern(s).
7337 (define_expand "neg<mode>2"
7339 [(set (match_operand:DSI 0 "register_operand" "=d")
7340 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
7341 (clobber (reg:CC CC_REGNUM))])]
7345 (define_insn "*negdi2_sign_cc"
7346 [(set (reg CC_REGNUM)
7347 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7348 (match_operand:SI 1 "register_operand" "d") 0)
7349 (const_int 32)) (const_int 32)))
7351 (set (match_operand:DI 0 "register_operand" "=d")
7352 (neg:DI (sign_extend:DI (match_dup 1))))]
7353 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7355 [(set_attr "op_type" "RRE")
7356 (set_attr "z10prop" "z10_c")])
7358 (define_insn "*negdi2_sign"
7359 [(set (match_operand:DI 0 "register_operand" "=d")
7360 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7361 (clobber (reg:CC CC_REGNUM))]
7364 [(set_attr "op_type" "RRE")
7365 (set_attr "z10prop" "z10_c")])
7368 (define_insn "*neg<mode>2_cc"
7369 [(set (reg CC_REGNUM)
7370 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7372 (set (match_operand:GPR 0 "register_operand" "=d")
7373 (neg:GPR (match_dup 1)))]
7374 "s390_match_ccmode (insn, CCAmode)"
7376 [(set_attr "op_type" "RR<E>")
7377 (set_attr "z10prop" "z10_super_c_E1")])
7380 (define_insn "*neg<mode>2_cconly"
7381 [(set (reg CC_REGNUM)
7382 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7384 (clobber (match_scratch:GPR 0 "=d"))]
7385 "s390_match_ccmode (insn, CCAmode)"
7387 [(set_attr "op_type" "RR<E>")
7388 (set_attr "z10prop" "z10_super_c_E1")])
7391 (define_insn "*neg<mode>2"
7392 [(set (match_operand:GPR 0 "register_operand" "=d")
7393 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7394 (clobber (reg:CC CC_REGNUM))]
7397 [(set_attr "op_type" "RR<E>")
7398 (set_attr "z10prop" "z10_super_c_E1")])
7400 (define_insn "*negdi2_31"
7401 [(set (match_operand:DI 0 "register_operand" "=d")
7402 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7403 (clobber (reg:CC CC_REGNUM))]
7407 ; Split a DImode NEG on 31bit into 2 SImode NEGs
7409 ; Doing the twos complement separately on the SImode parts does an
7410 ; unwanted +1 on the high part which needs to be subtracted afterwards
7411 ; ... unless the +1 on the low part created an overflow.
7414 [(set (match_operand:DI 0 "register_operand" "")
7415 (neg:DI (match_operand:DI 1 "register_operand" "")))
7416 (clobber (reg:CC CC_REGNUM))]
7418 && (REGNO (operands[0]) == REGNO (operands[1])
7419 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
7420 && reload_completed"
7422 [(set (match_dup 2) (neg:SI (match_dup 3)))
7423 (clobber (reg:CC CC_REGNUM))])
7425 [(set (reg:CCAP CC_REGNUM)
7426 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7427 (set (match_dup 4) (neg:SI (match_dup 5)))])
7429 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7431 (label_ref (match_dup 6))))
7433 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7434 (clobber (reg:CC CC_REGNUM))])
7436 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7437 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7438 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7439 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7440 operands[6] = gen_label_rtx ();")
7442 ; Like above but first make a copy of the low part of the src operand
7443 ; since it might overlap with the high part of the destination.
7446 [(set (match_operand:DI 0 "register_operand" "")
7447 (neg:DI (match_operand:DI 1 "register_operand" "")))
7448 (clobber (reg:CC CC_REGNUM))]
7450 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
7451 && reload_completed"
7452 [; Make a backup of op5 first
7453 (set (match_dup 4) (match_dup 5))
7454 ; Setting op2 here might clobber op5
7456 [(set (match_dup 2) (neg:SI (match_dup 3)))
7457 (clobber (reg:CC CC_REGNUM))])
7459 [(set (reg:CCAP CC_REGNUM)
7460 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
7461 (set (match_dup 4) (neg:SI (match_dup 4)))])
7463 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7465 (label_ref (match_dup 6))))
7467 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7468 (clobber (reg:CC CC_REGNUM))])
7470 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7471 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7472 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7473 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7474 operands[6] = gen_label_rtx ();")
7477 ; neg(df|sf)2 instruction pattern(s).
7480 (define_expand "neg<mode>2"
7482 [(set (match_operand:BFP 0 "register_operand" "=f")
7483 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7484 (clobber (reg:CC CC_REGNUM))])]
7488 ; lcxbr, lcdbr, lcebr
7489 (define_insn "*neg<mode>2_cc"
7490 [(set (reg CC_REGNUM)
7491 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7492 (match_operand:BFP 2 "const0_operand" "")))
7493 (set (match_operand:BFP 0 "register_operand" "=f")
7494 (neg:BFP (match_dup 1)))]
7495 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7497 [(set_attr "op_type" "RRE")
7498 (set_attr "type" "fsimp<mode>")])
7500 ; lcxbr, lcdbr, lcebr
7501 (define_insn "*neg<mode>2_cconly"
7502 [(set (reg CC_REGNUM)
7503 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7504 (match_operand:BFP 2 "const0_operand" "")))
7505 (clobber (match_scratch:BFP 0 "=f"))]
7506 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7508 [(set_attr "op_type" "RRE")
7509 (set_attr "type" "fsimp<mode>")])
7512 (define_insn "*neg<mode>2_nocc"
7513 [(set (match_operand:FP 0 "register_operand" "=f")
7514 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7517 [(set_attr "op_type" "RRE")
7518 (set_attr "type" "fsimp<mode>")])
7520 ; lcxbr, lcdbr, lcebr
7521 (define_insn "*neg<mode>2"
7522 [(set (match_operand:BFP 0 "register_operand" "=f")
7523 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7524 (clobber (reg:CC CC_REGNUM))]
7527 [(set_attr "op_type" "RRE")
7528 (set_attr "type" "fsimp<mode>")])
7532 ;;- Absolute value instructions.
7536 ; abs(di|si)2 instruction pattern(s).
7539 (define_insn "*absdi2_sign_cc"
7540 [(set (reg CC_REGNUM)
7541 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7542 (match_operand:SI 1 "register_operand" "d") 0)
7543 (const_int 32)) (const_int 32)))
7545 (set (match_operand:DI 0 "register_operand" "=d")
7546 (abs:DI (sign_extend:DI (match_dup 1))))]
7547 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7549 [(set_attr "op_type" "RRE")
7550 (set_attr "z10prop" "z10_c")])
7552 (define_insn "*absdi2_sign"
7553 [(set (match_operand:DI 0 "register_operand" "=d")
7554 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7555 (clobber (reg:CC CC_REGNUM))]
7558 [(set_attr "op_type" "RRE")
7559 (set_attr "z10prop" "z10_c")])
7562 (define_insn "*abs<mode>2_cc"
7563 [(set (reg CC_REGNUM)
7564 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7566 (set (match_operand:GPR 0 "register_operand" "=d")
7567 (abs:GPR (match_dup 1)))]
7568 "s390_match_ccmode (insn, CCAmode)"
7570 [(set_attr "op_type" "RR<E>")
7571 (set_attr "z10prop" "z10_c")])
7574 (define_insn "*abs<mode>2_cconly"
7575 [(set (reg CC_REGNUM)
7576 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7578 (clobber (match_scratch:GPR 0 "=d"))]
7579 "s390_match_ccmode (insn, CCAmode)"
7581 [(set_attr "op_type" "RR<E>")
7582 (set_attr "z10prop" "z10_c")])
7585 (define_insn "abs<mode>2"
7586 [(set (match_operand:GPR 0 "register_operand" "=d")
7587 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7588 (clobber (reg:CC CC_REGNUM))]
7591 [(set_attr "op_type" "RR<E>")
7592 (set_attr "z10prop" "z10_c")])
7595 ; abs(df|sf)2 instruction pattern(s).
7598 (define_expand "abs<mode>2"
7600 [(set (match_operand:BFP 0 "register_operand" "=f")
7601 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7602 (clobber (reg:CC CC_REGNUM))])]
7606 ; lpxbr, lpdbr, lpebr
7607 (define_insn "*abs<mode>2_cc"
7608 [(set (reg CC_REGNUM)
7609 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7610 (match_operand:BFP 2 "const0_operand" "")))
7611 (set (match_operand:BFP 0 "register_operand" "=f")
7612 (abs:BFP (match_dup 1)))]
7613 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7615 [(set_attr "op_type" "RRE")
7616 (set_attr "type" "fsimp<mode>")])
7618 ; lpxbr, lpdbr, lpebr
7619 (define_insn "*abs<mode>2_cconly"
7620 [(set (reg CC_REGNUM)
7621 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7622 (match_operand:BFP 2 "const0_operand" "")))
7623 (clobber (match_scratch:BFP 0 "=f"))]
7624 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7626 [(set_attr "op_type" "RRE")
7627 (set_attr "type" "fsimp<mode>")])
7630 (define_insn "*abs<mode>2_nocc"
7631 [(set (match_operand:FP 0 "register_operand" "=f")
7632 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7635 [(set_attr "op_type" "RRE")
7636 (set_attr "type" "fsimp<mode>")])
7638 ; lpxbr, lpdbr, lpebr
7639 (define_insn "*abs<mode>2"
7640 [(set (match_operand:BFP 0 "register_operand" "=f")
7641 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7642 (clobber (reg:CC CC_REGNUM))]
7645 [(set_attr "op_type" "RRE")
7646 (set_attr "type" "fsimp<mode>")])
7650 ;;- Negated absolute value instructions
7657 (define_insn "*negabsdi2_sign_cc"
7658 [(set (reg CC_REGNUM)
7659 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7660 (match_operand:SI 1 "register_operand" "d") 0)
7661 (const_int 32)) (const_int 32))))
7663 (set (match_operand:DI 0 "register_operand" "=d")
7664 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7665 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7667 [(set_attr "op_type" "RRE")
7668 (set_attr "z10prop" "z10_c")])
7670 (define_insn "*negabsdi2_sign"
7671 [(set (match_operand:DI 0 "register_operand" "=d")
7672 (neg:DI (abs:DI (sign_extend:DI
7673 (match_operand:SI 1 "register_operand" "d")))))
7674 (clobber (reg:CC CC_REGNUM))]
7677 [(set_attr "op_type" "RRE")
7678 (set_attr "z10prop" "z10_c")])
7681 (define_insn "*negabs<mode>2_cc"
7682 [(set (reg CC_REGNUM)
7683 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7685 (set (match_operand:GPR 0 "register_operand" "=d")
7686 (neg:GPR (abs:GPR (match_dup 1))))]
7687 "s390_match_ccmode (insn, CCAmode)"
7689 [(set_attr "op_type" "RR<E>")
7690 (set_attr "z10prop" "z10_c")])
7693 (define_insn "*negabs<mode>2_cconly"
7694 [(set (reg CC_REGNUM)
7695 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7697 (clobber (match_scratch:GPR 0 "=d"))]
7698 "s390_match_ccmode (insn, CCAmode)"
7700 [(set_attr "op_type" "RR<E>")
7701 (set_attr "z10prop" "z10_c")])
7704 (define_insn "*negabs<mode>2"
7705 [(set (match_operand:GPR 0 "register_operand" "=d")
7706 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7707 (clobber (reg:CC CC_REGNUM))]
7710 [(set_attr "op_type" "RR<E>")
7711 (set_attr "z10prop" "z10_c")])
7717 ; lnxbr, lndbr, lnebr
7718 (define_insn "*negabs<mode>2_cc"
7719 [(set (reg CC_REGNUM)
7720 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7721 (match_operand:BFP 2 "const0_operand" "")))
7722 (set (match_operand:BFP 0 "register_operand" "=f")
7723 (neg:BFP (abs:BFP (match_dup 1))))]
7724 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7726 [(set_attr "op_type" "RRE")
7727 (set_attr "type" "fsimp<mode>")])
7729 ; lnxbr, lndbr, lnebr
7730 (define_insn "*negabs<mode>2_cconly"
7731 [(set (reg CC_REGNUM)
7732 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7733 (match_operand:BFP 2 "const0_operand" "")))
7734 (clobber (match_scratch:BFP 0 "=f"))]
7735 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7737 [(set_attr "op_type" "RRE")
7738 (set_attr "type" "fsimp<mode>")])
7741 (define_insn "*negabs<mode>2_nocc"
7742 [(set (match_operand:FP 0 "register_operand" "=f")
7743 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7746 [(set_attr "op_type" "RRE")
7747 (set_attr "type" "fsimp<mode>")])
7749 ; lnxbr, lndbr, lnebr
7750 (define_insn "*negabs<mode>2"
7751 [(set (match_operand:BFP 0 "register_operand" "=f")
7752 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7753 (clobber (reg:CC CC_REGNUM))]
7756 [(set_attr "op_type" "RRE")
7757 (set_attr "type" "fsimp<mode>")])
7760 ;;- Square root instructions.
7764 ; sqrt(df|sf)2 instruction pattern(s).
7767 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7768 (define_insn "sqrt<mode>2"
7769 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7770 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7775 [(set_attr "op_type" "RRE,RXE")
7776 (set_attr "type" "fsqrt<mode>")])
7780 ;;- One complement instructions.
7784 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7787 (define_expand "one_cmpl<mode>2"
7789 [(set (match_operand:INT 0 "register_operand" "")
7790 (xor:INT (match_operand:INT 1 "register_operand" "")
7792 (clobber (reg:CC CC_REGNUM))])]
7798 ;; Find leftmost bit instructions.
7801 (define_expand "clzdi2"
7802 [(set (match_operand:DI 0 "register_operand" "=d")
7803 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7804 "TARGET_EXTIMM && TARGET_ZARCH"
7806 rtx insn, clz_equal;
7807 rtx wide_reg = gen_reg_rtx (TImode);
7808 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7810 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7812 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7814 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7815 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7820 (define_insn "clztidi2"
7821 [(set (match_operand:TI 0 "register_operand" "=d")
7825 (xor:DI (match_operand:DI 1 "register_operand" "d")
7826 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7827 (subreg:SI (clz:DI (match_dup 1)) 4))))
7830 (zero_extend:TI (clz:DI (match_dup 1)))))
7831 (clobber (reg:CC CC_REGNUM))]
7832 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7833 == (unsigned HOST_WIDE_INT) 1 << 63
7834 && TARGET_EXTIMM && TARGET_ZARCH"
7836 [(set_attr "op_type" "RRE")])
7840 ;;- Rotate instructions.
7844 ; rotl(di|si)3 instruction pattern(s).
7848 (define_insn "rotl<mode>3"
7849 [(set (match_operand:GPR 0 "register_operand" "=d")
7850 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7851 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7854 [(set_attr "op_type" "RSE")
7855 (set_attr "atype" "reg")
7856 (set_attr "z10prop" "z10_super_E1")])
7859 (define_insn "*rotl<mode>3_and"
7860 [(set (match_operand:GPR 0 "register_operand" "=d")
7861 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7862 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7863 (match_operand:SI 3 "const_int_operand" "n"))))]
7864 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7866 [(set_attr "op_type" "RSE")
7867 (set_attr "atype" "reg")
7868 (set_attr "z10prop" "z10_super_E1")])
7872 ;;- Shift instructions.
7876 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7877 ; Left shifts and logical right shifts
7879 (define_expand "<shift><mode>3"
7880 [(set (match_operand:DSI 0 "register_operand" "")
7881 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7882 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7887 (define_insn "*<shift>di3_31"
7888 [(set (match_operand:DI 0 "register_operand" "=d")
7889 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7890 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7893 [(set_attr "op_type" "RS")
7894 (set_attr "atype" "reg")
7895 (set_attr "z196prop" "z196_cracked")])
7897 ; sll, srl, sllg, srlg, sllk, srlk
7898 (define_insn "*<shift><mode>3"
7899 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7900 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7901 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7904 s<lr>l<g>\t%0,<1>%Y2
7905 s<lr>l<gk>\t%0,%1,%Y2"
7906 [(set_attr "op_type" "RS<E>,RSY")
7907 (set_attr "atype" "reg,reg")
7908 (set_attr "cpu_facility" "*,z196")
7909 (set_attr "z10prop" "z10_super_E1,*")])
7912 (define_insn "*<shift>di3_31_and"
7913 [(set (match_operand:DI 0 "register_operand" "=d")
7914 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7915 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7916 (match_operand:SI 3 "const_int_operand" "n"))))]
7917 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7919 [(set_attr "op_type" "RS")
7920 (set_attr "atype" "reg")])
7922 ; sll, srl, sllg, srlg, sllk, srlk
7923 (define_insn "*<shift><mode>3_and"
7924 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7925 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7926 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7927 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7928 "(INTVAL (operands[3]) & 63) == 63"
7930 s<lr>l<g>\t%0,<1>%Y2
7931 s<lr>l<gk>\t%0,%1,%Y2"
7932 [(set_attr "op_type" "RS<E>,RSY")
7933 (set_attr "atype" "reg,reg")
7934 (set_attr "cpu_facility" "*,z196")
7935 (set_attr "z10prop" "z10_super_E1,*")])
7938 ; ashr(di|si)3 instruction pattern(s).
7939 ; Arithmetic right shifts
7941 (define_expand "ashr<mode>3"
7943 [(set (match_operand:DSI 0 "register_operand" "")
7944 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7945 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7946 (clobber (reg:CC CC_REGNUM))])]
7950 (define_insn "*ashrdi3_cc_31"
7951 [(set (reg CC_REGNUM)
7952 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7953 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7955 (set (match_operand:DI 0 "register_operand" "=d")
7956 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7957 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7959 [(set_attr "op_type" "RS")
7960 (set_attr "atype" "reg")])
7962 (define_insn "*ashrdi3_cconly_31"
7963 [(set (reg CC_REGNUM)
7964 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7965 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7967 (clobber (match_scratch:DI 0 "=d"))]
7968 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7970 [(set_attr "op_type" "RS")
7971 (set_attr "atype" "reg")])
7973 (define_insn "*ashrdi3_31"
7974 [(set (match_operand:DI 0 "register_operand" "=d")
7975 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7976 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7977 (clobber (reg:CC CC_REGNUM))]
7980 [(set_attr "op_type" "RS")
7981 (set_attr "atype" "reg")])
7984 (define_insn "*ashr<mode>3_cc"
7985 [(set (reg CC_REGNUM)
7986 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7987 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7989 (set (match_operand:GPR 0 "register_operand" "=d,d")
7990 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7991 "s390_match_ccmode(insn, CCSmode)"
7995 [(set_attr "op_type" "RS<E>,RSY")
7996 (set_attr "atype" "reg,reg")
7997 (set_attr "cpu_facility" "*,z196")
7998 (set_attr "z10prop" "z10_super_E1,*")])
8001 (define_insn "*ashr<mode>3_cconly"
8002 [(set (reg CC_REGNUM)
8003 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8004 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
8006 (clobber (match_scratch:GPR 0 "=d,d"))]
8007 "s390_match_ccmode(insn, CCSmode)"
8011 [(set_attr "op_type" "RS<E>,RSY")
8012 (set_attr "atype" "reg,reg")
8013 (set_attr "cpu_facility" "*,z196")
8014 (set_attr "z10prop" "z10_super_E1,*")])
8017 (define_insn "*ashr<mode>3"
8018 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8019 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8020 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
8021 (clobber (reg:CC CC_REGNUM))]
8026 [(set_attr "op_type" "RS<E>,RSY")
8027 (set_attr "atype" "reg,reg")
8028 (set_attr "cpu_facility" "*,z196")
8029 (set_attr "z10prop" "z10_super_E1,*")])
8032 ; shift pattern with implicit ANDs
8034 (define_insn "*ashrdi3_cc_31_and"
8035 [(set (reg CC_REGNUM)
8036 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8037 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8038 (match_operand:SI 3 "const_int_operand" "n")))
8040 (set (match_operand:DI 0 "register_operand" "=d")
8041 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8042 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8043 && (INTVAL (operands[3]) & 63) == 63"
8045 [(set_attr "op_type" "RS")
8046 (set_attr "atype" "reg")])
8048 (define_insn "*ashrdi3_cconly_31_and"
8049 [(set (reg CC_REGNUM)
8050 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8051 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8052 (match_operand:SI 3 "const_int_operand" "n")))
8054 (clobber (match_scratch:DI 0 "=d"))]
8055 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
8056 && (INTVAL (operands[3]) & 63) == 63"
8058 [(set_attr "op_type" "RS")
8059 (set_attr "atype" "reg")])
8061 (define_insn "*ashrdi3_31_and"
8062 [(set (match_operand:DI 0 "register_operand" "=d")
8063 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8064 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
8065 (match_operand:SI 3 "const_int_operand" "n"))))
8066 (clobber (reg:CC CC_REGNUM))]
8067 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
8069 [(set_attr "op_type" "RS")
8070 (set_attr "atype" "reg")])
8073 (define_insn "*ashr<mode>3_cc_and"
8074 [(set (reg CC_REGNUM)
8075 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8076 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8077 (match_operand:SI 3 "const_int_operand" "n,n")))
8079 (set (match_operand:GPR 0 "register_operand" "=d,d")
8080 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
8081 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8085 [(set_attr "op_type" "RS<E>,RSY")
8086 (set_attr "atype" "reg,reg")
8087 (set_attr "cpu_facility" "*,z196")
8088 (set_attr "z10prop" "z10_super_E1,*")])
8091 (define_insn "*ashr<mode>3_cconly_and"
8092 [(set (reg CC_REGNUM)
8093 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8094 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8095 (match_operand:SI 3 "const_int_operand" "n,n")))
8097 (clobber (match_scratch:GPR 0 "=d,d"))]
8098 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
8102 [(set_attr "op_type" "RS<E>,RSY")
8103 (set_attr "atype" "reg,reg")
8104 (set_attr "cpu_facility" "*,z196")
8105 (set_attr "z10prop" "z10_super_E1,*")])
8108 (define_insn "*ashr<mode>3_and"
8109 [(set (match_operand:GPR 0 "register_operand" "=d,d")
8110 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
8111 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
8112 (match_operand:SI 3 "const_int_operand" "n,n"))))
8113 (clobber (reg:CC CC_REGNUM))]
8114 "(INTVAL (operands[3]) & 63) == 63"
8118 [(set_attr "op_type" "RS<E>,RSY")
8119 (set_attr "atype" "reg,reg")
8120 (set_attr "cpu_facility" "*,z196")
8121 (set_attr "z10prop" "z10_super_E1,*")])
8125 ;; Branch instruction patterns.
8128 (define_expand "cbranch<mode>4"
8130 (if_then_else (match_operator 0 "comparison_operator"
8131 [(match_operand:GPR 1 "register_operand" "")
8132 (match_operand:GPR 2 "general_operand" "")])
8133 (label_ref (match_operand 3 "" ""))
8136 "s390_emit_jump (operands[3],
8137 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8140 (define_expand "cbranch<mode>4"
8142 (if_then_else (match_operator 0 "comparison_operator"
8143 [(match_operand:FP 1 "register_operand" "")
8144 (match_operand:FP 2 "general_operand" "")])
8145 (label_ref (match_operand 3 "" ""))
8148 "s390_emit_jump (operands[3],
8149 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8152 (define_expand "cbranchcc4"
8154 (if_then_else (match_operator 0 "s390_comparison"
8155 [(match_operand 1 "cc_reg_operand" "")
8156 (match_operand 2 "const_int_operand" "")])
8157 (label_ref (match_operand 3 "" ""))
8164 ;;- Conditional jump instructions.
8167 (define_insn "*cjump_64"
8170 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8171 (match_operand 2 "const_int_operand" "")])
8172 (label_ref (match_operand 0 "" ""))
8176 if (get_attr_length (insn) == 4)
8179 return "jg%C1\t%l0";
8181 [(set_attr "op_type" "RI")
8182 (set_attr "type" "branch")
8183 (set (attr "length")
8184 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8185 (const_int 4) (const_int 6)))])
8187 (define_insn "*cjump_31"
8190 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
8191 (match_operand 2 "const_int_operand" "")])
8192 (label_ref (match_operand 0 "" ""))
8196 gcc_assert (get_attr_length (insn) == 4);
8199 [(set_attr "op_type" "RI")
8200 (set_attr "type" "branch")
8201 (set (attr "length")
8202 (if_then_else (not (match_test "flag_pic"))
8203 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8204 (const_int 4) (const_int 6))
8205 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8206 (const_int 4) (const_int 8))))])
8208 (define_insn "*cjump_long"
8211 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8212 (match_operand 0 "address_operand" "ZQZR")
8216 if (get_attr_op_type (insn) == OP_TYPE_RR)
8221 [(set (attr "op_type")
8222 (if_then_else (match_operand 0 "register_operand" "")
8223 (const_string "RR") (const_string "RX")))
8224 (set_attr "type" "branch")
8225 (set_attr "atype" "agen")])
8227 ;; A conditional return instruction.
8228 (define_insn "*c<code>"
8231 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8234 "s390_can_use_<code>_insn ()"
8236 [(set_attr "op_type" "RR")
8237 (set_attr "type" "jsr")
8238 (set_attr "atype" "agen")])
8241 ;;- Negated conditional jump instructions.
8244 (define_insn "*icjump_64"
8247 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8249 (label_ref (match_operand 0 "" ""))))]
8252 if (get_attr_length (insn) == 4)
8255 return "jg%D1\t%l0";
8257 [(set_attr "op_type" "RI")
8258 (set_attr "type" "branch")
8259 (set (attr "length")
8260 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8261 (const_int 4) (const_int 6)))])
8263 (define_insn "*icjump_31"
8266 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8268 (label_ref (match_operand 0 "" ""))))]
8271 gcc_assert (get_attr_length (insn) == 4);
8274 [(set_attr "op_type" "RI")
8275 (set_attr "type" "branch")
8276 (set (attr "length")
8277 (if_then_else (not (match_test "flag_pic"))
8278 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8279 (const_int 4) (const_int 6))
8280 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8281 (const_int 4) (const_int 8))))])
8283 (define_insn "*icjump_long"
8286 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
8288 (match_operand 0 "address_operand" "ZQZR")))]
8291 if (get_attr_op_type (insn) == OP_TYPE_RR)
8296 [(set (attr "op_type")
8297 (if_then_else (match_operand 0 "register_operand" "")
8298 (const_string "RR") (const_string "RX")))
8299 (set_attr "type" "branch")
8300 (set_attr "atype" "agen")])
8303 ;;- Trap instructions.
8307 [(trap_if (const_int 1) (const_int 0))]
8310 [(set_attr "op_type" "RI")
8311 (set_attr "type" "branch")])
8313 (define_expand "ctrap<mode>4"
8314 [(trap_if (match_operator 0 "comparison_operator"
8315 [(match_operand:GPR 1 "register_operand" "")
8316 (match_operand:GPR 2 "general_operand" "")])
8317 (match_operand 3 "const0_operand" ""))]
8320 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8321 operands[1], operands[2]);
8322 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8326 (define_expand "ctrap<mode>4"
8327 [(trap_if (match_operator 0 "comparison_operator"
8328 [(match_operand:FP 1 "register_operand" "")
8329 (match_operand:FP 2 "general_operand" "")])
8330 (match_operand 3 "const0_operand" ""))]
8333 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
8334 operands[1], operands[2]);
8335 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
8339 (define_insn "condtrap"
8340 [(trap_if (match_operator 0 "s390_comparison"
8341 [(match_operand 1 "cc_reg_operand" "c")
8346 [(set_attr "op_type" "RI")
8347 (set_attr "type" "branch")])
8349 ; crt, cgrt, cit, cgit
8350 (define_insn "*cmp_and_trap_signed_int<mode>"
8351 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
8352 [(match_operand:GPR 1 "register_operand" "d,d")
8353 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
8359 [(set_attr "op_type" "RRF,RIE")
8360 (set_attr "type" "branch")
8361 (set_attr "z10prop" "z10_super_c,z10_super")])
8363 ; clrt, clgrt, clfit, clgit, clt, clgt
8364 (define_insn "*cmp_and_trap_unsigned_int<mode>"
8365 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
8366 [(match_operand:GPR 1 "register_operand" "d,d, d")
8367 (match_operand:GPR 2 "general_operand" "d,D,RT")])
8374 [(set_attr "op_type" "RRF,RIE,RSY")
8375 (set_attr "type" "branch")
8376 (set_attr "z10prop" "z10_super_c,z10_super,*")
8377 (set_attr "cpu_facility" "z10,z10,zEC12")])
8380 (define_insn "*load_and_trap<mode>"
8381 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
8384 (set (match_operand:GPR 1 "register_operand" "=d")
8388 [(set_attr "op_type" "RXY")])
8392 ;;- Loop instructions.
8394 ;; This is all complicated by the fact that since this is a jump insn
8395 ;; we must handle our own output reloads.
8399 ; This splitter will be matched by combine and has to add the 2 moves
8400 ; necessary to load the compare and the increment values into a
8401 ; register pair as needed by brxle.
8403 (define_insn_and_split "*brx_stage1_<GPR:mode>"
8406 (match_operator 6 "s390_brx_operator"
8407 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8408 (match_operand:GPR 2 "general_operand" ""))
8409 (match_operand:GPR 3 "register_operand" "")])
8410 (label_ref (match_operand 0 "" ""))
8412 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8413 (plus:GPR (match_dup 1) (match_dup 2)))
8414 (clobber (match_scratch:GPR 5 ""))]
8417 "!reload_completed && !reload_in_progress"
8418 [(set (match_dup 7) (match_dup 2)) ; the increment
8419 (set (match_dup 8) (match_dup 3)) ; the comparison value
8420 (parallel [(set (pc)
8423 [(plus:GPR (match_dup 1) (match_dup 7))
8425 (label_ref (match_dup 0))
8428 (plus:GPR (match_dup 1) (match_dup 7)))
8429 (clobber (match_dup 5))
8430 (clobber (reg:CC CC_REGNUM))])]
8432 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8433 operands[7] = gen_lowpart (<GPR:MODE>mode,
8434 gen_highpart (word_mode, dreg));
8435 operands[8] = gen_lowpart (<GPR:MODE>mode,
8436 gen_lowpart (word_mode, dreg));
8441 (define_insn_and_split "*brxg_64bit"
8444 (match_operator 5 "s390_brx_operator"
8445 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8446 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8447 (subreg:DI (match_dup 2) 8)])
8448 (label_ref (match_operand 0 "" ""))
8450 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8451 (plus:DI (match_dup 1)
8452 (subreg:DI (match_dup 2) 0)))
8453 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8454 (clobber (reg:CC CC_REGNUM))]
8457 if (which_alternative != 0)
8459 else if (get_attr_length (insn) == 6)
8460 return "brx%E5g\t%1,%2,%l0";
8462 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8464 "&& reload_completed
8465 && (!REG_P (operands[3])
8466 || !rtx_equal_p (operands[1], operands[3]))"
8467 [(set (match_dup 4) (match_dup 1))
8468 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8469 (clobber (reg:CC CC_REGNUM))])
8470 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8471 (set (match_dup 3) (match_dup 4))
8472 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8473 (label_ref (match_dup 0))
8476 [(set_attr "op_type" "RIE")
8477 (set_attr "type" "branch")
8478 (set (attr "length")
8479 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8480 (const_int 6) (const_int 16)))])
8484 (define_insn_and_split "*brx_64bit"
8487 (match_operator 5 "s390_brx_operator"
8488 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8489 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8490 (subreg:SI (match_dup 2) 12)])
8491 (label_ref (match_operand 0 "" ""))
8493 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8494 (plus:SI (match_dup 1)
8495 (subreg:SI (match_dup 2) 4)))
8496 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8497 (clobber (reg:CC CC_REGNUM))]
8500 if (which_alternative != 0)
8502 else if (get_attr_length (insn) == 6)
8503 return "brx%C5\t%1,%2,%l0";
8505 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8507 "&& reload_completed
8508 && (!REG_P (operands[3])
8509 || !rtx_equal_p (operands[1], operands[3]))"
8510 [(set (match_dup 4) (match_dup 1))
8511 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8512 (clobber (reg:CC CC_REGNUM))])
8513 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8514 (set (match_dup 3) (match_dup 4))
8515 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8516 (label_ref (match_dup 0))
8519 [(set_attr "op_type" "RSI")
8520 (set_attr "type" "branch")
8521 (set (attr "length")
8522 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8523 (const_int 6) (const_int 14)))])
8527 (define_insn_and_split "*brx_31bit"
8530 (match_operator 5 "s390_brx_operator"
8531 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8532 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8533 (subreg:SI (match_dup 2) 4)])
8534 (label_ref (match_operand 0 "" ""))
8536 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8537 (plus:SI (match_dup 1)
8538 (subreg:SI (match_dup 2) 0)))
8539 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8540 (clobber (reg:CC CC_REGNUM))]
8541 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8543 if (which_alternative != 0)
8545 else if (get_attr_length (insn) == 6)
8546 return "brx%C5\t%1,%2,%l0";
8548 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8550 "&& reload_completed
8551 && (!REG_P (operands[3])
8552 || !rtx_equal_p (operands[1], operands[3]))"
8553 [(set (match_dup 4) (match_dup 1))
8554 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8555 (clobber (reg:CC CC_REGNUM))])
8556 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8557 (set (match_dup 3) (match_dup 4))
8558 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8559 (label_ref (match_dup 0))
8562 [(set_attr "op_type" "RSI")
8563 (set_attr "type" "branch")
8564 (set (attr "length")
8565 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8566 (const_int 6) (const_int 14)))])
8571 (define_expand "doloop_end"
8572 [(use (match_operand 0 "" "")) ; loop pseudo
8573 (use (match_operand 1 "" ""))] ; label
8576 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8577 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
8578 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8579 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
8580 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8581 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
8588 (define_insn_and_split "doloop_si64"
8591 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8593 (label_ref (match_operand 0 "" ""))
8595 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8596 (plus:SI (match_dup 1) (const_int -1)))
8597 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8598 (clobber (reg:CC CC_REGNUM))]
8601 if (which_alternative != 0)
8603 else if (get_attr_length (insn) == 4)
8604 return "brct\t%1,%l0";
8606 return "ahi\t%1,-1\;jgne\t%l0";
8608 "&& reload_completed
8609 && (! REG_P (operands[2])
8610 || ! rtx_equal_p (operands[1], operands[2]))"
8611 [(set (match_dup 3) (match_dup 1))
8612 (parallel [(set (reg:CCAN CC_REGNUM)
8613 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8615 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8616 (set (match_dup 2) (match_dup 3))
8617 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8618 (label_ref (match_dup 0))
8621 [(set_attr "op_type" "RI")
8622 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8623 ; hurt us in the (rare) case of ahi.
8624 (set_attr "z10prop" "z10_super_E1")
8625 (set_attr "type" "branch")
8626 (set (attr "length")
8627 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8628 (const_int 4) (const_int 10)))])
8630 (define_insn_and_split "doloop_si31"
8633 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8635 (label_ref (match_operand 0 "" ""))
8637 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8638 (plus:SI (match_dup 1) (const_int -1)))
8639 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8640 (clobber (reg:CC CC_REGNUM))]
8643 if (which_alternative != 0)
8645 else if (get_attr_length (insn) == 4)
8646 return "brct\t%1,%l0";
8650 "&& reload_completed
8651 && (! REG_P (operands[2])
8652 || ! rtx_equal_p (operands[1], operands[2]))"
8653 [(set (match_dup 3) (match_dup 1))
8654 (parallel [(set (reg:CCAN CC_REGNUM)
8655 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8657 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8658 (set (match_dup 2) (match_dup 3))
8659 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8660 (label_ref (match_dup 0))
8663 [(set_attr "op_type" "RI")
8664 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8665 ; hurt us in the (rare) case of ahi.
8666 (set_attr "z10prop" "z10_super_E1")
8667 (set_attr "type" "branch")
8668 (set (attr "length")
8669 (if_then_else (not (match_test "flag_pic"))
8670 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8671 (const_int 4) (const_int 6))
8672 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8673 (const_int 4) (const_int 8))))])
8675 (define_insn "*doloop_si_long"
8678 (ne (match_operand:SI 1 "register_operand" "d")
8680 (match_operand 0 "address_operand" "ZQZR")
8682 (set (match_operand:SI 2 "register_operand" "=1")
8683 (plus:SI (match_dup 1) (const_int -1)))
8684 (clobber (match_scratch:SI 3 "=X"))
8685 (clobber (reg:CC CC_REGNUM))]
8688 if (get_attr_op_type (insn) == OP_TYPE_RR)
8689 return "bctr\t%1,%0";
8691 return "bct\t%1,%a0";
8693 [(set (attr "op_type")
8694 (if_then_else (match_operand 0 "register_operand" "")
8695 (const_string "RR") (const_string "RX")))
8696 (set_attr "type" "branch")
8697 (set_attr "atype" "agen")
8698 (set_attr "z10prop" "z10_c")
8699 (set_attr "z196prop" "z196_cracked")])
8701 (define_insn_and_split "doloop_di"
8704 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8706 (label_ref (match_operand 0 "" ""))
8708 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8709 (plus:DI (match_dup 1) (const_int -1)))
8710 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8711 (clobber (reg:CC CC_REGNUM))]
8714 if (which_alternative != 0)
8716 else if (get_attr_length (insn) == 4)
8717 return "brctg\t%1,%l0";
8719 return "aghi\t%1,-1\;jgne\t%l0";
8721 "&& reload_completed
8722 && (! REG_P (operands[2])
8723 || ! rtx_equal_p (operands[1], operands[2]))"
8724 [(set (match_dup 3) (match_dup 1))
8725 (parallel [(set (reg:CCAN CC_REGNUM)
8726 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8728 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8729 (set (match_dup 2) (match_dup 3))
8730 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8731 (label_ref (match_dup 0))
8734 [(set_attr "op_type" "RI")
8735 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8736 ; hurt us in the (rare) case of ahi.
8737 (set_attr "z10prop" "z10_super_E1")
8738 (set_attr "type" "branch")
8739 (set (attr "length")
8740 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8741 (const_int 4) (const_int 10)))])
8744 ;;- Unconditional jump instructions.
8748 ; jump instruction pattern(s).
8751 (define_expand "jump"
8752 [(match_operand 0 "" "")]
8754 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8756 (define_insn "*jump64"
8757 [(set (pc) (label_ref (match_operand 0 "" "")))]
8760 if (get_attr_length (insn) == 4)
8765 [(set_attr "op_type" "RI")
8766 (set_attr "type" "branch")
8767 (set (attr "length")
8768 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8769 (const_int 4) (const_int 6)))])
8771 (define_insn "*jump31"
8772 [(set (pc) (label_ref (match_operand 0 "" "")))]
8775 gcc_assert (get_attr_length (insn) == 4);
8778 [(set_attr "op_type" "RI")
8779 (set_attr "type" "branch")
8780 (set (attr "length")
8781 (if_then_else (not (match_test "flag_pic"))
8782 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8783 (const_int 4) (const_int 6))
8784 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8785 (const_int 4) (const_int 8))))])
8788 ; indirect-jump instruction pattern(s).
8791 (define_insn "indirect_jump"
8792 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8795 if (get_attr_op_type (insn) == OP_TYPE_RR)
8800 [(set (attr "op_type")
8801 (if_then_else (match_operand 0 "register_operand" "")
8802 (const_string "RR") (const_string "RX")))
8803 (set_attr "type" "branch")
8804 (set_attr "atype" "agen")])
8807 ; casesi instruction pattern(s).
8810 (define_insn "casesi_jump"
8811 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8812 (use (label_ref (match_operand 1 "" "")))]
8815 if (get_attr_op_type (insn) == OP_TYPE_RR)
8820 [(set (attr "op_type")
8821 (if_then_else (match_operand 0 "register_operand" "")
8822 (const_string "RR") (const_string "RX")))
8823 (set_attr "type" "branch")
8824 (set_attr "atype" "agen")])
8826 (define_expand "casesi"
8827 [(match_operand:SI 0 "general_operand" "")
8828 (match_operand:SI 1 "general_operand" "")
8829 (match_operand:SI 2 "general_operand" "")
8830 (label_ref (match_operand 3 "" ""))
8831 (label_ref (match_operand 4 "" ""))]
8834 rtx index = gen_reg_rtx (SImode);
8835 rtx base = gen_reg_rtx (Pmode);
8836 rtx target = gen_reg_rtx (Pmode);
8838 emit_move_insn (index, operands[0]);
8839 emit_insn (gen_subsi3 (index, index, operands[1]));
8840 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8843 if (Pmode != SImode)
8844 index = convert_to_mode (Pmode, index, 1);
8845 if (GET_CODE (index) != REG)
8846 index = copy_to_mode_reg (Pmode, index);
8849 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8851 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8853 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8855 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8856 emit_move_insn (target, index);
8859 target = gen_rtx_PLUS (Pmode, base, target);
8860 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8867 ;;- Jump to subroutine.
8872 ; untyped call instruction pattern(s).
8875 ;; Call subroutine returning any type.
8876 (define_expand "untyped_call"
8877 [(parallel [(call (match_operand 0 "" "")
8879 (match_operand 1 "" "")
8880 (match_operand 2 "" "")])]
8885 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8887 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8889 rtx set = XVECEXP (operands[2], 0, i);
8890 emit_move_insn (SET_DEST (set), SET_SRC (set));
8893 /* The optimizer does not know that the call sets the function value
8894 registers we stored in the result block. We avoid problems by
8895 claiming that all hard registers are used and clobbered at this
8897 emit_insn (gen_blockage ());
8902 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8903 ;; all of memory. This blocks insns from being moved across this point.
8905 (define_insn "blockage"
8906 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8909 [(set_attr "type" "none")
8910 (set_attr "length" "0")])
8916 (define_expand "sibcall"
8917 [(call (match_operand 0 "" "")
8918 (match_operand 1 "" ""))]
8921 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8925 (define_insn "*sibcall_br"
8926 [(call (mem:QI (reg SIBCALL_REGNUM))
8927 (match_operand 0 "const_int_operand" "n"))]
8928 "SIBLING_CALL_P (insn)
8929 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8931 [(set_attr "op_type" "RR")
8932 (set_attr "type" "branch")
8933 (set_attr "atype" "agen")])
8935 (define_insn "*sibcall_brc"
8936 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8937 (match_operand 1 "const_int_operand" "n"))]
8938 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8940 [(set_attr "op_type" "RI")
8941 (set_attr "type" "branch")])
8943 (define_insn "*sibcall_brcl"
8944 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8945 (match_operand 1 "const_int_operand" "n"))]
8946 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8948 [(set_attr "op_type" "RIL")
8949 (set_attr "type" "branch")])
8952 ; sibcall_value patterns
8955 (define_expand "sibcall_value"
8956 [(set (match_operand 0 "" "")
8957 (call (match_operand 1 "" "")
8958 (match_operand 2 "" "")))]
8961 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8965 (define_insn "*sibcall_value_br"
8966 [(set (match_operand 0 "" "")
8967 (call (mem:QI (reg SIBCALL_REGNUM))
8968 (match_operand 1 "const_int_operand" "n")))]
8969 "SIBLING_CALL_P (insn)
8970 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8972 [(set_attr "op_type" "RR")
8973 (set_attr "type" "branch")
8974 (set_attr "atype" "agen")])
8976 (define_insn "*sibcall_value_brc"
8977 [(set (match_operand 0 "" "")
8978 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8979 (match_operand 2 "const_int_operand" "n")))]
8980 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8982 [(set_attr "op_type" "RI")
8983 (set_attr "type" "branch")])
8985 (define_insn "*sibcall_value_brcl"
8986 [(set (match_operand 0 "" "")
8987 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8988 (match_operand 2 "const_int_operand" "n")))]
8989 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8991 [(set_attr "op_type" "RIL")
8992 (set_attr "type" "branch")])
8996 ; call instruction pattern(s).
8999 (define_expand "call"
9000 [(call (match_operand 0 "" "")
9001 (match_operand 1 "" ""))
9002 (use (match_operand 2 "" ""))]
9005 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9006 gen_rtx_REG (Pmode, RETURN_REGNUM));
9010 (define_insn "*bras"
9011 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9012 (match_operand 1 "const_int_operand" "n"))
9013 (clobber (match_operand 2 "register_operand" "=r"))]
9014 "!SIBLING_CALL_P (insn)
9015 && TARGET_SMALL_EXEC
9016 && GET_MODE (operands[2]) == Pmode"
9018 [(set_attr "op_type" "RI")
9019 (set_attr "type" "jsr")
9020 (set_attr "z196prop" "z196_cracked")])
9022 (define_insn "*brasl"
9023 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9024 (match_operand 1 "const_int_operand" "n"))
9025 (clobber (match_operand 2 "register_operand" "=r"))]
9026 "!SIBLING_CALL_P (insn)
9028 && GET_MODE (operands[2]) == Pmode"
9030 [(set_attr "op_type" "RIL")
9031 (set_attr "type" "jsr")
9032 (set_attr "z196prop" "z196_cracked")])
9034 (define_insn "*basr"
9035 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
9036 (match_operand 1 "const_int_operand" "n"))
9037 (clobber (match_operand 2 "register_operand" "=r"))]
9038 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9040 if (get_attr_op_type (insn) == OP_TYPE_RR)
9041 return "basr\t%2,%0";
9043 return "bas\t%2,%a0";
9045 [(set (attr "op_type")
9046 (if_then_else (match_operand 0 "register_operand" "")
9047 (const_string "RR") (const_string "RX")))
9048 (set_attr "type" "jsr")
9049 (set_attr "atype" "agen")
9050 (set_attr "z196prop" "z196_cracked")])
9053 ; call_value instruction pattern(s).
9056 (define_expand "call_value"
9057 [(set (match_operand 0 "" "")
9058 (call (match_operand 1 "" "")
9059 (match_operand 2 "" "")))
9060 (use (match_operand 3 "" ""))]
9063 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9064 gen_rtx_REG (Pmode, RETURN_REGNUM));
9068 (define_insn "*bras_r"
9069 [(set (match_operand 0 "" "")
9070 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9071 (match_operand:SI 2 "const_int_operand" "n")))
9072 (clobber (match_operand 3 "register_operand" "=r"))]
9073 "!SIBLING_CALL_P (insn)
9074 && TARGET_SMALL_EXEC
9075 && GET_MODE (operands[3]) == Pmode"
9077 [(set_attr "op_type" "RI")
9078 (set_attr "type" "jsr")
9079 (set_attr "z196prop" "z196_cracked")])
9081 (define_insn "*brasl_r"
9082 [(set (match_operand 0 "" "")
9083 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9084 (match_operand 2 "const_int_operand" "n")))
9085 (clobber (match_operand 3 "register_operand" "=r"))]
9086 "!SIBLING_CALL_P (insn)
9088 && GET_MODE (operands[3]) == Pmode"
9090 [(set_attr "op_type" "RIL")
9091 (set_attr "type" "jsr")
9092 (set_attr "z196prop" "z196_cracked")])
9094 (define_insn "*basr_r"
9095 [(set (match_operand 0 "" "")
9096 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9097 (match_operand 2 "const_int_operand" "n")))
9098 (clobber (match_operand 3 "register_operand" "=r"))]
9099 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9101 if (get_attr_op_type (insn) == OP_TYPE_RR)
9102 return "basr\t%3,%1";
9104 return "bas\t%3,%a1";
9106 [(set (attr "op_type")
9107 (if_then_else (match_operand 1 "register_operand" "")
9108 (const_string "RR") (const_string "RX")))
9109 (set_attr "type" "jsr")
9110 (set_attr "atype" "agen")
9111 (set_attr "z196prop" "z196_cracked")])
9114 ;;- Thread-local storage support.
9117 (define_expand "get_thread_pointer<mode>"
9118 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9122 (define_expand "set_thread_pointer<mode>"
9123 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9124 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
9128 (define_insn "*set_tp"
9129 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
9132 [(set_attr "type" "none")
9133 (set_attr "length" "0")])
9135 (define_insn "*tls_load_64"
9136 [(set (match_operand:DI 0 "register_operand" "=d")
9137 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
9138 (match_operand:DI 2 "" "")]
9142 [(set_attr "op_type" "RXE")
9143 (set_attr "z10prop" "z10_fwd_A3")])
9145 (define_insn "*tls_load_31"
9146 [(set (match_operand:SI 0 "register_operand" "=d,d")
9147 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
9148 (match_operand:SI 2 "" "")]
9154 [(set_attr "op_type" "RX,RXY")
9155 (set_attr "type" "load")
9156 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
9158 (define_insn "*bras_tls"
9159 [(set (match_operand 0 "" "")
9160 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9161 (match_operand 2 "const_int_operand" "n")))
9162 (clobber (match_operand 3 "register_operand" "=r"))
9163 (use (match_operand 4 "" ""))]
9164 "!SIBLING_CALL_P (insn)
9165 && TARGET_SMALL_EXEC
9166 && GET_MODE (operands[3]) == Pmode"
9168 [(set_attr "op_type" "RI")
9169 (set_attr "type" "jsr")
9170 (set_attr "z196prop" "z196_cracked")])
9172 (define_insn "*brasl_tls"
9173 [(set (match_operand 0 "" "")
9174 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9175 (match_operand 2 "const_int_operand" "n")))
9176 (clobber (match_operand 3 "register_operand" "=r"))
9177 (use (match_operand 4 "" ""))]
9178 "!SIBLING_CALL_P (insn)
9180 && GET_MODE (operands[3]) == Pmode"
9182 [(set_attr "op_type" "RIL")
9183 (set_attr "type" "jsr")
9184 (set_attr "z196prop" "z196_cracked")])
9186 (define_insn "*basr_tls"
9187 [(set (match_operand 0 "" "")
9188 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
9189 (match_operand 2 "const_int_operand" "n")))
9190 (clobber (match_operand 3 "register_operand" "=r"))
9191 (use (match_operand 4 "" ""))]
9192 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9194 if (get_attr_op_type (insn) == OP_TYPE_RR)
9195 return "basr\t%3,%1%J4";
9197 return "bas\t%3,%a1%J4";
9199 [(set (attr "op_type")
9200 (if_then_else (match_operand 1 "register_operand" "")
9201 (const_string "RR") (const_string "RX")))
9202 (set_attr "type" "jsr")
9203 (set_attr "atype" "agen")
9204 (set_attr "z196prop" "z196_cracked")])
9207 ;;- Atomic operations
9211 ; memory barrier patterns.
9214 (define_expand "mem_signal_fence"
9215 [(match_operand:SI 0 "const_int_operand")] ;; model
9218 /* The s390 memory model is strong enough not to require any
9219 barrier in order to synchronize a thread with itself. */
9223 (define_expand "mem_thread_fence"
9224 [(match_operand:SI 0 "const_int_operand")] ;; model
9227 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
9228 enough not to require barriers of any kind. */
9229 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
9231 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
9232 MEM_VOLATILE_P (mem) = 1;
9233 emit_insn (gen_mem_thread_fence_1 (mem));
9238 ; Although bcr is superscalar on Z10, this variant will never
9239 ; become part of an execution group.
9240 ; With z196 we can make use of the fast-BCR-serialization facility.
9241 ; This allows for a slightly faster sync which is sufficient for our
9243 (define_insn "mem_thread_fence_1"
9244 [(set (match_operand:BLK 0 "" "")
9245 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
9253 [(set_attr "op_type" "RR")
9254 (set_attr "mnemonic" "bcr_flush")
9255 (set_attr "z196prop" "z196_alone")])
9258 ; atomic load/store operations
9261 ; Atomic loads need not examine the memory model at all.
9262 (define_expand "atomic_load<mode>"
9263 [(match_operand:DINT 0 "register_operand") ;; output
9264 (match_operand:DINT 1 "memory_operand") ;; memory
9265 (match_operand:SI 2 "const_int_operand")] ;; model
9268 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9271 if (<MODE>mode == TImode)
9272 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
9273 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9274 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
9276 emit_move_insn (operands[0], operands[1]);
9280 ; Different from movdi_31 in that we want no splitters.
9281 (define_insn "atomic_loaddi_1"
9282 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
9283 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
9291 [(set_attr "op_type" "RS,RSY,RS,RSY")
9292 (set_attr "type" "lm,lm,floaddf,floaddf")])
9294 (define_insn "atomic_loadti_1"
9295 [(set (match_operand:TI 0 "register_operand" "=r")
9296 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
9300 [(set_attr "op_type" "RXY")
9301 (set_attr "type" "other")])
9303 ; Atomic stores must(?) enforce sequential consistency.
9304 (define_expand "atomic_store<mode>"
9305 [(match_operand:DINT 0 "memory_operand") ;; memory
9306 (match_operand:DINT 1 "register_operand") ;; input
9307 (match_operand:SI 2 "const_int_operand")] ;; model
9310 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
9312 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
9315 if (<MODE>mode == TImode)
9316 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
9317 else if (<MODE>mode == DImode && !TARGET_ZARCH)
9318 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
9320 emit_move_insn (operands[0], operands[1]);
9321 if (model == MEMMODEL_SEQ_CST)
9322 emit_insn (gen_mem_thread_fence (operands[2]));
9326 ; Different from movdi_31 in that we want no splitters.
9327 (define_insn "atomic_storedi_1"
9328 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
9329 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
9337 [(set_attr "op_type" "RS,RSY,RS,RSY")
9338 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
9340 (define_insn "atomic_storeti_1"
9341 [(set (match_operand:TI 0 "memory_operand" "=RT")
9342 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
9346 [(set_attr "op_type" "RXY")
9347 (set_attr "type" "other")])
9350 ; compare and swap patterns.
9353 (define_expand "atomic_compare_and_swap<mode>"
9354 [(match_operand:SI 0 "register_operand") ;; bool success output
9355 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
9356 (match_operand:DGPR 2 "memory_operand") ;; memory
9357 (match_operand:DGPR 3 "register_operand") ;; expected intput
9358 (match_operand:DGPR 4 "register_operand") ;; newval intput
9359 (match_operand:SI 5 "const_int_operand") ;; is_weak
9360 (match_operand:SI 6 "const_int_operand") ;; success model
9361 (match_operand:SI 7 "const_int_operand")] ;; failure model
9364 rtx cc, cmp, output = operands[1];
9366 if (!register_operand (output, <MODE>mode))
9367 output = gen_reg_rtx (<MODE>mode);
9369 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
9372 emit_insn (gen_atomic_compare_and_swap<mode>_internal
9373 (output, operands[2], operands[3], operands[4]));
9375 /* We deliberately accept non-register operands in the predicate
9376 to ensure the write back to the output operand happens *before*
9377 the store-flags code below. This makes it easier for combine
9378 to merge the store-flags code with a potential test-and-branch
9379 pattern following (immediately!) afterwards. */
9380 if (output != operands[1])
9381 emit_move_insn (operands[1], output);
9383 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
9384 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
9385 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
9389 (define_expand "atomic_compare_and_swap<mode>"
9390 [(match_operand:SI 0 "register_operand") ;; bool success output
9391 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
9392 (match_operand:HQI 2 "memory_operand") ;; memory
9393 (match_operand:HQI 3 "general_operand") ;; expected intput
9394 (match_operand:HQI 4 "general_operand") ;; newval intput
9395 (match_operand:SI 5 "const_int_operand") ;; is_weak
9396 (match_operand:SI 6 "const_int_operand") ;; success model
9397 (match_operand:SI 7 "const_int_operand")] ;; failure model
9400 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
9401 operands[3], operands[4], INTVAL (operands[5]));
9405 (define_expand "atomic_compare_and_swap<mode>_internal"
9407 [(set (match_operand:DGPR 0 "register_operand")
9408 (match_operand:DGPR 1 "memory_operand"))
9410 (unspec_volatile:DGPR
9412 (match_operand:DGPR 2 "register_operand")
9413 (match_operand:DGPR 3 "register_operand")]
9415 (set (reg:CCZ1 CC_REGNUM)
9416 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
9420 (define_insn "*atomic_compare_and_swap<mode>_1"
9421 [(set (match_operand:TDI 0 "register_operand" "=r")
9422 (match_operand:TDI 1 "memory_operand" "+QS"))
9424 (unspec_volatile:TDI
9426 (match_operand:TDI 2 "register_operand" "0")
9427 (match_operand:TDI 3 "register_operand" "r")]
9429 (set (reg:CCZ1 CC_REGNUM)
9430 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9432 "c<td>sg\t%0,%3,%S1"
9433 [(set_attr "op_type" "RSY")
9434 (set_attr "type" "sem")])
9437 (define_insn "*atomic_compare_and_swapdi_2"
9438 [(set (match_operand:DI 0 "register_operand" "=r,r")
9439 (match_operand:DI 1 "memory_operand" "+Q,S"))
9443 (match_operand:DI 2 "register_operand" "0,0")
9444 (match_operand:DI 3 "register_operand" "r,r")]
9446 (set (reg:CCZ1 CC_REGNUM)
9447 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9452 [(set_attr "op_type" "RS,RSY")
9453 (set_attr "type" "sem")])
9456 (define_insn "*atomic_compare_and_swapsi_3"
9457 [(set (match_operand:SI 0 "register_operand" "=r,r")
9458 (match_operand:SI 1 "memory_operand" "+Q,S"))
9462 (match_operand:SI 2 "register_operand" "0,0")
9463 (match_operand:SI 3 "register_operand" "r,r")]
9465 (set (reg:CCZ1 CC_REGNUM)
9466 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9471 [(set_attr "op_type" "RS,RSY")
9472 (set_attr "type" "sem")])
9475 ; Other atomic instruction patterns.
9478 ; z196 load and add, xor, or and and instructions
9480 (define_expand "atomic_fetch_<atomic><mode>"
9481 [(match_operand:GPR 0 "register_operand") ;; val out
9483 (match_operand:GPR 1 "memory_operand") ;; memory
9484 (match_operand:GPR 2 "register_operand")) ;; val in
9485 (match_operand:SI 3 "const_int_operand")] ;; model
9488 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
9491 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9492 (operands[0], operands[1], operands[2]));
9496 ; lan, lang, lao, laog, lax, laxg, laa, laag
9497 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9498 [(set (match_operand:GPR 0 "register_operand" "=d")
9499 (match_operand:GPR 1 "memory_operand" "+QS"))
9501 (unspec_volatile:GPR
9502 [(ATOMIC_Z196:GPR (match_dup 1)
9503 (match_operand:GPR 2 "general_operand" "d"))]
9505 (clobber (reg:CC CC_REGNUM))]
9507 "la<noxa><g>\t%0,%2,%1"
9508 [(set_attr "op_type" "RSY")
9509 (set_attr "type" "sem")])
9511 ;; For SImode and larger, the optabs.c code will do just fine in
9512 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9513 ;; better by expanding our own loop.
9515 (define_expand "atomic_<atomic><mode>"
9517 (match_operand:HQI 0 "memory_operand") ;; memory
9518 (match_operand:HQI 1 "general_operand")) ;; val in
9519 (match_operand:SI 2 "const_int_operand")] ;; model
9522 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9523 operands[1], false);
9527 (define_expand "atomic_fetch_<atomic><mode>"
9528 [(match_operand:HQI 0 "register_operand") ;; val out
9530 (match_operand:HQI 1 "memory_operand") ;; memory
9531 (match_operand:HQI 2 "general_operand")) ;; val in
9532 (match_operand:SI 3 "const_int_operand")] ;; model
9535 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9536 operands[2], false);
9540 (define_expand "atomic_<atomic>_fetch<mode>"
9541 [(match_operand:HQI 0 "register_operand") ;; val out
9543 (match_operand:HQI 1 "memory_operand") ;; memory
9544 (match_operand:HQI 2 "general_operand")) ;; val in
9545 (match_operand:SI 3 "const_int_operand")] ;; model
9548 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9553 (define_expand "atomic_exchange<mode>"
9554 [(match_operand:HQI 0 "register_operand") ;; val out
9555 (match_operand:HQI 1 "memory_operand") ;; memory
9556 (match_operand:HQI 2 "general_operand") ;; val in
9557 (match_operand:SI 3 "const_int_operand")] ;; model
9560 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9561 operands[2], false);
9566 ;;- Miscellaneous instructions.
9570 ; allocate stack instruction pattern(s).
9573 (define_expand "allocate_stack"
9574 [(match_operand 0 "general_operand" "")
9575 (match_operand 1 "general_operand" "")]
9578 rtx temp = gen_reg_rtx (Pmode);
9580 emit_move_insn (temp, s390_back_chain_rtx ());
9581 anti_adjust_stack (operands[1]);
9582 emit_move_insn (s390_back_chain_rtx (), temp);
9584 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9590 ; setjmp instruction pattern.
9593 (define_expand "builtin_setjmp_receiver"
9594 [(match_operand 0 "" "")]
9597 emit_insn (s390_load_got ());
9598 emit_use (pic_offset_table_rtx);
9602 ;; These patterns say how to save and restore the stack pointer. We need not
9603 ;; save the stack pointer at function level since we are careful to
9604 ;; preserve the backchain. At block level, we have to restore the backchain
9605 ;; when we restore the stack pointer.
9607 ;; For nonlocal gotos, we must save both the stack pointer and its
9608 ;; backchain and restore both. Note that in the nonlocal case, the
9609 ;; save area is a memory location.
9611 (define_expand "save_stack_function"
9612 [(match_operand 0 "general_operand" "")
9613 (match_operand 1 "general_operand" "")]
9617 (define_expand "restore_stack_function"
9618 [(match_operand 0 "general_operand" "")
9619 (match_operand 1 "general_operand" "")]
9623 (define_expand "restore_stack_block"
9624 [(match_operand 0 "register_operand" "")
9625 (match_operand 1 "register_operand" "")]
9628 rtx temp = gen_reg_rtx (Pmode);
9630 emit_move_insn (temp, s390_back_chain_rtx ());
9631 emit_move_insn (operands[0], operands[1]);
9632 emit_move_insn (s390_back_chain_rtx (), temp);
9637 (define_expand "save_stack_nonlocal"
9638 [(match_operand 0 "memory_operand" "")
9639 (match_operand 1 "register_operand" "")]
9642 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9644 /* Copy the backchain to the first word, sp to the second and the
9645 literal pool base to the third. */
9647 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9648 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9649 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9651 if (TARGET_BACKCHAIN)
9652 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9654 emit_move_insn (save_sp, operands[1]);
9655 emit_move_insn (save_bp, base);
9660 (define_expand "restore_stack_nonlocal"
9661 [(match_operand 0 "register_operand" "")
9662 (match_operand 1 "memory_operand" "")]
9665 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9666 rtx temp = NULL_RTX;
9668 /* Restore the backchain from the first word, sp from the second and the
9669 literal pool base from the third. */
9671 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9672 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9673 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9675 if (TARGET_BACKCHAIN)
9676 temp = force_reg (Pmode, save_bc);
9678 emit_move_insn (base, save_bp);
9679 emit_move_insn (operands[0], save_sp);
9682 emit_move_insn (s390_back_chain_rtx (), temp);
9688 (define_expand "exception_receiver"
9692 s390_set_has_landing_pad_p (true);
9697 ; nop instruction pattern(s).
9704 [(set_attr "op_type" "RR")
9705 (set_attr "z10prop" "z10_fr_E1")])
9711 [(set_attr "op_type" "RR")])
9713 ;;- Undeletable nops (used for hotpatching)
9715 (define_insn "nop_2_byte"
9716 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
9719 [(set_attr "op_type" "RR")])
9721 (define_insn "nop_4_byte"
9722 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
9725 [(set_attr "op_type" "RX")])
9727 (define_insn "nop_6_byte"
9728 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
9731 [(set_attr "op_type" "RIL")])
9735 ; Special literal pool access instruction pattern(s).
9738 (define_insn "*pool_entry"
9739 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9740 UNSPECV_POOL_ENTRY)]
9743 machine_mode mode = GET_MODE (PATTERN (insn));
9744 unsigned int align = GET_MODE_BITSIZE (mode);
9745 s390_output_pool_entry (operands[0], mode, align);
9748 [(set (attr "length")
9749 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9751 (define_insn "pool_align"
9752 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9753 UNSPECV_POOL_ALIGN)]
9756 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9758 (define_insn "pool_section_start"
9759 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9762 [(set_attr "length" "0")])
9764 (define_insn "pool_section_end"
9765 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9768 [(set_attr "length" "0")])
9770 (define_insn "main_base_31_small"
9771 [(set (match_operand 0 "register_operand" "=a")
9772 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9773 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9775 [(set_attr "op_type" "RR")
9776 (set_attr "type" "la")
9777 (set_attr "z196prop" "z196_cracked")])
9779 (define_insn "main_base_31_large"
9780 [(set (match_operand 0 "register_operand" "=a")
9781 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9782 (set (pc) (label_ref (match_operand 2 "" "")))]
9783 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9785 [(set_attr "op_type" "RI")
9786 (set_attr "z196prop" "z196_cracked")])
9788 (define_insn "main_base_64"
9789 [(set (match_operand 0 "register_operand" "=a")
9790 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9791 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9793 [(set_attr "op_type" "RIL")
9794 (set_attr "type" "larl")
9795 (set_attr "z10prop" "z10_fwd_A1")])
9797 (define_insn "main_pool"
9798 [(set (match_operand 0 "register_operand" "=a")
9799 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9800 "GET_MODE (operands[0]) == Pmode"
9805 (if_then_else (match_test "TARGET_CPU_ZARCH")
9806 (const_string "larl") (const_string "la")))])
9808 (define_insn "reload_base_31"
9809 [(set (match_operand 0 "register_operand" "=a")
9810 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9811 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9812 "basr\t%0,0\;la\t%0,%1-.(%0)"
9813 [(set_attr "length" "6")
9814 (set_attr "type" "la")
9815 (set_attr "z196prop" "z196_cracked")])
9817 (define_insn "reload_base_64"
9818 [(set (match_operand 0 "register_operand" "=a")
9819 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9820 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9822 [(set_attr "op_type" "RIL")
9823 (set_attr "type" "larl")
9824 (set_attr "z10prop" "z10_fwd_A1")])
9827 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9832 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9835 ;; Insns related to generating the function prologue and epilogue.
9839 (define_expand "prologue"
9840 [(use (const_int 0))]
9842 "s390_emit_prologue (); DONE;")
9844 (define_expand "epilogue"
9845 [(use (const_int 1))]
9847 "s390_emit_epilogue (false); DONE;")
9849 (define_expand "sibcall_epilogue"
9850 [(use (const_int 0))]
9852 "s390_emit_epilogue (true); DONE;")
9854 ;; A direct return instruction, without using an epilogue.
9855 (define_insn "<code>"
9857 "s390_can_use_<code>_insn ()"
9859 [(set_attr "op_type" "RR")
9860 (set_attr "type" "jsr")
9861 (set_attr "atype" "agen")])
9863 (define_insn "*return"
9865 (use (match_operand 0 "register_operand" "a"))]
9866 "GET_MODE (operands[0]) == Pmode"
9868 [(set_attr "op_type" "RR")
9869 (set_attr "type" "jsr")
9870 (set_attr "atype" "agen")])
9873 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9874 ;; pointer. This is used for compatibility.
9876 (define_expand "ptr_extend"
9877 [(set (match_operand:DI 0 "register_operand" "=r")
9878 (match_operand:SI 1 "register_operand" "r"))]
9881 emit_insn (gen_anddi3 (operands[0],
9882 gen_lowpart (DImode, operands[1]),
9883 GEN_INT (0x7fffffff)));
9887 ;; Instruction definition to expand eh_return macro to support
9888 ;; swapping in special linkage return addresses.
9890 (define_expand "eh_return"
9891 [(use (match_operand 0 "register_operand" ""))]
9894 s390_emit_tpf_eh_return (operands[0]);
9899 ; Stack Protector Patterns
9902 (define_expand "stack_protect_set"
9903 [(set (match_operand 0 "memory_operand" "")
9904 (match_operand 1 "memory_operand" ""))]
9907 #ifdef TARGET_THREAD_SSP_OFFSET
9909 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9910 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9913 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9915 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9920 (define_insn "stack_protect_set<mode>"
9921 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9922 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9924 "mvc\t%O0(%G0,%R0),%S1"
9925 [(set_attr "op_type" "SS")])
9927 (define_expand "stack_protect_test"
9928 [(set (reg:CC CC_REGNUM)
9929 (compare (match_operand 0 "memory_operand" "")
9930 (match_operand 1 "memory_operand" "")))
9931 (match_operand 2 "" "")]
9935 #ifdef TARGET_THREAD_SSP_OFFSET
9937 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9938 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9941 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9943 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9945 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9946 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9947 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9951 (define_insn "stack_protect_test<mode>"
9952 [(set (reg:CCZ CC_REGNUM)
9953 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9954 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9956 "clc\t%O0(%G0,%R0),%S1"
9957 [(set_attr "op_type" "SS")])
9959 ; This is used in s390_emit_prologue in order to prevent insns
9960 ; adjusting the stack pointer to be moved over insns writing stack
9961 ; slots using a copy of the stack pointer in a different register.
9962 (define_insn "stack_tie"
9963 [(set (match_operand:BLK 0 "memory_operand" "+m")
9964 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9967 [(set_attr "length" "0")])
9971 ; Data prefetch patterns
9974 (define_insn "prefetch"
9975 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9976 (match_operand:SI 1 "const_int_operand" " n,n")
9977 (match_operand:SI 2 "const_int_operand" " n,n"))]
9980 switch (which_alternative)
9983 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9985 if (larl_operand (operands[0], Pmode))
9986 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9989 /* This might be reached for symbolic operands with an odd
9990 addend. We simply omit the prefetch for such rare cases. */
9995 [(set_attr "type" "load,larl")
9996 (set_attr "op_type" "RXY,RIL")
9997 (set_attr "z10prop" "z10_super")
9998 (set_attr "z196prop" "z196_alone")])
10002 ; Byte swap instructions
10005 (define_insn "bswap<mode>2"
10006 [(set (match_operand:GPR 0 "register_operand" "=d, d")
10007 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
10012 [(set_attr "type" "*,load")
10013 (set_attr "op_type" "RRE,RXY")
10014 (set_attr "z10prop" "z10_super")])
10018 ; Population count instruction
10021 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10022 ; portions and stores the result in the corresponding bytes in op0.
10023 (define_insn "*popcount<mode>"
10024 [(set (match_operand:INT 0 "register_operand" "=d")
10025 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10026 (clobber (reg:CC CC_REGNUM))]
10029 [(set_attr "op_type" "RRE")])
10031 (define_expand "popcountdi2"
10033 (parallel [(set (match_operand:DI 0 "register_operand" "")
10034 (unspec:DI [(match_operand:DI 1 "register_operand")]
10036 (clobber (reg:CC CC_REGNUM))])
10037 ; sllg op2, op0, 32
10038 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10040 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10041 (clobber (reg:CC CC_REGNUM))])
10042 ; sllg op2, op0, 16
10044 (ashift:DI (match_dup 0) (const_int 16)))
10046 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10047 (clobber (reg:CC CC_REGNUM))])
10049 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10051 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10052 (clobber (reg:CC CC_REGNUM))])
10053 ; srlg op0, op0, 56
10054 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10055 "TARGET_Z196 && TARGET_64BIT"
10056 "operands[2] = gen_reg_rtx (DImode);")
10058 (define_expand "popcountsi2"
10060 (parallel [(set (match_operand:SI 0 "register_operand" "")
10061 (unspec:SI [(match_operand:SI 1 "register_operand")]
10063 (clobber (reg:CC CC_REGNUM))])
10064 ; sllk op2, op0, 16
10066 (ashift:SI (match_dup 0) (const_int 16)))
10068 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10069 (clobber (reg:CC CC_REGNUM))])
10071 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10073 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10074 (clobber (reg:CC CC_REGNUM))])
10076 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10078 "operands[2] = gen_reg_rtx (SImode);")
10080 (define_expand "popcounthi2"
10082 (parallel [(set (match_operand:HI 0 "register_operand" "")
10083 (unspec:HI [(match_operand:HI 1 "register_operand")]
10085 (clobber (reg:CC CC_REGNUM))])
10088 (ashift:SI (match_dup 0) (const_int 8)))
10090 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10091 (clobber (reg:CC CC_REGNUM))])
10093 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10095 "operands[2] = gen_reg_rtx (SImode);")
10097 (define_expand "popcountqi2"
10099 (parallel [(set (match_operand:QI 0 "register_operand" "")
10100 (unspec:QI [(match_operand:QI 1 "register_operand")]
10102 (clobber (reg:CC CC_REGNUM))])]
10107 ;;- Copy sign instructions
10110 (define_insn "copysign<mode>3"
10111 [(set (match_operand:FP 0 "register_operand" "=f")
10112 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
10113 (match_operand:FP 2 "register_operand" "f")]
10117 [(set_attr "op_type" "RRF")
10118 (set_attr "type" "fsimp<mode>")])
10122 ;;- Transactional execution instructions
10125 ; This splitter helps combine to make use of CC directly when
10126 ; comparing the integer result of a tbegin builtin with a constant.
10127 ; The unspec is already removed by canonicalize_comparison. So this
10128 ; splitters only job is to turn the PARALLEL into separate insns
10129 ; again. Unfortunately this only works with the very first cc/int
10130 ; compare since combine is not able to deal with data flow across
10131 ; basic block boundaries.
10133 ; It needs to be an insn pattern as well since combine does not apply
10134 ; the splitter directly. Combine would only use it if it actually
10135 ; would reduce the number of instructions.
10136 (define_insn_and_split "*ccraw_to_int"
10139 (match_operator 0 "s390_eqne_operator"
10140 [(reg:CCRAW CC_REGNUM)
10141 (match_operand 1 "const_int_operand" "")])
10142 (label_ref (match_operand 2 "" ""))
10144 (set (match_operand:SI 3 "register_operand" "=d")
10145 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10149 [(set (match_dup 3)
10150 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
10152 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
10153 (label_ref (match_dup 2))
10157 ; Non-constrained transaction begin
10159 (define_expand "tbegin"
10160 [(match_operand:SI 0 "register_operand" "")
10161 (match_operand:BLK 1 "memory_operand" "")]
10164 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
10168 (define_expand "tbegin_nofloat"
10169 [(match_operand:SI 0 "register_operand" "")
10170 (match_operand:BLK 1 "memory_operand" "")]
10173 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
10177 (define_expand "tbegin_retry"
10178 [(match_operand:SI 0 "register_operand" "")
10179 (match_operand:BLK 1 "memory_operand" "")
10180 (match_operand:SI 2 "general_operand" "")]
10183 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
10187 (define_expand "tbegin_retry_nofloat"
10188 [(match_operand:SI 0 "register_operand" "")
10189 (match_operand:BLK 1 "memory_operand" "")
10190 (match_operand:SI 2 "general_operand" "")]
10193 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
10197 (define_insn "tbegin_1"
10198 [(set (reg:CCRAW CC_REGNUM)
10199 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10201 (set (match_operand:BLK 1 "memory_operand" "=Q")
10202 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
10203 (clobber (reg:DF 16))
10204 (clobber (reg:DF 17))
10205 (clobber (reg:DF 18))
10206 (clobber (reg:DF 19))
10207 (clobber (reg:DF 20))
10208 (clobber (reg:DF 21))
10209 (clobber (reg:DF 22))
10210 (clobber (reg:DF 23))
10211 (clobber (reg:DF 24))
10212 (clobber (reg:DF 25))
10213 (clobber (reg:DF 26))
10214 (clobber (reg:DF 27))
10215 (clobber (reg:DF 28))
10216 (clobber (reg:DF 29))
10217 (clobber (reg:DF 30))
10218 (clobber (reg:DF 31))]
10219 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
10220 ; not supposed to be used for immediates (see genpreds.c).
10221 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10223 [(set_attr "op_type" "SIL")])
10225 ; Same as above but without the FPR clobbers
10226 (define_insn "tbegin_nofloat_1"
10227 [(set (reg:CCRAW CC_REGNUM)
10228 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
10230 (set (match_operand:BLK 1 "memory_operand" "=Q")
10231 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
10232 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10234 [(set_attr "op_type" "SIL")])
10237 ; Constrained transaction begin
10239 (define_expand "tbeginc"
10240 [(set (reg:CCRAW CC_REGNUM)
10241 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
10246 (define_insn "*tbeginc_1"
10247 [(set (reg:CCRAW CC_REGNUM)
10248 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
10250 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
10252 [(set_attr "op_type" "SIL")])
10256 (define_expand "tend"
10257 [(set (reg:CCRAW CC_REGNUM)
10258 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
10259 (set (match_operand:SI 0 "register_operand" "")
10260 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
10264 (define_insn "*tend_1"
10265 [(set (reg:CCRAW CC_REGNUM)
10266 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
10269 [(set_attr "op_type" "S")])
10271 ; Transaction abort
10273 (define_expand "tabort"
10274 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
10276 "TARGET_HTM && operands != NULL"
10278 if (CONST_INT_P (operands[0])
10279 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
10281 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
10282 ". Values in range 0 through 255 are reserved.",
10283 INTVAL (operands[0]));
10288 (define_insn "*tabort_1"
10289 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
10291 "TARGET_HTM && operands != NULL"
10293 [(set_attr "op_type" "S")])
10295 ; Transaction extract nesting depth
10297 (define_insn "etnd"
10298 [(set (match_operand:SI 0 "register_operand" "=d")
10299 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
10302 [(set_attr "op_type" "RRE")])
10304 ; Non-transactional store
10306 (define_insn "ntstg"
10307 [(set (match_operand:DI 0 "memory_operand" "=RT")
10308 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
10312 [(set_attr "op_type" "RXY")])
10314 ; Transaction perform processor assist
10316 (define_expand "tx_assist"
10317 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
10318 (reg:SI GPR0_REGNUM)
10324 (define_insn "*ppa"
10325 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
10326 (match_operand:SI 1 "register_operand" "d")
10327 (match_operand 2 "const_int_operand" "I")]
10329 "TARGET_HTM && INTVAL (operands[2]) < 16"
10331 [(set_attr "op_type" "RRF")])
10334 ; Set and get floating point control register
10336 (define_insn "s390_sfpc"
10337 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
10339 "TARGET_HARD_FLOAT"
10342 (define_insn "s390_efpc"
10343 [(set (match_operand:SI 0 "register_operand" "=d")
10344 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
10345 "TARGET_HARD_FLOAT"