1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "insn-config.h"
37 #include "hard-reg-set.h"
39 #include "insn-attr.h"
40 #include "diagnostic-core.h"
42 #include "integrate.h"
46 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
57 #include "alloc-pool.h"
58 #include "tm-constrs.h"
62 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
64 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
65 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
67 /* These are some macros to abstract register modes. */
68 #define CONST_OK_FOR_ADD(size) \
69 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
70 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
71 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
72 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
74 /* Used to simplify the logic below. Find the attributes wherever
76 #define SH_ATTRIBUTES(decl) \
77 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
78 : DECL_ATTRIBUTES (decl) \
79 ? (DECL_ATTRIBUTES (decl)) \
80 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
82 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
83 int current_function_interrupt
;
85 tree sh_deferred_function_attributes
;
86 tree
*sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
88 /* Global variables for machine-dependent things. */
90 /* Which cpu are we scheduling for. */
91 enum processor_type sh_cpu
;
93 /* Definitions used in ready queue reordering for first scheduling pass. */
95 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
96 static short *regmode_weight
[2];
98 /* Total SFmode and SImode weights of scheduled insns. */
99 static int curr_regmode_pressure
[2];
101 /* Number of r0 life regions. */
102 static int r0_life_regions
;
104 /* If true, skip cycles for Q -> R movement. */
105 static int skip_cycles
= 0;
107 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
108 and returned from sh_reorder2. */
109 static short cached_can_issue_more
;
111 /* Unique number for UNSPEC_BBR pattern. */
112 static unsigned int unspec_bbr_uid
= 1;
114 /* Provides the class number of the smallest class containing
117 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
119 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
120 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
121 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
122 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
123 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
124 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
125 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
126 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
127 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
128 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
129 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
130 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
131 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
132 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
133 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
134 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
135 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
136 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
137 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
138 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
139 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
140 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
141 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
142 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
143 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
144 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
145 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
146 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
147 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
148 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
149 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
150 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
151 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
152 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
153 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
154 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
155 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
156 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
157 GENERAL_REGS
, GENERAL_REGS
,
160 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
161 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
163 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
167 int assembler_dialect
;
169 static bool shmedia_space_reserved_for_target_registers
;
171 static void split_branches (rtx
);
172 static int branch_dest (rtx
);
173 static void force_into (rtx
, rtx
);
174 static void print_slot (rtx
);
175 static rtx
add_constant (rtx
, enum machine_mode
, rtx
);
176 static void dump_table (rtx
, rtx
);
177 static int hi_const (rtx
);
178 static bool broken_move (rtx
);
179 static bool mova_p (rtx
);
180 static rtx
find_barrier (int, rtx
, rtx
);
181 static bool noncall_uses_reg (rtx
, rtx
, rtx
*);
182 static rtx
gen_block_redirect (rtx
, int, int);
183 static void sh_reorg (void);
184 static void sh_option_override (void);
185 static void output_stack_adjust (int, rtx
, int, HARD_REG_SET
*, bool);
186 static rtx
frame_insn (rtx
);
187 static rtx
push (int);
188 static void pop (int);
189 static void push_regs (HARD_REG_SET
*, int);
190 static int calc_live_regs (HARD_REG_SET
*);
191 static HOST_WIDE_INT
rounded_frame_size (int);
192 static bool sh_frame_pointer_required (void);
193 static rtx
mark_constant_pool_use (rtx
);
194 static tree
sh_handle_interrupt_handler_attribute (tree
*, tree
, tree
, int, bool *);
195 static tree
sh_handle_resbank_handler_attribute (tree
*, tree
,
197 static tree
sh2a_handle_function_vector_handler_attribute (tree
*, tree
,
199 static tree
sh_handle_sp_switch_attribute (tree
*, tree
, tree
, int, bool *);
200 static tree
sh_handle_trap_exit_attribute (tree
*, tree
, tree
, int, bool *);
201 static tree
sh_handle_renesas_attribute (tree
*, tree
, tree
, int, bool *);
202 static void sh_print_operand (FILE *, rtx
, int);
203 static void sh_print_operand_address (FILE *, rtx
);
204 static bool sh_print_operand_punct_valid_p (unsigned char code
);
205 static bool sh_asm_output_addr_const_extra (FILE *file
, rtx x
);
206 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT
);
207 static void sh_insert_attributes (tree
, tree
*);
208 static const char *sh_check_pch_target_flags (int);
209 static int sh_register_move_cost (enum machine_mode
, reg_class_t
, reg_class_t
);
210 static int sh_adjust_cost (rtx
, rtx
, rtx
, int);
211 static int sh_issue_rate (void);
212 static int sh_dfa_new_cycle (FILE *, int, rtx
, int, int, int *sort_p
);
213 static short find_set_regmode_weight (rtx
, enum machine_mode
);
214 static short find_insn_regmode_weight (rtx
, enum machine_mode
);
215 static void find_regmode_weight (basic_block
, enum machine_mode
);
216 static int find_r0_life_regions (basic_block
);
217 static void sh_md_init_global (FILE *, int, int);
218 static void sh_md_finish_global (FILE *, int);
219 static int rank_for_reorder (const void *, const void *);
220 static void swap_reorder (rtx
*, int);
221 static void ready_reorder (rtx
*, int);
222 static bool high_pressure (enum machine_mode
);
223 static int sh_reorder (FILE *, int, rtx
*, int *, int);
224 static int sh_reorder2 (FILE *, int, rtx
*, int *, int);
225 static void sh_md_init (FILE *, int, int);
226 static int sh_variable_issue (FILE *, int, rtx
, int);
228 static bool sh_function_ok_for_sibcall (tree
, tree
);
230 static bool sh_cannot_modify_jumps_p (void);
231 static reg_class_t
sh_target_reg_class (void);
232 static bool sh_optimize_target_register_callee_saved (bool);
233 static bool sh_ms_bitfield_layout_p (const_tree
);
235 static void sh_init_builtins (void);
236 static tree
sh_builtin_decl (unsigned, bool);
237 static void sh_media_init_builtins (void);
238 static tree
sh_media_builtin_decl (unsigned, bool);
239 static rtx
sh_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
240 static void sh_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
241 static void sh_file_start (void);
242 static bool flow_dependent_p (rtx
, rtx
);
243 static void flow_dependent_p_1 (rtx
, const_rtx
, void *);
244 static int shiftcosts (rtx
);
245 static int and_xor_ior_costs (rtx
, int);
246 static int addsubcosts (rtx
);
247 static int multcosts (rtx
);
248 static bool unspec_caller_rtx_p (rtx
);
249 static bool sh_cannot_copy_insn_p (rtx
);
250 static bool sh_rtx_costs (rtx
, int, int, int, int *, bool);
251 static int sh_address_cost (rtx
, bool);
252 static int sh_pr_n_sets (void);
253 static rtx
sh_allocate_initial_value (rtx
);
254 static reg_class_t
sh_preferred_reload_class (rtx
, reg_class_t
);
255 static reg_class_t
sh_secondary_reload (bool, rtx
, reg_class_t
,
257 struct secondary_reload_info
*);
258 static bool sh_legitimate_address_p (enum machine_mode
, rtx
, bool);
259 static rtx
sh_legitimize_address (rtx
, rtx
, enum machine_mode
);
260 static rtx
sh_delegitimize_address (rtx
);
261 static int shmedia_target_regs_stack_space (HARD_REG_SET
*);
262 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET
*);
263 static int shmedia_target_regs_stack_adjust (HARD_REG_SET
*);
264 static int scavenge_reg (HARD_REG_SET
*s
);
265 struct save_schedule_s
;
266 static struct save_entry_s
*sh5_schedule_saves (HARD_REG_SET
*,
267 struct save_schedule_s
*, int);
269 static rtx
sh_struct_value_rtx (tree
, int);
270 static rtx
sh_function_value (const_tree
, const_tree
, bool);
271 static bool sh_function_value_regno_p (const unsigned int);
272 static rtx
sh_libcall_value (enum machine_mode
, const_rtx
);
273 static bool sh_return_in_memory (const_tree
, const_tree
);
274 static rtx
sh_builtin_saveregs (void);
275 static void sh_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
, tree
, int *, int);
276 static bool sh_strict_argument_naming (cumulative_args_t
);
277 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t
);
278 static tree
sh_build_builtin_va_list (void);
279 static void sh_va_start (tree
, rtx
);
280 static tree
sh_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
281 static bool sh_promote_prototypes (const_tree
);
282 static enum machine_mode
sh_promote_function_mode (const_tree type
,
287 static bool sh_pass_by_reference (cumulative_args_t
, enum machine_mode
,
289 static bool sh_callee_copies (cumulative_args_t
, enum machine_mode
,
291 static int sh_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
293 static void sh_function_arg_advance (cumulative_args_t
, enum machine_mode
,
295 static rtx
sh_function_arg (cumulative_args_t
, enum machine_mode
,
297 static bool sh_scalar_mode_supported_p (enum machine_mode
);
298 static int sh_dwarf_calling_convention (const_tree
);
299 static void sh_encode_section_info (tree
, rtx
, int);
300 static bool sh2a_function_vector_p (tree
);
301 static void sh_trampoline_init (rtx
, tree
, rtx
);
302 static rtx
sh_trampoline_adjust_address (rtx
);
303 static void sh_conditional_register_usage (void);
304 static bool sh_legitimate_constant_p (enum machine_mode
, rtx
);
305 static int mov_insn_size (enum machine_mode
, bool);
306 static int max_mov_insn_displacement (enum machine_mode
, bool);
307 static int mov_insn_alignment_mask (enum machine_mode
, bool);
309 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
311 static const struct attribute_spec sh_attribute_table
[] =
313 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
314 affects_type_identity } */
315 { "interrupt_handler", 0, 0, true, false, false,
316 sh_handle_interrupt_handler_attribute
, false },
317 { "sp_switch", 1, 1, true, false, false,
318 sh_handle_sp_switch_attribute
, false },
319 { "trap_exit", 1, 1, true, false, false,
320 sh_handle_trap_exit_attribute
, false },
321 { "renesas", 0, 0, false, true, false,
322 sh_handle_renesas_attribute
, false },
323 { "trapa_handler", 0, 0, true, false, false,
324 sh_handle_interrupt_handler_attribute
, false },
325 { "nosave_low_regs", 0, 0, true, false, false,
326 sh_handle_interrupt_handler_attribute
, false },
327 { "resbank", 0, 0, true, false, false,
328 sh_handle_resbank_handler_attribute
, false },
329 { "function_vector", 1, 1, true, false, false,
330 sh2a_handle_function_vector_handler_attribute
, false },
331 { NULL
, 0, 0, false, false, false, NULL
, false }
334 /* Initialize the GCC target structure. */
335 #undef TARGET_ATTRIBUTE_TABLE
336 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
338 /* The next two are used for debug info when compiling with -gdwarf. */
339 #undef TARGET_ASM_UNALIGNED_HI_OP
340 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
341 #undef TARGET_ASM_UNALIGNED_SI_OP
342 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
344 /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
345 #undef TARGET_ASM_UNALIGNED_DI_OP
346 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
347 #undef TARGET_ASM_ALIGNED_DI_OP
348 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
350 #undef TARGET_OPTION_OVERRIDE
351 #define TARGET_OPTION_OVERRIDE sh_option_override
353 #undef TARGET_PRINT_OPERAND
354 #define TARGET_PRINT_OPERAND sh_print_operand
355 #undef TARGET_PRINT_OPERAND_ADDRESS
356 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
357 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
358 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
359 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
360 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
362 #undef TARGET_ASM_FUNCTION_EPILOGUE
363 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
365 #undef TARGET_ASM_OUTPUT_MI_THUNK
366 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
368 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
369 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
371 #undef TARGET_ASM_FILE_START
372 #define TARGET_ASM_FILE_START sh_file_start
373 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
374 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
376 #undef TARGET_REGISTER_MOVE_COST
377 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
379 #undef TARGET_INSERT_ATTRIBUTES
380 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
382 #undef TARGET_SCHED_ADJUST_COST
383 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
385 #undef TARGET_SCHED_ISSUE_RATE
386 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
388 /* The next 5 hooks have been implemented for reenabling sched1. With the
389 help of these macros we are limiting the movement of insns in sched1 to
390 reduce the register pressure. The overall idea is to keep count of SImode
391 and SFmode regs required by already scheduled insns. When these counts
392 cross some threshold values; give priority to insns that free registers.
393 The insn that frees registers is most likely to be the insn with lowest
394 LUID (original insn order); but such an insn might be there in the stalled
395 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
396 upto a max of 8 cycles so that such insns may move from Q -> R.
398 The description of the hooks are as below:
400 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
401 scheduler; it is called inside the sched_init function just after
402 find_insn_reg_weights function call. It is used to calculate the SImode
403 and SFmode weights of insns of basic blocks; much similar to what
404 find_insn_reg_weights does.
405 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
407 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
408 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
411 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
412 high; reorder the ready queue so that the insn with lowest LUID will be
415 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
416 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
418 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
419 can be returned from TARGET_SCHED_REORDER2.
421 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
423 #undef TARGET_SCHED_DFA_NEW_CYCLE
424 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
426 #undef TARGET_SCHED_INIT_GLOBAL
427 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
429 #undef TARGET_SCHED_FINISH_GLOBAL
430 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
432 #undef TARGET_SCHED_VARIABLE_ISSUE
433 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
435 #undef TARGET_SCHED_REORDER
436 #define TARGET_SCHED_REORDER sh_reorder
438 #undef TARGET_SCHED_REORDER2
439 #define TARGET_SCHED_REORDER2 sh_reorder2
441 #undef TARGET_SCHED_INIT
442 #define TARGET_SCHED_INIT sh_md_init
444 #undef TARGET_DELEGITIMIZE_ADDRESS
445 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
447 #undef TARGET_LEGITIMIZE_ADDRESS
448 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
450 #undef TARGET_CANNOT_MODIFY_JUMPS_P
451 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
452 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
453 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
454 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
455 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
456 sh_optimize_target_register_callee_saved
458 #undef TARGET_MS_BITFIELD_LAYOUT_P
459 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
461 #undef TARGET_INIT_BUILTINS
462 #define TARGET_INIT_BUILTINS sh_init_builtins
463 #undef TARGET_BUILTIN_DECL
464 #define TARGET_BUILTIN_DECL sh_builtin_decl
465 #undef TARGET_EXPAND_BUILTIN
466 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
468 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
469 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
471 #undef TARGET_CANNOT_COPY_INSN_P
472 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
473 #undef TARGET_RTX_COSTS
474 #define TARGET_RTX_COSTS sh_rtx_costs
475 #undef TARGET_ADDRESS_COST
476 #define TARGET_ADDRESS_COST sh_address_cost
477 #undef TARGET_ALLOCATE_INITIAL_VALUE
478 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
480 #undef TARGET_MACHINE_DEPENDENT_REORG
481 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
483 #undef TARGET_DWARF_REGISTER_SPAN
484 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
487 #undef TARGET_HAVE_TLS
488 #define TARGET_HAVE_TLS true
491 #undef TARGET_PROMOTE_PROTOTYPES
492 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
493 #undef TARGET_PROMOTE_FUNCTION_MODE
494 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
496 #undef TARGET_FUNCTION_VALUE
497 #define TARGET_FUNCTION_VALUE sh_function_value
498 #undef TARGET_FUNCTION_VALUE_REGNO_P
499 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
500 #undef TARGET_LIBCALL_VALUE
501 #define TARGET_LIBCALL_VALUE sh_libcall_value
502 #undef TARGET_STRUCT_VALUE_RTX
503 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
504 #undef TARGET_RETURN_IN_MEMORY
505 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
507 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
508 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
509 #undef TARGET_SETUP_INCOMING_VARARGS
510 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
511 #undef TARGET_STRICT_ARGUMENT_NAMING
512 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
513 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
514 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
515 #undef TARGET_MUST_PASS_IN_STACK
516 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
517 #undef TARGET_PASS_BY_REFERENCE
518 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
519 #undef TARGET_CALLEE_COPIES
520 #define TARGET_CALLEE_COPIES sh_callee_copies
521 #undef TARGET_ARG_PARTIAL_BYTES
522 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
523 #undef TARGET_FUNCTION_ARG
524 #define TARGET_FUNCTION_ARG sh_function_arg
525 #undef TARGET_FUNCTION_ARG_ADVANCE
526 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
528 #undef TARGET_BUILD_BUILTIN_VA_LIST
529 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
530 #undef TARGET_EXPAND_BUILTIN_VA_START
531 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
532 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
533 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
535 #undef TARGET_SCALAR_MODE_SUPPORTED_P
536 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
537 #undef TARGET_VECTOR_MODE_SUPPORTED_P
538 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
540 #undef TARGET_CHECK_PCH_TARGET_FLAGS
541 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
543 #undef TARGET_DWARF_CALLING_CONVENTION
544 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
546 #undef TARGET_FRAME_POINTER_REQUIRED
547 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
549 /* Return regmode weight for insn. */
550 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
552 /* Return current register pressure for regmode. */
553 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
555 #undef TARGET_ENCODE_SECTION_INFO
556 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
558 #undef TARGET_SECONDARY_RELOAD
559 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
561 #undef TARGET_PREFERRED_RELOAD_CLASS
562 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
564 #undef TARGET_CONDITIONAL_REGISTER_USAGE
565 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
567 #undef TARGET_LEGITIMATE_ADDRESS_P
568 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
570 #undef TARGET_TRAMPOLINE_INIT
571 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
572 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
573 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
575 #undef TARGET_LEGITIMATE_CONSTANT_P
576 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
578 /* Machine-specific symbol_ref flags. */
579 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
581 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
582 is used by optabs.c atomic op expansion code as well as in sync.md. */
583 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
584 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
586 struct gcc_target targetm
= TARGET_INITIALIZER
;
588 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
589 various options, and do some machine dependent initialization. */
591 sh_option_override (void)
595 SUBTARGET_OVERRIDE_OPTIONS
;
596 if (optimize
> 1 && !optimize_size
)
597 target_flags
|= MASK_SAVE_ALL_TARGET_REGS
;
598 if (flag_finite_math_only
== 2)
599 flag_finite_math_only
600 = !flag_signaling_nans
&& TARGET_SH2E
&& ! TARGET_IEEE
;
601 if (TARGET_SH2E
&& !flag_finite_math_only
)
602 target_flags
|= MASK_IEEE
;
603 sh_cpu
= PROCESSOR_SH1
;
604 assembler_dialect
= 0;
606 sh_cpu
= PROCESSOR_SH2
;
608 sh_cpu
= PROCESSOR_SH2E
;
610 sh_cpu
= PROCESSOR_SH2A
;
612 sh_cpu
= PROCESSOR_SH3
;
614 sh_cpu
= PROCESSOR_SH3E
;
617 assembler_dialect
= 1;
618 sh_cpu
= PROCESSOR_SH4
;
620 if (TARGET_SH4A_ARCH
)
622 assembler_dialect
= 1;
623 sh_cpu
= PROCESSOR_SH4A
;
627 sh_cpu
= PROCESSOR_SH5
;
628 target_flags
|= MASK_ALIGN_DOUBLE
;
629 if (TARGET_SHMEDIA_FPU
)
630 target_flags
|= MASK_FMOVD
;
633 /* There are no delay slots on SHmedia. */
634 flag_delayed_branch
= 0;
635 /* Relaxation isn't yet supported for SHmedia */
636 target_flags
&= ~MASK_RELAX
;
637 /* After reload, if conversion does little good but can cause
639 - find_if_block doesn't do anything for SH because we don't
640 have conditional execution patterns. (We use conditional
641 move patterns, which are handled differently, and only
643 - find_cond_trap doesn't do anything for the SH because we
644 don't have conditional traps.
645 - find_if_case_1 uses redirect_edge_and_branch_force in
646 the only path that does an optimization, and this causes
647 an ICE when branch targets are in registers.
648 - find_if_case_2 doesn't do anything for the SHmedia after
649 reload except when it can redirect a tablejump - and
650 that's rather rare. */
651 flag_if_conversion2
= 0;
652 if (! strcmp (sh_div_str
, "call"))
653 sh_div_strategy
= SH_DIV_CALL
;
654 else if (! strcmp (sh_div_str
, "call2"))
655 sh_div_strategy
= SH_DIV_CALL2
;
656 if (! strcmp (sh_div_str
, "fp") && TARGET_FPU_ANY
)
657 sh_div_strategy
= SH_DIV_FP
;
658 else if (! strcmp (sh_div_str
, "inv"))
659 sh_div_strategy
= SH_DIV_INV
;
660 else if (! strcmp (sh_div_str
, "inv:minlat"))
661 sh_div_strategy
= SH_DIV_INV_MINLAT
;
662 else if (! strcmp (sh_div_str
, "inv20u"))
663 sh_div_strategy
= SH_DIV_INV20U
;
664 else if (! strcmp (sh_div_str
, "inv20l"))
665 sh_div_strategy
= SH_DIV_INV20L
;
666 else if (! strcmp (sh_div_str
, "inv:call2"))
667 sh_div_strategy
= SH_DIV_INV_CALL2
;
668 else if (! strcmp (sh_div_str
, "inv:call"))
669 sh_div_strategy
= SH_DIV_INV_CALL
;
670 else if (! strcmp (sh_div_str
, "inv:fp"))
673 sh_div_strategy
= SH_DIV_INV_FP
;
675 sh_div_strategy
= SH_DIV_INV
;
677 TARGET_CBRANCHDI4
= 0;
678 /* Assembler CFI isn't yet fully supported for SHmedia. */
679 flag_dwarf2_cfi_asm
= 0;
684 /* Only the sh64-elf assembler fully supports .quad properly. */
685 targetm
.asm_out
.aligned_op
.di
= NULL
;
686 targetm
.asm_out
.unaligned_op
.di
= NULL
;
690 if (! strcmp (sh_div_str
, "call-div1"))
691 sh_div_strategy
= SH_DIV_CALL_DIV1
;
692 else if (! strcmp (sh_div_str
, "call-fp")
693 && (TARGET_FPU_DOUBLE
694 || (TARGET_HARD_SH4
&& TARGET_SH2E
)
695 || (TARGET_SHCOMPACT
&& TARGET_FPU_ANY
)))
696 sh_div_strategy
= SH_DIV_CALL_FP
;
697 else if (! strcmp (sh_div_str
, "call-table") && TARGET_SH2
)
698 sh_div_strategy
= SH_DIV_CALL_TABLE
;
700 /* Pick one that makes most sense for the target in general.
701 It is not much good to use different functions depending
702 on -Os, since then we'll end up with two different functions
703 when some of the code is compiled for size, and some for
706 /* SH4 tends to emphasize speed. */
708 sh_div_strategy
= SH_DIV_CALL_TABLE
;
709 /* These have their own way of doing things. */
710 else if (TARGET_SH2A
)
711 sh_div_strategy
= SH_DIV_INTRINSIC
;
712 /* ??? Should we use the integer SHmedia function instead? */
713 else if (TARGET_SHCOMPACT
&& TARGET_FPU_ANY
)
714 sh_div_strategy
= SH_DIV_CALL_FP
;
715 /* SH1 .. SH3 cores often go into small-footprint systems, so
716 default to the smallest implementation available. */
717 else if (TARGET_SH2
) /* ??? EXPERIMENTAL */
718 sh_div_strategy
= SH_DIV_CALL_TABLE
;
720 sh_div_strategy
= SH_DIV_CALL_DIV1
;
723 TARGET_PRETEND_CMOVE
= 0;
724 if (sh_divsi3_libfunc
[0])
725 ; /* User supplied - leave it alone. */
726 else if (TARGET_DIVIDE_CALL_FP
)
727 sh_divsi3_libfunc
= "__sdivsi3_i4";
728 else if (TARGET_DIVIDE_CALL_TABLE
)
729 sh_divsi3_libfunc
= "__sdivsi3_i4i";
731 sh_divsi3_libfunc
= "__sdivsi3_1";
733 sh_divsi3_libfunc
= "__sdivsi3";
734 if (sh_branch_cost
== -1)
738 /* The SH1 does not have delay slots, hence we get a pipeline stall
739 at every branch. The SH4 is superscalar, so the single delay slot
740 is not sufficient to keep both pipelines filled. */
741 if (! TARGET_SH2
|| TARGET_HARD_SH4
)
745 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
746 if (! VALID_REGISTER_P (regno
))
747 sh_register_names
[regno
][0] = '\0';
749 for (regno
= 0; regno
< ADDREGNAMES_SIZE
; regno
++)
750 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno
)))
751 sh_additional_register_names
[regno
][0] = '\0';
753 flag_omit_frame_pointer
= (PREFERRED_DEBUGGING_TYPE
== DWARF2_DEBUG
);
755 if ((flag_pic
&& ! TARGET_PREFERGOT
)
756 || (TARGET_SHMEDIA
&& !TARGET_PT_FIXED
))
757 flag_no_function_cse
= 1;
759 if (targetm
.small_register_classes_for_mode_p (VOIDmode
)) \
761 /* Never run scheduling before reload, since that can
762 break global alloc, and generates slower code anyway due
763 to the pressure on R0. */
764 /* Enable sched1 for SH4 if the user explicitly requests.
765 When sched1 is enabled, the ready queue will be reordered by
766 the target hooks if pressure is high. We can not do this for
767 PIC, SH3 and lower as they give spill failures for R0. */
768 if (!TARGET_HARD_SH4
|| flag_pic
)
769 flag_schedule_insns
= 0;
770 /* ??? Current exception handling places basic block boundaries
771 after call_insns. It causes the high pressure on R0 and gives
772 spill failures for R0 in reload. See PR 22553 and the thread
774 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
775 else if (flag_exceptions
)
777 if (flag_schedule_insns
&& global_options_set
.x_flag_schedule_insns
)
778 warning (0, "ignoring -fschedule-insns because of exception handling bug");
779 flag_schedule_insns
= 0;
781 else if (flag_schedule_insns
782 && !global_options_set
.x_flag_schedule_insns
)
783 flag_schedule_insns
= 0;
786 if ((target_flags_explicit
& MASK_ACCUMULATE_OUTGOING_ARGS
) == 0)
787 target_flags
|= MASK_ACCUMULATE_OUTGOING_ARGS
;
789 /* Unwind info is not correct around the CFG unless either a frame
790 pointer is present or M_A_O_A is set. Fixing this requires rewriting
791 unwind info generation to be aware of the CFG and propagating states
793 if ((flag_unwind_tables
|| flag_asynchronous_unwind_tables
794 || flag_exceptions
|| flag_non_call_exceptions
)
795 && flag_omit_frame_pointer
796 && !(target_flags
& MASK_ACCUMULATE_OUTGOING_ARGS
))
798 if (target_flags_explicit
& MASK_ACCUMULATE_OUTGOING_ARGS
)
799 warning (0, "unwind tables currently require either a frame pointer "
800 "or -maccumulate-outgoing-args for correctness");
801 target_flags
|= MASK_ACCUMULATE_OUTGOING_ARGS
;
804 /* Unwinding with -freorder-blocks-and-partition does not work on this
805 architecture, because it requires far jumps to label crossing between
806 hot/cold sections which are rejected on this architecture. */
807 if (flag_reorder_blocks_and_partition
)
811 inform (input_location
,
812 "-freorder-blocks-and-partition does not work with "
813 "exceptions on this architecture");
814 flag_reorder_blocks_and_partition
= 0;
815 flag_reorder_blocks
= 1;
817 else if (flag_unwind_tables
)
819 inform (input_location
,
820 "-freorder-blocks-and-partition does not support unwind "
821 "info on this architecture");
822 flag_reorder_blocks_and_partition
= 0;
823 flag_reorder_blocks
= 1;
827 /* Adjust loop, jump and function alignment values (in bytes), if those
828 were not specified by the user using -falign-loops, -falign-jumps
829 and -falign-functions options.
830 32 bit alignment is better for speed, because instructions can be
831 fetched as a pair from a longword boundary. For size use 16 bit
832 alignment to get more compact code.
833 Aligning all jumps increases the code size, even if it might
834 result in slightly faster code. Thus, it is set to the smallest
835 alignment possible if not specified by the user. */
836 if (align_loops
== 0)
841 align_loops
= optimize_size
? 2 : 4;
844 if (align_jumps
== 0)
847 align_jumps
= 1 << CACHE_LOG
;
851 else if (align_jumps
< (TARGET_SHMEDIA
? 4 : 2))
852 align_jumps
= TARGET_SHMEDIA
? 4 : 2;
854 if (align_functions
== 0)
857 align_functions
= optimize_size
858 ? FUNCTION_BOUNDARY
/8 : (1 << CACHE_LOG
);
860 align_functions
= optimize_size
? 2 : 4;
863 /* The linker relaxation code breaks when a function contains
864 alignments that are larger than that at the start of a
869 = align_loops
> align_jumps
? align_loops
: align_jumps
;
871 /* Also take possible .long constants / mova tables int account. */
874 if (align_functions
< min_align
)
875 align_functions
= min_align
;
878 if (sh_fixed_range_str
)
879 sh_fix_range (sh_fixed_range_str
);
881 /* This target defaults to strict volatile bitfields. */
882 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
883 flag_strict_volatile_bitfields
= 1;
886 /* Print the operand address in x to the stream. */
889 sh_print_operand_address (FILE *stream
, rtx x
)
891 switch (GET_CODE (x
))
895 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
900 rtx base
= XEXP (x
, 0);
901 rtx index
= XEXP (x
, 1);
903 switch (GET_CODE (index
))
906 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
907 reg_names
[true_regnum (base
)]);
913 int base_num
= true_regnum (base
);
914 int index_num
= true_regnum (index
);
916 fprintf (stream
, "@(r0,%s)",
917 reg_names
[MAX (base_num
, index_num
)]);
928 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
932 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
936 x
= mark_constant_pool_use (x
);
937 output_addr_const (stream
, x
);
942 /* Print operand x (an rtx) in assembler syntax to file stream
943 according to modifier code.
945 '.' print a .s if insn needs delay slot
946 ',' print LOCAL_LABEL_PREFIX
947 '@' print trap, rte or rts depending upon pragma interruptness
948 '#' output a nop if there is nothing to put in the delay slot
949 ''' print likelihood suffix (/u for unlikely).
950 '>' print branch target if -fverbose-asm
951 'O' print a constant without the #
952 'R' print the LSW of a dp value - changes if in little endian
953 'S' print the MSW of a dp value - changes if in little endian
954 'T' print the next word of a dp value - same as 'R' in big endian mode.
955 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
956 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
957 'N' print 'r63' if the operand is (const_int 0).
958 'd' print a V2SF reg as dN instead of fpN.
959 'm' print a pair `base,offset' or `base,index', for LD and ST.
960 'U' Likewise for {LD,ST}{HI,LO}.
961 'V' print the position of a single bit set.
962 'W' print the position of a single bit cleared.
963 't' print a memory address which is a register.
964 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
965 'o' output an operator. */
968 sh_print_operand (FILE *stream
, rtx x
, int code
)
971 enum machine_mode mode
;
979 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))
980 && get_attr_length (XVECEXP (final_sequence
, 0, 1)))
981 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
984 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
987 trapa_attr
= lookup_attribute ("trap_exit",
988 DECL_ATTRIBUTES (current_function_decl
));
990 fprintf (stream
, "trapa #%ld",
991 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr
))));
992 else if (sh_cfun_interrupt_handler_p ())
994 if (sh_cfun_resbank_handler_p ())
995 fprintf (stream
, "resbank\n");
996 fprintf (stream
, "rte");
999 fprintf (stream
, "rts");
1002 /* Output a nop if there's nothing in the delay slot. */
1003 if (dbr_sequence_length () == 0)
1004 fprintf (stream
, "\n\tnop");
1008 rtx note
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1010 if (note
&& INTVAL (XEXP (note
, 0)) * 2 < REG_BR_PROB_BASE
)
1011 fputs ("/u", stream
);
1015 if (flag_verbose_asm
&& JUMP_LABEL (current_output_insn
))
1017 fputs ("\t! target: ", stream
);
1018 output_addr_const (stream
, JUMP_LABEL (current_output_insn
));
1022 x
= mark_constant_pool_use (x
);
1023 output_addr_const (stream
, x
);
1025 /* N.B.: %R / %S / %T adjust memory addresses by four.
1026 For SHMEDIA, that means they can be used to access the first and
1027 second 32 bit part of a 64 bit (or larger) value that
1028 might be held in floating point registers or memory.
1029 While they can be used to access 64 bit parts of a larger value
1030 held in general purpose registers, that won't work with memory -
1031 neither for fp registers, since the frxx names are used. */
1033 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1035 regno
= true_regnum (x
);
1036 regno
+= FP_REGISTER_P (regno
) ? 1 : LSW
;
1037 fputs (reg_names
[regno
], (stream
));
1041 x
= adjust_address (x
, SImode
, 4 * LSW
);
1042 sh_print_operand_address (stream
, XEXP (x
, 0));
1048 mode
= GET_MODE (x
);
1049 if (mode
== VOIDmode
)
1051 if (GET_MODE_SIZE (mode
) >= 8)
1052 sub
= simplify_subreg (SImode
, x
, mode
, 4 * LSW
);
1054 sh_print_operand (stream
, sub
, 0);
1056 output_operand_lossage ("invalid operand to %%R");
1060 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1062 regno
= true_regnum (x
);
1063 regno
+= FP_REGISTER_P (regno
) ? 0 : MSW
;
1064 fputs (reg_names
[regno
], (stream
));
1068 x
= adjust_address (x
, SImode
, 4 * MSW
);
1069 sh_print_operand_address (stream
, XEXP (x
, 0));
1075 mode
= GET_MODE (x
);
1076 if (mode
== VOIDmode
)
1078 if (GET_MODE_SIZE (mode
) >= 8)
1079 sub
= simplify_subreg (SImode
, x
, mode
, 4 * MSW
);
1081 sh_print_operand (stream
, sub
, 0);
1083 output_operand_lossage ("invalid operand to %%S");
1087 /* Next word of a double. */
1088 switch (GET_CODE (x
))
1091 fputs (reg_names
[REGNO (x
) + 1], (stream
));
1094 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
1095 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
1096 x
= adjust_address (x
, SImode
, 4);
1097 sh_print_operand_address (stream
, XEXP (x
, 0));
1105 gcc_assert (MEM_P (x
));
1107 switch (GET_CODE (x
))
1111 sh_print_operand (stream
, x
, 0);
1119 switch (GET_CODE (x
))
1121 case PLUS
: fputs ("add", stream
); break;
1122 case MINUS
: fputs ("sub", stream
); break;
1123 case MULT
: fputs ("mul", stream
); break;
1124 case DIV
: fputs ("div", stream
); break;
1125 case EQ
: fputs ("eq", stream
); break;
1126 case NE
: fputs ("ne", stream
); break;
1127 case GT
: case LT
: fputs ("gt", stream
); break;
1128 case GE
: case LE
: fputs ("ge", stream
); break;
1129 case GTU
: case LTU
: fputs ("gtu", stream
); break;
1130 case GEU
: case LEU
: fputs ("geu", stream
); break;
1139 && GET_CODE (XEXP (x
, 0)) == PLUS
1140 && (REG_P (XEXP (XEXP (x
, 0), 1))
1141 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
1142 fputc ('x', stream
);
1148 switch (GET_MODE (x
))
1150 case QImode
: fputs (".b", stream
); break;
1151 case HImode
: fputs (".w", stream
); break;
1152 case SImode
: fputs (".l", stream
); break;
1153 case SFmode
: fputs (".s", stream
); break;
1154 case DFmode
: fputs (".d", stream
); break;
1155 default: gcc_unreachable ();
1162 gcc_assert (MEM_P (x
));
1166 switch (GET_CODE (x
))
1170 sh_print_operand (stream
, x
, 0);
1171 fputs (", 0", stream
);
1175 sh_print_operand (stream
, XEXP (x
, 0), 0);
1176 fputs (", ", stream
);
1177 sh_print_operand (stream
, XEXP (x
, 1), 0);
1187 int num
= exact_log2 (INTVAL (x
));
1188 gcc_assert (num
>= 0);
1189 fprintf (stream
, "#%d", num
);
1195 int num
= exact_log2 (~INTVAL (x
));
1196 gcc_assert (num
>= 0);
1197 fprintf (stream
, "#%d", num
);
1202 gcc_assert (REG_P (x
) && GET_MODE (x
) == V2SFmode
);
1204 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
1208 if (x
== CONST0_RTX (GET_MODE (x
)))
1210 fprintf ((stream
), "r63");
1213 goto default_output
;
1215 if (CONST_INT_P (x
))
1217 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
1225 mode
= GET_MODE (x
);
1227 switch (GET_CODE (x
))
1231 rtx inner
= XEXP (x
, 0);
1233 enum machine_mode inner_mode
;
1235 /* We might see SUBREGs with vector mode registers inside. */
1236 if (GET_CODE (inner
) == SUBREG
1237 && (GET_MODE_SIZE (GET_MODE (inner
))
1238 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1239 && subreg_lowpart_p (inner
))
1240 inner
= SUBREG_REG (inner
);
1241 if (CONST_INT_P (inner
))
1243 x
= GEN_INT (trunc_int_for_mode (INTVAL (inner
), GET_MODE (x
)));
1244 goto default_output
;
1246 inner_mode
= GET_MODE (inner
);
1247 if (GET_CODE (inner
) == SUBREG
1248 && (GET_MODE_SIZE (GET_MODE (inner
))
1249 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1250 && REG_P (SUBREG_REG (inner
)))
1252 offset
= subreg_regno_offset (REGNO (SUBREG_REG (inner
)),
1253 GET_MODE (SUBREG_REG (inner
)),
1254 SUBREG_BYTE (inner
),
1256 inner
= SUBREG_REG (inner
);
1258 if (!REG_P (inner
) || GET_MODE_SIZE (inner_mode
) > 8)
1260 /* Floating point register pairs are always big endian;
1261 general purpose registers are 64 bit wide. */
1262 regno
= REGNO (inner
);
1263 regno
= (HARD_REGNO_NREGS (regno
, inner_mode
)
1264 - HARD_REGNO_NREGS (regno
, mode
))
1272 /* FIXME: We need this on SHmedia32 because reload generates
1273 some sign-extended HI or QI loads into DImode registers
1274 but, because Pmode is SImode, the address ends up with a
1275 subreg:SI of the DImode register. Maybe reload should be
1276 fixed so as to apply alter_subreg to such loads? */
1278 gcc_assert (trapping_target_operand (x
, VOIDmode
));
1279 x
= XEXP (XEXP (x
, 2), 0);
1280 goto default_output
;
1282 gcc_assert (SUBREG_BYTE (x
) == 0
1283 && REG_P (SUBREG_REG (x
)));
1291 if (FP_REGISTER_P (regno
)
1292 && mode
== V16SFmode
)
1293 fprintf ((stream
), "mtrx%s", reg_names
[regno
] + 2);
1294 else if (FP_REGISTER_P (REGNO (x
))
1295 && mode
== V4SFmode
)
1296 fprintf ((stream
), "fv%s", reg_names
[regno
] + 2);
1298 && mode
== V2SFmode
)
1299 fprintf ((stream
), "fp%s", reg_names
[regno
] + 2);
1300 else if (FP_REGISTER_P (REGNO (x
))
1301 && GET_MODE_SIZE (mode
) > 4)
1302 fprintf ((stream
), "d%s", reg_names
[regno
] + 1);
1304 fputs (reg_names
[regno
], (stream
));
1308 output_address (XEXP (x
, 0));
1313 fputc ('#', stream
);
1314 output_addr_const (stream
, x
);
1322 sh_print_operand_punct_valid_p (unsigned char code
)
1324 return (code
== '.' || code
== '#' || code
== '@' || code
== ','
1325 || code
== '$' || code
== '\'' || code
== '>');
1328 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1331 sh_asm_output_addr_const_extra (FILE *file
, rtx x
)
1333 if (GET_CODE (x
) == UNSPEC
)
1335 switch (XINT (x
, 1))
1337 case UNSPEC_DATALABEL
:
1338 fputs ("datalabel ", file
);
1339 output_addr_const (file
, XVECEXP (x
, 0, 0));
1342 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1343 output_addr_const (file
, XVECEXP (x
, 0, 0));
1346 output_addr_const (file
, XVECEXP (x
, 0, 0));
1347 fputs ("@GOT", file
);
1350 output_addr_const (file
, XVECEXP (x
, 0, 0));
1351 fputs ("@GOTOFF", file
);
1354 output_addr_const (file
, XVECEXP (x
, 0, 0));
1355 fputs ("@PLT", file
);
1358 output_addr_const (file
, XVECEXP (x
, 0, 0));
1359 fputs ("@GOTPLT", file
);
1362 output_addr_const (file
, XVECEXP (x
, 0, 0));
1363 fputs ("@DTPOFF", file
);
1365 case UNSPEC_GOTTPOFF
:
1366 output_addr_const (file
, XVECEXP (x
, 0, 0));
1367 fputs ("@GOTTPOFF", file
);
1370 output_addr_const (file
, XVECEXP (x
, 0, 0));
1371 fputs ("@TPOFF", file
);
1376 /* LPCS stands for Label for PIC Call Site. */
1377 targetm
.asm_out
.generate_internal_label (name
, "LPCS",
1378 INTVAL (XVECEXP (x
, 0, 0)));
1379 assemble_name (file
, name
);
1382 case UNSPEC_EXTRACT_S16
:
1383 case UNSPEC_EXTRACT_U16
:
1387 val
= XVECEXP (x
, 0, 0);
1388 shift
= XVECEXP (x
, 0, 1);
1390 if (shift
!= const0_rtx
)
1392 if (GET_CODE (val
) == CONST
1393 || GET_RTX_CLASS (GET_CODE (val
)) != RTX_OBJ
)
1396 output_addr_const (file
, val
);
1400 output_addr_const (file
, val
);
1401 if (shift
!= const0_rtx
)
1403 fputs (" >> ", file
);
1404 output_addr_const (file
, shift
);
1407 fputs (" & 65535)", file
);
1411 output_addr_const (file
, XVECEXP (x
, 0, 0));
1413 if (GET_CODE (XVECEXP (x
, 0, 1)) == CONST
)
1416 output_addr_const (file
, XVECEXP (x
, 0, 1));
1420 output_addr_const (file
, XVECEXP (x
, 0, 1));
1422 case UNSPEC_PCREL_SYMOFF
:
1423 output_addr_const (file
, XVECEXP (x
, 0, 0));
1425 output_addr_const (file
, XVECEXP (x
, 0, 1));
1426 fputs ("-.)", file
);
1438 /* Encode symbol attributes of a SYMBOL_REF into its
1439 SYMBOL_REF_FLAGS. */
1441 sh_encode_section_info (tree decl
, rtx rtl
, int first
)
1443 default_encode_section_info (decl
, rtl
, first
);
1445 if (TREE_CODE (decl
) == FUNCTION_DECL
1446 && sh2a_function_vector_p (decl
) && TARGET_SH2A
)
1447 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
1450 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1452 force_into (rtx value
, rtx target
)
1454 value
= force_operand (value
, target
);
1455 if (! rtx_equal_p (value
, target
))
1456 emit_insn (gen_move_insn (target
, value
));
1459 /* Emit code to perform a block move. Choose the best method.
1461 OPERANDS[0] is the destination.
1462 OPERANDS[1] is the source.
1463 OPERANDS[2] is the size.
1464 OPERANDS[3] is the alignment safe to use. */
1467 expand_block_move (rtx
*operands
)
1469 int align
= INTVAL (operands
[3]);
1470 int constp
= (CONST_INT_P (operands
[2]));
1471 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
1476 /* If we could use mov.l to move words and dest is word-aligned, we
1477 can use movua.l for loads and still generate a relatively short
1478 and efficient sequence. */
1479 if (TARGET_SH4A_ARCH
&& align
< 4
1480 && MEM_ALIGN (operands
[0]) >= 32
1481 && can_move_by_pieces (bytes
, 32))
1483 rtx dest
= copy_rtx (operands
[0]);
1484 rtx src
= copy_rtx (operands
[1]);
1485 /* We could use different pseudos for each copied word, but
1486 since movua can only load into r0, it's kind of
1488 rtx temp
= gen_reg_rtx (SImode
);
1489 rtx src_addr
= copy_addr_to_reg (XEXP (src
, 0));
1492 while (copied
+ 4 <= bytes
)
1494 rtx to
= adjust_address (dest
, SImode
, copied
);
1495 rtx from
= adjust_automodify_address (src
, BLKmode
,
1498 set_mem_size (from
, 4);
1499 emit_insn (gen_movua (temp
, from
));
1500 emit_move_insn (src_addr
, plus_constant (src_addr
, 4));
1501 emit_move_insn (to
, temp
);
1506 move_by_pieces (adjust_address (dest
, BLKmode
, copied
),
1507 adjust_automodify_address (src
, BLKmode
,
1509 bytes
- copied
, align
, 0);
1514 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1515 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1516 if (align
< 4 || (bytes
% 4 != 0))
1519 if (TARGET_HARD_SH4
)
1523 else if (bytes
== 12)
1525 rtx func_addr_rtx
= gen_reg_rtx (Pmode
);
1526 rtx r4
= gen_rtx_REG (SImode
, 4);
1527 rtx r5
= gen_rtx_REG (SImode
, 5);
1529 function_symbol (func_addr_rtx
, "__movmemSI12_i4", SFUNC_STATIC
);
1530 force_into (XEXP (operands
[0], 0), r4
);
1531 force_into (XEXP (operands
[1], 0), r5
);
1532 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
1535 else if (! optimize_size
)
1537 const char *entry_name
;
1538 rtx func_addr_rtx
= gen_reg_rtx (Pmode
);
1540 rtx r4
= gen_rtx_REG (SImode
, 4);
1541 rtx r5
= gen_rtx_REG (SImode
, 5);
1542 rtx r6
= gen_rtx_REG (SImode
, 6);
1544 entry_name
= (bytes
& 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1545 function_symbol (func_addr_rtx
, entry_name
, SFUNC_STATIC
);
1546 force_into (XEXP (operands
[0], 0), r4
);
1547 force_into (XEXP (operands
[1], 0), r5
);
1549 dwords
= bytes
>> 3;
1550 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
1551 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
1560 rtx func_addr_rtx
= gen_reg_rtx (Pmode
);
1561 rtx r4
= gen_rtx_REG (SImode
, 4);
1562 rtx r5
= gen_rtx_REG (SImode
, 5);
1564 sprintf (entry
, "__movmemSI%d", bytes
);
1565 function_symbol (func_addr_rtx
, entry
, SFUNC_STATIC
);
1566 force_into (XEXP (operands
[0], 0), r4
);
1567 force_into (XEXP (operands
[1], 0), r5
);
1568 emit_insn (gen_block_move_real (func_addr_rtx
));
1572 /* This is the same number of bytes as a memcpy call, but to a different
1573 less common function name, so this will occasionally use more space. */
1574 if (! optimize_size
)
1576 rtx func_addr_rtx
= gen_reg_rtx (Pmode
);
1577 int final_switch
, while_loop
;
1578 rtx r4
= gen_rtx_REG (SImode
, 4);
1579 rtx r5
= gen_rtx_REG (SImode
, 5);
1580 rtx r6
= gen_rtx_REG (SImode
, 6);
1582 function_symbol (func_addr_rtx
, "__movmem", SFUNC_STATIC
);
1583 force_into (XEXP (operands
[0], 0), r4
);
1584 force_into (XEXP (operands
[1], 0), r5
);
1586 /* r6 controls the size of the move. 16 is decremented from it
1587 for each 64 bytes moved. Then the negative bit left over is used
1588 as an index into a list of move instructions. e.g., a 72 byte move
1589 would be set up with size(r6) = 14, for one iteration through the
1590 big while loop, and a switch of -2 for the last part. */
1592 final_switch
= 16 - ((bytes
/ 4) % 16);
1593 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
1594 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
1595 emit_insn (gen_block_lump_real (func_addr_rtx
));
1602 /* Prepare operands for a move define_expand; specifically, one of the
1603 operands must be in a register. */
1606 prepare_move_operands (rtx operands
[], enum machine_mode mode
)
1608 if ((mode
== SImode
|| mode
== DImode
)
1610 && ! ((mode
== Pmode
|| mode
== ptr_mode
)
1611 && tls_symbolic_operand (operands
[1], Pmode
) != TLS_MODEL_NONE
))
1614 if (SYMBOLIC_CONST_P (operands
[1]))
1616 if (MEM_P (operands
[0]))
1617 operands
[1] = force_reg (Pmode
, operands
[1]);
1618 else if (TARGET_SHMEDIA
1619 && GET_CODE (operands
[1]) == LABEL_REF
1620 && target_reg_operand (operands
[0], mode
))
1624 temp
= (!can_create_pseudo_p ()
1626 : gen_reg_rtx (Pmode
));
1627 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
1630 else if (GET_CODE (operands
[1]) == CONST
1631 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1632 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
1634 temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
1635 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
1637 operands
[1] = expand_binop (mode
, add_optab
, temp
,
1638 XEXP (XEXP (operands
[1], 0), 1),
1639 (!can_create_pseudo_p ()
1641 : gen_reg_rtx (Pmode
)),
1642 0, OPTAB_LIB_WIDEN
);
1646 if (! reload_in_progress
&& ! reload_completed
)
1648 /* Copy the source to a register if both operands aren't registers. */
1649 if (! register_operand (operands
[0], mode
)
1650 && ! sh_register_operand (operands
[1], mode
))
1651 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1653 if (MEM_P (operands
[0]) && ! memory_operand (operands
[0], mode
))
1655 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1656 except that we can't use that function because it is static. */
1657 rtx new_rtx
= change_address (operands
[0], mode
, 0);
1658 MEM_COPY_ATTRIBUTES (new_rtx
, operands
[0]);
1659 operands
[0] = new_rtx
;
1662 /* This case can happen while generating code to move the result
1663 of a library call to the target. Reject `st r0,@(rX,rY)' because
1664 reload will fail to find a spill register for rX, since r0 is already
1665 being used for the source. */
1667 && refers_to_regno_p (R0_REG
, R0_REG
+ 1, operands
[1], (rtx
*)0)
1668 && MEM_P (operands
[0])
1669 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
1670 && REG_P (XEXP (XEXP (operands
[0], 0), 1)))
1671 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1674 if (mode
== Pmode
|| mode
== ptr_mode
)
1677 enum tls_model tls_kind
;
1681 if (GET_CODE (op1
) == CONST
1682 && GET_CODE (XEXP (op1
, 0)) == PLUS
1683 && (tls_symbolic_operand (XEXP (XEXP (op1
, 0), 0), Pmode
)
1686 opc
= XEXP (XEXP (op1
, 0), 1);
1687 op1
= XEXP (XEXP (op1
, 0), 0);
1692 if ((tls_kind
= tls_symbolic_operand (op1
, Pmode
)) != TLS_MODEL_NONE
)
1694 rtx tga_op1
, tga_ret
, tmp
, tmp2
;
1697 && (tls_kind
== TLS_MODEL_GLOBAL_DYNAMIC
1698 || tls_kind
== TLS_MODEL_LOCAL_DYNAMIC
1699 || tls_kind
== TLS_MODEL_INITIAL_EXEC
))
1701 /* Don't schedule insns for getting GOT address when
1702 the first scheduling is enabled, to avoid spill
1704 if (flag_schedule_insns
)
1705 emit_insn (gen_blockage ());
1706 emit_insn (gen_GOTaddr2picreg ());
1707 emit_use (gen_rtx_REG (SImode
, PIC_REG
));
1708 if (flag_schedule_insns
)
1709 emit_insn (gen_blockage ());
1714 case TLS_MODEL_GLOBAL_DYNAMIC
:
1715 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1716 emit_call_insn (gen_tls_global_dynamic (tga_ret
, op1
));
1717 tmp
= gen_reg_rtx (Pmode
);
1718 emit_move_insn (tmp
, tga_ret
);
1722 case TLS_MODEL_LOCAL_DYNAMIC
:
1723 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1724 emit_call_insn (gen_tls_local_dynamic (tga_ret
, op1
));
1726 tmp
= gen_reg_rtx (Pmode
);
1727 emit_move_insn (tmp
, tga_ret
);
1729 if (register_operand (op0
, Pmode
))
1732 tmp2
= gen_reg_rtx (Pmode
);
1734 emit_insn (gen_symDTPOFF2reg (tmp2
, op1
, tmp
));
1738 case TLS_MODEL_INITIAL_EXEC
:
1739 tga_op1
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (Pmode
);
1740 tmp
= gen_sym2GOTTPOFF (op1
);
1741 emit_insn (gen_tls_initial_exec (tga_op1
, tmp
));
1745 case TLS_MODEL_LOCAL_EXEC
:
1746 tmp2
= gen_reg_rtx (Pmode
);
1747 emit_insn (gen_load_gbr (tmp2
));
1748 tmp
= gen_reg_rtx (Pmode
);
1749 emit_insn (gen_symTPOFF2reg (tmp
, op1
));
1751 if (register_operand (op0
, Pmode
))
1754 op1
= gen_reg_rtx (Pmode
);
1756 emit_insn (gen_addsi3 (op1
, tmp
, tmp2
));
1763 emit_insn (gen_addsi3 (op1
, op1
, force_reg (SImode
, opc
)));
1772 prepare_cbranch_operands (rtx
*operands
, enum machine_mode mode
,
1773 enum rtx_code comparison
)
1776 rtx scratch
= NULL_RTX
;
1778 if (comparison
== LAST_AND_UNUSED_RTX_CODE
)
1779 comparison
= GET_CODE (operands
[0]);
1781 scratch
= operands
[4];
1782 if (CONST_INT_P (operands
[1])
1783 && !CONST_INT_P (operands
[2]))
1785 rtx tmp
= operands
[1];
1787 operands
[1] = operands
[2];
1789 comparison
= swap_condition (comparison
);
1791 if (CONST_INT_P (operands
[2]))
1793 HOST_WIDE_INT val
= INTVAL (operands
[2]);
1794 if ((val
== -1 || val
== -0x81)
1795 && (comparison
== GT
|| comparison
== LE
))
1797 comparison
= (comparison
== GT
) ? GE
: LT
;
1798 operands
[2] = gen_int_mode (val
+ 1, mode
);
1800 else if ((val
== 1 || val
== 0x80)
1801 && (comparison
== GE
|| comparison
== LT
))
1803 comparison
= (comparison
== GE
) ? GT
: LE
;
1804 operands
[2] = gen_int_mode (val
- 1, mode
);
1806 else if (val
== 1 && (comparison
== GEU
|| comparison
== LTU
))
1808 comparison
= (comparison
== GEU
) ? NE
: EQ
;
1809 operands
[2] = CONST0_RTX (mode
);
1811 else if (val
== 0x80 && (comparison
== GEU
|| comparison
== LTU
))
1813 comparison
= (comparison
== GEU
) ? GTU
: LEU
;
1814 operands
[2] = gen_int_mode (val
- 1, mode
);
1816 else if (val
== 0 && (comparison
== GTU
|| comparison
== LEU
))
1817 comparison
= (comparison
== GTU
) ? NE
: EQ
;
1818 else if (mode
== SImode
1819 && ((val
== 0x7fffffff
1820 && (comparison
== GTU
|| comparison
== LEU
))
1821 || ((unsigned HOST_WIDE_INT
) val
1822 == (unsigned HOST_WIDE_INT
) 0x7fffffff + 1
1823 && (comparison
== GEU
|| comparison
== LTU
))))
1825 comparison
= (comparison
== GTU
|| comparison
== GEU
) ? LT
: GE
;
1826 operands
[2] = CONST0_RTX (mode
);
1830 if (can_create_pseudo_p ())
1831 operands
[1] = force_reg (mode
, op1
);
1832 /* When we are handling DImode comparisons, we want to keep constants so
1833 that we can optimize the component comparisons; however, memory loads
1834 are better issued as a whole so that they can be scheduled well.
1835 SImode equality comparisons allow I08 constants, but only when they
1836 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1837 into a register, that register might as well be r0, and we allow the
1838 constant. If it is already in a register, this is likely to be
1839 allocated to a different hard register, thus we load the constant into
1840 a register unless it is zero. */
1841 if (!REG_P (operands
[2])
1842 && (!CONST_INT_P (operands
[2])
1843 || (mode
== SImode
&& operands
[2] != CONST0_RTX (SImode
)
1844 && ((comparison
!= EQ
&& comparison
!= NE
)
1845 || (REG_P (op1
) && REGNO (op1
) != R0_REG
)
1846 || !satisfies_constraint_I08 (operands
[2])))))
1848 if (scratch
&& GET_MODE (scratch
) == mode
)
1850 emit_move_insn (scratch
, operands
[2]);
1851 operands
[2] = scratch
;
1853 else if (can_create_pseudo_p ())
1854 operands
[2] = force_reg (mode
, operands
[2]);
1860 expand_cbranchsi4 (rtx
*operands
, enum rtx_code comparison
, int probability
)
1862 rtx (*branch_expander
) (rtx
) = gen_branch_true
;
1865 comparison
= prepare_cbranch_operands (operands
, SImode
, comparison
);
1868 case NE
: case LT
: case LE
: case LTU
: case LEU
:
1869 comparison
= reverse_condition (comparison
);
1870 branch_expander
= gen_branch_false
;
1873 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, T_REG
),
1874 gen_rtx_fmt_ee (comparison
, SImode
,
1875 operands
[1], operands
[2])));
1876 jump
= emit_jump_insn (branch_expander (operands
[3]));
1877 if (probability
>= 0)
1878 add_reg_note (jump
, REG_BR_PROB
, GEN_INT (probability
));
1882 /* ??? How should we distribute probabilities when more than one branch
1883 is generated. So far we only have some ad-hoc observations:
1884 - If the operands are random, they are likely to differ in both parts.
1885 - If comparing items in a hash chain, the operands are random or equal;
1886 operation should be EQ or NE.
1887 - If items are searched in an ordered tree from the root, we can expect
1888 the highpart to be unequal about half of the time; operation should be
1889 an inequality comparison, operands non-constant, and overall probability
1890 about 50%. Likewise for quicksort.
1891 - Range checks will be often made against constants. Even if we assume for
1892 simplicity an even distribution of the non-constant operand over a
1893 sub-range here, the same probability could be generated with differently
1894 wide sub-ranges - as long as the ratio of the part of the subrange that
1895 is before the threshold to the part that comes after the threshold stays
1896 the same. Thus, we can't really tell anything here;
1897 assuming random distribution is at least simple.
1901 expand_cbranchdi4 (rtx
*operands
, enum rtx_code comparison
)
1903 enum rtx_code msw_taken
, msw_skip
, lsw_taken
;
1904 rtx skip_label
= NULL_RTX
;
1905 rtx op1h
, op1l
, op2h
, op2l
;
1908 int msw_taken_prob
= -1, msw_skip_prob
= -1, lsw_taken_prob
= -1;
1909 rtx scratch
= operands
[4];
1911 comparison
= prepare_cbranch_operands (operands
, DImode
, comparison
);
1912 op1h
= gen_highpart_mode (SImode
, DImode
, operands
[1]);
1913 op2h
= gen_highpart_mode (SImode
, DImode
, operands
[2]);
1914 op1l
= gen_lowpart (SImode
, operands
[1]);
1915 op2l
= gen_lowpart (SImode
, operands
[2]);
1916 msw_taken
= msw_skip
= lsw_taken
= LAST_AND_UNUSED_RTX_CODE
;
1917 prob
= split_branch_probability
;
1918 rev_prob
= REG_BR_PROB_BASE
- prob
;
1921 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1922 That costs 1 cycle more when the first branch can be predicted taken,
1923 but saves us mispredicts because only one branch needs prediction.
1924 It also enables generating the cmpeqdi_t-1 pattern. */
1926 if (TARGET_CMPEQDI_T
)
1928 emit_insn (gen_cmpeqdi_t (operands
[1], operands
[2]));
1929 emit_jump_insn (gen_branch_true (operands
[3]));
1936 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1938 msw_skip_prob
= rev_prob
;
1939 if (REG_BR_PROB_BASE
<= 65535)
1940 lsw_taken_prob
= prob
? REG_BR_PROB_BASE
: 0;
1943 gcc_assert (HOST_BITS_PER_WIDEST_INT
>= 64);
1947 - ((HOST_WIDEST_INT
) REG_BR_PROB_BASE
* rev_prob
1948 / ((HOST_WIDEST_INT
) prob
<< 32)))
1954 if (TARGET_CMPEQDI_T
)
1956 emit_insn (gen_cmpeqdi_t (operands
[1], operands
[2]));
1957 emit_jump_insn (gen_branch_false (operands
[3]));
1961 msw_taken_prob
= prob
;
1966 msw_taken
= comparison
;
1967 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
1969 if (comparison
!= GTU
|| op2h
!= CONST0_RTX (SImode
))
1970 msw_skip
= swap_condition (msw_taken
);
1974 if (op2l
== CONST0_RTX (SImode
))
1975 msw_taken
= comparison
;
1978 msw_taken
= comparison
== GE
? GT
: GTU
;
1979 msw_skip
= swap_condition (msw_taken
);
1984 msw_taken
= comparison
;
1985 if (op2l
== CONST0_RTX (SImode
))
1987 msw_skip
= swap_condition (msw_taken
);
1991 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
1992 msw_taken
= comparison
;
1996 if (comparison
== LE
)
1998 else if (op2h
!= CONST0_RTX (SImode
))
2002 msw_skip
= swap_condition (LTU
);
2005 msw_skip
= swap_condition (msw_taken
);
2008 default: return false;
2010 num_branches
= ((msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2011 + (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2012 + (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
));
2013 if (comparison
!= EQ
&& comparison
!= NE
&& num_branches
> 1)
2015 if (!CONSTANT_P (operands
[2])
2016 && prob
>= (int) (REG_BR_PROB_BASE
* 3 / 8U)
2017 && prob
<= (int) (REG_BR_PROB_BASE
* 5 / 8U))
2019 msw_taken_prob
= prob
/ 2U;
2021 = REG_BR_PROB_BASE
* rev_prob
/ (REG_BR_PROB_BASE
+ rev_prob
);
2022 lsw_taken_prob
= prob
;
2026 msw_taken_prob
= prob
;
2027 msw_skip_prob
= REG_BR_PROB_BASE
;
2028 /* ??? If we have a constant op2h, should we use that when
2029 calculating lsw_taken_prob? */
2030 lsw_taken_prob
= prob
;
2035 operands
[4] = NULL_RTX
;
2036 if (reload_completed
2037 && ! arith_reg_or_0_operand (op2h
, SImode
)
2038 && (true_regnum (op1h
) || (comparison
!= EQ
&& comparison
!= NE
))
2039 && (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
2040 || msw_skip
!= LAST_AND_UNUSED_RTX_CODE
))
2042 emit_move_insn (scratch
, operands
[2]);
2043 operands
[2] = scratch
;
2045 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2046 expand_cbranchsi4 (operands
, msw_taken
, msw_taken_prob
);
2047 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2049 rtx taken_label
= operands
[3];
2051 /* Operands were possibly modified, but msw_skip doesn't expect this.
2052 Always use the original ones. */
2053 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2057 if (reload_completed
2058 && ! arith_reg_or_0_operand (op2h
, SImode
)
2059 && (true_regnum (op1h
) || (comparison
!= EQ
&& comparison
!= NE
)))
2061 emit_move_insn (scratch
, operands
[2]);
2062 operands
[2] = scratch
;
2066 operands
[3] = skip_label
= gen_label_rtx ();
2067 expand_cbranchsi4 (operands
, msw_skip
, msw_skip_prob
);
2068 operands
[3] = taken_label
;
2072 if (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2074 if (reload_completed
2075 && ! arith_reg_or_0_operand (op2l
, SImode
)
2076 && (true_regnum (op1l
) || (lsw_taken
!= EQ
&& lsw_taken
!= NE
)))
2078 emit_move_insn (scratch
, operands
[2]);
2079 operands
[2] = scratch
;
2081 expand_cbranchsi4 (operands
, lsw_taken
, lsw_taken_prob
);
2083 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2084 emit_label (skip_label
);
2088 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2091 sh_emit_set_t_insn (rtx insn
, enum machine_mode mode
)
2093 if ((TARGET_SH4
|| TARGET_SH2A
) && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2095 insn
= gen_rtx_PARALLEL (VOIDmode
,
2097 gen_rtx_USE (VOIDmode
, get_fpscr_rtx ())));
2098 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
2104 /* Prepare the operands for an scc instruction; make sure that the
2105 compare has been done and the result is in T_REG. */
2107 sh_emit_scc_to_t (enum rtx_code code
, rtx op0
, rtx op1
)
2109 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
2110 enum rtx_code oldcode
= code
;
2111 enum machine_mode mode
;
2113 /* First need a compare insn. */
2117 /* It isn't possible to handle this case. */
2134 if (code
!= oldcode
)
2141 mode
= GET_MODE (op0
);
2142 if (mode
== VOIDmode
)
2143 mode
= GET_MODE (op1
);
2145 op0
= force_reg (mode
, op0
);
2146 if ((code
!= EQ
&& code
!= NE
2147 && (op1
!= const0_rtx
2148 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2149 || (mode
== DImode
&& op1
!= const0_rtx
)
2150 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2151 op1
= force_reg (mode
, op1
);
2153 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode
, t_reg
,
2154 gen_rtx_fmt_ee (code
, SImode
, op0
, op1
)),
2159 sh_emit_cheap_store_flag (enum machine_mode mode
, enum rtx_code code
,
2162 rtx target
= gen_reg_rtx (SImode
);
2165 gcc_assert (TARGET_SHMEDIA
);
2174 tmp
= gen_rtx_fmt_ee (code
, SImode
, op0
, op1
);
2175 emit_insn (gen_cstore4_media (target
, tmp
, op0
, op1
));
2185 tmp
= gen_rtx_fmt_ee (reverse_condition (code
), mode
, op0
, op1
);
2186 emit_insn (gen_cstore4_media (target
, tmp
, op0
, op1
));
2204 rtx t2
= gen_reg_rtx (DImode
);
2205 emit_insn (gen_extendsidi2 (t2
, target
));
2209 return gen_rtx_fmt_ee (code
, VOIDmode
, target
, const0_rtx
);
2212 /* Called from the md file, set up the operands of a compare instruction. */
2215 sh_emit_compare_and_branch (rtx
*operands
, enum machine_mode mode
)
2217 enum rtx_code code
= GET_CODE (operands
[0]);
2218 enum rtx_code branch_code
;
2219 rtx op0
= operands
[1];
2220 rtx op1
= operands
[2];
2222 bool need_ccmpeq
= false;
2224 if (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2226 op0
= force_reg (mode
, op0
);
2227 op1
= force_reg (mode
, op1
);
2231 if (code
!= EQ
|| mode
== DImode
)
2233 /* Force args into regs, since we can't use constants here. */
2234 op0
= force_reg (mode
, op0
);
2235 if (op1
!= const0_rtx
|| code
== GTU
|| code
== GEU
)
2236 op1
= force_reg (mode
, op1
);
2240 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2243 || (code
== LE
&& TARGET_IEEE
&& TARGET_SH2E
)
2244 || (code
== GE
&& !(TARGET_IEEE
&& TARGET_SH2E
)))
2246 tem
= op0
, op0
= op1
, op1
= tem
;
2247 code
= swap_condition (code
);
2250 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2253 gcc_assert (TARGET_IEEE
&& TARGET_SH2E
);
2258 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2259 to EQ/GT respectively. */
2260 gcc_assert (code
== EQ
|| code
== GT
|| code
== NE
|| code
== LE
);
2277 branch_code
= reverse_condition (code
);
2283 insn
= gen_rtx_SET (VOIDmode
,
2284 gen_rtx_REG (SImode
, T_REG
),
2285 gen_rtx_fmt_ee (branch_code
, SImode
, op0
, op1
));
2287 sh_emit_set_t_insn (insn
, mode
);
2289 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0
, op1
), mode
);
2291 if (branch_code
== code
)
2292 emit_jump_insn (gen_branch_true (operands
[3]));
2294 emit_jump_insn (gen_branch_false (operands
[3]));
2298 sh_emit_compare_and_set (rtx
*operands
, enum machine_mode mode
)
2300 enum rtx_code code
= GET_CODE (operands
[1]);
2301 rtx op0
= operands
[2];
2302 rtx op1
= operands
[3];
2304 bool invert
= false;
2307 op0
= force_reg (mode
, op0
);
2308 if ((code
!= EQ
&& code
!= NE
2309 && (op1
!= const0_rtx
2310 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2311 || (mode
== DImode
&& op1
!= const0_rtx
)
2312 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2313 op1
= force_reg (mode
, op1
);
2315 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2317 if (code
== LT
|| code
== LE
)
2319 code
= swap_condition (code
);
2320 tem
= op0
, op0
= op1
, op1
= tem
;
2326 lab
= gen_label_rtx ();
2327 sh_emit_scc_to_t (EQ
, op0
, op1
);
2328 emit_jump_insn (gen_branch_true (lab
));
2345 sh_emit_scc_to_t (code
, op0
, op1
);
2349 emit_insn (gen_movnegt (operands
[0]));
2351 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, T_REG
));
2354 /* Functions to output assembly code. */
2356 /* Return a sequence of instructions to perform DI or DF move.
2358 Since the SH cannot move a DI or DF in one instruction, we have
2359 to take care when we see overlapping source and dest registers. */
2362 output_movedouble (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
2363 enum machine_mode mode
)
2365 rtx dst
= operands
[0];
2366 rtx src
= operands
[1];
2369 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
2370 return "mov.l %T1,%0\n\tmov.l %1,%0";
2372 if (register_operand (dst
, mode
)
2373 && register_operand (src
, mode
))
2375 if (REGNO (src
) == MACH_REG
)
2376 return "sts mach,%S0\n\tsts macl,%R0";
2378 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2379 when mov.d r1,r0 do r1->r0 then r2->r1. */
2381 if (REGNO (src
) + 1 == REGNO (dst
))
2382 return "mov %T1,%T0\n\tmov %1,%0";
2384 return "mov %1,%0\n\tmov %T1,%T0";
2386 else if (CONST_INT_P (src
))
2388 if (INTVAL (src
) < 0)
2389 output_asm_insn ("mov #-1,%S0", operands
);
2391 output_asm_insn ("mov #0,%S0", operands
);
2393 return "mov %1,%R0";
2395 else if (MEM_P (src
))
2398 int dreg
= REGNO (dst
);
2399 rtx inside
= XEXP (src
, 0);
2401 switch (GET_CODE (inside
))
2404 ptrreg
= REGNO (inside
);
2408 ptrreg
= subreg_regno (inside
);
2412 ptrreg
= REGNO (XEXP (inside
, 0));
2413 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2414 an offsettable address. Unfortunately, offsettable addresses use
2415 QImode to check the offset, and a QImode offsettable address
2416 requires r0 for the other operand, which is not currently
2417 supported, so we can't use the 'o' constraint.
2418 Thus we must check for and handle r0+REG addresses here.
2419 We punt for now, since this is likely very rare. */
2420 gcc_assert (!REG_P (XEXP (inside
, 1)));
2424 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2426 return "mov.l %1,%0\n\tmov.l %1,%T0";
2431 /* Work out the safe way to copy. Copy into the second half first. */
2433 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2436 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2439 /* Print an instruction which would have gone into a delay slot after
2440 another instruction, but couldn't because the other instruction expanded
2441 into a sequence where putting the slot insn at the end wouldn't work. */
2444 print_slot (rtx insn
)
2446 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 1, NULL
);
2448 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
2452 output_far_jump (rtx insn
, rtx op
)
2454 struct { rtx lab
, reg
, op
; } this_jmp
;
2455 rtx braf_base_lab
= NULL_RTX
;
2458 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2461 this_jmp
.lab
= gen_label_rtx ();
2465 && offset
- get_attr_length (insn
) <= 32766)
2468 jump
= "mov.w %O0,%1; braf %1";
2476 jump
= "mov.l %O0,%1; braf %1";
2478 jump
= "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2481 jump
= "mov.l %O0,%1; jmp @%1";
2483 /* If we have a scratch register available, use it. */
2484 if (NONJUMP_INSN_P ((prev
= prev_nonnote_insn (insn
)))
2485 && INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
2487 this_jmp
.reg
= SET_DEST (XVECEXP (PATTERN (prev
), 0, 0));
2488 if (REGNO (this_jmp
.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
2489 jump
= "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2490 output_asm_insn (jump
, &this_jmp
.lab
);
2491 if (dbr_sequence_length ())
2492 print_slot (final_sequence
);
2494 output_asm_insn ("nop", 0);
2498 /* Output the delay slot insn first if any. */
2499 if (dbr_sequence_length ())
2500 print_slot (final_sequence
);
2502 this_jmp
.reg
= gen_rtx_REG (SImode
, 13);
2503 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2504 Fortunately, MACL is fixed and call-clobbered, and we never
2505 need its value across jumps, so save r13 in it instead of in
2508 output_asm_insn ("lds r13, macl", 0);
2510 output_asm_insn ("mov.l r13,@-r15", 0);
2511 output_asm_insn (jump
, &this_jmp
.lab
);
2513 output_asm_insn ("sts macl, r13", 0);
2515 output_asm_insn ("mov.l @r15+,r13", 0);
2517 if (far
&& flag_pic
&& TARGET_SH2
)
2519 braf_base_lab
= gen_label_rtx ();
2520 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
2521 CODE_LABEL_NUMBER (braf_base_lab
));
2524 output_asm_insn (".align 2", 0);
2525 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (this_jmp
.lab
));
2527 if (far
&& flag_pic
)
2530 this_jmp
.lab
= braf_base_lab
;
2531 output_asm_insn (".long %O2-%O0", &this_jmp
.lab
);
2534 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this_jmp
.lab
);
2538 /* Local label counter, used for constants in the pool and inside
2539 pattern branches. */
2541 static int lf
= 100;
2543 /* Output code for ordinary branches. */
2546 output_branch (int logic
, rtx insn
, rtx
*operands
)
2548 switch (get_attr_length (insn
))
2551 /* This can happen if filling the delay slot has caused a forward
2552 branch to exceed its range (we could reverse it, but only
2553 when we know we won't overextend other branches; this should
2554 best be handled by relaxation).
2555 It can also happen when other condbranches hoist delay slot insn
2556 from their destination, thus leading to code size increase.
2557 But the branch will still be in the range -4092..+4098 bytes. */
2562 /* The call to print_slot will clobber the operands. */
2563 rtx op0
= operands
[0];
2565 /* If the instruction in the delay slot is annulled (true), then
2566 there is no delay slot where we can put it now. The only safe
2567 place for it is after the label. final will do that by default. */
2570 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))
2571 && get_attr_length (XVECEXP (final_sequence
, 0, 1)))
2573 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
2574 ASSEMBLER_DIALECT
? "/" : ".", label
);
2575 print_slot (final_sequence
);
2578 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
2580 output_asm_insn ("bra\t%l0", &op0
);
2581 fprintf (asm_out_file
, "\tnop\n");
2582 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2586 /* When relaxing, handle this like a short branch. The linker
2587 will fix it up if it still doesn't fit after relaxation. */
2589 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
2591 /* These are for SH2e, in which we have to account for the
2592 extra nop because of the hardware bug in annulled branches. */
2598 gcc_assert (!final_sequence
2599 || !(INSN_ANNULLED_BRANCH_P
2600 (XVECEXP (final_sequence
, 0, 0))));
2601 asm_fprintf (asm_out_file
, "b%s%ss\t%LLF%d\n",
2603 ASSEMBLER_DIALECT
? "/" : ".", label
);
2604 fprintf (asm_out_file
, "\tnop\n");
2605 output_asm_insn ("bra\t%l0", operands
);
2606 fprintf (asm_out_file
, "\tnop\n");
2607 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2611 /* When relaxing, fall through. */
2616 sprintf (buffer
, "b%s%ss\t%%l0",
2618 ASSEMBLER_DIALECT
? "/" : ".");
2619 output_asm_insn (buffer
, &operands
[0]);
2624 /* There should be no longer branches now - that would
2625 indicate that something has destroyed the branches set
2626 up in machine_dependent_reorg. */
2631 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2632 fill in operands 9 as a label to the successor insn.
2633 We try to use jump threading where possible.
2634 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2635 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2636 follow jmp and bt, if the address is in range. */
2638 output_branchy_insn (enum rtx_code code
, const char *templ
,
2639 rtx insn
, rtx
*operands
)
2641 rtx next_insn
= NEXT_INSN (insn
);
2643 if (next_insn
&& JUMP_P (next_insn
) && condjump_p (next_insn
))
2645 rtx src
= SET_SRC (PATTERN (next_insn
));
2646 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
2648 /* Following branch not taken */
2649 operands
[9] = gen_label_rtx ();
2650 emit_label_after (operands
[9], next_insn
);
2651 INSN_ADDRESSES_NEW (operands
[9],
2652 INSN_ADDRESSES (INSN_UID (next_insn
))
2653 + get_attr_length (next_insn
));
2658 int offset
= (branch_dest (next_insn
)
2659 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
2660 if (offset
>= -252 && offset
<= 258)
2662 if (GET_CODE (src
) == IF_THEN_ELSE
)
2664 src
= XEXP (src
, 1);
2670 operands
[9] = gen_label_rtx ();
2671 emit_label_after (operands
[9], insn
);
2672 INSN_ADDRESSES_NEW (operands
[9],
2673 INSN_ADDRESSES (INSN_UID (insn
))
2674 + get_attr_length (insn
));
2679 output_ieee_ccmpeq (rtx insn
, rtx
*operands
)
2681 return output_branchy_insn (NE
, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2685 /* Output the start of the assembler file. */
2688 sh_file_start (void)
2690 default_file_start ();
2693 /* We need to show the text section with the proper
2694 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2695 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2696 will complain. We can teach GAS specifically about the
2697 default attributes for our choice of text section, but
2698 then we would have to change GAS again if/when we change
2699 the text section name. */
2700 fprintf (asm_out_file
, "%s\n", TEXT_SECTION_ASM_OP
);
2702 /* Switch to the data section so that the coffsem symbol
2703 isn't in the text section. */
2704 switch_to_section (data_section
);
2706 if (TARGET_LITTLE_ENDIAN
)
2707 fputs ("\t.little\n", asm_out_file
);
2711 if (TARGET_SHCOMPACT
)
2712 fputs ("\t.mode\tSHcompact\n", asm_out_file
);
2713 else if (TARGET_SHMEDIA
)
2714 fprintf (asm_out_file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2715 TARGET_SHMEDIA64
? 64 : 32);
2719 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2722 unspec_caller_rtx_p (rtx pat
)
2727 split_const (pat
, &base
, &offset
);
2728 if (GET_CODE (base
) == UNSPEC
)
2730 if (XINT (base
, 1) == UNSPEC_CALLER
)
2732 for (i
= 0; i
< XVECLEN (base
, 0); i
++)
2733 if (unspec_caller_rtx_p (XVECEXP (base
, 0, i
)))
2739 /* Indicate that INSN cannot be duplicated. This is true for insn
2740 that generates a unique label. */
2743 sh_cannot_copy_insn_p (rtx insn
)
2747 if (!reload_completed
|| !flag_pic
)
2750 if (!NONJUMP_INSN_P (insn
))
2752 if (asm_noperands (insn
) >= 0)
2755 pat
= PATTERN (insn
);
2756 if (GET_CODE (pat
) != SET
)
2758 pat
= SET_SRC (pat
);
2760 if (unspec_caller_rtx_p (pat
))
2766 /* Actual number of instructions used to make a shift by N. */
2767 static const char ashiftrt_insns
[] =
2768 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2770 /* Left shift and logical right shift are the same. */
2771 static const char shift_insns
[] =
2772 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2774 /* Individual shift amounts needed to get the above length sequences.
2775 One bit right shifts clobber the T bit, so when possible, put one bit
2776 shifts in the middle of the sequence, so the ends are eligible for
2777 branch delay slots. */
2778 static const short shift_amounts
[32][5] = {
2779 {0}, {1}, {2}, {2, 1},
2780 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2781 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2782 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2783 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2784 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2785 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2786 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2788 /* Likewise, but for shift amounts < 16, up to three highmost bits
2789 might be clobbered. This is typically used when combined with some
2790 kind of sign or zero extension. */
2792 static const char ext_shift_insns
[] =
2793 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2795 static const short ext_shift_amounts
[32][4] = {
2796 {0}, {1}, {2}, {2, 1},
2797 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2798 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2799 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2800 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2801 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2802 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2803 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2805 /* Assuming we have a value that has been sign-extended by at least one bit,
2806 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2807 to shift it by N without data loss, and quicker than by other means? */
2808 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2810 /* This is used in length attributes in sh.md to help compute the length
2811 of arbitrary constant shift instructions. */
2814 shift_insns_rtx (rtx insn
)
2816 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2817 int shift_count
= INTVAL (XEXP (set_src
, 1)) & 31;
2818 enum rtx_code shift_code
= GET_CODE (set_src
);
2823 return ashiftrt_insns
[shift_count
];
2826 return shift_insns
[shift_count
];
2832 /* Return the cost of a shift. */
2839 /* There is no pattern for constant first operand. */
2840 if (CONST_INT_P (XEXP (x
, 0)))
2844 return COSTS_N_INSNS (1);
2846 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
2848 if (GET_MODE (x
) == DImode
2849 && CONST_INT_P (XEXP (x
, 1))
2850 && INTVAL (XEXP (x
, 1)) == 1)
2851 return COSTS_N_INSNS (2);
2853 /* Everything else is invalid, because there is no pattern for it. */
2856 /* If shift by a non constant, then this will be expensive. */
2857 if (!CONST_INT_P (XEXP (x
, 1)))
2858 return COSTS_N_INSNS (SH_DYNAMIC_SHIFT_COST
);
2860 /* Otherwise, return the true cost in instructions. Cope with out of range
2861 shift counts more or less arbitrarily. */
2862 value
= INTVAL (XEXP (x
, 1)) & 31;
2864 if (GET_CODE (x
) == ASHIFTRT
)
2866 int cost
= ashiftrt_insns
[value
];
2867 /* If SH3, then we put the constant in a reg and use shad. */
2868 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
2869 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
2870 return COSTS_N_INSNS (cost
);
2873 return COSTS_N_INSNS (shift_insns
[value
]);
2876 /* Return the cost of an AND/XOR/IOR operation. */
2879 and_xor_ior_costs (rtx x
, int code
)
2883 /* A logical operation with two registers is a single cycle
2885 if (!CONST_INT_P (XEXP (x
, 1)))
2888 i
= INTVAL (XEXP (x
, 1));
2892 if (satisfies_constraint_I10 (XEXP (x
, 1))
2893 || satisfies_constraint_J16 (XEXP (x
, 1)))
2896 return 1 + rtx_cost (XEXP (x
, 1), AND
, 1, !optimize_size
);
2899 /* These constants are single cycle extu.[bw] instructions. */
2900 if ((i
== 0xff || i
== 0xffff) && code
== AND
)
2902 /* Constants that can be used in an instruction as an immediate are
2903 a single cycle, but this requires r0, so make it a little more
2905 if (CONST_OK_FOR_K08 (i
))
2907 /* Constants that can be loaded with a mov immediate need one more cycle.
2908 This case is probably unnecessary. */
2909 if (CONST_OK_FOR_I08 (i
))
2911 /* Any other constant requires an additional 2 cycle pc-relative load.
2912 This case is probably unnecessary. */
2916 /* Return the cost of an addition or a subtraction. */
2921 /* Adding a register is a single cycle insn. */
2922 if (REG_P (XEXP (x
, 1))
2923 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
2926 /* Likewise for small constants. */
2927 if (CONST_INT_P (XEXP (x
, 1))
2928 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
2932 switch (GET_CODE (XEXP (x
, 1)))
2937 return TARGET_SHMEDIA64
? 5 : 3;
2940 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1))))
2942 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1)) >> 16))
2944 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
2952 /* Any other constant requires a 2 cycle pc-relative load plus an
2957 /* Return the cost of a multiply. */
2959 multcosts (rtx x ATTRIBUTE_UNUSED
)
2961 if (sh_multcost
>= 0)
2964 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2965 accept constants. Ideally, we would use a cost of one or two and
2966 add the cost of the operand, but disregard the latter when inside loops
2967 and loop invariant code motion is still to follow.
2968 Using a multiply first and splitting it later if it's a loss
2969 doesn't work because of different sign / zero extension semantics
2970 of multiplies vs. shifts. */
2971 return optimize_size
? 2 : 3;
2975 /* We have a mul insn, so we can never take more than the mul and the
2976 read of the mac reg, but count more because of the latency and extra
2983 /* If we're aiming at small code, then just count the number of
2984 insns in a multiply call sequence. */
2988 /* Otherwise count all the insns in the routine we'd be calling too. */
2992 /* Compute a (partial) cost for rtx X. Return true if the complete
2993 cost has been computed, and false if subexpressions should be
2994 scanned. In either case, *TOTAL contains the cost result. */
2997 sh_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2998 int *total
, bool speed ATTRIBUTE_UNUSED
)
3005 if (INTVAL (x
) == 0)
3007 else if (outer_code
== AND
&& and_operand ((x
), DImode
))
3009 else if ((outer_code
== IOR
|| outer_code
== XOR
3010 || outer_code
== PLUS
)
3011 && CONST_OK_FOR_I10 (INTVAL (x
)))
3013 else if (CONST_OK_FOR_I16 (INTVAL (x
)))
3014 *total
= COSTS_N_INSNS (outer_code
!= SET
);
3015 else if (CONST_OK_FOR_I16 (INTVAL (x
) >> 16))
3016 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 1);
3017 else if (CONST_OK_FOR_I16 ((INTVAL (x
) >> 16) >> 16))
3018 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 2);
3020 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 3);
3023 if (CONST_OK_FOR_I08 (INTVAL (x
)))
3025 else if ((outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
3026 && CONST_OK_FOR_K08 (INTVAL (x
)))
3028 /* prepare_cmp_insn will force costly constants int registers before
3029 the cbranch[sd]i4 patterns can see them, so preserve potentially
3030 interesting ones not covered by I08 above. */
3031 else if (outer_code
== COMPARE
3032 && ((unsigned HOST_WIDE_INT
) INTVAL (x
)
3033 == (unsigned HOST_WIDE_INT
) 0x7fffffff + 1
3034 || INTVAL (x
) == 0x7fffffff
3035 || INTVAL (x
) == 0x80 || INTVAL (x
) == -0x81))
3042 /* An and with a constant compared against zero is
3043 most likely going to be a TST #imm, R0 instruction.
3044 Notice that this does not catch the zero_extract variants from
3046 if (GET_CODE (XEXP (x
, 0)) == AND
3047 && CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 0)
3058 if (TARGET_SHMEDIA64
)
3059 *total
= COSTS_N_INSNS (4);
3060 else if (TARGET_SHMEDIA32
)
3061 *total
= COSTS_N_INSNS (2);
3068 *total
= COSTS_N_INSNS (4);
3069 /* prepare_cmp_insn will force costly constants int registers before
3070 the cbranchdi4 pattern can see them, so preserve potentially
3071 interesting ones. */
3072 else if (outer_code
== COMPARE
&& GET_MODE (x
) == DImode
)
3078 if (x
== CONST0_RTX (GET_MODE (x
)))
3080 else if (sh_1el_vec (x
, VOIDmode
))
3081 *total
= outer_code
!= SET
;
3082 if (sh_rep_vec (x
, VOIDmode
))
3083 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3084 + (outer_code
!= SET
));
3085 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3090 *total
= COSTS_N_INSNS (addsubcosts (x
));
3096 *total
= COSTS_N_INSNS (and_xor_ior_costs (x
, code
));
3100 *total
= COSTS_N_INSNS (multcosts (x
));
3106 *total
= shiftcosts (x
);
3113 *total
= COSTS_N_INSNS (20);
3117 if (sh_1el_vec (x
, VOIDmode
))
3118 *total
= outer_code
!= SET
;
3119 if (sh_rep_vec (x
, VOIDmode
))
3120 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3121 + (outer_code
!= SET
));
3122 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3135 /* Determine the size of the fundamental move insn that will be used
3136 for the specified mode. */
3139 mov_insn_size (enum machine_mode mode
, bool consider_sh2a
)
3141 const int mode_sz
= GET_MODE_SIZE (mode
);
3143 if ((consider_sh2a
&& TARGET_SH2A_DOUBLE
&& mode
== DFmode
)
3144 || (TARGET_FMOVD
&& mode
== DFmode
))
3148 /* The max. available mode for actual move insns is SImode.
3149 Larger accesses will be split into multiple loads/stores. */
3150 const int max_mov_sz
= GET_MODE_SIZE (SImode
);
3151 return mode_sz
>= max_mov_sz
? max_mov_sz
: mode_sz
;
3155 /* Determine the maximum possible displacement for a move insn for the
3159 max_mov_insn_displacement (enum machine_mode mode
, bool consider_sh2a
)
3161 /* The 4 byte displacement move insns are the same as the 2 byte
3162 versions but take a 12 bit displacement. All we need to do is to
3163 scale the max. displacement value accordingly. */
3164 const int disp_scale
= consider_sh2a
? (4095 / 15) : 1;
3166 /* FIXME: HImode with displacement addressing is not supported yet.
3167 Make it purposefully fail for now. */
3171 /* SH2A supports FPU move insns with 12 bit displacements.
3172 Other variants to do not support any kind of displacements for
3174 if (! consider_sh2a
&& TARGET_FPU_ANY
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3178 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3179 const int mode_sz
= GET_MODE_SIZE (mode
);
3180 int r
= 15 * mov_insn_sz
* disp_scale
;
3182 /* If the mov insn will be split into multiple loads/stores, the
3183 maximum possible displacement is a bit smaller. */
3184 if (mode_sz
> mov_insn_sz
)
3185 r
-= mode_sz
- mov_insn_sz
;
3190 /* Determine the alignment mask for a move insn of the
3194 mov_insn_alignment_mask (enum machine_mode mode
, bool consider_sh2a
)
3196 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3197 return mov_insn_sz
> 0 ? (mov_insn_sz
- 1) : 0;
3200 /* Compute the cost of an address. */
3203 sh_address_cost (rtx x
, bool speed ATTRIBUTE_UNUSED
)
3205 /* 'reg + disp' addressing. */
3206 if (DISP_ADDR_P (x
))
3208 const HOST_WIDE_INT offset
= DISP_ADDR_OFFSET (x
);
3209 const enum machine_mode mode
= GET_MODE (x
);
3211 /* The displacement would fit into a 2 byte move insn. */
3212 if (offset
> 0 && offset
<= max_mov_insn_displacement (mode
, false))
3215 /* The displacement would fit into a 4 byte move insn (SH2A). */
3217 && offset
> 0 && offset
<= max_mov_insn_displacement (mode
, true))
3220 /* The displacement is probably out of range and will require extra
3225 /* 'reg + reg' addressing. Account a slightly higher cost because of
3226 increased pressure on R0. */
3227 if (GET_CODE (x
) == PLUS
&& ! CONSTANT_P (XEXP (x
, 1))
3228 && ! TARGET_SHMEDIA
)
3234 /* Code to expand a shift. */
3237 gen_ashift (int type
, int n
, rtx reg
)
3239 /* Negative values here come from the shift_amounts array. */
3252 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
3256 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
3258 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
3261 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
3266 /* Same for HImode */
3269 gen_ashift_hi (int type
, int n
, rtx reg
)
3271 /* Negative values here come from the shift_amounts array. */
3285 /* We don't have HImode right shift operations because using the
3286 ordinary 32 bit shift instructions for that doesn't generate proper
3287 zero/sign extension.
3288 gen_ashift_hi is only called in contexts where we know that the
3289 sign extension works out correctly. */
3292 if (GET_CODE (reg
) == SUBREG
)
3294 offset
= SUBREG_BYTE (reg
);
3295 reg
= SUBREG_REG (reg
);
3297 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
3301 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
3306 /* Output RTL to split a constant shift into its component SH constant
3307 shift instructions. */
3310 gen_shifty_op (int code
, rtx
*operands
)
3312 int value
= INTVAL (operands
[2]);
3315 /* Truncate the shift count in case it is out of bounds. */
3320 if (code
== LSHIFTRT
)
3322 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
3323 emit_insn (gen_movt (operands
[0]));
3326 else if (code
== ASHIFT
)
3328 /* There is a two instruction sequence for 31 bit left shifts,
3329 but it requires r0. */
3330 if (REG_P (operands
[0]) && REGNO (operands
[0]) == 0)
3332 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
3333 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
3338 else if (value
== 0)
3340 /* This can happen even when optimizing, if there were subregs before
3341 reload. Don't output a nop here, as this is never optimized away;
3342 use a no-op move instead. */
3343 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[0]));
3347 max
= shift_insns
[value
];
3348 for (i
= 0; i
< max
; i
++)
3349 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
3352 /* Same as above, but optimized for values where the topmost bits don't
3356 gen_shifty_hi_op (int code
, rtx
*operands
)
3358 int value
= INTVAL (operands
[2]);
3360 void (*gen_fun
) (int, int, rtx
);
3362 /* This operation is used by and_shl for SImode values with a few
3363 high bits known to be cleared. */
3367 emit_insn (gen_nop ());
3371 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
3374 max
= ext_shift_insns
[value
];
3375 for (i
= 0; i
< max
; i
++)
3376 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
3379 /* When shifting right, emit the shifts in reverse order, so that
3380 solitary negative values come first. */
3381 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
3382 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
3385 /* Output RTL for an arithmetic right shift. */
3387 /* ??? Rewrite to use super-optimizer sequences. */
3390 expand_ashiftrt (rtx
*operands
)
3396 if (TARGET_SH3
|| TARGET_SH2A
)
3398 if (!CONST_INT_P (operands
[2]))
3400 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
3401 emit_insn (gen_negsi2 (count
, count
));
3402 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
3405 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
3406 > 1 + SH_DYNAMIC_SHIFT_COST
)
3409 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
3410 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
3414 if (!CONST_INT_P (operands
[2]))
3417 value
= INTVAL (operands
[2]) & 31;
3421 /* If we are called from abs expansion, arrange things so that we
3422 we can use a single MT instruction that doesn't clobber the source,
3423 if LICM can hoist out the load of the constant zero. */
3424 if (currently_expanding_to_rtl
)
3426 emit_insn (gen_cmpgtsi_t (force_reg (SImode
, CONST0_RTX (SImode
)),
3428 emit_insn (gen_mov_neg_si_t (operands
[0]));
3431 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
3434 else if (value
>= 16 && value
<= 19)
3436 wrk
= gen_reg_rtx (SImode
);
3437 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
3440 gen_ashift (ASHIFTRT
, 1, wrk
);
3441 emit_move_insn (operands
[0], wrk
);
3444 /* Expand a short sequence inline, longer call a magic routine. */
3445 else if (value
<= 5)
3447 wrk
= gen_reg_rtx (SImode
);
3448 emit_move_insn (wrk
, operands
[1]);
3450 gen_ashift (ASHIFTRT
, 1, wrk
);
3451 emit_move_insn (operands
[0], wrk
);
3455 wrk
= gen_reg_rtx (Pmode
);
3457 /* Load the value into an arg reg and call a helper. */
3458 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
3459 sprintf (func
, "__ashiftrt_r4_%d", value
);
3460 function_symbol (wrk
, func
, SFUNC_STATIC
);
3461 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
3462 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
3467 sh_dynamicalize_shift_p (rtx count
)
3469 return shift_insns
[INTVAL (count
) & 31] > 1 + SH_DYNAMIC_SHIFT_COST
;
3472 /* Try to find a good way to implement the combiner pattern
3473 [(set (match_operand:SI 0 "register_operand" "r")
3474 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3475 (match_operand:SI 2 "const_int_operand" "n"))
3476 (match_operand:SI 3 "const_int_operand" "n"))) .
3477 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3478 return 0 for simple right / left or left/right shift combination.
3479 return 1 for a combination of shifts with zero_extend.
3480 return 2 for a combination of shifts with an AND that needs r0.
3481 return 3 for a combination of shifts with an AND that needs an extra
3482 scratch register, when the three highmost bits of the AND mask are clear.
3483 return 4 for a combination of shifts with an AND that needs an extra
3484 scratch register, when any of the three highmost bits of the AND mask
3486 If ATTRP is set, store an initial right shift width in ATTRP[0],
3487 and the instruction length in ATTRP[1] . These values are not valid
3489 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3490 shift_amounts for the last shift value that is to be used before the
3493 shl_and_kind (rtx left_rtx
, rtx mask_rtx
, int *attrp
)
3495 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
3496 int left
= INTVAL (left_rtx
), right
;
3498 int cost
, best_cost
= 10000;
3499 int best_right
= 0, best_len
= 0;
3503 if (left
< 0 || left
> 31)
3505 if (CONST_INT_P (mask_rtx
))
3506 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
3508 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
3509 /* Can this be expressed as a right shift / left shift pair? */
3510 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
3511 right
= exact_log2 (lsb
);
3512 mask2
= ~(mask
+ lsb
- 1);
3513 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
3514 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3516 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
3517 /* mask has no trailing zeroes <==> ! right */
3518 else if (! right
&& mask2
== ~(lsb2
- 1))
3520 int late_right
= exact_log2 (lsb2
);
3521 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
3523 /* Try to use zero extend. */
3524 if (mask2
== ~(lsb2
- 1))
3528 for (width
= 8; width
<= 16; width
+= 8)
3530 /* Can we zero-extend right away? */
3531 if (lsb2
== (unsigned HOST_WIDE_INT
) 1 << width
)
3534 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
3535 if (cost
< best_cost
)
3546 /* ??? Could try to put zero extend into initial right shift,
3547 or even shift a bit left before the right shift. */
3548 /* Determine value of first part of left shift, to get to the
3549 zero extend cut-off point. */
3550 first
= width
- exact_log2 (lsb2
) + right
;
3551 if (first
>= 0 && right
+ left
- first
>= 0)
3553 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
3554 + ext_shift_insns
[right
+ left
- first
];
3555 if (cost
< best_cost
)
3567 /* Try to use r0 AND pattern */
3568 for (i
= 0; i
<= 2; i
++)
3572 if (! CONST_OK_FOR_K08 (mask
>> i
))
3574 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
3575 if (cost
< best_cost
)
3580 best_len
= cost
- 1;
3583 /* Try to use a scratch register to hold the AND operand. */
3584 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
) 3 << 30)) == 0;
3585 for (i
= 0; i
<= 2; i
++)
3589 cost
= (i
!= 0) + (CONST_OK_FOR_I08 (mask
>> i
) ? 2 : 3)
3590 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
3591 if (cost
< best_cost
)
3596 best_len
= cost
- 1 - ! CONST_OK_FOR_I08 (mask
>> i
);
3602 attrp
[0] = best_right
;
3603 attrp
[1] = best_len
;
3608 /* This is used in length attributes of the unnamed instructions
3609 corresponding to shl_and_kind return values of 1 and 2. */
3611 shl_and_length (rtx insn
)
3613 rtx set_src
, left_rtx
, mask_rtx
;
3616 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
3617 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
3618 mask_rtx
= XEXP (set_src
, 1);
3619 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
3620 return attributes
[1];
3623 /* This is used in length attribute of the and_shl_scratch instruction. */
3626 shl_and_scr_length (rtx insn
)
3628 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
3629 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1)) & 31];
3630 rtx op
= XEXP (set_src
, 0);
3631 len
+= shift_insns
[INTVAL (XEXP (op
, 1)) & 31] + 1;
3632 op
= XEXP (XEXP (op
, 0), 0);
3633 return len
+ shift_insns
[INTVAL (XEXP (op
, 1)) & 31];
3636 /* Generate rtl for instructions for which shl_and_kind advised a particular
3637 method of generating them, i.e. returned zero. */
3640 gen_shl_and (rtx dest
, rtx left_rtx
, rtx mask_rtx
, rtx source
)
3643 unsigned HOST_WIDE_INT mask
;
3644 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
3645 int right
, total_shift
;
3646 void (*shift_gen_fun
) (int, rtx
*) = gen_shifty_hi_op
;
3648 right
= attributes
[0];
3649 total_shift
= INTVAL (left_rtx
) + right
;
3650 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
3657 int first
= attributes
[2];
3662 emit_insn ((mask
<< right
) <= 0xff
3663 ? gen_zero_extendqisi2 (dest
,
3664 gen_lowpart (QImode
, source
))
3665 : gen_zero_extendhisi2 (dest
,
3666 gen_lowpart (HImode
, source
)));
3670 emit_insn (gen_movsi (dest
, source
));
3674 operands
[2] = GEN_INT (right
);
3675 gen_shifty_hi_op (LSHIFTRT
, operands
);
3679 operands
[2] = GEN_INT (first
);
3680 gen_shifty_hi_op (ASHIFT
, operands
);
3681 total_shift
-= first
;
3685 emit_insn (mask
<= 0xff
3686 ? gen_zero_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
3687 : gen_zero_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
3688 if (total_shift
> 0)
3690 operands
[2] = GEN_INT (total_shift
);
3691 gen_shifty_hi_op (ASHIFT
, operands
);
3696 shift_gen_fun
= gen_shifty_op
;
3698 /* If the topmost bit that matters is set, set the topmost bits
3699 that don't matter. This way, we might be able to get a shorter
3701 if (mask
& ((HOST_WIDE_INT
) 1 << (31 - total_shift
)))
3702 mask
|= (HOST_WIDE_INT
) ~0 << (31 - total_shift
);
3704 /* Don't expand fine-grained when combining, because that will
3705 make the pattern fail. */
3706 if (currently_expanding_to_rtl
3707 || reload_in_progress
|| reload_completed
)
3711 /* Cases 3 and 4 should be handled by this split
3712 only while combining */
3713 gcc_assert (kind
<= 2);
3716 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
3719 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
3724 operands
[2] = GEN_INT (total_shift
);
3725 shift_gen_fun (ASHIFT
, operands
);
3732 if (kind
!= 4 && total_shift
< 16)
3734 neg
= -ext_shift_amounts
[total_shift
][1];
3736 neg
-= ext_shift_amounts
[total_shift
][2];
3740 emit_insn (gen_and_shl_scratch (dest
, source
,
3743 GEN_INT (total_shift
+ neg
),
3745 emit_insn (gen_movsi (dest
, dest
));
3752 /* Try to find a good way to implement the combiner pattern
3753 [(set (match_operand:SI 0 "register_operand" "=r")
3754 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3755 (match_operand:SI 2 "const_int_operand" "n")
3756 (match_operand:SI 3 "const_int_operand" "n")
3758 (clobber (reg:SI T_REG))]
3759 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3760 return 0 for simple left / right shift combination.
3761 return 1 for left shift / 8 bit sign extend / left shift.
3762 return 2 for left shift / 16 bit sign extend / left shift.
3763 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3764 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3765 return 5 for left shift / 16 bit sign extend / right shift
3766 return 6 for < 8 bit sign extend / left shift.
3767 return 7 for < 8 bit sign extend / left shift / single right shift.
3768 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3771 shl_sext_kind (rtx left_rtx
, rtx size_rtx
, int *costp
)
3773 int left
, size
, insize
, ext
;
3774 int cost
= 0, best_cost
;
3777 left
= INTVAL (left_rtx
);
3778 size
= INTVAL (size_rtx
);
3779 insize
= size
- left
;
3780 gcc_assert (insize
> 0);
3781 /* Default to left / right shift. */
3783 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
3786 /* 16 bit shift / sign extend / 16 bit shift */
3787 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
3788 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3789 below, by alternative 3 or something even better. */
3790 if (cost
< best_cost
)
3796 /* Try a plain sign extend between two shifts. */
3797 for (ext
= 16; ext
>= insize
; ext
-= 8)
3801 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
3802 if (cost
< best_cost
)
3804 kind
= ext
/ (unsigned) 8;
3808 /* Check if we can do a sloppy shift with a final signed shift
3809 restoring the sign. */
3810 if (EXT_SHIFT_SIGNED (size
- ext
))
3811 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
3812 /* If not, maybe it's still cheaper to do the second shift sloppy,
3813 and do a final sign extend? */
3814 else if (size
<= 16)
3815 cost
= ext_shift_insns
[ext
- insize
] + 1
3816 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
3819 if (cost
< best_cost
)
3821 kind
= ext
/ (unsigned) 8 + 2;
3825 /* Check if we can sign extend in r0 */
3828 cost
= 3 + shift_insns
[left
];
3829 if (cost
< best_cost
)
3834 /* Try the same with a final signed shift. */
3837 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
3838 if (cost
< best_cost
)
3845 if (TARGET_SH3
|| TARGET_SH2A
)
3847 /* Try to use a dynamic shift. */
3848 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
3849 if (cost
< best_cost
)
3860 /* Function to be used in the length attribute of the instructions
3861 implementing this pattern. */
3864 shl_sext_length (rtx insn
)
3866 rtx set_src
, left_rtx
, size_rtx
;
3869 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
3870 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
3871 size_rtx
= XEXP (set_src
, 1);
3872 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
3876 /* Generate rtl for this pattern */
3879 gen_shl_sext (rtx dest
, rtx left_rtx
, rtx size_rtx
, rtx source
)
3882 int left
, size
, insize
, cost
;
3885 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
3886 left
= INTVAL (left_rtx
);
3887 size
= INTVAL (size_rtx
);
3888 insize
= size
- left
;
3896 int ext
= kind
& 1 ? 8 : 16;
3897 int shift2
= size
- ext
;
3899 /* Don't expand fine-grained when combining, because that will
3900 make the pattern fail. */
3901 if (! currently_expanding_to_rtl
3902 && ! reload_in_progress
&& ! reload_completed
)
3904 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
3905 emit_insn (gen_movsi (dest
, source
));
3909 emit_insn (gen_movsi (dest
, source
));
3913 operands
[2] = GEN_INT (ext
- insize
);
3914 gen_shifty_hi_op (ASHIFT
, operands
);
3917 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
3918 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
3923 operands
[2] = GEN_INT (shift2
);
3924 gen_shifty_op (ASHIFT
, operands
);
3931 if (EXT_SHIFT_SIGNED (shift2
))
3933 operands
[2] = GEN_INT (shift2
+ 1);
3934 gen_shifty_op (ASHIFT
, operands
);
3935 operands
[2] = const1_rtx
;
3936 gen_shifty_op (ASHIFTRT
, operands
);
3939 operands
[2] = GEN_INT (shift2
);
3940 gen_shifty_hi_op (ASHIFT
, operands
);
3944 operands
[2] = GEN_INT (-shift2
);
3945 gen_shifty_hi_op (LSHIFTRT
, operands
);
3947 emit_insn (size
<= 8
3948 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
3949 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
3956 if (! currently_expanding_to_rtl
3957 && ! reload_in_progress
&& ! reload_completed
)
3958 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
3962 operands
[2] = GEN_INT (16 - insize
);
3963 gen_shifty_hi_op (ASHIFT
, operands
);
3964 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
3966 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3968 gen_ashift (ASHIFTRT
, 1, dest
);
3973 /* Don't expand fine-grained when combining, because that will
3974 make the pattern fail. */
3975 if (! currently_expanding_to_rtl
3976 && ! reload_in_progress
&& ! reload_completed
)
3978 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
3979 emit_insn (gen_movsi (dest
, source
));
3982 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
3983 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
3984 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
3986 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
3987 gen_shifty_op (ASHIFT
, operands
);
3989 emit_insn (gen_ashrsi3_k (dest
, dest
, const1_rtx
));
3997 /* Prefix a symbol_ref name with "datalabel". */
4000 gen_datalabel_ref (rtx sym
)
4004 if (GET_CODE (sym
) == LABEL_REF
)
4005 return gen_rtx_CONST (GET_MODE (sym
),
4006 gen_rtx_UNSPEC (GET_MODE (sym
),
4010 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
);
4012 str
= XSTR (sym
, 0);
4013 /* Share all SYMBOL_REF strings with the same value - that is important
4015 str
= IDENTIFIER_POINTER (get_identifier (str
));
4016 XSTR (sym
, 0) = str
;
4022 static alloc_pool label_ref_list_pool
;
4024 typedef struct label_ref_list_d
4027 struct label_ref_list_d
*next
;
4028 } *label_ref_list_t
;
4030 /* The SH cannot load a large constant into a register, constants have to
4031 come from a pc relative load. The reference of a pc relative load
4032 instruction must be less than 1k in front of the instruction. This
4033 means that we often have to dump a constant inside a function, and
4034 generate code to branch around it.
4036 It is important to minimize this, since the branches will slow things
4037 down and make things bigger.
4039 Worst case code looks like:
4057 We fix this by performing a scan before scheduling, which notices which
4058 instructions need to have their operands fetched from the constant table
4059 and builds the table.
4063 scan, find an instruction which needs a pcrel move. Look forward, find the
4064 last barrier which is within MAX_COUNT bytes of the requirement.
4065 If there isn't one, make one. Process all the instructions between
4066 the find and the barrier.
4068 In the above example, we can tell that L3 is within 1k of L1, so
4069 the first move can be shrunk from the 3 insn+constant sequence into
4070 just 1 insn, and the constant moved to L3 to make:
4081 Then the second move becomes the target for the shortening process. */
4085 rtx value
; /* Value in table. */
4086 rtx label
; /* Label of value. */
4087 label_ref_list_t wend
; /* End of window. */
4088 enum machine_mode mode
; /* Mode of value. */
4090 /* True if this constant is accessed as part of a post-increment
4091 sequence. Note that HImode constants are never accessed in this way. */
4092 bool part_of_sequence_p
;
4095 /* The maximum number of constants that can fit into one pool, since
4096 constants in the range 0..510 are at least 2 bytes long, and in the
4097 range from there to 1018 at least 4 bytes. */
4099 #define MAX_POOL_SIZE 372
4100 static pool_node pool_vector
[MAX_POOL_SIZE
];
4101 static int pool_size
;
4102 static rtx pool_window_label
;
4103 static int pool_window_last
;
4105 static int max_labelno_before_reorg
;
4107 /* ??? If we need a constant in HImode which is the truncated value of a
4108 constant we need in SImode, we could combine the two entries thus saving
4109 two bytes. Is this common enough to be worth the effort of implementing
4112 /* ??? This stuff should be done at the same time that we shorten branches.
4113 As it is now, we must assume that all branches are the maximum size, and
4114 this causes us to almost always output constant pools sooner than
4117 /* Add a constant to the pool and return its label. */
4120 add_constant (rtx x
, enum machine_mode mode
, rtx last_value
)
4124 label_ref_list_t ref
, newref
;
4126 /* First see if we've already got it. */
4127 for (i
= 0; i
< pool_size
; i
++)
4129 if (x
->code
== pool_vector
[i
].value
->code
4130 && mode
== pool_vector
[i
].mode
)
4132 if (x
->code
== CODE_LABEL
)
4134 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
4137 if (rtx_equal_p (x
, pool_vector
[i
].value
))
4142 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
4144 new_rtx
= gen_label_rtx ();
4145 LABEL_REFS (new_rtx
) = pool_vector
[i
].label
;
4146 pool_vector
[i
].label
= lab
= new_rtx
;
4148 if (lab
&& pool_window_label
)
4150 newref
= (label_ref_list_t
) pool_alloc (label_ref_list_pool
);
4151 newref
->label
= pool_window_label
;
4152 ref
= pool_vector
[pool_window_last
].wend
;
4154 pool_vector
[pool_window_last
].wend
= newref
;
4157 pool_window_label
= new_rtx
;
4158 pool_window_last
= i
;
4164 /* Need a new one. */
4165 pool_vector
[pool_size
].value
= x
;
4166 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
4169 pool_vector
[pool_size
- 1].part_of_sequence_p
= true;
4172 lab
= gen_label_rtx ();
4173 pool_vector
[pool_size
].mode
= mode
;
4174 pool_vector
[pool_size
].label
= lab
;
4175 pool_vector
[pool_size
].wend
= NULL
;
4176 pool_vector
[pool_size
].part_of_sequence_p
= (lab
== 0);
4177 if (lab
&& pool_window_label
)
4179 newref
= (label_ref_list_t
) pool_alloc (label_ref_list_pool
);
4180 newref
->label
= pool_window_label
;
4181 ref
= pool_vector
[pool_window_last
].wend
;
4183 pool_vector
[pool_window_last
].wend
= newref
;
4186 pool_window_label
= lab
;
4187 pool_window_last
= pool_size
;
4192 /* Output the literal table. START, if nonzero, is the first instruction
4193 this table is needed for, and also indicates that there is at least one
4194 casesi_worker_2 instruction; We have to emit the operand3 labels from
4195 these insns at a 4-byte aligned position. BARRIER is the barrier
4196 after which we are to place the table. */
4199 dump_table (rtx start
, rtx barrier
)
4205 label_ref_list_t ref
;
4208 /* Do two passes, first time dump out the HI sized constants. */
4210 for (i
= 0; i
< pool_size
; i
++)
4212 pool_node
*p
= &pool_vector
[i
];
4214 if (p
->mode
== HImode
)
4218 scan
= emit_insn_after (gen_align_2 (), scan
);
4221 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4222 scan
= emit_label_after (lab
, scan
);
4223 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
4225 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4228 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
4231 else if (p
->mode
== DFmode
)
4239 scan
= emit_insn_after (gen_align_4 (), scan
);
4241 for (; start
!= barrier
; start
= NEXT_INSN (start
))
4242 if (NONJUMP_INSN_P (start
)
4243 && recog_memoized (start
) == CODE_FOR_casesi_worker_2
)
4245 rtx src
= SET_SRC (XVECEXP (PATTERN (start
), 0, 0));
4246 rtx lab
= XEXP (XVECEXP (src
, 0, 3), 0);
4248 scan
= emit_label_after (lab
, scan
);
4251 if (TARGET_FMOVD
&& TARGET_ALIGN_DOUBLE
&& have_df
)
4253 rtx align_insn
= NULL_RTX
;
4255 scan
= emit_label_after (gen_label_rtx (), scan
);
4256 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4259 for (i
= 0; i
< pool_size
; i
++)
4261 pool_node
*p
= &pool_vector
[i
];
4269 if (align_insn
&& !p
->part_of_sequence_p
)
4271 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4272 emit_label_before (lab
, align_insn
);
4273 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
4275 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4278 emit_insn_before (gen_consttable_window_end (lab
),
4281 delete_insn (align_insn
);
4282 align_insn
= NULL_RTX
;
4287 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4288 scan
= emit_label_after (lab
, scan
);
4289 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
4291 need_align
= ! need_align
;
4297 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4302 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4303 scan
= emit_label_after (lab
, scan
);
4304 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4311 if (p
->mode
!= HImode
)
4313 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4316 scan
= emit_insn_after (gen_consttable_window_end (lab
),
4325 for (i
= 0; i
< pool_size
; i
++)
4327 pool_node
*p
= &pool_vector
[i
];
4338 scan
= emit_label_after (gen_label_rtx (), scan
);
4339 scan
= emit_insn_after (gen_align_4 (), scan
);
4341 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4342 scan
= emit_label_after (lab
, scan
);
4343 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
4351 scan
= emit_label_after (gen_label_rtx (), scan
);
4352 scan
= emit_insn_after (gen_align_4 (), scan
);
4354 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4355 scan
= emit_label_after (lab
, scan
);
4356 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4363 if (p
->mode
!= HImode
)
4365 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4368 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
4373 scan
= emit_insn_after (gen_consttable_end (), scan
);
4374 scan
= emit_barrier_after (scan
);
4376 pool_window_label
= NULL_RTX
;
4377 pool_window_last
= 0;
4380 /* Return nonzero if constant would be an ok source for a
4381 mov.w instead of a mov.l. */
4386 return (CONST_INT_P (src
)
4387 && INTVAL (src
) >= -32768
4388 && INTVAL (src
) <= 32767);
4391 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4393 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4395 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4396 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4397 need to fix it if the input value is CONST_OK_FOR_I08. */
4400 broken_move (rtx insn
)
4402 if (NONJUMP_INSN_P (insn
))
4404 rtx pat
= PATTERN (insn
);
4405 if (GET_CODE (pat
) == PARALLEL
)
4406 pat
= XVECEXP (pat
, 0, 0);
4407 if (GET_CODE (pat
) == SET
4408 /* We can load any 8-bit value if we don't care what the high
4409 order bits end up as. */
4410 && GET_MODE (SET_DEST (pat
)) != QImode
4411 && (CONSTANT_P (SET_SRC (pat
))
4412 /* Match mova_const. */
4413 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
4414 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
4415 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
4417 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
4418 && (fp_zero_operand (SET_SRC (pat
))
4419 || fp_one_operand (SET_SRC (pat
)))
4420 /* In general we don't know the current setting of fpscr, so disable fldi.
4421 There is an exception if this was a register-register move
4422 before reload - and hence it was ascertained that we have
4423 single precision setting - and in a post-reload optimization
4424 we changed this to do a constant load. In that case
4425 we don't have an r0 clobber, hence we must use fldi. */
4427 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
4429 && REG_P (SET_DEST (pat
))
4430 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
4432 && GET_MODE (SET_DEST (pat
)) == SImode
4433 && (satisfies_constraint_I20 (SET_SRC (pat
))
4434 || satisfies_constraint_I28 (SET_SRC (pat
))))
4435 && ! satisfies_constraint_I08 (SET_SRC (pat
)))
4445 return (NONJUMP_INSN_P (insn
)
4446 && GET_CODE (PATTERN (insn
)) == SET
4447 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
4448 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
4449 /* Don't match mova_const. */
4450 && GET_CODE (MOVA_LABELREF (insn
)) == LABEL_REF
);
4453 /* Fix up a mova from a switch that went out of range. */
4455 fixup_mova (rtx mova
)
4457 PUT_MODE (XEXP (MOVA_LABELREF (mova
), 0), QImode
);
4460 SET_SRC (PATTERN (mova
)) = MOVA_LABELREF (mova
);
4461 INSN_CODE (mova
) = -1;
4466 rtx lab
= gen_label_rtx ();
4467 rtx wpat
, wpat0
, wpat1
, wsrc
, target
, base
, diff
;
4471 worker
= NEXT_INSN (worker
);
4473 && !LABEL_P (worker
)
4474 && !JUMP_P (worker
));
4475 } while (NOTE_P (worker
)
4476 || recog_memoized (worker
) != CODE_FOR_casesi_worker_1
);
4477 wpat
= PATTERN (worker
);
4478 wpat0
= XVECEXP (wpat
, 0, 0);
4479 wpat1
= XVECEXP (wpat
, 0, 1);
4480 wsrc
= SET_SRC (wpat0
);
4481 PATTERN (worker
) = (gen_casesi_worker_2
4482 (SET_DEST (wpat0
), XVECEXP (wsrc
, 0, 1),
4483 XEXP (XVECEXP (wsrc
, 0, 2), 0), lab
,
4485 INSN_CODE (worker
) = -1;
4486 target
= XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
4487 base
= gen_rtx_LABEL_REF (Pmode
, lab
);
4488 diff
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, target
, base
), UNSPEC_SYMOFF
);
4489 SET_SRC (PATTERN (mova
)) = gen_rtx_CONST (Pmode
, diff
);
4490 INSN_CODE (mova
) = -1;
4494 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4495 *num_mova, and check if the new mova is not nested within the first one.
4496 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4497 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4499 untangle_mova (int *num_mova
, rtx
*first_mova
, rtx new_mova
)
4501 int n_addr
= 0; /* Initialization to shut up spurious warning. */
4502 int f_target
, n_target
= 0; /* Likewise. */
4506 /* If NEW_MOVA has no address yet, it will be handled later. */
4507 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova
))
4510 n_addr
= INSN_ADDRESSES (INSN_UID (new_mova
));
4511 n_target
= INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova
), 0)));
4512 if (n_addr
> n_target
|| n_addr
+ 1022 < n_target
)
4514 /* Change the mova into a load.
4515 broken_move will then return true for it. */
4516 fixup_mova (new_mova
);
4522 *first_mova
= new_mova
;
4527 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova
), 0))))
4532 if (f_target
- INSN_ADDRESSES (INSN_UID (*first_mova
))
4533 > n_target
- n_addr
)
4535 fixup_mova (*first_mova
);
4540 fixup_mova (new_mova
);
4545 /* Find the last barrier from insn FROM which is close enough to hold the
4546 constant pool. If we can't find one, then create one near the end of
4550 find_barrier (int num_mova
, rtx mova
, rtx from
)
4559 int leading_mova
= num_mova
;
4560 rtx barrier_before_mova
= 0, found_barrier
= 0, good_barrier
= 0;
4564 rtx last_got
= NULL_RTX
;
4565 rtx last_symoff
= NULL_RTX
;
4567 /* For HImode: range is 510, add 4 because pc counts from address of
4568 second instruction after this one, subtract 2 for the jump instruction
4569 that we may need to emit before the table, subtract 2 for the instruction
4570 that fills the jump delay slot (in very rare cases, reorg will take an
4571 instruction from after the constant pool or will leave the delay slot
4572 empty). This gives 510.
4573 For SImode: range is 1020, add 4 because pc counts from address of
4574 second instruction after this one, subtract 2 in case pc is 2 byte
4575 aligned, subtract 2 for the jump instruction that we may need to emit
4576 before the table, subtract 2 for the instruction that fills the jump
4577 delay slot. This gives 1018. */
4579 /* The branch will always be shortened now that the reference address for
4580 forward branches is the successor address, thus we need no longer make
4581 adjustments to the [sh]i_limit for -O0. */
4586 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
4588 int inc
= get_attr_length (from
);
4591 /* If this is a label that existed at the time of the compute_alignments
4592 call, determine the alignment. N.B. When find_barrier recurses for
4593 an out-of-reach mova, we might see labels at the start of previously
4594 inserted constant tables. */
4596 && CODE_LABEL_NUMBER (from
) <= max_labelno_before_reorg
)
4599 new_align
= 1 << label_to_alignment (from
);
4600 else if (BARRIER_P (prev_nonnote_insn (from
)))
4601 new_align
= 1 << barrier_align (from
);
4606 /* In case we are scanning a constant table because of recursion, check
4607 for explicit alignments. If the table is long, we might be forced
4608 to emit the new table in front of it; the length of the alignment
4609 might be the last straw. */
4610 else if (NONJUMP_INSN_P (from
)
4611 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
4612 && XINT (PATTERN (from
), 1) == UNSPECV_ALIGN
)
4613 new_align
= INTVAL (XVECEXP (PATTERN (from
), 0, 0));
4614 /* When we find the end of a constant table, paste the new constant
4615 at the end. That is better than putting it in front because
4616 this way, we don't need extra alignment for adding a 4-byte-aligned
4617 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4618 else if (NONJUMP_INSN_P (from
)
4619 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
4620 && XINT (PATTERN (from
), 1) == UNSPECV_CONST_END
)
4623 if (BARRIER_P (from
))
4627 found_barrier
= from
;
4629 /* If we are at the end of the function, or in front of an alignment
4630 instruction, we need not insert an extra alignment. We prefer
4631 this kind of barrier. */
4632 if (barrier_align (from
) > 2)
4633 good_barrier
= from
;
4635 /* If we are at the end of a hot/cold block, dump the constants
4637 next
= NEXT_INSN (from
);
4640 && NOTE_KIND (next
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
4644 if (broken_move (from
))
4647 enum machine_mode mode
;
4649 pat
= PATTERN (from
);
4650 if (GET_CODE (pat
) == PARALLEL
)
4651 pat
= XVECEXP (pat
, 0, 0);
4652 src
= SET_SRC (pat
);
4653 dst
= SET_DEST (pat
);
4654 mode
= GET_MODE (dst
);
4656 /* GOT pcrelat setting comes in pair of
4659 instructions. (plus add r0,r12).
4660 Remember if we see one without the other. */
4661 if (GET_CODE (src
) == UNSPEC
&& PIC_ADDR_P (XVECEXP (src
, 0, 0)))
4662 last_got
= last_got
? NULL_RTX
: from
;
4663 else if (PIC_ADDR_P (src
))
4664 last_got
= last_got
? NULL_RTX
: from
;
4666 /* We must explicitly check the mode, because sometimes the
4667 front end will generate code to load unsigned constants into
4668 HImode targets without properly sign extending them. */
4670 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
4673 /* We put the short constants before the long constants, so
4674 we must count the length of short constants in the range
4675 for the long constants. */
4676 /* ??? This isn't optimal, but is easy to do. */
4681 /* We dump DF/DI constants before SF/SI ones, because
4682 the limit is the same, but the alignment requirements
4683 are higher. We may waste up to 4 additional bytes
4684 for alignment, and the DF/DI constant may have
4685 another SF/SI constant placed before it. */
4686 if (TARGET_SHCOMPACT
4688 && (mode
== DFmode
|| mode
== DImode
))
4693 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
4695 if (found_si
> count_si
)
4696 count_si
= found_si
;
4697 found_si
+= GET_MODE_SIZE (mode
);
4699 si_limit
-= GET_MODE_SIZE (mode
);
4705 switch (untangle_mova (&num_mova
, &mova
, from
))
4710 rtx src
= SET_SRC (PATTERN (from
));
4711 if (GET_CODE (src
) == CONST
4712 && GET_CODE (XEXP (src
, 0)) == UNSPEC
4713 && XINT (XEXP (src
, 0), 1) == UNSPEC_SYMOFF
)
4717 case 0: return find_barrier (0, 0, mova
);
4722 = good_barrier
? good_barrier
: found_barrier
;
4726 if (found_si
> count_si
)
4727 count_si
= found_si
;
4729 else if (JUMP_TABLE_DATA_P (from
))
4731 if ((num_mova
> 1 && GET_MODE (prev_nonnote_insn (from
)) == VOIDmode
)
4733 && (prev_nonnote_insn (from
)
4734 == XEXP (MOVA_LABELREF (mova
), 0))))
4736 if (barrier_align (next_real_insn (from
)) == align_jumps_log
)
4738 /* We have just passed the barrier in front of the
4739 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4740 the ADDR_DIFF_VEC is accessed as data, just like our pool
4741 constants, this is a good opportunity to accommodate what
4742 we have gathered so far.
4743 If we waited any longer, we could end up at a barrier in
4744 front of code, which gives worse cache usage for separated
4745 instruction / data caches. */
4746 good_barrier
= found_barrier
;
4751 rtx body
= PATTERN (from
);
4752 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
4755 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4756 else if (JUMP_P (from
)
4761 /* There is a possibility that a bf is transformed into a bf/s by the
4762 delay slot scheduler. */
4763 if (JUMP_P (from
) && !JUMP_TABLE_DATA_P (from
)
4764 && get_attr_type (from
) == TYPE_CBRANCH
4765 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (from
)))) != SEQUENCE
)
4771 if (new_align
> si_align
)
4773 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
4774 si_align
= new_align
;
4776 count_si
= (count_si
+ new_align
- 1) & -new_align
;
4781 if (new_align
> hi_align
)
4783 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
4784 hi_align
= new_align
;
4786 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
4788 from
= NEXT_INSN (from
);
4795 /* Try as we might, the leading mova is out of range. Change
4796 it into a load (which will become a pcload) and retry. */
4798 return find_barrier (0, 0, mova
);
4802 /* Insert the constant pool table before the mova instruction,
4803 to prevent the mova label reference from going out of range. */
4805 good_barrier
= found_barrier
= barrier_before_mova
;
4811 if (good_barrier
&& next_real_insn (found_barrier
))
4812 found_barrier
= good_barrier
;
4816 /* We didn't find a barrier in time to dump our stuff,
4817 so we'll make one. */
4818 rtx label
= gen_label_rtx ();
4820 /* Don't emit a constant table in the middle of insns for
4821 casesi_worker_2. This is a bit overkill but is enough
4822 because casesi_worker_2 wouldn't appear so frequently. */
4826 /* If we exceeded the range, then we must back up over the last
4827 instruction we looked at. Otherwise, we just need to undo the
4828 NEXT_INSN at the end of the loop. */
4829 if (PREV_INSN (from
) != orig
4830 && (count_hi
> hi_limit
|| count_si
> si_limit
))
4831 from
= PREV_INSN (PREV_INSN (from
));
4833 from
= PREV_INSN (from
);
4835 /* Don't emit a constant table int the middle of global pointer setting,
4836 since that that would move the addressing base GOT into another table.
4837 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
4838 in the pool anyway, so just move up the whole constant pool.
4840 However, avoid doing so when the last single GOT mov is the starting
4841 insn itself. Going past above the start insn would create a negative
4842 offset, causing errors. */
4843 if (last_got
&& last_got
!= orig
)
4844 from
= PREV_INSN (last_got
);
4846 /* Don't insert the constant pool table at the position which
4847 may be the landing pad. */
4850 && find_reg_note (from
, REG_EH_REGION
, NULL_RTX
))
4851 from
= PREV_INSN (from
);
4853 /* Walk back to be just before any jump or label.
4854 Putting it before a label reduces the number of times the branch
4855 around the constant pool table will be hit. Putting it before
4856 a jump makes it more likely that the bra delay slot will be
4858 while (NOTE_P (from
) || JUMP_P (from
)
4860 from
= PREV_INSN (from
);
4862 /* Make sure we do not split between a call and its corresponding
4863 CALL_ARG_LOCATION note. */
4866 rtx next
= NEXT_INSN (from
);
4867 if (next
&& NOTE_P (next
)
4868 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
4872 from
= emit_jump_insn_after (gen_jump (label
), from
);
4873 JUMP_LABEL (from
) = label
;
4874 LABEL_NUSES (label
) = 1;
4875 found_barrier
= emit_barrier_after (from
);
4876 emit_label_after (label
, found_barrier
);
4879 return found_barrier
;
4882 /* If the instruction INSN is implemented by a special function, and we can
4883 positively find the register that is used to call the sfunc, and this
4884 register is not used anywhere else in this instruction - except as the
4885 destination of a set, return this register; else, return 0. */
4887 sfunc_uses_reg (rtx insn
)
4890 rtx pattern
, part
, reg_part
, reg
;
4892 if (!NONJUMP_INSN_P (insn
))
4894 pattern
= PATTERN (insn
);
4895 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
4898 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
4900 part
= XVECEXP (pattern
, 0, i
);
4901 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
4906 reg
= XEXP (reg_part
, 0);
4907 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
4909 part
= XVECEXP (pattern
, 0, i
);
4910 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
4912 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
4913 && REG_P (SET_DEST (part
)))
4914 ? SET_SRC (part
) : part
)))
4920 /* See if the only way in which INSN uses REG is by calling it, or by
4921 setting it while calling it. Set *SET to a SET rtx if the register
4925 noncall_uses_reg (rtx reg
, rtx insn
, rtx
*set
)
4931 reg2
= sfunc_uses_reg (insn
);
4932 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
4934 pattern
= single_set (insn
);
4936 && REG_P (SET_DEST (pattern
))
4937 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
4943 /* We don't use rtx_equal_p because we don't care if the mode is
4945 pattern
= single_set (insn
);
4947 && REG_P (SET_DEST (pattern
))
4948 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
4954 par
= PATTERN (insn
);
4955 if (GET_CODE (par
) == PARALLEL
)
4956 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
4958 part
= XVECEXP (par
, 0, i
);
4959 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
4962 return reg_mentioned_p (reg
, SET_SRC (pattern
));
4968 pattern
= PATTERN (insn
);
4970 if (GET_CODE (pattern
) == PARALLEL
)
4974 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
4975 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
4977 pattern
= XVECEXP (pattern
, 0, 0);
4980 if (GET_CODE (pattern
) == SET
)
4982 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
4984 /* We don't use rtx_equal_p, because we don't care if the
4985 mode is different. */
4986 if (!REG_P (SET_DEST (pattern
))
4987 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
4993 pattern
= SET_SRC (pattern
);
4996 if (GET_CODE (pattern
) != CALL
4997 || !MEM_P (XEXP (pattern
, 0))
4998 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
5004 /* Given a X, a pattern of an insn or a part of it, return a mask of used
5005 general registers. Bits 0..15 mean that the respective registers
5006 are used as inputs in the instruction. Bits 16..31 mean that the
5007 registers 0..15, respectively, are used as outputs, or are clobbered.
5008 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5010 regs_used (rtx x
, int is_dest
)
5018 code
= GET_CODE (x
);
5023 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
5024 << (REGNO (x
) + is_dest
));
5028 rtx y
= SUBREG_REG (x
);
5033 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
5035 subreg_regno_offset (REGNO (y
),
5038 GET_MODE (x
)) + is_dest
));
5042 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
5044 /* If there was a return value, it must have been indicated with USE. */
5059 fmt
= GET_RTX_FORMAT (code
);
5061 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5066 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5067 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
5069 else if (fmt
[i
] == 'e')
5070 used
|= regs_used (XEXP (x
, i
), is_dest
);
5075 /* Create an instruction that prevents redirection of a conditional branch
5076 to the destination of the JUMP with address ADDR.
5077 If the branch needs to be implemented as an indirect jump, try to find
5078 a scratch register for it.
5079 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5080 If any preceding insn that doesn't fit into a delay slot is good enough,
5081 pass 1. Pass 2 if a definite blocking insn is needed.
5082 -1 is used internally to avoid deep recursion.
5083 If a blocking instruction is made or recognized, return it. */
5086 gen_block_redirect (rtx jump
, int addr
, int need_block
)
5089 rtx prev
= prev_nonnote_insn (jump
);
5092 /* First, check if we already have an instruction that satisfies our need. */
5093 if (prev
&& NONJUMP_INSN_P (prev
) && ! INSN_DELETED_P (prev
))
5095 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
5097 if (GET_CODE (PATTERN (prev
)) == USE
5098 || GET_CODE (PATTERN (prev
)) == CLOBBER
5099 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
5101 else if ((need_block
&= ~1) < 0)
5103 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
5106 if (GET_CODE (PATTERN (jump
)) == RETURN
)
5110 /* Reorg even does nasty things with return insns that cause branches
5111 to go out of range - see find_end_label and callers. */
5112 return emit_insn_before (gen_block_branch_redirect (const0_rtx
) , jump
);
5114 /* We can't use JUMP_LABEL here because it might be undefined
5115 when not optimizing. */
5116 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
5117 /* If the branch is out of range, try to find a scratch register for it. */
5119 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5123 /* Don't look for the stack pointer as a scratch register,
5124 it would cause trouble if an interrupt occurred. */
5125 unsigned attempt
= 0x7fff, used
;
5126 int jump_left
= flag_expensive_optimizations
+ 1;
5128 /* It is likely that the most recent eligible instruction is wanted for
5129 the delay slot. Therefore, find out which registers it uses, and
5130 try to avoid using them. */
5132 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
5136 if (INSN_DELETED_P (scan
))
5138 code
= GET_CODE (scan
);
5139 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
5142 && GET_CODE (PATTERN (scan
)) != USE
5143 && GET_CODE (PATTERN (scan
)) != CLOBBER
5144 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
5146 attempt
&= ~regs_used (PATTERN (scan
), 0);
5150 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
5151 (scan
= NEXT_INSN (scan
)); )
5155 if (INSN_DELETED_P (scan
))
5157 code
= GET_CODE (scan
);
5160 used
|= regs_used (PATTERN (scan
), 0);
5161 if (code
== CALL_INSN
)
5162 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
5163 dead
|= (used
>> 16) & ~used
;
5169 if (code
== JUMP_INSN
)
5171 if (jump_left
-- && simplejump_p (scan
))
5172 scan
= JUMP_LABEL (scan
);
5178 /* Mask out the stack pointer again, in case it was
5179 the only 'free' register we have found. */
5182 /* If the immediate destination is still in range, check for possible
5183 threading with a jump beyond the delay slot insn.
5184 Don't check if we are called recursively; the jump has been or will be
5185 checked in a different invocation then. */
5187 else if (optimize
&& need_block
>= 0)
5189 rtx next
= next_active_insn (next_active_insn (dest
));
5190 if (next
&& JUMP_P (next
)
5191 && GET_CODE (PATTERN (next
)) == SET
5192 && recog_memoized (next
) == CODE_FOR_jump_compact
)
5194 dest
= JUMP_LABEL (next
);
5196 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5198 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
5204 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
5206 /* It would be nice if we could convert the jump into an indirect
5207 jump / far branch right now, and thus exposing all constituent
5208 instructions to further optimization. However, reorg uses
5209 simplejump_p to determine if there is an unconditional jump where
5210 it should try to schedule instructions from the target of the
5211 branch; simplejump_p fails for indirect jumps even if they have
5213 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
5214 (reg
, GEN_INT (unspec_bbr_uid
++)),
5216 /* ??? We would like this to have the scope of the jump, but that
5217 scope will change when a delay slot insn of an inner scope is added.
5218 Hence, after delay slot scheduling, we'll have to expect
5219 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5222 INSN_LOCATOR (insn
) = INSN_LOCATOR (jump
);
5223 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
5226 else if (need_block
)
5227 /* We can't use JUMP_LABEL here because it might be undefined
5228 when not optimizing. */
5229 return emit_insn_before (gen_block_branch_redirect
5230 (GEN_INT (unspec_bbr_uid
++)),
5235 #define CONDJUMP_MIN -252
5236 #define CONDJUMP_MAX 262
5239 /* A label (to be placed) in front of the jump
5240 that jumps to our ultimate destination. */
5242 /* Where we are going to insert it if we cannot move the jump any farther,
5243 or the jump itself if we have picked up an existing jump. */
5245 /* The ultimate destination. */
5247 struct far_branch
*prev
;
5248 /* If the branch has already been created, its address;
5249 else the address of its first prospective user. */
5253 static void gen_far_branch (struct far_branch
*);
5254 enum mdep_reorg_phase_e mdep_reorg_phase
;
5256 gen_far_branch (struct far_branch
*bp
)
5258 rtx insn
= bp
->insert_place
;
5260 rtx label
= gen_label_rtx ();
5263 emit_label_after (label
, insn
);
5266 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
5267 LABEL_NUSES (bp
->far_label
)++;
5270 jump
= emit_jump_insn_after (gen_return (), insn
);
5271 /* Emit a barrier so that reorg knows that any following instructions
5272 are not reachable via a fall-through path.
5273 But don't do this when not optimizing, since we wouldn't suppress the
5274 alignment for the barrier then, and could end up with out-of-range
5275 pc-relative loads. */
5277 emit_barrier_after (jump
);
5278 emit_label_after (bp
->near_label
, insn
);
5279 JUMP_LABEL (jump
) = bp
->far_label
;
5280 ok
= invert_jump (insn
, label
, 1);
5283 /* If we are branching around a jump (rather than a return), prevent
5284 reorg from using an insn from the jump target as the delay slot insn -
5285 when reorg did this, it pessimized code (we rather hide the delay slot)
5286 and it could cause branches to go out of range. */
5289 (gen_stuff_delay_slot
5290 (GEN_INT (unspec_bbr_uid
++),
5291 GEN_INT (recog_memoized (insn
) == CODE_FOR_branch_false
)),
5293 /* Prevent reorg from undoing our splits. */
5294 gen_block_redirect (jump
, bp
->address
+= 2, 2);
5297 /* Fix up ADDR_DIFF_VECs. */
5299 fixup_addr_diff_vecs (rtx first
)
5303 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5305 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
5308 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
5310 pat
= PATTERN (insn
);
5311 vec_lab
= XEXP (XEXP (pat
, 0), 0);
5313 /* Search the matching casesi_jump_2. */
5314 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
5318 prevpat
= PATTERN (prev
);
5319 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
5321 x
= XVECEXP (prevpat
, 0, 1);
5322 if (GET_CODE (x
) != USE
)
5325 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
5328 /* FIXME: This is a bug in the optimizer, but it seems harmless
5329 to just avoid panicing. */
5333 /* Emit the reference label of the braf where it belongs, right after
5334 the casesi_jump_2 (i.e. braf). */
5335 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
5336 emit_label_after (braf_label
, prev
);
5338 /* Fix up the ADDR_DIF_VEC to be relative
5339 to the reference address of the braf. */
5340 XEXP (XEXP (pat
, 0), 0) = braf_label
;
5344 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5345 a barrier. Return the base 2 logarithm of the desired alignment. */
5347 barrier_align (rtx barrier_or_label
)
5349 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
5350 int slot
, credit
, jump_to_next
= 0;
5355 pat
= PATTERN (next
);
5357 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
5360 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
5361 /* This is a barrier in front of a constant table. */
5364 prev
= prev_real_insn (barrier_or_label
);
5365 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
5367 pat
= PATTERN (prev
);
5368 /* If this is a very small table, we want to keep the alignment after
5369 the table to the minimum for proper code alignment. */
5370 return ((optimize_size
5371 || ((unsigned) XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
5372 <= (unsigned) 1 << (CACHE_LOG
- 2)))
5373 ? 1 << TARGET_SHMEDIA
: align_jumps_log
);
5379 if (! TARGET_SH2
|| ! optimize
)
5380 return align_jumps_log
;
5382 /* When fixing up pcloads, a constant table might be inserted just before
5383 the basic block that ends with the barrier. Thus, we can't trust the
5384 instruction lengths before that. */
5385 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
5387 /* Check if there is an immediately preceding branch to the insn beyond
5388 the barrier. We must weight the cost of discarding useful information
5389 from the current cache line when executing this branch and there is
5390 an alignment, against that of fetching unneeded insn in front of the
5391 branch target when there is no alignment. */
5393 /* There are two delay_slot cases to consider. One is the simple case
5394 where the preceding branch is to the insn beyond the barrier (simple
5395 delay slot filling), and the other is where the preceding branch has
5396 a delay slot that is a duplicate of the insn after the barrier
5397 (fill_eager_delay_slots) and the branch is to the insn after the insn
5398 after the barrier. */
5400 /* PREV is presumed to be the JUMP_INSN for the barrier under
5401 investigation. Skip to the insn before it. */
5402 prev
= prev_real_insn (prev
);
5404 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
5405 credit
>= 0 && prev
&& NONJUMP_INSN_P (prev
);
5406 prev
= prev_real_insn (prev
))
5409 if (GET_CODE (PATTERN (prev
)) == USE
5410 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
5412 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
5414 prev
= XVECEXP (PATTERN (prev
), 0, 1);
5415 if (INSN_UID (prev
) == INSN_UID (next
))
5417 /* Delay slot was filled with insn at jump target. */
5424 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
5426 credit
-= get_attr_length (prev
);
5428 if (prev
&& jump_to_label_p (prev
))
5432 || next_real_insn (JUMP_LABEL (prev
)) == next
5433 /* If relax_delay_slots() decides NEXT was redundant
5434 with some previous instruction, it will have
5435 redirected PREV's jump to the following insn. */
5436 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
5437 /* There is no upper bound on redundant instructions
5438 that might have been skipped, but we must not put an
5439 alignment where none had been before. */
5440 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
5442 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
5443 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
5444 || INSN_CODE (x
) == CODE_FOR_stuff_delay_slot
))))
5446 rtx pat
= PATTERN (prev
);
5447 if (GET_CODE (pat
) == PARALLEL
)
5448 pat
= XVECEXP (pat
, 0, 0);
5449 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
5455 return align_jumps_log
;
5458 /* If we are inside a phony loop, almost any kind of label can turn up as the
5459 first one in the loop. Aligning a braf label causes incorrect switch
5460 destination addresses; we can detect braf labels because they are
5461 followed by a BARRIER.
5462 Applying loop alignment to small constant or switch tables is a waste
5463 of space, so we suppress this too. */
5465 sh_loop_align (rtx label
)
5469 if (! optimize
|| optimize_size
)
5473 next
= next_nonnote_insn (next
);
5474 while (next
&& LABEL_P (next
));
5478 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
5479 || recog_memoized (next
) == CODE_FOR_consttable_2
)
5482 return align_loops_log
;
5485 /* Do a final pass over the function, just before delayed branch
5491 rtx first
, insn
, mova
= NULL_RTX
;
5493 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
5494 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
5496 first
= get_insns ();
5497 max_labelno_before_reorg
= max_label_num ();
5499 /* We must split call insns before introducing `mova's. If we're
5500 optimizing, they'll have already been split. Otherwise, make
5501 sure we don't split them too late. */
5503 split_all_insns_noflow ();
5508 /* If relaxing, generate pseudo-ops to associate function calls with
5509 the symbols they call. It does no harm to not generate these
5510 pseudo-ops. However, when we can generate them, it enables the
5511 linker to potentially relax the jsr to a bsr, and eliminate the
5512 register load and, possibly, the constant pool entry. */
5514 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
5517 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5518 own purposes. This works because none of the remaining passes
5519 need to look at them.
5521 ??? But it may break in the future. We should use a machine
5522 dependent REG_NOTE, or some other approach entirely. */
5523 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5529 while ((note
= find_reg_note (insn
, REG_LABEL_OPERAND
,
5531 remove_note (insn
, note
);
5535 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5537 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
5538 int rescan
= 0, foundinsn
= 0;
5542 pattern
= PATTERN (insn
);
5544 if (GET_CODE (pattern
) == PARALLEL
)
5545 pattern
= XVECEXP (pattern
, 0, 0);
5546 if (GET_CODE (pattern
) == SET
)
5547 pattern
= SET_SRC (pattern
);
5549 if (GET_CODE (pattern
) != CALL
5550 || !MEM_P (XEXP (pattern
, 0)))
5553 reg
= XEXP (XEXP (pattern
, 0), 0);
5557 reg
= sfunc_uses_reg (insn
);
5565 /* Try scanning backward to find where the register is set. */
5567 for (scan
= PREV_INSN (insn
);
5568 scan
&& !LABEL_P (scan
);
5569 scan
= PREV_INSN (scan
))
5571 if (! INSN_P (scan
))
5574 if (! reg_mentioned_p (reg
, scan
))
5577 if (noncall_uses_reg (reg
, scan
, &set
))
5590 /* The register is set at LINK. */
5592 /* We can only optimize the function call if the register is
5593 being set to a symbol. In theory, we could sometimes
5594 optimize calls to a constant location, but the assembler
5595 and linker do not support that at present. */
5596 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
5597 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
5600 /* Scan forward from LINK to the place where REG dies, and
5601 make sure that the only insns which use REG are
5602 themselves function calls. */
5604 /* ??? This doesn't work for call targets that were allocated
5605 by reload, since there may not be a REG_DEAD note for the
5609 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
5613 /* Don't try to trace forward past a CODE_LABEL if we haven't
5614 seen INSN yet. Ordinarily, we will only find the setting insn
5615 if it is in the same basic block. However,
5616 cross-jumping can insert code labels in between the load and
5617 the call, and can result in situations where a single call
5618 insn may have two targets depending on where we came from. */
5620 if (LABEL_P (scan
) && ! foundinsn
)
5623 if (! INSN_P (scan
))
5626 /* Don't try to trace forward past a JUMP. To optimize
5627 safely, we would have to check that all the
5628 instructions at the jump destination did not use REG. */
5633 if (! reg_mentioned_p (reg
, scan
))
5636 if (noncall_uses_reg (reg
, scan
, &scanset
))
5643 && (CALL_P (scan
) || sfunc_uses_reg (scan
)))
5645 /* There is a function call to this register other
5646 than the one we are checking. If we optimize
5647 this call, we need to rescan again below. */
5651 /* ??? We shouldn't have to worry about SCANSET here.
5652 We should just be able to check for a REG_DEAD note
5653 on a function call. However, the REG_DEAD notes are
5654 apparently not dependable around libcalls; c-torture
5655 execute/920501-2 is a test case. If SCANSET is set,
5656 then this insn sets the register, so it must have
5657 died earlier. Unfortunately, this will only handle
5658 the cases in which the register is, in fact, set in a
5661 /* ??? We shouldn't have to use FOUNDINSN here.
5662 This dates back to when we used LOG_LINKS to find
5663 the most recent insn which sets the register. */
5667 || find_reg_note (scan
, REG_DEAD
, reg
)))
5676 /* Either there was a branch, or some insn used REG
5677 other than as a function call address. */
5681 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5682 on the insn which sets the register, and on each call insn
5683 which uses the register. In final_prescan_insn we look for
5684 the REG_LABEL_OPERAND notes, and output the appropriate label
5687 label
= gen_label_rtx ();
5688 add_reg_note (link
, REG_LABEL_OPERAND
, label
);
5689 add_reg_note (insn
, REG_LABEL_OPERAND
, label
);
5697 scan
= NEXT_INSN (scan
);
5700 && reg_mentioned_p (reg
, scan
))
5701 || ((reg2
= sfunc_uses_reg (scan
))
5702 && REGNO (reg2
) == REGNO (reg
))))
5703 add_reg_note (scan
, REG_LABEL_OPERAND
, label
);
5705 while (scan
!= dies
);
5711 fixup_addr_diff_vecs (first
);
5715 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
5716 shorten_branches (first
);
5719 /* Scan the function looking for move instructions which have to be
5720 changed to pc-relative loads and insert the literal tables. */
5721 label_ref_list_pool
= create_alloc_pool ("label references list",
5722 sizeof (struct label_ref_list_d
),
5724 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
5725 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
5729 /* ??? basic block reordering can move a switch table dispatch
5730 below the switch table. Check if that has happened.
5731 We only have the addresses available when optimizing; but then,
5732 this check shouldn't be needed when not optimizing. */
5733 if (!untangle_mova (&num_mova
, &mova
, insn
))
5739 else if (JUMP_P (insn
)
5740 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
5742 /* ??? loop invariant motion can also move a mova out of a
5743 loop. Since loop does this code motion anyway, maybe we
5744 should wrap UNSPEC_MOVA into a CONST, so that reload can
5747 && GET_MODE (prev_nonnote_insn (insn
)) == VOIDmode
)
5748 || (prev_nonnote_insn (insn
)
5749 == XEXP (MOVA_LABELREF (mova
), 0))))
5756 /* Some code might have been inserted between the mova and
5757 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5758 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
5759 total
+= get_attr_length (scan
);
5761 /* range of mova is 1020, add 4 because pc counts from address of
5762 second instruction after this one, subtract 2 in case pc is 2
5763 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5764 cancels out with alignment effects of the mova itself. */
5767 /* Change the mova into a load, and restart scanning
5768 there. broken_move will then return true for mova. */
5773 if (broken_move (insn
)
5774 || (NONJUMP_INSN_P (insn
)
5775 && recog_memoized (insn
) == CODE_FOR_casesi_worker_2
))
5778 /* Scan ahead looking for a barrier to stick the constant table
5780 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
5781 rtx last_float_move
= NULL_RTX
, last_float
= 0, *last_float_addr
= NULL
;
5782 int need_aligned_label
= 0;
5784 if (num_mova
&& ! mova_p (mova
))
5786 /* find_barrier had to change the first mova into a
5787 pcload; thus, we have to start with this new pcload. */
5791 /* Now find all the moves between the points and modify them. */
5792 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
5796 if (NONJUMP_INSN_P (scan
)
5797 && recog_memoized (scan
) == CODE_FOR_casesi_worker_2
)
5798 need_aligned_label
= 1;
5799 if (broken_move (scan
))
5801 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
5805 enum machine_mode mode
;
5807 if (GET_CODE (pat
) == PARALLEL
)
5808 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
5809 src
= SET_SRC (pat
);
5810 dst
= SET_DEST (pat
);
5811 mode
= GET_MODE (dst
);
5813 if (mode
== SImode
&& hi_const (src
)
5814 && REGNO (dst
) != FPUL_REG
)
5819 while (GET_CODE (dst
) == SUBREG
)
5821 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
5822 GET_MODE (SUBREG_REG (dst
)),
5825 dst
= SUBREG_REG (dst
);
5827 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
5829 if (REG_P (dst
) && FP_ANY_REGISTER_P (REGNO (dst
)))
5831 /* This must be an insn that clobbers r0. */
5832 rtx
*clobberp
= &XVECEXP (PATTERN (scan
), 0,
5833 XVECLEN (PATTERN (scan
), 0)
5835 rtx clobber
= *clobberp
;
5837 gcc_assert (GET_CODE (clobber
) == CLOBBER
5838 && rtx_equal_p (XEXP (clobber
, 0), r0_rtx
));
5841 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
5845 && GET_MODE_SIZE (mode
) != 4
5846 && GET_MODE_SIZE (GET_MODE (last_float
)) == 4)
5848 lab
= add_constant (src
, mode
, last_float
);
5850 emit_insn_before (gen_mova (lab
), scan
);
5853 /* There will be a REG_UNUSED note for r0 on
5854 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5855 lest reorg:mark_target_live_regs will not
5856 consider r0 to be used, and we end up with delay
5857 slot insn in front of SCAN that clobbers r0. */
5859 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
5861 /* If we are not optimizing, then there may not be
5864 PUT_REG_NOTE_KIND (note
, REG_INC
);
5866 *last_float_addr
= r0_inc_rtx
;
5868 last_float_move
= scan
;
5870 newsrc
= gen_const_mem (mode
,
5871 (((TARGET_SH4
&& ! TARGET_FMOVD
)
5872 || REGNO (dst
) == FPUL_REG
)
5875 last_float_addr
= &XEXP (newsrc
, 0);
5877 /* Remove the clobber of r0. */
5878 *clobberp
= gen_rtx_CLOBBER (GET_MODE (clobber
),
5879 gen_rtx_SCRATCH (Pmode
));
5881 /* This is a mova needing a label. Create it. */
5882 else if (GET_CODE (src
) == UNSPEC
5883 && XINT (src
, 1) == UNSPEC_MOVA
5884 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
5886 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
5887 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
5888 newsrc
= gen_rtx_UNSPEC (SImode
,
5889 gen_rtvec (1, newsrc
),
5894 lab
= add_constant (src
, mode
, 0);
5895 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
5896 newsrc
= gen_const_mem (mode
, newsrc
);
5898 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
5899 INSN_CODE (scan
) = -1;
5902 dump_table (need_aligned_label
? insn
: 0, barrier
);
5906 free_alloc_pool (label_ref_list_pool
);
5907 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5908 PUT_MODE (insn
, VOIDmode
);
5910 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
5911 INSN_ADDRESSES_FREE ();
5912 split_branches (first
);
5914 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5915 also has an effect on the register that holds the address of the sfunc.
5916 Insert an extra dummy insn in front of each sfunc that pretends to
5917 use this register. */
5918 if (flag_delayed_branch
)
5920 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5922 rtx reg
= sfunc_uses_reg (insn
);
5926 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
5930 /* fpscr is not actually a user variable, but we pretend it is for the
5931 sake of the previous optimization passes, since we want it handled like
5932 one. However, we don't have any debugging information for it, so turn
5933 it into a non-user variable now. */
5935 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5937 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
5941 get_dest_uid (rtx label
, int max_uid
)
5943 rtx dest
= next_real_insn (label
);
5946 /* This can happen for an undefined label. */
5948 dest_uid
= INSN_UID (dest
);
5949 /* If this is a newly created branch redirection blocking instruction,
5950 we cannot index the branch_uid or insn_addresses arrays with its
5951 uid. But then, we won't need to, because the actual destination is
5952 the following branch. */
5953 while (dest_uid
>= max_uid
)
5955 dest
= NEXT_INSN (dest
);
5956 dest_uid
= INSN_UID (dest
);
5958 if (JUMP_P (dest
) && GET_CODE (PATTERN (dest
)) == RETURN
)
5963 /* Split condbranches that are out of range. Also add clobbers for
5964 scratch registers that are needed in far jumps.
5965 We do this before delay slot scheduling, so that it can take our
5966 newly created instructions into account. It also allows us to
5967 find branches with common targets more easily. */
5970 split_branches (rtx first
)
5973 struct far_branch
**uid_branch
, *far_branch_list
= 0;
5974 int max_uid
= get_max_uid ();
5977 /* Find out which branches are out of range. */
5978 shorten_branches (first
);
5980 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
5981 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
5983 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5984 if (! INSN_P (insn
))
5986 else if (INSN_DELETED_P (insn
))
5988 /* Shorten_branches would split this instruction again,
5989 so transform it into a note. */
5990 SET_INSN_DELETED (insn
);
5992 else if (JUMP_P (insn
)
5993 /* Don't mess with ADDR_DIFF_VEC */
5994 && (GET_CODE (PATTERN (insn
)) == SET
5995 || GET_CODE (PATTERN (insn
)) == RETURN
))
5997 enum attr_type type
= get_attr_type (insn
);
5998 if (type
== TYPE_CBRANCH
)
6002 if (get_attr_length (insn
) > 4)
6004 rtx src
= SET_SRC (PATTERN (insn
));
6005 rtx olabel
= XEXP (XEXP (src
, 1), 0);
6006 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6008 int dest_uid
= get_dest_uid (olabel
, max_uid
);
6009 struct far_branch
*bp
= uid_branch
[dest_uid
];
6011 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
6012 the label if the LABEL_NUSES count drops to zero. There is
6013 always a jump_optimize pass that sets these values, but it
6014 proceeds to delete unreferenced code, and then if not
6015 optimizing, to un-delete the deleted instructions, thus
6016 leaving labels with too low uses counts. */
6019 JUMP_LABEL (insn
) = olabel
;
6020 LABEL_NUSES (olabel
)++;
6024 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6025 uid_branch
[dest_uid
] = bp
;
6026 bp
->prev
= far_branch_list
;
6027 far_branch_list
= bp
;
6029 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
6030 LABEL_NUSES (bp
->far_label
)++;
6034 label
= bp
->near_label
;
6035 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
6037 rtx block
= bp
->insert_place
;
6039 if (GET_CODE (PATTERN (block
)) == RETURN
)
6040 block
= PREV_INSN (block
);
6042 block
= gen_block_redirect (block
,
6044 label
= emit_label_after (gen_label_rtx (),
6046 bp
->near_label
= label
;
6048 else if (label
&& ! NEXT_INSN (label
))
6050 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
6051 bp
->insert_place
= insn
;
6053 gen_far_branch (bp
);
6057 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
6059 bp
->near_label
= label
= gen_label_rtx ();
6060 bp
->insert_place
= insn
;
6063 ok
= redirect_jump (insn
, label
, 0);
6068 /* get_attr_length (insn) == 2 */
6069 /* Check if we have a pattern where reorg wants to redirect
6070 the branch to a label from an unconditional branch that
6072 /* We can't use JUMP_LABEL here because it might be undefined
6073 when not optimizing. */
6074 /* A syntax error might cause beyond to be NULL_RTX. */
6076 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
6081 || ((beyond
= next_active_insn (beyond
))
6082 && JUMP_P (beyond
)))
6083 && GET_CODE (PATTERN (beyond
)) == SET
6084 && recog_memoized (beyond
) == CODE_FOR_jump_compact
6086 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
6087 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6089 gen_block_redirect (beyond
,
6090 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
6093 next
= next_active_insn (insn
);
6097 || ((next
= next_active_insn (next
))
6099 && GET_CODE (PATTERN (next
)) == SET
6100 && recog_memoized (next
) == CODE_FOR_jump_compact
6102 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
6103 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6105 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
6107 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
6109 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6112 struct far_branch
*bp
;
6114 if (type
== TYPE_JUMP
)
6116 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
6117 dest_uid
= get_dest_uid (far_label
, max_uid
);
6120 /* Parse errors can lead to labels outside
6122 if (! NEXT_INSN (far_label
))
6127 JUMP_LABEL (insn
) = far_label
;
6128 LABEL_NUSES (far_label
)++;
6130 redirect_jump (insn
, ret_rtx
, 1);
6134 bp
= uid_branch
[dest_uid
];
6137 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6138 uid_branch
[dest_uid
] = bp
;
6139 bp
->prev
= far_branch_list
;
6140 far_branch_list
= bp
;
6142 bp
->far_label
= far_label
;
6144 LABEL_NUSES (far_label
)++;
6146 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
6147 if (addr
- bp
->address
<= CONDJUMP_MAX
)
6148 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
6151 gen_far_branch (bp
);
6157 bp
->insert_place
= insn
;
6159 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
6161 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
6164 /* Generate all pending far branches,
6165 and free our references to the far labels. */
6166 while (far_branch_list
)
6168 if (far_branch_list
->near_label
6169 && ! NEXT_INSN (far_branch_list
->near_label
))
6170 gen_far_branch (far_branch_list
);
6172 && far_branch_list
->far_label
6173 && ! --LABEL_NUSES (far_branch_list
->far_label
))
6174 delete_insn (far_branch_list
->far_label
);
6175 far_branch_list
= far_branch_list
->prev
;
6178 /* Instruction length information is no longer valid due to the new
6179 instructions that have been generated. */
6180 init_insn_lengths ();
6183 /* Dump out instruction addresses, which is useful for debugging the
6184 constant pool table stuff.
6186 If relaxing, output the label and pseudo-ops used to link together
6187 calls and the instruction which set the registers. */
6189 /* ??? The addresses printed by this routine for insns are nonsense for
6190 insns which are inside of a sequence where none of the inner insns have
6191 variable length. This is because the second pass of shorten_branches
6192 does not bother to update them. */
6195 final_prescan_insn (rtx insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
6196 int noperands ATTRIBUTE_UNUSED
)
6198 if (TARGET_DUMPISIZE
)
6199 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
6205 note
= find_reg_note (insn
, REG_LABEL_OPERAND
, NULL_RTX
);
6210 pattern
= PATTERN (insn
);
6211 if (GET_CODE (pattern
) == PARALLEL
)
6212 pattern
= XVECEXP (pattern
, 0, 0);
6213 switch (GET_CODE (pattern
))
6216 if (GET_CODE (SET_SRC (pattern
)) != CALL
6217 && get_attr_type (insn
) != TYPE_SFUNC
)
6219 targetm
.asm_out
.internal_label
6220 (asm_out_file
, "L", CODE_LABEL_NUMBER (XEXP (note
, 0)));
6223 /* else FALLTHROUGH */
6225 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
6226 CODE_LABEL_NUMBER (XEXP (note
, 0)));
6236 /* Dump out any constants accumulated in the final pass. These will
6240 output_jump_label_table (void)
6246 fprintf (asm_out_file
, "\t.align 2\n");
6247 for (i
= 0; i
< pool_size
; i
++)
6249 pool_node
*p
= &pool_vector
[i
];
6251 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
6252 CODE_LABEL_NUMBER (p
->label
));
6253 output_asm_insn (".long %O0", &p
->value
);
6261 /* A full frame looks like:
6265 [ if current_function_anonymous_args
6278 local-0 <- fp points here. */
6280 /* Number of bytes pushed for anonymous args, used to pass information
6281 between expand_prologue and expand_epilogue. */
6283 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6284 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6285 for an epilogue and a negative value means that it's for a sibcall
6286 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6287 all the registers that are about to be restored, and hence dead. */
6290 output_stack_adjust (int size
, rtx reg
, int epilogue_p
,
6291 HARD_REG_SET
*live_regs_mask
, bool frame_p
)
6293 rtx (*emit_fn
) (rtx
) = frame_p
? &frame_insn
: &emit_insn
;
6296 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6298 /* This test is bogus, as output_stack_adjust is used to re-align the
6301 gcc_assert (!(size
% align
));
6304 if (CONST_OK_FOR_ADD (size
))
6305 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
6306 /* Try to do it with two partial adjustments; however, we must make
6307 sure that the stack is properly aligned at all times, in case
6308 an interrupt occurs between the two partial adjustments. */
6309 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
6310 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
6312 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
6313 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
6319 int temp
= epilogue_p
? 7 : (TARGET_SH5
? 0 : 1);
6322 /* If TEMP is invalid, we could temporarily save a general
6323 register to MACL. However, there is currently no need
6324 to handle this case, so just die when we see it. */
6326 || current_function_interrupt
6327 || ! call_really_used_regs
[temp
] || fixed_regs
[temp
])
6329 if (temp
< 0 && ! current_function_interrupt
6330 && (TARGET_SHMEDIA
|| epilogue_p
>= 0))
6333 COPY_HARD_REG_SET (temps
, call_used_reg_set
);
6334 AND_COMPL_HARD_REG_SET (temps
, call_fixed_reg_set
);
6338 if (crtl
->return_rtx
)
6340 enum machine_mode mode
;
6341 mode
= GET_MODE (crtl
->return_rtx
);
6342 if (BASE_RETURN_VALUE_REG (mode
) == FIRST_RET_REG
)
6343 nreg
= HARD_REGNO_NREGS (FIRST_RET_REG
, mode
);
6345 for (i
= 0; i
< nreg
; i
++)
6346 CLEAR_HARD_REG_BIT (temps
, FIRST_RET_REG
+ i
);
6347 if (crtl
->calls_eh_return
)
6349 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_STACKADJ_REGNO
);
6350 for (i
= 0; i
<= 3; i
++)
6351 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_DATA_REGNO (i
));
6354 if (TARGET_SHMEDIA
&& epilogue_p
< 0)
6355 for (i
= FIRST_TARGET_REG
; i
<= LAST_TARGET_REG
; i
++)
6356 CLEAR_HARD_REG_BIT (temps
, i
);
6357 if (epilogue_p
<= 0)
6359 for (i
= FIRST_PARM_REG
;
6360 i
< FIRST_PARM_REG
+ NPARM_REGS (SImode
); i
++)
6361 CLEAR_HARD_REG_BIT (temps
, i
);
6362 if (cfun
->static_chain_decl
!= NULL
)
6363 CLEAR_HARD_REG_BIT (temps
, STATIC_CHAIN_REGNUM
);
6365 temp
= scavenge_reg (&temps
);
6367 if (temp
< 0 && live_regs_mask
)
6371 COPY_HARD_REG_SET (temps
, *live_regs_mask
);
6372 CLEAR_HARD_REG_BIT (temps
, REGNO (reg
));
6373 temp
= scavenge_reg (&temps
);
6377 rtx adj_reg
, tmp_reg
, mem
;
6379 /* If we reached here, the most likely case is the (sibcall)
6380 epilogue for non SHmedia. Put a special push/pop sequence
6381 for such case as the last resort. This looks lengthy but
6382 would not be problem because it seems to be very
6385 gcc_assert (!TARGET_SHMEDIA
&& epilogue_p
);
6388 /* ??? There is still the slight possibility that r4 or
6389 r5 have been reserved as fixed registers or assigned
6390 as global registers, and they change during an
6391 interrupt. There are possible ways to handle this:
6393 - If we are adjusting the frame pointer (r14), we can do
6394 with a single temp register and an ordinary push / pop
6396 - Grab any call-used or call-saved registers (i.e. not
6397 fixed or globals) for the temps we need. We might
6398 also grab r14 if we are adjusting the stack pointer.
6399 If we can't find enough available registers, issue
6400 a diagnostic and die - the user must have reserved
6401 way too many registers.
6402 But since all this is rather unlikely to happen and
6403 would require extra testing, we just die if r4 / r5
6404 are not available. */
6405 gcc_assert (!fixed_regs
[4] && !fixed_regs
[5]
6406 && !global_regs
[4] && !global_regs
[5]);
6408 adj_reg
= gen_rtx_REG (GET_MODE (reg
), 4);
6409 tmp_reg
= gen_rtx_REG (GET_MODE (reg
), 5);
6410 emit_move_insn (gen_tmp_stack_mem (Pmode
, reg
), adj_reg
);
6411 emit_insn (GEN_MOV (adj_reg
, GEN_INT (size
)));
6412 emit_insn (GEN_ADD3 (adj_reg
, adj_reg
, reg
));
6413 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
6414 emit_move_insn (mem
, tmp_reg
);
6415 emit_move_insn (tmp_reg
, gen_tmp_stack_mem (Pmode
, reg
));
6416 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
6417 emit_move_insn (mem
, tmp_reg
);
6418 emit_move_insn (reg
, adj_reg
);
6419 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
6420 emit_move_insn (adj_reg
, mem
);
6421 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
6422 emit_move_insn (tmp_reg
, mem
);
6423 /* Tell flow the insns that pop r4/r5 aren't dead. */
6428 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
6430 /* If SIZE is negative, subtract the positive value.
6431 This sometimes allows a constant pool entry to be shared
6432 between prologue and epilogue code. */
6435 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
6436 insn
= emit_fn (GEN_SUB3 (reg
, reg
, const_reg
));
6440 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
6441 insn
= emit_fn (GEN_ADD3 (reg
, reg
, const_reg
));
6444 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
6445 gen_rtx_SET (VOIDmode
, reg
,
6446 gen_rtx_PLUS (SImode
, reg
,
6456 RTX_FRAME_RELATED_P (x
) = 1;
6460 /* Output RTL to push register RN onto the stack. */
6467 x
= gen_push_fpul ();
6468 else if (rn
== FPSCR_REG
)
6469 x
= gen_push_fpscr ();
6470 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
6471 && FP_OR_XD_REGISTER_P (rn
))
6473 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
6475 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
6477 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
6478 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
6480 x
= gen_push (gen_rtx_REG (SImode
, rn
));
6483 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
6487 /* Output RTL to pop register RN from the stack. */
6494 x
= gen_pop_fpul ();
6495 else if (rn
== FPSCR_REG
)
6496 x
= gen_pop_fpscr ();
6497 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
6498 && FP_OR_XD_REGISTER_P (rn
))
6500 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
6502 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
6504 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
6505 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
6507 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
6510 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
6513 /* Generate code to push the regs specified in the mask. */
6516 push_regs (HARD_REG_SET
*mask
, int interrupt_handler
)
6518 int i
= interrupt_handler
? LAST_BANKED_REG
+ 1 : 0;
6521 /* Push PR last; this gives better latencies after the prologue, and
6522 candidates for the return delay slot when there are no general
6523 registers pushed. */
6524 for (; i
< FIRST_PSEUDO_REGISTER
; i
++)
6526 /* If this is an interrupt handler, and the SZ bit varies,
6527 and we have to push any floating point register, we need
6528 to switch to the correct precision first. */
6529 if (i
== FIRST_FP_REG
&& interrupt_handler
&& TARGET_FMOVD
6530 && hard_reg_set_intersect_p (*mask
, reg_class_contents
[DF_REGS
]))
6532 HARD_REG_SET unsaved
;
6535 COMPL_HARD_REG_SET (unsaved
, *mask
);
6536 fpscr_set_from_mem (NORMAL_MODE (FP_MODE
), unsaved
);
6540 && (i
!= FPSCR_REG
|| ! skip_fpscr
)
6541 && TEST_HARD_REG_BIT (*mask
, i
))
6543 /* If the ISR has RESBANK attribute assigned, don't push any of
6544 the following registers - R0-R14, MACH, MACL and GBR. */
6545 if (! (sh_cfun_resbank_handler_p ()
6546 && ((i
>= FIRST_GENERAL_REG
&& i
< LAST_GENERAL_REG
)
6554 /* Push banked registers last to improve delay slot opportunities. */
6555 if (interrupt_handler
)
6557 bool use_movml
= false;
6561 unsigned int count
= 0;
6563 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
6564 if (TEST_HARD_REG_BIT (*mask
, i
))
6569 /* Use movml when all banked registers are pushed. */
6570 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
6574 if (sh_cfun_resbank_handler_p ())
6578 rtx x
, mem
, reg
, set
;
6579 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
6581 /* We must avoid scheduling multiple store insn with another
6583 emit_insn (gen_blockage ());
6584 x
= gen_movml_push_banked (sp_reg
);
6586 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
6588 mem
= gen_rtx_MEM (SImode
, plus_constant (sp_reg
, i
* 4));
6589 reg
= gen_rtx_REG (SImode
, i
);
6590 add_reg_note (x
, REG_CFA_OFFSET
, gen_rtx_SET (SImode
, mem
, reg
));
6593 set
= gen_rtx_SET (SImode
, sp_reg
, plus_constant (sp_reg
, - 32));
6594 add_reg_note (x
, REG_CFA_ADJUST_CFA
, set
);
6595 emit_insn (gen_blockage ());
6598 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
6599 if (TEST_HARD_REG_BIT (*mask
, i
))
6603 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6604 if (TEST_HARD_REG_BIT (*mask
, PR_REG
) && !sh_cfun_resbank_handler_p ())
6608 /* Calculate how much extra space is needed to save all callee-saved
6610 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6613 shmedia_target_regs_stack_space (HARD_REG_SET
*live_regs_mask
)
6616 int stack_space
= 0;
6617 int interrupt_handler
= sh_cfun_interrupt_handler_p ();
6619 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
6620 if ((! call_really_used_regs
[reg
] || interrupt_handler
)
6621 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
6622 /* Leave space to save this target register on the stack,
6623 in case target register allocation wants to use it. */
6624 stack_space
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
6628 /* Decide whether we should reserve space for callee-save target registers,
6629 in case target register allocation wants to use them. REGS_SAVED is
6630 the space, in bytes, that is already required for register saves.
6631 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6634 shmedia_reserve_space_for_target_registers_p (int regs_saved
,
6635 HARD_REG_SET
*live_regs_mask
)
6639 return shmedia_target_regs_stack_space (live_regs_mask
) <= regs_saved
;
6642 /* Decide how much space to reserve for callee-save target registers
6643 in case target register allocation wants to use them.
6644 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6647 shmedia_target_regs_stack_adjust (HARD_REG_SET
*live_regs_mask
)
6649 if (shmedia_space_reserved_for_target_registers
)
6650 return shmedia_target_regs_stack_space (live_regs_mask
);
6655 /* Work out the registers which need to be saved, both as a mask and a
6656 count of saved words. Return the count.
6658 If doing a pragma interrupt function, then push all regs used by the
6659 function, and if we call another function (we can tell by looking at PR),
6660 make sure that all the regs it clobbers are safe too. */
6663 calc_live_regs (HARD_REG_SET
*live_regs_mask
)
6668 bool interrupt_or_trapa_handler
, trapa_handler
, interrupt_handler
;
6669 bool nosave_low_regs
;
6670 int pr_live
, has_call
;
6672 attrs
= DECL_ATTRIBUTES (current_function_decl
);
6673 interrupt_or_trapa_handler
= sh_cfun_interrupt_handler_p ();
6674 trapa_handler
= lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
;
6675 interrupt_handler
= interrupt_or_trapa_handler
&& ! trapa_handler
;
6676 nosave_low_regs
= lookup_attribute ("nosave_low_regs", attrs
) != NULL_TREE
;
6678 CLEAR_HARD_REG_SET (*live_regs_mask
);
6679 if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
&& interrupt_handler
6680 && df_regs_ever_live_p (FPSCR_REG
))
6681 target_flags
&= ~MASK_FPU_SINGLE
;
6682 /* If we can save a lot of saves by switching to double mode, do that. */
6683 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
6684 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
6685 if (df_regs_ever_live_p (reg
) && df_regs_ever_live_p (reg
+1)
6686 && (! call_really_used_regs
[reg
]
6687 || interrupt_handler
)
6690 target_flags
&= ~MASK_FPU_SINGLE
;
6693 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6694 knows how to use it. That means the pseudo originally allocated for
6695 the initial value can become the PR_MEDIA_REG hard register, as seen for
6696 execute/20010122-1.c:test9. */
6698 /* ??? this function is called from initial_elimination_offset, hence we
6699 can't use the result of sh_media_register_for_return here. */
6700 pr_live
= sh_pr_n_sets ();
6703 rtx pr_initial
= has_hard_reg_initial_val (Pmode
, PR_REG
);
6704 pr_live
= (pr_initial
6705 ? (!REG_P (pr_initial
)
6706 || REGNO (pr_initial
) != (PR_REG
))
6707 : df_regs_ever_live_p (PR_REG
));
6708 /* For Shcompact, if not optimizing, we end up with a memory reference
6709 using the return address pointer for __builtin_return_address even
6710 though there is no actual need to put the PR register on the stack. */
6711 pr_live
|= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM
);
6713 /* Force PR to be live if the prologue has to call the SHmedia
6714 argument decoder or register saver. */
6715 if (TARGET_SHCOMPACT
6716 && ((crtl
->args
.info
.call_cookie
6717 & ~ CALL_COOKIE_RET_TRAMP (1))
6718 || crtl
->saves_all_registers
))
6720 has_call
= TARGET_SHMEDIA
? ! leaf_function_p () : pr_live
;
6721 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
; reg
-- != 0; )
6723 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
6726 ? (/* Need to save all the regs ever live. */
6727 (df_regs_ever_live_p (reg
)
6728 || (call_really_used_regs
[reg
]
6729 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
6730 || reg
== PIC_OFFSET_TABLE_REGNUM
)
6732 || (TARGET_SHMEDIA
&& has_call
6733 && REGISTER_NATURAL_MODE (reg
) == SImode
6734 && (GENERAL_REGISTER_P (reg
) || TARGET_REGISTER_P (reg
))))
6735 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
6736 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
6737 && reg
!= T_REG
&& reg
!= GBR_REG
6738 /* Push fpscr only on targets which have FPU */
6739 && (reg
!= FPSCR_REG
|| TARGET_FPU_ANY
))
6740 : (/* Only push those regs which are used and need to be saved. */
6743 && crtl
->args
.info
.call_cookie
6744 && reg
== PIC_OFFSET_TABLE_REGNUM
)
6745 || (df_regs_ever_live_p (reg
)
6746 && ((!call_really_used_regs
[reg
]
6747 && !(reg
!= PIC_OFFSET_TABLE_REGNUM
6748 && fixed_regs
[reg
] && call_used_regs
[reg
]))
6749 || (trapa_handler
&& reg
== FPSCR_REG
&& TARGET_FPU_ANY
)))
6750 || (crtl
->calls_eh_return
6751 && (reg
== EH_RETURN_DATA_REGNO (0)
6752 || reg
== EH_RETURN_DATA_REGNO (1)
6753 || reg
== EH_RETURN_DATA_REGNO (2)
6754 || reg
== EH_RETURN_DATA_REGNO (3)))
6755 || ((reg
== MACL_REG
|| reg
== MACH_REG
)
6756 && df_regs_ever_live_p (reg
)
6757 && sh_cfun_attr_renesas_p ())
6760 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
6761 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
6763 if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
|| TARGET_SH5
) && TARGET_FMOVD
6764 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
6766 if (FP_REGISTER_P (reg
))
6768 if (! TARGET_FPU_SINGLE
&& ! df_regs_ever_live_p (reg
^ 1))
6770 SET_HARD_REG_BIT (*live_regs_mask
, (reg
^ 1));
6771 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
6774 else if (XD_REGISTER_P (reg
))
6776 /* Must switch to double mode to access these registers. */
6777 target_flags
&= ~MASK_FPU_SINGLE
;
6781 if (nosave_low_regs
&& reg
== R8_REG
)
6784 /* If we have a target register optimization pass after prologue / epilogue
6785 threading, we need to assume all target registers will be live even if
6787 if (flag_branch_target_load_optimize2
6788 && TARGET_SAVE_ALL_TARGET_REGS
6789 && shmedia_space_reserved_for_target_registers
)
6790 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
6791 if ((! call_really_used_regs
[reg
] || interrupt_handler
)
6792 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
6794 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
6795 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
6797 /* If this is an interrupt handler, we don't have any call-clobbered
6798 registers we can conveniently use for target register save/restore.
6799 Make sure we save at least one general purpose register when we need
6800 to save target registers. */
6801 if (interrupt_handler
6802 && hard_reg_set_intersect_p (*live_regs_mask
,
6803 reg_class_contents
[TARGET_REGS
])
6804 && ! hard_reg_set_intersect_p (*live_regs_mask
,
6805 reg_class_contents
[GENERAL_REGS
]))
6807 SET_HARD_REG_BIT (*live_regs_mask
, R0_REG
);
6808 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG
));
6814 /* Code to generate prologue and epilogue sequences */
6816 /* PUSHED is the number of bytes that are being pushed on the
6817 stack for register saves. Return the frame size, padded
6818 appropriately so that the stack stays properly aligned. */
6819 static HOST_WIDE_INT
6820 rounded_frame_size (int pushed
)
6822 HOST_WIDE_INT size
= get_frame_size ();
6823 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6825 if (ACCUMULATE_OUTGOING_ARGS
)
6826 size
+= crtl
->outgoing_args_size
;
6828 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
6831 /* Choose a call-clobbered target-branch register that remains
6832 unchanged along the whole function. We set it up as the return
6833 value in the prologue. */
6835 sh_media_register_for_return (void)
6840 if (! current_function_is_leaf
)
6842 if (lookup_attribute ("interrupt_handler",
6843 DECL_ATTRIBUTES (current_function_decl
)))
6845 if (sh_cfun_interrupt_handler_p ())
6848 tr0_used
= flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
6850 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
6851 if (call_really_used_regs
[regno
] && ! df_regs_ever_live_p (regno
))
6857 /* The maximum registers we need to save are:
6858 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6859 - 32 floating point registers (for each pair, we save none,
6860 one single precision value, or a double precision value).
6861 - 8 target registers
6862 - add 1 entry for a delimiter. */
6863 #define MAX_SAVED_REGS (62+32+8)
6865 typedef struct save_entry_s
6874 /* There will be a delimiter entry with VOIDmode both at the start and the
6875 end of a filled in schedule. The end delimiter has the offset of the
6876 save with the smallest (i.e. most negative) offset. */
6877 typedef struct save_schedule_s
6879 save_entry entries
[MAX_SAVED_REGS
+ 2];
6880 int temps
[MAX_TEMPS
+1];
6883 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6884 use reverse order. Returns the last entry written to (not counting
6885 the delimiter). OFFSET_BASE is a number to be added to all offset
6889 sh5_schedule_saves (HARD_REG_SET
*live_regs_mask
, save_schedule
*schedule
,
6893 save_entry
*entry
= schedule
->entries
;
6897 if (! current_function_interrupt
)
6898 for (i
= FIRST_GENERAL_REG
; tmpx
< MAX_TEMPS
&& i
<= LAST_GENERAL_REG
; i
++)
6899 if (call_really_used_regs
[i
] && ! fixed_regs
[i
] && i
!= PR_MEDIA_REG
6900 && ! FUNCTION_ARG_REGNO_P (i
)
6901 && i
!= FIRST_RET_REG
6902 && ! (cfun
->static_chain_decl
!= NULL
&& i
== STATIC_CHAIN_REGNUM
)
6903 && ! (crtl
->calls_eh_return
6904 && (i
== EH_RETURN_STACKADJ_REGNO
6905 || ((unsigned) i
>= EH_RETURN_DATA_REGNO (0)
6906 && (unsigned) i
<= EH_RETURN_DATA_REGNO (3)))))
6907 schedule
->temps
[tmpx
++] = i
;
6909 entry
->mode
= VOIDmode
;
6910 entry
->offset
= offset_base
;
6912 /* We loop twice: first, we save 8-byte aligned registers in the
6913 higher addresses, that are known to be aligned. Then, we
6914 proceed to saving 32-bit registers that don't need 8-byte
6916 If this is an interrupt function, all registers that need saving
6917 need to be saved in full. moreover, we need to postpone saving
6918 target registers till we have saved some general purpose registers
6919 we can then use as scratch registers. */
6920 offset
= offset_base
;
6921 for (align
= 1; align
>= 0; align
--)
6923 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
6924 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
6926 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
6929 if (current_function_interrupt
)
6931 if (TARGET_REGISTER_P (i
))
6933 if (GENERAL_REGISTER_P (i
))
6936 if (mode
== SFmode
&& (i
% 2) == 1
6937 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
6938 && (TEST_HARD_REG_BIT (*live_regs_mask
, (i
^ 1))))
6945 /* If we're doing the aligned pass and this is not aligned,
6946 or we're doing the unaligned pass and this is aligned,
6948 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
) == 0)
6952 if (current_function_interrupt
6953 && GENERAL_REGISTER_P (i
)
6954 && tmpx
< MAX_TEMPS
)
6955 schedule
->temps
[tmpx
++] = i
;
6957 offset
-= GET_MODE_SIZE (mode
);
6960 entry
->offset
= offset
;
6963 if (align
&& current_function_interrupt
)
6964 for (i
= LAST_TARGET_REG
; i
>= FIRST_TARGET_REG
; i
--)
6965 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
6967 offset
-= GET_MODE_SIZE (DImode
);
6969 entry
->mode
= DImode
;
6970 entry
->offset
= offset
;
6975 entry
->mode
= VOIDmode
;
6976 entry
->offset
= offset
;
6977 schedule
->temps
[tmpx
] = -1;
6982 sh_expand_prologue (void)
6984 HARD_REG_SET live_regs_mask
;
6987 int save_flags
= target_flags
;
6991 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
));
6993 current_function_interrupt
= sh_cfun_interrupt_handler_p ();
6995 /* We have pretend args if we had an object sent partially in registers
6996 and partially on the stack, e.g. a large structure. */
6997 pretend_args
= crtl
->args
.pretend_args_size
;
6998 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
)
6999 && (NPARM_REGS(SImode
)
7000 > crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]))
7003 output_stack_adjust (-pretend_args
7004 - crtl
->args
.info
.stack_regs
* 8,
7005 stack_pointer_rtx
, 0, NULL
, true);
7006 stack_usage
= pretend_args
+ crtl
->args
.info
.stack_regs
* 8;
7008 if (TARGET_SHCOMPACT
&& flag_pic
&& crtl
->args
.info
.call_cookie
)
7009 /* We're going to use the PIC register to load the address of the
7010 incoming-argument decoder and/or of the return trampoline from
7011 the GOT, so make sure the PIC register is preserved and
7013 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
7015 if (TARGET_SHCOMPACT
7016 && (crtl
->args
.info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
7020 /* First, make all registers with incoming arguments that will
7021 be pushed onto the stack live, so that register renaming
7022 doesn't overwrite them. */
7023 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
7024 if (CALL_COOKIE_STACKSEQ_GET (crtl
->args
.info
.call_cookie
)
7025 >= NPARM_REGS (SImode
) - reg
)
7026 for (; reg
< NPARM_REGS (SImode
); reg
++)
7027 emit_insn (gen_shcompact_preserve_incoming_args
7028 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
7029 else if (CALL_COOKIE_INT_REG_GET
7030 (crtl
->args
.info
.call_cookie
, reg
) == 1)
7031 emit_insn (gen_shcompact_preserve_incoming_args
7032 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
7034 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
7036 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
7037 GEN_INT (crtl
->args
.info
.call_cookie
));
7038 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
7039 gen_rtx_REG (SImode
, R0_REG
));
7041 else if (TARGET_SHMEDIA
)
7043 int tr
= sh_media_register_for_return ();
7046 emit_move_insn (gen_rtx_REG (DImode
, tr
),
7047 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
7050 /* Emit the code for SETUP_VARARGS. */
7053 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
7055 /* Push arg regs as if they'd been provided by caller in stack. */
7056 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
7058 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
7060 if (i
>= (NPARM_REGS(SImode
)
7061 - crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]
7065 stack_usage
+= GET_MODE_SIZE (SImode
);
7070 /* If we're supposed to switch stacks at function entry, do so now. */
7074 /* The argument specifies a variable holding the address of the
7075 stack the interrupt function should switch to/from at entry/exit. */
7076 tree arg
= TREE_VALUE ( TREE_VALUE (sp_switch_attr
));
7078 = ggc_strdup (TREE_STRING_POINTER (arg
));
7079 rtx sp_switch
= gen_rtx_SYMBOL_REF (Pmode
, s
);
7081 lab
= add_constant (sp_switch
, SImode
, 0);
7082 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
7083 newsrc
= gen_const_mem (SImode
, newsrc
);
7085 emit_insn (gen_sp_switch_1 (newsrc
));
7088 d
= calc_live_regs (&live_regs_mask
);
7089 /* ??? Maybe we could save some switching if we can move a mode switch
7090 that already happens to be at the function start into the prologue. */
7091 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7092 emit_insn (gen_toggle_sz ());
7096 int offset_base
, offset
;
7098 int offset_in_r0
= -1;
7100 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
7101 int total_size
, save_size
;
7102 save_schedule schedule
;
7106 if (call_really_used_regs
[R0_REG
] && ! fixed_regs
[R0_REG
]
7107 && ! current_function_interrupt
)
7108 r0
= gen_rtx_REG (Pmode
, R0_REG
);
7110 /* D is the actual number of bytes that we need for saving registers,
7111 however, in initial_elimination_offset we have committed to using
7112 an additional TREGS_SPACE amount of bytes - in order to keep both
7113 addresses to arguments supplied by the caller and local variables
7114 valid, we must keep this gap. Place it between the incoming
7115 arguments and the actually saved registers in a bid to optimize
7116 locality of reference. */
7117 total_size
= d
+ tregs_space
;
7118 total_size
+= rounded_frame_size (total_size
);
7119 save_size
= total_size
- rounded_frame_size (d
);
7120 if (save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
7121 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
7122 - save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
7124 /* If adjusting the stack in a single step costs nothing extra, do so.
7125 I.e. either if a single addi is enough, or we need a movi anyway,
7126 and we don't exceed the maximum offset range (the test for the
7127 latter is conservative for simplicity). */
7129 && (CONST_OK_FOR_I10 (-total_size
)
7130 || (! CONST_OK_FOR_I10 (-(save_size
+ d_rounding
))
7131 && total_size
<= 2044)))
7132 d_rounding
= total_size
- save_size
;
7134 offset_base
= d
+ d_rounding
;
7136 output_stack_adjust (-(save_size
+ d_rounding
), stack_pointer_rtx
,
7138 stack_usage
+= save_size
+ d_rounding
;
7140 sh5_schedule_saves (&live_regs_mask
, &schedule
, offset_base
);
7141 tmp_pnt
= schedule
.temps
;
7142 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
7144 enum machine_mode mode
= (enum machine_mode
) entry
->mode
;
7145 unsigned int reg
= entry
->reg
;
7146 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
7149 offset
= entry
->offset
;
7151 reg_rtx
= gen_rtx_REG (mode
, reg
);
7153 mem_rtx
= gen_frame_mem (mode
,
7154 gen_rtx_PLUS (Pmode
,
7158 if (!memory_address_p (mode
, XEXP (mem_rtx
, 0)))
7164 if (HAVE_PRE_DECREMENT
7165 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
7166 || mem_rtx
== NULL_RTX
7167 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
7169 pre_dec
= gen_frame_mem (mode
, gen_rtx_PRE_DEC (Pmode
, r0
));
7171 if (!memory_address_p (mode
, XEXP (pre_dec
, 0)))
7176 offset
+= GET_MODE_SIZE (mode
);
7180 if (mem_rtx
!= NULL_RTX
)
7183 if (offset_in_r0
== -1)
7185 emit_move_insn (r0
, GEN_INT (offset
));
7186 offset_in_r0
= offset
;
7188 else if (offset
!= offset_in_r0
)
7193 GEN_INT (offset
- offset_in_r0
)));
7194 offset_in_r0
+= offset
- offset_in_r0
;
7197 if (pre_dec
!= NULL_RTX
)
7203 (Pmode
, r0
, stack_pointer_rtx
));
7207 offset
-= GET_MODE_SIZE (mode
);
7208 offset_in_r0
-= GET_MODE_SIZE (mode
);
7213 mem_rtx
= gen_frame_mem (mode
, r0
);
7215 mem_rtx
= gen_frame_mem (mode
,
7216 gen_rtx_PLUS (Pmode
,
7220 /* We must not use an r0-based address for target-branch
7221 registers or for special registers without pre-dec
7222 memory addresses, since we store their values in r0
7224 gcc_assert (!TARGET_REGISTER_P (reg
)
7225 && ((reg
!= PR_REG
&& !SPECIAL_REGISTER_P (reg
))
7226 || mem_rtx
== pre_dec
));
7229 orig_reg_rtx
= reg_rtx
;
7230 if (TARGET_REGISTER_P (reg
)
7231 || ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
7232 && mem_rtx
!= pre_dec
))
7234 rtx tmp_reg
= gen_rtx_REG (GET_MODE (reg_rtx
), *tmp_pnt
);
7236 emit_move_insn (tmp_reg
, reg_rtx
);
7238 if (REGNO (tmp_reg
) == R0_REG
)
7242 gcc_assert (!refers_to_regno_p
7243 (R0_REG
, R0_REG
+1, mem_rtx
, (rtx
*) 0));
7246 if (*++tmp_pnt
<= 0)
7247 tmp_pnt
= schedule
.temps
;
7254 /* Mark as interesting for dwarf cfi generator */
7255 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
7256 RTX_FRAME_RELATED_P (insn
) = 1;
7257 /* If we use an intermediate register for the save, we can't
7258 describe this exactly in cfi as a copy of the to-be-saved
7259 register into the temporary register and then the temporary
7260 register on the stack, because the temporary register can
7261 have a different natural size than the to-be-saved register.
7262 Thus, we gloss over the intermediate copy and pretend we do
7263 a direct save from the to-be-saved register. */
7264 if (REGNO (reg_rtx
) != reg
)
7268 set
= gen_rtx_SET (VOIDmode
, mem_rtx
, orig_reg_rtx
);
7269 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
7272 if (TARGET_SHCOMPACT
&& (offset_in_r0
!= -1))
7274 rtx reg_rtx
= gen_rtx_REG (mode
, reg
);
7276 rtx mem_rtx
= gen_frame_mem (mode
,
7277 gen_rtx_PLUS (Pmode
,
7281 set
= gen_rtx_SET (VOIDmode
, mem_rtx
, reg_rtx
);
7282 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
7287 gcc_assert (entry
->offset
== d_rounding
);
7291 push_regs (&live_regs_mask
, current_function_interrupt
);
7295 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
7296 emit_insn (gen_GOTaddr2picreg ());
7298 if (SHMEDIA_REGS_STACK_ADJUST ())
7300 /* This must NOT go through the PLT, otherwise mach and macl
7301 may be clobbered. */
7302 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7304 ? "__GCC_push_shmedia_regs"
7305 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT
);
7306 emit_insn (gen_shmedia_save_restore_regs_compact
7307 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7310 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7311 emit_insn (gen_toggle_sz ());
7313 target_flags
= save_flags
;
7315 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
7316 stack_pointer_rtx
, 0, NULL
, true);
7317 stack_usage
+= rounded_frame_size (d
) - d_rounding
;
7319 if (frame_pointer_needed
)
7320 frame_insn (GEN_MOV (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7322 if (TARGET_SHCOMPACT
7323 && (crtl
->args
.info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
7325 /* This must NOT go through the PLT, otherwise mach and macl
7326 may be clobbered. */
7327 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7328 "__GCC_shcompact_incoming_args", SFUNC_GOT
);
7329 emit_insn (gen_shcompact_incoming_args ());
7332 /* If we are profiling, make sure no instructions are scheduled before
7333 the call to mcount. Similarly if some call instructions are swapped
7334 before frame related insns, it'll confuse the unwinder because
7335 currently SH has no unwind info for function epilogues. */
7336 if (crtl
->profile
|| flag_exceptions
|| flag_unwind_tables
)
7337 emit_insn (gen_blockage ());
7339 if (flag_stack_usage_info
)
7340 current_function_static_stack_size
= stack_usage
;
7344 sh_expand_epilogue (bool sibcall_p
)
7346 HARD_REG_SET live_regs_mask
;
7350 int save_flags
= target_flags
;
7351 int frame_size
, save_size
;
7352 int fpscr_deferred
= 0;
7353 int e
= sibcall_p
? -1 : 1;
7355 d
= calc_live_regs (&live_regs_mask
);
7358 frame_size
= rounded_frame_size (d
);
7362 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
7364 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
7365 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
7366 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
7368 total_size
= d
+ tregs_space
;
7369 total_size
+= rounded_frame_size (total_size
);
7370 save_size
= total_size
- frame_size
;
7372 /* If adjusting the stack in a single step costs nothing extra, do so.
7373 I.e. either if a single addi is enough, or we need a movi anyway,
7374 and we don't exceed the maximum offset range (the test for the
7375 latter is conservative for simplicity). */
7377 && ! frame_pointer_needed
7378 && (CONST_OK_FOR_I10 (total_size
)
7379 || (! CONST_OK_FOR_I10 (save_size
+ d_rounding
)
7380 && total_size
<= 2044)))
7381 d_rounding
= frame_size
;
7383 frame_size
-= d_rounding
;
7386 if (frame_pointer_needed
)
7388 /* We must avoid scheduling the epilogue with previous basic blocks.
7389 See PR/18032 and PR/40313. */
7390 emit_insn (gen_blockage ());
7391 output_stack_adjust (frame_size
, hard_frame_pointer_rtx
, e
,
7392 &live_regs_mask
, false);
7394 /* We must avoid moving the stack pointer adjustment past code
7395 which reads from the local frame, else an interrupt could
7396 occur after the SP adjustment and clobber data in the local
7398 emit_insn (gen_blockage ());
7399 emit_insn (GEN_MOV (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7401 else if (frame_size
)
7403 /* We must avoid moving the stack pointer adjustment past code
7404 which reads from the local frame, else an interrupt could
7405 occur after the SP adjustment and clobber data in the local
7407 emit_insn (gen_blockage ());
7408 output_stack_adjust (frame_size
, stack_pointer_rtx
, e
,
7409 &live_regs_mask
, false);
7412 if (SHMEDIA_REGS_STACK_ADJUST ())
7414 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7416 ? "__GCC_pop_shmedia_regs"
7417 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT
);
7418 /* This must NOT go through the PLT, otherwise mach and macl
7419 may be clobbered. */
7420 emit_insn (gen_shmedia_save_restore_regs_compact
7421 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7424 /* Pop all the registers. */
7426 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7427 emit_insn (gen_toggle_sz ());
7430 int offset_base
, offset
;
7431 int offset_in_r0
= -1;
7433 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
7434 save_schedule schedule
;
7438 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, d_rounding
);
7439 offset_base
= -entry
[1].offset
+ d_rounding
;
7440 tmp_pnt
= schedule
.temps
;
7441 for (; entry
->mode
!= VOIDmode
; entry
--)
7443 enum machine_mode mode
= (enum machine_mode
) entry
->mode
;
7444 int reg
= entry
->reg
;
7445 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
;
7447 offset
= offset_base
+ entry
->offset
;
7448 reg_rtx
= gen_rtx_REG (mode
, reg
);
7450 mem_rtx
= gen_frame_mem (mode
,
7451 gen_rtx_PLUS (Pmode
,
7455 if (!memory_address_p (mode
, XEXP (mem_rtx
, 0)))
7458 if (HAVE_POST_INCREMENT
7459 && (offset
== offset_in_r0
7460 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
7461 && mem_rtx
== NULL_RTX
)
7462 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
7464 post_inc
= gen_frame_mem (mode
, gen_rtx_POST_INC (Pmode
, r0
));
7466 if (!memory_address_p (mode
, XEXP (post_inc
, 0)))
7467 post_inc
= NULL_RTX
;
7472 if (mem_rtx
!= NULL_RTX
)
7475 if (offset_in_r0
== -1)
7477 emit_move_insn (r0
, GEN_INT (offset
));
7478 offset_in_r0
= offset
;
7480 else if (offset
!= offset_in_r0
)
7485 GEN_INT (offset
- offset_in_r0
)));
7486 offset_in_r0
+= offset
- offset_in_r0
;
7489 if (post_inc
!= NULL_RTX
)
7495 (Pmode
, r0
, stack_pointer_rtx
));
7501 offset_in_r0
+= GET_MODE_SIZE (mode
);
7504 mem_rtx
= gen_frame_mem (mode
, r0
);
7506 mem_rtx
= gen_frame_mem (mode
,
7507 gen_rtx_PLUS (Pmode
,
7511 gcc_assert ((reg
!= PR_REG
&& !SPECIAL_REGISTER_P (reg
))
7512 || mem_rtx
== post_inc
);
7515 if ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
7516 && mem_rtx
!= post_inc
)
7518 emit_move_insn (r0
, mem_rtx
);
7521 else if (TARGET_REGISTER_P (reg
))
7523 rtx tmp_reg
= gen_rtx_REG (mode
, *tmp_pnt
);
7525 /* Give the scheduler a bit of freedom by using up to
7526 MAX_TEMPS registers in a round-robin fashion. */
7527 emit_move_insn (tmp_reg
, mem_rtx
);
7530 tmp_pnt
= schedule
.temps
;
7533 emit_move_insn (reg_rtx
, mem_rtx
);
7536 gcc_assert (entry
->offset
+ offset_base
== d
+ d_rounding
);
7538 else /* ! TARGET_SH5 */
7543 /* For an ISR with RESBANK attribute assigned, don't pop PR
7545 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
)
7546 && !sh_cfun_resbank_handler_p ())
7548 if (!frame_pointer_needed
)
7549 emit_insn (gen_blockage ());
7553 /* Banked registers are popped first to avoid being scheduled in the
7554 delay slot. RTE switches banks before the ds instruction. */
7555 if (current_function_interrupt
)
7557 bool use_movml
= false;
7561 unsigned int count
= 0;
7563 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7564 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
7569 /* Use movml when all banked register are poped. */
7570 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
7574 if (sh_cfun_resbank_handler_p ())
7578 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
7580 /* We must avoid scheduling multiple load insn with another
7582 emit_insn (gen_blockage ());
7583 emit_insn (gen_movml_pop_banked (sp_reg
));
7584 emit_insn (gen_blockage ());
7587 for (i
= LAST_BANKED_REG
; i
>= FIRST_BANKED_REG
; i
--)
7588 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
7591 last_reg
= FIRST_PSEUDO_REGISTER
- LAST_BANKED_REG
- 1;
7594 last_reg
= FIRST_PSEUDO_REGISTER
;
7596 for (i
= 0; i
< last_reg
; i
++)
7598 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
7600 if (j
== FPSCR_REG
&& current_function_interrupt
&& TARGET_FMOVD
7601 && hard_reg_set_intersect_p (live_regs_mask
,
7602 reg_class_contents
[DF_REGS
]))
7604 /* For an ISR with RESBANK attribute assigned, don't pop
7605 following registers, R0-R14, MACH, MACL and GBR. */
7606 else if (j
!= PR_REG
&& TEST_HARD_REG_BIT (live_regs_mask
, j
)
7607 && ! (sh_cfun_resbank_handler_p ()
7608 && ((j
>= FIRST_GENERAL_REG
7609 && j
< LAST_GENERAL_REG
)
7615 if (j
== FIRST_FP_REG
&& fpscr_deferred
)
7619 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7620 emit_insn (gen_toggle_sz ());
7621 target_flags
= save_flags
;
7623 output_stack_adjust (crtl
->args
.pretend_args_size
7624 + save_size
+ d_rounding
7625 + crtl
->args
.info
.stack_regs
* 8,
7626 stack_pointer_rtx
, e
, NULL
, false);
7628 if (crtl
->calls_eh_return
)
7629 emit_insn (GEN_ADD3 (stack_pointer_rtx
, stack_pointer_rtx
,
7630 EH_RETURN_STACKADJ_RTX
));
7632 /* Switch back to the normal stack if necessary. */
7633 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
)))
7634 emit_insn (gen_sp_switch_2 ());
7636 /* Tell flow the insn that pops PR isn't dead. */
7637 /* PR_REG will never be live in SHmedia mode, and we don't need to
7638 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7639 by the return pattern. */
7640 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
7641 emit_use (gen_rtx_REG (SImode
, PR_REG
));
7644 static int sh_need_epilogue_known
= 0;
7647 sh_need_epilogue (void)
7649 if (! sh_need_epilogue_known
)
7654 sh_expand_epilogue (0);
7655 epilogue
= get_insns ();
7657 sh_need_epilogue_known
= (epilogue
== NULL
? -1 : 1);
7659 return sh_need_epilogue_known
> 0;
7662 /* Emit code to change the current function's return address to RA.
7663 TEMP is available as a scratch register, if needed. */
7666 sh_set_return_address (rtx ra
, rtx tmp
)
7668 HARD_REG_SET live_regs_mask
;
7670 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
7673 d
= calc_live_regs (&live_regs_mask
);
7675 /* If pr_reg isn't life, we can set it (or the register given in
7676 sh_media_register_for_return) directly. */
7677 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
7683 int rr_regno
= sh_media_register_for_return ();
7688 rr
= gen_rtx_REG (DImode
, rr_regno
);
7691 rr
= gen_rtx_REG (SImode
, pr_reg
);
7693 emit_insn (GEN_MOV (rr
, ra
));
7694 /* Tell flow the register for return isn't dead. */
7702 save_schedule schedule
;
7705 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, 0);
7706 offset
= entry
[1].offset
;
7707 for (; entry
->mode
!= VOIDmode
; entry
--)
7708 if (entry
->reg
== pr_reg
)
7711 /* We can't find pr register. */
7715 offset
= entry
->offset
- offset
;
7716 pr_offset
= (rounded_frame_size (d
) + offset
7717 + SHMEDIA_REGS_STACK_ADJUST ());
7720 pr_offset
= rounded_frame_size (d
);
7722 emit_insn (GEN_MOV (tmp
, GEN_INT (pr_offset
)));
7724 if (frame_pointer_needed
)
7725 emit_insn (GEN_ADD3 (tmp
, tmp
, hard_frame_pointer_rtx
));
7727 emit_insn (GEN_ADD3 (tmp
, tmp
, stack_pointer_rtx
));
7729 tmp
= gen_frame_mem (Pmode
, tmp
);
7730 emit_insn (GEN_MOV (tmp
, ra
));
7731 /* Tell this store isn't dead. */
7735 /* Clear variables at function end. */
7738 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
7739 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
7741 sh_need_epilogue_known
= 0;
7745 sh_builtin_saveregs (void)
7747 /* First unnamed integer register. */
7748 int first_intreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
];
7749 /* Number of integer registers we need to save. */
7750 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
7751 /* First unnamed SFmode float reg */
7752 int first_floatreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_FLOAT
];
7753 /* Number of SFmode float regs to save. */
7754 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
7757 alias_set_type alias_set
;
7763 int pushregs
= n_intregs
;
7765 while (pushregs
< NPARM_REGS (SImode
) - 1
7766 && (CALL_COOKIE_INT_REG_GET
7767 (crtl
->args
.info
.call_cookie
,
7768 NPARM_REGS (SImode
) - pushregs
)
7771 crtl
->args
.info
.call_cookie
7772 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
7777 if (pushregs
== NPARM_REGS (SImode
))
7778 crtl
->args
.info
.call_cookie
7779 |= (CALL_COOKIE_INT_REG (0, 1)
7780 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
7782 crtl
->args
.info
.call_cookie
7783 |= CALL_COOKIE_STACKSEQ (pushregs
);
7785 crtl
->args
.pretend_args_size
+= 8 * n_intregs
;
7787 if (TARGET_SHCOMPACT
)
7791 if (! TARGET_SH2E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
7793 error ("__builtin_saveregs not supported by this subtarget");
7800 /* Allocate block of memory for the regs. */
7801 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7802 Or can assign_stack_local accept a 0 SIZE argument? */
7803 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
7806 regbuf
= gen_frame_mem (BLKmode
, gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
7807 else if (n_floatregs
& 1)
7811 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
7812 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
7813 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
7814 regbuf
= change_address (regbuf
, BLKmode
, addr
);
7816 else if (STACK_BOUNDARY
< 64 && TARGET_FPU_DOUBLE
&& n_floatregs
)
7820 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
7821 addr
= copy_to_mode_reg (Pmode
, plus_constant (XEXP (regbuf
, 0), 4));
7822 mask
= copy_to_mode_reg (Pmode
, GEN_INT (-8));
7823 emit_insn (gen_andsi3 (addr
, addr
, mask
));
7824 regbuf
= change_address (regbuf
, BLKmode
, addr
);
7827 regbuf
= assign_stack_local (BLKmode
, bufsize
, TARGET_FPU_DOUBLE
? 64 : 0);
7828 alias_set
= get_varargs_alias_set ();
7829 set_mem_alias_set (regbuf
, alias_set
);
7832 This is optimized to only save the regs that are necessary. Explicitly
7833 named args need not be saved. */
7835 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
7836 adjust_address (regbuf
, BLKmode
,
7837 n_floatregs
* UNITS_PER_WORD
),
7841 /* Return the address of the regbuf. */
7842 return XEXP (regbuf
, 0);
7845 This is optimized to only save the regs that are necessary. Explicitly
7846 named args need not be saved.
7847 We explicitly build a pointer to the buffer because it halves the insn
7848 count when not optimizing (otherwise the pointer is built for each reg
7850 We emit the moves in reverse order so that we can use predecrement. */
7852 fpregs
= copy_to_mode_reg (Pmode
,
7853 plus_constant (XEXP (regbuf
, 0),
7854 n_floatregs
* UNITS_PER_WORD
));
7855 if (TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
7858 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
7860 emit_insn (gen_addsi3 (fpregs
, fpregs
,
7861 GEN_INT (-2 * UNITS_PER_WORD
)));
7862 mem
= change_address (regbuf
, DFmode
, fpregs
);
7863 emit_move_insn (mem
,
7864 gen_rtx_REG (DFmode
, BASE_ARG_REG (DFmode
) + regno
));
7866 regno
= first_floatreg
;
7869 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
7870 mem
= change_address (regbuf
, SFmode
, fpregs
);
7871 emit_move_insn (mem
,
7872 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
7873 - (TARGET_LITTLE_ENDIAN
!= 0)));
7877 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
7881 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
7882 mem
= change_address (regbuf
, SFmode
, fpregs
);
7883 emit_move_insn (mem
,
7884 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
7887 /* Return the address of the regbuf. */
7888 return XEXP (regbuf
, 0);
7891 /* Define the `__builtin_va_list' type for the ABI. */
7894 sh_build_builtin_va_list (void)
7896 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
7897 tree record
, type_decl
;
7899 if (TARGET_SH5
|| (! TARGET_SH2E
&& ! TARGET_SH4
)
7900 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
7901 return ptr_type_node
;
7903 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
7904 type_decl
= build_decl (BUILTINS_LOCATION
,
7905 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
7907 f_next_o
= build_decl (BUILTINS_LOCATION
,
7908 FIELD_DECL
, get_identifier ("__va_next_o"),
7910 f_next_o_limit
= build_decl (BUILTINS_LOCATION
,
7912 get_identifier ("__va_next_o_limit"),
7914 f_next_fp
= build_decl (BUILTINS_LOCATION
,
7915 FIELD_DECL
, get_identifier ("__va_next_fp"),
7917 f_next_fp_limit
= build_decl (BUILTINS_LOCATION
,
7919 get_identifier ("__va_next_fp_limit"),
7921 f_next_stack
= build_decl (BUILTINS_LOCATION
,
7922 FIELD_DECL
, get_identifier ("__va_next_stack"),
7925 DECL_FIELD_CONTEXT (f_next_o
) = record
;
7926 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
7927 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
7928 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
7929 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
7931 TYPE_STUB_DECL (record
) = type_decl
;
7932 TYPE_NAME (record
) = type_decl
;
7933 TYPE_FIELDS (record
) = f_next_o
;
7934 DECL_CHAIN (f_next_o
) = f_next_o_limit
;
7935 DECL_CHAIN (f_next_o_limit
) = f_next_fp
;
7936 DECL_CHAIN (f_next_fp
) = f_next_fp_limit
;
7937 DECL_CHAIN (f_next_fp_limit
) = f_next_stack
;
7939 layout_type (record
);
7944 /* Implement `va_start' for varargs and stdarg. */
7947 sh_va_start (tree valist
, rtx nextarg
)
7949 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
7950 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
7956 expand_builtin_saveregs ();
7957 std_expand_builtin_va_start (valist
, nextarg
);
7961 if ((! TARGET_SH2E
&& ! TARGET_SH4
)
7962 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
7964 std_expand_builtin_va_start (valist
, nextarg
);
7968 f_next_o
= TYPE_FIELDS (va_list_type_node
);
7969 f_next_o_limit
= DECL_CHAIN (f_next_o
);
7970 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
7971 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
7972 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
7974 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
7976 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
7977 valist
, f_next_o_limit
, NULL_TREE
);
7978 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
,
7980 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
7981 valist
, f_next_fp_limit
, NULL_TREE
);
7982 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
7983 valist
, f_next_stack
, NULL_TREE
);
7985 /* Call __builtin_saveregs. */
7986 u
= make_tree (sizetype
, expand_builtin_saveregs ());
7987 u
= fold_convert (ptr_type_node
, u
);
7988 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
7989 TREE_SIDE_EFFECTS (t
) = 1;
7990 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7992 nfp
= crtl
->args
.info
.arg_count
[SH_ARG_FLOAT
];
7997 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nfp
);
7998 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
7999 TREE_SIDE_EFFECTS (t
) = 1;
8000 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8002 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
8003 TREE_SIDE_EFFECTS (t
) = 1;
8004 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8006 nint
= crtl
->args
.info
.arg_count
[SH_ARG_INT
];
8011 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nint
);
8012 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
8013 TREE_SIDE_EFFECTS (t
) = 1;
8014 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8016 u
= make_tree (ptr_type_node
, nextarg
);
8017 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
8018 TREE_SIDE_EFFECTS (t
) = 1;
8019 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8022 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
8023 member, return it. */
8025 find_sole_member (tree type
)
8027 tree field
, member
= NULL_TREE
;
8029 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8031 if (TREE_CODE (field
) != FIELD_DECL
)
8033 if (!DECL_SIZE (field
))
8035 if (integer_zerop (DECL_SIZE (field
)))
8043 /* Implement `va_arg'. */
8046 sh_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
8047 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8049 HOST_WIDE_INT size
, rsize
;
8050 tree tmp
, pptr_type_node
;
8051 tree addr
, lab_over
= NULL
, result
= NULL
;
8055 if (!VOID_TYPE_P (type
))
8056 pass_by_ref
= targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
);
8058 pass_by_ref
= false;
8061 type
= build_pointer_type (type
);
8063 size
= int_size_in_bytes (type
);
8064 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
8065 pptr_type_node
= build_pointer_type (ptr_type_node
);
8067 if (! TARGET_SH5
&& (TARGET_SH2E
|| TARGET_SH4
)
8068 && ! (TARGET_HITACHI
|| sh_cfun_attr_renesas_p ()))
8070 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
8071 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
8076 f_next_o
= TYPE_FIELDS (va_list_type_node
);
8077 f_next_o_limit
= DECL_CHAIN (f_next_o
);
8078 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
8079 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
8080 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
8082 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
8084 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
8085 valist
, f_next_o_limit
, NULL_TREE
);
8086 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
8087 valist
, f_next_fp
, NULL_TREE
);
8088 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
8089 valist
, f_next_fp_limit
, NULL_TREE
);
8090 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
8091 valist
, f_next_stack
, NULL_TREE
);
8093 /* Structures with a single member with a distinct mode are passed
8094 like their member. This is relevant if the latter has a REAL_TYPE
8095 or COMPLEX_TYPE type. */
8097 while (TREE_CODE (eff_type
) == RECORD_TYPE
8098 && (member
= find_sole_member (eff_type
))
8099 && (TREE_CODE (TREE_TYPE (member
)) == REAL_TYPE
8100 || TREE_CODE (TREE_TYPE (member
)) == COMPLEX_TYPE
8101 || TREE_CODE (TREE_TYPE (member
)) == RECORD_TYPE
))
8103 tree field_type
= TREE_TYPE (member
);
8105 if (TYPE_MODE (eff_type
) == TYPE_MODE (field_type
))
8106 eff_type
= field_type
;
8109 gcc_assert ((TYPE_ALIGN (eff_type
)
8110 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type
)))
8111 || (TYPE_ALIGN (eff_type
)
8112 > GET_MODE_BITSIZE (TYPE_MODE (field_type
))));
8117 if (TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8119 pass_as_float
= ((TREE_CODE (eff_type
) == REAL_TYPE
&& size
<= 8)
8120 || (TREE_CODE (eff_type
) == COMPLEX_TYPE
8121 && TREE_CODE (TREE_TYPE (eff_type
)) == REAL_TYPE
8126 pass_as_float
= (TREE_CODE (eff_type
) == REAL_TYPE
&& size
== 4);
8129 addr
= create_tmp_var (pptr_type_node
, NULL
);
8130 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
8131 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
8133 valist
= build_simple_mem_ref (addr
);
8137 tree next_fp_tmp
= create_tmp_var (TREE_TYPE (f_next_fp
), NULL
);
8139 bool is_double
= size
== 8 && TREE_CODE (eff_type
) == REAL_TYPE
;
8141 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_fp
));
8142 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8144 gimplify_assign (unshare_expr (next_fp_tmp
), valist
, pre_p
);
8145 tmp
= next_fp_limit
;
8146 if (size
> 4 && !is_double
)
8147 tmp
= fold_build_pointer_plus_hwi (unshare_expr (tmp
), 4 - size
);
8148 tmp
= build2 (GE_EXPR
, boolean_type_node
,
8149 unshare_expr (next_fp_tmp
), unshare_expr (tmp
));
8150 cmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
8151 build1 (GOTO_EXPR
, void_type_node
,
8152 unshare_expr (lab_false
)), NULL_TREE
);
8154 gimplify_and_add (cmp
, pre_p
);
8156 if (TYPE_ALIGN (eff_type
) > BITS_PER_WORD
8157 || (is_double
|| size
== 16))
8159 tmp
= fold_convert (sizetype
, next_fp_tmp
);
8160 tmp
= build2 (BIT_AND_EXPR
, sizetype
, tmp
,
8161 size_int (UNITS_PER_WORD
));
8162 tmp
= fold_build_pointer_plus (unshare_expr (next_fp_tmp
), tmp
);
8163 gimplify_assign (unshare_expr (next_fp_tmp
), tmp
, pre_p
);
8166 gimplify_and_add (cmp
, pre_p
);
8168 #ifdef FUNCTION_ARG_SCmode_WART
8169 if (TYPE_MODE (eff_type
) == SCmode
8170 && TARGET_SH4
&& TARGET_LITTLE_ENDIAN
)
8172 tree subtype
= TREE_TYPE (eff_type
);
8176 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
8177 imag
= get_initialized_tmp_var (imag
, pre_p
, NULL
);
8180 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
8181 real
= get_initialized_tmp_var (real
, pre_p
, NULL
);
8183 result
= build2 (COMPLEX_EXPR
, eff_type
, real
, imag
);
8184 if (type
!= eff_type
)
8185 result
= build1 (VIEW_CONVERT_EXPR
, type
, result
);
8186 result
= get_initialized_tmp_var (result
, pre_p
, NULL
);
8188 #endif /* FUNCTION_ARG_SCmode_WART */
8190 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
8191 gimplify_and_add (tmp
, pre_p
);
8193 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
8194 gimplify_and_add (tmp
, pre_p
);
8196 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
8197 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8198 gimplify_assign (unshare_expr (next_fp_tmp
),
8199 unshare_expr (valist
), pre_p
);
8201 gimplify_assign (unshare_expr (valist
),
8202 unshare_expr (next_fp_tmp
), post_p
);
8203 valist
= next_fp_tmp
;
8207 tmp
= fold_build_pointer_plus_hwi (unshare_expr (next_o
), rsize
);
8208 tmp
= build2 (GT_EXPR
, boolean_type_node
, tmp
,
8209 unshare_expr (next_o_limit
));
8210 tmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
8211 build1 (GOTO_EXPR
, void_type_node
,
8212 unshare_expr (lab_false
)),
8214 gimplify_and_add (tmp
, pre_p
);
8216 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_o
));
8217 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8219 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
8220 gimplify_and_add (tmp
, pre_p
);
8222 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
8223 gimplify_and_add (tmp
, pre_p
);
8225 if (size
> 4 && ! (TARGET_SH4
|| TARGET_SH2A
))
8226 gimplify_assign (unshare_expr (next_o
),
8227 unshare_expr (next_o_limit
), pre_p
);
8229 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
8230 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8235 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
8236 gimplify_and_add (tmp
, pre_p
);
8240 /* ??? In va-sh.h, there had been code to make values larger than
8241 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8243 tmp
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, NULL
);
8246 gimplify_assign (result
, tmp
, pre_p
);
8247 result
= build1 (NOP_EXPR
, TREE_TYPE (result
), result
);
8248 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
8249 gimplify_and_add (tmp
, pre_p
);
8255 result
= build_va_arg_indirect_ref (result
);
8260 /* 64 bit floating points memory transfers are paired single precision loads
8261 or store. So DWARF information needs fixing in little endian (unless
8262 PR=SZ=1 in FPSCR). */
8264 sh_dwarf_register_span (rtx reg
)
8266 unsigned regno
= REGNO (reg
);
8268 if (WORDS_BIG_ENDIAN
|| GET_MODE (reg
) != DFmode
)
8272 gen_rtx_PARALLEL (VOIDmode
,
8274 gen_rtx_REG (SFmode
, regno
+ 1),
8275 gen_rtx_REG (SFmode
, regno
)));
8278 static enum machine_mode
8279 sh_promote_function_mode (const_tree type
, enum machine_mode mode
,
8280 int *punsignedp
, const_tree funtype
,
8283 if (sh_promote_prototypes (funtype
))
8284 return promote_mode (type
, mode
, punsignedp
);
8286 return default_promote_function_mode (type
, mode
, punsignedp
, funtype
,
8291 sh_promote_prototypes (const_tree type
)
8297 return ! sh_attr_renesas_p (type
);
8300 /* Whether an argument must be passed by reference. On SHcompact, we
8301 pretend arguments wider than 32-bits that would have been passed in
8302 registers are passed by reference, so that an SHmedia trampoline
8303 loads them into the full 64-bits registers. */
8306 shcompact_byref (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8307 const_tree type
, bool named
)
8309 unsigned HOST_WIDE_INT size
;
8312 size
= int_size_in_bytes (type
);
8314 size
= GET_MODE_SIZE (mode
);
8316 if (cum
->arg_count
[SH_ARG_INT
] < NPARM_REGS (SImode
)
8318 || GET_SH_ARG_CLASS (mode
) == SH_ARG_INT
8319 || (GET_SH_ARG_CLASS (mode
) == SH_ARG_FLOAT
8320 && cum
->arg_count
[SH_ARG_FLOAT
] >= NPARM_REGS (SFmode
)))
8322 && !SHCOMPACT_FORCE_ON_STACK (mode
, type
)
8323 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum
, mode
, type
, named
))
8330 sh_pass_by_reference (cumulative_args_t cum_v
, enum machine_mode mode
,
8331 const_tree type
, bool named
)
8333 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8335 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
8338 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8339 wants to know about pass-by-reference semantics for incoming
8344 if (TARGET_SHCOMPACT
)
8346 cum
->byref
= shcompact_byref (cum
, mode
, type
, named
);
8347 return cum
->byref
!= 0;
8354 sh_callee_copies (cumulative_args_t cum
, enum machine_mode mode
,
8355 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8357 /* ??? How can it possibly be correct to return true only on the
8358 caller side of the equation? Is there someplace else in the
8359 sh backend that's magically producing the copies? */
8360 return (get_cumulative_args (cum
)->outgoing
8361 && ((mode
== BLKmode
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
))
8362 % SH_MIN_ALIGN_FOR_CALLEE_COPY
== 0));
8366 sh_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
8367 tree type
, bool named ATTRIBUTE_UNUSED
)
8369 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8373 && PASS_IN_REG_P (*cum
, mode
, type
)
8374 && !(TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8375 && (ROUND_REG (*cum
, mode
)
8377 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
8378 : ROUND_ADVANCE (int_size_in_bytes (type
)))
8379 > NPARM_REGS (mode
)))
8380 words
= NPARM_REGS (mode
) - ROUND_REG (*cum
, mode
);
8382 else if (!TARGET_SHCOMPACT
8383 && SH5_WOULD_BE_PARTIAL_NREGS (*cum
, mode
, type
, named
))
8384 words
= NPARM_REGS (SImode
) - cum
->arg_count
[SH_ARG_INT
];
8386 return words
* UNITS_PER_WORD
;
8390 /* Define where to put the arguments to a function.
8391 Value is zero to push the argument on the stack,
8392 or a hard register in which to store the argument.
8394 MODE is the argument's machine mode.
8395 TYPE is the data type of the argument (as a tree).
8396 This is null for libcalls where that information may
8398 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8399 the preceding args and about the function being called.
8400 NAMED is nonzero if this argument is a named parameter
8401 (otherwise it is an extra parameter matching an ellipsis).
8403 On SH the first args are normally in registers
8404 and the rest are pushed. Any arg that starts within the first
8405 NPARM_REGS words is at least partially passed in a register unless
8406 its data type forbids. */
8409 sh_function_arg (cumulative_args_t ca_v
, enum machine_mode mode
,
8410 const_tree type
, bool named
)
8412 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
8414 if (! TARGET_SH5
&& mode
== VOIDmode
)
8415 return GEN_INT (ca
->renesas_abi
? 1 : 0);
8418 && PASS_IN_REG_P (*ca
, mode
, type
)
8419 && (named
|| ! (TARGET_HITACHI
|| ca
->renesas_abi
)))
8423 if (mode
== SCmode
&& TARGET_SH4
&& TARGET_LITTLE_ENDIAN
8424 && (! FUNCTION_ARG_SCmode_WART
|| (ROUND_REG (*ca
, mode
) & 1)))
8426 rtx r1
= gen_rtx_EXPR_LIST (VOIDmode
,
8427 gen_rtx_REG (SFmode
,
8429 + (ROUND_REG (*ca
, mode
) ^ 1)),
8431 rtx r2
= gen_rtx_EXPR_LIST (VOIDmode
,
8432 gen_rtx_REG (SFmode
,
8434 + ((ROUND_REG (*ca
, mode
) + 1) ^ 1)),
8436 return gen_rtx_PARALLEL(SCmode
, gen_rtvec(2, r1
, r2
));
8439 /* If the alignment of a DF value causes an SF register to be
8440 skipped, we will use that skipped register for the next SF
8442 if ((TARGET_HITACHI
|| ca
->renesas_abi
)
8443 && ca
->free_single_fp_reg
8445 return gen_rtx_REG (mode
, ca
->free_single_fp_reg
);
8447 regno
= (BASE_ARG_REG (mode
) + ROUND_REG (*ca
, mode
))
8448 ^ (mode
== SFmode
&& TARGET_SH4
8449 && TARGET_LITTLE_ENDIAN
!= 0
8450 && ! TARGET_HITACHI
&& ! ca
->renesas_abi
);
8451 return gen_rtx_REG (mode
, regno
);
8457 if (mode
== VOIDmode
&& TARGET_SHCOMPACT
)
8458 return GEN_INT (ca
->call_cookie
);
8460 /* The following test assumes unnamed arguments are promoted to
8462 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
8463 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
, ca
->free_single_fp_reg
);
8465 if ((GET_SH_ARG_CLASS (mode
) == SH_ARG_FLOAT
)
8466 && (named
|| ! ca
->prototype_p
)
8467 && ca
->arg_count
[(int) SH_ARG_FLOAT
] < NPARM_REGS (SFmode
))
8469 if (! ca
->prototype_p
&& TARGET_SHMEDIA
)
8470 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca
, mode
);
8472 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
,
8474 + ca
->arg_count
[(int) SH_ARG_FLOAT
]);
8477 if (ca
->arg_count
[(int) SH_ARG_INT
] < NPARM_REGS (SImode
)
8478 && (! TARGET_SHCOMPACT
8479 || (! SHCOMPACT_FORCE_ON_STACK (mode
, type
)
8480 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca
, mode
,
8483 return gen_rtx_REG (mode
, (FIRST_PARM_REG
8484 + ca
->arg_count
[(int) SH_ARG_INT
]));
8493 /* Update the data in CUM to advance over an argument
8494 of mode MODE and data type TYPE.
8495 (TYPE is null for libcalls where that information may not be
8499 sh_function_arg_advance (cumulative_args_t ca_v
, enum machine_mode mode
,
8500 const_tree type
, bool named
)
8502 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
8506 else if (TARGET_SH5
)
8508 const_tree type2
= (ca
->byref
&& type
8511 enum machine_mode mode2
= (ca
->byref
&& type
8514 int dwords
= ((ca
->byref
8517 ? int_size_in_bytes (type2
)
8518 : GET_MODE_SIZE (mode2
)) + 7) / 8;
8519 int numregs
= MIN (dwords
, NPARM_REGS (SImode
)
8520 - ca
->arg_count
[(int) SH_ARG_INT
]);
8524 ca
->arg_count
[(int) SH_ARG_INT
] += numregs
;
8525 if (TARGET_SHCOMPACT
8526 && SHCOMPACT_FORCE_ON_STACK (mode2
, type2
))
8529 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
8531 /* N.B. We want this also for outgoing. */
8532 ca
->stack_regs
+= numregs
;
8537 ca
->stack_regs
+= numregs
;
8538 ca
->byref_regs
+= numregs
;
8542 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
8546 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
8549 else if (dwords
> numregs
)
8551 int pushregs
= numregs
;
8553 if (TARGET_SHCOMPACT
)
8554 ca
->stack_regs
+= numregs
;
8555 while (pushregs
< NPARM_REGS (SImode
) - 1
8556 && (CALL_COOKIE_INT_REG_GET
8558 NPARM_REGS (SImode
) - pushregs
)
8562 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
8566 if (numregs
== NPARM_REGS (SImode
))
8568 |= CALL_COOKIE_INT_REG (0, 1)
8569 | CALL_COOKIE_STACKSEQ (numregs
- 1);
8572 |= CALL_COOKIE_STACKSEQ (numregs
);
8575 if (GET_SH_ARG_CLASS (mode2
) == SH_ARG_FLOAT
8576 && (named
|| ! ca
->prototype_p
))
8578 if (mode2
== SFmode
&& ca
->free_single_fp_reg
)
8579 ca
->free_single_fp_reg
= 0;
8580 else if (ca
->arg_count
[(int) SH_ARG_FLOAT
]
8581 < NPARM_REGS (SFmode
))
8584 = MIN ((GET_MODE_SIZE (mode2
) + 7) / 8 * 2,
8586 - ca
->arg_count
[(int) SH_ARG_FLOAT
]);
8588 ca
->arg_count
[(int) SH_ARG_FLOAT
] += numfpregs
;
8590 if (TARGET_SHCOMPACT
&& ! ca
->prototype_p
)
8592 if (ca
->outgoing
&& numregs
> 0)
8596 |= (CALL_COOKIE_INT_REG
8597 (ca
->arg_count
[(int) SH_ARG_INT
]
8598 - numregs
+ ((numfpregs
- 2) / 2),
8599 4 + (ca
->arg_count
[(int) SH_ARG_FLOAT
]
8602 while (numfpregs
-= 2);
8604 else if (mode2
== SFmode
&& (named
)
8605 && (ca
->arg_count
[(int) SH_ARG_FLOAT
]
8606 < NPARM_REGS (SFmode
)))
8607 ca
->free_single_fp_reg
8608 = FIRST_FP_PARM_REG
- numfpregs
8609 + ca
->arg_count
[(int) SH_ARG_FLOAT
] + 1;
8615 if ((TARGET_HITACHI
|| ca
->renesas_abi
) && TARGET_FPU_DOUBLE
)
8617 /* Note that we've used the skipped register. */
8618 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
8620 ca
->free_single_fp_reg
= 0;
8623 /* When we have a DF after an SF, there's an SF register that get
8624 skipped in order to align the DF value. We note this skipped
8625 register, because the next SF value will use it, and not the
8626 SF that follows the DF. */
8628 && ROUND_REG (*ca
, DFmode
) != ROUND_REG (*ca
, SFmode
))
8630 ca
->free_single_fp_reg
= (ROUND_REG (*ca
, SFmode
)
8631 + BASE_ARG_REG (mode
));
8635 if (! ((TARGET_SH4
|| TARGET_SH2A
) || ca
->renesas_abi
)
8636 || PASS_IN_REG_P (*ca
, mode
, type
))
8637 (ca
->arg_count
[(int) GET_SH_ARG_CLASS (mode
)]
8638 = (ROUND_REG (*ca
, mode
)
8640 ? ROUND_ADVANCE (int_size_in_bytes (type
))
8641 : ROUND_ADVANCE (GET_MODE_SIZE (mode
)))));
8644 /* The Renesas calling convention doesn't quite fit into this scheme since
8645 the address is passed like an invisible argument, but one that is always
8646 passed in memory. */
8648 sh_struct_value_rtx (tree fndecl
, int incoming ATTRIBUTE_UNUSED
)
8650 if (TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
8652 return gen_rtx_REG (Pmode
, 2);
8655 /* Worker function for TARGET_FUNCTION_VALUE.
8657 For the SH, this is like LIBCALL_VALUE, except that we must change the
8658 mode like PROMOTE_MODE does.
8659 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8660 tested here has to be kept in sync with the one in explow.c:promote_mode.
8664 sh_function_value (const_tree valtype
,
8665 const_tree fn_decl_or_type
,
8666 bool outgoing ATTRIBUTE_UNUSED
)
8669 && !DECL_P (fn_decl_or_type
))
8670 fn_decl_or_type
= NULL
;
8672 return gen_rtx_REG (
8673 ((GET_MODE_CLASS (TYPE_MODE (valtype
)) == MODE_INT
8674 && GET_MODE_SIZE (TYPE_MODE (valtype
)) < 4
8675 && (TREE_CODE (valtype
) == INTEGER_TYPE
8676 || TREE_CODE (valtype
) == ENUMERAL_TYPE
8677 || TREE_CODE (valtype
) == BOOLEAN_TYPE
8678 || TREE_CODE (valtype
) == REAL_TYPE
8679 || TREE_CODE (valtype
) == OFFSET_TYPE
))
8680 && sh_promote_prototypes (fn_decl_or_type
)
8681 ? (TARGET_SHMEDIA64
? DImode
: SImode
) : TYPE_MODE (valtype
)),
8682 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype
)));
8685 /* Worker function for TARGET_LIBCALL_VALUE. */
8688 sh_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
8690 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG (mode
));
8693 /* Return true if N is a possible register number of function value. */
8696 sh_function_value_regno_p (const unsigned int regno
)
8698 return ((regno
) == FIRST_RET_REG
8699 || (TARGET_SH2E
&& (regno
) == FIRST_FP_RET_REG
)
8700 || (TARGET_SHMEDIA_FPU
&& (regno
) == FIRST_FP_RET_REG
));
8703 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8706 sh_return_in_memory (const_tree type
, const_tree fndecl
)
8710 if (TYPE_MODE (type
) == BLKmode
)
8711 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)) > 8;
8713 return GET_MODE_SIZE (TYPE_MODE (type
)) > 8;
8717 return (TYPE_MODE (type
) == BLKmode
8718 || ((TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
8719 && TREE_CODE (type
) == RECORD_TYPE
));
8723 /* We actually emit the code in sh_expand_prologue. We used to use
8724 a static variable to flag that we need to emit this code, but that
8725 doesn't when inlining, when functions are deferred and then emitted
8726 later. Fortunately, we already have two flags that are part of struct
8727 function that tell if a function uses varargs or stdarg. */
8729 sh_setup_incoming_varargs (cumulative_args_t ca
,
8730 enum machine_mode mode
,
8732 int *pretend_arg_size
,
8733 int second_time ATTRIBUTE_UNUSED
)
8735 gcc_assert (cfun
->stdarg
);
8736 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
8738 int named_parm_regs
, anon_parm_regs
;
8740 named_parm_regs
= (ROUND_REG (*get_cumulative_args (ca
), mode
)
8742 ? ROUND_ADVANCE (int_size_in_bytes (type
))
8743 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))));
8744 anon_parm_regs
= NPARM_REGS (SImode
) - named_parm_regs
;
8745 if (anon_parm_regs
> 0)
8746 *pretend_arg_size
= anon_parm_regs
* 4;
8751 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
8757 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v
)
8759 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
8761 return ! (TARGET_HITACHI
|| ca
->renesas_abi
) && ! TARGET_SH5
;
8765 /* Define the offset between two registers, one to be eliminated, and
8766 the other its replacement, at the start of a routine. */
8769 initial_elimination_offset (int from
, int to
)
8772 int regs_saved_rounding
= 0;
8773 int total_saved_regs_space
;
8774 int total_auto_space
;
8775 int save_flags
= target_flags
;
8777 HARD_REG_SET live_regs_mask
;
8779 shmedia_space_reserved_for_target_registers
= false;
8780 regs_saved
= calc_live_regs (&live_regs_mask
);
8781 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
8783 if (shmedia_reserve_space_for_target_registers_p (regs_saved
, &live_regs_mask
))
8785 shmedia_space_reserved_for_target_registers
= true;
8786 regs_saved
+= shmedia_target_regs_stack_adjust (&live_regs_mask
);
8789 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
8790 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
8791 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
8793 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
8794 copy_flags
= target_flags
;
8795 target_flags
= save_flags
;
8797 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
8799 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8800 return total_saved_regs_space
+ total_auto_space
8801 + crtl
->args
.info
.byref_regs
* 8;
8803 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8804 return total_saved_regs_space
+ total_auto_space
8805 + crtl
->args
.info
.byref_regs
* 8;
8807 /* Initial gap between fp and sp is 0. */
8808 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8811 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8812 return rounded_frame_size (0);
8814 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8815 return rounded_frame_size (0);
8817 gcc_assert (from
== RETURN_ADDRESS_POINTER_REGNUM
8818 && (to
== HARD_FRAME_POINTER_REGNUM
8819 || to
== STACK_POINTER_REGNUM
));
8822 int n
= total_saved_regs_space
;
8823 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
8824 save_schedule schedule
;
8827 n
+= total_auto_space
;
8829 /* If it wasn't saved, there's not much we can do. */
8830 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
8833 target_flags
= copy_flags
;
8835 sh5_schedule_saves (&live_regs_mask
, &schedule
, n
);
8836 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
8837 if (entry
->reg
== pr_reg
)
8839 target_flags
= save_flags
;
8840 return entry
->offset
;
8845 return total_auto_space
;
8848 /* Parse the -mfixed-range= option string. */
8850 sh_fix_range (const char *const_str
)
8853 char *str
, *dash
, *comma
;
8855 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8856 REG2 are either register names or register numbers. The effect
8857 of this option is to mark the registers in the range from REG1 to
8858 REG2 as ``fixed'' so they won't be used by the compiler. */
8860 i
= strlen (const_str
);
8861 str
= (char *) alloca (i
+ 1);
8862 memcpy (str
, const_str
, i
+ 1);
8866 dash
= strchr (str
, '-');
8869 warning (0, "value of -mfixed-range must have form REG1-REG2");
8873 comma
= strchr (dash
+ 1, ',');
8877 first
= decode_reg_name (str
);
8880 warning (0, "unknown register name: %s", str
);
8884 last
= decode_reg_name (dash
+ 1);
8887 warning (0, "unknown register name: %s", dash
+ 1);
8895 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
8899 for (i
= first
; i
<= last
; ++i
)
8900 fixed_regs
[i
] = call_used_regs
[i
] = 1;
8910 /* Insert any deferred function attributes from earlier pragmas. */
8912 sh_insert_attributes (tree node
, tree
*attributes
)
8916 if (TREE_CODE (node
) != FUNCTION_DECL
)
8919 /* We are only interested in fields. */
8923 /* Append the attributes to the deferred attributes. */
8924 *sh_deferred_function_attributes_tail
= *attributes
;
8925 attrs
= sh_deferred_function_attributes
;
8929 /* Some attributes imply or require the interrupt attribute. */
8930 if (!lookup_attribute ("interrupt_handler", attrs
)
8931 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node
)))
8933 /* If we have a trapa_handler, but no interrupt_handler attribute,
8934 insert an interrupt_handler attribute. */
8935 if (lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
)
8936 /* We can't use sh_pr_interrupt here because that's not in the
8939 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE
, attrs
);
8940 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8941 if the interrupt attribute is missing, we ignore the attribute
8943 else if (lookup_attribute ("sp_switch", attrs
)
8944 || lookup_attribute ("trap_exit", attrs
)
8945 || lookup_attribute ("nosave_low_regs", attrs
)
8946 || lookup_attribute ("resbank", attrs
))
8950 for (tail
= attributes
; attrs
; attrs
= TREE_CHAIN (attrs
))
8952 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs
))
8953 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs
))
8954 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs
))
8955 || is_attribute_p ("resbank", TREE_PURPOSE (attrs
)))
8956 warning (OPT_Wattributes
,
8957 "%qE attribute only applies to interrupt functions",
8958 TREE_PURPOSE (attrs
));
8961 *tail
= tree_cons (TREE_PURPOSE (attrs
), NULL_TREE
,
8963 tail
= &TREE_CHAIN (*tail
);
8966 attrs
= *attributes
;
8970 /* Install the processed list. */
8971 *attributes
= attrs
;
8973 /* Clear deferred attributes. */
8974 sh_deferred_function_attributes
= NULL_TREE
;
8975 sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
8980 /* Supported attributes:
8982 interrupt_handler -- specifies this function is an interrupt handler.
8984 trapa_handler - like above, but don't save all registers.
8986 sp_switch -- specifies an alternate stack for an interrupt handler
8989 trap_exit -- use a trapa to exit an interrupt function instead of
8992 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8993 This is useful on the SH3 and upwards,
8994 which has a separate set of low regs for User and Supervisor modes.
8995 This should only be used for the lowest level of interrupts. Higher levels
8996 of interrupts must save the registers in case they themselves are
8999 renesas -- use Renesas calling/layout conventions (functions and
9002 resbank -- In case of an ISR, use a register bank to save registers
9003 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
9006 /* Handle a 'resbank' attribute. */
9008 sh_handle_resbank_handler_attribute (tree
* node
, tree name
,
9009 tree args ATTRIBUTE_UNUSED
,
9010 int flags ATTRIBUTE_UNUSED
,
9011 bool * no_add_attrs
)
9015 warning (OPT_Wattributes
, "%qE attribute is supported only for SH2A",
9017 *no_add_attrs
= true;
9019 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9021 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9023 *no_add_attrs
= true;
9029 /* Handle an "interrupt_handler" attribute; arguments as in
9030 struct attribute_spec.handler. */
9032 sh_handle_interrupt_handler_attribute (tree
*node
, tree name
,
9033 tree args ATTRIBUTE_UNUSED
,
9034 int flags ATTRIBUTE_UNUSED
,
9037 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9039 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9041 *no_add_attrs
= true;
9043 else if (TARGET_SHCOMPACT
)
9045 error ("attribute interrupt_handler is not compatible with -m5-compact");
9046 *no_add_attrs
= true;
9052 /* Handle an 'function_vector' attribute; arguments as in
9053 struct attribute_spec.handler. */
9055 sh2a_handle_function_vector_handler_attribute (tree
* node
, tree name
,
9056 tree args ATTRIBUTE_UNUSED
,
9057 int flags ATTRIBUTE_UNUSED
,
9058 bool * no_add_attrs
)
9062 warning (OPT_Wattributes
, "%qE attribute only applies to SH2A",
9064 *no_add_attrs
= true;
9066 else if (TREE_CODE (*node
) != FUNCTION_DECL
)
9068 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9070 *no_add_attrs
= true;
9072 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
9074 /* The argument must be a constant integer. */
9075 warning (OPT_Wattributes
,
9076 "%qE attribute argument not an integer constant",
9078 *no_add_attrs
= true;
9080 else if (TREE_INT_CST_LOW (TREE_VALUE (args
)) > 255)
9082 /* The argument value must be between 0 to 255. */
9083 warning (OPT_Wattributes
,
9084 "%qE attribute argument should be between 0 to 255",
9086 *no_add_attrs
= true;
9091 /* Returns true if current function has been assigned the attribute
9092 'function_vector'. */
9094 sh2a_is_function_vector_call (rtx x
)
9096 if (GET_CODE (x
) == SYMBOL_REF
9097 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
9099 tree tr
= SYMBOL_REF_DECL (x
);
9101 if (sh2a_function_vector_p (tr
))
9108 /* Returns the function vector number, if the attribute
9109 'function_vector' is assigned, otherwise returns zero. */
9111 sh2a_get_function_vector_number (rtx x
)
9116 if ((GET_CODE (x
) == SYMBOL_REF
)
9117 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
9119 t
= SYMBOL_REF_DECL (x
);
9121 if (TREE_CODE (t
) != FUNCTION_DECL
)
9124 list
= SH_ATTRIBUTES (t
);
9127 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
9129 num
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list
)));
9133 list
= TREE_CHAIN (list
);
9142 /* Handle an "sp_switch" attribute; arguments as in
9143 struct attribute_spec.handler. */
9145 sh_handle_sp_switch_attribute (tree
*node
, tree name
, tree args
,
9146 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
9148 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9150 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9152 *no_add_attrs
= true;
9154 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
9156 /* The argument must be a constant string. */
9157 warning (OPT_Wattributes
, "%qE attribute argument not a string constant",
9159 *no_add_attrs
= true;
9165 /* Handle an "trap_exit" attribute; arguments as in
9166 struct attribute_spec.handler. */
9168 sh_handle_trap_exit_attribute (tree
*node
, tree name
, tree args
,
9169 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
9171 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9173 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9175 *no_add_attrs
= true;
9177 /* The argument specifies a trap number to be used in a trapa instruction
9178 at function exit (instead of an rte instruction). */
9179 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
9181 /* The argument must be a constant integer. */
9182 warning (OPT_Wattributes
, "%qE attribute argument not an "
9183 "integer constant", name
);
9184 *no_add_attrs
= true;
9191 sh_handle_renesas_attribute (tree
*node ATTRIBUTE_UNUSED
,
9192 tree name ATTRIBUTE_UNUSED
,
9193 tree args ATTRIBUTE_UNUSED
,
9194 int flags ATTRIBUTE_UNUSED
,
9195 bool *no_add_attrs ATTRIBUTE_UNUSED
)
9200 /* True if __attribute__((renesas)) or -mrenesas. */
9202 sh_attr_renesas_p (const_tree td
)
9209 td
= TREE_TYPE (td
);
9210 if (td
== error_mark_node
)
9212 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td
))
9216 /* True if __attribute__((renesas)) or -mrenesas, for the current
9219 sh_cfun_attr_renesas_p (void)
9221 return sh_attr_renesas_p (current_function_decl
);
9225 sh_cfun_interrupt_handler_p (void)
9227 return (lookup_attribute ("interrupt_handler",
9228 DECL_ATTRIBUTES (current_function_decl
))
9232 /* Returns true if FUNC has been assigned the attribute
9233 "function_vector". */
9235 sh2a_function_vector_p (tree func
)
9238 if (TREE_CODE (func
) != FUNCTION_DECL
)
9241 list
= SH_ATTRIBUTES (func
);
9244 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
9247 list
= TREE_CHAIN (list
);
9252 /* Returns TRUE if given tree has the "resbank" attribute. */
9255 sh_cfun_resbank_handler_p (void)
9257 return ((lookup_attribute ("resbank",
9258 DECL_ATTRIBUTES (current_function_decl
))
9260 && (lookup_attribute ("interrupt_handler",
9261 DECL_ATTRIBUTES (current_function_decl
))
9262 != NULL_TREE
) && TARGET_SH2A
);
9265 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9268 sh_check_pch_target_flags (int old_flags
)
9270 if ((old_flags
^ target_flags
) & (MASK_SH1
| MASK_SH2
| MASK_SH3
9271 | MASK_SH_E
| MASK_HARD_SH4
9272 | MASK_FPU_SINGLE
| MASK_SH4
))
9273 return _("created and used with different architectures / ABIs");
9274 if ((old_flags
^ target_flags
) & MASK_HITACHI
)
9275 return _("created and used with different ABIs");
9276 if ((old_flags
^ target_flags
) & MASK_LITTLE_ENDIAN
)
9277 return _("created and used with different endianness");
9281 /* Predicates used by the templates. */
9283 /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx.
9284 Used only in general_movsrc_operand. */
9287 system_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9299 /* Returns true if OP is a floating point value with value 0.0. */
9302 fp_zero_operand (rtx op
)
9306 if (GET_MODE (op
) != SFmode
)
9309 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
9310 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
9313 /* Returns true if OP is a floating point value with value 1.0. */
9316 fp_one_operand (rtx op
)
9320 if (GET_MODE (op
) != SFmode
)
9323 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
9324 return REAL_VALUES_EQUAL (r
, dconst1
);
9327 /* In general mode switching is used. If we are
9328 compiling without -mfmovd, movsf_ie isn't taken into account for
9329 mode switching. We could check in machine_dependent_reorg for
9330 cases where we know we are in single precision mode, but there is
9331 interface to find that out during reload, so we must avoid
9332 choosing an fldi alternative during reload and thus failing to
9333 allocate a scratch register for the constant loading. */
9340 /* Return the TLS type for TLS symbols, 0 for otherwise. */
9342 tls_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
9344 if (GET_CODE (op
) != SYMBOL_REF
)
9345 return TLS_MODEL_NONE
;
9346 return SYMBOL_REF_TLS_MODEL (op
);
9349 /* Return the destination address of a branch. */
9352 branch_dest (rtx branch
)
9354 rtx dest
= SET_SRC (PATTERN (branch
));
9357 if (GET_CODE (dest
) == IF_THEN_ELSE
)
9358 dest
= XEXP (dest
, 1);
9359 dest
= XEXP (dest
, 0);
9360 dest_uid
= INSN_UID (dest
);
9361 return INSN_ADDRESSES (dest_uid
);
9364 /* Return nonzero if REG is not used after INSN.
9365 We assume REG is a reload reg, and therefore does
9366 not live past labels. It may live past calls or jumps though. */
9368 reg_unused_after (rtx reg
, rtx insn
)
9373 /* If the reg is set by this instruction, then it is safe for our
9374 case. Disregard the case where this is a store to memory, since
9375 we are checking a register used in the store address. */
9376 set
= single_set (insn
);
9377 if (set
&& !MEM_P (SET_DEST (set
))
9378 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
9381 while ((insn
= NEXT_INSN (insn
)))
9387 code
= GET_CODE (insn
);
9390 /* If this is a label that existed before reload, then the register
9391 is dead here. However, if this is a label added by reorg, then
9392 the register may still be live here. We can't tell the difference,
9393 so we just ignore labels completely. */
9394 if (code
== CODE_LABEL
)
9399 if (code
== JUMP_INSN
)
9402 /* If this is a sequence, we must handle them all at once.
9403 We could have for instance a call that sets the target register,
9404 and an insn in a delay slot that uses the register. In this case,
9405 we must return 0. */
9406 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
9411 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
9413 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
9414 rtx set
= single_set (this_insn
);
9416 if (CALL_P (this_insn
))
9418 else if (JUMP_P (this_insn
))
9420 if (INSN_ANNULLED_BRANCH_P (this_insn
))
9425 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
9427 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
9429 if (!MEM_P (SET_DEST (set
)))
9435 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
9440 else if (code
== JUMP_INSN
)
9444 set
= single_set (insn
);
9445 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
9447 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
9448 return !MEM_P (SET_DEST (set
));
9449 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
9452 if (code
== CALL_INSN
&& call_really_used_regs
[REGNO (reg
)])
9460 static GTY(()) rtx fpscr_rtx
;
9462 get_fpscr_rtx (void)
9466 fpscr_rtx
= gen_rtx_REG (PSImode
, FPSCR_REG
);
9467 REG_USERVAR_P (fpscr_rtx
) = 1;
9468 mark_user_reg (fpscr_rtx
);
9470 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
9471 mark_user_reg (fpscr_rtx
);
9475 static GTY(()) tree fpscr_values
;
9478 emit_fpu_switch (rtx scratch
, int index
)
9482 if (fpscr_values
== NULL
)
9486 t
= build_index_type (integer_one_node
);
9487 t
= build_array_type (integer_type_node
, t
);
9488 t
= build_decl (BUILTINS_LOCATION
,
9489 VAR_DECL
, get_identifier ("__fpscr_values"), t
);
9490 DECL_ARTIFICIAL (t
) = 1;
9491 DECL_IGNORED_P (t
) = 1;
9492 DECL_EXTERNAL (t
) = 1;
9493 TREE_STATIC (t
) = 1;
9494 TREE_PUBLIC (t
) = 1;
9500 src
= DECL_RTL (fpscr_values
);
9501 if (!can_create_pseudo_p ())
9503 emit_move_insn (scratch
, XEXP (src
, 0));
9505 emit_insn (gen_addsi3 (scratch
, scratch
, GEN_INT (index
* 4)));
9506 src
= adjust_automodify_address (src
, PSImode
, scratch
, index
* 4);
9509 src
= adjust_address (src
, PSImode
, index
* 4);
9511 dst
= get_fpscr_rtx ();
9512 emit_move_insn (dst
, src
);
9516 emit_sf_insn (rtx pat
)
9522 emit_df_insn (rtx pat
)
9528 expand_sf_unop (rtx (*fun
) (rtx
, rtx
, rtx
), rtx
*operands
)
9530 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
9534 expand_sf_binop (rtx (*fun
) (rtx
, rtx
, rtx
, rtx
), rtx
*operands
)
9536 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
9541 expand_df_unop (rtx (*fun
) (rtx
, rtx
, rtx
), rtx
*operands
)
9543 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
9547 expand_df_binop (rtx (*fun
) (rtx
, rtx
, rtx
, rtx
), rtx
*operands
)
9549 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
9553 static rtx
get_free_reg (HARD_REG_SET
);
9555 /* This function returns a register to use to load the address to load
9556 the fpscr from. Currently it always returns r1 or r7, but when we are
9557 able to use pseudo registers after combine, or have a better mechanism
9558 for choosing a register, it should be done here. */
9559 /* REGS_LIVE is the liveness information for the point for which we
9560 need this allocation. In some bare-bones exit blocks, r1 is live at the
9561 start. We can even have all of r0..r3 being live:
9562 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9563 INSN before which new insns are placed with will clobber the register
9564 we return. If a basic block consists only of setting the return value
9565 register to a pseudo and using that register, the return value is not
9566 live before or after this block, yet we we'll insert our insns right in
9570 get_free_reg (HARD_REG_SET regs_live
)
9572 if (! TEST_HARD_REG_BIT (regs_live
, 1))
9573 return gen_rtx_REG (Pmode
, 1);
9575 /* Hard reg 1 is live; since this is a small register classes target,
9576 there shouldn't be anything but a jump before the function end. */
9577 gcc_assert (!TEST_HARD_REG_BIT (regs_live
, 7));
9578 return gen_rtx_REG (Pmode
, 7);
9581 /* This function will set the fpscr from memory.
9582 MODE is the mode we are setting it to. */
9584 fpscr_set_from_mem (int mode
, HARD_REG_SET regs_live
)
9586 enum attr_fp_mode fp_mode
= (enum attr_fp_mode
) mode
;
9587 enum attr_fp_mode norm_mode
= ACTUAL_NORMAL_MODE (FP_MODE
);
9590 addr_reg
= !can_create_pseudo_p () ? get_free_reg (regs_live
) : NULL_RTX
;
9591 emit_fpu_switch (addr_reg
, fp_mode
== norm_mode
);
9594 /* Is the given character a logical line separator for the assembler? */
9595 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9596 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9600 sh_insn_length_adjustment (rtx insn
)
9602 /* Instructions with unfilled delay slots take up an extra two bytes for
9603 the nop in the delay slot. */
9604 if (((NONJUMP_INSN_P (insn
)
9605 && GET_CODE (PATTERN (insn
)) != USE
9606 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
9608 || (JUMP_P (insn
) && !JUMP_TABLE_DATA_P (insn
)))
9609 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
9610 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
9613 /* SH2e has a bug that prevents the use of annulled branches, so if
9614 the delay slot is not filled, we'll have to put a NOP in it. */
9615 if (sh_cpu_attr
== CPU_SH2E
9616 && JUMP_P (insn
) && !JUMP_TABLE_DATA_P (insn
)
9617 && get_attr_type (insn
) == TYPE_CBRANCH
9618 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
)
9621 /* sh-dsp parallel processing insn take four bytes instead of two. */
9623 if (NONJUMP_INSN_P (insn
))
9626 rtx body
= PATTERN (insn
);
9629 int maybe_label
= 1;
9631 if (GET_CODE (body
) == ASM_INPUT
)
9632 templ
= XSTR (body
, 0);
9633 else if (asm_noperands (body
) >= 0)
9635 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
, NULL
);
9644 while (c
== ' ' || c
== '\t');
9645 /* all sh-dsp parallel-processing insns start with p.
9646 The only non-ppi sh insn starting with p is pref.
9647 The only ppi starting with pr is prnd. */
9648 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", templ
, 2))
9650 /* The repeat pseudo-insn expands two three insns, a total of
9651 six bytes in size. */
9652 else if ((c
== 'r' || c
== 'R')
9653 && ! strncasecmp ("epeat", templ
, 5))
9655 while (c
&& c
!= '\n'
9656 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
, templ
))
9658 /* If this is a label, it is obviously not a ppi insn. */
9659 if (c
== ':' && maybe_label
)
9664 else if (c
== '\'' || c
== '"')
9669 maybe_label
= c
!= ':';
9677 /* Return TRUE for a valid displacement for the REG+disp addressing
9681 sh_legitimate_index_p (enum machine_mode mode
, rtx op
)
9683 if (! CONST_INT_P (op
))
9690 /* Check if this is the address of an unaligned load / store. */
9691 if (mode
== VOIDmode
)
9692 return CONST_OK_FOR_I06 (INTVAL (op
));
9694 size
= GET_MODE_SIZE (mode
);
9695 return (!(INTVAL (op
) & (size
- 1))
9696 && INTVAL (op
) >= -512 * size
9697 && INTVAL (op
) < 512 * size
);
9701 const HOST_WIDE_INT offset
= INTVAL (op
);
9702 const int max_disp
= max_mov_insn_displacement (mode
, TARGET_SH2A
);
9703 const int align_mask
= mov_insn_alignment_mask (mode
, TARGET_SH2A
);
9705 /* If the mode does not support any displacement always return false.
9706 Even though an index of '0' is actually always valid, it will cause
9707 troubles when e.g. a DFmode move is split into two SFmode moves,
9708 where one SFmode move will have index '0' and the other move will
9713 return offset
>= 0 && offset
<= max_disp
&& (offset
& align_mask
) == 0;
9717 /* Recognize an RTL expression that is a valid memory address for
9719 The MODE argument is the machine mode for the MEM expression
9720 that wants to use this address.
9728 sh_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
9730 if (MAYBE_BASE_REGISTER_RTX_P (x
, strict
))
9732 else if ((GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
9734 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x
, 0), strict
))
9736 else if (GET_CODE (x
) == PLUS
9737 && (mode
!= PSImode
|| reload_completed
))
9739 rtx xop0
= XEXP (x
, 0);
9740 rtx xop1
= XEXP (x
, 1);
9742 if (GET_MODE_SIZE (mode
) <= 8
9743 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
)
9744 && sh_legitimate_index_p (mode
, xop1
))
9747 if ((ALLOW_INDEXED_ADDRESS
|| GET_MODE (x
) == DImode
9748 || ((xop0
== stack_pointer_rtx
9749 || xop0
== hard_frame_pointer_rtx
)
9750 && REG_P (xop1
) && REGNO (xop1
) == R0_REG
)
9751 || ((xop1
== stack_pointer_rtx
9752 || xop1
== hard_frame_pointer_rtx
)
9753 && REG_P (xop0
) && REGNO (xop0
) == R0_REG
))
9754 && ((!TARGET_SHMEDIA
&& GET_MODE_SIZE (mode
) <= 4)
9755 || (TARGET_SHMEDIA
&& GET_MODE_SIZE (mode
) <= 8)
9756 || ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
9757 && TARGET_FMOVD
&& mode
== DFmode
)))
9759 if (MAYBE_BASE_REGISTER_RTX_P (xop1
, strict
)
9760 && MAYBE_INDEX_REGISTER_RTX_P (xop0
, strict
))
9762 if (MAYBE_INDEX_REGISTER_RTX_P (xop1
, strict
)
9763 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
))
9771 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9772 isn't protected by a PIC unspec. */
9774 nonpic_symbol_mentioned_p (rtx x
)
9779 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
9780 || GET_CODE (x
) == PC
)
9783 /* We don't want to look into the possible MEM location of a
9784 CONST_DOUBLE, since we're not going to use it, in general. */
9785 if (GET_CODE (x
) == CONST_DOUBLE
)
9788 if (GET_CODE (x
) == UNSPEC
9789 && (XINT (x
, 1) == UNSPEC_PIC
9790 || XINT (x
, 1) == UNSPEC_GOT
9791 || XINT (x
, 1) == UNSPEC_GOTOFF
9792 || XINT (x
, 1) == UNSPEC_GOTPLT
9793 || XINT (x
, 1) == UNSPEC_GOTTPOFF
9794 || XINT (x
, 1) == UNSPEC_DTPOFF
9795 || XINT (x
, 1) == UNSPEC_TPOFF
9796 || XINT (x
, 1) == UNSPEC_PLT
9797 || XINT (x
, 1) == UNSPEC_SYMOFF
9798 || XINT (x
, 1) == UNSPEC_PCREL_SYMOFF
))
9801 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
9802 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
9807 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9808 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
9811 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
9818 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9819 @GOTOFF in `reg'. */
9821 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
9824 if (tls_symbolic_operand (orig
, Pmode
) != TLS_MODEL_NONE
)
9827 if (GET_CODE (orig
) == LABEL_REF
9828 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
9831 reg
= gen_reg_rtx (Pmode
);
9833 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
9836 else if (GET_CODE (orig
) == SYMBOL_REF
)
9839 reg
= gen_reg_rtx (Pmode
);
9841 emit_insn (gen_symGOT2reg (reg
, orig
));
9847 /* Given a (logical) mode size and an offset in bytes, try to find a the
9848 appropriate displacement value for a mov insn. On SH the displacements
9849 are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max.
9850 15 bytes in QImode. To compensate this we create a new base address by
9851 adding an adjustment value to it.
9853 If the originally requested offset is greater than 127 we prefer using
9854 values 124..127 over 128..131 to increase opportunities to use the
9857 In some cases it is possible that a requested offset might seem unaligned
9858 or inappropriate for the mode size, like offset = 2 and mode size = 4.
9859 This is compensated by adjusting the base address so that the effective
9860 address of the displacement move insn will be aligned.
9862 This is not the best possible way of rebasing the base address, as it
9863 does not look at other present displacement addressings around it.
9864 In some cases this can create more base address adjustments than would
9865 actually be necessary. */
9873 static struct disp_adjust
9874 sh_find_mov_disp_adjust (enum machine_mode mode
, HOST_WIDE_INT offset
)
9876 struct disp_adjust res
= { NULL_RTX
, NULL_RTX
};
9878 /* Do not try to use SH2A's large displacements here, because this would
9879 effectively disable the small displacement insns. */
9880 const int mode_sz
= GET_MODE_SIZE (mode
);
9881 const int mov_insn_sz
= mov_insn_size (mode
, false);
9882 const int max_disp
= max_mov_insn_displacement (mode
, false);
9883 const int max_disp_next
= max_disp
+ mov_insn_sz
;
9884 HOST_WIDE_INT align_modifier
= offset
> 127 ? mov_insn_sz
: 0;
9885 HOST_WIDE_INT offset_adjust
;
9887 /* In some cases this actually does happen and we must check for it. */
9888 if (mode_sz
< 1 || mode_sz
> 8 || max_disp
< 1)
9891 /* FIXME: HImode with displacement addressing is not supported yet.
9892 Make it purposefully fail for now. */
9893 if (mov_insn_sz
== 2)
9896 /* Keeps the previous behavior for QImode displacement addressing.
9897 This just decides how the offset is re-based. Removing this special
9898 case will result in slightly bigger code on average, but it's not that
9900 if (mov_insn_sz
== 1)
9903 offset_adjust
= ((offset
+ align_modifier
) & ~max_disp
) - align_modifier
;
9905 if (mode_sz
+ offset
- offset_adjust
<= max_disp_next
)
9907 res
.offset_adjust
= GEN_INT (offset_adjust
);
9908 res
.mov_disp
= GEN_INT (offset
- offset_adjust
);
9914 /* Try to modify an illegitimate address and make it legitimate.
9915 If we find one, return the new, valid address.
9916 Otherwise, return the original address. */
9919 sh_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
9922 x
= legitimize_pic_address (oldx
, mode
, NULL_RTX
);
9927 if (((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && mode
== DFmode
)
9928 || (TARGET_SH2E
&& mode
== SFmode
))
9931 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
9932 && BASE_REGISTER_RTX_P (XEXP (x
, 0)))
9934 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
,
9935 INTVAL (XEXP (x
, 1)));
9937 if (adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
9939 rtx sum
= expand_binop (Pmode
, add_optab
, XEXP (x
, 0),
9940 adj
.offset_adjust
, NULL_RTX
, 0,
9942 return gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
9949 /* Attempt to replace *p, which is an address that needs reloading, with
9950 a valid memory address for an operand of mode MODE.
9951 Like for sh_legitimize_address, for the SH we try to get a normal form
9952 of the address. That will allow inheritance of the address reloads. */
9955 sh_legitimize_reload_address (rtx
*p
, enum machine_mode mode
, int opnum
,
9958 enum reload_type type
= (enum reload_type
) itype
;
9959 const int mode_sz
= GET_MODE_SIZE (mode
);
9964 if (GET_CODE (*p
) == PLUS
&& CONST_INT_P (XEXP (*p
, 1))
9965 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p
, 0), true)
9966 && ! (mode
== PSImode
&& type
== RELOAD_FOR_INPUT_ADDRESS
)
9967 && (ALLOW_INDEXED_ADDRESS
9968 || XEXP (*p
, 0) == stack_pointer_rtx
9969 || XEXP (*p
, 0) == hard_frame_pointer_rtx
))
9971 const HOST_WIDE_INT offset
= INTVAL (XEXP (*p
, 1));
9972 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
, offset
);
9974 if (TARGET_SH2A
&& mode
== DFmode
&& (offset
& 0x7))
9976 push_reload (*p
, NULL_RTX
, p
, NULL
,
9977 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
9981 if (TARGET_SH2E
&& mode
== SFmode
)
9984 push_reload (*p
, NULL_RTX
, p
, NULL
,
9985 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
9989 /* FIXME: Do not allow to legitimize QImode and HImode displacement
9990 moves because then reload has a problem figuring the constraint
9991 that the move insn target/source reg must be R0.
9992 Or maybe some handling is wrong in sh_secondary_reload for this
9993 to work properly? */
9994 if ((mode_sz
== 4 || mode_sz
== 8)
9995 && ! (TARGET_SH4
&& mode
== DFmode
)
9996 && adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
9998 rtx sum
= gen_rtx_PLUS (Pmode
, XEXP (*p
, 0), adj
.offset_adjust
);
9999 *p
= gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
10000 push_reload (sum
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
10001 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10006 /* We must re-recognize what we created before. */
10007 if (GET_CODE (*p
) == PLUS
10008 && (mode_sz
== 4 || mode_sz
== 8)
10009 && GET_CODE (XEXP (*p
, 0)) == PLUS
10010 && CONST_INT_P (XEXP (XEXP (*p
, 0), 1))
10011 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p
, 0), 0), true)
10012 && CONST_INT_P (XEXP (*p
, 1))
10013 && ! (TARGET_SH2E
&& mode
== SFmode
))
10015 /* Because this address is so complex, we know it must have
10016 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
10017 it is already unshared, and needs no further unsharing. */
10018 push_reload (XEXP (*p
, 0), NULL_RTX
, &XEXP (*p
, 0), NULL
,
10019 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10026 /* In the name of slightly smaller debug output, and to cater to
10027 general assembler lossage, recognize various UNSPEC sequences
10028 and turn them back into a direct symbol reference. */
10031 sh_delegitimize_address (rtx orig_x
)
10035 orig_x
= delegitimize_mem_from_attrs (orig_x
);
10040 if (GET_CODE (x
) == CONST
)
10043 if (GET_CODE (y
) == UNSPEC
)
10045 if (XINT (y
, 1) == UNSPEC_GOT
10046 || XINT (y
, 1) == UNSPEC_GOTOFF
10047 || XINT (y
, 1) == UNSPEC_SYMOFF
)
10048 return XVECEXP (y
, 0, 0);
10049 else if (XINT (y
, 1) == UNSPEC_PCREL_SYMOFF
)
10051 if (GET_CODE (XVECEXP (y
, 0, 0)) == CONST
)
10053 rtx symplt
= XEXP (XVECEXP (y
, 0, 0), 0);
10055 if (GET_CODE (symplt
) == UNSPEC
10056 && XINT (symplt
, 1) == UNSPEC_PLT
)
10057 return XVECEXP (symplt
, 0, 0);
10060 else if (TARGET_SHMEDIA
10061 && (XINT (y
, 1) == UNSPEC_EXTRACT_S16
10062 || XINT (y
, 1) == UNSPEC_EXTRACT_U16
))
10064 rtx offset
= XVECEXP (y
, 0, 1);
10066 x
= gen_rtx_PLUS (Pmode
, XVECEXP (y
, 0, 0), offset
);
10067 if (MEM_P (orig_x
))
10068 x
= replace_equiv_address_nv (orig_x
, x
);
10077 /* Mark the use of a constant in the literal table. If the constant
10078 has multiple labels, make it unique. */
10080 mark_constant_pool_use (rtx x
)
10082 rtx insn
, lab
, pattern
;
10087 switch (GET_CODE (x
))
10097 /* Get the first label in the list of labels for the same constant
10098 and delete another labels in the list. */
10100 for (insn
= PREV_INSN (x
); insn
; insn
= PREV_INSN (insn
))
10102 if (!LABEL_P (insn
)
10103 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
10108 for (insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
10109 INSN_DELETED_P (insn
) = 1;
10111 /* Mark constants in a window. */
10112 for (insn
= NEXT_INSN (x
); insn
; insn
= NEXT_INSN (insn
))
10114 if (!NONJUMP_INSN_P (insn
))
10117 pattern
= PATTERN (insn
);
10118 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
10121 switch (XINT (pattern
, 1))
10123 case UNSPECV_CONST2
:
10124 case UNSPECV_CONST4
:
10125 case UNSPECV_CONST8
:
10126 XVECEXP (pattern
, 0, 1) = const1_rtx
;
10128 case UNSPECV_WINDOW_END
:
10129 if (XVECEXP (pattern
, 0, 0) == x
)
10132 case UNSPECV_CONST_END
:
10142 /* Return true if it's possible to redirect BRANCH1 to the destination
10143 of an unconditional jump BRANCH2. We only want to do this if the
10144 resulting branch will have a short displacement. */
10146 sh_can_redirect_branch (rtx branch1
, rtx branch2
)
10148 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
10150 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
10154 for (distance
= 0, insn
= NEXT_INSN (branch1
);
10155 insn
&& distance
< 256;
10156 insn
= PREV_INSN (insn
))
10161 distance
+= get_attr_length (insn
);
10163 for (distance
= 0, insn
= NEXT_INSN (branch1
);
10164 insn
&& distance
< 256;
10165 insn
= NEXT_INSN (insn
))
10170 distance
+= get_attr_length (insn
);
10176 /* Return nonzero if register old_reg can be renamed to register new_reg. */
10178 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
10179 unsigned int new_reg
)
10181 /* Interrupt functions can only use registers that have already been
10182 saved by the prologue, even if they would normally be
10185 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg
))
10191 /* Function to update the integer COST
10192 based on the relationship between INSN that is dependent on
10193 DEP_INSN through the dependence LINK. The default is to make no
10194 adjustment to COST. This can be used for example to specify to
10195 the scheduler that an output- or anti-dependence does not incur
10196 the same cost as a data-dependence. The return value should be
10197 the new value for COST. */
10199 sh_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx dep_insn
, int cost
)
10203 if (TARGET_SHMEDIA
)
10205 /* On SHmedia, if the dependence is an anti-dependence or
10206 output-dependence, there is no cost. */
10207 if (REG_NOTE_KIND (link
) != 0)
10209 /* However, dependencies between target register loads and
10210 uses of the register in a subsequent block that are separated
10211 by a conditional branch are not modelled - we have to do with
10212 the anti-dependency between the target register load and the
10213 conditional branch that ends the current block. */
10214 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
10215 && GET_CODE (PATTERN (dep_insn
)) == SET
10216 && (get_attr_type (dep_insn
) == TYPE_PT_MEDIA
10217 || get_attr_type (dep_insn
) == TYPE_PTABS_MEDIA
)
10218 && get_attr_type (insn
) == TYPE_CBRANCH_MEDIA
)
10220 int orig_cost
= cost
;
10221 rtx note
= find_reg_note (insn
, REG_BR_PROB
, 0);
10222 rtx target
= ((! note
10223 || INTVAL (XEXP (note
, 0)) * 2 < REG_BR_PROB_BASE
)
10224 ? insn
: JUMP_LABEL (insn
));
10225 /* On the likely path, the branch costs 1, on the unlikely path,
10229 target
= next_active_insn (target
);
10230 while (target
&& ! flow_dependent_p (target
, dep_insn
)
10232 /* If two branches are executed in immediate succession, with the
10233 first branch properly predicted, this causes a stall at the
10234 second branch, hence we won't need the target for the
10235 second branch for two cycles after the launch of the first
10237 if (cost
> orig_cost
- 2)
10238 cost
= orig_cost
- 2;
10244 else if (get_attr_is_mac_media (insn
)
10245 && get_attr_is_mac_media (dep_insn
))
10248 else if (! reload_completed
10249 && GET_CODE (PATTERN (insn
)) == SET
10250 && GET_CODE (SET_SRC (PATTERN (insn
))) == FLOAT
10251 && GET_CODE (PATTERN (dep_insn
)) == SET
10252 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn
)), VOIDmode
)
10255 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10256 that is needed at the target. */
10257 else if (get_attr_type (insn
) == TYPE_JUMP_MEDIA
10258 && ! flow_dependent_p (insn
, dep_insn
))
10261 else if (REG_NOTE_KIND (link
) == 0)
10263 enum attr_type type
;
10266 if (recog_memoized (insn
) < 0
10267 || recog_memoized (dep_insn
) < 0)
10270 dep_set
= single_set (dep_insn
);
10272 /* The latency that we specify in the scheduling description refers
10273 to the actual output, not to an auto-increment register; for that,
10274 the latency is one. */
10275 if (dep_set
&& MEM_P (SET_SRC (dep_set
)) && cost
> 1)
10277 rtx set
= single_set (insn
);
10280 && !reg_mentioned_p (SET_DEST (dep_set
), SET_SRC (set
))
10281 && (!MEM_P (SET_DEST (set
))
10282 || !reg_mentioned_p (SET_DEST (dep_set
),
10283 XEXP (SET_DEST (set
), 0))))
10286 /* The only input for a call that is timing-critical is the
10287 function's address. */
10290 rtx call
= PATTERN (insn
);
10292 if (GET_CODE (call
) == PARALLEL
)
10293 call
= XVECEXP (call
, 0 ,0);
10294 if (GET_CODE (call
) == SET
)
10295 call
= SET_SRC (call
);
10296 if (GET_CODE (call
) == CALL
&& MEM_P (XEXP (call
, 0))
10297 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10298 && (GET_CODE (XEXP (XEXP (call
, 0), 0)) == UNSPEC
10299 || ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
)))
10300 cost
-= TARGET_SH4_300
? 3 : 6;
10302 /* Likewise, the most timing critical input for an sfuncs call
10303 is the function address. However, sfuncs typically start
10304 using their arguments pretty quickly.
10305 Assume a four cycle delay for SH4 before they are needed.
10306 Cached ST40-300 calls are quicker, so assume only a one
10308 ??? Maybe we should encode the delays till input registers
10309 are needed by sfuncs into the sfunc call insn. */
10310 /* All sfunc calls are parallels with at least four components.
10311 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10312 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
10313 && XVECLEN (PATTERN (insn
), 0) >= 4
10314 && (reg
= sfunc_uses_reg (insn
)))
10316 if (! reg_set_p (reg
, dep_insn
))
10317 cost
-= TARGET_SH4_300
? 1 : 4;
10319 if (TARGET_HARD_SH4
&& !TARGET_SH4_300
)
10321 enum attr_type dep_type
= get_attr_type (dep_insn
);
10323 if (dep_type
== TYPE_FLOAD
|| dep_type
== TYPE_PCFLOAD
)
10325 else if ((dep_type
== TYPE_LOAD_SI
|| dep_type
== TYPE_PCLOAD_SI
)
10326 && (type
= get_attr_type (insn
)) != TYPE_CALL
10327 && type
!= TYPE_SFUNC
)
10329 /* When the preceding instruction loads the shift amount of
10330 the following SHAD/SHLD, the latency of the load is increased
10332 if (get_attr_type (insn
) == TYPE_DYN_SHIFT
10333 && get_attr_any_int_load (dep_insn
) == ANY_INT_LOAD_YES
10334 && reg_overlap_mentioned_p (SET_DEST (dep_set
),
10335 XEXP (SET_SRC (single_set (insn
)),
10338 /* When an LS group instruction with a latency of less than
10339 3 cycles is followed by a double-precision floating-point
10340 instruction, FIPR, or FTRV, the latency of the first
10341 instruction is increased to 3 cycles. */
10343 && get_attr_insn_class (dep_insn
) == INSN_CLASS_LS_GROUP
10344 && get_attr_dfp_comp (insn
) == DFP_COMP_YES
)
10346 /* The lsw register of a double-precision computation is ready one
10348 else if (reload_completed
10349 && get_attr_dfp_comp (dep_insn
) == DFP_COMP_YES
10350 && (use_pat
= single_set (insn
))
10351 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn
))),
10352 SET_SRC (use_pat
)))
10355 if (get_attr_any_fp_comp (dep_insn
) == ANY_FP_COMP_YES
10356 && get_attr_late_fp_use (insn
) == LATE_FP_USE_YES
)
10359 else if (TARGET_SH4_300
)
10361 /* Stores need their input register two cycles later. */
10362 if (dep_set
&& cost
>= 1
10363 && ((type
= get_attr_type (insn
)) == TYPE_STORE
10364 || type
== TYPE_PSTORE
10365 || type
== TYPE_FSTORE
|| type
== TYPE_MAC_MEM
))
10367 rtx set
= single_set (insn
);
10369 if (!reg_mentioned_p (SET_SRC (set
), XEXP (SET_DEST (set
), 0))
10370 && rtx_equal_p (SET_SRC (set
), SET_DEST (dep_set
)))
10373 /* But don't reduce the cost below 1 if the address depends
10374 on a side effect of dep_insn. */
10376 && modified_in_p (XEXP (SET_DEST (set
), 0), dep_insn
))
10382 /* An anti-dependence penalty of two applies if the first insn is a double
10383 precision fadd / fsub / fmul. */
10384 else if (!TARGET_SH4_300
10385 && REG_NOTE_KIND (link
) == REG_DEP_ANTI
10386 && recog_memoized (dep_insn
) >= 0
10387 && (get_attr_type (dep_insn
) == TYPE_DFP_ARITH
10388 || get_attr_type (dep_insn
) == TYPE_DFP_MUL
)
10389 /* A lot of alleged anti-flow dependences are fake,
10390 so check this one is real. */
10391 && flow_dependent_p (dep_insn
, insn
))
10397 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10398 if DEP_INSN is anti-flow dependent on INSN. */
10400 flow_dependent_p (rtx insn
, rtx dep_insn
)
10402 rtx tmp
= PATTERN (insn
);
10404 note_stores (PATTERN (dep_insn
), flow_dependent_p_1
, &tmp
);
10405 return tmp
== NULL_RTX
;
10408 /* A helper function for flow_dependent_p called through note_stores. */
10410 flow_dependent_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
10412 rtx
* pinsn
= (rtx
*) data
;
10414 if (*pinsn
&& reg_referenced_p (x
, *pinsn
))
10418 /* For use by sh_allocate_initial_value. Note that sh.md contains some
10419 'special function' patterns (type sfunc) that clobber pr, but that
10420 do not look like function calls to leaf_function_p. Hence we must
10421 do this extra check. */
10423 sh_pr_n_sets (void)
10425 return DF_REG_DEF_COUNT (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
10428 /* Return where to allocate pseudo for a given hard register initial
10431 sh_allocate_initial_value (rtx hard_reg
)
10435 if (REGNO (hard_reg
) == (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
))
10437 if (current_function_is_leaf
10438 && ! sh_pr_n_sets ()
10439 && ! (TARGET_SHCOMPACT
10440 && ((crtl
->args
.info
.call_cookie
10441 & ~ CALL_COOKIE_RET_TRAMP (1))
10442 || crtl
->saves_all_registers
)))
10445 x
= gen_frame_mem (Pmode
, return_address_pointer_rtx
);
10453 /* This function returns "2" to indicate dual issue for the SH4
10454 processor. To be used by the DFA pipeline description. */
10456 sh_issue_rate (void)
10458 if (TARGET_SUPERSCALAR
)
10464 /* Functions for ready queue reordering for sched1. */
10466 /* Get weight for mode for a set x. */
10468 find_set_regmode_weight (rtx x
, enum machine_mode mode
)
10470 if (GET_CODE (x
) == CLOBBER
&& register_operand (SET_DEST (x
), mode
))
10472 if (GET_CODE (x
) == SET
&& register_operand (SET_DEST (x
), mode
))
10474 if (REG_P (SET_DEST (x
)))
10476 if (!reg_mentioned_p (SET_DEST (x
), SET_SRC (x
)))
10486 /* Get regmode weight for insn. */
10488 find_insn_regmode_weight (rtx insn
, enum machine_mode mode
)
10490 short reg_weight
= 0;
10493 /* Increment weight for each register born here. */
10494 x
= PATTERN (insn
);
10495 reg_weight
+= find_set_regmode_weight (x
, mode
);
10496 if (GET_CODE (x
) == PARALLEL
)
10499 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
10501 x
= XVECEXP (PATTERN (insn
), 0, j
);
10502 reg_weight
+= find_set_regmode_weight (x
, mode
);
10505 /* Decrement weight for each register that dies here. */
10506 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
10508 if (REG_NOTE_KIND (x
) == REG_DEAD
|| REG_NOTE_KIND (x
) == REG_UNUSED
)
10510 rtx note
= XEXP (x
, 0);
10511 if (REG_P (note
) && GET_MODE (note
) == mode
)
10518 /* Calculate regmode weights for all insns of a basic block. */
10520 find_regmode_weight (basic_block b
, enum machine_mode mode
)
10522 rtx insn
, next_tail
, head
, tail
;
10524 get_ebb_head_tail (b
, b
, &head
, &tail
);
10525 next_tail
= NEXT_INSN (tail
);
10527 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
10529 /* Handle register life information. */
10530 if (!INSN_P (insn
))
10533 if (mode
== SFmode
)
10534 INSN_REGMODE_WEIGHT (insn
, mode
) =
10535 find_insn_regmode_weight (insn
, mode
) + 2 * find_insn_regmode_weight (insn
, DFmode
);
10536 else if (mode
== SImode
)
10537 INSN_REGMODE_WEIGHT (insn
, mode
) =
10538 find_insn_regmode_weight (insn
, mode
) + 2 * find_insn_regmode_weight (insn
, DImode
);
10542 /* Comparison function for ready queue sorting. */
10544 rank_for_reorder (const void *x
, const void *y
)
10546 rtx tmp
= *(const rtx
*) y
;
10547 rtx tmp2
= *(const rtx
*) x
;
10549 /* The insn in a schedule group should be issued the first. */
10550 if (SCHED_GROUP_P (tmp
) != SCHED_GROUP_P (tmp2
))
10551 return SCHED_GROUP_P (tmp2
) ? 1 : -1;
10553 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10554 minimizes instruction movement, thus minimizing sched's effect on
10555 register pressure. */
10556 return INSN_LUID (tmp
) - INSN_LUID (tmp2
);
10559 /* Resort the array A in which only element at index N may be out of order. */
10561 swap_reorder (rtx
*a
, int n
)
10563 rtx insn
= a
[n
- 1];
10566 while (i
>= 0 && rank_for_reorder (a
+ i
, &insn
) >= 0)
10574 #define SCHED_REORDER(READY, N_READY) \
10577 if ((N_READY) == 2) \
10578 swap_reorder (READY, N_READY); \
10579 else if ((N_READY) > 2) \
10580 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10584 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10587 ready_reorder (rtx
*ready
, int nready
)
10589 SCHED_REORDER (ready
, nready
);
10592 /* Count life regions of r0 for a block. */
10594 find_r0_life_regions (basic_block b
)
10603 if (REGNO_REG_SET_P (df_get_live_in (b
), R0_REG
))
10614 insn
= BB_HEAD (b
);
10616 r0_reg
= gen_rtx_REG (SImode
, R0_REG
);
10621 if (find_regno_note (insn
, REG_DEAD
, R0_REG
))
10627 && (pset
= single_set (insn
))
10628 && reg_overlap_mentioned_p (r0_reg
, SET_DEST (pset
))
10629 && !find_regno_note (insn
, REG_UNUSED
, R0_REG
))
10637 insn
= NEXT_INSN (insn
);
10639 return set
- death
;
10642 /* Calculate regmode weights for all insns of all basic block. */
10644 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED
,
10645 int verbose ATTRIBUTE_UNUSED
,
10650 regmode_weight
[0] = (short *) xcalloc (old_max_uid
, sizeof (short));
10651 regmode_weight
[1] = (short *) xcalloc (old_max_uid
, sizeof (short));
10652 r0_life_regions
= 0;
10654 FOR_EACH_BB_REVERSE (b
)
10656 find_regmode_weight (b
, SImode
);
10657 find_regmode_weight (b
, SFmode
);
10658 if (!reload_completed
)
10659 r0_life_regions
+= find_r0_life_regions (b
);
10662 CURR_REGMODE_PRESSURE (SImode
) = 0;
10663 CURR_REGMODE_PRESSURE (SFmode
) = 0;
10669 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
10670 int verbose ATTRIBUTE_UNUSED
)
10672 if (regmode_weight
[0])
10674 free (regmode_weight
[0]);
10675 regmode_weight
[0] = NULL
;
10677 if (regmode_weight
[1])
10679 free (regmode_weight
[1]);
10680 regmode_weight
[1] = NULL
;
10684 /* The scalar modes supported differs from the default version in TImode
10685 for 32-bit SHMEDIA. */
10687 sh_scalar_mode_supported_p (enum machine_mode mode
)
10689 if (TARGET_SHMEDIA32
&& mode
== TImode
)
10692 return default_scalar_mode_supported_p (mode
);
10695 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10696 keep count of register pressures on SImode and SFmode. */
10698 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
10699 int sched_verbose ATTRIBUTE_UNUSED
,
10701 int can_issue_more
)
10703 if (GET_CODE (PATTERN (insn
)) != USE
10704 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10705 cached_can_issue_more
= can_issue_more
- 1;
10707 cached_can_issue_more
= can_issue_more
;
10709 if (reload_completed
)
10710 return cached_can_issue_more
;
10712 CURR_REGMODE_PRESSURE (SImode
) += INSN_REGMODE_WEIGHT (insn
, SImode
);
10713 CURR_REGMODE_PRESSURE (SFmode
) += INSN_REGMODE_WEIGHT (insn
, SFmode
);
10715 return cached_can_issue_more
;
10719 sh_md_init (FILE *dump ATTRIBUTE_UNUSED
,
10720 int verbose ATTRIBUTE_UNUSED
,
10721 int veclen ATTRIBUTE_UNUSED
)
10723 CURR_REGMODE_PRESSURE (SImode
) = 0;
10724 CURR_REGMODE_PRESSURE (SFmode
) = 0;
10727 /* Some magic numbers. */
10728 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10729 functions that already have high pressure on r0. */
10730 #define R0_MAX_LIFE_REGIONS 2
10731 /* Register Pressure thresholds for SImode and SFmode registers. */
10732 #define SIMODE_MAX_WEIGHT 5
10733 #define SFMODE_MAX_WEIGHT 10
10735 /* Return true if the pressure is high for MODE. */
10737 high_pressure (enum machine_mode mode
)
10739 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10740 functions that already have high pressure on r0. */
10741 if (r0_life_regions
>= R0_MAX_LIFE_REGIONS
)
10744 if (mode
== SFmode
)
10745 return (CURR_REGMODE_PRESSURE (SFmode
) > SFMODE_MAX_WEIGHT
);
10747 return (CURR_REGMODE_PRESSURE (SImode
) > SIMODE_MAX_WEIGHT
);
10750 /* Reorder ready queue if register pressure is high. */
10752 sh_reorder (FILE *dump ATTRIBUTE_UNUSED
,
10753 int sched_verbose ATTRIBUTE_UNUSED
,
10756 int clock_var ATTRIBUTE_UNUSED
)
10758 if (reload_completed
)
10759 return sh_issue_rate ();
10761 if (high_pressure (SFmode
) || high_pressure (SImode
))
10763 ready_reorder (ready
, *n_readyp
);
10766 return sh_issue_rate ();
10769 /* Skip cycles if the current register pressure is high. */
10771 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
10772 int sched_verbose ATTRIBUTE_UNUSED
,
10773 rtx
*ready ATTRIBUTE_UNUSED
,
10774 int *n_readyp ATTRIBUTE_UNUSED
,
10775 int clock_var ATTRIBUTE_UNUSED
)
10777 if (reload_completed
)
10778 return cached_can_issue_more
;
10780 if (high_pressure(SFmode
) || high_pressure (SImode
))
10783 return cached_can_issue_more
;
10786 /* Skip cycles without sorting the ready queue. This will move insn from
10787 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10788 queue by sh_reorder. */
10790 /* Generally, skipping these many cycles are sufficient for all insns to move
10792 #define MAX_SKIPS 8
10795 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED
,
10796 int sched_verbose ATTRIBUTE_UNUSED
,
10797 rtx insn ATTRIBUTE_UNUSED
,
10798 int last_clock_var
,
10802 if (reload_completed
)
10807 if ((clock_var
- last_clock_var
) < MAX_SKIPS
)
10812 /* If this is the last cycle we are skipping, allow reordering of R. */
10813 if ((clock_var
- last_clock_var
) == MAX_SKIPS
)
10825 /* SHmedia requires registers for branches, so we can't generate new
10826 branches past reload. */
10828 sh_cannot_modify_jumps_p (void)
10830 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
10834 sh_target_reg_class (void)
10836 return TARGET_SHMEDIA
? TARGET_REGS
: NO_REGS
;
10840 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen
)
10842 HARD_REG_SET dummy
;
10847 if (! shmedia_space_reserved_for_target_registers
)
10849 if (after_prologue_epilogue_gen
&& ! TARGET_SAVE_ALL_TARGET_REGS
)
10851 if (calc_live_regs (&dummy
) >= 6 * 8)
10857 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED
)
10859 return (TARGET_SH5
|| TARGET_HITACHI
|| sh_attr_renesas_p (record_type
));
10863 On the SH1..SH4, the trampoline looks like
10864 2 0002 D202 mov.l l2,r2
10865 1 0000 D301 mov.l l1,r3
10866 3 0004 422B jmp @r2
10868 5 0008 00000000 l1: .long area
10869 6 000c 00000000 l2: .long function
10871 SH5 (compact) uses r1 instead of r3 for the static chain. */
10874 /* Emit RTL insns to initialize the variable parts of a trampoline.
10875 FNADDR is an RTX for the address of the function's pure code.
10876 CXT is an RTX for the static chain value for the function. */
10879 sh_trampoline_init (rtx tramp_mem
, tree fndecl
, rtx cxt
)
10881 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
10882 rtx tramp
= force_reg (Pmode
, XEXP (tramp_mem
, 0));
10884 if (TARGET_SHMEDIA64
)
10889 rtx movi1
= GEN_INT (0xcc000010);
10890 rtx shori1
= GEN_INT (0xc8000010);
10893 /* The following trampoline works within a +- 128 KB range for cxt:
10894 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10895 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10896 gettr tr1,r1; blink tr0,r63 */
10897 /* Address rounding makes it hard to compute the exact bounds of the
10898 offset for this trampoline, but we have a rather generous offset
10899 range, so frame_offset should do fine as an upper bound. */
10900 if (cxt
== virtual_stack_vars_rtx
&& frame_offset
< 0x20000)
10902 /* ??? could optimize this trampoline initialization
10903 by writing DImode words with two insns each. */
10904 rtx mask
= force_reg (DImode
, GEN_INT (0x3fffc00));
10905 rtx insn
= gen_rtx_MINUS (DImode
, cxt
, tramp
);
10906 insn
= gen_rtx_ASHIFT (DImode
, insn
, GEN_INT (10-2));
10907 insn
= gen_rtx_AND (DImode
, insn
, mask
);
10908 /* Or in ptb/u .,tr1 pattern */
10909 insn
= gen_rtx_IOR (DImode
, insn
, gen_int_mode (0xec000010, SImode
));
10910 insn
= force_operand (insn
, NULL_RTX
);
10911 insn
= gen_lowpart (SImode
, insn
);
10912 emit_move_insn (change_address (tramp_mem
, SImode
, NULL_RTX
), insn
);
10913 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (38));
10914 insn
= gen_rtx_AND (DImode
, insn
, mask
);
10915 insn
= force_operand (gen_rtx_IOR (DImode
, movi1
, insn
), NULL_RTX
);
10916 insn
= gen_lowpart (SImode
, insn
);
10917 emit_move_insn (adjust_address (tramp_mem
, SImode
, 4), insn
);
10918 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (22));
10919 insn
= gen_rtx_AND (DImode
, insn
, mask
);
10920 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
10921 insn
= gen_lowpart (SImode
, insn
);
10922 emit_move_insn (adjust_address (tramp_mem
, SImode
, 8), insn
);
10923 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (6));
10924 insn
= gen_rtx_AND (DImode
, insn
, mask
);
10925 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
10926 insn
= gen_lowpart (SImode
, insn
);
10927 emit_move_insn (adjust_address (tramp_mem
, SImode
, 12), insn
);
10928 insn
= gen_rtx_ASHIFT (DImode
, fnaddr
, GEN_INT (10));
10929 insn
= gen_rtx_AND (DImode
, insn
, mask
);
10930 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
10931 insn
= gen_lowpart (SImode
, insn
);
10932 emit_move_insn (adjust_address (tramp_mem
, SImode
, 16), insn
);
10933 emit_move_insn (adjust_address (tramp_mem
, SImode
, 20),
10934 GEN_INT (0x6bf10600));
10935 emit_move_insn (adjust_address (tramp_mem
, SImode
, 24),
10936 GEN_INT (0x4415fc10));
10937 emit_move_insn (adjust_address (tramp_mem
, SImode
, 28),
10938 GEN_INT (0x4401fff0));
10939 emit_insn (gen_ic_invalidate_line (tramp
));
10942 tramp_templ
= gen_rtx_SYMBOL_REF (Pmode
,"__GCC_nested_trampoline");
10943 fixed_len
= TRAMPOLINE_SIZE
- 2 * GET_MODE_SIZE (Pmode
);
10945 tramp_templ
= gen_datalabel_ref (tramp_templ
);
10947 src
= gen_const_mem (BLKmode
, tramp_templ
);
10948 set_mem_align (dst
, 256);
10949 set_mem_align (src
, 64);
10950 emit_block_move (dst
, src
, GEN_INT (fixed_len
), BLOCK_OP_NORMAL
);
10952 emit_move_insn (adjust_address (tramp_mem
, Pmode
, fixed_len
), fnaddr
);
10953 emit_move_insn (adjust_address (tramp_mem
, Pmode
,
10954 fixed_len
+ GET_MODE_SIZE (Pmode
)),
10956 emit_insn (gen_ic_invalidate_line (tramp
));
10959 else if (TARGET_SHMEDIA
)
10961 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10962 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10963 rtx quad0
= gen_reg_rtx (DImode
), cxtload
= gen_reg_rtx (DImode
);
10964 rtx quad1
= gen_reg_rtx (DImode
), quad2
= gen_reg_rtx (DImode
);
10965 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10966 rotated 10 right, and higher 16 bit of every 32 selected. */
10968 = force_reg (V2HImode
, (simplify_gen_subreg
10969 (V2HImode
, GEN_INT (0x4330432), SImode
, 0)));
10970 rtx ptabs
= force_reg (DImode
, GEN_INT (0x6bf10600));
10971 rtx blink
= force_reg (DImode
, GEN_INT (0x4401fff0));
10973 fnaddr
= force_reg (SImode
, fnaddr
);
10974 cxt
= force_reg (SImode
, cxt
);
10975 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, quad0
, 0),
10976 gen_rtx_SUBREG (V2HImode
, fnaddr
, 0),
10978 emit_insn (gen_rotrdi3_mextr (quad0
, quad0
,
10979 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
10980 emit_insn (gen_ashldi3_media (quad0
, quad0
, const2_rtx
));
10981 emit_move_insn (change_address (tramp_mem
, DImode
, NULL_RTX
), quad0
);
10982 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, cxtload
, 0),
10983 gen_rtx_SUBREG (V2HImode
, cxt
, 0),
10985 emit_insn (gen_rotrdi3_mextr (cxtload
, cxtload
,
10986 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
10987 emit_insn (gen_ashldi3_media (cxtload
, cxtload
, const2_rtx
));
10988 if (TARGET_LITTLE_ENDIAN
)
10990 emit_insn (gen_mshflo_l_di (quad1
, ptabs
, cxtload
));
10991 emit_insn (gen_mextr4 (quad2
, cxtload
, blink
));
10995 emit_insn (gen_mextr4 (quad1
, cxtload
, ptabs
));
10996 emit_insn (gen_mshflo_l_di (quad2
, blink
, cxtload
));
10998 emit_move_insn (adjust_address (tramp_mem
, DImode
, 8), quad1
);
10999 emit_move_insn (adjust_address (tramp_mem
, DImode
, 16), quad2
);
11000 emit_insn (gen_ic_invalidate_line (tramp
));
11003 else if (TARGET_SHCOMPACT
)
11005 emit_insn (gen_initialize_trampoline (tramp
, cxt
, fnaddr
));
11008 emit_move_insn (change_address (tramp_mem
, SImode
, NULL_RTX
),
11009 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0xd301d202 : 0xd202d301,
11011 emit_move_insn (adjust_address (tramp_mem
, SImode
, 4),
11012 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0x0009422b : 0x422b0009,
11014 emit_move_insn (adjust_address (tramp_mem
, SImode
, 8), cxt
);
11015 emit_move_insn (adjust_address (tramp_mem
, SImode
, 12), fnaddr
);
11016 if (TARGET_HARVARD
)
11018 if (!TARGET_INLINE_IC_INVALIDATE
11019 || (!(TARGET_SH4A_ARCH
|| TARGET_SH4_300
) && TARGET_USERMODE
))
11020 emit_library_call (function_symbol (NULL
, "__ic_invalidate",
11021 FUNCTION_ORDINARY
),
11022 LCT_NORMAL
, VOIDmode
, 1, tramp
, SImode
);
11024 emit_insn (gen_ic_invalidate_line (tramp
));
11028 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
11031 sh_trampoline_adjust_address (rtx tramp
)
11033 if (TARGET_SHMEDIA
)
11034 tramp
= expand_simple_binop (Pmode
, PLUS
, tramp
, const1_rtx
,
11035 gen_reg_rtx (Pmode
), 0, OPTAB_LIB_WIDEN
);
11039 /* FIXME: This is overly conservative. A SHcompact function that
11040 receives arguments ``by reference'' will have them stored in its
11041 own stack frame, so it must not pass pointers or references to
11042 these arguments to other functions by means of sibling calls. */
11043 /* If PIC, we cannot make sibling calls to global functions
11044 because the PLT requires r12 to be live. */
11046 sh_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
11049 && (! TARGET_SHCOMPACT
11050 || crtl
->args
.info
.stack_regs
== 0)
11051 && ! sh_cfun_interrupt_handler_p ()
11053 || (decl
&& ! TREE_PUBLIC (decl
))
11054 || (decl
&& DECL_VISIBILITY (decl
) != VISIBILITY_DEFAULT
)));
11057 /* Machine specific built-in functions. */
11059 struct builtin_description
11061 const enum insn_code icode
;
11062 const char *const name
;
11067 /* describe number and signedness of arguments; arg[0] == result
11068 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
11069 /* 9: 64-bit pointer, 10: 32-bit pointer */
11070 static const char signature_args
[][4] =
11072 #define SH_BLTIN_V2SI2 0
11074 #define SH_BLTIN_V4HI2 1
11076 #define SH_BLTIN_V2SI3 2
11078 #define SH_BLTIN_V4HI3 3
11080 #define SH_BLTIN_V8QI3 4
11082 #define SH_BLTIN_MAC_HISI 5
11084 #define SH_BLTIN_SH_HI 6
11086 #define SH_BLTIN_SH_SI 7
11088 #define SH_BLTIN_V4HI2V2SI 8
11090 #define SH_BLTIN_V4HI2V8QI 9
11092 #define SH_BLTIN_SISF 10
11094 #define SH_BLTIN_LDUA_L 11
11096 #define SH_BLTIN_LDUA_Q 12
11098 #define SH_BLTIN_STUA_L 13
11100 #define SH_BLTIN_STUA_Q 14
11102 #define SH_BLTIN_LDUA_L64 15
11104 #define SH_BLTIN_LDUA_Q64 16
11106 #define SH_BLTIN_STUA_L64 17
11108 #define SH_BLTIN_STUA_Q64 18
11110 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
11111 #define SH_BLTIN_2 19
11112 #define SH_BLTIN_SU 19
11114 #define SH_BLTIN_3 20
11115 #define SH_BLTIN_SUS 20
11117 #define SH_BLTIN_PSSV 21
11119 #define SH_BLTIN_XXUU 22
11120 #define SH_BLTIN_UUUU 22
11122 #define SH_BLTIN_PV 23
11125 /* mcmv: operands considered unsigned. */
11126 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
11127 /* mperm: control value considered unsigned int. */
11128 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
11129 /* mshards_q: returns signed short. */
11130 /* nsb: takes long long arg, returns unsigned char. */
11131 static struct builtin_description bdesc
[] =
11133 { CODE_FOR_absv2si2
, "__builtin_absv2si2", SH_BLTIN_V2SI2
, 0 },
11134 { CODE_FOR_absv4hi2
, "__builtin_absv4hi2", SH_BLTIN_V4HI2
, 0 },
11135 { CODE_FOR_addv2si3
, "__builtin_addv2si3", SH_BLTIN_V2SI3
, 0 },
11136 { CODE_FOR_addv4hi3
, "__builtin_addv4hi3", SH_BLTIN_V4HI3
, 0 },
11137 { CODE_FOR_ssaddv2si3
,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3
, 0 },
11138 { CODE_FOR_usaddv8qi3
,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3
, 0 },
11139 { CODE_FOR_ssaddv4hi3
,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3
, 0 },
11140 { CODE_FOR_alloco_i
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
, 0 },
11141 { CODE_FOR_negcmpeqv8qi
,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3
, 0 },
11142 { CODE_FOR_negcmpeqv2si
,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3
, 0 },
11143 { CODE_FOR_negcmpeqv4hi
,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3
, 0 },
11144 { CODE_FOR_negcmpgtuv8qi
,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3
, 0 },
11145 { CODE_FOR_negcmpgtv2si
,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3
, 0 },
11146 { CODE_FOR_negcmpgtv4hi
,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3
, 0 },
11147 { CODE_FOR_mcmv
, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU
, 0 },
11148 { CODE_FOR_mcnvs_lw
, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3
, 0 },
11149 { CODE_FOR_mcnvs_wb
, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI
, 0 },
11150 { CODE_FOR_mcnvs_wub
, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI
, 0 },
11151 { CODE_FOR_mextr1
, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3
, 0 },
11152 { CODE_FOR_mextr2
, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3
, 0 },
11153 { CODE_FOR_mextr3
, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3
, 0 },
11154 { CODE_FOR_mextr4
, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3
, 0 },
11155 { CODE_FOR_mextr5
, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3
, 0 },
11156 { CODE_FOR_mextr6
, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3
, 0 },
11157 { CODE_FOR_mextr7
, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3
, 0 },
11158 { CODE_FOR_mmacfx_wl
, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI
, 0 },
11159 { CODE_FOR_mmacnfx_wl
,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI
, 0 },
11160 { CODE_FOR_mulv2si3
, "__builtin_mulv2si3", SH_BLTIN_V2SI3
, 0 },
11161 { CODE_FOR_mulv4hi3
, "__builtin_mulv4hi3", SH_BLTIN_V4HI3
, 0 },
11162 { CODE_FOR_mmulfx_l
, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3
, 0 },
11163 { CODE_FOR_mmulfx_w
, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3
, 0 },
11164 { CODE_FOR_mmulfxrp_w
,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3
, 0 },
11165 { CODE_FOR_mmulhi_wl
, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI
, 0 },
11166 { CODE_FOR_mmullo_wl
, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI
, 0 },
11167 { CODE_FOR_mmulsum_wq
,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU
, 0 },
11168 { CODE_FOR_mperm_w
, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI
, 0 },
11169 { CODE_FOR_msad_ubq
, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU
, 0 },
11170 { CODE_FOR_mshalds_l
, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI
, 0 },
11171 { CODE_FOR_mshalds_w
, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI
, 0 },
11172 { CODE_FOR_ashrv2si3
, "__builtin_ashrv2si3", SH_BLTIN_SH_SI
, 0 },
11173 { CODE_FOR_ashrv4hi3
, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI
, 0 },
11174 { CODE_FOR_mshards_q
, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS
, 0 },
11175 { CODE_FOR_mshfhi_b
, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3
, 0 },
11176 { CODE_FOR_mshfhi_l
, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3
, 0 },
11177 { CODE_FOR_mshfhi_w
, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3
, 0 },
11178 { CODE_FOR_mshflo_b
, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3
, 0 },
11179 { CODE_FOR_mshflo_l
, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3
, 0 },
11180 { CODE_FOR_mshflo_w
, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3
, 0 },
11181 { CODE_FOR_ashlv2si3
, "__builtin_ashlv2si3", SH_BLTIN_SH_SI
, 0 },
11182 { CODE_FOR_ashlv4hi3
, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI
, 0 },
11183 { CODE_FOR_lshrv2si3
, "__builtin_lshrv2si3", SH_BLTIN_SH_SI
, 0 },
11184 { CODE_FOR_lshrv4hi3
, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI
, 0 },
11185 { CODE_FOR_subv2si3
, "__builtin_subv2si3", SH_BLTIN_V2SI3
, 0 },
11186 { CODE_FOR_subv4hi3
, "__builtin_subv4hi3", SH_BLTIN_V4HI3
, 0 },
11187 { CODE_FOR_sssubv2si3
,"__builtin_sssubv2si3", SH_BLTIN_V2SI3
, 0 },
11188 { CODE_FOR_ussubv8qi3
,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3
, 0 },
11189 { CODE_FOR_sssubv4hi3
,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3
, 0 },
11190 { CODE_FOR_fcosa_s
, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF
, 0 },
11191 { CODE_FOR_fsina_s
, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF
, 0 },
11192 { CODE_FOR_fipr
, "__builtin_sh_media_FIPR_S", SH_BLTIN_3
, 0 },
11193 { CODE_FOR_ftrv
, "__builtin_sh_media_FTRV_S", SH_BLTIN_3
, 0 },
11194 { CODE_FOR_mac_media
, "__builtin_sh_media_FMAC_S", SH_BLTIN_3
, 0 },
11195 { CODE_FOR_sqrtdf2
, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2
, 0 },
11196 { CODE_FOR_sqrtsf2
, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2
, 0 },
11197 { CODE_FOR_fsrra_s
, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2
, 0 },
11198 { CODE_FOR_ldhi_l
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
, 0 },
11199 { CODE_FOR_ldhi_q
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
, 0 },
11200 { CODE_FOR_ldlo_l
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
, 0 },
11201 { CODE_FOR_ldlo_q
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
, 0 },
11202 { CODE_FOR_sthi_l
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
, 0 },
11203 { CODE_FOR_sthi_q
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
, 0 },
11204 { CODE_FOR_stlo_l
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
, 0 },
11205 { CODE_FOR_stlo_q
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
, 0 },
11206 { CODE_FOR_ldhi_l64
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64
, 0 },
11207 { CODE_FOR_ldhi_q64
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64
, 0 },
11208 { CODE_FOR_ldlo_l64
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64
, 0 },
11209 { CODE_FOR_ldlo_q64
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64
, 0 },
11210 { CODE_FOR_sthi_l64
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64
, 0 },
11211 { CODE_FOR_sthi_q64
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64
, 0 },
11212 { CODE_FOR_stlo_l64
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64
, 0 },
11213 { CODE_FOR_stlo_q64
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64
, 0 },
11214 { CODE_FOR_nsb
, "__builtin_sh_media_NSB", SH_BLTIN_SU
, 0 },
11215 { CODE_FOR_byterev
, "__builtin_sh_media_BYTEREV", SH_BLTIN_2
, 0 },
11216 { CODE_FOR_prefetch
, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV
, 0 },
11220 sh_media_init_builtins (void)
11222 tree shared
[SH_BLTIN_NUM_SHARED_SIGNATURES
];
11223 struct builtin_description
*d
;
11225 memset (shared
, 0, sizeof shared
);
11226 for (d
= bdesc
; d
- bdesc
< (int) ARRAY_SIZE (bdesc
); d
++)
11228 tree type
, arg_type
= 0;
11229 int signature
= d
->signature
;
11232 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
&& shared
[signature
])
11233 type
= shared
[signature
];
11236 int has_result
= signature_args
[signature
][0] != 0;
11239 if ((signature_args
[signature
][1] & 8)
11240 && (((signature_args
[signature
][1] & 1) && TARGET_SHMEDIA32
)
11241 || ((signature_args
[signature
][1] & 2) && TARGET_SHMEDIA64
)))
11243 if (! TARGET_FPU_ANY
11244 && FLOAT_MODE_P (insn_data
[d
->icode
].operand
[0].mode
))
11246 for (i
= 0; i
< (int) ARRAY_SIZE (args
); i
++)
11247 args
[i
] = NULL_TREE
;
11250 int arg
= signature_args
[signature
][i
];
11251 int opno
= i
- 1 + has_result
;
11254 arg_type
= ptr_type_node
;
11256 arg_type
= (*lang_hooks
.types
.type_for_mode
)
11257 (insn_data
[d
->icode
].operand
[opno
].mode
,
11262 arg_type
= void_type_node
;
11265 args
[i
-1] = arg_type
;
11267 type
= build_function_type_list (arg_type
, args
[0], args
[1],
11268 args
[2], NULL_TREE
);
11269 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
)
11270 shared
[signature
] = type
;
11273 add_builtin_function (d
->name
, type
, d
- bdesc
, BUILT_IN_MD
,
11278 /* Returns the shmedia builtin decl for CODE. */
11281 sh_media_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11283 if (code
>= ARRAY_SIZE (bdesc
))
11284 return error_mark_node
;
11286 return bdesc
[code
].fndecl
;
11289 /* Implements target hook vector_mode_supported_p. */
11291 sh_vector_mode_supported_p (enum machine_mode mode
)
11294 && ((mode
== V2SFmode
)
11295 || (mode
== V4SFmode
)
11296 || (mode
== V16SFmode
)))
11299 else if (TARGET_SHMEDIA
11300 && ((mode
== V8QImode
)
11301 || (mode
== V2HImode
)
11302 || (mode
== V4HImode
)
11303 || (mode
== V2SImode
)))
11310 sh_frame_pointer_required (void)
11312 /* If needed override this in other tm.h files to cope with various OS
11313 lossage requiring a frame pointer. */
11314 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
11323 /* Implements target hook dwarf_calling_convention. Return an enum
11324 of dwarf_calling_convention. */
11326 sh_dwarf_calling_convention (const_tree func
)
11328 if (sh_attr_renesas_p (func
))
11329 return DW_CC_GNU_renesas_sh
;
11331 return DW_CC_normal
;
11335 sh_init_builtins (void)
11337 if (TARGET_SHMEDIA
)
11338 sh_media_init_builtins ();
11341 /* Returns the sh builtin decl for CODE. */
11344 sh_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11346 if (TARGET_SHMEDIA
)
11347 return sh_media_builtin_decl (code
, initialize_p
);
11349 return error_mark_node
;
11352 /* Expand an expression EXP that calls a built-in function,
11353 with result going to TARGET if that's convenient
11354 (and in mode MODE if that's convenient).
11355 SUBTARGET may be used as the target for computing one of EXP's operands.
11356 IGNORE is nonzero if the value is to be ignored. */
11359 sh_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
11360 enum machine_mode mode ATTRIBUTE_UNUSED
, int ignore
)
11362 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11363 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11364 const struct builtin_description
*d
= &bdesc
[fcode
];
11365 enum insn_code icode
= d
->icode
;
11366 int signature
= d
->signature
;
11367 enum machine_mode tmode
= VOIDmode
;
11372 if (signature_args
[signature
][0])
11377 tmode
= insn_data
[icode
].operand
[0].mode
;
11379 || GET_MODE (target
) != tmode
11380 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11381 target
= gen_reg_rtx (tmode
);
11382 op
[nop
++] = target
;
11387 for (i
= 1; i
<= 3; i
++, nop
++)
11390 enum machine_mode opmode
, argmode
;
11393 if (! signature_args
[signature
][i
])
11395 arg
= CALL_EXPR_ARG (exp
, i
- 1);
11396 if (arg
== error_mark_node
)
11398 if (signature_args
[signature
][i
] & 8)
11401 optype
= ptr_type_node
;
11405 opmode
= insn_data
[icode
].operand
[nop
].mode
;
11406 optype
= (*lang_hooks
.types
.type_for_mode
) (opmode
, 0);
11408 argmode
= TYPE_MODE (TREE_TYPE (arg
));
11409 if (argmode
!= opmode
)
11410 arg
= build1 (NOP_EXPR
, optype
, arg
);
11411 op
[nop
] = expand_expr (arg
, NULL_RTX
, opmode
, EXPAND_NORMAL
);
11412 if (! (*insn_data
[icode
].operand
[nop
].predicate
) (op
[nop
], opmode
))
11413 op
[nop
] = copy_to_mode_reg (opmode
, op
[nop
]);
11419 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0]);
11422 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1]);
11425 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2]);
11428 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2], op
[3]);
11431 gcc_unreachable ();
11440 sh_expand_unop_v2sf (enum rtx_code code
, rtx op0
, rtx op1
)
11442 rtx sel0
= const0_rtx
;
11443 rtx sel1
= const1_rtx
;
11444 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
, rtx
) = gen_unary_sf_op
;
11445 rtx op
= gen_rtx_fmt_e (code
, SFmode
, op1
);
11447 emit_insn ((*fn
) (op0
, op1
, op
, sel0
, sel0
));
11448 emit_insn ((*fn
) (op0
, op1
, op
, sel1
, sel1
));
11452 sh_expand_binop_v2sf (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
11454 rtx op
= gen_rtx_fmt_ee (code
, SFmode
, op1
, op2
);
11456 emit_insn (gen_binary_sf_op0 (op0
, op1
, op2
, op
));
11457 emit_insn (gen_binary_sf_op1 (op0
, op1
, op2
, op
));
11460 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
11461 We can allow any mode in any general register. The special registers
11462 only allow SImode. Don't allow any mode in the PR.
11464 We cannot hold DCmode values in the XD registers because alter_reg
11465 handles subregs of them incorrectly. We could work around this by
11466 spacing the XD registers like the DR registers, but this would require
11467 additional memory in every compilation to hold larger register vectors.
11468 We could hold SFmode / SCmode values in XD registers, but that
11469 would require a tertiary reload when reloading from / to memory,
11470 and a secondary reload to reload from / to general regs; that
11471 seems to be a loosing proposition.
11473 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
11474 it won't be ferried through GP registers first. */
11477 sh_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11479 if (SPECIAL_REGISTER_P (regno
))
11480 return mode
== SImode
;
11482 if (regno
== FPUL_REG
)
11483 return (mode
== SImode
|| mode
== SFmode
);
11485 if (FP_REGISTER_P (regno
) && mode
== SFmode
)
11488 if (mode
== V2SFmode
)
11490 if (((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 2 == 0)
11491 || GENERAL_REGISTER_P (regno
)))
11497 if (mode
== V4SFmode
)
11499 if ((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 4 == 0)
11500 || GENERAL_REGISTER_P (regno
))
11506 if (mode
== V16SFmode
)
11508 if (TARGET_SHMEDIA
)
11510 if (FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 16 == 0)
11516 return regno
== FIRST_XD_REG
;
11519 if (FP_REGISTER_P (regno
))
11523 || ((TARGET_SH2E
|| TARGET_SHMEDIA
) && mode
== SCmode
)
11524 || ((((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && mode
== DFmode
)
11527 && (mode
== DFmode
|| mode
== DImode
11528 || mode
== V2SFmode
|| mode
== TImode
)))
11529 && ((regno
- FIRST_FP_REG
) & 1) == 0)
11530 || ((TARGET_SH4
|| TARGET_SHMEDIA
) && mode
== TImode
11531 && ((regno
- FIRST_FP_REG
) & 3) == 0))
11537 if (XD_REGISTER_P (regno
))
11538 return mode
== DFmode
;
11540 if (TARGET_REGISTER_P (regno
))
11541 return (mode
== DImode
|| mode
== SImode
|| mode
== PDImode
);
11543 if (regno
== PR_REG
)
11544 return mode
== SImode
;
11546 if (regno
== FPSCR_REG
)
11547 return mode
== PSImode
;
11549 /* FIXME. This works around PR target/37633 for -O0. */
11550 if (!optimize
&& TARGET_SHMEDIA32
&& GET_MODE_SIZE (mode
) > 4)
11552 unsigned int n
= GET_MODE_SIZE (mode
) / 8;
11554 if (regno
>= FIRST_GENERAL_REG
+ 10 - n
+ 1
11555 && regno
<= FIRST_GENERAL_REG
+ 14)
11562 /* Return the class of registers for which a mode change from FROM to TO
11565 sh_cannot_change_mode_class (enum machine_mode from
, enum machine_mode to
,
11566 enum reg_class rclass
)
11568 /* We want to enable the use of SUBREGs as a means to
11569 VEC_SELECT a single element of a vector. */
11571 /* This effectively disallows using GENERAL_REGS for SFmode vector subregs.
11572 This can be problematic when SFmode vector subregs need to be accessed
11573 on the stack with displacement addressing, as it happens with -O0.
11574 Thus we disallow the mode change for -O0. */
11575 if (to
== SFmode
&& VECTOR_MODE_P (from
) && GET_MODE_INNER (from
) == SFmode
)
11576 return optimize
? (reg_classes_intersect_p (GENERAL_REGS
, rclass
)) : false;
11578 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
11580 if (TARGET_LITTLE_ENDIAN
)
11582 if (GET_MODE_SIZE (to
) < 8 || GET_MODE_SIZE (from
) < 8)
11583 return reg_classes_intersect_p (DF_REGS
, rclass
);
11587 if (GET_MODE_SIZE (from
) < 8)
11588 return reg_classes_intersect_p (DF_HI_REGS
, rclass
);
11594 /* Return true if registers in machine mode MODE will likely be
11595 allocated to registers in small register classes. */
11598 sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED
)
11600 return (! TARGET_SHMEDIA
);
11603 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11604 that label is used. */
11607 sh_mark_label (rtx address
, int nuses
)
11609 if (GOTOFF_P (address
))
11611 /* Extract the label or symbol. */
11612 address
= XEXP (address
, 0);
11613 if (GET_CODE (address
) == PLUS
)
11614 address
= XEXP (address
, 0);
11615 address
= XVECEXP (address
, 0, 0);
11617 if (GET_CODE (address
) == LABEL_REF
11618 && LABEL_P (XEXP (address
, 0)))
11619 LABEL_NUSES (XEXP (address
, 0)) += nuses
;
11622 /* Compute extra cost of moving data between one register class
11625 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11626 uses this information. Hence, the general register <-> floating point
11627 register information here is not used for SFmode. */
11630 sh_register_move_cost (enum machine_mode mode
,
11631 reg_class_t srcclass
, reg_class_t dstclass
)
11633 if (dstclass
== T_REGS
|| dstclass
== PR_REGS
)
11636 if (dstclass
== MAC_REGS
&& srcclass
== MAC_REGS
)
11639 if (mode
== SImode
&& ! TARGET_SHMEDIA
&& TARGET_FMOVD
11640 && REGCLASS_HAS_FP_REG (srcclass
)
11641 && REGCLASS_HAS_FP_REG (dstclass
))
11644 if (REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== T_REGS
)
11645 return ((TARGET_HARD_SH4
&& !optimize_size
) ? 10 : 7);
11647 if ((REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== MAC_REGS
)
11648 || (dstclass
== MAC_REGS
&& REGCLASS_HAS_FP_REG (srcclass
)))
11651 if ((REGCLASS_HAS_FP_REG (dstclass
)
11652 && REGCLASS_HAS_GENERAL_REG (srcclass
))
11653 || (REGCLASS_HAS_GENERAL_REG (dstclass
)
11654 && REGCLASS_HAS_FP_REG (srcclass
)))
11656 /* Discourage trying to use fp regs for a pointer. This also
11657 discourages fp regs with SImode because Pmode is an alias
11658 of SImode on this target. See PR target/48596. */
11659 int addend
= (mode
== Pmode
) ? 40 : 0;
11661 return (((TARGET_SHMEDIA
? 4 : TARGET_FMOVD
? 8 : 12) + addend
)
11662 * ((GET_MODE_SIZE (mode
) + 7) / 8U));
11665 if ((dstclass
== FPUL_REGS
11666 && REGCLASS_HAS_GENERAL_REG (srcclass
))
11667 || (srcclass
== FPUL_REGS
11668 && REGCLASS_HAS_GENERAL_REG (dstclass
)))
11671 if ((dstclass
== FPUL_REGS
11672 && (srcclass
== PR_REGS
|| srcclass
== MAC_REGS
|| srcclass
== T_REGS
))
11673 || (srcclass
== FPUL_REGS
11674 && (dstclass
== PR_REGS
|| dstclass
== MAC_REGS
)))
11677 if ((srcclass
== TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
11678 || ((dstclass
) == TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
11681 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11683 && ((srcclass
) == TARGET_REGS
|| (srcclass
) == SIBCALL_REGS
))
11685 if (sh_gettrcost
>= 0)
11686 return sh_gettrcost
;
11687 else if (!TARGET_PT_FIXED
)
11691 if ((srcclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
11692 || (dstclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
11697 && ! REGCLASS_HAS_GENERAL_REG (srcclass
)
11698 && ! REGCLASS_HAS_GENERAL_REG (dstclass
)))
11699 return 2 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
11701 return 2 * ((GET_MODE_SIZE (mode
) + 3) / 4U);
11704 static rtx
emit_load_ptr (rtx
, rtx
);
11707 emit_load_ptr (rtx reg
, rtx addr
)
11709 rtx mem
= gen_const_mem (ptr_mode
, addr
);
11711 if (Pmode
!= ptr_mode
)
11712 mem
= gen_rtx_SIGN_EXTEND (Pmode
, mem
);
11713 return emit_move_insn (reg
, mem
);
11717 sh_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11718 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11721 CUMULATIVE_ARGS cum
;
11722 int structure_value_byref
= 0;
11723 rtx this_rtx
, this_value
, sibcall
, insns
, funexp
;
11724 tree funtype
= TREE_TYPE (function
);
11725 int simple_add
= CONST_OK_FOR_ADD (delta
);
11727 rtx scratch0
, scratch1
, scratch2
;
11730 reload_completed
= 1;
11731 epilogue_completed
= 1;
11732 current_function_uses_only_leaf_regs
= 1;
11734 emit_note (NOTE_INSN_PROLOGUE_END
);
11736 /* Find the "this" pointer. We have such a wide range of ABIs for the
11737 SH that it's best to do this completely machine independently.
11738 "this" is passed as first argument, unless a structure return pointer
11739 comes first, in which case "this" comes second. */
11740 INIT_CUMULATIVE_ARGS (cum
, funtype
, NULL_RTX
, 0, 1);
11741 #ifndef PCC_STATIC_STRUCT_RETURN
11742 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11743 structure_value_byref
= 1;
11744 #endif /* not PCC_STATIC_STRUCT_RETURN */
11745 if (structure_value_byref
&& sh_struct_value_rtx (function
, 0) == 0)
11747 tree ptype
= build_pointer_type (TREE_TYPE (funtype
));
11749 sh_function_arg_advance (pack_cumulative_args (&cum
), Pmode
, ptype
, true);
11752 = sh_function_arg (pack_cumulative_args (&cum
), Pmode
, ptr_type_node
, true);
11754 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11755 static chain pointer (even if you can't have nested virtual functions
11756 right now, someone might implement them sometime), and the rest of the
11757 registers are used for argument passing, are callee-saved, or reserved. */
11758 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11759 -ffixed-reg has been used. */
11760 if (! call_used_regs
[0] || fixed_regs
[0])
11761 error ("r0 needs to be available as a call-clobbered register");
11762 scratch0
= scratch1
= scratch2
= gen_rtx_REG (Pmode
, 0);
11765 if (call_used_regs
[1] && ! fixed_regs
[1])
11766 scratch1
= gen_rtx_REG (ptr_mode
, 1);
11767 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11768 pointing where to return struct values. */
11769 if (call_used_regs
[3] && ! fixed_regs
[3])
11770 scratch2
= gen_rtx_REG (Pmode
, 3);
11772 else if (TARGET_SHMEDIA
)
11774 for (i
= FIRST_GENERAL_REG
; i
<= LAST_GENERAL_REG
; i
++)
11775 if (i
!= REGNO (scratch0
) &&
11776 call_used_regs
[i
] && ! fixed_regs
[i
] && ! FUNCTION_ARG_REGNO_P (i
))
11778 scratch1
= gen_rtx_REG (ptr_mode
, i
);
11781 if (scratch1
== scratch0
)
11782 error ("need a second call-clobbered general purpose register");
11783 for (i
= FIRST_TARGET_REG
; i
<= LAST_TARGET_REG
; i
++)
11784 if (call_used_regs
[i
] && ! fixed_regs
[i
])
11786 scratch2
= gen_rtx_REG (Pmode
, i
);
11789 if (scratch2
== scratch0
)
11790 error ("need a call-clobbered target register");
11793 this_value
= plus_constant (this_rtx
, delta
);
11795 && (simple_add
|| scratch0
!= scratch1
)
11796 && strict_memory_address_p (ptr_mode
, this_value
))
11798 emit_load_ptr (scratch0
, this_value
);
11803 ; /* Do nothing. */
11804 else if (simple_add
)
11805 emit_move_insn (this_rtx
, this_value
);
11808 emit_move_insn (scratch1
, GEN_INT (delta
));
11809 emit_insn (gen_add2_insn (this_rtx
, scratch1
));
11817 emit_load_ptr (scratch0
, this_rtx
);
11819 offset_addr
= plus_constant (scratch0
, vcall_offset
);
11820 if (strict_memory_address_p (ptr_mode
, offset_addr
))
11821 ; /* Do nothing. */
11822 else if (! TARGET_SH5
&& scratch0
!= scratch1
)
11824 /* scratch0 != scratch1, and we have indexed loads. Get better
11825 schedule by loading the offset into r1 and using an indexed
11826 load - then the load of r1 can issue before the load from
11827 (this_rtx + delta) finishes. */
11828 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
11829 offset_addr
= gen_rtx_PLUS (Pmode
, scratch0
, scratch1
);
11831 else if (CONST_OK_FOR_ADD (vcall_offset
))
11833 emit_insn (gen_add2_insn (scratch0
, GEN_INT (vcall_offset
)));
11834 offset_addr
= scratch0
;
11836 else if (scratch0
!= scratch1
)
11838 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
11839 emit_insn (gen_add2_insn (scratch0
, scratch1
));
11840 offset_addr
= scratch0
;
11843 gcc_unreachable (); /* FIXME */
11844 emit_load_ptr (scratch0
, offset_addr
);
11846 if (Pmode
!= ptr_mode
)
11847 scratch0
= gen_rtx_TRUNCATE (ptr_mode
, scratch0
);
11848 emit_insn (gen_add2_insn (this_rtx
, scratch0
));
11851 /* Generate a tail call to the target function. */
11852 if (! TREE_USED (function
))
11854 assemble_external (function
);
11855 TREE_USED (function
) = 1;
11857 funexp
= XEXP (DECL_RTL (function
), 0);
11858 /* If the function is overridden, so is the thunk, hence we don't
11859 need GOT addressing even if this is a public symbol. */
11861 if (TARGET_SH1
&& ! flag_weak
)
11862 sibcall
= gen_sibcalli_thunk (funexp
, const0_rtx
);
11865 if (TARGET_SH2
&& flag_pic
)
11867 sibcall
= gen_sibcall_pcrel (funexp
, const0_rtx
);
11868 XEXP (XVECEXP (sibcall
, 0, 2), 0) = scratch2
;
11872 if (TARGET_SHMEDIA
&& flag_pic
)
11874 funexp
= gen_sym2PIC (funexp
);
11875 PUT_MODE (funexp
, Pmode
);
11877 emit_move_insn (scratch2
, funexp
);
11878 funexp
= gen_rtx_MEM (FUNCTION_MODE
, scratch2
);
11879 sibcall
= gen_sibcall (funexp
, const0_rtx
, NULL_RTX
);
11881 sibcall
= emit_call_insn (sibcall
);
11882 SIBLING_CALL_P (sibcall
) = 1;
11883 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall
), this_rtx
);
11886 /* Run just enough of rest_of_compilation to do scheduling and get
11887 the insns emitted. Note that use_thunk calls
11888 assemble_start_function and assemble_end_function. */
11890 insn_locators_alloc ();
11891 insns
= get_insns ();
11897 split_all_insns_noflow ();
11901 shorten_branches (insns
);
11902 final_start_function (insns
, file
, 1);
11903 final (insns
, file
, 1);
11904 final_end_function ();
11906 reload_completed
= 0;
11907 epilogue_completed
= 0;
11911 function_symbol (rtx target
, const char *name
, enum sh_function_kind kind
)
11915 /* If this is not an ordinary function, the name usually comes from a
11916 string literal or an sprintf buffer. Make sure we use the same
11917 string consistently, so that cse will be able to unify address loads. */
11918 if (kind
!= FUNCTION_ORDINARY
)
11919 name
= IDENTIFIER_POINTER (get_identifier (name
));
11920 sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
11921 SYMBOL_REF_FLAGS (sym
) = SYMBOL_FLAG_FUNCTION
;
11925 case FUNCTION_ORDINARY
:
11929 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
11931 emit_insn (gen_symGOT2reg (reg
, sym
));
11937 /* ??? To allow cse to work, we use GOTOFF relocations.
11938 we could add combiner patterns to transform this into
11939 straight pc-relative calls with sym2PIC / bsrf when
11940 label load and function call are still 1:1 and in the
11941 same basic block during combine. */
11942 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
11944 emit_insn (gen_symGOTOFF2reg (reg
, sym
));
11949 if (target
&& sym
!= target
)
11951 emit_move_insn (target
, sym
);
11957 /* Find the number of a general purpose register in S. */
11959 scavenge_reg (HARD_REG_SET
*s
)
11962 for (r
= FIRST_GENERAL_REG
; r
<= LAST_GENERAL_REG
; r
++)
11963 if (TEST_HARD_REG_BIT (*s
, r
))
11969 sh_get_pr_initial_val (void)
11973 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11974 PR register on SHcompact, because it might be clobbered by the prologue.
11975 We check first if that is known to be the case. */
11976 if (TARGET_SHCOMPACT
11977 && ((crtl
->args
.info
.call_cookie
11978 & ~ CALL_COOKIE_RET_TRAMP (1))
11979 || crtl
->saves_all_registers
))
11980 return gen_frame_mem (SImode
, return_address_pointer_rtx
);
11982 /* If we haven't finished rtl generation, there might be a nonlocal label
11983 that we haven't seen yet.
11984 ??? get_hard_reg_initial_val fails if it is called after register
11985 allocation has started, unless it has been called before for the
11986 same register. And even then, we end in trouble if we didn't use
11987 the register in the same basic block before. So call
11988 get_hard_reg_initial_val now and wrap it in an unspec if we might
11989 need to replace it. */
11990 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11991 combine can put the pseudo returned by get_hard_reg_initial_val into
11992 instructions that need a general purpose registers, which will fail to
11993 be recognized when the pseudo becomes allocated to PR. */
11995 = get_hard_reg_initial_val (Pmode
, TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
11997 return gen_rtx_UNSPEC (SImode
, gen_rtvec (1, val
), UNSPEC_RA
);
12002 sh_expand_t_scc (rtx operands
[])
12004 enum rtx_code code
= GET_CODE (operands
[1]);
12005 rtx target
= operands
[0];
12006 rtx op0
= operands
[2];
12007 rtx op1
= operands
[3];
12008 rtx result
= target
;
12011 if (!REG_P (op0
) || REGNO (op0
) != T_REG
12012 || !CONST_INT_P (op1
))
12014 if (!REG_P (result
))
12015 result
= gen_reg_rtx (SImode
);
12016 val
= INTVAL (op1
);
12017 if ((code
== EQ
&& val
== 1) || (code
== NE
&& val
== 0))
12018 emit_insn (gen_movt (result
));
12019 else if ((code
== EQ
&& val
== 0) || (code
== NE
&& val
== 1))
12020 emit_insn (gen_movnegt (result
));
12021 else if (code
== EQ
|| code
== NE
)
12022 emit_insn (gen_move_insn (result
, GEN_INT (code
== NE
)));
12025 if (result
!= target
)
12026 emit_move_insn (target
, result
);
12030 /* INSN is an sfunc; return the rtx that describes the address used. */
12032 extract_sfunc_addr (rtx insn
)
12034 rtx pattern
, part
= NULL_RTX
;
12037 pattern
= PATTERN (insn
);
12038 len
= XVECLEN (pattern
, 0);
12039 for (i
= 0; i
< len
; i
++)
12041 part
= XVECEXP (pattern
, 0, i
);
12042 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == Pmode
12043 && GENERAL_REGISTER_P (true_regnum (XEXP (part
, 0))))
12044 return XEXP (part
, 0);
12046 gcc_assert (GET_CODE (XVECEXP (pattern
, 0, 0)) == UNSPEC_VOLATILE
);
12047 return XVECEXP (XVECEXP (pattern
, 0, 0), 0, 1);
12050 /* Verify that the register in use_sfunc_addr still agrees with the address
12051 used in the sfunc. This prevents fill_slots_from_thread from changing
12053 INSN is the use_sfunc_addr instruction, and REG is the register it
12056 check_use_sfunc_addr (rtx insn
, rtx reg
)
12058 /* Search for the sfunc. It should really come right after INSN. */
12059 while ((insn
= NEXT_INSN (insn
)))
12061 if (LABEL_P (insn
) || JUMP_P (insn
))
12063 if (! INSN_P (insn
))
12066 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
12067 insn
= XVECEXP (PATTERN (insn
), 0, 0);
12068 if (GET_CODE (PATTERN (insn
)) != PARALLEL
12069 || get_attr_type (insn
) != TYPE_SFUNC
)
12071 return rtx_equal_p (extract_sfunc_addr (insn
), reg
);
12073 gcc_unreachable ();
12076 /* This function returns a constant rtx that represents pi / 2**15 in
12077 SFmode. it's used to scale SFmode angles, in radians, to a
12078 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
12079 maps to 0x10000). */
12081 static GTY(()) rtx sh_fsca_sf2int_rtx
;
12084 sh_fsca_sf2int (void)
12086 if (! sh_fsca_sf2int_rtx
)
12088 REAL_VALUE_TYPE rv
;
12090 real_from_string (&rv
, "10430.378350470453");
12091 sh_fsca_sf2int_rtx
= const_double_from_real_value (rv
, SFmode
);
12094 return sh_fsca_sf2int_rtx
;
12097 /* This function returns a constant rtx that represents 2**15 / pi in
12098 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
12099 of a full circle back to a SFmode value, i.e., 0x10000 maps to
12102 static GTY(()) rtx sh_fsca_int2sf_rtx
;
12105 sh_fsca_int2sf (void)
12107 if (! sh_fsca_int2sf_rtx
)
12109 REAL_VALUE_TYPE rv
;
12111 real_from_string (&rv
, "9.587379924285257e-5");
12112 sh_fsca_int2sf_rtx
= const_double_from_real_value (rv
, SFmode
);
12115 return sh_fsca_int2sf_rtx
;
12118 /* Initialize the CUMULATIVE_ARGS structure. */
12121 sh_init_cumulative_args (CUMULATIVE_ARGS
* pcum
,
12123 rtx libname ATTRIBUTE_UNUSED
,
12125 signed int n_named_args
,
12126 enum machine_mode mode
)
12128 pcum
->arg_count
[(int) SH_ARG_FLOAT
] = 0;
12129 pcum
->free_single_fp_reg
= 0;
12130 pcum
->stack_regs
= 0;
12131 pcum
->byref_regs
= 0;
12133 pcum
->outgoing
= (n_named_args
== -1) ? 0 : 1;
12135 /* XXX - Should we check TARGET_HITACHI here ??? */
12136 pcum
->renesas_abi
= sh_attr_renesas_p (fntype
) ? 1 : 0;
12140 pcum
->force_mem
= ((TARGET_HITACHI
|| pcum
->renesas_abi
)
12141 && aggregate_value_p (TREE_TYPE (fntype
), fndecl
));
12142 pcum
->prototype_p
= prototype_p (fntype
);
12143 pcum
->arg_count
[(int) SH_ARG_INT
]
12144 = TARGET_SH5
&& aggregate_value_p (TREE_TYPE (fntype
), fndecl
);
12147 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12148 && pcum
->arg_count
[(int) SH_ARG_INT
] == 0
12149 && (TYPE_MODE (TREE_TYPE (fntype
)) == BLKmode
12150 ? int_size_in_bytes (TREE_TYPE (fntype
))
12151 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype
)))) > 4
12152 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype
)))
12153 == FIRST_RET_REG
));
12157 pcum
->arg_count
[(int) SH_ARG_INT
] = 0;
12158 pcum
->prototype_p
= FALSE
;
12159 if (mode
!= VOIDmode
)
12161 pcum
->call_cookie
=
12162 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12163 && GET_MODE_SIZE (mode
) > 4
12164 && BASE_RETURN_VALUE_REG (mode
) == FIRST_RET_REG
);
12166 /* If the default ABI is the Renesas ABI then all library
12167 calls must assume that the library will be using the
12168 Renesas ABI. So if the function would return its result
12169 in memory then we must force the address of this memory
12170 block onto the stack. Ideally we would like to call
12171 targetm.calls.return_in_memory() here but we do not have
12172 the TYPE or the FNDECL available so we synthesize the
12173 contents of that function as best we can. */
12175 (TARGET_DEFAULT
& MASK_HITACHI
)
12176 && (mode
== BLKmode
12177 || (GET_MODE_SIZE (mode
) > 4
12178 && !(mode
== DFmode
12179 && TARGET_FPU_DOUBLE
)));
12183 pcum
->call_cookie
= 0;
12184 pcum
->force_mem
= FALSE
;
12189 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
12190 not enter into CONST_DOUBLE for the replace.
12192 Note that copying is not done so X must not be shared unless all copies
12193 are to be modified.
12195 This is like replace_rtx, except that we operate on N_REPLACEMENTS
12196 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
12197 replacements[n*2+1] - and that we take mode changes into account.
12199 If a replacement is ambiguous, return NULL_RTX.
12201 If MODIFY is zero, don't modify any rtl in place,
12202 just return zero or nonzero for failure / success. */
12205 replace_n_hard_rtx (rtx x
, rtx
*replacements
, int n_replacements
, int modify
)
12210 /* The following prevents loops occurrence when we change MEM in
12211 CONST_DOUBLE onto the same CONST_DOUBLE. */
12212 if (x
!= 0 && GET_CODE (x
) == CONST_DOUBLE
)
12215 for (i
= n_replacements
- 1; i
>= 0 ; i
--)
12216 if (x
== replacements
[i
*2] && GET_MODE (x
) == GET_MODE (replacements
[i
*2+1]))
12217 return replacements
[i
*2+1];
12219 /* Allow this function to make replacements in EXPR_LISTs. */
12223 if (GET_CODE (x
) == SUBREG
)
12225 rtx new_rtx
= replace_n_hard_rtx (SUBREG_REG (x
), replacements
,
12226 n_replacements
, modify
);
12228 if (CONST_INT_P (new_rtx
))
12230 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
12231 GET_MODE (SUBREG_REG (x
)),
12237 SUBREG_REG (x
) = new_rtx
;
12241 else if (REG_P (x
))
12243 unsigned regno
= REGNO (x
);
12244 unsigned nregs
= (regno
< FIRST_PSEUDO_REGISTER
12245 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
12246 rtx result
= NULL_RTX
;
12248 for (i
= n_replacements
- 1; i
>= 0; i
--)
12250 rtx from
= replacements
[i
*2];
12251 rtx to
= replacements
[i
*2+1];
12252 unsigned from_regno
, from_nregs
, to_regno
, new_regno
;
12256 from_regno
= REGNO (from
);
12257 from_nregs
= (from_regno
< FIRST_PSEUDO_REGISTER
12258 ? HARD_REGNO_NREGS (from_regno
, GET_MODE (from
)) : 1);
12259 if (regno
< from_regno
+ from_nregs
&& regno
+ nregs
> from_regno
)
12261 if (regno
< from_regno
12262 || regno
+ nregs
> from_regno
+ nregs
12266 to_regno
= REGNO (to
);
12267 if (to_regno
< FIRST_PSEUDO_REGISTER
)
12269 new_regno
= regno
+ to_regno
- from_regno
;
12270 if ((unsigned) HARD_REGNO_NREGS (new_regno
, GET_MODE (x
))
12273 result
= gen_rtx_REG (GET_MODE (x
), new_regno
);
12275 else if (GET_MODE (x
) <= GET_MODE (to
))
12276 result
= gen_lowpart_common (GET_MODE (x
), to
);
12278 result
= gen_lowpart_SUBREG (GET_MODE (x
), to
);
12281 return result
? result
: x
;
12283 else if (GET_CODE (x
) == ZERO_EXTEND
)
12285 rtx new_rtx
= replace_n_hard_rtx (XEXP (x
, 0), replacements
,
12286 n_replacements
, modify
);
12288 if (CONST_INT_P (new_rtx
))
12290 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
12291 new_rtx
, GET_MODE (XEXP (x
, 0)));
12296 XEXP (x
, 0) = new_rtx
;
12301 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12302 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
12308 new_rtx
= replace_n_hard_rtx (XEXP (x
, i
), replacements
,
12309 n_replacements
, modify
);
12313 XEXP (x
, i
) = new_rtx
;
12315 else if (fmt
[i
] == 'E')
12316 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12318 new_rtx
= replace_n_hard_rtx (XVECEXP (x
, i
, j
), replacements
,
12319 n_replacements
, modify
);
12323 XVECEXP (x
, i
, j
) = new_rtx
;
12331 sh_gen_truncate (enum machine_mode mode
, rtx x
, int need_sign_ext
)
12333 enum rtx_code code
= TRUNCATE
;
12335 if (GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
12337 rtx inner
= XEXP (x
, 0);
12338 enum machine_mode inner_mode
= GET_MODE (inner
);
12340 if (inner_mode
== mode
)
12342 else if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
12344 else if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
)
12345 && (! need_sign_ext
|| GET_CODE (x
) == SIGN_EXTEND
))
12347 code
= GET_CODE (x
);
12351 return gen_rtx_fmt_e (code
, mode
, x
);
12354 /* called via for_each_rtx after reload, to clean up truncates of
12355 registers that span multiple actual hard registers. */
12357 shmedia_cleanup_truncate (rtx
*p
, void *n_changes
)
12361 if (GET_CODE (x
) != TRUNCATE
)
12364 if (GET_MODE_SIZE (GET_MODE (reg
)) > 8 && REG_P (reg
))
12366 enum machine_mode reg_mode
= GET_MODE (reg
);
12367 XEXP (x
, 0) = simplify_subreg (DImode
, reg
, reg_mode
,
12368 subreg_lowpart_offset (DImode
, reg_mode
));
12369 *(int*) n_changes
+= 1;
12375 /* Load and store depend on the highpart of the address. However,
12376 set_attr_alternative does not give well-defined results before reload,
12377 so we must look at the rtl ourselves to see if any of the feeding
12378 registers is used in a memref. */
12380 /* Called by sh_contains_memref_p via for_each_rtx. */
12382 sh_contains_memref_p_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12384 return (MEM_P (*loc
));
12387 /* Return true iff INSN contains a MEM. */
12389 sh_contains_memref_p (rtx insn
)
12391 return for_each_rtx (&PATTERN (insn
), &sh_contains_memref_p_1
, NULL
);
12394 /* Return true iff INSN loads a banked register. */
12396 sh_loads_bankedreg_p (rtx insn
)
12398 if (GET_CODE (PATTERN (insn
)) == SET
)
12400 rtx op
= SET_DEST (PATTERN(insn
));
12401 if (REG_P (op
) && BANKED_REGISTER_P (REGNO (op
)))
12408 /* FNADDR is the MEM expression from a call expander. Return an address
12409 to use in an SHmedia insn pattern. */
12411 shmedia_prepare_call_address (rtx fnaddr
, int is_sibcall
)
12415 fnaddr
= XEXP (fnaddr
, 0);
12416 is_sym
= GET_CODE (fnaddr
) == SYMBOL_REF
;
12417 if (flag_pic
&& is_sym
)
12419 if (! SYMBOL_REF_LOCAL_P (fnaddr
))
12421 rtx reg
= gen_reg_rtx (Pmode
);
12423 /* We must not use GOTPLT for sibcalls, because PIC_REG
12424 must be restored before the PLT code gets to run. */
12426 emit_insn (gen_symGOT2reg (reg
, fnaddr
));
12428 emit_insn (gen_symGOTPLT2reg (reg
, fnaddr
));
12433 fnaddr
= gen_sym2PIC (fnaddr
);
12434 PUT_MODE (fnaddr
, Pmode
);
12437 /* If ptabs might trap, make this visible to the rest of the compiler.
12438 We generally assume that symbols pertain to valid locations, but
12439 it is possible to generate invalid symbols with asm or linker tricks.
12440 In a list of functions where each returns its successor, an invalid
12441 symbol might denote an empty list. */
12442 if (!TARGET_PT_FIXED
12443 && (!is_sym
|| TARGET_INVALID_SYMBOLS
)
12444 && (!REG_P (fnaddr
) || ! TARGET_REGISTER_P (REGNO (fnaddr
))))
12446 rtx tr
= gen_reg_rtx (PDImode
);
12448 emit_insn (gen_ptabs (tr
, fnaddr
));
12451 else if (! target_reg_operand (fnaddr
, Pmode
))
12452 fnaddr
= copy_to_mode_reg (Pmode
, fnaddr
);
12456 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12459 sh_preferred_reload_class (rtx x
, reg_class_t rclass
)
12461 if (rclass
== NO_REGS
12463 && (CONST_DOUBLE_P (x
)
12464 || GET_CODE (x
) == SYMBOL_REF
12465 || PIC_ADDR_P (x
)))
12466 return GENERAL_REGS
;
12471 /* Implement TARGET_SECONDARY_RELOAD. */
12474 sh_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
12475 enum machine_mode mode
, secondary_reload_info
*sri
)
12477 enum reg_class rclass
= (enum reg_class
) rclass_i
;
12481 if (REGCLASS_HAS_FP_REG (rclass
)
12482 && ! TARGET_SHMEDIA
12483 && immediate_operand ((x
), mode
)
12484 && ! ((fp_zero_operand (x
) || fp_one_operand (x
))
12485 && mode
== SFmode
&& fldi_ok ()))
12489 sri
->icode
= CODE_FOR_reload_insf__frn
;
12492 sri
->icode
= CODE_FOR_reload_indf__frn
;
12495 /* ??? If we knew that we are in the appropriate mode -
12496 single precision - we could use a reload pattern directly. */
12501 if (rclass
== FPUL_REGS
12503 && (REGNO (x
) == MACL_REG
|| REGNO (x
) == MACH_REG
12504 || REGNO (x
) == T_REG
))
12505 || GET_CODE (x
) == PLUS
))
12506 return GENERAL_REGS
;
12507 if (rclass
== FPUL_REGS
&& immediate_operand (x
, mode
))
12509 if (satisfies_constraint_I08 (x
) || fp_zero_operand (x
))
12510 return GENERAL_REGS
;
12511 else if (mode
== SFmode
)
12513 sri
->icode
= CODE_FOR_reload_insi__i_fpul
;
12516 if (rclass
== FPSCR_REGS
12517 && ((REG_P (x
) && REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
12518 || (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == PLUS
)))
12519 return GENERAL_REGS
;
12520 if (REGCLASS_HAS_FP_REG (rclass
)
12522 && immediate_operand (x
, mode
)
12523 && x
!= CONST0_RTX (GET_MODE (x
))
12524 && GET_MODE (x
) != V4SFmode
)
12525 return GENERAL_REGS
;
12526 if ((mode
== QImode
|| mode
== HImode
)
12527 && TARGET_SHMEDIA
&& inqhi_operand (x
, mode
))
12529 sri
->icode
= ((mode
== QImode
)
12530 ? CODE_FOR_reload_inqi
: CODE_FOR_reload_inhi
);
12533 if (TARGET_SHMEDIA
&& rclass
== GENERAL_REGS
12534 && (GET_CODE (x
) == LABEL_REF
|| PIC_ADDR_P (x
)))
12535 return TARGET_REGS
;
12536 } /* end of input-only processing. */
12538 if (((REGCLASS_HAS_FP_REG (rclass
)
12540 && (GENERAL_OR_AP_REGISTER_P (REGNO (x
))
12541 || (FP_REGISTER_P (REGNO (x
)) && mode
== SImode
12542 && TARGET_FMOVD
))))
12543 || (REGCLASS_HAS_GENERAL_REG (rclass
)
12545 && FP_REGISTER_P (REGNO (x
))))
12546 && ! TARGET_SHMEDIA
12547 && (mode
== SFmode
|| mode
== SImode
))
12549 if ((rclass
== FPUL_REGS
12550 || (REGCLASS_HAS_FP_REG (rclass
)
12551 && ! TARGET_SHMEDIA
&& mode
== SImode
))
12554 && (REGNO (x
) >= FIRST_PSEUDO_REGISTER
12555 || REGNO (x
) == T_REG
12556 || system_reg_operand (x
, VOIDmode
)))))
12558 if (rclass
== FPUL_REGS
)
12559 return GENERAL_REGS
;
12562 if ((rclass
== TARGET_REGS
12563 || (TARGET_SHMEDIA
&& rclass
== SIBCALL_REGS
))
12564 && !satisfies_constraint_Csy (x
)
12565 && (!REG_P (x
) || ! GENERAL_REGISTER_P (REGNO (x
))))
12566 return GENERAL_REGS
;
12567 if ((rclass
== MAC_REGS
|| rclass
== PR_REGS
)
12568 && REG_P (x
) && ! GENERAL_REGISTER_P (REGNO (x
))
12569 && rclass
!= REGNO_REG_CLASS (REGNO (x
)))
12570 return GENERAL_REGS
;
12571 if (rclass
!= GENERAL_REGS
&& REG_P (x
)
12572 && TARGET_REGISTER_P (REGNO (x
)))
12573 return GENERAL_REGS
;
12575 /* If here fall back to loading FPUL register through general registers.
12576 This case can happen when movsi_ie insn is picked initially to
12577 load/store the FPUL register from/to another register, and then the
12578 other register is allocated on the stack. */
12579 if (rclass
== FPUL_REGS
&& true_regnum (x
) == -1)
12580 return GENERAL_REGS
;
12582 /* Force mov.b displacement addressing insn to use R0 as the other operand.
12583 On SH2A could also just leave it alone here, which would result in a
12584 4 byte move insn being generated instead. However, for this to work
12585 the insns must have the appropriate alternatives. */
12586 if (mode
== QImode
&& rclass
!= R0_REGS
12587 && DISP_ADDR_P (x
) && DISP_ADDR_OFFSET (x
) < 16)
12590 /* When reload is trying to address a QImode or HImode subreg on the stack,
12591 force any subreg byte into R0_REGS, as this is going to become a
12592 displacement address.
12593 We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg
12594 is on the stack, the memref to it might already require a displacement
12595 and that has to be added to the final address. At this point we don't
12596 know the cumulative displacement so we assume the worst case. */
12597 if ((mode
== QImode
|| mode
== HImode
) && rclass
!= R0_REGS
12598 && GET_CODE (x
) == SUBREG
&& true_regnum (x
) == -1)
12605 sh_conditional_register_usage (void)
12608 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12609 if (! VALID_REGISTER_P (regno
))
12610 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12611 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
12614 call_used_regs
[FIRST_GENERAL_REG
+ 8]
12615 = call_used_regs
[FIRST_GENERAL_REG
+ 9] = 1;
12616 call_really_used_regs
[FIRST_GENERAL_REG
+ 8]
12617 = call_really_used_regs
[FIRST_GENERAL_REG
+ 9] = 1;
12619 if (TARGET_SHMEDIA
)
12621 regno_reg_class
[FIRST_GENERAL_REG
] = GENERAL_REGS
;
12622 CLEAR_HARD_REG_SET (reg_class_contents
[FP0_REGS
]);
12623 regno_reg_class
[FIRST_FP_REG
] = FP_REGS
;
12627 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12628 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12630 /* Renesas saves and restores mac registers on call. */
12631 if (TARGET_HITACHI
&& ! TARGET_NOMACSAVE
)
12633 call_really_used_regs
[MACH_REG
] = 0;
12634 call_really_used_regs
[MACL_REG
] = 0;
12636 for (regno
= FIRST_FP_REG
+ (TARGET_LITTLE_ENDIAN
!= 0);
12637 regno
<= LAST_FP_REG
; regno
+= 2)
12638 SET_HARD_REG_BIT (reg_class_contents
[DF_HI_REGS
], regno
);
12639 if (TARGET_SHMEDIA
)
12641 for (regno
= FIRST_TARGET_REG
; regno
<= LAST_TARGET_REG
; regno
++)
12642 if (! fixed_regs
[regno
] && call_really_used_regs
[regno
])
12643 SET_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
12646 for (regno
= FIRST_GENERAL_REG
; regno
<= LAST_GENERAL_REG
; regno
++)
12647 if (! fixed_regs
[regno
] && call_really_used_regs
[regno
])
12648 SET_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
12651 /* Implement TARGET_LEGITIMATE_CONSTANT_P
12653 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
12656 sh_legitimate_constant_p (enum machine_mode mode
, rtx x
)
12658 return (TARGET_SHMEDIA
12659 ? ((mode
!= DFmode
&& GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
12660 || x
== CONST0_RTX (mode
)
12661 || !TARGET_SHMEDIA_FPU
12662 || TARGET_SHMEDIA64
)
12663 : (GET_CODE (x
) != CONST_DOUBLE
12664 || mode
== DFmode
|| mode
== SFmode
12665 || mode
== DImode
|| GET_MODE (x
) == VOIDmode
));
12668 enum sh_divide_strategy_e sh_div_strategy
= SH_DIV_STRATEGY_DEFAULT
;
12671 sh_init_sync_libfuncs (void)
12673 init_sync_libfuncs (UNITS_PER_WORD
);