1 /* Definitions of target machine for GNU compiler, for Hitachi Super-H.
2 Copyright (C) 1993 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* Run-time Target Specification. */
26 #define TARGET_VERSION \
27 fputs (" (Hitachi SH)", stderr);
29 /* Generate SDB debugging information. */
31 #define SDB_DEBUGGING_INFO 1
35 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
38 /* Omitting the frame pointer is a very good idea on the SH */
40 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
43 flag_omit_frame_pointer = 1; \
44 if (OPTIMIZE==0)OPTIMIZE=1; \
47 /* Run-time compilation parameters selecting different hardware subsets. */
49 extern int target_flags
;
63 #define SPACE_BIT (1<<13)
65 /* Nonzero if we should generate code using type 0 insns */
66 #define TARGET_SH0 (target_flags & SH0_BIT)
68 /* Nonzero if we should generate code using type 1 insns */
69 #define TARGET_SH1 (target_flags & SH1_BIT)
71 /* Nonzero if we should generate code using type 2 insns */
72 #define TARGET_SH2 (target_flags & SH2_BIT)
74 /* Nonzero if we should generate code using type 3 insns */
75 #define TARGET_SH3 (target_flags & SH3_BIT)
77 /* Nonzero if we should generate faster code rather than smaller code */
78 #define TARGET_FASTCODE (target_flags & FAST_BIT)
80 /* Nonzero if we should generate faster code rather than smaller code */
81 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
83 /* Nonzero if we should dump out instruction size info */
84 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
86 /* Nonzero if we should try to generate mac instructions */
87 #define TARGET_MAC (target_flags & MAC_BIT)
89 /* Nonzero if we should dump the rtl in the assembly file. */
90 #define TARGET_DUMP_RTL (target_flags & RTL_BIT)
92 /* Nonzero if we should dump the rtl somewher else. */
93 #define TARGET_DUMP_R (target_flags & R_BIT)
95 /* Nonzero to align doubles on 64 bit boundaries */
96 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
99 /* Nonzero if Combine dumping wanted */
100 #define TARGET_CDUMP (target_flags & C_BIT)
102 #define TARGET_SWITCHES \
103 { {"isize", ( ISIZE_BIT) },\
104 {"space", ( SPACE_BIT) },\
109 {"ac", ( MAC_BIT) },\
110 {"dalign", ( DALIGN_BIT) },\
114 {"", TARGET_DEFAULT} \
117 #define TARGET_DEFAULT FAST_BIT
119 #define OVERRIDE_OPTIONS override_options();
122 /* Target machine storage Layout. */
124 /* Define to use software floating point emulator for REAL_ARITHMETIC and
125 decimal <-> binary conversion. */
126 #define REAL_ARITHMETIC
128 /* Define this if most significant bit is lowest numbered
129 in instructions that operate on numbered bit-fields. */
130 #define BITS_BIG_ENDIAN 0
132 /* Define this if most significant byte of a word is the lowest numbered. */
133 #define BYTES_BIG_ENDIAN 1
135 /* Define this if most significant word of a multiword number is the lowest
137 #define WORDS_BIG_ENDIAN 1
139 /* Number of bits in an addressable storage unit */
140 #define BITS_PER_UNIT 8
142 /* Width in bits of a "word", which is the contents of a machine register.
143 Note that this is not necessarily the width of data type `int';
144 if using 16-bit ints on a 68000, this would still be 32.
145 But on a machine with 16-bit registers, this would be 16. */
146 #define BITS_PER_WORD 32
147 #define MAX_BITS_PER_WORD 32
149 /* Width of a word, in units (bytes). */
150 #define UNITS_PER_WORD 4
152 /* Width in bits of a pointer.
153 See also the macro `Pmode' defined below. */
154 #define POINTER_SIZE 32
156 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
157 #define PARM_BOUNDARY 32
159 /* Boundary (in *bits*) on which stack pointer should be aligned. */
160 #define STACK_BOUNDARY 32
162 /* Allocation boundary (in *bits*) for the code of a function. */
163 #define FUNCTION_BOUNDARY 16
165 /* Alignment of field after `int : 0' in a structure. */
166 #define EMPTY_FIELD_BOUNDARY 32
168 /* No data type wants to be aligned rounder than this. */
169 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
171 /* The best alignment to use in cases where we have a choice. */
172 #define FASTEST_ALIGNMENT 32
174 /* Every structures size must be a multiple of 32 bits. */
175 #define STRUCTURE_SIZE_BOUNDARY 32
177 /* Make strings word-aligned so strcpy from constants will be faster. */
178 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
179 ((TREE_CODE (EXP) == STRING_CST \
180 && (ALIGN) < FASTEST_ALIGNMENT) \
181 ? FASTEST_ALIGNMENT : (ALIGN))
183 /* Make arrays of chars word-aligned for the same reasons. */
184 #define DATA_ALIGNMENT(TYPE, ALIGN) \
185 (TREE_CODE (TYPE) == ARRAY_TYPE \
186 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
187 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
189 /* Set this nonzero if move instructions will actually fail to work
190 when given unaligned data. */
191 #define STRICT_ALIGNMENT 1
194 /* Standard register usage. */
196 /* Register allocation for our first guess
199 r4-r7 args in and out
204 ap arg pointer (doesn't really exist, always eliminated)
205 pr subroutine return address
207 mach multiply/accumulate result
211 /* Number of actual hardware registers.
212 The hardware registers are assigned numbers for the compiler
213 from 0 to just below FIRST_PSEUDO_REGISTER.
214 All registers that the compiler knows about must be given numbers,
215 even those that are not normally considered general registers.
217 SH has 16 integer registers and 4 control registers + the arg
220 #define FIRST_PSEUDO_REGISTER 22
229 /* 1 for registers that have pervasive standard uses
230 and are not available for the register allocator. */
231 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap pr t gbr mh ml */
232 #define FIXED_REGISTERS \
233 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1}
235 /* 1 for registers not available across function calls.
236 These must include the FIXED_REGISTERS and also any
237 registers that can be used without being saved.
238 The latter must include the registers where values are returned
239 and the register where structure-value addresses are passed.
240 Aside from that, you can include as many other registers as you like. */
242 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap pr t gbr mh ml */
243 #define CALL_USED_REGISTERS \
244 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1}
246 /* Return number of consecutive hard regs needed starting at reg REGNO
247 to hold something of mode MODE.
248 This is ordinarily the length in words of a value of mode MODE
249 but can be less for certain modes in special long registers.
251 On the SH regs are UNITS_PER_WORD bits wide; */
252 #define HARD_REGNO_NREGS(REGNO, MODE) \
253 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
255 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
256 We may keep double values in even registers */
258 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
259 ((TARGET_ALIGN_DOUBLE && GET_MODE_SIZE(MODE) > 4) ? (((REGNO)&1)==0) : 1)
261 /* Value is 1 if it is a good idea to tie two pseudo registers
262 when one has mode MODE1 and one has mode MODE2.
263 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
264 for any hard reg, then this must be 0 for correct output. */
266 #define MODES_TIEABLE_P(MODE1, MODE2) \
267 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
269 /* Specify the registers used for certain standard purposes.
270 The values of these macros are register numbers. */
272 /* Define this if the program counter is overloaded on a register. */
273 /* #define PC_REGNUM 15*/
275 /* Register to use for pushing function arguments. */
276 #define STACK_POINTER_REGNUM 15
278 /* Base register for access to local variables of the function. */
279 #define FRAME_POINTER_REGNUM 14
281 /* Value should be nonzero if functions must have frame pointers.
282 Zero means the frame pointer need not be set up (and parms may be accessed
283 via the stack pointer) in functions that seem suitable. */
286 #define FRAME_POINTER_REQUIRED (get_frame_size() > 1000)
288 /* Definitions for register eliminations.
290 We have two registers that can be eliminated on the m88k. First, the
291 frame pointer register can often be eliminated in favor of the stack
292 pointer register. Secondly, the argument pointer register can always be
293 eliminated; it is replaced with either the stack or frame pointer. */
295 /* This is an array of structures. Each structure initializes one pair
296 of eliminable registers. The "from" register number is given first,
297 followed by "to". Eliminations of the same "from" register are listed
298 in order of preference. */
300 #define ELIMINABLE_REGS \
301 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
302 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
303 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
305 /* Given FROM and TO register numbers, say whether this elimination
307 #define CAN_ELIMINATE(FROM, TO) \
308 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
310 /* Define the offset between two registers, one to be eliminated, and the other
311 its replacement, at the start of a routine. */
313 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
314 OFFSET = initial_elimination_offset (FROM, TO)
316 /* Base register for access to arguments of the function. */
317 #define ARG_POINTER_REGNUM 16
319 /* Register in which the static-chain is passed to a function. */
320 #define STATIC_CHAIN_REGNUM 13
322 /* The register in which a struct value address is passed */
324 #define STRUCT_VALUE_REGNUM 3
328 /* Define the classes of registers for register constraints in the
329 machine description. Also define ranges of constants.
331 One of the classes must always be named ALL_REGS and include all hard regs.
332 If there is more than one class, another class must be named NO_REGS
333 and contain no registers.
335 The name GENERAL_REGS must be the name of a class (or an alias for
336 another name such as ALL_REGS). This is the class of registers
337 that is allowed by "g" or "r" in a register constraint.
338 Also, registers outside this class are allocated only when
339 instructions express preferences for them.
341 The classes must be numbered in nondecreasing order; that is,
342 a larger-numbered class must never be contained completely
343 in a smaller-numbered class.
345 For any two classes, it is very desirable that there be another
346 class that represents their union. */
348 /* The SH has two sorts of general registers, R0 and the rest. R0 can
349 be used as the destination of some of the arithmetic ops. There are
350 also some special purpose registers; the T bit register, the
351 Procedure Return Register and the Multipy Accumulate Registers */
365 #define N_REG_CLASSES (int) LIM_REG_CLASSES
367 /* Give names of register classes as strings for dump file. */
368 #define REG_CLASS_NAMES \
379 /* Define which registers fit in which classes.
380 This is an initializer for a vector of HARD_REG_SET
381 of length N_REG_CLASSES. */
383 #define REG_CLASS_CONTENTS \
385 0x000000, /* NO_REGS */ \
386 0x000001, /* R0_REGS */ \
387 0x01FFFF, /* GENERAL_REGS */ \
388 0x020000, /* PR_REGS */ \
389 0x040000, /* T_REGS */ \
390 0x300000, /* MAC_REGS */ \
391 0x37FFFF /* ALL_REGS */ \
394 /* The same information, inverted:
395 Return the class number of the smallest class containing
396 reg number REGNO. This could be a conditional expression
397 or could index an array. */
399 extern int regno_reg_class
[];
400 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
402 /* The order in which register should be allocated. */
403 #define REG_ALLOC_ORDER \
404 { 1,2,3,7,4,5,6,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21}
406 /* The class value for index registers, and the one for base regs. */
407 #define INDEX_REG_CLASS R0_REGS
408 #define BASE_REG_CLASS GENERAL_REGS
410 /* Get reg_class from a letter such as appears in the machine
412 extern enum reg_class reg_class_from_letter
[];
414 #define REG_CLASS_FROM_LETTER(C) \
415 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
418 /* The letters I, J, K, L and M in a register constraint string
419 can be used to stand for particular ranges of immediate operands.
420 This macro defines what the ranges are.
421 C is the letter, and VALUE is a constant value.
422 Return 1 if VALUE is in the range specified by C.
423 I: arithmetic operand -127..128, as used in add, sub, etc
424 L: logical operand 0..255, as used in and, or, etc.
426 K: shift operand 1,2,8 or 16 */
429 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
430 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
431 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
432 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
434 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
435 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
436 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
437 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
438 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
441 /* Similar, but for floating constants, and defining letters G and H.
442 Here VALUE is the CONST_DOUBLE rtx itself. */
444 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
445 ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
446 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
449 /* Given an rtx X being reloaded into a reg required to be
450 in class CLASS, return the class of reg to actually use.
451 In general this is just CLASS; but on some machines
452 in some cases it is preferable to use a more restrictive class. */
454 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
456 /* Return the register class of a scratch register needed to copy IN into
457 or out of a register in CLASS in MODE. If it can be done directly,
458 NO_REGS is returned. */
460 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
462 /* Return the maximum number of consecutive registers
463 needed to represent mode MODE in a register of class CLASS.
465 On SH this is the size of MODE in words */
466 #define CLASS_MAX_NREGS(CLASS, MODE) \
467 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
470 /* Stack layout; function entry, exit and calling. */
472 /* Define the number of register that can hold parameters.
473 These two macros are used only in other macro definitions below. */
475 #define FIRST_PARM_REG 4
476 #define FIRST_RET_REG 4
478 /* Define this if pushing a word on the stack
479 makes the stack pointer a smaller address. */
480 #define STACK_GROWS_DOWNWARD
482 /* Define this if the nominal address of the stack frame
483 is at the high-address end of the local variables;
484 that is, each additional local variable allocated
485 goes at a more negative offset in the frame. */
486 #define FRAME_GROWS_DOWNWARD
488 /* Offset within stack frame to start allocating local variables at.
489 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
490 first local allocated. Otherwise, it is the offset to the BEGINNING
491 of the first local allocated. */
492 #define STARTING_FRAME_OFFSET 0
494 /* If we generate an insn to push BYTES bytes,
495 this says how many the stack pointer really advances by. */
496 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
498 /* Offset of first parameter from the argument pointer register value. */
499 #define FIRST_PARM_OFFSET(FNDECL) 0
501 /* Value is the number of byte of arguments automatically
502 popped when returning from a subroutine call.
503 FUNTYPE is the data type of the function (as a tree),
504 or for a library call it is an identifier node for the subroutine name.
505 SIZE is the number of bytes of arguments passed on the stack.
507 On the SH, the caller does not pop any of its arguments that were passed
509 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
511 /* Define how to find the value returned by a function.
512 VALTYPE is the data type of the value (as a tree).
513 If the precise function being called is known, FUNC is its FUNCTION_DECL;
514 otherwise, FUNC is 0. */
515 #define FUNCTION_VALUE(VALTYPE, FUNC) \
516 gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG)
518 /* Define how to find the value returned by a library function
519 assuming the value has mode MODE. */
520 #define LIBCALL_VALUE(MODE) \
521 gen_rtx (REG, MODE, FIRST_RET_REG)
523 /* 1 if N is a possible register number for a function value.
524 On the SH, only r4 can return results. */
525 #define FUNCTION_VALUE_REGNO_P(REGNO) \
526 ((REGNO) == FIRST_RET_REG)
528 /* 1 if N is a possible register number for function argument passing.*/
530 #define FUNCTION_ARG_REGNO_P(REGNO) \
531 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
535 /* Define a data type for recording info about an argument list
536 during the scan of that argument list. This data type should
537 hold all necessary information about the function itself
538 and about the args processed so far, enough to enable macros
539 such as FUNCTION_ARG to determine where the next arg should go.
541 On SH, this is a single integer, which is a number of words
542 of arguments scanned so far (including the invisible argument,
543 if any, which holds the structure-value-address).
544 Thus NARGREGS or more means all following args should go on the stack. */
546 #define CUMULATIVE_ARGS int
548 #define ROUND_ADVANCE(SIZE) \
549 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
551 /* Round a register number up to a proper boundary for an arg of mode
554 We round to an even reg for things larger than a word */
556 #define ROUND_REG(X, MODE) \
557 ((TARGET_ALIGN_DOUBLE \
558 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
559 ? ((X) + ((X) & 1)) : (X))
562 /* Initialize a variable CUM of type CUMULATIVE_ARGS
563 for a call to a function whose data type is FNTYPE.
564 For a library call, FNTYPE is 0.
566 On SH, the offset always starts at 0: the first parm reg is always
569 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
572 /* Update the data in CUM to advance over an argument
573 of mode MODE and data type TYPE.
574 (TYPE is null for libcalls where that information may not be
577 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
578 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
579 + ((MODE) != BLKmode \
580 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
581 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
583 /* Define where to put the arguments to a function.
584 Value is zero to push the argument on the stack,
585 or a hard register in which to store the argument.
587 MODE is the argument's machine mode.
588 TYPE is the data type of the argument (as a tree).
589 This is null for libcalls where that information may
591 CUM is a variable of type CUMULATIVE_ARGS which gives info about
592 the preceding args and about the function being called.
593 NAMED is nonzero if this argument is a named parameter
594 (otherwise it is an extra parameter matching an ellipsis).
596 On SH the first args are normally in registers
597 and the rest are pushed. Any arg that starts within the first
598 NPARM_REGS words is at least partially passed in a register unless
599 its data type forbids. */
601 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
602 (NAMED && ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
603 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
604 && ((TYPE)==0 || (MODE) != BLKmode \
605 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
606 ? gen_rtx (REG, (MODE), \
607 (FIRST_PARM_REG + ROUND_REG ((CUM), (MODE)))) \
610 /* For an arg passed partly in registers and partly in memory,
611 this is the number of registers used.
612 For args passed entirely in registers or entirely in memory, zero.
613 Any arg that starts in the first NPARM_REGS regs but won't entirely
614 fit in them needs partial registers on the SH. */
616 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
617 ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
618 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
619 && ((TYPE)==0 || (MODE) != BLKmode \
620 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
621 && (ROUND_REG ((CUM), (MODE)) \
622 + ((MODE) == BLKmode \
623 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
624 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
625 ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
628 extern int current_function_anonymous_args
;
630 /* Perform any needed actions needed for a function that is receiving a
631 variable number of arguments. */
633 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
634 current_function_anonymous_args = 1;
637 /* Call the function profiler with a given profile label. */
639 #define FUNCTION_PROFILER(STREAM,LABELNO) \
641 fprintf(STREAM, " trapa #5\n"); \
642 fprintf(STREAM, " .align 2\n"); \
643 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
647 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
648 the stack pointer does not matter. The value is tested only in
649 functions that have frame pointers.
650 No definition is equivalent to always zero. */
652 #define EXIT_IGNORE_STACK 0
654 /* Generate the assembly code for function exit
655 Just dump out any accumulated constant table.*/
657 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
660 /* Output assembler code for a block containing the constant parts
661 of a trampoline, leaving space for the variable parts.
663 On the SH, the trapoline looks like
664 1 0000 D301 mov.l l1,r3
665 2 0002 DD02 mov.l l2,r13
668 5 0008 00000000 l1: .long function
669 6 000c 00000000 l2: .long area
671 #define TRAMPOLINE_TEMPLATE(FILE) \
673 fprintf ((FILE), " .word 0xd301\n"); \
674 fprintf ((FILE), " .word 0xdd02\n"); \
675 fprintf ((FILE), " .word 0x4d2b\n"); \
676 fprintf ((FILE), " .word 0x200b\n"); \
677 fprintf ((FILE), " .long 0\n"); \
678 fprintf ((FILE), " .long 0\n"); \
681 /* Length in units of the trampoline for entering a nested function. */
682 #define TRAMPOLINE_SIZE 16
684 /* Alignment required for a trampoline in units. */
685 #define TRAMPOLINE_ALIGN 4
687 /* Emit RTL insns to initialize the variable parts of a trampoline.
688 FNADDR is an RTX for the address of the function's pure code.
689 CXT is an RTX for the static chain value for the function. */
691 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
693 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
695 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
700 /* Addressing modes, and classification of registers for them. */
702 /*#define HAVE_POST_INCREMENT 1*/
703 /*#define HAVE_PRE_INCREMENT 1*/
704 /*#define HAVE_POST_DECREMENT 1*/
705 /*#define HAVE_PRE_DECREMENT 1*/
707 /* Macros to check register numbers against specific register classes. */
709 /* These assume that REGNO is a hard or pseudo reg number.
710 They give nonzero only if REGNO is a hard reg of the suitable class
711 or a pseudo reg currently allocated to a suitable hard reg.
712 Since they use reg_renumber, they are safe only once reg_renumber
713 has been allocated, which happens in local-alloc.c.
716 #define REGNO_OK_FOR_BASE_P(REGNO) \
717 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
719 #define REGNO_OK_FOR_INDEX_P(REGNO) ((REGNO)==0)
721 /* Maximum number of registers that can appear in a valid memory
724 #define MAX_REGS_PER_ADDRESS 4
726 /* Recognize any constant value that is a valid address. */
728 #define CONSTANT_ADDRESS_P(X) \
729 (GET_CODE (X) == LABEL_REF)
731 /* Nonzero if the constant value X is a legitimate general operand.
732 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
734 On the SH, allow anything but a double */
736 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
738 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
739 and check its validity for a certain class.
740 We have two alternate definitions for each of them.
741 The usual definition accepts all pseudo regs; the other rejects
742 them unless they have been allocated suitable hard regs.
743 The symbol REG_OK_STRICT causes the latter definition to be used. */
745 #ifndef REG_OK_STRICT
747 /* Nonzero if X is a hard reg that can be used as a base reg
748 or if it is a pseudo reg. */
749 #define REG_OK_FOR_BASE_P(X) \
750 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
752 /* Nonzero if X is a hard reg that can be used as an index
753 or if it is a pseudo reg. */
754 #define REG_OK_FOR_INDEX_P(X) \
755 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
757 #define REG_OK_FOR_PRE_POST_P(X) \
762 /* Nonzero if X is a hard reg that can be used as a base reg. */
763 #define REG_OK_FOR_BASE_P(X) \
764 REGNO_OK_FOR_BASE_P (REGNO (X))
766 /* Nonzero if X is a hard reg that can be used as an index. */
767 #define REG_OK_FOR_INDEX_P(X) \
768 REGNO_OK_FOR_INDEX_P (REGNO (X))
770 #define REG_OK_FOR_PRE_POST_P(X) \
771 (REGNO (X) <= 16 || (unsigned) reg_renumber[REGNO (X)] <=16)
774 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
775 that is a valid memory address for an instruction.
776 The MODE argument is the machine mode for the MEM expression
777 that wants to use this address.
779 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
781 #define BASE_REGISTER_RTX_P(X) \
782 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
784 #define INDEX_REGISTER_RTX_P(X) \
785 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
788 /* Jump to LABEL if X is a valid address RTX. This must also take
789 REG_OK_STRICT into account when deciding about valid registers, but it uses
790 the above macros so we are in luck.
799 /* The SH allows a displacement in a QI or HI amode, but only when the
800 other operand is R0. GCC doesn't handle this very well, so we forgo
803 A legitimate index for a QI or HI is 0, SI and above can be any
806 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
808 if (GET_CODE (OP) == CONST_INT) \
810 if (0&&GET_MODE_SIZE (MODE) == 2 && ((unsigned)INTVAL(OP)) <=30)\
812 if (0&&GET_MODE_SIZE (MODE) == 1 && ((unsigned)INTVAL(OP)) <=15)\
814 if (GET_MODE_SIZE (MODE) >=4 \
815 && ((unsigned)INTVAL(OP)) < 64) \
821 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
823 if (BASE_REGISTER_RTX_P (X)) \
825 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
826 && GET_CODE (XEXP (X, 0)) == REG \
827 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
829 else if (GET_CODE (X) == PLUS || GET_CODE(X) == LO_SUM) \
831 rtx xop0 = XEXP(X,0); \
832 rtx xop1 = XEXP(X,1); \
833 if (GET_MODE_SIZE(MODE) >= 4 && BASE_REGISTER_RTX_P (xop0)) \
834 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
835 if (GET_MODE_SIZE(MODE) >= 4 && BASE_REGISTER_RTX_P (xop1)) \
836 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
837 if (GET_MODE_SIZE(MODE)<=4) { \
838 if(BASE_REGISTER_RTX_P(xop1) && \
839 INDEX_REGISTER_RTX_P(xop0)) goto LABEL; \
840 if(INDEX_REGISTER_RTX_P(xop1) && \
841 BASE_REGISTER_RTX_P(xop0)) goto LABEL; \
844 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
845 && GET_CODE (XEXP (X, 0)) == REG \
846 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
851 /* Try machine-dependent ways of modifying an illegitimate address
852 to be legitimate. If we find one, return the new, valid address.
853 This macro is used in only one place: `memory_address' in explow.c.
855 OLDX is the address as it was before break_out_memory_refs was called.
856 In some cases it is useful to look at this to decide what needs to be done.
858 MODE and WIN are passed so that this macro can use
859 GO_IF_LEGITIMATE_ADDRESS.
861 It is always safe for this macro to do nothing. It exists to recognize
862 opportunities to optimize the output.
864 On the SH we don't try anything */
866 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) ;
868 /* Go to LABEL if ADDR (a legitimate address expression)
869 has an effect that depends on the machine mode it is used for. */
870 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
872 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
873 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
877 /* Specify the machine mode that this machine uses
878 for the index in the tablejump instruction. */
879 #define CASE_VECTOR_MODE SImode
881 /* Define this if the tablejump instruction expects the table
882 to contain offsets from the address of the table.
883 Do not define this if the table should contain absolute addresses. */
884 /* #define CASE_VECTOR_PC_RELATIVE */
886 /* Specify the tree operation to be used to convert reals to integers. */
887 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
889 /* This is the kind of divide that is easiest to do in the general case. */
890 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
892 /* 'char' is signed by default */
893 #define DEFAULT_SIGNED_CHAR 1
895 /* The type of size_t unsigned int. */
896 #define SIZE_TYPE "unsigned int"
898 /* Don't cse the address of the function being compiled. */
899 #define NO_RECURSIVE_FUNCTION_CSE 1
901 /* Max number of bytes we can move from memory to memory
902 in one reasonably fast instruction. */
905 /* Define if operations between registers always perform the operation
906 on the full register even if a narrower mode is specified. */
907 #define WORD_REGISTER_OPERATIONS
909 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
910 will either zero-extend or sign-extend. The value of this macro should
911 be the code that says which one of the two operations is implicitly
912 done, NIL if none. */
913 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
915 /* Define this if zero-extension is slow (more than one real instruction).
916 On the SH, it's only one instruction */
917 /* #define SLOW_ZERO_EXTEND */
919 /* Nonzero if access to memory by bytes is slow and undesirable. */
920 #define SLOW_BYTE_ACCESS 0
922 /* We assume that the store-condition-codes instructions store 0 for false
923 and some other value for true. This is the value stored for true. */
925 #define STORE_FLAG_VALUE 1
927 /* Immediate shift counts are truncated by the output routines (or was it
928 the assembler?). Shift counts in a register are truncated by ARM. Note
929 that the native compiler puts too large (> 32) immediate shift counts
930 into a register and shifts by the register, letting the ARM decide what
931 to do instead of doing that itself. */
932 #define SHIFT_COUNT_TRUNCATED 1
934 /* All integers have the same format so truncation is easy. */
935 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
937 /* Define this if addresses of constant functions
938 shouldn't be put through pseudo regs where they can be cse'd.
939 Desirable on machines where ordinary constants are expensive
940 but a CALL with constant address is cheap. */
941 /*#define NO_FUNCTION_CSE 1*/
943 /* Chars and shorts should be passed as ints. */
944 #define PROMOTE_PROTOTYPES 1
946 /* The machine modes of pointers and functions */
948 #define FUNCTION_MODE Pmode
950 /* The structure type of the machine dependent info field of insns
951 No uses for this yet. */
952 /* #define INSN_MACHINE_INFO struct machine_info */
954 /* The relative costs of various types of constants. Note that cse.c defines
955 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
957 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
959 if (CONST_OK_FOR_I (INTVAL(RTX))) \
970 #define RTX_COSTS(X, CODE, OUTER_CODE) \
972 return COSTS_N_INSNS (multcosts (X)); \
976 return COSTS_N_INSNS (shiftcosts (X)) ; \
981 return COSTS_N_INSNS (100); \
986 /* Compute extra cost of moving data between one register class
989 On the SH it is hard to move into the T reg, but simple to load
993 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
994 ((DSTCLASS == T_REGS) ? 10 : 1)
996 /* Assembler output control */
998 /* The text to go at the start of the assembler file */
999 #define ASM_FILE_START(STREAM) \
1000 output_file_start (STREAM, f_options, sizeof f_options / sizeof f_options[0], \
1001 W_options, sizeof W_options / sizeof W_options[0]);
1004 #define ASM_FILE_END(STREAM) \
1007 #define ASM_APP_ON ""
1008 #define ASM_APP_OFF ""
1010 #define FILE_ASM_OP "\t.file\n"
1011 #define IDENT_ASM_OP "\t.ident\n"
1014 /* Switch to the text or data segment. */
1015 #define TEXT_SECTION_ASM_OP "\t.text"
1016 #define DATA_SECTION_ASM_OP "\t.data"
1017 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1018 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1020 #define EXTRA_SECTIONS in_ctors, in_dtors
1021 #define EXTRA_SECTION_FUNCTIONS \
1025 if (in_section != in_ctors) \
1027 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1028 in_section = in_ctors; \
1034 if (in_section != in_dtors) \
1036 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1037 in_section = in_dtors; \
1041 #define ASM_OUTPUT_SECTION(file, nam) \
1042 do { fprintf (file, "\t.section\t%s\n", nam); } while(0)
1044 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1045 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1047 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1048 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1051 #undef DO_GLOBAL_CTORS_BODY
1052 #define DO_GLOBAL_CTORS_BODY \
1054 typedef (*pfunc)(); \
1055 extern pfunc __ctors[]; \
1056 extern pfunc __ctors_end[]; \
1058 for (p = __ctors; p < __ctors_end; p++) \
1064 #undef DO_GLOBAL_DTORS_BODY
1065 #define DO_GLOBAL_DTORS_BODY \
1067 typedef (*pfunc)(); \
1068 extern pfunc __dtors[]; \
1069 extern pfunc __dtors_end[]; \
1071 for (p = __dtors; p < __dtors_end; p++) \
1079 #define ASM_OUTPUT_REG_PUSH(file, v) \
1080 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1082 #define ASM_OUTPUT_REG_POP(file, v) \
1083 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1087 /* The assembler's names for the registers. RFP need not always be used as
1088 the Real framepointer; it can also be used as a normal general register.
1089 Note that the name `fp' is horribly misleading since `fp' is in fact only
1090 the argument-and-return-context pointer. */
1091 #define REGISTER_NAMES \
1093 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1094 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1095 "ap", "pr", "t", "gbr", "mach","macl" \
1098 /* DBX register number for a given compiler register number */
1099 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1101 /* Output a label definition. */
1102 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1103 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1106 /* This is how to output an assembler line
1107 that says to advance the location counter
1108 to a multiple of 2**LOG bytes. */
1110 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1112 fprintf (FILE, "\t.align %d\n", LOG)
1114 /* Output a function label definition. */
1115 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1116 ASM_OUTPUT_LABEL(STREAM, NAME)
1118 /* Output a globalising directive for a label. */
1119 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1120 (fprintf (STREAM, "\t.global\t"), \
1121 assemble_name (STREAM, NAME), \
1122 fputc ('\n',STREAM)) \
1124 /* Output a reference to a label. */
1125 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1126 fprintf (STREAM, "_%s", NAME)
1128 /* Make an internal label into a string. */
1129 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1130 sprintf (STRING, "*%s%d", PREFIX, NUM)
1132 /* Output an internal label definition. */
1133 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1134 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1136 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1138 /* Construct a private name. */
1139 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1140 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1141 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1143 /* Jump tables must be 32 bit aligned. */
1144 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1145 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1147 /* Output a relative address. Not needed since jump tables are absolute
1148 but we must define it anyway. */
1149 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1150 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1152 /* Output an element of a dispatch table. */
1153 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1154 fprintf (STREAM, "\t.long\tL%d\n", VALUE)
1156 /* Output various types of constants. */
1159 /* This is how to output an assembler line defining a `double' */
1161 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1162 do { char dstr[30]; \
1163 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1164 fprintf (FILE, "\t.double %s\n", dstr); \
1168 /* This is how to output an assembler line defining a `float' constant. */
1169 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1170 do { char dstr[30]; \
1171 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1172 fprintf (FILE, "\t.float %s\n", dstr); \
1176 #define ASM_OUTPUT_INT(STREAM, EXP) \
1177 (fprintf (STREAM, "\t.long\t"), \
1178 output_addr_const (STREAM, (EXP)), \
1179 fputc ('\n', STREAM))
1181 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1182 (fprintf (STREAM, "\t.short\t"), \
1183 output_addr_const (STREAM, (EXP)), \
1184 fputc ('\n', STREAM))
1186 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1187 (fprintf (STREAM, "\t.byte\t"), \
1188 output_addr_const (STREAM, (EXP)), \
1189 fputc ('\n', STREAM))
1191 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1192 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1194 /* This is how to output an assembler line
1195 that says to advance the location counter by SIZE bytes. */
1197 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1198 fprintf (FILE, "\t.space %d\n", (SIZE))
1200 /* This says how to output an assembler line
1201 to define a global common symbol. */
1203 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1204 ( fputs ("\t.comm ", (FILE)), \
1205 assemble_name ((FILE), (NAME)), \
1206 fprintf ((FILE), ",%d\n", (SIZE)))
1208 /* This says how to output an assembler line
1209 to define a local common symbol. */
1211 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1212 ( fputs ("\t.lcomm ", (FILE)), \
1213 assemble_name ((FILE), (NAME)), \
1214 fprintf ((FILE), ",%d\n", (SIZE)))
1217 /* The assembler's parentheses characters. */
1218 #define ASM_OPEN_PAREN "("
1219 #define ASM_CLOSE_PAREN ")"
1221 /* Target characters. */
1222 #define TARGET_BELL 007
1223 #define TARGET_BS 010
1224 #define TARGET_TAB 011
1225 #define TARGET_NEWLINE 012
1226 #define TARGET_VT 013
1227 #define TARGET_FF 014
1228 #define TARGET_CR 015
1231 /* Only perform branch elimination (by making instructions conditional) if
1232 we're optimising. Otherwise it's of no use anyway. */
1233 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1234 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1236 /* Print operand X (an rtx) in assembler syntax to file FILE.
1237 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1238 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1240 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1242 /* Print a memory address as an operand to reference that memory location. */
1244 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1246 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1247 ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!')
1250 /* Define the information needed to generate branch insns. This is stored
1251 from the compare operation. Note that we can't use "rtx" here since it
1252 hasn't been defined! */
1254 extern struct rtx_def
*sh_compare_op0
;
1255 extern struct rtx_def
*sh_compare_op1
;
1256 extern struct rtx_def
*prepare_scc_operands();
1258 extern enum attr_cpu sh_cpu
; /* target cpu */
1260 /* Declare functions defined in sh.c and used in templates. */
1262 extern char *output_branch();
1263 extern char *output_shift();
1264 extern char *output_movedouble();
1265 extern char *output_movepcrel();
1268 #define ADJUST_INSN_LENGTH(insn, length) \
1269 adjust_insn_length (insn, insn_lengths)