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[gcc.git] / gcc / config / sh / sh.h
1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23
24 #define TARGET_VERSION \
25 fputs (" (Hitachi SH)", stderr);
26
27 /* Generate SDB debugging information. */
28
29 #define SDB_DEBUGGING_INFO
30
31 /* Output DBX (stabs) debugging information if doing -gstabs. */
32
33 #include "dbxcoff.h"
34
35 #define SDB_DELIM ";"
36
37 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \
38 %{m1:-D__sh1__} \
39 %{m2:-D__sh2__} \
40 %{m3:-D__sh3__} \
41 %{m3e:-D__SH3E__}"
42
43 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
44
45 #define ASM_SPEC "%{ml:-little} %{mrelax:-relax}"
46
47 #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
48
49 /* We can not debug without a frame pointer. */
50 /* #define CAN_DEBUG_WITHOUT_FP */
51
52 #define CONDITIONAL_REGISTER_USAGE \
53 if (! TARGET_SH3E) \
54 { \
55 int regno; \
56 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
57 fixed_regs[regno] = call_used_regs[regno] = 1; \
58 } \
59 /* Hitachi saves and restores mac registers on call. */ \
60 if (TARGET_HITACHI) \
61 { \
62 call_used_regs[MACH_REG] = 0; \
63 call_used_regs[MACL_REG] = 0; \
64 }
65 \f
66 /* ??? Need to write documentation for all SH options and add it to the
67 invoke.texi file. */
68
69 /* Run-time compilation parameters selecting different hardware subsets. */
70
71 extern int target_flags;
72 #define ISIZE_BIT (1<<1)
73 #define DALIGN_BIT (1<<6)
74 #define SH0_BIT (1<<7)
75 #define SH1_BIT (1<<8)
76 #define SH2_BIT (1<<9)
77 #define SH3_BIT (1<<10)
78 #define SH3E_BIT (1<<11)
79 #define SPACE_BIT (1<<13)
80 #define BIGTABLE_BIT (1<<14)
81 #define RELAX_BIT (1<<15)
82 #define HITACHI_BIT (1<<22)
83 #define PADSTRUCT_BIT (1<<28)
84 #define LITTLE_ENDIAN_BIT (1<<29)
85
86 /* Nonzero if we should dump out instruction size info. */
87 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
88
89 /* Nonzero to align doubles on 64 bit boundaries. */
90 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
91
92 /* Nonzero if we should generate code using type 0 insns. */
93 /* ??? Is there such a thing as SH0? If not, we should delete all
94 references to it. */
95 #define TARGET_SH0 (target_flags & SH0_BIT)
96
97 /* Nonzero if we should generate code using type 1 insns. */
98 #define TARGET_SH1 (target_flags & SH1_BIT)
99
100 /* Nonzero if we should generate code using type 2 insns. */
101 #define TARGET_SH2 (target_flags & SH2_BIT)
102
103 /* Nonzero if we should generate code using type 3 insns. */
104 #define TARGET_SH3 (target_flags & SH3_BIT)
105
106 /* Nonzero if we should generate code using type 3E insns. */
107 #define TARGET_SH3E (target_flags & SH3E_BIT)
108
109 /* Nonzero if we should generate smaller code rather than faster code. */
110 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
111
112 /* Nonzero to use long jump tables. */
113 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
114
115 /* Nonzero to generate pseudo-ops needed by the assembler and linker
116 to do function call relaxing. */
117 #define TARGET_RELAX (target_flags & RELAX_BIT)
118
119 /* Nonzero if using Hitachi's calling convention. */
120 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
121
122 /* Nonzero if padding structures to a multiple of 4 bytes. This is
123 incompatible with Hitachi's compiler, and gives unusual structure layouts
124 which confuse programmers.
125 ??? This option is not useful, but is retained in case there are people
126 who are still relying on it. It may be deleted in the future. */
127 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
128
129 /* Nonzero if generating code for a little endian SH. */
130 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
131
132 #define TARGET_SWITCHES \
133 { {"0", SH0_BIT}, \
134 {"1", SH1_BIT}, \
135 {"2", SH2_BIT}, \
136 {"3", SH3_BIT|SH2_BIT}, \
137 {"3e", SH3E_BIT|SH3_BIT|SH2_BIT}, \
138 {"b", -LITTLE_ENDIAN_BIT}, \
139 {"bigtable", BIGTABLE_BIT}, \
140 {"dalign", DALIGN_BIT}, \
141 {"hitachi", HITACHI_BIT}, \
142 {"isize", ISIZE_BIT}, \
143 {"l", LITTLE_ENDIAN_BIT}, \
144 {"padstruct", PADSTRUCT_BIT}, \
145 {"relax", RELAX_BIT}, \
146 {"space", SPACE_BIT}, \
147 {"", TARGET_DEFAULT} \
148 }
149
150 #define TARGET_DEFAULT (0)
151
152 #define OVERRIDE_OPTIONS \
153 do { \
154 sh_cpu = CPU_SH0; \
155 if (TARGET_SH1) \
156 sh_cpu = CPU_SH1; \
157 if (TARGET_SH2) \
158 sh_cpu = CPU_SH2; \
159 if (TARGET_SH3) \
160 sh_cpu = CPU_SH3; \
161 if (TARGET_SH3E) \
162 sh_cpu = CPU_SH3E; \
163 \
164 /* Never run scheduling before reload, since that can \
165 break global alloc, and generates slower code anyway due \
166 to the pressure on R0. */ \
167 flag_schedule_insns = 0; \
168 } while (0)
169 \f
170 /* Target machine storage layout. */
171
172 /* Define to use software floating point emulator for REAL_ARITHMETIC and
173 decimal <-> binary conversion. */
174 #define REAL_ARITHMETIC
175
176 /* Define this if most significant bit is lowest numbered
177 in instructions that operate on numbered bit-fields. */
178
179 #define BITS_BIG_ENDIAN 0
180
181 /* Define this if most significant byte of a word is the lowest numbered. */
182 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
183
184 /* Define this if most significant word of a multiword number is the lowest
185 numbered. */
186 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
187
188 /* Define this to set the endianness to use in libgcc2.c, which can
189 not depend on target_flags. */
190 #if defined(__LITTLE_ENDIAN__)
191 #define LIBGCC2_WORDS_BIG_ENDIAN 0
192 #else
193 #define LIBGCC2_WORDS_BIG_ENDIAN 1
194 #endif
195
196 /* Number of bits in an addressable storage unit. */
197 #define BITS_PER_UNIT 8
198
199 /* Width in bits of a "word", which is the contents of a machine register.
200 Note that this is not necessarily the width of data type `int';
201 if using 16-bit ints on a 68000, this would still be 32.
202 But on a machine with 16-bit registers, this would be 16. */
203 #define BITS_PER_WORD 32
204 #define MAX_BITS_PER_WORD 32
205
206 /* Width of a word, in units (bytes). */
207 #define UNITS_PER_WORD 4
208
209 /* Width in bits of a pointer.
210 See also the macro `Pmode' defined below. */
211 #define POINTER_SIZE 32
212
213 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
214 #define PARM_BOUNDARY 32
215
216 /* Boundary (in *bits*) on which stack pointer should be aligned. */
217 #define STACK_BOUNDARY 32
218
219 /* Allocation boundary (in *bits*) for the code of a function.
220 32 bit alignment is faster, because instructions are always fetched as a
221 pair from a longword boundary. */
222 /* ??? Perhaps also define ASM_OUTPUT_ALIGN_CODE and/or ASM_OUTPUT_LOOP_ALIGN
223 so as to align jump targets and/or loops to 4 byte boundaries when not
224 optimizing for space? */
225 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32)
226
227 /* Alignment of field after `int : 0' in a structure. */
228 #define EMPTY_FIELD_BOUNDARY 32
229
230 /* No data type wants to be aligned rounder than this. */
231 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
232
233 /* The best alignment to use in cases where we have a choice. */
234 #define FASTEST_ALIGNMENT 32
235
236 /* Make strings word-aligned so strcpy from constants will be faster. */
237 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
238 ((TREE_CODE (EXP) == STRING_CST \
239 && (ALIGN) < FASTEST_ALIGNMENT) \
240 ? FASTEST_ALIGNMENT : (ALIGN))
241
242 /* Make arrays of chars word-aligned for the same reasons. */
243 #define DATA_ALIGNMENT(TYPE, ALIGN) \
244 (TREE_CODE (TYPE) == ARRAY_TYPE \
245 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
246 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
247
248 /* Number of bits which any structure or union's size must be a
249 multiple of. Each structure or union's size is rounded up to a
250 multiple of this. */
251 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
252
253 /* Set this nonzero if move instructions will actually fail to work
254 when given unaligned data. */
255 #define STRICT_ALIGNMENT 1
256 \f
257 /* Standard register usage. */
258
259 /* Register allocation for the Hitachi calling convention:
260
261 r0 arg return
262 r1..r3 scratch
263 r4..r7 args in
264 r8..r13 call saved
265 r14 frame pointer/call saved
266 r15 stack pointer
267 ap arg pointer (doesn't really exist, always eliminated)
268 pr subroutine return address
269 t t bit
270 mach multiply/accumulate result, high part
271 macl multiply/accumulate result, low part.
272 fpul fp/int communication register
273 fr0 fp arg return
274 fr1..fr3 scratch floating point registers
275 fr4..fr11 fp args in
276 fr12..fr15 call saved floating point registers */
277
278 /* Number of actual hardware registers.
279 The hardware registers are assigned numbers for the compiler
280 from 0 to just below FIRST_PSEUDO_REGISTER.
281 All registers that the compiler knows about must be given numbers,
282 even those that are not normally considered general registers. */
283
284 #define AP_REG 16
285 #define PR_REG 17
286 #define T_REG 18
287 #define GBR_REG 19
288 #define MACH_REG 20
289 #define MACL_REG 21
290 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
291 #define FPUL_REG 22
292 /* Number 23 is unused. Reserved for future expansion. */
293 #define FIRST_FP_REG 24
294 #define LAST_FP_REG 39
295
296 #define FIRST_PSEUDO_REGISTER 40
297
298 /* 1 for registers that have pervasive standard uses
299 and are not available for the register allocator.
300
301 Mach register is fixed 'cause it's only 10 bits wide for SH1.
302 It is 32 bits wide for SH2. */
303
304 #define FIXED_REGISTERS \
305 { 0, 0, 0, 0, \
306 0, 0, 0, 0, \
307 0, 0, 0, 0, \
308 0, 0, 0, 1, \
309 1, 1, 1, 1, \
310 1, 1, 1, 1, \
311 0, 0, 0, 0, \
312 0, 0, 0, 0, \
313 0, 0, 0, 0, \
314 0, 0, 0, 0 \
315 }
316
317 /* 1 for registers not available across function calls.
318 These must include the FIXED_REGISTERS and also any
319 registers that can be used without being saved.
320 The latter must include the registers where values are returned
321 and the register where structure-value addresses are passed.
322 Aside from that, you can include as many other registers as you like. */
323
324 #define CALL_USED_REGISTERS \
325 { 1, 1, 1, 1, \
326 1, 1, 1, 1, \
327 0, 0, 0, 0, \
328 0, 0, 0, 1, \
329 1, 0, 1, 1, \
330 1, 1, 1, 1, \
331 1, 1, 1, 1, \
332 1, 1, 1, 1, \
333 1, 1, 1, 1, \
334 0, 0, 0, 0 \
335 }
336
337 /* Return number of consecutive hard regs needed starting at reg REGNO
338 to hold something of mode MODE.
339 This is ordinarily the length in words of a value of mode MODE
340 but can be less for certain modes in special long registers.
341
342 On the SH regs are UNITS_PER_WORD bits wide. */
343
344 #define HARD_REGNO_NREGS(REGNO, MODE) \
345 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
346
347 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
348 We can allow any mode in any general register. The special registers
349 only allow SImode. Don't allow any mode in the PR. */
350
351 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
352 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
353 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
354 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG ? (MODE) == SFmode \
355 : (REGNO) == PR_REG ? 0 \
356 : 1)
357
358 /* Value is 1 if it is a good idea to tie two pseudo registers
359 when one has mode MODE1 and one has mode MODE2.
360 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
361 for any hard reg, then this must be 0 for correct output. */
362
363 #define MODES_TIEABLE_P(MODE1, MODE2) \
364 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
365
366 /* Specify the registers used for certain standard purposes.
367 The values of these macros are register numbers. */
368
369 /* Define this if the program counter is overloaded on a register. */
370 /* #define PC_REGNUM 15*/
371
372 /* Register to use for pushing function arguments. */
373 #define STACK_POINTER_REGNUM 15
374
375 /* Base register for access to local variables of the function. */
376 #define FRAME_POINTER_REGNUM 14
377
378 /* Value should be nonzero if functions must have frame pointers.
379 Zero means the frame pointer need not be set up (and parms may be accessed
380 via the stack pointer) in functions that seem suitable. */
381
382 #define FRAME_POINTER_REQUIRED 0
383
384 /* Definitions for register eliminations.
385
386 We have two registers that can be eliminated on the SH. First, the
387 frame pointer register can often be eliminated in favor of the stack
388 pointer register. Secondly, the argument pointer register can always be
389 eliminated; it is replaced with either the stack or frame pointer. */
390
391 /* This is an array of structures. Each structure initializes one pair
392 of eliminable registers. The "from" register number is given first,
393 followed by "to". Eliminations of the same "from" register are listed
394 in order of preference. */
395
396 #define ELIMINABLE_REGS \
397 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
398 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
399 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
400
401 /* Given FROM and TO register numbers, say whether this elimination
402 is allowed. */
403 #define CAN_ELIMINATE(FROM, TO) \
404 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
405
406 /* Define the offset between two registers, one to be eliminated, and the other
407 its replacement, at the start of a routine. */
408
409 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
410 OFFSET = initial_elimination_offset (FROM, TO)
411
412 /* Base register for access to arguments of the function. */
413 #define ARG_POINTER_REGNUM 16
414
415 /* Register in which the static-chain is passed to a function. */
416 #define STATIC_CHAIN_REGNUM 13
417
418 /* The register in which a struct value address is passed. */
419
420 #define STRUCT_VALUE_REGNUM 2
421
422 /* If the structure value address is not passed in a register, define
423 `STRUCT_VALUE' as an expression returning an RTX for the place
424 where the address is passed. If it returns 0, the address is
425 passed as an "invisible" first argument. */
426
427 /*#define STRUCT_VALUE ((rtx)0)*/
428
429 /* Don't default to pcc-struct-return, because we have already specified
430 exactly how to return structures in the RETURN_IN_MEMORY macro. */
431
432 #define DEFAULT_PCC_STRUCT_RETURN 0
433 \f
434 /* Define the classes of registers for register constraints in the
435 machine description. Also define ranges of constants.
436
437 One of the classes must always be named ALL_REGS and include all hard regs.
438 If there is more than one class, another class must be named NO_REGS
439 and contain no registers.
440
441 The name GENERAL_REGS must be the name of a class (or an alias for
442 another name such as ALL_REGS). This is the class of registers
443 that is allowed by "g" or "r" in a register constraint.
444 Also, registers outside this class are allocated only when
445 instructions express preferences for them.
446
447 The classes must be numbered in nondecreasing order; that is,
448 a larger-numbered class must never be contained completely
449 in a smaller-numbered class.
450
451 For any two classes, it is very desirable that there be another
452 class that represents their union. */
453
454 /* The SH has two sorts of general registers, R0 and the rest. R0 can
455 be used as the destination of some of the arithmetic ops. There are
456 also some special purpose registers; the T bit register, the
457 Procedure Return Register and the Multiply Accumulate Registers. */
458
459 enum reg_class
460 {
461 NO_REGS,
462 R0_REGS,
463 PR_REGS,
464 T_REGS,
465 MAC_REGS,
466 GENERAL_REGS,
467 FPUL_REGS,
468 FP0_REGS,
469 FP_REGS,
470 ALL_REGS,
471 LIM_REG_CLASSES
472 };
473
474 #define N_REG_CLASSES (int) LIM_REG_CLASSES
475
476 /* Give names of register classes as strings for dump file. */
477 #define REG_CLASS_NAMES \
478 { \
479 "NO_REGS", \
480 "R0_REGS", \
481 "PR_REGS", \
482 "T_REGS", \
483 "MAC_REGS", \
484 "GENERAL_REGS", \
485 "FPUL_REGS", \
486 "FP0_REGS", \
487 "FP_REGS", \
488 "ALL_REGS", \
489 }
490
491 /* Define which registers fit in which classes.
492 This is an initializer for a vector of HARD_REG_SET
493 of length N_REG_CLASSES. */
494
495 #define REG_CLASS_CONTENTS \
496 { \
497 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
498 { 0x00000001, 0x00000000 }, /* R0_REGS */ \
499 { 0x00020000, 0x00000000 }, /* PR_REGS */ \
500 { 0x00040000, 0x00000000 }, /* T_REGS */ \
501 { 0x00300000, 0x00000000 }, /* MAC_REGS */ \
502 { 0x0001FFFF, 0x00000000 }, /* GENERAL_REGS */ \
503 { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
504 { 0x01000000, 0x00000000 }, /* FP0_REGS */ \
505 { 0xFF000000, 0x000000FF }, /* FP_REGS */ \
506 { 0xFF7FFFFF, 0x000000FF }, /* ALL_REGS */ \
507 }
508
509 /* The same information, inverted:
510 Return the class number of the smallest class containing
511 reg number REGNO. This could be a conditional expression
512 or could index an array. */
513
514 extern int regno_reg_class[];
515 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
516
517 /* When defined, the compiler allows registers explicitly used in the
518 rtl to be used as spill registers but prevents the compiler from
519 extending the lifetime of these registers. */
520
521 #define SMALL_REGISTER_CLASSES
522
523 /* The order in which register should be allocated. */
524 #define REG_ALLOC_ORDER \
525 { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
526 24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, \
527 22,15,16,17,18,19,20,21,23 }
528
529 /* The class value for index registers, and the one for base regs. */
530 #define INDEX_REG_CLASS R0_REGS
531 #define BASE_REG_CLASS GENERAL_REGS
532
533 /* Get reg_class from a letter such as appears in the machine
534 description. */
535 extern enum reg_class reg_class_from_letter[];
536
537 #define REG_CLASS_FROM_LETTER(C) \
538 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
539 \f
540 /* The letters I, J, K, L and M in a register constraint string
541 can be used to stand for particular ranges of immediate operands.
542 This macro defines what the ranges are.
543 C is the letter, and VALUE is a constant value.
544 Return 1 if VALUE is in the range specified by C.
545 I: arithmetic operand -127..128, as used in add, sub, etc
546 K: shift operand 1,2,8 or 16
547 L: logical operand 0..255, as used in and, or, etc.
548 M: constant 1
549 N: constant 0 */
550
551 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
552 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
553 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
554 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
555 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
556 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
557 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
558 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
559 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
560 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
561 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
562 : 0)
563
564 /* Similar, but for floating constants, and defining letters G and H.
565 Here VALUE is the CONST_DOUBLE rtx itself. */
566
567 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
568 ((C) == 'G' ? fp_zero_operand (VALUE) \
569 : (C) == 'H' ? fp_one_operand (VALUE) \
570 : 0)
571
572 /* Given an rtx X being reloaded into a reg required to be
573 in class CLASS, return the class of reg to actually use.
574 In general this is just CLASS; but on some machines
575 in some cases it is preferable to use a more restrictive class. */
576
577 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
578
579 /* Return the maximum number of consecutive registers
580 needed to represent mode MODE in a register of class CLASS.
581
582 On SH this is the size of MODE in words. */
583 #define CLASS_MAX_NREGS(CLASS, MODE) \
584 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
585 \f
586 /* Stack layout; function entry, exit and calling. */
587
588 /* Define the number of registers that can hold parameters.
589 These macros are used only in other macro definitions below. */
590
591 #define NPARM_REGS(MODE) \
592 ((TARGET_SH3E && ((MODE) == SFmode)) ? 8 : 4)
593
594 #define FIRST_PARM_REG 4
595 #define FIRST_RET_REG 0
596
597 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
598 #define FIRST_FP_RET_REG FIRST_FP_REG
599
600 /* Define this if pushing a word on the stack
601 makes the stack pointer a smaller address. */
602 #define STACK_GROWS_DOWNWARD
603
604 /* Define this macro if the addresses of local variable slots are at
605 negative offsets from the frame pointer.
606
607 The SH only has positive indexes, so grow the frame up. */
608 /* #define FRAME_GROWS_DOWNWARD */
609
610 /* Offset from the frame pointer to the first local variable slot to
611 be allocated. */
612 #define STARTING_FRAME_OFFSET 0
613
614 /* If we generate an insn to push BYTES bytes,
615 this says how many the stack pointer really advances by. */
616 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
617
618 /* Offset of first parameter from the argument pointer register value. */
619 #define FIRST_PARM_OFFSET(FNDECL) 0
620
621 /* Value is the number of byte of arguments automatically
622 popped when returning from a subroutine call.
623 FUNDECL is the declaration node of the function (as a tree),
624 FUNTYPE is the data type of the function (as a tree),
625 or for a library call it is an identifier node for the subroutine name.
626 SIZE is the number of bytes of arguments passed on the stack.
627
628 On the SH, the caller does not pop any of its arguments that were passed
629 on the stack. */
630 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
631
632 /* Some subroutine macros specific to this machine. */
633
634 #define BASE_RETURN_VALUE_REG(MODE) \
635 ((TARGET_SH3E && ((MODE) == SFmode)) \
636 ? FIRST_FP_RET_REG \
637 : FIRST_RET_REG)
638
639 #define BASE_ARG_REG(MODE) \
640 ((TARGET_SH3E && ((MODE) == SFmode)) \
641 ? FIRST_FP_PARM_REG \
642 : FIRST_PARM_REG)
643
644 /* Define how to find the value returned by a function.
645 VALTYPE is the data type of the value (as a tree).
646 If the precise function being called is known, FUNC is its FUNCTION_DECL;
647 otherwise, FUNC is 0. */
648
649 #define FUNCTION_VALUE(VALTYPE, FUNC) \
650 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
651
652 /* Define how to find the value returned by a library function
653 assuming the value has mode MODE. */
654 #define LIBCALL_VALUE(MODE) \
655 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE));
656
657 /* 1 if N is a possible register number for a function value. */
658 #define FUNCTION_VALUE_REGNO_P(REGNO) \
659 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
660
661 /* 1 if N is a possible register number for function argument passing. */
662 #define FUNCTION_ARG_REGNO_P(REGNO) \
663 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
664 || (TARGET_SH3E \
665 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
666 \f
667 /* Define a data type for recording info about an argument list
668 during the scan of that argument list. This data type should
669 hold all necessary information about the function itself
670 and about the args processed so far, enough to enable macros
671 such as FUNCTION_ARG to determine where the next arg should go.
672
673 On SH, this is a single integer, which is a number of words
674 of arguments scanned so far (including the invisible argument,
675 if any, which holds the structure-value-address).
676 Thus NARGREGS or more means all following args should go on the stack. */
677
678 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
679 struct sh_args {
680 int arg_count[2];
681 };
682
683 #define CUMULATIVE_ARGS struct sh_args
684
685 #define GET_SH_ARG_CLASS(MODE) \
686 ((TARGET_SH3E && ((MODE) == SFmode)) ? SH_ARG_FLOAT : SH_ARG_INT)
687
688 #define ROUND_ADVANCE(SIZE) \
689 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
690
691 /* Round a register number up to a proper boundary for an arg of mode
692 MODE.
693
694 The SH doesn't care about double alignment, so we only
695 round doubles to even regs when asked to explicitly. */
696
697 #define ROUND_REG(CUM, MODE) \
698 ((TARGET_ALIGN_DOUBLE \
699 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
700 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
701 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
702 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
703
704 /* Initialize a variable CUM of type CUMULATIVE_ARGS
705 for a call to a function whose data type is FNTYPE.
706 For a library call, FNTYPE is 0.
707
708 On SH, the offset always starts at 0: the first parm reg is always
709 the same reg. */
710
711 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
712 do { \
713 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
714 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
715 } while (0)
716
717 /* Update the data in CUM to advance over an argument
718 of mode MODE and data type TYPE.
719 (TYPE is null for libcalls where that information may not be
720 available.) */
721
722 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
723 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] = \
724 (ROUND_REG ((CUM), (MODE)) \
725 + ((MODE) != BLKmode \
726 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
727 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
728
729 /* Return boolean indicating arg of mode MODE will be passed in a reg.
730 This macro is only used in this file. */
731
732 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
733 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
734 && ((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
735 && (! TARGET_SH3E || (ROUND_REG((CUM), (MODE)) + (GET_MODE_SIZE(MODE)/4) <= NPARM_REGS (MODE))))
736
737 /* Define where to put the arguments to a function.
738 Value is zero to push the argument on the stack,
739 or a hard register in which to store the argument.
740
741 MODE is the argument's machine mode.
742 TYPE is the data type of the argument (as a tree).
743 This is null for libcalls where that information may
744 not be available.
745 CUM is a variable of type CUMULATIVE_ARGS which gives info about
746 the preceding args and about the function being called.
747 NAMED is nonzero if this argument is a named parameter
748 (otherwise it is an extra parameter matching an ellipsis).
749
750 On SH the first args are normally in registers
751 and the rest are pushed. Any arg that starts within the first
752 NPARM_REGS words is at least partially passed in a register unless
753 its data type forbids. */
754
755 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
756 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
757 && (NAMED || TARGET_SH3E)) \
758 ? gen_rtx (REG, (MODE), \
759 (BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
760 : 0)
761
762 /* For an arg passed partly in registers and partly in memory,
763 this is the number of registers used.
764 For args passed entirely in registers or entirely in memory, zero.
765
766 We sometimes split args. */
767
768 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
769 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
770 && (NAMED || TARGET_SH3E) \
771 && (ROUND_REG ((CUM), (MODE)) \
772 + (MODE != BLKmode \
773 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
774 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
775 - NPARM_REGS (MODE) > 0)) \
776 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
777 : 0)
778
779 extern int current_function_anonymous_args;
780
781 /* Perform any needed actions needed for a function that is receiving a
782 variable number of arguments. */
783
784 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
785 current_function_anonymous_args = 1;
786
787 /* Call the function profiler with a given profile label.
788 We use two .aligns, so as to make sure that both the .long is aligned
789 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
790 from the trapa instruction. */
791
792 #define FUNCTION_PROFILER(STREAM,LABELNO) \
793 { \
794 fprintf(STREAM, " .align 2\n"); \
795 fprintf(STREAM, " trapa #33\n"); \
796 fprintf(STREAM, " .align 2\n"); \
797 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
798 }
799
800 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
801 the stack pointer does not matter. The value is tested only in
802 functions that have frame pointers.
803 No definition is equivalent to always zero. */
804
805 #define EXIT_IGNORE_STACK 1
806
807 /* Generate the assembly code for function exit
808 Just dump out any accumulated constant table. */
809
810 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
811
812 /* Output assembler code for a block containing the constant parts
813 of a trampoline, leaving space for the variable parts.
814
815 On the SH, the trampoline looks like
816 1 0000 D301 mov.l l1,r3
817 2 0002 DD02 mov.l l2,r13
818 3 0004 4D2B jmp @r13
819 4 0006 200B or r0,r0
820 5 0008 00000000 l1: .long function
821 6 000c 00000000 l2: .long area */
822 #define TRAMPOLINE_TEMPLATE(FILE) \
823 { \
824 fprintf ((FILE), " .word 0xd301\n"); \
825 fprintf ((FILE), " .word 0xdd02\n"); \
826 fprintf ((FILE), " .word 0x4d2b\n"); \
827 fprintf ((FILE), " .word 0x200b\n"); \
828 fprintf ((FILE), " .long 0\n"); \
829 fprintf ((FILE), " .long 0\n"); \
830 }
831
832 /* Length in units of the trampoline for entering a nested function. */
833 #define TRAMPOLINE_SIZE 16
834
835 /* Alignment required for a trampoline in units. */
836 #define TRAMPOLINE_ALIGN 4
837
838 /* Emit RTL insns to initialize the variable parts of a trampoline.
839 FNADDR is an RTX for the address of the function's pure code.
840 CXT is an RTX for the static chain value for the function. */
841
842 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
843 { \
844 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
845 (CXT)); \
846 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
847 (FNADDR)); \
848 }
849 \f
850 /* Generate necessary RTL for __builtin_saveregs().
851 ARGLIST is the argument list; see expr.c. */
852 extern struct rtx_def *sh_builtin_saveregs ();
853 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST)
854 \f
855 /* Addressing modes, and classification of registers for them. */
856 #define HAVE_POST_INCREMENT 1
857 /*#define HAVE_PRE_INCREMENT 1*/
858 /*#define HAVE_POST_DECREMENT 1*/
859 #define HAVE_PRE_DECREMENT 1
860
861 /* Macros to check register numbers against specific register classes. */
862
863 /* These assume that REGNO is a hard or pseudo reg number.
864 They give nonzero only if REGNO is a hard reg of the suitable class
865 or a pseudo reg currently allocated to a suitable hard reg.
866 Since they use reg_renumber, they are safe only once reg_renumber
867 has been allocated, which happens in local-alloc.c. */
868
869 #define REGNO_OK_FOR_BASE_P(REGNO) \
870 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
871 #define REGNO_OK_FOR_INDEX_P(REGNO) \
872 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
873
874 /* Maximum number of registers that can appear in a valid memory
875 address. */
876
877 #define MAX_REGS_PER_ADDRESS 2
878
879 /* Recognize any constant value that is a valid address. */
880
881 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
882
883 /* Nonzero if the constant value X is a legitimate general operand. */
884
885 /* ??? Should modify this to accept CONST_DOUBLE, and then modify the
886 constant pool table code to fix loads of CONST_DOUBLEs. If that doesn't
887 work well, then we can at least handle simple CONST_DOUBLEs here
888 such as 0.0. */
889
890 #define LEGITIMATE_CONSTANT_P(X) \
891 (GET_CODE (X) != CONST_DOUBLE \
892 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
893
894 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
895 and check its validity for a certain class.
896 We have two alternate definitions for each of them.
897 The usual definition accepts all pseudo regs; the other rejects
898 them unless they have been allocated suitable hard regs.
899 The symbol REG_OK_STRICT causes the latter definition to be used. */
900
901 #ifndef REG_OK_STRICT
902
903 /* Nonzero if X is a hard reg that can be used as a base reg
904 or if it is a pseudo reg. */
905 #define REG_OK_FOR_BASE_P(X) \
906 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
907
908 /* Nonzero if X is a hard reg that can be used as an index
909 or if it is a pseudo reg. */
910 #define REG_OK_FOR_INDEX_P(X) \
911 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
912
913 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
914 or if X is a pseudo reg. */
915 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
916 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
917
918 #else
919
920 /* Nonzero if X is a hard reg that can be used as a base reg. */
921 #define REG_OK_FOR_BASE_P(X) \
922 REGNO_OK_FOR_BASE_P (REGNO (X))
923
924 /* Nonzero if X is a hard reg that can be used as an index. */
925 #define REG_OK_FOR_INDEX_P(X) \
926 REGNO_OK_FOR_INDEX_P (REGNO (X))
927
928 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
929 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
930 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && OFFSET == 0)
931
932 #endif
933
934 /* The 'Q' constraint is a pc relative load operand. */
935 #define EXTRA_CONSTRAINT_Q(OP) \
936 (GET_CODE (OP) == MEM && \
937 ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
938 || (GET_CODE (XEXP (OP, 0)) == CONST \
939 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
940 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
941 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
942
943 #define EXTRA_CONSTRAINT(OP, C) \
944 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
945 : 0)
946 \f
947 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
948 that is a valid memory address for an instruction.
949 The MODE argument is the machine mode for the MEM expression
950 that wants to use this address.
951
952 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
953
954 #define MODE_DISP_OK_4(X,MODE) \
955 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
956 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && MODE == SFmode))
957 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
958
959 #define BASE_REGISTER_RTX_P(X) \
960 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
961 || (GET_CODE (X) == SUBREG \
962 && GET_CODE (SUBREG_REG (X)) == REG \
963 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
964
965 /* Since this must be r0, which is a single register class, we must check
966 SUBREGs more carefully, to be sure that we don't accept one that extends
967 outside the class. */
968 #define INDEX_REGISTER_RTX_P(X) \
969 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
970 || (GET_CODE (X) == SUBREG \
971 && GET_CODE (SUBREG_REG (X)) == REG \
972 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
973
974 /* Jump to LABEL if X is a valid address RTX. This must also take
975 REG_OK_STRICT into account when deciding about valid registers, but it uses
976 the above macros so we are in luck.
977
978 Allow REG
979 REG+disp
980 REG+r0
981 REG++
982 --REG */
983
984 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
985 into the FRx registers. We implement this by setting the maximum offset
986 to zero when the value is SFmode. This also restricts loading of SFmode
987 values into the integer registers, but that can't be helped. */
988
989 /* The SH allows a displacement in a QI or HI amode, but only when the
990 other operand is R0. GCC doesn't handle this very well, so we forgo
991 all of that.
992
993 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
994 DI can be any number 0..60. */
995
996 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
997 do { \
998 if (GET_CODE (OP) == CONST_INT) \
999 { \
1000 if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
1001 if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
1002 } \
1003 } while(0)
1004
1005 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1006 { \
1007 if (BASE_REGISTER_RTX_P (X)) \
1008 goto LABEL; \
1009 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1010 && BASE_REGISTER_RTX_P (XEXP (X, 0))) \
1011 goto LABEL; \
1012 else if (GET_CODE (X) == PLUS) \
1013 { \
1014 rtx xop0 = XEXP (X, 0); \
1015 rtx xop1 = XEXP (X, 1); \
1016 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1017 GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \
1018 if (GET_MODE_SIZE (MODE) <= 4) \
1019 { \
1020 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1021 goto LABEL; \
1022 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1023 goto LABEL; \
1024 } \
1025 } \
1026 }
1027 \f
1028 /* Try machine-dependent ways of modifying an illegitimate address
1029 to be legitimate. If we find one, return the new, valid address.
1030 This macro is used in only one place: `memory_address' in explow.c.
1031
1032 OLDX is the address as it was before break_out_memory_refs was called.
1033 In some cases it is useful to look at this to decide what needs to be done.
1034
1035 MODE and WIN are passed so that this macro can use
1036 GO_IF_LEGITIMATE_ADDRESS.
1037
1038 It is always safe for this macro to do nothing. It exists to recognize
1039 opportunities to optimize the output. */
1040
1041 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
1042
1043 /* Go to LABEL if ADDR (a legitimate address expression)
1044 has an effect that depends on the machine mode it is used for. */
1045 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1046 { \
1047 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1048 goto LABEL; \
1049 }
1050 \f
1051 /* Specify the machine mode that this machine uses
1052 for the index in the tablejump instruction. */
1053 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1054
1055 /* Define this if the tablejump instruction expects the table
1056 to contain offsets from the address of the table.
1057 Do not define this if the table should contain absolute addresses. */
1058 #define CASE_VECTOR_PC_RELATIVE
1059
1060 /* Specify the tree operation to be used to convert reals to integers. */
1061 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1062
1063 /* This is the kind of divide that is easiest to do in the general case. */
1064 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1065
1066 /* Since the SH3e has only `float' support, it is desirable to make all
1067 floating point types equivalent to `float'. */
1068 #define DOUBLE_TYPE_SIZE (TARGET_SH3E ? 32 : 64)
1069
1070 /* 'char' is signed by default. */
1071 #define DEFAULT_SIGNED_CHAR 1
1072
1073 /* The type of size_t unsigned int. */
1074 #define SIZE_TYPE "unsigned int"
1075
1076 #define WCHAR_TYPE "short unsigned int"
1077 #define WCHAR_TYPE_SIZE 16
1078
1079 /* Don't cse the address of the function being compiled. */
1080 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1081
1082 /* Max number of bytes we can move from memory to memory
1083 in one reasonably fast instruction. */
1084 #define MOVE_MAX 4
1085
1086 /* Define if operations between registers always perform the operation
1087 on the full register even if a narrower mode is specified. */
1088 #define WORD_REGISTER_OPERATIONS
1089
1090 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1091 will either zero-extend or sign-extend. The value of this macro should
1092 be the code that says which one of the two operations is implicitly
1093 done, NIL if none. */
1094 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1095
1096 /* Define this if zero-extension is slow (more than one real instruction).
1097 On the SH, it's only one instruction. */
1098 /* #define SLOW_ZERO_EXTEND */
1099
1100 /* Nonzero if access to memory by bytes is slow and undesirable. */
1101 #define SLOW_BYTE_ACCESS 0
1102
1103 /* We assume that the store-condition-codes instructions store 0 for false
1104 and some other value for true. This is the value stored for true. */
1105
1106 #define STORE_FLAG_VALUE 1
1107
1108 /* Immediate shift counts are truncated by the output routines (or was it
1109 the assembler?). Shift counts in a register are truncated by SH. Note
1110 that the native compiler puts too large (> 32) immediate shift counts
1111 into a register and shifts by the register, letting the SH decide what
1112 to do instead of doing that itself. */
1113 /* ??? This is defined, but the library routines in lib1funcs.asm do not
1114 truncate the shift count. This may result in incorrect results for
1115 unusual cases. Truncating the shift counts in the library routines would
1116 make them faster. However, the SH3 has hardware shifts that do not
1117 truncate, so it appears that we need to leave this undefined for correct
1118 SH3 code. We can still using truncation in the library routines though to
1119 make them faster. */
1120 #define SHIFT_COUNT_TRUNCATED 1
1121
1122 /* All integers have the same format so truncation is easy. */
1123 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1124
1125 /* Define this if addresses of constant functions
1126 shouldn't be put through pseudo regs where they can be cse'd.
1127 Desirable on machines where ordinary constants are expensive
1128 but a CALL with constant address is cheap. */
1129 /*#define NO_FUNCTION_CSE 1*/
1130
1131 /* Chars and shorts should be passed as ints. */
1132 #define PROMOTE_PROTOTYPES 1
1133
1134 /* The machine modes of pointers and functions. */
1135 #define Pmode SImode
1136 #define FUNCTION_MODE Pmode
1137
1138 /* The relative costs of various types of constants. Note that cse.c defines
1139 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1140
1141 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1142 case CONST_INT: \
1143 if (INTVAL (RTX) == 0) \
1144 return 0; \
1145 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1146 return 1; \
1147 else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \
1148 && CONST_OK_FOR_L (INTVAL (RTX))) \
1149 return 1; \
1150 else \
1151 return 8; \
1152 case CONST: \
1153 case LABEL_REF: \
1154 case SYMBOL_REF: \
1155 return 5; \
1156 case CONST_DOUBLE: \
1157 return 10;
1158
1159 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1160 case AND: \
1161 return COSTS_N_INSNS (andcosts (X)); \
1162 case MULT: \
1163 return COSTS_N_INSNS (multcosts (X)); \
1164 case ASHIFT: \
1165 case ASHIFTRT: \
1166 case LSHIFTRT: \
1167 return COSTS_N_INSNS (shiftcosts (X)) ; \
1168 case DIV: \
1169 case UDIV: \
1170 case MOD: \
1171 case UMOD: \
1172 return COSTS_N_INSNS (20); \
1173 case FLOAT: \
1174 case FIX: \
1175 return 100;
1176
1177 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1178 are actually function calls with some special constraints on arguments
1179 and register usage.
1180
1181 These macros tell reorg that the references to arguments and
1182 register clobbers for insns of type sfunc do not appear to happen
1183 until after the millicode call. This allows reorg to put insns
1184 which set the argument registers into the delay slot of the millicode
1185 call -- thus they act more like traditional CALL_INSNs.
1186
1187 get_attr_type will try to recognize the given insn, so make sure to
1188 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1189 in particular. */
1190
1191 #define INSN_SETS_ARE_DELAYED(X) \
1192 ((GET_CODE (X) == INSN \
1193 && GET_CODE (PATTERN (X)) != SEQUENCE \
1194 && GET_CODE (PATTERN (X)) != USE \
1195 && GET_CODE (PATTERN (X)) != CLOBBER \
1196 && get_attr_type (X) == TYPE_SFUNC))
1197
1198 #define INSN_REFERENCES_ARE_DELAYED(X) \
1199 ((GET_CODE (X) == INSN \
1200 && GET_CODE (PATTERN (X)) != SEQUENCE \
1201 && GET_CODE (PATTERN (X)) != USE \
1202 && GET_CODE (PATTERN (X)) != CLOBBER \
1203 && get_attr_type (X) == TYPE_SFUNC))
1204
1205 /* Compute the cost of an address. For the SH, all valid addresses are
1206 the same cost. */
1207 /* ??? Perhaps we should make reg+reg addresses have higher cost because
1208 they add to register pressure on r0. */
1209
1210 #define ADDRESS_COST(RTX) 1
1211
1212 /* Compute extra cost of moving data between one register class
1213 and another.
1214
1215 On the SH it is hard to move into the T reg, but simple to load
1216 from it. */
1217
1218 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1219 (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 \
1220 : ((DSTCLASS == FP_REGS && SRCCLASS == GENERAL_REGS) \
1221 || (DSTCLASS == GENERAL_REGS && SRCCLASS == FP_REGS)) ? 4 \
1222 : 1)
1223
1224 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1225 would be so that people would slow memory systems could generate
1226 different code that does fewer memory accesses. */
1227 \f
1228 /* Assembler output control. */
1229
1230 /* The text to go at the start of the assembler file. */
1231 #define ASM_FILE_START(STREAM) \
1232 output_file_start (STREAM, f_options, \
1233 sizeof f_options / sizeof f_options[0], \
1234 W_options, sizeof W_options / sizeof W_options[0]);
1235
1236 #define ASM_FILE_END(STREAM)
1237
1238 #define ASM_APP_ON ""
1239 #define ASM_APP_OFF ""
1240 #define FILE_ASM_OP "\t.file\n"
1241 #define IDENT_ASM_OP "\t.ident\n"
1242
1243 /* How to change between sections. */
1244
1245 #define TEXT_SECTION_ASM_OP "\t.text"
1246 #define DATA_SECTION_ASM_OP "\t.data"
1247 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1248 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1249 #define EXTRA_SECTIONS in_ctors, in_dtors
1250 #define EXTRA_SECTION_FUNCTIONS \
1251 void \
1252 ctors_section() \
1253 { \
1254 if (in_section != in_ctors) \
1255 { \
1256 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1257 in_section = in_ctors; \
1258 } \
1259 } \
1260 void \
1261 dtors_section() \
1262 { \
1263 if (in_section != in_dtors) \
1264 { \
1265 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1266 in_section = in_dtors; \
1267 } \
1268 }
1269
1270 /* Define this so that jump tables go in same section as the current function,
1271 which could be text or it could be a user defined section. */
1272 #define JUMP_TABLES_IN_TEXT_SECTION
1273
1274 /* A C statement to output something to the assembler file to switch to section
1275 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1276 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1277 define this macro in such cases. */
1278
1279 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
1280 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1281
1282 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1283 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1284
1285 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1286 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1287
1288 #undef DO_GLOBAL_CTORS_BODY
1289
1290 #define DO_GLOBAL_CTORS_BODY \
1291 { \
1292 typedef (*pfunc)(); \
1293 extern pfunc __ctors[]; \
1294 extern pfunc __ctors_end[]; \
1295 pfunc *p; \
1296 for (p = __ctors_end; p > __ctors; ) \
1297 { \
1298 (*--p)(); \
1299 } \
1300 }
1301
1302 #undef DO_GLOBAL_DTORS_BODY
1303 #define DO_GLOBAL_DTORS_BODY \
1304 { \
1305 typedef (*pfunc)(); \
1306 extern pfunc __dtors[]; \
1307 extern pfunc __dtors_end[]; \
1308 pfunc *p; \
1309 for (p = __dtors; p < __dtors_end; p++) \
1310 { \
1311 (*p)(); \
1312 } \
1313 }
1314
1315 #define ASM_OUTPUT_REG_PUSH(file, v) \
1316 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1317
1318 #define ASM_OUTPUT_REG_POP(file, v) \
1319 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1320
1321 /* The assembler's names for the registers. RFP need not always be used as
1322 the Real framepointer; it can also be used as a normal general register.
1323 Note that the name `fp' is horribly misleading since `fp' is in fact only
1324 the argument-and-return-context pointer. */
1325 #define REGISTER_NAMES \
1326 { \
1327 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1328 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1329 "ap", "pr", "t", "gbr", "mach","macl", "fpul", "X", \
1330 "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1331 "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
1332 }
1333
1334 /* DBX register number for a given compiler register number. */
1335 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1336 to match gdb. */
1337 #define DBX_REGISTER_NUMBER(REGNO) \
1338 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
1339
1340 /* Output a label definition. */
1341 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1342 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1343
1344 /* This is how to output an assembler line
1345 that says to advance the location counter
1346 to a multiple of 2**LOG bytes. */
1347
1348 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1349 if ((LOG) != 0) \
1350 fprintf (FILE, "\t.align %d\n", LOG)
1351
1352 /* Output a function label definition. */
1353 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1354 ASM_OUTPUT_LABEL(STREAM, NAME)
1355
1356 /* Output a globalising directive for a label. */
1357 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1358 (fprintf (STREAM, "\t.global\t"), \
1359 assemble_name (STREAM, NAME), \
1360 fputc ('\n',STREAM))
1361
1362 /* Output a reference to a label. */
1363 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1364 fprintf (STREAM, "_%s", NAME)
1365
1366 /* Make an internal label into a string. */
1367 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1368 sprintf (STRING, "*%s%d", PREFIX, NUM)
1369
1370 /* Output an internal label definition. */
1371 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1372 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1373
1374 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1375
1376 /* Construct a private name. */
1377 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1378 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1379 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1380
1381 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
1382 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1383 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1384
1385 /* Output a relative address table. */
1386
1387 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1388 if (TARGET_BIGTABLE) \
1389 fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
1390 else \
1391 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
1392
1393 /* Output an absolute table element. */
1394
1395 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1396 if (TARGET_BIGTABLE) \
1397 fprintf (STREAM, "\t.long L%d\n", VALUE); \
1398 else \
1399 fprintf (STREAM, "\t.word L%d\n", VALUE); \
1400
1401 /* Output various types of constants. */
1402
1403 /* This is how to output an assembler line defining a `double'. */
1404
1405 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1406 do { char dstr[30]; \
1407 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1408 fprintf (FILE, "\t.double %s\n", dstr); \
1409 } while (0)
1410
1411 /* This is how to output an assembler line defining a `float' constant. */
1412 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1413 do { char dstr[30]; \
1414 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1415 fprintf (FILE, "\t.float %s\n", dstr); \
1416 } while (0)
1417
1418 #define ASM_OUTPUT_INT(STREAM, EXP) \
1419 (fprintf (STREAM, "\t.long\t"), \
1420 output_addr_const (STREAM, (EXP)), \
1421 fputc ('\n', STREAM))
1422
1423 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1424 (fprintf (STREAM, "\t.short\t"), \
1425 output_addr_const (STREAM, (EXP)), \
1426 fputc ('\n', STREAM))
1427
1428 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1429 (fprintf (STREAM, "\t.byte\t"), \
1430 output_addr_const (STREAM, (EXP)), \
1431 fputc ('\n', STREAM))
1432
1433 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1434 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1435
1436 /* This is how to output an assembler line
1437 that says to advance the location counter by SIZE bytes. */
1438
1439 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1440 fprintf (FILE, "\t.space %d\n", (SIZE))
1441
1442 /* This says how to output an assembler line
1443 to define a global common symbol. */
1444
1445 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1446 ( fputs ("\t.comm ", (FILE)), \
1447 assemble_name ((FILE), (NAME)), \
1448 fprintf ((FILE), ",%d\n", (SIZE)))
1449
1450 /* This says how to output an assembler line
1451 to define a local common symbol. */
1452
1453 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1454 ( fputs ("\t.lcomm ", (FILE)), \
1455 assemble_name ((FILE), (NAME)), \
1456 fprintf ((FILE), ",%d\n", (SIZE)))
1457
1458 /* The assembler's parentheses characters. */
1459 #define ASM_OPEN_PAREN "("
1460 #define ASM_CLOSE_PAREN ")"
1461
1462 /* Target characters. */
1463 #define TARGET_BELL 007
1464 #define TARGET_BS 010
1465 #define TARGET_TAB 011
1466 #define TARGET_NEWLINE 012
1467 #define TARGET_VT 013
1468 #define TARGET_FF 014
1469 #define TARGET_CR 015
1470 \f
1471 /* Only perform branch elimination (by making instructions conditional) if
1472 we're optimizing. Otherwise it's of no use anyway. */
1473 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1474 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1475
1476 /* Print operand X (an rtx) in assembler syntax to file FILE.
1477 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1478 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1479
1480 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1481
1482 /* Print a memory address as an operand to reference that memory location. */
1483
1484 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1485
1486 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1487 ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
1488 \f
1489 extern struct rtx_def *sh_compare_op0;
1490 extern struct rtx_def *sh_compare_op1;
1491 extern struct rtx_def *prepare_scc_operands();
1492
1493 /* Which processor to schedule for. The elements of the enumeration must
1494 match exactly the cpu attribute in the sh.md file. */
1495
1496 enum processor_type {
1497 PROCESSOR_SH0,
1498 PROCESSOR_SH1,
1499 PROCESSOR_SH2,
1500 PROCESSOR_SH3,
1501 PROCESSOR_SH3E
1502 };
1503
1504 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1505 extern enum processor_type sh_cpu;
1506
1507 /* Declare functions defined in sh.c and used in templates. */
1508
1509 extern char *output_branch();
1510 extern char *output_shift();
1511 extern char *output_movedouble();
1512 extern char *output_movepcrel();
1513 extern char *output_jump_label_table();
1514 extern char *output_far_jump();
1515
1516 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1517
1518 /* Generate calls to memcpy, memcmp and memset. */
1519
1520 #define TARGET_MEM_FUNCTIONS
1521
1522 /* Define this macro if you want to implement any pragmas. If defined, it
1523 is a C expression to be executed when #pragma is seen. The
1524 argument FILE is the stdio input stream from which the source
1525 text can be read. CH is the first character after the #pragma. The
1526 result of the expression is the terminating character found
1527 (newline or EOF). */
1528 #define HANDLE_PRAGMA(FILE, CH) handle_pragma (FILE, CH)
1529
1530 /* Set when processing a function with pragma interrupt turned on. */
1531
1532 extern int pragma_interrupt;
1533
1534 #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
1535 \f
1536 /* Instructions with unfilled delay slots take up an extra two bytes for
1537 the nop in the delay slot. */
1538
1539 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1540 if (((GET_CODE (X) == INSN \
1541 && GET_CODE (PATTERN (X)) != SEQUENCE \
1542 && GET_CODE (PATTERN (X)) != USE \
1543 && GET_CODE (PATTERN (X)) != CLOBBER) \
1544 || GET_CODE (X) == CALL_INSN \
1545 || (GET_CODE (X) == JUMP_INSN \
1546 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
1547 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
1548 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
1549 LENGTH += 2;
1550
1551 /* Enable a bug fix for the shorten_branches pass. */
1552 #define SHORTEN_WITH_ADJUST_INSN_LENGTH
1553 \f
1554 /* Define the codes that are matched by predicates in sh.c. */
1555 #define PREDICATE_CODES \
1556 {"arith_reg_operand", {SUBREG, REG}}, \
1557 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1558 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1559 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
1560 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1561 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
1562
1563 /* Define this macro if it is advisable to hold scalars in registers
1564 in a wider mode than that declared by the program. In such cases,
1565 the value is constrained to be within the bounds of the declared
1566 type, but kept valid in the wider mode. The signedness of the
1567 extension may differ from that of the type.
1568
1569 Leaving the unsignedp unchanged gives better code than always setting it
1570 to 0. This is despite the fact that we have only signed char and short
1571 load instructions. */
1572 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1573 if (GET_MODE_CLASS (MODE) == MODE_INT \
1574 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1575 MODE = SImode;
1576
1577 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
1578 extensions applied to char/short functions arguments. Defining
1579 PROMOTE_FUNCTION_RETURN does the same for function returns. */
1580
1581 #define PROMOTE_FUNCTION_ARGS
1582 #define PROMOTE_FUNCTION_RETURN
1583
1584 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
1585 and poping arguments. However, we do have push/pop instructions, and
1586 rather limited offsets (4 bits) in load/store instructions, so it isn't
1587 clear if this would give better code. If implemented, should check for
1588 compatibility problems. */
1589
1590 /* ??? Define ADJUST_COSTS? */
1591
1592 /* For the sake of libgcc2.c, indicate target supports atexit. */
1593 #define HAVE_ATEXIT