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[gcc.git] / gcc / config / sh / sh.h
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_SH_H
23 #define GCC_SH_H
24
25 #include "config/vxworks-dummy.h"
26
27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
28 include it here, because bconfig.h is also included by gencodes.c . */
29 /* ??? No longer true. */
30 extern int code_for_indirect_jump_scratch;
31
32 #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
33
34 /* Value should be nonzero if functions must have frame pointers.
35 Zero means the frame pointer need not be set up (and parms may be accessed
36 via the stack pointer) in functions that seem suitable. */
37
38 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
39 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
40 #endif
41
42 \f
43 /* Nonzero if this is an ELF target - compile time only */
44 #define TARGET_ELF 0
45
46 /* Nonzero if we should generate code using type 2E insns. */
47 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
48
49 /* Nonzero if we should generate code using type 2A insns. */
50 #define TARGET_SH2A TARGET_HARD_SH2A
51 /* Nonzero if we should generate code using type 2A SF insns. */
52 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
53 /* Nonzero if we should generate code using type 2A DF insns. */
54 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
55
56 /* Nonzero if we should generate code using type 3E insns. */
57 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
58
59 /* Nonzero if we schedule for a superscalar implementation. */
60 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A)
61
62 /* Nonzero if a double-precision FPU is available. */
63 #define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE)
64
65 /* Nonzero if an FPU is available. */
66 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
67
68 /* Nonzero if we're generating code for SH4a, unless the use of the
69 FPU is disabled (which makes it compatible with SH4al-dsp). */
70 #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY)
71
72
73 /* This is not used by the SH2E calling convention */
74 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
75 (! TARGET_SH2E \
76 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
77
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT SELECT_SH1
80 #define SUPPORT_SH1 1
81 #define SUPPORT_SH2E 1
82 #define SUPPORT_SH4 1
83 #define SUPPORT_SH4_SINGLE 1
84 #define SUPPORT_SH2A 1
85 #define SUPPORT_SH2A_SINGLE 1
86 #endif
87
88 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
89 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
90 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
91
92 #define SELECT_SH1 (MASK_SH1)
93 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
94 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
95 | MASK_FPU_SINGLE)
96 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
97 | MASK_HARD_SH2A_DOUBLE \
98 | MASK_SH2 | MASK_SH1)
99 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
100 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
101 | MASK_SH1 | MASK_FPU_SINGLE \
102 | MASK_FPU_SINGLE_ONLY)
103 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
104 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
105 | MASK_SH2 | MASK_SH1)
106 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
107 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
108 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
109 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \
110 | MASK_FPU_SINGLE_ONLY)
111 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
112 | SELECT_SH3)
113 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
114 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
115 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
116 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
117 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
118
119 #if SUPPORT_SH1
120 #define SUPPORT_SH2 1
121 #endif
122 #if SUPPORT_SH2
123 #define SUPPORT_SH3 1
124 #define SUPPORT_SH2A_NOFPU 1
125 #endif
126 #if SUPPORT_SH3
127 #define SUPPORT_SH4_NOFPU 1
128 #endif
129 #if SUPPORT_SH4_NOFPU
130 #define SUPPORT_SH4A_NOFPU 1
131 #define SUPPORT_SH4AL 1
132 #endif
133
134 #if SUPPORT_SH2E
135 #define SUPPORT_SH3E 1
136 #define SUPPORT_SH2A_SINGLE_ONLY 1
137 #endif
138 #if SUPPORT_SH3E
139 #define SUPPORT_SH4_SINGLE_ONLY 1
140 #endif
141 #if SUPPORT_SH4_SINGLE_ONLY
142 #define SUPPORT_SH4A_SINGLE_ONLY 1
143 #endif
144
145 #if SUPPORT_SH4
146 #define SUPPORT_SH4A 1
147 #endif
148
149 #if SUPPORT_SH4_SINGLE
150 #define SUPPORT_SH4A_SINGLE 1
151 #endif
152
153 /* Reset all target-selection flags. */
154 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
155 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
156 | MASK_HARD_SH4 | MASK_FPU_SINGLE \
157 | MASK_FPU_SINGLE_ONLY)
158
159 /* This defaults us to big-endian. */
160 #ifndef TARGET_ENDIAN_DEFAULT
161 #define TARGET_ENDIAN_DEFAULT 0
162 #endif
163
164 #ifndef TARGET_OPT_DEFAULT
165 #define TARGET_OPT_DEFAULT 0
166 #endif
167
168 #define TARGET_DEFAULT \
169 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
170
171 #ifndef SH_MULTILIB_CPU_DEFAULT
172 #define SH_MULTILIB_CPU_DEFAULT "m1"
173 #endif
174
175 #if TARGET_ENDIAN_DEFAULT
176 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
177 #else
178 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
179 #endif
180
181 #define CPP_SPEC " %(subtarget_cpp_spec) "
182
183 #ifndef SUBTARGET_CPP_SPEC
184 #define SUBTARGET_CPP_SPEC ""
185 #endif
186
187 #ifndef SUBTARGET_EXTRA_SPECS
188 #define SUBTARGET_EXTRA_SPECS
189 #endif
190
191 #define EXTRA_SPECS \
192 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
193 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
194 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
195 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
196 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
197 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
198 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
199 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
200 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
201 SUBTARGET_EXTRA_SPECS
202
203 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
204 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:-isa=sh4-up}}}"
205 #else
206 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
207 #endif
208
209 /* Define which ISA type to pass to the assembler.
210 For SH4 we pass SH4A to allow using some instructions that are available
211 on some SH4 variants, but officially are part of the SH4A ISA. */
212 #define SH_ASM_SPEC \
213 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \
214 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
215 %{m1:--isa=sh} \
216 %{m2:--isa=sh2} \
217 %{m2e:--isa=sh2e} \
218 %{m3:--isa=sh3} \
219 %{m3e:--isa=sh3e} \
220 %{m4:--isa=sh4a} \
221 %{m4-single:--isa=sh4a} \
222 %{m4-single-only:--isa=sh4a} \
223 %{m4-nofpu:--isa=sh4a-nofpu} \
224 %{m4a:--isa=sh4a} \
225 %{m4a-single:--isa=sh4a} \
226 %{m4a-single-only:--isa=sh4a} \
227 %{m4a-nofpu:--isa=sh4a-nofpu} \
228 %{m2a:--isa=sh2a} \
229 %{m2a-single:--isa=sh2a} \
230 %{m2a-single-only:--isa=sh2a} \
231 %{m2a-nofpu:--isa=sh2a-nofpu} \
232 %{m4al:-dsp}"
233
234 #define ASM_SPEC SH_ASM_SPEC
235
236 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
237 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
238 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
239 #else
240 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
241 #endif
242 #endif
243
244 #if STRICT_NOFPU == 1
245 /* Strict nofpu means that the compiler should tell the assembler
246 to reject FPU instructions. E.g. from ASM inserts. */
247 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
248 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}"
249 #else
250
251 #define SUBTARGET_ASM_ISA_SPEC \
252 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
253 #endif
254 #else /* ! STRICT_NOFPU */
255 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
256 #endif
257
258 #ifndef SUBTARGET_ASM_SPEC
259 #define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}"
260 #endif
261
262 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
263 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
264 #else
265 #define LINK_EMUL_PREFIX "sh%{ml:l}"
266 #endif
267
268 #define LINK_DEFAULT_CPU_EMUL ""
269 #define ASM_ISA_DEFAULT_SPEC ""
270
271 #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}"
272 #define SUBTARGET_LINK_SPEC ""
273
274 /* Go via SH_LINK_SPEC to avoid code replication. */
275 #define LINK_SPEC SH_LINK_SPEC
276
277 #define SH_LINK_SPEC "\
278 -m %(link_emul_prefix)\
279 %{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\
280 %(subtarget_link_emul_suffix) \
281 %{mrelax:-relax} %(subtarget_link_spec)"
282
283 #ifndef SH_DIV_STR_FOR_SIZE
284 #define SH_DIV_STR_FOR_SIZE "call"
285 #endif
286
287 /* SH2A does not support little-endian. Catch such combinations
288 taking into account the default configuration. */
289 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
290 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
291 #else
292 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
293 #endif
294
295 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
296 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
297 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}"
298 #else
299 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
300 "%{m2a*:%eSH2a does not support little-endian}}"
301 #endif
302
303 #ifdef FDPIC_DEFAULT
304 #define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}"
305 #else
306 #define FDPIC_SELF_SPECS
307 #endif
308
309 #undef DRIVER_SELF_SPECS
310 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \
311 FDPIC_SELF_SPECS
312
313 #undef SUBTARGET_DRIVER_SELF_SPECS
314 #define SUBTARGET_DRIVER_SELF_SPECS
315
316 #define ASSEMBLER_DIALECT assembler_dialect
317
318 extern int assembler_dialect;
319
320 enum sh_divide_strategy_e {
321 /* SH1 .. SH4 strategies. Because of the small number of registers
322 available, the compiler uses knowledge of the actual set of registers
323 being clobbered by the different functions called. */
324 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
325 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
326 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
327 SH_DIV_INTRINSIC
328 };
329
330 extern enum sh_divide_strategy_e sh_div_strategy;
331
332 #ifndef SH_DIV_STRATEGY_DEFAULT
333 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1
334 #endif
335
336 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
337
338 \f
339 /* Target machine storage layout. */
340
341 #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN)
342
343 #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0)
344 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1)
345
346 /* Define this if most significant bit is lowest numbered
347 in instructions that operate on numbered bit-fields. */
348 #define BITS_BIG_ENDIAN 0
349
350 /* Define this if most significant byte of a word is the lowest numbered. */
351 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN
352
353 /* Define this if most significant word of a multiword number is the lowest
354 numbered. */
355 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN
356
357 #define MAX_BITS_PER_WORD 64
358
359 /* Width in bits of an `int'. We want just 32-bits, even if words are
360 longer. */
361 #define INT_TYPE_SIZE 32
362
363 /* Width in bits of a `long'. */
364 #define LONG_TYPE_SIZE (32)
365
366 /* Width in bits of a `long long'. */
367 #define LONG_LONG_TYPE_SIZE 64
368
369 /* Width in bits of a `long double'. */
370 #define LONG_DOUBLE_TYPE_SIZE 64
371
372 /* Width of a word, in units (bytes). */
373 #define UNITS_PER_WORD (4)
374 #define MIN_UNITS_PER_WORD 4
375
376 /* Scaling factor for Dwarf data offsets for CFI information.
377 The dwarf2out.c default would use -UNITS_PER_WORD. */
378 #define DWARF_CIE_DATA_ALIGNMENT -4
379
380 /* Width in bits of a pointer.
381 See also the macro `Pmode' defined below. */
382 #define POINTER_SIZE (32)
383
384 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
385 #define PARM_BOUNDARY (32)
386
387 /* Boundary (in *bits*) on which stack pointer should be aligned. */
388 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
389
390 /* The log (base 2) of the cache line size, in bytes. Processors prior to
391 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
392 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
393 #define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2)
394
395 /* ABI given & required minimum allocation boundary (in *bits*) for the
396 code of a function. */
397 #define FUNCTION_BOUNDARY (16)
398
399 /* Alignment of field after `int : 0' in a structure. */
400 #define EMPTY_FIELD_BOUNDARY 32
401
402 /* No data type wants to be aligned rounder than this. */
403 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
404
405 /* The best alignment to use in cases where we have a choice. */
406 #define FASTEST_ALIGNMENT (32)
407
408 /* Make strings word-aligned so strcpy from constants will be faster. */
409 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
410 ((TREE_CODE (EXP) == STRING_CST \
411 && (ALIGN) < FASTEST_ALIGNMENT) \
412 ? FASTEST_ALIGNMENT : (ALIGN))
413
414 /* get_mode_alignment assumes complex values are always held in multiple
415 registers, but that is not the case on the SH; CQImode and CHImode are
416 held in a single integer register. */
417 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
418 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
419 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
420 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
421 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
422
423 /* Make arrays of chars word-aligned for the same reasons. */
424 #define DATA_ALIGNMENT(TYPE, ALIGN) \
425 (TREE_CODE (TYPE) == ARRAY_TYPE \
426 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
427 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
428
429 /* Number of bits which any structure or union's size must be a
430 multiple of. Each structure or union's size is rounded up to a
431 multiple of this. */
432 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
433
434 /* Set this nonzero if move instructions will actually fail to work
435 when given unaligned data. */
436 #define STRICT_ALIGNMENT 1
437
438 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
439 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
440 barrier_align (LABEL_AFTER_BARRIER)
441
442 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL)
443
444 #define LABEL_ALIGN(A_LABEL) \
445 ( \
446 (PREV_INSN (A_LABEL) \
447 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
448 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
449 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
450 /* explicit alignment insn in constant tables. */ \
451 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
452 : 0)
453
454 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
455 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
456
457 /* The base two logarithm of the known minimum alignment of an insn length. */
458 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
459 (NONJUMP_INSN_P (A_INSN) \
460 ? 1 \
461 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
462 ? 1 \
463 : CACHE_LOG)
464 \f
465 /* Standard register usage. */
466
467 /* Register allocation for the Renesas calling convention:
468
469 r0 arg return
470 r1..r3 scratch
471 r4..r7 args in
472 r8..r13 call saved
473 r14 frame pointer/call saved
474 r15 stack pointer
475 ap arg pointer (doesn't really exist, always eliminated)
476 pr subroutine return address
477 t t bit
478 mach multiply/accumulate result, high part
479 macl multiply/accumulate result, low part.
480 fpul fp/int communication register
481 rap return address pointer register
482 fr0 fp arg return
483 fr1..fr3 scratch floating point registers
484 fr4..fr11 fp args in
485 fr12..fr15 call saved floating point registers */
486
487 #define MAX_REGISTER_NAME_LENGTH 6
488 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
489
490 #define SH_REGISTER_NAMES_INITIALIZER \
491 { \
492 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
493 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
494 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
495 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
496 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
497 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
498 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
499 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
500 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
501 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
502 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
503 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
504 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
505 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
506 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
507 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
508 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
509 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
510 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
511 "rap", "sfp", "fpscr0", "fpscr1" \
512 }
513
514 #define REGNAMES_ARR_INDEX_1(index) \
515 (sh_register_names[index])
516 #define REGNAMES_ARR_INDEX_2(index) \
517 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
518 #define REGNAMES_ARR_INDEX_4(index) \
519 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
520 #define REGNAMES_ARR_INDEX_8(index) \
521 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
522 #define REGNAMES_ARR_INDEX_16(index) \
523 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
524 #define REGNAMES_ARR_INDEX_32(index) \
525 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
526 #define REGNAMES_ARR_INDEX_64(index) \
527 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
528
529 #define REGISTER_NAMES \
530 { \
531 REGNAMES_ARR_INDEX_64 (0), \
532 REGNAMES_ARR_INDEX_64 (64), \
533 REGNAMES_ARR_INDEX_8 (128), \
534 REGNAMES_ARR_INDEX_8 (136), \
535 REGNAMES_ARR_INDEX_8 (144), \
536 REGNAMES_ARR_INDEX_4 (152) \
537 }
538
539 #define ADDREGNAMES_SIZE 32
540 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
541 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
542 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
543
544 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
545 { \
546 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
547 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
548 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
549 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
550 }
551
552 #define ADDREGNAMES_REGNO(index) \
553 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
554 : (-1))
555
556 #define ADDREGNAMES_ARR_INDEX_1(index) \
557 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
558 #define ADDREGNAMES_ARR_INDEX_2(index) \
559 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
560 #define ADDREGNAMES_ARR_INDEX_4(index) \
561 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
562 #define ADDREGNAMES_ARR_INDEX_8(index) \
563 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
564 #define ADDREGNAMES_ARR_INDEX_16(index) \
565 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
566 #define ADDREGNAMES_ARR_INDEX_32(index) \
567 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
568
569 #define ADDITIONAL_REGISTER_NAMES \
570 { \
571 ADDREGNAMES_ARR_INDEX_32 (0) \
572 }
573
574 /* Number of actual hardware registers.
575 The hardware registers are assigned numbers for the compiler
576 from 0 to just below FIRST_PSEUDO_REGISTER.
577 All registers that the compiler knows about must be given numbers,
578 even those that are not normally considered general registers. */
579
580 /* There are many other relevant definitions in sh.md's md_constants. */
581
582 #define FIRST_GENERAL_REG R0_REG
583 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15))
584 #define FIRST_FP_REG DR0_REG
585 #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1))
586 #define FIRST_XD_REG XD0_REG
587 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
588
589 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
590 #define FIRST_BANKED_REG R0_REG
591 #define LAST_BANKED_REG R7_REG
592
593 #define BANKED_REGISTER_P(REGNO) \
594 IN_RANGE ((REGNO), \
595 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
596 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
597
598 #define GENERAL_REGISTER_P(REGNO) \
599 IN_RANGE ((REGNO), \
600 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
601 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
602
603 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
604 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
605 || ((REGNO) == FRAME_POINTER_REGNUM))
606
607 #define FP_REGISTER_P(REGNO) \
608 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
609
610 #define XD_REGISTER_P(REGNO) \
611 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
612
613 #define FP_OR_XD_REGISTER_P(REGNO) \
614 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
615
616 #define FP_ANY_REGISTER_P(REGNO) \
617 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
618
619 #define SPECIAL_REGISTER_P(REGNO) \
620 ((REGNO) == GBR_REG || (REGNO) == T_REG \
621 || (REGNO) == MACH_REG || (REGNO) == MACL_REG \
622 || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG)
623
624 #define VALID_REGISTER_P(REGNO) \
625 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
626 || XD_REGISTER_P (REGNO) \
627 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
628 || (REGNO) == FRAME_POINTER_REGNUM \
629 || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
630 || (TARGET_SH2E && (REGNO) == FPUL_REG))
631
632 /* The mode that should be generally used to store a register by
633 itself in the stack, or to load it back. */
634 #define REGISTER_NATURAL_MODE(REGNO) \
635 (FP_REGISTER_P (REGNO) ? SFmode : XD_REGISTER_P (REGNO) ? DFmode : SImode)
636
637
638 #define FIRST_PSEUDO_REGISTER 156
639
640 /* Don't count soft frame pointer. */
641 #define DWARF_FRAME_REGISTERS (153)
642
643 /* 1 for registers that have pervasive standard uses
644 and are not available for the register allocator.
645
646 Mach register is fixed 'cause it's only 10 bits wide for SH1.
647 It is 32 bits wide for SH2. */
648 #define FIXED_REGISTERS \
649 { \
650 /* Regular registers. */ \
651 0, 0, 0, 0, 0, 0, 0, 0, \
652 0, 0, 0, 0, 0, 0, 0, 1, \
653 /* r16 is reserved, r18 is the former pr. */ \
654 1, 0, 0, 0, 0, 0, 0, 0, \
655 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
656 /* r26 is a global variable data pointer; r27 is for constants. */ \
657 1, 1, 1, 1, 0, 0, 0, 0, \
658 0, 0, 0, 0, 0, 0, 0, 0, \
659 0, 0, 0, 0, 0, 0, 0, 0, \
660 0, 0, 0, 0, 0, 0, 0, 0, \
661 0, 0, 0, 0, 0, 0, 0, 1, \
662 /* FP registers. */ \
663 0, 0, 0, 0, 0, 0, 0, 0, \
664 0, 0, 0, 0, 0, 0, 0, 0, \
665 0, 0, 0, 0, 0, 0, 0, 0, \
666 0, 0, 0, 0, 0, 0, 0, 0, \
667 0, 0, 0, 0, 0, 0, 0, 0, \
668 0, 0, 0, 0, 0, 0, 0, 0, \
669 0, 0, 0, 0, 0, 0, 0, 0, \
670 0, 0, 0, 0, 0, 0, 0, 0, \
671 /* Branch target registers. */ \
672 0, 0, 0, 0, 0, 0, 0, 0, \
673 /* XD registers. */ \
674 0, 0, 0, 0, 0, 0, 0, 0, \
675 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
676 1, 1, 1, 1, 1, 1, 0, 1, \
677 /*"rap", "sfp","fpscr0","fpscr1" */ \
678 1, 1, 1, 1, \
679 }
680
681 /* 1 for registers not available across function calls.
682 These must include the FIXED_REGISTERS and also any
683 registers that can be used without being saved.
684 The latter must include the registers where values are returned
685 and the register where structure-value addresses are passed.
686 Aside from that, you can include as many other registers as you like. */
687 #define CALL_USED_REGISTERS \
688 { \
689 /* Regular registers. */ \
690 1, 1, 1, 1, 1, 1, 1, 1, \
691 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
692 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
693 across SH5 function calls. */ \
694 0, 0, 0, 0, 0, 0, 0, 1, \
695 1, 1, 1, 1, 1, 1, 1, 1, \
696 1, 1, 1, 1, 0, 0, 0, 0, \
697 0, 0, 0, 0, 1, 1, 1, 1, \
698 1, 1, 1, 1, 0, 0, 0, 0, \
699 0, 0, 0, 0, 0, 0, 0, 0, \
700 0, 0, 0, 0, 1, 1, 1, 1, \
701 /* FP registers. */ \
702 1, 1, 1, 1, 1, 1, 1, 1, \
703 1, 1, 1, 1, 0, 0, 0, 0, \
704 1, 1, 1, 1, 1, 1, 1, 1, \
705 1, 1, 1, 1, 1, 1, 1, 1, \
706 1, 1, 1, 1, 0, 0, 0, 0, \
707 0, 0, 0, 0, 0, 0, 0, 0, \
708 0, 0, 0, 0, 0, 0, 0, 0, \
709 0, 0, 0, 0, 0, 0, 0, 0, \
710 /* Branch target registers. */ \
711 1, 1, 1, 1, 1, 0, 0, 0, \
712 /* XD registers. */ \
713 1, 1, 1, 1, 1, 1, 0, 0, \
714 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
715 1, 1, 1, 1, 1, 1, 1, 1, \
716 /*"rap", "sfp","fpscr0","fpscr1" */ \
717 1, 1, 1, 1, \
718 }
719
720 /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then
721 overridden by -fcall-saved-* and -fcall-used-* options and then by
722 TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a
723 register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
724 #define CALL_REALLY_USED_REGISTERS \
725 { \
726 /* Regular registers. */ \
727 1, 1, 1, 1, 1, 1, 1, 1, \
728 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
729 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
730 across SH5 function calls. */ \
731 0, 0, 0, 0, 0, 0, 0, 1, \
732 1, 1, 1, 1, 1, 1, 1, 1, \
733 1, 1, 1, 1, 0, 0, 0, 0, \
734 0, 0, 0, 0, 1, 1, 1, 1, \
735 1, 1, 1, 1, 0, 0, 0, 0, \
736 0, 0, 0, 0, 0, 0, 0, 0, \
737 0, 0, 0, 0, 1, 1, 1, 1, \
738 /* FP registers. */ \
739 1, 1, 1, 1, 1, 1, 1, 1, \
740 1, 1, 1, 1, 0, 0, 0, 0, \
741 1, 1, 1, 1, 1, 1, 1, 1, \
742 1, 1, 1, 1, 1, 1, 1, 1, \
743 1, 1, 1, 1, 0, 0, 0, 0, \
744 0, 0, 0, 0, 0, 0, 0, 0, \
745 0, 0, 0, 0, 0, 0, 0, 0, \
746 0, 0, 0, 0, 0, 0, 0, 0, \
747 /* Branch target registers. */ \
748 1, 1, 1, 1, 1, 0, 0, 0, \
749 /* XD registers. */ \
750 1, 1, 1, 1, 1, 1, 0, 0, \
751 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
752 0, 1, 1, 1, 1, 1, 1, 1, \
753 /*"rap", "sfp","fpscr0","fpscr1" */ \
754 1, 1, 0, 0, \
755 }
756
757 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) (false)
758
759 /* Return number of consecutive hard regs needed starting at reg REGNO
760 to hold something of mode MODE.
761 This is ordinarily the length in words of a value of mode MODE
762 but can be less for certain modes in special long registers.
763
764 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
765 #define HARD_REGNO_NREGS(REGNO, MODE) \
766 (XD_REGISTER_P (REGNO) \
767 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
768 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
769
770 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
771 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
772 sh_hard_regno_mode_ok ((REGNO), (MODE))
773
774 /* Value is 1 if it is a good idea to tie two pseudo registers
775 when one has mode MODE1 and one has mode MODE2.
776 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
777 for any hard reg, then this must be 0 for correct output.
778 That's the case for xd registers: we don't hold SFmode values in
779 them, so we can't tie an SFmode pseudos with one in another
780 floating-point mode. */
781 #define MODES_TIEABLE_P(MODE1, MODE2) \
782 ((MODE1) == (MODE2) \
783 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
784 && (((MODE1) != SFmode && (MODE2) != SFmode))))
785
786 /* Specify the modes required to caller save a given hard regno. */
787 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
788 sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
789
790 /* A C expression that is nonzero if hard register NEW_REG can be
791 considered for use as a rename register for OLD_REG register */
792 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
793 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
794
795 /* Specify the registers used for certain standard purposes.
796 The values of these macros are register numbers. */
797
798 /* Define this if the program counter is overloaded on a register. */
799 /* #define PC_REGNUM 15*/
800
801 /* Register to use for pushing function arguments. */
802 #define STACK_POINTER_REGNUM SP_REG
803
804 /* Base register for access to local variables of the function. */
805 #define HARD_FRAME_POINTER_REGNUM FP_REG
806
807 /* Base register for access to local variables of the function. */
808 #define FRAME_POINTER_REGNUM 153
809
810 /* Fake register that holds the address on the stack of the
811 current function's return address. */
812 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
813
814 /* Register to hold the addressing base for position independent
815 code access to data items. */
816 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
817
818 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT
819 entries would need to handle saving and restoring it). */
820 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC
821
822 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
823
824 /* Definitions for register eliminations.
825
826 We have three registers that can be eliminated on the SH. First, the
827 frame pointer register can often be eliminated in favor of the stack
828 pointer register. Secondly, the argument pointer register can always be
829 eliminated; it is replaced with either the stack or frame pointer.
830 Third, there is the return address pointer, which can also be replaced
831 with either the stack or the frame pointer.
832
833 This is an array of structures. Each structure initializes one pair
834 of eliminable registers. The "from" register number is given first,
835 followed by "to". Eliminations of the same "from" register are listed
836 in order of preference.
837
838 If you add any registers here that are not actually hard registers,
839 and that have any alternative of elimination that doesn't always
840 apply, you need to amend calc_live_regs to exclude it, because
841 reload spills all eliminable registers where it sees an
842 can_eliminate == 0 entry, thus making them 'live' .
843 If you add any hard registers that can be eliminated in different
844 ways, you have to patch reload to spill them only when all alternatives
845 of elimination fail. */
846 #define ELIMINABLE_REGS \
847 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
848 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
849 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
850 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
851 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
852 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
853 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
854
855 /* Define the offset between two registers, one to be eliminated, and the other
856 its replacement, at the start of a routine. */
857 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
858 OFFSET = initial_elimination_offset ((FROM), (TO))
859
860 /* Base register for access to arguments of the function. */
861 #define ARG_POINTER_REGNUM AP_REG
862
863 /* Register in which the static-chain is passed to a function. */
864 #define STATIC_CHAIN_REGNUM (3)
865
866 /* Don't default to pcc-struct-return, because we have already specified
867 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
868 target hook. */
869 #define DEFAULT_PCC_STRUCT_RETURN 0
870
871 \f
872 /* Define the classes of registers for register constraints in the
873 machine description. Also define ranges of constants.
874
875 One of the classes must always be named ALL_REGS and include all hard regs.
876 If there is more than one class, another class must be named NO_REGS
877 and contain no registers.
878
879 The name GENERAL_REGS must be the name of a class (or an alias for
880 another name such as ALL_REGS). This is the class of registers
881 that is allowed by "g" or "r" in a register constraint.
882 Also, registers outside this class are allocated only when
883 instructions express preferences for them.
884
885 The classes must be numbered in nondecreasing order; that is,
886 a larger-numbered class must never be contained completely
887 in a smaller-numbered class.
888
889 For any two classes, it is very desirable that there be another
890 class that represents their union.
891
892 The SH has two sorts of general registers, R0 and the rest. R0 can
893 be used as the destination of some of the arithmetic ops. There are
894 also some special purpose registers; the T bit register, the
895 Procedure Return Register and the Multiply Accumulate Registers.
896
897 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
898 reg_class_subunion. We don't want to have an actual union class
899 of these, because it would only be used when both classes are calculated
900 to give the same cost, but there is only one FPUL register.
901 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
902 applying to the actual instruction alternative considered. E.g., the
903 y/r alternative of movsi_ie is considered to have no more cost that
904 the r/r alternative, which is patently untrue. */
905 enum reg_class
906 {
907 NO_REGS,
908 R0_REGS,
909 PR_REGS,
910 T_REGS,
911 MAC_REGS,
912 FPUL_REGS,
913 SIBCALL_REGS,
914 NON_SP_REGS,
915 GENERAL_REGS,
916 FP0_REGS,
917 FP_REGS,
918 DF_REGS,
919 FPSCR_REGS,
920 GENERAL_FP_REGS,
921 GENERAL_DF_REGS,
922 TARGET_REGS,
923 ALL_REGS,
924 LIM_REG_CLASSES
925 };
926
927 #define N_REG_CLASSES (int) LIM_REG_CLASSES
928
929 /* Give names of register classes as strings for dump file. */
930 #define REG_CLASS_NAMES \
931 { \
932 "NO_REGS", \
933 "R0_REGS", \
934 "PR_REGS", \
935 "T_REGS", \
936 "MAC_REGS", \
937 "FPUL_REGS", \
938 "SIBCALL_REGS", \
939 "NON_SP_REGS", \
940 "GENERAL_REGS", \
941 "FP0_REGS", \
942 "FP_REGS", \
943 "DF_REGS", \
944 "FPSCR_REGS", \
945 "GENERAL_FP_REGS", \
946 "GENERAL_DF_REGS", \
947 "TARGET_REGS", \
948 "ALL_REGS", \
949 }
950
951 /* Define which registers fit in which classes.
952 This is an initializer for a vector of HARD_REG_SET
953 of length N_REG_CLASSES. */
954 #define REG_CLASS_CONTENTS \
955 { \
956 /* NO_REGS: */ \
957 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
958 /* R0_REGS: */ \
959 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
960 /* PR_REGS: */ \
961 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
962 /* T_REGS: */ \
963 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
964 /* MAC_REGS: */ \
965 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
966 /* FPUL_REGS: */ \
967 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
968 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
969 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
970 /* NON_SP_REGS: */ \
971 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
972 /* GENERAL_REGS: */ \
973 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
974 /* FP0_REGS: */ \
975 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
976 /* FP_REGS: */ \
977 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
978 /* DF_REGS: */ \
979 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
980 /* FPSCR_REGS: */ \
981 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
982 /* GENERAL_FP_REGS: */ \
983 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
984 /* GENERAL_DF_REGS: */ \
985 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
986 /* TARGET_REGS: */ \
987 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
988 /* ALL_REGS: */ \
989 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \
990 }
991
992 /* The same information, inverted:
993 Return the class number of the smallest class containing
994 reg number REGNO. This could be a conditional expression
995 or could index an array. */
996 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
997 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
998
999 /* When this hook returns true for MODE, the compiler allows
1000 registers explicitly used in the rtl to be used as spill registers
1001 but prevents the compiler from extending the lifetime of these
1002 registers. */
1003 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1004 sh_small_register_classes_for_mode_p
1005
1006 /* The order in which register should be allocated. */
1007 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1008 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1009 spilled or used otherwise, we better have the FP_REGS allocated first. */
1010 #define REG_ALLOC_ORDER \
1011 {/* Caller-saved FPRs */ \
1012 65, 66, 67, 68, 69, 70, 71, 64, \
1013 72, 73, 74, 75, 80, 81, 82, 83, \
1014 84, 85, 86, 87, 88, 89, 90, 91, \
1015 92, 93, 94, 95, 96, 97, 98, 99, \
1016 /* Callee-saved FPRs */ \
1017 76, 77, 78, 79,100,101,102,103, \
1018 104,105,106,107,108,109,110,111, \
1019 112,113,114,115,116,117,118,119, \
1020 120,121,122,123,124,125,126,127, \
1021 136,137,138,139,140,141,142,143, \
1022 /* FPSCR */ 151, \
1023 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1024 1, 2, 3, 7, 6, 5, 4, 0, \
1025 8, 9, 17, 19, 20, 21, 22, 23, \
1026 36, 37, 38, 39, 40, 41, 42, 43, \
1027 60, 61, 62, \
1028 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1029 10, 11, 12, 13, 14, 18, \
1030 /* SH5 callee-saved GPRs */ \
1031 28, 29, 30, 31, 32, 33, 34, 35, \
1032 44, 45, 46, 47, 48, 49, 50, 51, \
1033 52, 53, 54, 55, 56, 57, 58, 59, \
1034 /* FPUL */ 150, \
1035 /* Fixed registers */ \
1036 15, 16, 24, 25, 26, 27, 63,144, \
1037 145,146,147,148,149,152,153,154,155 }
1038
1039 /* The class value for index registers, and the one for base regs. */
1040 #define INDEX_REG_CLASS R0_REGS
1041 #define BASE_REG_CLASS GENERAL_REGS
1042 \f
1043 /* Defines for sh.md and constraints.md. */
1044
1045 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1046 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1047
1048 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1049 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1050
1051 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1052 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1053
1054 /* Return the maximum number of consecutive registers
1055 needed to represent mode MODE in a register of class CLASS.
1056
1057 If TARGET_SHMEDIA, we need two FP registers per word.
1058 Otherwise we will need at most one register per word. */
1059 #define CLASS_MAX_NREGS(CLASS, MODE) \
1060 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1061
1062 /* If defined, gives a class of registers that cannot be used as the
1063 operand of a SUBREG that changes the mode of the object illegally.
1064 ??? We need to renumber the internal numbers for the frnn registers
1065 when in little endian in order to allow mode size changes. */
1066 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1067 sh_cannot_change_mode_class (FROM, TO, CLASS)
1068 \f
1069 /* Stack layout; function entry, exit and calling. */
1070
1071 /* Define the number of registers that can hold parameters.
1072 These macros are used only in other macro definitions below. */
1073 #define NPARM_REGS(MODE) \
1074 (TARGET_FPU_ANY && (MODE) == SFmode \
1075 ? 8 \
1076 : TARGET_FPU_DOUBLE \
1077 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1078 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1079 ? 8 \
1080 : 4)
1081
1082 #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
1083 #define FIRST_RET_REG (FIRST_GENERAL_REG + 0)
1084
1085 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
1086 #define FIRST_FP_RET_REG FIRST_FP_REG
1087
1088 /* Define this if pushing a word on the stack
1089 makes the stack pointer a smaller address. */
1090 #define STACK_GROWS_DOWNWARD 1
1091
1092 /* Define this macro to nonzero if the addresses of local variable slots
1093 are at negative offsets from the frame pointer. */
1094 #define FRAME_GROWS_DOWNWARD 1
1095
1096 /* Offset from the frame pointer to the first local variable slot to
1097 be allocated. */
1098 #define STARTING_FRAME_OFFSET 0
1099
1100 /* If we generate an insn to push BYTES bytes,
1101 this says how many the stack pointer really advances by. */
1102 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1103 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1104 do correct alignment. */
1105 #if 0
1106 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1107 #endif
1108
1109 /* Offset of first parameter from the argument pointer register value. */
1110 #define FIRST_PARM_OFFSET(FNDECL) 0
1111
1112 /* Value is the number of bytes of arguments automatically popped when
1113 calling a subroutine.
1114 CUM is the accumulated argument list. */
1115 #define CALL_POPS_ARGS(CUM) (0)
1116
1117 /* Some subroutine macros specific to this machine. */
1118
1119 #define BASE_RETURN_VALUE_REG(MODE) \
1120 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1121 ? FIRST_FP_RET_REG \
1122 : TARGET_FPU_ANY && (MODE) == SCmode \
1123 ? FIRST_FP_RET_REG \
1124 : (TARGET_FPU_DOUBLE \
1125 && ((MODE) == DFmode || (MODE) == SFmode \
1126 || (MODE) == DCmode || (MODE) == SCmode )) \
1127 ? FIRST_FP_RET_REG \
1128 : FIRST_RET_REG)
1129
1130 #define BASE_ARG_REG(MODE) \
1131 ((TARGET_SH2E && ((MODE) == SFmode)) \
1132 ? FIRST_FP_PARM_REG \
1133 : TARGET_FPU_DOUBLE \
1134 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1135 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1136 ? FIRST_FP_PARM_REG \
1137 : FIRST_PARM_REG)
1138
1139 /* 1 if N is a possible register number for function argument passing. */
1140 /* ??? There are some callers that pass REGNO as int, and others that pass
1141 it as unsigned. We get warnings unless we do casts everywhere. */
1142 #define FUNCTION_ARG_REGNO_P(REGNO) \
1143 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1144 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1145 || (TARGET_FPU_ANY \
1146 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1147 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1148 + NPARM_REGS (SFmode))))
1149 \f
1150 #ifdef __cplusplus
1151
1152 /* Define a data type for recording info about an argument list
1153 during the scan of that argument list. This data type should
1154 hold all necessary information about the function itself
1155 and about the args processed so far, enough to enable macros
1156 such as FUNCTION_ARG to determine where the next arg should go.
1157
1158 On SH, this is a single integer, which is a number of words
1159 of arguments scanned so far (including the invisible argument,
1160 if any, which holds the structure-value-address).
1161 Thus NARGREGS or more means all following args should go on the stack. */
1162
1163 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1164
1165 struct sh_args
1166 {
1167 /* How many SH_ARG_INT and how many SH_ARG_FLOAT args there are. */
1168 int arg_count[2];
1169
1170 bool force_mem;
1171
1172 /* Nonzero if a prototype is available for the function. */
1173 bool prototype_p;
1174
1175 /* The number of an odd floating-point register, that should be used
1176 for the next argument of type float. */
1177 int free_single_fp_reg;
1178
1179 /* Whether we're processing an outgoing function call. */
1180 bool outgoing;
1181
1182 /* This is set to nonzero when the call in question must use the Renesas ABI,
1183 even without the -mrenesas option. */
1184 bool renesas_abi;
1185 };
1186
1187 typedef sh_args CUMULATIVE_ARGS;
1188
1189 /* Set when processing a function with interrupt attribute. */
1190 extern bool current_function_interrupt;
1191
1192 #endif // __cplusplus
1193
1194 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1195 for a call to a function whose data type is FNTYPE.
1196 For a library call, FNTYPE is 0.
1197
1198 On SH, the offset always starts at 0: the first parm reg is always
1199 the same reg for a given argument class.
1200
1201 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1202 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1203 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
1204 (N_NAMED_ARGS), VOIDmode)
1205
1206 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1207 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1208
1209 /* By accident we got stuck with passing SCmode on SH4 little endian
1210 in two registers that are nominally successive - which is different from
1211 two single SFmode values, where we take endianness translation into
1212 account. That does not work at all if an odd number of registers is
1213 already in use, so that got fixed, but library functions are still more
1214 likely to use complex numbers without mixing them with SFmode arguments
1215 (which in C would have to be structures), so for the sake of ABI
1216 compatibility the way SCmode values are passed when an even number of
1217 FP registers is in use remains different from a pair of SFmode values for
1218 now.
1219 I.e.:
1220 foo (double); a: fr5,fr4
1221 foo (float a, float b); a: fr5 b: fr4
1222 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1223 this should be the other way round...
1224 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1225 #define FUNCTION_ARG_SCmode_WART 1
1226
1227 /* Minimum alignment for an argument to be passed by callee-copy
1228 reference. We need such arguments to be aligned to 8 byte
1229 boundaries, because they'll be loaded using quad loads. */
1230 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1231
1232 /* Perform any needed actions needed for a function that is receiving a
1233 variable number of arguments. */
1234
1235 /* Call the function profiler with a given profile label.
1236 We use two .aligns, so as to make sure that both the .long is aligned
1237 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1238 from the trapa instruction. */
1239 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1240 { \
1241 fprintf((STREAM), "\t.align\t2\n"); \
1242 fprintf((STREAM), "\ttrapa\t#33\n"); \
1243 fprintf((STREAM), "\t.align\t2\n"); \
1244 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1245 }
1246
1247 /* Define this macro if the code for function profiling should come
1248 before the function prologue. Normally, the profiling code comes
1249 after. */
1250 #define PROFILE_BEFORE_PROLOGUE
1251
1252 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1253 the stack pointer does not matter. The value is tested only in
1254 functions that have frame pointers.
1255 No definition is equivalent to always zero. */
1256 #define EXIT_IGNORE_STACK 1
1257
1258 /*
1259 On the SH, the trampoline looks like
1260 2 0002 D202 mov.l l2,r2
1261 1 0000 D301 mov.l l1,r3
1262 3 0004 422B jmp @r2
1263 4 0006 0009 nop
1264 5 0008 00000000 l1: .long area
1265 6 000c 00000000 l2: .long function */
1266
1267 /* Length in units of the trampoline for entering a nested function. */
1268 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16)
1269
1270 /* Alignment required for a trampoline in bits. */
1271 #define TRAMPOLINE_ALIGNMENT \
1272 ((CACHE_LOG < 3 \
1273 || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \
1274 : 64)
1275
1276 /* A C expression whose value is RTL representing the value of the return
1277 address for the frame COUNT steps up from the current frame.
1278 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1279 can ignore COUNT. */
1280 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1281 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
1282
1283 /* A C expression whose value is RTL representing the location of the
1284 incoming return address at the beginning of any function, before the
1285 prologue. This RTL is either a REG, indicating that the return
1286 value is saved in REG, or a MEM representing a location in
1287 the stack. */
1288 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG)
1289 \f
1290 /* Addressing modes, and classification of registers for them. */
1291 #define HAVE_POST_INCREMENT TARGET_SH1
1292 #define HAVE_PRE_DECREMENT TARGET_SH1
1293
1294 #define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1
1295 #define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A
1296 #define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A
1297 #define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1
1298
1299 /* If a memory clear move would take CLEAR_RATIO or more simple
1300 move-instruction pairs, we will do a setmem instead. */
1301
1302 #define CLEAR_RATIO(speed) ((speed) ? 15 : 3)
1303
1304 /* Macros to check register numbers against specific register classes. */
1305
1306 /* These assume that REGNO is a hard or pseudo reg number.
1307 They give nonzero only if REGNO is a hard reg of the suitable class
1308 or a pseudo reg currently allocated to a suitable hard reg.
1309 Since they use reg_renumber, they are safe only once reg_renumber
1310 has been allocated, which happens in reginfo.c during register
1311 allocation. */
1312 #define REGNO_OK_FOR_BASE_P(REGNO) \
1313 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1314 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1315 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1316 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1317
1318 /* True if SYMBOL + OFFSET constants must refer to something within
1319 SYMBOL's section. */
1320 #define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC
1321
1322 /* Maximum number of registers that can appear in a valid memory
1323 address. */
1324 #define MAX_REGS_PER_ADDRESS 2
1325
1326 /* Recognize any constant value that is a valid address. */
1327 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1328
1329 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1330 and check its validity for a certain class.
1331 The suitable hard regs are always accepted and all pseudo regs
1332 are also accepted if STRICT is not set. */
1333
1334 /* Nonzero if X is a reg that can be used as a base reg. */
1335 #define REG_OK_FOR_BASE_P(X, STRICT) \
1336 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1337 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1338
1339 /* Nonzero if X is a reg that can be used as an index. */
1340 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1341 ((REGNO (X) == R0_REG) \
1342 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1343
1344 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1345 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1346 ((REGNO (X) == R0_REG && OFFSET == 0) \
1347 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1348
1349 /* Macros for extra constraints. */
1350
1351 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1352 ((GET_CODE ((OP)) == LABEL_REF) \
1353 || (GET_CODE ((OP)) == CONST \
1354 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1355 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1356 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1357
1358 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1359 (CONSTANT_P (OP) \
1360 && !CONST_INT_P (OP) \
1361 && GET_CODE (OP) != CONST_DOUBLE \
1362 && (!flag_pic \
1363 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1364 && !PIC_ADDR_P (OP) \
1365 && GET_CODE (OP) != LABEL_REF)))
1366
1367 #define GOT_ENTRY_P(OP) \
1368 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1369 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1370
1371 #define GOTPLT_ENTRY_P(OP) \
1372 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1373 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1374
1375 #define UNSPEC_GOTOFF_P(OP) \
1376 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1377
1378 #define GOTOFF_P(OP) \
1379 (GET_CODE (OP) == CONST \
1380 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1381 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1382 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1383 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1384
1385 #define PIC_ADDR_P(OP) \
1386 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1387 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1388
1389 #define PCREL_SYMOFF_P(OP) \
1390 (GET_CODE (OP) == CONST \
1391 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1392 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1393
1394 #define NON_PIC_REFERENCE_P(OP) \
1395 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1396 || (GET_CODE (OP) == CONST \
1397 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1398 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \
1399 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1400 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1401 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \
1402 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1403
1404 #define PIC_REFERENCE_P(OP) \
1405 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1406 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1407
1408 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1409 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1410 || (GET_CODE (X) == SUBREG \
1411 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1412 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1413 && REG_P (SUBREG_REG (X)) \
1414 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1415
1416 /* Since this must be r0, which is a single register class, we must check
1417 SUBREGs more carefully, to be sure that we don't accept one that extends
1418 outside the class. */
1419 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1420 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1421 || (GET_CODE (X) == SUBREG \
1422 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1423 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1424 && REG_P (SUBREG_REG (X)) \
1425 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1426
1427 #ifdef REG_OK_STRICT
1428 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1429 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1430 #else
1431 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1432 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1433 #endif
1434
1435 \f
1436 /* A C compound statement that attempts to replace X, which is an address
1437 that needs reloading, with a valid memory address for an operand of
1438 mode MODE. WIN is a C statement label elsewhere in the code. */
1439 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1440 do { \
1441 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1442 goto WIN; \
1443 } while (0)
1444 \f
1445 /* Specify the machine mode that this machine uses
1446 for the index in the tablejump instruction. */
1447 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1448
1449 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1450 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1451 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1452 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1453 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1454 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1455 : SImode)
1456
1457 /* Define as C expression which evaluates to nonzero if the tablejump
1458 instruction expects the table to contain offsets from the address of the
1459 table.
1460 Do not define this if the table should contain absolute addresses. */
1461 #define CASE_VECTOR_PC_RELATIVE 1
1462
1463 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1464 #define FLOAT_TYPE_SIZE 32
1465
1466 /* Since the SH2e has only `float' support, it is desirable to make all
1467 floating point types equivalent to `float'. */
1468 #define DOUBLE_TYPE_SIZE (TARGET_FPU_SINGLE_ONLY ? 32 : 64)
1469
1470 /* 'char' is signed by default. */
1471 #define DEFAULT_SIGNED_CHAR 1
1472
1473 /* The type of size_t unsigned int. */
1474 #define SIZE_TYPE ("unsigned int")
1475
1476 #undef PTRDIFF_TYPE
1477 #define PTRDIFF_TYPE ("int")
1478
1479 #define WCHAR_TYPE "short unsigned int"
1480 #define WCHAR_TYPE_SIZE 16
1481
1482 #define SH_ELF_WCHAR_TYPE "long int"
1483
1484 /* Max number of bytes we can move from memory to memory
1485 in one reasonably fast instruction. */
1486 #define MOVE_MAX (4)
1487
1488 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1489 MOVE_MAX is not a compile-time constant. */
1490 #define MAX_MOVE_MAX 8
1491
1492 /* Max number of bytes we want move_by_pieces to be able to copy
1493 efficiently. */
1494 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1495
1496 /* Define if operations between registers always perform the operation
1497 on the full register even if a narrower mode is specified. */
1498 #define WORD_REGISTER_OPERATIONS 1
1499
1500 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1501 will either zero-extend or sign-extend. The value of this macro should
1502 be the code that says which one of the two operations is implicitly
1503 done, UNKNOWN if none. */
1504 #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1505
1506 /* Define if loading short immediate values into registers sign extends. */
1507 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1508
1509 /* Nonzero if access to memory by bytes is no faster than for words. */
1510 #define SLOW_BYTE_ACCESS 1
1511
1512 /* Nonzero if the target supports dynamic shift instructions
1513 like shad and shld. */
1514 #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
1515
1516 /* The cost of using the dynamic shift insns (shad, shld) are the same
1517 if they are available. If they are not available a library function will
1518 be emitted instead, which is more expensive. */
1519 #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20)
1520
1521 /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like
1522 (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1523 This is not generally true when hardware dynamic shifts (shad, shld) are
1524 used, because they check the sign bit _before_ the modulo op. The sign
1525 bit determines whether it is a left shift or a right shift:
1526 if (Y < 0)
1527 return X << (Y & 31);
1528 else
1529 return X >> (-Y) & 31);
1530
1531 The dynamic shift library routines in lib1funcs.S do not use the sign bit
1532 like the hardware dynamic shifts and truncate the shift count to 31.
1533 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count
1534 truncation in the library function call patterns, as this gives slightly
1535 more compact code. */
1536 #define SHIFT_COUNT_TRUNCATED (0)
1537
1538 /* All integers have the same format so truncation is easy. */
1539 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) (true)
1540
1541 /* Define this if addresses of constant functions
1542 shouldn't be put through pseudo regs where they can be cse'd.
1543 Desirable on machines where ordinary constants are expensive
1544 but a CALL with constant address is cheap. */
1545 /*#define NO_FUNCTION_CSE 1*/
1546
1547 /* The machine modes of pointers and functions. */
1548 #define Pmode (SImode)
1549 #define FUNCTION_MODE Pmode
1550
1551 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1552 are actually function calls with some special constraints on arguments
1553 and register usage.
1554
1555 These macros tell reorg that the references to arguments and
1556 register clobbers for insns of type sfunc do not appear to happen
1557 until after the millicode call. This allows reorg to put insns
1558 which set the argument registers into the delay slot of the millicode
1559 call -- thus they act more like traditional CALL_INSNs.
1560
1561 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1562 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1563 in particular. */
1564
1565 #define INSN_SETS_ARE_DELAYED(X) \
1566 ((NONJUMP_INSN_P (X) \
1567 && GET_CODE (PATTERN (X)) != SEQUENCE \
1568 && GET_CODE (PATTERN (X)) != USE \
1569 && GET_CODE (PATTERN (X)) != CLOBBER \
1570 && get_attr_is_sfunc (X)))
1571
1572 #define INSN_REFERENCES_ARE_DELAYED(X) \
1573 ((NONJUMP_INSN_P (X) \
1574 && GET_CODE (PATTERN (X)) != SEQUENCE \
1575 && GET_CODE (PATTERN (X)) != USE \
1576 && GET_CODE (PATTERN (X)) != CLOBBER \
1577 && get_attr_is_sfunc (X)))
1578
1579 \f
1580 /* Position Independent Code. */
1581
1582 /* We can't directly access anything that contains a symbol,
1583 nor can we indirect via the constant pool. */
1584 #define LEGITIMATE_PIC_OPERAND_P(X) \
1585 ((! nonpic_symbol_mentioned_p (X) \
1586 && (GET_CODE (X) != SYMBOL_REF \
1587 || ! CONSTANT_POOL_ADDRESS_P (X) \
1588 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))))
1589
1590 #define SYMBOLIC_CONST_P(X) \
1591 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1592 && nonpic_symbol_mentioned_p (X))
1593 \f
1594 /* Compute extra cost of moving data between one register class
1595 and another. */
1596
1597 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
1598 uses this information. Hence, the general register <-> floating point
1599 register information here is not used for SFmode. */
1600 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
1601 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
1602 || ((CLASS) == SIBCALL_REGS))
1603
1604 #define REGCLASS_HAS_FP_REG(CLASS) \
1605 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
1606 || (CLASS) == DF_REGS)
1607
1608 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1609 would be so that people with slow memory systems could generate
1610 different code that does fewer memory accesses. */
1611
1612 /* A C expression for the cost of a branch instruction. A value of 1
1613 is the default; other values are interpreted relative to that. */
1614 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
1615 \f
1616 /* Assembler output control. */
1617
1618 /* A C string constant describing how to begin a comment in the target
1619 assembler language. The compiler assumes that the comment will end at
1620 the end of the line. */
1621 #define ASM_COMMENT_START "!"
1622
1623 #define ASM_APP_ON ""
1624 #define ASM_APP_OFF ""
1625 #define FILE_ASM_OP "\t.file\n"
1626 #define SET_ASM_OP "\t.set\t"
1627
1628 /* How to change between sections. */
1629 #define TEXT_SECTION_ASM_OP "\t.text"
1630 #define DATA_SECTION_ASM_OP "\t.data"
1631
1632 #if defined CRT_BEGIN || defined CRT_END
1633 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
1634 #undef TEXT_SECTION_ASM_OP
1635 #define TEXT_SECTION_ASM_OP "\t.text"
1636 #endif
1637
1638 #ifndef BSS_SECTION_ASM_OP
1639 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1640 #endif
1641
1642 #ifndef ASM_OUTPUT_ALIGNED_BSS
1643 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1644 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1645 #endif
1646
1647 /* Define this so that jump tables go in same section as the current function,
1648 which could be text or it could be a user defined section. */
1649 #define JUMP_TABLES_IN_TEXT_SECTION 1
1650
1651 #undef DO_GLOBAL_CTORS_BODY
1652 #define DO_GLOBAL_CTORS_BODY \
1653 { \
1654 typedef void (*pfunc) (void); \
1655 extern pfunc __ctors[]; \
1656 extern pfunc __ctors_end[]; \
1657 pfunc *p; \
1658 for (p = __ctors_end; p > __ctors; ) \
1659 { \
1660 (*--p)(); \
1661 } \
1662 }
1663
1664 #undef DO_GLOBAL_DTORS_BODY
1665 #define DO_GLOBAL_DTORS_BODY \
1666 { \
1667 typedef void (*pfunc) (void); \
1668 extern pfunc __dtors[]; \
1669 extern pfunc __dtors_end[]; \
1670 pfunc *p; \
1671 for (p = __dtors; p < __dtors_end; p++) \
1672 { \
1673 (*p)(); \
1674 } \
1675 }
1676
1677 #define ASM_OUTPUT_REG_PUSH(file, v) \
1678 { \
1679 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
1680 }
1681
1682 #define ASM_OUTPUT_REG_POP(file, v) \
1683 { \
1684 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
1685 }
1686
1687 /* DBX register number for a given compiler register number. */
1688 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1689 to match gdb. */
1690 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
1691 register exists, so we should return -1 for invalid register numbers. */
1692 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
1693
1694 #define SH_DBX_REGISTER_NUMBER(REGNO) \
1695 (IN_RANGE ((REGNO), \
1696 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1697 FIRST_GENERAL_REG + 15U) \
1698 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
1699 : ((int) (REGNO) >= FIRST_FP_REG \
1700 && ((int) (REGNO) \
1701 <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \
1702 ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \
1703 : XD_REGISTER_P (REGNO) \
1704 ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \
1705 : (REGNO) == PR_REG \
1706 ? (17) \
1707 : (REGNO) == GBR_REG \
1708 ? (18) \
1709 : (REGNO) == MACH_REG \
1710 ? (20) \
1711 : (REGNO) == MACL_REG \
1712 ? (21) \
1713 : (REGNO) == T_REG \
1714 ? (22) \
1715 : (REGNO) == FPUL_REG \
1716 ? (23) \
1717 : (REGNO) == FPSCR_REG \
1718 ? (24) \
1719 : (unsigned) -1)
1720
1721 /* This is how to output a reference to a symbol_ref. On SH5,
1722 references to non-code symbols must be preceded by `datalabel'. */
1723 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
1724 do \
1725 { \
1726 assemble_name ((FILE), XSTR ((SYM), 0)); \
1727 } \
1728 while (0)
1729
1730 /* This is how to output an assembler line
1731 that says to advance the location counter
1732 to a multiple of 2**LOG bytes. */
1733
1734 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1735 if ((LOG) != 0) \
1736 fprintf ((FILE), "\t.align %d\n", (LOG))
1737
1738 /* Globalizing directive for a label. */
1739 #define GLOBAL_ASM_OP "\t.global\t"
1740
1741 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1742
1743 /* Output a relative address table. */
1744 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1745 switch (GET_MODE (BODY)) \
1746 { \
1747 case SImode: \
1748 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1749 break; \
1750 case HImode: \
1751 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1752 break; \
1753 case QImode: \
1754 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1755 break; \
1756 default: \
1757 break; \
1758 }
1759
1760 /* Output an absolute table element. */
1761 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1762 if (! optimize || TARGET_BIGTABLE) \
1763 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
1764 else \
1765 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
1766
1767 \f
1768 /* A C statement to be executed just prior to the output of
1769 assembler code for INSN, to modify the extracted operands so
1770 they will be output differently.
1771
1772 Here the argument OPVEC is the vector containing the operands
1773 extracted from INSN, and NOPERANDS is the number of elements of
1774 the vector which contain meaningful data for this insn.
1775 The contents of this vector are what will be used to convert the insn
1776 template into assembler code, so you can change the assembler output
1777 by changing the contents of the vector. */
1778 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1779 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
1780
1781 /* Which processor to schedule for. The elements of the enumeration must
1782 match exactly the cpu attribute in the sh.md file. */
1783 enum processor_type {
1784 PROCESSOR_SH1,
1785 PROCESSOR_SH2,
1786 PROCESSOR_SH2E,
1787 PROCESSOR_SH2A,
1788 PROCESSOR_SH3,
1789 PROCESSOR_SH3E,
1790 PROCESSOR_SH4,
1791 PROCESSOR_SH4A
1792 };
1793
1794 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1795 extern enum processor_type sh_cpu;
1796
1797 enum mdep_reorg_phase_e
1798 {
1799 SH_BEFORE_MDEP_REORG,
1800 SH_INSERT_USES_LABELS,
1801 SH_SHORTEN_BRANCHES0,
1802 SH_FIXUP_PCLOAD,
1803 SH_SHORTEN_BRANCHES1,
1804 SH_AFTER_MDEP_REORG
1805 };
1806
1807 extern enum mdep_reorg_phase_e mdep_reorg_phase;
1808
1809 /* Handle Renesas compiler's pragmas. */
1810 #define REGISTER_TARGET_PRAGMAS() do { \
1811 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
1812 c_register_pragma (0, "trapa", sh_pr_trapa); \
1813 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
1814 } while (0)
1815
1816 extern tree sh_deferred_function_attributes;
1817 extern tree *sh_deferred_function_attributes_tail;
1818
1819
1820 \f
1821 /* Instructions with unfilled delay slots take up an
1822 extra two bytes for the nop in the delay slot.
1823 sh-dsp parallel processing insns are four bytes long. */
1824 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1825 (LENGTH) += sh_insn_length_adjustment (X);
1826 \f
1827 /* Define this macro if it is advisable to hold scalars in registers
1828 in a wider mode than that declared by the program. In such cases,
1829 the value is constrained to be within the bounds of the declared
1830 type, but kept valid in the wider mode. The signedness of the
1831 extension may differ from that of the type.
1832
1833 Leaving the unsignedp unchanged gives better code than always setting it
1834 to 0. This is despite the fact that we have only signed char and short
1835 load instructions. */
1836 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1837 if (GET_MODE_CLASS (MODE) == MODE_INT \
1838 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
1839 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode;
1840
1841 #define MAX_FIXED_MODE_SIZE (64)
1842
1843 /* Better to allocate once the maximum space for outgoing args in the
1844 prologue rather than duplicate around each call. */
1845 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1846
1847 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
1848
1849 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE)
1850
1851 #define ACTUAL_NORMAL_MODE(ENTITY) \
1852 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
1853
1854 #define NORMAL_MODE(ENTITY) \
1855 (sh_cfun_interrupt_handler_p () \
1856 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
1857 : ACTUAL_NORMAL_MODE (ENTITY))
1858
1859 #define EPILOGUE_USES(REGNO) (TARGET_FPU_ANY && REGNO == FPSCR_REG)
1860
1861 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG))
1862
1863 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM)
1864
1865 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
1866 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
1867
1868 /* We have to distinguish between code and data, so that we apply
1869 datalabel where and only where appropriate. Use sdataN for data. */
1870 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1871 ((TARGET_FDPIC \
1872 ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \
1873 : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
1874 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \
1875 | ((CODE) ? 0 : DW_EH_PE_sdata4))
1876
1877 /* Handle special EH pointer encodings. Absolute, pc-relative, and
1878 indirect are handled automatically. */
1879 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1880 do { \
1881 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
1882 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
1883 { \
1884 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
1885 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
1886 if (0) goto DONE; \
1887 } \
1888 if (TARGET_FDPIC \
1889 && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \
1890 { \
1891 fputs ("\t.ualong ", FILE); \
1892 output_addr_const (FILE, ADDR); \
1893 if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \
1894 fputs ("@GOTFUNCDESC", FILE); \
1895 else \
1896 fputs ("@GOT", FILE); \
1897 goto DONE; \
1898 } \
1899 } while (0)
1900
1901 #if (defined CRT_BEGIN || defined CRT_END)
1902 /* SH constant pool breaks the devices in crtstuff.c to control section
1903 in where code resides. We have to write it as asm code. */
1904 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1905 asm (SECTION_OP "\n\
1906 mov.l 1f,r1\n\
1907 mova 2f,r0\n\
1908 braf r1\n\
1909 lds r0,pr\n\
1910 0: .p2align 2\n\
1911 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
1912 2:\n" TEXT_SECTION_ASM_OP);
1913 #endif /* (defined CRT_BEGIN || defined CRT_END) */
1914
1915 #endif /* ! GCC_SH_H */