1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #define TARGET_VERSION \
25 fputs (" (Hitachi SH)", stderr);
27 /* Generate SDB debugging information. */
29 #define SDB_DEBUGGING_INFO
31 /* Output DBX (stabs) debugging information if doing -gstabs. */
37 #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \
43 #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
45 #define ASM_SPEC "%{ml:-little} %{mrelax:-relax}"
47 #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
49 /* We can not debug without a frame pointer. */
50 /* #define CAN_DEBUG_WITHOUT_FP */
52 #define CONDITIONAL_REGISTER_USAGE \
56 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
57 fixed_regs[regno] = call_used_regs[regno] = 1; \
59 /* Hitachi saves and restores mac registers on call. */ \
62 call_used_regs[MACH_REG] = 0; \
63 call_used_regs[MACL_REG] = 0; \
66 /* ??? Need to write documentation for all SH options and add it to the
69 /* Run-time compilation parameters selecting different hardware subsets. */
71 extern int target_flags
;
72 #define ISIZE_BIT (1<<1)
73 #define DALIGN_BIT (1<<6)
74 #define SH0_BIT (1<<7)
75 #define SH1_BIT (1<<8)
76 #define SH2_BIT (1<<9)
77 #define SH3_BIT (1<<10)
78 #define SH3E_BIT (1<<11)
79 #define SPACE_BIT (1<<13)
80 #define BIGTABLE_BIT (1<<14)
81 #define RELAX_BIT (1<<15)
82 #define HITACHI_BIT (1<<22)
83 #define PADSTRUCT_BIT (1<<28)
84 #define LITTLE_ENDIAN_BIT (1<<29)
86 /* Nonzero if we should dump out instruction size info. */
87 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
89 /* Nonzero to align doubles on 64 bit boundaries. */
90 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
92 /* Nonzero if we should generate code using type 0 insns. */
93 /* ??? Is there such a thing as SH0? If not, we should delete all
95 #define TARGET_SH0 (target_flags & SH0_BIT)
97 /* Nonzero if we should generate code using type 1 insns. */
98 #define TARGET_SH1 (target_flags & SH1_BIT)
100 /* Nonzero if we should generate code using type 2 insns. */
101 #define TARGET_SH2 (target_flags & SH2_BIT)
103 /* Nonzero if we should generate code using type 3 insns. */
104 #define TARGET_SH3 (target_flags & SH3_BIT)
106 /* Nonzero if we should generate code using type 3E insns. */
107 #define TARGET_SH3E (target_flags & SH3E_BIT)
109 /* Nonzero if we should generate smaller code rather than faster code. */
110 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
112 /* Nonzero to use long jump tables. */
113 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
115 /* Nonzero to generate pseudo-ops needed by the assembler and linker
116 to do function call relaxing. */
117 #define TARGET_RELAX (target_flags & RELAX_BIT)
119 /* Nonzero if using Hitachi's calling convention. */
120 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
122 /* Nonzero if padding structures to a multiple of 4 bytes. This is
123 incompatible with Hitachi's compiler, and gives unusual structure layouts
124 which confuse programmers.
125 ??? This option is not useful, but is retained in case there are people
126 who are still relying on it. It may be deleted in the future. */
127 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
129 /* Nonzero if generating code for a little endian SH. */
130 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
132 #define TARGET_SWITCHES \
136 {"3", SH3_BIT|SH2_BIT}, \
137 {"3e", SH3E_BIT|SH3_BIT|SH2_BIT}, \
138 {"b", -LITTLE_ENDIAN_BIT}, \
139 {"bigtable", BIGTABLE_BIT}, \
140 {"dalign", DALIGN_BIT}, \
141 {"hitachi", HITACHI_BIT}, \
142 {"isize", ISIZE_BIT}, \
143 {"l", LITTLE_ENDIAN_BIT}, \
144 {"padstruct", PADSTRUCT_BIT}, \
145 {"relax", RELAX_BIT}, \
146 {"space", SPACE_BIT}, \
147 {"", TARGET_DEFAULT} \
150 #define TARGET_DEFAULT (0)
152 #define PRESERVE_DEATH_INFO_REGNO_P(regno) (TARGET_RELAX || optimize)
154 #define OVERRIDE_OPTIONS \
166 /* Never run scheduling before reload, since that can \
167 break global alloc, and generates slower code anyway due \
168 to the pressure on R0. */ \
169 flag_schedule_insns = 0; \
172 /* Target machine storage layout. */
174 /* Define to use software floating point emulator for REAL_ARITHMETIC and
175 decimal <-> binary conversion. */
176 #define REAL_ARITHMETIC
178 /* Define this if most significant bit is lowest numbered
179 in instructions that operate on numbered bit-fields. */
181 #define BITS_BIG_ENDIAN 0
183 /* Define this if most significant byte of a word is the lowest numbered. */
184 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
186 /* Define this if most significant word of a multiword number is the lowest
188 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
190 /* Define this to set the endianness to use in libgcc2.c, which can
191 not depend on target_flags. */
192 #if defined(__LITTLE_ENDIAN__)
193 #define LIBGCC2_WORDS_BIG_ENDIAN 0
195 #define LIBGCC2_WORDS_BIG_ENDIAN 1
198 /* Number of bits in an addressable storage unit. */
199 #define BITS_PER_UNIT 8
201 /* Width in bits of a "word", which is the contents of a machine register.
202 Note that this is not necessarily the width of data type `int';
203 if using 16-bit ints on a 68000, this would still be 32.
204 But on a machine with 16-bit registers, this would be 16. */
205 #define BITS_PER_WORD 32
206 #define MAX_BITS_PER_WORD 32
208 /* Width of a word, in units (bytes). */
209 #define UNITS_PER_WORD 4
211 /* Width in bits of a pointer.
212 See also the macro `Pmode' defined below. */
213 #define POINTER_SIZE 32
215 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
216 #define PARM_BOUNDARY 32
218 /* Boundary (in *bits*) on which stack pointer should be aligned. */
219 #define STACK_BOUNDARY 32
221 /* Allocation boundary (in *bits*) for the code of a function.
222 32 bit alignment is faster, because instructions are always fetched as a
223 pair from a longword boundary. */
224 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32)
226 /* Alignment of field after `int : 0' in a structure. */
227 #define EMPTY_FIELD_BOUNDARY 32
229 /* No data type wants to be aligned rounder than this. */
230 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
232 /* The best alignment to use in cases where we have a choice. */
233 #define FASTEST_ALIGNMENT 32
235 /* Make strings word-aligned so strcpy from constants will be faster. */
236 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
237 ((TREE_CODE (EXP) == STRING_CST \
238 && (ALIGN) < FASTEST_ALIGNMENT) \
239 ? FASTEST_ALIGNMENT : (ALIGN))
241 /* Make arrays of chars word-aligned for the same reasons. */
242 #define DATA_ALIGNMENT(TYPE, ALIGN) \
243 (TREE_CODE (TYPE) == ARRAY_TYPE \
244 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
245 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
247 /* Number of bits which any structure or union's size must be a
248 multiple of. Each structure or union's size is rounded up to a
250 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
252 /* Set this nonzero if move instructions will actually fail to work
253 when given unaligned data. */
254 #define STRICT_ALIGNMENT 1
256 /* Standard register usage. */
258 /* Register allocation for the Hitachi calling convention:
264 r14 frame pointer/call saved
266 ap arg pointer (doesn't really exist, always eliminated)
267 pr subroutine return address
269 mach multiply/accumulate result, high part
270 macl multiply/accumulate result, low part.
271 fpul fp/int communication register
272 rap return address pointer register
274 fr1..fr3 scratch floating point registers
276 fr12..fr15 call saved floating point registers */
278 /* Number of actual hardware registers.
279 The hardware registers are assigned numbers for the compiler
280 from 0 to just below FIRST_PSEUDO_REGISTER.
281 All registers that the compiler knows about must be given numbers,
282 even those that are not normally considered general registers. */
290 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
293 #define FIRST_FP_REG 24
294 #define LAST_FP_REG 39
296 #define FIRST_PSEUDO_REGISTER 40
298 /* 1 for registers that have pervasive standard uses
299 and are not available for the register allocator.
301 Mach register is fixed 'cause it's only 10 bits wide for SH1.
302 It is 32 bits wide for SH2. */
304 #define FIXED_REGISTERS \
317 /* 1 for registers not available across function calls.
318 These must include the FIXED_REGISTERS and also any
319 registers that can be used without being saved.
320 The latter must include the registers where values are returned
321 and the register where structure-value addresses are passed.
322 Aside from that, you can include as many other registers as you like. */
324 #define CALL_USED_REGISTERS \
337 /* Return number of consecutive hard regs needed starting at reg REGNO
338 to hold something of mode MODE.
339 This is ordinarily the length in words of a value of mode MODE
340 but can be less for certain modes in special long registers.
342 On the SH regs are UNITS_PER_WORD bits wide. */
344 #define HARD_REGNO_NREGS(REGNO, MODE) \
345 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
347 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
348 We can allow any mode in any general register. The special registers
349 only allow SImode. Don't allow any mode in the PR. */
351 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
352 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
353 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
354 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG ? (MODE) == SFmode \
355 : (REGNO) == PR_REG ? 0 \
358 /* Value is 1 if it is a good idea to tie two pseudo registers
359 when one has mode MODE1 and one has mode MODE2.
360 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
361 for any hard reg, then this must be 0 for correct output. */
363 #define MODES_TIEABLE_P(MODE1, MODE2) \
364 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
366 /* Specify the registers used for certain standard purposes.
367 The values of these macros are register numbers. */
369 /* Define this if the program counter is overloaded on a register. */
370 /* #define PC_REGNUM 15*/
372 /* Register to use for pushing function arguments. */
373 #define STACK_POINTER_REGNUM 15
375 /* Base register for access to local variables of the function. */
376 #define FRAME_POINTER_REGNUM 14
378 /* Fake register that holds the address on the stack of the
379 current function's return address. */
380 #define RETURN_ADDRESS_POINTER_REGNUM 23
382 /* Value should be nonzero if functions must have frame pointers.
383 Zero means the frame pointer need not be set up (and parms may be accessed
384 via the stack pointer) in functions that seem suitable. */
386 #define FRAME_POINTER_REQUIRED 0
388 /* Definitions for register eliminations.
390 We have three registers that can be eliminated on the SH. First, the
391 frame pointer register can often be eliminated in favor of the stack
392 pointer register. Secondly, the argument pointer register can always be
393 eliminated; it is replaced with either the stack or frame pointer.
394 Third, there is the retuen address pointer, which can also be replaced
395 with either the stack or the frame pointer. */
397 /* This is an array of structures. Each structure initializes one pair
398 of eliminable registers. The "from" register number is given first,
399 followed by "to". Eliminations of the same "from" register are listed
400 in order of preference. */
402 /* If you add any registers here that are not actually hard registers,
403 and that have any alternative of elimination that doesn't always
404 apply, you need to amend calc_live_regs to exclude it, because
405 reload spills all eliminable registers where it sees an
406 can_eliminate == 0 entry, thus making them 'live' .
407 If you add any hard registers that can be eliminated in different
408 ways, you have to patch reload to spill them only when all alternatives
409 of elimination fail. */
411 #define ELIMINABLE_REGS \
412 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
413 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
414 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
415 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
416 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
418 /* Given FROM and TO register numbers, say whether this elimination
420 #define CAN_ELIMINATE(FROM, TO) \
421 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
423 /* Define the offset between two registers, one to be eliminated, and the other
424 its replacement, at the start of a routine. */
426 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
427 OFFSET = initial_elimination_offset (FROM, TO)
429 /* Base register for access to arguments of the function. */
430 #define ARG_POINTER_REGNUM 16
432 /* Register in which the static-chain is passed to a function. */
433 #define STATIC_CHAIN_REGNUM 13
435 /* The register in which a struct value address is passed. */
437 #define STRUCT_VALUE_REGNUM 2
439 /* If the structure value address is not passed in a register, define
440 `STRUCT_VALUE' as an expression returning an RTX for the place
441 where the address is passed. If it returns 0, the address is
442 passed as an "invisible" first argument. */
444 /*#define STRUCT_VALUE ((rtx)0)*/
446 /* Don't default to pcc-struct-return, because we have already specified
447 exactly how to return structures in the RETURN_IN_MEMORY macro. */
449 #define DEFAULT_PCC_STRUCT_RETURN 0
451 /* Define the classes of registers for register constraints in the
452 machine description. Also define ranges of constants.
454 One of the classes must always be named ALL_REGS and include all hard regs.
455 If there is more than one class, another class must be named NO_REGS
456 and contain no registers.
458 The name GENERAL_REGS must be the name of a class (or an alias for
459 another name such as ALL_REGS). This is the class of registers
460 that is allowed by "g" or "r" in a register constraint.
461 Also, registers outside this class are allocated only when
462 instructions express preferences for them.
464 The classes must be numbered in nondecreasing order; that is,
465 a larger-numbered class must never be contained completely
466 in a smaller-numbered class.
468 For any two classes, it is very desirable that there be another
469 class that represents their union. */
471 /* The SH has two sorts of general registers, R0 and the rest. R0 can
472 be used as the destination of some of the arithmetic ops. There are
473 also some special purpose registers; the T bit register, the
474 Procedure Return Register and the Multiply Accumulate Registers. */
492 #define N_REG_CLASSES (int) LIM_REG_CLASSES
494 /* Give names of register classes as strings for dump file. */
495 #define REG_CLASS_NAMES \
510 /* Define which registers fit in which classes.
511 This is an initializer for a vector of HARD_REG_SET
512 of length N_REG_CLASSES. */
514 #define REG_CLASS_CONTENTS \
516 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
517 { 0x00000001, 0x00000000 }, /* R0_REGS */ \
518 { 0x00020000, 0x00000000 }, /* PR_REGS */ \
519 { 0x00040000, 0x00000000 }, /* T_REGS */ \
520 { 0x00300000, 0x00000000 }, /* MAC_REGS */ \
521 { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \
522 { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
523 { 0x01000000, 0x00000000 }, /* FP0_REGS */ \
524 { 0xFF000000, 0x000000FF }, /* FP_REGS */ \
525 { 0xFF81FFFF, 0x000000FF }, /* GENERAL_FP_REGS */ \
526 { 0xFFFFFFFF, 0x000000FF }, /* ALL_REGS */ \
529 /* The same information, inverted:
530 Return the class number of the smallest class containing
531 reg number REGNO. This could be a conditional expression
532 or could index an array. */
534 extern int regno_reg_class
[];
535 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
537 /* When defined, the compiler allows registers explicitly used in the
538 rtl to be used as spill registers but prevents the compiler from
539 extending the lifetime of these registers. */
541 #define SMALL_REGISTER_CLASSES 1
543 /* The order in which register should be allocated. */
544 #define REG_ALLOC_ORDER \
545 { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
546 24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, \
547 22,15,16,17,18,19,20,21,23 }
549 /* The class value for index registers, and the one for base regs. */
550 #define INDEX_REG_CLASS R0_REGS
551 #define BASE_REG_CLASS GENERAL_REGS
553 /* Get reg_class from a letter such as appears in the machine
555 extern enum reg_class reg_class_from_letter
[];
557 #define REG_CLASS_FROM_LETTER(C) \
558 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
560 /* The letters I, J, K, L and M in a register constraint string
561 can be used to stand for particular ranges of immediate operands.
562 This macro defines what the ranges are.
563 C is the letter, and VALUE is a constant value.
564 Return 1 if VALUE is in the range specified by C.
565 I: arithmetic operand -127..128, as used in add, sub, etc
566 K: shift operand 1,2,8 or 16
567 L: logical operand 0..255, as used in and, or, etc.
571 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
572 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
573 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
574 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
575 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
576 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
577 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
578 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
579 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
580 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
581 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
584 /* Similar, but for floating constants, and defining letters G and H.
585 Here VALUE is the CONST_DOUBLE rtx itself. */
587 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
588 ((C) == 'G' ? fp_zero_operand (VALUE) \
589 : (C) == 'H' ? fp_one_operand (VALUE) \
592 /* Given an rtx X being reloaded into a reg required to be
593 in class CLASS, return the class of reg to actually use.
594 In general this is just CLASS; but on some machines
595 in some cases it is preferable to use a more restrictive class. */
597 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
599 /* ??? Should make FPUL register a nn-fixed register and make it's
600 use explicit in the rtl; then change this definition here to
601 ... ? FPUL_REGS : NO_REGS) . */
602 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
603 ((((CLASS == FP_REGS || CLASS == FP0_REGS) \
604 && GET_CODE (X) == REG && REGNO (X) <= AP_REG) \
605 || (CLASS == GENERAL_REGS && GET_CODE (X) == REG \
606 && REGNO (X) <= FIRST_FP_REG && REGNO (X) >= LAST_FP_REG)) \
607 ? /* FPUL_REGS */ NO_REGS : NO_REGS)
609 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
610 (((CLASS == FP_REGS || CLASS == FP0_REGS) && immediate_operand (X, MODE)\
611 && ! (fp_one_operand (X) || fp_one_operand (X))) \
612 ? R0_REGS : SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X))
614 /* Return the maximum number of consecutive registers
615 needed to represent mode MODE in a register of class CLASS.
617 On SH this is the size of MODE in words. */
618 #define CLASS_MAX_NREGS(CLASS, MODE) \
619 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
621 /* Stack layout; function entry, exit and calling. */
623 /* Define the number of registers that can hold parameters.
624 These macros are used only in other macro definitions below. */
626 #define NPARM_REGS(MODE) \
627 ((TARGET_SH3E && ((MODE) == SFmode)) ? 8 : 4)
629 #define FIRST_PARM_REG 4
630 #define FIRST_RET_REG 0
632 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
633 #define FIRST_FP_RET_REG FIRST_FP_REG
635 /* Define this if pushing a word on the stack
636 makes the stack pointer a smaller address. */
637 #define STACK_GROWS_DOWNWARD
639 /* Define this macro if the addresses of local variable slots are at
640 negative offsets from the frame pointer.
642 The SH only has positive indexes, so grow the frame up. */
643 /* #define FRAME_GROWS_DOWNWARD */
645 /* Offset from the frame pointer to the first local variable slot to
647 #define STARTING_FRAME_OFFSET 0
649 /* If we generate an insn to push BYTES bytes,
650 this says how many the stack pointer really advances by. */
651 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
653 /* Offset of first parameter from the argument pointer register value. */
654 #define FIRST_PARM_OFFSET(FNDECL) 0
656 /* Value is the number of byte of arguments automatically
657 popped when returning from a subroutine call.
658 FUNDECL is the declaration node of the function (as a tree),
659 FUNTYPE is the data type of the function (as a tree),
660 or for a library call it is an identifier node for the subroutine name.
661 SIZE is the number of bytes of arguments passed on the stack.
663 On the SH, the caller does not pop any of its arguments that were passed
665 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
667 /* Some subroutine macros specific to this machine. */
669 #define BASE_RETURN_VALUE_REG(MODE) \
670 ((TARGET_SH3E && ((MODE) == SFmode)) \
674 #define BASE_ARG_REG(MODE) \
675 ((TARGET_SH3E && ((MODE) == SFmode)) \
676 ? FIRST_FP_PARM_REG \
679 /* Define how to find the value returned by a function.
680 VALTYPE is the data type of the value (as a tree).
681 If the precise function being called is known, FUNC is its FUNCTION_DECL;
682 otherwise, FUNC is 0. */
684 #define FUNCTION_VALUE(VALTYPE, FUNC) \
685 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
687 /* Define how to find the value returned by a library function
688 assuming the value has mode MODE. */
689 #define LIBCALL_VALUE(MODE) \
690 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE));
692 /* 1 if N is a possible register number for a function value. */
693 #define FUNCTION_VALUE_REGNO_P(REGNO) \
694 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
696 /* 1 if N is a possible register number for function argument passing. */
697 #define FUNCTION_ARG_REGNO_P(REGNO) \
698 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
700 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
702 /* Define a data type for recording info about an argument list
703 during the scan of that argument list. This data type should
704 hold all necessary information about the function itself
705 and about the args processed so far, enough to enable macros
706 such as FUNCTION_ARG to determine where the next arg should go.
708 On SH, this is a single integer, which is a number of words
709 of arguments scanned so far (including the invisible argument,
710 if any, which holds the structure-value-address).
711 Thus NARGREGS or more means all following args should go on the stack. */
713 enum sh_arg_class
{ SH_ARG_INT
= 0, SH_ARG_FLOAT
= 1 };
718 #define CUMULATIVE_ARGS struct sh_args
720 #define GET_SH_ARG_CLASS(MODE) \
721 ((TARGET_SH3E && ((MODE) == SFmode)) ? SH_ARG_FLOAT : SH_ARG_INT)
723 #define ROUND_ADVANCE(SIZE) \
724 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
726 /* Round a register number up to a proper boundary for an arg of mode
729 The SH doesn't care about double alignment, so we only
730 round doubles to even regs when asked to explicitly. */
732 #define ROUND_REG(CUM, MODE) \
733 ((TARGET_ALIGN_DOUBLE \
734 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
735 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
736 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
737 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
739 /* Initialize a variable CUM of type CUMULATIVE_ARGS
740 for a call to a function whose data type is FNTYPE.
741 For a library call, FNTYPE is 0.
743 On SH, the offset always starts at 0: the first parm reg is always
746 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
748 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
749 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
752 /* Update the data in CUM to advance over an argument
753 of mode MODE and data type TYPE.
754 (TYPE is null for libcalls where that information may not be
757 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
758 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] = \
759 (ROUND_REG ((CUM), (MODE)) \
760 + ((MODE) != BLKmode \
761 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
762 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
764 /* Return boolean indicating arg of mode MODE will be passed in a reg.
765 This macro is only used in this file. */
767 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
768 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
769 && ((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
770 && (! TARGET_SH3E || (ROUND_REG((CUM), (MODE)) + (GET_MODE_SIZE(MODE)/4) <= NPARM_REGS (MODE))))
772 /* Define where to put the arguments to a function.
773 Value is zero to push the argument on the stack,
774 or a hard register in which to store the argument.
776 MODE is the argument's machine mode.
777 TYPE is the data type of the argument (as a tree).
778 This is null for libcalls where that information may
780 CUM is a variable of type CUMULATIVE_ARGS which gives info about
781 the preceding args and about the function being called.
782 NAMED is nonzero if this argument is a named parameter
783 (otherwise it is an extra parameter matching an ellipsis).
785 On SH the first args are normally in registers
786 and the rest are pushed. Any arg that starts within the first
787 NPARM_REGS words is at least partially passed in a register unless
788 its data type forbids. */
790 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
791 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
792 && (NAMED || TARGET_SH3E)) \
793 ? gen_rtx (REG, (MODE), \
794 (BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
797 /* For an arg passed partly in registers and partly in memory,
798 this is the number of registers used.
799 For args passed entirely in registers or entirely in memory, zero.
801 We sometimes split args. */
803 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
804 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
805 && (NAMED || TARGET_SH3E) \
806 && (ROUND_REG ((CUM), (MODE)) \
808 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
809 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
810 - NPARM_REGS (MODE) > 0)) \
811 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
814 extern int current_function_anonymous_args
;
816 /* Perform any needed actions needed for a function that is receiving a
817 variable number of arguments. */
819 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
820 current_function_anonymous_args = 1;
822 /* Call the function profiler with a given profile label.
823 We use two .aligns, so as to make sure that both the .long is aligned
824 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
825 from the trapa instruction. */
827 #define FUNCTION_PROFILER(STREAM,LABELNO) \
829 fprintf(STREAM, " .align 2\n"); \
830 fprintf(STREAM, " trapa #33\n"); \
831 fprintf(STREAM, " .align 2\n"); \
832 fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
835 /* Define this macro if the code for function profiling should come
836 before the function prologue. Normally, the profiling code comes
839 #define PROFILE_BEFORE_PROLOGUE
841 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
842 the stack pointer does not matter. The value is tested only in
843 functions that have frame pointers.
844 No definition is equivalent to always zero. */
846 #define EXIT_IGNORE_STACK 1
848 /* Generate the assembly code for function exit
849 Just dump out any accumulated constant table. */
851 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
853 /* Output assembler code for a block containing the constant parts
854 of a trampoline, leaving space for the variable parts.
856 On the SH, the trampoline looks like
857 1 0000 D301 mov.l l1,r3
858 2 0002 DD02 mov.l l2,r13
861 5 0008 00000000 l1: .long function
862 6 000c 00000000 l2: .long area */
863 #define TRAMPOLINE_TEMPLATE(FILE) \
865 fprintf ((FILE), " .word 0xd301\n"); \
866 fprintf ((FILE), " .word 0xdd02\n"); \
867 fprintf ((FILE), " .word 0x4d2b\n"); \
868 fprintf ((FILE), " .word 0x200b\n"); \
869 fprintf ((FILE), " .long 0\n"); \
870 fprintf ((FILE), " .long 0\n"); \
873 /* Length in units of the trampoline for entering a nested function. */
874 #define TRAMPOLINE_SIZE 16
876 /* Alignment required for a trampoline in units. */
877 #define TRAMPOLINE_ALIGN 4
879 /* Emit RTL insns to initialize the variable parts of a trampoline.
880 FNADDR is an RTX for the address of the function's pure code.
881 CXT is an RTX for the static chain value for the function. */
883 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
885 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
887 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
891 /* A C expression whose value is RTL representing the value of the return
892 address for the frame COUNT steps up from the current frame.
893 FRAMEADDR is already the frame pointer of the COUNT frame, so we
896 #define RETURN_ADDR_RTX(COUNT, FRAME) \
898 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
901 /* Generate necessary RTL for __builtin_saveregs().
902 ARGLIST is the argument list; see expr.c. */
903 extern struct rtx_def
*sh_builtin_saveregs ();
904 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST)
906 /* Addressing modes, and classification of registers for them. */
907 #define HAVE_POST_INCREMENT 1
908 /*#define HAVE_PRE_INCREMENT 1*/
909 /*#define HAVE_POST_DECREMENT 1*/
910 #define HAVE_PRE_DECREMENT 1
912 /* Macros to check register numbers against specific register classes. */
914 /* These assume that REGNO is a hard or pseudo reg number.
915 They give nonzero only if REGNO is a hard reg of the suitable class
916 or a pseudo reg currently allocated to a suitable hard reg.
917 Since they use reg_renumber, they are safe only once reg_renumber
918 has been allocated, which happens in local-alloc.c. */
920 #define REGNO_OK_FOR_BASE_P(REGNO) \
921 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
922 #define REGNO_OK_FOR_INDEX_P(REGNO) \
923 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
925 /* Maximum number of registers that can appear in a valid memory
928 #define MAX_REGS_PER_ADDRESS 2
930 /* Recognize any constant value that is a valid address. */
932 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
934 /* Nonzero if the constant value X is a legitimate general operand. */
936 #define LEGITIMATE_CONSTANT_P(X) \
937 (GET_CODE (X) != CONST_DOUBLE \
938 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
939 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
941 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
942 and check its validity for a certain class.
943 We have two alternate definitions for each of them.
944 The usual definition accepts all pseudo regs; the other rejects
945 them unless they have been allocated suitable hard regs.
946 The symbol REG_OK_STRICT causes the latter definition to be used. */
948 #ifndef REG_OK_STRICT
950 /* Nonzero if X is a hard reg that can be used as a base reg
951 or if it is a pseudo reg. */
952 #define REG_OK_FOR_BASE_P(X) \
953 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
955 /* Nonzero if X is a hard reg that can be used as an index
956 or if it is a pseudo reg. */
957 #define REG_OK_FOR_INDEX_P(X) \
958 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
960 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
961 or if X is a pseudo reg. */
962 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
963 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
967 /* Nonzero if X is a hard reg that can be used as a base reg. */
968 #define REG_OK_FOR_BASE_P(X) \
969 REGNO_OK_FOR_BASE_P (REGNO (X))
971 /* Nonzero if X is a hard reg that can be used as an index. */
972 #define REG_OK_FOR_INDEX_P(X) \
973 REGNO_OK_FOR_INDEX_P (REGNO (X))
975 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
976 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
977 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && OFFSET == 0)
981 /* The 'Q' constraint is a pc relative load operand. */
982 #define EXTRA_CONSTRAINT_Q(OP) \
983 (GET_CODE (OP) == MEM && \
984 ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
985 || (GET_CODE (XEXP (OP, 0)) == CONST \
986 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
987 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
988 && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
990 #define EXTRA_CONSTRAINT(OP, C) \
991 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
994 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
995 that is a valid memory address for an instruction.
996 The MODE argument is the machine mode for the MEM expression
997 that wants to use this address.
999 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1001 #define MODE_DISP_OK_4(X,MODE) \
1002 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
1003 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && MODE == SFmode))
1004 #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
1006 #define BASE_REGISTER_RTX_P(X) \
1007 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1008 || (GET_CODE (X) == SUBREG \
1009 && GET_CODE (SUBREG_REG (X)) == REG \
1010 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1012 /* Since this must be r0, which is a single register class, we must check
1013 SUBREGs more carefully, to be sure that we don't accept one that extends
1014 outside the class. */
1015 #define INDEX_REGISTER_RTX_P(X) \
1016 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1017 || (GET_CODE (X) == SUBREG \
1018 && GET_CODE (SUBREG_REG (X)) == REG \
1019 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
1021 /* Jump to LABEL if X is a valid address RTX. This must also take
1022 REG_OK_STRICT into account when deciding about valid registers, but it uses
1023 the above macros so we are in luck.
1031 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
1032 into the FRx registers. We implement this by setting the maximum offset
1033 to zero when the value is SFmode. This also restricts loading of SFmode
1034 values into the integer registers, but that can't be helped. */
1036 /* The SH allows a displacement in a QI or HI amode, but only when the
1037 other operand is R0. GCC doesn't handle this very well, so we forgo
1040 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
1041 DI can be any number 0..60. */
1043 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
1045 if (GET_CODE (OP) == CONST_INT) \
1047 if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
1048 if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
1052 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1054 if (BASE_REGISTER_RTX_P (X)) \
1056 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1057 && BASE_REGISTER_RTX_P (XEXP (X, 0))) \
1059 else if (GET_CODE (X) == PLUS) \
1061 rtx xop0 = XEXP (X, 0); \
1062 rtx xop1 = XEXP (X, 1); \
1063 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1064 GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \
1065 if (GET_MODE_SIZE (MODE) <= 4) \
1067 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1069 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1075 /* Try machine-dependent ways of modifying an illegitimate address
1076 to be legitimate. If we find one, return the new, valid address.
1077 This macro is used in only one place: `memory_address' in explow.c.
1079 OLDX is the address as it was before break_out_memory_refs was called.
1080 In some cases it is useful to look at this to decide what needs to be done.
1082 MODE and WIN are passed so that this macro can use
1083 GO_IF_LEGITIMATE_ADDRESS.
1085 It is always safe for this macro to do nothing. It exists to recognize
1086 opportunities to optimize the output.
1088 For the SH, if X is almost suitable for indexing, but the offset is
1089 out of range, convert it into a normal form so that cse has a chance
1090 of reducing the number of address registers used. */
1092 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1094 if (GET_CODE (X) == PLUS \
1095 && (GET_MODE_SIZE (MODE) == 4 \
1096 || GET_MODE_SIZE (MODE) == 8) \
1097 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1098 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1099 && ! (TARGET_SH3E && MODE == SFmode)) \
1101 rtx index_rtx = XEXP (X, 1); \
1102 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1105 GO_IF_LEGITIMATE_INDEX (MODE, index_rtx, WIN); \
1106 /* On rare occasions, we might get an unaligned pointer \
1107 that is indexed in a way to give an aligned address. \
1108 Therefore, keep the lower two bits in offset_base. */ \
1109 /* Instead of offset_base 128..131 use 124..127, so that \
1110 simple add suffices. */ \
1113 offset_base = ((offset + 4) & ~60) - 4; \
1116 offset_base = offset & ~60; \
1117 /* Sometimes the normal form does not suit DImode. We \
1118 could avoid that by using smaller ranges, but that \
1119 would give less optimized code when SImode is \
1121 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1123 sum = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1124 GEN_INT (offset_base), NULL_RTX, 0, \
1127 (X) = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base)); \
1133 /* Go to LABEL if ADDR (a legitimate address expression)
1134 has an effect that depends on the machine mode it is used for. */
1135 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1137 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1141 /* Specify the machine mode that this machine uses
1142 for the index in the tablejump instruction. */
1143 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1145 /* Define this if the tablejump instruction expects the table
1146 to contain offsets from the address of the table.
1147 Do not define this if the table should contain absolute addresses. */
1148 #define CASE_VECTOR_PC_RELATIVE
1150 /* Specify the tree operation to be used to convert reals to integers. */
1151 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1153 /* This is the kind of divide that is easiest to do in the general case. */
1154 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1156 /* Since the SH3e has only `float' support, it is desirable to make all
1157 floating point types equivalent to `float'. */
1158 #define DOUBLE_TYPE_SIZE (TARGET_SH3E ? 32 : 64)
1160 /* 'char' is signed by default. */
1161 #define DEFAULT_SIGNED_CHAR 1
1163 /* The type of size_t unsigned int. */
1164 #define SIZE_TYPE "unsigned int"
1166 #define WCHAR_TYPE "short unsigned int"
1167 #define WCHAR_TYPE_SIZE 16
1169 /* Don't cse the address of the function being compiled. */
1170 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1172 /* Max number of bytes we can move from memory to memory
1173 in one reasonably fast instruction. */
1176 /* Define if operations between registers always perform the operation
1177 on the full register even if a narrower mode is specified. */
1178 #define WORD_REGISTER_OPERATIONS
1180 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1181 will either zero-extend or sign-extend. The value of this macro should
1182 be the code that says which one of the two operations is implicitly
1183 done, NIL if none. */
1184 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1186 /* Define if loading short immediate values into registers sign extends. */
1187 #define SHORT_IMMEDIATES_SIGN_EXTEND
1189 /* Define this if zero-extension is slow (more than one real instruction).
1190 On the SH, it's only one instruction. */
1191 /* #define SLOW_ZERO_EXTEND */
1193 /* Nonzero if access to memory by bytes is slow and undesirable. */
1194 #define SLOW_BYTE_ACCESS 0
1196 /* We assume that the store-condition-codes instructions store 0 for false
1197 and some other value for true. This is the value stored for true. */
1199 #define STORE_FLAG_VALUE 1
1201 /* Immediate shift counts are truncated by the output routines (or was it
1202 the assembler?). Shift counts in a register are truncated by SH. Note
1203 that the native compiler puts too large (> 32) immediate shift counts
1204 into a register and shifts by the register, letting the SH decide what
1205 to do instead of doing that itself. */
1206 /* ??? This is defined, but the library routines in lib1funcs.asm do not
1207 truncate the shift count. This may result in incorrect results for
1208 unusual cases. Truncating the shift counts in the library routines would
1209 make them faster. However, the SH3 has hardware shifts that do not
1210 truncate, so it appears that we need to leave this undefined for correct
1211 SH3 code. We can still using truncation in the library routines though to
1212 make them faster. */
1213 #define SHIFT_COUNT_TRUNCATED 1
1215 /* All integers have the same format so truncation is easy. */
1216 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1218 /* Define this if addresses of constant functions
1219 shouldn't be put through pseudo regs where they can be cse'd.
1220 Desirable on machines where ordinary constants are expensive
1221 but a CALL with constant address is cheap. */
1222 /*#define NO_FUNCTION_CSE 1*/
1224 /* Chars and shorts should be passed as ints. */
1225 #define PROMOTE_PROTOTYPES 1
1227 /* The machine modes of pointers and functions. */
1228 #define Pmode SImode
1229 #define FUNCTION_MODE Pmode
1231 /* The relative costs of various types of constants. Note that cse.c defines
1232 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1234 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1236 if (INTVAL (RTX) == 0) \
1238 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1240 else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \
1241 && CONST_OK_FOR_L (INTVAL (RTX))) \
1249 case CONST_DOUBLE: \
1252 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1254 return COSTS_N_INSNS (andcosts (X)); \
1256 return COSTS_N_INSNS (multcosts (X)); \
1260 return COSTS_N_INSNS (shiftcosts (X)) ; \
1265 return COSTS_N_INSNS (20); \
1270 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1271 are actually function calls with some special constraints on arguments
1274 These macros tell reorg that the references to arguments and
1275 register clobbers for insns of type sfunc do not appear to happen
1276 until after the millicode call. This allows reorg to put insns
1277 which set the argument registers into the delay slot of the millicode
1278 call -- thus they act more like traditional CALL_INSNs.
1280 get_attr_type will try to recognize the given insn, so make sure to
1281 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1284 #define INSN_SETS_ARE_DELAYED(X) \
1285 ((GET_CODE (X) == INSN \
1286 && GET_CODE (PATTERN (X)) != SEQUENCE \
1287 && GET_CODE (PATTERN (X)) != USE \
1288 && GET_CODE (PATTERN (X)) != CLOBBER \
1289 && get_attr_type (X) == TYPE_SFUNC))
1291 #define INSN_REFERENCES_ARE_DELAYED(X) \
1292 ((GET_CODE (X) == INSN \
1293 && GET_CODE (PATTERN (X)) != SEQUENCE \
1294 && GET_CODE (PATTERN (X)) != USE \
1295 && GET_CODE (PATTERN (X)) != CLOBBER \
1296 && get_attr_type (X) == TYPE_SFUNC))
1298 /* Compute the cost of an address. For the SH, all valid addresses are
1300 /* ??? Perhaps we should make reg+reg addresses have higher cost because
1301 they add to register pressure on r0. */
1303 #define ADDRESS_COST(RTX) 1
1305 /* Compute extra cost of moving data between one register class
1308 On the SH it is hard to move into the T reg, but simple to load
1311 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1312 (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 \
1313 : ((DSTCLASS == FP_REGS && SRCCLASS == GENERAL_REGS) \
1314 || (DSTCLASS == GENERAL_REGS && SRCCLASS == FP_REGS)) ? 4 \
1317 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1318 would be so that people would slow memory systems could generate
1319 different code that does fewer memory accesses. */
1321 /* Assembler output control. */
1323 /* A C string constant describing how to begin a comment in the target
1324 assembler language. The compiler assumes that the comment will end at
1325 the end of the line. */
1326 #define ASM_COMMENT_START "!"
1328 /* The text to go at the start of the assembler file. */
1329 #define ASM_FILE_START(STREAM) \
1330 output_file_start (STREAM)
1332 #define ASM_FILE_END(STREAM)
1334 #define ASM_APP_ON ""
1335 #define ASM_APP_OFF ""
1336 #define FILE_ASM_OP "\t.file\n"
1337 #define IDENT_ASM_OP "\t.ident\n"
1338 #define SET_ASM_OP ".set"
1340 /* How to change between sections. */
1342 #define TEXT_SECTION_ASM_OP "\t.text"
1343 #define DATA_SECTION_ASM_OP "\t.data"
1344 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
1345 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
1346 #define EXTRA_SECTIONS in_ctors, in_dtors
1347 #define EXTRA_SECTION_FUNCTIONS \
1351 if (in_section != in_ctors) \
1353 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1354 in_section = in_ctors; \
1360 if (in_section != in_dtors) \
1362 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1363 in_section = in_dtors; \
1367 /* Define this so that jump tables go in same section as the current function,
1368 which could be text or it could be a user defined section. */
1369 #define JUMP_TABLES_IN_TEXT_SECTION
1371 /* A C statement to output something to the assembler file to switch to section
1372 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1373 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1374 define this macro in such cases. */
1376 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
1377 do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
1379 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1380 do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1382 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1383 do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
1385 #undef DO_GLOBAL_CTORS_BODY
1387 #define DO_GLOBAL_CTORS_BODY \
1389 typedef (*pfunc)(); \
1390 extern pfunc __ctors[]; \
1391 extern pfunc __ctors_end[]; \
1393 for (p = __ctors_end; p > __ctors; ) \
1399 #undef DO_GLOBAL_DTORS_BODY
1400 #define DO_GLOBAL_DTORS_BODY \
1402 typedef (*pfunc)(); \
1403 extern pfunc __dtors[]; \
1404 extern pfunc __dtors_end[]; \
1406 for (p = __dtors; p < __dtors_end; p++) \
1412 #define ASM_OUTPUT_REG_PUSH(file, v) \
1413 fprintf (file, "\tmov.l r%s,-@r15\n", v);
1415 #define ASM_OUTPUT_REG_POP(file, v) \
1416 fprintf (file, "\tmov.l @r15+,r%s\n", v);
1418 /* The assembler's names for the registers. RFP need not always be used as
1419 the Real framepointer; it can also be used as a normal general register.
1420 Note that the name `fp' is horribly misleading since `fp' is in fact only
1421 the argument-and-return-context pointer. */
1422 #define REGISTER_NAMES \
1424 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1425 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1426 "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \
1427 "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1428 "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
1431 /* DBX register number for a given compiler register number. */
1432 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1434 #define DBX_REGISTER_NUMBER(REGNO) \
1435 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
1437 /* Output a label definition. */
1438 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1439 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1441 /* This is how to output an assembler line
1442 that says to advance the location counter
1443 to a multiple of 2**LOG bytes. */
1445 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1447 fprintf (FILE, "\t.align %d\n", LOG)
1449 /* Output a function label definition. */
1450 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1451 ASM_OUTPUT_LABEL(STREAM, NAME)
1453 /* Output a globalising directive for a label. */
1454 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1455 (fprintf (STREAM, "\t.global\t"), \
1456 assemble_name (STREAM, NAME), \
1457 fputc ('\n',STREAM))
1459 /* The prefix to add to user-visible assembler symbols. */
1461 #define USER_LABEL_PREFIX "_"
1463 /* Make an internal label into a string. */
1464 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1465 sprintf (STRING, "*%s%d", PREFIX, NUM)
1467 /* Output an internal label definition. */
1468 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1469 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1471 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1473 /* Construct a private name. */
1474 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1475 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1476 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1478 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
1479 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1480 fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
1482 /* Output a relative address table. */
1484 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1485 if (TARGET_BIGTABLE) \
1486 fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
1488 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
1490 /* Output an absolute table element. */
1492 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1493 if (TARGET_BIGTABLE) \
1494 fprintf (STREAM, "\t.long L%d\n", VALUE); \
1496 fprintf (STREAM, "\t.word L%d\n", VALUE); \
1498 /* Output various types of constants. */
1500 /* This is how to output an assembler line defining a `double'. */
1502 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1503 do { char dstr[30]; \
1504 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1505 fprintf (FILE, "\t.double %s\n", dstr); \
1508 /* This is how to output an assembler line defining a `float' constant. */
1509 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1510 do { char dstr[30]; \
1511 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1512 fprintf (FILE, "\t.float %s\n", dstr); \
1515 #define ASM_OUTPUT_INT(STREAM, EXP) \
1516 (fprintf (STREAM, "\t.long\t"), \
1517 output_addr_const (STREAM, (EXP)), \
1518 fputc ('\n', STREAM))
1520 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1521 (fprintf (STREAM, "\t.short\t"), \
1522 output_addr_const (STREAM, (EXP)), \
1523 fputc ('\n', STREAM))
1525 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1526 (fprintf (STREAM, "\t.byte\t"), \
1527 output_addr_const (STREAM, (EXP)), \
1528 fputc ('\n', STREAM))
1530 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1531 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1533 /* Align loops and labels after unconditional branches to get faster
1536 #define ASM_OUTPUT_LOOP_ALIGN(FILE) \
1537 if (! TARGET_SMALLCODE) \
1538 ASM_OUTPUT_ALIGN ((FILE), 2)
1540 #define ASM_OUTPUT_ALIGN_CODE(FILE) \
1541 if (! TARGET_SMALLCODE) \
1542 ASM_OUTPUT_ALIGN ((FILE), (TARGET_SH3 || TARGET_SH3E) ? 4 : 2)
1544 /* This is how to output an assembler line
1545 that says to advance the location counter by SIZE bytes. */
1547 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1548 fprintf (FILE, "\t.space %d\n", (SIZE))
1550 /* This says how to output an assembler line
1551 to define a global common symbol. */
1553 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1554 ( fputs ("\t.comm ", (FILE)), \
1555 assemble_name ((FILE), (NAME)), \
1556 fprintf ((FILE), ",%d\n", (SIZE)))
1558 /* This says how to output an assembler line
1559 to define a local common symbol. */
1561 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1562 ( fputs ("\t.lcomm ", (FILE)), \
1563 assemble_name ((FILE), (NAME)), \
1564 fprintf ((FILE), ",%d\n", (SIZE)))
1566 /* The assembler's parentheses characters. */
1567 #define ASM_OPEN_PAREN "("
1568 #define ASM_CLOSE_PAREN ")"
1570 /* Target characters. */
1571 #define TARGET_BELL 007
1572 #define TARGET_BS 010
1573 #define TARGET_TAB 011
1574 #define TARGET_NEWLINE 012
1575 #define TARGET_VT 013
1576 #define TARGET_FF 014
1577 #define TARGET_CR 015
1579 /* Only perform branch elimination (by making instructions conditional) if
1580 we're optimizing. Otherwise it's of no use anyway. */
1581 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1582 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1584 /* Print operand X (an rtx) in assembler syntax to file FILE.
1585 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1586 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1588 #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
1590 /* Print a memory address as an operand to reference that memory location. */
1592 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
1594 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1595 ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
1597 extern struct rtx_def
*sh_compare_op0
;
1598 extern struct rtx_def
*sh_compare_op1
;
1599 extern struct rtx_def
*prepare_scc_operands();
1601 /* Which processor to schedule for. The elements of the enumeration must
1602 match exactly the cpu attribute in the sh.md file. */
1604 enum processor_type
{
1612 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1613 extern enum processor_type sh_cpu
;
1615 /* Declare functions defined in sh.c and used in templates. */
1617 extern char *output_branch();
1618 extern char *output_shift();
1619 extern char *output_movedouble();
1620 extern char *output_movepcrel();
1621 extern char *output_jump_label_table();
1622 extern char *output_far_jump();
1624 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
1626 /* Generate calls to memcpy, memcmp and memset. */
1628 #define TARGET_MEM_FUNCTIONS
1630 /* Define this macro if you want to implement any pragmas. If defined, it
1631 is a C expression to be executed when #pragma is seen. The
1632 argument FILE is the stdio input stream from which the source
1633 text can be read. CH is the first character after the #pragma. The
1634 result of the expression is the terminating character found
1635 (newline or EOF). */
1636 #define HANDLE_PRAGMA(FILE, NODE) handle_pragma (FILE, NODE)
1638 /* Set when processing a function with pragma interrupt turned on. */
1640 extern int pragma_interrupt
;
1642 #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
1644 /* Instructions with unfilled delay slots take up an extra two bytes for
1645 the nop in the delay slot. Instructions at the start of loops, or
1646 after unconditional branches, may take up extra room when they are
1647 aligned. ??? We would get more accurate results if we did instruction
1648 alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
1649 here is too conservative. */
1651 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1652 if (((GET_CODE (X) == INSN \
1653 && GET_CODE (PATTERN (X)) != SEQUENCE \
1654 && GET_CODE (PATTERN (X)) != USE \
1655 && GET_CODE (PATTERN (X)) != CLOBBER) \
1656 || GET_CODE (X) == CALL_INSN \
1657 || (GET_CODE (X) == JUMP_INSN \
1658 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
1659 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
1660 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
1662 if (! TARGET_SMALLCODE) \
1664 /* After the folowing loop, PAD will be an upper bound \
1665 for the number of padding bytes the alignment will \
1669 for (aip = PREV_INSN (X); aip; aip = PREV_INSN (aip)) \
1671 if (GET_CODE (aip) == BARRIER) \
1673 if (TARGET_SH3 || TARGET_SH3E) \
1679 else if ((GET_CODE (aip) == NOTE \
1680 && NOTE_LINE_NUMBER (aip) == NOTE_INSN_LOOP_BEG)) \
1683 /* Don't break here, because there might be a \
1684 preceding BARRIER, which requires mores \
1685 alignment for SH3[E] . */ \
1687 else if (GET_CODE (aip) != NOTE \
1688 && GET_CODE (aip) != CODE_LABEL) \
1694 /* Enable a bug fix for the shorten_branches pass. */
1695 #define SHORTEN_WITH_ADJUST_INSN_LENGTH
1697 /* Define the codes that are matched by predicates in sh.c. */
1698 #define PREDICATE_CODES \
1699 {"arith_reg_operand", {SUBREG, REG}}, \
1700 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1701 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1702 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
1703 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1704 {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
1706 /* Define this macro if it is advisable to hold scalars in registers
1707 in a wider mode than that declared by the program. In such cases,
1708 the value is constrained to be within the bounds of the declared
1709 type, but kept valid in the wider mode. The signedness of the
1710 extension may differ from that of the type.
1712 Leaving the unsignedp unchanged gives better code than always setting it
1713 to 0. This is despite the fact that we have only signed char and short
1714 load instructions. */
1715 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1716 if (GET_MODE_CLASS (MODE) == MODE_INT \
1717 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1720 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
1721 extensions applied to char/short functions arguments. Defining
1722 PROMOTE_FUNCTION_RETURN does the same for function returns. */
1724 #define PROMOTE_FUNCTION_ARGS
1725 #define PROMOTE_FUNCTION_RETURN
1727 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
1728 and poping arguments. However, we do have push/pop instructions, and
1729 rather limited offsets (4 bits) in load/store instructions, so it isn't
1730 clear if this would give better code. If implemented, should check for
1731 compatibility problems. */
1733 /* A C statement (sans semicolon) to update the integer variable COST
1734 based on the relationship between INSN that is dependent on
1735 DEP_INSN through the dependence LINK. The default is to make no
1736 adjustment to COST. This can be used for example to specify to
1737 the scheduler that an output- or anti-dependence does not incur
1738 the same cost as a data-dependence. */
1740 /* ??? Should anticipate the effect of delayed branch scheduling
1741 and arrange for a second instruction to be put between the
1742 load of the function's address and the call. */
1744 #define ADJUST_COST(insn,link,dep_insn,cost) \
1745 if (GET_CODE(insn) == CALL_INSN) \
1747 /* The only input for a call that is timing-critical is the \
1748 function's address. */ \
1749 rtx call = PATTERN (insn); \
1751 if (GET_CODE (call) == PARALLEL) \
1752 call = XVECEXP (call, 0 ,0); \
1753 if (GET_CODE (call) == SET) \
1754 call = SET_SRC (call); \
1755 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM) \
1757 rtx set = single_set (dep_insn); \
1759 if (set && ! rtx_equal_p (SET_DEST (set), XEXP (XEXP (call, 0), 0)))\
1764 /* Since the SH architecture lacks negative address offsets,
1765 the givs should be sorted smallest to largest so combine_givs
1766 has maximum opportunity to combine givs. */
1767 #define GIV_SORT_CRITERION(X, Y) \
1768 if (GET_CODE ((X)->add_val) == CONST_INT \
1769 && GET_CODE ((Y)->add_val) == CONST_INT) \
1770 return INTVAL ((X)->add_val) - INTVAL ((Y)->add_val);
1772 /* For the sake of libgcc2.c, indicate target supports atexit. */