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sh-protos.h (sh_legitimate_address_p): Remove.
[gcc.git] / gcc / config / sh / sh.h
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #ifndef GCC_SH_H
24 #define GCC_SH_H
25
26 #include "config/vxworks-dummy.h"
27
28 #define TARGET_VERSION \
29 fputs (" (Hitachi SH)", stderr);
30
31 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
32 include it here, because bconfig.h is also included by gencodes.c . */
33 /* ??? No longer true. */
34 extern int code_for_indirect_jump_scratch;
35
36 #define TARGET_CPU_CPP_BUILTINS() \
37 do { \
38 builtin_define ("__sh__"); \
39 builtin_assert ("cpu=sh"); \
40 builtin_assert ("machine=sh"); \
41 switch ((int) sh_cpu) \
42 { \
43 case PROCESSOR_SH1: \
44 builtin_define ("__sh1__"); \
45 break; \
46 case PROCESSOR_SH2: \
47 builtin_define ("__sh2__"); \
48 break; \
49 case PROCESSOR_SH2E: \
50 builtin_define ("__SH2E__"); \
51 break; \
52 case PROCESSOR_SH2A: \
53 builtin_define ("__SH2A__"); \
54 builtin_define (TARGET_SH2A_DOUBLE \
55 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
56 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
57 : "__SH2A_NOFPU__"); \
58 break; \
59 case PROCESSOR_SH3: \
60 builtin_define ("__sh3__"); \
61 builtin_define ("__SH3__"); \
62 if (TARGET_HARD_SH4) \
63 builtin_define ("__SH4_NOFPU__"); \
64 break; \
65 case PROCESSOR_SH3E: \
66 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
67 break; \
68 case PROCESSOR_SH4: \
69 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
70 break; \
71 case PROCESSOR_SH4A: \
72 builtin_define ("__SH4A__"); \
73 builtin_define (TARGET_SH4 \
74 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
75 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
76 : "__SH4_NOFPU__"); \
77 break; \
78 case PROCESSOR_SH5: \
79 { \
80 builtin_define_with_value ("__SH5__", \
81 TARGET_SHMEDIA64 ? "64" : "32", 0); \
82 builtin_define_with_value ("__SHMEDIA__", \
83 TARGET_SHMEDIA ? "1" : "0", 0); \
84 if (! TARGET_FPU_DOUBLE) \
85 builtin_define ("__SH4_NOFPU__"); \
86 } \
87 } \
88 if (TARGET_FPU_ANY) \
89 builtin_define ("__SH_FPU_ANY__"); \
90 if (TARGET_FPU_DOUBLE) \
91 builtin_define ("__SH_FPU_DOUBLE__"); \
92 if (TARGET_HITACHI) \
93 builtin_define ("__HITACHI__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
96 } while (0)
97
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
100
101 #define CONDITIONAL_REGISTER_USAGE do \
102 { \
103 int regno; \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
108 if (TARGET_SH5) \
109 { \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
114 } \
115 if (TARGET_SHMEDIA) \
116 { \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
120 } \
121 if (flag_pic) \
122 { \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
125 } \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
128 { \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
131 } \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
136 { \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
140 } \
141 else \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
145 } while (0)
146 \f
147 /* Nonzero if this is an ELF target - compile time only */
148 #define TARGET_ELF 0
149
150 /* Nonzero if we should generate code using type 2E insns. */
151 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
152
153 /* Nonzero if we should generate code using type 2A insns. */
154 #define TARGET_SH2A TARGET_HARD_SH2A
155 /* Nonzero if we should generate code using type 2A SF insns. */
156 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
157 /* Nonzero if we should generate code using type 2A DF insns. */
158 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
159
160 /* Nonzero if we should generate code using type 3E insns. */
161 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
162
163 /* Nonzero if the cache line size is 32. */
164 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
165
166 /* Nonzero if we schedule for a superscalar implementation. */
167 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
168
169 /* Nonzero if the target has separate instruction and data caches. */
170 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
171
172 /* Nonzero if a double-precision FPU is available. */
173 #define TARGET_FPU_DOUBLE \
174 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
175
176 /* Nonzero if an FPU is available. */
177 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
178
179 /* Nonzero if we should generate code using type 4 insns. */
180 #undef TARGET_SH4
181 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
182
183 /* Nonzero if we're generating code for the common subset of
184 instructions present on both SH4a and SH4al-dsp. */
185 #define TARGET_SH4A_ARCH TARGET_SH4A
186
187 /* Nonzero if we're generating code for SH4a, unless the use of the
188 FPU is disabled (which makes it compatible with SH4al-dsp). */
189 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
190
191 /* Nonzero if we should generate code using the SHcompact instruction
192 set and 32-bit ABI. */
193 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
194
195 /* Nonzero if we should generate code using the SHmedia instruction
196 set and ABI. */
197 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
198
199 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
200 ABI. */
201 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
202
203 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
204 ABI. */
205 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
206
207 /* Nonzero if we should generate code using SHmedia FPU instructions. */
208 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
209
210 /* This is not used by the SH2E calling convention */
211 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
212 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
213 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
214
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT SELECT_SH1
217 #define SUPPORT_SH1 1
218 #define SUPPORT_SH2E 1
219 #define SUPPORT_SH4 1
220 #define SUPPORT_SH4_SINGLE 1
221 #define SUPPORT_SH2A 1
222 #define SUPPORT_SH2A_SINGLE 1
223 #endif
224
225 #define TARGET_DIVIDE_INV \
226 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
227 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
228 || sh_div_strategy == SH_DIV_INV_CALL \
229 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
230 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
231 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
232 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
233 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
234 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
235 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
236 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
237 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
238 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
239 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
240 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
241
242 #define SELECT_SH1 (MASK_SH1)
243 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
244 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
245 | MASK_FPU_SINGLE)
246 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
247 | MASK_HARD_SH2A_DOUBLE \
248 | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
251 | MASK_SH1 | MASK_FPU_SINGLE)
252 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
253 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
254 | MASK_SH2 | MASK_SH1)
255 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
256 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
257 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
258 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
259 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
260 | SELECT_SH3)
261 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
262 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
263 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
264 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
265 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
266 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
267 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
268 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
269 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
270 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
271 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
272
273 #if SUPPORT_SH1
274 #define SUPPORT_SH2 1
275 #endif
276 #if SUPPORT_SH2
277 #define SUPPORT_SH3 1
278 #define SUPPORT_SH2A_NOFPU 1
279 #endif
280 #if SUPPORT_SH3
281 #define SUPPORT_SH4_NOFPU 1
282 #endif
283 #if SUPPORT_SH4_NOFPU
284 #define SUPPORT_SH4A_NOFPU 1
285 #define SUPPORT_SH4AL 1
286 #endif
287
288 #if SUPPORT_SH2E
289 #define SUPPORT_SH3E 1
290 #define SUPPORT_SH2A_SINGLE_ONLY 1
291 #endif
292 #if SUPPORT_SH3E
293 #define SUPPORT_SH4_SINGLE_ONLY 1
294 #endif
295 #if SUPPORT_SH4_SINGLE_ONLY
296 #define SUPPORT_SH4A_SINGLE_ONLY 1
297 #endif
298
299 #if SUPPORT_SH4
300 #define SUPPORT_SH4A 1
301 #endif
302
303 #if SUPPORT_SH4_SINGLE
304 #define SUPPORT_SH4A_SINGLE 1
305 #endif
306
307 #if SUPPORT_SH5_COMPAT
308 #define SUPPORT_SH5_32MEDIA 1
309 #endif
310
311 #if SUPPORT_SH5_COMPACT_NOFPU
312 #define SUPPORT_SH5_32MEDIA_NOFPU 1
313 #endif
314
315 #define SUPPORT_ANY_SH5_32MEDIA \
316 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
317 #define SUPPORT_ANY_SH5_64MEDIA \
318 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
319 #define SUPPORT_ANY_SH5 \
320 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
321
322 /* Reset all target-selection flags. */
323 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
324 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
325 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
326
327 /* This defaults us to big-endian. */
328 #ifndef TARGET_ENDIAN_DEFAULT
329 #define TARGET_ENDIAN_DEFAULT 0
330 #endif
331
332 #ifndef TARGET_OPT_DEFAULT
333 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
334 #endif
335
336 #define TARGET_DEFAULT \
337 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
338
339 #ifndef SH_MULTILIB_CPU_DEFAULT
340 #define SH_MULTILIB_CPU_DEFAULT "m1"
341 #endif
342
343 #if TARGET_ENDIAN_DEFAULT
344 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
345 #else
346 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
347 #endif
348
349 #define CPP_SPEC " %(subtarget_cpp_spec) "
350
351 #ifndef SUBTARGET_CPP_SPEC
352 #define SUBTARGET_CPP_SPEC ""
353 #endif
354
355 #ifndef SUBTARGET_EXTRA_SPECS
356 #define SUBTARGET_EXTRA_SPECS
357 #endif
358
359 #define EXTRA_SPECS \
360 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
361 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
362 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
363 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
364 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
365 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
366 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
367 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
368 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
369 SUBTARGET_EXTRA_SPECS
370
371 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
372 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
373 #else
374 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
375 #endif
376
377 #define SH_ASM_SPEC \
378 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
379 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
380 %{m2a:--isa=sh2a} \
381 %{m2a-single:--isa=sh2a} \
382 %{m2a-single-only:--isa=sh2a} \
383 %{m2a-nofpu:--isa=sh2a-nofpu} \
384 %{m5-compact*:--isa=SHcompact} \
385 %{m5-32media*:--isa=SHmedia --abi=32} \
386 %{m5-64media*:--isa=SHmedia --abi=64} \
387 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
388
389 #define ASM_SPEC SH_ASM_SPEC
390
391 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
392 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
393 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
394 #else
395 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
396 #endif
397 #endif
398
399 #if STRICT_NOFPU == 1
400 /* Strict nofpu means that the compiler should tell the assembler
401 to reject FPU instructions. E.g. from ASM inserts. */
402 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
403 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
404 #else
405 /* If there were an -isa option for sh5-nofpu then it would also go here. */
406 #define SUBTARGET_ASM_ISA_SPEC \
407 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
408 #endif
409 #else /* ! STRICT_NOFPU */
410 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
411 #endif
412
413 #ifndef SUBTARGET_ASM_SPEC
414 #define SUBTARGET_ASM_SPEC ""
415 #endif
416
417 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
418 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
419 #else
420 #define LINK_EMUL_PREFIX "sh%{ml:l}"
421 #endif
422
423 #if TARGET_CPU_DEFAULT & MASK_SH5
424 #if TARGET_CPU_DEFAULT & MASK_SH_E
425 #define LINK_DEFAULT_CPU_EMUL "32"
426 #if TARGET_CPU_DEFAULT & MASK_SH1
427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
428 #else
429 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
430 #endif /* MASK_SH1 */
431 #else /* !MASK_SH_E */
432 #define LINK_DEFAULT_CPU_EMUL "64"
433 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
434 #endif /* MASK_SH_E */
435 #define ASM_ISA_DEFAULT_SPEC \
436 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
437 #else /* !MASK_SH5 */
438 #define LINK_DEFAULT_CPU_EMUL ""
439 #define ASM_ISA_DEFAULT_SPEC ""
440 #endif /* MASK_SH5 */
441
442 #define SUBTARGET_LINK_EMUL_SUFFIX ""
443 #define SUBTARGET_LINK_SPEC ""
444
445 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
446 so that we can undo the damage without code replication. */
447 #define LINK_SPEC SH_LINK_SPEC
448
449 #define SH_LINK_SPEC "\
450 -m %(link_emul_prefix)\
451 %{m5-compact*|m5-32media*:32}\
452 %{m5-64media*:64}\
453 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
454 %(subtarget_link_emul_suffix) \
455 %{mrelax:-relax} %(subtarget_link_spec)"
456
457 #ifndef SH_DIV_STR_FOR_SIZE
458 #define SH_DIV_STR_FOR_SIZE "call"
459 #endif
460
461 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
462 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
463 do { \
464 if (LEVEL) \
465 { \
466 flag_omit_frame_pointer = 2; \
467 if (! SIZE) \
468 sh_div_str = "inv:minlat"; \
469 } \
470 if (SIZE) \
471 { \
472 target_flags |= MASK_SMALLCODE; \
473 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
474 } \
475 else \
476 TARGET_CBRANCHDI4 = 1; \
477 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
478 haven't been parsed yet, hence we'd read only the default. \
479 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
480 it's OK to always set flag_branch_target_load_optimize. */ \
481 if (LEVEL > 1) \
482 { \
483 flag_branch_target_load_optimize = 1; \
484 if (! (SIZE)) \
485 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
486 } \
487 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
488 here, so leave it to OVERRIDE_OPTIONS to set \
489 flag_finite_math_only. We set it to 2 here so we know if the user \
490 explicitly requested this to be on or off. */ \
491 flag_finite_math_only = 2; \
492 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
493 the user explicitly requested this to be on or off. */ \
494 if (flag_schedule_insns > 0) \
495 flag_schedule_insns = 2; \
496 \
497 set_param_value ("simultaneous-prefetches", 2); \
498 } while (0)
499
500 #define ASSEMBLER_DIALECT assembler_dialect
501
502 extern int assembler_dialect;
503
504 enum sh_divide_strategy_e {
505 /* SH5 strategies. */
506 SH_DIV_CALL,
507 SH_DIV_CALL2,
508 SH_DIV_FP, /* We could do this also for SH4. */
509 SH_DIV_INV,
510 SH_DIV_INV_MINLAT,
511 SH_DIV_INV20U,
512 SH_DIV_INV20L,
513 SH_DIV_INV_CALL,
514 SH_DIV_INV_CALL2,
515 SH_DIV_INV_FP,
516 /* SH1 .. SH4 strategies. Because of the small number of registers
517 available, the compiler uses knowledge of the actual set of registers
518 being clobbered by the different functions called. */
519 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
520 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
521 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
522 SH_DIV_INTRINSIC
523 };
524
525 extern enum sh_divide_strategy_e sh_div_strategy;
526
527 #ifndef SH_DIV_STRATEGY_DEFAULT
528 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
529 #endif
530
531 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
532
533 extern const char *sh_fixed_range_str;
534
535 #define OVERRIDE_OPTIONS \
536 do { \
537 int regno; \
538 \
539 SUBTARGET_OVERRIDE_OPTIONS; \
540 if (flag_finite_math_only == 2) \
541 flag_finite_math_only \
542 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
543 if (TARGET_SH2E && !flag_finite_math_only) \
544 target_flags |= MASK_IEEE; \
545 sh_cpu = PROCESSOR_SH1; \
546 assembler_dialect = 0; \
547 if (TARGET_SH2) \
548 sh_cpu = PROCESSOR_SH2; \
549 if (TARGET_SH2E) \
550 sh_cpu = PROCESSOR_SH2E; \
551 if (TARGET_SH2A) \
552 { \
553 sh_cpu = PROCESSOR_SH2A; \
554 if (TARGET_SH2A_DOUBLE) \
555 target_flags |= MASK_FMOVD; \
556 } \
557 if (TARGET_SH3) \
558 sh_cpu = PROCESSOR_SH3; \
559 if (TARGET_SH3E) \
560 sh_cpu = PROCESSOR_SH3E; \
561 if (TARGET_SH4) \
562 { \
563 assembler_dialect = 1; \
564 sh_cpu = PROCESSOR_SH4; \
565 } \
566 if (TARGET_SH4A_ARCH) \
567 { \
568 assembler_dialect = 1; \
569 sh_cpu = PROCESSOR_SH4A; \
570 } \
571 if (TARGET_SH5) \
572 { \
573 sh_cpu = PROCESSOR_SH5; \
574 target_flags |= MASK_ALIGN_DOUBLE; \
575 if (TARGET_SHMEDIA_FPU) \
576 target_flags |= MASK_FMOVD; \
577 if (TARGET_SHMEDIA) \
578 { \
579 /* There are no delay slots on SHmedia. */ \
580 flag_delayed_branch = 0; \
581 /* Relaxation isn't yet supported for SHmedia */ \
582 target_flags &= ~MASK_RELAX; \
583 /* After reload, if conversion does little good but can cause \
584 ICEs: \
585 - find_if_block doesn't do anything for SH because we don't\
586 have conditional execution patterns. (We use conditional\
587 move patterns, which are handled differently, and only \
588 before reload). \
589 - find_cond_trap doesn't do anything for the SH because we \
590 don't have conditional traps. \
591 - find_if_case_1 uses redirect_edge_and_branch_force in \
592 the only path that does an optimization, and this causes \
593 an ICE when branch targets are in registers. \
594 - find_if_case_2 doesn't do anything for the SHmedia after \
595 reload except when it can redirect a tablejump - and \
596 that's rather rare. */ \
597 flag_if_conversion2 = 0; \
598 if (! strcmp (sh_div_str, "call")) \
599 sh_div_strategy = SH_DIV_CALL; \
600 else if (! strcmp (sh_div_str, "call2")) \
601 sh_div_strategy = SH_DIV_CALL2; \
602 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
603 sh_div_strategy = SH_DIV_FP; \
604 else if (! strcmp (sh_div_str, "inv")) \
605 sh_div_strategy = SH_DIV_INV; \
606 else if (! strcmp (sh_div_str, "inv:minlat")) \
607 sh_div_strategy = SH_DIV_INV_MINLAT; \
608 else if (! strcmp (sh_div_str, "inv20u")) \
609 sh_div_strategy = SH_DIV_INV20U; \
610 else if (! strcmp (sh_div_str, "inv20l")) \
611 sh_div_strategy = SH_DIV_INV20L; \
612 else if (! strcmp (sh_div_str, "inv:call2")) \
613 sh_div_strategy = SH_DIV_INV_CALL2; \
614 else if (! strcmp (sh_div_str, "inv:call")) \
615 sh_div_strategy = SH_DIV_INV_CALL; \
616 else if (! strcmp (sh_div_str, "inv:fp")) \
617 { \
618 if (TARGET_FPU_ANY) \
619 sh_div_strategy = SH_DIV_INV_FP; \
620 else \
621 sh_div_strategy = SH_DIV_INV; \
622 } \
623 TARGET_CBRANCHDI4 = 0; \
624 /* Assembler CFI isn't yet fully supported for SHmedia. */ \
625 flag_dwarf2_cfi_asm = 0; \
626 } \
627 } \
628 else \
629 { \
630 /* Only the sh64-elf assembler fully supports .quad properly. */\
631 targetm.asm_out.aligned_op.di = NULL; \
632 targetm.asm_out.unaligned_op.di = NULL; \
633 } \
634 if (TARGET_SH1) \
635 { \
636 if (! strcmp (sh_div_str, "call-div1")) \
637 sh_div_strategy = SH_DIV_CALL_DIV1; \
638 else if (! strcmp (sh_div_str, "call-fp") \
639 && (TARGET_FPU_DOUBLE \
640 || (TARGET_HARD_SH4 && TARGET_SH2E) \
641 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
642 sh_div_strategy = SH_DIV_CALL_FP; \
643 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
644 sh_div_strategy = SH_DIV_CALL_TABLE; \
645 else \
646 /* Pick one that makes most sense for the target in general. \
647 It is not much good to use different functions depending \
648 on -Os, since then we'll end up with two different functions \
649 when some of the code is compiled for size, and some for \
650 speed. */ \
651 \
652 /* SH4 tends to emphasize speed. */ \
653 if (TARGET_HARD_SH4) \
654 sh_div_strategy = SH_DIV_CALL_TABLE; \
655 /* These have their own way of doing things. */ \
656 else if (TARGET_SH2A) \
657 sh_div_strategy = SH_DIV_INTRINSIC; \
658 /* ??? Should we use the integer SHmedia function instead? */ \
659 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
660 sh_div_strategy = SH_DIV_CALL_FP; \
661 /* SH1 .. SH3 cores often go into small-footprint systems, so \
662 default to the smallest implementation available. */ \
663 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
664 sh_div_strategy = SH_DIV_CALL_TABLE; \
665 else \
666 sh_div_strategy = SH_DIV_CALL_DIV1; \
667 } \
668 if (!TARGET_SH1) \
669 TARGET_PRETEND_CMOVE = 0; \
670 if (sh_divsi3_libfunc[0]) \
671 ; /* User supplied - leave it alone. */ \
672 else if (TARGET_DIVIDE_CALL_FP) \
673 sh_divsi3_libfunc = "__sdivsi3_i4"; \
674 else if (TARGET_DIVIDE_CALL_TABLE) \
675 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
676 else if (TARGET_SH5) \
677 sh_divsi3_libfunc = "__sdivsi3_1"; \
678 else \
679 sh_divsi3_libfunc = "__sdivsi3"; \
680 if (sh_branch_cost == -1) \
681 sh_branch_cost \
682 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
683 \
684 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
685 if (! VALID_REGISTER_P (regno)) \
686 sh_register_names[regno][0] = '\0'; \
687 \
688 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
689 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
690 sh_additional_register_names[regno][0] = '\0'; \
691 \
692 if (flag_omit_frame_pointer == 2) \
693 { \
694 /* The debugging information is sufficient, \
695 but gdb doesn't implement this yet */ \
696 if (0) \
697 flag_omit_frame_pointer \
698 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
699 else \
700 flag_omit_frame_pointer = 0; \
701 } \
702 \
703 if ((flag_pic && ! TARGET_PREFERGOT) \
704 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
705 flag_no_function_cse = 1; \
706 \
707 if (SMALL_REGISTER_CLASSES) \
708 { \
709 /* Never run scheduling before reload, since that can \
710 break global alloc, and generates slower code anyway due \
711 to the pressure on R0. */ \
712 /* Enable sched1 for SH4 if the user explicitly requests. \
713 When sched1 is enabled, the ready queue will be reordered by \
714 the target hooks if pressure is high. We can not do this for \
715 PIC, SH3 and lower as they give spill failures for R0. */ \
716 if (!TARGET_HARD_SH4 || flag_pic) \
717 flag_schedule_insns = 0; \
718 /* ??? Current exception handling places basic block boundaries \
719 after call_insns. It causes the high pressure on R0 and gives \
720 spill failures for R0 in reload. See PR 22553 and the thread \
721 on gcc-patches \
722 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
723 else if (flag_exceptions) \
724 { \
725 if (flag_schedule_insns == 1) \
726 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
727 flag_schedule_insns = 0; \
728 } \
729 else if (flag_schedule_insns == 2) \
730 flag_schedule_insns = 0; \
731 } \
732 \
733 if (align_loops == 0) \
734 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
735 if (align_jumps == 0) \
736 align_jumps = 1 << CACHE_LOG; \
737 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
738 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
739 \
740 /* Allocation boundary (in *bytes*) for the code of a function. \
741 SH1: 32 bit alignment is faster, because instructions are always \
742 fetched as a pair from a longword boundary. \
743 SH2 .. SH5 : align to cache line start. */ \
744 if (align_functions == 0) \
745 align_functions \
746 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
747 /* The linker relaxation code breaks when a function contains \
748 alignments that are larger than that at the start of a \
749 compilation unit. */ \
750 if (TARGET_RELAX) \
751 { \
752 int min_align \
753 = align_loops > align_jumps ? align_loops : align_jumps; \
754 \
755 /* Also take possible .long constants / mova tables int account. */\
756 if (min_align < 4) \
757 min_align = 4; \
758 if (align_functions < min_align) \
759 align_functions = min_align; \
760 } \
761 \
762 if (sh_fixed_range_str) \
763 sh_fix_range (sh_fixed_range_str); \
764 } while (0)
765 \f
766 /* Target machine storage layout. */
767
768 /* Define this if most significant bit is lowest numbered
769 in instructions that operate on numbered bit-fields. */
770
771 #define BITS_BIG_ENDIAN 0
772
773 /* Define this if most significant byte of a word is the lowest numbered. */
774 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
775
776 /* Define this if most significant word of a multiword number is the lowest
777 numbered. */
778 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
779
780 /* Define this to set the endianness to use in libgcc2.c, which can
781 not depend on target_flags. */
782 #if defined(__LITTLE_ENDIAN__)
783 #define LIBGCC2_WORDS_BIG_ENDIAN 0
784 #else
785 #define LIBGCC2_WORDS_BIG_ENDIAN 1
786 #endif
787
788 #define MAX_BITS_PER_WORD 64
789
790 /* Width in bits of an `int'. We want just 32-bits, even if words are
791 longer. */
792 #define INT_TYPE_SIZE 32
793
794 /* Width in bits of a `long'. */
795 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
796
797 /* Width in bits of a `long long'. */
798 #define LONG_LONG_TYPE_SIZE 64
799
800 /* Width in bits of a `long double'. */
801 #define LONG_DOUBLE_TYPE_SIZE 64
802
803 /* Width of a word, in units (bytes). */
804 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
805 #define MIN_UNITS_PER_WORD 4
806
807 /* Scaling factor for Dwarf data offsets for CFI information.
808 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
809 SHmedia; however, since we do partial register saves for the registers
810 visible to SHcompact, and for target registers for SHMEDIA32, we have
811 to allow saves that are only 4-byte aligned. */
812 #define DWARF_CIE_DATA_ALIGNMENT -4
813
814 /* Width in bits of a pointer.
815 See also the macro `Pmode' defined below. */
816 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
817
818 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
819 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
820
821 /* Boundary (in *bits*) on which stack pointer should be aligned. */
822 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
823
824 /* The log (base 2) of the cache line size, in bytes. Processors prior to
825 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
826 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
827 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
828
829 /* ABI given & required minimum allocation boundary (in *bits*) for the
830 code of a function. */
831 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
832
833 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
834 the vbit must go into the delta field of
835 pointers-to-member-functions. */
836 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
837 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
838
839 /* Alignment of field after `int : 0' in a structure. */
840 #define EMPTY_FIELD_BOUNDARY 32
841
842 /* No data type wants to be aligned rounder than this. */
843 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
844
845 /* The best alignment to use in cases where we have a choice. */
846 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
847
848 /* Make strings word-aligned so strcpy from constants will be faster. */
849 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
850 ((TREE_CODE (EXP) == STRING_CST \
851 && (ALIGN) < FASTEST_ALIGNMENT) \
852 ? FASTEST_ALIGNMENT : (ALIGN))
853
854 /* get_mode_alignment assumes complex values are always held in multiple
855 registers, but that is not the case on the SH; CQImode and CHImode are
856 held in a single integer register. SH5 also holds CSImode and SCmode
857 values in integer registers. This is relevant for argument passing on
858 SHcompact as we use a stack temp in order to pass CSImode by reference. */
859 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
860 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
861 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
862 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
863 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
864
865 /* Make arrays of chars word-aligned for the same reasons. */
866 #define DATA_ALIGNMENT(TYPE, ALIGN) \
867 (TREE_CODE (TYPE) == ARRAY_TYPE \
868 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
869 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
870
871 /* Number of bits which any structure or union's size must be a
872 multiple of. Each structure or union's size is rounded up to a
873 multiple of this. */
874 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
875
876 /* Set this nonzero if move instructions will actually fail to work
877 when given unaligned data. */
878 #define STRICT_ALIGNMENT 1
879
880 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
881 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
882 barrier_align (LABEL_AFTER_BARRIER)
883
884 #define LOOP_ALIGN(A_LABEL) \
885 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
886 ? 0 : sh_loop_align (A_LABEL))
887
888 #define LABEL_ALIGN(A_LABEL) \
889 ( \
890 (PREV_INSN (A_LABEL) \
891 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
892 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
893 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
894 /* explicit alignment insn in constant tables. */ \
895 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
896 : 0)
897
898 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
899 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
900
901 /* The base two logarithm of the known minimum alignment of an insn length. */
902 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
903 (GET_CODE (A_INSN) == INSN \
904 ? 1 << TARGET_SHMEDIA \
905 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
906 ? 1 << TARGET_SHMEDIA \
907 : CACHE_LOG)
908 \f
909 /* Standard register usage. */
910
911 /* Register allocation for the Renesas calling convention:
912
913 r0 arg return
914 r1..r3 scratch
915 r4..r7 args in
916 r8..r13 call saved
917 r14 frame pointer/call saved
918 r15 stack pointer
919 ap arg pointer (doesn't really exist, always eliminated)
920 pr subroutine return address
921 t t bit
922 mach multiply/accumulate result, high part
923 macl multiply/accumulate result, low part.
924 fpul fp/int communication register
925 rap return address pointer register
926 fr0 fp arg return
927 fr1..fr3 scratch floating point registers
928 fr4..fr11 fp args in
929 fr12..fr15 call saved floating point registers */
930
931 #define MAX_REGISTER_NAME_LENGTH 5
932 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
933
934 #define SH_REGISTER_NAMES_INITIALIZER \
935 { \
936 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
937 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
938 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
939 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
940 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
941 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
942 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
943 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
944 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
945 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
946 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
947 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
948 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
949 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
950 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
951 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
952 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
953 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
954 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
955 "rap", "sfp" \
956 }
957
958 #define REGNAMES_ARR_INDEX_1(index) \
959 (sh_register_names[index])
960 #define REGNAMES_ARR_INDEX_2(index) \
961 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
962 #define REGNAMES_ARR_INDEX_4(index) \
963 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
964 #define REGNAMES_ARR_INDEX_8(index) \
965 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
966 #define REGNAMES_ARR_INDEX_16(index) \
967 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
968 #define REGNAMES_ARR_INDEX_32(index) \
969 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
970 #define REGNAMES_ARR_INDEX_64(index) \
971 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
972
973 #define REGISTER_NAMES \
974 { \
975 REGNAMES_ARR_INDEX_64 (0), \
976 REGNAMES_ARR_INDEX_64 (64), \
977 REGNAMES_ARR_INDEX_8 (128), \
978 REGNAMES_ARR_INDEX_8 (136), \
979 REGNAMES_ARR_INDEX_8 (144), \
980 REGNAMES_ARR_INDEX_2 (152) \
981 }
982
983 #define ADDREGNAMES_SIZE 32
984 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
985 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
986 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
987
988 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
989 { \
990 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
991 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
992 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
993 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
994 }
995
996 #define ADDREGNAMES_REGNO(index) \
997 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
998 : (-1))
999
1000 #define ADDREGNAMES_ARR_INDEX_1(index) \
1001 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1002 #define ADDREGNAMES_ARR_INDEX_2(index) \
1003 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1004 #define ADDREGNAMES_ARR_INDEX_4(index) \
1005 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1006 #define ADDREGNAMES_ARR_INDEX_8(index) \
1007 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1008 #define ADDREGNAMES_ARR_INDEX_16(index) \
1009 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1010 #define ADDREGNAMES_ARR_INDEX_32(index) \
1011 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1012
1013 #define ADDITIONAL_REGISTER_NAMES \
1014 { \
1015 ADDREGNAMES_ARR_INDEX_32 (0) \
1016 }
1017
1018 /* Number of actual hardware registers.
1019 The hardware registers are assigned numbers for the compiler
1020 from 0 to just below FIRST_PSEUDO_REGISTER.
1021 All registers that the compiler knows about must be given numbers,
1022 even those that are not normally considered general registers. */
1023
1024 /* There are many other relevant definitions in sh.md's md_constants. */
1025
1026 #define FIRST_GENERAL_REG R0_REG
1027 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1028 #define FIRST_FP_REG DR0_REG
1029 #define LAST_FP_REG (FIRST_FP_REG + \
1030 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1031 #define FIRST_XD_REG XD0_REG
1032 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1033 #define FIRST_TARGET_REG TR0_REG
1034 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1035
1036 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
1037
1038 #define FIRST_BANKED_REG R0_REG
1039 #define LAST_BANKED_REG R7_REG
1040
1041 #define BANKED_REGISTER_P(REGNO) \
1042 IN_RANGE ((REGNO), \
1043 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
1044 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
1045
1046 #define GENERAL_REGISTER_P(REGNO) \
1047 IN_RANGE ((REGNO), \
1048 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1049 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1050
1051 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1052 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1053 || ((REGNO) == FRAME_POINTER_REGNUM))
1054
1055 #define FP_REGISTER_P(REGNO) \
1056 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1057
1058 #define XD_REGISTER_P(REGNO) \
1059 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1060
1061 #define FP_OR_XD_REGISTER_P(REGNO) \
1062 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1063
1064 #define FP_ANY_REGISTER_P(REGNO) \
1065 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1066
1067 #define SPECIAL_REGISTER_P(REGNO) \
1068 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1069 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1070
1071 #define TARGET_REGISTER_P(REGNO) \
1072 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1073
1074 #define SHMEDIA_REGISTER_P(REGNO) \
1075 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1076 || TARGET_REGISTER_P (REGNO))
1077
1078 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1079 that should be fixed. */
1080 #define VALID_REGISTER_P(REGNO) \
1081 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1082 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1083 || (REGNO) == FRAME_POINTER_REGNUM \
1084 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1085 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1086
1087 /* The mode that should be generally used to store a register by
1088 itself in the stack, or to load it back. */
1089 #define REGISTER_NATURAL_MODE(REGNO) \
1090 (FP_REGISTER_P (REGNO) ? SFmode \
1091 : XD_REGISTER_P (REGNO) ? DFmode \
1092 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1093 ? DImode \
1094 : SImode)
1095
1096 #define FIRST_PSEUDO_REGISTER 154
1097
1098 /* Don't count soft frame pointer. */
1099 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1100
1101 /* 1 for registers that have pervasive standard uses
1102 and are not available for the register allocator.
1103
1104 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1105 It is 32 bits wide for SH2. */
1106
1107 #define FIXED_REGISTERS \
1108 { \
1109 /* Regular registers. */ \
1110 0, 0, 0, 0, 0, 0, 0, 0, \
1111 0, 0, 0, 0, 0, 0, 0, 1, \
1112 /* r16 is reserved, r18 is the former pr. */ \
1113 1, 0, 0, 0, 0, 0, 0, 0, \
1114 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1115 /* r26 is a global variable data pointer; r27 is for constants. */ \
1116 1, 1, 1, 1, 0, 0, 0, 0, \
1117 0, 0, 0, 0, 0, 0, 0, 0, \
1118 0, 0, 0, 0, 0, 0, 0, 0, \
1119 0, 0, 0, 0, 0, 0, 0, 0, \
1120 0, 0, 0, 0, 0, 0, 0, 1, \
1121 /* FP registers. */ \
1122 0, 0, 0, 0, 0, 0, 0, 0, \
1123 0, 0, 0, 0, 0, 0, 0, 0, \
1124 0, 0, 0, 0, 0, 0, 0, 0, \
1125 0, 0, 0, 0, 0, 0, 0, 0, \
1126 0, 0, 0, 0, 0, 0, 0, 0, \
1127 0, 0, 0, 0, 0, 0, 0, 0, \
1128 0, 0, 0, 0, 0, 0, 0, 0, \
1129 0, 0, 0, 0, 0, 0, 0, 0, \
1130 /* Branch target registers. */ \
1131 0, 0, 0, 0, 0, 0, 0, 0, \
1132 /* XD registers. */ \
1133 0, 0, 0, 0, 0, 0, 0, 0, \
1134 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1135 1, 1, 1, 1, 1, 1, 0, 1, \
1136 /*"rap", "sfp" */ \
1137 1, 1, \
1138 }
1139
1140 /* 1 for registers not available across function calls.
1141 These must include the FIXED_REGISTERS and also any
1142 registers that can be used without being saved.
1143 The latter must include the registers where values are returned
1144 and the register where structure-value addresses are passed.
1145 Aside from that, you can include as many other registers as you like. */
1146
1147 #define CALL_USED_REGISTERS \
1148 { \
1149 /* Regular registers. */ \
1150 1, 1, 1, 1, 1, 1, 1, 1, \
1151 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1152 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1153 across SH5 function calls. */ \
1154 0, 0, 0, 0, 0, 0, 0, 1, \
1155 1, 1, 1, 1, 1, 1, 1, 1, \
1156 1, 1, 1, 1, 0, 0, 0, 0, \
1157 0, 0, 0, 0, 1, 1, 1, 1, \
1158 1, 1, 1, 1, 0, 0, 0, 0, \
1159 0, 0, 0, 0, 0, 0, 0, 0, \
1160 0, 0, 0, 0, 1, 1, 1, 1, \
1161 /* FP registers. */ \
1162 1, 1, 1, 1, 1, 1, 1, 1, \
1163 1, 1, 1, 1, 0, 0, 0, 0, \
1164 1, 1, 1, 1, 1, 1, 1, 1, \
1165 1, 1, 1, 1, 1, 1, 1, 1, \
1166 1, 1, 1, 1, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 0, 0, 0, 0, 0, 0, 0, 0, \
1170 /* Branch target registers. */ \
1171 1, 1, 1, 1, 1, 0, 0, 0, \
1172 /* XD registers. */ \
1173 1, 1, 1, 1, 1, 1, 0, 0, \
1174 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1175 1, 1, 1, 1, 1, 1, 1, 1, \
1176 /*"rap", "sfp" */ \
1177 1, 1, \
1178 }
1179
1180 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1181 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1182 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1183
1184 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1185 across SHcompact function calls. We can't tell whether a called
1186 function is SHmedia or SHcompact, so we assume it may be when
1187 compiling SHmedia code with the 32-bit ABI, since that's the only
1188 ABI that can be linked with SHcompact code. */
1189 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1190 (TARGET_SHMEDIA32 \
1191 && GET_MODE_SIZE (MODE) > 4 \
1192 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1193 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1194 || TARGET_REGISTER_P (REGNO) \
1195 || (REGNO) == PR_MEDIA_REG))
1196
1197 /* Return number of consecutive hard regs needed starting at reg REGNO
1198 to hold something of mode MODE.
1199 This is ordinarily the length in words of a value of mode MODE
1200 but can be less for certain modes in special long registers.
1201
1202 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1203
1204 #define HARD_REGNO_NREGS(REGNO, MODE) \
1205 (XD_REGISTER_P (REGNO) \
1206 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1207 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1208 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1209 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1210
1211 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1212
1213 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1214 sh_hard_regno_mode_ok ((REGNO), (MODE))
1215
1216 /* Value is 1 if it is a good idea to tie two pseudo registers
1217 when one has mode MODE1 and one has mode MODE2.
1218 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1219 for any hard reg, then this must be 0 for correct output.
1220 That's the case for xd registers: we don't hold SFmode values in
1221 them, so we can't tie an SFmode pseudos with one in another
1222 floating-point mode. */
1223
1224 #define MODES_TIEABLE_P(MODE1, MODE2) \
1225 ((MODE1) == (MODE2) \
1226 || (TARGET_SHMEDIA \
1227 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1228 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1229 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1230 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1231 && (GET_MODE_SIZE (MODE2) <= 4)) \
1232 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1233
1234 /* A C expression that is nonzero if hard register NEW_REG can be
1235 considered for use as a rename register for OLD_REG register */
1236
1237 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1238 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1239
1240 /* Specify the registers used for certain standard purposes.
1241 The values of these macros are register numbers. */
1242
1243 /* Define this if the program counter is overloaded on a register. */
1244 /* #define PC_REGNUM 15*/
1245
1246 /* Register to use for pushing function arguments. */
1247 #define STACK_POINTER_REGNUM SP_REG
1248
1249 /* Base register for access to local variables of the function. */
1250 #define HARD_FRAME_POINTER_REGNUM FP_REG
1251
1252 /* Base register for access to local variables of the function. */
1253 #define FRAME_POINTER_REGNUM 153
1254
1255 /* Fake register that holds the address on the stack of the
1256 current function's return address. */
1257 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1258
1259 /* Register to hold the addressing base for position independent
1260 code access to data items. */
1261 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1262
1263 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1264
1265 /* Definitions for register eliminations.
1266
1267 We have three registers that can be eliminated on the SH. First, the
1268 frame pointer register can often be eliminated in favor of the stack
1269 pointer register. Secondly, the argument pointer register can always be
1270 eliminated; it is replaced with either the stack or frame pointer.
1271 Third, there is the return address pointer, which can also be replaced
1272 with either the stack or the frame pointer. */
1273
1274 /* This is an array of structures. Each structure initializes one pair
1275 of eliminable registers. The "from" register number is given first,
1276 followed by "to". Eliminations of the same "from" register are listed
1277 in order of preference. */
1278
1279 /* If you add any registers here that are not actually hard registers,
1280 and that have any alternative of elimination that doesn't always
1281 apply, you need to amend calc_live_regs to exclude it, because
1282 reload spills all eliminable registers where it sees an
1283 can_eliminate == 0 entry, thus making them 'live' .
1284 If you add any hard registers that can be eliminated in different
1285 ways, you have to patch reload to spill them only when all alternatives
1286 of elimination fail. */
1287
1288 #define ELIMINABLE_REGS \
1289 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1290 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1291 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1292 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1293 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1294 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1295 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1296
1297 /* Given FROM and TO register numbers, say whether this elimination
1298 is allowed. */
1299 #define CAN_ELIMINATE(FROM, TO) \
1300 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1301
1302 /* Define the offset between two registers, one to be eliminated, and the other
1303 its replacement, at the start of a routine. */
1304
1305 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1306 OFFSET = initial_elimination_offset ((FROM), (TO))
1307
1308 /* Base register for access to arguments of the function. */
1309 #define ARG_POINTER_REGNUM AP_REG
1310
1311 /* Register in which the static-chain is passed to a function. */
1312 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1313
1314 /* Don't default to pcc-struct-return, because we have already specified
1315 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1316 target hook. */
1317
1318 #define DEFAULT_PCC_STRUCT_RETURN 0
1319
1320 #define SHMEDIA_REGS_STACK_ADJUST() \
1321 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1322 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1323 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1324 : 0)
1325
1326 \f
1327 /* Define the classes of registers for register constraints in the
1328 machine description. Also define ranges of constants.
1329
1330 One of the classes must always be named ALL_REGS and include all hard regs.
1331 If there is more than one class, another class must be named NO_REGS
1332 and contain no registers.
1333
1334 The name GENERAL_REGS must be the name of a class (or an alias for
1335 another name such as ALL_REGS). This is the class of registers
1336 that is allowed by "g" or "r" in a register constraint.
1337 Also, registers outside this class are allocated only when
1338 instructions express preferences for them.
1339
1340 The classes must be numbered in nondecreasing order; that is,
1341 a larger-numbered class must never be contained completely
1342 in a smaller-numbered class.
1343
1344 For any two classes, it is very desirable that there be another
1345 class that represents their union. */
1346
1347 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1348 be used as the destination of some of the arithmetic ops. There are
1349 also some special purpose registers; the T bit register, the
1350 Procedure Return Register and the Multiply Accumulate Registers. */
1351 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1352 reg_class_subunion. We don't want to have an actual union class
1353 of these, because it would only be used when both classes are calculated
1354 to give the same cost, but there is only one FPUL register.
1355 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1356 applying to the actual instruction alternative considered. E.g., the
1357 y/r alternative of movsi_ie is considered to have no more cost that
1358 the r/r alternative, which is patently untrue. */
1359
1360 enum reg_class
1361 {
1362 NO_REGS,
1363 R0_REGS,
1364 PR_REGS,
1365 T_REGS,
1366 MAC_REGS,
1367 FPUL_REGS,
1368 SIBCALL_REGS,
1369 GENERAL_REGS,
1370 FP0_REGS,
1371 FP_REGS,
1372 DF_HI_REGS,
1373 DF_REGS,
1374 FPSCR_REGS,
1375 GENERAL_FP_REGS,
1376 GENERAL_DF_REGS,
1377 TARGET_REGS,
1378 ALL_REGS,
1379 LIM_REG_CLASSES
1380 };
1381
1382 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1383
1384 /* Give names of register classes as strings for dump file. */
1385 #define REG_CLASS_NAMES \
1386 { \
1387 "NO_REGS", \
1388 "R0_REGS", \
1389 "PR_REGS", \
1390 "T_REGS", \
1391 "MAC_REGS", \
1392 "FPUL_REGS", \
1393 "SIBCALL_REGS", \
1394 "GENERAL_REGS", \
1395 "FP0_REGS", \
1396 "FP_REGS", \
1397 "DF_HI_REGS", \
1398 "DF_REGS", \
1399 "FPSCR_REGS", \
1400 "GENERAL_FP_REGS", \
1401 "GENERAL_DF_REGS", \
1402 "TARGET_REGS", \
1403 "ALL_REGS", \
1404 }
1405
1406 /* Define which registers fit in which classes.
1407 This is an initializer for a vector of HARD_REG_SET
1408 of length N_REG_CLASSES. */
1409
1410 #define REG_CLASS_CONTENTS \
1411 { \
1412 /* NO_REGS: */ \
1413 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1414 /* R0_REGS: */ \
1415 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1416 /* PR_REGS: */ \
1417 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1418 /* T_REGS: */ \
1419 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1420 /* MAC_REGS: */ \
1421 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1422 /* FPUL_REGS: */ \
1423 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1424 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1425 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1426 /* GENERAL_REGS: */ \
1427 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1428 /* FP0_REGS: */ \
1429 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1430 /* FP_REGS: */ \
1431 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1432 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1433 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1434 /* DF_REGS: */ \
1435 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1436 /* FPSCR_REGS: */ \
1437 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1438 /* GENERAL_FP_REGS: */ \
1439 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1440 /* GENERAL_DF_REGS: */ \
1441 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1442 /* TARGET_REGS: */ \
1443 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1444 /* ALL_REGS: */ \
1445 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1446 }
1447
1448 /* The same information, inverted:
1449 Return the class number of the smallest class containing
1450 reg number REGNO. This could be a conditional expression
1451 or could index an array. */
1452
1453 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1454 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1455
1456 /* The following macro defines cover classes for Integrated Register
1457 Allocator. Cover classes is a set of non-intersected register
1458 classes covering all hard registers used for register allocation
1459 purpose. Any move between two registers of a cover class should be
1460 cheaper than load or store of the registers. The macro value is
1461 array of register classes with LIM_REG_CLASSES used as the end
1462 marker. */
1463
1464 #define IRA_COVER_CLASSES \
1465 { \
1466 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1467 FPUL_REGS, LIM_REG_CLASSES \
1468 }
1469
1470 /* When defined, the compiler allows registers explicitly used in the
1471 rtl to be used as spill registers but prevents the compiler from
1472 extending the lifetime of these registers. */
1473
1474 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1475
1476 /* The order in which register should be allocated. */
1477 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1478 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1479 spilled or used otherwise, we better have the FP_REGS allocated first. */
1480 #define REG_ALLOC_ORDER \
1481 {/* Caller-saved FPRs */ \
1482 65, 66, 67, 68, 69, 70, 71, 64, \
1483 72, 73, 74, 75, 80, 81, 82, 83, \
1484 84, 85, 86, 87, 88, 89, 90, 91, \
1485 92, 93, 94, 95, 96, 97, 98, 99, \
1486 /* Callee-saved FPRs */ \
1487 76, 77, 78, 79,100,101,102,103, \
1488 104,105,106,107,108,109,110,111, \
1489 112,113,114,115,116,117,118,119, \
1490 120,121,122,123,124,125,126,127, \
1491 136,137,138,139,140,141,142,143, \
1492 /* FPSCR */ 151, \
1493 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1494 1, 2, 3, 7, 6, 5, 4, 0, \
1495 8, 9, 17, 19, 20, 21, 22, 23, \
1496 36, 37, 38, 39, 40, 41, 42, 43, \
1497 60, 61, 62, \
1498 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1499 10, 11, 12, 13, 14, 18, \
1500 /* SH5 callee-saved GPRs */ \
1501 28, 29, 30, 31, 32, 33, 34, 35, \
1502 44, 45, 46, 47, 48, 49, 50, 51, \
1503 52, 53, 54, 55, 56, 57, 58, 59, \
1504 /* FPUL */ 150, \
1505 /* SH5 branch target registers */ \
1506 128,129,130,131,132,133,134,135, \
1507 /* Fixed registers */ \
1508 15, 16, 24, 25, 26, 27, 63,144, \
1509 145,146,147,148,149,152,153 }
1510
1511 /* The class value for index registers, and the one for base regs. */
1512 #define INDEX_REG_CLASS \
1513 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1514 #define BASE_REG_CLASS GENERAL_REGS
1515 \f
1516 /* Defines for sh.md and constraints.md. */
1517
1518 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1519 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1520 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1521 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1522 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1523 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1524 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1525 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1526
1527 #define CONST_OK_FOR_J16(VALUE) \
1528 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1529 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1530
1531 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1532 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1533
1534 /* Given an rtx X being reloaded into a reg required to be
1535 in class CLASS, return the class of reg to actually use.
1536 In general this is just CLASS; but on some machines
1537 in some cases it is preferable to use a more restrictive class. */
1538
1539 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1540 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1541 && (GET_CODE (X) == CONST_DOUBLE \
1542 || GET_CODE (X) == SYMBOL_REF \
1543 || PIC_ADDR_P (X)) \
1544 ? GENERAL_REGS \
1545 : (CLASS)) \
1546
1547 #if 0
1548 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1549 ((((REGCLASS_HAS_FP_REG (CLASS) \
1550 && (GET_CODE (X) == REG \
1551 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1552 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1553 && TARGET_FMOVD)))) \
1554 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1555 && GET_CODE (X) == REG \
1556 && FP_REGISTER_P (REGNO (X)))) \
1557 && ! TARGET_SHMEDIA \
1558 && ((MODE) == SFmode || (MODE) == SImode)) \
1559 ? FPUL_REGS \
1560 : (((CLASS) == FPUL_REGS \
1561 || (REGCLASS_HAS_FP_REG (CLASS) \
1562 && ! TARGET_SHMEDIA && MODE == SImode)) \
1563 && (GET_CODE (X) == MEM \
1564 || (GET_CODE (X) == REG \
1565 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1566 || REGNO (X) == T_REG \
1567 || system_reg_operand (X, VOIDmode))))) \
1568 ? GENERAL_REGS \
1569 : (((CLASS) == TARGET_REGS \
1570 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1571 && !satisfies_constraint_Csy (X) \
1572 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1573 ? GENERAL_REGS \
1574 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1575 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1576 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1577 ? GENERAL_REGS \
1578 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1579 && TARGET_REGISTER_P (REGNO (X))) \
1580 ? GENERAL_REGS : (ELSE))
1581
1582 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1583 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1584
1585 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1586 ((REGCLASS_HAS_FP_REG (CLASS) \
1587 && ! TARGET_SHMEDIA \
1588 && immediate_operand ((X), (MODE)) \
1589 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1590 && (MODE) == SFmode && fldi_ok ())) \
1591 ? R0_REGS \
1592 : ((CLASS) == FPUL_REGS \
1593 && ((GET_CODE (X) == REG \
1594 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1595 || REGNO (X) == T_REG)) \
1596 || GET_CODE (X) == PLUS)) \
1597 ? GENERAL_REGS \
1598 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1599 ? (satisfies_constraint_I08 (X) \
1600 ? GENERAL_REGS \
1601 : R0_REGS) \
1602 : ((CLASS) == FPSCR_REGS \
1603 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1604 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1605 ? GENERAL_REGS \
1606 : (REGCLASS_HAS_FP_REG (CLASS) \
1607 && TARGET_SHMEDIA \
1608 && immediate_operand ((X), (MODE)) \
1609 && (X) != CONST0_RTX (GET_MODE (X)) \
1610 && GET_MODE (X) != V4SFmode) \
1611 ? GENERAL_REGS \
1612 : (((MODE) == QImode || (MODE) == HImode) \
1613 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1614 ? GENERAL_REGS \
1615 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1616 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1617 ? TARGET_REGS \
1618 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1619 #endif
1620
1621 /* Return the maximum number of consecutive registers
1622 needed to represent mode MODE in a register of class CLASS.
1623
1624 If TARGET_SHMEDIA, we need two FP registers per word.
1625 Otherwise we will need at most one register per word. */
1626 #define CLASS_MAX_NREGS(CLASS, MODE) \
1627 (TARGET_SHMEDIA \
1628 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1629 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1630 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1631
1632 /* If defined, gives a class of registers that cannot be used as the
1633 operand of a SUBREG that changes the mode of the object illegally. */
1634 /* ??? We need to renumber the internal numbers for the frnn registers
1635 when in little endian in order to allow mode size changes. */
1636
1637 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1638 sh_cannot_change_mode_class (FROM, TO, CLASS)
1639 \f
1640 /* Stack layout; function entry, exit and calling. */
1641
1642 /* Define the number of registers that can hold parameters.
1643 These macros are used only in other macro definitions below. */
1644
1645 #define NPARM_REGS(MODE) \
1646 (TARGET_FPU_ANY && (MODE) == SFmode \
1647 ? (TARGET_SH5 ? 12 : 8) \
1648 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1649 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1650 ? (TARGET_SH5 ? 12 : 8) \
1651 : (TARGET_SH5 ? 8 : 4))
1652
1653 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1654 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1655
1656 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1657 #define FIRST_FP_RET_REG FIRST_FP_REG
1658
1659 /* Define this if pushing a word on the stack
1660 makes the stack pointer a smaller address. */
1661 #define STACK_GROWS_DOWNWARD
1662
1663 /* Define this macro to nonzero if the addresses of local variable slots
1664 are at negative offsets from the frame pointer. */
1665 #define FRAME_GROWS_DOWNWARD 1
1666
1667 /* Offset from the frame pointer to the first local variable slot to
1668 be allocated. */
1669 #define STARTING_FRAME_OFFSET 0
1670
1671 /* If we generate an insn to push BYTES bytes,
1672 this says how many the stack pointer really advances by. */
1673 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1674 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1675 do correct alignment. */
1676 #if 0
1677 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1678 #endif
1679
1680 /* Offset of first parameter from the argument pointer register value. */
1681 #define FIRST_PARM_OFFSET(FNDECL) 0
1682
1683 /* Value is the number of byte of arguments automatically
1684 popped when returning from a subroutine call.
1685 FUNDECL is the declaration node of the function (as a tree),
1686 FUNTYPE is the data type of the function (as a tree),
1687 or for a library call it is an identifier node for the subroutine name.
1688 SIZE is the number of bytes of arguments passed on the stack.
1689
1690 On the SH, the caller does not pop any of its arguments that were passed
1691 on the stack. */
1692 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1693
1694 /* Value is the number of bytes of arguments automatically popped when
1695 calling a subroutine.
1696 CUM is the accumulated argument list.
1697
1698 On SHcompact, the call trampoline pops arguments off the stack. */
1699 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1700
1701 /* Some subroutine macros specific to this machine. */
1702
1703 #define BASE_RETURN_VALUE_REG(MODE) \
1704 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1705 ? FIRST_FP_RET_REG \
1706 : TARGET_FPU_ANY && (MODE) == SCmode \
1707 ? FIRST_FP_RET_REG \
1708 : (TARGET_FPU_DOUBLE \
1709 && ((MODE) == DFmode || (MODE) == SFmode \
1710 || (MODE) == DCmode || (MODE) == SCmode )) \
1711 ? FIRST_FP_RET_REG \
1712 : FIRST_RET_REG)
1713
1714 #define BASE_ARG_REG(MODE) \
1715 ((TARGET_SH2E && ((MODE) == SFmode)) \
1716 ? FIRST_FP_PARM_REG \
1717 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1718 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1719 ? FIRST_FP_PARM_REG \
1720 : FIRST_PARM_REG)
1721
1722 /* Define how to find the value returned by a function.
1723 VALTYPE is the data type of the value (as a tree).
1724 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1725 otherwise, FUNC is 0.
1726 For the SH, this is like LIBCALL_VALUE, except that we must change the
1727 mode like PROMOTE_MODE does.
1728 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1729 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1730
1731 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1732 gen_rtx_REG ( \
1733 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1734 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1735 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1736 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1737 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1738 || TREE_CODE (VALTYPE) == REAL_TYPE \
1739 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1740 && sh_promote_prototypes (FUNC) \
1741 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1742 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1743
1744 /* Define how to find the value returned by a library function
1745 assuming the value has mode MODE. */
1746 #define LIBCALL_VALUE(MODE) \
1747 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1748
1749 /* 1 if N is a possible register number for a function value. */
1750 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1751 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1752 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1753
1754 /* 1 if N is a possible register number for function argument passing. */
1755 /* ??? There are some callers that pass REGNO as int, and others that pass
1756 it as unsigned. We get warnings unless we do casts everywhere. */
1757 #define FUNCTION_ARG_REGNO_P(REGNO) \
1758 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1759 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1760 || (TARGET_FPU_ANY \
1761 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1762 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1763 + NPARM_REGS (SFmode))))
1764 \f
1765 /* Define a data type for recording info about an argument list
1766 during the scan of that argument list. This data type should
1767 hold all necessary information about the function itself
1768 and about the args processed so far, enough to enable macros
1769 such as FUNCTION_ARG to determine where the next arg should go.
1770
1771 On SH, this is a single integer, which is a number of words
1772 of arguments scanned so far (including the invisible argument,
1773 if any, which holds the structure-value-address).
1774 Thus NARGREGS or more means all following args should go on the stack. */
1775
1776 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1777 struct sh_args {
1778 int arg_count[2];
1779 int force_mem;
1780 /* Nonzero if a prototype is available for the function. */
1781 int prototype_p;
1782 /* The number of an odd floating-point register, that should be used
1783 for the next argument of type float. */
1784 int free_single_fp_reg;
1785 /* Whether we're processing an outgoing function call. */
1786 int outgoing;
1787 /* The number of general-purpose registers that should have been
1788 used to pass partial arguments, that are passed totally on the
1789 stack. On SHcompact, a call trampoline will pop them off the
1790 stack before calling the actual function, and, if the called
1791 function is implemented in SHcompact mode, the incoming arguments
1792 decoder will push such arguments back onto the stack. For
1793 incoming arguments, STACK_REGS also takes into account other
1794 arguments passed by reference, that the decoder will also push
1795 onto the stack. */
1796 int stack_regs;
1797 /* The number of general-purpose registers that should have been
1798 used to pass arguments, if the arguments didn't have to be passed
1799 by reference. */
1800 int byref_regs;
1801 /* Set as by shcompact_byref if the current argument is to be passed
1802 by reference. */
1803 int byref;
1804
1805 /* call_cookie is a bitmask used by call expanders, as well as
1806 function prologue and epilogues, to allow SHcompact to comply
1807 with the SH5 32-bit ABI, that requires 64-bit registers to be
1808 used even though only the lower 32-bit half is visible in
1809 SHcompact mode. The strategy is to call SHmedia trampolines.
1810
1811 The alternatives for each of the argument-passing registers are
1812 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1813 contents from the address in it; (d) add 8 to it, storing the
1814 result in the next register, then (c); (e) copy it from some
1815 floating-point register,
1816
1817 Regarding copies from floating-point registers, r2 may only be
1818 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1819 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1820 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1821 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1822 dr10.
1823
1824 The bit mask is structured as follows:
1825
1826 - 1 bit to tell whether to set up a return trampoline.
1827
1828 - 3 bits to count the number consecutive registers to pop off the
1829 stack.
1830
1831 - 4 bits for each of r9, r8, r7 and r6.
1832
1833 - 3 bits for each of r5, r4, r3 and r2.
1834
1835 - 3 bits set to 0 (the most significant ones)
1836
1837 3 2 1 0
1838 1098 7654 3210 9876 5432 1098 7654 3210
1839 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1840 2223 3344 4555 6666 7777 8888 9999 SSS-
1841
1842 - If F is set, the register must be copied from an FP register,
1843 whose number is encoded in the remaining bits.
1844
1845 - Else, if L is set, the register must be loaded from the address
1846 contained in it. If the P bit is *not* set, the address of the
1847 following dword should be computed first, and stored in the
1848 following register.
1849
1850 - Else, if P is set, the register alone should be popped off the
1851 stack.
1852
1853 - After all this processing, the number of registers represented
1854 in SSS will be popped off the stack. This is an optimization
1855 for pushing/popping consecutive registers, typically used for
1856 varargs and large arguments partially passed in registers.
1857
1858 - If T is set, a return trampoline will be set up for 64-bit
1859 return values to be split into 2 32-bit registers. */
1860 long call_cookie;
1861
1862 /* This is set to nonzero when the call in question must use the Renesas ABI,
1863 even without the -mrenesas option. */
1864 int renesas_abi;
1865 };
1866
1867 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1868 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1869 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1870 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1871 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1872 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1873 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1874 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1875 #define CALL_COOKIE_INT_REG(REG, VAL) \
1876 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1877 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1878 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1879
1880 #define CUMULATIVE_ARGS struct sh_args
1881
1882 #define GET_SH_ARG_CLASS(MODE) \
1883 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1884 ? SH_ARG_FLOAT \
1885 /* There's no mention of complex float types in the SH5 ABI, so we
1886 should presumably handle them as aggregate types. */ \
1887 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1888 ? SH_ARG_INT \
1889 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1890 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1891 ? SH_ARG_FLOAT : SH_ARG_INT)
1892
1893 #define ROUND_ADVANCE(SIZE) \
1894 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1895
1896 /* Round a register number up to a proper boundary for an arg of mode
1897 MODE.
1898
1899 The SH doesn't care about double alignment, so we only
1900 round doubles to even regs when asked to explicitly. */
1901
1902 #define ROUND_REG(CUM, MODE) \
1903 (((TARGET_ALIGN_DOUBLE \
1904 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1905 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1906 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1907 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1908 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1909 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1910
1911 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1912 for a call to a function whose data type is FNTYPE.
1913 For a library call, FNTYPE is 0.
1914
1915 On SH, the offset always starts at 0: the first parm reg is always
1916 the same reg for a given argument class.
1917
1918 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1919
1920 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1921 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1922
1923 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1924 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1925
1926 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1927 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1928 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1929 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1930
1931 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1932 This macro is only used in this file. */
1933
1934 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1935 (((TYPE) == 0 \
1936 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1937 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1938 || ! (AGGREGATE_TYPE_P (TYPE) \
1939 || (!TARGET_FPU_ANY \
1940 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1941 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1942 && ! (CUM).force_mem \
1943 && (TARGET_SH2E \
1944 ? ((MODE) == BLKmode \
1945 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1946 + int_size_in_bytes (TYPE)) \
1947 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1948 : ((ROUND_REG((CUM), (MODE)) \
1949 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1950 <= NPARM_REGS (MODE))) \
1951 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1952
1953 /* By accident we got stuck with passing SCmode on SH4 little endian
1954 in two registers that are nominally successive - which is different from
1955 two single SFmode values, where we take endianness translation into
1956 account. That does not work at all if an odd number of registers is
1957 already in use, so that got fixed, but library functions are still more
1958 likely to use complex numbers without mixing them with SFmode arguments
1959 (which in C would have to be structures), so for the sake of ABI
1960 compatibility the way SCmode values are passed when an even number of
1961 FP registers is in use remains different from a pair of SFmode values for
1962 now.
1963 I.e.:
1964 foo (double); a: fr5,fr4
1965 foo (float a, float b); a: fr5 b: fr4
1966 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1967 this should be the other way round...
1968 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1969 #define FUNCTION_ARG_SCmode_WART 1
1970
1971 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1972 register in SHcompact mode, it must be padded in the most
1973 significant end. This means that passing it by reference wouldn't
1974 pad properly on a big-endian machine. In this particular case, we
1975 pass this argument on the stack, in a way that the call trampoline
1976 will load its value into the appropriate register. */
1977 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1978 ((MODE) == BLKmode \
1979 && TARGET_SHCOMPACT \
1980 && ! TARGET_LITTLE_ENDIAN \
1981 && int_size_in_bytes (TYPE) > 4 \
1982 && int_size_in_bytes (TYPE) < 8)
1983
1984 /* Minimum alignment for an argument to be passed by callee-copy
1985 reference. We need such arguments to be aligned to 8 byte
1986 boundaries, because they'll be loaded using quad loads. */
1987 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1988
1989 /* The SH5 ABI requires floating-point arguments to be passed to
1990 functions without a prototype in both an FP register and a regular
1991 register or the stack. When passing the argument in both FP and
1992 general-purpose registers, list the FP register first. */
1993 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1994 (gen_rtx_PARALLEL \
1995 ((MODE), \
1996 gen_rtvec (2, \
1997 gen_rtx_EXPR_LIST \
1998 (VOIDmode, \
1999 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2000 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2001 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2002 : NULL_RTX), \
2003 const0_rtx), \
2004 gen_rtx_EXPR_LIST \
2005 (VOIDmode, \
2006 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2007 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2008 + (CUM).arg_count[(int) SH_ARG_INT]) \
2009 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2010 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2011 const0_rtx))))
2012
2013 /* The SH5 ABI requires regular registers or stack slots to be
2014 reserved for floating-point arguments. Registers are taken care of
2015 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2016 Unfortunately, there's no way to just reserve a stack slot, so
2017 we'll end up needlessly storing a copy of the argument in the
2018 stack. For incoming arguments, however, the PARALLEL will be
2019 optimized to the register-only form, and the value in the stack
2020 slot won't be used at all. */
2021 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2022 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2023 ? gen_rtx_REG ((MODE), (REG)) \
2024 : gen_rtx_PARALLEL ((MODE), \
2025 gen_rtvec (2, \
2026 gen_rtx_EXPR_LIST \
2027 (VOIDmode, NULL_RTX, \
2028 const0_rtx), \
2029 gen_rtx_EXPR_LIST \
2030 (VOIDmode, gen_rtx_REG ((MODE), \
2031 (REG)), \
2032 const0_rtx))))
2033
2034 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2035 (TARGET_SH5 \
2036 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2037 || (MODE) == DCmode) \
2038 && ((CUM).arg_count[(int) SH_ARG_INT] \
2039 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2040 : GET_MODE_SIZE (MODE)) \
2041 + 7) / 8) > NPARM_REGS (SImode))
2042
2043 /* Perform any needed actions needed for a function that is receiving a
2044 variable number of arguments. */
2045
2046 /* Call the function profiler with a given profile label.
2047 We use two .aligns, so as to make sure that both the .long is aligned
2048 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2049 from the trapa instruction. */
2050
2051 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2052 { \
2053 if (TARGET_SHMEDIA) \
2054 { \
2055 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2056 fprintf((STREAM), "\ttrapa\tr0\n"); \
2057 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2058 } \
2059 else \
2060 { \
2061 fprintf((STREAM), "\t.align\t2\n"); \
2062 fprintf((STREAM), "\ttrapa\t#33\n"); \
2063 fprintf((STREAM), "\t.align\t2\n"); \
2064 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2065 } \
2066 }
2067
2068 /* Define this macro if the code for function profiling should come
2069 before the function prologue. Normally, the profiling code comes
2070 after. */
2071
2072 #define PROFILE_BEFORE_PROLOGUE
2073
2074 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2075 the stack pointer does not matter. The value is tested only in
2076 functions that have frame pointers.
2077 No definition is equivalent to always zero. */
2078
2079 #define EXIT_IGNORE_STACK 1
2080
2081 /*
2082 On the SH, the trampoline looks like
2083 2 0002 D202 mov.l l2,r2
2084 1 0000 D301 mov.l l1,r3
2085 3 0004 422B jmp @r2
2086 4 0006 0009 nop
2087 5 0008 00000000 l1: .long area
2088 6 000c 00000000 l2: .long function */
2089
2090 /* Length in units of the trampoline for entering a nested function. */
2091 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2092
2093 /* Alignment required for a trampoline in bits . */
2094 #define TRAMPOLINE_ALIGNMENT \
2095 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2096 : TARGET_SHMEDIA ? 256 : 64)
2097
2098 /* Emit RTL insns to initialize the variable parts of a trampoline.
2099 FNADDR is an RTX for the address of the function's pure code.
2100 CXT is an RTX for the static chain value for the function. */
2101
2102 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2103 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2104
2105 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2106
2107 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2108 { \
2109 if (TARGET_SHMEDIA) \
2110 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2111 gen_reg_rtx (Pmode), 0, \
2112 OPTAB_LIB_WIDEN); \
2113 } while (0)
2114
2115 /* A C expression whose value is RTL representing the value of the return
2116 address for the frame COUNT steps up from the current frame.
2117 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2118 can ignore COUNT. */
2119
2120 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2121 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2122
2123 /* A C expression whose value is RTL representing the location of the
2124 incoming return address at the beginning of any function, before the
2125 prologue. This RTL is either a REG, indicating that the return
2126 value is saved in REG, or a MEM representing a location in
2127 the stack. */
2128 #define INCOMING_RETURN_ADDR_RTX \
2129 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2130 \f
2131 /* Addressing modes, and classification of registers for them. */
2132 #define HAVE_POST_INCREMENT TARGET_SH1
2133 #define HAVE_PRE_DECREMENT TARGET_SH1
2134
2135 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2136 ? 0 : TARGET_SH1)
2137 #define USE_LOAD_PRE_DECREMENT(mode) 0
2138 #define USE_STORE_POST_INCREMENT(mode) 0
2139 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2140 ? 0 : TARGET_SH1)
2141
2142 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2143 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2144 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2145
2146 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2147 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2148 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2149
2150 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
2151
2152 /* Macros to check register numbers against specific register classes. */
2153
2154 /* These assume that REGNO is a hard or pseudo reg number.
2155 They give nonzero only if REGNO is a hard reg of the suitable class
2156 or a pseudo reg currently allocated to a suitable hard reg.
2157 Since they use reg_renumber, they are safe only once reg_renumber
2158 has been allocated, which happens in local-alloc.c. */
2159
2160 #define REGNO_OK_FOR_BASE_P(REGNO) \
2161 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2162 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2163 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2164 (TARGET_SHMEDIA \
2165 ? (GENERAL_REGISTER_P (REGNO) \
2166 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2167 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2168
2169 /* Maximum number of registers that can appear in a valid memory
2170 address. */
2171
2172 #define MAX_REGS_PER_ADDRESS 2
2173
2174 /* Recognize any constant value that is a valid address. */
2175
2176 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2177
2178 /* Nonzero if the constant value X is a legitimate general operand. */
2179 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2180
2181 #define LEGITIMATE_CONSTANT_P(X) \
2182 (TARGET_SHMEDIA \
2183 ? ((GET_MODE (X) != DFmode \
2184 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2185 || (X) == CONST0_RTX (GET_MODE (X)) \
2186 || ! TARGET_SHMEDIA_FPU \
2187 || TARGET_SHMEDIA64) \
2188 : (GET_CODE (X) != CONST_DOUBLE \
2189 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2190 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2191
2192 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2193 and check its validity for a certain class.
2194 The suitable hard regs are always accepted and all pseudo regs
2195 are also accepted if STRICT is not set. */
2196
2197 /* Nonzero if X is a reg that can be used as a base reg. */
2198 #define REG_OK_FOR_BASE_P(X, STRICT) \
2199 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
2200 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
2201
2202 /* Nonzero if X is a reg that can be used as an index. */
2203 #define REG_OK_FOR_INDEX_P(X, STRICT) \
2204 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2205 : REGNO (X) == R0_REG) \
2206 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
2207
2208 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
2209 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
2210 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2211 : REGNO (X) == R0_REG && OFFSET == 0) \
2212 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
2213
2214 /* Macros for extra constraints. */
2215
2216 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2217 ((GET_CODE ((OP)) == LABEL_REF) \
2218 || (GET_CODE ((OP)) == CONST \
2219 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2220 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2221 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2222
2223 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2224 (CONSTANT_P (OP) \
2225 && GET_CODE (OP) != CONST_INT \
2226 && GET_CODE (OP) != CONST_DOUBLE \
2227 && (!flag_pic \
2228 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2229 && !PIC_ADDR_P (OP) \
2230 && GET_CODE (OP) != LABEL_REF)))
2231
2232 /* Check whether OP is a datalabel unspec. */
2233 #define DATALABEL_REF_NO_CONST_P(OP) \
2234 (GET_CODE (OP) == UNSPEC \
2235 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2236 && XVECLEN ((OP), 0) == 1 \
2237 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2238
2239 #define GOT_ENTRY_P(OP) \
2240 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2241 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2242
2243 #define GOTPLT_ENTRY_P(OP) \
2244 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2245 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2246
2247 #define UNSPEC_GOTOFF_P(OP) \
2248 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2249
2250 #define GOTOFF_P(OP) \
2251 (GET_CODE (OP) == CONST \
2252 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2253 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2254 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2255 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2256
2257 #define PIC_ADDR_P(OP) \
2258 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2259 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2260
2261 #define PCREL_SYMOFF_P(OP) \
2262 (GET_CODE (OP) == CONST \
2263 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2264 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
2265
2266 #define NON_PIC_REFERENCE_P(OP) \
2267 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2268 || (GET_CODE (OP) == CONST \
2269 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2270 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2271 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2272 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2273 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2274 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2275 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2276 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2277
2278 #define PIC_REFERENCE_P(OP) \
2279 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2280 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2281
2282 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2283 (flag_pic \
2284 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2285 || PCREL_SYMOFF_P (OP)) \
2286 : NON_PIC_REFERENCE_P (OP))
2287 \f
2288 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
2289 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X, STRICT)) \
2290 || (GET_CODE (X) == SUBREG \
2291 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2292 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2293 && GET_CODE (SUBREG_REG (X)) == REG \
2294 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
2295
2296 /* Since this must be r0, which is a single register class, we must check
2297 SUBREGs more carefully, to be sure that we don't accept one that extends
2298 outside the class. */
2299 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
2300 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X, STRICT)) \
2301 || (GET_CODE (X) == SUBREG \
2302 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2303 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2304 && GET_CODE (SUBREG_REG (X)) == REG \
2305 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
2306
2307 #ifdef REG_OK_STRICT
2308 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
2309 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
2310 #else
2311 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
2312 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
2313 #endif
2314
2315 #define ALLOW_INDEXED_ADDRESS \
2316 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2317
2318 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
2319 do { \
2320 if (sh_legitimate_index_p ((MODE), (OP))) \
2321 goto WIN; \
2322 } while (0)
2323 \f
2324 /* A C compound statement that attempts to replace X, which is an address
2325 that needs reloading, with a valid memory address for an operand of
2326 mode MODE. WIN is a C statement label elsewhere in the code.
2327
2328 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2329 of the address. That will allow inheritance of the address reloads. */
2330
2331 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2332 { \
2333 if (GET_CODE (X) == PLUS \
2334 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2335 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2336 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2337 && ! TARGET_SHMEDIA \
2338 && ! (TARGET_SH4 && (MODE) == DFmode) \
2339 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2340 && (ALLOW_INDEXED_ADDRESS \
2341 || XEXP ((X), 0) == stack_pointer_rtx \
2342 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2343 { \
2344 rtx index_rtx = XEXP (X, 1); \
2345 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2346 rtx sum; \
2347 \
2348 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2349 { \
2350 push_reload (X, NULL_RTX, &X, NULL, \
2351 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2352 (TYPE)); \
2353 goto WIN; \
2354 } \
2355 if (TARGET_SH2E && MODE == SFmode) \
2356 { \
2357 X = copy_rtx (X); \
2358 push_reload (X, NULL_RTX, &X, NULL, \
2359 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2360 (TYPE)); \
2361 goto WIN; \
2362 } \
2363 /* Instead of offset_base 128..131 use 124..127, so that \
2364 simple add suffices. */ \
2365 if (offset > 127) \
2366 { \
2367 offset_base = ((offset + 4) & ~60) - 4; \
2368 } \
2369 else \
2370 offset_base = offset & ~60; \
2371 /* Sometimes the normal form does not suit DImode. We \
2372 could avoid that by using smaller ranges, but that \
2373 would give less optimized code when SImode is \
2374 prevalent. */ \
2375 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2376 { \
2377 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2378 GEN_INT (offset_base)); \
2379 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2380 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2381 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2382 (TYPE)); \
2383 goto WIN; \
2384 } \
2385 } \
2386 /* We must re-recognize what we created before. */ \
2387 else if (GET_CODE (X) == PLUS \
2388 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2389 && GET_CODE (XEXP (X, 0)) == PLUS \
2390 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2391 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2392 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2393 && ! TARGET_SHMEDIA \
2394 && ! (TARGET_SH2E && MODE == SFmode)) \
2395 { \
2396 /* Because this address is so complex, we know it must have \
2397 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2398 it is already unshared, and needs no further unsharing. */ \
2399 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2400 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2401 goto WIN; \
2402 } \
2403 }
2404 \f
2405 /* Specify the machine mode that this machine uses
2406 for the index in the tablejump instruction. */
2407 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2408
2409 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2410 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2411 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2412 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2413 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2414 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2415 : SImode)
2416
2417 /* Define as C expression which evaluates to nonzero if the tablejump
2418 instruction expects the table to contain offsets from the address of the
2419 table.
2420 Do not define this if the table should contain absolute addresses. */
2421 #define CASE_VECTOR_PC_RELATIVE 1
2422
2423 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2424 #define FLOAT_TYPE_SIZE 32
2425
2426 /* Since the SH2e has only `float' support, it is desirable to make all
2427 floating point types equivalent to `float'. */
2428 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2429
2430 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2431 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2432 #else
2433 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2434 #endif
2435
2436 /* 'char' is signed by default. */
2437 #define DEFAULT_SIGNED_CHAR 1
2438
2439 /* The type of size_t unsigned int. */
2440 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2441
2442 #undef PTRDIFF_TYPE
2443 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2444
2445 #define WCHAR_TYPE "short unsigned int"
2446 #define WCHAR_TYPE_SIZE 16
2447
2448 #define SH_ELF_WCHAR_TYPE "long int"
2449
2450 /* Max number of bytes we can move from memory to memory
2451 in one reasonably fast instruction. */
2452 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2453
2454 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2455 MOVE_MAX is not a compile-time constant. */
2456 #define MAX_MOVE_MAX 8
2457
2458 /* Max number of bytes we want move_by_pieces to be able to copy
2459 efficiently. */
2460 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2461
2462 /* Define if operations between registers always perform the operation
2463 on the full register even if a narrower mode is specified. */
2464 #define WORD_REGISTER_OPERATIONS
2465
2466 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2467 will either zero-extend or sign-extend. The value of this macro should
2468 be the code that says which one of the two operations is implicitly
2469 done, UNKNOWN if none. */
2470 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2471 /* FP registers can load SImode values, but don't implicitly sign-extend
2472 them to DImode. */
2473 #define LOAD_EXTEND_OP(MODE) \
2474 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2475 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2476
2477 /* Define if loading short immediate values into registers sign extends. */
2478 #define SHORT_IMMEDIATES_SIGN_EXTEND
2479
2480 /* Nonzero if access to memory by bytes is no faster than for words. */
2481 #define SLOW_BYTE_ACCESS 1
2482
2483 /* Immediate shift counts are truncated by the output routines (or was it
2484 the assembler?). Shift counts in a register are truncated by SH. Note
2485 that the native compiler puts too large (> 32) immediate shift counts
2486 into a register and shifts by the register, letting the SH decide what
2487 to do instead of doing that itself. */
2488 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2489 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2490 expects - the sign bit is significant - so it appears that we need to
2491 leave this zero for correct SH3 code. */
2492 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2493
2494 /* All integers have the same format so truncation is easy. */
2495 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2496 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2497 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2498
2499 /* Define this if addresses of constant functions
2500 shouldn't be put through pseudo regs where they can be cse'd.
2501 Desirable on machines where ordinary constants are expensive
2502 but a CALL with constant address is cheap. */
2503 /*#define NO_FUNCTION_CSE 1*/
2504
2505 /* The machine modes of pointers and functions. */
2506 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2507 #define FUNCTION_MODE Pmode
2508
2509 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2510 are actually function calls with some special constraints on arguments
2511 and register usage.
2512
2513 These macros tell reorg that the references to arguments and
2514 register clobbers for insns of type sfunc do not appear to happen
2515 until after the millicode call. This allows reorg to put insns
2516 which set the argument registers into the delay slot of the millicode
2517 call -- thus they act more like traditional CALL_INSNs.
2518
2519 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2520 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2521 in particular. */
2522
2523 #define INSN_SETS_ARE_DELAYED(X) \
2524 ((GET_CODE (X) == INSN \
2525 && GET_CODE (PATTERN (X)) != SEQUENCE \
2526 && GET_CODE (PATTERN (X)) != USE \
2527 && GET_CODE (PATTERN (X)) != CLOBBER \
2528 && get_attr_is_sfunc (X)))
2529
2530 #define INSN_REFERENCES_ARE_DELAYED(X) \
2531 ((GET_CODE (X) == INSN \
2532 && GET_CODE (PATTERN (X)) != SEQUENCE \
2533 && GET_CODE (PATTERN (X)) != USE \
2534 && GET_CODE (PATTERN (X)) != CLOBBER \
2535 && get_attr_is_sfunc (X)))
2536
2537 \f
2538 /* Position Independent Code. */
2539
2540 /* We can't directly access anything that contains a symbol,
2541 nor can we indirect via the constant pool. */
2542 #define LEGITIMATE_PIC_OPERAND_P(X) \
2543 ((! nonpic_symbol_mentioned_p (X) \
2544 && (GET_CODE (X) != SYMBOL_REF \
2545 || ! CONSTANT_POOL_ADDRESS_P (X) \
2546 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2547 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2548
2549 #define SYMBOLIC_CONST_P(X) \
2550 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2551 && nonpic_symbol_mentioned_p (X))
2552 \f
2553 /* Compute extra cost of moving data between one register class
2554 and another. */
2555
2556 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2557 uses this information. Hence, the general register <-> floating point
2558 register information here is not used for SFmode. */
2559
2560 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2561 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2562 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2563
2564 #define REGCLASS_HAS_FP_REG(CLASS) \
2565 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2566 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2567
2568 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2569 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2570
2571 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2572 would be so that people with slow memory systems could generate
2573 different code that does fewer memory accesses. */
2574
2575 /* A C expression for the cost of a branch instruction. A value of 1
2576 is the default; other values are interpreted relative to that.
2577 The SH1 does not have delay slots, hence we get a pipeline stall
2578 at every branch. The SH4 is superscalar, so the single delay slot
2579 is not sufficient to keep both pipelines filled. */
2580 #define BRANCH_COST(speed_p, predictable_p) \
2581 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2582 \f
2583 /* Assembler output control. */
2584
2585 /* A C string constant describing how to begin a comment in the target
2586 assembler language. The compiler assumes that the comment will end at
2587 the end of the line. */
2588 #define ASM_COMMENT_START "!"
2589
2590 #define ASM_APP_ON ""
2591 #define ASM_APP_OFF ""
2592 #define FILE_ASM_OP "\t.file\n"
2593 #define SET_ASM_OP "\t.set\t"
2594
2595 /* How to change between sections. */
2596
2597 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2598 #define DATA_SECTION_ASM_OP "\t.data"
2599
2600 #if defined CRT_BEGIN || defined CRT_END
2601 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2602 # undef TEXT_SECTION_ASM_OP
2603 # if __SHMEDIA__ == 1 && __SH5__ == 32
2604 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2605 # else
2606 # define TEXT_SECTION_ASM_OP "\t.text"
2607 # endif
2608 #endif
2609
2610
2611 /* If defined, a C expression whose value is a string containing the
2612 assembler operation to identify the following data as
2613 uninitialized global data. If not defined, and neither
2614 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2615 uninitialized global data will be output in the data section if
2616 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2617 used. */
2618 #ifndef BSS_SECTION_ASM_OP
2619 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2620 #endif
2621
2622 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2623 separate, explicit argument. If you define this macro, it is used
2624 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2625 handling the required alignment of the variable. The alignment is
2626 specified as the number of bits.
2627
2628 Try to use function `asm_output_aligned_bss' defined in file
2629 `varasm.c' when defining this macro. */
2630 #ifndef ASM_OUTPUT_ALIGNED_BSS
2631 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2632 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2633 #endif
2634
2635 /* Define this so that jump tables go in same section as the current function,
2636 which could be text or it could be a user defined section. */
2637 #define JUMP_TABLES_IN_TEXT_SECTION 1
2638
2639 #undef DO_GLOBAL_CTORS_BODY
2640 #define DO_GLOBAL_CTORS_BODY \
2641 { \
2642 typedef void (*pfunc) (void); \
2643 extern pfunc __ctors[]; \
2644 extern pfunc __ctors_end[]; \
2645 pfunc *p; \
2646 for (p = __ctors_end; p > __ctors; ) \
2647 { \
2648 (*--p)(); \
2649 } \
2650 }
2651
2652 #undef DO_GLOBAL_DTORS_BODY
2653 #define DO_GLOBAL_DTORS_BODY \
2654 { \
2655 typedef void (*pfunc) (void); \
2656 extern pfunc __dtors[]; \
2657 extern pfunc __dtors_end[]; \
2658 pfunc *p; \
2659 for (p = __dtors; p < __dtors_end; p++) \
2660 { \
2661 (*p)(); \
2662 } \
2663 }
2664
2665 #define ASM_OUTPUT_REG_PUSH(file, v) \
2666 { \
2667 if (TARGET_SHMEDIA) \
2668 { \
2669 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2670 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2671 } \
2672 else \
2673 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2674 }
2675
2676 #define ASM_OUTPUT_REG_POP(file, v) \
2677 { \
2678 if (TARGET_SHMEDIA) \
2679 { \
2680 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2681 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2682 } \
2683 else \
2684 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2685 }
2686
2687 /* DBX register number for a given compiler register number. */
2688 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2689 to match gdb. */
2690 /* svr4.h undefines this macro, yet we really want to use the same numbers
2691 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2692 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2693 register exists, so we should return -1 for invalid register numbers. */
2694 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2695
2696 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2697 used to use the encodings 245..260, but that doesn't make sense:
2698 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2699 the FP registers stay the same when switching between compact and media
2700 mode. Hence, we also need to use the same dwarf frame columns.
2701 Likewise, we need to support unwind information for SHmedia registers
2702 even in compact code. */
2703 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2704 (IN_RANGE ((REGNO), \
2705 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2706 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2707 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2708 : ((int) (REGNO) >= FIRST_FP_REG \
2709 && ((int) (REGNO) \
2710 <= (FIRST_FP_REG + \
2711 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2712 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2713 + (TARGET_SH5 ? 77 : 25)) \
2714 : XD_REGISTER_P (REGNO) \
2715 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2716 : TARGET_REGISTER_P (REGNO) \
2717 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2718 : (REGNO) == PR_REG \
2719 ? (TARGET_SH5 ? 18 : 17) \
2720 : (REGNO) == PR_MEDIA_REG \
2721 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2722 : (REGNO) == GBR_REG \
2723 ? (TARGET_SH5 ? 238 : 18) \
2724 : (REGNO) == MACH_REG \
2725 ? (TARGET_SH5 ? 239 : 20) \
2726 : (REGNO) == MACL_REG \
2727 ? (TARGET_SH5 ? 240 : 21) \
2728 : (REGNO) == T_REG \
2729 ? (TARGET_SH5 ? 242 : 22) \
2730 : (REGNO) == FPUL_REG \
2731 ? (TARGET_SH5 ? 244 : 23) \
2732 : (REGNO) == FPSCR_REG \
2733 ? (TARGET_SH5 ? 243 : 24) \
2734 : (unsigned) -1)
2735
2736 /* This is how to output a reference to a symbol_ref. On SH5,
2737 references to non-code symbols must be preceded by `datalabel'. */
2738 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2739 do \
2740 { \
2741 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2742 fputs ("datalabel ", (FILE)); \
2743 assemble_name ((FILE), XSTR ((SYM), 0)); \
2744 } \
2745 while (0)
2746
2747 /* This is how to output an assembler line
2748 that says to advance the location counter
2749 to a multiple of 2**LOG bytes. */
2750
2751 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2752 if ((LOG) != 0) \
2753 fprintf ((FILE), "\t.align %d\n", (LOG))
2754
2755 /* Globalizing directive for a label. */
2756 #define GLOBAL_ASM_OP "\t.global\t"
2757
2758 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2759
2760 /* Output a relative address table. */
2761
2762 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2763 switch (GET_MODE (BODY)) \
2764 { \
2765 case SImode: \
2766 if (TARGET_SH5) \
2767 { \
2768 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2769 (VALUE), (REL)); \
2770 break; \
2771 } \
2772 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2773 break; \
2774 case HImode: \
2775 if (TARGET_SH5) \
2776 { \
2777 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2778 (VALUE), (REL)); \
2779 break; \
2780 } \
2781 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2782 break; \
2783 case QImode: \
2784 if (TARGET_SH5) \
2785 { \
2786 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2787 (VALUE), (REL)); \
2788 break; \
2789 } \
2790 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2791 break; \
2792 default: \
2793 break; \
2794 }
2795
2796 /* Output an absolute table element. */
2797
2798 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2799 if (! optimize || TARGET_BIGTABLE) \
2800 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2801 else \
2802 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2803
2804 \f
2805 /* A C statement to be executed just prior to the output of
2806 assembler code for INSN, to modify the extracted operands so
2807 they will be output differently.
2808
2809 Here the argument OPVEC is the vector containing the operands
2810 extracted from INSN, and NOPERANDS is the number of elements of
2811 the vector which contain meaningful data for this insn.
2812 The contents of this vector are what will be used to convert the insn
2813 template into assembler code, so you can change the assembler output
2814 by changing the contents of the vector. */
2815
2816 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2817 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2818
2819 /* Print operand X (an rtx) in assembler syntax to file FILE.
2820 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2821 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2822
2823 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2824
2825 /* Print a memory address as an operand to reference that memory location. */
2826
2827 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2828
2829 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2830 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
2831 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
2832
2833 /* Recognize machine-specific patterns that may appear within
2834 constants. Used for PIC-specific UNSPECs. */
2835 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2836 do \
2837 if (GET_CODE (X) == UNSPEC) \
2838 { \
2839 switch (XINT ((X), 1)) \
2840 { \
2841 case UNSPEC_DATALABEL: \
2842 fputs ("datalabel ", (STREAM)); \
2843 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2844 break; \
2845 case UNSPEC_PIC: \
2846 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
2847 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2848 break; \
2849 case UNSPEC_GOT: \
2850 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2851 fputs ("@GOT", (STREAM)); \
2852 break; \
2853 case UNSPEC_GOTOFF: \
2854 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2855 fputs ("@GOTOFF", (STREAM)); \
2856 break; \
2857 case UNSPEC_PLT: \
2858 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2859 fputs ("@PLT", (STREAM)); \
2860 break; \
2861 case UNSPEC_GOTPLT: \
2862 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2863 fputs ("@GOTPLT", (STREAM)); \
2864 break; \
2865 case UNSPEC_DTPOFF: \
2866 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2867 fputs ("@DTPOFF", (STREAM)); \
2868 break; \
2869 case UNSPEC_GOTTPOFF: \
2870 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2871 fputs ("@GOTTPOFF", (STREAM)); \
2872 break; \
2873 case UNSPEC_TPOFF: \
2874 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2875 fputs ("@TPOFF", (STREAM)); \
2876 break; \
2877 case UNSPEC_CALLER: \
2878 { \
2879 char name[32]; \
2880 /* LPCS stands for Label for PIC Call Site. */ \
2881 ASM_GENERATE_INTERNAL_LABEL \
2882 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
2883 assemble_name ((STREAM), name); \
2884 } \
2885 break; \
2886 case UNSPEC_EXTRACT_S16: \
2887 case UNSPEC_EXTRACT_U16: \
2888 { \
2889 rtx val, shift; \
2890 \
2891 val = XVECEXP (X, 0, 0); \
2892 shift = XVECEXP (X, 0, 1); \
2893 fputc ('(', STREAM); \
2894 if (shift != const0_rtx) \
2895 fputc ('(', STREAM); \
2896 if (GET_CODE (val) == CONST \
2897 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \
2898 { \
2899 fputc ('(', STREAM); \
2900 output_addr_const (STREAM, val); \
2901 fputc (')', STREAM); \
2902 } \
2903 else \
2904 output_addr_const (STREAM, val); \
2905 if (shift != const0_rtx) \
2906 { \
2907 fputs (" >> ", STREAM); \
2908 output_addr_const (STREAM, shift); \
2909 fputc (')', STREAM); \
2910 } \
2911 fputs (" & 65535)", STREAM); \
2912 } \
2913 break; \
2914 case UNSPEC_SYMOFF: \
2915 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2916 fputc ('-', STREAM); \
2917 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \
2918 { \
2919 fputc ('(', STREAM); \
2920 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2921 fputc (')', STREAM); \
2922 } \
2923 else \
2924 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2925 break; \
2926 case UNSPEC_PCREL_SYMOFF: \
2927 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2928 fputs ("-(", STREAM); \
2929 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2930 fputs ("-.)", STREAM); \
2931 break; \
2932 default: \
2933 goto FAIL; \
2934 } \
2935 break; \
2936 } \
2937 else \
2938 goto FAIL; \
2939 while (0)
2940
2941 \f
2942 extern struct rtx_def *sh_compare_op0;
2943 extern struct rtx_def *sh_compare_op1;
2944
2945 /* Which processor to schedule for. The elements of the enumeration must
2946 match exactly the cpu attribute in the sh.md file. */
2947
2948 enum processor_type {
2949 PROCESSOR_SH1,
2950 PROCESSOR_SH2,
2951 PROCESSOR_SH2E,
2952 PROCESSOR_SH2A,
2953 PROCESSOR_SH3,
2954 PROCESSOR_SH3E,
2955 PROCESSOR_SH4,
2956 PROCESSOR_SH4A,
2957 PROCESSOR_SH5
2958 };
2959
2960 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2961 extern enum processor_type sh_cpu;
2962
2963 extern int optimize; /* needed for gen_casesi. */
2964
2965 enum mdep_reorg_phase_e
2966 {
2967 SH_BEFORE_MDEP_REORG,
2968 SH_INSERT_USES_LABELS,
2969 SH_SHORTEN_BRANCHES0,
2970 SH_FIXUP_PCLOAD,
2971 SH_SHORTEN_BRANCHES1,
2972 SH_AFTER_MDEP_REORG
2973 };
2974
2975 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2976
2977 /* Handle Renesas compiler's pragmas. */
2978 #define REGISTER_TARGET_PRAGMAS() do { \
2979 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2980 c_register_pragma (0, "trapa", sh_pr_trapa); \
2981 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2982 } while (0)
2983
2984 extern tree sh_deferred_function_attributes;
2985 extern tree *sh_deferred_function_attributes_tail;
2986
2987 /* Set when processing a function with interrupt attribute. */
2988
2989 extern int current_function_interrupt;
2990
2991 \f
2992 /* Instructions with unfilled delay slots take up an
2993 extra two bytes for the nop in the delay slot.
2994 sh-dsp parallel processing insns are four bytes long. */
2995
2996 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2997 (LENGTH) += sh_insn_length_adjustment (X);
2998 \f
2999 /* Define this macro if it is advisable to hold scalars in registers
3000 in a wider mode than that declared by the program. In such cases,
3001 the value is constrained to be within the bounds of the declared
3002 type, but kept valid in the wider mode. The signedness of the
3003 extension may differ from that of the type.
3004
3005 Leaving the unsignedp unchanged gives better code than always setting it
3006 to 0. This is despite the fact that we have only signed char and short
3007 load instructions. */
3008 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3009 if (GET_MODE_CLASS (MODE) == MODE_INT \
3010 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3011 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3012 (MODE) = (TARGET_SH1 ? SImode \
3013 : TARGET_SHMEDIA32 ? SImode : DImode);
3014
3015 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3016
3017 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3018
3019 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3020 and popping arguments. However, we do have push/pop instructions, and
3021 rather limited offsets (4 bits) in load/store instructions, so it isn't
3022 clear if this would give better code. If implemented, should check for
3023 compatibility problems. */
3024
3025 #define SH_DYNAMIC_SHIFT_COST \
3026 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3027
3028
3029 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3030
3031 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3032
3033 #define ACTUAL_NORMAL_MODE(ENTITY) \
3034 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3035
3036 #define NORMAL_MODE(ENTITY) \
3037 (sh_cfun_interrupt_handler_p () \
3038 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3039 : ACTUAL_NORMAL_MODE (ENTITY))
3040
3041 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3042
3043 #define MODE_EXIT(ENTITY) \
3044 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3045
3046 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3047 && (REGNO) == FPSCR_REG)
3048
3049 #define MODE_NEEDED(ENTITY, INSN) \
3050 (recog_memoized (INSN) >= 0 \
3051 ? get_attr_fp_mode (INSN) \
3052 : FP_MODE_NONE)
3053
3054 #define MODE_AFTER(MODE, INSN) \
3055 (TARGET_HITACHI \
3056 && recog_memoized (INSN) >= 0 \
3057 && get_attr_fp_set (INSN) != FP_SET_NONE \
3058 ? (int) get_attr_fp_set (INSN) \
3059 : (MODE))
3060
3061 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3062 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3063
3064 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3065 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3066
3067 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3068 sh_can_redirect_branch ((INSN), (SEQ))
3069
3070 #define DWARF_FRAME_RETURN_COLUMN \
3071 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3072
3073 #define EH_RETURN_DATA_REGNO(N) \
3074 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3075
3076 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3077 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3078
3079 /* We have to distinguish between code and data, so that we apply
3080 datalabel where and only where appropriate. Use sdataN for data. */
3081 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3082 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3083 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3084 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3085
3086 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3087 indirect are handled automatically. */
3088 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3089 do { \
3090 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3091 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3092 { \
3093 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3094 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3095 if (0) goto DONE; \
3096 } \
3097 } while (0)
3098
3099 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3100 /* SH constant pool breaks the devices in crtstuff.c to control section
3101 in where code resides. We have to write it as asm code. */
3102 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3103 asm (SECTION_OP "\n\
3104 mov.l 1f,r1\n\
3105 mova 2f,r0\n\
3106 braf r1\n\
3107 lds r0,pr\n\
3108 0: .p2align 2\n\
3109 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3110 2:\n" TEXT_SECTION_ASM_OP);
3111 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3112
3113 /* FIXME: middle-end support for highpart optimizations is missing. */
3114 #define high_life_started reload_in_progress
3115
3116 #endif /* ! GCC_SH_H */