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re PR target/50751 (SH Target: Displacement addressing does not work for QImode and...
[gcc.git] / gcc / config / sh / sh.h
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #include "config/vxworks-dummy.h"
28
29 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
30 include it here, because bconfig.h is also included by gencodes.c . */
31 /* ??? No longer true. */
32 extern int code_for_indirect_jump_scratch;
33
34 #define TARGET_CPU_CPP_BUILTINS() \
35 do { \
36 builtin_define ("__sh__"); \
37 builtin_assert ("cpu=sh"); \
38 builtin_assert ("machine=sh"); \
39 switch ((int) sh_cpu) \
40 { \
41 case PROCESSOR_SH1: \
42 builtin_define ("__sh1__"); \
43 break; \
44 case PROCESSOR_SH2: \
45 builtin_define ("__sh2__"); \
46 break; \
47 case PROCESSOR_SH2E: \
48 builtin_define ("__SH2E__"); \
49 break; \
50 case PROCESSOR_SH2A: \
51 builtin_define ("__SH2A__"); \
52 builtin_define (TARGET_SH2A_DOUBLE \
53 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
54 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
55 : "__SH2A_NOFPU__"); \
56 break; \
57 case PROCESSOR_SH3: \
58 builtin_define ("__sh3__"); \
59 builtin_define ("__SH3__"); \
60 if (TARGET_HARD_SH4) \
61 builtin_define ("__SH4_NOFPU__"); \
62 break; \
63 case PROCESSOR_SH3E: \
64 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
65 break; \
66 case PROCESSOR_SH4: \
67 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
68 break; \
69 case PROCESSOR_SH4A: \
70 builtin_define ("__SH4A__"); \
71 builtin_define (TARGET_SH4 \
72 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
73 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
74 : "__SH4_NOFPU__"); \
75 break; \
76 case PROCESSOR_SH5: \
77 { \
78 builtin_define_with_value ("__SH5__", \
79 TARGET_SHMEDIA64 ? "64" : "32", 0); \
80 builtin_define_with_value ("__SHMEDIA__", \
81 TARGET_SHMEDIA ? "1" : "0", 0); \
82 if (! TARGET_FPU_DOUBLE) \
83 builtin_define ("__SH4_NOFPU__"); \
84 } \
85 } \
86 if (TARGET_FPU_ANY) \
87 builtin_define ("__SH_FPU_ANY__"); \
88 if (TARGET_FPU_DOUBLE) \
89 builtin_define ("__SH_FPU_DOUBLE__"); \
90 if (TARGET_HITACHI) \
91 builtin_define ("__HITACHI__"); \
92 if (TARGET_FMOVD) \
93 builtin_define ("__FMOVD_ENABLED__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
96 } while (0)
97
98 /* Value should be nonzero if functions must have frame pointers.
99 Zero means the frame pointer need not be set up (and parms may be accessed
100 via the stack pointer) in functions that seem suitable. */
101
102 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
103 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
104 #endif
105
106 \f
107 /* Nonzero if this is an ELF target - compile time only */
108 #define TARGET_ELF 0
109
110 /* Nonzero if we should generate code using type 2E insns. */
111 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
112
113 /* Nonzero if we should generate code using type 2A insns. */
114 #define TARGET_SH2A TARGET_HARD_SH2A
115 /* Nonzero if we should generate code using type 2A SF insns. */
116 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
117 /* Nonzero if we should generate code using type 2A DF insns. */
118 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
119
120 /* Nonzero if we should generate code using type 3E insns. */
121 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
122
123 /* Nonzero if the cache line size is 32. */
124 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
125
126 /* Nonzero if we schedule for a superscalar implementation. */
127 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
128
129 /* Nonzero if the target has separate instruction and data caches. */
130 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
131
132 /* Nonzero if a double-precision FPU is available. */
133 #define TARGET_FPU_DOUBLE \
134 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
135
136 /* Nonzero if an FPU is available. */
137 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
138
139 /* Nonzero if we should generate code using type 4 insns. */
140 #undef TARGET_SH4
141 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
142
143 /* Nonzero if we're generating code for the common subset of
144 instructions present on both SH4a and SH4al-dsp. */
145 #define TARGET_SH4A_ARCH TARGET_SH4A
146
147 /* Nonzero if we're generating code for SH4a, unless the use of the
148 FPU is disabled (which makes it compatible with SH4al-dsp). */
149 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
150
151 /* Nonzero if we should generate code using the SHcompact instruction
152 set and 32-bit ABI. */
153 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
154
155 /* Nonzero if we should generate code using the SHmedia instruction
156 set and ABI. */
157 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
158
159 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
160 ABI. */
161 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
162
163 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
164 ABI. */
165 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
166
167 /* Nonzero if we should generate code using SHmedia FPU instructions. */
168 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
169
170 /* This is not used by the SH2E calling convention */
171 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
172 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
173 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
174
175 #ifndef TARGET_CPU_DEFAULT
176 #define TARGET_CPU_DEFAULT SELECT_SH1
177 #define SUPPORT_SH1 1
178 #define SUPPORT_SH2E 1
179 #define SUPPORT_SH4 1
180 #define SUPPORT_SH4_SINGLE 1
181 #define SUPPORT_SH2A 1
182 #define SUPPORT_SH2A_SINGLE 1
183 #endif
184
185 #define TARGET_DIVIDE_INV \
186 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
187 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
188 || sh_div_strategy == SH_DIV_INV_CALL \
189 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
190 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
191 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
192 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
193 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
194 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
195 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
196 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
197 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
198 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
199 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
200 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
201
202 #define SELECT_SH1 (MASK_SH1)
203 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
204 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
205 | MASK_FPU_SINGLE)
206 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
207 | MASK_HARD_SH2A_DOUBLE \
208 | MASK_SH2 | MASK_SH1)
209 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
210 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
211 | MASK_SH1 | MASK_FPU_SINGLE)
212 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
213 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
214 | MASK_SH2 | MASK_SH1)
215 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
216 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
217 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
218 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
219 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
220 | SELECT_SH3)
221 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
222 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
223 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
224 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
225 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
226 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
227 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
228 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
229 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
230 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
231 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
232
233 #if SUPPORT_SH1
234 #define SUPPORT_SH2 1
235 #endif
236 #if SUPPORT_SH2
237 #define SUPPORT_SH3 1
238 #define SUPPORT_SH2A_NOFPU 1
239 #endif
240 #if SUPPORT_SH3
241 #define SUPPORT_SH4_NOFPU 1
242 #endif
243 #if SUPPORT_SH4_NOFPU
244 #define SUPPORT_SH4A_NOFPU 1
245 #define SUPPORT_SH4AL 1
246 #endif
247
248 #if SUPPORT_SH2E
249 #define SUPPORT_SH3E 1
250 #define SUPPORT_SH2A_SINGLE_ONLY 1
251 #endif
252 #if SUPPORT_SH3E
253 #define SUPPORT_SH4_SINGLE_ONLY 1
254 #endif
255 #if SUPPORT_SH4_SINGLE_ONLY
256 #define SUPPORT_SH4A_SINGLE_ONLY 1
257 #endif
258
259 #if SUPPORT_SH4
260 #define SUPPORT_SH4A 1
261 #endif
262
263 #if SUPPORT_SH4_SINGLE
264 #define SUPPORT_SH4A_SINGLE 1
265 #endif
266
267 #if SUPPORT_SH5_COMPAT
268 #define SUPPORT_SH5_32MEDIA 1
269 #endif
270
271 #if SUPPORT_SH5_COMPACT_NOFPU
272 #define SUPPORT_SH5_32MEDIA_NOFPU 1
273 #endif
274
275 #define SUPPORT_ANY_SH5_32MEDIA \
276 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
277 #define SUPPORT_ANY_SH5_64MEDIA \
278 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
279 #define SUPPORT_ANY_SH5 \
280 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
281
282 /* Reset all target-selection flags. */
283 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
284 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
285 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
286
287 /* This defaults us to big-endian. */
288 #ifndef TARGET_ENDIAN_DEFAULT
289 #define TARGET_ENDIAN_DEFAULT 0
290 #endif
291
292 #ifndef TARGET_OPT_DEFAULT
293 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
294 #endif
295
296 #define TARGET_DEFAULT \
297 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
298
299 #ifndef SH_MULTILIB_CPU_DEFAULT
300 #define SH_MULTILIB_CPU_DEFAULT "m1"
301 #endif
302
303 #if TARGET_ENDIAN_DEFAULT
304 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
305 #else
306 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
307 #endif
308
309 #define CPP_SPEC " %(subtarget_cpp_spec) "
310
311 #ifndef SUBTARGET_CPP_SPEC
312 #define SUBTARGET_CPP_SPEC ""
313 #endif
314
315 #ifndef SUBTARGET_EXTRA_SPECS
316 #define SUBTARGET_EXTRA_SPECS
317 #endif
318
319 #define EXTRA_SPECS \
320 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
321 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
322 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
323 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
324 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
325 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
326 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
327 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
328 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
329 SUBTARGET_EXTRA_SPECS
330
331 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
332 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
333 #else
334 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
335 #endif
336
337 #define SH_ASM_SPEC \
338 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
339 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
340 %{m2a:--isa=sh2a} \
341 %{m2a-single:--isa=sh2a} \
342 %{m2a-single-only:--isa=sh2a} \
343 %{m2a-nofpu:--isa=sh2a-nofpu} \
344 %{m5-compact*:--isa=SHcompact} \
345 %{m5-32media*:--isa=SHmedia --abi=32} \
346 %{m5-64media*:--isa=SHmedia --abi=64} \
347 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
348
349 #define ASM_SPEC SH_ASM_SPEC
350
351 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
352 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
353 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
354 #else
355 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
356 #endif
357 #endif
358
359 #if STRICT_NOFPU == 1
360 /* Strict nofpu means that the compiler should tell the assembler
361 to reject FPU instructions. E.g. from ASM inserts. */
362 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
363 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
364 #else
365 /* If there were an -isa option for sh5-nofpu then it would also go here. */
366 #define SUBTARGET_ASM_ISA_SPEC \
367 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
368 #endif
369 #else /* ! STRICT_NOFPU */
370 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
371 #endif
372
373 #ifndef SUBTARGET_ASM_SPEC
374 #define SUBTARGET_ASM_SPEC ""
375 #endif
376
377 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
378 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
379 #else
380 #define LINK_EMUL_PREFIX "sh%{ml:l}"
381 #endif
382
383 #if TARGET_CPU_DEFAULT & MASK_SH5
384 #if TARGET_CPU_DEFAULT & MASK_SH_E
385 #define LINK_DEFAULT_CPU_EMUL "32"
386 #if TARGET_CPU_DEFAULT & MASK_SH1
387 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
388 #else
389 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
390 #endif /* MASK_SH1 */
391 #else /* !MASK_SH_E */
392 #define LINK_DEFAULT_CPU_EMUL "64"
393 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
394 #endif /* MASK_SH_E */
395 #define ASM_ISA_DEFAULT_SPEC \
396 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
397 #else /* !MASK_SH5 */
398 #define LINK_DEFAULT_CPU_EMUL ""
399 #define ASM_ISA_DEFAULT_SPEC ""
400 #endif /* MASK_SH5 */
401
402 #define SUBTARGET_LINK_EMUL_SUFFIX ""
403 #define SUBTARGET_LINK_SPEC ""
404
405 /* Go via SH_LINK_SPEC to avoid code replication. */
406 #define LINK_SPEC SH_LINK_SPEC
407
408 #define SH_LINK_SPEC "\
409 -m %(link_emul_prefix)\
410 %{m5-compact*|m5-32media*:32}\
411 %{m5-64media*:64}\
412 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
413 %(subtarget_link_emul_suffix) \
414 %{mrelax:-relax} %(subtarget_link_spec)"
415
416 #ifndef SH_DIV_STR_FOR_SIZE
417 #define SH_DIV_STR_FOR_SIZE "call"
418 #endif
419
420 /* SH2A does not support little-endian. Catch such combinations
421 taking into account the default configuration. */
422 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
423 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
424 #else
425 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
426 #endif
427
428 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
429 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
430 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}"
431 #else
432 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
433 "%{m2a*:%eSH2a does not support little-endian}}"
434 #endif
435
436 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
437
438 #define ASSEMBLER_DIALECT assembler_dialect
439
440 extern int assembler_dialect;
441
442 enum sh_divide_strategy_e {
443 /* SH5 strategies. */
444 SH_DIV_CALL,
445 SH_DIV_CALL2,
446 SH_DIV_FP, /* We could do this also for SH4. */
447 SH_DIV_INV,
448 SH_DIV_INV_MINLAT,
449 SH_DIV_INV20U,
450 SH_DIV_INV20L,
451 SH_DIV_INV_CALL,
452 SH_DIV_INV_CALL2,
453 SH_DIV_INV_FP,
454 /* SH1 .. SH4 strategies. Because of the small number of registers
455 available, the compiler uses knowledge of the actual set of registers
456 being clobbered by the different functions called. */
457 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
458 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
459 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
460 SH_DIV_INTRINSIC
461 };
462
463 extern enum sh_divide_strategy_e sh_div_strategy;
464
465 #ifndef SH_DIV_STRATEGY_DEFAULT
466 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
467 #endif
468
469 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
470
471 \f
472 /* Target machine storage layout. */
473
474 /* Define this if most significant bit is lowest numbered
475 in instructions that operate on numbered bit-fields. */
476
477 #define BITS_BIG_ENDIAN 0
478
479 /* Define this if most significant byte of a word is the lowest numbered. */
480 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
481
482 /* Define this if most significant word of a multiword number is the lowest
483 numbered. */
484 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
485
486 #define MAX_BITS_PER_WORD 64
487
488 /* Width in bits of an `int'. We want just 32-bits, even if words are
489 longer. */
490 #define INT_TYPE_SIZE 32
491
492 /* Width in bits of a `long'. */
493 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
494
495 /* Width in bits of a `long long'. */
496 #define LONG_LONG_TYPE_SIZE 64
497
498 /* Width in bits of a `long double'. */
499 #define LONG_DOUBLE_TYPE_SIZE 64
500
501 /* Width of a word, in units (bytes). */
502 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
503 #define MIN_UNITS_PER_WORD 4
504
505 /* Scaling factor for Dwarf data offsets for CFI information.
506 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
507 SHmedia; however, since we do partial register saves for the registers
508 visible to SHcompact, and for target registers for SHMEDIA32, we have
509 to allow saves that are only 4-byte aligned. */
510 #define DWARF_CIE_DATA_ALIGNMENT -4
511
512 /* Width in bits of a pointer.
513 See also the macro `Pmode' defined below. */
514 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
515
516 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
517 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
518
519 /* Boundary (in *bits*) on which stack pointer should be aligned. */
520 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
521
522 /* The log (base 2) of the cache line size, in bytes. Processors prior to
523 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
524 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
525 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
526
527 /* ABI given & required minimum allocation boundary (in *bits*) for the
528 code of a function. */
529 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
530
531 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
532 the vbit must go into the delta field of
533 pointers-to-member-functions. */
534 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
535 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
536
537 /* Alignment of field after `int : 0' in a structure. */
538 #define EMPTY_FIELD_BOUNDARY 32
539
540 /* No data type wants to be aligned rounder than this. */
541 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
542
543 /* The best alignment to use in cases where we have a choice. */
544 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
545
546 /* Make strings word-aligned so strcpy from constants will be faster. */
547 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
548 ((TREE_CODE (EXP) == STRING_CST \
549 && (ALIGN) < FASTEST_ALIGNMENT) \
550 ? FASTEST_ALIGNMENT : (ALIGN))
551
552 /* get_mode_alignment assumes complex values are always held in multiple
553 registers, but that is not the case on the SH; CQImode and CHImode are
554 held in a single integer register. SH5 also holds CSImode and SCmode
555 values in integer registers. This is relevant for argument passing on
556 SHcompact as we use a stack temp in order to pass CSImode by reference. */
557 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
558 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
559 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
560 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
561 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
562
563 /* Make arrays of chars word-aligned for the same reasons. */
564 #define DATA_ALIGNMENT(TYPE, ALIGN) \
565 (TREE_CODE (TYPE) == ARRAY_TYPE \
566 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
567 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
568
569 /* Number of bits which any structure or union's size must be a
570 multiple of. Each structure or union's size is rounded up to a
571 multiple of this. */
572 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
573
574 /* Set this nonzero if move instructions will actually fail to work
575 when given unaligned data. */
576 #define STRICT_ALIGNMENT 1
577
578 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
579 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
580 barrier_align (LABEL_AFTER_BARRIER)
581
582 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL)
583
584 #define LABEL_ALIGN(A_LABEL) \
585 ( \
586 (PREV_INSN (A_LABEL) \
587 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
588 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
589 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
590 /* explicit alignment insn in constant tables. */ \
591 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
592 : 0)
593
594 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
595 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
596
597 /* The base two logarithm of the known minimum alignment of an insn length. */
598 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
599 (NONJUMP_INSN_P (A_INSN) \
600 ? 1 << TARGET_SHMEDIA \
601 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
602 ? 1 << TARGET_SHMEDIA \
603 : CACHE_LOG)
604 \f
605 /* Standard register usage. */
606
607 /* Register allocation for the Renesas calling convention:
608
609 r0 arg return
610 r1..r3 scratch
611 r4..r7 args in
612 r8..r13 call saved
613 r14 frame pointer/call saved
614 r15 stack pointer
615 ap arg pointer (doesn't really exist, always eliminated)
616 pr subroutine return address
617 t t bit
618 mach multiply/accumulate result, high part
619 macl multiply/accumulate result, low part.
620 fpul fp/int communication register
621 rap return address pointer register
622 fr0 fp arg return
623 fr1..fr3 scratch floating point registers
624 fr4..fr11 fp args in
625 fr12..fr15 call saved floating point registers */
626
627 #define MAX_REGISTER_NAME_LENGTH 5
628 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
629
630 #define SH_REGISTER_NAMES_INITIALIZER \
631 { \
632 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
633 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
634 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
635 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
636 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
637 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
638 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
639 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
640 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
641 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
642 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
643 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
644 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
645 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
646 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
647 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
648 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
649 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
650 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
651 "rap", "sfp" \
652 }
653
654 #define REGNAMES_ARR_INDEX_1(index) \
655 (sh_register_names[index])
656 #define REGNAMES_ARR_INDEX_2(index) \
657 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
658 #define REGNAMES_ARR_INDEX_4(index) \
659 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
660 #define REGNAMES_ARR_INDEX_8(index) \
661 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
662 #define REGNAMES_ARR_INDEX_16(index) \
663 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
664 #define REGNAMES_ARR_INDEX_32(index) \
665 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
666 #define REGNAMES_ARR_INDEX_64(index) \
667 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
668
669 #define REGISTER_NAMES \
670 { \
671 REGNAMES_ARR_INDEX_64 (0), \
672 REGNAMES_ARR_INDEX_64 (64), \
673 REGNAMES_ARR_INDEX_8 (128), \
674 REGNAMES_ARR_INDEX_8 (136), \
675 REGNAMES_ARR_INDEX_8 (144), \
676 REGNAMES_ARR_INDEX_2 (152) \
677 }
678
679 #define ADDREGNAMES_SIZE 32
680 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
681 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
682 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
683
684 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
685 { \
686 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
687 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
688 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
689 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
690 }
691
692 #define ADDREGNAMES_REGNO(index) \
693 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
694 : (-1))
695
696 #define ADDREGNAMES_ARR_INDEX_1(index) \
697 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
698 #define ADDREGNAMES_ARR_INDEX_2(index) \
699 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
700 #define ADDREGNAMES_ARR_INDEX_4(index) \
701 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
702 #define ADDREGNAMES_ARR_INDEX_8(index) \
703 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
704 #define ADDREGNAMES_ARR_INDEX_16(index) \
705 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
706 #define ADDREGNAMES_ARR_INDEX_32(index) \
707 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
708
709 #define ADDITIONAL_REGISTER_NAMES \
710 { \
711 ADDREGNAMES_ARR_INDEX_32 (0) \
712 }
713
714 /* Number of actual hardware registers.
715 The hardware registers are assigned numbers for the compiler
716 from 0 to just below FIRST_PSEUDO_REGISTER.
717 All registers that the compiler knows about must be given numbers,
718 even those that are not normally considered general registers. */
719
720 /* There are many other relevant definitions in sh.md's md_constants. */
721
722 #define FIRST_GENERAL_REG R0_REG
723 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
724 #define FIRST_FP_REG DR0_REG
725 #define LAST_FP_REG (FIRST_FP_REG + \
726 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
727 #define FIRST_XD_REG XD0_REG
728 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
729 #define FIRST_TARGET_REG TR0_REG
730 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
731
732 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
733
734 #define FIRST_BANKED_REG R0_REG
735 #define LAST_BANKED_REG R7_REG
736
737 #define BANKED_REGISTER_P(REGNO) \
738 IN_RANGE ((REGNO), \
739 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
740 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
741
742 #define GENERAL_REGISTER_P(REGNO) \
743 IN_RANGE ((REGNO), \
744 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
745 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
746
747 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
748 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
749 || ((REGNO) == FRAME_POINTER_REGNUM))
750
751 #define FP_REGISTER_P(REGNO) \
752 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
753
754 #define XD_REGISTER_P(REGNO) \
755 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
756
757 #define FP_OR_XD_REGISTER_P(REGNO) \
758 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
759
760 #define FP_ANY_REGISTER_P(REGNO) \
761 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
762
763 #define SPECIAL_REGISTER_P(REGNO) \
764 ((REGNO) == GBR_REG || (REGNO) == T_REG \
765 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
766
767 #define TARGET_REGISTER_P(REGNO) \
768 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
769
770 #define SHMEDIA_REGISTER_P(REGNO) \
771 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
772 || TARGET_REGISTER_P (REGNO))
773
774 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
775 registers that should be fixed. */
776 #define VALID_REGISTER_P(REGNO) \
777 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
778 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
779 || (REGNO) == FRAME_POINTER_REGNUM \
780 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
781 || (TARGET_SH2E && (REGNO) == FPUL_REG))
782
783 /* The mode that should be generally used to store a register by
784 itself in the stack, or to load it back. */
785 #define REGISTER_NATURAL_MODE(REGNO) \
786 (FP_REGISTER_P (REGNO) ? SFmode \
787 : XD_REGISTER_P (REGNO) ? DFmode \
788 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
789 ? DImode \
790 : SImode)
791
792 #define FIRST_PSEUDO_REGISTER 154
793
794 /* Don't count soft frame pointer. */
795 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
796
797 /* 1 for registers that have pervasive standard uses
798 and are not available for the register allocator.
799
800 Mach register is fixed 'cause it's only 10 bits wide for SH1.
801 It is 32 bits wide for SH2. */
802
803 #define FIXED_REGISTERS \
804 { \
805 /* Regular registers. */ \
806 0, 0, 0, 0, 0, 0, 0, 0, \
807 0, 0, 0, 0, 0, 0, 0, 1, \
808 /* r16 is reserved, r18 is the former pr. */ \
809 1, 0, 0, 0, 0, 0, 0, 0, \
810 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
811 /* r26 is a global variable data pointer; r27 is for constants. */ \
812 1, 1, 1, 1, 0, 0, 0, 0, \
813 0, 0, 0, 0, 0, 0, 0, 0, \
814 0, 0, 0, 0, 0, 0, 0, 0, \
815 0, 0, 0, 0, 0, 0, 0, 0, \
816 0, 0, 0, 0, 0, 0, 0, 1, \
817 /* FP registers. */ \
818 0, 0, 0, 0, 0, 0, 0, 0, \
819 0, 0, 0, 0, 0, 0, 0, 0, \
820 0, 0, 0, 0, 0, 0, 0, 0, \
821 0, 0, 0, 0, 0, 0, 0, 0, \
822 0, 0, 0, 0, 0, 0, 0, 0, \
823 0, 0, 0, 0, 0, 0, 0, 0, \
824 0, 0, 0, 0, 0, 0, 0, 0, \
825 0, 0, 0, 0, 0, 0, 0, 0, \
826 /* Branch target registers. */ \
827 0, 0, 0, 0, 0, 0, 0, 0, \
828 /* XD registers. */ \
829 0, 0, 0, 0, 0, 0, 0, 0, \
830 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
831 1, 1, 1, 1, 1, 1, 0, 1, \
832 /*"rap", "sfp" */ \
833 1, 1, \
834 }
835
836 /* 1 for registers not available across function calls.
837 These must include the FIXED_REGISTERS and also any
838 registers that can be used without being saved.
839 The latter must include the registers where values are returned
840 and the register where structure-value addresses are passed.
841 Aside from that, you can include as many other registers as you like. */
842
843 #define CALL_USED_REGISTERS \
844 { \
845 /* Regular registers. */ \
846 1, 1, 1, 1, 1, 1, 1, 1, \
847 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
848 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
849 across SH5 function calls. */ \
850 0, 0, 0, 0, 0, 0, 0, 1, \
851 1, 1, 1, 1, 1, 1, 1, 1, \
852 1, 1, 1, 1, 0, 0, 0, 0, \
853 0, 0, 0, 0, 1, 1, 1, 1, \
854 1, 1, 1, 1, 0, 0, 0, 0, \
855 0, 0, 0, 0, 0, 0, 0, 0, \
856 0, 0, 0, 0, 1, 1, 1, 1, \
857 /* FP registers. */ \
858 1, 1, 1, 1, 1, 1, 1, 1, \
859 1, 1, 1, 1, 0, 0, 0, 0, \
860 1, 1, 1, 1, 1, 1, 1, 1, \
861 1, 1, 1, 1, 1, 1, 1, 1, \
862 1, 1, 1, 1, 0, 0, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 0, \
864 0, 0, 0, 0, 0, 0, 0, 0, \
865 0, 0, 0, 0, 0, 0, 0, 0, \
866 /* Branch target registers. */ \
867 1, 1, 1, 1, 1, 0, 0, 0, \
868 /* XD registers. */ \
869 1, 1, 1, 1, 1, 1, 0, 0, \
870 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
871 1, 1, 1, 1, 1, 1, 1, 1, \
872 /*"rap", "sfp" */ \
873 1, 1, \
874 }
875
876 /* TARGET_CONDITIONAL_REGISTER_USAGE might want to make a register
877 call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
878 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
879
880 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
881 across SHcompact function calls. We can't tell whether a called
882 function is SHmedia or SHcompact, so we assume it may be when
883 compiling SHmedia code with the 32-bit ABI, since that's the only
884 ABI that can be linked with SHcompact code. */
885 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
886 (TARGET_SHMEDIA32 \
887 && GET_MODE_SIZE (MODE) > 4 \
888 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
889 && (REGNO) <= FIRST_GENERAL_REG + 15) \
890 || TARGET_REGISTER_P (REGNO) \
891 || (REGNO) == PR_MEDIA_REG))
892
893 /* Return number of consecutive hard regs needed starting at reg REGNO
894 to hold something of mode MODE.
895 This is ordinarily the length in words of a value of mode MODE
896 but can be less for certain modes in special long registers.
897
898 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
899
900 #define HARD_REGNO_NREGS(REGNO, MODE) \
901 (XD_REGISTER_P (REGNO) \
902 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
903 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
904 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
905 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
906
907 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
908
909 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
910 sh_hard_regno_mode_ok ((REGNO), (MODE))
911
912 /* Value is 1 if it is a good idea to tie two pseudo registers
913 when one has mode MODE1 and one has mode MODE2.
914 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
915 for any hard reg, then this must be 0 for correct output.
916 That's the case for xd registers: we don't hold SFmode values in
917 them, so we can't tie an SFmode pseudos with one in another
918 floating-point mode. */
919
920 #define MODES_TIEABLE_P(MODE1, MODE2) \
921 ((MODE1) == (MODE2) \
922 || (TARGET_SHMEDIA \
923 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
924 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
925 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
926 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
927 && (GET_MODE_SIZE (MODE2) <= 4)) \
928 : ((MODE1) != SFmode && (MODE2) != SFmode))))
929
930 /* A C expression that is nonzero if hard register NEW_REG can be
931 considered for use as a rename register for OLD_REG register */
932
933 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
934 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
935
936 /* Specify the registers used for certain standard purposes.
937 The values of these macros are register numbers. */
938
939 /* Define this if the program counter is overloaded on a register. */
940 /* #define PC_REGNUM 15*/
941
942 /* Register to use for pushing function arguments. */
943 #define STACK_POINTER_REGNUM SP_REG
944
945 /* Base register for access to local variables of the function. */
946 #define HARD_FRAME_POINTER_REGNUM FP_REG
947
948 /* Base register for access to local variables of the function. */
949 #define FRAME_POINTER_REGNUM 153
950
951 /* Fake register that holds the address on the stack of the
952 current function's return address. */
953 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
954
955 /* Register to hold the addressing base for position independent
956 code access to data items. */
957 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
958
959 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
960
961 /* Definitions for register eliminations.
962
963 We have three registers that can be eliminated on the SH. First, the
964 frame pointer register can often be eliminated in favor of the stack
965 pointer register. Secondly, the argument pointer register can always be
966 eliminated; it is replaced with either the stack or frame pointer.
967 Third, there is the return address pointer, which can also be replaced
968 with either the stack or the frame pointer. */
969
970 /* This is an array of structures. Each structure initializes one pair
971 of eliminable registers. The "from" register number is given first,
972 followed by "to". Eliminations of the same "from" register are listed
973 in order of preference. */
974
975 /* If you add any registers here that are not actually hard registers,
976 and that have any alternative of elimination that doesn't always
977 apply, you need to amend calc_live_regs to exclude it, because
978 reload spills all eliminable registers where it sees an
979 can_eliminate == 0 entry, thus making them 'live' .
980 If you add any hard registers that can be eliminated in different
981 ways, you have to patch reload to spill them only when all alternatives
982 of elimination fail. */
983
984 #define ELIMINABLE_REGS \
985 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
986 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
987 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
988 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
989 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
990 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
991 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
992
993 /* Define the offset between two registers, one to be eliminated, and the other
994 its replacement, at the start of a routine. */
995
996 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
997 OFFSET = initial_elimination_offset ((FROM), (TO))
998
999 /* Base register for access to arguments of the function. */
1000 #define ARG_POINTER_REGNUM AP_REG
1001
1002 /* Register in which the static-chain is passed to a function. */
1003 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1004
1005 /* Don't default to pcc-struct-return, because we have already specified
1006 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1007 target hook. */
1008
1009 #define DEFAULT_PCC_STRUCT_RETURN 0
1010
1011 #define SHMEDIA_REGS_STACK_ADJUST() \
1012 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1013 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1014 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1015 : 0)
1016
1017 \f
1018 /* Define the classes of registers for register constraints in the
1019 machine description. Also define ranges of constants.
1020
1021 One of the classes must always be named ALL_REGS and include all hard regs.
1022 If there is more than one class, another class must be named NO_REGS
1023 and contain no registers.
1024
1025 The name GENERAL_REGS must be the name of a class (or an alias for
1026 another name such as ALL_REGS). This is the class of registers
1027 that is allowed by "g" or "r" in a register constraint.
1028 Also, registers outside this class are allocated only when
1029 instructions express preferences for them.
1030
1031 The classes must be numbered in nondecreasing order; that is,
1032 a larger-numbered class must never be contained completely
1033 in a smaller-numbered class.
1034
1035 For any two classes, it is very desirable that there be another
1036 class that represents their union. */
1037
1038 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1039 be used as the destination of some of the arithmetic ops. There are
1040 also some special purpose registers; the T bit register, the
1041 Procedure Return Register and the Multiply Accumulate Registers. */
1042 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1043 reg_class_subunion. We don't want to have an actual union class
1044 of these, because it would only be used when both classes are calculated
1045 to give the same cost, but there is only one FPUL register.
1046 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1047 applying to the actual instruction alternative considered. E.g., the
1048 y/r alternative of movsi_ie is considered to have no more cost that
1049 the r/r alternative, which is patently untrue. */
1050
1051 enum reg_class
1052 {
1053 NO_REGS,
1054 R0_REGS,
1055 PR_REGS,
1056 T_REGS,
1057 MAC_REGS,
1058 FPUL_REGS,
1059 SIBCALL_REGS,
1060 NON_SP_REGS,
1061 GENERAL_REGS,
1062 FP0_REGS,
1063 FP_REGS,
1064 DF_HI_REGS,
1065 DF_REGS,
1066 FPSCR_REGS,
1067 GENERAL_FP_REGS,
1068 GENERAL_DF_REGS,
1069 TARGET_REGS,
1070 ALL_REGS,
1071 LIM_REG_CLASSES
1072 };
1073
1074 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1075
1076 /* Give names of register classes as strings for dump file. */
1077 #define REG_CLASS_NAMES \
1078 { \
1079 "NO_REGS", \
1080 "R0_REGS", \
1081 "PR_REGS", \
1082 "T_REGS", \
1083 "MAC_REGS", \
1084 "FPUL_REGS", \
1085 "SIBCALL_REGS", \
1086 "NON_SP_REGS", \
1087 "GENERAL_REGS", \
1088 "FP0_REGS", \
1089 "FP_REGS", \
1090 "DF_HI_REGS", \
1091 "DF_REGS", \
1092 "FPSCR_REGS", \
1093 "GENERAL_FP_REGS", \
1094 "GENERAL_DF_REGS", \
1095 "TARGET_REGS", \
1096 "ALL_REGS", \
1097 }
1098
1099 /* Define which registers fit in which classes.
1100 This is an initializer for a vector of HARD_REG_SET
1101 of length N_REG_CLASSES. */
1102
1103 #define REG_CLASS_CONTENTS \
1104 { \
1105 /* NO_REGS: */ \
1106 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1107 /* R0_REGS: */ \
1108 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1109 /* PR_REGS: */ \
1110 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1111 /* T_REGS: */ \
1112 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1113 /* MAC_REGS: */ \
1114 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1115 /* FPUL_REGS: */ \
1116 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1117 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1118 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1119 /* NON_SP_REGS: */ \
1120 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1121 /* GENERAL_REGS: */ \
1122 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1123 /* FP0_REGS: */ \
1124 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1125 /* FP_REGS: */ \
1126 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1127 /* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1128 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1129 /* DF_REGS: */ \
1130 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1131 /* FPSCR_REGS: */ \
1132 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1133 /* GENERAL_FP_REGS: */ \
1134 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1135 /* GENERAL_DF_REGS: */ \
1136 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1137 /* TARGET_REGS: */ \
1138 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1139 /* ALL_REGS: */ \
1140 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1141 }
1142
1143 /* The same information, inverted:
1144 Return the class number of the smallest class containing
1145 reg number REGNO. This could be a conditional expression
1146 or could index an array. */
1147
1148 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1149 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1150
1151 /* When this hook returns true for MODE, the compiler allows
1152 registers explicitly used in the rtl to be used as spill registers
1153 but prevents the compiler from extending the lifetime of these
1154 registers. */
1155 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1156 sh_small_register_classes_for_mode_p
1157
1158 /* The order in which register should be allocated. */
1159 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1160 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1161 spilled or used otherwise, we better have the FP_REGS allocated first. */
1162 #define REG_ALLOC_ORDER \
1163 {/* Caller-saved FPRs */ \
1164 65, 66, 67, 68, 69, 70, 71, 64, \
1165 72, 73, 74, 75, 80, 81, 82, 83, \
1166 84, 85, 86, 87, 88, 89, 90, 91, \
1167 92, 93, 94, 95, 96, 97, 98, 99, \
1168 /* Callee-saved FPRs */ \
1169 76, 77, 78, 79,100,101,102,103, \
1170 104,105,106,107,108,109,110,111, \
1171 112,113,114,115,116,117,118,119, \
1172 120,121,122,123,124,125,126,127, \
1173 136,137,138,139,140,141,142,143, \
1174 /* FPSCR */ 151, \
1175 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1176 1, 2, 3, 7, 6, 5, 4, 0, \
1177 8, 9, 17, 19, 20, 21, 22, 23, \
1178 36, 37, 38, 39, 40, 41, 42, 43, \
1179 60, 61, 62, \
1180 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1181 10, 11, 12, 13, 14, 18, \
1182 /* SH5 callee-saved GPRs */ \
1183 28, 29, 30, 31, 32, 33, 34, 35, \
1184 44, 45, 46, 47, 48, 49, 50, 51, \
1185 52, 53, 54, 55, 56, 57, 58, 59, \
1186 /* FPUL */ 150, \
1187 /* SH5 branch target registers */ \
1188 128,129,130,131,132,133,134,135, \
1189 /* Fixed registers */ \
1190 15, 16, 24, 25, 26, 27, 63,144, \
1191 145,146,147,148,149,152,153 }
1192
1193 /* The class value for index registers, and the one for base regs. */
1194 #define INDEX_REG_CLASS \
1195 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1196 #define BASE_REG_CLASS GENERAL_REGS
1197 \f
1198 /* Defines for sh.md and constraints.md. */
1199
1200 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1201 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1202 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1203 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1204 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1205 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1206 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1207 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1208
1209 #define CONST_OK_FOR_J16(VALUE) \
1210 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1211 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1212
1213 #define CONST_OK_FOR_K04(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1214 && ((HOST_WIDE_INT)(VALUE)) <= 15)
1215
1216 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1217 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1218
1219 #define CONST_OK_FOR_K12(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1220 && ((HOST_WIDE_INT)(VALUE)) <= 4095)
1221
1222 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1223 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1224
1225 #define DISP_ADDR_P(X) (MEM_P (X) && GET_CODE (XEXP (X, 0)) == PLUS \
1226 && REG_P (XEXP (XEXP (X, 0), 0)) \
1227 && CONST_INT_P (XEXP (XEXP (X, 0), 1)))
1228
1229 #define DISP_ADDR_OFFSET(X) (INTVAL (XEXP (XEXP (X, 0), 1)))
1230
1231 #if 0
1232 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1233 ((((REGCLASS_HAS_FP_REG (CLASS) \
1234 && (REG_P (X) \
1235 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1236 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1237 && TARGET_FMOVD)))) \
1238 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1239 && REG_P (X) \
1240 && FP_REGISTER_P (REGNO (X)))) \
1241 && ! TARGET_SHMEDIA \
1242 && ((MODE) == SFmode || (MODE) == SImode)) \
1243 ? FPUL_REGS \
1244 : (((CLASS) == FPUL_REGS \
1245 || (REGCLASS_HAS_FP_REG (CLASS) \
1246 && ! TARGET_SHMEDIA && MODE == SImode)) \
1247 && (MEM_P (X) \
1248 || (REG_P (X) \
1249 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1250 || REGNO (X) == T_REG \
1251 || system_reg_operand (X, VOIDmode))))) \
1252 ? GENERAL_REGS \
1253 : (((CLASS) == TARGET_REGS \
1254 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1255 && !satisfies_constraint_Csy (X) \
1256 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1257 ? GENERAL_REGS \
1258 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1259 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1260 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1261 ? GENERAL_REGS \
1262 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1263 && TARGET_REGISTER_P (REGNO (X))) \
1264 ? GENERAL_REGS : (ELSE))
1265
1266 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1267 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1268
1269 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1270 ((REGCLASS_HAS_FP_REG (CLASS) \
1271 && ! TARGET_SHMEDIA \
1272 && immediate_operand ((X), (MODE)) \
1273 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1274 && (MODE) == SFmode && fldi_ok ())) \
1275 ? R0_REGS \
1276 : ((CLASS) == FPUL_REGS \
1277 && ((REG_P (X) \
1278 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1279 || REGNO (X) == T_REG)) \
1280 || GET_CODE (X) == PLUS)) \
1281 ? GENERAL_REGS \
1282 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1283 ? (satisfies_constraint_I08 (X) \
1284 ? GENERAL_REGS \
1285 : R0_REGS) \
1286 : ((CLASS) == FPSCR_REGS \
1287 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1288 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1289 ? GENERAL_REGS \
1290 : (REGCLASS_HAS_FP_REG (CLASS) \
1291 && TARGET_SHMEDIA \
1292 && immediate_operand ((X), (MODE)) \
1293 && (X) != CONST0_RTX (GET_MODE (X)) \
1294 && GET_MODE (X) != V4SFmode) \
1295 ? GENERAL_REGS \
1296 : (((MODE) == QImode || (MODE) == HImode) \
1297 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1298 ? GENERAL_REGS \
1299 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1300 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1301 ? TARGET_REGS \
1302 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1303 #endif
1304
1305 /* Return the maximum number of consecutive registers
1306 needed to represent mode MODE in a register of class CLASS.
1307
1308 If TARGET_SHMEDIA, we need two FP registers per word.
1309 Otherwise we will need at most one register per word. */
1310 #define CLASS_MAX_NREGS(CLASS, MODE) \
1311 (TARGET_SHMEDIA \
1312 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1313 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1314 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1315
1316 /* If defined, gives a class of registers that cannot be used as the
1317 operand of a SUBREG that changes the mode of the object illegally. */
1318 /* ??? We need to renumber the internal numbers for the frnn registers
1319 when in little endian in order to allow mode size changes. */
1320
1321 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1322 sh_cannot_change_mode_class (FROM, TO, CLASS)
1323 \f
1324 /* Stack layout; function entry, exit and calling. */
1325
1326 /* Define the number of registers that can hold parameters.
1327 These macros are used only in other macro definitions below. */
1328
1329 #define NPARM_REGS(MODE) \
1330 (TARGET_FPU_ANY && (MODE) == SFmode \
1331 ? (TARGET_SH5 ? 12 : 8) \
1332 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1333 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1334 ? (TARGET_SH5 ? 12 : 8) \
1335 : (TARGET_SH5 ? 8 : 4))
1336
1337 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1338 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1339
1340 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1341 #define FIRST_FP_RET_REG FIRST_FP_REG
1342
1343 /* Define this if pushing a word on the stack
1344 makes the stack pointer a smaller address. */
1345 #define STACK_GROWS_DOWNWARD
1346
1347 /* Define this macro to nonzero if the addresses of local variable slots
1348 are at negative offsets from the frame pointer. */
1349 #define FRAME_GROWS_DOWNWARD 1
1350
1351 /* Offset from the frame pointer to the first local variable slot to
1352 be allocated. */
1353 #define STARTING_FRAME_OFFSET 0
1354
1355 /* If we generate an insn to push BYTES bytes,
1356 this says how many the stack pointer really advances by. */
1357 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1358 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1359 do correct alignment. */
1360 #if 0
1361 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1362 #endif
1363
1364 /* Offset of first parameter from the argument pointer register value. */
1365 #define FIRST_PARM_OFFSET(FNDECL) 0
1366
1367 /* Value is the number of bytes of arguments automatically popped when
1368 calling a subroutine.
1369 CUM is the accumulated argument list.
1370
1371 On SHcompact, the call trampoline pops arguments off the stack. */
1372 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1373
1374 /* Some subroutine macros specific to this machine. */
1375
1376 #define BASE_RETURN_VALUE_REG(MODE) \
1377 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1378 ? FIRST_FP_RET_REG \
1379 : TARGET_FPU_ANY && (MODE) == SCmode \
1380 ? FIRST_FP_RET_REG \
1381 : (TARGET_FPU_DOUBLE \
1382 && ((MODE) == DFmode || (MODE) == SFmode \
1383 || (MODE) == DCmode || (MODE) == SCmode )) \
1384 ? FIRST_FP_RET_REG \
1385 : FIRST_RET_REG)
1386
1387 #define BASE_ARG_REG(MODE) \
1388 ((TARGET_SH2E && ((MODE) == SFmode)) \
1389 ? FIRST_FP_PARM_REG \
1390 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1391 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1392 ? FIRST_FP_PARM_REG \
1393 : FIRST_PARM_REG)
1394
1395 /* 1 if N is a possible register number for function argument passing. */
1396 /* ??? There are some callers that pass REGNO as int, and others that pass
1397 it as unsigned. We get warnings unless we do casts everywhere. */
1398 #define FUNCTION_ARG_REGNO_P(REGNO) \
1399 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1400 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1401 || (TARGET_FPU_ANY \
1402 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1403 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1404 + NPARM_REGS (SFmode))))
1405 \f
1406 /* Define a data type for recording info about an argument list
1407 during the scan of that argument list. This data type should
1408 hold all necessary information about the function itself
1409 and about the args processed so far, enough to enable macros
1410 such as FUNCTION_ARG to determine where the next arg should go.
1411
1412 On SH, this is a single integer, which is a number of words
1413 of arguments scanned so far (including the invisible argument,
1414 if any, which holds the structure-value-address).
1415 Thus NARGREGS or more means all following args should go on the stack. */
1416
1417 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1418 struct sh_args {
1419 int arg_count[2];
1420 int force_mem;
1421 /* Nonzero if a prototype is available for the function. */
1422 int prototype_p;
1423 /* The number of an odd floating-point register, that should be used
1424 for the next argument of type float. */
1425 int free_single_fp_reg;
1426 /* Whether we're processing an outgoing function call. */
1427 int outgoing;
1428 /* The number of general-purpose registers that should have been
1429 used to pass partial arguments, that are passed totally on the
1430 stack. On SHcompact, a call trampoline will pop them off the
1431 stack before calling the actual function, and, if the called
1432 function is implemented in SHcompact mode, the incoming arguments
1433 decoder will push such arguments back onto the stack. For
1434 incoming arguments, STACK_REGS also takes into account other
1435 arguments passed by reference, that the decoder will also push
1436 onto the stack. */
1437 int stack_regs;
1438 /* The number of general-purpose registers that should have been
1439 used to pass arguments, if the arguments didn't have to be passed
1440 by reference. */
1441 int byref_regs;
1442 /* Set as by shcompact_byref if the current argument is to be passed
1443 by reference. */
1444 int byref;
1445
1446 /* call_cookie is a bitmask used by call expanders, as well as
1447 function prologue and epilogues, to allow SHcompact to comply
1448 with the SH5 32-bit ABI, that requires 64-bit registers to be
1449 used even though only the lower 32-bit half is visible in
1450 SHcompact mode. The strategy is to call SHmedia trampolines.
1451
1452 The alternatives for each of the argument-passing registers are
1453 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1454 contents from the address in it; (d) add 8 to it, storing the
1455 result in the next register, then (c); (e) copy it from some
1456 floating-point register,
1457
1458 Regarding copies from floating-point registers, r2 may only be
1459 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1460 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1461 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1462 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1463 dr10.
1464
1465 The bit mask is structured as follows:
1466
1467 - 1 bit to tell whether to set up a return trampoline.
1468
1469 - 3 bits to count the number consecutive registers to pop off the
1470 stack.
1471
1472 - 4 bits for each of r9, r8, r7 and r6.
1473
1474 - 3 bits for each of r5, r4, r3 and r2.
1475
1476 - 3 bits set to 0 (the most significant ones)
1477
1478 3 2 1 0
1479 1098 7654 3210 9876 5432 1098 7654 3210
1480 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1481 2223 3344 4555 6666 7777 8888 9999 SSS-
1482
1483 - If F is set, the register must be copied from an FP register,
1484 whose number is encoded in the remaining bits.
1485
1486 - Else, if L is set, the register must be loaded from the address
1487 contained in it. If the P bit is *not* set, the address of the
1488 following dword should be computed first, and stored in the
1489 following register.
1490
1491 - Else, if P is set, the register alone should be popped off the
1492 stack.
1493
1494 - After all this processing, the number of registers represented
1495 in SSS will be popped off the stack. This is an optimization
1496 for pushing/popping consecutive registers, typically used for
1497 varargs and large arguments partially passed in registers.
1498
1499 - If T is set, a return trampoline will be set up for 64-bit
1500 return values to be split into 2 32-bit registers. */
1501 long call_cookie;
1502
1503 /* This is set to nonzero when the call in question must use the Renesas ABI,
1504 even without the -mrenesas option. */
1505 int renesas_abi;
1506 };
1507
1508 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1509 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1510 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1511 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1512 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1513 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1514 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1515 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1516 #define CALL_COOKIE_INT_REG(REG, VAL) \
1517 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1518 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1519 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1520
1521 #define CUMULATIVE_ARGS struct sh_args
1522
1523 #define GET_SH_ARG_CLASS(MODE) \
1524 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1525 ? SH_ARG_FLOAT \
1526 /* There's no mention of complex float types in the SH5 ABI, so we
1527 should presumably handle them as aggregate types. */ \
1528 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1529 ? SH_ARG_INT \
1530 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1531 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1532 ? SH_ARG_FLOAT : SH_ARG_INT)
1533
1534 #define ROUND_ADVANCE(SIZE) \
1535 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1536
1537 /* Round a register number up to a proper boundary for an arg of mode
1538 MODE.
1539
1540 The SH doesn't care about double alignment, so we only
1541 round doubles to even regs when asked to explicitly. */
1542
1543 #define ROUND_REG(CUM, MODE) \
1544 (((TARGET_ALIGN_DOUBLE \
1545 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1546 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1547 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1548 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1549 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1550 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1551
1552 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1553 for a call to a function whose data type is FNTYPE.
1554 For a library call, FNTYPE is 0.
1555
1556 On SH, the offset always starts at 0: the first parm reg is always
1557 the same reg for a given argument class.
1558
1559 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1560
1561 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1562 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1563
1564 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1565 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1566
1567 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1568 This macro is only used in this file. */
1569
1570 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1571 (((TYPE) == 0 \
1572 || (! TREE_ADDRESSABLE ((TYPE)) \
1573 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1574 || ! (AGGREGATE_TYPE_P (TYPE) \
1575 || (!TARGET_FPU_ANY \
1576 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1577 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1578 && ! (CUM).force_mem \
1579 && (TARGET_SH2E \
1580 ? ((MODE) == BLKmode \
1581 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1582 + int_size_in_bytes (TYPE)) \
1583 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1584 : ((ROUND_REG((CUM), (MODE)) \
1585 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1586 <= NPARM_REGS (MODE))) \
1587 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1588
1589 /* By accident we got stuck with passing SCmode on SH4 little endian
1590 in two registers that are nominally successive - which is different from
1591 two single SFmode values, where we take endianness translation into
1592 account. That does not work at all if an odd number of registers is
1593 already in use, so that got fixed, but library functions are still more
1594 likely to use complex numbers without mixing them with SFmode arguments
1595 (which in C would have to be structures), so for the sake of ABI
1596 compatibility the way SCmode values are passed when an even number of
1597 FP registers is in use remains different from a pair of SFmode values for
1598 now.
1599 I.e.:
1600 foo (double); a: fr5,fr4
1601 foo (float a, float b); a: fr5 b: fr4
1602 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1603 this should be the other way round...
1604 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1605 #define FUNCTION_ARG_SCmode_WART 1
1606
1607 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1608 register in SHcompact mode, it must be padded in the most
1609 significant end. This means that passing it by reference wouldn't
1610 pad properly on a big-endian machine. In this particular case, we
1611 pass this argument on the stack, in a way that the call trampoline
1612 will load its value into the appropriate register. */
1613 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1614 ((MODE) == BLKmode \
1615 && TARGET_SHCOMPACT \
1616 && ! TARGET_LITTLE_ENDIAN \
1617 && int_size_in_bytes (TYPE) > 4 \
1618 && int_size_in_bytes (TYPE) < 8)
1619
1620 /* Minimum alignment for an argument to be passed by callee-copy
1621 reference. We need such arguments to be aligned to 8 byte
1622 boundaries, because they'll be loaded using quad loads. */
1623 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1624
1625 /* The SH5 ABI requires floating-point arguments to be passed to
1626 functions without a prototype in both an FP register and a regular
1627 register or the stack. When passing the argument in both FP and
1628 general-purpose registers, list the FP register first. */
1629 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1630 (gen_rtx_PARALLEL \
1631 ((MODE), \
1632 gen_rtvec (2, \
1633 gen_rtx_EXPR_LIST \
1634 (VOIDmode, \
1635 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1636 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1637 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1638 : NULL_RTX), \
1639 const0_rtx), \
1640 gen_rtx_EXPR_LIST \
1641 (VOIDmode, \
1642 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1643 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1644 + (CUM).arg_count[(int) SH_ARG_INT]) \
1645 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1646 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1647 const0_rtx))))
1648
1649 /* The SH5 ABI requires regular registers or stack slots to be
1650 reserved for floating-point arguments. Registers are taken care of
1651 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1652 Unfortunately, there's no way to just reserve a stack slot, so
1653 we'll end up needlessly storing a copy of the argument in the
1654 stack. For incoming arguments, however, the PARALLEL will be
1655 optimized to the register-only form, and the value in the stack
1656 slot won't be used at all. */
1657 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1658 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1659 ? gen_rtx_REG ((MODE), (REG)) \
1660 : gen_rtx_PARALLEL ((MODE), \
1661 gen_rtvec (2, \
1662 gen_rtx_EXPR_LIST \
1663 (VOIDmode, NULL_RTX, \
1664 const0_rtx), \
1665 gen_rtx_EXPR_LIST \
1666 (VOIDmode, gen_rtx_REG ((MODE), \
1667 (REG)), \
1668 const0_rtx))))
1669
1670 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1671 (TARGET_SH5 \
1672 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1673 || (MODE) == DCmode) \
1674 && ((CUM).arg_count[(int) SH_ARG_INT] \
1675 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1676 : GET_MODE_SIZE (MODE)) \
1677 + 7) / 8) > NPARM_REGS (SImode))
1678
1679 /* Perform any needed actions needed for a function that is receiving a
1680 variable number of arguments. */
1681
1682 /* Call the function profiler with a given profile label.
1683 We use two .aligns, so as to make sure that both the .long is aligned
1684 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1685 from the trapa instruction. */
1686
1687 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1688 { \
1689 if (TARGET_SHMEDIA) \
1690 { \
1691 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1692 fprintf((STREAM), "\ttrapa\tr0\n"); \
1693 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1694 } \
1695 else \
1696 { \
1697 fprintf((STREAM), "\t.align\t2\n"); \
1698 fprintf((STREAM), "\ttrapa\t#33\n"); \
1699 fprintf((STREAM), "\t.align\t2\n"); \
1700 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1701 } \
1702 }
1703
1704 /* Define this macro if the code for function profiling should come
1705 before the function prologue. Normally, the profiling code comes
1706 after. */
1707
1708 #define PROFILE_BEFORE_PROLOGUE
1709
1710 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1711 the stack pointer does not matter. The value is tested only in
1712 functions that have frame pointers.
1713 No definition is equivalent to always zero. */
1714
1715 #define EXIT_IGNORE_STACK 1
1716
1717 /*
1718 On the SH, the trampoline looks like
1719 2 0002 D202 mov.l l2,r2
1720 1 0000 D301 mov.l l1,r3
1721 3 0004 422B jmp @r2
1722 4 0006 0009 nop
1723 5 0008 00000000 l1: .long area
1724 6 000c 00000000 l2: .long function */
1725
1726 /* Length in units of the trampoline for entering a nested function. */
1727 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1728
1729 /* Alignment required for a trampoline in bits . */
1730 #define TRAMPOLINE_ALIGNMENT \
1731 ((CACHE_LOG < 3 || (optimize_size && ! TARGET_HARVARD)) ? 32 \
1732 : TARGET_SHMEDIA ? 256 : 64)
1733
1734 /* A C expression whose value is RTL representing the value of the return
1735 address for the frame COUNT steps up from the current frame.
1736 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1737 can ignore COUNT. */
1738
1739 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1740 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1741
1742 /* A C expression whose value is RTL representing the location of the
1743 incoming return address at the beginning of any function, before the
1744 prologue. This RTL is either a REG, indicating that the return
1745 value is saved in REG, or a MEM representing a location in
1746 the stack. */
1747 #define INCOMING_RETURN_ADDR_RTX \
1748 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1749 \f
1750 /* Addressing modes, and classification of registers for them. */
1751 #define HAVE_POST_INCREMENT TARGET_SH1
1752 #define HAVE_PRE_DECREMENT TARGET_SH1
1753
1754 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1755 ? 0 : TARGET_SH1)
1756 #define USE_LOAD_PRE_DECREMENT(mode) 0
1757 #define USE_STORE_POST_INCREMENT(mode) 0
1758 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1759 ? 0 : TARGET_SH1)
1760
1761 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1762 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1763 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1764
1765 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1766 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1767 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1768
1769 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1770
1771 /* Macros to check register numbers against specific register classes. */
1772
1773 /* These assume that REGNO is a hard or pseudo reg number.
1774 They give nonzero only if REGNO is a hard reg of the suitable class
1775 or a pseudo reg currently allocated to a suitable hard reg.
1776 Since they use reg_renumber, they are safe only once reg_renumber
1777 has been allocated, which happens in local-alloc.c. */
1778
1779 #define REGNO_OK_FOR_BASE_P(REGNO) \
1780 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1781 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1782 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1783 (TARGET_SHMEDIA \
1784 ? (GENERAL_REGISTER_P (REGNO) \
1785 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1786 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1787
1788 /* Maximum number of registers that can appear in a valid memory
1789 address. */
1790
1791 #define MAX_REGS_PER_ADDRESS 2
1792
1793 /* Recognize any constant value that is a valid address. */
1794
1795 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1796
1797 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1798 and check its validity for a certain class.
1799 The suitable hard regs are always accepted and all pseudo regs
1800 are also accepted if STRICT is not set. */
1801
1802 /* Nonzero if X is a reg that can be used as a base reg. */
1803 #define REG_OK_FOR_BASE_P(X, STRICT) \
1804 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1805 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1806
1807 /* Nonzero if X is a reg that can be used as an index. */
1808 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1809 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1810 : REGNO (X) == R0_REG) \
1811 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1812
1813 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1814 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1815 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1816 : REGNO (X) == R0_REG && OFFSET == 0) \
1817 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1818
1819 /* Macros for extra constraints. */
1820
1821 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1822 ((GET_CODE ((OP)) == LABEL_REF) \
1823 || (GET_CODE ((OP)) == CONST \
1824 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1825 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1826 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1827
1828 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1829 (CONSTANT_P (OP) \
1830 && !CONST_INT_P (OP) \
1831 && GET_CODE (OP) != CONST_DOUBLE \
1832 && (!flag_pic \
1833 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1834 && !PIC_ADDR_P (OP) \
1835 && GET_CODE (OP) != LABEL_REF)))
1836
1837 /* Check whether OP is a datalabel unspec. */
1838 #define DATALABEL_REF_NO_CONST_P(OP) \
1839 (GET_CODE (OP) == UNSPEC \
1840 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1841 && XVECLEN ((OP), 0) == 1 \
1842 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1843
1844 #define GOT_ENTRY_P(OP) \
1845 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1846 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1847
1848 #define GOTPLT_ENTRY_P(OP) \
1849 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1850 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1851
1852 #define UNSPEC_GOTOFF_P(OP) \
1853 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1854
1855 #define GOTOFF_P(OP) \
1856 (GET_CODE (OP) == CONST \
1857 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1858 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1859 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1860 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1861
1862 #define PIC_ADDR_P(OP) \
1863 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1864 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1865
1866 #define PCREL_SYMOFF_P(OP) \
1867 (GET_CODE (OP) == CONST \
1868 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1869 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1870
1871 #define NON_PIC_REFERENCE_P(OP) \
1872 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1873 || (GET_CODE (OP) == CONST \
1874 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1875 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1876 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1877 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1878 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1879 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1880 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1881 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1882
1883 #define PIC_REFERENCE_P(OP) \
1884 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1885 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1886
1887 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1888 (flag_pic \
1889 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1890 || PCREL_SYMOFF_P (OP)) \
1891 : NON_PIC_REFERENCE_P (OP))
1892 \f
1893 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1894 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1895 || (GET_CODE (X) == SUBREG \
1896 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1897 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1898 && REG_P (SUBREG_REG (X)) \
1899 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1900
1901 /* Since this must be r0, which is a single register class, we must check
1902 SUBREGs more carefully, to be sure that we don't accept one that extends
1903 outside the class. */
1904 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1905 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1906 || (GET_CODE (X) == SUBREG \
1907 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1908 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1909 && REG_P (SUBREG_REG (X)) \
1910 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1911
1912 #ifdef REG_OK_STRICT
1913 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1914 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1915 #else
1916 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1917 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1918 #endif
1919
1920 #define ALLOW_INDEXED_ADDRESS \
1921 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1922 \f
1923 /* A C compound statement that attempts to replace X, which is an address
1924 that needs reloading, with a valid memory address for an operand of
1925 mode MODE. WIN is a C statement label elsewhere in the code. */
1926
1927 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1928 do { \
1929 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1930 goto WIN; \
1931 } while (0)
1932 \f
1933 /* Specify the machine mode that this machine uses
1934 for the index in the tablejump instruction. */
1935 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1936
1937 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1938 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1939 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1940 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1941 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1942 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1943 : SImode)
1944
1945 /* Define as C expression which evaluates to nonzero if the tablejump
1946 instruction expects the table to contain offsets from the address of the
1947 table.
1948 Do not define this if the table should contain absolute addresses. */
1949 #define CASE_VECTOR_PC_RELATIVE 1
1950
1951 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1952 #define FLOAT_TYPE_SIZE 32
1953
1954 /* Since the SH2e has only `float' support, it is desirable to make all
1955 floating point types equivalent to `float'. */
1956 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
1957
1958 /* 'char' is signed by default. */
1959 #define DEFAULT_SIGNED_CHAR 1
1960
1961 /* The type of size_t unsigned int. */
1962 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
1963
1964 #undef PTRDIFF_TYPE
1965 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
1966
1967 #define WCHAR_TYPE "short unsigned int"
1968 #define WCHAR_TYPE_SIZE 16
1969
1970 #define SH_ELF_WCHAR_TYPE "long int"
1971
1972 /* Max number of bytes we can move from memory to memory
1973 in one reasonably fast instruction. */
1974 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
1975
1976 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1977 MOVE_MAX is not a compile-time constant. */
1978 #define MAX_MOVE_MAX 8
1979
1980 /* Max number of bytes we want move_by_pieces to be able to copy
1981 efficiently. */
1982 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
1983
1984 /* Define if operations between registers always perform the operation
1985 on the full register even if a narrower mode is specified. */
1986 #define WORD_REGISTER_OPERATIONS
1987
1988 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1989 will either zero-extend or sign-extend. The value of this macro should
1990 be the code that says which one of the two operations is implicitly
1991 done, UNKNOWN if none. */
1992 /* For SHmedia, we can truncate to QImode easier using zero extension. */
1993 /* FP registers can load SImode values, but don't implicitly sign-extend
1994 them to DImode. */
1995 #define LOAD_EXTEND_OP(MODE) \
1996 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
1997 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1998
1999 /* Define if loading short immediate values into registers sign extends. */
2000 #define SHORT_IMMEDIATES_SIGN_EXTEND
2001
2002 /* Nonzero if access to memory by bytes is no faster than for words. */
2003 #define SLOW_BYTE_ACCESS 1
2004
2005 /* Immediate shift counts are truncated by the output routines (or was it
2006 the assembler?). Shift counts in a register are truncated by SH. Note
2007 that the native compiler puts too large (> 32) immediate shift counts
2008 into a register and shifts by the register, letting the SH decide what
2009 to do instead of doing that itself. */
2010 /* ??? The library routines in lib1funcs.S truncate the shift count.
2011 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2012 expects - the sign bit is significant - so it appears that we need to
2013 leave this zero for correct SH3 code. */
2014 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2015
2016 /* All integers have the same format so truncation is easy. */
2017 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2018 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2019 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2020
2021 /* Define this if addresses of constant functions
2022 shouldn't be put through pseudo regs where they can be cse'd.
2023 Desirable on machines where ordinary constants are expensive
2024 but a CALL with constant address is cheap. */
2025 /*#define NO_FUNCTION_CSE 1*/
2026
2027 /* The machine modes of pointers and functions. */
2028 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2029 #define FUNCTION_MODE Pmode
2030
2031 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2032 are actually function calls with some special constraints on arguments
2033 and register usage.
2034
2035 These macros tell reorg that the references to arguments and
2036 register clobbers for insns of type sfunc do not appear to happen
2037 until after the millicode call. This allows reorg to put insns
2038 which set the argument registers into the delay slot of the millicode
2039 call -- thus they act more like traditional CALL_INSNs.
2040
2041 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2042 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2043 in particular. */
2044
2045 #define INSN_SETS_ARE_DELAYED(X) \
2046 ((NONJUMP_INSN_P (X) \
2047 && GET_CODE (PATTERN (X)) != SEQUENCE \
2048 && GET_CODE (PATTERN (X)) != USE \
2049 && GET_CODE (PATTERN (X)) != CLOBBER \
2050 && get_attr_is_sfunc (X)))
2051
2052 #define INSN_REFERENCES_ARE_DELAYED(X) \
2053 ((NONJUMP_INSN_P (X) \
2054 && GET_CODE (PATTERN (X)) != SEQUENCE \
2055 && GET_CODE (PATTERN (X)) != USE \
2056 && GET_CODE (PATTERN (X)) != CLOBBER \
2057 && get_attr_is_sfunc (X)))
2058
2059 \f
2060 /* Position Independent Code. */
2061
2062 /* We can't directly access anything that contains a symbol,
2063 nor can we indirect via the constant pool. */
2064 #define LEGITIMATE_PIC_OPERAND_P(X) \
2065 ((! nonpic_symbol_mentioned_p (X) \
2066 && (GET_CODE (X) != SYMBOL_REF \
2067 || ! CONSTANT_POOL_ADDRESS_P (X) \
2068 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2069 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2070
2071 #define SYMBOLIC_CONST_P(X) \
2072 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2073 && nonpic_symbol_mentioned_p (X))
2074 \f
2075 /* Compute extra cost of moving data between one register class
2076 and another. */
2077
2078 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2079 uses this information. Hence, the general register <-> floating point
2080 register information here is not used for SFmode. */
2081
2082 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2083 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
2084 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2085
2086 #define REGCLASS_HAS_FP_REG(CLASS) \
2087 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2088 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2089
2090 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2091 would be so that people with slow memory systems could generate
2092 different code that does fewer memory accesses. */
2093
2094 /* A C expression for the cost of a branch instruction. A value of 1
2095 is the default; other values are interpreted relative to that. */
2096 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
2097 \f
2098 /* Assembler output control. */
2099
2100 /* A C string constant describing how to begin a comment in the target
2101 assembler language. The compiler assumes that the comment will end at
2102 the end of the line. */
2103 #define ASM_COMMENT_START "!"
2104
2105 #define ASM_APP_ON ""
2106 #define ASM_APP_OFF ""
2107 #define FILE_ASM_OP "\t.file\n"
2108 #define SET_ASM_OP "\t.set\t"
2109
2110 /* How to change between sections. */
2111
2112 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2113 #define DATA_SECTION_ASM_OP "\t.data"
2114
2115 #if defined CRT_BEGIN || defined CRT_END
2116 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2117 # undef TEXT_SECTION_ASM_OP
2118 # if __SHMEDIA__ == 1 && __SH5__ == 32
2119 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2120 # else
2121 # define TEXT_SECTION_ASM_OP "\t.text"
2122 # endif
2123 #endif
2124
2125 #ifndef BSS_SECTION_ASM_OP
2126 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2127 #endif
2128
2129 #ifndef ASM_OUTPUT_ALIGNED_BSS
2130 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2131 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2132 #endif
2133
2134 /* Define this so that jump tables go in same section as the current function,
2135 which could be text or it could be a user defined section. */
2136 #define JUMP_TABLES_IN_TEXT_SECTION 1
2137
2138 #undef DO_GLOBAL_CTORS_BODY
2139 #define DO_GLOBAL_CTORS_BODY \
2140 { \
2141 typedef void (*pfunc) (void); \
2142 extern pfunc __ctors[]; \
2143 extern pfunc __ctors_end[]; \
2144 pfunc *p; \
2145 for (p = __ctors_end; p > __ctors; ) \
2146 { \
2147 (*--p)(); \
2148 } \
2149 }
2150
2151 #undef DO_GLOBAL_DTORS_BODY
2152 #define DO_GLOBAL_DTORS_BODY \
2153 { \
2154 typedef void (*pfunc) (void); \
2155 extern pfunc __dtors[]; \
2156 extern pfunc __dtors_end[]; \
2157 pfunc *p; \
2158 for (p = __dtors; p < __dtors_end; p++) \
2159 { \
2160 (*p)(); \
2161 } \
2162 }
2163
2164 #define ASM_OUTPUT_REG_PUSH(file, v) \
2165 { \
2166 if (TARGET_SHMEDIA) \
2167 { \
2168 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2169 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2170 } \
2171 else \
2172 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2173 }
2174
2175 #define ASM_OUTPUT_REG_POP(file, v) \
2176 { \
2177 if (TARGET_SHMEDIA) \
2178 { \
2179 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2180 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2181 } \
2182 else \
2183 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2184 }
2185
2186 /* DBX register number for a given compiler register number. */
2187 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2188 to match gdb. */
2189 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2190 register exists, so we should return -1 for invalid register numbers. */
2191 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2192
2193 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2194 used to use the encodings 245..260, but that doesn't make sense:
2195 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2196 the FP registers stay the same when switching between compact and media
2197 mode. Hence, we also need to use the same dwarf frame columns.
2198 Likewise, we need to support unwind information for SHmedia registers
2199 even in compact code. */
2200 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2201 (IN_RANGE ((REGNO), \
2202 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2203 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2204 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2205 : ((int) (REGNO) >= FIRST_FP_REG \
2206 && ((int) (REGNO) \
2207 <= (FIRST_FP_REG + \
2208 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2209 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2210 + (TARGET_SH5 ? 77 : 25)) \
2211 : XD_REGISTER_P (REGNO) \
2212 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2213 : TARGET_REGISTER_P (REGNO) \
2214 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2215 : (REGNO) == PR_REG \
2216 ? (TARGET_SH5 ? 18 : 17) \
2217 : (REGNO) == PR_MEDIA_REG \
2218 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2219 : (REGNO) == GBR_REG \
2220 ? (TARGET_SH5 ? 238 : 18) \
2221 : (REGNO) == MACH_REG \
2222 ? (TARGET_SH5 ? 239 : 20) \
2223 : (REGNO) == MACL_REG \
2224 ? (TARGET_SH5 ? 240 : 21) \
2225 : (REGNO) == T_REG \
2226 ? (TARGET_SH5 ? 242 : 22) \
2227 : (REGNO) == FPUL_REG \
2228 ? (TARGET_SH5 ? 244 : 23) \
2229 : (REGNO) == FPSCR_REG \
2230 ? (TARGET_SH5 ? 243 : 24) \
2231 : (unsigned) -1)
2232
2233 /* This is how to output a reference to a symbol_ref. On SH5,
2234 references to non-code symbols must be preceded by `datalabel'. */
2235 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2236 do \
2237 { \
2238 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2239 fputs ("datalabel ", (FILE)); \
2240 assemble_name ((FILE), XSTR ((SYM), 0)); \
2241 } \
2242 while (0)
2243
2244 /* This is how to output an assembler line
2245 that says to advance the location counter
2246 to a multiple of 2**LOG bytes. */
2247
2248 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2249 if ((LOG) != 0) \
2250 fprintf ((FILE), "\t.align %d\n", (LOG))
2251
2252 /* Globalizing directive for a label. */
2253 #define GLOBAL_ASM_OP "\t.global\t"
2254
2255 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2256
2257 /* Output a relative address table. */
2258
2259 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2260 switch (GET_MODE (BODY)) \
2261 { \
2262 case SImode: \
2263 if (TARGET_SH5) \
2264 { \
2265 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2266 (VALUE), (REL)); \
2267 break; \
2268 } \
2269 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2270 break; \
2271 case HImode: \
2272 if (TARGET_SH5) \
2273 { \
2274 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2275 (VALUE), (REL)); \
2276 break; \
2277 } \
2278 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2279 break; \
2280 case QImode: \
2281 if (TARGET_SH5) \
2282 { \
2283 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2284 (VALUE), (REL)); \
2285 break; \
2286 } \
2287 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2288 break; \
2289 default: \
2290 break; \
2291 }
2292
2293 /* Output an absolute table element. */
2294
2295 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2296 if (! optimize || TARGET_BIGTABLE) \
2297 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2298 else \
2299 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2300
2301 \f
2302 /* A C statement to be executed just prior to the output of
2303 assembler code for INSN, to modify the extracted operands so
2304 they will be output differently.
2305
2306 Here the argument OPVEC is the vector containing the operands
2307 extracted from INSN, and NOPERANDS is the number of elements of
2308 the vector which contain meaningful data for this insn.
2309 The contents of this vector are what will be used to convert the insn
2310 template into assembler code, so you can change the assembler output
2311 by changing the contents of the vector. */
2312
2313 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2314 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2315
2316 \f
2317 extern rtx sh_compare_op0;
2318 extern rtx sh_compare_op1;
2319
2320 /* Which processor to schedule for. The elements of the enumeration must
2321 match exactly the cpu attribute in the sh.md file. */
2322
2323 enum processor_type {
2324 PROCESSOR_SH1,
2325 PROCESSOR_SH2,
2326 PROCESSOR_SH2E,
2327 PROCESSOR_SH2A,
2328 PROCESSOR_SH3,
2329 PROCESSOR_SH3E,
2330 PROCESSOR_SH4,
2331 PROCESSOR_SH4A,
2332 PROCESSOR_SH5
2333 };
2334
2335 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2336 extern enum processor_type sh_cpu;
2337
2338 enum mdep_reorg_phase_e
2339 {
2340 SH_BEFORE_MDEP_REORG,
2341 SH_INSERT_USES_LABELS,
2342 SH_SHORTEN_BRANCHES0,
2343 SH_FIXUP_PCLOAD,
2344 SH_SHORTEN_BRANCHES1,
2345 SH_AFTER_MDEP_REORG
2346 };
2347
2348 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2349
2350 /* Handle Renesas compiler's pragmas. */
2351 #define REGISTER_TARGET_PRAGMAS() do { \
2352 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2353 c_register_pragma (0, "trapa", sh_pr_trapa); \
2354 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2355 } while (0)
2356
2357 extern tree sh_deferred_function_attributes;
2358 extern tree *sh_deferred_function_attributes_tail;
2359
2360 /* Set when processing a function with interrupt attribute. */
2361
2362 extern int current_function_interrupt;
2363
2364 \f
2365 /* Instructions with unfilled delay slots take up an
2366 extra two bytes for the nop in the delay slot.
2367 sh-dsp parallel processing insns are four bytes long. */
2368
2369 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2370 (LENGTH) += sh_insn_length_adjustment (X);
2371 \f
2372 /* Define this macro if it is advisable to hold scalars in registers
2373 in a wider mode than that declared by the program. In such cases,
2374 the value is constrained to be within the bounds of the declared
2375 type, but kept valid in the wider mode. The signedness of the
2376 extension may differ from that of the type.
2377
2378 Leaving the unsignedp unchanged gives better code than always setting it
2379 to 0. This is despite the fact that we have only signed char and short
2380 load instructions. */
2381 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2382 if (GET_MODE_CLASS (MODE) == MODE_INT \
2383 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2384 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2385 (MODE) = (TARGET_SH1 ? SImode \
2386 : TARGET_SHMEDIA32 ? SImode : DImode);
2387
2388 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2389
2390 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2391
2392 /* Better to allocate once the maximum space for outgoing args in the
2393 prologue rather than duplicate around each call. */
2394 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2395
2396 #define SH_DYNAMIC_SHIFT_COST \
2397 (TARGET_HARD_SH4 ? 1 \
2398 : (TARGET_SH3 || TARGET_SH2A) ? (optimize_size ? 1 : 2) : 20)
2399
2400
2401 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2402
2403 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2404
2405 #define ACTUAL_NORMAL_MODE(ENTITY) \
2406 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2407
2408 #define NORMAL_MODE(ENTITY) \
2409 (sh_cfun_interrupt_handler_p () \
2410 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2411 : ACTUAL_NORMAL_MODE (ENTITY))
2412
2413 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2414
2415 #define MODE_EXIT(ENTITY) \
2416 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2417
2418 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2419 && (REGNO) == FPSCR_REG)
2420
2421 #define MODE_NEEDED(ENTITY, INSN) \
2422 (recog_memoized (INSN) >= 0 \
2423 ? get_attr_fp_mode (INSN) \
2424 : FP_MODE_NONE)
2425
2426 #define MODE_AFTER(MODE, INSN) \
2427 (TARGET_HITACHI \
2428 && recog_memoized (INSN) >= 0 \
2429 && get_attr_fp_set (INSN) != FP_SET_NONE \
2430 ? (int) get_attr_fp_set (INSN) \
2431 : (MODE))
2432
2433 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2434 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2435
2436 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2437 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2438
2439 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2440 sh_can_redirect_branch ((INSN), (SEQ))
2441
2442 #define DWARF_FRAME_RETURN_COLUMN \
2443 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2444
2445 #define EH_RETURN_DATA_REGNO(N) \
2446 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2447
2448 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2449 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2450
2451 /* We have to distinguish between code and data, so that we apply
2452 datalabel where and only where appropriate. Use sdataN for data. */
2453 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2454 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2455 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2456 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2457
2458 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2459 indirect are handled automatically. */
2460 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2461 do { \
2462 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2463 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2464 { \
2465 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2466 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2467 if (0) goto DONE; \
2468 } \
2469 } while (0)
2470
2471 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2472 /* SH constant pool breaks the devices in crtstuff.c to control section
2473 in where code resides. We have to write it as asm code. */
2474 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2475 asm (SECTION_OP "\n\
2476 mov.l 1f,r1\n\
2477 mova 2f,r0\n\
2478 braf r1\n\
2479 lds r0,pr\n\
2480 0: .p2align 2\n\
2481 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2482 2:\n" TEXT_SECTION_ASM_OP);
2483 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2484
2485 /* FIXME: middle-end support for highpart optimizations is missing. */
2486 #define high_life_started reload_in_progress
2487
2488 #endif /* ! GCC_SH_H */