projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
sh.h (PREFERRED_RELOAD_CLASS): Remove.
[gcc.git] / gcc / config / sh / sh.h
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #include "config/vxworks-dummy.h"
28
29 #define TARGET_VERSION \
30 fputs (" (Hitachi SH)", stderr);
31
32 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
33 include it here, because bconfig.h is also included by gencodes.c . */
34 /* ??? No longer true. */
35 extern int code_for_indirect_jump_scratch;
36
37 #define TARGET_CPU_CPP_BUILTINS() \
38 do { \
39 builtin_define ("__sh__"); \
40 builtin_assert ("cpu=sh"); \
41 builtin_assert ("machine=sh"); \
42 switch ((int) sh_cpu) \
43 { \
44 case PROCESSOR_SH1: \
45 builtin_define ("__sh1__"); \
46 break; \
47 case PROCESSOR_SH2: \
48 builtin_define ("__sh2__"); \
49 break; \
50 case PROCESSOR_SH2E: \
51 builtin_define ("__SH2E__"); \
52 break; \
53 case PROCESSOR_SH2A: \
54 builtin_define ("__SH2A__"); \
55 builtin_define (TARGET_SH2A_DOUBLE \
56 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
57 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
58 : "__SH2A_NOFPU__"); \
59 break; \
60 case PROCESSOR_SH3: \
61 builtin_define ("__sh3__"); \
62 builtin_define ("__SH3__"); \
63 if (TARGET_HARD_SH4) \
64 builtin_define ("__SH4_NOFPU__"); \
65 break; \
66 case PROCESSOR_SH3E: \
67 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
68 break; \
69 case PROCESSOR_SH4: \
70 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
71 break; \
72 case PROCESSOR_SH4A: \
73 builtin_define ("__SH4A__"); \
74 builtin_define (TARGET_SH4 \
75 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
76 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
77 : "__SH4_NOFPU__"); \
78 break; \
79 case PROCESSOR_SH5: \
80 { \
81 builtin_define_with_value ("__SH5__", \
82 TARGET_SHMEDIA64 ? "64" : "32", 0); \
83 builtin_define_with_value ("__SHMEDIA__", \
84 TARGET_SHMEDIA ? "1" : "0", 0); \
85 if (! TARGET_FPU_DOUBLE) \
86 builtin_define ("__SH4_NOFPU__"); \
87 } \
88 } \
89 if (TARGET_FPU_ANY) \
90 builtin_define ("__SH_FPU_ANY__"); \
91 if (TARGET_FPU_DOUBLE) \
92 builtin_define ("__SH_FPU_DOUBLE__"); \
93 if (TARGET_HITACHI) \
94 builtin_define ("__HITACHI__"); \
95 if (TARGET_FMOVD) \
96 builtin_define ("__FMOVD_ENABLED__"); \
97 builtin_define (TARGET_LITTLE_ENDIAN \
98 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
99 } while (0)
100
101 /* Value should be nonzero if functions must have frame pointers.
102 Zero means the frame pointer need not be set up (and parms may be accessed
103 via the stack pointer) in functions that seem suitable. */
104
105 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
106 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
107 #endif
108
109 \f
110 /* Nonzero if this is an ELF target - compile time only */
111 #define TARGET_ELF 0
112
113 /* Nonzero if we should generate code using type 2E insns. */
114 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
115
116 /* Nonzero if we should generate code using type 2A insns. */
117 #define TARGET_SH2A TARGET_HARD_SH2A
118 /* Nonzero if we should generate code using type 2A SF insns. */
119 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
120 /* Nonzero if we should generate code using type 2A DF insns. */
121 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
122
123 /* Nonzero if we should generate code using type 3E insns. */
124 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
125
126 /* Nonzero if the cache line size is 32. */
127 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
128
129 /* Nonzero if we schedule for a superscalar implementation. */
130 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
131
132 /* Nonzero if the target has separate instruction and data caches. */
133 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
134
135 /* Nonzero if a double-precision FPU is available. */
136 #define TARGET_FPU_DOUBLE \
137 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
138
139 /* Nonzero if an FPU is available. */
140 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
141
142 /* Nonzero if we should generate code using type 4 insns. */
143 #undef TARGET_SH4
144 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
145
146 /* Nonzero if we're generating code for the common subset of
147 instructions present on both SH4a and SH4al-dsp. */
148 #define TARGET_SH4A_ARCH TARGET_SH4A
149
150 /* Nonzero if we're generating code for SH4a, unless the use of the
151 FPU is disabled (which makes it compatible with SH4al-dsp). */
152 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
153
154 /* Nonzero if we should generate code using the SHcompact instruction
155 set and 32-bit ABI. */
156 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
157
158 /* Nonzero if we should generate code using the SHmedia instruction
159 set and ABI. */
160 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
161
162 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
163 ABI. */
164 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
165
166 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
167 ABI. */
168 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
169
170 /* Nonzero if we should generate code using SHmedia FPU instructions. */
171 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
172
173 /* This is not used by the SH2E calling convention */
174 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
175 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
176 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
177
178 #ifndef TARGET_CPU_DEFAULT
179 #define TARGET_CPU_DEFAULT SELECT_SH1
180 #define SUPPORT_SH1 1
181 #define SUPPORT_SH2E 1
182 #define SUPPORT_SH4 1
183 #define SUPPORT_SH4_SINGLE 1
184 #define SUPPORT_SH2A 1
185 #define SUPPORT_SH2A_SINGLE 1
186 #endif
187
188 #define TARGET_DIVIDE_INV \
189 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
190 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
191 || sh_div_strategy == SH_DIV_INV_CALL \
192 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
193 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
194 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
195 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
196 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
197 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
198 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
199 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
200 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
201 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
202 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
203 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
204
205 #define SELECT_SH1 (MASK_SH1)
206 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
207 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
208 | MASK_FPU_SINGLE)
209 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
210 | MASK_HARD_SH2A_DOUBLE \
211 | MASK_SH2 | MASK_SH1)
212 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
213 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
214 | MASK_SH1 | MASK_FPU_SINGLE)
215 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
216 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
217 | MASK_SH2 | MASK_SH1)
218 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
219 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
220 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
221 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
222 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
223 | SELECT_SH3)
224 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
225 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
226 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
227 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
228 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
229 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
230 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
231 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
232 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
233 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
234 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
235
236 #if SUPPORT_SH1
237 #define SUPPORT_SH2 1
238 #endif
239 #if SUPPORT_SH2
240 #define SUPPORT_SH3 1
241 #define SUPPORT_SH2A_NOFPU 1
242 #endif
243 #if SUPPORT_SH3
244 #define SUPPORT_SH4_NOFPU 1
245 #endif
246 #if SUPPORT_SH4_NOFPU
247 #define SUPPORT_SH4A_NOFPU 1
248 #define SUPPORT_SH4AL 1
249 #endif
250
251 #if SUPPORT_SH2E
252 #define SUPPORT_SH3E 1
253 #define SUPPORT_SH2A_SINGLE_ONLY 1
254 #endif
255 #if SUPPORT_SH3E
256 #define SUPPORT_SH4_SINGLE_ONLY 1
257 #endif
258 #if SUPPORT_SH4_SINGLE_ONLY
259 #define SUPPORT_SH4A_SINGLE_ONLY 1
260 #endif
261
262 #if SUPPORT_SH4
263 #define SUPPORT_SH4A 1
264 #endif
265
266 #if SUPPORT_SH4_SINGLE
267 #define SUPPORT_SH4A_SINGLE 1
268 #endif
269
270 #if SUPPORT_SH5_COMPAT
271 #define SUPPORT_SH5_32MEDIA 1
272 #endif
273
274 #if SUPPORT_SH5_COMPACT_NOFPU
275 #define SUPPORT_SH5_32MEDIA_NOFPU 1
276 #endif
277
278 #define SUPPORT_ANY_SH5_32MEDIA \
279 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
280 #define SUPPORT_ANY_SH5_64MEDIA \
281 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
282 #define SUPPORT_ANY_SH5 \
283 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
284
285 /* Reset all target-selection flags. */
286 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
287 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
288 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
289
290 /* This defaults us to big-endian. */
291 #ifndef TARGET_ENDIAN_DEFAULT
292 #define TARGET_ENDIAN_DEFAULT 0
293 #endif
294
295 #ifndef TARGET_OPT_DEFAULT
296 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
297 #endif
298
299 #define TARGET_DEFAULT \
300 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
301
302 #ifndef SH_MULTILIB_CPU_DEFAULT
303 #define SH_MULTILIB_CPU_DEFAULT "m1"
304 #endif
305
306 #if TARGET_ENDIAN_DEFAULT
307 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
308 #else
309 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
310 #endif
311
312 #define CPP_SPEC " %(subtarget_cpp_spec) "
313
314 #ifndef SUBTARGET_CPP_SPEC
315 #define SUBTARGET_CPP_SPEC ""
316 #endif
317
318 #ifndef SUBTARGET_EXTRA_SPECS
319 #define SUBTARGET_EXTRA_SPECS
320 #endif
321
322 #define EXTRA_SPECS \
323 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
324 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
325 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
326 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
327 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
328 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
329 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
330 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
331 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
332 SUBTARGET_EXTRA_SPECS
333
334 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
335 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
336 #else
337 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
338 #endif
339
340 #define SH_ASM_SPEC \
341 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
342 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
343 %{m2a:--isa=sh2a} \
344 %{m2a-single:--isa=sh2a} \
345 %{m2a-single-only:--isa=sh2a} \
346 %{m2a-nofpu:--isa=sh2a-nofpu} \
347 %{m5-compact*:--isa=SHcompact} \
348 %{m5-32media*:--isa=SHmedia --abi=32} \
349 %{m5-64media*:--isa=SHmedia --abi=64} \
350 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
351
352 #define ASM_SPEC SH_ASM_SPEC
353
354 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
355 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
356 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
357 #else
358 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
359 #endif
360 #endif
361
362 #if STRICT_NOFPU == 1
363 /* Strict nofpu means that the compiler should tell the assembler
364 to reject FPU instructions. E.g. from ASM inserts. */
365 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
366 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
367 #else
368 /* If there were an -isa option for sh5-nofpu then it would also go here. */
369 #define SUBTARGET_ASM_ISA_SPEC \
370 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
371 #endif
372 #else /* ! STRICT_NOFPU */
373 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
374 #endif
375
376 #ifndef SUBTARGET_ASM_SPEC
377 #define SUBTARGET_ASM_SPEC ""
378 #endif
379
380 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
381 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
382 #else
383 #define LINK_EMUL_PREFIX "sh%{ml:l}"
384 #endif
385
386 #if TARGET_CPU_DEFAULT & MASK_SH5
387 #if TARGET_CPU_DEFAULT & MASK_SH_E
388 #define LINK_DEFAULT_CPU_EMUL "32"
389 #if TARGET_CPU_DEFAULT & MASK_SH1
390 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
391 #else
392 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
393 #endif /* MASK_SH1 */
394 #else /* !MASK_SH_E */
395 #define LINK_DEFAULT_CPU_EMUL "64"
396 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
397 #endif /* MASK_SH_E */
398 #define ASM_ISA_DEFAULT_SPEC \
399 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
400 #else /* !MASK_SH5 */
401 #define LINK_DEFAULT_CPU_EMUL ""
402 #define ASM_ISA_DEFAULT_SPEC ""
403 #endif /* MASK_SH5 */
404
405 #define SUBTARGET_LINK_EMUL_SUFFIX ""
406 #define SUBTARGET_LINK_SPEC ""
407
408 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
409 so that we can undo the damage without code replication. */
410 #define LINK_SPEC SH_LINK_SPEC
411
412 #define SH_LINK_SPEC "\
413 -m %(link_emul_prefix)\
414 %{m5-compact*|m5-32media*:32}\
415 %{m5-64media*:64}\
416 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
417 %(subtarget_link_emul_suffix) \
418 %{mrelax:-relax} %(subtarget_link_spec)"
419
420 #ifndef SH_DIV_STR_FOR_SIZE
421 #define SH_DIV_STR_FOR_SIZE "call"
422 #endif
423
424 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
425
426 #define ASSEMBLER_DIALECT assembler_dialect
427
428 extern int assembler_dialect;
429
430 enum sh_divide_strategy_e {
431 /* SH5 strategies. */
432 SH_DIV_CALL,
433 SH_DIV_CALL2,
434 SH_DIV_FP, /* We could do this also for SH4. */
435 SH_DIV_INV,
436 SH_DIV_INV_MINLAT,
437 SH_DIV_INV20U,
438 SH_DIV_INV20L,
439 SH_DIV_INV_CALL,
440 SH_DIV_INV_CALL2,
441 SH_DIV_INV_FP,
442 /* SH1 .. SH4 strategies. Because of the small number of registers
443 available, the compiler uses knowledge of the actual set of registers
444 being clobbered by the different functions called. */
445 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
446 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
447 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
448 SH_DIV_INTRINSIC
449 };
450
451 extern enum sh_divide_strategy_e sh_div_strategy;
452
453 #ifndef SH_DIV_STRATEGY_DEFAULT
454 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
455 #endif
456
457 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
458
459 \f
460 /* Target machine storage layout. */
461
462 /* Define this if most significant bit is lowest numbered
463 in instructions that operate on numbered bit-fields. */
464
465 #define BITS_BIG_ENDIAN 0
466
467 /* Define this if most significant byte of a word is the lowest numbered. */
468 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
469
470 /* Define this if most significant word of a multiword number is the lowest
471 numbered. */
472 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
473
474 #define MAX_BITS_PER_WORD 64
475
476 /* Width in bits of an `int'. We want just 32-bits, even if words are
477 longer. */
478 #define INT_TYPE_SIZE 32
479
480 /* Width in bits of a `long'. */
481 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
482
483 /* Width in bits of a `long long'. */
484 #define LONG_LONG_TYPE_SIZE 64
485
486 /* Width in bits of a `long double'. */
487 #define LONG_DOUBLE_TYPE_SIZE 64
488
489 /* Width of a word, in units (bytes). */
490 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
491 #define MIN_UNITS_PER_WORD 4
492
493 /* Scaling factor for Dwarf data offsets for CFI information.
494 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
495 SHmedia; however, since we do partial register saves for the registers
496 visible to SHcompact, and for target registers for SHMEDIA32, we have
497 to allow saves that are only 4-byte aligned. */
498 #define DWARF_CIE_DATA_ALIGNMENT -4
499
500 /* Width in bits of a pointer.
501 See also the macro `Pmode' defined below. */
502 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
503
504 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
505 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
506
507 /* Boundary (in *bits*) on which stack pointer should be aligned. */
508 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
509
510 /* The log (base 2) of the cache line size, in bytes. Processors prior to
511 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
512 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
513 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
514
515 /* ABI given & required minimum allocation boundary (in *bits*) for the
516 code of a function. */
517 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
518
519 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
520 the vbit must go into the delta field of
521 pointers-to-member-functions. */
522 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
523 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
524
525 /* Alignment of field after `int : 0' in a structure. */
526 #define EMPTY_FIELD_BOUNDARY 32
527
528 /* No data type wants to be aligned rounder than this. */
529 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
530
531 /* The best alignment to use in cases where we have a choice. */
532 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
533
534 /* Make strings word-aligned so strcpy from constants will be faster. */
535 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
536 ((TREE_CODE (EXP) == STRING_CST \
537 && (ALIGN) < FASTEST_ALIGNMENT) \
538 ? FASTEST_ALIGNMENT : (ALIGN))
539
540 /* get_mode_alignment assumes complex values are always held in multiple
541 registers, but that is not the case on the SH; CQImode and CHImode are
542 held in a single integer register. SH5 also holds CSImode and SCmode
543 values in integer registers. This is relevant for argument passing on
544 SHcompact as we use a stack temp in order to pass CSImode by reference. */
545 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
546 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
547 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
548 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
549 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
550
551 /* Make arrays of chars word-aligned for the same reasons. */
552 #define DATA_ALIGNMENT(TYPE, ALIGN) \
553 (TREE_CODE (TYPE) == ARRAY_TYPE \
554 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
555 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
556
557 /* Number of bits which any structure or union's size must be a
558 multiple of. Each structure or union's size is rounded up to a
559 multiple of this. */
560 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
561
562 /* Set this nonzero if move instructions will actually fail to work
563 when given unaligned data. */
564 #define STRICT_ALIGNMENT 1
565
566 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
567 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
568 barrier_align (LABEL_AFTER_BARRIER)
569
570 #define LOOP_ALIGN(A_LABEL) \
571 ((! optimize || TARGET_HARD_SH4 || optimize_size) \
572 ? 0 : sh_loop_align (A_LABEL))
573
574 #define LABEL_ALIGN(A_LABEL) \
575 ( \
576 (PREV_INSN (A_LABEL) \
577 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
578 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
579 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
580 /* explicit alignment insn in constant tables. */ \
581 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
582 : 0)
583
584 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
585 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
586
587 /* The base two logarithm of the known minimum alignment of an insn length. */
588 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
589 (NONJUMP_INSN_P (A_INSN) \
590 ? 1 << TARGET_SHMEDIA \
591 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
592 ? 1 << TARGET_SHMEDIA \
593 : CACHE_LOG)
594 \f
595 /* Standard register usage. */
596
597 /* Register allocation for the Renesas calling convention:
598
599 r0 arg return
600 r1..r3 scratch
601 r4..r7 args in
602 r8..r13 call saved
603 r14 frame pointer/call saved
604 r15 stack pointer
605 ap arg pointer (doesn't really exist, always eliminated)
606 pr subroutine return address
607 t t bit
608 mach multiply/accumulate result, high part
609 macl multiply/accumulate result, low part.
610 fpul fp/int communication register
611 rap return address pointer register
612 fr0 fp arg return
613 fr1..fr3 scratch floating point registers
614 fr4..fr11 fp args in
615 fr12..fr15 call saved floating point registers */
616
617 #define MAX_REGISTER_NAME_LENGTH 5
618 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
619
620 #define SH_REGISTER_NAMES_INITIALIZER \
621 { \
622 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
623 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
624 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
625 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
626 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
627 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
628 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
629 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
630 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
631 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
632 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
633 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
634 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
635 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
636 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
637 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
638 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
639 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
640 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
641 "rap", "sfp" \
642 }
643
644 #define REGNAMES_ARR_INDEX_1(index) \
645 (sh_register_names[index])
646 #define REGNAMES_ARR_INDEX_2(index) \
647 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
648 #define REGNAMES_ARR_INDEX_4(index) \
649 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
650 #define REGNAMES_ARR_INDEX_8(index) \
651 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
652 #define REGNAMES_ARR_INDEX_16(index) \
653 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
654 #define REGNAMES_ARR_INDEX_32(index) \
655 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
656 #define REGNAMES_ARR_INDEX_64(index) \
657 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
658
659 #define REGISTER_NAMES \
660 { \
661 REGNAMES_ARR_INDEX_64 (0), \
662 REGNAMES_ARR_INDEX_64 (64), \
663 REGNAMES_ARR_INDEX_8 (128), \
664 REGNAMES_ARR_INDEX_8 (136), \
665 REGNAMES_ARR_INDEX_8 (144), \
666 REGNAMES_ARR_INDEX_2 (152) \
667 }
668
669 #define ADDREGNAMES_SIZE 32
670 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
671 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
672 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
673
674 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
675 { \
676 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
677 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
678 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
679 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
680 }
681
682 #define ADDREGNAMES_REGNO(index) \
683 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
684 : (-1))
685
686 #define ADDREGNAMES_ARR_INDEX_1(index) \
687 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
688 #define ADDREGNAMES_ARR_INDEX_2(index) \
689 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
690 #define ADDREGNAMES_ARR_INDEX_4(index) \
691 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
692 #define ADDREGNAMES_ARR_INDEX_8(index) \
693 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
694 #define ADDREGNAMES_ARR_INDEX_16(index) \
695 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
696 #define ADDREGNAMES_ARR_INDEX_32(index) \
697 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
698
699 #define ADDITIONAL_REGISTER_NAMES \
700 { \
701 ADDREGNAMES_ARR_INDEX_32 (0) \
702 }
703
704 /* Number of actual hardware registers.
705 The hardware registers are assigned numbers for the compiler
706 from 0 to just below FIRST_PSEUDO_REGISTER.
707 All registers that the compiler knows about must be given numbers,
708 even those that are not normally considered general registers. */
709
710 /* There are many other relevant definitions in sh.md's md_constants. */
711
712 #define FIRST_GENERAL_REG R0_REG
713 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
714 #define FIRST_FP_REG DR0_REG
715 #define LAST_FP_REG (FIRST_FP_REG + \
716 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
717 #define FIRST_XD_REG XD0_REG
718 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
719 #define FIRST_TARGET_REG TR0_REG
720 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
721
722 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
723
724 #define FIRST_BANKED_REG R0_REG
725 #define LAST_BANKED_REG R7_REG
726
727 #define BANKED_REGISTER_P(REGNO) \
728 IN_RANGE ((REGNO), \
729 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
730 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
731
732 #define GENERAL_REGISTER_P(REGNO) \
733 IN_RANGE ((REGNO), \
734 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
735 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
736
737 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
738 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
739 || ((REGNO) == FRAME_POINTER_REGNUM))
740
741 #define FP_REGISTER_P(REGNO) \
742 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
743
744 #define XD_REGISTER_P(REGNO) \
745 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
746
747 #define FP_OR_XD_REGISTER_P(REGNO) \
748 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
749
750 #define FP_ANY_REGISTER_P(REGNO) \
751 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
752
753 #define SPECIAL_REGISTER_P(REGNO) \
754 ((REGNO) == GBR_REG || (REGNO) == T_REG \
755 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
756
757 #define TARGET_REGISTER_P(REGNO) \
758 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
759
760 #define SHMEDIA_REGISTER_P(REGNO) \
761 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
762 || TARGET_REGISTER_P (REGNO))
763
764 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
765 registers that should be fixed. */
766 #define VALID_REGISTER_P(REGNO) \
767 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
768 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
769 || (REGNO) == FRAME_POINTER_REGNUM \
770 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
771 || (TARGET_SH2E && (REGNO) == FPUL_REG))
772
773 /* The mode that should be generally used to store a register by
774 itself in the stack, or to load it back. */
775 #define REGISTER_NATURAL_MODE(REGNO) \
776 (FP_REGISTER_P (REGNO) ? SFmode \
777 : XD_REGISTER_P (REGNO) ? DFmode \
778 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
779 ? DImode \
780 : SImode)
781
782 #define FIRST_PSEUDO_REGISTER 154
783
784 /* Don't count soft frame pointer. */
785 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
786
787 /* 1 for registers that have pervasive standard uses
788 and are not available for the register allocator.
789
790 Mach register is fixed 'cause it's only 10 bits wide for SH1.
791 It is 32 bits wide for SH2. */
792
793 #define FIXED_REGISTERS \
794 { \
795 /* Regular registers. */ \
796 0, 0, 0, 0, 0, 0, 0, 0, \
797 0, 0, 0, 0, 0, 0, 0, 1, \
798 /* r16 is reserved, r18 is the former pr. */ \
799 1, 0, 0, 0, 0, 0, 0, 0, \
800 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
801 /* r26 is a global variable data pointer; r27 is for constants. */ \
802 1, 1, 1, 1, 0, 0, 0, 0, \
803 0, 0, 0, 0, 0, 0, 0, 0, \
804 0, 0, 0, 0, 0, 0, 0, 0, \
805 0, 0, 0, 0, 0, 0, 0, 0, \
806 0, 0, 0, 0, 0, 0, 0, 1, \
807 /* FP registers. */ \
808 0, 0, 0, 0, 0, 0, 0, 0, \
809 0, 0, 0, 0, 0, 0, 0, 0, \
810 0, 0, 0, 0, 0, 0, 0, 0, \
811 0, 0, 0, 0, 0, 0, 0, 0, \
812 0, 0, 0, 0, 0, 0, 0, 0, \
813 0, 0, 0, 0, 0, 0, 0, 0, \
814 0, 0, 0, 0, 0, 0, 0, 0, \
815 0, 0, 0, 0, 0, 0, 0, 0, \
816 /* Branch target registers. */ \
817 0, 0, 0, 0, 0, 0, 0, 0, \
818 /* XD registers. */ \
819 0, 0, 0, 0, 0, 0, 0, 0, \
820 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
821 1, 1, 1, 1, 1, 1, 0, 1, \
822 /*"rap", "sfp" */ \
823 1, 1, \
824 }
825
826 /* 1 for registers not available across function calls.
827 These must include the FIXED_REGISTERS and also any
828 registers that can be used without being saved.
829 The latter must include the registers where values are returned
830 and the register where structure-value addresses are passed.
831 Aside from that, you can include as many other registers as you like. */
832
833 #define CALL_USED_REGISTERS \
834 { \
835 /* Regular registers. */ \
836 1, 1, 1, 1, 1, 1, 1, 1, \
837 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
838 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
839 across SH5 function calls. */ \
840 0, 0, 0, 0, 0, 0, 0, 1, \
841 1, 1, 1, 1, 1, 1, 1, 1, \
842 1, 1, 1, 1, 0, 0, 0, 0, \
843 0, 0, 0, 0, 1, 1, 1, 1, \
844 1, 1, 1, 1, 0, 0, 0, 0, \
845 0, 0, 0, 0, 0, 0, 0, 0, \
846 0, 0, 0, 0, 1, 1, 1, 1, \
847 /* FP registers. */ \
848 1, 1, 1, 1, 1, 1, 1, 1, \
849 1, 1, 1, 1, 0, 0, 0, 0, \
850 1, 1, 1, 1, 1, 1, 1, 1, \
851 1, 1, 1, 1, 1, 1, 1, 1, \
852 1, 1, 1, 1, 0, 0, 0, 0, \
853 0, 0, 0, 0, 0, 0, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 0, \
855 0, 0, 0, 0, 0, 0, 0, 0, \
856 /* Branch target registers. */ \
857 1, 1, 1, 1, 1, 0, 0, 0, \
858 /* XD registers. */ \
859 1, 1, 1, 1, 1, 1, 0, 0, \
860 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
861 1, 1, 1, 1, 1, 1, 1, 1, \
862 /*"rap", "sfp" */ \
863 1, 1, \
864 }
865
866 /* TARGET_CONDITIONAL_REGISTER_USAGE might want to make a register
867 call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
868 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
869
870 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
871 across SHcompact function calls. We can't tell whether a called
872 function is SHmedia or SHcompact, so we assume it may be when
873 compiling SHmedia code with the 32-bit ABI, since that's the only
874 ABI that can be linked with SHcompact code. */
875 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
876 (TARGET_SHMEDIA32 \
877 && GET_MODE_SIZE (MODE) > 4 \
878 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
879 && (REGNO) <= FIRST_GENERAL_REG + 15) \
880 || TARGET_REGISTER_P (REGNO) \
881 || (REGNO) == PR_MEDIA_REG))
882
883 /* Return number of consecutive hard regs needed starting at reg REGNO
884 to hold something of mode MODE.
885 This is ordinarily the length in words of a value of mode MODE
886 but can be less for certain modes in special long registers.
887
888 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
889
890 #define HARD_REGNO_NREGS(REGNO, MODE) \
891 (XD_REGISTER_P (REGNO) \
892 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
893 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
894 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
895 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
896
897 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
898
899 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
900 sh_hard_regno_mode_ok ((REGNO), (MODE))
901
902 /* Value is 1 if it is a good idea to tie two pseudo registers
903 when one has mode MODE1 and one has mode MODE2.
904 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
905 for any hard reg, then this must be 0 for correct output.
906 That's the case for xd registers: we don't hold SFmode values in
907 them, so we can't tie an SFmode pseudos with one in another
908 floating-point mode. */
909
910 #define MODES_TIEABLE_P(MODE1, MODE2) \
911 ((MODE1) == (MODE2) \
912 || (TARGET_SHMEDIA \
913 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
914 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
915 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
916 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
917 && (GET_MODE_SIZE (MODE2) <= 4)) \
918 : ((MODE1) != SFmode && (MODE2) != SFmode))))
919
920 /* A C expression that is nonzero if hard register NEW_REG can be
921 considered for use as a rename register for OLD_REG register */
922
923 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
924 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
925
926 /* Specify the registers used for certain standard purposes.
927 The values of these macros are register numbers. */
928
929 /* Define this if the program counter is overloaded on a register. */
930 /* #define PC_REGNUM 15*/
931
932 /* Register to use for pushing function arguments. */
933 #define STACK_POINTER_REGNUM SP_REG
934
935 /* Base register for access to local variables of the function. */
936 #define HARD_FRAME_POINTER_REGNUM FP_REG
937
938 /* Base register for access to local variables of the function. */
939 #define FRAME_POINTER_REGNUM 153
940
941 /* Fake register that holds the address on the stack of the
942 current function's return address. */
943 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
944
945 /* Register to hold the addressing base for position independent
946 code access to data items. */
947 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
948
949 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
950
951 /* Definitions for register eliminations.
952
953 We have three registers that can be eliminated on the SH. First, the
954 frame pointer register can often be eliminated in favor of the stack
955 pointer register. Secondly, the argument pointer register can always be
956 eliminated; it is replaced with either the stack or frame pointer.
957 Third, there is the return address pointer, which can also be replaced
958 with either the stack or the frame pointer. */
959
960 /* This is an array of structures. Each structure initializes one pair
961 of eliminable registers. The "from" register number is given first,
962 followed by "to". Eliminations of the same "from" register are listed
963 in order of preference. */
964
965 /* If you add any registers here that are not actually hard registers,
966 and that have any alternative of elimination that doesn't always
967 apply, you need to amend calc_live_regs to exclude it, because
968 reload spills all eliminable registers where it sees an
969 can_eliminate == 0 entry, thus making them 'live' .
970 If you add any hard registers that can be eliminated in different
971 ways, you have to patch reload to spill them only when all alternatives
972 of elimination fail. */
973
974 #define ELIMINABLE_REGS \
975 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
976 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
977 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
978 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
979 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
980 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
981 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
982
983 /* Define the offset between two registers, one to be eliminated, and the other
984 its replacement, at the start of a routine. */
985
986 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
987 OFFSET = initial_elimination_offset ((FROM), (TO))
988
989 /* Base register for access to arguments of the function. */
990 #define ARG_POINTER_REGNUM AP_REG
991
992 /* Register in which the static-chain is passed to a function. */
993 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
994
995 /* Don't default to pcc-struct-return, because we have already specified
996 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
997 target hook. */
998
999 #define DEFAULT_PCC_STRUCT_RETURN 0
1000
1001 #define SHMEDIA_REGS_STACK_ADJUST() \
1002 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1003 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1004 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1005 : 0)
1006
1007 \f
1008 /* Define the classes of registers for register constraints in the
1009 machine description. Also define ranges of constants.
1010
1011 One of the classes must always be named ALL_REGS and include all hard regs.
1012 If there is more than one class, another class must be named NO_REGS
1013 and contain no registers.
1014
1015 The name GENERAL_REGS must be the name of a class (or an alias for
1016 another name such as ALL_REGS). This is the class of registers
1017 that is allowed by "g" or "r" in a register constraint.
1018 Also, registers outside this class are allocated only when
1019 instructions express preferences for them.
1020
1021 The classes must be numbered in nondecreasing order; that is,
1022 a larger-numbered class must never be contained completely
1023 in a smaller-numbered class.
1024
1025 For any two classes, it is very desirable that there be another
1026 class that represents their union. */
1027
1028 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1029 be used as the destination of some of the arithmetic ops. There are
1030 also some special purpose registers; the T bit register, the
1031 Procedure Return Register and the Multiply Accumulate Registers. */
1032 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1033 reg_class_subunion. We don't want to have an actual union class
1034 of these, because it would only be used when both classes are calculated
1035 to give the same cost, but there is only one FPUL register.
1036 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1037 applying to the actual instruction alternative considered. E.g., the
1038 y/r alternative of movsi_ie is considered to have no more cost that
1039 the r/r alternative, which is patently untrue. */
1040
1041 enum reg_class
1042 {
1043 NO_REGS,
1044 R0_REGS,
1045 PR_REGS,
1046 T_REGS,
1047 MAC_REGS,
1048 FPUL_REGS,
1049 SIBCALL_REGS,
1050 GENERAL_REGS,
1051 FP0_REGS,
1052 FP_REGS,
1053 DF_HI_REGS,
1054 DF_REGS,
1055 FPSCR_REGS,
1056 GENERAL_FP_REGS,
1057 GENERAL_DF_REGS,
1058 TARGET_REGS,
1059 ALL_REGS,
1060 LIM_REG_CLASSES
1061 };
1062
1063 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1064
1065 /* Give names of register classes as strings for dump file. */
1066 #define REG_CLASS_NAMES \
1067 { \
1068 "NO_REGS", \
1069 "R0_REGS", \
1070 "PR_REGS", \
1071 "T_REGS", \
1072 "MAC_REGS", \
1073 "FPUL_REGS", \
1074 "SIBCALL_REGS", \
1075 "GENERAL_REGS", \
1076 "FP0_REGS", \
1077 "FP_REGS", \
1078 "DF_HI_REGS", \
1079 "DF_REGS", \
1080 "FPSCR_REGS", \
1081 "GENERAL_FP_REGS", \
1082 "GENERAL_DF_REGS", \
1083 "TARGET_REGS", \
1084 "ALL_REGS", \
1085 }
1086
1087 /* Define which registers fit in which classes.
1088 This is an initializer for a vector of HARD_REG_SET
1089 of length N_REG_CLASSES. */
1090
1091 #define REG_CLASS_CONTENTS \
1092 { \
1093 /* NO_REGS: */ \
1094 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1095 /* R0_REGS: */ \
1096 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1097 /* PR_REGS: */ \
1098 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1099 /* T_REGS: */ \
1100 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1101 /* MAC_REGS: */ \
1102 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1103 /* FPUL_REGS: */ \
1104 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1105 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1106 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1107 /* GENERAL_REGS: */ \
1108 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1109 /* FP0_REGS: */ \
1110 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1111 /* FP_REGS: */ \
1112 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1113 /* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1114 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1115 /* DF_REGS: */ \
1116 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1117 /* FPSCR_REGS: */ \
1118 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1119 /* GENERAL_FP_REGS: */ \
1120 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1121 /* GENERAL_DF_REGS: */ \
1122 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1123 /* TARGET_REGS: */ \
1124 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1125 /* ALL_REGS: */ \
1126 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1127 }
1128
1129 /* The same information, inverted:
1130 Return the class number of the smallest class containing
1131 reg number REGNO. This could be a conditional expression
1132 or could index an array. */
1133
1134 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1135 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1136
1137 /* The following macro defines cover classes for Integrated Register
1138 Allocator. Cover classes is a set of non-intersected register
1139 classes covering all hard registers used for register allocation
1140 purpose. Any move between two registers of a cover class should be
1141 cheaper than load or store of the registers. The macro value is
1142 array of register classes with LIM_REG_CLASSES used as the end
1143 marker. */
1144
1145 #define IRA_COVER_CLASSES \
1146 { \
1147 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1148 FPUL_REGS, LIM_REG_CLASSES \
1149 }
1150
1151 /* When this hook returns true for MODE, the compiler allows
1152 registers explicitly used in the rtl to be used as spill registers
1153 but prevents the compiler from extending the lifetime of these
1154 registers. */
1155 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1156 sh_small_register_classes_for_mode_p
1157
1158 /* The order in which register should be allocated. */
1159 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1160 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1161 spilled or used otherwise, we better have the FP_REGS allocated first. */
1162 #define REG_ALLOC_ORDER \
1163 {/* Caller-saved FPRs */ \
1164 65, 66, 67, 68, 69, 70, 71, 64, \
1165 72, 73, 74, 75, 80, 81, 82, 83, \
1166 84, 85, 86, 87, 88, 89, 90, 91, \
1167 92, 93, 94, 95, 96, 97, 98, 99, \
1168 /* Callee-saved FPRs */ \
1169 76, 77, 78, 79,100,101,102,103, \
1170 104,105,106,107,108,109,110,111, \
1171 112,113,114,115,116,117,118,119, \
1172 120,121,122,123,124,125,126,127, \
1173 136,137,138,139,140,141,142,143, \
1174 /* FPSCR */ 151, \
1175 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1176 1, 2, 3, 7, 6, 5, 4, 0, \
1177 8, 9, 17, 19, 20, 21, 22, 23, \
1178 36, 37, 38, 39, 40, 41, 42, 43, \
1179 60, 61, 62, \
1180 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1181 10, 11, 12, 13, 14, 18, \
1182 /* SH5 callee-saved GPRs */ \
1183 28, 29, 30, 31, 32, 33, 34, 35, \
1184 44, 45, 46, 47, 48, 49, 50, 51, \
1185 52, 53, 54, 55, 56, 57, 58, 59, \
1186 /* FPUL */ 150, \
1187 /* SH5 branch target registers */ \
1188 128,129,130,131,132,133,134,135, \
1189 /* Fixed registers */ \
1190 15, 16, 24, 25, 26, 27, 63,144, \
1191 145,146,147,148,149,152,153 }
1192
1193 /* The class value for index registers, and the one for base regs. */
1194 #define INDEX_REG_CLASS \
1195 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1196 #define BASE_REG_CLASS GENERAL_REGS
1197 \f
1198 /* Defines for sh.md and constraints.md. */
1199
1200 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1201 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1202 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1203 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1204 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1205 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1206 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1207 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1208
1209 #define CONST_OK_FOR_J16(VALUE) \
1210 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1211 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1212
1213 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1214 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1215
1216 #if 0
1217 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1218 ((((REGCLASS_HAS_FP_REG (CLASS) \
1219 && (REG_P (X) \
1220 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1221 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1222 && TARGET_FMOVD)))) \
1223 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1224 && REG_P (X) \
1225 && FP_REGISTER_P (REGNO (X)))) \
1226 && ! TARGET_SHMEDIA \
1227 && ((MODE) == SFmode || (MODE) == SImode)) \
1228 ? FPUL_REGS \
1229 : (((CLASS) == FPUL_REGS \
1230 || (REGCLASS_HAS_FP_REG (CLASS) \
1231 && ! TARGET_SHMEDIA && MODE == SImode)) \
1232 && (MEM_P (X) \
1233 || (REG_P (X) \
1234 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1235 || REGNO (X) == T_REG \
1236 || system_reg_operand (X, VOIDmode))))) \
1237 ? GENERAL_REGS \
1238 : (((CLASS) == TARGET_REGS \
1239 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1240 && !satisfies_constraint_Csy (X) \
1241 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1242 ? GENERAL_REGS \
1243 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1244 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1245 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1246 ? GENERAL_REGS \
1247 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1248 && TARGET_REGISTER_P (REGNO (X))) \
1249 ? GENERAL_REGS : (ELSE))
1250
1251 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1252 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1253
1254 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1255 ((REGCLASS_HAS_FP_REG (CLASS) \
1256 && ! TARGET_SHMEDIA \
1257 && immediate_operand ((X), (MODE)) \
1258 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1259 && (MODE) == SFmode && fldi_ok ())) \
1260 ? R0_REGS \
1261 : ((CLASS) == FPUL_REGS \
1262 && ((REG_P (X) \
1263 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1264 || REGNO (X) == T_REG)) \
1265 || GET_CODE (X) == PLUS)) \
1266 ? GENERAL_REGS \
1267 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1268 ? (satisfies_constraint_I08 (X) \
1269 ? GENERAL_REGS \
1270 : R0_REGS) \
1271 : ((CLASS) == FPSCR_REGS \
1272 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1273 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1274 ? GENERAL_REGS \
1275 : (REGCLASS_HAS_FP_REG (CLASS) \
1276 && TARGET_SHMEDIA \
1277 && immediate_operand ((X), (MODE)) \
1278 && (X) != CONST0_RTX (GET_MODE (X)) \
1279 && GET_MODE (X) != V4SFmode) \
1280 ? GENERAL_REGS \
1281 : (((MODE) == QImode || (MODE) == HImode) \
1282 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1283 ? GENERAL_REGS \
1284 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1285 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1286 ? TARGET_REGS \
1287 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1288 #endif
1289
1290 /* Return the maximum number of consecutive registers
1291 needed to represent mode MODE in a register of class CLASS.
1292
1293 If TARGET_SHMEDIA, we need two FP registers per word.
1294 Otherwise we will need at most one register per word. */
1295 #define CLASS_MAX_NREGS(CLASS, MODE) \
1296 (TARGET_SHMEDIA \
1297 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1298 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1299 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1300
1301 /* If defined, gives a class of registers that cannot be used as the
1302 operand of a SUBREG that changes the mode of the object illegally. */
1303 /* ??? We need to renumber the internal numbers for the frnn registers
1304 when in little endian in order to allow mode size changes. */
1305
1306 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1307 sh_cannot_change_mode_class (FROM, TO, CLASS)
1308 \f
1309 /* Stack layout; function entry, exit and calling. */
1310
1311 /* Define the number of registers that can hold parameters.
1312 These macros are used only in other macro definitions below. */
1313
1314 #define NPARM_REGS(MODE) \
1315 (TARGET_FPU_ANY && (MODE) == SFmode \
1316 ? (TARGET_SH5 ? 12 : 8) \
1317 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1318 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1319 ? (TARGET_SH5 ? 12 : 8) \
1320 : (TARGET_SH5 ? 8 : 4))
1321
1322 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1323 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1324
1325 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1326 #define FIRST_FP_RET_REG FIRST_FP_REG
1327
1328 /* Define this if pushing a word on the stack
1329 makes the stack pointer a smaller address. */
1330 #define STACK_GROWS_DOWNWARD
1331
1332 /* Define this macro to nonzero if the addresses of local variable slots
1333 are at negative offsets from the frame pointer. */
1334 #define FRAME_GROWS_DOWNWARD 1
1335
1336 /* Offset from the frame pointer to the first local variable slot to
1337 be allocated. */
1338 #define STARTING_FRAME_OFFSET 0
1339
1340 /* If we generate an insn to push BYTES bytes,
1341 this says how many the stack pointer really advances by. */
1342 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1343 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1344 do correct alignment. */
1345 #if 0
1346 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1347 #endif
1348
1349 /* Offset of first parameter from the argument pointer register value. */
1350 #define FIRST_PARM_OFFSET(FNDECL) 0
1351
1352 /* Value is the number of bytes of arguments automatically popped when
1353 calling a subroutine.
1354 CUM is the accumulated argument list.
1355
1356 On SHcompact, the call trampoline pops arguments off the stack. */
1357 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1358
1359 /* Some subroutine macros specific to this machine. */
1360
1361 #define BASE_RETURN_VALUE_REG(MODE) \
1362 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1363 ? FIRST_FP_RET_REG \
1364 : TARGET_FPU_ANY && (MODE) == SCmode \
1365 ? FIRST_FP_RET_REG \
1366 : (TARGET_FPU_DOUBLE \
1367 && ((MODE) == DFmode || (MODE) == SFmode \
1368 || (MODE) == DCmode || (MODE) == SCmode )) \
1369 ? FIRST_FP_RET_REG \
1370 : FIRST_RET_REG)
1371
1372 #define BASE_ARG_REG(MODE) \
1373 ((TARGET_SH2E && ((MODE) == SFmode)) \
1374 ? FIRST_FP_PARM_REG \
1375 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1376 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1377 ? FIRST_FP_PARM_REG \
1378 : FIRST_PARM_REG)
1379
1380 /* 1 if N is a possible register number for function argument passing. */
1381 /* ??? There are some callers that pass REGNO as int, and others that pass
1382 it as unsigned. We get warnings unless we do casts everywhere. */
1383 #define FUNCTION_ARG_REGNO_P(REGNO) \
1384 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1385 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1386 || (TARGET_FPU_ANY \
1387 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1388 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1389 + NPARM_REGS (SFmode))))
1390 \f
1391 /* Define a data type for recording info about an argument list
1392 during the scan of that argument list. This data type should
1393 hold all necessary information about the function itself
1394 and about the args processed so far, enough to enable macros
1395 such as FUNCTION_ARG to determine where the next arg should go.
1396
1397 On SH, this is a single integer, which is a number of words
1398 of arguments scanned so far (including the invisible argument,
1399 if any, which holds the structure-value-address).
1400 Thus NARGREGS or more means all following args should go on the stack. */
1401
1402 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1403 struct sh_args {
1404 int arg_count[2];
1405 int force_mem;
1406 /* Nonzero if a prototype is available for the function. */
1407 int prototype_p;
1408 /* The number of an odd floating-point register, that should be used
1409 for the next argument of type float. */
1410 int free_single_fp_reg;
1411 /* Whether we're processing an outgoing function call. */
1412 int outgoing;
1413 /* The number of general-purpose registers that should have been
1414 used to pass partial arguments, that are passed totally on the
1415 stack. On SHcompact, a call trampoline will pop them off the
1416 stack before calling the actual function, and, if the called
1417 function is implemented in SHcompact mode, the incoming arguments
1418 decoder will push such arguments back onto the stack. For
1419 incoming arguments, STACK_REGS also takes into account other
1420 arguments passed by reference, that the decoder will also push
1421 onto the stack. */
1422 int stack_regs;
1423 /* The number of general-purpose registers that should have been
1424 used to pass arguments, if the arguments didn't have to be passed
1425 by reference. */
1426 int byref_regs;
1427 /* Set as by shcompact_byref if the current argument is to be passed
1428 by reference. */
1429 int byref;
1430
1431 /* call_cookie is a bitmask used by call expanders, as well as
1432 function prologue and epilogues, to allow SHcompact to comply
1433 with the SH5 32-bit ABI, that requires 64-bit registers to be
1434 used even though only the lower 32-bit half is visible in
1435 SHcompact mode. The strategy is to call SHmedia trampolines.
1436
1437 The alternatives for each of the argument-passing registers are
1438 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1439 contents from the address in it; (d) add 8 to it, storing the
1440 result in the next register, then (c); (e) copy it from some
1441 floating-point register,
1442
1443 Regarding copies from floating-point registers, r2 may only be
1444 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1445 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1446 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1447 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1448 dr10.
1449
1450 The bit mask is structured as follows:
1451
1452 - 1 bit to tell whether to set up a return trampoline.
1453
1454 - 3 bits to count the number consecutive registers to pop off the
1455 stack.
1456
1457 - 4 bits for each of r9, r8, r7 and r6.
1458
1459 - 3 bits for each of r5, r4, r3 and r2.
1460
1461 - 3 bits set to 0 (the most significant ones)
1462
1463 3 2 1 0
1464 1098 7654 3210 9876 5432 1098 7654 3210
1465 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1466 2223 3344 4555 6666 7777 8888 9999 SSS-
1467
1468 - If F is set, the register must be copied from an FP register,
1469 whose number is encoded in the remaining bits.
1470
1471 - Else, if L is set, the register must be loaded from the address
1472 contained in it. If the P bit is *not* set, the address of the
1473 following dword should be computed first, and stored in the
1474 following register.
1475
1476 - Else, if P is set, the register alone should be popped off the
1477 stack.
1478
1479 - After all this processing, the number of registers represented
1480 in SSS will be popped off the stack. This is an optimization
1481 for pushing/popping consecutive registers, typically used for
1482 varargs and large arguments partially passed in registers.
1483
1484 - If T is set, a return trampoline will be set up for 64-bit
1485 return values to be split into 2 32-bit registers. */
1486 long call_cookie;
1487
1488 /* This is set to nonzero when the call in question must use the Renesas ABI,
1489 even without the -mrenesas option. */
1490 int renesas_abi;
1491 };
1492
1493 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1494 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1495 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1496 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1497 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1498 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1499 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1500 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1501 #define CALL_COOKIE_INT_REG(REG, VAL) \
1502 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1503 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1504 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1505
1506 #define CUMULATIVE_ARGS struct sh_args
1507
1508 #define GET_SH_ARG_CLASS(MODE) \
1509 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1510 ? SH_ARG_FLOAT \
1511 /* There's no mention of complex float types in the SH5 ABI, so we
1512 should presumably handle them as aggregate types. */ \
1513 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1514 ? SH_ARG_INT \
1515 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1516 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1517 ? SH_ARG_FLOAT : SH_ARG_INT)
1518
1519 #define ROUND_ADVANCE(SIZE) \
1520 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1521
1522 /* Round a register number up to a proper boundary for an arg of mode
1523 MODE.
1524
1525 The SH doesn't care about double alignment, so we only
1526 round doubles to even regs when asked to explicitly. */
1527
1528 #define ROUND_REG(CUM, MODE) \
1529 (((TARGET_ALIGN_DOUBLE \
1530 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1531 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1532 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1533 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1534 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1535 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1536
1537 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1538 for a call to a function whose data type is FNTYPE.
1539 For a library call, FNTYPE is 0.
1540
1541 On SH, the offset always starts at 0: the first parm reg is always
1542 the same reg for a given argument class.
1543
1544 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1545
1546 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1547 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1548
1549 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1550 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1551
1552 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1553 This macro is only used in this file. */
1554
1555 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1556 (((TYPE) == 0 \
1557 || (! TREE_ADDRESSABLE ((TYPE)) \
1558 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1559 || ! (AGGREGATE_TYPE_P (TYPE) \
1560 || (!TARGET_FPU_ANY \
1561 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1562 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1563 && ! (CUM).force_mem \
1564 && (TARGET_SH2E \
1565 ? ((MODE) == BLKmode \
1566 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1567 + int_size_in_bytes (TYPE)) \
1568 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1569 : ((ROUND_REG((CUM), (MODE)) \
1570 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1571 <= NPARM_REGS (MODE))) \
1572 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1573
1574 /* By accident we got stuck with passing SCmode on SH4 little endian
1575 in two registers that are nominally successive - which is different from
1576 two single SFmode values, where we take endianness translation into
1577 account. That does not work at all if an odd number of registers is
1578 already in use, so that got fixed, but library functions are still more
1579 likely to use complex numbers without mixing them with SFmode arguments
1580 (which in C would have to be structures), so for the sake of ABI
1581 compatibility the way SCmode values are passed when an even number of
1582 FP registers is in use remains different from a pair of SFmode values for
1583 now.
1584 I.e.:
1585 foo (double); a: fr5,fr4
1586 foo (float a, float b); a: fr5 b: fr4
1587 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1588 this should be the other way round...
1589 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1590 #define FUNCTION_ARG_SCmode_WART 1
1591
1592 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1593 register in SHcompact mode, it must be padded in the most
1594 significant end. This means that passing it by reference wouldn't
1595 pad properly on a big-endian machine. In this particular case, we
1596 pass this argument on the stack, in a way that the call trampoline
1597 will load its value into the appropriate register. */
1598 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1599 ((MODE) == BLKmode \
1600 && TARGET_SHCOMPACT \
1601 && ! TARGET_LITTLE_ENDIAN \
1602 && int_size_in_bytes (TYPE) > 4 \
1603 && int_size_in_bytes (TYPE) < 8)
1604
1605 /* Minimum alignment for an argument to be passed by callee-copy
1606 reference. We need such arguments to be aligned to 8 byte
1607 boundaries, because they'll be loaded using quad loads. */
1608 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1609
1610 /* The SH5 ABI requires floating-point arguments to be passed to
1611 functions without a prototype in both an FP register and a regular
1612 register or the stack. When passing the argument in both FP and
1613 general-purpose registers, list the FP register first. */
1614 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1615 (gen_rtx_PARALLEL \
1616 ((MODE), \
1617 gen_rtvec (2, \
1618 gen_rtx_EXPR_LIST \
1619 (VOIDmode, \
1620 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1621 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1622 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1623 : NULL_RTX), \
1624 const0_rtx), \
1625 gen_rtx_EXPR_LIST \
1626 (VOIDmode, \
1627 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1628 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1629 + (CUM).arg_count[(int) SH_ARG_INT]) \
1630 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1631 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1632 const0_rtx))))
1633
1634 /* The SH5 ABI requires regular registers or stack slots to be
1635 reserved for floating-point arguments. Registers are taken care of
1636 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1637 Unfortunately, there's no way to just reserve a stack slot, so
1638 we'll end up needlessly storing a copy of the argument in the
1639 stack. For incoming arguments, however, the PARALLEL will be
1640 optimized to the register-only form, and the value in the stack
1641 slot won't be used at all. */
1642 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1643 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1644 ? gen_rtx_REG ((MODE), (REG)) \
1645 : gen_rtx_PARALLEL ((MODE), \
1646 gen_rtvec (2, \
1647 gen_rtx_EXPR_LIST \
1648 (VOIDmode, NULL_RTX, \
1649 const0_rtx), \
1650 gen_rtx_EXPR_LIST \
1651 (VOIDmode, gen_rtx_REG ((MODE), \
1652 (REG)), \
1653 const0_rtx))))
1654
1655 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1656 (TARGET_SH5 \
1657 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1658 || (MODE) == DCmode) \
1659 && ((CUM).arg_count[(int) SH_ARG_INT] \
1660 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1661 : GET_MODE_SIZE (MODE)) \
1662 + 7) / 8) > NPARM_REGS (SImode))
1663
1664 /* Perform any needed actions needed for a function that is receiving a
1665 variable number of arguments. */
1666
1667 /* Call the function profiler with a given profile label.
1668 We use two .aligns, so as to make sure that both the .long is aligned
1669 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1670 from the trapa instruction. */
1671
1672 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1673 { \
1674 if (TARGET_SHMEDIA) \
1675 { \
1676 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1677 fprintf((STREAM), "\ttrapa\tr0\n"); \
1678 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1679 } \
1680 else \
1681 { \
1682 fprintf((STREAM), "\t.align\t2\n"); \
1683 fprintf((STREAM), "\ttrapa\t#33\n"); \
1684 fprintf((STREAM), "\t.align\t2\n"); \
1685 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1686 } \
1687 }
1688
1689 /* Define this macro if the code for function profiling should come
1690 before the function prologue. Normally, the profiling code comes
1691 after. */
1692
1693 #define PROFILE_BEFORE_PROLOGUE
1694
1695 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1696 the stack pointer does not matter. The value is tested only in
1697 functions that have frame pointers.
1698 No definition is equivalent to always zero. */
1699
1700 #define EXIT_IGNORE_STACK 1
1701
1702 /*
1703 On the SH, the trampoline looks like
1704 2 0002 D202 mov.l l2,r2
1705 1 0000 D301 mov.l l1,r3
1706 3 0004 422B jmp @r2
1707 4 0006 0009 nop
1708 5 0008 00000000 l1: .long area
1709 6 000c 00000000 l2: .long function */
1710
1711 /* Length in units of the trampoline for entering a nested function. */
1712 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1713
1714 /* Alignment required for a trampoline in bits . */
1715 #define TRAMPOLINE_ALIGNMENT \
1716 ((CACHE_LOG < 3 || (optimize_size && ! TARGET_HARVARD)) ? 32 \
1717 : TARGET_SHMEDIA ? 256 : 64)
1718
1719 /* A C expression whose value is RTL representing the value of the return
1720 address for the frame COUNT steps up from the current frame.
1721 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1722 can ignore COUNT. */
1723
1724 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1725 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1726
1727 /* A C expression whose value is RTL representing the location of the
1728 incoming return address at the beginning of any function, before the
1729 prologue. This RTL is either a REG, indicating that the return
1730 value is saved in REG, or a MEM representing a location in
1731 the stack. */
1732 #define INCOMING_RETURN_ADDR_RTX \
1733 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1734 \f
1735 /* Addressing modes, and classification of registers for them. */
1736 #define HAVE_POST_INCREMENT TARGET_SH1
1737 #define HAVE_PRE_DECREMENT TARGET_SH1
1738
1739 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1740 ? 0 : TARGET_SH1)
1741 #define USE_LOAD_PRE_DECREMENT(mode) 0
1742 #define USE_STORE_POST_INCREMENT(mode) 0
1743 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1744 ? 0 : TARGET_SH1)
1745
1746 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1747 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1748 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1749
1750 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1751 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1752 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1753
1754 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1755
1756 /* Macros to check register numbers against specific register classes. */
1757
1758 /* These assume that REGNO is a hard or pseudo reg number.
1759 They give nonzero only if REGNO is a hard reg of the suitable class
1760 or a pseudo reg currently allocated to a suitable hard reg.
1761 Since they use reg_renumber, they are safe only once reg_renumber
1762 has been allocated, which happens in local-alloc.c. */
1763
1764 #define REGNO_OK_FOR_BASE_P(REGNO) \
1765 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1766 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1767 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1768 (TARGET_SHMEDIA \
1769 ? (GENERAL_REGISTER_P (REGNO) \
1770 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1771 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1772
1773 /* Maximum number of registers that can appear in a valid memory
1774 address. */
1775
1776 #define MAX_REGS_PER_ADDRESS 2
1777
1778 /* Recognize any constant value that is a valid address. */
1779
1780 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1781
1782 /* Nonzero if the constant value X is a legitimate general operand. */
1783 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
1784
1785 #define LEGITIMATE_CONSTANT_P(X) \
1786 (TARGET_SHMEDIA \
1787 ? ((GET_MODE (X) != DFmode \
1788 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
1789 || (X) == CONST0_RTX (GET_MODE (X)) \
1790 || ! TARGET_SHMEDIA_FPU \
1791 || TARGET_SHMEDIA64) \
1792 : (GET_CODE (X) != CONST_DOUBLE \
1793 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1794 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
1795
1796 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1797 and check its validity for a certain class.
1798 The suitable hard regs are always accepted and all pseudo regs
1799 are also accepted if STRICT is not set. */
1800
1801 /* Nonzero if X is a reg that can be used as a base reg. */
1802 #define REG_OK_FOR_BASE_P(X, STRICT) \
1803 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1804 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1805
1806 /* Nonzero if X is a reg that can be used as an index. */
1807 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1808 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1809 : REGNO (X) == R0_REG) \
1810 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1811
1812 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1813 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1814 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1815 : REGNO (X) == R0_REG && OFFSET == 0) \
1816 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1817
1818 /* Macros for extra constraints. */
1819
1820 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1821 ((GET_CODE ((OP)) == LABEL_REF) \
1822 || (GET_CODE ((OP)) == CONST \
1823 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1824 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1825 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1826
1827 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1828 (CONSTANT_P (OP) \
1829 && !CONST_INT_P (OP) \
1830 && GET_CODE (OP) != CONST_DOUBLE \
1831 && (!flag_pic \
1832 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1833 && !PIC_ADDR_P (OP) \
1834 && GET_CODE (OP) != LABEL_REF)))
1835
1836 /* Check whether OP is a datalabel unspec. */
1837 #define DATALABEL_REF_NO_CONST_P(OP) \
1838 (GET_CODE (OP) == UNSPEC \
1839 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1840 && XVECLEN ((OP), 0) == 1 \
1841 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1842
1843 #define GOT_ENTRY_P(OP) \
1844 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1845 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1846
1847 #define GOTPLT_ENTRY_P(OP) \
1848 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1849 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1850
1851 #define UNSPEC_GOTOFF_P(OP) \
1852 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1853
1854 #define GOTOFF_P(OP) \
1855 (GET_CODE (OP) == CONST \
1856 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1857 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1858 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1859 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1860
1861 #define PIC_ADDR_P(OP) \
1862 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1863 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1864
1865 #define PCREL_SYMOFF_P(OP) \
1866 (GET_CODE (OP) == CONST \
1867 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1868 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1869
1870 #define NON_PIC_REFERENCE_P(OP) \
1871 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1872 || (GET_CODE (OP) == CONST \
1873 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1874 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1875 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1876 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1877 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1878 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1879 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1880 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1881
1882 #define PIC_REFERENCE_P(OP) \
1883 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1884 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1885
1886 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1887 (flag_pic \
1888 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1889 || PCREL_SYMOFF_P (OP)) \
1890 : NON_PIC_REFERENCE_P (OP))
1891 \f
1892 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1893 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1894 || (GET_CODE (X) == SUBREG \
1895 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1896 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1897 && REG_P (SUBREG_REG (X)) \
1898 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1899
1900 /* Since this must be r0, which is a single register class, we must check
1901 SUBREGs more carefully, to be sure that we don't accept one that extends
1902 outside the class. */
1903 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1904 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1905 || (GET_CODE (X) == SUBREG \
1906 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1907 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1908 && REG_P (SUBREG_REG (X)) \
1909 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1910
1911 #ifdef REG_OK_STRICT
1912 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1913 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1914 #else
1915 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1916 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1917 #endif
1918
1919 #define ALLOW_INDEXED_ADDRESS \
1920 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1921
1922 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
1923 do { \
1924 if (sh_legitimate_index_p ((MODE), (OP))) \
1925 goto WIN; \
1926 } while (0)
1927 \f
1928 /* A C compound statement that attempts to replace X, which is an address
1929 that needs reloading, with a valid memory address for an operand of
1930 mode MODE. WIN is a C statement label elsewhere in the code. */
1931
1932 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1933 do { \
1934 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1935 goto WIN; \
1936 } while (0)
1937 \f
1938 /* Specify the machine mode that this machine uses
1939 for the index in the tablejump instruction. */
1940 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1941
1942 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1943 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1944 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1945 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1946 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1947 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1948 : SImode)
1949
1950 /* Define as C expression which evaluates to nonzero if the tablejump
1951 instruction expects the table to contain offsets from the address of the
1952 table.
1953 Do not define this if the table should contain absolute addresses. */
1954 #define CASE_VECTOR_PC_RELATIVE 1
1955
1956 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1957 #define FLOAT_TYPE_SIZE 32
1958
1959 /* Since the SH2e has only `float' support, it is desirable to make all
1960 floating point types equivalent to `float'. */
1961 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
1962
1963 /* 'char' is signed by default. */
1964 #define DEFAULT_SIGNED_CHAR 1
1965
1966 /* The type of size_t unsigned int. */
1967 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
1968
1969 #undef PTRDIFF_TYPE
1970 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
1971
1972 #define WCHAR_TYPE "short unsigned int"
1973 #define WCHAR_TYPE_SIZE 16
1974
1975 #define SH_ELF_WCHAR_TYPE "long int"
1976
1977 /* Max number of bytes we can move from memory to memory
1978 in one reasonably fast instruction. */
1979 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
1980
1981 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1982 MOVE_MAX is not a compile-time constant. */
1983 #define MAX_MOVE_MAX 8
1984
1985 /* Max number of bytes we want move_by_pieces to be able to copy
1986 efficiently. */
1987 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
1988
1989 /* Define if operations between registers always perform the operation
1990 on the full register even if a narrower mode is specified. */
1991 #define WORD_REGISTER_OPERATIONS
1992
1993 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1994 will either zero-extend or sign-extend. The value of this macro should
1995 be the code that says which one of the two operations is implicitly
1996 done, UNKNOWN if none. */
1997 /* For SHmedia, we can truncate to QImode easier using zero extension. */
1998 /* FP registers can load SImode values, but don't implicitly sign-extend
1999 them to DImode. */
2000 #define LOAD_EXTEND_OP(MODE) \
2001 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2002 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2003
2004 /* Define if loading short immediate values into registers sign extends. */
2005 #define SHORT_IMMEDIATES_SIGN_EXTEND
2006
2007 /* Nonzero if access to memory by bytes is no faster than for words. */
2008 #define SLOW_BYTE_ACCESS 1
2009
2010 /* Immediate shift counts are truncated by the output routines (or was it
2011 the assembler?). Shift counts in a register are truncated by SH. Note
2012 that the native compiler puts too large (> 32) immediate shift counts
2013 into a register and shifts by the register, letting the SH decide what
2014 to do instead of doing that itself. */
2015 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2016 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2017 expects - the sign bit is significant - so it appears that we need to
2018 leave this zero for correct SH3 code. */
2019 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2020
2021 /* All integers have the same format so truncation is easy. */
2022 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2023 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2024 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2025
2026 /* Define this if addresses of constant functions
2027 shouldn't be put through pseudo regs where they can be cse'd.
2028 Desirable on machines where ordinary constants are expensive
2029 but a CALL with constant address is cheap. */
2030 /*#define NO_FUNCTION_CSE 1*/
2031
2032 /* The machine modes of pointers and functions. */
2033 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2034 #define FUNCTION_MODE Pmode
2035
2036 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2037 are actually function calls with some special constraints on arguments
2038 and register usage.
2039
2040 These macros tell reorg that the references to arguments and
2041 register clobbers for insns of type sfunc do not appear to happen
2042 until after the millicode call. This allows reorg to put insns
2043 which set the argument registers into the delay slot of the millicode
2044 call -- thus they act more like traditional CALL_INSNs.
2045
2046 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2047 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2048 in particular. */
2049
2050 #define INSN_SETS_ARE_DELAYED(X) \
2051 ((NONJUMP_INSN_P (X) \
2052 && GET_CODE (PATTERN (X)) != SEQUENCE \
2053 && GET_CODE (PATTERN (X)) != USE \
2054 && GET_CODE (PATTERN (X)) != CLOBBER \
2055 && get_attr_is_sfunc (X)))
2056
2057 #define INSN_REFERENCES_ARE_DELAYED(X) \
2058 ((NONJUMP_INSN_P (X) \
2059 && GET_CODE (PATTERN (X)) != SEQUENCE \
2060 && GET_CODE (PATTERN (X)) != USE \
2061 && GET_CODE (PATTERN (X)) != CLOBBER \
2062 && get_attr_is_sfunc (X)))
2063
2064 \f
2065 /* Position Independent Code. */
2066
2067 /* We can't directly access anything that contains a symbol,
2068 nor can we indirect via the constant pool. */
2069 #define LEGITIMATE_PIC_OPERAND_P(X) \
2070 ((! nonpic_symbol_mentioned_p (X) \
2071 && (GET_CODE (X) != SYMBOL_REF \
2072 || ! CONSTANT_POOL_ADDRESS_P (X) \
2073 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2074 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2075
2076 #define SYMBOLIC_CONST_P(X) \
2077 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2078 && nonpic_symbol_mentioned_p (X))
2079 \f
2080 /* Compute extra cost of moving data between one register class
2081 and another. */
2082
2083 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2084 uses this information. Hence, the general register <-> floating point
2085 register information here is not used for SFmode. */
2086
2087 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2088 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2089 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2090
2091 #define REGCLASS_HAS_FP_REG(CLASS) \
2092 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2093 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2094
2095 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2096 would be so that people with slow memory systems could generate
2097 different code that does fewer memory accesses. */
2098
2099 /* A C expression for the cost of a branch instruction. A value of 1
2100 is the default; other values are interpreted relative to that.
2101 The SH1 does not have delay slots, hence we get a pipeline stall
2102 at every branch. The SH4 is superscalar, so the single delay slot
2103 is not sufficient to keep both pipelines filled. */
2104 #define BRANCH_COST(speed_p, predictable_p) \
2105 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2106 \f
2107 /* Assembler output control. */
2108
2109 /* A C string constant describing how to begin a comment in the target
2110 assembler language. The compiler assumes that the comment will end at
2111 the end of the line. */
2112 #define ASM_COMMENT_START "!"
2113
2114 #define ASM_APP_ON ""
2115 #define ASM_APP_OFF ""
2116 #define FILE_ASM_OP "\t.file\n"
2117 #define SET_ASM_OP "\t.set\t"
2118
2119 /* How to change between sections. */
2120
2121 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2122 #define DATA_SECTION_ASM_OP "\t.data"
2123
2124 #if defined CRT_BEGIN || defined CRT_END
2125 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2126 # undef TEXT_SECTION_ASM_OP
2127 # if __SHMEDIA__ == 1 && __SH5__ == 32
2128 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2129 # else
2130 # define TEXT_SECTION_ASM_OP "\t.text"
2131 # endif
2132 #endif
2133
2134
2135 /* If defined, a C expression whose value is a string containing the
2136 assembler operation to identify the following data as
2137 uninitialized global data. If not defined, and neither
2138 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2139 uninitialized global data will be output in the data section if
2140 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2141 used. */
2142 #ifndef BSS_SECTION_ASM_OP
2143 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2144 #endif
2145
2146 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2147 separate, explicit argument. If you define this macro, it is used
2148 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2149 handling the required alignment of the variable. The alignment is
2150 specified as the number of bits.
2151
2152 Try to use function `asm_output_aligned_bss' defined in file
2153 `varasm.c' when defining this macro. */
2154 #ifndef ASM_OUTPUT_ALIGNED_BSS
2155 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2156 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2157 #endif
2158
2159 /* Define this so that jump tables go in same section as the current function,
2160 which could be text or it could be a user defined section. */
2161 #define JUMP_TABLES_IN_TEXT_SECTION 1
2162
2163 #undef DO_GLOBAL_CTORS_BODY
2164 #define DO_GLOBAL_CTORS_BODY \
2165 { \
2166 typedef void (*pfunc) (void); \
2167 extern pfunc __ctors[]; \
2168 extern pfunc __ctors_end[]; \
2169 pfunc *p; \
2170 for (p = __ctors_end; p > __ctors; ) \
2171 { \
2172 (*--p)(); \
2173 } \
2174 }
2175
2176 #undef DO_GLOBAL_DTORS_BODY
2177 #define DO_GLOBAL_DTORS_BODY \
2178 { \
2179 typedef void (*pfunc) (void); \
2180 extern pfunc __dtors[]; \
2181 extern pfunc __dtors_end[]; \
2182 pfunc *p; \
2183 for (p = __dtors; p < __dtors_end; p++) \
2184 { \
2185 (*p)(); \
2186 } \
2187 }
2188
2189 #define ASM_OUTPUT_REG_PUSH(file, v) \
2190 { \
2191 if (TARGET_SHMEDIA) \
2192 { \
2193 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2194 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2195 } \
2196 else \
2197 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2198 }
2199
2200 #define ASM_OUTPUT_REG_POP(file, v) \
2201 { \
2202 if (TARGET_SHMEDIA) \
2203 { \
2204 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2205 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2206 } \
2207 else \
2208 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2209 }
2210
2211 /* DBX register number for a given compiler register number. */
2212 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2213 to match gdb. */
2214 /* svr4.h undefines this macro, yet we really want to use the same numbers
2215 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2216 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2217 register exists, so we should return -1 for invalid register numbers. */
2218 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2219
2220 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2221 used to use the encodings 245..260, but that doesn't make sense:
2222 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2223 the FP registers stay the same when switching between compact and media
2224 mode. Hence, we also need to use the same dwarf frame columns.
2225 Likewise, we need to support unwind information for SHmedia registers
2226 even in compact code. */
2227 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2228 (IN_RANGE ((REGNO), \
2229 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2230 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2231 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2232 : ((int) (REGNO) >= FIRST_FP_REG \
2233 && ((int) (REGNO) \
2234 <= (FIRST_FP_REG + \
2235 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2236 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2237 + (TARGET_SH5 ? 77 : 25)) \
2238 : XD_REGISTER_P (REGNO) \
2239 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2240 : TARGET_REGISTER_P (REGNO) \
2241 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2242 : (REGNO) == PR_REG \
2243 ? (TARGET_SH5 ? 18 : 17) \
2244 : (REGNO) == PR_MEDIA_REG \
2245 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2246 : (REGNO) == GBR_REG \
2247 ? (TARGET_SH5 ? 238 : 18) \
2248 : (REGNO) == MACH_REG \
2249 ? (TARGET_SH5 ? 239 : 20) \
2250 : (REGNO) == MACL_REG \
2251 ? (TARGET_SH5 ? 240 : 21) \
2252 : (REGNO) == T_REG \
2253 ? (TARGET_SH5 ? 242 : 22) \
2254 : (REGNO) == FPUL_REG \
2255 ? (TARGET_SH5 ? 244 : 23) \
2256 : (REGNO) == FPSCR_REG \
2257 ? (TARGET_SH5 ? 243 : 24) \
2258 : (unsigned) -1)
2259
2260 /* This is how to output a reference to a symbol_ref. On SH5,
2261 references to non-code symbols must be preceded by `datalabel'. */
2262 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2263 do \
2264 { \
2265 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2266 fputs ("datalabel ", (FILE)); \
2267 assemble_name ((FILE), XSTR ((SYM), 0)); \
2268 } \
2269 while (0)
2270
2271 /* This is how to output an assembler line
2272 that says to advance the location counter
2273 to a multiple of 2**LOG bytes. */
2274
2275 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2276 if ((LOG) != 0) \
2277 fprintf ((FILE), "\t.align %d\n", (LOG))
2278
2279 /* Globalizing directive for a label. */
2280 #define GLOBAL_ASM_OP "\t.global\t"
2281
2282 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2283
2284 /* Output a relative address table. */
2285
2286 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2287 switch (GET_MODE (BODY)) \
2288 { \
2289 case SImode: \
2290 if (TARGET_SH5) \
2291 { \
2292 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2293 (VALUE), (REL)); \
2294 break; \
2295 } \
2296 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2297 break; \
2298 case HImode: \
2299 if (TARGET_SH5) \
2300 { \
2301 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2302 (VALUE), (REL)); \
2303 break; \
2304 } \
2305 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2306 break; \
2307 case QImode: \
2308 if (TARGET_SH5) \
2309 { \
2310 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2311 (VALUE), (REL)); \
2312 break; \
2313 } \
2314 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2315 break; \
2316 default: \
2317 break; \
2318 }
2319
2320 /* Output an absolute table element. */
2321
2322 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2323 if (! optimize || TARGET_BIGTABLE) \
2324 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2325 else \
2326 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2327
2328 \f
2329 /* A C statement to be executed just prior to the output of
2330 assembler code for INSN, to modify the extracted operands so
2331 they will be output differently.
2332
2333 Here the argument OPVEC is the vector containing the operands
2334 extracted from INSN, and NOPERANDS is the number of elements of
2335 the vector which contain meaningful data for this insn.
2336 The contents of this vector are what will be used to convert the insn
2337 template into assembler code, so you can change the assembler output
2338 by changing the contents of the vector. */
2339
2340 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2341 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2342
2343 \f
2344 extern struct rtx_def *sh_compare_op0;
2345 extern struct rtx_def *sh_compare_op1;
2346
2347 /* Which processor to schedule for. The elements of the enumeration must
2348 match exactly the cpu attribute in the sh.md file. */
2349
2350 enum processor_type {
2351 PROCESSOR_SH1,
2352 PROCESSOR_SH2,
2353 PROCESSOR_SH2E,
2354 PROCESSOR_SH2A,
2355 PROCESSOR_SH3,
2356 PROCESSOR_SH3E,
2357 PROCESSOR_SH4,
2358 PROCESSOR_SH4A,
2359 PROCESSOR_SH5
2360 };
2361
2362 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2363 extern enum processor_type sh_cpu;
2364
2365 enum mdep_reorg_phase_e
2366 {
2367 SH_BEFORE_MDEP_REORG,
2368 SH_INSERT_USES_LABELS,
2369 SH_SHORTEN_BRANCHES0,
2370 SH_FIXUP_PCLOAD,
2371 SH_SHORTEN_BRANCHES1,
2372 SH_AFTER_MDEP_REORG
2373 };
2374
2375 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2376
2377 /* Handle Renesas compiler's pragmas. */
2378 #define REGISTER_TARGET_PRAGMAS() do { \
2379 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2380 c_register_pragma (0, "trapa", sh_pr_trapa); \
2381 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2382 } while (0)
2383
2384 extern tree sh_deferred_function_attributes;
2385 extern tree *sh_deferred_function_attributes_tail;
2386
2387 /* Set when processing a function with interrupt attribute. */
2388
2389 extern int current_function_interrupt;
2390
2391 \f
2392 /* Instructions with unfilled delay slots take up an
2393 extra two bytes for the nop in the delay slot.
2394 sh-dsp parallel processing insns are four bytes long. */
2395
2396 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2397 (LENGTH) += sh_insn_length_adjustment (X);
2398 \f
2399 /* Define this macro if it is advisable to hold scalars in registers
2400 in a wider mode than that declared by the program. In such cases,
2401 the value is constrained to be within the bounds of the declared
2402 type, but kept valid in the wider mode. The signedness of the
2403 extension may differ from that of the type.
2404
2405 Leaving the unsignedp unchanged gives better code than always setting it
2406 to 0. This is despite the fact that we have only signed char and short
2407 load instructions. */
2408 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2409 if (GET_MODE_CLASS (MODE) == MODE_INT \
2410 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2411 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2412 (MODE) = (TARGET_SH1 ? SImode \
2413 : TARGET_SHMEDIA32 ? SImode : DImode);
2414
2415 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2416
2417 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2418
2419 /* Better to allocate once the maximum space for outgoing args in the
2420 prologue rather than duplicate around each call. */
2421 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2422
2423 #define SH_DYNAMIC_SHIFT_COST \
2424 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (optimize_size ? 1 : 2) : 20)
2425
2426
2427 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2428
2429 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2430
2431 #define ACTUAL_NORMAL_MODE(ENTITY) \
2432 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2433
2434 #define NORMAL_MODE(ENTITY) \
2435 (sh_cfun_interrupt_handler_p () \
2436 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2437 : ACTUAL_NORMAL_MODE (ENTITY))
2438
2439 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2440
2441 #define MODE_EXIT(ENTITY) \
2442 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2443
2444 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2445 && (REGNO) == FPSCR_REG)
2446
2447 #define MODE_NEEDED(ENTITY, INSN) \
2448 (recog_memoized (INSN) >= 0 \
2449 ? get_attr_fp_mode (INSN) \
2450 : FP_MODE_NONE)
2451
2452 #define MODE_AFTER(MODE, INSN) \
2453 (TARGET_HITACHI \
2454 && recog_memoized (INSN) >= 0 \
2455 && get_attr_fp_set (INSN) != FP_SET_NONE \
2456 ? (int) get_attr_fp_set (INSN) \
2457 : (MODE))
2458
2459 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2460 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2461
2462 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2463 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2464
2465 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2466 sh_can_redirect_branch ((INSN), (SEQ))
2467
2468 #define DWARF_FRAME_RETURN_COLUMN \
2469 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2470
2471 #define EH_RETURN_DATA_REGNO(N) \
2472 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2473
2474 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2475 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2476
2477 /* We have to distinguish between code and data, so that we apply
2478 datalabel where and only where appropriate. Use sdataN for data. */
2479 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2480 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2481 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2482 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2483
2484 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2485 indirect are handled automatically. */
2486 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2487 do { \
2488 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2489 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2490 { \
2491 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2492 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2493 if (0) goto DONE; \
2494 } \
2495 } while (0)
2496
2497 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2498 /* SH constant pool breaks the devices in crtstuff.c to control section
2499 in where code resides. We have to write it as asm code. */
2500 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2501 asm (SECTION_OP "\n\
2502 mov.l 1f,r1\n\
2503 mova 2f,r0\n\
2504 braf r1\n\
2505 lds r0,pr\n\
2506 0: .p2align 2\n\
2507 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2508 2:\n" TEXT_SECTION_ASM_OP);
2509 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2510
2511 /* FIXME: middle-end support for highpart optimizations is missing. */
2512 #define high_life_started reload_in_progress
2513
2514 #endif /* ! GCC_SH_H */