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re PR target/36780 (Wrong reload generated for subreg address on SH)
[gcc.git] / gcc / config / sh / sh.h
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #ifndef GCC_SH_H
24 #define GCC_SH_H
25
26 #include "config/vxworks-dummy.h"
27
28 #define TARGET_VERSION \
29 fputs (" (Hitachi SH)", stderr);
30
31 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
32 include it here, because bconfig.h is also included by gencodes.c . */
33 /* ??? No longer true. */
34 extern int code_for_indirect_jump_scratch;
35
36 #define TARGET_CPU_CPP_BUILTINS() \
37 do { \
38 builtin_define ("__sh__"); \
39 builtin_assert ("cpu=sh"); \
40 builtin_assert ("machine=sh"); \
41 switch ((int) sh_cpu) \
42 { \
43 case PROCESSOR_SH1: \
44 builtin_define ("__sh1__"); \
45 break; \
46 case PROCESSOR_SH2: \
47 builtin_define ("__sh2__"); \
48 break; \
49 case PROCESSOR_SH2E: \
50 builtin_define ("__SH2E__"); \
51 break; \
52 case PROCESSOR_SH2A: \
53 builtin_define ("__SH2A__"); \
54 builtin_define (TARGET_SH2A_DOUBLE \
55 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
56 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
57 : "__SH2A_NOFPU__"); \
58 break; \
59 case PROCESSOR_SH3: \
60 builtin_define ("__sh3__"); \
61 builtin_define ("__SH3__"); \
62 if (TARGET_HARD_SH4) \
63 builtin_define ("__SH4_NOFPU__"); \
64 break; \
65 case PROCESSOR_SH3E: \
66 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
67 break; \
68 case PROCESSOR_SH4: \
69 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
70 break; \
71 case PROCESSOR_SH4A: \
72 builtin_define ("__SH4A__"); \
73 builtin_define (TARGET_SH4 \
74 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
75 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
76 : "__SH4_NOFPU__"); \
77 break; \
78 case PROCESSOR_SH5: \
79 { \
80 builtin_define_with_value ("__SH5__", \
81 TARGET_SHMEDIA64 ? "64" : "32", 0); \
82 builtin_define_with_value ("__SHMEDIA__", \
83 TARGET_SHMEDIA ? "1" : "0", 0); \
84 if (! TARGET_FPU_DOUBLE) \
85 builtin_define ("__SH4_NOFPU__"); \
86 } \
87 } \
88 if (TARGET_FPU_ANY) \
89 builtin_define ("__SH_FPU_ANY__"); \
90 if (TARGET_FPU_DOUBLE) \
91 builtin_define ("__SH_FPU_DOUBLE__"); \
92 if (TARGET_HITACHI) \
93 builtin_define ("__HITACHI__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
96 } while (0)
97
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
100
101 #define CONDITIONAL_REGISTER_USAGE do \
102 { \
103 int regno; \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
108 if (TARGET_SH5) \
109 { \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
114 } \
115 if (TARGET_SHMEDIA) \
116 { \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
120 } \
121 if (flag_pic) \
122 { \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
125 } \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
128 { \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
131 } \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
136 { \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
140 } \
141 else \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
145 } while (0)
146 \f
147 /* Nonzero if this is an ELF target - compile time only */
148 #define TARGET_ELF 0
149
150 /* Nonzero if we should generate code using type 2E insns. */
151 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
152
153 /* Nonzero if we should generate code using type 2A insns. */
154 #define TARGET_SH2A TARGET_HARD_SH2A
155 /* Nonzero if we should generate code using type 2A SF insns. */
156 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
157 /* Nonzero if we should generate code using type 2A DF insns. */
158 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
159
160 /* Nonzero if we should generate code using type 3E insns. */
161 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
162
163 /* Nonzero if the cache line size is 32. */
164 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
165
166 /* Nonzero if we schedule for a superscalar implementation. */
167 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
168
169 /* Nonzero if the target has separate instruction and data caches. */
170 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
171
172 /* Nonzero if a double-precision FPU is available. */
173 #define TARGET_FPU_DOUBLE \
174 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
175
176 /* Nonzero if an FPU is available. */
177 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
178
179 /* Nonzero if we should generate code using type 4 insns. */
180 #undef TARGET_SH4
181 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
182
183 /* Nonzero if we're generating code for the common subset of
184 instructions present on both SH4a and SH4al-dsp. */
185 #define TARGET_SH4A_ARCH TARGET_SH4A
186
187 /* Nonzero if we're generating code for SH4a, unless the use of the
188 FPU is disabled (which makes it compatible with SH4al-dsp). */
189 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
190
191 /* Nonzero if we should generate code using the SHcompact instruction
192 set and 32-bit ABI. */
193 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
194
195 /* Nonzero if we should generate code using the SHmedia instruction
196 set and ABI. */
197 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
198
199 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
200 ABI. */
201 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
202
203 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
204 ABI. */
205 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
206
207 /* Nonzero if we should generate code using SHmedia FPU instructions. */
208 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
209
210 /* This is not used by the SH2E calling convention */
211 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
212 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
213 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
214
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT SELECT_SH1
217 #define SUPPORT_SH1 1
218 #define SUPPORT_SH2E 1
219 #define SUPPORT_SH4 1
220 #define SUPPORT_SH4_SINGLE 1
221 #define SUPPORT_SH2A 1
222 #define SUPPORT_SH2A_SINGLE 1
223 #endif
224
225 #define TARGET_DIVIDE_INV \
226 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
227 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
228 || sh_div_strategy == SH_DIV_INV_CALL \
229 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
230 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
231 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
232 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
233 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
234 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
235 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
236 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
237 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
238 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
239 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
240 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
241
242 #define SELECT_SH1 (MASK_SH1)
243 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
244 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
245 | MASK_FPU_SINGLE)
246 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
247 | MASK_HARD_SH2A_DOUBLE \
248 | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
251 | MASK_SH1 | MASK_FPU_SINGLE)
252 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
253 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
254 | MASK_SH2 | MASK_SH1)
255 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
256 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
257 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
258 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
259 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
260 | SELECT_SH3)
261 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
262 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
263 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
264 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
265 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
266 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
267 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
268 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
269 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
270 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
271 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
272
273 #if SUPPORT_SH1
274 #define SUPPORT_SH2 1
275 #endif
276 #if SUPPORT_SH2
277 #define SUPPORT_SH3 1
278 #define SUPPORT_SH2A_NOFPU 1
279 #endif
280 #if SUPPORT_SH3
281 #define SUPPORT_SH4_NOFPU 1
282 #endif
283 #if SUPPORT_SH4_NOFPU
284 #define SUPPORT_SH4A_NOFPU 1
285 #define SUPPORT_SH4AL 1
286 #endif
287
288 #if SUPPORT_SH2E
289 #define SUPPORT_SH3E 1
290 #define SUPPORT_SH2A_SINGLE_ONLY 1
291 #endif
292 #if SUPPORT_SH3E
293 #define SUPPORT_SH4_SINGLE_ONLY 1
294 #endif
295 #if SUPPORT_SH4_SINGLE_ONLY
296 #define SUPPORT_SH4A_SINGLE_ONLY 1
297 #endif
298
299 #if SUPPORT_SH4
300 #define SUPPORT_SH4A 1
301 #endif
302
303 #if SUPPORT_SH4_SINGLE
304 #define SUPPORT_SH4A_SINGLE 1
305 #endif
306
307 #if SUPPORT_SH5_COMPAT
308 #define SUPPORT_SH5_32MEDIA 1
309 #endif
310
311 #if SUPPORT_SH5_COMPACT_NOFPU
312 #define SUPPORT_SH5_32MEDIA_NOFPU 1
313 #endif
314
315 #define SUPPORT_ANY_SH5_32MEDIA \
316 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
317 #define SUPPORT_ANY_SH5_64MEDIA \
318 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
319 #define SUPPORT_ANY_SH5 \
320 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
321
322 /* Reset all target-selection flags. */
323 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
324 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
325 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
326
327 /* This defaults us to big-endian. */
328 #ifndef TARGET_ENDIAN_DEFAULT
329 #define TARGET_ENDIAN_DEFAULT 0
330 #endif
331
332 #ifndef TARGET_OPT_DEFAULT
333 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
334 #endif
335
336 #define TARGET_DEFAULT \
337 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
338
339 #ifndef SH_MULTILIB_CPU_DEFAULT
340 #define SH_MULTILIB_CPU_DEFAULT "m1"
341 #endif
342
343 #if TARGET_ENDIAN_DEFAULT
344 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
345 #else
346 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
347 #endif
348
349 #define CPP_SPEC " %(subtarget_cpp_spec) "
350
351 #ifndef SUBTARGET_CPP_SPEC
352 #define SUBTARGET_CPP_SPEC ""
353 #endif
354
355 #ifndef SUBTARGET_EXTRA_SPECS
356 #define SUBTARGET_EXTRA_SPECS
357 #endif
358
359 #define EXTRA_SPECS \
360 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
361 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
362 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
363 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
364 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
365 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
366 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
367 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
368 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
369 SUBTARGET_EXTRA_SPECS
370
371 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
372 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
373 #else
374 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
375 #endif
376
377 #define SH_ASM_SPEC \
378 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
379 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
380 %{m2a:--isa=sh2a} \
381 %{m2a-single:--isa=sh2a} \
382 %{m2a-single-only:--isa=sh2a} \
383 %{m2a-nofpu:--isa=sh2a-nofpu} \
384 %{m5-compact*:--isa=SHcompact} \
385 %{m5-32media*:--isa=SHmedia --abi=32} \
386 %{m5-64media*:--isa=SHmedia --abi=64} \
387 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
388
389 #define ASM_SPEC SH_ASM_SPEC
390
391 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
392 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
393 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
394 #else
395 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
396 #endif
397 #endif
398
399 #if STRICT_NOFPU == 1
400 /* Strict nofpu means that the compiler should tell the assembler
401 to reject FPU instructions. E.g. from ASM inserts. */
402 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
403 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
404 #else
405 /* If there were an -isa option for sh5-nofpu then it would also go here. */
406 #define SUBTARGET_ASM_ISA_SPEC \
407 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
408 #endif
409 #else /* ! STRICT_NOFPU */
410 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
411 #endif
412
413 #ifndef SUBTARGET_ASM_SPEC
414 #define SUBTARGET_ASM_SPEC ""
415 #endif
416
417 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
418 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
419 #else
420 #define LINK_EMUL_PREFIX "sh%{ml:l}"
421 #endif
422
423 #if TARGET_CPU_DEFAULT & MASK_SH5
424 #if TARGET_CPU_DEFAULT & MASK_SH_E
425 #define LINK_DEFAULT_CPU_EMUL "32"
426 #if TARGET_CPU_DEFAULT & MASK_SH1
427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
428 #else
429 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
430 #endif /* MASK_SH1 */
431 #else /* !MASK_SH_E */
432 #define LINK_DEFAULT_CPU_EMUL "64"
433 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
434 #endif /* MASK_SH_E */
435 #define ASM_ISA_DEFAULT_SPEC \
436 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
437 #else /* !MASK_SH5 */
438 #define LINK_DEFAULT_CPU_EMUL ""
439 #define ASM_ISA_DEFAULT_SPEC ""
440 #endif /* MASK_SH5 */
441
442 #define SUBTARGET_LINK_EMUL_SUFFIX ""
443 #define SUBTARGET_LINK_SPEC ""
444
445 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
446 so that we can undo the damage without code replication. */
447 #define LINK_SPEC SH_LINK_SPEC
448
449 #define SH_LINK_SPEC "\
450 -m %(link_emul_prefix)\
451 %{m5-compact*|m5-32media*:32}\
452 %{m5-64media*:64}\
453 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
454 %(subtarget_link_emul_suffix) \
455 %{mrelax:-relax} %(subtarget_link_spec)"
456
457 #ifndef SH_DIV_STR_FOR_SIZE
458 #define SH_DIV_STR_FOR_SIZE "call"
459 #endif
460
461 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
462 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
463 do { \
464 if (LEVEL) \
465 { \
466 flag_omit_frame_pointer = -1; \
467 if (! SIZE) \
468 sh_div_str = "inv:minlat"; \
469 } \
470 if (SIZE) \
471 { \
472 target_flags |= MASK_SMALLCODE; \
473 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
474 } \
475 else \
476 { \
477 TARGET_CBRANCHDI4 = 1; \
478 TARGET_EXPAND_CBRANCHDI4 = 1; \
479 } \
480 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
481 haven't been parsed yet, hence we'd read only the default. \
482 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
483 it's OK to always set flag_branch_target_load_optimize. */ \
484 if (LEVEL > 1) \
485 { \
486 flag_branch_target_load_optimize = 1; \
487 if (! (SIZE)) \
488 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
489 } \
490 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
491 here, so leave it to OVERRIDE_OPTIONS to set \
492 flag_finite_math_only. We set it to 2 here so we know if the user \
493 explicitly requested this to be on or off. */ \
494 flag_finite_math_only = 2; \
495 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
496 the user explicitly requested this to be on or off. */ \
497 if (flag_schedule_insns > 0) \
498 flag_schedule_insns = 2; \
499 \
500 set_param_value ("simultaneous-prefetches", 2); \
501 } while (0)
502
503 #define ASSEMBLER_DIALECT assembler_dialect
504
505 extern int assembler_dialect;
506
507 enum sh_divide_strategy_e {
508 /* SH5 strategies. */
509 SH_DIV_CALL,
510 SH_DIV_CALL2,
511 SH_DIV_FP, /* We could do this also for SH4. */
512 SH_DIV_INV,
513 SH_DIV_INV_MINLAT,
514 SH_DIV_INV20U,
515 SH_DIV_INV20L,
516 SH_DIV_INV_CALL,
517 SH_DIV_INV_CALL2,
518 SH_DIV_INV_FP,
519 /* SH1 .. SH4 strategies. Because of the small number of registers
520 available, the compiler uses knowledge of the actual set of registers
521 being clobbered by the different functions called. */
522 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
523 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
524 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
525 SH_DIV_INTRINSIC
526 };
527
528 extern enum sh_divide_strategy_e sh_div_strategy;
529
530 #ifndef SH_DIV_STRATEGY_DEFAULT
531 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
532 #endif
533
534 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
535
536 extern const char *sh_fixed_range_str;
537
538 #define OVERRIDE_OPTIONS \
539 do { \
540 int regno; \
541 \
542 SUBTARGET_OVERRIDE_OPTIONS; \
543 if (flag_finite_math_only == 2) \
544 flag_finite_math_only \
545 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
546 if (TARGET_SH2E && !flag_finite_math_only) \
547 target_flags |= MASK_IEEE; \
548 sh_cpu = CPU_SH1; \
549 assembler_dialect = 0; \
550 if (TARGET_SH2) \
551 sh_cpu = CPU_SH2; \
552 if (TARGET_SH2E) \
553 sh_cpu = CPU_SH2E; \
554 if (TARGET_SH2A) \
555 { \
556 sh_cpu = CPU_SH2A; \
557 if (TARGET_SH2A_DOUBLE) \
558 target_flags |= MASK_FMOVD; \
559 } \
560 if (TARGET_SH3) \
561 sh_cpu = CPU_SH3; \
562 if (TARGET_SH3E) \
563 sh_cpu = CPU_SH3E; \
564 if (TARGET_SH4) \
565 { \
566 assembler_dialect = 1; \
567 sh_cpu = CPU_SH4; \
568 } \
569 if (TARGET_SH4A_ARCH) \
570 { \
571 assembler_dialect = 1; \
572 sh_cpu = CPU_SH4A; \
573 } \
574 if (TARGET_SH5) \
575 { \
576 sh_cpu = CPU_SH5; \
577 target_flags |= MASK_ALIGN_DOUBLE; \
578 if (TARGET_SHMEDIA_FPU) \
579 target_flags |= MASK_FMOVD; \
580 if (TARGET_SHMEDIA) \
581 { \
582 /* There are no delay slots on SHmedia. */ \
583 flag_delayed_branch = 0; \
584 /* Relaxation isn't yet supported for SHmedia */ \
585 target_flags &= ~MASK_RELAX; \
586 /* After reload, if conversion does little good but can cause \
587 ICEs: \
588 - find_if_block doesn't do anything for SH because we don't\
589 have conditional execution patterns. (We use conditional\
590 move patterns, which are handled differently, and only \
591 before reload). \
592 - find_cond_trap doesn't do anything for the SH because we \
593 don't have conditional traps. \
594 - find_if_case_1 uses redirect_edge_and_branch_force in \
595 the only path that does an optimization, and this causes \
596 an ICE when branch targets are in registers. \
597 - find_if_case_2 doesn't do anything for the SHmedia after \
598 reload except when it can redirect a tablejump - and \
599 that's rather rare. */ \
600 flag_if_conversion2 = 0; \
601 if (! strcmp (sh_div_str, "call")) \
602 sh_div_strategy = SH_DIV_CALL; \
603 else if (! strcmp (sh_div_str, "call2")) \
604 sh_div_strategy = SH_DIV_CALL2; \
605 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
606 sh_div_strategy = SH_DIV_FP; \
607 else if (! strcmp (sh_div_str, "inv")) \
608 sh_div_strategy = SH_DIV_INV; \
609 else if (! strcmp (sh_div_str, "inv:minlat")) \
610 sh_div_strategy = SH_DIV_INV_MINLAT; \
611 else if (! strcmp (sh_div_str, "inv20u")) \
612 sh_div_strategy = SH_DIV_INV20U; \
613 else if (! strcmp (sh_div_str, "inv20l")) \
614 sh_div_strategy = SH_DIV_INV20L; \
615 else if (! strcmp (sh_div_str, "inv:call2")) \
616 sh_div_strategy = SH_DIV_INV_CALL2; \
617 else if (! strcmp (sh_div_str, "inv:call")) \
618 sh_div_strategy = SH_DIV_INV_CALL; \
619 else if (! strcmp (sh_div_str, "inv:fp")) \
620 { \
621 if (TARGET_FPU_ANY) \
622 sh_div_strategy = SH_DIV_INV_FP; \
623 else \
624 sh_div_strategy = SH_DIV_INV; \
625 } \
626 TARGET_CBRANCHDI4 = 0; \
627 } \
628 } \
629 else \
630 { \
631 /* Only the sh64-elf assembler fully supports .quad properly. */\
632 targetm.asm_out.aligned_op.di = NULL; \
633 targetm.asm_out.unaligned_op.di = NULL; \
634 } \
635 if (TARGET_SH1) \
636 { \
637 if (! strcmp (sh_div_str, "call-div1")) \
638 sh_div_strategy = SH_DIV_CALL_DIV1; \
639 else if (! strcmp (sh_div_str, "call-fp") \
640 && (TARGET_FPU_DOUBLE \
641 || (TARGET_HARD_SH4 && TARGET_SH2E) \
642 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
643 sh_div_strategy = SH_DIV_CALL_FP; \
644 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
645 sh_div_strategy = SH_DIV_CALL_TABLE; \
646 else \
647 /* Pick one that makes most sense for the target in general. \
648 It is not much good to use different functions depending \
649 on -Os, since then we'll end up with two different functions \
650 when some of the code is compiled for size, and some for \
651 speed. */ \
652 \
653 /* SH4 tends to emphasize speed. */ \
654 if (TARGET_HARD_SH4) \
655 sh_div_strategy = SH_DIV_CALL_TABLE; \
656 /* These have their own way of doing things. */ \
657 else if (TARGET_SH2A) \
658 sh_div_strategy = SH_DIV_INTRINSIC; \
659 /* ??? Should we use the integer SHmedia function instead? */ \
660 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
661 sh_div_strategy = SH_DIV_CALL_FP; \
662 /* SH1 .. SH3 cores often go into small-footprint systems, so \
663 default to the smallest implementation available. */ \
664 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
665 sh_div_strategy = SH_DIV_CALL_TABLE; \
666 else \
667 sh_div_strategy = SH_DIV_CALL_DIV1; \
668 } \
669 if (!TARGET_SH1) \
670 TARGET_PRETEND_CMOVE = 0; \
671 if (sh_divsi3_libfunc[0]) \
672 ; /* User supplied - leave it alone. */ \
673 else if (TARGET_DIVIDE_CALL_FP) \
674 sh_divsi3_libfunc = "__sdivsi3_i4"; \
675 else if (TARGET_DIVIDE_CALL_TABLE) \
676 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
677 else if (TARGET_SH5) \
678 sh_divsi3_libfunc = "__sdivsi3_1"; \
679 else \
680 sh_divsi3_libfunc = "__sdivsi3"; \
681 if (sh_branch_cost == -1) \
682 sh_branch_cost \
683 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
684 \
685 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
686 if (! VALID_REGISTER_P (regno)) \
687 sh_register_names[regno][0] = '\0'; \
688 \
689 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
690 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
691 sh_additional_register_names[regno][0] = '\0'; \
692 \
693 if (flag_omit_frame_pointer < 0) \
694 { \
695 /* The debugging information is sufficient, \
696 but gdb doesn't implement this yet */ \
697 if (0) \
698 flag_omit_frame_pointer \
699 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
700 else \
701 flag_omit_frame_pointer = 0; \
702 } \
703 \
704 if ((flag_pic && ! TARGET_PREFERGOT) \
705 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
706 flag_no_function_cse = 1; \
707 \
708 if (SMALL_REGISTER_CLASSES) \
709 { \
710 /* Never run scheduling before reload, since that can \
711 break global alloc, and generates slower code anyway due \
712 to the pressure on R0. */ \
713 /* Enable sched1 for SH4; ready queue will be reordered by \
714 the target hooks when pressure is high. We can not do this for \
715 PIC, SH3 and lower as they give spill failures for R0. */ \
716 if (!TARGET_HARD_SH4 || flag_pic) \
717 flag_schedule_insns = 0; \
718 /* ??? Current exception handling places basic block boundaries \
719 after call_insns. It causes the high pressure on R0 and gives \
720 spill failures for R0 in reload. See PR 22553 and the thread \
721 on gcc-patches \
722 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
723 else if (flag_exceptions) \
724 { \
725 if (flag_schedule_insns == 1) \
726 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
727 flag_schedule_insns = 0; \
728 } \
729 } \
730 \
731 if (align_loops == 0) \
732 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
733 if (align_jumps == 0) \
734 align_jumps = 1 << CACHE_LOG; \
735 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
736 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
737 \
738 /* Allocation boundary (in *bytes*) for the code of a function. \
739 SH1: 32 bit alignment is faster, because instructions are always \
740 fetched as a pair from a longword boundary. \
741 SH2 .. SH5 : align to cache line start. */ \
742 if (align_functions == 0) \
743 align_functions \
744 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
745 /* The linker relaxation code breaks when a function contains \
746 alignments that are larger than that at the start of a \
747 compilation unit. */ \
748 if (TARGET_RELAX) \
749 { \
750 int min_align \
751 = align_loops > align_jumps ? align_loops : align_jumps; \
752 \
753 /* Also take possible .long constants / mova tables int account. */\
754 if (min_align < 4) \
755 min_align = 4; \
756 if (align_functions < min_align) \
757 align_functions = min_align; \
758 } \
759 \
760 if (sh_fixed_range_str) \
761 sh_fix_range (sh_fixed_range_str); \
762 } while (0)
763 \f
764 /* Target machine storage layout. */
765
766 /* Define this if most significant bit is lowest numbered
767 in instructions that operate on numbered bit-fields. */
768
769 #define BITS_BIG_ENDIAN 0
770
771 /* Define this if most significant byte of a word is the lowest numbered. */
772 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
773
774 /* Define this if most significant word of a multiword number is the lowest
775 numbered. */
776 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
777
778 /* Define this to set the endianness to use in libgcc2.c, which can
779 not depend on target_flags. */
780 #if defined(__LITTLE_ENDIAN__)
781 #define LIBGCC2_WORDS_BIG_ENDIAN 0
782 #else
783 #define LIBGCC2_WORDS_BIG_ENDIAN 1
784 #endif
785
786 #define MAX_BITS_PER_WORD 64
787
788 /* Width in bits of an `int'. We want just 32-bits, even if words are
789 longer. */
790 #define INT_TYPE_SIZE 32
791
792 /* Width in bits of a `long'. */
793 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
794
795 /* Width in bits of a `long long'. */
796 #define LONG_LONG_TYPE_SIZE 64
797
798 /* Width in bits of a `long double'. */
799 #define LONG_DOUBLE_TYPE_SIZE 64
800
801 /* Width of a word, in units (bytes). */
802 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
803 #define MIN_UNITS_PER_WORD 4
804
805 /* Scaling factor for Dwarf data offsets for CFI information.
806 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
807 SHmedia; however, since we do partial register saves for the registers
808 visible to SHcompact, and for target registers for SHMEDIA32, we have
809 to allow saves that are only 4-byte aligned. */
810 #define DWARF_CIE_DATA_ALIGNMENT -4
811
812 /* Width in bits of a pointer.
813 See also the macro `Pmode' defined below. */
814 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
815
816 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
817 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
818
819 /* Boundary (in *bits*) on which stack pointer should be aligned. */
820 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
821
822 /* The log (base 2) of the cache line size, in bytes. Processors prior to
823 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
824 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
825 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
826
827 /* ABI given & required minimum allocation boundary (in *bits*) for the
828 code of a function. */
829 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
830
831 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
832 the vbit must go into the delta field of
833 pointers-to-member-functions. */
834 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
835 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
836
837 /* Alignment of field after `int : 0' in a structure. */
838 #define EMPTY_FIELD_BOUNDARY 32
839
840 /* No data type wants to be aligned rounder than this. */
841 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
842
843 /* The best alignment to use in cases where we have a choice. */
844 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
845
846 /* Make strings word-aligned so strcpy from constants will be faster. */
847 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
848 ((TREE_CODE (EXP) == STRING_CST \
849 && (ALIGN) < FASTEST_ALIGNMENT) \
850 ? FASTEST_ALIGNMENT : (ALIGN))
851
852 /* get_mode_alignment assumes complex values are always held in multiple
853 registers, but that is not the case on the SH; CQImode and CHImode are
854 held in a single integer register. SH5 also holds CSImode and SCmode
855 values in integer registers. This is relevant for argument passing on
856 SHcompact as we use a stack temp in order to pass CSImode by reference. */
857 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
858 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
859 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
860 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
861 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
862
863 /* Make arrays of chars word-aligned for the same reasons. */
864 #define DATA_ALIGNMENT(TYPE, ALIGN) \
865 (TREE_CODE (TYPE) == ARRAY_TYPE \
866 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
867 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
868
869 /* Number of bits which any structure or union's size must be a
870 multiple of. Each structure or union's size is rounded up to a
871 multiple of this. */
872 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
873
874 /* Set this nonzero if move instructions will actually fail to work
875 when given unaligned data. */
876 #define STRICT_ALIGNMENT 1
877
878 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
879 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
880 barrier_align (LABEL_AFTER_BARRIER)
881
882 #define LOOP_ALIGN(A_LABEL) \
883 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
884 ? 0 : sh_loop_align (A_LABEL))
885
886 #define LABEL_ALIGN(A_LABEL) \
887 ( \
888 (PREV_INSN (A_LABEL) \
889 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
890 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
891 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
892 /* explicit alignment insn in constant tables. */ \
893 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
894 : 0)
895
896 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
897 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
898
899 /* The base two logarithm of the known minimum alignment of an insn length. */
900 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
901 (GET_CODE (A_INSN) == INSN \
902 ? 1 << TARGET_SHMEDIA \
903 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
904 ? 1 << TARGET_SHMEDIA \
905 : CACHE_LOG)
906 \f
907 /* Standard register usage. */
908
909 /* Register allocation for the Renesas calling convention:
910
911 r0 arg return
912 r1..r3 scratch
913 r4..r7 args in
914 r8..r13 call saved
915 r14 frame pointer/call saved
916 r15 stack pointer
917 ap arg pointer (doesn't really exist, always eliminated)
918 pr subroutine return address
919 t t bit
920 mach multiply/accumulate result, high part
921 macl multiply/accumulate result, low part.
922 fpul fp/int communication register
923 rap return address pointer register
924 fr0 fp arg return
925 fr1..fr3 scratch floating point registers
926 fr4..fr11 fp args in
927 fr12..fr15 call saved floating point registers */
928
929 #define MAX_REGISTER_NAME_LENGTH 5
930 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
931
932 #define SH_REGISTER_NAMES_INITIALIZER \
933 { \
934 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
935 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
936 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
937 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
938 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
939 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
940 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
941 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
942 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
943 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
944 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
945 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
946 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
947 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
948 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
949 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
950 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
951 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
952 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
953 "rap", "sfp" \
954 }
955
956 #define REGNAMES_ARR_INDEX_1(index) \
957 (sh_register_names[index])
958 #define REGNAMES_ARR_INDEX_2(index) \
959 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
960 #define REGNAMES_ARR_INDEX_4(index) \
961 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
962 #define REGNAMES_ARR_INDEX_8(index) \
963 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
964 #define REGNAMES_ARR_INDEX_16(index) \
965 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
966 #define REGNAMES_ARR_INDEX_32(index) \
967 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
968 #define REGNAMES_ARR_INDEX_64(index) \
969 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
970
971 #define REGISTER_NAMES \
972 { \
973 REGNAMES_ARR_INDEX_64 (0), \
974 REGNAMES_ARR_INDEX_64 (64), \
975 REGNAMES_ARR_INDEX_8 (128), \
976 REGNAMES_ARR_INDEX_8 (136), \
977 REGNAMES_ARR_INDEX_8 (144), \
978 REGNAMES_ARR_INDEX_2 (152) \
979 }
980
981 #define ADDREGNAMES_SIZE 32
982 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
983 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
984 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
985
986 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
987 { \
988 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
989 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
990 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
991 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
992 }
993
994 #define ADDREGNAMES_REGNO(index) \
995 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
996 : (-1))
997
998 #define ADDREGNAMES_ARR_INDEX_1(index) \
999 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1000 #define ADDREGNAMES_ARR_INDEX_2(index) \
1001 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1002 #define ADDREGNAMES_ARR_INDEX_4(index) \
1003 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1004 #define ADDREGNAMES_ARR_INDEX_8(index) \
1005 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1006 #define ADDREGNAMES_ARR_INDEX_16(index) \
1007 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1008 #define ADDREGNAMES_ARR_INDEX_32(index) \
1009 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1010
1011 #define ADDITIONAL_REGISTER_NAMES \
1012 { \
1013 ADDREGNAMES_ARR_INDEX_32 (0) \
1014 }
1015
1016 /* Number of actual hardware registers.
1017 The hardware registers are assigned numbers for the compiler
1018 from 0 to just below FIRST_PSEUDO_REGISTER.
1019 All registers that the compiler knows about must be given numbers,
1020 even those that are not normally considered general registers. */
1021
1022 /* There are many other relevant definitions in sh.md's md_constants. */
1023
1024 #define FIRST_GENERAL_REG R0_REG
1025 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1026 #define FIRST_FP_REG DR0_REG
1027 #define LAST_FP_REG (FIRST_FP_REG + \
1028 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1029 #define FIRST_XD_REG XD0_REG
1030 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1031 #define FIRST_TARGET_REG TR0_REG
1032 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1033
1034 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
1035
1036 #define FIRST_BANKED_REG R0_REG
1037 #define LAST_BANKED_REG R7_REG
1038
1039 #define BANKED_REGISTER_P(REGNO) \
1040 IN_RANGE ((REGNO), \
1041 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
1042 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
1043
1044 #define GENERAL_REGISTER_P(REGNO) \
1045 IN_RANGE ((REGNO), \
1046 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1047 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1048
1049 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1050 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1051 || ((REGNO) == FRAME_POINTER_REGNUM))
1052
1053 #define FP_REGISTER_P(REGNO) \
1054 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1055
1056 #define XD_REGISTER_P(REGNO) \
1057 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1058
1059 #define FP_OR_XD_REGISTER_P(REGNO) \
1060 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1061
1062 #define FP_ANY_REGISTER_P(REGNO) \
1063 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1064
1065 #define SPECIAL_REGISTER_P(REGNO) \
1066 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1067 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1068
1069 #define TARGET_REGISTER_P(REGNO) \
1070 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1071
1072 #define SHMEDIA_REGISTER_P(REGNO) \
1073 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1074 || TARGET_REGISTER_P (REGNO))
1075
1076 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1077 that should be fixed. */
1078 #define VALID_REGISTER_P(REGNO) \
1079 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1080 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1081 || (REGNO) == FRAME_POINTER_REGNUM \
1082 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1083 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1084
1085 /* The mode that should be generally used to store a register by
1086 itself in the stack, or to load it back. */
1087 #define REGISTER_NATURAL_MODE(REGNO) \
1088 (FP_REGISTER_P (REGNO) ? SFmode \
1089 : XD_REGISTER_P (REGNO) ? DFmode \
1090 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1091 ? DImode \
1092 : SImode)
1093
1094 #define FIRST_PSEUDO_REGISTER 154
1095
1096 /* Don't count soft frame pointer. */
1097 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1098
1099 /* 1 for registers that have pervasive standard uses
1100 and are not available for the register allocator.
1101
1102 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1103 It is 32 bits wide for SH2. */
1104
1105 #define FIXED_REGISTERS \
1106 { \
1107 /* Regular registers. */ \
1108 0, 0, 0, 0, 0, 0, 0, 0, \
1109 0, 0, 0, 0, 0, 0, 0, 1, \
1110 /* r16 is reserved, r18 is the former pr. */ \
1111 1, 0, 0, 0, 0, 0, 0, 0, \
1112 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1113 /* r26 is a global variable data pointer; r27 is for constants. */ \
1114 1, 1, 1, 1, 0, 0, 0, 0, \
1115 0, 0, 0, 0, 0, 0, 0, 0, \
1116 0, 0, 0, 0, 0, 0, 0, 0, \
1117 0, 0, 0, 0, 0, 0, 0, 0, \
1118 0, 0, 0, 0, 0, 0, 0, 1, \
1119 /* FP registers. */ \
1120 0, 0, 0, 0, 0, 0, 0, 0, \
1121 0, 0, 0, 0, 0, 0, 0, 0, \
1122 0, 0, 0, 0, 0, 0, 0, 0, \
1123 0, 0, 0, 0, 0, 0, 0, 0, \
1124 0, 0, 0, 0, 0, 0, 0, 0, \
1125 0, 0, 0, 0, 0, 0, 0, 0, \
1126 0, 0, 0, 0, 0, 0, 0, 0, \
1127 0, 0, 0, 0, 0, 0, 0, 0, \
1128 /* Branch target registers. */ \
1129 0, 0, 0, 0, 0, 0, 0, 0, \
1130 /* XD registers. */ \
1131 0, 0, 0, 0, 0, 0, 0, 0, \
1132 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1133 1, 1, 1, 1, 1, 1, 0, 1, \
1134 /*"rap", "sfp" */ \
1135 1, 1, \
1136 }
1137
1138 /* 1 for registers not available across function calls.
1139 These must include the FIXED_REGISTERS and also any
1140 registers that can be used without being saved.
1141 The latter must include the registers where values are returned
1142 and the register where structure-value addresses are passed.
1143 Aside from that, you can include as many other registers as you like. */
1144
1145 #define CALL_USED_REGISTERS \
1146 { \
1147 /* Regular registers. */ \
1148 1, 1, 1, 1, 1, 1, 1, 1, \
1149 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1150 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1151 across SH5 function calls. */ \
1152 0, 0, 0, 0, 0, 0, 0, 1, \
1153 1, 1, 1, 1, 1, 1, 1, 1, \
1154 1, 1, 1, 1, 0, 0, 0, 0, \
1155 0, 0, 0, 0, 1, 1, 1, 1, \
1156 1, 1, 1, 1, 0, 0, 0, 0, \
1157 0, 0, 0, 0, 0, 0, 0, 0, \
1158 0, 0, 0, 0, 1, 1, 1, 1, \
1159 /* FP registers. */ \
1160 1, 1, 1, 1, 1, 1, 1, 1, \
1161 1, 1, 1, 1, 0, 0, 0, 0, \
1162 1, 1, 1, 1, 1, 1, 1, 1, \
1163 1, 1, 1, 1, 1, 1, 1, 1, \
1164 1, 1, 1, 1, 0, 0, 0, 0, \
1165 0, 0, 0, 0, 0, 0, 0, 0, \
1166 0, 0, 0, 0, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 /* Branch target registers. */ \
1169 1, 1, 1, 1, 1, 0, 0, 0, \
1170 /* XD registers. */ \
1171 1, 1, 1, 1, 1, 1, 0, 0, \
1172 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1173 1, 1, 1, 1, 1, 1, 1, 1, \
1174 /*"rap", "sfp" */ \
1175 1, 1, \
1176 }
1177
1178 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1179 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1180 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1181
1182 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1183 across SHcompact function calls. We can't tell whether a called
1184 function is SHmedia or SHcompact, so we assume it may be when
1185 compiling SHmedia code with the 32-bit ABI, since that's the only
1186 ABI that can be linked with SHcompact code. */
1187 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1188 (TARGET_SHMEDIA32 \
1189 && GET_MODE_SIZE (MODE) > 4 \
1190 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1191 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1192 || TARGET_REGISTER_P (REGNO) \
1193 || (REGNO) == PR_MEDIA_REG))
1194
1195 /* Return number of consecutive hard regs needed starting at reg REGNO
1196 to hold something of mode MODE.
1197 This is ordinarily the length in words of a value of mode MODE
1198 but can be less for certain modes in special long registers.
1199
1200 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1201
1202 #define HARD_REGNO_NREGS(REGNO, MODE) \
1203 (XD_REGISTER_P (REGNO) \
1204 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1205 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1206 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1207 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1208
1209 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1210 We can allow any mode in any general register. The special registers
1211 only allow SImode. Don't allow any mode in the PR. */
1212
1213 /* We cannot hold DCmode values in the XD registers because alter_reg
1214 handles subregs of them incorrectly. We could work around this by
1215 spacing the XD registers like the DR registers, but this would require
1216 additional memory in every compilation to hold larger register vectors.
1217 We could hold SFmode / SCmode values in XD registers, but that
1218 would require a tertiary reload when reloading from / to memory,
1219 and a secondary reload to reload from / to general regs; that
1220 seems to be a loosing proposition. */
1221 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1222 it won't be ferried through GP registers first. */
1223 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1224 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1225 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1226 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1227 ? 1 \
1228 : (MODE) == V2SFmode \
1229 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1230 || GENERAL_REGISTER_P (REGNO)) \
1231 : (MODE) == V4SFmode \
1232 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1233 || GENERAL_REGISTER_P (REGNO)) \
1234 : (MODE) == V16SFmode \
1235 ? (TARGET_SHMEDIA \
1236 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1237 : (REGNO) == FIRST_XD_REG) \
1238 : FP_REGISTER_P (REGNO) \
1239 ? ((MODE) == SFmode || (MODE) == SImode \
1240 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1241 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1242 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1243 || (MODE) == V2SFmode || (MODE) == TImode))) \
1244 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1245 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1246 && (MODE) == TImode \
1247 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1248 : XD_REGISTER_P (REGNO) \
1249 ? (MODE) == DFmode \
1250 : TARGET_REGISTER_P (REGNO) \
1251 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1252 : (REGNO) == PR_REG ? (MODE) == SImode \
1253 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1254 : 1)
1255
1256 /* Value is 1 if it is a good idea to tie two pseudo registers
1257 when one has mode MODE1 and one has mode MODE2.
1258 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1259 for any hard reg, then this must be 0 for correct output.
1260 That's the case for xd registers: we don't hold SFmode values in
1261 them, so we can't tie an SFmode pseudos with one in another
1262 floating-point mode. */
1263
1264 #define MODES_TIEABLE_P(MODE1, MODE2) \
1265 ((MODE1) == (MODE2) \
1266 || (TARGET_SHMEDIA \
1267 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1268 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1269 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1270 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1271 && (GET_MODE_SIZE (MODE2) <= 4)) \
1272 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1273
1274 /* A C expression that is nonzero if hard register NEW_REG can be
1275 considered for use as a rename register for OLD_REG register */
1276
1277 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1278 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1279
1280 /* Specify the registers used for certain standard purposes.
1281 The values of these macros are register numbers. */
1282
1283 /* Define this if the program counter is overloaded on a register. */
1284 /* #define PC_REGNUM 15*/
1285
1286 /* Register to use for pushing function arguments. */
1287 #define STACK_POINTER_REGNUM SP_REG
1288
1289 /* Base register for access to local variables of the function. */
1290 #define HARD_FRAME_POINTER_REGNUM FP_REG
1291
1292 /* Base register for access to local variables of the function. */
1293 #define FRAME_POINTER_REGNUM 153
1294
1295 /* Fake register that holds the address on the stack of the
1296 current function's return address. */
1297 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1298
1299 /* Register to hold the addressing base for position independent
1300 code access to data items. */
1301 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1302
1303 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1304
1305 /* Value should be nonzero if functions must have frame pointers.
1306 Zero means the frame pointer need not be set up (and parms may be accessed
1307 via the stack pointer) in functions that seem suitable. */
1308
1309 #define FRAME_POINTER_REQUIRED 0
1310
1311 /* Definitions for register eliminations.
1312
1313 We have three registers that can be eliminated on the SH. First, the
1314 frame pointer register can often be eliminated in favor of the stack
1315 pointer register. Secondly, the argument pointer register can always be
1316 eliminated; it is replaced with either the stack or frame pointer.
1317 Third, there is the return address pointer, which can also be replaced
1318 with either the stack or the frame pointer. */
1319
1320 /* This is an array of structures. Each structure initializes one pair
1321 of eliminable registers. The "from" register number is given first,
1322 followed by "to". Eliminations of the same "from" register are listed
1323 in order of preference. */
1324
1325 /* If you add any registers here that are not actually hard registers,
1326 and that have any alternative of elimination that doesn't always
1327 apply, you need to amend calc_live_regs to exclude it, because
1328 reload spills all eliminable registers where it sees an
1329 can_eliminate == 0 entry, thus making them 'live' .
1330 If you add any hard registers that can be eliminated in different
1331 ways, you have to patch reload to spill them only when all alternatives
1332 of elimination fail. */
1333
1334 #define ELIMINABLE_REGS \
1335 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1336 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1337 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1338 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1339 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1340 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1341 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1342
1343 /* Given FROM and TO register numbers, say whether this elimination
1344 is allowed. */
1345 #define CAN_ELIMINATE(FROM, TO) \
1346 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1347
1348 /* Define the offset between two registers, one to be eliminated, and the other
1349 its replacement, at the start of a routine. */
1350
1351 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1352 OFFSET = initial_elimination_offset ((FROM), (TO))
1353
1354 /* Base register for access to arguments of the function. */
1355 #define ARG_POINTER_REGNUM AP_REG
1356
1357 /* Register in which the static-chain is passed to a function. */
1358 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1359
1360 /* Don't default to pcc-struct-return, because we have already specified
1361 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1362 target hook. */
1363
1364 #define DEFAULT_PCC_STRUCT_RETURN 0
1365
1366 #define SHMEDIA_REGS_STACK_ADJUST() \
1367 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1368 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1369 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1370 : 0)
1371
1372 \f
1373 /* Define the classes of registers for register constraints in the
1374 machine description. Also define ranges of constants.
1375
1376 One of the classes must always be named ALL_REGS and include all hard regs.
1377 If there is more than one class, another class must be named NO_REGS
1378 and contain no registers.
1379
1380 The name GENERAL_REGS must be the name of a class (or an alias for
1381 another name such as ALL_REGS). This is the class of registers
1382 that is allowed by "g" or "r" in a register constraint.
1383 Also, registers outside this class are allocated only when
1384 instructions express preferences for them.
1385
1386 The classes must be numbered in nondecreasing order; that is,
1387 a larger-numbered class must never be contained completely
1388 in a smaller-numbered class.
1389
1390 For any two classes, it is very desirable that there be another
1391 class that represents their union. */
1392
1393 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1394 be used as the destination of some of the arithmetic ops. There are
1395 also some special purpose registers; the T bit register, the
1396 Procedure Return Register and the Multiply Accumulate Registers. */
1397 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1398 reg_class_subunion. We don't want to have an actual union class
1399 of these, because it would only be used when both classes are calculated
1400 to give the same cost, but there is only one FPUL register.
1401 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1402 applying to the actual instruction alternative considered. E.g., the
1403 y/r alternative of movsi_ie is considered to have no more cost that
1404 the r/r alternative, which is patently untrue. */
1405
1406 enum reg_class
1407 {
1408 NO_REGS,
1409 R0_REGS,
1410 PR_REGS,
1411 T_REGS,
1412 MAC_REGS,
1413 FPUL_REGS,
1414 SIBCALL_REGS,
1415 GENERAL_REGS,
1416 FP0_REGS,
1417 FP_REGS,
1418 DF_HI_REGS,
1419 DF_REGS,
1420 FPSCR_REGS,
1421 GENERAL_FP_REGS,
1422 GENERAL_DF_REGS,
1423 TARGET_REGS,
1424 ALL_REGS,
1425 LIM_REG_CLASSES
1426 };
1427
1428 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1429
1430 /* Give names of register classes as strings for dump file. */
1431 #define REG_CLASS_NAMES \
1432 { \
1433 "NO_REGS", \
1434 "R0_REGS", \
1435 "PR_REGS", \
1436 "T_REGS", \
1437 "MAC_REGS", \
1438 "FPUL_REGS", \
1439 "SIBCALL_REGS", \
1440 "GENERAL_REGS", \
1441 "FP0_REGS", \
1442 "FP_REGS", \
1443 "DF_HI_REGS", \
1444 "DF_REGS", \
1445 "FPSCR_REGS", \
1446 "GENERAL_FP_REGS", \
1447 "GENERAL_DF_REGS", \
1448 "TARGET_REGS", \
1449 "ALL_REGS", \
1450 }
1451
1452 /* Define which registers fit in which classes.
1453 This is an initializer for a vector of HARD_REG_SET
1454 of length N_REG_CLASSES. */
1455
1456 #define REG_CLASS_CONTENTS \
1457 { \
1458 /* NO_REGS: */ \
1459 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1460 /* R0_REGS: */ \
1461 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1462 /* PR_REGS: */ \
1463 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1464 /* T_REGS: */ \
1465 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1466 /* MAC_REGS: */ \
1467 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1468 /* FPUL_REGS: */ \
1469 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1470 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1471 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1472 /* GENERAL_REGS: */ \
1473 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1474 /* FP0_REGS: */ \
1475 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1476 /* FP_REGS: */ \
1477 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1478 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1479 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1480 /* DF_REGS: */ \
1481 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1482 /* FPSCR_REGS: */ \
1483 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1484 /* GENERAL_FP_REGS: */ \
1485 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1486 /* GENERAL_DF_REGS: */ \
1487 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1488 /* TARGET_REGS: */ \
1489 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1490 /* ALL_REGS: */ \
1491 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1492 }
1493
1494 /* The same information, inverted:
1495 Return the class number of the smallest class containing
1496 reg number REGNO. This could be a conditional expression
1497 or could index an array. */
1498
1499 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1500 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1501
1502 /* When defined, the compiler allows registers explicitly used in the
1503 rtl to be used as spill registers but prevents the compiler from
1504 extending the lifetime of these registers. */
1505
1506 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1507
1508 /* The order in which register should be allocated. */
1509 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1510 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1511 spilled or used otherwise, we better have the FP_REGS allocated first. */
1512 #define REG_ALLOC_ORDER \
1513 {/* Caller-saved FPRs */ \
1514 65, 66, 67, 68, 69, 70, 71, 64, \
1515 72, 73, 74, 75, 80, 81, 82, 83, \
1516 84, 85, 86, 87, 88, 89, 90, 91, \
1517 92, 93, 94, 95, 96, 97, 98, 99, \
1518 /* Callee-saved FPRs */ \
1519 76, 77, 78, 79,100,101,102,103, \
1520 104,105,106,107,108,109,110,111, \
1521 112,113,114,115,116,117,118,119, \
1522 120,121,122,123,124,125,126,127, \
1523 136,137,138,139,140,141,142,143, \
1524 /* FPSCR */ 151, \
1525 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1526 1, 2, 3, 7, 6, 5, 4, 0, \
1527 8, 9, 17, 19, 20, 21, 22, 23, \
1528 36, 37, 38, 39, 40, 41, 42, 43, \
1529 60, 61, 62, \
1530 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1531 10, 11, 12, 13, 14, 18, \
1532 /* SH5 callee-saved GPRs */ \
1533 28, 29, 30, 31, 32, 33, 34, 35, \
1534 44, 45, 46, 47, 48, 49, 50, 51, \
1535 52, 53, 54, 55, 56, 57, 58, 59, \
1536 /* FPUL */ 150, \
1537 /* SH5 branch target registers */ \
1538 128,129,130,131,132,133,134,135, \
1539 /* Fixed registers */ \
1540 15, 16, 24, 25, 26, 27, 63,144, \
1541 145,146,147,148,149,152,153 }
1542
1543 /* The class value for index registers, and the one for base regs. */
1544 #define INDEX_REG_CLASS \
1545 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1546 #define BASE_REG_CLASS GENERAL_REGS
1547 \f
1548 /* Defines for sh.md and constraints.md. */
1549
1550 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1551 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1552 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1553 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1554 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1555 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1556 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1557 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1558
1559 #define CONST_OK_FOR_J16(VALUE) \
1560 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1561 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1562
1563 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1564 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1565
1566 /* Given an rtx X being reloaded into a reg required to be
1567 in class CLASS, return the class of reg to actually use.
1568 In general this is just CLASS; but on some machines
1569 in some cases it is preferable to use a more restrictive class. */
1570
1571 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1572 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1573 && (GET_CODE (X) == CONST_DOUBLE \
1574 || GET_CODE (X) == SYMBOL_REF \
1575 || PIC_DIRECT_ADDR_P (X)) \
1576 ? GENERAL_REGS \
1577 : (CLASS)) \
1578
1579 #if 0
1580 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1581 ((((REGCLASS_HAS_FP_REG (CLASS) \
1582 && (GET_CODE (X) == REG \
1583 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1584 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1585 && TARGET_FMOVD)))) \
1586 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1587 && GET_CODE (X) == REG \
1588 && FP_REGISTER_P (REGNO (X)))) \
1589 && ! TARGET_SHMEDIA \
1590 && ((MODE) == SFmode || (MODE) == SImode)) \
1591 ? FPUL_REGS \
1592 : (((CLASS) == FPUL_REGS \
1593 || (REGCLASS_HAS_FP_REG (CLASS) \
1594 && ! TARGET_SHMEDIA && MODE == SImode)) \
1595 && (GET_CODE (X) == MEM \
1596 || (GET_CODE (X) == REG \
1597 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1598 || REGNO (X) == T_REG \
1599 || system_reg_operand (X, VOIDmode))))) \
1600 ? GENERAL_REGS \
1601 : (((CLASS) == TARGET_REGS \
1602 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1603 && !satisfies_constraint_Csy (X) \
1604 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1605 ? GENERAL_REGS \
1606 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1607 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1608 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1609 ? GENERAL_REGS \
1610 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1611 && TARGET_REGISTER_P (REGNO (X))) \
1612 ? GENERAL_REGS : (ELSE))
1613
1614 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1615 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1616
1617 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1618 ((REGCLASS_HAS_FP_REG (CLASS) \
1619 && ! TARGET_SHMEDIA \
1620 && immediate_operand ((X), (MODE)) \
1621 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1622 && (MODE) == SFmode && fldi_ok ())) \
1623 ? R0_REGS \
1624 : ((CLASS) == FPUL_REGS \
1625 && ((GET_CODE (X) == REG \
1626 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1627 || REGNO (X) == T_REG)) \
1628 || GET_CODE (X) == PLUS)) \
1629 ? GENERAL_REGS \
1630 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1631 ? (satisfies_constraint_I08 (X) \
1632 ? GENERAL_REGS \
1633 : R0_REGS) \
1634 : ((CLASS) == FPSCR_REGS \
1635 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1636 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1637 ? GENERAL_REGS \
1638 : (REGCLASS_HAS_FP_REG (CLASS) \
1639 && TARGET_SHMEDIA \
1640 && immediate_operand ((X), (MODE)) \
1641 && (X) != CONST0_RTX (GET_MODE (X)) \
1642 && GET_MODE (X) != V4SFmode) \
1643 ? GENERAL_REGS \
1644 : (((MODE) == QImode || (MODE) == HImode) \
1645 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1646 ? GENERAL_REGS \
1647 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1648 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1649 ? TARGET_REGS \
1650 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1651 #endif
1652
1653 /* Return the maximum number of consecutive registers
1654 needed to represent mode MODE in a register of class CLASS.
1655
1656 If TARGET_SHMEDIA, we need two FP registers per word.
1657 Otherwise we will need at most one register per word. */
1658 #define CLASS_MAX_NREGS(CLASS, MODE) \
1659 (TARGET_SHMEDIA \
1660 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1661 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1662 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1663
1664 /* If defined, gives a class of registers that cannot be used as the
1665 operand of a SUBREG that changes the mode of the object illegally. */
1666 /* ??? We need to renumber the internal numbers for the frnn registers
1667 when in little endian in order to allow mode size changes. */
1668
1669 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1670 sh_cannot_change_mode_class (FROM, TO, CLASS)
1671 \f
1672 /* Stack layout; function entry, exit and calling. */
1673
1674 /* Define the number of registers that can hold parameters.
1675 These macros are used only in other macro definitions below. */
1676
1677 #define NPARM_REGS(MODE) \
1678 (TARGET_FPU_ANY && (MODE) == SFmode \
1679 ? (TARGET_SH5 ? 12 : 8) \
1680 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1681 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1682 ? (TARGET_SH5 ? 12 : 8) \
1683 : (TARGET_SH5 ? 8 : 4))
1684
1685 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1686 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1687
1688 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1689 #define FIRST_FP_RET_REG FIRST_FP_REG
1690
1691 /* Define this if pushing a word on the stack
1692 makes the stack pointer a smaller address. */
1693 #define STACK_GROWS_DOWNWARD
1694
1695 /* Define this macro to nonzero if the addresses of local variable slots
1696 are at negative offsets from the frame pointer. */
1697 #define FRAME_GROWS_DOWNWARD 1
1698
1699 /* Offset from the frame pointer to the first local variable slot to
1700 be allocated. */
1701 #define STARTING_FRAME_OFFSET 0
1702
1703 /* If we generate an insn to push BYTES bytes,
1704 this says how many the stack pointer really advances by. */
1705 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1706 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1707 do correct alignment. */
1708 #if 0
1709 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1710 #endif
1711
1712 /* Offset of first parameter from the argument pointer register value. */
1713 #define FIRST_PARM_OFFSET(FNDECL) 0
1714
1715 /* Value is the number of byte of arguments automatically
1716 popped when returning from a subroutine call.
1717 FUNDECL is the declaration node of the function (as a tree),
1718 FUNTYPE is the data type of the function (as a tree),
1719 or for a library call it is an identifier node for the subroutine name.
1720 SIZE is the number of bytes of arguments passed on the stack.
1721
1722 On the SH, the caller does not pop any of its arguments that were passed
1723 on the stack. */
1724 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1725
1726 /* Value is the number of bytes of arguments automatically popped when
1727 calling a subroutine.
1728 CUM is the accumulated argument list.
1729
1730 On SHcompact, the call trampoline pops arguments off the stack. */
1731 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1732
1733 /* Some subroutine macros specific to this machine. */
1734
1735 #define BASE_RETURN_VALUE_REG(MODE) \
1736 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1737 ? FIRST_FP_RET_REG \
1738 : TARGET_FPU_ANY && (MODE) == SCmode \
1739 ? FIRST_FP_RET_REG \
1740 : (TARGET_FPU_DOUBLE \
1741 && ((MODE) == DFmode || (MODE) == SFmode \
1742 || (MODE) == DCmode || (MODE) == SCmode )) \
1743 ? FIRST_FP_RET_REG \
1744 : FIRST_RET_REG)
1745
1746 #define BASE_ARG_REG(MODE) \
1747 ((TARGET_SH2E && ((MODE) == SFmode)) \
1748 ? FIRST_FP_PARM_REG \
1749 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1750 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1751 ? FIRST_FP_PARM_REG \
1752 : FIRST_PARM_REG)
1753
1754 /* Define how to find the value returned by a function.
1755 VALTYPE is the data type of the value (as a tree).
1756 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1757 otherwise, FUNC is 0.
1758 For the SH, this is like LIBCALL_VALUE, except that we must change the
1759 mode like PROMOTE_MODE does.
1760 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1761 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1762
1763 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1764 gen_rtx_REG ( \
1765 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1766 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1767 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1768 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1769 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1770 || TREE_CODE (VALTYPE) == REAL_TYPE \
1771 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1772 && sh_promote_prototypes (VALTYPE) \
1773 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1774 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1775
1776 /* Define how to find the value returned by a library function
1777 assuming the value has mode MODE. */
1778 #define LIBCALL_VALUE(MODE) \
1779 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1780
1781 /* 1 if N is a possible register number for a function value. */
1782 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1783 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1784 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1785
1786 /* 1 if N is a possible register number for function argument passing. */
1787 /* ??? There are some callers that pass REGNO as int, and others that pass
1788 it as unsigned. We get warnings unless we do casts everywhere. */
1789 #define FUNCTION_ARG_REGNO_P(REGNO) \
1790 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1791 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1792 || (TARGET_FPU_ANY \
1793 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1794 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1795 + NPARM_REGS (SFmode))))
1796 \f
1797 /* Define a data type for recording info about an argument list
1798 during the scan of that argument list. This data type should
1799 hold all necessary information about the function itself
1800 and about the args processed so far, enough to enable macros
1801 such as FUNCTION_ARG to determine where the next arg should go.
1802
1803 On SH, this is a single integer, which is a number of words
1804 of arguments scanned so far (including the invisible argument,
1805 if any, which holds the structure-value-address).
1806 Thus NARGREGS or more means all following args should go on the stack. */
1807
1808 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1809 struct sh_args {
1810 int arg_count[2];
1811 int force_mem;
1812 /* Nonzero if a prototype is available for the function. */
1813 int prototype_p;
1814 /* The number of an odd floating-point register, that should be used
1815 for the next argument of type float. */
1816 int free_single_fp_reg;
1817 /* Whether we're processing an outgoing function call. */
1818 int outgoing;
1819 /* The number of general-purpose registers that should have been
1820 used to pass partial arguments, that are passed totally on the
1821 stack. On SHcompact, a call trampoline will pop them off the
1822 stack before calling the actual function, and, if the called
1823 function is implemented in SHcompact mode, the incoming arguments
1824 decoder will push such arguments back onto the stack. For
1825 incoming arguments, STACK_REGS also takes into account other
1826 arguments passed by reference, that the decoder will also push
1827 onto the stack. */
1828 int stack_regs;
1829 /* The number of general-purpose registers that should have been
1830 used to pass arguments, if the arguments didn't have to be passed
1831 by reference. */
1832 int byref_regs;
1833 /* Set as by shcompact_byref if the current argument is to be passed
1834 by reference. */
1835 int byref;
1836
1837 /* call_cookie is a bitmask used by call expanders, as well as
1838 function prologue and epilogues, to allow SHcompact to comply
1839 with the SH5 32-bit ABI, that requires 64-bit registers to be
1840 used even though only the lower 32-bit half is visible in
1841 SHcompact mode. The strategy is to call SHmedia trampolines.
1842
1843 The alternatives for each of the argument-passing registers are
1844 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1845 contents from the address in it; (d) add 8 to it, storing the
1846 result in the next register, then (c); (e) copy it from some
1847 floating-point register,
1848
1849 Regarding copies from floating-point registers, r2 may only be
1850 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1851 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1852 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1853 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1854 dr10.
1855
1856 The bit mask is structured as follows:
1857
1858 - 1 bit to tell whether to set up a return trampoline.
1859
1860 - 3 bits to count the number consecutive registers to pop off the
1861 stack.
1862
1863 - 4 bits for each of r9, r8, r7 and r6.
1864
1865 - 3 bits for each of r5, r4, r3 and r2.
1866
1867 - 3 bits set to 0 (the most significant ones)
1868
1869 3 2 1 0
1870 1098 7654 3210 9876 5432 1098 7654 3210
1871 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1872 2223 3344 4555 6666 7777 8888 9999 SSS-
1873
1874 - If F is set, the register must be copied from an FP register,
1875 whose number is encoded in the remaining bits.
1876
1877 - Else, if L is set, the register must be loaded from the address
1878 contained in it. If the P bit is *not* set, the address of the
1879 following dword should be computed first, and stored in the
1880 following register.
1881
1882 - Else, if P is set, the register alone should be popped off the
1883 stack.
1884
1885 - After all this processing, the number of registers represented
1886 in SSS will be popped off the stack. This is an optimization
1887 for pushing/popping consecutive registers, typically used for
1888 varargs and large arguments partially passed in registers.
1889
1890 - If T is set, a return trampoline will be set up for 64-bit
1891 return values to be split into 2 32-bit registers. */
1892 long call_cookie;
1893
1894 /* This is set to nonzero when the call in question must use the Renesas ABI,
1895 even without the -mrenesas option. */
1896 int renesas_abi;
1897 };
1898
1899 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1900 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1901 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1902 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1903 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1904 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1905 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1906 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1907 #define CALL_COOKIE_INT_REG(REG, VAL) \
1908 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1909 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1910 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1911
1912 #define CUMULATIVE_ARGS struct sh_args
1913
1914 #define GET_SH_ARG_CLASS(MODE) \
1915 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1916 ? SH_ARG_FLOAT \
1917 /* There's no mention of complex float types in the SH5 ABI, so we
1918 should presumably handle them as aggregate types. */ \
1919 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1920 ? SH_ARG_INT \
1921 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1922 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1923 ? SH_ARG_FLOAT : SH_ARG_INT)
1924
1925 #define ROUND_ADVANCE(SIZE) \
1926 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1927
1928 /* Round a register number up to a proper boundary for an arg of mode
1929 MODE.
1930
1931 The SH doesn't care about double alignment, so we only
1932 round doubles to even regs when asked to explicitly. */
1933
1934 #define ROUND_REG(CUM, MODE) \
1935 (((TARGET_ALIGN_DOUBLE \
1936 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1937 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1938 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1939 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1940 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1941 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1942
1943 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1944 for a call to a function whose data type is FNTYPE.
1945 For a library call, FNTYPE is 0.
1946
1947 On SH, the offset always starts at 0: the first parm reg is always
1948 the same reg for a given argument class.
1949
1950 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1951
1952 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1953 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1954
1955 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1956 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1957
1958 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1959 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1960 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1961 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1962
1963 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1964 This macro is only used in this file. */
1965
1966 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1967 (((TYPE) == 0 \
1968 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1969 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1970 || ! (AGGREGATE_TYPE_P (TYPE) \
1971 || (!TARGET_FPU_ANY \
1972 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1973 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1974 && ! (CUM).force_mem \
1975 && (TARGET_SH2E \
1976 ? ((MODE) == BLKmode \
1977 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1978 + int_size_in_bytes (TYPE)) \
1979 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1980 : ((ROUND_REG((CUM), (MODE)) \
1981 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1982 <= NPARM_REGS (MODE))) \
1983 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1984
1985 /* By accident we got stuck with passing SCmode on SH4 little endian
1986 in two registers that are nominally successive - which is different from
1987 two single SFmode values, where we take endianness translation into
1988 account. That does not work at all if an odd number of registers is
1989 already in use, so that got fixed, but library functions are still more
1990 likely to use complex numbers without mixing them with SFmode arguments
1991 (which in C would have to be structures), so for the sake of ABI
1992 compatibility the way SCmode values are passed when an even number of
1993 FP registers is in use remains different from a pair of SFmode values for
1994 now.
1995 I.e.:
1996 foo (double); a: fr5,fr4
1997 foo (float a, float b); a: fr5 b: fr4
1998 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1999 this should be the other way round...
2000 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2001 #define FUNCTION_ARG_SCmode_WART 1
2002
2003 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2004 register in SHcompact mode, it must be padded in the most
2005 significant end. This means that passing it by reference wouldn't
2006 pad properly on a big-endian machine. In this particular case, we
2007 pass this argument on the stack, in a way that the call trampoline
2008 will load its value into the appropriate register. */
2009 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2010 ((MODE) == BLKmode \
2011 && TARGET_SHCOMPACT \
2012 && ! TARGET_LITTLE_ENDIAN \
2013 && int_size_in_bytes (TYPE) > 4 \
2014 && int_size_in_bytes (TYPE) < 8)
2015
2016 /* Minimum alignment for an argument to be passed by callee-copy
2017 reference. We need such arguments to be aligned to 8 byte
2018 boundaries, because they'll be loaded using quad loads. */
2019 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2020
2021 /* The SH5 ABI requires floating-point arguments to be passed to
2022 functions without a prototype in both an FP register and a regular
2023 register or the stack. When passing the argument in both FP and
2024 general-purpose registers, list the FP register first. */
2025 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2026 (gen_rtx_PARALLEL \
2027 ((MODE), \
2028 gen_rtvec (2, \
2029 gen_rtx_EXPR_LIST \
2030 (VOIDmode, \
2031 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2032 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2033 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2034 : NULL_RTX), \
2035 const0_rtx), \
2036 gen_rtx_EXPR_LIST \
2037 (VOIDmode, \
2038 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2039 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2040 + (CUM).arg_count[(int) SH_ARG_INT]) \
2041 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2042 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2043 const0_rtx))))
2044
2045 /* The SH5 ABI requires regular registers or stack slots to be
2046 reserved for floating-point arguments. Registers are taken care of
2047 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2048 Unfortunately, there's no way to just reserve a stack slot, so
2049 we'll end up needlessly storing a copy of the argument in the
2050 stack. For incoming arguments, however, the PARALLEL will be
2051 optimized to the register-only form, and the value in the stack
2052 slot won't be used at all. */
2053 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2054 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2055 ? gen_rtx_REG ((MODE), (REG)) \
2056 : gen_rtx_PARALLEL ((MODE), \
2057 gen_rtvec (2, \
2058 gen_rtx_EXPR_LIST \
2059 (VOIDmode, NULL_RTX, \
2060 const0_rtx), \
2061 gen_rtx_EXPR_LIST \
2062 (VOIDmode, gen_rtx_REG ((MODE), \
2063 (REG)), \
2064 const0_rtx))))
2065
2066 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2067 (TARGET_SH5 \
2068 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2069 || (MODE) == DCmode) \
2070 && ((CUM).arg_count[(int) SH_ARG_INT] \
2071 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2072 : GET_MODE_SIZE (MODE)) \
2073 + 7) / 8) > NPARM_REGS (SImode))
2074
2075 /* Perform any needed actions needed for a function that is receiving a
2076 variable number of arguments. */
2077
2078 /* Call the function profiler with a given profile label.
2079 We use two .aligns, so as to make sure that both the .long is aligned
2080 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2081 from the trapa instruction. */
2082
2083 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2084 { \
2085 if (TARGET_SHMEDIA) \
2086 { \
2087 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2088 fprintf((STREAM), "\ttrapa\tr0\n"); \
2089 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2090 } \
2091 else \
2092 { \
2093 fprintf((STREAM), "\t.align\t2\n"); \
2094 fprintf((STREAM), "\ttrapa\t#33\n"); \
2095 fprintf((STREAM), "\t.align\t2\n"); \
2096 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2097 } \
2098 }
2099
2100 /* Define this macro if the code for function profiling should come
2101 before the function prologue. Normally, the profiling code comes
2102 after. */
2103
2104 #define PROFILE_BEFORE_PROLOGUE
2105
2106 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2107 the stack pointer does not matter. The value is tested only in
2108 functions that have frame pointers.
2109 No definition is equivalent to always zero. */
2110
2111 #define EXIT_IGNORE_STACK 1
2112
2113 /*
2114 On the SH, the trampoline looks like
2115 2 0002 D202 mov.l l2,r2
2116 1 0000 D301 mov.l l1,r3
2117 3 0004 422B jmp @r2
2118 4 0006 0009 nop
2119 5 0008 00000000 l1: .long area
2120 6 000c 00000000 l2: .long function */
2121
2122 /* Length in units of the trampoline for entering a nested function. */
2123 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2124
2125 /* Alignment required for a trampoline in bits . */
2126 #define TRAMPOLINE_ALIGNMENT \
2127 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2128 : TARGET_SHMEDIA ? 256 : 64)
2129
2130 /* Emit RTL insns to initialize the variable parts of a trampoline.
2131 FNADDR is an RTX for the address of the function's pure code.
2132 CXT is an RTX for the static chain value for the function. */
2133
2134 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2135 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2136
2137 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2138
2139 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2140 { \
2141 if (TARGET_SHMEDIA) \
2142 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2143 gen_reg_rtx (Pmode), 0, \
2144 OPTAB_LIB_WIDEN); \
2145 } while (0)
2146
2147 /* A C expression whose value is RTL representing the value of the return
2148 address for the frame COUNT steps up from the current frame.
2149 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2150 can ignore COUNT. */
2151
2152 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2153 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2154
2155 /* A C expression whose value is RTL representing the location of the
2156 incoming return address at the beginning of any function, before the
2157 prologue. This RTL is either a REG, indicating that the return
2158 value is saved in REG, or a MEM representing a location in
2159 the stack. */
2160 #define INCOMING_RETURN_ADDR_RTX \
2161 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2162 \f
2163 /* Addressing modes, and classification of registers for them. */
2164 #define HAVE_POST_INCREMENT TARGET_SH1
2165 #define HAVE_PRE_DECREMENT TARGET_SH1
2166
2167 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2168 ? 0 : TARGET_SH1)
2169 #define USE_LOAD_PRE_DECREMENT(mode) 0
2170 #define USE_STORE_POST_INCREMENT(mode) 0
2171 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2172 ? 0 : TARGET_SH1)
2173
2174 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2175 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2176 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2177
2178 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2179 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2180 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2181
2182 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
2183
2184 /* Macros to check register numbers against specific register classes. */
2185
2186 /* These assume that REGNO is a hard or pseudo reg number.
2187 They give nonzero only if REGNO is a hard reg of the suitable class
2188 or a pseudo reg currently allocated to a suitable hard reg.
2189 Since they use reg_renumber, they are safe only once reg_renumber
2190 has been allocated, which happens in local-alloc.c. */
2191
2192 #define REGNO_OK_FOR_BASE_P(REGNO) \
2193 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2194 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2195 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2196 (TARGET_SHMEDIA \
2197 ? (GENERAL_REGISTER_P (REGNO) \
2198 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2199 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2200
2201 /* Maximum number of registers that can appear in a valid memory
2202 address. */
2203
2204 #define MAX_REGS_PER_ADDRESS 2
2205
2206 /* Recognize any constant value that is a valid address. */
2207
2208 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2209
2210 /* Nonzero if the constant value X is a legitimate general operand. */
2211 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2212
2213 #define LEGITIMATE_CONSTANT_P(X) \
2214 (TARGET_SHMEDIA \
2215 ? ((GET_MODE (X) != DFmode \
2216 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2217 || (X) == CONST0_RTX (GET_MODE (X)) \
2218 || ! TARGET_SHMEDIA_FPU \
2219 || TARGET_SHMEDIA64) \
2220 : (GET_CODE (X) != CONST_DOUBLE \
2221 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2222 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2223
2224 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2225 and check its validity for a certain class.
2226 We have two alternate definitions for each of them.
2227 The usual definition accepts all pseudo regs; the other rejects
2228 them unless they have been allocated suitable hard regs.
2229 The symbol REG_OK_STRICT causes the latter definition to be used. */
2230
2231 #ifndef REG_OK_STRICT
2232
2233 /* Nonzero if X is a hard reg that can be used as a base reg
2234 or if it is a pseudo reg. */
2235 #define REG_OK_FOR_BASE_P(X) \
2236 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2237
2238 /* Nonzero if X is a hard reg that can be used as an index
2239 or if it is a pseudo reg. */
2240 #define REG_OK_FOR_INDEX_P(X) \
2241 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2242 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2243
2244 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2245 or if X is a pseudo reg. */
2246 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2247 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2248 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2249
2250 #else
2251
2252 /* Nonzero if X is a hard reg that can be used as a base reg. */
2253 #define REG_OK_FOR_BASE_P(X) \
2254 REGNO_OK_FOR_BASE_P (REGNO (X))
2255
2256 /* Nonzero if X is a hard reg that can be used as an index. */
2257 #define REG_OK_FOR_INDEX_P(X) \
2258 REGNO_OK_FOR_INDEX_P (REGNO (X))
2259
2260 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2261 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2262 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2263
2264 #endif
2265
2266 /* Macros for extra constraints. */
2267
2268 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2269 ((GET_CODE ((OP)) == LABEL_REF) \
2270 || (GET_CODE ((OP)) == CONST \
2271 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2272 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2273 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2274
2275 #define IS_LITERAL_OR_SYMBOLIC_S16_P(OP) \
2276 (GET_CODE ((OP)) == SIGN_EXTEND \
2277 && (GET_MODE ((OP)) == DImode \
2278 || GET_MODE ((OP)) == SImode) \
2279 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2280 && GET_MODE (XEXP ((OP), 0)) == HImode \
2281 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2282 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2283 && (MOVI_SHORI_BASE_OPERAND_P \
2284 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2285 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2286
2287 #define IS_LITERAL_OR_SYMBOLIC_U16_P(OP) \
2288 (GET_CODE ((OP)) == ZERO_EXTEND \
2289 && (GET_MODE ((OP)) == DImode \
2290 || GET_MODE ((OP)) == SImode) \
2291 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2292 && GET_MODE (XEXP ((OP), 0)) == HImode \
2293 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2294 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2295 && (MOVI_SHORI_BASE_OPERAND_P \
2296 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2297 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2298
2299 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2300 (CONSTANT_P (OP) \
2301 && GET_CODE (OP) != CONST_INT \
2302 && GET_CODE (OP) != CONST_DOUBLE \
2303 && (!flag_pic \
2304 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2305 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2306 && GET_CODE (OP) != LABEL_REF)))
2307
2308 /* Check whether OP is a datalabel unspec. */
2309 #define DATALABEL_REF_NO_CONST_P(OP) \
2310 (GET_CODE (OP) == UNSPEC \
2311 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2312 && XVECLEN ((OP), 0) == 1 \
2313 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2314
2315 #define GOT_ENTRY_P(OP) \
2316 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2317 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2318
2319 #define GOTPLT_ENTRY_P(OP) \
2320 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2321 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2322
2323 #define UNSPEC_GOTOFF_P(OP) \
2324 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2325
2326 #define GOTOFF_P(OP) \
2327 (GET_CODE (OP) == CONST \
2328 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2329 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2330 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2331 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2332
2333 #define PIC_ADDR_P(OP) \
2334 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2335 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2336
2337 #define PIC_OFFSET_P(OP) \
2338 (PIC_ADDR_P (OP) \
2339 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2340 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2341
2342 #define PIC_DIRECT_ADDR_P(OP) \
2343 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2344
2345 #define NON_PIC_REFERENCE_P(OP) \
2346 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2347 || (GET_CODE (OP) == CONST \
2348 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2349 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2350 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2351 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2352 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2353 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2354 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2355 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2356
2357 #define PIC_REFERENCE_P(OP) \
2358 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2359 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2360
2361 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2362 (flag_pic \
2363 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2364 || PIC_OFFSET_P (OP)) \
2365 : NON_PIC_REFERENCE_P (OP))
2366 \f
2367 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2368 that is a valid memory address for an instruction.
2369 The MODE argument is the machine mode for the MEM expression
2370 that wants to use this address. */
2371
2372 #define MODE_DISP_OK_4(X,MODE) \
2373 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2374 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2375
2376 #define MODE_DISP_OK_8(X,MODE) \
2377 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2378 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2379
2380 #undef MODE_DISP_OK_4
2381 #define MODE_DISP_OK_4(X,MODE) \
2382 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2383 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2384 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2385 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2386
2387 #undef MODE_DISP_OK_8
2388 #define MODE_DISP_OK_8(X,MODE) \
2389 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2390 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2391 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2392 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2393
2394 #define BASE_REGISTER_RTX_P(X) \
2395 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2396 || (GET_CODE (X) == SUBREG \
2397 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2398 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2399 && GET_CODE (SUBREG_REG (X)) == REG \
2400 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2401
2402 /* Since this must be r0, which is a single register class, we must check
2403 SUBREGs more carefully, to be sure that we don't accept one that extends
2404 outside the class. */
2405 #define INDEX_REGISTER_RTX_P(X) \
2406 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2407 || (GET_CODE (X) == SUBREG \
2408 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2409 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2410 && GET_CODE (SUBREG_REG (X)) == REG \
2411 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2412
2413 /* Jump to LABEL if X is a valid address RTX. This must also take
2414 REG_OK_STRICT into account when deciding about valid registers, but it uses
2415 the above macros so we are in luck.
2416
2417 Allow REG
2418 REG+disp
2419 REG+r0
2420 REG++
2421 --REG */
2422
2423 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2424 into the FRx registers. We implement this by setting the maximum offset
2425 to zero when the value is SFmode. This also restricts loading of SFmode
2426 values into the integer registers, but that can't be helped. */
2427
2428 /* The SH allows a displacement in a QI or HI amode, but only when the
2429 other operand is R0. GCC doesn't handle this very well, so we forgo
2430 all of that.
2431
2432 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2433 DI can be any number 0..60. */
2434
2435 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2436 do { \
2437 if (GET_CODE (OP) == CONST_INT) \
2438 { \
2439 if (TARGET_SHMEDIA) \
2440 { \
2441 int MODE_SIZE; \
2442 /* Check if this the address of an unaligned load / store. */\
2443 if ((MODE) == VOIDmode) \
2444 { \
2445 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2446 goto LABEL; \
2447 break; \
2448 } \
2449 MODE_SIZE = GET_MODE_SIZE (MODE); \
2450 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2451 && INTVAL (OP) >= -512 * MODE_SIZE \
2452 && INTVAL (OP) < 512 * MODE_SIZE) \
2453 goto LABEL; \
2454 else \
2455 break; \
2456 } \
2457 if (TARGET_SH2A) \
2458 { \
2459 if (GET_MODE_SIZE (MODE) == 1 \
2460 && (unsigned) INTVAL (OP) < 4096) \
2461 goto LABEL; \
2462 } \
2463 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2464 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2465 } \
2466 } while(0)
2467
2468 #define ALLOW_INDEXED_ADDRESS \
2469 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2470
2471 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2472 { \
2473 if (BASE_REGISTER_RTX_P (X)) \
2474 goto LABEL; \
2475 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2476 && ! TARGET_SHMEDIA \
2477 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2478 goto LABEL; \
2479 else if (GET_CODE (X) == PLUS \
2480 && ((MODE) != PSImode || reload_completed)) \
2481 { \
2482 rtx xop0 = XEXP ((X), 0); \
2483 rtx xop1 = XEXP ((X), 1); \
2484 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2485 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2486 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2487 || ((xop0 == stack_pointer_rtx \
2488 || xop0 == hard_frame_pointer_rtx) \
2489 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2490 || ((xop1 == stack_pointer_rtx \
2491 || xop1 == hard_frame_pointer_rtx) \
2492 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2493 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2494 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2495 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2496 && TARGET_FMOVD && MODE == DFmode))) \
2497 { \
2498 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2499 goto LABEL; \
2500 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2501 goto LABEL; \
2502 } \
2503 } \
2504 }
2505 \f
2506 /* Try machine-dependent ways of modifying an illegitimate address
2507 to be legitimate. If we find one, return the new, valid address.
2508 This macro is used in only one place: `memory_address' in explow.c.
2509
2510 OLDX is the address as it was before break_out_memory_refs was called.
2511 In some cases it is useful to look at this to decide what needs to be done.
2512
2513 MODE and WIN are passed so that this macro can use
2514 GO_IF_LEGITIMATE_ADDRESS.
2515
2516 It is always safe for this macro to do nothing. It exists to recognize
2517 opportunities to optimize the output.
2518
2519 For the SH, if X is almost suitable for indexing, but the offset is
2520 out of range, convert it into a normal form so that cse has a chance
2521 of reducing the number of address registers used. */
2522
2523 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2524 { \
2525 if (flag_pic) \
2526 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2527 if (GET_CODE (X) == PLUS \
2528 && (GET_MODE_SIZE (MODE) == 4 \
2529 || GET_MODE_SIZE (MODE) == 8) \
2530 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2531 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2532 && ! TARGET_SHMEDIA \
2533 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2534 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2535 { \
2536 rtx index_rtx = XEXP ((X), 1); \
2537 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2538 rtx sum; \
2539 \
2540 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2541 /* On rare occasions, we might get an unaligned pointer \
2542 that is indexed in a way to give an aligned address. \
2543 Therefore, keep the lower two bits in offset_base. */ \
2544 /* Instead of offset_base 128..131 use 124..127, so that \
2545 simple add suffices. */ \
2546 if (offset > 127) \
2547 { \
2548 offset_base = ((offset + 4) & ~60) - 4; \
2549 } \
2550 else \
2551 offset_base = offset & ~60; \
2552 /* Sometimes the normal form does not suit DImode. We \
2553 could avoid that by using smaller ranges, but that \
2554 would give less optimized code when SImode is \
2555 prevalent. */ \
2556 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2557 { \
2558 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2559 GEN_INT (offset_base), NULL_RTX, 0, \
2560 OPTAB_LIB_WIDEN); \
2561 \
2562 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2563 goto WIN; \
2564 } \
2565 } \
2566 }
2567
2568 /* A C compound statement that attempts to replace X, which is an address
2569 that needs reloading, with a valid memory address for an operand of
2570 mode MODE. WIN is a C statement label elsewhere in the code.
2571
2572 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2573 of the address. That will allow inheritance of the address reloads. */
2574
2575 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2576 { \
2577 if (GET_CODE (X) == PLUS \
2578 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2579 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2580 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2581 && ! TARGET_SHMEDIA \
2582 && ! (TARGET_SH4 && (MODE) == DFmode) \
2583 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2584 && (ALLOW_INDEXED_ADDRESS \
2585 || XEXP ((X), 0) == stack_pointer_rtx \
2586 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2587 { \
2588 rtx index_rtx = XEXP (X, 1); \
2589 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2590 rtx sum; \
2591 \
2592 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2593 { \
2594 push_reload (X, NULL_RTX, &X, NULL, \
2595 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2596 (TYPE)); \
2597 goto WIN; \
2598 } \
2599 if (TARGET_SH2E && MODE == SFmode) \
2600 { \
2601 X = copy_rtx (X); \
2602 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2603 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2604 (TYPE)); \
2605 goto WIN; \
2606 } \
2607 /* Instead of offset_base 128..131 use 124..127, so that \
2608 simple add suffices. */ \
2609 if (offset > 127) \
2610 { \
2611 offset_base = ((offset + 4) & ~60) - 4; \
2612 } \
2613 else \
2614 offset_base = offset & ~60; \
2615 /* Sometimes the normal form does not suit DImode. We \
2616 could avoid that by using smaller ranges, but that \
2617 would give less optimized code when SImode is \
2618 prevalent. */ \
2619 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2620 { \
2621 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2622 GEN_INT (offset_base)); \
2623 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2624 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2625 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2626 (TYPE)); \
2627 goto WIN; \
2628 } \
2629 } \
2630 /* We must re-recognize what we created before. */ \
2631 else if (GET_CODE (X) == PLUS \
2632 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2633 && GET_CODE (XEXP (X, 0)) == PLUS \
2634 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2635 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2636 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2637 && ! TARGET_SHMEDIA \
2638 && ! (TARGET_SH2E && MODE == SFmode)) \
2639 { \
2640 /* Because this address is so complex, we know it must have \
2641 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2642 it is already unshared, and needs no further unsharing. */ \
2643 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2644 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2645 goto WIN; \
2646 } \
2647 }
2648
2649 /* Go to LABEL if ADDR (a legitimate address expression)
2650 has an effect that depends on the machine mode it is used for.
2651
2652 ??? Strictly speaking, we should also include all indexed addressing,
2653 because the index scale factor is the length of the operand.
2654 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2655 high if we did that. So we rely on reload to fix things up.
2656
2657 Auto-increment addressing is now treated in recog.c. */
2658
2659 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2660 \f
2661 /* Specify the machine mode that this machine uses
2662 for the index in the tablejump instruction. */
2663 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2664
2665 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2666 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2667 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2668 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2669 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2670 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2671 : SImode)
2672
2673 /* Define as C expression which evaluates to nonzero if the tablejump
2674 instruction expects the table to contain offsets from the address of the
2675 table.
2676 Do not define this if the table should contain absolute addresses. */
2677 #define CASE_VECTOR_PC_RELATIVE 1
2678
2679 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2680 #define FLOAT_TYPE_SIZE 32
2681
2682 /* Since the SH2e has only `float' support, it is desirable to make all
2683 floating point types equivalent to `float'. */
2684 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2685
2686 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
2687 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2688 #else
2689 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2690 #endif
2691
2692 /* 'char' is signed by default. */
2693 #define DEFAULT_SIGNED_CHAR 1
2694
2695 /* The type of size_t unsigned int. */
2696 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2697
2698 #undef PTRDIFF_TYPE
2699 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2700
2701 #define WCHAR_TYPE "short unsigned int"
2702 #define WCHAR_TYPE_SIZE 16
2703
2704 #define SH_ELF_WCHAR_TYPE "long int"
2705
2706 /* Max number of bytes we can move from memory to memory
2707 in one reasonably fast instruction. */
2708 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2709
2710 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2711 MOVE_MAX is not a compile-time constant. */
2712 #define MAX_MOVE_MAX 8
2713
2714 /* Max number of bytes we want move_by_pieces to be able to copy
2715 efficiently. */
2716 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2717
2718 /* Define if operations between registers always perform the operation
2719 on the full register even if a narrower mode is specified. */
2720 #define WORD_REGISTER_OPERATIONS
2721
2722 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2723 will either zero-extend or sign-extend. The value of this macro should
2724 be the code that says which one of the two operations is implicitly
2725 done, UNKNOWN if none. */
2726 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2727 /* FP registers can load SImode values, but don't implicitly sign-extend
2728 them to DImode. */
2729 #define LOAD_EXTEND_OP(MODE) \
2730 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2731 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2732
2733 /* Define if loading short immediate values into registers sign extends. */
2734 #define SHORT_IMMEDIATES_SIGN_EXTEND
2735
2736 /* Nonzero if access to memory by bytes is no faster than for words. */
2737 #define SLOW_BYTE_ACCESS 1
2738
2739 /* Immediate shift counts are truncated by the output routines (or was it
2740 the assembler?). Shift counts in a register are truncated by SH. Note
2741 that the native compiler puts too large (> 32) immediate shift counts
2742 into a register and shifts by the register, letting the SH decide what
2743 to do instead of doing that itself. */
2744 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2745 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2746 expects - the sign bit is significant - so it appears that we need to
2747 leave this zero for correct SH3 code. */
2748 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2749
2750 /* All integers have the same format so truncation is easy. */
2751 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2752 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2753 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2754
2755 /* Define this if addresses of constant functions
2756 shouldn't be put through pseudo regs where they can be cse'd.
2757 Desirable on machines where ordinary constants are expensive
2758 but a CALL with constant address is cheap. */
2759 /*#define NO_FUNCTION_CSE 1*/
2760
2761 /* The machine modes of pointers and functions. */
2762 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2763 #define FUNCTION_MODE Pmode
2764
2765 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2766 are actually function calls with some special constraints on arguments
2767 and register usage.
2768
2769 These macros tell reorg that the references to arguments and
2770 register clobbers for insns of type sfunc do not appear to happen
2771 until after the millicode call. This allows reorg to put insns
2772 which set the argument registers into the delay slot of the millicode
2773 call -- thus they act more like traditional CALL_INSNs.
2774
2775 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2776 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2777 in particular. */
2778
2779 #define INSN_SETS_ARE_DELAYED(X) \
2780 ((GET_CODE (X) == INSN \
2781 && GET_CODE (PATTERN (X)) != SEQUENCE \
2782 && GET_CODE (PATTERN (X)) != USE \
2783 && GET_CODE (PATTERN (X)) != CLOBBER \
2784 && get_attr_is_sfunc (X)))
2785
2786 #define INSN_REFERENCES_ARE_DELAYED(X) \
2787 ((GET_CODE (X) == INSN \
2788 && GET_CODE (PATTERN (X)) != SEQUENCE \
2789 && GET_CODE (PATTERN (X)) != USE \
2790 && GET_CODE (PATTERN (X)) != CLOBBER \
2791 && get_attr_is_sfunc (X)))
2792
2793 \f
2794 /* Position Independent Code. */
2795
2796 /* We can't directly access anything that contains a symbol,
2797 nor can we indirect via the constant pool. */
2798 #define LEGITIMATE_PIC_OPERAND_P(X) \
2799 ((! nonpic_symbol_mentioned_p (X) \
2800 && (GET_CODE (X) != SYMBOL_REF \
2801 || ! CONSTANT_POOL_ADDRESS_P (X) \
2802 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2803 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2804
2805 #define SYMBOLIC_CONST_P(X) \
2806 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2807 && nonpic_symbol_mentioned_p (X))
2808 \f
2809 /* Compute extra cost of moving data between one register class
2810 and another. */
2811
2812 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2813 uses this information. Hence, the general register <-> floating point
2814 register information here is not used for SFmode. */
2815
2816 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2817 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2818 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2819
2820 #define REGCLASS_HAS_FP_REG(CLASS) \
2821 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2822 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2823
2824 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2825 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2826
2827 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2828 would be so that people with slow memory systems could generate
2829 different code that does fewer memory accesses. */
2830
2831 /* A C expression for the cost of a branch instruction. A value of 1
2832 is the default; other values are interpreted relative to that.
2833 The SH1 does not have delay slots, hence we get a pipeline stall
2834 at every branch. The SH4 is superscalar, so the single delay slot
2835 is not sufficient to keep both pipelines filled. */
2836 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2837 \f
2838 /* Assembler output control. */
2839
2840 /* A C string constant describing how to begin a comment in the target
2841 assembler language. The compiler assumes that the comment will end at
2842 the end of the line. */
2843 #define ASM_COMMENT_START "!"
2844
2845 #define ASM_APP_ON ""
2846 #define ASM_APP_OFF ""
2847 #define FILE_ASM_OP "\t.file\n"
2848 #define SET_ASM_OP "\t.set\t"
2849
2850 /* How to change between sections. */
2851
2852 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2853 #define DATA_SECTION_ASM_OP "\t.data"
2854
2855 #if defined CRT_BEGIN || defined CRT_END
2856 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2857 # undef TEXT_SECTION_ASM_OP
2858 # if __SHMEDIA__ == 1 && __SH5__ == 32
2859 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2860 # else
2861 # define TEXT_SECTION_ASM_OP "\t.text"
2862 # endif
2863 #endif
2864
2865
2866 /* If defined, a C expression whose value is a string containing the
2867 assembler operation to identify the following data as
2868 uninitialized global data. If not defined, and neither
2869 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2870 uninitialized global data will be output in the data section if
2871 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2872 used. */
2873 #ifndef BSS_SECTION_ASM_OP
2874 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2875 #endif
2876
2877 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2878 separate, explicit argument. If you define this macro, it is used
2879 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2880 handling the required alignment of the variable. The alignment is
2881 specified as the number of bits.
2882
2883 Try to use function `asm_output_aligned_bss' defined in file
2884 `varasm.c' when defining this macro. */
2885 #ifndef ASM_OUTPUT_ALIGNED_BSS
2886 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2887 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2888 #endif
2889
2890 /* Define this so that jump tables go in same section as the current function,
2891 which could be text or it could be a user defined section. */
2892 #define JUMP_TABLES_IN_TEXT_SECTION 1
2893
2894 #undef DO_GLOBAL_CTORS_BODY
2895 #define DO_GLOBAL_CTORS_BODY \
2896 { \
2897 typedef void (*pfunc) (void); \
2898 extern pfunc __ctors[]; \
2899 extern pfunc __ctors_end[]; \
2900 pfunc *p; \
2901 for (p = __ctors_end; p > __ctors; ) \
2902 { \
2903 (*--p)(); \
2904 } \
2905 }
2906
2907 #undef DO_GLOBAL_DTORS_BODY
2908 #define DO_GLOBAL_DTORS_BODY \
2909 { \
2910 typedef void (*pfunc) (void); \
2911 extern pfunc __dtors[]; \
2912 extern pfunc __dtors_end[]; \
2913 pfunc *p; \
2914 for (p = __dtors; p < __dtors_end; p++) \
2915 { \
2916 (*p)(); \
2917 } \
2918 }
2919
2920 #define ASM_OUTPUT_REG_PUSH(file, v) \
2921 { \
2922 if (TARGET_SHMEDIA) \
2923 { \
2924 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2925 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2926 } \
2927 else \
2928 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2929 }
2930
2931 #define ASM_OUTPUT_REG_POP(file, v) \
2932 { \
2933 if (TARGET_SHMEDIA) \
2934 { \
2935 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2936 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2937 } \
2938 else \
2939 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2940 }
2941
2942 /* DBX register number for a given compiler register number. */
2943 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2944 to match gdb. */
2945 /* svr4.h undefines this macro, yet we really want to use the same numbers
2946 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2947 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2948 register exists, so we should return -1 for invalid register numbers. */
2949 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2950
2951 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2952 used to use the encodings 245..260, but that doesn't make sense:
2953 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2954 the FP registers stay the same when switching between compact and media
2955 mode. Hence, we also need to use the same dwarf frame columns.
2956 Likewise, we need to support unwind information for SHmedia registers
2957 even in compact code. */
2958 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2959 (IN_RANGE ((REGNO), \
2960 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2961 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2962 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2963 : ((int) (REGNO) >= FIRST_FP_REG \
2964 && ((int) (REGNO) \
2965 <= (FIRST_FP_REG + \
2966 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2967 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2968 + (TARGET_SH5 ? 77 : 25)) \
2969 : XD_REGISTER_P (REGNO) \
2970 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2971 : TARGET_REGISTER_P (REGNO) \
2972 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2973 : (REGNO) == PR_REG \
2974 ? (TARGET_SH5 ? 18 : 17) \
2975 : (REGNO) == PR_MEDIA_REG \
2976 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2977 : (REGNO) == GBR_REG \
2978 ? (TARGET_SH5 ? 238 : 18) \
2979 : (REGNO) == MACH_REG \
2980 ? (TARGET_SH5 ? 239 : 20) \
2981 : (REGNO) == MACL_REG \
2982 ? (TARGET_SH5 ? 240 : 21) \
2983 : (REGNO) == T_REG \
2984 ? (TARGET_SH5 ? 242 : 22) \
2985 : (REGNO) == FPUL_REG \
2986 ? (TARGET_SH5 ? 244 : 23) \
2987 : (REGNO) == FPSCR_REG \
2988 ? (TARGET_SH5 ? 243 : 24) \
2989 : (unsigned) -1)
2990
2991 /* This is how to output a reference to a symbol_ref. On SH5,
2992 references to non-code symbols must be preceded by `datalabel'. */
2993 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2994 do \
2995 { \
2996 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2997 fputs ("datalabel ", (FILE)); \
2998 assemble_name ((FILE), XSTR ((SYM), 0)); \
2999 } \
3000 while (0)
3001
3002 /* This is how to output an assembler line
3003 that says to advance the location counter
3004 to a multiple of 2**LOG bytes. */
3005
3006 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3007 if ((LOG) != 0) \
3008 fprintf ((FILE), "\t.align %d\n", (LOG))
3009
3010 /* Globalizing directive for a label. */
3011 #define GLOBAL_ASM_OP "\t.global\t"
3012
3013 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3014
3015 /* Output a relative address table. */
3016
3017 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3018 switch (GET_MODE (BODY)) \
3019 { \
3020 case SImode: \
3021 if (TARGET_SH5) \
3022 { \
3023 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3024 (VALUE), (REL)); \
3025 break; \
3026 } \
3027 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3028 break; \
3029 case HImode: \
3030 if (TARGET_SH5) \
3031 { \
3032 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3033 (VALUE), (REL)); \
3034 break; \
3035 } \
3036 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3037 break; \
3038 case QImode: \
3039 if (TARGET_SH5) \
3040 { \
3041 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3042 (VALUE), (REL)); \
3043 break; \
3044 } \
3045 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3046 break; \
3047 default: \
3048 break; \
3049 }
3050
3051 /* Output an absolute table element. */
3052
3053 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3054 if (! optimize || TARGET_BIGTABLE) \
3055 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3056 else \
3057 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3058
3059 \f
3060 /* A C statement to be executed just prior to the output of
3061 assembler code for INSN, to modify the extracted operands so
3062 they will be output differently.
3063
3064 Here the argument OPVEC is the vector containing the operands
3065 extracted from INSN, and NOPERANDS is the number of elements of
3066 the vector which contain meaningful data for this insn.
3067 The contents of this vector are what will be used to convert the insn
3068 template into assembler code, so you can change the assembler output
3069 by changing the contents of the vector. */
3070
3071 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3072 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3073
3074 /* Print operand X (an rtx) in assembler syntax to file FILE.
3075 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3076 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3077
3078 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3079
3080 /* Print a memory address as an operand to reference that memory location. */
3081
3082 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3083
3084 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3085 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3086 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3087
3088 /* Recognize machine-specific patterns that may appear within
3089 constants. Used for PIC-specific UNSPECs. */
3090 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3091 do \
3092 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3093 { \
3094 switch (XINT ((X), 1)) \
3095 { \
3096 case UNSPEC_DATALABEL: \
3097 fputs ("datalabel ", (STREAM)); \
3098 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3099 break; \
3100 case UNSPEC_PIC: \
3101 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3102 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3103 break; \
3104 case UNSPEC_GOT: \
3105 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3106 fputs ("@GOT", (STREAM)); \
3107 break; \
3108 case UNSPEC_GOTOFF: \
3109 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3110 fputs ("@GOTOFF", (STREAM)); \
3111 break; \
3112 case UNSPEC_PLT: \
3113 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3114 fputs ("@PLT", (STREAM)); \
3115 break; \
3116 case UNSPEC_GOTPLT: \
3117 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3118 fputs ("@GOTPLT", (STREAM)); \
3119 break; \
3120 case UNSPEC_DTPOFF: \
3121 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3122 fputs ("@DTPOFF", (STREAM)); \
3123 break; \
3124 case UNSPEC_GOTTPOFF: \
3125 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3126 fputs ("@GOTTPOFF", (STREAM)); \
3127 break; \
3128 case UNSPEC_TPOFF: \
3129 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3130 fputs ("@TPOFF", (STREAM)); \
3131 break; \
3132 case UNSPEC_CALLER: \
3133 { \
3134 char name[32]; \
3135 /* LPCS stands for Label for PIC Call Site. */ \
3136 ASM_GENERATE_INTERNAL_LABEL \
3137 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3138 assemble_name ((STREAM), name); \
3139 } \
3140 break; \
3141 default: \
3142 goto FAIL; \
3143 } \
3144 break; \
3145 } \
3146 else \
3147 goto FAIL; \
3148 while (0)
3149
3150 \f
3151 extern struct rtx_def *sh_compare_op0;
3152 extern struct rtx_def *sh_compare_op1;
3153
3154 /* Which processor to schedule for. The elements of the enumeration must
3155 match exactly the cpu attribute in the sh.md file. */
3156
3157 enum processor_type {
3158 PROCESSOR_SH1,
3159 PROCESSOR_SH2,
3160 PROCESSOR_SH2E,
3161 PROCESSOR_SH2A,
3162 PROCESSOR_SH3,
3163 PROCESSOR_SH3E,
3164 PROCESSOR_SH4,
3165 PROCESSOR_SH4A,
3166 PROCESSOR_SH5
3167 };
3168
3169 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3170 extern enum processor_type sh_cpu;
3171
3172 extern int optimize; /* needed for gen_casesi. */
3173
3174 enum mdep_reorg_phase_e
3175 {
3176 SH_BEFORE_MDEP_REORG,
3177 SH_INSERT_USES_LABELS,
3178 SH_SHORTEN_BRANCHES0,
3179 SH_FIXUP_PCLOAD,
3180 SH_SHORTEN_BRANCHES1,
3181 SH_AFTER_MDEP_REORG
3182 };
3183
3184 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3185
3186 /* Handle Renesas compiler's pragmas. */
3187 #define REGISTER_TARGET_PRAGMAS() do { \
3188 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3189 c_register_pragma (0, "trapa", sh_pr_trapa); \
3190 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3191 } while (0)
3192
3193 extern tree sh_deferred_function_attributes;
3194 extern tree *sh_deferred_function_attributes_tail;
3195
3196 /* Set when processing a function with interrupt attribute. */
3197
3198 extern int current_function_interrupt;
3199
3200 \f
3201 /* Instructions with unfilled delay slots take up an
3202 extra two bytes for the nop in the delay slot.
3203 sh-dsp parallel processing insns are four bytes long. */
3204
3205 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3206 (LENGTH) += sh_insn_length_adjustment (X);
3207 \f
3208 /* Define this macro if it is advisable to hold scalars in registers
3209 in a wider mode than that declared by the program. In such cases,
3210 the value is constrained to be within the bounds of the declared
3211 type, but kept valid in the wider mode. The signedness of the
3212 extension may differ from that of the type.
3213
3214 Leaving the unsignedp unchanged gives better code than always setting it
3215 to 0. This is despite the fact that we have only signed char and short
3216 load instructions. */
3217 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3218 if (GET_MODE_CLASS (MODE) == MODE_INT \
3219 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3220 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3221 (MODE) = (TARGET_SH1 ? SImode \
3222 : TARGET_SHMEDIA32 ? SImode : DImode);
3223
3224 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3225
3226 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3227
3228 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3229 and popping arguments. However, we do have push/pop instructions, and
3230 rather limited offsets (4 bits) in load/store instructions, so it isn't
3231 clear if this would give better code. If implemented, should check for
3232 compatibility problems. */
3233
3234 #define SH_DYNAMIC_SHIFT_COST \
3235 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3236
3237
3238 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3239
3240 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3241
3242 #define ACTUAL_NORMAL_MODE(ENTITY) \
3243 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3244
3245 #define NORMAL_MODE(ENTITY) \
3246 (sh_cfun_interrupt_handler_p () \
3247 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3248 : ACTUAL_NORMAL_MODE (ENTITY))
3249
3250 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3251
3252 #define MODE_EXIT(ENTITY) \
3253 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3254
3255 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3256 && (REGNO) == FPSCR_REG)
3257
3258 #define MODE_NEEDED(ENTITY, INSN) \
3259 (recog_memoized (INSN) >= 0 \
3260 ? get_attr_fp_mode (INSN) \
3261 : FP_MODE_NONE)
3262
3263 #define MODE_AFTER(MODE, INSN) \
3264 (TARGET_HITACHI \
3265 && recog_memoized (INSN) >= 0 \
3266 && get_attr_fp_set (INSN) != FP_SET_NONE \
3267 ? (int) get_attr_fp_set (INSN) \
3268 : (MODE))
3269
3270 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3271 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3272
3273 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3274 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3275
3276 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3277 sh_can_redirect_branch ((INSN), (SEQ))
3278
3279 #define DWARF_FRAME_RETURN_COLUMN \
3280 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3281
3282 #define EH_RETURN_DATA_REGNO(N) \
3283 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3284
3285 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3286 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3287
3288 /* We have to distinguish between code and data, so that we apply
3289 datalabel where and only where appropriate. Use sdataN for data. */
3290 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3291 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3292 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3293 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3294
3295 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3296 indirect are handled automatically. */
3297 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3298 do { \
3299 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3300 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3301 { \
3302 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3303 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3304 if (0) goto DONE; \
3305 } \
3306 } while (0)
3307
3308 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3309 /* SH constant pool breaks the devices in crtstuff.c to control section
3310 in where code resides. We have to write it as asm code. */
3311 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3312 asm (SECTION_OP "\n\
3313 mov.l 1f,r1\n\
3314 mova 2f,r0\n\
3315 braf r1\n\
3316 lds r0,pr\n\
3317 0: .p2align 2\n\
3318 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3319 2:\n" TEXT_SECTION_ASM_OP);
3320 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3321
3322 /* FIXME: middle-end support for highpart optimizations is missing. */
3323 #define high_life_started reload_in_progress
3324
3325 #endif /* ! GCC_SH_H */