1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 ;; 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
6 ;; Improved by Jim Wilson (wilson@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
118 ;; These are used with unspec.
119 (UNSPEC_COMPACT_ARGS 0)
132 (UNSPEC_INIT_TRAMP 13)
145 (UNSPEC_DIV_INV_M0 30)
146 (UNSPEC_DIV_INV_M1 31)
147 (UNSPEC_DIV_INV_M2 32)
148 (UNSPEC_DIV_INV_M3 33)
149 (UNSPEC_DIV_INV20 34)
150 (UNSPEC_DIV_INV_TABLE 37)
158 ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT).
159 ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent.
160 (UNSPEC_EXTRACT_S16 43)
161 (UNSPEC_EXTRACT_U16 44)
163 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
166 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
167 (UNSPEC_PCREL_SYMOFF 46)
169 ;; These are used with unspec_volatile.
175 (UNSPECV_WINDOW_END 10)
176 (UNSPECV_CONST_END 11)
177 (UNSPECV_EH_RETURN 12)
180 ;; -------------------------------------------------------------------------
182 ;; -------------------------------------------------------------------------
187 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
188 (const (symbol_ref "sh_cpu_attr")))
190 (define_attr "endian" "big,little"
191 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
192 (const_string "little") (const_string "big"))))
194 ;; Indicate if the default fpu mode is single precision.
195 (define_attr "fpu_single" "yes,no"
196 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
197 (const_string "yes") (const_string "no"))))
199 (define_attr "fmovd" "yes,no"
200 (const (if_then_else (symbol_ref "TARGET_FMOVD")
201 (const_string "yes") (const_string "no"))))
203 (define_attr "pipe_model" "sh1,sh4,sh5media"
205 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
206 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
207 (const_string "sh1"))))
209 ;; cbranch conditional branch instructions
210 ;; jump unconditional jumps
211 ;; arith ordinary arithmetic
212 ;; arith3 a compound insn that behaves similarly to a sequence of
213 ;; three insns of type arith
214 ;; arith3b like above, but might end with a redirected branch
216 ;; load_si Likewise, SImode variant for general register.
217 ;; fload Likewise, but load to fp register.
219 ;; fstore floating point register to memory
220 ;; move general purpose register to register
221 ;; movi8 8-bit immediate to general purpose register
222 ;; mt_group other sh4 mt instructions
223 ;; fmove register to register, floating point
224 ;; smpy word precision integer multiply
225 ;; dmpy longword or doublelongword precision integer multiply
227 ;; pload load of pr reg, which can't be put into delay slot of rts
228 ;; prset copy register to pr reg, ditto
229 ;; pstore store of pr reg, which can't be put into delay slot of jsr
230 ;; prget copy pr to register, ditto
231 ;; pcload pc relative load of constant value
232 ;; pcfload Likewise, but load to fp register.
233 ;; pcload_si Likewise, SImode variant for general register.
234 ;; rte return from exception
235 ;; sfunc special function call with known used registers
236 ;; call function call
238 ;; fpscr_toggle toggle a bit in the fpscr
239 ;; fdiv floating point divide (or square root)
240 ;; gp_fpul move from general purpose register to fpul
241 ;; fpul_gp move from fpul to general purpose register
242 ;; mac_gp move from mac[lh] to general purpose register
243 ;; gp_mac move from general purpose register to mac[lh]
244 ;; mac_mem move from mac[lh] to memory
245 ;; mem_mac move from memory to mac[lh]
246 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
247 ;; ftrc_s fix_truncsfsi2_i4
248 ;; dfdiv double precision floating point divide (or square root)
249 ;; cwb ic_invalidate_line_i
250 ;; movua SH4a unaligned load
251 ;; fsrra square root reciprocal approximate
252 ;; fsca sine and cosine approximate
253 ;; tls_load load TLS related address
254 ;; arith_media SHmedia arithmetic, logical, and shift instructions
255 ;; cbranch_media SHmedia conditional branch instructions
256 ;; cmp_media SHmedia compare instructions
257 ;; dfdiv_media SHmedia double precision divide and square root
258 ;; dfmul_media SHmedia double precision multiply instruction
259 ;; dfparith_media SHmedia double precision floating point arithmetic
260 ;; dfpconv_media SHmedia double precision floating point conversions
261 ;; dmpy_media SHmedia longword multiply
262 ;; fcmp_media SHmedia floating point compare instructions
263 ;; fdiv_media SHmedia single precision divide and square root
264 ;; fload_media SHmedia floating point register load instructions
265 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
266 ;; fparith_media SHmedia single precision floating point arithmetic
267 ;; fpconv_media SHmedia single precision floating point conversions
268 ;; fstore_media SHmedia floating point register store instructions
269 ;; gettr_media SHmedia gettr instruction
270 ;; invalidate_line_media SHmedia invalidate_line sequence
271 ;; jump_media SHmedia unconditional branch instructions
272 ;; load_media SHmedia general register load instructions
273 ;; pt_media SHmedia pt instruction (expanded by assembler)
274 ;; ptabs_media SHmedia ptabs instruction
275 ;; store_media SHmedia general register store instructions
276 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
277 ;; mac_media SHmedia mac-style fixed point operations
278 ;; d2mpy_media SHmedia: two 32-bit integer multiplies
279 ;; atrans_media SHmedia approximate transcendental functions
280 ;; ustore_media SHmedia unaligned stores
281 ;; nil no-op move, will be deleted.
284 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
285 (const_string "other"))
287 ;; We define a new attribute namely "insn_class".We use
288 ;; this for the DFA based pipeline description.
290 ;; mt_group SH4 "mt" group instructions.
292 ;; ex_group SH4 "ex" group instructions.
294 ;; ls_group SH4 "ls" group instructions.
297 (define_attr "insn_class"
298 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
299 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
300 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
301 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
302 (eq_attr "type" "cbranch,jump") (const_string "br_group")
303 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
304 (const_string "fe_group")
305 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,gp_mac,mac_mem,mem_mac") (const_string "co_group")]
306 (const_string "none")))
307 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
308 ;; so these do not belong in an insn group, although they are modeled
309 ;; with their own define_insn_reservations.
311 ;; Indicate what precision must be selected in fpscr for this insn, if any.
313 (define_attr "fp_mode" "single,double,none" (const_string "none"))
315 ;; Indicate if the fpu mode is set by this instruction
316 ;; "unknown" must have the value as "none" in fp_mode, and means
317 ;; that the instruction/abi has left the processor in an unknown
319 ;; "none" means that nothing has changed and no mode is set.
320 ;; This attribute is only used for the Renesas ABI.
321 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
323 ; If a conditional branch destination is within -252..258 bytes away
324 ; from the instruction it can be 2 bytes long. Something in the
325 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
326 ; branches are initially assumed to be 16 bytes long.
327 ; In machine_dependent_reorg, we split all branches that are longer than
330 ;; The maximum range used for SImode constant pool entries is 1018. A final
331 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
332 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
333 ;; instruction around the pool table, 2 bytes of alignment before the table,
334 ;; and 30 bytes of alignment after the table. That gives a maximum total
335 ;; pool size of 1058 bytes.
336 ;; Worst case code/pool content size ratio is 1:2 (using asms).
337 ;; Thus, in the worst case, there is one instruction in front of a maximum
338 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
339 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
340 ;; If we have a forward branch, the initial table will be put after the
341 ;; unconditional branch.
343 ;; ??? We could do much better by keeping track of the actual pcloads within
344 ;; the branch range and in the pcload range in front of the branch range.
346 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
348 (define_attr "short_cbranch_p" "no,yes"
349 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
351 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
353 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
355 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
357 ] (const_string "no")))
359 (define_attr "med_branch_p" "no,yes"
360 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
363 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
365 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
368 ] (const_string "no")))
370 (define_attr "med_cbranch_p" "no,yes"
371 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
374 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
379 ] (const_string "no")))
381 (define_attr "braf_branch_p" "no,yes"
382 (cond [(match_test "! TARGET_SH2")
384 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
387 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
389 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
392 ] (const_string "no")))
394 (define_attr "braf_cbranch_p" "no,yes"
395 (cond [(match_test "! TARGET_SH2")
397 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
400 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
402 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
405 ] (const_string "no")))
407 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
408 ; For wider ranges, we need a combination of a code and a data part.
409 ; If we can get a scratch register for a long range jump, the code
410 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
411 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
412 ; long; otherwise, it must be 6 bytes long.
414 ; All other instructions are two bytes long by default.
416 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
417 ;; but getattrtab doesn't understand this.
418 (define_attr "length" ""
419 (cond [(eq_attr "type" "cbranch")
420 (cond [(eq_attr "short_cbranch_p" "yes")
422 (eq_attr "med_cbranch_p" "yes")
424 (eq_attr "braf_cbranch_p" "yes")
426 ;; ??? using pc is not computed transitively.
427 (ne (match_dup 0) (match_dup 0))
429 (match_test "flag_pic")
432 (eq_attr "type" "jump")
433 (cond [(eq_attr "med_branch_p" "yes")
435 (and (match_test "prev_nonnote_insn (insn)")
436 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))") (symbol_ref "INSN"))
437 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))") (symbol_ref "code_for_indirect_jump_scratch"))))
438 (cond [(eq_attr "braf_branch_p" "yes")
440 (not (match_test "flag_pic"))
442 (match_test "TARGET_SH2")
443 (const_int 10)] (const_int 18))
444 (eq_attr "braf_branch_p" "yes")
446 ;; ??? using pc is not computed transitively.
447 (ne (match_dup 0) (match_dup 0))
449 (match_test "flag_pic")
452 (eq_attr "type" "pt_media")
453 (if_then_else (match_test "TARGET_SHMEDIA64")
454 (const_int 20) (const_int 12))
455 (and (eq_attr "type" "jump_media")
456 (match_test "TARGET_SH5_CUT2_WORKAROUND"))
458 ] (if_then_else (match_test "TARGET_SHMEDIA")
462 ;; DFA descriptions for the pipelines
465 (include "shmedia.md")
468 (include "predicates.md")
469 (include "constraints.md")
471 ;; Definitions for filling delay slots
473 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
475 (define_attr "banked" "yes,no"
476 (cond [(match_test "sh_loads_bankedreg_p (insn)")
477 (const_string "yes")]
478 (const_string "no")))
480 ;; ??? This should be (nil) instead of (const_int 0)
481 (define_attr "hit_stack" "yes,no"
482 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
484 (const_string "yes")))
486 (define_attr "interrupt_function" "no,yes"
487 (const (symbol_ref "current_function_interrupt")))
489 (define_attr "in_delay_slot" "yes,no"
490 (cond [(eq_attr "type" "cbranch") (const_string "no")
491 (eq_attr "type" "pcload,pcload_si") (const_string "no")
492 (eq_attr "needs_delay_slot" "yes") (const_string "no")
493 (eq_attr "length" "2") (const_string "yes")
494 ] (const_string "no")))
496 (define_attr "cond_delay_slot" "yes,no"
497 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
498 ] (const_string "no")))
500 (define_attr "is_sfunc" ""
501 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
503 (define_attr "is_mac_media" ""
504 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
506 (define_attr "branch_zero" "yes,no"
507 (cond [(eq_attr "type" "!cbranch") (const_string "no")
508 (ne (symbol_ref "(next_active_insn (insn)\
509 == (prev_active_insn\
510 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
511 && get_attr_length (next_active_insn (insn)) == 2")
513 (const_string "yes")]
514 (const_string "no")))
516 ;; SH4 Double-precision computation with double-precision result -
517 ;; the two halves are ready at different times.
518 (define_attr "dfp_comp" "yes,no"
519 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
520 (const_string "no")))
522 ;; Insns for which the latency of a preceding fp insn is decreased by one.
523 (define_attr "late_fp_use" "yes,no" (const_string "no"))
524 ;; And feeding insns for which this relevant.
525 (define_attr "any_fp_comp" "yes,no"
526 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
527 (const_string "yes")]
528 (const_string "no")))
530 (define_attr "any_int_load" "yes,no"
531 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
532 (const_string "yes")]
533 (const_string "no")))
535 (define_attr "highpart" "user, ignore, extend, depend, must_split"
536 (const_string "user"))
539 (eq_attr "needs_delay_slot" "yes")
540 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
542 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
543 ;; and thus we can't put a pop instruction in its delay slot.
544 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
545 ;; instruction can go in the delay slot.
547 ;; Since a normal return (rts) implicitly uses the PR register,
548 ;; we can't allow PR register loads in an rts delay slot.
551 (eq_attr "type" "return")
552 [(and (eq_attr "in_delay_slot" "yes")
553 (ior (and (eq_attr "interrupt_function" "no")
554 (eq_attr "type" "!pload,prset"))
555 (and (eq_attr "interrupt_function" "yes")
557 (not (match_test "TARGET_SH3"))
558 (eq_attr "hit_stack" "no")
559 (eq_attr "banked" "no"))))) (nil) (nil)])
561 ;; Since a call implicitly uses the PR register, we can't allow
562 ;; a PR register store in a jsr delay slot.
565 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
566 [(and (eq_attr "in_delay_slot" "yes")
567 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
569 ;; Say that we have annulled true branches, since this gives smaller and
570 ;; faster code when branches are predicted as not taken.
572 ;; ??? The non-annulled condition should really be "in_delay_slot",
573 ;; but insns that can be filled in non-annulled get priority over insns
574 ;; that can only be filled in anulled.
577 (and (eq_attr "type" "cbranch")
578 (match_test "TARGET_SH2"))
579 ;; SH2e has a hardware bug that pretty much prohibits the use of
580 ;; annuled delay slots.
581 [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
582 (not (eq_attr "cpu" "sh2e"))) (nil)])
584 ;; -------------------------------------------------------------------------
585 ;; SImode signed integer comparisons
586 ;; -------------------------------------------------------------------------
588 ;; Various patterns to generate the TST #imm, R0 instruction.
589 ;; Although this adds some pressure on the R0 register, it can potentially
590 ;; result in faster code, even if the operand has to be moved to R0 first.
591 ;; This is because on SH4 TST #imm, R0 and MOV Rm, Rn are both MT group
592 ;; instructions and thus will be executed in parallel. On SH4A TST #imm, R0
593 ;; is an EX group instruction but still can be executed in parallel with the
594 ;; MT group MOV Rm, Rn instruction.
596 ;; Usual TST #imm, R0 patterns for SI, HI and QI
597 ;; This is usually used for bit patterns other than contiguous bits
600 (define_insn "tstsi_t"
602 (eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r")
603 (match_operand:SI 1 "logical_operand" "K08,r"))
607 [(set_attr "type" "mt_group")])
609 (define_insn "tsthi_t"
611 (eq:SI (subreg:SI (and:HI (match_operand:HI 0 "logical_operand" "%z")
612 (match_operand 1 "const_int_operand")) 0)
615 && CONST_OK_FOR_K08 (INTVAL (operands[1]))"
617 [(set_attr "type" "mt_group")])
619 (define_insn "tstqi_t"
621 (eq:SI (subreg:SI (and:QI (match_operand:QI 0 "logical_operand" "%z")
622 (match_operand 1 "const_int_operand")) 0)
625 && (CONST_OK_FOR_K08 (INTVAL (operands[1]))
626 || CONST_OK_FOR_I08 (INTVAL (operands[1])))"
628 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
631 [(set_attr "type" "mt_group")])
633 ;; Test low QI subreg against zero.
634 ;; This avoids unecessary zero extension before the test.
636 (define_insn "tstqi_t_zero"
638 (eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))]
641 [(set_attr "type" "mt_group")])
643 ;; Extract LSB, negate and store in T bit.
645 (define_insn "tstsi_t_and_not"
647 (and:SI (not:SI (match_operand:SI 0 "logical_operand" "z"))
651 [(set_attr "type" "mt_group")])
653 ;; Extract contiguous bits and compare them against zero.
655 (define_insn "tstsi_t_zero_extract_eq"
657 (eq:SI (zero_extract:SI (match_operand 0 "logical_operand" "z")
658 (match_operand:SI 1 "const_int_operand")
659 (match_operand:SI 2 "const_int_operand"))
662 && CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))"
664 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
667 [(set_attr "type" "mt_group")])
669 ;; This split is required when testing bits in a QI subreg.
673 (eq:SI (if_then_else:SI (zero_extract:SI
674 (match_operand 0 "logical_operand" "")
675 (match_operand 1 "const_int_operand")
676 (match_operand 2 "const_int_operand"))
677 (match_operand 3 "const_int_operand")
681 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
682 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
683 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 3))
687 if (GET_MODE (operands[0]) == QImode)
688 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
691 ;; Extract single bit, negate and store it in the T bit.
692 ;; Not used for SH4A.
694 (define_insn "tstsi_t_zero_extract_xor"
696 (zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z")
697 (match_operand:SI 3 "const_int_operand"))
698 (match_operand:SI 1 "const_int_operand")
699 (match_operand:SI 2 "const_int_operand")))]
701 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
702 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
704 [(set_attr "type" "mt_group")])
706 ;; Extract single bit, negate and store it in the T bit.
707 ;; Used for SH4A little endian.
709 (define_insn "tstsi_t_zero_extract_subreg_xor_little"
712 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
713 (match_operand:SI 3 "const_int_operand")) 0)
714 (match_operand:SI 1 "const_int_operand")
715 (match_operand:SI 2 "const_int_operand")))]
716 "TARGET_SH1 && TARGET_LITTLE_ENDIAN
717 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
718 == (INTVAL (operands[3]) & 255)
719 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
721 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
724 [(set_attr "type" "mt_group")])
726 ;; Extract single bit, negate and store it in the T bit.
727 ;; Used for SH4A big endian.
729 (define_insn "tstsi_t_zero_extract_subreg_xor_big"
732 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
733 (match_operand:SI 3 "const_int_operand")) 3)
734 (match_operand:SI 1 "const_int_operand")
735 (match_operand:SI 2 "const_int_operand")))]
736 "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN
737 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
738 == (INTVAL (operands[3]) & 255)
739 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
741 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
744 [(set_attr "type" "mt_group")])
746 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
747 ;; That would still allow reload to create cmpi instructions, but would
748 ;; perhaps allow forcing the constant into a register when that is better.
749 ;; Probably should use r0 for mem/imm compares, but force constant into a
750 ;; register for pseudo/imm compares.
752 (define_insn "cmpeqsi_t"
754 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
755 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
761 [(set_attr "type" "mt_group")])
763 (define_insn "cmpgtsi_t"
765 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
766 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
771 [(set_attr "type" "mt_group")])
773 (define_insn "cmpgesi_t"
775 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
776 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
781 [(set_attr "type" "mt_group")])
783 ;; -------------------------------------------------------------------------
784 ;; SImode compare and branch
785 ;; -------------------------------------------------------------------------
787 (define_expand "cbranchsi4"
789 (if_then_else (match_operator 0 "comparison_operator"
790 [(match_operand:SI 1 "arith_operand" "")
791 (match_operand:SI 2 "arith_operand" "")])
792 (label_ref (match_operand 3 "" ""))
794 (clobber (reg:SI T_REG))]
797 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
798 operands[2], operands[3]));
799 else if (TARGET_CBRANCHDI4)
800 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
802 sh_emit_compare_and_branch (operands, SImode);
805 ;; -------------------------------------------------------------------------
806 ;; SImode unsigned integer comparisons
807 ;; -------------------------------------------------------------------------
809 (define_insn_and_split "cmpgeusi_t"
811 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
812 (match_operand:SI 1 "arith_reg_or_0_operand" "rN")))]
815 "&& operands[1] == CONST0_RTX (SImode)"
819 emit_insn (gen_sett ());
822 [(set_attr "type" "mt_group")])
824 (define_insn "cmpgtusi_t"
826 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
827 (match_operand:SI 1 "arith_reg_operand" "r")))]
830 [(set_attr "type" "mt_group")])
833 ;; -------------------------------------------------------------------------
834 ;; DImode compare and branch
835 ;; -------------------------------------------------------------------------
838 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
839 ;; Therefore, we aim to have a set of three branches that go straight to the
840 ;; destination, i.e. only one of them is taken at any one time.
841 ;; This mechanism should also be slightly better for the sh4-200.
843 (define_expand "cbranchdi4"
845 (if_then_else (match_operator 0 "comparison_operator"
846 [(match_operand:DI 1 "arith_operand" "")
847 (match_operand:DI 2 "arith_operand" "")])
848 (label_ref (match_operand 3 "" ""))
850 (clobber (match_dup 4))
851 (clobber (reg:SI T_REG))]
852 "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA"
855 enum rtx_code comparison;
859 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
860 operands[2], operands[3]));
864 else if (!TARGET_CBRANCHDI4)
866 sh_emit_compare_and_branch (operands, DImode);
872 if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
875 comparison = prepare_cbranch_operands (operands, DImode,
876 LAST_AND_UNUSED_RTX_CODE);
877 if (comparison != GET_CODE (operands[0]))
879 = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
880 operands[4] = gen_rtx_SCRATCH (SImode);
884 (define_insn_and_split "cbranchdi4_i"
886 (if_then_else (match_operator 0 "comparison_operator"
887 [(match_operand:DI 1 "arith_operand" "r,r")
888 (match_operand:DI 2 "arith_operand" "rN,I08")])
889 (label_ref (match_operand 3 "" ""))
891 (clobber (match_scratch:SI 4 "=X,&r"))
892 (clobber (reg:SI T_REG))]
895 "&& reload_completed"
899 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
904 ;; -------------------------------------------------------------------------
905 ;; DImode signed integer comparisons
906 ;; -------------------------------------------------------------------------
910 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
911 (match_operand:DI 1 "arith_operand" "r"))
914 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
916 [(set_attr "length" "6")
917 (set_attr "type" "arith3b")])
919 (define_insn "cmpeqdi_t"
921 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
922 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
925 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
926 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
927 [(set_attr "length" "6")
928 (set_attr "type" "arith3b")])
932 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
933 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
934 ;; If we applied this split when not optimizing, it would only be
935 ;; applied during the machine-dependent reorg, when no new basic blocks
937 "TARGET_SH1 && reload_completed && optimize"
938 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
939 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
940 (label_ref (match_dup 6))
942 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
947 = gen_rtx_REG (SImode,
948 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
950 = (operands[1] == const0_rtx
952 : gen_rtx_REG (SImode,
953 true_regnum (operands[1])
954 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
955 operands[4] = gen_lowpart (SImode, operands[0]);
956 operands[5] = gen_lowpart (SImode, operands[1]);
957 operands[6] = gen_label_rtx ();
960 (define_insn "cmpgtdi_t"
962 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
963 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
966 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
967 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
968 [(set_attr "length" "8")
969 (set_attr "type" "arith3")])
971 (define_insn "cmpgedi_t"
973 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
974 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
977 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
979 [(set_attr "length" "8,2")
980 (set_attr "type" "arith3,mt_group")])
982 ;; -------------------------------------------------------------------------
983 ;; DImode unsigned integer comparisons
984 ;; -------------------------------------------------------------------------
986 (define_insn "cmpgeudi_t"
988 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
989 (match_operand:DI 1 "arith_reg_operand" "r")))]
991 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
992 [(set_attr "length" "8")
993 (set_attr "type" "arith3")])
995 (define_insn "cmpgtudi_t"
997 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
998 (match_operand:DI 1 "arith_reg_operand" "r")))]
1000 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
1001 [(set_attr "length" "8")
1002 (set_attr "type" "arith3")])
1004 (define_insn "cmpeqsi_media"
1005 [(set (match_operand:SI 0 "register_operand" "=r")
1006 (eq:SI (match_operand:SI 1 "logical_operand" "%r")
1007 (match_operand:SI 2 "cmp_operand" "Nr")))]
1010 [(set_attr "type" "cmp_media")])
1012 (define_insn "cmpeqdi_media"
1013 [(set (match_operand:SI 0 "register_operand" "=r")
1014 (eq:SI (match_operand:DI 1 "register_operand" "%r")
1015 (match_operand:DI 2 "cmp_operand" "Nr")))]
1018 [(set_attr "type" "cmp_media")])
1020 (define_insn "cmpgtsi_media"
1021 [(set (match_operand:SI 0 "register_operand" "=r")
1022 (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
1023 (match_operand:SI 2 "cmp_operand" "rN")))]
1025 "cmpgt %N1, %N2, %0"
1026 [(set_attr "type" "cmp_media")])
1028 (define_insn "cmpgtdi_media"
1029 [(set (match_operand:SI 0 "register_operand" "=r")
1030 (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1031 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1033 "cmpgt %N1, %N2, %0"
1034 [(set_attr "type" "cmp_media")])
1036 (define_insn "cmpgtusi_media"
1037 [(set (match_operand:SI 0 "register_operand" "=r")
1038 (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
1039 (match_operand:SI 2 "cmp_operand" "rN")))]
1041 "cmpgtu %N1, %N2, %0"
1042 [(set_attr "type" "cmp_media")])
1044 (define_insn "cmpgtudi_media"
1045 [(set (match_operand:SI 0 "register_operand" "=r")
1046 (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1047 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1049 "cmpgtu %N1, %N2, %0"
1050 [(set_attr "type" "cmp_media")])
1052 ; These two patterns are for combine.
1053 (define_insn "*cmpne0sisi_media"
1054 [(set (match_operand:SI 0 "register_operand" "=r")
1055 (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
1058 [(set_attr "type" "cmp_media")])
1060 ;; -------------------------------------------------------------------------
1061 ;; Conditional move instructions
1062 ;; -------------------------------------------------------------------------
1064 ;; The insn names may seem reversed, but note that cmveq performs the move
1065 ;; if op1 == 0, and cmvne does it if op1 != 0.
1067 (define_insn "movdicc_false"
1068 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1069 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
1071 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1072 (match_operand:DI 3 "arith_reg_operand" "0")))]
1075 [(set_attr "type" "arith_media")])
1077 (define_insn "movdicc_true"
1078 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1079 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
1081 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1082 (match_operand:DI 3 "arith_reg_operand" "0")))]
1085 [(set_attr "type" "arith_media")])
1088 [(set (match_operand:DI 0 "arith_reg_dest" "")
1089 (if_then_else:DI (match_operator 3 "equality_comparison_operator"
1090 [(match_operand:DI 1 "arith_reg_operand" "")
1092 (match_operand:DI 2 "arith_reg_dest" "")
1094 (set (match_dup 2) (match_dup 0))]
1095 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1097 (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
1100 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1101 VOIDmode, operands[1], CONST0_RTX (DImode));
1105 [(set (match_operand:DI 0 "general_movdst_operand" "")
1106 (match_operand:DI 1 "arith_reg_or_0_operand" ""))
1107 (set (match_operand:DI 2 "arith_reg_dest" "")
1108 (if_then_else:DI (match_operator 4 "equality_comparison_operator"
1109 [(match_operand:DI 3 "arith_reg_operand" "")
1113 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1115 (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
1118 (define_expand "movdicc"
1119 [(set (match_operand:DI 0 "register_operand" "")
1120 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1121 (match_operand:DI 2 "register_operand" "")
1122 (match_operand:DI 3 "register_operand" "")))]
1126 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1127 && GET_MODE (XEXP (operands[1], 0)) == DImode
1128 && XEXP (operands[1], 1) == const0_rtx)
1132 if (!can_create_pseudo_p ())
1135 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1136 GET_CODE (operands[1]),
1137 XEXP (operands[1], 0),
1138 XEXP (operands[1], 1));
1144 ;; Add SImode variants for cmveq / cmvne to compensate for not promoting
1145 ;; SImode to DImode.
1146 (define_insn "movsicc_false"
1147 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1148 (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
1150 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1151 (match_operand:SI 3 "arith_reg_operand" "0")))]
1154 [(set_attr "type" "arith_media")])
1156 (define_insn "movsicc_true"
1157 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1158 (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
1160 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1161 (match_operand:SI 3 "arith_reg_operand" "0")))]
1164 [(set_attr "type" "arith_media")])
1167 [(set (match_operand:SI 0 "arith_reg_dest" "")
1168 (if_then_else:SI (match_operator 3 "equality_comparison_operator"
1169 [(match_operand:SI 1 "arith_reg_operand" "")
1171 (match_operand:SI 2 "arith_reg_dest" "")
1173 (set (match_dup 2) (match_dup 0))]
1174 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1176 (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
1179 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1180 VOIDmode, operands[1], CONST0_RTX (SImode));
1184 [(set (match_operand:SI 0 "general_movdst_operand" "")
1185 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1186 (set (match_operand:SI 2 "arith_reg_dest" "")
1187 (if_then_else:SI (match_operator 4 "equality_comparison_operator"
1188 [(match_operand:SI 3 "arith_reg_operand" "")
1192 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
1193 && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
1195 (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
1198 replace_rtx (operands[4], operands[0], operands[1]);
1202 [(set (match_operand 0 "any_register_operand" "")
1203 (match_operand 1 "any_register_operand" ""))
1204 (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
1205 (set (match_operand 4 "" "") (match_operand 5 "" ""))]
1206 "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
1207 <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
1208 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
1209 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0])
1210 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2])
1211 && ! reg_overlap_mentioned_p (operands[0], operands[3])
1212 && ! reg_overlap_mentioned_p (operands[2], operands[0])
1213 && ! reg_overlap_mentioned_p (operands[0], operands[1])
1214 && (REGNO_REG_CLASS (REGNO (operands[0]))
1215 == REGNO_REG_CLASS (REGNO (operands[2])))
1216 && (REGNO_REG_CLASS (REGNO (operands[1]))
1217 == REGNO_REG_CLASS (REGNO (operands[0])))"
1218 [(set (match_dup 0) (match_dup 3))
1219 (set (match_dup 4) (match_dup 5))]
1222 rtx set1, set2, insn2;
1223 rtx replacements[4];
1225 /* We want to replace occurrences of operands[0] with operands[1] and
1226 operands[2] with operands[0] in operands[4]/operands[5].
1227 Doing just two replace_rtx calls naively would result in the second
1228 replacement undoing all that the first did if operands[1] and operands[2]
1229 are identical, so we must do this simultaneously. */
1230 replacements[0] = operands[0];
1231 replacements[1] = operands[1];
1232 replacements[2] = operands[2];
1233 replacements[3] = operands[0];
1234 if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
1235 || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
1236 || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
1239 operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
1240 replace_n_hard_rtx (operands[4], replacements, 2, 1);
1241 operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
1242 /* The operands array is aliased to recog_data.operand, which gets
1243 clobbered by extract_insn, so finish with it now. */
1244 set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
1245 set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
1246 /* ??? The last insn might be a jump insn, but the generic peephole2 code
1247 always uses emit_insn. */
1248 /* Check that we don't violate matching constraints or earlyclobbers. */
1249 extract_insn (emit_insn (set1));
1250 if (! constrain_operands (1))
1252 insn2 = emit (set2);
1253 if (GET_CODE (insn2) == BARRIER)
1255 extract_insn (insn2);
1256 if (! constrain_operands (1))
1260 tmp = replacements[0];
1261 replacements[0] = replacements[1];
1262 replacements[1] = tmp;
1263 tmp = replacements[2];
1264 replacements[2] = replacements[3];
1265 replacements[3] = tmp;
1266 replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
1267 replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
1268 replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
1274 ;; The register allocator is rather clumsy in handling multi-way conditional
1275 ;; moves, so allow the combiner to make them, and we split them up after
1277 (define_insn_and_split "*movsicc_umin"
1278 [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
1279 (umin:SI (if_then_else:SI
1280 (eq (match_operand:SI 1 "arith_reg_operand" "r")
1282 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1283 (match_operand:SI 3 "register_operand" "0"))
1284 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
1285 (clobber (match_scratch:SI 5 "=&r"))]
1286 "TARGET_SHMEDIA && !can_create_pseudo_p ()"
1288 "TARGET_SHMEDIA && reload_completed"
1292 emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
1294 emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
1295 emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
1300 (define_insn "*movsicc_t_false"
1301 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1302 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1303 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1304 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1305 "TARGET_PRETEND_CMOVE
1306 && (arith_reg_operand (operands[1], SImode)
1307 || (immediate_operand (operands[1], SImode)
1308 && satisfies_constraint_I08 (operands[1])))"
1309 "bt 0f\;mov %1,%0\\n0:"
1310 [(set_attr "type" "mt_group,arith") ;; poor approximation
1311 (set_attr "length" "4")])
1313 (define_insn "*movsicc_t_true"
1314 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1315 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1316 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1317 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1318 "TARGET_PRETEND_CMOVE
1319 && (arith_reg_operand (operands[1], SImode)
1320 || (immediate_operand (operands[1], SImode)
1321 && satisfies_constraint_I08 (operands[1])))"
1322 "bf 0f\;mov %1,%0\\n0:"
1323 [(set_attr "type" "mt_group,arith") ;; poor approximation
1324 (set_attr "length" "4")])
1326 (define_expand "movsicc"
1327 [(set (match_operand:SI 0 "arith_reg_dest" "")
1328 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1329 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1330 (match_operand:SI 3 "arith_reg_operand" "")))]
1331 "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
1334 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1335 && GET_MODE (XEXP (operands[1], 0)) == SImode
1337 || (REG_P (XEXP (operands[1], 0))
1338 && REGNO (XEXP (operands[1], 0)) == T_REG))
1339 && XEXP (operands[1], 1) == const0_rtx)
1342 else if (TARGET_PRETEND_CMOVE)
1344 enum rtx_code code = GET_CODE (operands[1]);
1345 enum rtx_code new_code = code;
1346 rtx op0 = XEXP (operands[1], 0);
1347 rtx op1 = XEXP (operands[1], 1);
1349 if (! currently_expanding_to_rtl)
1353 case LT: case LE: case LEU: case LTU:
1354 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1357 new_code = reverse_condition (code);
1359 case EQ: case GT: case GE: case GEU: case GTU:
1364 sh_emit_scc_to_t (new_code, op0, op1);
1365 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1366 gen_rtx_REG (SImode, T_REG), const0_rtx);
1370 if (!can_create_pseudo_p ())
1373 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1374 GET_CODE (operands[1]),
1375 XEXP (operands[1], 0),
1376 XEXP (operands[1], 1));
1382 (define_expand "movqicc"
1383 [(set (match_operand:QI 0 "register_operand" "")
1384 (if_then_else:QI (match_operand 1 "comparison_operator" "")
1385 (match_operand:QI 2 "register_operand" "")
1386 (match_operand:QI 3 "register_operand" "")))]
1390 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
1391 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
1392 operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
1393 emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
1397 ;; -------------------------------------------------------------------------
1398 ;; Addition instructions
1399 ;; -------------------------------------------------------------------------
1401 (define_expand "adddi3"
1402 [(set (match_operand:DI 0 "arith_reg_operand" "")
1403 (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
1404 (match_operand:DI 2 "arith_operand" "")))]
1410 if (!can_create_pseudo_p () && ! arith_reg_operand (operands[2], DImode))
1412 operands[2] = force_reg (DImode, operands[2]);
1413 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1418 (define_insn "*adddi3_media"
1419 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1420 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1421 (match_operand:DI 2 "arith_operand" "r,I10")))]
1426 [(set_attr "type" "arith_media")])
1428 (define_insn "*adddisi3_media"
1429 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
1430 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1431 (match_operand:DI 2 "arith_operand" "r,I10")))]
1436 [(set_attr "type" "arith_media")
1437 (set_attr "highpart" "ignore")])
1439 (define_insn "adddi3z_media"
1440 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1442 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1443 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1445 "addz.l %1, %N2, %0"
1446 [(set_attr "type" "arith_media")
1447 (set_attr "highpart" "ignore")])
1449 (define_insn "adddi3_compact"
1450 [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
1451 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
1452 (match_operand:DI 2 "arith_reg_operand" "r")))
1453 (clobber (reg:SI T_REG))]
1456 [(set_attr "length" "6")])
1459 [(set (match_operand:DI 0 "arith_reg_dest" "")
1460 (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
1461 (match_operand:DI 2 "arith_reg_operand" "")))
1462 (clobber (reg:SI T_REG))]
1463 "TARGET_SH1 && reload_completed"
1467 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
1468 high0 = gen_rtx_REG (SImode,
1469 true_regnum (operands[0])
1470 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1471 high2 = gen_rtx_REG (SImode,
1472 true_regnum (operands[2])
1473 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1474 emit_insn (gen_clrt ());
1475 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
1476 emit_insn (gen_addc1 (high0, high0, high2));
1481 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1482 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1483 (match_operand:SI 2 "arith_reg_operand" "r"))
1486 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1489 [(set_attr "type" "arith")])
1491 (define_insn "addc1"
1492 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1493 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1494 (match_operand:SI 2 "arith_reg_operand" "r"))
1496 (clobber (reg:SI T_REG))]
1499 [(set_attr "type" "arith")])
1501 (define_expand "addsi3"
1502 [(set (match_operand:SI 0 "arith_reg_operand" "")
1503 (plus:SI (match_operand:SI 1 "arith_operand" "")
1504 (match_operand:SI 2 "arith_operand" "")))]
1509 operands[1] = force_reg (SImode, operands[1]);
1512 (define_insn "addsi3_media"
1513 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1514 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
1515 (match_operand:SI 2 "arith_operand" "r,I10")))]
1520 [(set_attr "type" "arith_media")
1521 (set_attr "highpart" "ignore")])
1523 (define_insn "addsidi3_media"
1524 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1525 (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
1527 (match_operand:SI 2 "arith_operand"
1533 [(set_attr "type" "arith_media")
1534 (set_attr "highpart" "ignore")])
1536 (define_insn "*addsi3_compact"
1537 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1538 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
1539 (match_operand:SI 2 "arith_operand" "rI08")))]
1542 [(set_attr "type" "arith")])
1544 ;; -------------------------------------------------------------------------
1545 ;; Subtraction instructions
1546 ;; -------------------------------------------------------------------------
1548 (define_expand "subdi3"
1549 [(set (match_operand:DI 0 "arith_reg_operand" "")
1550 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
1551 (match_operand:DI 2 "arith_reg_operand" "")))]
1557 operands[1] = force_reg (DImode, operands[1]);
1558 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
1563 (define_insn "*subdi3_media"
1564 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1565 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
1566 (match_operand:DI 2 "arith_reg_operand" "r")))]
1569 [(set_attr "type" "arith_media")])
1571 (define_insn "subdisi3_media"
1572 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
1573 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
1574 (match_operand:DI 2 "arith_reg_operand" "r")))]
1577 [(set_attr "type" "arith_media")
1578 (set_attr "highpart" "ignore")])
1580 (define_insn "subdi3_compact"
1581 [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
1582 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
1583 (match_operand:DI 2 "arith_reg_operand" "r")))
1584 (clobber (reg:SI T_REG))]
1587 [(set_attr "length" "6")])
1590 [(set (match_operand:DI 0 "arith_reg_dest" "")
1591 (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
1592 (match_operand:DI 2 "arith_reg_operand" "")))
1593 (clobber (reg:SI T_REG))]
1594 "TARGET_SH1 && reload_completed"
1598 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
1599 high0 = gen_rtx_REG (SImode,
1600 true_regnum (operands[0])
1601 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1602 high2 = gen_rtx_REG (SImode,
1603 true_regnum (operands[2])
1604 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
1605 emit_insn (gen_clrt ());
1606 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
1607 emit_insn (gen_subc1 (high0, high0, high2));
1612 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1613 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1614 (match_operand:SI 2 "arith_reg_operand" "r"))
1617 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1622 [(set_attr "type" "arith")])
1624 (define_insn "subc1"
1625 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1626 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1627 (match_operand:SI 2 "arith_reg_operand" "r"))
1629 (clobber (reg:SI T_REG))]
1632 [(set_attr "type" "arith")])
1634 ;; life_analysis thinks rn is live before subc rn,rn, so make a special
1635 ;; pattern for this case. This helps multimedia applications that compute
1636 ;; the sum of absolute differences.
1637 (define_insn "mov_neg_si_t"
1638 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (neg:SI (reg:SI T_REG)))]
1641 [(set_attr "type" "arith")])
1643 (define_insn "*subsi3_internal"
1644 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1645 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1646 (match_operand:SI 2 "arith_reg_operand" "r")))]
1649 [(set_attr "type" "arith")])
1651 (define_insn_and_split "*subsi3_media"
1652 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1653 (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
1654 (match_operand:SI 2 "extend_reg_operand" "r")))]
1656 && (operands[1] != constm1_rtx
1657 || (GET_CODE (operands[2]) != TRUNCATE
1658 && GET_CODE (operands[2]) != SUBREG))"
1660 "operands[1] == constm1_rtx"
1661 [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
1663 [(set_attr "type" "arith_media")
1664 (set_attr "highpart" "ignore")])
1667 [(set (match_operand:SI 0 "arith_reg_dest" "")
1668 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
1669 "general_extend_operand"
1671 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
1672 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
1673 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
1677 [(set (match_operand:SI 0 "arith_reg_dest" "")
1678 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
1679 "general_extend_operand"
1681 "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
1682 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
1683 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
1685 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
1686 ;; will sometimes save one instruction. Otherwise we might get
1687 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
1690 (define_expand "subsi3"
1691 [(set (match_operand:SI 0 "arith_reg_operand" "")
1692 (minus:SI (match_operand:SI 1 "arith_operand" "")
1693 (match_operand:SI 2 "arith_reg_operand" "")))]
1697 if (TARGET_SH1 && CONST_INT_P (operands[1]))
1699 emit_insn (gen_negsi2 (operands[0], operands[2]));
1700 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
1705 if (!can_create_pseudo_p ()
1706 && ! arith_reg_or_0_operand (operands[1], SImode))
1708 if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
1709 operands[1] = force_reg (SImode, operands[1]);
1713 ;; -------------------------------------------------------------------------
1714 ;; Division instructions
1715 ;; -------------------------------------------------------------------------
1717 ;; We take advantage of the library routines which don't clobber as many
1718 ;; registers as a normal function call would.
1720 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
1721 ;; also has an effect on the register that holds the address of the sfunc.
1722 ;; To make this work, we have an extra dummy insn that shows the use
1723 ;; of this register for reorg.
1725 (define_insn "use_sfunc_addr"
1726 [(set (reg:SI PR_REG)
1727 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
1728 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
1730 [(set_attr "length" "0")])
1732 (define_insn "udivsi3_sh2a"
1733 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1734 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
1735 (match_operand:SI 2 "arith_reg_operand" "z")))]
1738 [(set_attr "type" "arith")
1739 (set_attr "in_delay_slot" "no")])
1741 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
1742 ;; hard register 0. If we used hard register 0, then the next instruction
1743 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
1744 ;; gets allocated to a stack slot that needs its address reloaded, then
1745 ;; there is nothing to prevent reload from using r0 to reload the address.
1746 ;; This reload would clobber the value in r0 we are trying to store.
1747 ;; If we let reload allocate r0, then this problem can never happen.
1749 (define_insn "udivsi3_i1"
1750 [(set (match_operand:SI 0 "register_operand" "=z")
1751 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1752 (clobber (reg:SI T_REG))
1753 (clobber (reg:SI PR_REG))
1754 (clobber (reg:SI R4_REG))
1755 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1756 "TARGET_SH1 && (! TARGET_SH4 || TARGET_DIVIDE_CALL_DIV1)"
1758 [(set_attr "type" "sfunc")
1759 (set_attr "needs_delay_slot" "yes")])
1761 ; Since shmedia-nofpu code could be linked against shcompact code, and
1762 ; the udivsi3 libcall has the same name, we must consider all registers
1763 ; clobbered that are in the union of the registers clobbered by the
1764 ; shmedia and the shcompact implementation. Note, if the shcompact
1765 ; implementation actually used shcompact code, we'd need to clobber
1766 ; also r23 and fr23.
1767 (define_insn "udivsi3_i1_media"
1768 [(set (match_operand:SI 0 "register_operand" "=z")
1769 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1770 (clobber (reg:SI T_MEDIA_REG))
1771 (clobber (reg:SI PR_MEDIA_REG))
1772 (clobber (reg:SI R20_REG))
1773 (clobber (reg:SI R21_REG))
1774 (clobber (reg:SI R22_REG))
1775 (clobber (reg:DI TR0_REG))
1776 (clobber (reg:DI TR1_REG))
1777 (clobber (reg:DI TR2_REG))
1778 (use (match_operand 1 "target_reg_operand" "b"))]
1779 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
1781 [(set_attr "type" "sfunc")
1782 (set_attr "needs_delay_slot" "yes")])
1784 (define_expand "udivsi3_i4_media"
1786 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
1788 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
1789 (set (match_dup 5) (float:DF (match_dup 3)))
1790 (set (match_dup 6) (float:DF (match_dup 4)))
1791 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
1792 (set (match_dup 8) (fix:DI (match_dup 7)))
1793 (set (match_operand:SI 0 "register_operand" "")
1794 (truncate:SI (match_dup 8)))]
1795 "TARGET_SHMEDIA_FPU"
1798 operands[3] = gen_reg_rtx (DImode);
1799 operands[4] = gen_reg_rtx (DImode);
1800 operands[5] = gen_reg_rtx (DFmode);
1801 operands[6] = gen_reg_rtx (DFmode);
1802 operands[7] = gen_reg_rtx (DFmode);
1803 operands[8] = gen_reg_rtx (DImode);
1806 (define_insn "udivsi3_i4"
1807 [(set (match_operand:SI 0 "register_operand" "=y")
1808 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1809 (clobber (reg:SI T_REG))
1810 (clobber (reg:SI PR_REG))
1811 (clobber (reg:DF DR0_REG))
1812 (clobber (reg:DF DR2_REG))
1813 (clobber (reg:DF DR4_REG))
1814 (clobber (reg:SI R0_REG))
1815 (clobber (reg:SI R1_REG))
1816 (clobber (reg:SI R4_REG))
1817 (clobber (reg:SI R5_REG))
1818 (use (reg:PSI FPSCR_REG))
1819 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1820 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1822 [(set_attr "type" "sfunc")
1823 (set_attr "fp_mode" "double")
1824 (set_attr "needs_delay_slot" "yes")])
1826 (define_insn "udivsi3_i4_single"
1827 [(set (match_operand:SI 0 "register_operand" "=y")
1828 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1829 (clobber (reg:SI T_REG))
1830 (clobber (reg:SI PR_REG))
1831 (clobber (reg:DF DR0_REG))
1832 (clobber (reg:DF DR2_REG))
1833 (clobber (reg:DF DR4_REG))
1834 (clobber (reg:SI R0_REG))
1835 (clobber (reg:SI R1_REG))
1836 (clobber (reg:SI R4_REG))
1837 (clobber (reg:SI R5_REG))
1838 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1839 "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
1841 [(set_attr "type" "sfunc")
1842 (set_attr "needs_delay_slot" "yes")])
1844 (define_insn "udivsi3_i4_int"
1845 [(set (match_operand:SI 0 "register_operand" "=z")
1846 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1847 (clobber (reg:SI T_REG))
1848 (clobber (reg:SI R1_REG))
1849 (clobber (reg:SI PR_REG))
1850 (clobber (reg:SI MACH_REG))
1851 (clobber (reg:SI MACL_REG))
1852 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1855 [(set_attr "type" "sfunc")
1856 (set_attr "needs_delay_slot" "yes")])
1859 (define_expand "udivsi3"
1860 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1861 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1862 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1863 (parallel [(set (match_operand:SI 0 "register_operand" "")
1864 (udiv:SI (reg:SI R4_REG)
1866 (clobber (reg:SI T_REG))
1867 (clobber (reg:SI PR_REG))
1868 (clobber (reg:SI R4_REG))
1869 (use (match_dup 3))])]
1875 operands[3] = gen_reg_rtx (Pmode);
1876 /* Emit the move of the address to a pseudo outside of the libcall. */
1877 if (TARGET_DIVIDE_CALL_TABLE)
1879 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
1880 that causes problems when the divide code is supposed to come from a
1881 separate library. Division by zero is undefined, so dividing 1 can be
1882 implemented by comparing with the divisor. */
1883 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
1885 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
1886 emit_insn (gen_cstoresi4 (operands[0], test,
1887 operands[1], operands[2]));
1890 else if (operands[2] == const0_rtx)
1892 emit_move_insn (operands[0], operands[2]);
1895 function_symbol (operands[3], \"__udivsi3_i4i\", SFUNC_GOT);
1896 last = gen_udivsi3_i4_int (operands[0], operands[3]);
1898 else if (TARGET_DIVIDE_CALL_FP)
1900 function_symbol (operands[3], \"__udivsi3_i4\", SFUNC_STATIC);
1901 if (TARGET_FPU_SINGLE)
1902 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1904 last = gen_udivsi3_i4 (operands[0], operands[3]);
1906 else if (TARGET_SHMEDIA_FPU)
1908 operands[1] = force_reg (SImode, operands[1]);
1909 operands[2] = force_reg (SImode, operands[2]);
1910 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
1913 else if (TARGET_SH2A)
1915 operands[1] = force_reg (SImode, operands[1]);
1916 operands[2] = force_reg (SImode, operands[2]);
1917 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
1920 else if (TARGET_SH5)
1922 function_symbol (operands[3],
1923 TARGET_FPU_ANY ? \"__udivsi3_i4\" : \"__udivsi3\",
1927 last = gen_udivsi3_i1_media (operands[0], operands[3]);
1928 else if (TARGET_FPU_ANY)
1929 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1931 last = gen_udivsi3_i1 (operands[0], operands[3]);
1935 function_symbol (operands[3], \"__udivsi3\", SFUNC_STATIC);
1936 last = gen_udivsi3_i1 (operands[0], operands[3]);
1938 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1939 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1944 (define_insn "divsi3_sh2a"
1945 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1946 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
1947 (match_operand:SI 2 "arith_reg_operand" "z")))]
1950 [(set_attr "type" "arith")
1951 (set_attr "in_delay_slot" "no")])
1953 (define_insn "divsi3_i1"
1954 [(set (match_operand:SI 0 "register_operand" "=z")
1955 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1956 (clobber (reg:SI T_REG))
1957 (clobber (reg:SI PR_REG))
1958 (clobber (reg:SI R1_REG))
1959 (clobber (reg:SI R2_REG))
1960 (clobber (reg:SI R3_REG))
1961 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1962 "TARGET_SH1 && (! TARGET_SH4 || TARGET_DIVIDE_CALL_DIV1)"
1964 [(set_attr "type" "sfunc")
1965 (set_attr "needs_delay_slot" "yes")])
1967 (define_insn "divsi3_i1_media"
1968 [(set (match_operand:SI 0 "register_operand" "=z")
1969 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1970 (clobber (reg:SI T_MEDIA_REG))
1971 (clobber (reg:SI PR_MEDIA_REG))
1972 (clobber (reg:SI R1_REG))
1973 (clobber (reg:SI R20_REG))
1974 (clobber (reg:SI R21_REG))
1975 (clobber (reg:SI TR0_REG))
1976 (use (match_operand 1 "target_reg_operand" "b"))]
1977 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
1979 [(set_attr "type" "sfunc")])
1981 (define_insn "divsi3_media_2"
1982 [(set (match_operand:SI 0 "register_operand" "=z")
1983 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1984 (clobber (reg:SI T_MEDIA_REG))
1985 (clobber (reg:SI PR_MEDIA_REG))
1986 (clobber (reg:SI R1_REG))
1987 (clobber (reg:SI R21_REG))
1988 (clobber (reg:SI TR0_REG))
1989 (use (reg:SI R20_REG))
1990 (use (match_operand 1 "target_reg_operand" "b"))]
1991 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
1993 [(set_attr "type" "sfunc")])
1995 ;; This pattern acts as a placeholder for -mdiv=inv:call to carry
1996 ;; hard reg clobbers and data dependencies that we need when we want
1997 ;; to rematerialize the division into a call.
1998 (define_insn_and_split "divsi_inv_call"
1999 [(set (match_operand:SI 0 "register_operand" "=r")
2000 (div:SI (match_operand:SI 1 "register_operand" "r")
2001 (match_operand:SI 2 "register_operand" "r")))
2002 (clobber (reg:SI R4_REG))
2003 (clobber (reg:SI R5_REG))
2004 (clobber (reg:SI T_MEDIA_REG))
2005 (clobber (reg:SI PR_MEDIA_REG))
2006 (clobber (reg:SI R1_REG))
2007 (clobber (reg:SI R21_REG))
2008 (clobber (reg:SI TR0_REG))
2009 (clobber (reg:SI R20_REG))
2010 (use (match_operand:SI 3 "register_operand" "r"))]
2013 "&& (high_life_started || reload_completed)"
2014 [(set (match_dup 0) (match_dup 3))]
2016 [(set_attr "highpart" "must_split")])
2018 ;; This is the combiner pattern for -mdiv=inv:call .
2019 (define_insn_and_split "*divsi_inv_call_combine"
2020 [(set (match_operand:SI 0 "register_operand" "=z")
2021 (div:SI (match_operand:SI 1 "register_operand" "r")
2022 (match_operand:SI 2 "register_operand" "r")))
2023 (clobber (reg:SI R4_REG))
2024 (clobber (reg:SI R5_REG))
2025 (clobber (reg:SI T_MEDIA_REG))
2026 (clobber (reg:SI PR_MEDIA_REG))
2027 (clobber (reg:SI R1_REG))
2028 (clobber (reg:SI R21_REG))
2029 (clobber (reg:SI TR0_REG))
2030 (clobber (reg:SI R20_REG))
2031 (use (unspec:SI [(match_dup 1)
2032 (match_operand:SI 3 "" "")
2033 (unspec:SI [(match_operand:SI 4 "" "")
2035 (match_operand:DI 5 "" "")]
2037 (match_operand:DI 6 "" "")
2040 UNSPEC_DIV_INV_M3))]
2043 "&& (high_life_started || reload_completed)"
2047 const char *name = sh_divsi3_libfunc;
2048 enum sh_function_kind kind = SFUNC_GOT;
2051 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2052 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2053 while (TARGET_DIVIDE_INV_CALL2)
2055 rtx x = operands[3];
2057 if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
2059 x = XVECEXP (x, 0, 0);
2060 name = \"__sdivsi3_2\";
2061 kind = SFUNC_STATIC;
2062 emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
2065 sym = function_symbol (NULL, name, kind);
2066 emit_insn (gen_divsi3_media_2 (operands[0], sym));
2069 [(set_attr "highpart" "must_split")])
2071 (define_expand "divsi3_i4_media"
2072 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
2073 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
2074 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
2075 (set (match_operand:SI 0 "register_operand" "=r")
2076 (fix:SI (match_dup 5)))]
2077 "TARGET_SHMEDIA_FPU"
2080 operands[3] = gen_reg_rtx (DFmode);
2081 operands[4] = gen_reg_rtx (DFmode);
2082 operands[5] = gen_reg_rtx (DFmode);
2085 (define_insn "divsi3_i4"
2086 [(set (match_operand:SI 0 "register_operand" "=y")
2087 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2088 (clobber (reg:SI PR_REG))
2089 (clobber (reg:DF DR0_REG))
2090 (clobber (reg:DF DR2_REG))
2091 (use (reg:PSI FPSCR_REG))
2092 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2093 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
2095 [(set_attr "type" "sfunc")
2096 (set_attr "fp_mode" "double")
2097 (set_attr "needs_delay_slot" "yes")])
2099 (define_insn "divsi3_i4_single"
2100 [(set (match_operand:SI 0 "register_operand" "=y")
2101 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2102 (clobber (reg:SI PR_REG))
2103 (clobber (reg:DF DR0_REG))
2104 (clobber (reg:DF DR2_REG))
2105 (clobber (reg:SI R2_REG))
2106 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2107 "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
2109 [(set_attr "type" "sfunc")
2110 (set_attr "needs_delay_slot" "yes")])
2112 (define_insn "divsi3_i4_int"
2113 [(set (match_operand:SI 0 "register_operand" "=z")
2114 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2115 (clobber (reg:SI T_REG))
2116 (clobber (reg:SI PR_REG))
2117 (clobber (reg:SI R1_REG))
2118 (clobber (reg:SI MACH_REG))
2119 (clobber (reg:SI MACL_REG))
2120 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2123 [(set_attr "type" "sfunc")
2124 (set_attr "needs_delay_slot" "yes")])
2126 (define_expand "divsi3"
2127 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
2128 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2129 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2130 (parallel [(set (match_operand:SI 0 "register_operand" "")
2131 (div:SI (reg:SI R4_REG)
2133 (clobber (reg:SI T_REG))
2134 (clobber (reg:SI PR_REG))
2135 (clobber (reg:SI R1_REG))
2136 (clobber (reg:SI R2_REG))
2137 (clobber (reg:SI R3_REG))
2138 (use (match_dup 3))])]
2144 operands[3] = gen_reg_rtx (Pmode);
2145 /* Emit the move of the address to a pseudo outside of the libcall. */
2146 if (TARGET_DIVIDE_CALL_TABLE)
2148 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2149 last = gen_divsi3_i4_int (operands[0], operands[3]);
2151 else if (TARGET_DIVIDE_CALL_FP)
2153 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2154 if (TARGET_FPU_SINGLE)
2155 last = gen_divsi3_i4_single (operands[0], operands[3]);
2157 last = gen_divsi3_i4 (operands[0], operands[3]);
2159 else if (TARGET_SH2A)
2161 operands[1] = force_reg (SImode, operands[1]);
2162 operands[2] = force_reg (SImode, operands[2]);
2163 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2166 else if (TARGET_DIVIDE_INV)
2168 rtx dividend = operands[1];
2169 rtx divisor = operands[2];
2171 rtx nsb_res = gen_reg_rtx (DImode);
2172 rtx norm64 = gen_reg_rtx (DImode);
2173 rtx tab_ix = gen_reg_rtx (DImode);
2174 rtx norm32 = gen_reg_rtx (SImode);
2175 rtx i92 = force_reg (DImode, GEN_INT (92));
2176 rtx scratch0a = gen_reg_rtx (DImode);
2177 rtx scratch0b = gen_reg_rtx (DImode);
2178 rtx inv0 = gen_reg_rtx (SImode);
2179 rtx scratch1a = gen_reg_rtx (DImode);
2180 rtx scratch1b = gen_reg_rtx (DImode);
2181 rtx shift = gen_reg_rtx (DImode);
2183 rtx inv1 = gen_reg_rtx (SImode);
2184 rtx scratch2a = gen_reg_rtx (DImode);
2185 rtx scratch2b = gen_reg_rtx (SImode);
2186 rtx inv2 = gen_reg_rtx (SImode);
2187 rtx scratch3a = gen_reg_rtx (DImode);
2188 rtx scratch3b = gen_reg_rtx (DImode);
2189 rtx scratch3c = gen_reg_rtx (DImode);
2190 rtx scratch3d = gen_reg_rtx (SImode);
2191 rtx scratch3e = gen_reg_rtx (DImode);
2192 rtx result = gen_reg_rtx (SImode);
2194 if (! arith_reg_or_0_operand (dividend, SImode))
2195 dividend = force_reg (SImode, dividend);
2196 if (! arith_reg_operand (divisor, SImode))
2197 divisor = force_reg (SImode, divisor);
2198 if (flag_pic && Pmode != DImode)
2200 tab_base = gen_rtx_SYMBOL_REF (Pmode, \"__div_table\");
2201 tab_base = gen_datalabel_ref (tab_base);
2202 tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
2206 tab_base = gen_rtx_SYMBOL_REF (DImode, \"__div_table\");
2207 tab_base = gen_datalabel_ref (tab_base);
2208 tab_base = force_reg (DImode, tab_base);
2210 if (TARGET_DIVIDE_INV20U)
2211 i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
2213 i2p27 = GEN_INT (0);
2214 if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
2215 i43 = force_reg (DImode, GEN_INT (43));
2218 emit_insn (gen_nsbdi (nsb_res,
2219 simplify_gen_subreg (DImode, divisor, SImode, 0)));
2220 emit_insn (gen_ashldi3_media (norm64,
2221 gen_rtx_SUBREG (DImode, divisor, 0),
2223 emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
2224 emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
2225 emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
2226 inv0, scratch0a, scratch0b,
2227 scratch1a, scratch1b));
2228 emit_insn (gen_subdi3 (shift, i92, nsb_res));
2229 emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
2231 emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
2233 scratch3a, scratch3b, scratch3c,
2234 scratch2a, scratch2b, scratch3d, scratch3e));
2235 if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
2236 emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
2237 else if (TARGET_DIVIDE_INV_FP)
2238 emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
2239 gen_reg_rtx (SImode), gen_reg_rtx (SImode),
2240 gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
2241 gen_reg_rtx (DFmode)));
2243 emit_move_insn (operands[0], result);
2246 else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
2248 operands[1] = force_reg (SImode, operands[1]);
2249 operands[2] = force_reg (SImode, operands[2]);
2250 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
2253 else if (TARGET_SH5)
2255 if (TARGET_DIVIDE_CALL2)
2257 rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, \"__div_table\");
2258 tab_base = gen_datalabel_ref (tab_base);
2259 emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
2261 if (TARGET_FPU_ANY && TARGET_SH1)
2262 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2263 else if (TARGET_DIVIDE_CALL2)
2264 function_symbol (operands[3], \"__sdivsi3_2\", SFUNC_STATIC);
2266 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2269 last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
2270 (operands[0], operands[3]));
2271 else if (TARGET_FPU_ANY)
2272 last = gen_divsi3_i4_single (operands[0], operands[3]);
2274 last = gen_divsi3_i1 (operands[0], operands[3]);
2278 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2279 last = gen_divsi3_i1 (operands[0], operands[3]);
2281 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2282 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2287 ;; operands: scratch, tab_base, tab_ix
2288 ;; These are unspecs because we could generate an indexed addressing mode
2289 ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
2290 ;; confuse reload. See PR27117.
2292 (define_insn "divsi_inv_qitable"
2293 [(set (match_operand:DI 0 "register_operand" "=r")
2294 (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
2295 (match_operand:DI 2 "register_operand" "r")]
2296 UNSPEC_DIV_INV_TABLE)))]
2300 [(set_attr "type" "load_media")
2301 (set_attr "highpart" "user")])
2303 ;; operands: scratch, tab_base, tab_ix
2304 (define_insn "divsi_inv_hitable"
2305 [(set (match_operand:DI 0 "register_operand" "=r")
2306 (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
2307 (match_operand:DI 2 "register_operand" "r")]
2308 UNSPEC_DIV_INV_TABLE)))]
2312 [(set_attr "type" "load_media")
2313 (set_attr "highpart" "user")])
2315 ;; operands: inv0, tab_base, tab_ix, norm32
2316 ;; scratch equiv in sdivsi3_2: r19, r21
2317 (define_expand "divsi_inv_m0"
2318 [(set (match_operand:SI 0 "register_operand" "=r")
2319 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2320 (match_operand:DI 2 "register_operand" "r")
2321 (match_operand:SI 3 "register_operand" "r")]
2323 (clobber (match_operand:DI 4 "register_operand" "=r"))
2324 (clobber (match_operand:DI 5 "register_operand" "=r"))]
2332 ldx.ub r20, r21, r19 // u0.8
2334 muls.l r25, r19, r19 // s2.38
2335 ldx.w r20, r21, r21 // s2.14
2336 shari r19, 24, r19 // truncate to s2.14
2337 sub r21, r19, r19 // some 11 bit inverse in s1.14
2340 rtx inv0 = operands[0];
2341 rtx tab_base = operands[1];
2342 rtx tab_ix = operands[2];
2343 rtx norm32 = operands[3];
2344 rtx scratch0 = operands[4];
2345 rtx scratch0_si = simplify_gen_subreg (SImode, scratch0, DImode, SIDI_OFF);
2346 rtx scratch1 = operands[5];
2348 emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
2349 emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
2350 emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
2351 emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
2352 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
2353 emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
2357 ;; operands: inv1, tab_base, tab_ix, norm32
2358 (define_insn_and_split "divsi_inv_m1"
2359 [(set (match_operand:SI 0 "register_operand" "=r")
2360 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2361 (match_operand:DI 2 "register_operand" "r")
2362 (match_operand:SI 3 "register_operand" "r")]
2364 (clobber (match_operand:SI 4 "register_operand" "=r"))
2365 (clobber (match_operand:DI 5 "register_operand" "=r"))
2366 (clobber (match_operand:DI 6 "register_operand" "=r"))
2367 (clobber (match_operand:DI 7 "register_operand" "=r"))
2368 (clobber (match_operand:DI 8 "register_operand" "=r"))]
2371 "&& !can_create_pseudo_p ()"
2376 muls.l r19, r19, r18 // u0.28
2377 muls.l r25, r18, r18 // s2.58
2378 shlli r19, 45, r0 // multiply by two and convert to s2.58
2380 shari r18, 28, r18 // some 18 bit inverse in s1.30
2383 rtx inv1 = operands[0];
2384 rtx tab_base = operands[1];
2385 rtx tab_ix = operands[2];
2386 rtx norm32 = operands[3];
2387 rtx inv0 = operands[4];
2388 rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
2389 rtx scratch0a = operands[5];
2390 rtx scratch0b = operands[6];
2391 rtx scratch0 = operands[7];
2392 rtx scratch1 = operands[8];
2393 rtx scratch1_si = simplify_gen_subreg (SImode, scratch1, DImode, SIDI_OFF);
2395 emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
2396 scratch0a, scratch0b));
2397 emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
2398 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
2399 emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
2400 emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
2401 emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
2405 ;; operands: inv2, norm32, inv1, i92
2406 (define_insn_and_split "divsi_inv_m2"
2407 [(set (match_operand:SI 0 "register_operand" "=r")
2408 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2409 (match_operand:SI 2 "register_operand" "r")
2410 (match_operand:DI 3 "register_operand" "r")]
2412 (clobber (match_operand:DI 4 "register_operand" "=r"))]
2415 "&& !can_create_pseudo_p ()"
2420 muls.l r18, r25, r0 // s2.60
2421 shari r0, 16, r0 // s-16.44
2423 muls.l r0, r18, r19 // s-16.74
2424 shari r19, 30, r19 // s-16.44
2426 rtx inv2 = operands[0];
2427 rtx norm32 = operands[1];
2428 rtx inv1 = operands[2];
2429 rtx i92 = operands[3];
2430 rtx scratch0 = operands[4];
2431 rtx scratch0_si = simplify_gen_subreg (SImode, scratch0, DImode, SIDI_OFF);
2433 emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
2434 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
2435 emit_insn (gen_subdi3 (scratch0, i92, scratch0));
2436 emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
2437 emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
2441 (define_insn_and_split "divsi_inv_m3"
2442 [(set (match_operand:SI 0 "register_operand" "=r")
2443 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
2444 (match_operand:SI 2 "register_operand" "r")
2445 (match_operand:SI 3 "register_operand" "r")
2446 (match_operand:DI 4 "register_operand" "r")
2447 (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
2448 (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
2450 (clobber (match_operand:DI 7 "register_operand" "=r"))
2451 (clobber (match_operand:DI 8 "register_operand" "=r"))
2452 (clobber (match_operand:DI 9 "register_operand" "=r"))
2453 (clobber (match_operand:DI 10 "register_operand" "=r"))
2454 (clobber (match_operand:SI 11 "register_operand" "=r"))
2455 (clobber (match_operand:SI 12 "register_operand" "=r"))
2456 (clobber (match_operand:DI 13 "register_operand" "=r"))]
2459 "&& !can_create_pseudo_p ()"
2464 r0: result r1: shift r4: dividend r18: inv1 r19: inv2
2465 r0: scratch0 r19: scratch1 r21: scratch2
2467 muls.l r18, r4, r25 // s32.30
2468 muls.l r19, r4, r19 // s15.30
2470 shari r19, 14, r19 // s18.-14
2476 rtx result = operands[0];
2477 rtx dividend = operands[1];
2478 rtx inv1 = operands[2];
2479 rtx inv2 = operands[3];
2480 rtx shift = operands[4];
2481 rtx scratch0 = operands[7];
2482 rtx scratch1 = operands[8];
2483 rtx scratch2 = operands[9];
2485 if (satisfies_constraint_N (dividend))
2487 emit_move_insn (result, dividend);
2491 emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
2492 emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
2493 emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
2494 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
2495 emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
2496 emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
2497 emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
2501 ;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
2502 ;; inv1: tab_base, tab_ix, norm32
2503 ;; inv2: norm32, inv1, i92
2504 (define_insn_and_split "divsi_inv_m1_3"
2505 [(set (match_operand:SI 0 "register_operand" "=r")
2506 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
2507 (unspec:SI [(match_operand:DI 2 "register_operand" "r")
2508 (match_operand:DI 3 "register_operand" "r")
2509 (match_operand:SI 4 "register_operand" "r")]
2511 (unspec:SI [(match_dup 4)
2512 (unspec:SI [(match_dup 2)
2514 (match_dup 4)] UNSPEC_DIV_INV_M1)
2515 (match_operand:SI 5 "" "")]
2517 (match_operand:DI 6 "register_operand" "r")
2518 (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
2519 (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
2521 (clobber (match_operand:DI 9 "register_operand" "=r"))
2522 (clobber (match_operand:DI 10 "register_operand" "=r"))
2523 (clobber (match_operand:DI 11 "register_operand" "=r"))
2524 (clobber (match_operand:DI 12 "register_operand" "=r"))
2525 (clobber (match_operand:SI 13 "register_operand" "=r"))
2526 (clobber (match_operand:SI 14 "register_operand" "=r"))
2527 (clobber (match_operand:DI 15 "register_operand" "=r"))]
2529 && (TARGET_DIVIDE_INV_MINLAT
2530 || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
2532 "&& !can_create_pseudo_p ()"
2536 rtx result = operands[0];
2537 rtx dividend = operands[1];
2538 rtx tab_base = operands[2];
2539 rtx tab_ix = operands[3];
2540 rtx norm32 = operands[4];
2541 /* rtx i92 = operands[5]; */
2542 rtx shift = operands[6];
2543 rtx i2p27 = operands[7];
2544 rtx i43 = operands[8];
2545 rtx scratch0 = operands[9];
2546 rtx scratch0_si = simplify_gen_subreg (SImode, scratch0, DImode, SIDI_OFF);
2547 rtx scratch1 = operands[10];
2548 rtx scratch1_si = simplify_gen_subreg (SImode, scratch1, DImode, SIDI_OFF);
2549 rtx scratch2 = operands[11];
2550 rtx scratch3 = operands[12];
2551 rtx scratch4 = operands[13];
2552 rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
2553 rtx scratch5 = operands[14];
2554 rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
2555 rtx scratch6 = operands[15];
2557 emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
2558 scratch0, scratch1));
2559 /* inv0 == scratch4 */
2560 if (! TARGET_DIVIDE_INV20U)
2562 emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
2564 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
2568 emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
2569 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
2571 emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
2572 emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
2573 emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
2574 /* inv1 == scratch4 */
2576 if (TARGET_DIVIDE_INV_MINLAT)
2578 emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
2579 emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
2580 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
2581 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
2582 emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
2583 emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
2584 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
2585 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
2586 emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
2587 emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
2588 emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
2592 rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
2593 /* Use separate scratch regs for nsb and sign to allow scheduling. */
2594 emit_insn (gen_nsbdi (scratch6,
2595 simplify_gen_subreg (DImode, dividend, SImode, 0)));
2596 emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
2597 emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
2598 emit_insn (gen_divsi_inv20 (scratch2,
2599 norm32, scratch4, dividend,
2600 scratch6, scratch3, i43,
2601 /* scratch0 may be shared with i2p27. */
2602 scratch0, scratch1, scratch5,
2603 label, label, i2p27));
2605 emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
2606 emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
2610 (define_insn "divsi_inv20"
2611 [(set (match_operand:DI 0 "register_operand" "=&r")
2612 (unspec:DI [(match_operand:SI 1 "register_operand" "r")
2613 (match_operand:SI 2 "register_operand" "r")
2614 (match_operand:SI 3 "register_operand" "r")
2615 (match_operand:DI 4 "register_operand" "r")
2616 (match_operand:DI 5 "register_operand" "r")
2617 (match_operand:DI 6 "register_operand" "r")
2618 (match_operand:DI 12 "register_operand" "r")
2619 (match_operand 10 "target_operand" "b")
2620 (match_operand 11 "immediate_operand" "i")]
2622 (clobber (match_operand:DI 7 "register_operand" "=&r"))
2623 (clobber (match_operand:DI 8 "register_operand" "=&r"))
2624 (clobber (match_operand:SI 9 "register_operand" "=r"))]
2626 && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
2629 /* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
2630 %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
2631 %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
2632 %10 label (tr), %11 label (imm)
2634 muls.l inv1, norm32, scratch0 // s2.60
2635 muls.l inv1, dividend, result // s32.30
2636 xor i2p27, result_sign, round_scratch
2637 bge/u dividend_nsb, i43, tr.. (label)
2638 shari scratch0, 16, scratch0 // s-16.44
2639 muls.l sratch0_si, inv1, scratch0 // s-16.74
2640 sub result, round_scratch, result
2641 shari dividend, 14, scratch1 // s19.-14
2642 shari scratch0, 30, scratch0 // s-16.44
2643 muls.l scratch0, scratch1, round_scratch // s15.30
2645 sub result, round_scratch, result */
2647 int likely = TARGET_DIVIDE_INV20L;
2649 if (! likely) output_asm_insn (\"muls.l\t%2, %1 , %8\", operands);
2650 output_asm_insn (\"muls.l\t%2, %3, %0\;xor\t%12, %5, %7\", operands);
2651 output_asm_insn (likely
2652 ? \"bge/l\t%4, %6, %10\;muls.l\t%2, %1 , %8\"
2653 : \"bge/u\t%4, %6, %10\", operands);
2654 output_asm_insn (\"shari\t%8, 16, %8\;muls.l\t%8, %2, %8\", operands);
2655 if (! likely) output_asm_insn (\"sub\t%0, %7, %0\", operands);
2656 output_asm_insn (\"shari\t%3, 14, %9\;shari\t%8, 30, %8\", operands);
2658 ? \"muls.l\t%8, %9, %8\;sub\t%0, %8, %0\n%11:\tadd\t%0, %7, %0\"
2659 : \"muls.l\t%8, %9, %7\n%11:\tsub\t%0, %7, %0\");
2662 (define_insn_and_split "divsi_inv_fp"
2663 [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
2664 (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
2665 (match_operand:SI 2 "register_operand" "rf")))
2666 (use (match_operand:SI 3 "general_movsrc_operand" "r"))
2667 (clobber (match_operand:SI 4 "register_operand" "=r"))
2668 (clobber (match_operand:SI 5 "register_operand" "=r"))
2669 (clobber (match_operand:DF 6 "register_operand" "=r"))
2670 (clobber (match_operand:DF 7 "register_operand" "=r"))
2671 (clobber (match_operand:DF 8 "register_operand" "=r"))]
2672 "TARGET_SHMEDIA_FPU"
2674 "&& (high_life_started || reload_completed)"
2675 [(set (match_dup 0) (match_dup 3))]
2677 [(set_attr "highpart" "must_split")])
2679 ;; If a matching group of divide-by-inverse instructions is in the same
2680 ;; basic block after gcse & loop optimizations, we want to transform them
2681 ;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
2682 (define_insn_and_split "*divsi_inv_fp_combine"
2683 [(set (match_operand:SI 0 "register_operand" "=f")
2684 (div:SI (match_operand:SI 1 "register_operand" "f")
2685 (match_operand:SI 2 "register_operand" "f")))
2686 (use (unspec:SI [(match_dup 1)
2687 (match_operand:SI 3 "" "")
2688 (unspec:SI [(match_operand:SI 4 "" "")
2690 (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
2691 (match_operand:DI 6 "" "")
2693 (const_int 0)] UNSPEC_DIV_INV_M3))
2694 (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
2695 (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
2696 (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
2697 (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
2698 (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
2699 "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
2702 [(set (match_dup 9) (float:DF (match_dup 1)))
2703 (set (match_dup 10) (float:DF (match_dup 2)))
2704 (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
2706 (fix:SI (match_dup 11)))
2707 (set (match_dup 0) (match_dup 8))]
2710 if (! fp_arith_reg_operand (operands[1], SImode))
2712 emit_move_insn (operands[7], operands[1]);
2713 operands[1] = operands[7];
2715 if (! fp_arith_reg_operand (operands[2], SImode))
2717 emit_move_insn (operands[8], operands[2]);
2718 operands[2] = operands[8];
2721 [(set_attr "highpart" "must_split")])
2723 ;; -------------------------------------------------------------------------
2724 ;; Multiplication instructions
2725 ;; -------------------------------------------------------------------------
2727 (define_insn "umulhisi3_i"
2728 [(set (reg:SI MACL_REG)
2729 (mult:SI (zero_extend:SI
2730 (match_operand:HI 0 "arith_reg_operand" "r"))
2732 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2735 [(set_attr "type" "smpy")])
2737 (define_insn "mulhisi3_i"
2738 [(set (reg:SI MACL_REG)
2739 (mult:SI (sign_extend:SI
2740 (match_operand:HI 0 "arith_reg_operand" "r"))
2742 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2745 [(set_attr "type" "smpy")])
2747 (define_expand "mulhisi3"
2748 [(set (reg:SI MACL_REG)
2749 (mult:SI (sign_extend:SI
2750 (match_operand:HI 1 "arith_reg_operand" ""))
2752 (match_operand:HI 2 "arith_reg_operand" ""))))
2753 (set (match_operand:SI 0 "arith_reg_operand" "")
2760 macl = gen_rtx_REG (SImode, MACL_REG);
2762 emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
2763 insn = get_insns ();
2765 /* expand_binop can't find a suitable code in umul_widen_optab to
2766 make a REG_EQUAL note from, so make one here.
2767 See also smulsi3_highpart.
2768 ??? Alternatively, we could put this at the calling site of expand_binop,
2769 i.e. expand_expr. */
2770 /* Use emit_libcall_block for loop invariant code motion and to make
2771 a REG_EQUAL note. */
2772 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
2777 (define_expand "umulhisi3"
2778 [(set (reg:SI MACL_REG)
2779 (mult:SI (zero_extend:SI
2780 (match_operand:HI 1 "arith_reg_operand" ""))
2782 (match_operand:HI 2 "arith_reg_operand" ""))))
2783 (set (match_operand:SI 0 "arith_reg_operand" "")
2790 macl = gen_rtx_REG (SImode, MACL_REG);
2792 emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
2793 insn = get_insns ();
2795 /* expand_binop can't find a suitable code in umul_widen_optab to
2796 make a REG_EQUAL note from, so make one here.
2797 See also smulsi3_highpart.
2798 ??? Alternatively, we could put this at the calling site of expand_binop,
2799 i.e. expand_expr. */
2800 /* Use emit_libcall_block for loop invariant code motion and to make
2801 a REG_EQUAL note. */
2802 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
2807 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
2808 ;; a call to a routine which clobbers known registers.
2811 [(set (match_operand:SI 1 "register_operand" "=z")
2812 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2813 (clobber (reg:SI MACL_REG))
2814 (clobber (reg:SI T_REG))
2815 (clobber (reg:SI PR_REG))
2816 (clobber (reg:SI R3_REG))
2817 (clobber (reg:SI R2_REG))
2818 (clobber (reg:SI R1_REG))
2819 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
2822 [(set_attr "type" "sfunc")
2823 (set_attr "needs_delay_slot" "yes")])
2825 (define_expand "mulsi3_call"
2826 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2827 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2828 (parallel[(set (match_operand:SI 0 "register_operand" "")
2829 (mult:SI (reg:SI R4_REG)
2831 (clobber (reg:SI MACL_REG))
2832 (clobber (reg:SI T_REG))
2833 (clobber (reg:SI PR_REG))
2834 (clobber (reg:SI R3_REG))
2835 (clobber (reg:SI R2_REG))
2836 (clobber (reg:SI R1_REG))
2837 (use (match_operand:SI 3 "register_operand" ""))])]
2841 (define_insn "mul_r"
2842 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2843 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
2844 (match_operand:SI 2 "arith_reg_operand" "z")))]
2847 [(set_attr "type" "dmpy")])
2849 (define_insn "mul_l"
2850 [(set (reg:SI MACL_REG)
2851 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
2852 (match_operand:SI 1 "arith_reg_operand" "r")))]
2855 [(set_attr "type" "dmpy")])
2857 (define_expand "mulsi3"
2858 [(set (reg:SI MACL_REG)
2859 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
2860 (match_operand:SI 2 "arith_reg_operand" "")))
2861 (set (match_operand:SI 0 "arith_reg_operand" "")
2868 /* The address must be set outside the libcall,
2869 since it goes into a pseudo. */
2870 rtx sym = function_symbol (NULL, \"__mulsi3\", SFUNC_STATIC);
2871 rtx addr = force_reg (SImode, sym);
2872 rtx insns = gen_mulsi3_call (operands[0], operands[1],
2878 rtx macl = gen_rtx_REG (SImode, MACL_REG);
2880 emit_insn (gen_mul_l (operands[1], operands[2]));
2881 /* consec_sets_giv can only recognize the first insn that sets a
2882 giv as the giv insn. So we must tag this also with a REG_EQUAL
2884 emit_insn (gen_movsi_i ((operands[0]), macl));
2889 (define_insn "mulsidi3_i"
2890 [(set (reg:SI MACH_REG)
2894 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2895 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2897 (set (reg:SI MACL_REG)
2898 (mult:SI (match_dup 0)
2902 [(set_attr "type" "dmpy")])
2904 (define_expand "mulsidi3"
2905 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2906 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
2907 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2908 "TARGET_SH2 || TARGET_SHMEDIA"
2913 emit_insn (gen_mulsidi3_compact (operands[0], operands[1],
2919 (define_insn "mulsidi3_media"
2920 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2921 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
2922 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
2925 [(set_attr "type" "dmpy_media")
2926 (set_attr "highpart" "ignore")])
2928 (define_insn "mulsidi3_compact"
2929 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2931 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
2932 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
2933 (clobber (reg:SI MACH_REG))
2934 (clobber (reg:SI MACL_REG))]
2939 [(set (match_operand:DI 0 "arith_reg_dest" "")
2941 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
2942 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
2943 (clobber (reg:SI MACH_REG))
2944 (clobber (reg:SI MACL_REG))]
2949 rtx low_dst = gen_lowpart (SImode, operands[0]);
2950 rtx high_dst = gen_highpart (SImode, operands[0]);
2952 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
2954 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2955 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2956 /* We need something to tag the possible REG_EQUAL notes on to. */
2957 emit_move_insn (operands[0], operands[0]);
2961 (define_insn "umulsidi3_i"
2962 [(set (reg:SI MACH_REG)
2966 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2967 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2969 (set (reg:SI MACL_REG)
2970 (mult:SI (match_dup 0)
2974 [(set_attr "type" "dmpy")])
2976 (define_expand "umulsidi3"
2977 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
2978 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
2979 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
2980 "TARGET_SH2 || TARGET_SHMEDIA"
2985 emit_insn (gen_umulsidi3_compact (operands[0], operands[1],
2991 (define_insn "umulsidi3_media"
2992 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2993 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
2994 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
2997 [(set_attr "type" "dmpy_media")
2998 (set_attr "highpart" "ignore")])
3000 (define_insn "umulsidi3_compact"
3001 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3003 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3004 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3005 (clobber (reg:SI MACH_REG))
3006 (clobber (reg:SI MACL_REG))]
3011 [(set (match_operand:DI 0 "arith_reg_dest" "")
3012 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3013 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
3014 (clobber (reg:SI MACH_REG))
3015 (clobber (reg:SI MACL_REG))]
3020 rtx low_dst = gen_lowpart (SImode, operands[0]);
3021 rtx high_dst = gen_highpart (SImode, operands[0]);
3023 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
3025 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3026 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3027 /* We need something to tag the possible REG_EQUAL notes on to. */
3028 emit_move_insn (operands[0], operands[0]);
3032 (define_insn "smulsi3_highpart_i"
3033 [(set (reg:SI MACH_REG)
3037 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3038 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3040 (clobber (reg:SI MACL_REG))]
3043 [(set_attr "type" "dmpy")])
3045 (define_expand "smulsi3_highpart"
3047 [(set (reg:SI MACH_REG)
3051 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3052 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3054 (clobber (reg:SI MACL_REG))])
3055 (set (match_operand:SI 0 "arith_reg_operand" "")
3062 mach = gen_rtx_REG (SImode, MACH_REG);
3064 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
3065 insn = get_insns ();
3067 /* expand_binop can't find a suitable code in mul_highpart_optab to
3068 make a REG_EQUAL note from, so make one here.
3069 See also {,u}mulhisi.
3070 ??? Alternatively, we could put this at the calling site of expand_binop,
3071 i.e. expand_mult_highpart. */
3072 /* Use emit_libcall_block for loop invariant code motion and to make
3073 a REG_EQUAL note. */
3074 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3079 (define_insn "umulsi3_highpart_i"
3080 [(set (reg:SI MACH_REG)
3084 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3085 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3087 (clobber (reg:SI MACL_REG))]
3090 [(set_attr "type" "dmpy")])
3092 (define_expand "umulsi3_highpart"
3094 [(set (reg:SI MACH_REG)
3098 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3099 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3101 (clobber (reg:SI MACL_REG))])
3102 (set (match_operand:SI 0 "arith_reg_operand" "")
3109 mach = gen_rtx_REG (SImode, MACH_REG);
3111 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
3112 insn = get_insns ();
3114 /* Use emit_libcall_block for loop invariant code motion and to make
3115 a REG_EQUAL note. */
3116 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3121 (define_insn_and_split "muldi3"
3122 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3123 (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
3124 (match_operand:DI 2 "arith_reg_operand" "r")))
3125 (clobber (match_scratch:DI 3 "=&r"))
3126 (clobber (match_scratch:DI 4 "=r"))]
3133 rtx op3_v2si, op2_v2si;
3135 op3_v2si = operands[3];
3136 if (GET_CODE (op3_v2si) == SIGN_EXTEND)
3138 op3_v2si = XEXP (op3_v2si, 0);
3139 op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
3141 op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
3142 op2_v2si = operands[2];
3143 if (GET_CODE (op2_v2si) == SIGN_EXTEND)
3145 op2_v2si = XEXP (op2_v2si, 0);
3146 op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
3148 op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
3149 emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
3150 emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
3151 emit_insn (gen_umulsidi3_media (operands[4],
3152 sh_gen_truncate (SImode, operands[1], 0),
3153 sh_gen_truncate (SImode, operands[2], 0)));
3154 emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
3155 emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
3156 emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
3157 emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
3162 ;; -------------------------------------------------------------------------
3163 ;; Logical operations
3164 ;; -------------------------------------------------------------------------
3166 (define_insn "*andsi3_compact"
3167 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
3168 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3169 (match_operand:SI 2 "logical_operand" "K08,r")))]
3172 [(set_attr "type" "arith")])
3174 (define_insn "*andsi3_media"
3175 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3176 (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3177 (match_operand:SI 2 "logical_operand" "r,I10")))]
3182 [(set_attr "type" "arith_media")])
3184 (define_insn "*andsi3_bclr"
3185 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3186 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3187 (match_operand:SI 2 "const_int_operand" "Psz")))]
3188 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
3190 [(set_attr "type" "arith")])
3192 ;; If the constant is 255, then emit an extu.b instruction instead of an
3193 ;; and, since that will give better code.
3195 (define_expand "andsi3"
3196 [(set (match_operand:SI 0 "arith_reg_operand" "")
3197 (and:SI (match_operand:SI 1 "logical_reg_operand" "")
3198 (match_operand:SI 2 "logical_operand" "")))]
3203 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 255)
3205 emit_insn (gen_zero_extendqisi2 (operands[0],
3206 gen_lowpart (QImode, operands[1])));
3211 (define_insn_and_split "anddi3"
3212 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
3213 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
3214 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
3221 && ! logical_operand (operands[2], DImode)"
3225 if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
3226 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
3228 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
3231 [(set_attr "type" "arith_media")])
3233 (define_insn "andcsi3"
3234 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3235 (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
3236 (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3239 [(set_attr "type" "arith_media")])
3241 (define_insn "andcdi3"
3242 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3243 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
3244 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
3247 [(set_attr "type" "arith_media")])
3249 (define_expand "iorsi3"
3250 [(set (match_operand:SI 0 "arith_reg_operand" "")
3251 (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
3252 (match_operand:SI 2 "logical_operand" "")))]
3256 (define_insn "*iorsi3_compact"
3257 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
3258 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3259 (match_operand:SI 2 "logical_operand" "r,K08")))]
3261 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
3263 [(set_attr "type" "arith")])
3265 (define_insn "*iorsi3_media"
3266 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3267 (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3268 (match_operand:SI 2 "logical_operand" "r,I10")))]
3273 [(set_attr "type" "arith_media")])
3275 (define_insn "*iorsi3_bset"
3276 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3277 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3278 (match_operand:SI 2 "const_int_operand" "Pso")))]
3279 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
3281 [(set_attr "type" "arith")])
3283 (define_insn "iordi3"
3284 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3285 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3286 (match_operand:DI 2 "logical_operand" "r,I10")))]
3291 [(set_attr "type" "arith_media")])
3293 (define_insn_and_split "*logical_sidi3"
3294 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3295 (sign_extend:DI (match_operator:SI 3 "logical_operator"
3296 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3297 (match_operand:SI 2 "logical_operand" "r,I10")])))]
3300 "&& reload_completed"
3301 [(set (match_dup 0) (match_dup 3))]
3305 = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
3306 simplify_gen_subreg (DImode, operands[1], SImode, 0),
3307 simplify_gen_subreg (DImode, operands[2], SImode, 0));
3310 (define_insn_and_split "*logical_sidisi3"
3311 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3312 (truncate:SI (sign_extend:DI
3313 (match_operator:SI 3 "logical_operator"
3314 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3315 (match_operand:SI 2 "logical_operand" "r,I10")]))))]
3319 [(set (match_dup 0) (match_dup 3))])
3321 (define_insn_and_split "*logical_sidi3_2"
3322 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3323 (sign_extend:DI (truncate:SI (sign_extend:DI
3324 (match_operator:SI 3 "logical_operator"
3325 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3326 (match_operand:SI 2 "logical_operand" "r,I10")])))))]
3330 [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])
3332 (define_expand "xorsi3"
3333 [(set (match_operand:SI 0 "arith_reg_operand" "")
3334 (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
3335 (match_operand:SI 2 "xor_operand" "")))]
3339 (define_insn "*xorsi3_compact"
3340 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
3341 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3342 (match_operand:SI 2 "logical_operand" "K08,r")))]
3345 [(set_attr "type" "arith")])
3347 (define_insn "*xorsi3_media"
3348 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3349 (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3350 (match_operand:SI 2 "xor_operand" "r,I06")))]
3355 [(set_attr "type" "arith_media")])
3357 (define_insn "xordi3"
3358 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3359 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3360 (match_operand:DI 2 "xor_operand" "r,I06")))]
3365 [(set_attr "type" "arith_media")])
3367 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
3368 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
3370 [(set (match_operand:DI 0 "arith_reg_dest" "")
3371 (sign_extend:DI (match_operator 4 "binary_logical_operator"
3372 [(match_operand 1 "any_register_operand" "")
3373 (match_operand 2 "any_register_operand" "")])))]
3375 [(set (match_dup 5) (match_dup 4))
3376 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
3379 enum machine_mode inmode = GET_MODE (operands[1]);
3382 if (GET_CODE (operands[0]) == SUBREG)
3384 offset = SUBREG_BYTE (operands[0]);
3385 operands[0] = SUBREG_REG (operands[0]);
3387 gcc_assert (REG_P (operands[0]));
3388 if (! TARGET_LITTLE_ENDIAN)
3389 offset += 8 - GET_MODE_SIZE (inmode);
3390 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
3393 ;; -------------------------------------------------------------------------
3394 ;; Shifts and rotates
3395 ;; -------------------------------------------------------------------------
3397 (define_expand "rotldi3"
3398 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3399 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
3400 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3402 "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
3404 (define_insn "rotldi3_mextr"
3405 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3406 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
3407 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3411 static char templ[16];
3413 sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\",
3414 8 - (int) (INTVAL (operands[2]) >> 3));
3417 [(set_attr "type" "arith_media")])
3419 (define_expand "rotrdi3"
3420 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3421 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
3422 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3424 "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
3426 (define_insn "rotrdi3_mextr"
3427 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3428 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
3429 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3433 static char templ[16];
3435 sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\", (int) INTVAL (operands[2]) >> 3);
3438 [(set_attr "type" "arith_media")])
3441 [(set (match_operand:DI 0 "arith_reg_dest" "")
3442 (ior:DI (zero_extend:DI (mem:QI (match_operand 1
3443 "ua_address_operand" "")))
3444 (ashift:DI (match_operand:DI 2 "arith_reg_operand" "")
3446 (clobber (match_operand:DI 3 "register_operand" ""))]
3448 [(match_dup 4) (match_dup 5)]
3451 operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q)
3452 (operands[3], operands[1]));
3453 operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2],
3454 GEN_INT (56), GEN_INT (8));
3457 (define_insn "rotlsi3_1"
3458 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3459 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
3462 (lshiftrt:SI (match_dup 1) (const_int 31)))]
3465 [(set_attr "type" "arith")])
3467 (define_insn "rotlsi3_31"
3468 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3469 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
3471 (clobber (reg:SI T_REG))]
3474 [(set_attr "type" "arith")])
3476 (define_insn "rotlsi3_16"
3477 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3478 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
3482 [(set_attr "type" "arith")])
3484 (define_expand "rotlsi3"
3485 [(set (match_operand:SI 0 "arith_reg_dest" "")
3486 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
3487 (match_operand:SI 2 "immediate_operand" "")))]
3491 static const char rot_tab[] = {
3492 000, 000, 000, 000, 000, 000, 010, 001,
3493 001, 001, 011, 013, 003, 003, 003, 003,
3494 003, 003, 003, 003, 003, 013, 012, 002,
3495 002, 002, 010, 000, 000, 000, 000, 000,
3500 if (!CONST_INT_P (operands[2]))
3502 count = INTVAL (operands[2]);
3503 choice = rot_tab[count];
3504 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
3510 emit_move_insn (operands[0], operands[1]);
3511 count -= (count & 16) * 2;
3514 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
3521 parts[0] = gen_reg_rtx (SImode);
3522 parts[1] = gen_reg_rtx (SImode);
3523 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
3524 emit_move_insn (parts[choice-1], operands[1]);
3525 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
3526 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
3527 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
3528 count = (count & ~16) - 8;
3532 for (; count > 0; count--)
3533 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3534 for (; count < 0; count++)
3535 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3540 (define_insn "*rotlhi3_8"
3541 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
3542 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
3546 [(set_attr "type" "arith")])
3548 (define_expand "rotlhi3"
3549 [(set (match_operand:HI 0 "arith_reg_operand" "")
3550 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
3551 (match_operand:HI 2 "immediate_operand" "")))]
3555 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 8)
3562 ;; This pattern is used by init_expmed for computing the costs of shift
3565 (define_insn_and_split "ashlsi3_std"
3566 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,r,r")
3567 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
3568 (match_operand:SI 2 "nonmemory_operand" "r,M,P27,?ri")))
3569 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
3570 "(TARGET_SH3 || TARGET_SH2A)
3571 || (TARGET_SH1 && satisfies_constraint_P27 (operands[2]))"
3577 "(TARGET_SH3 || TARGET_SH2A)
3579 && CONST_INT_P (operands[2])
3580 && ! satisfies_constraint_P27 (operands[2])"
3581 [(set (match_dup 3) (match_dup 2))
3583 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
3584 (clobber (match_dup 4))])]
3585 "operands[4] = gen_rtx_SCRATCH (SImode);"
3586 [(set_attr "length" "*,*,*,4")
3587 (set_attr "type" "dyn_shift,arith,arith,arith")])
3589 (define_insn "ashlhi3_k"
3590 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
3591 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
3592 (match_operand:HI 2 "const_int_operand" "M,P27")))]
3593 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
3597 [(set_attr "type" "arith")])
3599 (define_insn "ashlsi3_n"
3600 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3601 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3602 (match_operand:SI 2 "const_int_operand" "n")))
3603 (clobber (reg:SI T_REG))]
3604 "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
3606 [(set (attr "length")
3607 (cond [(match_test "shift_insns_rtx (insn)")
3609 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
3611 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
3613 (const_string "8")))
3614 (set_attr "type" "arith")])
3617 [(set (match_operand:SI 0 "arith_reg_dest" "")
3618 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
3619 (match_operand:SI 2 "const_int_operand" "")))
3620 (clobber (reg:SI T_REG))]
3621 "TARGET_SH1 && reload_completed"
3622 [(use (reg:SI R0_REG))]
3625 gen_shifty_op (ASHIFT, operands);
3629 (define_insn "ashlsi3_media"
3630 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3631 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
3632 (match_operand:SI 2 "shift_count_operand" "r,n")))]
3637 [(set_attr "type" "arith_media")
3638 (set_attr "highpart" "ignore")])
3640 (define_expand "ashlsi3"
3641 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
3642 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
3643 (match_operand:SI 2 "nonmemory_operand" "")))
3644 (clobber (reg:SI T_REG))])]
3650 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
3653 if (CONST_INT_P (operands[2])
3654 && sh_dynamicalize_shift_p (operands[2]))
3655 operands[2] = force_reg (SImode, operands[2]);
3656 if (TARGET_SH3 || TARGET_SH2A)
3658 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
3661 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
3665 (define_insn "*ashlhi3_n"
3666 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
3667 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
3668 (match_operand:HI 2 "const_int_operand" "n")))
3669 (clobber (reg:SI T_REG))]
3672 [(set (attr "length")
3673 (cond [(match_test "shift_insns_rtx (insn)")
3675 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
3677 (const_string "6")))
3678 (set_attr "type" "arith")])
3680 (define_expand "ashlhi3"
3681 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
3682 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
3683 (match_operand:SI 2 "nonmemory_operand" "")))
3684 (clobber (reg:SI T_REG))])]
3688 if (!CONST_INT_P (operands[2]))
3690 /* It may be possible to call gen_ashlhi3 directly with more generic
3691 operands. Make sure operands[1] is a HImode register here. */
3692 if (!arith_reg_operand (operands[1], HImode))
3693 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3697 [(set (match_operand:HI 0 "arith_reg_dest" "")
3698 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
3699 (match_operand:HI 2 "const_int_operand" "")))
3700 (clobber (reg:SI T_REG))]
3701 "TARGET_SH1 && reload_completed"
3702 [(use (reg:SI R0_REG))]
3705 gen_shifty_hi_op (ASHIFT, operands);
3710 ; arithmetic shift right
3713 (define_insn "ashrsi3_k"
3714 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3715 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3716 (match_operand:SI 2 "const_int_operand" "M")))
3717 (clobber (reg:SI T_REG))]
3718 "TARGET_SH1 && INTVAL (operands[2]) == 1"
3720 [(set_attr "type" "arith")])
3722 ;; We can't do HImode right shifts correctly unless we start out with an
3723 ;; explicit zero / sign extension; doing that would result in worse overall
3724 ;; code, so just let the machine independent code widen the mode.
3725 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
3728 ;; ??? This should be a define expand.
3730 (define_insn "ashrsi2_16"
3731 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3732 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
3736 [(set_attr "length" "4")])
3739 [(set (match_operand:SI 0 "arith_reg_dest" "")
3740 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3743 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
3744 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
3745 "operands[2] = gen_lowpart (HImode, operands[0]);")
3747 ;; ??? This should be a define expand.
3749 (define_insn "ashrsi2_31"
3750 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3751 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3753 (clobber (reg:SI T_REG))]
3756 [(set_attr "length" "4")])
3759 [(set (match_operand:SI 0 "arith_reg_dest" "")
3760 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3762 (clobber (reg:SI T_REG))]
3767 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
3768 emit_insn (gen_mov_neg_si_t (copy_rtx (operands[0])));
3773 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
3775 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
3777 && peep2_reg_dead_p (2, operands[0])
3778 && peep2_reg_dead_p (2, operands[1])"
3782 emit_insn (gen_ashlsi_c (operands[1], operands[1]));
3786 (define_insn "ashlsi_c"
3787 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3788 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
3790 (lt:SI (match_dup 1) (const_int 0)))]
3793 [(set_attr "type" "arith")])
3795 (define_insn "*ashlsi_c_void"
3796 [(set (reg:SI T_REG)
3797 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
3798 (clobber (match_scratch:SI 1 "=0"))]
3799 "TARGET_SH1 && cse_not_expected"
3801 [(set_attr "type" "arith")])
3803 (define_insn "ashrsi3_d"
3804 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3805 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3806 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3807 "TARGET_SH3 || TARGET_SH2A"
3809 [(set_attr "type" "dyn_shift")])
3811 (define_insn "ashrsi3_n"
3812 [(set (reg:SI R4_REG)
3813 (ashiftrt:SI (reg:SI R4_REG)
3814 (match_operand:SI 0 "const_int_operand" "i")))
3815 (clobber (reg:SI T_REG))
3816 (clobber (reg:SI PR_REG))
3817 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
3820 [(set_attr "type" "sfunc")
3821 (set_attr "needs_delay_slot" "yes")])
3823 (define_insn "ashrsi3_media"
3824 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3825 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
3826 (match_operand:SI 2 "shift_count_operand" "r,n")))]
3831 [(set_attr "type" "arith_media")
3832 (set_attr "highpart" "ignore")])
3834 (define_expand "ashrsi3"
3835 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
3836 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3837 (match_operand:SI 2 "nonmemory_operand" "")))
3838 (clobber (reg:SI T_REG))])]
3844 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
3847 if (expand_ashiftrt (operands))
3853 ;; logical shift right
3855 (define_insn "lshrsi3_d"
3856 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3857 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3858 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3859 "TARGET_SH3 || TARGET_SH2A"
3861 [(set_attr "type" "dyn_shift")])
3863 ;; Only the single bit shift clobbers the T bit.
3865 (define_insn "lshrsi3_m"
3866 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3867 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3868 (match_operand:SI 2 "const_int_operand" "M")))
3869 (clobber (reg:SI T_REG))]
3870 "TARGET_SH1 && satisfies_constraint_M (operands[2])"
3872 [(set_attr "type" "arith")])
3874 (define_insn "lshrsi3_k"
3875 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3876 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3877 (match_operand:SI 2 "const_int_operand" "P27")))]
3878 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])
3879 && ! satisfies_constraint_M (operands[2])"
3881 [(set_attr "type" "arith")])
3883 (define_insn "lshrsi3_n"
3884 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3885 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3886 (match_operand:SI 2 "const_int_operand" "n")))
3887 (clobber (reg:SI T_REG))]
3888 "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
3890 [(set (attr "length")
3891 (cond [(match_test "shift_insns_rtx (insn)")
3893 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
3895 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
3897 (const_string "8")))
3898 (set_attr "type" "arith")])
3901 [(set (match_operand:SI 0 "arith_reg_dest" "")
3902 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3903 (match_operand:SI 2 "const_int_operand" "")))
3904 (clobber (reg:SI T_REG))]
3905 "TARGET_SH1 && reload_completed"
3906 [(use (reg:SI R0_REG))]
3909 gen_shifty_op (LSHIFTRT, operands);
3913 (define_insn "lshrsi3_media"
3914 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3915 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
3916 (match_operand:SI 2 "shift_count_operand" "r,n")))]
3921 [(set_attr "type" "arith_media")
3922 (set_attr "highpart" "ignore")])
3924 (define_expand "lshrsi3"
3925 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
3926 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3927 (match_operand:SI 2 "nonmemory_operand" "")))
3928 (clobber (reg:SI T_REG))])]
3934 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
3937 if (CONST_INT_P (operands[2])
3938 && sh_dynamicalize_shift_p (operands[2]))
3939 operands[2] = force_reg (SImode, operands[2]);
3940 if ((TARGET_SH3 || TARGET_SH2A)
3941 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
3943 rtx count = copy_to_mode_reg (SImode, operands[2]);
3944 emit_insn (gen_negsi2 (count, count));
3945 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
3948 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
3952 ;; ??? This should be a define expand.
3954 (define_insn "ashldi3_k"
3955 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3956 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
3958 (clobber (reg:SI T_REG))]
3960 "shll %R0\;rotcl %S0"
3961 [(set_attr "length" "4")
3962 (set_attr "type" "arith")])
3964 ;; Expander for DImode shift left with SImode operations.
3966 (define_expand "ashldi3_std"
3967 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3968 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
3969 (match_operand:DI 2 "const_int_operand" "n")))]
3970 "TARGET_SH1 && INTVAL (operands[2]) < 32"
3973 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
3974 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
3975 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
3976 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
3977 rtx dst = gen_reg_rtx (DImode);
3978 rtx low_dst = operand_subword (dst, low_word, 1, DImode);
3979 rtx high_dst = operand_subword (dst, high_word, 1, DImode);
3982 tmp0 = gen_reg_rtx (SImode);
3983 tmp1 = gen_reg_rtx (SImode);
3984 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
3985 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
3986 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
3987 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
3988 emit_move_insn (operands[0], dst);
3992 (define_insn "ashldi3_media"
3993 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3994 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
3995 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4000 [(set_attr "type" "arith_media")])
4002 (define_insn "*ashldisi3_media"
4003 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4004 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4005 (match_operand:DI 2 "const_int_operand" "n")))]
4006 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4007 "shlli.l %1, %2, %0"
4008 [(set_attr "type" "arith_media")
4009 (set_attr "highpart" "ignore")])
4011 (define_expand "ashldi3"
4012 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4013 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
4014 (match_operand:DI 2 "immediate_operand" "")))
4015 (clobber (reg:SI T_REG))])]
4021 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
4024 if (CONST_INT_P (operands[2])
4025 && INTVAL (operands[2]) == 1)
4027 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
4030 else if (CONST_INT_P (operands[2])
4031 && INTVAL (operands[2]) < 32)
4033 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
4040 ;; ??? This should be a define expand.
4042 (define_insn "lshrdi3_k"
4043 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4044 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4046 (clobber (reg:SI T_REG))]
4048 "shlr %S0\;rotcr %R0"
4049 [(set_attr "length" "4")
4050 (set_attr "type" "arith")])
4052 (define_insn "lshrdi3_media"
4053 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
4054 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4055 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4057 && (arith_reg_dest (operands[0], DImode)
4058 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
4062 [(set_attr "type" "arith_media")])
4064 (define_insn "*lshrdisi3_media"
4065 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4066 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
4067 (match_operand:DI 2 "const_int_operand" "n")))]
4068 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4069 "shlri.l %1, %2, %0"
4070 [(set_attr "type" "arith_media")
4071 (set_attr "highpart" "ignore")])
4073 (define_expand "lshrdi3"
4074 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4075 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4076 (match_operand:DI 2 "immediate_operand" "")))
4077 (clobber (reg:SI T_REG))])]
4083 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
4086 if (!CONST_INT_P (operands[2])
4087 || INTVAL (operands[2]) != 1)
4091 ;; ??? This should be a define expand.
4093 (define_insn "ashrdi3_k"
4094 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4095 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4097 (clobber (reg:SI T_REG))]
4099 "shar %S0\;rotcr %R0"
4100 [(set_attr "length" "4")
4101 (set_attr "type" "arith")])
4103 (define_insn "ashrdi3_media"
4104 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
4105 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4106 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4108 && (arith_reg_dest (operands[0], DImode)
4109 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
4113 [(set_attr "type" "arith_media")])
4115 (define_insn "*ashrdisi3_media"
4116 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4117 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
4118 (match_operand:DI 2 "const_int_operand" "n")))]
4119 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4120 "shari.l %1, %2, %0"
4121 [(set_attr "type" "arith_media")
4122 (set_attr "highpart" "ignore")])
4124 (define_insn "ashrdisi3_media_high"
4125 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4127 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
4128 (match_operand:DI 2 "const_int_operand" "n"))))]
4129 "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
4131 [(set_attr "type" "arith_media")])
4133 (define_insn "ashrdisi3_media_opaque"
4134 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4135 (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
4136 (match_operand:DI 2 "const_int_operand" "n")]
4140 [(set_attr "type" "arith_media")])
4142 (define_expand "ashrdi3"
4143 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4144 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4145 (match_operand:DI 2 "immediate_operand" "")))
4146 (clobber (reg:SI T_REG))])]
4152 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
4155 if (!CONST_INT_P (operands[2])
4156 || INTVAL (operands[2]) != 1)
4160 ;; combined left/right shift
4163 [(set (match_operand:SI 0 "register_operand" "")
4164 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4165 (match_operand:SI 2 "const_int_operand" ""))
4166 (match_operand:SI 3 "const_int_operand" "")))]
4167 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4168 [(use (reg:SI R0_REG))]
4169 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
4173 [(set (match_operand:SI 0 "register_operand" "")
4174 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4175 (match_operand:SI 2 "const_int_operand" ""))
4176 (match_operand:SI 3 "const_int_operand" "")))
4177 (clobber (reg:SI T_REG))]
4178 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4179 [(use (reg:SI R0_REG))]
4180 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
4184 [(set (match_operand:SI 0 "register_operand" "=r")
4185 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4186 (match_operand:SI 2 "const_int_operand" "n"))
4187 (match_operand:SI 3 "const_int_operand" "n")))
4188 (clobber (reg:SI T_REG))]
4189 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
4191 [(set (attr "length")
4192 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4194 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4196 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4198 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
4200 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
4202 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
4204 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
4205 (const_string "16")]
4206 (const_string "18")))
4207 (set_attr "type" "arith")])
4210 [(set (match_operand:SI 0 "register_operand" "=z")
4211 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4212 (match_operand:SI 2 "const_int_operand" "n"))
4213 (match_operand:SI 3 "const_int_operand" "n")))
4214 (clobber (reg:SI T_REG))]
4215 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
4217 [(set (attr "length")
4218 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4220 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4222 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4224 (const_string "10")))
4225 (set_attr "type" "arith")])
4227 ;; shift left / and combination with a scratch register: The combine pass
4228 ;; does not accept the individual instructions, even though they are
4229 ;; cheap. But it needs a precise description so that it is usable after
4231 (define_insn "and_shl_scratch"
4232 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4236 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
4237 (match_operand:SI 2 "const_int_operand" "N,n"))
4238 (match_operand:SI 3 "" "0,r"))
4239 (match_operand:SI 4 "const_int_operand" "n,n"))
4240 (match_operand:SI 5 "const_int_operand" "n,n")))
4241 (clobber (reg:SI T_REG))]
4244 [(set (attr "length")
4245 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
4247 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
4249 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
4251 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
4252 (const_string "10")]
4253 (const_string "12")))
4254 (set_attr "type" "arith")])
4257 [(set (match_operand:SI 0 "register_operand" "")
4261 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
4262 (match_operand:SI 2 "const_int_operand" ""))
4263 (match_operand:SI 3 "register_operand" ""))
4264 (match_operand:SI 4 "const_int_operand" ""))
4265 (match_operand:SI 5 "const_int_operand" "")))
4266 (clobber (reg:SI T_REG))]
4268 [(use (reg:SI R0_REG))]
4271 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
4273 if (INTVAL (operands[2]))
4275 gen_shifty_op (LSHIFTRT, operands);
4277 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
4278 operands[2] = operands[4];
4279 gen_shifty_op (ASHIFT, operands);
4280 if (INTVAL (operands[5]))
4282 operands[2] = operands[5];
4283 gen_shifty_op (LSHIFTRT, operands);
4288 ;; signed left/right shift combination.
4290 [(set (match_operand:SI 0 "register_operand" "")
4292 (ashift:SI (match_operand:SI 1 "register_operand" "")
4293 (match_operand:SI 2 "const_int_operand" ""))
4294 (match_operand:SI 3 "const_int_operand" "")
4296 (clobber (reg:SI T_REG))]
4298 [(use (reg:SI R0_REG))]
4299 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
4302 (define_insn "shl_sext_ext"
4303 [(set (match_operand:SI 0 "register_operand" "=r")
4305 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4306 (match_operand:SI 2 "const_int_operand" "n"))
4307 (match_operand:SI 3 "const_int_operand" "n")
4309 (clobber (reg:SI T_REG))]
4310 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
4312 [(set (attr "length")
4313 (cond [(match_test "shl_sext_length (insn)")
4315 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
4317 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4319 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4321 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4323 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4325 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
4327 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
4328 (const_string "16")]
4329 (const_string "18")))
4330 (set_attr "type" "arith")])
4332 (define_insn "shl_sext_sub"
4333 [(set (match_operand:SI 0 "register_operand" "=z")
4335 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4336 (match_operand:SI 2 "const_int_operand" "n"))
4337 (match_operand:SI 3 "const_int_operand" "n")
4339 (clobber (reg:SI T_REG))]
4340 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
4342 [(set (attr "length")
4343 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4345 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4347 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4349 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4350 (const_string "12")]
4351 (const_string "14")))
4352 (set_attr "type" "arith")])
4354 ;; These patterns are found in expansions of DImode shifts by 16, and
4355 ;; allow the xtrct instruction to be generated from C source.
4357 (define_insn "xtrct_left"
4358 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4359 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4361 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
4365 [(set_attr "type" "arith")])
4367 (define_insn "xtrct_right"
4368 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4369 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4371 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
4375 [(set_attr "type" "arith")])
4377 ;; -------------------------------------------------------------------------
4379 ;; -------------------------------------------------------------------------
4381 (define_expand "negc"
4382 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
4383 (neg:SI (plus:SI (reg:SI T_REG)
4384 (match_operand:SI 1 "arith_reg_operand" ""))))
4386 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
4391 (define_insn "*negc"
4392 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4393 (neg:SI (plus:SI (reg:SI T_REG)
4394 (match_operand:SI 1 "arith_reg_operand" "r"))))
4396 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
4400 [(set_attr "type" "arith")])
4402 (define_insn "*negdi_media"
4403 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4404 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
4407 [(set_attr "type" "arith_media")])
4409 ;; Don't expand immediately because otherwise neg:DI (abs:DI) will not be
4411 (define_expand "negdi2"
4412 [(set (match_operand:DI 0 "arith_reg_dest" "")
4413 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
4414 (clobber (reg:SI T_REG))]
4418 (define_insn_and_split "*negdi2"
4419 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4420 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
4427 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
4428 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
4430 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
4431 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
4433 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
4434 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
4436 emit_insn (gen_clrt ());
4437 emit_insn (gen_negc (low_dst, low_src));
4438 emit_insn (gen_negc (high_dst, high_src));
4442 (define_insn "negsi2"
4443 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4444 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4447 [(set_attr "type" "arith")])
4449 (define_insn "one_cmplsi2"
4450 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4451 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4454 [(set_attr "type" "arith")])
4456 (define_expand "one_cmpldi2"
4457 [(set (match_operand:DI 0 "arith_reg_dest" "")
4458 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
4460 "TARGET_SHMEDIA" "")
4462 (define_expand "abssi2"
4463 [(set (match_operand:SI 0 "arith_reg_dest" "")
4464 (abs:SI (match_operand:SI 1 "arith_reg_operand" "")))
4465 (clobber (reg:SI T_REG))]
4469 (define_insn_and_split "*abssi2"
4470 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4471 (abs:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4478 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4479 emit_insn (gen_negsi_cond (operands[0], operands[1], operands[1],
4484 (define_insn_and_split "*negabssi2"
4485 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4486 (neg:SI (abs:SI (match_operand:SI 1 "arith_reg_operand" "r"))))]
4493 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4494 emit_insn (gen_negsi_cond (operands[0], operands[1], operands[1],
4499 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
4500 ;; This can be used as some kind of conditional execution, which is useful
4502 ;; Actually the instruction scheduling should decide whether to use a
4503 ;; zero-offset branch or not for any generic case involving a single
4504 ;; instruction on SH4 202.
4506 (define_insn_and_split "negsi_cond"
4507 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4508 (if_then_else:SI (eq:SI (reg:SI T_REG)
4509 (match_operand:SI 3 "const_int_operand" "M,N"))
4510 (match_operand:SI 1 "arith_reg_operand" "0,0")
4511 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
4514 bt\\t0f\;neg\\t%2,%0\\n0:
4515 bf\\t0f\;neg\\t%2,%0\\n0:"
4520 rtx skip_neg_label = gen_label_rtx ();
4522 emit_insn (gen_movsi (operands[0], operands[1]));
4524 emit_jump_insn (INTVAL (operands[3])
4525 ? gen_branch_true (skip_neg_label)
4526 : gen_branch_false (skip_neg_label));
4528 emit_label_after (skip_neg_label,
4529 emit_insn (gen_negsi2 (operands[0], operands[1])));
4532 [(set_attr "type" "arith") ;; poor approximation
4533 (set_attr "length" "4")])
4535 (define_expand "absdi2"
4536 [(set (match_operand:DI 0 "arith_reg_dest" "")
4537 (abs:DI (match_operand:DI 1 "arith_reg_operand" "")))
4538 (clobber (reg:SI T_REG))]
4542 (define_insn_and_split "*absdi2"
4543 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4544 (abs:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
4547 "&& reload_completed"
4550 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
4551 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
4552 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4553 emit_insn (gen_negdi_cond (operands[0], operands[1], operands[1],
4558 (define_insn_and_split "*negabsdi2"
4559 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4560 (neg:DI (abs:DI (match_operand:DI 1 "arith_reg_operand" "r"))))]
4563 "&& reload_completed"
4566 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
4567 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
4569 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4570 emit_insn (gen_negdi_cond (operands[0], operands[1], operands[1],
4575 (define_insn_and_split "negdi_cond"
4576 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4577 (if_then_else:DI (eq:SI (reg:SI T_REG)
4578 (match_operand:SI 3 "const_int_operand" "M,N"))
4579 (match_operand:DI 1 "arith_reg_operand" "r,r")
4580 (neg:DI (match_operand:DI 2 "arith_reg_operand" "1,1"))))]
4586 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
4587 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
4589 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
4590 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
4592 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
4593 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
4595 rtx skip_neg_label = gen_label_rtx ();
4597 emit_insn (gen_movsi (low_dst, low_src));
4598 emit_insn (gen_movsi (high_dst, high_src));
4600 emit_jump_insn (INTVAL (operands[3])
4601 ? gen_branch_true (skip_neg_label)
4602 : gen_branch_false (skip_neg_label));
4604 if (!INTVAL (operands[3]))
4605 emit_insn (gen_clrt ());
4607 emit_insn (gen_negc (low_dst, low_src));
4608 emit_label_after (skip_neg_label, emit_insn (gen_negc (high_dst, high_src)));
4612 ;; -------------------------------------------------------------------------
4613 ;; Zero extension instructions
4614 ;; -------------------------------------------------------------------------
4616 (define_insn "zero_extendsidi2"
4617 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4618 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
4620 "addz.l %1, r63, %0"
4621 [(set_attr "type" "arith_media")
4622 (set_attr "highpart" "extend")])
4624 (define_insn "zero_extendhidi2"
4625 [(set (match_operand:DI 0 "register_operand" "=r,r")
4626 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
4631 [(set_attr "type" "*,load_media")
4632 (set (attr "highpart")
4633 (cond [(match_test "sh_contains_memref_p (insn)")
4634 (const_string "user")]
4635 (const_string "ignore")))])
4638 [(set (match_operand:DI 0 "register_operand" "")
4639 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
4640 "TARGET_SHMEDIA && reload_completed"
4641 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
4642 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
4645 if (GET_CODE (operands[1]) == TRUNCATE)
4646 operands[1] = XEXP (operands[1], 0);
4649 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
4650 ;; reload the entire truncate expression.
4651 (define_insn_and_split "*loaddi_trunc"
4652 [(set (match_operand 0 "any_register_operand" "=r")
4653 (truncate (match_operand:DI 1 "memory_operand" "m")))]
4654 "TARGET_SHMEDIA && reload_completed"
4656 "TARGET_SHMEDIA && reload_completed"
4657 [(set (match_dup 0) (match_dup 1))]
4658 "operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));")
4660 (define_insn "zero_extendqidi2"
4661 [(set (match_operand:DI 0 "register_operand" "=r,r")
4662 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
4667 [(set_attr "type" "arith_media,load_media")
4668 (set (attr "highpart")
4669 (cond [(match_test "sh_contains_memref_p (insn)")
4670 (const_string "user")]
4671 (const_string "ignore")))])
4673 (define_expand "zero_extendhisi2"
4674 [(set (match_operand:SI 0 "arith_reg_operand" "")
4675 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "")))]
4679 if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], HImode))
4680 operands[1] = copy_to_mode_reg (HImode, operands[1]);
4683 (define_insn "*zero_extendhisi2_compact"
4684 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4685 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
4688 [(set_attr "type" "arith")])
4690 (define_insn "*zero_extendhisi2_media"
4691 [(set (match_operand:SI 0 "register_operand" "=r,r")
4692 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
4697 [(set_attr "type" "arith_media,load_media")
4698 (set (attr "highpart")
4699 (cond [(match_test "sh_contains_memref_p (insn)")
4700 (const_string "user")]
4701 (const_string "ignore")))])
4704 [(set (match_operand:SI 0 "register_operand" "")
4705 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
4706 "TARGET_SHMEDIA && reload_completed"
4707 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
4708 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
4711 rtx op1 = operands[1];
4713 if (GET_CODE (op1) == TRUNCATE)
4714 op1 = XEXP (op1, 0);
4716 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
4717 subreg_lowpart_offset (SImode, GET_MODE (op1)));
4720 (define_expand "zero_extendqisi2"
4721 [(set (match_operand:SI 0 "arith_reg_operand" "")
4722 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "")))]
4726 if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], QImode))
4727 operands[1] = copy_to_mode_reg (QImode, operands[1]);
4730 (define_insn "*zero_extendqisi2_compact"
4731 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4732 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
4735 [(set_attr "type" "arith")])
4737 (define_insn "*zero_extendqisi2_media"
4738 [(set (match_operand:SI 0 "register_operand" "=r,r")
4739 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
4744 [(set_attr "type" "arith_media,load_media")
4745 (set (attr "highpart")
4746 (cond [(match_test "sh_contains_memref_p (insn)")
4747 (const_string "user")]
4748 (const_string "ignore")))])
4750 (define_insn "zero_extendqihi2"
4751 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4752 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4755 [(set_attr "type" "arith")])
4757 ;; -------------------------------------------------------------------------
4758 ;; Sign extension instructions
4759 ;; -------------------------------------------------------------------------
4761 ;; ??? This should be a define expand.
4762 ;; ??? Or perhaps it should be dropped?
4764 ;; convert_move generates good code for SH[1-4].
4765 (define_insn "extendsidi2"
4766 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4767 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))]
4773 [(set_attr "type" "arith_media,load_media,fpconv_media")
4774 (set (attr "highpart")
4775 (cond [(match_test "sh_contains_memref_p (insn)")
4776 (const_string "user")]
4777 (const_string "extend")))])
4779 (define_insn "extendhidi2"
4780 [(set (match_operand:DI 0 "register_operand" "=r,r")
4781 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
4786 [(set_attr "type" "*,load_media")
4787 (set (attr "highpart")
4788 (cond [(match_test "sh_contains_memref_p (insn)")
4789 (const_string "user")]
4790 (const_string "ignore")))])
4793 [(set (match_operand:DI 0 "register_operand" "")
4794 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
4795 "TARGET_SHMEDIA && reload_completed"
4796 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
4797 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
4800 if (GET_CODE (operands[1]) == TRUNCATE)
4801 operands[1] = XEXP (operands[1], 0);
4804 (define_insn "extendqidi2"
4805 [(set (match_operand:DI 0 "register_operand" "=r,r")
4806 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
4811 [(set_attr "type" "*,load_media")
4812 (set (attr "highpart")
4813 (cond [(match_test "sh_contains_memref_p (insn)")
4814 (const_string "user")]
4815 (const_string "ignore")))])
4818 [(set (match_operand:DI 0 "register_operand" "")
4819 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
4820 "TARGET_SHMEDIA && reload_completed"
4821 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
4822 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
4825 if (GET_CODE (operands[1]) == TRUNCATE)
4826 operands[1] = XEXP (operands[1], 0);
4829 (define_expand "extendhisi2"
4830 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4831 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
4835 (define_insn "*extendhisi2_compact"
4836 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4837 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
4842 [(set_attr "type" "arith,load")])
4844 (define_insn "*extendhisi2_media"
4845 [(set (match_operand:SI 0 "register_operand" "=r,r")
4846 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
4851 [(set_attr "type" "arith_media,load_media")
4852 (set (attr "highpart")
4853 (cond [(match_test "sh_contains_memref_p (insn)")
4854 (const_string "user")]
4855 (const_string "ignore")))])
4858 [(set (match_operand:SI 0 "register_operand" "")
4859 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
4860 "TARGET_SHMEDIA && reload_completed"
4861 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
4862 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
4865 rtx op1 = operands[1];
4866 if (GET_CODE (op1) == TRUNCATE)
4867 op1 = XEXP (op1, 0);
4869 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
4870 subreg_lowpart_offset (SImode, GET_MODE (op1)));
4873 (define_expand "extendqisi2"
4874 [(set (match_operand:SI 0 "arith_reg_dest" "")
4875 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "")))]
4879 (define_insn "*extendqisi2_compact_reg"
4880 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4881 (sign_extend:SI (match_operand:QI 1 "register_operand" "r,t")))]
4886 [(set_attr "type" "arith,arith")])
4888 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
4890 (define_insn "*extendqisi2_compact_mem_disp"
4891 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
4893 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
4894 (match_operand:SI 2 "const_int_operand" "K04,N")))))]
4895 "TARGET_SH1 && ! TARGET_SH2A && CONST_OK_FOR_K04 (INTVAL (operands[2]))"
4899 [(set_attr "type" "load")])
4901 (define_insn "*extendqisi2_compact_mem_disp"
4902 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
4904 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
4905 (match_operand:SI 2 "const_int_operand" "K04,N,K12")))))]
4907 && (CONST_OK_FOR_K04 (INTVAL (operands[2]))
4908 || (CONST_OK_FOR_K12 (INTVAL (operands[2]))))"
4913 [(set_attr "type" "load")
4914 (set_attr "length" "2,2,4")])
4916 ;; This will take care of other QImode addressing modes than displacement
4918 (define_insn "*extendqisi2_compact_snd"
4919 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4920 (sign_extend:SI (match_operand:QI 1 "movsrc_no_disp_mem_operand" "Snd")))]
4923 [(set_attr "type" "load")])
4925 (define_insn "*extendqisi2_media"
4926 [(set (match_operand:SI 0 "register_operand" "=r,r")
4927 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
4932 [(set_attr "type" "arith_media,load_media")
4933 (set (attr "highpart")
4934 (cond [(match_test "sh_contains_memref_p (insn)")
4935 (const_string "user")]
4936 (const_string "ignore")))])
4939 [(set (match_operand:SI 0 "register_operand" "")
4940 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
4941 "TARGET_SHMEDIA && reload_completed"
4942 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
4943 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
4946 rtx op1 = operands[1];
4947 if (GET_CODE (op1) == TRUNCATE)
4948 op1 = XEXP (op1, 0);
4950 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
4951 subreg_lowpart_offset (SImode, GET_MODE (op1)));
4954 (define_expand "extendqihi2"
4955 [(set (match_operand:HI 0 "arith_reg_dest" "")
4956 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "")))]
4960 (define_insn "*extendqihi2_compact_reg"
4961 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4962 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4965 [(set_attr "type" "arith")])
4967 /* It would seem useful to combine the truncXi patterns into the movXi
4968 patterns, but unary operators are ignored when matching constraints,
4969 so we need separate patterns. */
4970 (define_insn "truncdisi2"
4971 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
4972 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
4981 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,fpconv_media,fmove_media")
4982 (set (attr "highpart")
4983 (cond [(match_test "sh_contains_memref_p (insn)")
4984 (const_string "user")]
4985 (const_string "extend")))])
4987 (define_insn "truncdihi2"
4988 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
4989 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
4992 shlli\\t%1,48,%0\;shlri\\t%0,48,%0
4994 [(set_attr "type" "arith_media,store_media")
4995 (set_attr "length" "8,4")
4996 (set (attr "highpart")
4997 (cond [(match_test "sh_contains_memref_p (insn)")
4998 (const_string "user")]
4999 (const_string "extend")))])
5001 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
5002 ; Because we use zero extension, we can't provide signed QImode compares
5003 ; using a simple compare or conditional branch insn.
5004 (define_insn "truncdiqi2"
5005 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
5006 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
5011 [(set_attr "type" "arith_media,store")
5012 (set (attr "highpart")
5013 (cond [(match_test "sh_contains_memref_p (insn)")
5014 (const_string "user")]
5015 (const_string "extend")))])
5016 ;; -------------------------------------------------------------------------
5017 ;; Move instructions
5018 ;; -------------------------------------------------------------------------
5020 ;; define push and pop so it is easy for sh.c
5021 ;; We can't use push and pop on SHcompact because the stack must always
5022 ;; be 8-byte aligned.
5024 (define_expand "push"
5025 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5026 (match_operand:SI 0 "register_operand" "r,l,x"))]
5027 "TARGET_SH1 && ! TARGET_SH5"
5030 (define_expand "pop"
5031 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
5032 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
5033 "TARGET_SH1 && ! TARGET_SH5"
5036 (define_expand "push_e"
5037 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
5038 (match_operand:SF 0 "" ""))
5039 (use (reg:PSI FPSCR_REG))
5040 (clobber (scratch:SI))])]
5041 "TARGET_SH1 && ! TARGET_SH5"
5044 (define_insn "push_fpul"
5045 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
5046 "TARGET_SH2E && ! TARGET_SH5"
5048 [(set_attr "type" "fstore")
5049 (set_attr "late_fp_use" "yes")
5050 (set_attr "hit_stack" "yes")])
5052 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
5054 (define_expand "push_4"
5055 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
5056 (match_operand:DF 0 "" ""))
5057 (use (reg:PSI FPSCR_REG))
5058 (clobber (scratch:SI))])]
5059 "TARGET_SH1 && ! TARGET_SH5"
5062 (define_expand "pop_e"
5063 [(parallel [(set (match_operand:SF 0 "" "")
5064 (mem:SF (post_inc:SI (reg:SI SP_REG))))
5065 (use (reg:PSI FPSCR_REG))
5066 (clobber (scratch:SI))])]
5067 "TARGET_SH1 && ! TARGET_SH5"
5070 (define_insn "pop_fpul"
5071 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
5072 "TARGET_SH2E && ! TARGET_SH5"
5074 [(set_attr "type" "load")
5075 (set_attr "hit_stack" "yes")])
5077 (define_expand "pop_4"
5078 [(parallel [(set (match_operand:DF 0 "" "")
5079 (mem:DF (post_inc:SI (reg:SI SP_REG))))
5080 (use (reg:PSI FPSCR_REG))
5081 (clobber (scratch:SI))])]
5082 "TARGET_SH1 && ! TARGET_SH5"
5085 (define_expand "push_fpscr"
5090 rtx insn = emit_insn (gen_fpu_switch (gen_frame_mem (PSImode,
5091 gen_rtx_PRE_DEC (Pmode,
5092 stack_pointer_rtx)),
5094 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5098 (define_expand "pop_fpscr"
5103 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
5104 gen_frame_mem (PSImode,
5105 gen_rtx_POST_INC (Pmode,
5106 stack_pointer_rtx))));
5107 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5111 ;; These two patterns can happen as the result of optimization, when
5112 ;; comparisons get simplified to a move of zero or 1 into the T reg.
5113 ;; They don't disappear completely, because the T reg is a fixed hard reg.
5116 [(set (reg:SI T_REG) (const_int 0))]
5121 [(set (reg:SI T_REG) (const_int 1))]
5125 ;; Define additional pop for SH1 and SH2 so it does not get
5126 ;; placed in the delay slot.
5127 (define_insn "*movsi_pop"
5128 [(set (match_operand:SI 0 "register_operand" "=r,x,l")
5129 (match_operand:SI 1 "sh_no_delay_pop_operand" ">,>,>"))]
5130 "(TARGET_SH1 || TARGET_SH2E || TARGET_SH2A)
5136 [(set_attr "type" "load_si,mem_mac,pload")
5137 (set_attr "length" "2,2,2")
5138 (set_attr "in_delay_slot" "no,no,no")])
5140 ;; t/r must come after r/r, lest reload will try to reload stuff like
5141 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
5142 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
5143 (define_insn "movsi_i"
5144 [(set (match_operand:SI 0 "general_movdst_operand"
5145 "=r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
5146 (match_operand:SI 1 "general_movsrc_operand"
5147 "Q,r,I08,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
5151 && (register_operand (operands[0], SImode)
5152 || register_operand (operands[1], SImode))"
5170 [(set_attr "type" "pcload_si,move,movi8,mt_group,load_si,mac_gp,prget,arith,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
5171 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
5173 ;; t/r must come after r/r, lest reload will try to reload stuff like
5174 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
5175 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
5176 ;; will require a reload.
5177 ;; ??? We can't include f/f because we need the proper FPSCR setting when
5178 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
5179 (define_insn "movsi_ie"
5180 [(set (match_operand:SI 0 "general_movdst_operand"
5181 "=r,r,r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
5182 (match_operand:SI 1 "general_movsrc_operand"
5183 "Q,r,I08,I20,I28,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
5184 "(TARGET_SH2E || TARGET_SH2A)
5185 && (register_operand (operands[0], SImode)
5186 || register_operand (operands[1], SImode))"
5213 ! move optimized away"
5214 [(set_attr "type" "pcload_si,move,movi8,move,move,*,load_si,mac_gp,prget,arith,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
5215 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
5216 (set_attr_alternative "length"
5224 (match_test "TARGET_SH2A")
5225 (const_int 4) (const_int 2))
5230 (match_test "TARGET_SH2A")
5231 (const_int 4) (const_int 2))
5248 (define_insn "movsi_i_lowpart"
5249 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,r,m,r"))
5250 (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,t,r,i"))]
5252 && (register_operand (operands[0], SImode)
5253 || register_operand (operands[1], SImode))"
5264 [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,arith,store,pcload")])
5266 (define_insn_and_split "load_ra"
5267 [(set (match_operand:SI 0 "general_movdst_operand" "")
5268 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
5271 "&& ! currently_expanding_to_rtl"
5272 [(set (match_dup 0) (match_dup 1))]
5275 if (TARGET_SHCOMPACT && crtl->saves_all_registers)
5276 operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
5279 ;; The '?'s in the following constraints may not reflect the time taken
5280 ;; to perform the move. They are there to discourage the use of floating-
5281 ;; point registers for storing integer values.
5282 (define_insn "*movsi_media"
5283 [(set (match_operand:SI 0 "general_movdst_operand"
5284 "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b")
5285 (match_operand:SI 1 "general_movsrc_operand"
5286 "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
5288 && (register_operand (operands[0], SImode)
5289 || sh_register_operand (operands[1], SImode)
5290 || GET_CODE (operands[1]) == TRUNCATE)"
5305 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,fpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
5306 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
5307 (set (attr "highpart")
5308 (cond [(match_test "sh_contains_memref_p (insn)")
5309 (const_string "user")]
5310 (const_string "ignore")))])
5312 (define_insn "*movsi_media_nofpu"
5313 [(set (match_operand:SI 0 "general_movdst_operand"
5314 "=r,r,r,r,m,*b,r,*b")
5315 (match_operand:SI 1 "general_movsrc_operand"
5316 "r,I16Css,nCpg,m,rZ,r,*b,Csy"))]
5318 && (register_operand (operands[0], SImode)
5319 || sh_register_operand (operands[1], SImode)
5320 || GET_CODE (operands[1]) == TRUNCATE)"
5330 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
5331 (set_attr "length" "4,4,8,4,4,4,4,12")
5332 (set (attr "highpart")
5333 (cond [(match_test "sh_contains_memref_p (insn)")
5334 (const_string "user")]
5335 (const_string "ignore")))])
5337 (define_expand "movsi_const"
5338 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
5339 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
5340 (const_int 16)] UNSPEC_EXTRACT_S16)))
5342 (ior:SI (ashift:SI (match_dup 0) (const_int 16))
5343 (const:SI (unspec:SI [(match_dup 1)
5344 (const_int 0)] UNSPEC_EXTRACT_U16))))]
5345 "TARGET_SHMEDIA && reload_completed
5346 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
5349 if (GET_CODE (operands[1]) == LABEL_REF
5350 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
5351 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
5352 else if (GOTOFF_P (operands[1]))
5354 rtx unspec = XEXP (operands[1], 0);
5356 if (! UNSPEC_GOTOFF_P (unspec))
5358 unspec = XEXP (unspec, 0);
5359 if (! UNSPEC_GOTOFF_P (unspec))
5362 if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF
5363 && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL))
5364 LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2;
5368 (define_expand "movsi_const_16bit"
5369 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
5370 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
5371 (const_int 0)] UNSPEC_EXTRACT_S16)))]
5372 "TARGET_SHMEDIA && flag_pic && reload_completed
5373 && GET_CODE (operands[1]) == SYMBOL_REF"
5377 [(set (match_operand:SI 0 "arith_reg_dest" "")
5378 (match_operand:SI 1 "immediate_operand" ""))]
5379 "TARGET_SHMEDIA && reload_completed
5380 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
5384 rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1]));
5386 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
5392 [(set (match_operand:SI 0 "register_operand" "")
5393 (match_operand:SI 1 "immediate_operand" ""))]
5394 "TARGET_SHMEDIA && reload_completed
5395 && ((CONST_INT_P (operands[1])
5396 && ! satisfies_constraint_I16 (operands[1]))
5397 || GET_CODE (operands[1]) == CONST_DOUBLE)"
5398 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
5400 (define_expand "movsi"
5401 [(set (match_operand:SI 0 "general_movdst_operand" "")
5402 (match_operand:SI 1 "general_movsrc_operand" ""))]
5404 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
5406 (define_expand "ic_invalidate_line"
5407 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
5408 (match_dup 1)] UNSPEC_ICACHE)
5409 (clobber (scratch:SI))])]
5410 "TARGET_HARD_SH4 || TARGET_SH5"
5415 emit_insn (gen_ic_invalidate_line_media (operands[0]));
5418 else if (TARGET_SHCOMPACT)
5420 operands[1] = function_symbol (NULL, \"__ic_invalidate\", SFUNC_STATIC);
5421 operands[1] = force_reg (Pmode, operands[1]);
5422 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
5425 else if (TARGET_SH4A_ARCH || TARGET_SH4_300)
5427 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
5430 operands[0] = force_reg (Pmode, operands[0]);
5431 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
5435 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
5436 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
5437 ;; the requirement *1*00 for associative address writes. The alignment of
5438 ;; %0 implies that its least significant bit is cleared,
5439 ;; thus we clear the V bit of a matching entry if there is one.
5440 (define_insn "ic_invalidate_line_i"
5441 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
5442 (match_operand:SI 1 "register_operand" "r")]
5444 (clobber (match_scratch:SI 2 "=&r"))]
5446 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
5447 [(set_attr "length" "8")
5448 (set_attr "type" "cwb")])
5450 (define_insn "ic_invalidate_line_sh4a"
5451 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
5453 "TARGET_SH4A_ARCH || TARGET_SH4_300"
5454 "ocbwb\\t@%0\;synco\;icbi\\t@%0"
5455 [(set_attr "length" "16")
5456 (set_attr "type" "cwb")])
5458 ;; ??? could make arg 0 an offsettable memory operand to allow to save
5459 ;; an add in the code that calculates the address.
5460 (define_insn "ic_invalidate_line_media"
5461 [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
5464 "ocbwb %0,0\;synco\;icbi %0, 0\;synci"
5465 [(set_attr "length" "16")
5466 (set_attr "type" "invalidate_line_media")])
5468 (define_insn "ic_invalidate_line_compact"
5469 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
5470 (match_operand:SI 1 "register_operand" "r")]
5472 (clobber (reg:SI PR_REG))]
5475 [(set_attr "type" "sfunc")
5476 (set_attr "needs_delay_slot" "yes")])
5478 (define_expand "initialize_trampoline"
5479 [(match_operand:SI 0 "" "")
5480 (match_operand:SI 1 "" "")
5481 (match_operand:SI 2 "" "")]
5487 tramp = force_reg (Pmode, operands[0]);
5488 sfun = force_reg (Pmode, function_symbol (NULL, \"__init_trampoline\",
5490 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
5491 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
5493 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
5497 (define_insn "initialize_trampoline_compact"
5498 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
5499 (match_operand:SI 1 "register_operand" "r")
5500 (reg:SI R2_REG) (reg:SI R3_REG)]
5503 (clobber (reg:SI PR_REG))]
5506 [(set_attr "type" "sfunc")
5507 (set_attr "needs_delay_slot" "yes")])
5509 (define_expand "movqi"
5510 [(set (match_operand:QI 0 "general_operand" "")
5511 (match_operand:QI 1 "general_operand" ""))]
5513 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
5515 ;; If movqi_reg_reg is specified as an alternative of movqi, movqi will be
5516 ;; selected to copy QImode regs. If one of them happens to be allocated
5517 ;; on the stack, reload will stick to movqi insn and generate wrong
5518 ;; displacement addressing because of the generic m alternatives.
5519 ;; With the movqi_reg_reg being specified before movqi it will be intially
5520 ;; picked to load/store regs. If the regs regs are on the stack reload will
5521 ;; try other insns and not stick to movqi_reg_reg.
5522 (define_insn "*movqi_reg_reg"
5523 [(set (match_operand:QI 0 "arith_reg_dest" "=r,r")
5524 (match_operand:QI 1 "register_operand" "r,t"))]
5529 [(set_attr "type" "move,arith")])
5531 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
5532 ;; "enabled" attribute as it is done in other targets.
5533 (define_insn "*movqi_store_mem_disp04"
5534 [(set (mem:QI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
5535 (match_operand:SI 1 "const_int_operand" "K04,N")))
5536 (match_operand:QI 2 "arith_reg_operand" "z,r"))]
5537 "TARGET_SH1 && CONST_OK_FOR_K04 (INTVAL (operands[1]))"
5541 [(set_attr "type" "store")])
5543 (define_insn "*movqi_store_mem_disp12"
5544 [(set (mem:QI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
5545 (match_operand:SI 1 "const_int_operand" "K12")))
5546 (match_operand:QI 2 "arith_reg_operand" "r"))]
5547 "TARGET_SH2A && CONST_OK_FOR_K12 (INTVAL (operands[1]))"
5548 "mov.b %2,@(%O1,%0)"
5549 [(set_attr "type" "store")
5550 (set_attr "length" "4")])
5552 (define_insn "*movqi_load_mem_disp"
5553 [(set (match_operand:QI 0 "arith_reg_dest" "=z,r")
5554 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
5555 (match_operand:SI 2 "const_int_operand" "K04,N"))))]
5556 "TARGET_SH1 && ! TARGET_SH2A && CONST_OK_FOR_K04 (INTVAL (operands[2]))"
5560 [(set_attr "type" "load")])
5562 (define_insn "*movqi_load_mem_disp"
5563 [(set (match_operand:QI 0 "arith_reg_dest" "=z,r,r")
5564 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
5565 (match_operand:SI 2 "const_int_operand" "K04,N,K12"))))]
5567 && (CONST_OK_FOR_K04 (INTVAL (operands[2]))
5568 || CONST_OK_FOR_K12 (INTVAL (operands[2])))"
5573 [(set_attr "type" "load")
5574 (set_attr "length" "2,2,4")])
5576 ;; The m constraints basically allow any kind of addresses to be used with any
5577 ;; source/target register as the other operand. This is not true for
5578 ;; displacement addressing modes on anything but SH2A. That's why the
5579 ;; specialized load/store insns are specified above.
5580 (define_insn "*movqi"
5581 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,l")
5582 (match_operand:QI 1 "general_movsrc_operand" "i,m,r,l,r"))]
5584 && (arith_reg_operand (operands[0], QImode)
5585 || arith_reg_operand (operands[1], QImode))"
5592 [(set_attr "type" "movi8,load,store,prget,prset")])
5594 (define_insn "*movqi_media"
5595 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
5596 (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))]
5598 && (arith_reg_operand (operands[0], QImode)
5599 || extend_reg_or_0_operand (operands[1], QImode))"
5605 [(set_attr "type" "arith_media,arith_media,load_media,store_media")
5606 (set (attr "highpart")
5607 (cond [(match_test "sh_contains_memref_p (insn)")
5608 (const_string "user")]
5609 (const_string "ignore")))])
5611 (define_expand "reload_inqi"
5612 [(set (match_operand:SI 2 "" "=&r")
5613 (match_operand:QI 1 "inqhi_operand" ""))
5614 (set (match_operand:QI 0 "arith_reg_operand" "=r")
5615 (truncate:QI (match_dup 3)))]
5619 rtx inner = XEXP (operands[1], 0);
5620 int regno = REGNO (inner);
5622 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
5623 operands[1] = gen_rtx_REG (SImode, regno);
5624 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
5627 ;; When storing r0, we have to avoid reg+reg addressing.
5628 (define_insn "movhi_i"
5629 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
5630 (match_operand:HI 1 "general_movsrc_operand" "Q,rI08,m,t,r,l,r,i"))]
5632 && (arith_reg_operand (operands[0], HImode)
5633 || arith_reg_operand (operands[1], HImode))
5634 && (!MEM_P (operands[0])
5635 || GET_CODE (XEXP (operands[0], 0)) != PLUS
5636 || !REG_P (XEXP (XEXP (operands[0], 0), 1))
5637 || ! refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0))"
5647 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
5649 (define_insn "*movhi_media"
5650 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
5651 (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))]
5653 && (arith_reg_operand (operands[0], HImode)
5654 || arith_reg_or_0_operand (operands[1], HImode))"
5661 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
5662 (set (attr "highpart")
5663 (cond [(match_test "sh_contains_memref_p (insn)")
5664 (const_string "user")]
5665 (const_string "ignore")))])
5668 [(set (match_operand:HI 0 "register_operand" "")
5669 (match_operand:HI 1 "immediate_operand" ""))]
5670 "TARGET_SHMEDIA && reload_completed
5671 && ! satisfies_constraint_I16 (operands[1])"
5672 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
5674 (define_expand "movhi"
5675 [(set (match_operand:HI 0 "general_movdst_operand" "")
5676 (match_operand:HI 1 "general_movsrc_operand" ""))]
5678 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
5680 (define_expand "reload_inhi"
5681 [(set (match_operand:SI 2 "" "=&r")
5682 (match_operand:HI 1 "inqhi_operand" ""))
5683 (set (match_operand:HI 0 "arith_reg_operand" "=r")
5684 (truncate:HI (match_dup 3)))]
5688 rtx inner = XEXP (operands[1], 0);
5689 int regno = REGNO (inner);
5691 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
5692 operands[1] = gen_rtx_REG (SImode, regno);
5693 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
5696 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
5697 ;; compiled with -m2 -ml -O3 -funroll-loops
5698 (define_insn "*movdi_i"
5699 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
5700 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
5702 && (arith_reg_operand (operands[0], DImode)
5703 || arith_reg_operand (operands[1], DImode))"
5704 "* return output_movedouble (insn, operands, DImode);"
5705 [(set_attr "length" "4")
5706 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
5708 ;; If the output is a register and the input is memory or a register, we have
5709 ;; to be careful and see which word needs to be loaded first.
5712 [(set (match_operand:DI 0 "general_movdst_operand" "")
5713 (match_operand:DI 1 "general_movsrc_operand" ""))]
5714 "TARGET_SH1 && reload_completed"
5715 [(set (match_dup 2) (match_dup 3))
5716 (set (match_dup 4) (match_dup 5))]
5721 if ((MEM_P (operands[0])
5722 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5723 || (MEM_P (operands[1])
5724 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5727 switch (GET_CODE (operands[0]))
5730 regno = REGNO (operands[0]);
5733 regno = subreg_regno (operands[0]);
5743 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
5745 operands[2] = operand_subword (operands[0], 0, 0, DImode);
5746 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5747 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5748 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5752 operands[2] = operand_subword (operands[0], 1, 0, DImode);
5753 operands[3] = operand_subword (operands[1], 1, 0, DImode);
5754 operands[4] = operand_subword (operands[0], 0, 0, DImode);
5755 operands[5] = operand_subword (operands[1], 0, 0, DImode);
5758 if (operands[2] == 0 || operands[3] == 0
5759 || operands[4] == 0 || operands[5] == 0)
5763 ;; The '?'s in the following constraints may not reflect the time taken
5764 ;; to perform the move. They are there to discourage the use of floating-
5765 ;; point registers for storing integer values.
5766 (define_insn "*movdi_media"
5767 [(set (match_operand:DI 0 "general_movdst_operand"
5768 "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b")
5769 (match_operand:DI 1 "general_movsrc_operand"
5770 "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
5772 && (register_operand (operands[0], DImode)
5773 || sh_register_operand (operands[1], DImode))"
5788 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,fload_media,fstore_media,fload_media,dfpconv_media,fmove_media,ptabs_media,gettr_media,pt_media")
5789 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
5791 (define_insn "*movdi_media_nofpu"
5792 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b");
5793 (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))]
5795 && (register_operand (operands[0], DImode)
5796 || sh_register_operand (operands[1], DImode))"
5806 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,ptabs_media,gettr_media,pt_media")
5807 (set_attr "length" "4,4,16,4,4,4,4,*")])
5809 (define_insn "*movdi_media_I16"
5810 [(set (match_operand:DI 0 "ext_dest_operand" "=r")
5811 (match_operand:DI 1 "const_int_operand" "I16"))]
5812 "TARGET_SHMEDIA && reload_completed"
5814 [(set_attr "type" "arith_media")
5815 (set_attr "length" "4")])
5818 [(set (match_operand:DI 0 "arith_reg_dest" "")
5819 (match_operand:DI 1 "immediate_operand" ""))]
5820 "TARGET_SHMEDIA && reload_completed
5821 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
5822 [(set (match_dup 0) (match_dup 1))]
5827 if (TARGET_SHMEDIA64)
5828 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
5830 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
5832 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
5837 (define_expand "movdi_const"
5838 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
5839 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
5840 (const_int 48)] UNSPEC_EXTRACT_S16)))
5842 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
5843 (const:DI (unspec:DI [(match_dup 1)
5844 (const_int 32)] UNSPEC_EXTRACT_U16))))
5846 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
5847 (const:DI (unspec:DI [(match_dup 1)
5848 (const_int 16)] UNSPEC_EXTRACT_U16))))
5850 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
5851 (const:DI (unspec:DI [(match_dup 1)
5852 (const_int 0)] UNSPEC_EXTRACT_U16))))]
5853 "TARGET_SHMEDIA64 && reload_completed
5854 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
5857 sh_mark_label (operands[1], 4);
5860 (define_expand "movdi_const_32bit"
5861 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
5862 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
5863 (const_int 16)] UNSPEC_EXTRACT_S16)))
5865 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
5866 (const:DI (unspec:DI [(match_dup 1)
5867 (const_int 0)] UNSPEC_EXTRACT_U16))))]
5868 "TARGET_SHMEDIA32 && reload_completed
5869 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
5872 sh_mark_label (operands[1], 2);
5875 (define_expand "movdi_const_16bit"
5876 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
5877 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
5878 (const_int 0)] UNSPEC_EXTRACT_S16)))]
5879 "TARGET_SHMEDIA && flag_pic && reload_completed
5880 && GET_CODE (operands[1]) == SYMBOL_REF"
5884 [(set (match_operand:DI 0 "ext_dest_operand" "")
5885 (match_operand:DI 1 "immediate_operand" ""))]
5886 "TARGET_SHMEDIA && reload_completed
5887 && CONST_INT_P (operands[1])
5888 && ! satisfies_constraint_I16 (operands[1])"
5889 [(set (match_dup 0) (match_dup 2))
5893 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
5894 unsigned HOST_WIDE_INT low = val;
5895 unsigned HOST_WIDE_INT high = val;
5896 unsigned HOST_WIDE_INT sign;
5897 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
5899 /* Zero-extend the 16 least-significant bits. */
5902 /* Arithmetic shift right the word by 16 bits. */
5904 if (GET_CODE (operands[0]) == SUBREG
5905 && GET_MODE (SUBREG_REG (operands[0])) == SImode)
5914 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
5920 /* If we can't generate the constant with a two-insn movi / shori
5921 sequence, try some other strategies. */
5922 if (! CONST_OK_FOR_I16 (high))
5924 /* Try constant load / left shift. We know VAL != 0. */
5925 val2 = val ^ (val-1);
5928 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
5930 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
5931 || (! CONST_OK_FOR_I16 (high >> 16)
5932 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
5934 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
5935 operands[1] = gen_ashldi3_media (operands[0], operands[0],
5936 GEN_INT (trailing_zeroes));
5940 /* Try constant load / right shift. */
5941 val2 = (val >> 15) + 1;
5942 if (val2 == (val2 & -val2))
5944 int shift = 49 - exact_log2 (val2);
5946 val2 = trunc_int_for_mode (val << shift, DImode);
5947 if (CONST_OK_FOR_I16 (val2))
5949 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
5955 val2 = val & 0xffff;
5956 if ((val >> 16 & 0xffff) == val2
5957 && (val >> 32 & 0xffff) == val2
5958 && (val >> 48 & 0xffff) == val2)
5960 val2 = (HOST_WIDE_INT) val >> 48;
5961 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
5962 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
5965 /* Try movi / mshflo.l */
5966 val2 = (HOST_WIDE_INT) val >> 32;
5967 if (val2 == ((unsigned HOST_WIDE_INT)
5968 trunc_int_for_mode (val, SImode)))
5970 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
5974 /* Try movi / mshflo.l w/ r63. */
5975 val2 = val + ((HOST_WIDE_INT) -1 << 32);
5976 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
5978 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
5984 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
5987 operands[2] = GEN_INT (val2);
5991 [(set (match_operand:DI 0 "ext_dest_operand" "")
5992 (match_operand:DI 1 "immediate_operand" ""))]
5993 "TARGET_SHMEDIA && reload_completed
5994 && GET_CODE (operands[1]) == CONST_DOUBLE"
5995 [(set (match_dup 0) (match_dup 2))
5997 (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))]
6000 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
6001 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
6002 unsigned HOST_WIDE_INT val = low;
6003 unsigned HOST_WIDE_INT sign;
6005 /* Zero-extend the 16 least-significant bits. */
6007 operands[1] = GEN_INT (val);
6009 /* Arithmetic shift right the double-word by 16 bits. */
6011 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
6014 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
6018 /* This will only be true if high is a sign-extension of low, i.e.,
6019 it must be either 0 or (unsigned)-1, and be zero iff the
6020 most-significant bit of low is set. */
6021 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
6022 operands[2] = GEN_INT (low);
6024 operands[2] = immed_double_const (low, high, DImode);
6027 (define_insn "shori_media"
6028 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
6029 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
6031 (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))]
6032 "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))"
6036 [(set_attr "type" "arith_media,*")])
6038 (define_insn "*shori_media_si"
6039 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6040 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
6042 (match_operand:SI 2 "immediate_operand" "K16Csu")))]
6046 (define_expand "movdi"
6047 [(set (match_operand:DI 0 "general_movdst_operand" "")
6048 (match_operand:DI 1 "general_movsrc_operand" ""))]
6050 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
6052 (define_insn "movdf_media"
6053 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
6054 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
6056 && (register_operand (operands[0], DFmode)
6057 || sh_register_operand (operands[1], DFmode))"
6068 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
6070 (define_insn "movdf_media_nofpu"
6071 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
6072 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
6074 && (register_operand (operands[0], DFmode)
6075 || sh_register_operand (operands[1], DFmode))"
6081 [(set_attr "type" "arith_media,*,load_media,store_media")])
6084 [(set (match_operand:DF 0 "arith_reg_dest" "")
6085 (match_operand:DF 1 "immediate_operand" ""))]
6086 "TARGET_SHMEDIA && reload_completed"
6087 [(set (match_dup 3) (match_dup 2))]
6090 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
6092 REAL_VALUE_TYPE value;
6094 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
6095 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
6097 if (HOST_BITS_PER_WIDE_INT >= 64)
6098 operands[2] = immed_double_const ((unsigned long) values[endian]
6099 | ((HOST_WIDE_INT) values[1 - endian]
6103 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
6104 operands[2] = immed_double_const (values[endian], values[1 - endian],
6108 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
6111 ;; ??? This should be a define expand.
6113 (define_insn "movdf_k"
6114 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
6115 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
6117 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
6118 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
6119 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
6120 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
6121 && (arith_reg_operand (operands[0], DFmode)
6122 || arith_reg_operand (operands[1], DFmode))"
6123 "* return output_movedouble (insn, operands, DFmode);"
6124 [(set_attr "length" "4")
6125 (set_attr "type" "move,pcload,load,store")])
6127 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
6128 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
6129 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
6130 ;; the d/m/c/X alternative, which is split later into single-precision
6131 ;; instructions. And when not optimizing, no splits are done before fixing
6132 ;; up pcloads, so we need usable length information for that.
6133 (define_insn "movdf_i4"
6134 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
6135 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
6136 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
6137 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
6138 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
6139 && (arith_reg_operand (operands[0], DFmode)
6140 || arith_reg_operand (operands[1], DFmode))"
6142 switch (which_alternative)
6146 return "fmov %1,%0";
6147 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
6148 return "fmov %R1,%R0\n\tfmov %S1,%S0";
6150 return "fmov %S1,%S0\n\tfmov %R1,%R0";
6153 return "fmov.d %1,%0";
6158 [(set_attr_alternative "length"
6159 [(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
6161 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
6162 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
6163 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
6165 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
6166 ;; We can't use 4-byte push/pop on SHcompact, so we have to
6167 ;; increment or decrement r15 explicitly.
6169 (match_test "TARGET_SHCOMPACT")
6170 (const_int 10) (const_int 8))
6172 (match_test "TARGET_SHCOMPACT")
6173 (const_int 10) (const_int 8))])
6174 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload")
6175 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
6176 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
6177 (const_string "double")
6178 (const_string "none")))])
6180 ;; Moving DFmode between fp/general registers through memory
6181 ;; (the top of the stack) is faster than moving through fpul even for
6182 ;; little endian. Because the type of an instruction is important for its
6183 ;; scheduling, it is beneficial to split these operations, rather than
6184 ;; emitting them in one single chunk, even if this will expose a stack
6185 ;; use that will prevent scheduling of other stack accesses beyond this
6188 [(set (match_operand:DF 0 "register_operand" "")
6189 (match_operand:DF 1 "register_operand" ""))
6190 (use (match_operand:PSI 2 "fpscr_operand" ""))
6191 (clobber (match_scratch:SI 3 "=X"))]
6192 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
6193 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
6199 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
6201 emit_move_insn (stack_pointer_rtx,
6202 plus_constant (stack_pointer_rtx, -8));
6203 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
6206 tos = gen_tmp_stack_mem (DFmode,
6207 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
6208 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
6209 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
6210 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6211 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
6212 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
6214 tos = gen_tmp_stack_mem (DFmode,
6215 gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
6216 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
6217 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
6218 emit_move_insn (stack_pointer_rtx, plus_constant (stack_pointer_rtx, 8));
6220 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6224 ;; local-alloc sometimes allocates scratch registers even when not required,
6225 ;; so we must be prepared to handle these.
6227 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
6229 [(set (match_operand:DF 0 "general_movdst_operand" "")
6230 (match_operand:DF 1 "general_movsrc_operand" ""))
6231 (use (match_operand:PSI 2 "fpscr_operand" ""))
6232 (clobber (match_scratch:SI 3 ""))]
6233 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
6235 && true_regnum (operands[0]) < 16
6236 && true_regnum (operands[1]) < 16"
6237 [(set (match_dup 0) (match_dup 1))]
6240 /* If this was a reg <-> mem operation with base + index reg addressing,
6241 we have to handle this in a special way. */
6242 rtx mem = operands[0];
6244 if (! memory_operand (mem, DFmode))
6249 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
6250 mem = SUBREG_REG (mem);
6253 rtx addr = XEXP (mem, 0);
6254 if (GET_CODE (addr) == PLUS
6255 && REG_P (XEXP (addr, 0))
6256 && REG_P (XEXP (addr, 1)))
6259 rtx reg0 = gen_rtx_REG (Pmode, 0);
6260 rtx regop = operands[store_p], word0 ,word1;
6262 if (GET_CODE (regop) == SUBREG)
6263 alter_subreg (®op);
6264 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
6268 mem = copy_rtx (mem);
6269 PUT_MODE (mem, SImode);
6270 word0 = gen_rtx_SUBREG (SImode, regop, 0);
6271 alter_subreg (&word0);
6272 word1 = gen_rtx_SUBREG (SImode, regop, 4);
6273 alter_subreg (&word1);
6274 if (store_p || ! refers_to_regno_p (REGNO (word0),
6275 REGNO (word0) + 1, addr, 0))
6278 ? gen_movsi_ie (mem, word0)
6279 : gen_movsi_ie (word0, mem));
6280 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
6281 mem = copy_rtx (mem);
6283 ? gen_movsi_ie (mem, word1)
6284 : gen_movsi_ie (word1, mem));
6285 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
6289 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
6290 emit_insn (gen_movsi_ie (word1, mem));
6291 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
6292 mem = copy_rtx (mem);
6293 emit_insn (gen_movsi_ie (word0, mem));
6300 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
6302 [(set (match_operand:DF 0 "register_operand" "")
6303 (match_operand:DF 1 "memory_operand" ""))
6304 (use (match_operand:PSI 2 "fpscr_operand" ""))
6305 (clobber (reg:SI R0_REG))]
6306 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
6307 [(parallel [(set (match_dup 0) (match_dup 1))
6309 (clobber (scratch:SI))])]
6312 (define_expand "reload_indf__frn"
6313 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
6314 (match_operand:DF 1 "immediate_operand" "FQ"))
6315 (use (reg:PSI FPSCR_REG))
6316 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6320 (define_expand "reload_outdf__RnFRm"
6321 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
6322 (match_operand:DF 1 "register_operand" "af,r"))
6323 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
6327 ;; Simplify no-op moves.
6329 [(set (match_operand:SF 0 "register_operand" "")
6330 (match_operand:SF 1 "register_operand" ""))
6331 (use (match_operand:PSI 2 "fpscr_operand" ""))
6332 (clobber (match_scratch:SI 3 ""))]
6333 "TARGET_SH2E && reload_completed
6334 && true_regnum (operands[0]) == true_regnum (operands[1])"
6335 [(set (match_dup 0) (match_dup 0))]
6338 ;; fmovd substitute post-reload splits
6340 [(set (match_operand:DF 0 "register_operand" "")
6341 (match_operand:DF 1 "register_operand" ""))
6342 (use (match_operand:PSI 2 "fpscr_operand" ""))
6343 (clobber (match_scratch:SI 3 ""))]
6344 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
6345 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
6346 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
6350 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
6351 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
6352 gen_rtx_REG (SFmode, src), operands[2]));
6353 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
6354 gen_rtx_REG (SFmode, src + 1), operands[2]));
6359 [(set (match_operand:DF 0 "register_operand" "")
6360 (mem:DF (match_operand:SI 1 "register_operand" "")))
6361 (use (match_operand:PSI 2 "fpscr_operand" ""))
6362 (clobber (match_scratch:SI 3 ""))]
6363 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
6364 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
6365 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
6369 int regno = true_regnum (operands[0]);
6371 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
6373 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
6374 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
6375 regno + !! TARGET_LITTLE_ENDIAN),
6376 mem2, operands[2]));
6377 add_reg_note (insn, REG_INC, operands[1]);
6378 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
6379 regno + ! TARGET_LITTLE_ENDIAN),
6380 change_address (mem, SFmode, NULL_RTX),
6386 [(set (match_operand:DF 0 "register_operand" "")
6387 (match_operand:DF 1 "memory_operand" ""))
6388 (use (match_operand:PSI 2 "fpscr_operand" ""))
6389 (clobber (match_scratch:SI 3 ""))]
6390 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
6391 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
6394 int regno = true_regnum (operands[0]);
6396 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
6397 rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
6398 rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
6400 operands[1] = copy_rtx (mem2);
6401 addr = XEXP (mem2, 0);
6403 switch (GET_CODE (addr))
6406 /* This is complicated. If the register is an arithmetic register
6407 we can just fall through to the REG+DISP case below. Otherwise
6408 we have to use a combination of POST_INC and REG addressing... */
6409 if (! arith_reg_operand (operands[1], SFmode))
6411 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
6412 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
6413 add_reg_note (insn, REG_INC, XEXP (addr, 0));
6415 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
6417 /* If we have modified the stack pointer, the value that we have
6418 read with post-increment might be modified by an interrupt,
6419 so write it back. */
6420 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
6421 emit_insn (gen_push_e (reg0));
6423 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0), GEN_INT (-4)));
6429 emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
6430 operands[1] = copy_rtx (operands[1]);
6431 XEXP (operands[1], 0) = plus_constant (addr, 4);
6432 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
6436 insn = emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
6437 add_reg_note (insn, REG_INC, XEXP (addr, 0));
6439 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
6440 add_reg_note (insn, REG_INC, XEXP (addr, 0));
6452 [(set (match_operand:DF 0 "memory_operand" "")
6453 (match_operand:DF 1 "register_operand" ""))
6454 (use (match_operand:PSI 2 "fpscr_operand" ""))
6455 (clobber (match_scratch:SI 3 ""))]
6456 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
6457 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
6460 int regno = true_regnum (operands[1]);
6462 rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
6463 rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
6465 operands[0] = copy_rtx (operands[0]);
6466 PUT_MODE (operands[0], SFmode);
6467 addr = XEXP (operands[0], 0);
6469 switch (GET_CODE (addr))
6472 /* This is complicated. If the register is an arithmetic register
6473 we can just fall through to the REG+DISP case below. Otherwise
6474 we have to use a combination of REG and PRE_DEC addressing... */
6475 if (! arith_reg_operand (operands[0], SFmode))
6477 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
6478 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
6480 operands[0] = copy_rtx (operands[0]);
6481 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
6483 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
6484 add_reg_note (insn, REG_INC, XEXP (addr, 0));
6490 /* Since REG+DISP addressing has already been decided upon by gcc
6491 we can rely upon it having chosen an arithmetic register as the
6492 register component of the address. Just emit the lower numbered
6493 register first, to the lower address, then the higher numbered
6494 register to the higher address. */
6495 emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
6497 operands[0] = copy_rtx (operands[0]);
6498 XEXP (operands[0], 0) = plus_constant (addr, 4);
6500 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
6504 /* This is easy. Output the word to go to the higher address
6505 first (ie the word in the higher numbered register) then the
6506 word to go to the lower address. */
6508 insn = emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
6509 add_reg_note (insn, REG_INC, XEXP (addr, 0));
6511 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
6512 add_reg_note (insn, REG_INC, XEXP (addr, 0));
6524 ;; If the output is a register and the input is memory or a register, we have
6525 ;; to be careful and see which word needs to be loaded first.
6528 [(set (match_operand:DF 0 "general_movdst_operand" "")
6529 (match_operand:DF 1 "general_movsrc_operand" ""))]
6530 "TARGET_SH1 && reload_completed"
6531 [(set (match_dup 2) (match_dup 3))
6532 (set (match_dup 4) (match_dup 5))]
6537 if ((MEM_P (operands[0])
6538 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
6539 || (MEM_P (operands[1])
6540 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
6543 switch (GET_CODE (operands[0]))
6546 regno = REGNO (operands[0]);
6549 regno = subreg_regno (operands[0]);
6559 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
6561 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
6562 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
6563 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
6564 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
6568 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
6569 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
6570 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
6571 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
6574 if (operands[2] == 0 || operands[3] == 0
6575 || operands[4] == 0 || operands[5] == 0)
6579 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
6580 ;; used only once, let combine add in the index again.
6583 [(set (match_operand:SI 0 "register_operand" "")
6584 (match_operand:SI 1 "" ""))
6585 (clobber (match_operand 2 "register_operand" ""))]
6586 "TARGET_SH1 && ! reload_in_progress && ! reload_completed
6587 && ALLOW_INDEXED_ADDRESS"
6588 [(use (reg:SI R0_REG))]
6591 rtx addr, reg, const_int;
6593 if (!MEM_P (operands[1]))
6595 addr = XEXP (operands[1], 0);
6596 if (GET_CODE (addr) != PLUS)
6598 reg = XEXP (addr, 0);
6599 const_int = XEXP (addr, 1);
6600 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
6601 && CONST_INT_P (const_int)))
6603 emit_move_insn (operands[2], const_int);
6604 emit_move_insn (operands[0],
6605 change_address (operands[1], VOIDmode,
6606 gen_rtx_PLUS (SImode, reg, operands[2])));
6611 [(set (match_operand:SI 1 "" "")
6612 (match_operand:SI 0 "register_operand" ""))
6613 (clobber (match_operand 2 "register_operand" ""))]
6614 "TARGET_SH1 && ! reload_in_progress && ! reload_completed
6615 && ALLOW_INDEXED_ADDRESS"
6616 [(use (reg:SI R0_REG))]
6619 rtx addr, reg, const_int;
6621 if (!MEM_P (operands[1]))
6623 addr = XEXP (operands[1], 0);
6624 if (GET_CODE (addr) != PLUS)
6626 reg = XEXP (addr, 0);
6627 const_int = XEXP (addr, 1);
6628 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
6629 && CONST_INT_P (const_int)))
6631 emit_move_insn (operands[2], const_int);
6632 emit_move_insn (change_address (operands[1], VOIDmode,
6633 gen_rtx_PLUS (SImode, reg, operands[2])),
6638 (define_expand "movdf"
6639 [(set (match_operand:DF 0 "general_movdst_operand" "")
6640 (match_operand:DF 1 "general_movsrc_operand" ""))]
6644 if (prepare_move_operands (operands, DFmode)) DONE;
6647 if (TARGET_SHMEDIA_FPU)
6648 emit_insn (gen_movdf_media (operands[0], operands[1]));
6650 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
6653 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
6655 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
6660 ;;This is incompatible with the way gcc uses subregs.
6661 ;;(define_insn "movv2sf_i"
6662 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
6663 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
6664 ;; "TARGET_SHMEDIA_FPU
6665 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
6666 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
6670 ;; fst%M0.p %m0, %1"
6671 ;; [(set_attr "type" "*,fload_media,fstore_media")])
6673 (define_insn_and_split "movv2sf_i"
6674 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
6675 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
6676 "TARGET_SHMEDIA_FPU"
6678 "TARGET_SHMEDIA_FPU && reload_completed"
6679 [(set (match_dup 0) (match_dup 1))]
6682 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
6683 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
6686 (define_expand "movv2sf"
6687 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
6688 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
6689 "TARGET_SHMEDIA_FPU"
6692 if (prepare_move_operands (operands, V2SFmode))
6696 (define_expand "addv2sf3"
6697 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
6698 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
6699 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
6700 "TARGET_SHMEDIA_FPU"
6703 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
6707 (define_expand "subv2sf3"
6708 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
6709 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
6710 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
6711 "TARGET_SHMEDIA_FPU"
6714 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
6718 (define_expand "mulv2sf3"
6719 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
6720 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
6721 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
6722 "TARGET_SHMEDIA_FPU"
6725 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
6729 (define_expand "divv2sf3"
6730 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
6731 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
6732 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
6733 "TARGET_SHMEDIA_FPU"
6736 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
6740 (define_insn_and_split "*movv4sf_i"
6741 [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
6742 (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
6743 "TARGET_SHMEDIA_FPU"
6745 "&& reload_completed"
6751 for (i = 0; i < 4/2; i++)
6755 if (MEM_P (operands[0]))
6756 x = adjust_address (operands[0], V2SFmode,
6757 i * GET_MODE_SIZE (V2SFmode));
6759 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
6761 if (MEM_P (operands[1]))
6762 y = adjust_address (operands[1], V2SFmode,
6763 i * GET_MODE_SIZE (V2SFmode));
6765 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
6767 emit_insn (gen_movv2sf_i (x, y));
6772 [(set_attr "length" "8")])
6774 (define_expand "movv4sf"
6775 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
6776 (match_operand:V4SF 1 "general_operand" ""))]
6777 "TARGET_SHMEDIA_FPU"
6780 if (prepare_move_operands (operands, V4SFmode))
6784 (define_insn_and_split "*movv16sf_i"
6785 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
6786 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
6787 "TARGET_SHMEDIA_FPU"
6789 "&& reload_completed"
6795 for (i = 0; i < 16/2; i++)
6799 if (MEM_P (operands[0]))
6800 x = adjust_address (operands[0], V2SFmode,
6801 i * GET_MODE_SIZE (V2SFmode));
6804 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
6808 if (MEM_P (operands[1]))
6809 y = adjust_address (operands[1], V2SFmode,
6810 i * GET_MODE_SIZE (V2SFmode));
6813 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
6817 emit_insn (gen_movv2sf_i (x, y));
6822 [(set_attr "length" "32")])
6824 (define_expand "movv16sf"
6825 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
6826 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
6827 "TARGET_SHMEDIA_FPU"
6830 if (prepare_move_operands (operands, V16SFmode))
6834 (define_insn "movsf_media"
6835 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
6836 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
6838 && (register_operand (operands[0], SFmode)
6839 || sh_register_operand (operands[1], SFmode))"
6850 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")
6851 (set (attr "highpart")
6852 (cond [(match_test "sh_contains_memref_p (insn)")
6853 (const_string "user")]
6854 (const_string "ignore")))])
6856 (define_insn "movsf_media_nofpu"
6857 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
6858 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
6860 && (register_operand (operands[0], SFmode)
6861 || sh_register_operand (operands[1], SFmode))"
6867 [(set_attr "type" "arith_media,*,load_media,store_media")
6868 (set (attr "highpart")
6869 (cond [(match_test "sh_contains_memref_p (insn)")
6870 (const_string "user")]
6871 (const_string "ignore")))])
6874 [(set (match_operand:SF 0 "arith_reg_dest" "")
6875 (match_operand:SF 1 "immediate_operand" ""))]
6876 "TARGET_SHMEDIA && reload_completed
6877 && ! FP_REGISTER_P (true_regnum (operands[0]))"
6878 [(set (match_dup 3) (match_dup 2))]
6882 REAL_VALUE_TYPE value;
6884 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
6885 REAL_VALUE_TO_TARGET_SINGLE (value, values);
6886 operands[2] = GEN_INT (values);
6888 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
6891 (define_insn "movsf_i"
6892 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
6893 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
6896 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
6897 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
6898 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
6899 && (arith_reg_operand (operands[0], SFmode)
6900 || arith_reg_operand (operands[1], SFmode))"
6909 [(set_attr "type" "move,move,pcload,load,store,move,move")])
6911 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
6912 ;; update_flow_info would not know where to put REG_EQUAL notes
6913 ;; when the destination changes mode.
6914 (define_insn "movsf_ie"
6915 [(set (match_operand:SF 0 "general_movdst_operand"
6916 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
6917 (match_operand:SF 1 "general_movsrc_operand"
6918 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
6919 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
6920 (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
6923 && (arith_reg_operand (operands[0], SFmode)
6924 || arith_reg_operand (operands[1], SFmode)
6925 || arith_reg_operand (operands[3], SImode)
6926 || (fpul_operand (operands[0], SFmode)
6927 && memory_operand (operands[1], SFmode)
6928 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
6929 || (fpul_operand (operands[1], SFmode)
6930 && memory_operand (operands[0], SFmode)
6931 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))"
6951 ! move optimized away"
6952 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6953 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6954 (set_attr_alternative "length"
6961 (match_test "TARGET_SH2A")
6962 (const_int 4) (const_int 2))
6964 (match_test "TARGET_SH2A")
6965 (const_int 4) (const_int 2))
6968 (match_test "TARGET_SH2A")
6969 (const_int 4) (const_int 2))
6971 (match_test "TARGET_SH2A")
6972 (const_int 4) (const_int 2))
6982 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
6983 (const_string "single")
6984 (const_string "single")))])
6987 [(set (match_operand:SF 0 "register_operand" "")
6988 (match_operand:SF 1 "register_operand" ""))
6989 (use (match_operand:PSI 2 "fpscr_operand" ""))
6990 (clobber (reg:SI FPUL_REG))]
6992 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
6994 (clobber (scratch:SI))])
6995 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
6997 (clobber (scratch:SI))])]
7000 (define_expand "movsf"
7001 [(set (match_operand:SF 0 "general_movdst_operand" "")
7002 (match_operand:SF 1 "general_movsrc_operand" ""))]
7006 if (prepare_move_operands (operands, SFmode))
7010 if (TARGET_SHMEDIA_FPU)
7011 emit_insn (gen_movsf_media (operands[0], operands[1]));
7013 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
7018 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
7023 (define_insn "mov_nop"
7024 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
7027 [(set_attr "length" "0")
7028 (set_attr "type" "nil")])
7030 (define_expand "reload_insf__frn"
7031 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
7032 (match_operand:SF 1 "immediate_operand" "FQ"))
7033 (use (reg:PSI FPSCR_REG))
7034 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
7038 (define_expand "reload_insi__i_fpul"
7039 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
7040 (match_operand:SI 1 "immediate_operand" "i"))
7041 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
7045 (define_expand "ptabs"
7046 [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))]
7050 if (!TARGET_PT_FIXED)
7052 rtx eq = operands[1];
7054 /* ??? For canonical RTL we really should remove any CONST from EQ
7055 before wrapping it in the AND, and finally wrap the EQ into a
7056 const if is constant. However, for reload we must expose the
7057 input register or symbolic constant, and we can't have
7058 different insn structures outside of the operands for different
7059 alternatives of the same pattern. */
7060 eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)),
7063 = (gen_rtx_IF_THEN_ELSE
7066 gen_rtx_MEM (PDImode, operands[1]),
7067 gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE,
7068 PDImode, operands[1])));
7072 ;; expanded by ptabs expander.
7073 (define_insn "*extendsipdi_media"
7074 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
7075 (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand"
7079 (mem:PDI (match_dup 1))
7080 (sign_extend:PDI (match_dup 1))))]
7081 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
7085 [(set_attr "type" "ptabs_media,pt_media")
7086 (set_attr "length" "4,*")])
7088 (define_insn "*truncdipdi_media"
7089 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
7090 (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand"
7094 (mem:PDI (match_dup 1))
7095 (truncate:PDI (match_dup 1))))]
7096 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
7100 [(set_attr "type" "ptabs_media,pt_media")
7101 (set_attr "length" "4,*")])
7103 (define_insn "*movsi_y"
7104 [(set (match_operand:SI 0 "register_operand" "=y,y")
7105 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
7106 (clobber (match_scratch:SI 2 "=&z,r"))]
7108 && (reload_in_progress || reload_completed)"
7110 [(set_attr "length" "4")
7111 (set_attr "type" "pcload,move")])
7114 [(set (match_operand:SI 0 "register_operand" "")
7115 (match_operand:SI 1 "immediate_operand" ""))
7116 (clobber (match_operand:SI 2 "register_operand" ""))]
7118 [(set (match_dup 2) (match_dup 1))
7119 (set (match_dup 0) (match_dup 2))]
7122 ;; ------------------------------------------------------------------------
7123 ;; Define the real conditional branch instructions.
7124 ;; ------------------------------------------------------------------------
7126 (define_insn "branch_true"
7127 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
7128 (label_ref (match_operand 0 "" ""))
7131 "* return output_branch (1, insn, operands);"
7132 [(set_attr "type" "cbranch")])
7134 (define_insn "branch_false"
7135 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
7136 (label_ref (match_operand 0 "" ""))
7139 "* return output_branch (0, insn, operands);"
7140 [(set_attr "type" "cbranch")])
7142 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
7143 ;; which destination is too far away.
7144 ;; The const_int_operand is distinct for each branch target; it avoids
7145 ;; unwanted matches with redundant_insn.
7146 (define_insn "block_branch_redirect"
7147 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
7150 [(set_attr "length" "0")])
7152 ;; This one has the additional purpose to record a possible scratch register
7153 ;; for the following branch.
7154 ;; ??? Unfortunately, just setting the scratch register is not good enough,
7155 ;; because the insn then might be deemed dead and deleted. And we can't
7156 ;; make the use in the jump insn explicit because that would disable
7157 ;; delay slot scheduling from the target.
7158 (define_insn "indirect_jump_scratch"
7159 [(set (match_operand:SI 0 "register_operand" "=r")
7160 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
7161 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
7164 [(set_attr "length" "0")])
7166 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
7167 ;; being pulled into the delay slot of a condbranch that has been made to
7168 ;; jump around the unconditional jump because it was out of range.
7169 (define_insn "stuff_delay_slot"
7171 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
7172 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
7175 [(set_attr "length" "0")
7176 (set_attr "cond_delay_slot" "yes")])
7178 ;; Conditional branch insns
7180 (define_expand "cbranchint4_media"
7182 (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator"
7183 [(match_operand 1 "" "")
7184 (match_operand 2 "" "")])
7185 (match_operand 3 "" "")
7190 enum machine_mode mode = GET_MODE (operands[1]);
7191 if (mode == VOIDmode)
7192 mode = GET_MODE (operands[2]);
7193 if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
7195 operands[1] = force_reg (mode, operands[1]);
7196 if (CONSTANT_P (operands[2])
7197 && (! satisfies_constraint_I06 (operands[2])))
7198 operands[2] = force_reg (mode, operands[2]);
7202 if (operands[1] != const0_rtx)
7203 operands[1] = force_reg (mode, operands[1]);
7204 if (operands[2] != const0_rtx)
7205 operands[2] = force_reg (mode, operands[2]);
7207 switch (GET_CODE (operands[0]))
7213 operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])),
7214 VOIDmode, operands[2], operands[1]);
7215 operands[1] = XEXP (operands[0], 0);
7216 operands[2] = XEXP (operands[0], 1);
7219 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
7220 VOIDmode, operands[1], operands[2]);
7223 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
7226 (define_expand "cbranchfp4_media"
7228 (if_then_else (match_operator 0 "sh_float_comparison_operator"
7229 [(match_operand 1 "" "")
7230 (match_operand 2 "" "")])
7231 (match_operand 3 "" "")
7236 rtx tmp = gen_reg_rtx (SImode);
7238 if (GET_CODE (operands[0]) == NE)
7239 cmp = gen_rtx_EQ (SImode, operands[1], operands[2]);
7241 cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode,
7242 operands[1], operands[2]);
7244 emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2]));
7246 if (GET_CODE (cmp) == GET_CODE (operands[0]))
7247 operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
7249 operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
7251 operands[2] = const0_rtx;
7252 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
7255 (define_insn "*beq_media_i"
7257 (if_then_else (match_operator 3 "equality_comparison_operator"
7258 [(match_operand:DI 1 "arith_reg_operand" "r,r")
7259 (match_operand:DI 2 "arith_operand" "r,I06")])
7260 (match_operand 0 "target_operand" "b,b")
7265 b%o3i%' %1, %2, %0%>"
7266 [(set_attr "type" "cbranch_media")])
7268 (define_insn "*beq_media_i32"
7270 (if_then_else (match_operator 3 "equality_comparison_operator"
7271 [(match_operand:SI 1 "arith_reg_operand" "r,r")
7272 (match_operand:SI 2 "arith_operand" "r,I06")])
7273 (match_operand 0 "target_operand" "b,b")
7278 b%o3i%' %1, %2, %0%>"
7279 [(set_attr "type" "cbranch_media")])
7281 (define_insn "*bgt_media_i"
7283 (if_then_else (match_operator 3 "greater_comparison_operator"
7284 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
7285 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
7286 (match_operand 0 "target_operand" "b")
7289 "b%o3%' %N1, %N2, %0%>"
7290 [(set_attr "type" "cbranch_media")])
7292 (define_insn "*bgt_media_i32"
7294 (if_then_else (match_operator 3 "greater_comparison_operator"
7295 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
7296 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
7297 (match_operand 0 "target_operand" "b")
7300 "b%o3%' %N1, %N2, %0%>"
7301 [(set_attr "type" "cbranch_media")])
7303 ;; These are only needed to make invert_jump() happy - otherwise, jump
7304 ;; optimization will be silently disabled.
7305 (define_insn "*blt_media_i"
7307 (if_then_else (match_operator 3 "less_comparison_operator"
7308 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
7309 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
7310 (match_operand 0 "target_operand" "b")
7313 "b%o3%' %N2, %N1, %0%>"
7314 [(set_attr "type" "cbranch_media")])
7316 (define_insn "*blt_media_i32"
7318 (if_then_else (match_operator 3 "less_comparison_operator"
7319 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
7320 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
7321 (match_operand 0 "target_operand" "b")
7324 "b%o3%' %N2, %N1, %0%>"
7325 [(set_attr "type" "cbranch_media")])
7327 ;; combiner splitter for test-and-branch on single bit in register. This
7328 ;; is endian dependent because the non-paradoxical subreg looks different
7333 (match_operator 3 "equality_comparison_operator"
7334 [(subreg:SI (zero_extract:DI (subreg:DI (match_operand:SI 1
7335 "extend_reg_operand" "")
7339 "const_int_operand" "")) 0)
7341 (match_operand 0 "target_operand" "")
7343 (clobber (match_operand:SI 4 "arith_reg_dest" ""))]
7344 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
7345 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5)))
7346 (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))]
7350 operands[5] = GEN_INT (31 - INTVAL (operands[2]));
7351 operands[6] = (GET_CODE (operands[3]) == EQ
7352 ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx)
7353 : gen_rtx_GT (VOIDmode, const0_rtx, operands[4]));
7356 ; operand 0 is the loop count pseudo register
7357 ; operand 1 is the number of loop iterations or 0 if it is unknown
7358 ; operand 2 is the maximum number of loop iterations
7359 ; operand 3 is the number of levels of enclosed loops
7360 ; operand 4 is the label to jump to at the top of the loop
7362 (define_expand "doloop_end"
7363 [(parallel [(set (pc) (if_then_else
7364 (ne:SI (match_operand:SI 0 "" "")
7366 (label_ref (match_operand 4 "" ""))
7369 (plus:SI (match_dup 0) (const_int -1)))
7370 (clobber (reg:SI T_REG))])]
7374 if (GET_MODE (operands[0]) != SImode)
7379 (define_insn_and_split "doloop_end_split"
7381 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
7383 (label_ref (match_operand 1 "" ""))
7385 (set (match_operand:SI 0 "arith_reg_dest" "=r")
7386 (plus (match_dup 2) (const_int -1)))
7387 (clobber (reg:SI T_REG))]
7391 [(parallel [(set (reg:SI T_REG)
7392 (eq:SI (match_dup 2) (const_int 1)))
7393 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
7394 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
7395 (label_ref (match_dup 1))
7398 [(set_attr "type" "cbranch")])
7401 ;; ------------------------------------------------------------------------
7402 ;; Jump and linkage insns
7403 ;; ------------------------------------------------------------------------
7405 (define_insn "jump_compact"
7407 (label_ref (match_operand 0 "" "")))]
7408 "TARGET_SH1 && !find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)"
7411 /* The length is 16 if the delay slot is unfilled. */
7412 if (get_attr_length(insn) > 4)
7413 return output_far_jump(insn, operands[0]);
7415 return \"bra %l0%#\";
7417 [(set_attr "type" "jump")
7418 (set_attr "needs_delay_slot" "yes")])
7420 ;; ??? It would be much saner to explicitly use the scratch register
7421 ;; in the jump insn, and have indirect_jump_scratch only set it,
7422 ;; but fill_simple_delay_slots would refuse to do delay slot filling
7423 ;; from the target then, as it uses simplejump_p.
7424 ;;(define_insn "jump_compact_far"
7426 ;; (label_ref (match_operand 0 "" "")))
7427 ;; (use (match_operand 1 "register_operand" "r")]
7429 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
7430 ;; [(set_attr "type" "jump")
7431 ;; (set_attr "needs_delay_slot" "yes")])
7433 (define_insn "jump_media"
7435 (match_operand 0 "target_operand" "b"))]
7438 [(set_attr "type" "jump_media")])
7440 (define_expand "jump"
7442 (label_ref (match_operand 0 "" "")))]
7447 emit_jump_insn (gen_jump_compact (operands[0]));
7448 else if (TARGET_SHMEDIA)
7450 if (reload_in_progress || reload_completed)
7452 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode,
7458 (define_insn "force_mode_for_call"
7459 [(use (reg:PSI FPSCR_REG))]
7462 [(set_attr "length" "0")
7463 (set (attr "fp_mode")
7464 (if_then_else (eq_attr "fpu_single" "yes")
7465 (const_string "single") (const_string "double")))])
7467 (define_insn "calli"
7468 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
7469 (match_operand 1 "" ""))
7470 (use (reg:PSI FPSCR_REG))
7471 (clobber (reg:SI PR_REG))]
7475 if (TARGET_SH2A && (dbr_sequence_length () == 0))
7476 return \"jsr/n\\t@%0\";
7478 return \"jsr\\t@%0%#\";
7481 [(set_attr "type" "call")
7482 (set (attr "fp_mode")
7483 (if_then_else (eq_attr "fpu_single" "yes")
7484 (const_string "single") (const_string "double")))
7485 (set_attr "needs_delay_slot" "yes")
7486 (set_attr "fp_set" "unknown")])
7488 ;; This is TBR relative jump instruction for SH2A architecture.
7489 ;; Its use is enabled assigning an attribute "function_vector"
7490 ;; and the vector number to a function during its declaration.
7492 (define_insn "calli_tbr_rel"
7493 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
7494 (match_operand 1 "" ""))
7495 (use (reg:PSI FPSCR_REG))
7496 (clobber (reg:SI PR_REG))]
7497 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
7500 unsigned HOST_WIDE_INT vect_num;
7501 vect_num = sh2a_get_function_vector_number (operands[0]);
7502 operands[2] = GEN_INT (vect_num * 4);
7504 return \"jsr/n\\t@@(%O2,tbr)\";
7506 [(set_attr "type" "call")
7507 (set (attr "fp_mode")
7508 (if_then_else (eq_attr "fpu_single" "yes")
7509 (const_string "single") (const_string "double")))
7510 (set_attr "needs_delay_slot" "no")
7511 (set_attr "fp_set" "unknown")])
7513 ;; This is a pc-rel call, using bsrf, for use with PIC.
7515 (define_insn "calli_pcrel"
7516 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
7517 (match_operand 1 "" ""))
7518 (use (reg:PSI FPSCR_REG))
7519 (use (reg:SI PIC_REG))
7520 (use (match_operand 2 "" ""))
7521 (clobber (reg:SI PR_REG))]
7524 [(set_attr "type" "call")
7525 (set (attr "fp_mode")
7526 (if_then_else (eq_attr "fpu_single" "yes")
7527 (const_string "single") (const_string "double")))
7528 (set_attr "needs_delay_slot" "yes")
7529 (set_attr "fp_set" "unknown")])
7531 (define_insn_and_split "call_pcrel"
7532 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
7533 (match_operand 1 "" ""))
7534 (use (reg:PSI FPSCR_REG))
7535 (use (reg:SI PIC_REG))
7536 (clobber (reg:SI PR_REG))
7537 (clobber (match_scratch:SI 2 "=r"))]
7544 rtx lab = PATTERN (gen_call_site ());
7546 if (SYMBOL_REF_LOCAL_P (operands[0]))
7547 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
7549 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
7550 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
7553 [(set_attr "type" "call")
7554 (set (attr "fp_mode")
7555 (if_then_else (eq_attr "fpu_single" "yes")
7556 (const_string "single") (const_string "double")))
7557 (set_attr "needs_delay_slot" "yes")
7558 (set_attr "fp_set" "unknown")])
7560 (define_insn "call_compact"
7561 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
7562 (match_operand 1 "" ""))
7563 (match_operand 2 "immediate_operand" "n")
7564 (use (reg:SI R0_REG))
7565 (use (reg:SI R1_REG))
7566 (use (reg:PSI FPSCR_REG))
7567 (clobber (reg:SI PR_REG))]
7568 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
7570 [(set_attr "type" "call")
7571 (set (attr "fp_mode")
7572 (if_then_else (eq_attr "fpu_single" "yes")
7573 (const_string "single") (const_string "double")))
7574 (set_attr "needs_delay_slot" "yes")])
7576 (define_insn "call_compact_rettramp"
7577 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
7578 (match_operand 1 "" ""))
7579 (match_operand 2 "immediate_operand" "n")
7580 (use (reg:SI R0_REG))
7581 (use (reg:SI R1_REG))
7582 (use (reg:PSI FPSCR_REG))
7583 (clobber (reg:SI R10_REG))
7584 (clobber (reg:SI PR_REG))]
7585 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
7587 [(set_attr "type" "call")
7588 (set (attr "fp_mode")
7589 (if_then_else (eq_attr "fpu_single" "yes")
7590 (const_string "single") (const_string "double")))
7591 (set_attr "needs_delay_slot" "yes")])
7593 (define_insn "call_media"
7594 [(call (mem:DI (match_operand 0 "target_reg_operand" "b"))
7595 (match_operand 1 "" ""))
7596 (clobber (reg:DI PR_MEDIA_REG))]
7599 [(set_attr "type" "jump_media")])
7601 (define_insn "call_valuei"
7602 [(set (match_operand 0 "" "=rf")
7603 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
7604 (match_operand 2 "" "")))
7605 (use (reg:PSI FPSCR_REG))
7606 (clobber (reg:SI PR_REG))]
7610 if (TARGET_SH2A && (dbr_sequence_length () == 0))
7611 return \"jsr/n\\t@%1\";
7613 return \"jsr\\t@%1%#\";
7615 [(set_attr "type" "call")
7616 (set (attr "fp_mode")
7617 (if_then_else (eq_attr "fpu_single" "yes")
7618 (const_string "single") (const_string "double")))
7619 (set_attr "needs_delay_slot" "yes")
7620 (set_attr "fp_set" "unknown")])
7622 ;; This is TBR relative jump instruction for SH2A architecture.
7623 ;; Its use is enabled by assigning an attribute "function_vector"
7624 ;; and the vector number to a function during its declaration.
7626 (define_insn "call_valuei_tbr_rel"
7627 [(set (match_operand 0 "" "=rf")
7628 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
7629 (match_operand 2 "" "")))
7630 (use (reg:PSI FPSCR_REG))
7631 (clobber (reg:SI PR_REG))]
7632 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
7635 unsigned HOST_WIDE_INT vect_num;
7636 vect_num = sh2a_get_function_vector_number (operands[1]);
7637 operands[3] = GEN_INT (vect_num * 4);
7639 return \"jsr/n\\t@@(%O3,tbr)\";
7641 [(set_attr "type" "call")
7642 (set (attr "fp_mode")
7643 (if_then_else (eq_attr "fpu_single" "yes")
7644 (const_string "single") (const_string "double")))
7645 (set_attr "needs_delay_slot" "no")
7646 (set_attr "fp_set" "unknown")])
7648 (define_insn "call_valuei_pcrel"
7649 [(set (match_operand 0 "" "=rf")
7650 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
7651 (match_operand 2 "" "")))
7652 (use (reg:PSI FPSCR_REG))
7653 (use (reg:SI PIC_REG))
7654 (use (match_operand 3 "" ""))
7655 (clobber (reg:SI PR_REG))]
7658 [(set_attr "type" "call")
7659 (set (attr "fp_mode")
7660 (if_then_else (eq_attr "fpu_single" "yes")
7661 (const_string "single") (const_string "double")))
7662 (set_attr "needs_delay_slot" "yes")
7663 (set_attr "fp_set" "unknown")])
7665 (define_insn_and_split "call_value_pcrel"
7666 [(set (match_operand 0 "" "=rf")
7667 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
7668 (match_operand 2 "" "")))
7669 (use (reg:PSI FPSCR_REG))
7670 (use (reg:SI PIC_REG))
7671 (clobber (reg:SI PR_REG))
7672 (clobber (match_scratch:SI 3 "=r"))]
7679 rtx lab = PATTERN (gen_call_site ());
7681 if (SYMBOL_REF_LOCAL_P (operands[1]))
7682 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
7684 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
7685 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
7686 operands[2], copy_rtx (lab)));
7689 [(set_attr "type" "call")
7690 (set (attr "fp_mode")
7691 (if_then_else (eq_attr "fpu_single" "yes")
7692 (const_string "single") (const_string "double")))
7693 (set_attr "needs_delay_slot" "yes")
7694 (set_attr "fp_set" "unknown")])
7696 (define_insn "call_value_compact"
7697 [(set (match_operand 0 "" "=rf")
7698 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
7699 (match_operand 2 "" "")))
7700 (match_operand 3 "immediate_operand" "n")
7701 (use (reg:SI R0_REG))
7702 (use (reg:SI R1_REG))
7703 (use (reg:PSI FPSCR_REG))
7704 (clobber (reg:SI PR_REG))]
7705 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
7707 [(set_attr "type" "call")
7708 (set (attr "fp_mode")
7709 (if_then_else (eq_attr "fpu_single" "yes")
7710 (const_string "single") (const_string "double")))
7711 (set_attr "needs_delay_slot" "yes")])
7713 (define_insn "call_value_compact_rettramp"
7714 [(set (match_operand 0 "" "=rf")
7715 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
7716 (match_operand 2 "" "")))
7717 (match_operand 3 "immediate_operand" "n")
7718 (use (reg:SI R0_REG))
7719 (use (reg:SI R1_REG))
7720 (use (reg:PSI FPSCR_REG))
7721 (clobber (reg:SI R10_REG))
7722 (clobber (reg:SI PR_REG))]
7723 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
7725 [(set_attr "type" "call")
7726 (set (attr "fp_mode")
7727 (if_then_else (eq_attr "fpu_single" "yes")
7728 (const_string "single") (const_string "double")))
7729 (set_attr "needs_delay_slot" "yes")])
7731 (define_insn "call_value_media"
7732 [(set (match_operand 0 "" "=rf")
7733 (call (mem:DI (match_operand 1 "target_reg_operand" "b"))
7734 (match_operand 2 "" "")))
7735 (clobber (reg:DI PR_MEDIA_REG))]
7738 [(set_attr "type" "jump_media")])
7740 (define_expand "call"
7741 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
7742 (match_operand 1 "" ""))
7743 (match_operand 2 "" "")
7744 (use (reg:PSI FPSCR_REG))
7745 (clobber (reg:SI PR_REG))])]
7751 operands[0] = shmedia_prepare_call_address (operands[0], 0);
7752 emit_call_insn (gen_call_media (operands[0], operands[1]));
7755 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
7757 rtx cookie_rtx = operands[2];
7758 long cookie = INTVAL (cookie_rtx);
7759 rtx func = XEXP (operands[0], 0);
7764 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
7766 rtx reg = gen_reg_rtx (Pmode);
7768 emit_insn (gen_symGOTPLT2reg (reg, func));
7772 func = legitimize_pic_address (func, Pmode, 0);
7775 r0 = gen_rtx_REG (SImode, R0_REG);
7776 r1 = gen_rtx_REG (SImode, R1_REG);
7778 /* Since such a call function may use all call-clobbered
7779 registers, we force a mode switch earlier, so that we don't
7780 run out of registers when adjusting fpscr for the call. */
7781 emit_insn (gen_force_mode_for_call ());
7784 = function_symbol (NULL, \"__GCC_shcompact_call_trampoline\",
7786 operands[0] = force_reg (SImode, operands[0]);
7788 emit_move_insn (r0, func);
7789 emit_move_insn (r1, cookie_rtx);
7791 if (cookie & CALL_COOKIE_RET_TRAMP (1))
7792 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
7795 emit_call_insn (gen_call_compact (operands[0], operands[1],
7800 else if (TARGET_SHCOMPACT && flag_pic
7801 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
7802 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
7804 rtx reg = gen_reg_rtx (Pmode);
7806 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
7807 XEXP (operands[0], 0) = reg;
7809 if (!flag_pic && TARGET_SH2A
7810 && MEM_P (operands[0])
7811 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
7813 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
7815 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
7820 if (flag_pic && TARGET_SH2
7821 && MEM_P (operands[0])
7822 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
7824 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
7829 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
7830 operands[1] = operands[2];
7833 emit_call_insn (gen_calli (operands[0], operands[1]));
7837 (define_insn "call_pop_compact"
7838 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
7839 (match_operand 1 "" ""))
7840 (match_operand 2 "immediate_operand" "n")
7841 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7842 (match_operand 3 "immediate_operand" "n")))
7843 (use (reg:SI R0_REG))
7844 (use (reg:SI R1_REG))
7845 (use (reg:PSI FPSCR_REG))
7846 (clobber (reg:SI PR_REG))]
7847 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
7849 [(set_attr "type" "call")
7850 (set (attr "fp_mode")
7851 (if_then_else (eq_attr "fpu_single" "yes")
7852 (const_string "single") (const_string "double")))
7853 (set_attr "needs_delay_slot" "yes")])
7855 (define_insn "call_pop_compact_rettramp"
7856 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
7857 (match_operand 1 "" ""))
7858 (match_operand 2 "immediate_operand" "n")
7859 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7860 (match_operand 3 "immediate_operand" "n")))
7861 (use (reg:SI R0_REG))
7862 (use (reg:SI R1_REG))
7863 (use (reg:PSI FPSCR_REG))
7864 (clobber (reg:SI R10_REG))
7865 (clobber (reg:SI PR_REG))]
7866 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
7868 [(set_attr "type" "call")
7869 (set (attr "fp_mode")
7870 (if_then_else (eq_attr "fpu_single" "yes")
7871 (const_string "single") (const_string "double")))
7872 (set_attr "needs_delay_slot" "yes")])
7874 (define_expand "call_pop"
7875 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
7876 (match_operand 1 "" ""))
7877 (match_operand 2 "" "")
7878 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7879 (match_operand 3 "" "")))])]
7888 gcc_assert (operands[2] && INTVAL (operands[2]));
7889 cookie_rtx = operands[2];
7890 cookie = INTVAL (cookie_rtx);
7891 func = XEXP (operands[0], 0);
7895 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
7897 rtx reg = gen_reg_rtx (Pmode);
7898 emit_insn (gen_symGOTPLT2reg (reg, func));
7902 func = legitimize_pic_address (func, Pmode, 0);
7905 r0 = gen_rtx_REG (SImode, R0_REG);
7906 r1 = gen_rtx_REG (SImode, R1_REG);
7908 /* Since such a call function may use all call-clobbered
7909 registers, we force a mode switch earlier, so that we don't
7910 run out of registers when adjusting fpscr for the call. */
7911 emit_insn (gen_force_mode_for_call ());
7913 operands[0] = function_symbol (NULL, \"__GCC_shcompact_call_trampoline\",
7915 operands[0] = force_reg (SImode, operands[0]);
7917 emit_move_insn (r0, func);
7918 emit_move_insn (r1, cookie_rtx);
7920 if (cookie & CALL_COOKIE_RET_TRAMP (1))
7921 emit_call_insn (gen_call_pop_compact_rettramp
7922 (operands[0], operands[1], operands[2], operands[3]));
7924 emit_call_insn (gen_call_pop_compact
7925 (operands[0], operands[1], operands[2], operands[3]));
7930 (define_expand "call_value"
7931 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
7932 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
7933 (match_operand 2 "" "")))
7934 (match_operand 3 "" "")
7935 (use (reg:PSI FPSCR_REG))
7936 (clobber (reg:SI PR_REG))])]
7942 operands[1] = shmedia_prepare_call_address (operands[1], 0);
7943 emit_call_insn (gen_call_value_media (operands[0], operands[1],
7947 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
7949 rtx cookie_rtx = operands[3];
7950 long cookie = INTVAL (cookie_rtx);
7951 rtx func = XEXP (operands[1], 0);
7956 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
7958 rtx reg = gen_reg_rtx (Pmode);
7960 emit_insn (gen_symGOTPLT2reg (reg, func));
7964 func = legitimize_pic_address (func, Pmode, 0);
7967 r0 = gen_rtx_REG (SImode, R0_REG);
7968 r1 = gen_rtx_REG (SImode, R1_REG);
7970 /* Since such a call function may use all call-clobbered
7971 registers, we force a mode switch earlier, so that we don't
7972 run out of registers when adjusting fpscr for the call. */
7973 emit_insn (gen_force_mode_for_call ());
7976 = function_symbol (NULL, \"__GCC_shcompact_call_trampoline\",
7978 operands[1] = force_reg (SImode, operands[1]);
7980 emit_move_insn (r0, func);
7981 emit_move_insn (r1, cookie_rtx);
7983 if (cookie & CALL_COOKIE_RET_TRAMP (1))
7984 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
7989 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
7990 operands[2], operands[3]));
7994 else if (TARGET_SHCOMPACT && flag_pic
7995 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7996 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
7998 rtx reg = gen_reg_rtx (Pmode);
8000 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
8001 XEXP (operands[1], 0) = reg;
8003 if (!flag_pic && TARGET_SH2A
8004 && MEM_P (operands[1])
8005 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
8007 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
8009 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
8010 XEXP (operands[1], 0), operands[2]));
8014 if (flag_pic && TARGET_SH2
8015 && MEM_P (operands[1])
8016 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
8018 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
8023 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
8025 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
8029 (define_insn "sibcalli"
8030 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
8031 (match_operand 1 "" ""))
8032 (use (reg:PSI FPSCR_REG))
8036 [(set_attr "needs_delay_slot" "yes")
8037 (set (attr "fp_mode")
8038 (if_then_else (eq_attr "fpu_single" "yes")
8039 (const_string "single") (const_string "double")))
8040 (set_attr "type" "jump_ind")])
8042 (define_insn "sibcalli_pcrel"
8043 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
8044 (match_operand 1 "" ""))
8045 (use (match_operand 2 "" ""))
8046 (use (reg:PSI FPSCR_REG))
8050 [(set_attr "needs_delay_slot" "yes")
8051 (set (attr "fp_mode")
8052 (if_then_else (eq_attr "fpu_single" "yes")
8053 (const_string "single") (const_string "double")))
8054 (set_attr "type" "jump_ind")])
8056 ;; This uses an unspec to describe that the symbol_ref is very close.
8057 (define_insn "sibcalli_thunk"
8058 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
8060 (match_operand 1 "" ""))
8061 (use (reg:PSI FPSCR_REG))
8065 [(set_attr "needs_delay_slot" "yes")
8066 (set (attr "fp_mode")
8067 (if_then_else (eq_attr "fpu_single" "yes")
8068 (const_string "single") (const_string "double")))
8069 (set_attr "type" "jump")
8070 (set_attr "length" "2")])
8072 (define_insn_and_split "sibcall_pcrel"
8073 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
8074 (match_operand 1 "" ""))
8075 (use (reg:PSI FPSCR_REG))
8076 (clobber (match_scratch:SI 2 "=k"))
8084 rtx lab = PATTERN (gen_call_site ());
8087 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
8088 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
8090 SIBLING_CALL_P (call_insn) = 1;
8093 [(set_attr "needs_delay_slot" "yes")
8094 (set (attr "fp_mode")
8095 (if_then_else (eq_attr "fpu_single" "yes")
8096 (const_string "single") (const_string "double")))
8097 (set_attr "type" "jump_ind")])
8099 (define_insn "sibcall_compact"
8100 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
8101 (match_operand 1 "" ""))
8103 (use (match_operand:SI 2 "register_operand" "z,x"))
8104 (use (reg:SI R1_REG))
8105 (use (reg:PSI FPSCR_REG))
8106 ;; We want to make sure the `x' above will only match MACH_REG
8107 ;; because sibcall_epilogue may clobber MACL_REG.
8108 (clobber (reg:SI MACL_REG))]
8112 jmp @%0\\n sts %2, r0"
8113 [(set_attr "needs_delay_slot" "yes,no")
8114 (set_attr "length" "2,4")
8115 (set (attr "fp_mode") (const_string "single"))
8116 (set_attr "type" "jump_ind")])
8118 (define_insn "sibcall_media"
8119 [(call (mem:DI (match_operand 0 "target_reg_operand" "k"))
8120 (match_operand 1 "" ""))
8121 (use (reg:SI PR_MEDIA_REG))
8125 [(set_attr "type" "jump_media")])
8127 (define_expand "sibcall"
8129 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
8130 (match_operand 1 "" ""))
8131 (match_operand 2 "" "")
8132 (use (reg:PSI FPSCR_REG))
8139 operands[0] = shmedia_prepare_call_address (operands[0], 1);
8140 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
8143 else if (TARGET_SHCOMPACT && operands[2]
8144 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
8146 rtx cookie_rtx = operands[2];
8147 long cookie = INTVAL (cookie_rtx);
8148 rtx func = XEXP (operands[0], 0);
8153 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
8155 rtx reg = gen_reg_rtx (Pmode);
8157 emit_insn (gen_symGOT2reg (reg, func));
8161 func = legitimize_pic_address (func, Pmode, 0);
8164 /* FIXME: if we could tell whether all argument registers are
8165 already taken, we could decide whether to force the use of
8166 MACH_REG or to stick to R0_REG. Unfortunately, there's no
8167 simple way to tell. We could use the CALL_COOKIE, but we
8168 can't currently tell a register used for regular argument
8169 passing from one that is unused. If we leave it up to reload
8170 to decide which register to use, it seems to always choose
8171 R0_REG, which leaves no available registers in SIBCALL_REGS
8172 to hold the address of the trampoline. */
8173 mach = gen_rtx_REG (SImode, MACH_REG);
8174 r1 = gen_rtx_REG (SImode, R1_REG);
8176 /* Since such a call function may use all call-clobbered
8177 registers, we force a mode switch earlier, so that we don't
8178 run out of registers when adjusting fpscr for the call. */
8179 emit_insn (gen_force_mode_for_call ());
8182 = function_symbol (NULL, \"__GCC_shcompact_call_trampoline\",
8184 operands[0] = force_reg (SImode, operands[0]);
8186 /* We don't need a return trampoline, since the callee will
8187 return directly to the upper caller. */
8188 if (cookie & CALL_COOKIE_RET_TRAMP (1))
8190 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
8191 cookie_rtx = GEN_INT (cookie);
8194 emit_move_insn (mach, func);
8195 emit_move_insn (r1, cookie_rtx);
8197 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
8200 else if (TARGET_SHCOMPACT && flag_pic
8201 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
8202 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
8204 rtx reg = gen_reg_rtx (Pmode);
8206 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
8207 XEXP (operands[0], 0) = reg;
8209 if (flag_pic && TARGET_SH2
8210 && MEM_P (operands[0])
8211 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
8212 /* The PLT needs the PIC register, but the epilogue would have
8213 to restore it, so we can only use PC-relative PIC calls for
8214 static functions. */
8215 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
8217 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
8221 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
8223 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
8227 (define_insn "sibcall_valuei"
8228 [(set (match_operand 0 "" "=rf")
8229 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
8230 (match_operand 2 "" "")))
8231 (use (reg:PSI FPSCR_REG))
8235 [(set_attr "needs_delay_slot" "yes")
8236 (set (attr "fp_mode")
8237 (if_then_else (eq_attr "fpu_single" "yes")
8238 (const_string "single") (const_string "double")))
8239 (set_attr "type" "jump_ind")])
8241 (define_insn "sibcall_valuei_pcrel"
8242 [(set (match_operand 0 "" "=rf")
8243 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
8244 (match_operand 2 "" "")))
8245 (use (match_operand 3 "" ""))
8246 (use (reg:PSI FPSCR_REG))
8250 [(set_attr "needs_delay_slot" "yes")
8251 (set (attr "fp_mode")
8252 (if_then_else (eq_attr "fpu_single" "yes")
8253 (const_string "single") (const_string "double")))
8254 (set_attr "type" "jump_ind")])
8256 (define_insn_and_split "sibcall_value_pcrel"
8257 [(set (match_operand 0 "" "=rf")
8258 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
8259 (match_operand 2 "" "")))
8260 (use (reg:PSI FPSCR_REG))
8261 (clobber (match_scratch:SI 3 "=k"))
8269 rtx lab = PATTERN (gen_call_site ());
8272 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
8273 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
8277 SIBLING_CALL_P (call_insn) = 1;
8280 [(set_attr "needs_delay_slot" "yes")
8281 (set (attr "fp_mode")
8282 (if_then_else (eq_attr "fpu_single" "yes")
8283 (const_string "single") (const_string "double")))
8284 (set_attr "type" "jump_ind")])
8286 (define_insn "sibcall_value_compact"
8287 [(set (match_operand 0 "" "=rf,rf")
8288 (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
8289 (match_operand 2 "" "")))
8291 (use (match_operand:SI 3 "register_operand" "z,x"))
8292 (use (reg:SI R1_REG))
8293 (use (reg:PSI FPSCR_REG))
8294 ;; We want to make sure the `x' above will only match MACH_REG
8295 ;; because sibcall_epilogue may clobber MACL_REG.
8296 (clobber (reg:SI MACL_REG))]
8300 jmp @%1\\n sts %3, r0"
8301 [(set_attr "needs_delay_slot" "yes,no")
8302 (set_attr "length" "2,4")
8303 (set (attr "fp_mode") (const_string "single"))
8304 (set_attr "type" "jump_ind")])
8306 (define_insn "sibcall_value_media"
8307 [(set (match_operand 0 "" "=rf")
8308 (call (mem:DI (match_operand 1 "target_reg_operand" "k"))
8309 (match_operand 2 "" "")))
8310 (use (reg:SI PR_MEDIA_REG))
8314 [(set_attr "type" "jump_media")])
8316 (define_expand "sibcall_value"
8318 [(set (match_operand 0 "arith_reg_operand" "")
8319 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
8320 (match_operand 2 "" "")))
8321 (match_operand 3 "" "")
8322 (use (reg:PSI FPSCR_REG))
8329 operands[1] = shmedia_prepare_call_address (operands[1], 1);
8330 emit_call_insn (gen_sibcall_value_media (operands[0], operands[1],
8334 else if (TARGET_SHCOMPACT && operands[3]
8335 && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1)))
8337 rtx cookie_rtx = operands[3];
8338 long cookie = INTVAL (cookie_rtx);
8339 rtx func = XEXP (operands[1], 0);
8344 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
8346 rtx reg = gen_reg_rtx (Pmode);
8348 emit_insn (gen_symGOT2reg (reg, func));
8352 func = legitimize_pic_address (func, Pmode, 0);
8355 /* FIXME: if we could tell whether all argument registers are
8356 already taken, we could decide whether to force the use of
8357 MACH_REG or to stick to R0_REG. Unfortunately, there's no
8358 simple way to tell. We could use the CALL_COOKIE, but we
8359 can't currently tell a register used for regular argument
8360 passing from one that is unused. If we leave it up to reload
8361 to decide which register to use, it seems to always choose
8362 R0_REG, which leaves no available registers in SIBCALL_REGS
8363 to hold the address of the trampoline. */
8364 mach = gen_rtx_REG (SImode, MACH_REG);
8365 r1 = gen_rtx_REG (SImode, R1_REG);
8367 /* Since such a call function may use all call-clobbered
8368 registers, we force a mode switch earlier, so that we don't
8369 run out of registers when adjusting fpscr for the call. */
8370 emit_insn (gen_force_mode_for_call ());
8373 = function_symbol (NULL, \"__GCC_shcompact_call_trampoline\",
8375 operands[1] = force_reg (SImode, operands[1]);
8377 /* We don't need a return trampoline, since the callee will
8378 return directly to the upper caller. */
8379 if (cookie & CALL_COOKIE_RET_TRAMP (1))
8381 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
8382 cookie_rtx = GEN_INT (cookie);
8385 emit_move_insn (mach, func);
8386 emit_move_insn (r1, cookie_rtx);
8388 emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1],
8389 operands[2], mach));
8392 else if (TARGET_SHCOMPACT && flag_pic
8393 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
8394 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
8396 rtx reg = gen_reg_rtx (Pmode);
8398 emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0)));
8399 XEXP (operands[1], 0) = reg;
8401 if (flag_pic && TARGET_SH2
8402 && MEM_P (operands[1])
8403 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
8404 /* The PLT needs the PIC register, but the epilogue would have
8405 to restore it, so we can only use PC-relative PIC calls for
8406 static functions. */
8407 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
8409 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
8410 XEXP (operands[1], 0),
8415 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
8417 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
8421 (define_insn "call_value_pop_compact"
8422 [(set (match_operand 0 "" "=rf")
8423 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
8424 (match_operand 2 "" "")))
8425 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
8426 (match_operand 4 "immediate_operand" "n")))
8427 (match_operand 3 "immediate_operand" "n")
8428 (use (reg:SI R0_REG))
8429 (use (reg:SI R1_REG))
8430 (use (reg:PSI FPSCR_REG))
8431 (clobber (reg:SI PR_REG))]
8432 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
8434 [(set_attr "type" "call")
8435 (set (attr "fp_mode")
8436 (if_then_else (eq_attr "fpu_single" "yes")
8437 (const_string "single") (const_string "double")))
8438 (set_attr "needs_delay_slot" "yes")])
8440 (define_insn "call_value_pop_compact_rettramp"
8441 [(set (match_operand 0 "" "=rf")
8442 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
8443 (match_operand 2 "" "")))
8444 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
8445 (match_operand 4 "immediate_operand" "n")))
8446 (match_operand 3 "immediate_operand" "n")
8447 (use (reg:SI R0_REG))
8448 (use (reg:SI R1_REG))
8449 (use (reg:PSI FPSCR_REG))
8450 (clobber (reg:SI R10_REG))
8451 (clobber (reg:SI PR_REG))]
8452 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
8454 [(set_attr "type" "call")
8455 (set (attr "fp_mode")
8456 (if_then_else (eq_attr "fpu_single" "yes")
8457 (const_string "single") (const_string "double")))
8458 (set_attr "needs_delay_slot" "yes")])
8460 (define_expand "call_value_pop"
8461 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
8462 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
8463 (match_operand 2 "" "")))
8464 (match_operand 3 "" "")
8465 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
8466 (match_operand 4 "" "")))])]
8475 gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]));
8476 cookie_rtx = operands[3];
8477 cookie = INTVAL (cookie_rtx);
8478 func = XEXP (operands[1], 0);
8482 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
8484 rtx reg = gen_reg_rtx (Pmode);
8486 emit_insn (gen_symGOTPLT2reg (reg, func));
8490 func = legitimize_pic_address (func, Pmode, 0);
8493 r0 = gen_rtx_REG (SImode, R0_REG);
8494 r1 = gen_rtx_REG (SImode, R1_REG);
8496 /* Since such a call function may use all call-clobbered
8497 registers, we force a mode switch earlier, so that we don't
8498 run out of registers when adjusting fpscr for the call. */
8499 emit_insn (gen_force_mode_for_call ());
8501 operands[1] = function_symbol (NULL, \"__GCC_shcompact_call_trampoline\",
8503 operands[1] = force_reg (SImode, operands[1]);
8505 emit_move_insn (r0, func);
8506 emit_move_insn (r1, cookie_rtx);
8508 if (cookie & CALL_COOKIE_RET_TRAMP (1))
8509 emit_call_insn (gen_call_value_pop_compact_rettramp
8510 (operands[0], operands[1], operands[2],
8511 operands[3], operands[4]));
8513 emit_call_insn (gen_call_value_pop_compact
8514 (operands[0], operands[1], operands[2],
8515 operands[3], operands[4]));
8520 (define_expand "sibcall_epilogue"
8525 sh_expand_epilogue (1);
8526 if (TARGET_SHCOMPACT)
8530 /* If epilogue clobbers r0, preserve it in macl. */
8531 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8532 if ((set = single_set (insn))
8533 && REG_P (SET_DEST (set))
8534 && REGNO (SET_DEST (set)) == R0_REG)
8536 rtx r0 = gen_rtx_REG (SImode, R0_REG);
8537 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
8539 /* We can't tell at this point whether the sibcall is a
8540 sibcall_compact and, if it is, whether it uses r0 or
8541 mach as operand 2, so let the instructions that
8542 preserve r0 be optimized away if r0 turns out to be
8544 emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
8545 emit_move_insn (r0, tmp);
8552 (define_insn "indirect_jump_compact"
8554 (match_operand:SI 0 "arith_reg_operand" "r"))]
8557 [(set_attr "needs_delay_slot" "yes")
8558 (set_attr "type" "jump_ind")])
8560 (define_expand "indirect_jump"
8562 (match_operand 0 "register_operand" ""))]
8566 if (GET_MODE (operands[0]) != Pmode)
8567 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
8570 ;; The use of operand 1 / 2 helps us distinguish case table jumps
8571 ;; which can be present in structured code from indirect jumps which can not
8572 ;; be present in structured code. This allows -fprofile-arcs to work.
8574 ;; For SH1 processors.
8575 (define_insn "casesi_jump_1"
8577 (match_operand:SI 0 "register_operand" "r"))
8578 (use (label_ref (match_operand 1 "" "")))]
8581 [(set_attr "needs_delay_slot" "yes")
8582 (set_attr "type" "jump_ind")])
8584 ;; For all later processors.
8585 (define_insn "casesi_jump_2"
8586 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
8587 (label_ref (match_operand 1 "" ""))))
8588 (use (label_ref (match_operand 2 "" "")))]
8590 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
8592 [(set_attr "needs_delay_slot" "yes")
8593 (set_attr "type" "jump_ind")])
8595 (define_insn "casesi_jump_media"
8596 [(set (pc) (match_operand 0 "target_reg_operand" "b"))
8597 (use (label_ref (match_operand 1 "" "")))]
8600 [(set_attr "type" "jump_media")])
8602 ;; Call subroutine returning any type.
8603 ;; ??? This probably doesn't work.
8605 (define_expand "untyped_call"
8606 [(parallel [(call (match_operand 0 "" "")
8608 (match_operand 1 "" "")
8609 (match_operand 2 "" "")])]
8610 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
8615 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8617 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8619 rtx set = XVECEXP (operands[2], 0, i);
8620 emit_move_insn (SET_DEST (set), SET_SRC (set));
8623 /* The optimizer does not know that the call sets the function value
8624 registers we stored in the result block. We avoid problems by
8625 claiming that all hard registers are used and clobbered at this
8627 emit_insn (gen_blockage ());
8632 ;; ------------------------------------------------------------------------
8634 ;; ------------------------------------------------------------------------
8637 [(set (reg:SI T_REG)
8638 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
8639 (set (match_operand:SI 0 "arith_reg_dest" "=r")
8640 (plus:SI (match_dup 1) (const_int -1)))]
8643 [(set_attr "type" "arith")])
8650 ;; Load address of a label. This is only generated by the casesi expand,
8651 ;; and by machine_dependent_reorg (fixing up fp moves).
8652 ;; This must use unspec, because this only works for labels that are
8656 [(set (reg:SI R0_REG)
8657 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
8660 [(set_attr "in_delay_slot" "no")
8661 (set_attr "type" "arith")])
8663 ;; machine_dependent_reorg will make this a `mova'.
8664 (define_insn "mova_const"
8665 [(set (reg:SI R0_REG)
8666 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
8669 [(set_attr "in_delay_slot" "no")
8670 (set_attr "type" "arith")])
8672 (define_expand "GOTaddr2picreg"
8673 [(set (reg:SI R0_REG)
8674 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
8676 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
8677 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
8680 if (TARGET_VXWORKS_RTP)
8682 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
8683 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
8684 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
8688 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
8689 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
8693 rtx tr = gen_rtx_REG (Pmode, TR0_REG);
8694 rtx pic = operands[0];
8695 rtx lab = PATTERN (gen_call_site ());
8698 equiv = operands[1];
8699 operands[1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1], lab),
8700 UNSPEC_PCREL_SYMOFF);
8701 operands[1] = gen_rtx_CONST (Pmode, operands[1]);
8703 if (Pmode == SImode)
8705 emit_insn (gen_movsi_const (pic, operands[1]));
8706 emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab)));
8710 emit_insn (gen_movdi_const (pic, operands[1]));
8711 emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab)));
8714 insn = emit_move_insn (operands[0], tr);
8716 set_unique_reg_note (insn, REG_EQUAL, equiv);
8723 ;; A helper for GOTaddr2picreg to finish up the initialization of the
8726 (define_expand "vxworks_picreg"
8727 [(set (reg:SI PIC_REG)
8728 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
8729 (set (reg:SI R0_REG)
8730 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
8731 (set (reg:SI PIC_REG)
8732 (mem:SI (reg:SI PIC_REG)))
8733 (set (reg:SI PIC_REG)
8734 (mem:SI (plus:SI (reg:SI PIC_REG)
8736 "TARGET_VXWORKS_RTP")
8739 [(set (match_operand 0 "target_reg_operand" "=b")
8740 (const (unspec [(match_operand 1 "" "Csy")]
8741 UNSPEC_DATALABEL)))]
8742 "TARGET_SHMEDIA && flag_pic
8743 && satisfies_constraint_Csy (operands[1])"
8744 "ptb/u datalabel %1, %0"
8745 [(set_attr "type" "ptabs_media")
8746 (set_attr "length" "*")])
8748 (define_insn "ptrel_si"
8749 [(set (match_operand:SI 0 "target_reg_operand" "=b")
8750 (plus:SI (match_operand:SI 1 "register_operand" "r")
8752 (match_operand:SI 2 "" "")]
8754 "%O2: ptrel/u %1, %0"
8755 [(set_attr "type" "ptabs_media")])
8757 (define_insn "ptrel_di"
8758 [(set (match_operand:DI 0 "target_reg_operand" "=b")
8759 (plus:DI (match_operand:DI 1 "register_operand" "r")
8761 (match_operand:DI 2 "" "")]
8763 "%O2: ptrel/u %1, %0"
8764 [(set_attr "type" "ptabs_media")])
8766 (define_expand "builtin_setjmp_receiver"
8767 [(match_operand 0 "" "")]
8771 emit_insn (gen_GOTaddr2picreg ());
8775 (define_expand "call_site"
8776 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
8780 static HOST_WIDE_INT i = 0;
8781 operands[0] = GEN_INT (i);
8785 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
8786 ;; in symGOT_load expand.
8788 (define_insn_and_split "chk_guard_add"
8789 [(set (match_operand:SI 0 "register_operand" "=&r")
8790 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
8795 "TARGET_SH1 && reload_completed"
8796 [(set (match_dup 0) (reg:SI PIC_REG))
8797 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
8799 [(set_attr "type" "arith")])
8801 (define_expand "sym_label2reg"
8802 [(set (match_operand:SI 0 "" "")
8803 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
8804 (const (plus:SI (match_operand:SI 2 "" "")
8809 (define_expand "symGOT_load"
8810 [(set (match_dup 2) (match_operand 1 "" ""))
8811 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
8812 (set (match_operand 0 "" "") (mem (match_dup 3)))]
8818 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
8819 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
8823 rtx reg = operands[2];
8825 if (Pmode == DImode)
8828 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
8830 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
8835 emit_insn (gen_movsi_const (reg, operands[1]));
8837 emit_insn (gen_movsi_const_16bit (reg, operands[1]));
8841 emit_move_insn (operands[2], operands[1]);
8843 /* When stack protector inserts codes after the result is set to
8844 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
8845 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
8846 when rX is a GOT address for the guard symbol. Ugly but doesn't
8847 matter because this is a rare situation. */
8849 && flag_stack_protect
8850 && GET_CODE (operands[1]) == CONST
8851 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
8852 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
8853 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
8854 \"__stack_chk_guard\") == 0)
8855 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
8857 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
8858 gen_rtx_REG (Pmode, PIC_REG)));
8860 /* N.B. This is not constant for a GOTPLT relocation. */
8861 mem = gen_rtx_MEM (Pmode, operands[3]);
8862 MEM_NOTRAP_P (mem) = 1;
8863 /* ??? Should we have a special alias set for the GOT? */
8864 emit_move_insn (operands[0], mem);
8869 (define_expand "sym2GOT"
8870 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
8874 (define_expand "symGOT2reg"
8875 [(match_operand 0 "" "") (match_operand 1 "" "")]
8881 gotsym = gen_sym2GOT (operands[1]);
8882 PUT_MODE (gotsym, Pmode);
8883 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
8885 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
8890 (define_expand "symGOTPLT2reg"
8891 [(match_operand 0 "" "") (match_operand 1 "" "")]
8895 rtx pltsym = gen_rtx_CONST (Pmode,
8896 gen_rtx_UNSPEC (Pmode,
8897 gen_rtvec (1, operands[1]),
8899 emit_insn (gen_symGOT_load (operands[0], pltsym));
8903 (define_expand "sym2GOTOFF"
8904 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
8908 (define_expand "symGOTOFF2reg"
8909 [(match_operand 0 "" "") (match_operand 1 "" "")]
8913 rtx gotoffsym, insn;
8914 rtx t = (!can_create_pseudo_p ()
8916 : gen_reg_rtx (GET_MODE (operands[0])));
8918 gotoffsym = gen_sym2GOTOFF (operands[1]);
8919 PUT_MODE (gotoffsym, Pmode);
8920 emit_move_insn (t, gotoffsym);
8921 insn = emit_move_insn (operands[0],
8922 gen_rtx_PLUS (Pmode, t,
8923 gen_rtx_REG (Pmode, PIC_REG)));
8925 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
8930 (define_expand "symPLT_label2reg"
8931 [(set (match_operand:SI 0 "" "")
8934 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
8935 (const:SI (plus:SI (match_operand:SI 2 "" "")
8936 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
8937 ;; Even though the PIC register is not really used by the call
8938 ;; sequence in which this is expanded, the PLT code assumes the PIC
8939 ;; register is set, so we must not skip its initialization. Since
8940 ;; we only use this expand as part of calling sequences, and never
8941 ;; to take the address of a function, this is the best point to
8942 ;; insert the (use). Using the PLT to take the address of a
8943 ;; function would be wrong, not only because the PLT entry could
8944 ;; then be called from a function that doesn't initialize the PIC
8945 ;; register to the proper GOT, but also because pointers to the
8946 ;; same function might not compare equal, should they be set by
8947 ;; different shared libraries.
8948 (use (reg:SI PIC_REG))]
8952 (define_expand "sym2PIC"
8953 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
8957 ;; TLS code generation.
8958 ;; ??? this should be a define_insn_and_split
8959 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
8960 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
8963 (define_insn "tls_global_dynamic"
8964 [(set (match_operand:SI 0 "register_operand" "=&z")
8965 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
8968 (use (reg:PSI FPSCR_REG))
8969 (use (reg:SI PIC_REG))
8970 (clobber (reg:SI PR_REG))
8971 (clobber (scratch:SI))]
8977 \\tmova\\t2f,r0\\n\\
8978 \\tmov.l\\t2f,r1\\n\\
8981 \\tadd\\tr12,r4\\n\\
8985 1:\\t.long\\t%a1@TLSGD\\n\\
8986 2:\\t.long\\t__tls_get_addr@PLT\\n\\
8989 [(set_attr "type" "tls_load")
8990 (set_attr "length" "26")])
8992 (define_insn "tls_local_dynamic"
8993 [(set (match_operand:SI 0 "register_operand" "=&z")
8994 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
8997 (use (reg:PSI FPSCR_REG))
8998 (use (reg:SI PIC_REG))
8999 (clobber (reg:SI PR_REG))
9000 (clobber (scratch:SI))]
9006 \\tmova\\t2f,r0\\n\\
9007 \\tmov.l\\t2f,r1\\n\\
9010 \\tadd\\tr12,r4\\n\\
9014 1:\\t.long\\t%a1@TLSLDM\\n\\
9015 2:\\t.long\\t__tls_get_addr@PLT\\n\\
9018 [(set_attr "type" "tls_load")
9019 (set_attr "length" "26")])
9021 (define_expand "sym2DTPOFF"
9022 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
9026 (define_expand "symDTPOFF2reg"
9027 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
9032 rtx t = (!can_create_pseudo_p ()
9034 : gen_reg_rtx (GET_MODE (operands[0])));
9036 dtpoffsym = gen_sym2DTPOFF (operands[1]);
9037 PUT_MODE (dtpoffsym, Pmode);
9038 emit_move_insn (t, dtpoffsym);
9039 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
9043 (define_expand "sym2GOTTPOFF"
9044 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
9048 (define_insn "tls_initial_exec"
9049 [(set (match_operand:SI 0 "register_operand" "=&r")
9050 (unspec:SI [(match_operand:SI 1 "" "")]
9052 (use (reg:SI GBR_REG))
9053 (use (reg:SI PIC_REG))
9054 (clobber (reg:SI R0_REG))]
9060 \\tstc\\tgbr,%0\\n\\
9061 \\tmov.l\\t@(r0,r12),r0\\n\\
9065 1:\\t.long\\t%a1\\n\\
9068 [(set_attr "type" "tls_load")
9069 (set_attr "length" "16")])
9071 (define_expand "sym2TPOFF"
9072 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
9076 (define_expand "symTPOFF2reg"
9077 [(match_operand 0 "" "") (match_operand 1 "" "")]
9083 tpoffsym = gen_sym2TPOFF (operands[1]);
9084 PUT_MODE (tpoffsym, Pmode);
9085 emit_move_insn (operands[0], tpoffsym);
9089 (define_insn "load_gbr"
9090 [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GBR_REG))
9091 (use (reg:SI GBR_REG))]
9094 [(set_attr "type" "tls_load")])
9096 ;; case instruction for switch statements.
9098 ;; Operand 0 is index
9099 ;; operand 1 is the minimum bound
9100 ;; operand 2 is the maximum bound - minimum bound + 1
9101 ;; operand 3 is CODE_LABEL for the table;
9102 ;; operand 4 is the CODE_LABEL to go to if index out of range.
9104 (define_expand "casesi"
9105 [(match_operand:SI 0 "arith_reg_operand" "")
9106 (match_operand:SI 1 "arith_reg_operand" "")
9107 (match_operand:SI 2 "arith_reg_operand" "")
9108 (match_operand 3 "" "") (match_operand 4 "" "")]
9112 rtx reg = gen_reg_rtx (SImode);
9113 rtx reg2 = gen_reg_rtx (SImode);
9116 rtx reg = gen_reg_rtx (DImode);
9117 rtx reg2 = gen_reg_rtx (DImode);
9118 rtx reg3 = gen_reg_rtx (Pmode);
9119 rtx reg4 = gen_reg_rtx (Pmode);
9120 rtx reg5 = gen_reg_rtx (Pmode);
9123 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
9124 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
9125 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
9127 test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
9128 emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0], operands[4]));
9129 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
9130 test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
9131 emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
9132 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
9133 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
9134 (Pmode, operands[3])));
9135 /* Messy: can we subreg to clean this up? */
9136 if (Pmode == DImode)
9137 load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]);
9139 load = gen_casesi_load_media (reg4,
9140 gen_rtx_SUBREG (DImode, reg3, 0),
9142 PUT_MODE (SET_SRC (load), Pmode);
9144 /* ??? The following add could be eliminated if we used ptrel. */
9145 emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4));
9146 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
9150 operands[1] = copy_to_mode_reg (SImode, operands[1]);
9151 operands[2] = copy_to_mode_reg (SImode, operands[2]);
9152 /* If optimizing, casesi_worker depends on the mode of the instruction
9153 before label it 'uses' - operands[3]. */
9154 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
9156 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
9158 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
9160 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
9161 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
9162 operands[3], but to lab. We will fix this up in
9163 machine_dependent_reorg. */
9168 (define_expand "casesi_0"
9169 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
9170 (set (match_dup 4) (minus:SI (match_dup 4)
9171 (match_operand:SI 1 "arith_operand" "")))
9173 (gtu:SI (match_dup 4)
9174 (match_operand:SI 2 "arith_reg_operand" "")))
9176 (if_then_else (ne (reg:SI T_REG)
9178 (label_ref (match_operand 3 "" ""))
9183 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
9184 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
9185 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
9187 (define_insn "casesi_worker_0"
9188 [(set (match_operand:SI 0 "register_operand" "=r,r")
9189 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
9190 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
9191 (clobber (match_scratch:SI 3 "=X,1"))
9192 (clobber (match_scratch:SI 4 "=&z,z"))]
9197 [(set (match_operand:SI 0 "register_operand" "")
9198 (unspec:SI [(match_operand:SI 1 "register_operand" "")
9199 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
9200 (clobber (match_scratch:SI 3 ""))
9201 (clobber (match_scratch:SI 4 ""))]
9202 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
9203 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
9204 (parallel [(set (match_dup 0)
9205 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
9206 (label_ref (match_dup 2))] UNSPEC_CASESI))
9207 (clobber (match_dup 3))])
9208 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
9209 "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
9212 [(set (match_operand:SI 0 "register_operand" "")
9213 (unspec:SI [(match_operand:SI 1 "register_operand" "")
9214 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
9215 (clobber (match_scratch:SI 3 ""))
9216 (clobber (match_scratch:SI 4 ""))]
9217 "TARGET_SH2 && reload_completed"
9218 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
9219 (parallel [(set (match_dup 0)
9220 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
9221 (label_ref (match_dup 2))] UNSPEC_CASESI))
9222 (clobber (match_dup 3))])]
9223 "if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
9225 (define_insn "casesi_worker_1"
9226 [(set (match_operand:SI 0 "register_operand" "=r,r")
9227 (unspec:SI [(reg:SI R0_REG)
9228 (match_operand:SI 1 "register_operand" "0,r")
9229 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
9230 (clobber (match_scratch:SI 3 "=X,1"))]
9234 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
9236 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
9238 switch (GET_MODE (diff_vec))
9241 return \"shll2 %1\;mov.l @(r0,%1),%0\";
9243 return \"add %1,%1\;mov.w @(r0,%1),%0\";
9245 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
9246 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
9247 return \"mov.b @(r0,%1),%0\";
9252 [(set_attr "length" "4")])
9254 (define_insn "casesi_worker_2"
9255 [(set (match_operand:SI 0 "register_operand" "=r,r")
9256 (unspec:SI [(reg:SI R0_REG)
9257 (match_operand:SI 1 "register_operand" "0,r")
9258 (label_ref (match_operand 2 "" ""))
9259 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
9260 (clobber (match_operand:SI 4 "" "=X,1"))]
9261 "TARGET_SH2 && reload_completed && flag_pic"
9264 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
9267 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
9269 switch (GET_MODE (diff_vec))
9272 output_asm_insn (\"shll2 %1\", operands);
9273 load = \"mov.l @(r0,%1),%0\"; break;
9275 output_asm_insn (\"add %1,%1\", operands);
9276 load = \"mov.w @(r0,%1),%0\"; break;
9278 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
9279 load = \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
9281 load = \"mov.b @(r0,%1),%0\";
9286 output_asm_insn (\"add\tr0,%1\;mova\t%O3,r0\\n\", operands);
9289 [(set_attr "length" "8")])
9291 (define_insn "casesi_shift_media"
9292 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
9293 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
9294 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
9299 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
9301 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
9303 switch (GET_MODE (diff_vec))
9306 return \"shlli %1, 2, %0\";
9308 return \"shlli %1, 1, %0\";
9310 if (rtx_equal_p (operands[0], operands[1]))
9312 return \"add %1, r63, %0\";
9317 [(set_attr "type" "arith_media")])
9319 (define_insn "casesi_load_media"
9320 [(set (match_operand 0 "any_arith_reg_dest" "=r")
9321 (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
9322 (match_operand:DI 2 "arith_reg_operand" "r")
9323 (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
9327 rtx diff_vec = PATTERN (next_real_insn (operands[3]));
9329 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
9331 switch (GET_MODE (diff_vec))
9334 return \"ldx.l %1, %2, %0\";
9337 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
9338 return \"ldx.uw %1, %2, %0\";
9340 return \"ldx.w %1, %2, %0\";
9342 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
9343 return \"ldx.ub %1, %2, %0\";
9344 return \"ldx.b %1, %2, %0\";
9349 [(set_attr "type" "load_media")])
9351 (define_expand "return"
9353 "reload_completed && ! sh_need_epilogue ()"
9358 emit_jump_insn (gen_return_media ());
9362 if (TARGET_SHCOMPACT
9363 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
9365 emit_jump_insn (gen_shcompact_return_tramp ());
9370 (define_insn "*return_i"
9372 "TARGET_SH1 && ! (TARGET_SHCOMPACT
9373 && (crtl->args.info.call_cookie
9374 & CALL_COOKIE_RET_TRAMP (1)))
9376 && lookup_attribute (\"trap_exit\",
9377 DECL_ATTRIBUTES (current_function_decl)) == NULL_TREE"
9380 if (TARGET_SH2A && (dbr_sequence_length () == 0)
9381 && !current_function_interrupt)
9386 [(set_attr "type" "return")
9387 (set_attr "needs_delay_slot" "yes")])
9389 ;; trapa has no delay slot.
9390 (define_insn "*return_trapa"
9392 "TARGET_SH1 && !TARGET_SHCOMPACT
9393 && reload_completed"
9395 [(set_attr "type" "return")])
9397 (define_expand "shcompact_return_tramp"
9400 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
9403 rtx reg = gen_rtx_REG (Pmode, R0_REG);
9405 function_symbol (reg, \"__GCC_shcompact_return_trampoline\", SFUNC_STATIC);
9406 emit_jump_insn (gen_shcompact_return_tramp_i ());
9410 (define_insn "shcompact_return_tramp_i"
9411 [(parallel [(return) (use (reg:SI R0_REG))])]
9413 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
9415 [(set_attr "type" "jump_ind")
9416 (set_attr "needs_delay_slot" "yes")])
9418 (define_insn "return_media_i"
9419 [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])]
9420 "TARGET_SHMEDIA && reload_completed"
9422 [(set_attr "type" "jump_media")])
9424 (define_insn "return_media_rte"
9426 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
9428 [(set_attr "type" "jump_media")])
9430 (define_expand "return_media"
9432 "TARGET_SHMEDIA && reload_completed"
9435 int tr_regno = sh_media_register_for_return ();
9438 if (current_function_interrupt)
9440 emit_jump_insn (gen_return_media_rte ());
9445 rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG);
9447 gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]);
9449 tr = gen_rtx_REG (Pmode, tr_regno);
9450 emit_move_insn (tr, r18);
9453 tr = gen_rtx_REG (Pmode, tr_regno);
9455 emit_jump_insn (gen_return_media_i (tr));
9459 (define_insn "shcompact_preserve_incoming_args"
9460 [(set (match_operand:SI 0 "register_operand" "+r")
9461 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
9464 [(set_attr "length" "0")])
9466 (define_insn "shcompact_incoming_args"
9467 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
9468 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
9469 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
9470 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
9471 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
9472 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
9473 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
9474 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
9475 (set (mem:BLK (reg:SI MACL_REG))
9476 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
9477 (use (reg:SI R0_REG))
9478 (clobber (reg:SI R0_REG))
9479 (clobber (reg:SI MACL_REG))
9480 (clobber (reg:SI MACH_REG))
9481 (clobber (reg:SI PR_REG))]
9484 [(set_attr "needs_delay_slot" "yes")])
9486 (define_insn "shmedia_save_restore_regs_compact"
9487 [(set (reg:SI SP_REG)
9488 (plus:SI (reg:SI SP_REG)
9489 (match_operand:SI 0 "immediate_operand" "i")))
9490 (use (reg:SI R0_REG))
9491 (clobber (reg:SI PR_REG))]
9493 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
9494 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
9496 [(set_attr "needs_delay_slot" "yes")])
9498 (define_expand "prologue"
9501 "sh_expand_prologue (); DONE;")
9503 (define_expand "epilogue"
9508 sh_expand_epilogue (0);
9509 emit_jump_insn (gen_return ());
9513 (define_expand "eh_return"
9514 [(use (match_operand 0 "register_operand" ""))]
9517 rtx ra = operands[0];
9519 if (TARGET_SHMEDIA64)
9520 emit_insn (gen_eh_set_ra_di (ra));
9522 emit_insn (gen_eh_set_ra_si (ra));
9527 ;; Clobber the return address on the stack. We can't expand this
9528 ;; until we know where it will be put in the stack frame.
9530 (define_insn "eh_set_ra_si"
9531 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
9533 (clobber (match_scratch:SI 1 "=&r"))]
9534 "! TARGET_SHMEDIA64"
9537 (define_insn "eh_set_ra_di"
9538 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
9540 (clobber (match_scratch:DI 1 "=&r"))]
9545 [(unspec_volatile [(match_operand 0 "register_operand" "")]
9547 (clobber (match_scratch 1 ""))]
9552 sh_set_return_address (operands[0], operands[1]);
9556 (define_insn "blockage"
9557 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9560 [(set_attr "length" "0")])
9562 ;; Define movml instructions for SH2A target. Currently they are
9563 ;; used to push and pop all banked registers only.
9565 (define_insn "movml_push_banked"
9566 [(set (match_operand:SI 0 "register_operand" "=r")
9567 (plus (match_dup 0) (const_int -32)))
9568 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
9569 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
9570 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
9571 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
9572 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
9573 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
9574 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
9575 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
9576 "TARGET_SH2A && REGNO (operands[0]) == 15"
9578 [(set_attr "in_delay_slot" "no")])
9580 (define_insn "movml_pop_banked"
9581 [(set (match_operand:SI 0 "register_operand" "=r")
9582 (plus (match_dup 0) (const_int 32)))
9583 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
9584 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
9585 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
9586 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
9587 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
9588 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
9589 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
9590 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
9591 "TARGET_SH2A && REGNO (operands[0]) == 15"
9593 [(set_attr "in_delay_slot" "no")])
9595 ;; ------------------------------------------------------------------------
9597 ;; ------------------------------------------------------------------------
9600 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
9601 (eq:SI (reg:SI T_REG) (const_int 1)))]
9604 [(set_attr "type" "arith")])
9606 (define_insn "movrt"
9607 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
9608 (xor:SI (reg:SI T_REG) (const_int 1)))]
9611 [(set_attr "type" "arith")])
9613 (define_expand "cstore4_media"
9614 [(set (match_operand:SI 0 "register_operand" "=r")
9615 (match_operator:SI 1 "sh_float_comparison_operator"
9616 [(match_operand 2 "logical_operand" "")
9617 (match_operand 3 "cmp_operand" "")]))]
9621 enum machine_mode mode = GET_MODE (operands[2]);
9622 enum rtx_code code = GET_CODE (operands[1]);
9624 if (mode == VOIDmode)
9625 mode = GET_MODE (operands[3]);
9626 if (operands[2] == const0_rtx)
9628 if (code == EQ || code == NE)
9629 operands[2] = operands[3], operands[3] = const0_rtx;
9632 operands[2] = force_reg (mode, operands[2]);
9633 if (operands[3] != const0_rtx)
9634 operands[3] = force_reg (mode, operands[3]);
9640 swap = invert = !FLOAT_MODE_P (mode);
9645 swap = FLOAT_MODE_P (mode), invert = !swap;
9650 swap = true, invert = false;
9657 swap = invert = false;
9661 swap = invert = true;
9670 rtx tem = operands[2];
9671 operands[2] = operands[3];
9673 code = swap_condition (code);
9678 rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
9679 code = reverse_condition (code);
9680 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
9681 emit_insn (gen_cstore4_media (tem, operands[1],
9682 operands[2], operands[3]));
9685 operands[3] = const0_rtx;
9688 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
9691 (define_expand "cstoresi4"
9692 [(set (match_operand:SI 0 "register_operand" "=r")
9693 (match_operator:SI 1 "comparison_operator"
9694 [(match_operand:SI 2 "cmpsi_operand" "")
9695 (match_operand:SI 3 "arith_operand" "")]))]
9696 "TARGET_SH1 || TARGET_SHMEDIA"
9697 "if (TARGET_SHMEDIA)
9699 emit_insn (gen_cstore4_media (operands[0], operands[1],
9700 operands[2], operands[3]));
9704 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
9705 && sh_expand_t_scc (operands))
9708 if (! currently_expanding_to_rtl)
9711 sh_emit_compare_and_set (operands, SImode);
9715 (define_expand "cstoredi4"
9716 [(set (match_operand:SI 0 "register_operand" "=r")
9717 (match_operator:SI 1 "comparison_operator"
9718 [(match_operand:DI 2 "arith_operand" "")
9719 (match_operand:DI 3 "arith_operand" "")]))]
9720 "TARGET_SH2 || TARGET_SHMEDIA"
9721 "if (TARGET_SHMEDIA)
9723 emit_insn (gen_cstore4_media (operands[0], operands[1],
9724 operands[2], operands[3]));
9728 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
9729 && sh_expand_t_scc (operands))
9732 if (! currently_expanding_to_rtl)
9735 sh_emit_compare_and_set (operands, DImode);
9739 ;; Move the complement of the T reg to a reg.
9740 ;; On SH2A the movrt insn can be used.
9741 ;; On anything else than SH2A this has to be done with multiple instructions.
9742 ;; One obvious way would be:
9747 ;; However, this puts pressure on r0 in most cases and thus the following is
9753 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
9754 ;; becomes a one instruction operation. Moreover, care must be taken that
9755 ;; the insn can still be combined with inverted compare and branch code
9756 ;; around it. On the other hand, if a function returns the complement of
9757 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
9758 ;; lead to better code.
9760 (define_expand "movnegt"
9761 [(set (match_operand:SI 0 "arith_reg_dest" "")
9762 (xor:SI (reg:SI T_REG) (const_int 1)))]
9766 emit_insn (gen_movrt (operands[0]));
9769 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
9770 emit_insn (gen_movrt_negc (operands[0], val));
9775 (define_insn "movrt_negc"
9776 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
9777 (xor:SI (reg:SI T_REG) (const_int 1)))
9778 (set (reg:SI T_REG) (const_int 1))
9779 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
9782 [(set_attr "type" "arith")])
9784 ;; The *negnegt patterns help the combine pass to figure out how to fold
9785 ;; an explicit double T bit negation.
9786 (define_insn_and_split "*negnegt"
9787 [(set (reg:SI T_REG)
9788 (eq:SI (subreg:QI (xor:SI (reg:SI T_REG) (const_int 1)) 3)
9790 "! TARGET_LITTLE_ENDIAN"
9795 (define_insn_and_split "*negnegt"
9796 [(set (reg:SI T_REG)
9797 (eq:SI (subreg:QI (xor:SI (reg:SI T_REG) (const_int 1)) 0)
9799 "TARGET_LITTLE_ENDIAN"
9804 ;; The *movtt patterns improve code at -O1.
9805 (define_insn_and_split "*movtt"
9806 [(set (reg:SI T_REG)
9807 (eq:SI (zero_extend:SI (subreg:QI (reg:SI T_REG) 3))
9809 "! TARGET_LITTLE_ENDIAN"
9814 (define_insn_and_split "*movtt"
9815 [(set (reg:SI T_REG)
9816 (eq:SI (zero_extend:SI (subreg:QI (reg:SI T_REG) 0))
9818 "TARGET_LITTLE_ENDIAN"
9823 ;; The *movt_qi patterns help the combine pass convert a movrt_negc pattern
9824 ;; into a movt Rn, xor #1 Rn pattern. This can happen when e.g. a function
9825 ;; returns the inverted T bit value.
9826 (define_insn "*movt_qi"
9827 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
9828 (zero_extend:SI (subreg:QI (reg:SI T_REG) 3)))]
9829 "! TARGET_LITTLE_ENDIAN"
9831 [(set_attr "type" "arith")])
9833 (define_insn "*movt_qi"
9834 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
9835 (zero_extend:SI (subreg:QI (reg:SI T_REG) 0)))]
9836 "TARGET_LITTLE_ENDIAN"
9838 [(set_attr "type" "arith")])
9840 (define_expand "cstoresf4"
9841 [(set (match_operand:SI 0 "register_operand" "=r")
9842 (match_operator:SI 1 "sh_float_comparison_operator"
9843 [(match_operand:SF 2 "arith_operand" "")
9844 (match_operand:SF 3 "arith_operand" "")]))]
9845 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
9846 "if (TARGET_SHMEDIA)
9848 emit_insn (gen_cstore4_media (operands[0], operands[1],
9849 operands[2], operands[3]));
9853 if (! currently_expanding_to_rtl)
9856 sh_emit_compare_and_set (operands, SFmode);
9860 (define_expand "cstoredf4"
9861 [(set (match_operand:SI 0 "register_operand" "=r")
9862 (match_operator:SI 1 "sh_float_comparison_operator"
9863 [(match_operand:DF 2 "arith_operand" "")
9864 (match_operand:DF 3 "arith_operand" "")]))]
9865 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
9866 "if (TARGET_SHMEDIA)
9868 emit_insn (gen_cstore4_media (operands[0], operands[1],
9869 operands[2], operands[3]));
9873 if (! currently_expanding_to_rtl)
9876 sh_emit_compare_and_set (operands, DFmode);
9880 ;; -------------------------------------------------------------------------
9881 ;; Instructions to cope with inline literal tables
9882 ;; -------------------------------------------------------------------------
9884 ; 2 byte integer in line
9886 (define_insn "consttable_2"
9887 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
9888 (match_operand 1 "" "")]
9893 if (operands[1] != const0_rtx)
9894 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
9897 [(set_attr "length" "2")
9898 (set_attr "in_delay_slot" "no")])
9900 ; 4 byte integer in line
9902 (define_insn "consttable_4"
9903 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
9904 (match_operand 1 "" "")]
9909 if (operands[1] != const0_rtx)
9911 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
9912 mark_symbol_refs_as_used (operands[0]);
9916 [(set_attr "length" "4")
9917 (set_attr "in_delay_slot" "no")])
9919 ; 8 byte integer in line
9921 (define_insn "consttable_8"
9922 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
9923 (match_operand 1 "" "")]
9928 if (operands[1] != const0_rtx)
9929 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
9932 [(set_attr "length" "8")
9933 (set_attr "in_delay_slot" "no")])
9935 ; 4 byte floating point
9937 (define_insn "consttable_sf"
9938 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
9939 (match_operand 1 "" "")]
9944 if (operands[1] != const0_rtx)
9947 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
9948 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
9952 [(set_attr "length" "4")
9953 (set_attr "in_delay_slot" "no")])
9955 ; 8 byte floating point
9957 (define_insn "consttable_df"
9958 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
9959 (match_operand 1 "" "")]
9964 if (operands[1] != const0_rtx)
9967 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
9968 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
9972 [(set_attr "length" "8")
9973 (set_attr "in_delay_slot" "no")])
9975 ;; Alignment is needed for some constant tables; it may also be added for
9976 ;; Instructions at the start of loops, or after unconditional branches.
9977 ;; ??? We would get more accurate lengths if we did instruction
9978 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
9979 ;; here is too conservative.
9981 ; align to a two byte boundary
9983 (define_expand "align_2"
9984 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
9988 ; align to a four byte boundary
9989 ;; align_4 and align_log are instructions for the starts of loops, or
9990 ;; after unconditional branches, which may take up extra room.
9992 (define_expand "align_4"
9993 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
9997 ; align to a cache line boundary
9999 (define_insn "align_log"
10000 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
10003 [(set_attr "length" "0")
10004 (set_attr "in_delay_slot" "no")])
10006 ; emitted at the end of the literal table, used to emit the
10007 ; 32bit branch labels if needed.
10009 (define_insn "consttable_end"
10010 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
10012 "* return output_jump_label_table ();"
10013 [(set_attr "in_delay_slot" "no")])
10015 ; emitted at the end of the window in the literal table.
10017 (define_insn "consttable_window_end"
10018 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
10021 [(set_attr "length" "0")
10022 (set_attr "in_delay_slot" "no")])
10024 ;; -------------------------------------------------------------------------
10026 ;; -------------------------------------------------------------------------
10028 ;; String/block move insn.
10030 (define_expand "movmemsi"
10031 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
10032 (mem:BLK (match_operand:BLK 1 "" "")))
10033 (use (match_operand:SI 2 "nonmemory_operand" ""))
10034 (use (match_operand:SI 3 "immediate_operand" ""))
10035 (clobber (reg:SI PR_REG))
10036 (clobber (reg:SI R4_REG))
10037 (clobber (reg:SI R5_REG))
10038 (clobber (reg:SI R0_REG))])]
10039 "TARGET_SH1 && ! TARGET_SH5"
10042 if(expand_block_move (operands))
10047 (define_insn "block_move_real"
10048 [(parallel [(set (mem:BLK (reg:SI R4_REG))
10049 (mem:BLK (reg:SI R5_REG)))
10050 (use (match_operand:SI 0 "arith_reg_operand" "r"))
10051 (clobber (reg:SI PR_REG))
10052 (clobber (reg:SI R0_REG))])]
10053 "TARGET_SH1 && ! TARGET_HARD_SH4"
10055 [(set_attr "type" "sfunc")
10056 (set_attr "needs_delay_slot" "yes")])
10058 (define_insn "block_lump_real"
10059 [(parallel [(set (mem:BLK (reg:SI R4_REG))
10060 (mem:BLK (reg:SI R5_REG)))
10061 (use (match_operand:SI 0 "arith_reg_operand" "r"))
10062 (use (reg:SI R6_REG))
10063 (clobber (reg:SI PR_REG))
10064 (clobber (reg:SI T_REG))
10065 (clobber (reg:SI R4_REG))
10066 (clobber (reg:SI R5_REG))
10067 (clobber (reg:SI R6_REG))
10068 (clobber (reg:SI R0_REG))])]
10069 "TARGET_SH1 && ! TARGET_HARD_SH4"
10071 [(set_attr "type" "sfunc")
10072 (set_attr "needs_delay_slot" "yes")])
10074 (define_insn "block_move_real_i4"
10075 [(parallel [(set (mem:BLK (reg:SI R4_REG))
10076 (mem:BLK (reg:SI R5_REG)))
10077 (use (match_operand:SI 0 "arith_reg_operand" "r"))
10078 (clobber (reg:SI PR_REG))
10079 (clobber (reg:SI R0_REG))
10080 (clobber (reg:SI R1_REG))
10081 (clobber (reg:SI R2_REG))])]
10084 [(set_attr "type" "sfunc")
10085 (set_attr "needs_delay_slot" "yes")])
10087 (define_insn "block_lump_real_i4"
10088 [(parallel [(set (mem:BLK (reg:SI R4_REG))
10089 (mem:BLK (reg:SI R5_REG)))
10090 (use (match_operand:SI 0 "arith_reg_operand" "r"))
10091 (use (reg:SI R6_REG))
10092 (clobber (reg:SI PR_REG))
10093 (clobber (reg:SI T_REG))
10094 (clobber (reg:SI R4_REG))
10095 (clobber (reg:SI R5_REG))
10096 (clobber (reg:SI R6_REG))
10097 (clobber (reg:SI R0_REG))
10098 (clobber (reg:SI R1_REG))
10099 (clobber (reg:SI R2_REG))
10100 (clobber (reg:SI R3_REG))])]
10103 [(set_attr "type" "sfunc")
10104 (set_attr "needs_delay_slot" "yes")])
10106 ;; -------------------------------------------------------------------------
10107 ;; Floating point instructions.
10108 ;; -------------------------------------------------------------------------
10110 ;; ??? All patterns should have a type attribute.
10112 (define_expand "movpsi"
10113 [(set (match_operand:PSI 0 "register_operand" "")
10114 (match_operand:PSI 1 "general_movsrc_operand" ""))]
10115 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
10118 ;; The c / m alternative is a fake to guide reload to load directly into
10119 ;; fpscr, since reload doesn't know how to use post-increment.
10120 ;; TARGET_LEGITIMATE_ADDRESS_P guards about bogus addresses before reload,
10121 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
10122 ;; predicate after reload.
10123 ;; The mac_gp type for r/!c might look a bit odd, but it actually schedules
10124 ;; like a mac -> gpr move.
10125 (define_insn "fpu_switch"
10126 [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
10127 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
10129 && (! reload_completed
10130 || true_regnum (operands[0]) != FPSCR_REG
10131 || !MEM_P (operands[1])
10132 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
10134 ! precision stays the same
10143 [(set_attr "length" "0,2,2,4,2,2,2,2,2")
10144 (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,mac_gp,fstore")])
10147 [(set (reg:PSI FPSCR_REG)
10148 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
10149 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && peep2_reg_dead_p (1, operands[0])"
10152 rtx fpscr, mem, new_insn;
10154 fpscr = SET_DEST (PATTERN (curr_insn));
10155 mem = SET_SRC (PATTERN (curr_insn));
10156 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
10158 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
10159 add_reg_note (new_insn, REG_INC, operands[0]);
10164 [(set (reg:PSI FPSCR_REG)
10165 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
10166 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
10167 && (flag_peephole2 ? epilogue_completed : reload_completed)"
10170 rtx fpscr, mem, new_insn;
10172 fpscr = SET_DEST (PATTERN (curr_insn));
10173 mem = SET_SRC (PATTERN (curr_insn));
10174 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
10176 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
10177 add_reg_note (new_insn, REG_INC, operands[0]);
10179 if (!find_regno_note (curr_insn, REG_DEAD, true_regnum (operands[0])))
10180 emit_insn (gen_addsi3 (operands[0], operands[0], GEN_INT (-4)));
10184 ;; ??? This uses the fp unit, but has no type indicating that.
10185 ;; If we did that, this would either give a bogus latency or introduce
10186 ;; a bogus FIFO constraint.
10187 ;; Since this insn is currently only used for prologues/epilogues,
10188 ;; it is probably best to claim no function unit, which matches the
10189 ;; current setting.
10190 (define_insn "toggle_sz"
10191 [(set (reg:PSI FPSCR_REG)
10192 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
10193 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
10195 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
10197 ;; There's no way we can use it today, since optimize mode switching
10198 ;; doesn't enable us to know from which mode we're switching to the
10199 ;; mode it requests, to tell whether we can use a relative mode switch
10200 ;; (like toggle_pr) or an absolute switch (like loading fpscr from
10202 (define_insn "toggle_pr"
10203 [(set (reg:PSI FPSCR_REG)
10204 (xor:PSI (reg:PSI FPSCR_REG) (const_int 524288)))]
10205 "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE"
10207 [(set_attr "type" "fpscr_toggle")])
10209 (define_expand "addsf3"
10210 [(set (match_operand:SF 0 "arith_reg_operand" "")
10211 (plus:SF (match_operand:SF 1 "arith_reg_operand" "")
10212 (match_operand:SF 2 "arith_reg_operand" "")))]
10213 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10218 expand_sf_binop (&gen_addsf3_i, operands);
10223 (define_insn "*addsf3_media"
10224 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10225 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
10226 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10227 "TARGET_SHMEDIA_FPU"
10228 "fadd.s %1, %2, %0"
10229 [(set_attr "type" "fparith_media")])
10231 (define_insn_and_split "unary_sf_op"
10232 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
10237 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
10238 (match_operator:SF 2 "unary_float_operator"
10239 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
10240 (parallel [(match_operand 4
10241 "const_int_operand" "n")]))]))
10242 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
10243 "TARGET_SHMEDIA_FPU"
10245 "TARGET_SHMEDIA_FPU && reload_completed"
10246 [(set (match_dup 5) (match_dup 6))]
10249 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
10250 rtx op1 = gen_rtx_REG (SFmode,
10251 (true_regnum (operands[1])
10252 + (INTVAL (operands[4]) ^ endian)));
10254 operands[7] = gen_rtx_REG (SFmode,
10255 (true_regnum (operands[0])
10256 + (INTVAL (operands[3]) ^ endian)));
10257 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
10259 [(set_attr "type" "fparith_media")])
10261 (define_insn_and_split "binary_sf_op0"
10262 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
10264 (match_operator:SF 3 "binary_float_operator"
10265 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
10266 (parallel [(const_int 0)]))
10267 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
10268 (parallel [(const_int 0)]))])
10271 (parallel [(const_int 1)]))))]
10272 "TARGET_SHMEDIA_FPU"
10274 "&& reload_completed"
10275 [(set (match_dup 4) (match_dup 5))]
10278 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
10279 rtx op1 = gen_rtx_REG (SFmode,
10280 true_regnum (operands[1]) + endian);
10281 rtx op2 = gen_rtx_REG (SFmode,
10282 true_regnum (operands[2]) + endian);
10284 operands[4] = gen_rtx_REG (SFmode,
10285 true_regnum (operands[0]) + endian);
10286 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
10288 [(set_attr "type" "fparith_media")])
10290 (define_insn_and_split "binary_sf_op1"
10291 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
10295 (parallel [(const_int 0)]))
10296 (match_operator:SF 3 "binary_float_operator"
10297 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
10298 (parallel [(const_int 1)]))
10299 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
10300 (parallel [(const_int 1)]))])))]
10301 "TARGET_SHMEDIA_FPU"
10303 "&& reload_completed"
10304 [(set (match_dup 4) (match_dup 5))]
10307 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
10308 rtx op1 = gen_rtx_REG (SFmode,
10309 true_regnum (operands[1]) + (1 ^ endian));
10310 rtx op2 = gen_rtx_REG (SFmode,
10311 true_regnum (operands[2]) + (1 ^ endian));
10313 operands[4] = gen_rtx_REG (SFmode,
10314 true_regnum (operands[0]) + (1 ^ endian));
10315 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
10317 [(set_attr "type" "fparith_media")])
10319 (define_insn "addsf3_i"
10320 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10321 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
10322 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
10323 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10326 [(set_attr "type" "fp")
10327 (set_attr "fp_mode" "single")])
10329 (define_expand "subsf3"
10330 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
10331 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
10332 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
10333 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10338 expand_sf_binop (&gen_subsf3_i, operands);
10343 (define_insn "*subsf3_media"
10344 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10345 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
10346 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10347 "TARGET_SHMEDIA_FPU"
10348 "fsub.s %1, %2, %0"
10349 [(set_attr "type" "fparith_media")])
10351 (define_insn "subsf3_i"
10352 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10353 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
10354 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
10355 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10358 [(set_attr "type" "fp")
10359 (set_attr "fp_mode" "single")])
10361 (define_expand "mulsf3"
10362 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
10363 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
10364 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
10365 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10368 (define_insn "*mulsf3_media"
10369 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10370 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
10371 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10372 "TARGET_SHMEDIA_FPU"
10373 "fmul.s %1, %2, %0"
10374 [(set_attr "type" "fparith_media")])
10376 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
10377 ;; register in feeding fp instructions. Thus, in order to generate fmac,
10378 ;; we start out with a mulsf pattern that does not depend on fpscr.
10379 ;; This is split after combine to introduce the dependency, in order to
10380 ;; get mode switching and scheduling right.
10381 (define_insn_and_split "mulsf3_ie"
10382 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10383 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
10384 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10387 "TARGET_SH4 || TARGET_SH2A_SINGLE"
10391 emit_insn (gen_mulsf3_i4 (operands[0], operands[1], operands[2],
10392 get_fpscr_rtx ()));
10395 [(set_attr "type" "fp")])
10397 (define_insn "mulsf3_i4"
10398 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10399 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
10400 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
10401 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10404 [(set_attr "type" "fp")
10405 (set_attr "fp_mode" "single")])
10407 (define_insn "mac_media"
10408 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10409 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
10410 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
10411 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
10412 "TARGET_SHMEDIA_FPU && TARGET_FMAC"
10413 "fmac.s %1, %2, %0"
10414 [(set_attr "type" "fparith_media")])
10416 (define_insn "*macsf3"
10417 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10418 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
10419 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
10420 (match_operand:SF 3 "arith_reg_operand" "0")))
10421 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
10422 "TARGET_SH2E && TARGET_FMAC"
10424 [(set_attr "type" "fp")
10425 (set_attr "fp_mode" "single")])
10427 (define_expand "divsf3"
10428 [(set (match_operand:SF 0 "arith_reg_operand" "")
10429 (div:SF (match_operand:SF 1 "arith_reg_operand" "")
10430 (match_operand:SF 2 "arith_reg_operand" "")))]
10431 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10436 expand_sf_binop (&gen_divsf3_i, operands);
10441 (define_insn "*divsf3_media"
10442 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10443 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
10444 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10445 "TARGET_SHMEDIA_FPU"
10446 "fdiv.s %1, %2, %0"
10447 [(set_attr "type" "fdiv_media")])
10449 (define_insn "divsf3_i"
10450 [(set (match_operand:SF 0 "arith_reg_dest" "=f")
10451 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
10452 (match_operand:SF 2 "arith_reg_operand" "f")))
10453 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10456 [(set_attr "type" "fdiv")
10457 (set_attr "fp_mode" "single")])
10459 (define_insn "floatdisf2"
10460 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10461 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
10462 "TARGET_SHMEDIA_FPU"
10464 [(set_attr "type" "fpconv_media")])
10466 (define_expand "floatsisf2"
10467 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
10468 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
10469 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10472 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
10474 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
10479 (define_insn "*floatsisf2_media"
10480 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10481 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
10482 "TARGET_SHMEDIA_FPU"
10484 [(set_attr "type" "fpconv_media")])
10486 (define_insn "floatsisf2_i4"
10487 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10488 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
10489 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10490 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
10492 [(set_attr "type" "fp")
10493 (set_attr "fp_mode" "single")])
10495 (define_insn "*floatsisf2_ie"
10496 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10497 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
10498 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
10500 [(set_attr "type" "fp")])
10502 (define_insn "fix_truncsfdi2"
10503 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
10504 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10505 "TARGET_SHMEDIA_FPU"
10507 [(set_attr "type" "fpconv_media")])
10509 (define_expand "fix_truncsfsi2"
10510 [(set (match_operand:SI 0 "fpul_operand" "=y")
10511 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10512 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10515 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
10517 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
10522 (define_insn "*fix_truncsfsi2_media"
10523 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
10524 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10525 "TARGET_SHMEDIA_FPU"
10527 [(set_attr "type" "fpconv_media")])
10529 (define_insn "fix_truncsfsi2_i4"
10530 [(set (match_operand:SI 0 "fpul_operand" "=y")
10531 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
10532 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10533 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
10535 [(set_attr "type" "ftrc_s")
10536 (set_attr "fp_mode" "single")])
10538 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
10539 ;; fix_truncsfsi2_i4.
10540 ;; (define_insn "fix_truncsfsi2_i4_2"
10541 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
10542 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
10543 ;; (use (reg:PSI FPSCR_REG))
10544 ;; (clobber (reg:SI FPUL_REG))]
10547 ;; [(set_attr "length" "4")
10548 ;; (set_attr "fp_mode" "single")])
10551 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
10552 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
10553 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
10554 ;; (clobber (reg:SI FPUL_REG))]
10556 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
10557 ;; (use (match_dup 2))])
10558 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
10560 (define_insn "*fixsfsi"
10561 [(set (match_operand:SI 0 "fpul_operand" "=y")
10562 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10563 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
10565 [(set_attr "type" "fp")])
10567 (define_insn "cmpgtsf_t"
10568 [(set (reg:SI T_REG)
10569 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
10570 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10571 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
10573 [(set_attr "type" "fp_cmp")
10574 (set_attr "fp_mode" "single")])
10576 (define_insn "cmpeqsf_t"
10577 [(set (reg:SI T_REG)
10578 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
10579 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10580 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
10582 [(set_attr "type" "fp_cmp")
10583 (set_attr "fp_mode" "single")])
10585 (define_insn "ieee_ccmpeqsf_t"
10586 [(set (reg:SI T_REG)
10587 (ior:SI (reg:SI T_REG)
10588 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
10589 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
10590 "TARGET_SH2E && TARGET_IEEE && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
10591 "* return output_ieee_ccmpeq (insn, operands);"
10592 [(set_attr "length" "4")])
10595 (define_insn "cmpgtsf_t_i4"
10596 [(set (reg:SI T_REG)
10597 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
10598 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
10599 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10600 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
10602 [(set_attr "type" "fp_cmp")
10603 (set_attr "fp_mode" "single")])
10605 (define_insn "cmpeqsf_t_i4"
10606 [(set (reg:SI T_REG)
10607 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
10608 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
10609 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10610 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
10612 [(set_attr "type" "fp_cmp")
10613 (set_attr "fp_mode" "single")])
10615 (define_insn "*ieee_ccmpeqsf_t_4"
10616 [(set (reg:SI T_REG)
10617 (ior:SI (reg:SI T_REG)
10618 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
10619 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
10620 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10621 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_SINGLE)"
10622 "* return output_ieee_ccmpeq (insn, operands);"
10623 [(set_attr "length" "4")
10624 (set_attr "fp_mode" "single")])
10626 (define_insn "cmpeqsf_media"
10627 [(set (match_operand:SI 0 "register_operand" "=r")
10628 (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
10629 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10630 "TARGET_SHMEDIA_FPU"
10631 "fcmpeq.s %1, %2, %0"
10632 [(set_attr "type" "fcmp_media")])
10634 (define_insn "cmpgtsf_media"
10635 [(set (match_operand:SI 0 "register_operand" "=r")
10636 (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
10637 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10638 "TARGET_SHMEDIA_FPU"
10639 "fcmpgt.s %1, %2, %0"
10640 [(set_attr "type" "fcmp_media")])
10642 (define_insn "cmpgesf_media"
10643 [(set (match_operand:SI 0 "register_operand" "=r")
10644 (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
10645 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10646 "TARGET_SHMEDIA_FPU"
10647 "fcmpge.s %1, %2, %0"
10648 [(set_attr "type" "fcmp_media")])
10650 (define_insn "cmpunsf_media"
10651 [(set (match_operand:SI 0 "register_operand" "=r")
10652 (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
10653 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
10654 "TARGET_SHMEDIA_FPU"
10655 "fcmpun.s %1, %2, %0"
10656 [(set_attr "type" "fcmp_media")])
10658 (define_expand "cbranchsf4"
10660 (if_then_else (match_operator 0 "sh_float_comparison_operator"
10661 [(match_operand:SF 1 "arith_operand" "")
10662 (match_operand:SF 2 "arith_operand" "")])
10663 (match_operand 3 "" "")
10665 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10668 if (TARGET_SHMEDIA)
10669 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
10672 sh_emit_compare_and_branch (operands, SFmode);
10676 (define_expand "negsf2"
10677 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
10678 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
10679 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10684 expand_sf_unop (&gen_negsf2_i, operands);
10689 (define_insn "*negsf2_media"
10690 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10691 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10692 "TARGET_SHMEDIA_FPU"
10694 [(set_attr "type" "fmove_media")])
10696 (define_insn "negsf2_i"
10697 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10698 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
10699 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10702 [(set_attr "type" "fmove")
10703 (set_attr "fp_mode" "single")])
10705 (define_expand "sqrtsf2"
10706 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
10707 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
10708 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
10713 expand_sf_unop (&gen_sqrtsf2_i, operands);
10718 (define_insn "*sqrtsf2_media"
10719 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10720 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10721 "TARGET_SHMEDIA_FPU"
10723 [(set_attr "type" "fdiv_media")])
10725 (define_insn "sqrtsf2_i"
10726 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10727 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
10728 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10731 [(set_attr "type" "fdiv")
10732 (set_attr "fp_mode" "single")])
10734 (define_insn "rsqrtsf2"
10735 [(set (match_operand:SF 0 "register_operand" "=f")
10736 (div:SF (match_operand:SF 1 "immediate_operand" "i")
10737 (sqrt:SF (match_operand:SF 2 "register_operand" "0"))))
10738 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10739 "TARGET_SH4A_FP && flag_unsafe_math_optimizations
10740 && operands[1] == CONST1_RTX (SFmode)"
10742 [(set_attr "type" "fsrra")
10743 (set_attr "fp_mode" "single")])
10745 (define_insn "fsca"
10746 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
10748 (unspec:SF [(mult:SF
10749 (float:SF (match_operand:SI 1 "fpul_operand" "y"))
10750 (match_operand:SF 2 "immediate_operand" "i"))
10752 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
10754 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10755 "TARGET_SH4A_FP && flag_unsafe_math_optimizations
10756 && operands[2] == sh_fsca_int2sf ()"
10758 [(set_attr "type" "fsca")
10759 (set_attr "fp_mode" "single")])
10761 (define_expand "sinsf2"
10762 [(set (match_operand:SF 0 "nonimmediate_operand" "")
10763 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "")]
10765 "TARGET_SH4A_FP && flag_unsafe_math_optimizations"
10768 rtx scaled = gen_reg_rtx (SFmode);
10769 rtx truncated = gen_reg_rtx (SImode);
10770 rtx fsca = gen_reg_rtx (V2SFmode);
10771 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
10773 emit_sf_insn (gen_mulsf3 (scaled, operands[1], scale_reg));
10774 emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
10775 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
10776 get_fpscr_rtx ()));
10777 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 0));
10781 (define_expand "cossf2"
10782 [(set (match_operand:SF 0 "nonimmediate_operand" "")
10783 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "")]
10785 "TARGET_SH4A_FP && flag_unsafe_math_optimizations"
10788 rtx scaled = gen_reg_rtx (SFmode);
10789 rtx truncated = gen_reg_rtx (SImode);
10790 rtx fsca = gen_reg_rtx (V2SFmode);
10791 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
10793 emit_sf_insn (gen_mulsf3 (scaled, operands[1], scale_reg));
10794 emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
10795 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
10796 get_fpscr_rtx ()));
10797 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
10801 (define_expand "sindf2"
10802 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
10803 (unspec:DF [(match_operand:DF 1 "fp_arith_reg_operand" "")]
10805 "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE && flag_unsafe_math_optimizations"
10808 rtx scaled = gen_reg_rtx (DFmode);
10809 rtx truncated = gen_reg_rtx (SImode);
10810 rtx fsca = gen_reg_rtx (V2SFmode);
10811 rtx scale_reg = force_reg (DFmode, sh_fsca_df2int ());
10812 rtx sfresult = gen_reg_rtx (SFmode);
10814 emit_df_insn (gen_muldf3 (scaled, operands[1], scale_reg));
10815 emit_df_insn (gen_fix_truncdfsi2 (truncated, scaled));
10816 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
10817 get_fpscr_rtx ()));
10818 emit_move_insn (sfresult, gen_rtx_SUBREG (SFmode, fsca, 0));
10819 emit_df_insn (gen_extendsfdf2 (operands[0], sfresult));
10823 (define_expand "cosdf2"
10824 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
10825 (unspec:DF [(match_operand:DF 1 "fp_arith_reg_operand" "")]
10827 "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE && flag_unsafe_math_optimizations"
10830 rtx scaled = gen_reg_rtx (DFmode);
10831 rtx truncated = gen_reg_rtx (SImode);
10832 rtx fsca = gen_reg_rtx (V2SFmode);
10833 rtx scale_reg = force_reg (DFmode, sh_fsca_df2int ());
10834 rtx sfresult = gen_reg_rtx (SFmode);
10836 emit_df_insn (gen_muldf3 (scaled, operands[1], scale_reg));
10837 emit_df_insn (gen_fix_truncdfsi2 (truncated, scaled));
10838 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
10839 get_fpscr_rtx ()));
10840 emit_move_insn (sfresult, gen_rtx_SUBREG (SFmode, fsca, 4));
10841 emit_df_insn (gen_extendsfdf2 (operands[0], sfresult));
10845 (define_expand "abssf2"
10846 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
10847 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
10848 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
10853 expand_sf_unop (&gen_abssf2_i, operands);
10858 (define_insn "*abssf2_media"
10859 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10860 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
10861 "TARGET_SHMEDIA_FPU"
10863 [(set_attr "type" "fmove_media")])
10865 (define_insn "abssf2_i"
10866 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
10867 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
10868 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
10871 [(set_attr "type" "fmove")
10872 (set_attr "fp_mode" "single")])
10874 (define_expand "adddf3"
10875 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
10876 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
10877 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
10878 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
10881 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
10883 expand_df_binop (&gen_adddf3_i, operands);
10888 (define_insn "*adddf3_media"
10889 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10890 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
10891 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
10892 "TARGET_SHMEDIA_FPU"
10893 "fadd.d %1, %2, %0"
10894 [(set_attr "type" "dfparith_media")])
10896 (define_insn "adddf3_i"
10897 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10898 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
10899 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
10900 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10901 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
10903 [(set_attr "type" "dfp_arith")
10904 (set_attr "fp_mode" "double")])
10906 (define_expand "subdf3"
10907 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
10908 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
10909 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
10910 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
10913 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
10915 expand_df_binop (&gen_subdf3_i, operands);
10920 (define_insn "*subdf3_media"
10921 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10922 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
10923 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
10924 "TARGET_SHMEDIA_FPU"
10925 "fsub.d %1, %2, %0"
10926 [(set_attr "type" "dfparith_media")])
10928 (define_insn "subdf3_i"
10929 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10930 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
10931 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
10932 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10933 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
10935 [(set_attr "type" "dfp_arith")
10936 (set_attr "fp_mode" "double")])
10938 (define_expand "muldf3"
10939 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
10940 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
10941 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
10942 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
10945 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
10947 expand_df_binop (&gen_muldf3_i, operands);
10952 (define_insn "*muldf3_media"
10953 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10954 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
10955 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
10956 "TARGET_SHMEDIA_FPU"
10957 "fmul.d %1, %2, %0"
10958 [(set_attr "type" "dfmul_media")])
10960 (define_insn "muldf3_i"
10961 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10962 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
10963 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
10964 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10965 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
10967 [(set_attr "type" "dfp_mul")
10968 (set_attr "fp_mode" "double")])
10970 (define_expand "divdf3"
10971 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
10972 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
10973 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
10974 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
10977 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
10979 expand_df_binop (&gen_divdf3_i, operands);
10984 (define_insn "*divdf3_media"
10985 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10986 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
10987 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
10988 "TARGET_SHMEDIA_FPU"
10989 "fdiv.d %1, %2, %0"
10990 [(set_attr "type" "dfdiv_media")])
10992 (define_insn "divdf3_i"
10993 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
10994 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
10995 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
10996 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
10997 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
10999 [(set_attr "type" "dfdiv")
11000 (set_attr "fp_mode" "double")])
11002 (define_insn "floatdidf2"
11003 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11004 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
11005 "TARGET_SHMEDIA_FPU"
11007 [(set_attr "type" "dfpconv_media")])
11009 (define_expand "floatsidf2"
11010 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
11011 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
11012 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11015 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
11017 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1],
11018 get_fpscr_rtx ()));
11023 (define_insn "*floatsidf2_media"
11024 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11025 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
11026 "TARGET_SHMEDIA_FPU"
11028 [(set_attr "type" "dfpconv_media")])
11030 (define_insn "floatsidf2_i"
11031 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11032 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
11033 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11034 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11036 [(set_attr "type" "dfp_conv")
11037 (set_attr "fp_mode" "double")])
11039 (define_insn "fix_truncdfdi2"
11040 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
11041 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
11042 "TARGET_SHMEDIA_FPU"
11044 [(set_attr "type" "dfpconv_media")])
11046 (define_expand "fix_truncdfsi2"
11047 [(set (match_operand:SI 0 "fpul_operand" "")
11048 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
11049 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11052 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
11054 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1],
11055 get_fpscr_rtx ()));
11060 (define_insn "*fix_truncdfsi2_media"
11061 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
11062 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
11063 "TARGET_SHMEDIA_FPU"
11065 [(set_attr "type" "dfpconv_media")])
11067 (define_insn "fix_truncdfsi2_i"
11068 [(set (match_operand:SI 0 "fpul_operand" "=y")
11069 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
11070 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11071 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11073 [(set_attr "type" "dfp_conv")
11074 (set_attr "dfp_comp" "no")
11075 (set_attr "fp_mode" "double")])
11077 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
11078 ;; fix_truncdfsi2_i.
11079 ;; (define_insn "fix_truncdfsi2_i4"
11080 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
11081 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
11082 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
11083 ;; (clobber (reg:SI FPUL_REG))]
11086 ;; [(set_attr "length" "4")
11087 ;; (set_attr "fp_mode" "double")])
11090 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
11091 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
11092 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
11093 ;; (clobber (reg:SI FPUL_REG))]
11095 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
11096 ;; (use (match_dup 2))])
11097 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
11099 (define_insn "cmpgtdf_t"
11100 [(set (reg:SI T_REG)
11101 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
11102 (match_operand:DF 1 "arith_reg_operand" "f")))
11103 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11104 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11106 [(set_attr "type" "dfp_cmp")
11107 (set_attr "fp_mode" "double")])
11109 (define_insn "cmpeqdf_t"
11110 [(set (reg:SI T_REG)
11111 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
11112 (match_operand:DF 1 "arith_reg_operand" "f")))
11113 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11114 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11116 [(set_attr "type" "dfp_cmp")
11117 (set_attr "fp_mode" "double")])
11119 (define_insn "*ieee_ccmpeqdf_t"
11120 [(set (reg:SI T_REG)
11121 (ior:SI (reg:SI T_REG)
11122 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
11123 (match_operand:DF 1 "arith_reg_operand" "f"))))
11124 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11125 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11126 "* return output_ieee_ccmpeq (insn, operands);"
11127 [(set_attr "length" "4")
11128 (set_attr "fp_mode" "double")])
11130 (define_insn "cmpeqdf_media"
11131 [(set (match_operand:SI 0 "register_operand" "=r")
11132 (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
11133 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
11134 "TARGET_SHMEDIA_FPU"
11135 "fcmpeq.d %1,%2,%0"
11136 [(set_attr "type" "fcmp_media")])
11138 (define_insn "cmpgtdf_media"
11139 [(set (match_operand:SI 0 "register_operand" "=r")
11140 (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
11141 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
11142 "TARGET_SHMEDIA_FPU"
11143 "fcmpgt.d %1,%2,%0"
11144 [(set_attr "type" "fcmp_media")])
11146 (define_insn "cmpgedf_media"
11147 [(set (match_operand:SI 0 "register_operand" "=r")
11148 (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
11149 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
11150 "TARGET_SHMEDIA_FPU"
11151 "fcmpge.d %1,%2,%0"
11152 [(set_attr "type" "fcmp_media")])
11154 (define_insn "cmpundf_media"
11155 [(set (match_operand:SI 0 "register_operand" "=r")
11156 (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
11157 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
11158 "TARGET_SHMEDIA_FPU"
11159 "fcmpun.d %1,%2,%0"
11160 [(set_attr "type" "fcmp_media")])
11162 (define_expand "cbranchdf4"
11164 (if_then_else (match_operator 0 "sh_float_comparison_operator"
11165 [(match_operand:DF 1 "arith_operand" "")
11166 (match_operand:DF 2 "arith_operand" "")])
11167 (match_operand 3 "" "")
11169 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11172 if (TARGET_SHMEDIA)
11173 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
11176 sh_emit_compare_and_branch (operands, DFmode);
11181 (define_expand "negdf2"
11182 [(set (match_operand:DF 0 "arith_reg_operand" "")
11183 (neg:DF (match_operand:DF 1 "arith_reg_operand" "")))]
11184 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11187 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
11189 expand_df_unop (&gen_negdf2_i, operands);
11194 (define_insn "*negdf2_media"
11195 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11196 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
11197 "TARGET_SHMEDIA_FPU"
11199 [(set_attr "type" "fmove_media")])
11201 (define_insn "negdf2_i"
11202 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11203 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
11204 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11205 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11207 [(set_attr "type" "fmove")
11208 (set_attr "fp_mode" "double")])
11210 (define_expand "sqrtdf2"
11211 [(set (match_operand:DF 0 "arith_reg_operand" "")
11212 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "")))]
11213 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11216 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
11218 expand_df_unop (&gen_sqrtdf2_i, operands);
11223 (define_insn "*sqrtdf2_media"
11224 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11225 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
11226 "TARGET_SHMEDIA_FPU"
11228 [(set_attr "type" "dfdiv_media")])
11230 (define_insn "sqrtdf2_i"
11231 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11232 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
11233 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11234 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11236 [(set_attr "type" "dfdiv")
11237 (set_attr "fp_mode" "double")])
11239 (define_expand "absdf2"
11240 [(set (match_operand:DF 0 "arith_reg_operand" "")
11241 (abs:DF (match_operand:DF 1 "arith_reg_operand" "")))]
11242 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11245 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
11247 expand_df_unop (&gen_absdf2_i, operands);
11252 (define_insn "*absdf2_media"
11253 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11254 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
11255 "TARGET_SHMEDIA_FPU"
11257 [(set_attr "type" "fmove_media")])
11259 (define_insn "absdf2_i"
11260 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11261 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
11262 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11263 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11265 [(set_attr "type" "fmove")
11266 (set_attr "fp_mode" "double")])
11268 (define_expand "extendsfdf2"
11269 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
11270 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
11271 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11274 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
11276 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1],
11277 get_fpscr_rtx ()));
11282 (define_insn "*extendsfdf2_media"
11283 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11284 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
11285 "TARGET_SHMEDIA_FPU"
11287 [(set_attr "type" "dfpconv_media")])
11289 (define_insn "extendsfdf2_i4"
11290 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
11291 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
11292 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11293 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11295 [(set_attr "type" "fp")
11296 (set_attr "fp_mode" "double")])
11298 (define_expand "truncdfsf2"
11299 [(set (match_operand:SF 0 "fpul_operand" "")
11300 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
11301 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11304 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
11306 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1],
11307 get_fpscr_rtx ()));
11312 (define_insn "*truncdfsf2_media"
11313 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
11314 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
11315 "TARGET_SHMEDIA_FPU"
11317 [(set_attr "type" "dfpconv_media")])
11319 (define_insn "truncdfsf2_i4"
11320 [(set (match_operand:SF 0 "fpul_operand" "=y")
11321 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
11322 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
11323 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11325 [(set_attr "type" "fp")
11326 (set_attr "fp_mode" "double")])
11328 ;; Bit field extract patterns. These give better code for packed bitfields,
11329 ;; because they allow auto-increment addresses to be generated.
11331 (define_expand "insv"
11332 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
11333 (match_operand:SI 1 "immediate_operand" "")
11334 (match_operand:SI 2 "immediate_operand" ""))
11335 (match_operand:SI 3 "general_operand" ""))]
11336 "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN"
11339 rtx addr_target, orig_address, shift_reg, qi_val;
11340 HOST_WIDE_INT bitsize, size, v = 0;
11341 rtx x = operands[3];
11343 if (TARGET_SH2A && TARGET_BITOPS
11344 && (satisfies_constraint_Sbw (operands[0])
11345 || satisfies_constraint_Sbv (operands[0]))
11346 && satisfies_constraint_M (operands[1])
11347 && satisfies_constraint_K03 (operands[2]))
11349 if (satisfies_constraint_N (operands[3]))
11351 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
11354 else if (satisfies_constraint_M (operands[3]))
11356 emit_insn (gen_bset_m2a (operands[0], operands[2]));
11359 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
11360 && satisfies_constraint_M (operands[1]))
11362 emit_insn (gen_bst_m2a (operands[0], operands[2]));
11365 else if (REG_P (operands[3])
11366 && satisfies_constraint_M (operands[1]))
11368 emit_insn (gen_bld_reg (operands[3], const0_rtx));
11369 emit_insn (gen_bst_m2a (operands[0], operands[2]));
11373 /* ??? expmed doesn't care for non-register predicates. */
11374 if (! memory_operand (operands[0], VOIDmode)
11375 || ! immediate_operand (operands[1], VOIDmode)
11376 || ! immediate_operand (operands[2], VOIDmode)
11377 || ! general_operand (x, VOIDmode))
11379 /* If this isn't a 16 / 24 / 32 bit field, or if
11380 it doesn't start on a byte boundary, then fail. */
11381 bitsize = INTVAL (operands[1]);
11382 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
11383 || (INTVAL (operands[2]) % 8) != 0)
11386 size = bitsize / 8;
11387 orig_address = XEXP (operands[0], 0);
11388 shift_reg = gen_reg_rtx (SImode);
11389 if (CONST_INT_P (x))
11392 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
11396 emit_insn (gen_movsi (shift_reg, operands[3]));
11397 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
11399 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
11401 operands[0] = replace_equiv_address (operands[0], addr_target);
11402 emit_insn (gen_movqi (operands[0], qi_val));
11406 if (CONST_INT_P (x))
11408 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
11411 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
11412 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
11414 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
11415 emit_insn (gen_movqi (operands[0], qi_val));
11421 (define_insn "movua"
11422 [(set (match_operand:SI 0 "register_operand" "=z")
11423 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
11427 [(set_attr "type" "movua")])
11429 ;; We shouldn't need this, but cse replaces increments with references
11430 ;; to other regs before flow has a chance to create post_inc
11431 ;; addressing modes, and only postreload's cse_move2add brings the
11432 ;; increments back to a usable form.
11434 [(set (match_operand:SI 0 "register_operand" "")
11435 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
11436 (const_int 32) (const_int 0)))
11437 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
11438 "TARGET_SH4A_ARCH && REGNO (operands[0]) != REGNO (operands[1])"
11439 [(set (match_operand:SI 0 "register_operand" "")
11440 (sign_extract:SI (mem:SI (post_inc:SI
11441 (match_operand:SI 1 "register_operand" "")))
11442 (const_int 32) (const_int 0)))]
11445 (define_expand "extv"
11446 [(set (match_operand:SI 0 "register_operand" "")
11447 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
11448 (match_operand 2 "const_int_operand" "")
11449 (match_operand 3 "const_int_operand" "")))]
11450 "TARGET_SH4A_ARCH || TARGET_SH2A"
11452 if (TARGET_SH2A && TARGET_BITOPS
11453 && (satisfies_constraint_Sbw (operands[1])
11454 || satisfies_constraint_Sbv (operands[1]))
11455 && satisfies_constraint_M (operands[2])
11456 && satisfies_constraint_K03 (operands[3]))
11458 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
11459 if (REGNO (operands[0]) != T_REG)
11460 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
11463 if (TARGET_SH4A_ARCH
11464 && INTVAL (operands[2]) == 32
11465 && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
11466 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
11468 rtx src = adjust_address (operands[1], BLKmode, 0);
11469 set_mem_size (src, 4);
11470 emit_insn (gen_movua (operands[0], src));
11477 (define_expand "extzv"
11478 [(set (match_operand:SI 0 "register_operand" "")
11479 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
11480 (match_operand 2 "const_int_operand" "")
11481 (match_operand 3 "const_int_operand" "")))]
11482 "TARGET_SH4A_ARCH || TARGET_SH2A"
11484 if (TARGET_SH2A && TARGET_BITOPS
11485 && (satisfies_constraint_Sbw (operands[1])
11486 || satisfies_constraint_Sbv (operands[1]))
11487 && satisfies_constraint_M (operands[2])
11488 && satisfies_constraint_K03 (operands[3]))
11490 emit_insn (gen_bld_m2a (operands[1], operands[3]));
11491 if (REGNO (operands[0]) != T_REG)
11492 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
11495 if (TARGET_SH4A_ARCH
11496 && INTVAL (operands[2]) == 32
11497 && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
11498 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
11500 rtx src = adjust_address (operands[1], BLKmode, 0);
11501 set_mem_size (src, 4);
11502 emit_insn (gen_movua (operands[0], src));
11509 ;; SH2A instructions for bitwise operations.
11511 ;; Clear a bit in a memory location.
11512 (define_insn "bclr_m2a"
11513 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
11515 (not:QI (ashift:QI (const_int 1)
11516 (match_operand:QI 1 "const_int_operand" "K03,K03")))
11518 "TARGET_SH2A && TARGET_BITOPS"
11521 bclr.b\\t%1,@(0,%t0)"
11522 [(set_attr "length" "4,4")])
11524 (define_insn "bclrmem_m2a"
11525 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
11526 (and:QI (match_dup 0)
11527 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
11528 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
11531 bclr.b\\t%W1,@(0,%t0)"
11532 [(set_attr "length" "4,4")])
11534 ;; Set a bit in a memory location.
11535 (define_insn "bset_m2a"
11536 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
11538 (ashift:QI (const_int 1)
11539 (match_operand:QI 1 "const_int_operand" "K03,K03"))
11541 "TARGET_SH2A && TARGET_BITOPS"
11544 bset.b\\t%1,@(0,%t0)"
11545 [(set_attr "length" "4,4")])
11547 (define_insn "bsetmem_m2a"
11548 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
11549 (ior:QI (match_dup 0)
11550 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
11551 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
11554 bset.b\\t%V1,@(0,%t0)"
11555 [(set_attr "length" "4,4")])
11557 ;;; Transfer the contents of the T bit to a specified bit of memory.
11558 (define_insn "bst_m2a"
11559 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
11560 (if_then_else (eq (reg:SI T_REG) (const_int 0))
11562 (not:QI (ashift:QI (const_int 1)
11563 (match_operand:QI 1 "const_int_operand" "K03,K03")))
11566 (ashift:QI (const_int 1) (match_dup 1))
11568 "TARGET_SH2A && TARGET_BITOPS"
11571 bst.b\\t%1,@(0,%t0)"
11572 [(set_attr "length" "4")])
11574 ;; Store a specified bit of memory in the T bit.
11575 (define_insn "bld_m2a"
11576 [(set (reg:SI T_REG)
11578 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
11580 (match_operand 1 "const_int_operand" "K03,K03")))]
11581 "TARGET_SH2A && TARGET_BITOPS"
11584 bld.b\\t%1,@(0,%t0)"
11585 [(set_attr "length" "4,4")])
11587 ;; Store a specified bit of memory in the T bit.
11588 (define_insn "bldsign_m2a"
11589 [(set (reg:SI T_REG)
11591 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
11593 (match_operand 1 "const_int_operand" "K03,K03")))]
11594 "TARGET_SH2A && TARGET_BITOPS"
11597 bld.b\\t%1,@(0,%t0)"
11598 [(set_attr "length" "4,4")])
11600 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
11601 (define_insn "bld_reg"
11602 [(set (reg:SI T_REG)
11603 (zero_extract:SI (match_operand:SI 0 "arith_reg_operand" "r")
11605 (match_operand 1 "const_int_operand" "K03")))]
11609 (define_insn "*bld_regqi"
11610 [(set (reg:SI T_REG)
11611 (zero_extract:SI (match_operand:QI 0 "arith_reg_operand" "r")
11613 (match_operand 1 "const_int_operand" "K03")))]
11617 ;; Take logical and of a specified bit of memory with the T bit and
11618 ;; store its result in the T bit.
11619 (define_insn "band_m2a"
11620 [(set (reg:SI T_REG)
11621 (and:SI (reg:SI T_REG)
11623 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
11625 (match_operand 1 "const_int_operand" "K03,K03"))))]
11626 "TARGET_SH2A && TARGET_BITOPS"
11629 band.b\\t%1,@(0,%t0)"
11630 [(set_attr "length" "4,4")])
11632 (define_insn "bandreg_m2a"
11633 [(set (match_operand:SI 0 "register_operand" "=r,r")
11634 (and:SI (zero_extract:SI
11635 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
11637 (match_operand 2 "const_int_operand" "K03,K03"))
11638 (match_operand:SI 3 "register_operand" "r,r")))]
11639 "TARGET_SH2A && TARGET_BITOPS"
11641 band.b\\t%2,%1\;movt\\t%0
11642 band.b\\t%2,@(0,%t1)\;movt\\t%0"
11643 [(set_attr "length" "6,6")])
11645 ;; Take logical or of a specified bit of memory with the T bit and
11646 ;; store its result in the T bit.
11647 (define_insn "bor_m2a"
11648 [(set (reg:SI T_REG)
11649 (ior:SI (reg:SI T_REG)
11651 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
11653 (match_operand 1 "const_int_operand" "K03,K03"))))]
11654 "TARGET_SH2A && TARGET_BITOPS"
11657 bor.b\\t%1,@(0,%t0)"
11658 [(set_attr "length" "4,4")])
11660 (define_insn "borreg_m2a"
11661 [(set (match_operand:SI 0 "register_operand" "=r,r")
11662 (ior:SI (zero_extract:SI
11663 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
11665 (match_operand 2 "const_int_operand" "K03,K03"))
11666 (match_operand:SI 3 "register_operand" "=r,r")))]
11667 "TARGET_SH2A && TARGET_BITOPS"
11669 bor.b\\t%2,%1\;movt\\t%0
11670 bor.b\\t%2,@(0,%t1)\;movt\\t%0"
11671 [(set_attr "length" "6,6")])
11673 ;; Take exclusive or of a specified bit of memory with the T bit and
11674 ;; store its result in the T bit.
11675 (define_insn "bxor_m2a"
11676 [(set (reg:SI T_REG)
11677 (xor:SI (reg:SI T_REG)
11679 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
11681 (match_operand 1 "const_int_operand" "K03,K03"))))]
11682 "TARGET_SH2A && TARGET_BITOPS"
11685 bxor.b\\t%1,@(0,%t0)"
11686 [(set_attr "length" "4,4")])
11688 (define_insn "bxorreg_m2a"
11689 [(set (match_operand:SI 0 "register_operand" "=r,r")
11690 (xor:SI (zero_extract:SI
11691 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
11693 (match_operand 2 "const_int_operand" "K03,K03"))
11694 (match_operand:SI 3 "register_operand" "=r,r")))]
11695 "TARGET_SH2A && TARGET_BITOPS"
11697 bxor.b\\t%2,%1\;movt\\t%0
11698 bxor.b\\t%2,@(0,%t1)\;movt\\t%0"
11699 [(set_attr "length" "6,6")])
11702 ;; -------------------------------------------------------------------------
11704 ;; -------------------------------------------------------------------------
11705 ;; This matches cases where the bit in a memory location is set.
11707 [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
11708 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
11710 (ior:SI (match_dup 0)
11711 (match_operand:SI 2 "const_int_operand" "Pso,Pso")))
11713 (match_operand 3 "arith_reg_operand" "r,r"))]
11714 "TARGET_SH2A && TARGET_BITOPS
11715 && satisfies_constraint_Pso (operands[2])
11716 && REGNO (operands[0]) == REGNO (operands[3])"
11717 [(set (match_dup 1)
11718 (ior:QI (match_dup 1)
11722 ;; This matches cases where the bit in a memory location is cleared.
11724 [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
11725 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
11727 (and:SI (match_dup 0)
11728 (match_operand:SI 2 "const_int_operand" "Psz,Psz")))
11730 (match_operand 3 "arith_reg_operand" "r,r"))]
11731 "TARGET_SH2A && TARGET_BITOPS
11732 && satisfies_constraint_Psz (operands[2])
11733 && REGNO (operands[0]) == REGNO (operands[3])"
11734 [(set (match_dup 1)
11735 (and:QI (match_dup 1)
11739 ;; This matches cases where a stack pointer increment at the start of the
11740 ;; epilogue combines with a stack slot read loading the return value.
11743 [(set (match_operand:SI 0 "arith_reg_operand" "")
11744 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
11745 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
11746 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
11749 ;; See the comment on the dt combiner pattern above.
11752 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
11753 (plus:SI (match_dup 0)
11755 (set (reg:SI T_REG)
11756 (eq:SI (match_dup 0)
11761 ;; The following peepholes fold load sequences for which reload was not
11762 ;; able to generate a displacement addressing move insn.
11763 ;; This can happen when reload has to transform a move insn
11764 ;; without displacement into one with displacement. Or when reload can't
11765 ;; fit a displacement into the insn's constraints. In the latter case, the
11766 ;; load destination reg remains at r0, which reload compensates by inserting
11767 ;; another mov insn.
11771 ;; mov.b @(r0,r15),r0
11774 ;; mov.b @(54,r15),r3
11777 [(set (match_operand:SI 0 "arith_reg_dest" "")
11778 (match_operand:SI 1 "const_int_operand" ""))
11779 (set (match_operand:SI 2 "arith_reg_dest" "")
11781 (mem:QI (plus:SI (match_dup 0)
11782 (match_operand:SI 3 "arith_reg_operand" "")))))
11783 (set (match_operand:QI 4 "arith_reg_dest" "")
11784 (match_operand:QI 5 "arith_reg_operand" ""))]
11786 && CONST_OK_FOR_K12 (INTVAL (operands[1]))
11787 && REGNO (operands[2]) == REGNO (operands[5])
11788 && peep2_reg_dead_p (3, operands[5])"
11789 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
11794 ;; mov.b @(r0,r15),r1
11796 ;; mov.b @(54,r15),r1
11799 [(set (match_operand:SI 0 "arith_reg_dest" "")
11800 (match_operand:SI 1 "const_int_operand" ""))
11801 (set (match_operand:SI 2 "arith_reg_dest" "")
11803 (mem:QI (plus:SI (match_dup 0)
11804 (match_operand:SI 3 "arith_reg_operand" "")))))]
11806 && CONST_OK_FOR_K12 (INTVAL (operands[1]))
11807 && (peep2_reg_dead_p (2, operands[0])
11808 || REGNO (operands[0]) == REGNO (operands[2]))"
11809 [(set (match_dup 2)
11810 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
11814 ;; mov.b @(r0,r15),r0
11817 ;; mov.b @(r0,r15),r3
11820 [(set (match_operand:SI 0 "arith_reg_dest" "")
11822 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
11823 (match_operand:SI 2 "arith_reg_operand" "")))))
11824 (set (match_operand:QI 3 "arith_reg_dest" "")
11825 (match_operand:QI 4 "arith_reg_operand" ""))]
11827 && REGNO (operands[0]) == REGNO (operands[4])
11828 && peep2_reg_dead_p (2, operands[0])"
11829 [(set (match_dup 3)
11830 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
11833 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
11834 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
11835 ;; reload when the constant is too large for a reg+offset address.
11837 ;; ??? We would get much better code if this was done in reload. This would
11838 ;; require modifying find_reloads_address to recognize that if the constant
11839 ;; is out-of-range for an immediate add, then we get better code by reloading
11840 ;; the constant into a register than by reloading the sum into a register,
11841 ;; since the former is one instruction shorter if the address does not need
11842 ;; to be offsettable. Unfortunately this does not work, because there is
11843 ;; only one register, r0, that can be used as an index register. This register
11844 ;; is also the function return value register. So, if we try to force reload
11845 ;; to use double-reg addresses, then we end up with some instructions that
11846 ;; need to use r0 twice. The only way to fix this is to change the calling
11847 ;; convention so that r0 is not used to return values.
11850 [(set (match_operand:SI 0 "register_operand" "=r")
11851 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11852 (set (mem:SI (match_dup 0))
11853 (match_operand:SI 2 "general_movsrc_operand" ""))]
11854 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
11855 "mov.l %2,@(%0,%1)")
11858 [(set (match_operand:SI 0 "register_operand" "=r")
11859 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11860 (set (match_operand:SI 2 "general_movdst_operand" "")
11861 (mem:SI (match_dup 0)))]
11862 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
11863 "mov.l @(%0,%1),%2")
11866 [(set (match_operand:SI 0 "register_operand" "=r")
11867 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11868 (set (mem:HI (match_dup 0))
11869 (match_operand:HI 2 "general_movsrc_operand" ""))]
11870 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
11871 "mov.w %2,@(%0,%1)")
11874 [(set (match_operand:SI 0 "register_operand" "=r")
11875 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11876 (set (match_operand:HI 2 "general_movdst_operand" "")
11877 (mem:HI (match_dup 0)))]
11878 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
11879 "mov.w @(%0,%1),%2")
11882 [(set (match_operand:SI 0 "register_operand" "=r")
11883 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11884 (set (mem:QI (match_dup 0))
11885 (match_operand:QI 2 "general_movsrc_operand" ""))]
11886 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
11887 "mov.b %2,@(%0,%1)")
11890 [(set (match_operand:SI 0 "register_operand" "=r")
11891 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11892 (set (match_operand:QI 2 "general_movdst_operand" "")
11893 (mem:QI (match_dup 0)))]
11894 "TARGET_SH1 && REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
11895 "mov.b @(%0,%1),%2")
11898 [(set (match_operand:SI 0 "register_operand" "=r")
11899 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11900 (set (mem:SF (match_dup 0))
11901 (match_operand:SF 2 "general_movsrc_operand" ""))]
11902 "TARGET_SH1 && REGNO (operands[0]) == 0
11903 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
11904 || (GET_CODE (operands[2]) == SUBREG
11905 && REGNO (SUBREG_REG (operands[2])) < 16))
11906 && reg_unused_after (operands[0], insn)"
11907 "mov.l %2,@(%0,%1)")
11910 [(set (match_operand:SI 0 "register_operand" "=r")
11911 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11912 (set (match_operand:SF 2 "general_movdst_operand" "")
11914 (mem:SF (match_dup 0)))]
11915 "TARGET_SH1 && REGNO (operands[0]) == 0
11916 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
11917 || (GET_CODE (operands[2]) == SUBREG
11918 && REGNO (SUBREG_REG (operands[2])) < 16))
11919 && reg_unused_after (operands[0], insn)"
11920 "mov.l @(%0,%1),%2")
11923 [(set (match_operand:SI 0 "register_operand" "=r")
11924 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11925 (set (mem:SF (match_dup 0))
11926 (match_operand:SF 2 "general_movsrc_operand" ""))]
11927 "TARGET_SH2E && REGNO (operands[0]) == 0
11928 && ((REG_P (operands[2])
11929 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
11930 || (GET_CODE (operands[2]) == SUBREG
11931 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
11932 && reg_unused_after (operands[0], insn)"
11933 "fmov{.s|} %2,@(%0,%1)")
11936 [(set (match_operand:SI 0 "register_operand" "=r")
11937 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
11938 (set (match_operand:SF 2 "general_movdst_operand" "")
11940 (mem:SF (match_dup 0)))]
11941 "TARGET_SH2E && REGNO (operands[0]) == 0
11942 && ((REG_P (operands[2])
11943 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
11944 || (GET_CODE (operands[2]) == SUBREG
11945 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
11946 && reg_unused_after (operands[0], insn)"
11947 "fmov{.s|} @(%0,%1),%2")
11949 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
11950 (define_insn "sp_switch_1"
11951 [(const_int 1) (match_operand:SI 0 "symbol_ref_operand" "s")]
11955 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", operands);
11956 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", operands);
11957 return \"mov r0,r15\";
11959 [(set_attr "length" "10")])
11961 ;; Switch back to the original stack for interrupt functions with the
11962 ;; sp_switch attribute. */
11963 (define_insn "sp_switch_2"
11966 "mov.l @r15+,r15\;mov.l @r15+,r0"
11967 [(set_attr "length" "4")])
11969 ;; Integer vector moves
11971 (define_expand "movv8qi"
11972 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
11973 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
11975 "{ if (prepare_move_operands (operands, V8QImode)) DONE; }")
11977 (define_insn "movv8qi_i"
11978 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
11979 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
11981 && (register_operand (operands[0], V8QImode)
11982 || sh_register_operand (operands[1], V8QImode))"
11989 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
11990 (set_attr "length" "4,4,16,4,4")])
11993 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
11994 (subreg:V8QI (const_int 0) 0))]
11996 [(set (match_dup 0)
11997 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
11998 (const_int 0) (const_int 0) (const_int 0)
11999 (const_int 0) (const_int 0)]))])
12002 [(set (match_operand 0 "arith_reg_dest" "")
12003 (match_operand 1 "sh_rep_vec" ""))]
12004 "TARGET_SHMEDIA && reload_completed
12005 && GET_MODE (operands[0]) == GET_MODE (operands[1])
12006 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
12007 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
12008 && (XVECEXP (operands[1], 0, 0) != const0_rtx
12009 || XVECEXP (operands[1], 0, 1) != const0_rtx)
12010 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
12011 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
12012 [(set (match_dup 0) (match_dup 1))
12016 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
12017 rtx elt1 = XVECEXP (operands[1], 0, 1);
12020 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
12024 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
12025 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
12027 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
12028 operands[1] = XVECEXP (operands[1], 0, 0);
12031 if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
12033 = GEN_INT (TARGET_LITTLE_ENDIAN
12034 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
12035 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
12038 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
12040 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
12046 [(set (match_operand 0 "arith_reg_dest" "")
12047 (match_operand 1 "sh_const_vec" ""))]
12048 "TARGET_SHMEDIA && reload_completed
12049 && GET_MODE (operands[0]) == GET_MODE (operands[1])
12050 && sh_vector_mode_supported_p (GET_MODE (operands[0]))"
12051 [(set (match_dup 0) (match_dup 1))]
12054 rtx v = operands[1];
12055 enum machine_mode new_mode
12056 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
12058 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
12060 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
12063 (define_expand "movv2hi"
12064 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
12065 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
12067 "{ if (prepare_move_operands (operands, V2HImode)) DONE; }")
12069 (define_insn "movv2hi_i"
12070 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
12071 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
12073 && (register_operand (operands[0], V2HImode)
12074 || sh_register_operand (operands[1], V2HImode))"
12081 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
12082 (set_attr "length" "4,4,16,4,4")
12083 (set (attr "highpart")
12084 (cond [(match_test "sh_contains_memref_p (insn)")
12085 (const_string "user")]
12086 (const_string "ignore")))])
12088 (define_expand "movv4hi"
12089 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
12090 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
12092 "{ if (prepare_move_operands (operands, V4HImode)) DONE; }")
12094 (define_insn "movv4hi_i"
12095 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
12096 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
12098 && (register_operand (operands[0], V4HImode)
12099 || sh_register_operand (operands[1], V4HImode))"
12106 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
12107 (set_attr "length" "4,4,16,4,4")
12108 (set_attr "highpart" "depend")])
12110 (define_expand "movv2si"
12111 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
12112 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
12114 "{ if (prepare_move_operands (operands, V2SImode)) DONE; }")
12116 (define_insn "movv2si_i"
12117 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
12118 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
12120 && (register_operand (operands[0], V2SImode)
12121 || sh_register_operand (operands[1], V2SImode))"
12128 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
12129 (set_attr "length" "4,4,16,4,4")
12130 (set_attr "highpart" "depend")])
12132 ;; Multimedia Intrinsics
12134 (define_insn "absv2si2"
12135 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12136 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
12139 [(set_attr "type" "mcmp_media")
12140 (set_attr "highpart" "depend")])
12142 (define_insn "absv4hi2"
12143 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12144 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
12147 [(set_attr "type" "mcmp_media")
12148 (set_attr "highpart" "depend")])
12150 (define_insn "addv2si3"
12151 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12152 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
12153 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
12155 "madd.l %1, %2, %0"
12156 [(set_attr "type" "arith_media")
12157 (set_attr "highpart" "depend")])
12159 (define_insn "addv4hi3"
12160 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12161 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
12162 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
12164 "madd.w %1, %2, %0"
12165 [(set_attr "type" "arith_media")
12166 (set_attr "highpart" "depend")])
12168 (define_insn_and_split "addv2hi3"
12169 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
12170 (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r")
12171 (match_operand:V2HI 2 "extend_reg_operand" "r")))]
12178 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
12179 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
12180 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
12181 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
12182 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
12184 emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1));
12185 emit_insn (gen_truncdisi2 (si_dst, di_dst));
12188 [(set_attr "highpart" "must_split")])
12190 (define_insn "ssaddv2si3"
12191 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12192 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
12193 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
12195 "madds.l %1, %2, %0"
12196 [(set_attr "type" "mcmp_media")
12197 (set_attr "highpart" "depend")])
12199 (define_insn "usaddv8qi3"
12200 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
12201 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
12202 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
12204 "madds.ub %1, %2, %0"
12205 [(set_attr "type" "mcmp_media")
12206 (set_attr "highpart" "depend")])
12208 (define_insn "ssaddv4hi3"
12209 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12210 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
12211 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
12213 "madds.w %1, %2, %0"
12214 [(set_attr "type" "mcmp_media")
12215 (set_attr "highpart" "depend")])
12217 (define_insn "negcmpeqv8qi"
12218 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
12219 (neg:V8QI (eq:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
12220 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
12222 "mcmpeq.b %N1, %N2, %0"
12223 [(set_attr "type" "mcmp_media")
12224 (set_attr "highpart" "depend")])
12226 (define_insn "negcmpeqv2si"
12227 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12228 (neg:V2SI (eq:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
12229 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
12231 "mcmpeq.l %N1, %N2, %0"
12232 [(set_attr "type" "mcmp_media")
12233 (set_attr "highpart" "depend")])
12235 (define_insn "negcmpeqv4hi"
12236 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12237 (neg:V4HI (eq:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
12238 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
12240 "mcmpeq.w %N1, %N2, %0"
12241 [(set_attr "type" "mcmp_media")
12242 (set_attr "highpart" "depend")])
12244 (define_insn "negcmpgtuv8qi"
12245 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
12246 (neg:V8QI (gtu:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
12247 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
12249 "mcmpgt.ub %N1, %N2, %0"
12250 [(set_attr "type" "mcmp_media")
12251 (set_attr "highpart" "depend")])
12253 (define_insn "negcmpgtv2si"
12254 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12255 (neg:V2SI (gt:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
12256 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
12258 "mcmpgt.l %N1, %N2, %0"
12259 [(set_attr "type" "mcmp_media")
12260 (set_attr "highpart" "depend")])
12262 (define_insn "negcmpgtv4hi"
12263 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12264 (neg:V4HI (gt:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
12265 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
12267 "mcmpgt.w %N1, %N2, %0"
12268 [(set_attr "type" "mcmp_media")
12269 (set_attr "highpart" "depend")])
12271 (define_insn "mcmv"
12272 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
12273 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12274 (match_operand:DI 2 "arith_reg_operand" "r"))
12275 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
12276 (not:DI (match_dup 2)))))]
12279 [(set_attr "type" "arith_media")
12280 (set_attr "highpart" "depend")])
12282 (define_insn "mcnvs_lw"
12283 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12285 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
12286 (ss_truncate:V2HI (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
12288 "mcnvs.lw %N1, %N2, %0"
12289 [(set_attr "type" "mcmp_media")])
12291 (define_insn "mcnvs_wb"
12292 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
12294 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
12295 (ss_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
12297 "mcnvs.wb %N1, %N2, %0"
12298 [(set_attr "type" "mcmp_media")])
12300 (define_insn "mcnvs_wub"
12301 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
12303 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
12304 (us_truncate:V4QI (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
12306 "mcnvs.wub %N1, %N2, %0"
12307 [(set_attr "type" "mcmp_media")])
12309 (define_insn "mextr_rl"
12310 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
12311 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12312 (match_operand:HI 3 "mextr_bit_offset" "i"))
12313 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
12314 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
12315 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
12318 static char templ[21];
12320 sprintf (templ, \"mextr%d\\t%%N1, %%N2, %%0\",
12321 (int) INTVAL (operands[3]) >> 3);
12324 [(set_attr "type" "arith_media")])
12326 (define_insn "*mextr_lr"
12327 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
12328 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12329 (match_operand:HI 3 "mextr_bit_offset" "i"))
12330 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
12331 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
12332 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
12335 static char templ[21];
12337 sprintf (templ, \"mextr%d\\t%%N2, %%N1, %%0\",
12338 (int) INTVAL (operands[4]) >> 3);
12341 [(set_attr "type" "arith_media")])
12343 ; mextrN can be modelled with vec_select / vec_concat, but the selection
12344 ; vector then varies depending on endianness.
12345 (define_expand "mextr1"
12346 [(match_operand:DI 0 "arith_reg_dest" "")
12347 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12348 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
12352 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
12353 GEN_INT (1 * 8), GEN_INT (7 * 8)));
12357 (define_expand "mextr2"
12358 [(match_operand:DI 0 "arith_reg_dest" "")
12359 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12360 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
12364 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
12365 GEN_INT (2 * 8), GEN_INT (6 * 8)));
12369 (define_expand "mextr3"
12370 [(match_operand:DI 0 "arith_reg_dest" "")
12371 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12372 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
12376 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
12377 GEN_INT (3 * 8), GEN_INT (5 * 8)));
12381 (define_expand "mextr4"
12382 [(match_operand:DI 0 "arith_reg_dest" "")
12383 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12384 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
12388 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
12389 GEN_INT (4 * 8), GEN_INT (4 * 8)));
12393 (define_expand "mextr5"
12394 [(match_operand:DI 0 "arith_reg_dest" "")
12395 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12396 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
12400 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
12401 GEN_INT (5 * 8), GEN_INT (3 * 8)));
12405 (define_expand "mextr6"
12406 [(match_operand:DI 0 "arith_reg_dest" "")
12407 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12408 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
12412 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
12413 GEN_INT (6 * 8), GEN_INT (2 * 8)));
12417 (define_expand "mextr7"
12418 [(match_operand:DI 0 "arith_reg_dest" "")
12419 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
12420 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
12424 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
12425 GEN_INT (7 * 8), GEN_INT (1 * 8)));
12429 (define_expand "mmacfx_wl"
12430 [(match_operand:V2SI 0 "arith_reg_dest" "")
12431 (match_operand:V2HI 1 "extend_reg_operand" "")
12432 (match_operand:V2HI 2 "extend_reg_operand" "")
12433 (match_operand:V2SI 3 "arith_reg_operand" "")]
12437 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
12438 operands[1], operands[2]));
12442 ;; This could be highpart ignore if it only had inputs 2 or 3, but input 1
12444 (define_insn "mmacfx_wl_i"
12445 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12447 (match_operand:V2SI 1 "arith_reg_operand" "0")
12452 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
12453 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
12456 "mmacfx.wl %2, %3, %0"
12457 [(set_attr "type" "mac_media")
12458 (set_attr "highpart" "depend")])
12460 (define_expand "mmacnfx_wl"
12461 [(match_operand:V2SI 0 "arith_reg_dest" "")
12462 (match_operand:V2HI 1 "extend_reg_operand" "")
12463 (match_operand:V2HI 2 "extend_reg_operand" "")
12464 (match_operand:V2SI 3 "arith_reg_operand" "")]
12468 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
12469 operands[1], operands[2]));
12473 (define_insn "mmacnfx_wl_i"
12474 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12476 (match_operand:V2SI 1 "arith_reg_operand" "0")
12481 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
12482 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
12485 "mmacnfx.wl %2, %3, %0"
12486 [(set_attr "type" "mac_media")
12487 (set_attr "highpart" "depend")])
12489 (define_insn "mulv2si3"
12490 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12491 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
12492 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
12494 "mmul.l %1, %2, %0"
12495 [(set_attr "type" "d2mpy_media")
12496 (set_attr "highpart" "depend")])
12498 (define_insn "mulv4hi3"
12499 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12500 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
12501 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
12503 "mmul.w %1, %2, %0"
12504 [(set_attr "type" "dmpy_media")
12505 (set_attr "highpart" "depend")])
12507 (define_insn "mmulfx_l"
12508 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12512 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
12513 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
12516 "mmulfx.l %1, %2, %0"
12517 [(set_attr "type" "d2mpy_media")
12518 (set_attr "highpart" "depend")])
12520 (define_insn "mmulfx_w"
12521 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12525 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
12526 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
12529 "mmulfx.w %1, %2, %0"
12530 [(set_attr "type" "dmpy_media")
12531 (set_attr "highpart" "depend")])
12533 (define_insn "mmulfxrp_w"
12534 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12539 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
12540 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
12544 "mmulfxrp.w %1, %2, %0"
12545 [(set_attr "type" "dmpy_media")
12546 (set_attr "highpart" "depend")])
12549 (define_expand "mmulhi_wl"
12550 [(match_operand:V2SI 0 "arith_reg_dest" "")
12551 (match_operand:V4HI 1 "arith_reg_operand" "")
12552 (match_operand:V4HI 2 "arith_reg_operand" "")]
12556 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
12557 (operands[0], operands[1], operands[2]));
12561 (define_expand "mmullo_wl"
12562 [(match_operand:V2SI 0 "arith_reg_dest" "")
12563 (match_operand:V4HI 1 "arith_reg_operand" "")
12564 (match_operand:V4HI 2 "arith_reg_operand" "")]
12568 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
12569 (operands[0], operands[1], operands[2]));
12573 (define_insn "mmul23_wl"
12574 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12577 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
12578 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
12579 (parallel [(const_int 2) (const_int 3)])))]
12581 "* return (TARGET_LITTLE_ENDIAN
12582 ? \"mmulhi.wl %1, %2, %0\"
12583 : \"mmullo.wl %1, %2, %0\");"
12584 [(set_attr "type" "dmpy_media")
12585 (set (attr "highpart")
12586 (cond [(eq_attr "endian" "big") (const_string "ignore")]
12587 (const_string "user")))])
12589 (define_insn "mmul01_wl"
12590 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12593 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
12594 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
12595 (parallel [(const_int 0) (const_int 1)])))]
12597 "* return (TARGET_LITTLE_ENDIAN
12598 ? \"mmullo.wl %1, %2, %0\"
12599 : \"mmulhi.wl %1, %2, %0\");"
12600 [(set_attr "type" "dmpy_media")
12601 (set (attr "highpart")
12602 (cond [(eq_attr "endian" "little") (const_string "ignore")]
12603 (const_string "user")))])
12606 (define_expand "mmulsum_wq"
12607 [(match_operand:DI 0 "arith_reg_dest" "")
12608 (match_operand:V4HI 1 "arith_reg_operand" "")
12609 (match_operand:V4HI 2 "arith_reg_operand" "")
12610 (match_operand:DI 3 "arith_reg_operand" "")]
12614 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
12615 operands[1], operands[2]));
12619 (define_insn "mmulsum_wq_i"
12620 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
12621 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
12626 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
12627 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
12628 (parallel [(const_int 0)]))
12629 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
12630 (sign_extend:V4DI (match_dup 3)))
12631 (parallel [(const_int 1)])))
12633 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
12634 (sign_extend:V4DI (match_dup 3)))
12635 (parallel [(const_int 2)]))
12636 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
12637 (sign_extend:V4DI (match_dup 3)))
12638 (parallel [(const_int 3)]))))))]
12640 "mmulsum.wq %2, %3, %0"
12641 [(set_attr "type" "mac_media")])
12643 (define_expand "mperm_w"
12644 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
12645 (match_operand:V4HI 1 "arith_reg_operand" "r")
12646 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
12650 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
12651 (operands[0], operands[1], operands[2]));
12655 ; This use of vec_select isn't exactly correct according to rtl.texi
12656 ; (because not constant), but it seems a straightforward extension.
12657 (define_insn "mperm_w_little"
12658 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12660 (match_operand:V4HI 1 "arith_reg_operand" "r")
12662 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
12663 (const_int 2) (const_int 0))
12664 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
12665 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
12666 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
12667 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
12668 "mperm.w %1, %N2, %0"
12669 [(set_attr "type" "arith_media")])
12671 (define_insn "mperm_w_big"
12672 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12674 (match_operand:V4HI 1 "arith_reg_operand" "r")
12676 [(zero_extract:QI (not:QI (match_operand:QI 2
12677 "extend_reg_or_0_operand" "rZ"))
12678 (const_int 2) (const_int 0))
12679 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
12680 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
12681 (zero_extract:QI (not:QI (match_dup 2))
12682 (const_int 2) (const_int 6))])))]
12683 "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
12684 "mperm.w %1, %N2, %0"
12685 [(set_attr "type" "arith_media")])
12687 (define_insn "mperm_w0"
12688 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12689 (vec_duplicate:V4HI (truncate:HI (match_operand 1
12690 "trunc_hi_operand" "r"))))]
12692 "mperm.w %1, r63, %0"
12693 [(set_attr "type" "arith_media")
12694 (set_attr "highpart" "ignore")])
12696 (define_expand "msad_ubq"
12697 [(match_operand:DI 0 "arith_reg_dest" "")
12698 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
12699 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
12700 (match_operand:DI 3 "arith_reg_operand" "")]
12704 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
12705 operands[1], operands[2]));
12709 (define_insn "msad_ubq_i"
12710 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
12715 (match_operand:DI 1 "arith_reg_operand" "0")
12716 (abs:DI (vec_select:DI
12719 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
12721 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
12722 (parallel [(const_int 0)]))))
12723 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
12724 (zero_extend:V8DI (match_dup 3)))
12725 (parallel [(const_int 1)]))))
12727 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
12728 (zero_extend:V8DI (match_dup 3)))
12729 (parallel [(const_int 2)])))
12730 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
12731 (zero_extend:V8DI (match_dup 3)))
12732 (parallel [(const_int 3)])))))
12735 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
12736 (zero_extend:V8DI (match_dup 3)))
12737 (parallel [(const_int 4)])))
12738 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
12739 (zero_extend:V8DI (match_dup 3)))
12740 (parallel [(const_int 5)]))))
12742 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
12743 (zero_extend:V8DI (match_dup 3)))
12744 (parallel [(const_int 6)])))
12745 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
12746 (zero_extend:V8DI (match_dup 3)))
12747 (parallel [(const_int 7)])))))))]
12749 "msad.ubq %N2, %N3, %0"
12750 [(set_attr "type" "mac_media")])
12752 (define_insn "mshalds_l"
12753 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12756 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
12757 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
12758 (const_int 31)))))]
12760 "mshalds.l %1, %2, %0"
12761 [(set_attr "type" "mcmp_media")
12762 (set_attr "highpart" "depend")])
12764 (define_insn "mshalds_w"
12765 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12768 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
12769 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
12770 (const_int 15)))))]
12772 "mshalds.w %1, %2, %0"
12773 [(set_attr "type" "mcmp_media")
12774 (set_attr "highpart" "depend")])
12776 (define_insn "ashrv2si3"
12777 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12778 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
12779 (match_operand:DI 2 "arith_reg_operand" "r")))]
12781 "mshard.l %1, %2, %0"
12782 [(set_attr "type" "arith_media")
12783 (set_attr "highpart" "depend")])
12785 (define_insn "ashrv4hi3"
12786 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12787 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
12788 (match_operand:DI 2 "arith_reg_operand" "r")))]
12790 "mshard.w %1, %2, %0"
12791 [(set_attr "type" "arith_media")
12792 (set_attr "highpart" "depend")])
12794 (define_insn "mshards_q"
12795 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
12797 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
12798 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
12800 "mshards.q %1, %N2, %0"
12801 [(set_attr "type" "mcmp_media")])
12803 (define_expand "mshfhi_b"
12804 [(match_operand:V8QI 0 "arith_reg_dest" "")
12805 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
12806 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
12810 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
12811 (operands[0], operands[1], operands[2]));
12815 (define_expand "mshflo_b"
12816 [(match_operand:V8QI 0 "arith_reg_dest" "")
12817 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
12818 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
12822 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
12823 (operands[0], operands[1], operands[2]));
12827 (define_insn "mshf4_b"
12829 (match_operand:V8QI 0 "arith_reg_dest" "=r")
12831 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
12832 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
12833 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
12834 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
12836 "* return (TARGET_LITTLE_ENDIAN
12837 ? \"mshfhi.b %N1, %N2, %0\"
12838 : \"mshflo.b %N1, %N2, %0\");"
12839 [(set_attr "type" "arith_media")
12840 (set (attr "highpart")
12841 (cond [(eq_attr "endian" "big") (const_string "ignore")]
12842 (const_string "user")))])
12844 (define_insn "mshf0_b"
12846 (match_operand:V8QI 0 "arith_reg_dest" "=r")
12848 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
12849 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
12850 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
12851 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
12853 "* return (TARGET_LITTLE_ENDIAN
12854 ? \"mshflo.b %N1, %N2, %0\"
12855 : \"mshfhi.b %N1, %N2, %0\");"
12856 [(set_attr "type" "arith_media")
12857 (set (attr "highpart")
12858 (cond [(eq_attr "endian" "little") (const_string "ignore")]
12859 (const_string "user")))])
12861 (define_expand "mshfhi_l"
12862 [(match_operand:V2SI 0 "arith_reg_dest" "")
12863 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
12864 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
12868 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
12869 (operands[0], operands[1], operands[2]));
12873 (define_expand "mshflo_l"
12874 [(match_operand:V2SI 0 "arith_reg_dest" "")
12875 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
12876 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
12880 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
12881 (operands[0], operands[1], operands[2]));
12885 (define_insn "mshf4_l"
12886 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12888 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
12889 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
12890 (parallel [(const_int 1) (const_int 3)])))]
12892 "* return (TARGET_LITTLE_ENDIAN
12893 ? \"mshfhi.l %N1, %N2, %0\"
12894 : \"mshflo.l %N1, %N2, %0\");"
12895 [(set_attr "type" "arith_media")
12896 (set (attr "highpart")
12897 (cond [(eq_attr "endian" "big") (const_string "ignore")]
12898 (const_string "user")))])
12900 (define_insn "mshf0_l"
12901 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
12903 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
12904 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
12905 (parallel [(const_int 0) (const_int 2)])))]
12907 "* return (TARGET_LITTLE_ENDIAN
12908 ? \"mshflo.l %N1, %N2, %0\"
12909 : \"mshfhi.l %N1, %N2, %0\");"
12910 [(set_attr "type" "arith_media")
12911 (set (attr "highpart")
12912 (cond [(eq_attr "endian" "little") (const_string "ignore")]
12913 (const_string "user")))])
12915 (define_expand "mshfhi_w"
12916 [(match_operand:V4HI 0 "arith_reg_dest" "")
12917 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
12918 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
12922 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
12923 (operands[0], operands[1], operands[2]));
12927 (define_expand "mshflo_w"
12928 [(match_operand:V4HI 0 "arith_reg_dest" "")
12929 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
12930 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
12934 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
12935 (operands[0], operands[1], operands[2]));
12939 (define_insn "mshf4_w"
12940 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12942 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
12943 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
12944 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
12946 "* return (TARGET_LITTLE_ENDIAN
12947 ? \"mshfhi.w %N1, %N2, %0\"
12948 : \"mshflo.w %N1, %N2, %0\");"
12949 [(set_attr "type" "arith_media")
12950 (set (attr "highpart")
12951 (cond [(eq_attr "endian" "big") (const_string "ignore")]
12952 (const_string "user")))])
12954 (define_insn "mshf0_w"
12955 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12957 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
12958 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
12959 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
12961 "* return (TARGET_LITTLE_ENDIAN
12962 ? \"mshflo.w %N1, %N2, %0\"
12963 : \"mshfhi.w %N1, %N2, %0\");"
12964 [(set_attr "type" "arith_media")
12965 (set (attr "highpart")
12966 (cond [(eq_attr "endian" "little") (const_string "ignore")]
12967 (const_string "user")))])
12969 (define_insn "mshflo_w_x"
12970 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
12972 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
12973 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
12974 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
12976 "mshflo.w %N1, %N2, %0"
12977 [(set_attr "type" "arith_media")
12978 (set_attr "highpart" "ignore")])
12980 ;; These are useful to expand ANDs and as combiner patterns.
12981 (define_insn_and_split "mshfhi_l_di"
12982 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
12983 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
12985 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
12986 (const_int -4294967296))))]
12989 mshfhi.l %N1, %N2, %0
12991 "TARGET_SHMEDIA && reload_completed
12992 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
12993 [(set (match_dup 3) (match_dup 4))
12994 (set (match_dup 5) (match_dup 6))]
12997 operands[3] = gen_lowpart (SImode, operands[0]);
12998 operands[4] = gen_highpart (SImode, operands[1]);
12999 operands[5] = gen_highpart (SImode, operands[0]);
13000 operands[6] = gen_highpart (SImode, operands[2]);
13002 [(set_attr "type" "arith_media")])
13004 (define_insn "*mshfhi_l_di_rev"
13005 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13006 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
13007 (const_int -4294967296))
13008 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
13011 "mshfhi.l %N2, %N1, %0"
13012 [(set_attr "type" "arith_media")])
13015 [(set (match_operand:DI 0 "arith_reg_dest" "")
13016 (ior:DI (zero_extend:DI (match_operand:SI 1
13017 "extend_reg_or_0_operand" ""))
13018 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
13019 (const_int -4294967296))))
13020 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
13025 emit_insn (gen_ashldi3_media (operands[3],
13026 simplify_gen_subreg (DImode, operands[1],
13029 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
13033 (define_insn "mshflo_l_di"
13034 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13035 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
13036 (const_int 4294967295))
13037 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
13041 "mshflo.l %N1, %N2, %0"
13042 [(set_attr "type" "arith_media")
13043 (set_attr "highpart" "ignore")])
13045 (define_insn "*mshflo_l_di_rev"
13046 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13047 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
13049 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
13050 (const_int 4294967295))))]
13053 "mshflo.l %N2, %N1, %0"
13054 [(set_attr "type" "arith_media")
13055 (set_attr "highpart" "ignore")])
13057 ;; Combiner pattern for trampoline initialization.
13058 (define_insn_and_split "*double_shori"
13059 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13060 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
13062 (match_operand:DI 2 "const_int_operand" "n")))]
13064 && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
13066 "rtx_equal_p (operands[0], operands[1])"
13070 HOST_WIDE_INT v = INTVAL (operands[2]);
13072 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16)));
13073 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535)));
13076 [(set_attr "highpart" "ignore")])
13079 (define_insn "*mshflo_l_di_x"
13080 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13081 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
13083 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
13087 "mshflo.l %N1, %N2, %0"
13088 [(set_attr "type" "arith_media")
13089 (set_attr "highpart" "ignore")])
13091 (define_insn_and_split "concat_v2sf"
13092 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
13093 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
13094 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
13095 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
13099 mshflo.l %N1, %N2, %0
13102 "TARGET_SHMEDIA && reload_completed
13103 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
13104 [(set (match_dup 3) (match_dup 1))
13105 (set (match_dup 4) (match_dup 2))]
13108 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
13109 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
13111 [(set_attr "type" "arith_media")
13112 (set_attr "highpart" "ignore")])
13114 (define_insn "*mshflo_l_di_x_rev"
13115 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13116 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
13118 (zero_extend:DI (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
13121 "mshflo.l %N2, %N1, %0"
13122 [(set_attr "type" "arith_media")
13123 (set_attr "highpart" "ignore")])
13125 (define_insn "ashlv2si3"
13126 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
13127 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
13128 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
13130 "mshlld.l %1, %2, %0"
13131 [(set_attr "type" "arith_media")
13132 (set_attr "highpart" "depend")])
13135 [(set (match_operand 0 "any_register_operand" "")
13136 (match_operator 3 "shift_operator"
13137 [(match_operand 1 "any_register_operand" "")
13138 (match_operand 2 "shift_count_reg_operand" "")]))]
13139 "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)"
13140 [(set (match_dup 0) (match_dup 3))]
13143 rtx count = operands[2];
13144 enum machine_mode outer_mode = GET_MODE (operands[2]), inner_mode;
13146 while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND
13147 || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0)
13148 || GET_CODE (count) == TRUNCATE)
13149 count = XEXP (count, 0);
13150 inner_mode = GET_MODE (count);
13151 count = simplify_gen_subreg (outer_mode, count, inner_mode,
13152 subreg_lowpart_offset (outer_mode, inner_mode));
13153 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
13154 operands[1], count);
13157 (define_insn "ashlv4hi3"
13158 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
13159 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
13160 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
13162 "mshlld.w %1, %2, %0"
13163 [(set_attr "type" "arith_media")
13164 (set_attr "highpart" "depend")])
13166 (define_insn "lshrv2si3"
13167 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
13168 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
13169 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
13171 "mshlrd.l %1, %2, %0"
13172 [(set_attr "type" "arith_media")
13173 (set_attr "highpart" "depend")])
13175 (define_insn "lshrv4hi3"
13176 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
13177 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
13178 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
13180 "mshlrd.w %1, %2, %0"
13181 [(set_attr "type" "arith_media")
13182 (set_attr "highpart" "depend")])
13184 (define_insn "subv2si3"
13185 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
13186 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
13187 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
13189 "msub.l %N1, %2, %0"
13190 [(set_attr "type" "arith_media")
13191 (set_attr "highpart" "depend")])
13193 (define_insn "subv4hi3"
13194 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
13195 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
13196 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
13198 "msub.w %N1, %2, %0"
13199 [(set_attr "type" "arith_media")
13200 (set_attr "highpart" "depend")])
13202 (define_insn_and_split "subv2hi3"
13203 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
13204 (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ")
13205 (match_operand:V2HI 2 "arith_reg_operand" "r")))]
13212 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
13213 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
13214 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
13215 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
13216 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
13218 emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1));
13219 emit_insn (gen_truncdisi2 (si_dst, di_dst));
13222 [(set_attr "highpart" "must_split")])
13224 (define_insn "sssubv2si3"
13225 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
13226 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
13227 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
13229 "msubs.l %N1, %2, %0"
13230 [(set_attr "type" "mcmp_media")
13231 (set_attr "highpart" "depend")])
13233 (define_insn "ussubv8qi3"
13234 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
13235 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
13236 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
13238 "msubs.ub %N1, %2, %0"
13239 [(set_attr "type" "mcmp_media")
13240 (set_attr "highpart" "depend")])
13242 (define_insn "sssubv4hi3"
13243 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
13244 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
13245 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
13247 "msubs.w %N1, %2, %0"
13248 [(set_attr "type" "mcmp_media")
13249 (set_attr "highpart" "depend")])
13251 ;; Floating Point Intrinsics
13253 (define_insn "fcosa_s"
13254 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13255 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
13259 [(set_attr "type" "atrans_media")])
13261 (define_insn "fsina_s"
13262 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13263 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
13267 [(set_attr "type" "atrans_media")])
13269 (define_insn "fipr"
13270 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13271 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
13272 "fp_arith_reg_operand" "f")
13273 (match_operand:V4SF 2
13274 "fp_arith_reg_operand" "f"))
13275 (parallel [(const_int 0)]))
13276 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
13277 (parallel [(const_int 1)])))
13278 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
13279 (parallel [(const_int 2)]))
13280 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
13281 (parallel [(const_int 3)])))))]
13283 "fipr.s %1, %2, %0"
13284 [(set_attr "type" "fparith_media")])
13286 (define_insn "fsrra_s"
13287 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13288 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
13292 [(set_attr "type" "atrans_media")])
13294 (define_insn "ftrv"
13295 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
13299 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
13300 (parallel [(const_int 0) (const_int 5)
13301 (const_int 10) (const_int 15)]))
13302 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
13304 (vec_select:V4SF (match_dup 1)
13305 (parallel [(const_int 4) (const_int 9)
13306 (const_int 14) (const_int 3)]))
13307 (vec_select:V4SF (match_dup 2)
13308 (parallel [(const_int 1) (const_int 2)
13309 (const_int 3) (const_int 0)]))))
13312 (vec_select:V4SF (match_dup 1)
13313 (parallel [(const_int 8) (const_int 13)
13314 (const_int 2) (const_int 7)]))
13315 (vec_select:V4SF (match_dup 2)
13316 (parallel [(const_int 2) (const_int 3)
13317 (const_int 0) (const_int 1)])))
13319 (vec_select:V4SF (match_dup 1)
13320 (parallel [(const_int 12) (const_int 1)
13321 (const_int 6) (const_int 11)]))
13322 (vec_select:V4SF (match_dup 2)
13323 (parallel [(const_int 3) (const_int 0)
13324 (const_int 1) (const_int 2)]))))))]
13326 "ftrv.s %1, %2, %0"
13327 [(set_attr "type" "fparith_media")])
13329 (define_insn "ldhi_l"
13330 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
13332 (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
13335 (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1))
13339 [(set_attr "type" "load_media")])
13341 (define_insn "ldhi_q"
13342 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13344 (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
13347 (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1))
13351 [(set_attr "type" "load_media")])
13353 (define_insn_and_split "*ldhi_q_comb0"
13354 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13356 (mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 1
13357 "register_operand" "r")
13358 (match_operand:SI 2
13359 "ua_offset" "I06"))
13362 (plus:SI (and:SI (match_dup 1) (const_int 7))
13365 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
13369 "emit_insn (gen_ldhi_q (operands[0],
13370 gen_rtx_PLUS (SImode, operands[1], operands[2])));
13374 (define_insn_and_split "*ldhi_q_comb1"
13375 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13377 (mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 1
13378 "register_operand" "r")
13379 (match_operand:SI 2
13380 "ua_offset" "I06"))
13383 (plus:SI (and:SI (plus:SI (match_dup 1) (match_operand:SI 3
13384 "ua_offset" "I06"))
13388 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
13389 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
13393 "emit_insn (gen_ldhi_q (operands[0],
13394 gen_rtx_PLUS (SImode, operands[1], operands[2])));
13398 (define_insn "ldlo_l"
13399 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
13401 (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
13403 (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3)))
13404 (and:SI (match_dup 1) (const_int 3))))]
13407 [(set_attr "type" "load_media")])
13409 (define_insn "ldlo_q"
13410 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13412 (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
13414 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
13415 (and:SI (match_dup 1) (const_int 7))))]
13418 [(set_attr "type" "load_media")])
13420 (define_insn_and_split "*ldlo_q_comb0"
13421 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13423 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
13424 (match_operand:SI 2 "ua_offset" "I06"))
13426 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
13427 (and:SI (match_dup 1) (const_int 7))))]
13428 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
13432 "emit_insn (gen_ldlo_q (operands[0],
13433 gen_rtx_PLUS (SImode, operands[1], operands[2])));
13436 (define_insn_and_split "*ldlo_q_comb1"
13437 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13439 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
13440 (match_operand:SI 2 "ua_offset" "I06"))
13442 (minus:SI (const_int 8)
13443 (and:SI (plus:SI (match_dup 1)
13444 (match_operand:SI 3 "ua_offset" "I06"))
13446 (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))]
13447 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
13448 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
13452 "emit_insn (gen_ldlo_q (operands[0],
13453 gen_rtx_PLUS (SImode, operands[1], operands[2])));
13456 (define_insn "sthi_l"
13457 [(set (zero_extract:SI
13458 (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
13461 (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1))
13463 (match_operand:SI 1 "arith_reg_operand" "r"))]
13466 [(set_attr "type" "ustore_media")])
13468 ;; All unaligned stores are considered to be 'narrow' because they typically
13469 ;; operate on less that a quadword, and when they operate on a full quadword,
13470 ;; the vanilla store high / store low sequence will cause a stall if not
13471 ;; scheduled apart.
13472 (define_insn "sthi_q"
13473 [(set (zero_extract:DI
13474 (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
13477 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
13479 (match_operand:DI 1 "arith_reg_operand" "r"))]
13482 [(set_attr "type" "ustore_media")])
13484 (define_insn_and_split "*sthi_q_comb0"
13485 [(set (zero_extract:DI
13486 (mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 0
13487 "register_operand" "r")
13488 (match_operand:SI 1 "ua_offset"
13492 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
13494 (match_operand:DI 2 "arith_reg_operand" "r"))]
13495 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
13499 "emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
13503 (define_insn_and_split "*sthi_q_comb1"
13504 [(set (zero_extract:DI
13505 (mem:DI (plus:SI (ior:SI (plus:SI (match_operand:SI 0
13506 "register_operand" "r")
13507 (match_operand:SI 1 "ua_offset"
13511 (plus:SI (and:SI (plus:SI (match_dup 0)
13512 (match_operand:SI 2 "ua_offset" "I06"))
13516 (match_operand:DI 3 "arith_reg_operand" "r"))]
13517 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8)
13518 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
13522 "emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
13526 ;; This is highpart user because the address is used as full 64 bit.
13527 (define_insn "stlo_l"
13528 [(set (zero_extract:SI
13529 (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
13531 (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3)))
13532 (and:SI (match_dup 0) (const_int 3)))
13533 (match_operand:SI 1 "arith_reg_operand" "r"))]
13536 [(set_attr "type" "ustore_media")])
13538 (define_insn "stlo_q"
13539 [(set (zero_extract:DI
13540 (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
13542 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
13543 (and:SI (match_dup 0) (const_int 7)))
13544 (match_operand:DI 1 "arith_reg_operand" "r"))]
13547 [(set_attr "type" "ustore_media")])
13549 (define_insn_and_split "*stlo_q_comb0"
13550 [(set (zero_extract:DI
13551 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
13552 (match_operand:SI 1 "ua_offset" "I06"))
13554 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
13555 (and:SI (match_dup 0) (const_int 7)))
13556 (match_operand:DI 2 "arith_reg_operand" "r"))]
13557 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
13561 "emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
13565 (define_insn_and_split "*stlo_q_comb1"
13566 [(set (zero_extract:DI
13567 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
13568 (match_operand:SI 1 "ua_offset" "I06"))
13570 (minus:SI (const_int 8) (and:SI (plus:SI (match_dup 0)
13571 (match_operand:SI 2
13572 "ua_offset" "I06"))
13574 (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
13575 (match_operand:DI 3 "arith_reg_operand" "r"))]
13576 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
13580 "emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
13584 (define_insn "ldhi_l64"
13585 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
13587 (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
13590 (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1))
13594 [(set_attr "type" "load_media")])
13596 (define_insn "ldhi_q64"
13597 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13599 (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
13602 (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1))
13606 [(set_attr "type" "load_media")])
13608 (define_insn "ldlo_l64"
13609 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
13611 (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
13613 (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3)))
13614 (and:DI (match_dup 1) (const_int 3))))]
13617 [(set_attr "type" "load_media")])
13619 (define_insn "ldlo_q64"
13620 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13622 (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
13624 (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7)))
13625 (and:DI (match_dup 1) (const_int 7))))]
13628 [(set_attr "type" "load_media")])
13630 (define_insn "sthi_l64"
13631 [(set (zero_extract:SI
13632 (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
13635 (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1))
13637 (match_operand:SI 1 "arith_reg_operand" "r"))]
13640 [(set_attr "type" "ustore_media")])
13642 (define_insn "sthi_q64"
13643 [(set (zero_extract:DI
13644 (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
13647 (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1))
13649 (match_operand:DI 1 "arith_reg_operand" "r"))]
13652 [(set_attr "type" "ustore_media")])
13654 (define_insn "stlo_l64"
13655 [(set (zero_extract:SI
13656 (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
13658 (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3)))
13659 (and:DI (match_dup 0) (const_int 3)))
13660 (match_operand:SI 1 "arith_reg_operand" "r"))]
13663 [(set_attr "type" "ustore_media")])
13665 (define_insn "stlo_q64"
13666 [(set (zero_extract:DI
13667 (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
13669 (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7)))
13670 (and:DI (match_dup 0) (const_int 7)))
13671 (match_operand:DI 1 "arith_reg_operand" "r"))]
13674 [(set_attr "type" "ustore_media")])
13677 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
13678 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
13682 [(set_attr "type" "arith_media")])
13684 (define_insn "nsbsi"
13685 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
13687 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
13691 [(set_attr "type" "arith_media")])
13693 (define_insn "nsbdi"
13694 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
13696 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
13700 [(set_attr "type" "arith_media")])
13702 (define_expand "ffsdi2"
13703 [(set (match_operand:DI 0 "arith_reg_dest" "")
13704 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
13708 rtx scratch = gen_reg_rtx (DImode);
13711 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
13712 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
13713 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
13714 emit_insn (gen_nsbdi (scratch, scratch));
13715 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
13716 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
13717 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
13718 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0]));
13723 (define_expand "ffssi2"
13724 [(set (match_operand:SI 0 "arith_reg_dest" "")
13725 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
13729 rtx scratch = gen_reg_rtx (SImode);
13730 rtx discratch = gen_reg_rtx (DImode);
13733 emit_insn (gen_adddi3 (discratch,
13734 simplify_gen_subreg (DImode, operands[1], SImode, 0),
13736 emit_insn (gen_andcdi3 (discratch,
13737 simplify_gen_subreg (DImode, operands[1], SImode, 0),
13739 emit_insn (gen_nsbsi (scratch, discratch));
13740 last = emit_insn (gen_subsi3 (operands[0],
13741 force_reg (SImode, GEN_INT (63)), scratch));
13742 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0]));
13747 (define_insn "byterev"
13748 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
13749 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
13750 (parallel [(const_int 7) (const_int 6) (const_int 5)
13751 (const_int 4) (const_int 3) (const_int 2)
13752 (const_int 1) (const_int 0)])))]
13755 [(set_attr "type" "arith_media")])
13757 (define_insn "*prefetch_media"
13758 [(prefetch (match_operand:QI 0 "address_operand" "p")
13759 (match_operand:SI 1 "const_int_operand" "n")
13760 (match_operand:SI 2 "const_int_operand" "n"))]
13764 operands[0] = gen_rtx_MEM (QImode, operands[0]);
13765 output_asm_insn (\"ld%M0.b %m0,r63\", operands);
13768 [(set_attr "type" "other")])
13770 (define_insn "*prefetch_i4"
13771 [(prefetch (match_operand:SI 0 "register_operand" "r")
13772 (match_operand:SI 1 "const_int_operand" "n")
13773 (match_operand:SI 2 "const_int_operand" "n"))]
13774 "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
13777 return \"pref @%0\";
13779 [(set_attr "type" "other")])
13781 ;; In user mode, the "pref" instruction will raise a RADDERR exception
13782 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
13783 ;; implementation of __builtin_prefetch for VxWorks RTPs.
13784 (define_expand "prefetch"
13785 [(prefetch (match_operand 0 "address_operand" "p")
13786 (match_operand:SI 1 "const_int_operand" "n")
13787 (match_operand:SI 2 "const_int_operand" "n"))]
13788 "TARGET_SH2A || ((TARGET_HARD_SH4 || TARGET_SH5)
13789 && (TARGET_SHMEDIA || !TARGET_VXWORKS_RTP))"
13792 if (GET_MODE (operands[0]) != Pmode
13793 || !CONST_INT_P (operands[1])
13794 || !CONST_INT_P (operands[2]))
13796 if (! TARGET_SHMEDIA)
13797 operands[0] = force_reg (Pmode, operands[0]);
13800 (define_insn "prefetch_m2a"
13801 [(prefetch (match_operand:SI 0 "register_operand" "r")
13802 (match_operand:SI 1 "const_int_operand" "n")
13803 (match_operand:SI 2 "const_int_operand" "n"))]
13806 [(set_attr "type" "other")])
13808 (define_insn "alloco_i"
13809 [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
13810 (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
13816 if (GET_CODE (operands[0]) == PLUS)
13818 xops[0] = XEXP (operands[0], 0);
13819 xops[1] = XEXP (operands[0], 1);
13823 xops[0] = operands[0];
13824 xops[1] = const0_rtx;
13826 output_asm_insn (\"alloco %0, %1\", xops);
13829 [(set_attr "type" "other")])
13832 [(set (match_operand 0 "any_register_operand" "")
13833 (match_operand 1 "" ""))]
13834 "TARGET_SHMEDIA && reload_completed"
13835 [(set (match_dup 0) (match_dup 1))]
13840 for_each_rtx (&operands[1], shmedia_cleanup_truncate, &n_changes);
13845 ; Stack Protector Patterns
13847 (define_expand "stack_protect_set"
13848 [(set (match_operand 0 "memory_operand" "")
13849 (match_operand 1 "memory_operand" ""))]
13852 if (TARGET_SHMEDIA)
13854 if (TARGET_SHMEDIA64)
13855 emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1]));
13857 emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1]));
13860 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
13865 (define_insn "stack_protect_set_si"
13866 [(set (match_operand:SI 0 "memory_operand" "=m")
13867 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13868 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13870 "mov.l\t%1, %2\;mov.l\t%2, %0\;mov\t#0, %2"
13871 [(set_attr "type" "other")
13872 (set_attr "length" "6")])
13874 (define_insn "stack_protect_set_si_media"
13875 [(set (match_operand:SI 0 "memory_operand" "=m")
13876 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13877 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13879 "ld%M1.l\t%m1, %2\;st%M0.l\t%m0, %2\;movi\t0, %2"
13880 [(set_attr "type" "other")
13881 (set_attr "length" "12")])
13883 (define_insn "stack_protect_set_di_media"
13884 [(set (match_operand:DI 0 "memory_operand" "=m")
13885 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13886 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13888 "ld%M1.q\t%m1, %2\;st%M0.q\t%m0, %2\;movi\t0, %2"
13889 [(set_attr "type" "other")
13890 (set_attr "length" "12")])
13892 (define_expand "stack_protect_test"
13893 [(match_operand 0 "memory_operand" "")
13894 (match_operand 1 "memory_operand" "")
13895 (match_operand 2 "" "")]
13898 if (TARGET_SHMEDIA)
13900 rtx tmp = gen_reg_rtx (GET_MODE (operands[0]));
13903 test = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
13904 if (TARGET_SHMEDIA64)
13906 emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
13908 emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
13912 emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
13914 emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
13919 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
13920 emit_jump_insn (gen_branch_true (operands[2]));
13926 (define_insn "stack_protect_test_si"
13927 [(set (reg:SI T_REG)
13928 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
13929 (match_operand:SI 1 "memory_operand" "m")]
13931 (set (match_scratch:SI 2 "=&r") (const_int 0))
13932 (set (match_scratch:SI 3 "=&r") (const_int 0))]
13934 "mov.l\t%0, %2\;mov.l\t%1, %3\;cmp/eq\t%2, %3\;mov\t#0, %2\;mov\t#0, %3"
13935 [(set_attr "type" "other")
13936 (set_attr "length" "10")])
13938 (define_insn "stack_protect_test_si_media"
13939 [(set (match_operand:SI 0 "register_operand" "=&r")
13940 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
13941 (match_operand:SI 2 "memory_operand" "m")]
13943 (set (match_scratch:SI 3 "=&r") (const_int 0))]
13945 "ld%M1.l\t%m1, %0\;ld%M2.l\t%m2, %3\;cmpeq\t%0, %3, %0\;movi\t0, %3"
13946 [(set_attr "type" "other")
13947 (set_attr "length" "16")])
13949 (define_insn "stack_protect_test_di_media"
13950 [(set (match_operand:DI 0 "register_operand" "=&r")
13951 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
13952 (match_operand:DI 2 "memory_operand" "m")]
13954 (set (match_scratch:DI 3 "=&r") (const_int 0))]
13956 "ld%M1.q\t%m1, %0\;ld%M2.q\t%m2, %3\;cmpeq\t%0, %3, %0\;movi\t0, %3"
13957 [(set_attr "type" "other")
13958 (set_attr "length" "16")])
13960 (include "sync.md")