1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
102 ;; These are used with unspec.
114 ;; These are used with unspec_volatile.
120 (UNSPECV_CONST_END 11)
123 ;; -------------------------------------------------------------------------
125 ;; -------------------------------------------------------------------------
130 "sh1,sh2,sh3,sh3e,sh4"
131 (const (symbol_ref "sh_cpu_attr")))
133 (define_attr "endian" "big,little"
134 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
135 (const_string "little") (const_string "big"))))
137 ;; Indicate if the default fpu mode is single precision.
138 (define_attr "fpu_single" "yes,no"
139 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
140 (const_string "yes") (const_string "no"))))
142 (define_attr "fmovd" "yes,no"
143 (const (if_then_else (symbol_ref "TARGET_FMOVD")
144 (const_string "yes") (const_string "no"))))
146 (define_attr "issues" "1,2"
147 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
149 ;; cbranch conditional branch instructions
150 ;; jump unconditional jumps
151 ;; arith ordinary arithmetic
152 ;; arith3 a compound insn that behaves similarly to a sequence of
153 ;; three insns of type arith
154 ;; arith3b like above, but might end with a redirected branch
156 ;; load_si Likewise, SImode variant for general register.
158 ;; move register to register
159 ;; fmove register to register, floating point
160 ;; smpy word precision integer multiply
161 ;; dmpy longword or doublelongword precision integer multiply
163 ;; pload load of pr reg, which can't be put into delay slot of rts
164 ;; prset copy register to pr reg, ditto
165 ;; pstore store of pr reg, which can't be put into delay slot of jsr
166 ;; prget copy pr to register, ditto
167 ;; pcload pc relative load of constant value
168 ;; pcload_si Likewise, SImode variant for general register.
169 ;; rte return from exception
170 ;; sfunc special function call with known used registers
171 ;; call function call
173 ;; fdiv floating point divide (or square root)
174 ;; gp_fpul move between general purpose register and fpul
175 ;; dfp_arith, dfp_cmp,dfp_conv
176 ;; dfdiv double precision floating point divide (or square root)
177 ;; nil no-op move, will be deleted.
180 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
181 (const_string "other"))
183 ;; Indicate what precision must be selected in fpscr for this insn, if any.
185 (define_attr "fp_mode" "single,double,none" (const_string "none"))
187 ; If a conditional branch destination is within -252..258 bytes away
188 ; from the instruction it can be 2 bytes long. Something in the
189 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
190 ; branches are initially assumed to be 16 bytes long.
191 ; In machine_dependent_reorg, we split all branches that are longer than
194 ;; The maximum range used for SImode constant pool entries is 1018. A final
195 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
196 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
197 ;; instruction around the pool table, 2 bytes of alignment before the table,
198 ;; and 30 bytes of alignment after the table. That gives a maximum total
199 ;; pool size of 1058 bytes.
200 ;; Worst case code/pool content size ratio is 1:2 (using asms).
201 ;; Thus, in the worst case, there is one instruction in front of a maximum
202 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
203 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
204 ;; If we have a forward branch, the initial table will be put after the
205 ;; unconditional branch.
207 ;; ??? We could do much better by keeping track of the actual pcloads within
208 ;; the branch range and in the pcload range in front of the branch range.
210 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
212 (define_attr "short_cbranch_p" "no,yes"
213 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
215 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
217 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
219 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
221 ] (const_string "no")))
223 (define_attr "med_branch_p" "no,yes"
224 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
227 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
229 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
232 ] (const_string "no")))
234 (define_attr "med_cbranch_p" "no,yes"
235 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
238 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
240 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
243 ] (const_string "no")))
245 (define_attr "braf_branch_p" "no,yes"
246 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
248 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
251 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
253 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
256 ] (const_string "no")))
258 (define_attr "braf_cbranch_p" "no,yes"
259 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
261 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
264 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
266 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
269 ] (const_string "no")))
271 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
272 ; For wider ranges, we need a combination of a code and a data part.
273 ; If we can get a scratch register for a long range jump, the code
274 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
275 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
276 ; long; otherwise, it must be 6 bytes long.
278 ; All other instructions are two bytes long by default.
280 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
281 ;; but getattrtab doesn't understand this.
282 (define_attr "length" ""
283 (cond [(eq_attr "type" "cbranch")
284 (cond [(eq_attr "short_cbranch_p" "yes")
286 (eq_attr "med_cbranch_p" "yes")
288 (eq_attr "braf_cbranch_p" "yes")
290 ;; ??? using pc is not computed transitively.
291 (ne (match_dup 0) (match_dup 0))
293 (ne (symbol_ref ("flag_pic")) (const_int 0))
296 (eq_attr "type" "jump")
297 (cond [(eq_attr "med_branch_p" "yes")
299 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
301 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
302 (symbol_ref "code_for_indirect_jump_scratch")))
303 (if_then_else (eq_attr "braf_branch_p" "yes")
306 (eq_attr "braf_branch_p" "yes")
308 ;; ??? using pc is not computed transitively.
309 (ne (match_dup 0) (match_dup 0))
311 (ne (symbol_ref ("flag_pic")) (const_int 0))
316 ;; (define_function_unit {name} {num-units} {n-users} {test}
317 ;; {ready-delay} {issue-delay} [{conflict-list}])
319 ;; Load and store instructions save a cycle if they are aligned on a
320 ;; four byte boundary. Using a function unit for stores encourages
321 ;; gcc to separate load and store instructions by one instruction,
322 ;; which makes it more likely that the linker will be able to word
323 ;; align them when relaxing.
325 ;; Loads have a latency of two.
326 ;; However, call insns can have a delay slot, so that we want one more
327 ;; insn to be scheduled between the load of the function address and the call.
328 ;; This is equivalent to a latency of three.
329 ;; We cannot use a conflict list for this, because we need to distinguish
330 ;; between the actual call address and the function arguments.
331 ;; ADJUST_COST can only properly handle reductions of the cost, so we
332 ;; use a latency of three here.
333 ;; We only do this for SImode loads of general registers, to make the work
334 ;; for ADJUST_COST easier.
335 (define_function_unit "memory" 1 0
336 (and (eq_attr "issues" "1")
337 (eq_attr "type" "load_si,pcload_si"))
339 (define_function_unit "memory" 1 0
340 (and (eq_attr "issues" "1")
341 (eq_attr "type" "load,pcload,pload,store,pstore"))
344 (define_function_unit "int" 1 0
345 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
347 (define_function_unit "int" 1 0
348 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
350 (define_function_unit "int" 1 0
351 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
353 ;; ??? These are approximations.
354 (define_function_unit "mpy" 1 0
355 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
356 (define_function_unit "mpy" 1 0
357 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
359 (define_function_unit "fp" 1 0
360 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
361 (define_function_unit "fp" 1 0
362 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
366 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
367 ;; costs by at least two.
368 ;; There will be single increments of the modeled that don't correspond
369 ;; to the actual target ;; whenever two insns to be issued depend one a
370 ;; single resource, and the scheduler picks to be the first one.
371 ;; If we multiplied the costs just by two, just two of these single
372 ;; increments would amount to an actual cycle. By picking a larger
373 ;; factor, we can ameliorate the effect; However, we then have to make sure
374 ;; that only two insns are modeled as issued per actual cycle.
375 ;; Moreover, we need a way to specify the latency of insns that don't
376 ;; use an actual function unit.
377 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
379 (define_function_unit "issue" 2 0
380 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
383 (define_function_unit "issue" 2 0
384 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
387 ;; There is no point in providing exact scheduling information about branches,
388 ;; because they are at the starts / ends of basic blocks anyways.
390 ;; Some insns cannot be issued before/after another insn in the same cycle,
391 ;; irrespective of the type of the other insn.
393 ;; default is dual-issue, but can't be paired with an insn that
394 ;; uses multiple function units.
395 (define_function_unit "single_issue" 1 0
396 (and (eq_attr "issues" "2")
397 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
399 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
401 (define_function_unit "single_issue" 1 0
402 (and (eq_attr "issues" "2")
403 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
407 ;; arith3 insns are always pairable at the start, but not inecessarily at
408 ;; the end; however, there doesn;t seem to be a way to express that.
409 (define_function_unit "single_issue" 1 0
410 (and (eq_attr "issues" "2")
411 (eq_attr "type" "arith3"))
415 ;; arith3b insn are pairable at the end and have latency that prevents pairing
416 ;; with the following branch, but we don't want this latency be respected;
417 ;; When the following branch is immediately adjacent, we can redirect the
418 ;; internal branch, which is likly to be a larger win.
419 (define_function_unit "single_issue" 1 0
420 (and (eq_attr "issues" "2")
421 (eq_attr "type" "arith3b"))
425 ;; calls introduce a longisch delay that is likely to flush the pipelines.
426 (define_function_unit "single_issue" 1 0
427 (and (eq_attr "issues" "2")
428 (eq_attr "type" "call,sfunc"))
430 [(eq_attr "type" "!call") (eq_attr "type" "call")])
432 ;; Load and store instructions have no alignment peculiarities for the SH4,
433 ;; but they use the load-store unit, which they share with the fmove type
434 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
435 ;; Loads have a latency of two.
436 ;; However, call insns can only paired with a preceding insn, and have
437 ;; a delay slot, so that we want two more insns to be scheduled between the
438 ;; load of the function address and the call. This is equivalent to a
440 ;; We cannot use a conflict list for this, because we need to distinguish
441 ;; between the actual call address and the function arguments.
442 ;; ADJUST_COST can only properly handle reductions of the cost, so we
443 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
444 ;; We only do this for SImode loads of general registers, to make the work
445 ;; for ADJUST_COST easier.
447 ;; When specifying different latencies for different insns using the
448 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
449 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
450 ;; for an executing insn E and a candidate insn C.
451 ;; Therefore, we define three different function units for load_store:
452 ;; load_store, load and load_si.
454 (define_function_unit "load_si" 1 0
455 (and (eq_attr "issues" "2")
456 (eq_attr "type" "load_si,pcload_si")) 30 10)
457 (define_function_unit "load" 1 0
458 (and (eq_attr "issues" "2")
459 (eq_attr "type" "load,pcload,pload")) 20 10)
460 (define_function_unit "load_store" 1 0
461 (and (eq_attr "issues" "2")
462 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
465 (define_function_unit "int" 1 0
466 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
468 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
469 ;; spurious FIFO constraint; the multiply instructions use the "int"
470 ;; unit actually only for two cycles.
471 (define_function_unit "int" 1 0
472 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
474 ;; We use a fictous "mpy" unit to express the actual latency.
475 (define_function_unit "mpy" 1 0
476 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
478 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
479 ;; spurious FIFO constraint.
480 (define_function_unit "int" 1 0
481 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
483 ;; We use a fictous "gp_fpul" unit to express the actual latency.
484 (define_function_unit "gp_fpul" 1 0
485 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
487 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
488 ;; Thus, a simple single-precision fp operation could finish if issued in
489 ;; the very next cycle, but stalls when issued two or three cycles later.
490 ;; Similarily, a divide / sqrt can work without stalls if issued in
491 ;; the very next cycle, while it would have to block if issued two or
492 ;; three cycles later.
493 ;; There is no way to model this with gcc's function units. This problem is
494 ;; actually mentioned in md.texi. Tackling this problem requires first that
495 ;; it is possible to speak about the target in an open discussion.
497 ;; However, simple double-precision operations always conflict.
499 (define_function_unit "fp" 1 0
500 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
501 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
503 ;; The "fp" unit is for pipeline stages F1 and F2.
505 (define_function_unit "fp" 1 0
506 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
508 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
509 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
511 (define_function_unit "fp" 1 0
512 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
514 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
515 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
516 ;; We also use it to give the actual latency here.
517 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
518 ;; but that will hardly matter in practice for scheduling.
519 (define_function_unit "fdiv" 1 0
520 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
522 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
523 ;; that we can't express.
525 (define_function_unit "fp" 1 0
526 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
528 (define_function_unit "fp" 1 0
529 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
531 (define_function_unit "fp" 1 0
532 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
534 (define_function_unit "fdiv" 1 0
535 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
537 ; Definitions for filling branch delay slots.
539 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
541 ;; ??? This should be (nil) instead of (const_int 0)
542 (define_attr "hit_stack" "yes,no"
543 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
546 (const_string "yes")))
548 (define_attr "interrupt_function" "no,yes"
549 (const (symbol_ref "pragma_interrupt")))
551 (define_attr "in_delay_slot" "yes,no"
552 (cond [(eq_attr "type" "cbranch") (const_string "no")
553 (eq_attr "type" "pcload,pcload_si") (const_string "no")
554 (eq_attr "needs_delay_slot" "yes") (const_string "no")
555 (eq_attr "length" "2") (const_string "yes")
556 ] (const_string "no")))
558 (define_attr "is_sfunc" ""
559 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
562 (eq_attr "needs_delay_slot" "yes")
563 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
565 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
566 ;; and thus we can't put a pop instruction in its delay slot.
567 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
568 ;; instruction can go in the delay slot.
570 ;; Since a normal return (rts) implicitly uses the PR register,
571 ;; we can't allow PR register loads in an rts delay slot.
574 (eq_attr "type" "return")
575 [(and (eq_attr "in_delay_slot" "yes")
576 (ior (and (eq_attr "interrupt_function" "no")
577 (eq_attr "type" "!pload,prset"))
578 (and (eq_attr "interrupt_function" "yes")
579 (eq_attr "hit_stack" "no")))) (nil) (nil)])
581 ;; Since a call implicitly uses the PR register, we can't allow
582 ;; a PR register store in a jsr delay slot.
585 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
586 [(and (eq_attr "in_delay_slot" "yes")
587 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
589 ;; Say that we have annulled true branches, since this gives smaller and
590 ;; faster code when branches are predicted as not taken.
593 (and (eq_attr "type" "cbranch")
594 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
595 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
597 ;; -------------------------------------------------------------------------
598 ;; SImode signed integer comparisons
599 ;; -------------------------------------------------------------------------
603 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
604 (match_operand:SI 1 "arith_operand" "L,r"))
609 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
610 ;; That would still allow reload to create cmpi instructions, but would
611 ;; perhaps allow forcing the constant into a register when that is better.
612 ;; Probably should use r0 for mem/imm compares, but force constant into a
613 ;; register for pseudo/imm compares.
615 (define_insn "cmpeqsi_t"
617 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
618 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
625 (define_insn "cmpgtsi_t"
627 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
628 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
634 (define_insn "cmpgesi_t"
636 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
637 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
643 ;; -------------------------------------------------------------------------
644 ;; SImode unsigned integer comparisons
645 ;; -------------------------------------------------------------------------
647 (define_insn "cmpgeusi_t"
649 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
650 (match_operand:SI 1 "arith_reg_operand" "r")))]
654 (define_insn "cmpgtusi_t"
656 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
657 (match_operand:SI 1 "arith_reg_operand" "r")))]
661 ;; We save the compare operands in the cmpxx patterns and use them when
662 ;; we generate the branch.
664 (define_expand "cmpsi"
666 (compare (match_operand:SI 0 "arith_operand" "")
667 (match_operand:SI 1 "arith_operand" "")))]
671 sh_compare_op0 = operands[0];
672 sh_compare_op1 = operands[1];
676 ;; -------------------------------------------------------------------------
677 ;; DImode signed integer comparisons
678 ;; -------------------------------------------------------------------------
680 ;; ??? Could get better scheduling by splitting the initial test from the
681 ;; rest of the insn after reload. However, the gain would hardly justify
682 ;; the sh.md size increase necessary to do that.
686 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
687 (match_operand:DI 1 "arith_operand" "r"))
690 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
692 [(set_attr "length" "6")
693 (set_attr "type" "arith3b")])
695 (define_insn "cmpeqdi_t"
697 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
698 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
701 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
702 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
703 [(set_attr "length" "6")
704 (set_attr "type" "arith3b")])
708 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
709 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
710 ;; If we applied this split when not optimizing, it would only be
711 ;; applied during the machine-dependent reorg, when no new basic blocks
713 "reload_completed && optimize"
714 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
715 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
716 (label_ref (match_dup 6))
718 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
723 = gen_rtx_REG (SImode,
724 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
726 = (operands[1] == const0_rtx
728 : gen_rtx_REG (SImode,
729 true_regnum (operands[1])
730 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
731 operands[4] = gen_lowpart (SImode, operands[0]);
732 operands[5] = gen_lowpart (SImode, operands[1]);
733 operands[6] = gen_label_rtx ();
736 (define_insn "cmpgtdi_t"
738 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
739 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
742 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
743 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
744 [(set_attr "length" "8")
745 (set_attr "type" "arith3")])
747 (define_insn "cmpgedi_t"
749 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
750 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
753 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
755 [(set_attr "length" "8,2")
756 (set_attr "type" "arith3,arith")])
758 ;; -------------------------------------------------------------------------
759 ;; DImode unsigned integer comparisons
760 ;; -------------------------------------------------------------------------
762 (define_insn "cmpgeudi_t"
764 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
765 (match_operand:DI 1 "arith_reg_operand" "r")))]
767 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
768 [(set_attr "length" "8")
769 (set_attr "type" "arith3")])
771 (define_insn "cmpgtudi_t"
773 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
774 (match_operand:DI 1 "arith_reg_operand" "r")))]
776 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
777 [(set_attr "length" "8")
778 (set_attr "type" "arith3")])
780 ;; We save the compare operands in the cmpxx patterns and use them when
781 ;; we generate the branch.
783 (define_expand "cmpdi"
785 (compare (match_operand:DI 0 "arith_operand" "")
786 (match_operand:DI 1 "arith_operand" "")))]
790 sh_compare_op0 = operands[0];
791 sh_compare_op1 = operands[1];
795 ;; -------------------------------------------------------------------------
796 ;; Addition instructions
797 ;; -------------------------------------------------------------------------
799 ;; ??? This should be a define expand.
801 (define_insn "adddi3"
802 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
803 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
804 (match_operand:DI 2 "arith_reg_operand" "r")))
805 (clobber (reg:SI T_REG))]
808 [(set_attr "length" "6")])
811 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
812 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
813 (match_operand:DI 2 "arith_reg_operand" "r")))
814 (clobber (reg:SI T_REG))]
819 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
820 high0 = gen_rtx_REG (SImode,
821 true_regnum (operands[0])
822 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
823 high2 = gen_rtx_REG (SImode,
824 true_regnum (operands[2])
825 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
826 emit_insn (gen_clrt ());
827 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
828 emit_insn (gen_addc1 (high0, high0, high2));
833 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
834 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
835 (match_operand:SI 2 "arith_reg_operand" "r"))
838 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
841 [(set_attr "type" "arith")])
844 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
845 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
846 (match_operand:SI 2 "arith_reg_operand" "r"))
848 (clobber (reg:SI T_REG))]
851 [(set_attr "type" "arith")])
853 (define_insn "addsi3"
854 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
855 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
856 (match_operand:SI 2 "arith_operand" "rI")))]
859 [(set_attr "type" "arith")])
861 ;; -------------------------------------------------------------------------
862 ;; Subtraction instructions
863 ;; -------------------------------------------------------------------------
865 ;; ??? This should be a define expand.
867 (define_insn "subdi3"
868 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
869 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
870 (match_operand:DI 2 "arith_reg_operand" "r")))
871 (clobber (reg:SI T_REG))]
874 [(set_attr "length" "6")])
877 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
878 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
879 (match_operand:DI 2 "arith_reg_operand" "r")))
880 (clobber (reg:SI T_REG))]
885 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
886 high0 = gen_rtx_REG (SImode,
887 true_regnum (operands[0])
888 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
889 high2 = gen_rtx_REG (SImode,
890 true_regnum (operands[2])
891 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
892 emit_insn (gen_clrt ());
893 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
894 emit_insn (gen_subc1 (high0, high0, high2));
899 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
900 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
901 (match_operand:SI 2 "arith_reg_operand" "r"))
904 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
907 [(set_attr "type" "arith")])
910 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
911 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
912 (match_operand:SI 2 "arith_reg_operand" "r"))
914 (clobber (reg:SI T_REG))]
917 [(set_attr "type" "arith")])
919 (define_insn "*subsi3_internal"
920 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
921 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
922 (match_operand:SI 2 "arith_reg_operand" "r")))]
925 [(set_attr "type" "arith")])
927 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
928 ;; will sometimes save one instruction. Otherwise we might get
929 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
932 (define_expand "subsi3"
933 [(set (match_operand:SI 0 "arith_reg_operand" "")
934 (minus:SI (match_operand:SI 1 "arith_operand" "")
935 (match_operand:SI 2 "arith_reg_operand" "")))]
939 if (GET_CODE (operands[1]) == CONST_INT)
941 emit_insn (gen_negsi2 (operands[0], operands[2]));
942 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
947 ;; -------------------------------------------------------------------------
948 ;; Division instructions
949 ;; -------------------------------------------------------------------------
951 ;; We take advantage of the library routines which don't clobber as many
952 ;; registers as a normal function call would.
954 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
955 ;; also has an effect on the register that holds the address of the sfunc.
956 ;; To make this work, we have an extra dummy insns that shows the use
957 ;; of this register for reorg.
959 (define_insn "use_sfunc_addr"
960 [(set (reg:SI PR_REG)
961 (unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
964 [(set_attr "length" "0")])
966 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
967 ;; hard register 0. If we used hard register 0, then the next instruction
968 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
969 ;; gets allocated to a stack slot that needs its address reloaded, then
970 ;; there is nothing to prevent reload from using r0 to reload the address.
971 ;; This reload would clobber the value in r0 we are trying to store.
972 ;; If we let reload allocate r0, then this problem can never happen.
974 (define_insn "udivsi3_i1"
975 [(set (match_operand:SI 0 "register_operand" "=z")
976 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
977 (clobber (reg:SI T_REG))
978 (clobber (reg:SI PR_REG))
979 (clobber (reg:SI R4_REG))
980 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
983 [(set_attr "type" "sfunc")
984 (set_attr "needs_delay_slot" "yes")])
986 (define_insn "udivsi3_i4"
987 [(set (match_operand:SI 0 "register_operand" "=y")
988 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
989 (clobber (reg:SI T_REG))
990 (clobber (reg:SI PR_REG))
991 (clobber (reg:DF DR0_REG))
992 (clobber (reg:DF DR2_REG))
993 (clobber (reg:DF DR4_REG))
994 (clobber (reg:SI R0_REG))
995 (clobber (reg:SI R1_REG))
996 (clobber (reg:SI R4_REG))
997 (clobber (reg:SI R5_REG))
998 (use (reg:PSI FPSCR_REG))
999 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1000 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1002 [(set_attr "type" "sfunc")
1003 (set_attr "fp_mode" "double")
1004 (set_attr "needs_delay_slot" "yes")])
1006 (define_insn "udivsi3_i4_single"
1007 [(set (match_operand:SI 0 "register_operand" "=y")
1008 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1009 (clobber (reg:SI T_REG))
1010 (clobber (reg:SI PR_REG))
1011 (clobber (reg:DF DR0_REG))
1012 (clobber (reg:DF DR2_REG))
1013 (clobber (reg:DF DR4_REG))
1014 (clobber (reg:SI R0_REG))
1015 (clobber (reg:SI R1_REG))
1016 (clobber (reg:SI R4_REG))
1017 (clobber (reg:SI R5_REG))
1018 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1019 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1021 [(set_attr "type" "sfunc")
1022 (set_attr "needs_delay_slot" "yes")])
1024 (define_expand "udivsi3"
1025 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1026 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1027 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1028 (parallel [(set (match_operand:SI 0 "register_operand" "")
1029 (udiv:SI (reg:SI R4_REG)
1031 (clobber (reg:SI T_REG))
1032 (clobber (reg:SI PR_REG))
1033 (clobber (reg:SI R4_REG))
1034 (use (match_dup 3))])]
1040 operands[3] = gen_reg_rtx(SImode);
1041 /* Emit the move of the address to a pseudo outside of the libcall. */
1042 if (TARGET_HARD_SH4 && TARGET_SH3E)
1044 emit_move_insn (operands[3],
1045 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
1046 if (TARGET_FPU_SINGLE)
1047 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1049 last = gen_udivsi3_i4 (operands[0], operands[3]);
1053 emit_move_insn (operands[3],
1054 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
1055 last = gen_udivsi3_i1 (operands[0], operands[3]);
1057 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1058 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1059 last = emit_insn (last);
1060 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1061 invariant code motion can move it. */
1062 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1063 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1067 (define_insn "divsi3_i1"
1068 [(set (match_operand:SI 0 "register_operand" "=z")
1069 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1070 (clobber (reg:SI T_REG))
1071 (clobber (reg:SI PR_REG))
1072 (clobber (reg:SI R1_REG))
1073 (clobber (reg:SI R2_REG))
1074 (clobber (reg:SI R3_REG))
1075 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1078 [(set_attr "type" "sfunc")
1079 (set_attr "needs_delay_slot" "yes")])
1081 (define_insn "divsi3_i4"
1082 [(set (match_operand:SI 0 "register_operand" "=y")
1083 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1084 (clobber (reg:SI PR_REG))
1085 (clobber (reg:DF DR0_REG))
1086 (clobber (reg:DF DR2_REG))
1087 (use (reg:PSI FPSCR_REG))
1088 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1089 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1091 [(set_attr "type" "sfunc")
1092 (set_attr "fp_mode" "double")
1093 (set_attr "needs_delay_slot" "yes")])
1095 (define_insn "divsi3_i4_single"
1096 [(set (match_operand:SI 0 "register_operand" "=y")
1097 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1098 (clobber (reg:SI PR_REG))
1099 (clobber (reg:DF DR0_REG))
1100 (clobber (reg:DF DR2_REG))
1101 (clobber (reg:SI R2_REG))
1102 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1103 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1105 [(set_attr "type" "sfunc")
1106 (set_attr "needs_delay_slot" "yes")])
1108 (define_expand "divsi3"
1109 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1110 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1111 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1112 (parallel [(set (match_operand:SI 0 "register_operand" "")
1113 (div:SI (reg:SI R4_REG)
1115 (clobber (reg:SI T_REG))
1116 (clobber (reg:SI PR_REG))
1117 (clobber (reg:SI R1_REG))
1118 (clobber (reg:SI R2_REG))
1119 (clobber (reg:SI R3_REG))
1120 (use (match_dup 3))])]
1126 operands[3] = gen_reg_rtx(SImode);
1127 /* Emit the move of the address to a pseudo outside of the libcall. */
1128 if (TARGET_HARD_SH4 && TARGET_SH3E)
1130 emit_move_insn (operands[3],
1131 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1132 if (TARGET_FPU_SINGLE)
1133 last = gen_divsi3_i4_single (operands[0], operands[3]);
1135 last = gen_divsi3_i4 (operands[0], operands[3]);
1139 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1140 last = gen_divsi3_i1 (operands[0], operands[3]);
1142 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1143 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1144 last = emit_insn (last);
1145 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1146 invariant code motion can move it. */
1147 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1148 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1152 ;; -------------------------------------------------------------------------
1153 ;; Multiplication instructions
1154 ;; -------------------------------------------------------------------------
1156 (define_insn "umulhisi3_i"
1157 [(set (reg:SI MACL_REG)
1158 (mult:SI (zero_extend:SI
1159 (match_operand:HI 0 "arith_reg_operand" "r"))
1161 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1164 [(set_attr "type" "smpy")])
1166 (define_insn "mulhisi3_i"
1167 [(set (reg:SI MACL_REG)
1168 (mult:SI (sign_extend:SI
1169 (match_operand:HI 0 "arith_reg_operand" "r"))
1171 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1174 [(set_attr "type" "smpy")])
1176 (define_expand "mulhisi3"
1177 [(set (reg:SI MACL_REG)
1178 (mult:SI (sign_extend:SI
1179 (match_operand:HI 1 "arith_reg_operand" ""))
1181 (match_operand:HI 2 "arith_reg_operand" ""))))
1182 (set (match_operand:SI 0 "arith_reg_operand" "")
1189 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1190 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1191 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1192 invariant code motion can move it. */
1193 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1194 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1198 (define_expand "umulhisi3"
1199 [(set (reg:SI MACL_REG)
1200 (mult:SI (zero_extend:SI
1201 (match_operand:HI 1 "arith_reg_operand" ""))
1203 (match_operand:HI 2 "arith_reg_operand" ""))))
1204 (set (match_operand:SI 0 "arith_reg_operand" "")
1211 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1212 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1213 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1214 invariant code motion can move it. */
1215 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1216 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1220 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1221 ;; a call to a routine which clobbers known registers.
1224 [(set (match_operand:SI 1 "register_operand" "=z")
1225 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1226 (clobber (reg:SI MACL_REG))
1227 (clobber (reg:SI T_REG))
1228 (clobber (reg:SI PR_REG))
1229 (clobber (reg:SI R3_REG))
1230 (clobber (reg:SI R2_REG))
1231 (clobber (reg:SI R1_REG))
1232 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1235 [(set_attr "type" "sfunc")
1236 (set_attr "needs_delay_slot" "yes")])
1238 (define_expand "mulsi3_call"
1239 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1240 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1241 (parallel[(set (match_operand:SI 0 "register_operand" "")
1242 (mult:SI (reg:SI R4_REG)
1244 (clobber (reg:SI MACL_REG))
1245 (clobber (reg:SI T_REG))
1246 (clobber (reg:SI PR_REG))
1247 (clobber (reg:SI R3_REG))
1248 (clobber (reg:SI R2_REG))
1249 (clobber (reg:SI R1_REG))
1250 (use (match_operand:SI 3 "register_operand" ""))])]
1254 (define_insn "mul_l"
1255 [(set (reg:SI MACL_REG)
1256 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1257 (match_operand:SI 1 "arith_reg_operand" "r")))]
1260 [(set_attr "type" "dmpy")])
1262 (define_expand "mulsi3"
1263 [(set (reg:SI MACL_REG)
1264 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1265 (match_operand:SI 2 "arith_reg_operand" "")))
1266 (set (match_operand:SI 0 "arith_reg_operand" "")
1275 /* The address must be set outside the libcall,
1276 since it goes into a pseudo. */
1277 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1278 rtx addr = force_reg (SImode, sym);
1279 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1281 first = XVECEXP (insns, 0, 0);
1282 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1287 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1289 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1290 /* consec_sets_giv can only recognize the first insn that sets a
1291 giv as the giv insn. So we must tag this also with a REG_EQUAL
1293 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1295 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1296 invariant code motion can move it. */
1297 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1298 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1302 (define_insn "mulsidi3_i"
1303 [(set (reg:SI MACH_REG)
1307 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1308 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1310 (set (reg:SI MACL_REG)
1311 (mult:SI (match_dup 0)
1315 [(set_attr "type" "dmpy")])
1317 (define_insn "mulsidi3"
1318 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1320 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1321 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1322 (clobber (reg:SI MACH_REG))
1323 (clobber (reg:SI MACL_REG))]
1328 [(set (match_operand:DI 0 "arith_reg_operand" "")
1330 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1331 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1332 (clobber (reg:SI MACH_REG))
1333 (clobber (reg:SI MACL_REG))]
1338 rtx low_dst = gen_lowpart (SImode, operands[0]);
1339 rtx high_dst = gen_highpart (SImode, operands[0]);
1341 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1343 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1344 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1345 /* We need something to tag the possible REG_EQUAL notes on to. */
1346 emit_move_insn (operands[0], operands[0]);
1350 (define_insn "umulsidi3_i"
1351 [(set (reg:SI MACH_REG)
1355 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1356 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1358 (set (reg:SI MACL_REG)
1359 (mult:SI (match_dup 0)
1363 [(set_attr "type" "dmpy")])
1365 (define_insn "umulsidi3"
1366 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1368 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1369 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1370 (clobber (reg:SI MACH_REG))
1371 (clobber (reg:SI MACL_REG))]
1376 [(set (match_operand:DI 0 "arith_reg_operand" "")
1377 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1378 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1379 (clobber (reg:SI MACH_REG))
1380 (clobber (reg:SI MACL_REG))]
1385 rtx low_dst = gen_lowpart (SImode, operands[0]);
1386 rtx high_dst = gen_highpart (SImode, operands[0]);
1388 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1390 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1391 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1392 /* We need something to tag the possible REG_EQUAL notes on to. */
1393 emit_move_insn (operands[0], operands[0]);
1397 (define_insn "smulsi3_highpart_i"
1398 [(set (reg:SI MACH_REG)
1402 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1403 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1405 (clobber (reg:SI MACL_REG))]
1408 [(set_attr "type" "dmpy")])
1410 (define_expand "smulsi3_highpart"
1412 [(set (reg:SI MACH_REG)
1416 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1417 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1419 (clobber (reg:SI MACL_REG))])
1420 (set (match_operand:SI 0 "arith_reg_operand" "")
1427 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1428 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1429 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1430 invariant code motion can move it. */
1431 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1432 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1433 /* expand_binop can't find a suitable code in mul_highpart_optab to
1434 make a REG_EQUAL note from, so make one here.
1435 ??? Alternatively, we could put this at the calling site of expand_binop,
1436 i.e. expand_mult_highpart. */
1438 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1443 (define_insn "umulsi3_highpart_i"
1444 [(set (reg:SI MACH_REG)
1448 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1449 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1451 (clobber (reg:SI MACL_REG))]
1454 [(set_attr "type" "dmpy")])
1456 (define_expand "umulsi3_highpart"
1458 [(set (reg:SI MACH_REG)
1462 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1463 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1465 (clobber (reg:SI MACL_REG))])
1466 (set (match_operand:SI 0 "arith_reg_operand" "")
1473 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1474 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1475 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1476 invariant code motion can move it. */
1477 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1478 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1482 ;; -------------------------------------------------------------------------
1483 ;; Logical operations
1484 ;; -------------------------------------------------------------------------
1487 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1488 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1489 (match_operand:SI 2 "logical_operand" "r,L")))]
1492 [(set_attr "type" "arith")])
1494 ;; If the constant is 255, then emit a extu.b instruction instead of an
1495 ;; and, since that will give better code.
1497 (define_expand "andsi3"
1498 [(set (match_operand:SI 0 "arith_reg_operand" "")
1499 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1500 (match_operand:SI 2 "logical_operand" "")))]
1504 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1506 emit_insn (gen_zero_extendqisi2 (operands[0],
1507 gen_lowpart (QImode, operands[1])));
1512 (define_insn "iorsi3"
1513 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1514 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1515 (match_operand:SI 2 "logical_operand" "r,L")))]
1518 [(set_attr "type" "arith")])
1520 (define_insn "xorsi3"
1521 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1522 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1523 (match_operand:SI 2 "logical_operand" "L,r")))]
1526 [(set_attr "type" "arith")])
1528 ;; -------------------------------------------------------------------------
1529 ;; Shifts and rotates
1530 ;; -------------------------------------------------------------------------
1532 (define_insn "rotlsi3_1"
1533 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1534 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1537 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1540 [(set_attr "type" "arith")])
1542 (define_insn "rotlsi3_31"
1543 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1544 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1546 (clobber (reg:SI T_REG))]
1549 [(set_attr "type" "arith")])
1551 (define_insn "rotlsi3_16"
1552 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1553 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1557 [(set_attr "type" "arith")])
1559 (define_expand "rotlsi3"
1560 [(set (match_operand:SI 0 "arith_reg_operand" "")
1561 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1562 (match_operand:SI 2 "immediate_operand" "")))]
1566 static char rot_tab[] = {
1567 000, 000, 000, 000, 000, 000, 010, 001,
1568 001, 001, 011, 013, 003, 003, 003, 003,
1569 003, 003, 003, 003, 003, 013, 012, 002,
1570 002, 002, 010, 000, 000, 000, 000, 000,
1575 if (GET_CODE (operands[2]) != CONST_INT)
1577 count = INTVAL (operands[2]);
1578 choice = rot_tab[count];
1579 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1585 emit_move_insn (operands[0], operands[1]);
1586 count -= (count & 16) * 2;
1589 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1596 parts[0] = gen_reg_rtx (SImode);
1597 parts[1] = gen_reg_rtx (SImode);
1598 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1599 parts[choice-1] = operands[1];
1600 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1601 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1602 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1603 count = (count & ~16) - 8;
1607 for (; count > 0; count--)
1608 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1609 for (; count < 0; count++)
1610 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1615 (define_insn "*rotlhi3_8"
1616 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1617 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1621 [(set_attr "type" "arith")])
1623 (define_expand "rotlhi3"
1624 [(set (match_operand:HI 0 "arith_reg_operand" "")
1625 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1626 (match_operand:HI 2 "immediate_operand" "")))]
1630 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1637 ;; This pattern is used by init_expmed for computing the costs of shift
1640 (define_insn_and_split "ashlsi3_std"
1641 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
1642 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
1643 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
1644 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
1646 || (GET_CODE (operands[2]) == CONST_INT
1647 && CONST_OK_FOR_K (INTVAL (operands[2])))"
1654 && GET_CODE (operands[2]) == CONST_INT
1655 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
1656 [(set (match_dup 3) (match_dup 2))
1658 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
1659 (clobber (match_dup 4))])]
1660 "operands[4] = gen_rtx_SCRATCH (SImode);"
1661 [(set_attr "length" "*,*,*,4")
1662 (set_attr "type" "dyn_shift,arith,arith,arith")])
1664 (define_insn "ashlhi3_k"
1665 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1666 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1667 (match_operand:HI 2 "const_int_operand" "M,K")))]
1668 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1672 [(set_attr "type" "arith")])
1674 (define_insn "ashlsi3_n"
1675 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1676 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1677 (match_operand:SI 2 "const_int_operand" "n")))
1678 (clobber (reg:SI T_REG))]
1679 "! sh_dynamicalize_shift_p (operands[2])"
1681 [(set (attr "length")
1682 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1684 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1686 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1688 (const_string "8")))
1689 (set_attr "type" "arith")])
1692 [(set (match_operand:SI 0 "arith_reg_operand" "")
1693 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1694 (match_operand:SI 2 "const_int_operand" "n")))
1695 (clobber (reg:SI T_REG))]
1697 [(use (reg:SI R0_REG))]
1700 gen_shifty_op (ASHIFT, operands);
1704 (define_expand "ashlsi3"
1705 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1706 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1707 (match_operand:SI 2 "nonmemory_operand" "")))
1708 (clobber (reg:SI T_REG))])]
1712 if (GET_CODE (operands[2]) == CONST_INT
1713 && sh_dynamicalize_shift_p (operands[2]))
1714 operands[2] = force_reg (SImode, operands[2]);
1717 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
1720 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1724 (define_insn "ashlhi3"
1725 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1726 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1727 (match_operand:HI 2 "const_int_operand" "n")))
1728 (clobber (reg:SI T_REG))]
1731 [(set (attr "length")
1732 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1734 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1736 (const_string "6")))
1737 (set_attr "type" "arith")])
1740 [(set (match_operand:HI 0 "arith_reg_operand" "")
1741 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1742 (match_operand:HI 2 "const_int_operand" "n")))
1743 (clobber (reg:SI T_REG))]
1745 [(use (reg:SI R0_REG))]
1748 gen_shifty_hi_op (ASHIFT, operands);
1753 ; arithmetic shift right
1756 (define_insn "ashrsi3_k"
1757 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1758 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1759 (match_operand:SI 2 "const_int_operand" "M")))
1760 (clobber (reg:SI T_REG))]
1761 "INTVAL (operands[2]) == 1"
1763 [(set_attr "type" "arith")])
1765 ;; We can't do HImode right shifts correctly unless we start out with an
1766 ;; explicit zero / sign extension; doing that would result in worse overall
1767 ;; code, so just let the machine independent code widen the mode.
1768 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1771 ;; ??? This should be a define expand.
1773 (define_insn "ashrsi2_16"
1774 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1775 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1779 [(set_attr "length" "4")])
1782 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1783 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1786 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1787 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1788 "operands[2] = gen_lowpart (HImode, operands[0]);")
1790 ;; ??? This should be a define expand.
1792 (define_insn "ashrsi2_31"
1793 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1794 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1796 (clobber (reg:SI T_REG))]
1799 [(set_attr "length" "4")])
1802 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1803 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1805 (clobber (reg:SI T_REG))]
1810 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1811 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1815 (define_insn "ashlsi_c"
1816 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1817 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1819 (lt:SI (match_dup 1) (const_int 0)))]
1822 [(set_attr "type" "arith")])
1824 (define_insn "ashrsi3_d"
1825 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1826 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1827 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1830 [(set_attr "type" "dyn_shift")])
1832 (define_insn "ashrsi3_n"
1833 [(set (reg:SI R4_REG)
1834 (ashiftrt:SI (reg:SI R4_REG)
1835 (match_operand:SI 0 "const_int_operand" "i")))
1836 (clobber (reg:SI T_REG))
1837 (clobber (reg:SI PR_REG))
1838 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1841 [(set_attr "type" "sfunc")
1842 (set_attr "needs_delay_slot" "yes")])
1844 (define_expand "ashrsi3"
1845 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1846 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1847 (match_operand:SI 2 "nonmemory_operand" "")))
1848 (clobber (reg:SI T_REG))])]
1850 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1852 ;; logical shift right
1854 (define_insn "lshrsi3_d"
1855 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1856 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1857 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1860 [(set_attr "type" "dyn_shift")])
1862 ;; Only the single bit shift clobbers the T bit.
1864 (define_insn "lshrsi3_m"
1865 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1866 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1867 (match_operand:SI 2 "const_int_operand" "M")))
1868 (clobber (reg:SI T_REG))]
1869 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1871 [(set_attr "type" "arith")])
1873 (define_insn "lshrsi3_k"
1874 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1875 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1876 (match_operand:SI 2 "const_int_operand" "K")))]
1877 "CONST_OK_FOR_K (INTVAL (operands[2]))
1878 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1880 [(set_attr "type" "arith")])
1882 (define_insn "lshrsi3_n"
1883 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1884 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1885 (match_operand:SI 2 "const_int_operand" "n")))
1886 (clobber (reg:SI T_REG))]
1887 "! sh_dynamicalize_shift_p (operands[2])"
1889 [(set (attr "length")
1890 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1892 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1894 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1896 (const_string "8")))
1897 (set_attr "type" "arith")])
1900 [(set (match_operand:SI 0 "arith_reg_operand" "")
1901 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1902 (match_operand:SI 2 "const_int_operand" "n")))
1903 (clobber (reg:SI T_REG))]
1905 [(use (reg:SI R0_REG))]
1908 gen_shifty_op (LSHIFTRT, operands);
1912 (define_expand "lshrsi3"
1913 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1914 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1915 (match_operand:SI 2 "nonmemory_operand" "")))
1916 (clobber (reg:SI T_REG))])]
1920 if (GET_CODE (operands[2]) == CONST_INT
1921 && sh_dynamicalize_shift_p (operands[2]))
1922 operands[2] = force_reg (SImode, operands[2]);
1923 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1925 rtx count = copy_to_mode_reg (SImode, operands[2]);
1926 emit_insn (gen_negsi2 (count, count));
1927 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1930 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1934 ;; ??? This should be a define expand.
1936 (define_insn "ashldi3_k"
1937 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1938 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1940 (clobber (reg:SI T_REG))]
1942 "shll %R0\;rotcl %S0"
1943 [(set_attr "length" "4")
1944 (set_attr "type" "arith")])
1946 (define_expand "ashldi3"
1947 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1948 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1949 (match_operand:DI 2 "immediate_operand" "")))
1950 (clobber (reg:SI T_REG))])]
1952 "{ if (GET_CODE (operands[2]) != CONST_INT
1953 || INTVAL (operands[2]) != 1) FAIL;} ")
1955 ;; ??? This should be a define expand.
1957 (define_insn "lshrdi3_k"
1958 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1959 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1961 (clobber (reg:SI T_REG))]
1963 "shlr %S0\;rotcr %R0"
1964 [(set_attr "length" "4")
1965 (set_attr "type" "arith")])
1967 (define_expand "lshrdi3"
1968 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1969 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1970 (match_operand:DI 2 "immediate_operand" "")))
1971 (clobber (reg:SI T_REG))])]
1973 "{ if (GET_CODE (operands[2]) != CONST_INT
1974 || INTVAL (operands[2]) != 1) FAIL;} ")
1976 ;; ??? This should be a define expand.
1978 (define_insn "ashrdi3_k"
1979 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1980 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1982 (clobber (reg:SI T_REG))]
1984 "shar %S0\;rotcr %R0"
1985 [(set_attr "length" "4")
1986 (set_attr "type" "arith")])
1988 (define_expand "ashrdi3"
1989 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1990 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1991 (match_operand:DI 2 "immediate_operand" "")))
1992 (clobber (reg:SI T_REG))])]
1994 "{ if (GET_CODE (operands[2]) != CONST_INT
1995 || INTVAL (operands[2]) != 1) FAIL; } ")
1997 ;; combined left/right shift
2000 [(set (match_operand:SI 0 "register_operand" "")
2001 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2002 (match_operand:SI 2 "const_int_operand" "n"))
2003 (match_operand:SI 3 "const_int_operand" "n")))]
2004 "(unsigned)INTVAL (operands[2]) < 32"
2005 [(use (reg:SI R0_REG))]
2006 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2010 [(set (match_operand:SI 0 "register_operand" "")
2011 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2012 (match_operand:SI 2 "const_int_operand" "n"))
2013 (match_operand:SI 3 "const_int_operand" "n")))
2014 (clobber (reg:SI T_REG))]
2015 "(unsigned)INTVAL (operands[2]) < 32"
2016 [(use (reg:SI R0_REG))]
2017 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2021 [(set (match_operand:SI 0 "register_operand" "=r")
2022 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2023 (match_operand:SI 2 "const_int_operand" "n"))
2024 (match_operand:SI 3 "const_int_operand" "n")))
2025 (clobber (reg:SI T_REG))]
2026 "shl_and_kind (operands[2], operands[3], 0) == 1"
2028 [(set (attr "length")
2029 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2031 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2033 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2035 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
2037 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
2039 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
2041 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
2042 (const_string "16")]
2043 (const_string "18")))
2044 (set_attr "type" "arith")])
2047 [(set (match_operand:SI 0 "register_operand" "=z")
2048 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2049 (match_operand:SI 2 "const_int_operand" "n"))
2050 (match_operand:SI 3 "const_int_operand" "n")))
2051 (clobber (reg:SI T_REG))]
2052 "shl_and_kind (operands[2], operands[3], 0) == 2"
2054 [(set (attr "length")
2055 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2057 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2059 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2061 (const_string "10")))
2062 (set_attr "type" "arith")])
2064 ;; shift left / and combination with a scratch register: The combine pass
2065 ;; does not accept the individual instructions, even though they are
2066 ;; cheap. But it needs a precise description so that it is usable after
2068 (define_insn "and_shl_scratch"
2069 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2073 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2074 (match_operand:SI 2 "const_int_operand" "N,n"))
2075 (match_operand:SI 3 "" "0,r"))
2076 (match_operand:SI 4 "const_int_operand" "n,n"))
2077 (match_operand:SI 5 "const_int_operand" "n,n")))
2078 (clobber (reg:SI T_REG))]
2081 [(set (attr "length")
2082 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
2084 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
2086 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
2088 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2089 (const_string "10")]
2090 (const_string "12")))
2091 (set_attr "type" "arith")])
2094 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2098 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2099 (match_operand:SI 2 "const_int_operand" "N,n"))
2100 (match_operand:SI 3 "register_operand" "0,r"))
2101 (match_operand:SI 4 "const_int_operand" "n,n"))
2102 (match_operand:SI 5 "const_int_operand" "n,n")))
2103 (clobber (reg:SI T_REG))]
2105 [(use (reg:SI R0_REG))]
2108 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2110 if (INTVAL (operands[2]))
2112 gen_shifty_op (LSHIFTRT, operands);
2114 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2115 operands[2] = operands[4];
2116 gen_shifty_op (ASHIFT, operands);
2117 if (INTVAL (operands[5]))
2119 operands[2] = operands[5];
2120 gen_shifty_op (LSHIFTRT, operands);
2125 ;; signed left/right shift combination.
2127 [(set (match_operand:SI 0 "register_operand" "=r")
2129 (ashift:SI (match_operand:SI 1 "register_operand" "r")
2130 (match_operand:SI 2 "const_int_operand" "n"))
2131 (match_operand:SI 3 "const_int_operand" "n")
2133 (clobber (reg:SI T_REG))]
2135 [(use (reg:SI R0_REG))]
2136 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2139 (define_insn "shl_sext_ext"
2140 [(set (match_operand:SI 0 "register_operand" "=r")
2142 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2143 (match_operand:SI 2 "const_int_operand" "n"))
2144 (match_operand:SI 3 "const_int_operand" "n")
2146 (clobber (reg:SI T_REG))]
2147 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2149 [(set (attr "length")
2150 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2152 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2154 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2156 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2158 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2160 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2162 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2164 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2165 (const_string "16")]
2166 (const_string "18")))
2167 (set_attr "type" "arith")])
2169 (define_insn "shl_sext_sub"
2170 [(set (match_operand:SI 0 "register_operand" "=z")
2172 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2173 (match_operand:SI 2 "const_int_operand" "n"))
2174 (match_operand:SI 3 "const_int_operand" "n")
2176 (clobber (reg:SI T_REG))]
2177 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2179 [(set (attr "length")
2180 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2182 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2184 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2186 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2187 (const_string "12")]
2188 (const_string "14")))
2189 (set_attr "type" "arith")])
2191 ;; These patterns are found in expansions of DImode shifts by 16, and
2192 ;; allow the xtrct instruction to be generated from C source.
2194 (define_insn "xtrct_left"
2195 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2196 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2198 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2202 [(set_attr "type" "arith")])
2204 (define_insn "xtrct_right"
2205 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2206 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2208 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2212 [(set_attr "type" "arith")])
2214 ;; -------------------------------------------------------------------------
2216 ;; -------------------------------------------------------------------------
2219 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2220 (neg:SI (plus:SI (reg:SI T_REG)
2221 (match_operand:SI 1 "arith_reg_operand" "r"))))
2223 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
2227 [(set_attr "type" "arith")])
2229 (define_expand "negdi2"
2230 [(set (match_operand:DI 0 "arith_reg_operand" "")
2231 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
2232 (clobber (reg:SI T_REG))]
2236 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2237 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2239 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2240 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2242 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2243 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2245 emit_insn (gen_clrt ());
2246 emit_insn (gen_negc (low_dst, low_src));
2247 emit_insn (gen_negc (high_dst, high_src));
2251 (define_insn "negsi2"
2252 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2253 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2256 [(set_attr "type" "arith")])
2258 (define_insn "one_cmplsi2"
2259 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2260 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2263 [(set_attr "type" "arith")])
2265 ;; -------------------------------------------------------------------------
2266 ;; Zero extension instructions
2267 ;; -------------------------------------------------------------------------
2269 (define_insn "zero_extendhisi2"
2270 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2271 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2274 [(set_attr "type" "arith")])
2276 (define_insn "zero_extendqisi2"
2277 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2278 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2281 [(set_attr "type" "arith")])
2283 (define_insn "zero_extendqihi2"
2284 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2285 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2288 [(set_attr "type" "arith")])
2290 ;; -------------------------------------------------------------------------
2291 ;; Sign extension instructions
2292 ;; -------------------------------------------------------------------------
2294 ;; ??? This should be a define expand.
2295 ;; ??? Or perhaps it should be dropped?
2297 /* There is no point in defining extendsidi2; convert_move generates good
2300 (define_insn "extendhisi2"
2301 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2302 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2307 [(set_attr "type" "arith,load")])
2309 (define_insn "extendqisi2"
2310 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2311 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2316 [(set_attr "type" "arith,load")])
2318 (define_insn "extendqihi2"
2319 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2320 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2325 [(set_attr "type" "arith,load")])
2327 ;; -------------------------------------------------------------------------
2328 ;; Move instructions
2329 ;; -------------------------------------------------------------------------
2331 ;; define push and pop so it is easy for sh.c
2333 (define_expand "push"
2334 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2335 (match_operand:SI 0 "register_operand" "r,l,x"))]
2339 (define_expand "pop"
2340 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2341 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2345 (define_expand "push_e"
2346 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
2347 (match_operand:SF 0 "" ""))
2348 (use (reg:PSI FPSCR_REG))
2349 (clobber (scratch:SI))])]
2353 (define_insn "push_fpul"
2354 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
2357 [(set_attr "type" "store")
2358 (set_attr "hit_stack" "yes")])
2360 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2362 (define_expand "push_4"
2363 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
2364 (match_operand:DF 0 "" ""))
2365 (use (reg:PSI FPSCR_REG))
2366 (clobber (scratch:SI))])]
2370 (define_expand "pop_e"
2371 [(parallel [(set (match_operand:SF 0 "" "")
2372 (mem:SF (post_inc:SI (reg:SI SP_REG))))
2373 (use (reg:PSI FPSCR_REG))
2374 (clobber (scratch:SI))])]
2378 (define_insn "pop_fpul"
2379 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
2382 [(set_attr "type" "load")
2383 (set_attr "hit_stack" "yes")])
2385 (define_expand "pop_4"
2386 [(parallel [(set (match_operand:DF 0 "" "")
2387 (mem:DF (post_inc:SI (reg:SI SP_REG))))
2388 (use (reg:PSI FPSCR_REG))
2389 (clobber (scratch:SI))])]
2393 ;; These two patterns can happen as the result of optimization, when
2394 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2395 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2398 [(set (reg:SI T_REG) (const_int 0))]
2403 [(set (reg:SI T_REG) (const_int 1))]
2407 ;; t/r must come after r/r, lest reload will try to reload stuff like
2408 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
2409 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
2410 (define_insn "movsi_i"
2411 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
2412 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
2415 && (register_operand (operands[0], SImode)
2416 || register_operand (operands[1], SImode))"
2433 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
2434 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
2436 ;; t/r must come after r/r, lest reload will try to reload stuff like
2437 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2438 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2439 ;; will require a reload.
2440 (define_insn "movsi_ie"
2441 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,y")
2442 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y"))]
2444 && (register_operand (operands[0], SImode)
2445 || register_operand (operands[1], SImode))"
2466 ! move optimized away"
2467 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,gp_fpul,nil")
2468 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2470 (define_insn "movsi_i_lowpart"
2471 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
2472 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))]
2473 "register_operand (operands[0], SImode)
2474 || register_operand (operands[1], SImode)"
2484 [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
2486 (define_expand "movsi"
2487 [(set (match_operand:SI 0 "general_movdst_operand" "")
2488 (match_operand:SI 1 "general_movsrc_operand" ""))]
2490 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2492 (define_expand "ic_invalidate_line"
2493 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2494 (match_dup 1)] UNSPEC_ICACHE)
2495 (clobber (scratch:SI))])]
2499 operands[0] = force_reg (Pmode, operands[0]);
2500 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2503 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2504 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2505 ;; the requirement *1*00 for associative address writes. The alignment of
2506 ;; %0 implies that its least significant bit is cleared,
2507 ;; thus we clear the V bit of a matching entry if there is one.
2508 (define_insn "ic_invalidate_line_i"
2509 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2510 (match_operand:SI 1 "register_operand" "r")]
2512 (clobber (match_scratch:SI 2 "=&r"))]
2514 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2515 [(set_attr "length" "8")])
2517 (define_insn "movqi_i"
2518 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2519 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2520 "arith_reg_operand (operands[0], QImode)
2521 || arith_reg_operand (operands[1], QImode)"
2529 [(set_attr "type" "move,load,store,move,move,move")])
2531 (define_expand "movqi"
2532 [(set (match_operand:QI 0 "general_operand" "")
2533 (match_operand:QI 1 "general_operand" ""))]
2535 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2537 (define_insn "movhi_i"
2538 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2539 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2540 "arith_reg_operand (operands[0], HImode)
2541 || arith_reg_operand (operands[1], HImode)"
2551 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2553 (define_expand "movhi"
2554 [(set (match_operand:HI 0 "general_movdst_operand" "")
2555 (match_operand:HI 1 "general_movsrc_operand" ""))]
2557 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2559 ;; ??? This should be a define expand.
2561 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2562 ;; compiled with -m2 -ml -O3 -funroll-loops
2564 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2565 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2566 "arith_reg_operand (operands[0], DImode)
2567 || arith_reg_operand (operands[1], DImode)"
2568 "* return output_movedouble (insn, operands, DImode);"
2569 [(set_attr "length" "4")
2570 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2572 ;; If the output is a register and the input is memory or a register, we have
2573 ;; to be careful and see which word needs to be loaded first.
2576 [(set (match_operand:DI 0 "general_movdst_operand" "")
2577 (match_operand:DI 1 "general_movsrc_operand" ""))]
2579 [(set (match_dup 2) (match_dup 3))
2580 (set (match_dup 4) (match_dup 5))]
2585 if ((GET_CODE (operands[0]) == MEM
2586 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2587 || (GET_CODE (operands[1]) == MEM
2588 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2591 if (GET_CODE (operands[0]) == REG)
2592 regno = REGNO (operands[0]);
2593 else if (GET_CODE (operands[0]) == SUBREG)
2594 regno = subreg_regno (operands[0]);
2595 else if (GET_CODE (operands[0]) == MEM)
2599 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2601 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2602 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2603 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2604 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2608 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2609 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2610 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2611 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2614 if (operands[2] == 0 || operands[3] == 0
2615 || operands[4] == 0 || operands[5] == 0)
2619 (define_expand "movdi"
2620 [(set (match_operand:DI 0 "general_movdst_operand" "")
2621 (match_operand:DI 1 "general_movsrc_operand" ""))]
2623 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
2625 ;; ??? This should be a define expand.
2627 (define_insn "movdf_k"
2628 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2629 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2630 "(! TARGET_SH4 || reload_completed
2631 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2632 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2633 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2634 && (arith_reg_operand (operands[0], DFmode)
2635 || arith_reg_operand (operands[1], DFmode))"
2636 "* return output_movedouble (insn, operands, DFmode);"
2637 [(set_attr "length" "4")
2638 (set_attr "type" "move,pcload,load,store")])
2640 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2641 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2642 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2643 ;; the d/m/c/X alternative, which is split later into single-precision
2644 ;; instructions. And when not optimizing, no splits are done before fixing
2645 ;; up pcloads, so we need usable length information for that.
2646 (define_insn "movdf_i4"
2647 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2648 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2649 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2650 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2652 && (arith_reg_operand (operands[0], DFmode)
2653 || arith_reg_operand (operands[1], DFmode))"
2665 [(set_attr_alternative "length"
2666 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2668 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2669 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2670 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2672 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2673 (const_int 8) (const_int 8)])
2674 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
2675 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
2676 (const_string "double")
2677 (const_string "none")))])
2679 ;; Moving DFmode between fp/general registers through memory
2680 ;; (the top of the stack) is faster than moving through fpul even for
2681 ;; little endian. Because the type of an instruction is important for its
2682 ;; scheduling, it is beneficial to split these operations, rather than
2683 ;; emitting them in one single chunk, even if this will expose a stack
2684 ;; use that will prevent scheduling of other stack accesses beyond this
2687 [(set (match_operand:DF 0 "register_operand" "")
2688 (match_operand:DF 1 "register_operand" ""))
2689 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2690 (clobber (match_scratch:SI 3 "=X"))]
2691 "TARGET_SH4 && reload_completed
2692 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2698 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2699 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2700 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2701 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2702 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2703 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2707 ;; local-alloc sometimes allocates scratch registers even when not required,
2708 ;; so we must be prepared to handle these.
2710 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2712 [(set (match_operand:DF 0 "general_movdst_operand" "")
2713 (match_operand:DF 1 "general_movsrc_operand" ""))
2714 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2715 (clobber (match_scratch:SI 3 "X"))]
2718 && true_regnum (operands[0]) < 16
2719 && true_regnum (operands[1]) < 16"
2720 [(set (match_dup 0) (match_dup 1))]
2723 /* If this was a reg <-> mem operation with base + index reg addressing,
2724 we have to handle this in a special way. */
2725 rtx mem = operands[0];
2727 if (! memory_operand (mem, DFmode))
2732 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
2733 mem = SUBREG_REG (mem);
2734 if (GET_CODE (mem) == MEM)
2736 rtx addr = XEXP (mem, 0);
2737 if (GET_CODE (addr) == PLUS
2738 && GET_CODE (XEXP (addr, 0)) == REG
2739 && GET_CODE (XEXP (addr, 1)) == REG)
2742 rtx reg0 = gen_rtx (REG, Pmode, 0);
2743 rtx regop = operands[store_p], word0 ,word1;
2745 if (GET_CODE (regop) == SUBREG)
2746 regop = alter_subreg (regop);
2747 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2751 mem = copy_rtx (mem);
2752 PUT_MODE (mem, SImode);
2753 word0 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 0));
2754 word1 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 4));
2755 if (store_p || ! refers_to_regno_p (REGNO (word0),
2756 REGNO (word0) + 1, addr, 0))
2759 ? gen_movsi_ie (mem, word0)
2760 : gen_movsi_ie (word0, mem));
2761 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2762 mem = copy_rtx (mem);
2764 ? gen_movsi_ie (mem, word1)
2765 : gen_movsi_ie (word1, mem));
2766 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2770 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2771 emit_insn (gen_movsi_ie (word1, mem));
2772 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2773 mem = copy_rtx (mem);
2774 emit_insn (gen_movsi_ie (word0, mem));
2781 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2783 [(set (match_operand:DF 0 "register_operand" "")
2784 (match_operand:DF 1 "memory_operand" ""))
2785 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2786 (clobber (reg:SI R0_REG))]
2787 "TARGET_SH4 && reload_completed"
2788 [(parallel [(set (match_dup 0) (match_dup 1))
2790 (clobber (scratch:SI))])]
2793 (define_expand "reload_indf"
2794 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2795 (match_operand:DF 1 "immediate_operand" "FQ"))
2796 (use (reg:PSI FPSCR_REG))
2797 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2801 (define_expand "reload_outdf"
2802 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2803 (match_operand:DF 1 "register_operand" "af,r"))
2804 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2808 ;; Simplify no-op moves.
2810 [(set (match_operand:SF 0 "register_operand" "")
2811 (match_operand:SF 1 "register_operand" ""))
2812 (use (match_operand:PSI 2 "fpscr_operand" ""))
2813 (clobber (match_scratch:SI 3 "X"))]
2814 "TARGET_SH3E && reload_completed
2815 && true_regnum (operands[0]) == true_regnum (operands[1])"
2816 [(set (match_dup 0) (match_dup 0))]
2819 ;; fmovd substitute post-reload splits
2821 [(set (match_operand:DF 0 "register_operand" "")
2822 (match_operand:DF 1 "register_operand" ""))
2823 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2824 (clobber (match_scratch:SI 3 "X"))]
2825 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2826 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
2827 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2831 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2832 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2833 gen_rtx (REG, SFmode, src), operands[2]));
2834 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2835 gen_rtx (REG, SFmode, src + 1), operands[2]));
2840 [(set (match_operand:DF 0 "register_operand" "")
2841 (mem:DF (match_operand:SI 1 "register_operand" "")))
2842 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2843 (clobber (match_scratch:SI 3 "X"))]
2844 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2845 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
2846 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2850 int regno = true_regnum (operands[0]);
2852 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2854 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2855 regno + !! TARGET_LITTLE_ENDIAN),
2856 mem2, operands[2]));
2857 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2858 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2859 regno + ! TARGET_LITTLE_ENDIAN),
2860 gen_rtx (MEM, SFmode, operands[1]),
2866 [(set (match_operand:DF 0 "register_operand" "")
2867 (match_operand:DF 1 "memory_operand" ""))
2868 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2869 (clobber (match_scratch:SI 3 "X"))]
2870 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2871 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
2875 int regno = true_regnum (operands[0]);
2876 rtx addr, insn, adjust = NULL_RTX;
2877 rtx mem2 = copy_rtx (operands[1]);
2878 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2879 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2881 PUT_MODE (mem2, SFmode);
2882 operands[1] = copy_rtx (mem2);
2883 addr = XEXP (mem2, 0);
2884 if (GET_CODE (addr) != POST_INC)
2886 /* If we have to modify the stack pointer, the value that we have
2887 read with post-increment might be modified by an interrupt,
2888 so write it back. */
2889 if (REGNO (addr) == STACK_POINTER_REGNUM)
2890 adjust = gen_push_e (reg0);
2892 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2893 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2895 addr = XEXP (addr, 0);
2896 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2897 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2898 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2902 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2907 [(set (match_operand:DF 0 "memory_operand" "")
2908 (match_operand:DF 1 "register_operand" ""))
2909 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2910 (clobber (match_scratch:SI 3 "X"))]
2911 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2912 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2916 int regno = true_regnum (operands[1]);
2917 rtx insn, addr, adjust = NULL_RTX;
2919 operands[0] = copy_rtx (operands[0]);
2920 PUT_MODE (operands[0], SFmode);
2921 insn = emit_insn (gen_movsf_ie (operands[0],
2922 gen_rtx (REG, SFmode,
2923 regno + ! TARGET_LITTLE_ENDIAN),
2925 operands[0] = copy_rtx (operands[0]);
2926 addr = XEXP (operands[0], 0);
2927 if (GET_CODE (addr) != PRE_DEC)
2929 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2930 emit_insn_before (adjust, insn);
2931 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2933 addr = XEXP (addr, 0);
2935 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2936 insn = emit_insn (gen_movsf_ie (operands[0],
2937 gen_rtx (REG, SFmode,
2938 regno + !! TARGET_LITTLE_ENDIAN),
2940 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2944 ;; If the output is a register and the input is memory or a register, we have
2945 ;; to be careful and see which word needs to be loaded first.
2948 [(set (match_operand:DF 0 "general_movdst_operand" "")
2949 (match_operand:DF 1 "general_movsrc_operand" ""))]
2951 [(set (match_dup 2) (match_dup 3))
2952 (set (match_dup 4) (match_dup 5))]
2957 if ((GET_CODE (operands[0]) == MEM
2958 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2959 || (GET_CODE (operands[1]) == MEM
2960 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2963 if (GET_CODE (operands[0]) == REG)
2964 regno = REGNO (operands[0]);
2965 else if (GET_CODE (operands[0]) == SUBREG)
2966 regno = subreg_regno (operands[0]);
2967 else if (GET_CODE (operands[0]) == MEM)
2971 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2973 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2974 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2975 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2976 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2980 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2981 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2982 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2983 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2986 if (operands[2] == 0 || operands[3] == 0
2987 || operands[4] == 0 || operands[5] == 0)
2991 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
2992 ;; used only once, let combine add in the index again.
2995 [(set (match_operand:SI 0 "register_operand" "")
2996 (match_operand:SI 1 "" ""))
2997 (clobber (match_operand 2 "register_operand" ""))]
2998 "! reload_in_progress && ! reload_completed"
2999 [(use (reg:SI R0_REG))]
3002 rtx addr, reg, const_int;
3004 if (GET_CODE (operands[1]) != MEM)
3006 addr = XEXP (operands[1], 0);
3007 if (GET_CODE (addr) != PLUS)
3009 reg = XEXP (addr, 0);
3010 const_int = XEXP (addr, 1);
3011 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3012 && GET_CODE (const_int) == CONST_INT))
3014 emit_move_insn (operands[2], const_int);
3015 emit_move_insn (operands[0],
3016 change_address (operands[1], VOIDmode,
3017 gen_rtx_PLUS (SImode, reg, operands[2])));
3022 [(set (match_operand:SI 1 "" "")
3023 (match_operand:SI 0 "register_operand" ""))
3024 (clobber (match_operand 2 "register_operand" ""))]
3025 "! reload_in_progress && ! reload_completed"
3026 [(use (reg:SI R0_REG))]
3029 rtx addr, reg, const_int;
3031 if (GET_CODE (operands[1]) != MEM)
3033 addr = XEXP (operands[1], 0);
3034 if (GET_CODE (addr) != PLUS)
3036 reg = XEXP (addr, 0);
3037 const_int = XEXP (addr, 1);
3038 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3039 && GET_CODE (const_int) == CONST_INT))
3041 emit_move_insn (operands[2], const_int);
3042 emit_move_insn (change_address (operands[1], VOIDmode,
3043 gen_rtx_PLUS (SImode, reg, operands[2])),
3048 (define_expand "movdf"
3049 [(set (match_operand:DF 0 "general_movdst_operand" "")
3050 (match_operand:DF 1 "general_movsrc_operand" ""))]
3054 if (prepare_move_operands (operands, DFmode)) DONE;
3057 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
3063 (define_insn "movsf_i"
3064 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
3065 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
3068 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
3069 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
3070 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
3071 && (arith_reg_operand (operands[0], SFmode)
3072 || arith_reg_operand (operands[1], SFmode))"
3081 [(set_attr "type" "move,move,pcload,load,store,move,move")])
3083 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
3084 ;; update_flow_info would not know where to put REG_EQUAL notes
3085 ;; when the destination changes mode.
3086 (define_insn "movsf_ie"
3087 [(set (match_operand:SF 0 "general_movdst_operand"
3088 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
3089 (match_operand:SF 1 "general_movsrc_operand"
3090 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
3091 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
3092 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
3095 && (arith_reg_operand (operands[0], SFmode)
3096 || arith_reg_operand (operands[1], SFmode)
3097 || arith_reg_operand (operands[3], SImode)
3098 || (fpul_operand (operands[0], SFmode)
3099 && memory_operand (operands[1], SFmode)
3100 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3101 || (fpul_operand (operands[1], SFmode)
3102 && memory_operand (operands[0], SFmode)
3103 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))"
3123 ! move optimized away"
3124 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,store,load,nil")
3125 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,2,2,0")
3126 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
3127 (const_string "single")
3128 (const_string "none")))])
3131 [(set (match_operand:SF 0 "register_operand" "")
3132 (match_operand:SF 1 "register_operand" ""))
3133 (use (match_operand:PSI 2 "fpscr_operand" "c"))
3134 (clobber (reg:SI FPUL_REG))]
3136 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
3138 (clobber (scratch:SI))])
3139 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
3141 (clobber (scratch:SI))])]
3144 (define_expand "movsf"
3145 [(set (match_operand:SF 0 "general_movdst_operand" "")
3146 (match_operand:SF 1 "general_movsrc_operand" ""))]
3150 if (prepare_move_operands (operands, SFmode))
3154 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
3159 (define_insn "mov_nop"
3160 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
3163 [(set_attr "length" "0")
3164 (set_attr "type" "nil")])
3166 (define_expand "reload_insf"
3167 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
3168 (match_operand:SF 1 "immediate_operand" "FQ"))
3169 (use (reg:PSI FPSCR_REG))
3170 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3174 (define_expand "reload_insi"
3175 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
3176 (match_operand:SF 1 "immediate_operand" "FQ"))
3177 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3181 (define_insn "*movsi_y"
3182 [(set (match_operand:SI 0 "register_operand" "=y,y")
3183 (match_operand:SI 1 "immediate_operand" "Qi,I"))
3184 (clobber (match_scratch:SI 2 "=&z,r"))]
3186 && (reload_in_progress || reload_completed)"
3188 [(set_attr "length" "4")
3189 (set_attr "type" "pcload,move")])
3192 [(set (match_operand:SI 0 "register_operand" "")
3193 (match_operand:SI 1 "immediate_operand" ""))
3194 (clobber (match_operand:SI 2 "register_operand" ""))]
3196 [(set (match_dup 2) (match_dup 1))
3197 (set (match_dup 0) (match_dup 2))]
3201 [(set (match_operand:SI 0 "register_operand" "")
3202 (match_operand:SI 1 "memory_operand" ""))
3203 (clobber (reg:SI R0_REG))]
3205 [(set (match_dup 0) (match_dup 1))]
3208 ;; ------------------------------------------------------------------------
3209 ;; Define the real conditional branch instructions.
3210 ;; ------------------------------------------------------------------------
3212 (define_insn "branch_true"
3213 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
3214 (label_ref (match_operand 0 "" ""))
3217 "* return output_branch (1, insn, operands);"
3218 [(set_attr "type" "cbranch")])
3220 (define_insn "branch_false"
3221 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
3222 (label_ref (match_operand 0 "" ""))
3225 "* return output_branch (0, insn, operands);"
3226 [(set_attr "type" "cbranch")])
3228 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
3229 ;; which destination is too far away.
3230 ;; The const_int_operand is distinct for each branch target; it avoids
3231 ;; unwanted matches with redundant_insn.
3232 (define_insn "block_branch_redirect"
3233 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
3236 [(set_attr "length" "0")])
3238 ;; This one has the additional purpose to record a possible scratch register
3239 ;; for the following branch.
3240 (define_insn "indirect_jump_scratch"
3241 [(set (match_operand 0 "register_operand" "=r")
3242 (unspec [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
3245 [(set_attr "length" "0")])
3247 ;; Conditional branch insns
3249 (define_expand "beq"
3251 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3252 (label_ref (match_operand 0 "" ""))
3255 "from_compare (operands, EQ);")
3257 (define_expand "bne"
3259 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3260 (label_ref (match_operand 0 "" ""))
3263 "from_compare (operands, EQ);")
3265 (define_expand "bgt"
3267 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3268 (label_ref (match_operand 0 "" ""))
3271 "from_compare (operands, GT);")
3273 (define_expand "blt"
3275 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3276 (label_ref (match_operand 0 "" ""))
3281 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3283 rtx tmp = sh_compare_op0;
3284 sh_compare_op0 = sh_compare_op1;
3285 sh_compare_op1 = tmp;
3286 emit_insn (gen_bgt (operands[0]));
3289 from_compare (operands, GE);
3292 (define_expand "ble"
3294 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3295 (label_ref (match_operand 0 "" ""))
3302 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3304 rtx tmp = sh_compare_op0;
3305 sh_compare_op0 = sh_compare_op1;
3306 sh_compare_op1 = tmp;
3307 emit_insn (gen_bge (operands[0]));
3310 from_compare (operands, GT);
3313 (define_expand "bge"
3315 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3316 (label_ref (match_operand 0 "" ""))
3323 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3325 rtx tmp = sh_compare_op0;
3326 sh_compare_op0 = sh_compare_op1;
3327 sh_compare_op1 = tmp;
3328 emit_insn (gen_ble (operands[0]));
3331 from_compare (operands, GE);
3334 (define_expand "bgtu"
3336 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3337 (label_ref (match_operand 0 "" ""))
3340 "from_compare (operands, GTU); ")
3342 (define_expand "bltu"
3344 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3345 (label_ref (match_operand 0 "" ""))
3348 "from_compare (operands, GEU);")
3350 (define_expand "bgeu"
3352 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3353 (label_ref (match_operand 0 "" ""))
3356 "from_compare (operands, GEU);")
3358 (define_expand "bleu"
3360 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3361 (label_ref (match_operand 0 "" ""))
3364 "from_compare (operands, GTU);")
3366 ;; ------------------------------------------------------------------------
3367 ;; Jump and linkage insns
3368 ;; ------------------------------------------------------------------------
3372 (label_ref (match_operand 0 "" "")))]
3376 /* The length is 16 if the delay slot is unfilled. */
3377 if (get_attr_length(insn) > 4)
3378 return output_far_jump(insn, operands[0]);
3380 return \"bra %l0%#\";
3382 [(set_attr "type" "jump")
3383 (set_attr "needs_delay_slot" "yes")])
3385 (define_insn "calli"
3386 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3387 (match_operand 1 "" ""))
3388 (use (reg:PSI FPSCR_REG))
3389 (clobber (reg:SI PR_REG))]
3392 [(set_attr "type" "call")
3393 (set (attr "fp_mode")
3394 (if_then_else (eq_attr "fpu_single" "yes")
3395 (const_string "single") (const_string "double")))
3396 (set_attr "needs_delay_slot" "yes")])
3398 ;; This is a pc-rel call, using bsrf, for use with PIC.
3400 (define_insn "calli_pcrel"
3401 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3402 (match_operand 1 "" ""))
3403 (use (reg:PSI FPSCR_REG))
3404 (use (reg:SI PIC_REG))
3405 (use (match_operand 2 "" ""))
3406 (clobber (reg:SI PR_REG))]
3409 [(set_attr "type" "call")
3410 (set (attr "fp_mode")
3411 (if_then_else (eq_attr "fpu_single" "yes")
3412 (const_string "single") (const_string "double")))
3413 (set_attr "needs_delay_slot" "yes")])
3415 (define_insn_and_split "call_pcrel"
3416 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3417 (match_operand 1 "" ""))
3418 (use (reg:PSI FPSCR_REG))
3419 (use (reg:SI PIC_REG))
3420 (clobber (reg:SI PR_REG))
3421 (clobber (match_scratch:SI 2 "=r"))]
3428 rtx lab = gen_call_site ();
3430 if (SYMBOL_REF_FLAG (operands[0]))
3431 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3433 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
3434 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], lab));
3437 [(set_attr "type" "call")
3438 (set (attr "fp_mode")
3439 (if_then_else (eq_attr "fpu_single" "yes")
3440 (const_string "single") (const_string "double")))
3441 (set_attr "needs_delay_slot" "yes")])
3443 (define_insn "call_valuei"
3444 [(set (match_operand 0 "" "=rf")
3445 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3446 (match_operand 2 "" "")))
3447 (use (reg:PSI FPSCR_REG))
3448 (clobber (reg:SI PR_REG))]
3451 [(set_attr "type" "call")
3452 (set (attr "fp_mode")
3453 (if_then_else (eq_attr "fpu_single" "yes")
3454 (const_string "single") (const_string "double")))
3455 (set_attr "needs_delay_slot" "yes")])
3457 (define_insn "call_valuei_pcrel"
3458 [(set (match_operand 0 "" "=rf")
3459 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3460 (match_operand 2 "" "")))
3461 (use (reg:PSI FPSCR_REG))
3462 (use (reg:SI PIC_REG))
3463 (use (match_operand 3 "" ""))
3464 (clobber (reg:SI PR_REG))]
3467 [(set_attr "type" "call")
3468 (set (attr "fp_mode")
3469 (if_then_else (eq_attr "fpu_single" "yes")
3470 (const_string "single") (const_string "double")))
3471 (set_attr "needs_delay_slot" "yes")])
3473 (define_insn_and_split "call_value_pcrel"
3474 [(set (match_operand 0 "" "=rf")
3475 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
3476 (match_operand 2 "" "")))
3477 (use (reg:PSI FPSCR_REG))
3478 (use (reg:SI PIC_REG))
3479 (clobber (reg:SI PR_REG))
3480 (clobber (match_scratch:SI 3 "=r"))]
3487 rtx lab = gen_call_site ();
3489 if (SYMBOL_REF_FLAG (operands[1]))
3490 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
3492 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
3493 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
3497 [(set_attr "type" "call")
3498 (set (attr "fp_mode")
3499 (if_then_else (eq_attr "fpu_single" "yes")
3500 (const_string "single") (const_string "double")))
3501 (set_attr "needs_delay_slot" "yes")])
3503 (define_expand "call"
3504 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3505 (match_operand 1 "" ""))
3506 (use (reg:PSI FPSCR_REG))
3507 (clobber (reg:SI PR_REG))])]
3511 if (flag_pic && TARGET_SH2
3512 && GET_CODE (operands[0]) == MEM
3513 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3515 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
3519 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3522 (define_expand "call_value"
3523 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3524 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3525 (match_operand 2 "" "")))
3526 (use (reg:PSI FPSCR_REG))
3527 (clobber (reg:SI PR_REG))])]
3531 if (flag_pic && TARGET_SH2
3532 && GET_CODE (operands[1]) == MEM
3533 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3535 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
3540 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
3543 (define_insn "sibcalli"
3544 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
3545 (match_operand 1 "" ""))
3546 (use (reg:PSI FPSCR_REG))
3550 [(set_attr "needs_delay_slot" "yes")
3551 (set (attr "fp_mode")
3552 (if_then_else (eq_attr "fpu_single" "yes")
3553 (const_string "single") (const_string "double")))
3554 (set_attr "type" "jump_ind")])
3556 (define_insn "sibcalli_pcrel"
3557 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
3558 (match_operand 1 "" ""))
3559 (use (match_operand 2 "" ""))
3560 (use (reg:PSI FPSCR_REG))
3564 [(set_attr "needs_delay_slot" "yes")
3565 (set (attr "fp_mode")
3566 (if_then_else (eq_attr "fpu_single" "yes")
3567 (const_string "single") (const_string "double")))
3568 (set_attr "type" "jump_ind")])
3570 (define_insn_and_split "sibcall_pcrel"
3571 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3572 (match_operand 1 "" ""))
3573 (use (reg:PSI FPSCR_REG))
3574 (clobber (match_scratch:SI 2 "=k"))
3582 rtx lab = gen_call_site ();
3585 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3586 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
3588 SIBLING_CALL_P (call_insn) = 1;
3591 [(set_attr "needs_delay_slot" "yes")
3592 (set (attr "fp_mode")
3593 (if_then_else (eq_attr "fpu_single" "yes")
3594 (const_string "single") (const_string "double")))
3595 (set_attr "type" "jump_ind")])
3597 (define_expand "sibcall"
3599 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3600 (match_operand 1 "" ""))
3601 (use (reg:PSI FPSCR_REG))
3606 if (flag_pic && TARGET_SH2
3607 && GET_CODE (operands[0]) == MEM
3608 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3609 /* The PLT needs the PIC register, but the epilogue would have
3610 to restore it, so we can only use PC-relative PIC calls for
3611 static functions. */
3612 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
3614 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
3618 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3621 (define_expand "sibcall_value"
3622 [(set (match_operand 0 "" "")
3623 (call (match_operand 1 "" "")
3624 (match_operand 2 "" "")))]
3628 emit_call_insn (gen_sibcall (operands[1], operands[2]));
3632 (define_expand "sibcall_epilogue"
3637 sh_expand_epilogue ();
3641 (define_insn "indirect_jump"
3643 (match_operand:SI 0 "arith_reg_operand" "r"))]
3646 [(set_attr "needs_delay_slot" "yes")
3647 (set_attr "type" "jump_ind")])
3649 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3650 ;; which can be present in structured code from indirect jumps which can not
3651 ;; be present in structured code. This allows -fprofile-arcs to work.
3653 ;; For SH1 processors.
3654 (define_insn "casesi_jump_1"
3656 (match_operand:SI 0 "register_operand" "r"))
3657 (use (label_ref (match_operand 1 "" "")))]
3660 [(set_attr "needs_delay_slot" "yes")
3661 (set_attr "type" "jump_ind")])
3663 ;; For all later processors.
3664 (define_insn "casesi_jump_2"
3665 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3666 (label_ref (match_operand 1 "" ""))))
3667 (use (label_ref (match_operand 2 "" "")))]
3669 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
3671 [(set_attr "needs_delay_slot" "yes")
3672 (set_attr "type" "jump_ind")])
3674 ;; Call subroutine returning any type.
3675 ;; ??? This probably doesn't work.
3677 (define_expand "untyped_call"
3678 [(parallel [(call (match_operand 0 "" "")
3680 (match_operand 1 "" "")
3681 (match_operand 2 "" "")])]
3687 emit_call_insn (gen_call (operands[0], const0_rtx));
3689 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3691 rtx set = XVECEXP (operands[2], 0, i);
3692 emit_move_insn (SET_DEST (set), SET_SRC (set));
3695 /* The optimizer does not know that the call sets the function value
3696 registers we stored in the result block. We avoid problems by
3697 claiming that all hard registers are used and clobbered at this
3699 emit_insn (gen_blockage ());
3704 ;; ------------------------------------------------------------------------
3706 ;; ------------------------------------------------------------------------
3709 [(set (reg:SI T_REG)
3710 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3711 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3714 [(set_attr "type" "arith")])
3721 ;; Load address of a label. This is only generated by the casesi expand,
3722 ;; and by machine_dependent_reorg (fixing up fp moves).
3723 ;; This must use unspec, because this only works for labels that are
3727 [(set (reg:SI R0_REG)
3728 (unspec [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
3731 [(set_attr "in_delay_slot" "no")
3732 (set_attr "type" "arith")])
3734 ;; machine_dependent_reorg() will make this a `mova'.
3735 (define_insn "mova_const"
3736 [(set (reg:SI R0_REG)
3737 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
3740 [(set_attr "in_delay_slot" "no")
3741 (set_attr "type" "arith")])
3743 (define_expand "GOTaddr2picreg"
3744 [(set (reg:SI R0_REG)
3745 (unspec [(const (unspec [(match_dup 1)] UNSPEC_PIC))]
3747 (set (match_dup 0) (const (unspec [(match_dup 1)] UNSPEC_PIC)))
3748 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3751 operands[0] = pic_offset_table_rtx;
3752 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
3756 (define_expand "builtin_setjmp_receiver"
3757 [(match_operand 0 "" "")]
3761 emit_insn (gen_GOTaddr2picreg ());
3765 (define_expand "call_site"
3766 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
3770 static HOST_WIDE_INT i = 0;
3771 operands[0] = GEN_INT (i);
3775 (define_expand "sym_label2reg"
3776 [(set (match_operand:SI 0 "" "")
3778 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_PIC))
3780 (match_operand:SI 2 "" "")
3784 (define_expand "symGOT2reg"
3785 [(set (match_operand:SI 0 "" "")
3786 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOT)))
3787 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
3788 (set (match_dup 0) (mem:SI (match_dup 0)))]
3792 operands[2] = pic_offset_table_rtx;
3795 (define_expand "symGOTOFF2reg"
3796 [(set (match_operand:SI 0 "" "")
3797 (const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOTOFF)))
3798 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3802 operands[2] = pic_offset_table_rtx;
3805 (define_expand "symPLT_label2reg"
3806 [(set (match_operand:SI 0 "" "")
3809 (unspec [(match_operand:SI 1 "" "")] UNSPEC_PLT)
3812 (match_operand:SI 2 "" "")
3814 ;; Even though the PIC register is not really used by the call
3815 ;; sequence in which this is expanded, the PLT code assumes the PIC
3816 ;; register is set, so we must not skip its initialization. Since
3817 ;; we only use this expand as part of calling sequences, and never
3818 ;; to take the address of a function, this is the best point to
3819 ;; insert the (use). Using the PLT to take the address of a
3820 ;; function would be wrong, not only because the PLT entry could
3821 ;; then be called from a function that doesn't initialize the PIC
3822 ;; register to the proper GOT, but also because pointers to the
3823 ;; same function might not compare equal, should they be set by
3824 ;; different shared libraries.
3825 (use (reg:SI PIC_REG))]
3829 ;; case instruction for switch statements.
3831 ;; Operand 0 is index
3832 ;; operand 1 is the minimum bound
3833 ;; operand 2 is the maximum bound - minimum bound + 1
3834 ;; operand 3 is CODE_LABEL for the table;
3835 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3837 (define_expand "casesi"
3838 [(match_operand:SI 0 "arith_reg_operand" "")
3839 (match_operand:SI 1 "arith_reg_operand" "")
3840 (match_operand:SI 2 "arith_reg_operand" "")
3841 (match_operand 3 "" "") (match_operand 4 "" "")]
3845 rtx reg = gen_reg_rtx (SImode);
3846 rtx reg2 = gen_reg_rtx (SImode);
3847 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3848 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3849 /* If optimizing, casesi_worker depends on the mode of the instruction
3850 before label it 'uses' - operands[3]. */
3851 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3853 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3855 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3857 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3858 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3859 operands[3], but to lab. We will fix this up in
3860 machine_dependent_reorg. */
3865 (define_expand "casesi_0"
3866 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3867 (set (match_dup 4) (minus:SI (match_dup 4)
3868 (match_operand:SI 1 "arith_operand" "")))
3870 (gtu:SI (match_dup 4)
3871 (match_operand:SI 2 "arith_reg_operand" "")))
3873 (if_then_else (ne (reg:SI T_REG)
3875 (label_ref (match_operand 3 "" ""))
3880 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3881 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3882 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3884 (define_insn "casesi_worker_0"
3885 [(set (match_operand:SI 0 "register_operand" "=r,r")
3886 (unspec [(match_operand 1 "register_operand" "0,r")
3887 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3888 (clobber (match_scratch:SI 3 "=X,1"))
3889 (clobber (match_scratch:SI 4 "=&z,z"))]
3894 [(set (match_operand:SI 0 "register_operand" "")
3895 (unspec [(match_operand 1 "register_operand" "")
3896 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3897 (clobber (match_scratch:SI 3 ""))
3898 (clobber (match_scratch:SI 4 ""))]
3899 "! TARGET_SH2 && reload_completed"
3900 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3901 (parallel [(set (match_dup 0)
3902 (unspec [(reg:SI R0_REG) (match_dup 1)
3903 (label_ref (match_dup 2))] UNSPEC_CASESI))
3904 (clobber (match_dup 3))])
3905 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3906 "LABEL_NUSES (operands[2])++;")
3909 [(set (match_operand:SI 0 "register_operand" "")
3910 (unspec [(match_operand 1 "register_operand" "")
3911 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3912 (clobber (match_scratch:SI 3 ""))
3913 (clobber (match_scratch:SI 4 ""))]
3914 "TARGET_SH2 && reload_completed"
3915 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3916 (parallel [(set (match_dup 0)
3917 (unspec [(reg:SI R0_REG) (match_dup 1)
3918 (label_ref (match_dup 2))] UNSPEC_CASESI))
3919 (clobber (match_dup 3))])]
3920 "LABEL_NUSES (operands[2])++;")
3922 (define_insn "*casesi_worker"
3923 [(set (match_operand:SI 0 "register_operand" "=r,r")
3924 (unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
3925 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3926 (clobber (match_scratch:SI 3 "=X,1"))]
3930 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3932 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3935 switch (GET_MODE (diff_vec))
3938 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3940 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3942 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3943 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3944 return \"mov.b @(r0,%1),%0\";
3949 [(set_attr "length" "4")])
3951 (define_expand "return"
3953 "reload_completed && ! sh_need_epilogue ()"
3956 (define_insn "*return_i"
3960 [(set_attr "type" "return")
3961 (set_attr "needs_delay_slot" "yes")])
3963 (define_expand "prologue"
3966 "sh_expand_prologue (); DONE;")
3968 (define_expand "epilogue"
3971 "sh_expand_epilogue ();")
3973 (define_insn "blockage"
3974 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
3977 [(set_attr "length" "0")])
3979 ;; ------------------------------------------------------------------------
3981 ;; ------------------------------------------------------------------------
3984 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3985 (eq:SI (reg:SI T_REG) (const_int 1)))]
3988 [(set_attr "type" "arith")])
3990 (define_expand "seq"
3991 [(set (match_operand:SI 0 "arith_reg_operand" "")
3994 "operands[1] = prepare_scc_operands (EQ);")
3996 (define_expand "slt"
3997 [(set (match_operand:SI 0 "arith_reg_operand" "")
4000 "operands[1] = prepare_scc_operands (LT);")
4002 (define_expand "sle"
4003 [(match_operand:SI 0 "arith_reg_operand" "")]
4007 rtx tmp = sh_compare_op0;
4008 sh_compare_op0 = sh_compare_op1;
4009 sh_compare_op1 = tmp;
4010 emit_insn (gen_sge (operands[0]));
4014 (define_expand "sgt"
4015 [(set (match_operand:SI 0 "arith_reg_operand" "")
4018 "operands[1] = prepare_scc_operands (GT);")
4020 (define_expand "sge"
4021 [(set (match_operand:SI 0 "arith_reg_operand" "")
4026 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
4030 rtx lab = gen_label_rtx ();
4031 prepare_scc_operands (EQ);
4032 emit_jump_insn (gen_branch_true (lab));
4033 prepare_scc_operands (GT);
4035 emit_insn (gen_movt (operands[0]));
4038 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
4041 operands[1] = prepare_scc_operands (GE);
4044 (define_expand "sgtu"
4045 [(set (match_operand:SI 0 "arith_reg_operand" "")
4048 "operands[1] = prepare_scc_operands (GTU);")
4050 (define_expand "sltu"
4051 [(set (match_operand:SI 0 "arith_reg_operand" "")
4054 "operands[1] = prepare_scc_operands (LTU);")
4056 (define_expand "sleu"
4057 [(set (match_operand:SI 0 "arith_reg_operand" "")
4060 "operands[1] = prepare_scc_operands (LEU);")
4062 (define_expand "sgeu"
4063 [(set (match_operand:SI 0 "arith_reg_operand" "")
4066 "operands[1] = prepare_scc_operands (GEU);")
4068 ;; sne moves the complement of the T reg to DEST like this:
4072 ;; This is better than xoring compare result with 1 because it does
4073 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
4076 (define_expand "sne"
4077 [(set (match_dup 2) (const_int -1))
4078 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
4079 (neg:SI (plus:SI (match_dup 1)
4082 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
4087 operands[1] = prepare_scc_operands (EQ);
4088 operands[2] = gen_reg_rtx (SImode);
4091 ;; Use the same trick for FP sle / sge
4092 (define_expand "movnegt"
4093 [(set (match_dup 2) (const_int -1))
4094 (parallel [(set (match_operand 0 "" "")
4095 (neg:SI (plus:SI (match_dup 1)
4098 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
4101 "operands[2] = gen_reg_rtx (SImode);")
4103 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
4104 ;; This prevents a regression that occurred when we switched from xor to
4108 [(set (match_operand:SI 0 "arith_reg_operand" "")
4109 (plus:SI (reg:SI T_REG)
4112 [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
4113 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
4116 ;; -------------------------------------------------------------------------
4117 ;; Instructions to cope with inline literal tables
4118 ;; -------------------------------------------------------------------------
4120 ; 2 byte integer in line
4122 (define_insn "consttable_2"
4123 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4128 assemble_integer (operands[0], 2, 1);
4131 [(set_attr "length" "2")
4132 (set_attr "in_delay_slot" "no")])
4134 ; 4 byte integer in line
4136 (define_insn "consttable_4"
4137 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4142 assemble_integer (operands[0], 4, 1);
4145 [(set_attr "length" "4")
4146 (set_attr "in_delay_slot" "no")])
4148 ; 8 byte integer in line
4150 (define_insn "consttable_8"
4151 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")]
4156 assemble_integer (operands[0], 8, 1);
4159 [(set_attr "length" "8")
4160 (set_attr "in_delay_slot" "no")])
4162 ; 4 byte floating point
4164 (define_insn "consttable_sf"
4165 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")]
4170 union real_extract u;
4171 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4172 assemble_real (u.d, SFmode);
4175 [(set_attr "length" "4")
4176 (set_attr "in_delay_slot" "no")])
4178 ; 8 byte floating point
4180 (define_insn "consttable_df"
4181 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")]
4186 union real_extract u;
4187 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4188 assemble_real (u.d, DFmode);
4191 [(set_attr "length" "8")
4192 (set_attr "in_delay_slot" "no")])
4194 ;; Alignment is needed for some constant tables; it may also be added for
4195 ;; Instructions at the start of loops, or after unconditional branches.
4196 ;; ??? We would get more accurate lengths if we did instruction
4197 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
4198 ;; here is too conservative.
4200 ; align to a two byte boundary
4202 (define_expand "align_2"
4203 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
4207 ; align to a four byte boundary
4208 ;; align_4 and align_log are instructions for the starts of loops, or
4209 ;; after unconditional branches, which may take up extra room.
4211 (define_expand "align_4"
4212 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
4216 ; align to a cache line boundary
4218 (define_insn "align_log"
4219 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
4222 [(set_attr "length" "0")
4223 (set_attr "in_delay_slot" "no")])
4225 ; emitted at the end of the literal table, used to emit the
4226 ; 32bit branch labels if needed.
4228 (define_insn "consttable_end"
4229 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
4231 "* return output_jump_label_table ();"
4232 [(set_attr "in_delay_slot" "no")])
4234 ;; -------------------------------------------------------------------------
4236 ;; -------------------------------------------------------------------------
4238 ;; String/block move insn.
4240 (define_expand "movstrsi"
4241 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
4242 (mem:BLK (match_operand:BLK 1 "" "")))
4243 (use (match_operand:SI 2 "nonmemory_operand" ""))
4244 (use (match_operand:SI 3 "immediate_operand" ""))
4245 (clobber (reg:SI PR_REG))
4246 (clobber (reg:SI R4_REG))
4247 (clobber (reg:SI R5_REG))
4248 (clobber (reg:SI R0_REG))])]
4252 if(expand_block_move (operands))
4257 (define_insn "block_move_real"
4258 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4259 (mem:BLK (reg:SI R5_REG)))
4260 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4261 (clobber (reg:SI PR_REG))
4262 (clobber (reg:SI R0_REG))])]
4265 [(set_attr "type" "sfunc")
4266 (set_attr "needs_delay_slot" "yes")])
4268 (define_insn "block_lump_real"
4269 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4270 (mem:BLK (reg:SI R5_REG)))
4271 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4272 (use (reg:SI R6_REG))
4273 (clobber (reg:SI PR_REG))
4274 (clobber (reg:SI T_REG))
4275 (clobber (reg:SI R4_REG))
4276 (clobber (reg:SI R5_REG))
4277 (clobber (reg:SI R6_REG))
4278 (clobber (reg:SI R0_REG))])]
4281 [(set_attr "type" "sfunc")
4282 (set_attr "needs_delay_slot" "yes")])
4284 (define_insn "block_move_real_i4"
4285 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4286 (mem:BLK (reg:SI R5_REG)))
4287 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4288 (clobber (reg:SI PR_REG))
4289 (clobber (reg:SI R0_REG))
4290 (clobber (reg:SI R1_REG))
4291 (clobber (reg:SI R2_REG))])]
4294 [(set_attr "type" "sfunc")
4295 (set_attr "needs_delay_slot" "yes")])
4297 (define_insn "block_lump_real_i4"
4298 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4299 (mem:BLK (reg:SI R5_REG)))
4300 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4301 (use (reg:SI R6_REG))
4302 (clobber (reg:SI PR_REG))
4303 (clobber (reg:SI T_REG))
4304 (clobber (reg:SI R4_REG))
4305 (clobber (reg:SI R5_REG))
4306 (clobber (reg:SI R6_REG))
4307 (clobber (reg:SI R0_REG))
4308 (clobber (reg:SI R1_REG))
4309 (clobber (reg:SI R2_REG))
4310 (clobber (reg:SI R3_REG))])]
4313 [(set_attr "type" "sfunc")
4314 (set_attr "needs_delay_slot" "yes")])
4316 ;; -------------------------------------------------------------------------
4317 ;; Floating point instructions.
4318 ;; -------------------------------------------------------------------------
4320 ;; ??? All patterns should have a type attribute.
4322 (define_expand "fpu_switch0"
4323 [(set (match_operand:SI 0 "" "") (match_dup 2))
4324 (set (match_dup 1) (mem:PSI (match_dup 0)))]
4328 operands[1] = get_fpscr_rtx ();
4329 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4331 operands[2] = legitimize_pic_address (operands[2], SImode,
4332 no_new_pseudos ? operands[0] : 0);
4335 (define_expand "fpu_switch1"
4336 [(set (match_operand:SI 0 "" "") (match_dup 2))
4337 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
4338 (set (match_dup 1) (mem:PSI (match_dup 3)))]
4342 operands[1] = get_fpscr_rtx ();
4343 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4345 operands[2] = legitimize_pic_address (operands[2], SImode,
4346 no_new_pseudos ? operands[0] : 0);
4347 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
4350 (define_expand "movpsi"
4351 [(set (match_operand:PSI 0 "register_operand" "")
4352 (match_operand:PSI 1 "general_movsrc_operand" ""))]
4356 ;; The c / m alternative is a fake to guide reload to load directly into
4357 ;; fpscr, since reload doesn't know how to use post-increment.
4358 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
4359 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
4360 ;; predicate after reload.
4361 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
4362 ;; like a gpr <-> fpul move.
4363 (define_insn "fpu_switch"
4364 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
4365 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
4367 && (! reload_completed
4368 || true_regnum (operands[0]) != FPSCR_REG
4369 || GET_CODE (operands[1]) != MEM
4370 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
4372 ! precision stays the same
4380 [(set_attr "length" "0,2,2,4,2,2,2,2")
4381 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
4384 [(set (reg:PSI FPSCR_REG)
4385 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4386 "TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
4387 [(set (match_dup 0) (match_dup 0))]
4390 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4391 gen_rtx (MEM, PSImode,
4392 gen_rtx (POST_INC, Pmode,
4394 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4398 [(set (reg:PSI FPSCR_REG)
4399 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4401 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
4404 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4405 gen_rtx (MEM, PSImode,
4406 gen_rtx (POST_INC, Pmode,
4408 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4411 ;; ??? This uses the fp unit, but has no type indicating that.
4412 ;; If we did that, this would either give a bogus latency or introduce
4413 ;; a bogus FIFO constraint.
4414 ;; Since this insn is currently only used for prologues/epilogues,
4415 ;; it is probably best to claim no function unit, which matches the
4417 (define_insn "toggle_sz"
4418 [(set (reg:PSI FPSCR_REG)
4419 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
4423 (define_expand "addsf3"
4424 [(match_operand:SF 0 "arith_reg_operand" "")
4425 (match_operand:SF 1 "arith_reg_operand" "")
4426 (match_operand:SF 2 "arith_reg_operand" "")]
4428 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
4430 (define_insn "addsf3_i"
4431 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4432 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4433 (match_operand:SF 2 "arith_reg_operand" "f")))
4434 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4437 [(set_attr "type" "fp")
4438 (set_attr "fp_mode" "single")])
4440 (define_expand "subsf3"
4441 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4442 (match_operand:SF 1 "fp_arith_reg_operand" "")
4443 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4445 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
4447 (define_insn "subsf3_i"
4448 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4449 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
4450 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4451 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4454 [(set_attr "type" "fp")
4455 (set_attr "fp_mode" "single")])
4457 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
4458 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
4459 ;; mixed-precision SH4 targets. To allow it to be still generated for the
4460 ;; SH3E, we use a separate insn for SH3E mulsf3.
4462 (define_expand "mulsf3"
4463 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4464 (match_operand:SF 1 "fp_arith_reg_operand" "")
4465 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4470 expand_sf_binop (&gen_mulsf3_i4, operands);
4472 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
4476 (define_insn "mulsf3_i4"
4477 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4478 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4479 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4480 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4483 [(set_attr "type" "fp")
4484 (set_attr "fp_mode" "single")])
4486 (define_insn "mulsf3_ie"
4487 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4488 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4489 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
4490 "TARGET_SH3E && ! TARGET_SH4"
4492 [(set_attr "type" "fp")])
4494 (define_insn "*macsf3"
4495 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4496 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
4497 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
4498 (match_operand:SF 3 "arith_reg_operand" "0")))
4499 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
4500 "TARGET_SH3E && ! TARGET_SH4"
4502 [(set_attr "type" "fp")
4503 (set_attr "fp_mode" "single")])
4505 (define_expand "divsf3"
4506 [(match_operand:SF 0 "arith_reg_operand" "")
4507 (match_operand:SF 1 "arith_reg_operand" "")
4508 (match_operand:SF 2 "arith_reg_operand" "")]
4510 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
4512 (define_insn "divsf3_i"
4513 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4514 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
4515 (match_operand:SF 2 "arith_reg_operand" "f")))
4516 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4519 [(set_attr "type" "fdiv")
4520 (set_attr "fp_mode" "single")])
4522 (define_expand "floatsisf2"
4523 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
4524 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
4530 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4535 (define_insn "floatsisf2_i4"
4536 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4537 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
4538 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4541 [(set_attr "type" "fp")
4542 (set_attr "fp_mode" "single")])
4544 (define_insn "*floatsisf2_ie"
4545 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4546 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
4547 "TARGET_SH3E && ! TARGET_SH4"
4549 [(set_attr "type" "fp")])
4551 (define_expand "fix_truncsfsi2"
4552 [(set (match_operand:SI 0 "fpul_operand" "=y")
4553 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4559 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4564 (define_insn "fix_truncsfsi2_i4"
4565 [(set (match_operand:SI 0 "fpul_operand" "=y")
4566 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4567 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4570 [(set_attr "type" "fp")
4571 (set_attr "fp_mode" "single")])
4573 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
4574 ;; fix_truncsfsi2_i4.
4575 ;; (define_insn "fix_truncsfsi2_i4_2"
4576 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4577 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4578 ;; (use (reg:PSI FPSCR_REG))
4579 ;; (clobber (reg:SI FPUL_REG))]
4582 ;; [(set_attr "length" "4")
4583 ;; (set_attr "fp_mode" "single")])
4586 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4587 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4588 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4589 ;; (clobber (reg:SI FPUL_REG))]
4591 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4592 ;; (use (match_dup 2))])
4593 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4595 (define_insn "*fixsfsi"
4596 [(set (match_operand:SI 0 "fpul_operand" "=y")
4597 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4598 "TARGET_SH3E && ! TARGET_SH4"
4600 [(set_attr "type" "fp")])
4602 (define_insn "cmpgtsf_t"
4603 [(set (reg:SI T_REG)
4604 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4605 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4606 "TARGET_SH3E && ! TARGET_SH4"
4608 [(set_attr "type" "fp")
4609 (set_attr "fp_mode" "single")])
4611 (define_insn "cmpeqsf_t"
4612 [(set (reg:SI T_REG)
4613 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4614 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4615 "TARGET_SH3E && ! TARGET_SH4"
4617 [(set_attr "type" "fp")
4618 (set_attr "fp_mode" "single")])
4620 (define_insn "ieee_ccmpeqsf_t"
4621 [(set (reg:SI T_REG)
4622 (ior:SI (reg:SI T_REG)
4623 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4624 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
4625 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4626 "* return output_ieee_ccmpeq (insn, operands);"
4627 [(set_attr "length" "4")])
4630 (define_insn "cmpgtsf_t_i4"
4631 [(set (reg:SI T_REG)
4632 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4633 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4634 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4637 [(set_attr "type" "fp")
4638 (set_attr "fp_mode" "single")])
4640 (define_insn "cmpeqsf_t_i4"
4641 [(set (reg:SI T_REG)
4642 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4643 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4644 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4647 [(set_attr "type" "fp")
4648 (set_attr "fp_mode" "single")])
4650 (define_insn "*ieee_ccmpeqsf_t_4"
4651 [(set (reg:SI T_REG)
4652 (ior:SI (reg:SI T_REG)
4653 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4654 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
4655 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4656 "TARGET_IEEE && TARGET_SH4"
4657 "* return output_ieee_ccmpeq (insn, operands);"
4658 [(set_attr "length" "4")
4659 (set_attr "fp_mode" "single")])
4661 (define_expand "cmpsf"
4662 [(set (reg:SI T_REG)
4663 (compare (match_operand:SF 0 "arith_operand" "")
4664 (match_operand:SF 1 "arith_operand" "")))]
4668 sh_compare_op0 = operands[0];
4669 sh_compare_op1 = operands[1];
4673 (define_expand "negsf2"
4674 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4675 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4677 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4679 (define_insn "negsf2_i"
4680 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4681 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4682 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4685 [(set_attr "type" "fmove")
4686 (set_attr "fp_mode" "single")])
4688 (define_expand "sqrtsf2"
4689 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4690 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4692 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4694 (define_insn "sqrtsf2_i"
4695 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4696 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4697 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4700 [(set_attr "type" "fdiv")
4701 (set_attr "fp_mode" "single")])
4703 (define_expand "abssf2"
4704 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4705 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4707 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4709 (define_insn "abssf2_i"
4710 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4711 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4712 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4715 [(set_attr "type" "fmove")
4716 (set_attr "fp_mode" "single")])
4718 (define_expand "adddf3"
4719 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4720 (match_operand:DF 1 "fp_arith_reg_operand" "")
4721 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4723 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4725 (define_insn "adddf3_i"
4726 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4727 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4728 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4729 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4732 [(set_attr "type" "dfp_arith")
4733 (set_attr "fp_mode" "double")])
4735 (define_expand "subdf3"
4736 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4737 (match_operand:DF 1 "fp_arith_reg_operand" "")
4738 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4740 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4742 (define_insn "subdf3_i"
4743 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4744 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4745 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4746 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4749 [(set_attr "type" "dfp_arith")
4750 (set_attr "fp_mode" "double")])
4752 (define_expand "muldf3"
4753 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4754 (match_operand:DF 1 "fp_arith_reg_operand" "")
4755 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4757 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4759 (define_insn "muldf3_i"
4760 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4761 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4762 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4763 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4766 [(set_attr "type" "dfp_arith")
4767 (set_attr "fp_mode" "double")])
4769 (define_expand "divdf3"
4770 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4771 (match_operand:DF 1 "fp_arith_reg_operand" "")
4772 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4774 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4776 (define_insn "divdf3_i"
4777 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4778 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4779 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4780 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4783 [(set_attr "type" "dfdiv")
4784 (set_attr "fp_mode" "double")])
4786 (define_expand "floatsidf2"
4787 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4788 (match_operand:SI 1 "fpul_operand" "")]
4792 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1], get_fpscr_rtx ()));
4796 (define_insn "floatsidf2_i"
4797 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4798 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
4799 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4802 [(set_attr "type" "dfp_conv")
4803 (set_attr "fp_mode" "double")])
4805 (define_expand "fix_truncdfsi2"
4806 [(match_operand:SI 0 "fpul_operand" "")
4807 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4811 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1], get_fpscr_rtx ()));
4815 (define_insn "fix_truncdfsi2_i"
4816 [(set (match_operand:SI 0 "fpul_operand" "=y")
4817 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4818 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4821 [(set_attr "type" "dfp_conv")
4822 (set_attr "fp_mode" "double")])
4824 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
4825 ;; fix_truncdfsi2_i.
4826 ;; (define_insn "fix_truncdfsi2_i4"
4827 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4828 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4829 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4830 ;; (clobber (reg:SI FPUL_REG))]
4833 ;; [(set_attr "length" "4")
4834 ;; (set_attr "fp_mode" "double")])
4837 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4838 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4839 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4840 ;; (clobber (reg:SI FPUL_REG))]
4842 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4843 ;; (use (match_dup 2))])
4844 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4846 (define_insn "cmpgtdf_t"
4847 [(set (reg:SI T_REG)
4848 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4849 (match_operand:DF 1 "arith_reg_operand" "f")))
4850 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4853 [(set_attr "type" "dfp_cmp")
4854 (set_attr "fp_mode" "double")])
4856 (define_insn "cmpeqdf_t"
4857 [(set (reg:SI T_REG)
4858 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4859 (match_operand:DF 1 "arith_reg_operand" "f")))
4860 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4863 [(set_attr "type" "dfp_cmp")
4864 (set_attr "fp_mode" "double")])
4866 (define_insn "*ieee_ccmpeqdf_t"
4867 [(set (reg:SI T_REG)
4868 (ior:SI (reg:SI T_REG)
4869 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4870 (match_operand:DF 1 "arith_reg_operand" "f"))))
4871 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4872 "TARGET_IEEE && TARGET_SH4"
4873 "* return output_ieee_ccmpeq (insn, operands);"
4874 [(set_attr "length" "4")
4875 (set_attr "fp_mode" "double")])
4877 (define_expand "cmpdf"
4878 [(set (reg:SI T_REG)
4879 (compare (match_operand:DF 0 "arith_operand" "")
4880 (match_operand:DF 1 "arith_operand" "")))]
4884 sh_compare_op0 = operands[0];
4885 sh_compare_op1 = operands[1];
4889 (define_expand "negdf2"
4890 [(match_operand:DF 0 "arith_reg_operand" "")
4891 (match_operand:DF 1 "arith_reg_operand" "")]
4893 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4895 (define_insn "negdf2_i"
4896 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4897 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4898 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4901 [(set_attr "type" "fmove")
4902 (set_attr "fp_mode" "double")])
4904 (define_expand "sqrtdf2"
4905 [(match_operand:DF 0 "arith_reg_operand" "")
4906 (match_operand:DF 1 "arith_reg_operand" "")]
4908 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4910 (define_insn "sqrtdf2_i"
4911 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4912 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4913 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4916 [(set_attr "type" "dfdiv")
4917 (set_attr "fp_mode" "double")])
4919 (define_expand "absdf2"
4920 [(match_operand:DF 0 "arith_reg_operand" "")
4921 (match_operand:DF 1 "arith_reg_operand" "")]
4923 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4925 (define_insn "absdf2_i"
4926 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4927 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4928 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4931 [(set_attr "type" "fmove")
4932 (set_attr "fp_mode" "double")])
4934 (define_expand "extendsfdf2"
4935 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4936 (match_operand:SF 1 "fpul_operand" "")]
4940 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4944 (define_insn "extendsfdf2_i4"
4945 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4946 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
4947 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4950 [(set_attr "type" "fp")
4951 (set_attr "fp_mode" "double")])
4953 (define_expand "truncdfsf2"
4954 [(match_operand:SF 0 "fpul_operand" "")
4955 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4959 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4963 (define_insn "truncdfsf2_i4"
4964 [(set (match_operand:SF 0 "fpul_operand" "=y")
4965 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4966 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4969 [(set_attr "type" "fp")
4970 (set_attr "fp_mode" "double")])
4972 ;; Bit field extract patterns. These give better code for packed bitfields,
4973 ;; because they allow auto-increment addresses to be generated.
4975 (define_expand "insv"
4976 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
4977 (match_operand:SI 1 "immediate_operand" "")
4978 (match_operand:SI 2 "immediate_operand" ""))
4979 (match_operand:SI 3 "general_operand" ""))]
4980 "! TARGET_LITTLE_ENDIAN"
4983 rtx addr_target, orig_address, shift_reg;
4986 /* ??? expmed doesn't care for non-register predicates. */
4987 if (! memory_operand (operands[0], VOIDmode)
4988 || ! immediate_operand (operands[1], VOIDmode)
4989 || ! immediate_operand (operands[2], VOIDmode)
4990 || ! general_operand (operands[3], VOIDmode))
4992 /* If this isn't a 16 / 24 / 32 bit field, or if
4993 it doesn't start on a byte boundary, then fail. */
4994 size = INTVAL (operands[1]);
4995 if (size < 16 || size > 32 || size % 8 != 0
4996 || (INTVAL (operands[2]) % 8) != 0)
5000 orig_address = XEXP (operands[0], 0);
5001 shift_reg = gen_reg_rtx (SImode);
5002 emit_insn (gen_movsi (shift_reg, operands[3]));
5003 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
5005 operands[0] = change_address (operands[0], QImode, addr_target);
5006 emit_insn (gen_movqi (operands[0], gen_rtx_SUBREG (QImode, shift_reg, 0)));
5010 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
5011 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
5012 emit_insn (gen_movqi (operands[0],
5013 gen_rtx_SUBREG (QImode, shift_reg, 0)));
5019 ;; -------------------------------------------------------------------------
5021 ;; -------------------------------------------------------------------------
5023 ;; This matches cases where a stack pointer increment at the start of the
5024 ;; epilogue combines with a stack slot read loading the return value.
5027 [(set (match_operand:SI 0 "arith_reg_operand" "")
5028 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
5029 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
5030 "REGNO (operands[1]) != REGNO (operands[0])"
5033 ;; See the comment on the dt combiner pattern above.
5036 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
5037 (plus:SI (match_dup 0)
5040 (eq:SI (match_dup 0)
5045 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
5046 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
5047 ;; reload when the constant is too large for a reg+offset address.
5049 ;; ??? We would get much better code if this was done in reload. This would
5050 ;; require modifying find_reloads_address to recognize that if the constant
5051 ;; is out-of-range for an immediate add, then we get better code by reloading
5052 ;; the constant into a register than by reloading the sum into a register,
5053 ;; since the former is one instruction shorter if the address does not need
5054 ;; to be offsettable. Unfortunately this does not work, because there is
5055 ;; only one register, r0, that can be used as an index register. This register
5056 ;; is also the function return value register. So, if we try to force reload
5057 ;; to use double-reg addresses, then we end up with some instructions that
5058 ;; need to use r0 twice. The only way to fix this is to change the calling
5059 ;; convention so that r0 is not used to return values.
5062 [(set (match_operand:SI 0 "register_operand" "=r")
5063 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5064 (set (mem:SI (match_dup 0))
5065 (match_operand:SI 2 "general_movsrc_operand" ""))]
5066 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5067 "mov.l %2,@(%0,%1)")
5070 [(set (match_operand:SI 0 "register_operand" "=r")
5071 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5072 (set (match_operand:SI 2 "general_movdst_operand" "")
5073 (mem:SI (match_dup 0)))]
5074 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5075 "mov.l @(%0,%1),%2")
5078 [(set (match_operand:SI 0 "register_operand" "=r")
5079 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5080 (set (mem:HI (match_dup 0))
5081 (match_operand:HI 2 "general_movsrc_operand" ""))]
5082 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5083 "mov.w %2,@(%0,%1)")
5086 [(set (match_operand:SI 0 "register_operand" "=r")
5087 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5088 (set (match_operand:HI 2 "general_movdst_operand" "")
5089 (mem:HI (match_dup 0)))]
5090 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5091 "mov.w @(%0,%1),%2")
5094 [(set (match_operand:SI 0 "register_operand" "=r")
5095 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5096 (set (mem:QI (match_dup 0))
5097 (match_operand:QI 2 "general_movsrc_operand" ""))]
5098 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5099 "mov.b %2,@(%0,%1)")
5102 [(set (match_operand:SI 0 "register_operand" "=r")
5103 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5104 (set (match_operand:QI 2 "general_movdst_operand" "")
5105 (mem:QI (match_dup 0)))]
5106 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5107 "mov.b @(%0,%1),%2")
5110 [(set (match_operand:SI 0 "register_operand" "=r")
5111 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5112 (set (mem:SF (match_dup 0))
5113 (match_operand:SF 2 "general_movsrc_operand" ""))]
5114 "REGNO (operands[0]) == 0
5115 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5116 || (GET_CODE (operands[2]) == SUBREG
5117 && REGNO (SUBREG_REG (operands[2])) < 16))
5118 && reg_unused_after (operands[0], insn)"
5119 "mov.l %2,@(%0,%1)")
5122 [(set (match_operand:SI 0 "register_operand" "=r")
5123 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5124 (set (match_operand:SF 2 "general_movdst_operand" "")
5126 (mem:SF (match_dup 0)))]
5127 "REGNO (operands[0]) == 0
5128 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5129 || (GET_CODE (operands[2]) == SUBREG
5130 && REGNO (SUBREG_REG (operands[2])) < 16))
5131 && reg_unused_after (operands[0], insn)"
5132 "mov.l @(%0,%1),%2")
5135 [(set (match_operand:SI 0 "register_operand" "=r")
5136 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5137 (set (mem:SF (match_dup 0))
5138 (match_operand:SF 2 "general_movsrc_operand" ""))]
5139 "REGNO (operands[0]) == 0
5140 && ((GET_CODE (operands[2]) == REG
5141 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5142 || (GET_CODE (operands[2]) == SUBREG
5143 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5144 && reg_unused_after (operands[0], insn)"
5145 "fmov{.s|} %2,@(%0,%1)")
5148 [(set (match_operand:SI 0 "register_operand" "=r")
5149 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5150 (set (match_operand:SF 2 "general_movdst_operand" "")
5152 (mem:SF (match_dup 0)))]
5153 "REGNO (operands[0]) == 0
5154 && ((GET_CODE (operands[2]) == REG
5155 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5156 || (GET_CODE (operands[2]) == SUBREG
5157 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5158 && reg_unused_after (operands[0], insn)"
5159 "fmov{.s|} @(%0,%1),%2")
5161 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
5162 (define_insn "sp_switch_1"
5169 xoperands[0] = sp_switch;
5170 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
5171 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
5172 return \"mov r0,r15\";
5174 [(set_attr "length" "10")])
5176 ;; Switch back to the original stack for interrupt functions with the
5177 ;; sp_switch attribute. */
5178 (define_insn "sp_switch_2"
5181 "mov.l @r15+,r15\;mov.l @r15+,r0"
5182 [(set_attr "length" "4")])