1 ;; Scheduling description for Niagara-2 and Niagara-3.
2 ;; Copyright (C) 2007, 2011 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Niagara-2 and Niagara-3 are single-issue processors.
22 (define_automaton "niagara2_0")
24 (define_cpu_unit "niag2_pipe" "niagara2_0")
26 (define_insn_reservation "niag2_25cycle" 25
27 (and (eq_attr "cpu" "niagara2,niagara3")
28 (eq_attr "type" "flushw"))
31 (define_insn_reservation "niag2_5cycle" 5
32 (and (eq_attr "cpu" "niagara2,niagara3")
33 (eq_attr "type" "multi,flushw,iflush,trap"))
36 (define_insn_reservation "niag2_6cycle" 4
37 (and (eq_attr "cpu" "niagara2,niagara3")
38 (eq_attr "type" "savew"))
41 /* Most basic operations are single-cycle. */
42 (define_insn_reservation "niag2_ialu" 1
43 (and (eq_attr "cpu" "niagara2,niagara3")
44 (eq_attr "type" "ialu,shift,compare,cmove"))
47 (define_insn_reservation "niag2_imul" 5
48 (and (eq_attr "cpu" "niagara2,niagara3")
49 (eq_attr "type" "imul"))
52 (define_insn_reservation "niag2_idiv" 31
53 (and (eq_attr "cpu" "niagara2,niagara3")
54 (eq_attr "type" "idiv"))
57 (define_insn_reservation "niag2_branch" 5
58 (and (eq_attr "cpu" "niagara2,niagara3")
59 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
62 (define_insn_reservation "niag2_3cycle_load" 3
63 (and (eq_attr "cpu" "niagara2,niagara3")
64 (eq_attr "type" "load,fpload"))
67 (define_insn_reservation "niag2_1cycle_store" 1
68 (and (eq_attr "cpu" "niagara2,niagara3")
69 (eq_attr "type" "store,fpstore"))
72 (define_insn_reservation "niag2_fp" 3
73 (and (eq_attr "cpu" "niagara2,niagara3")
74 (eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
77 (define_insn_reservation "niag2_fdivs" 19
78 (and (eq_attr "cpu" "niagara2,niagara3")
79 (eq_attr "type" "fpdivs"))
82 (define_insn_reservation "niag2_fdivd" 33
83 (and (eq_attr "cpu" "niagara2,niagara3")
84 (eq_attr "type" "fpdivd"))
87 (define_insn_reservation "niag2_vis" 6
88 (and (eq_attr "cpu" "niagara2,niagara3")
89 (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))