gcc/config/sparc/predicates.md

   1 ;; Predicate definitions for SPARC.
   2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  19 ;; Boston, MA 02111-1307, USA.
  20
  21 ;; Predicates for numerical constants.
  22
  23 ;; Return true if OP is the zero constant for MODE.
  24 (define_predicate "const_zero_operand"
  25   (and (match_code "const_int,const_double,const_vector")
  26        (match_test "op == CONST0_RTX (mode)")))
  27
  28 ;; Return true if OP is the one constant for MODE.
  29 (define_predicate "const_one_operand"
  30   (and (match_code "const_int,const_double,const_vector")
  31        (match_test "op == CONST1_RTX (mode)")))
  32
  33 ;; Return true if OP is the integer constant 4096.
  34 (define_predicate "const_4096_operand"
  35   (and (match_code "const_int")
  36        (match_test "INTVAL (op) == 4096")))
  37
  38 ;; Return true if OP is a constant that is representable by a 13-bit
  39 ;; signed field.  This is an acceptable immediate operand for most
  40 ;; 3-address instructions.
  41 (define_predicate "small_int_operand"
  42   (and (match_code "const_int")
  43        (match_test "SPARC_SIMM13_P (INTVAL (op))")))
  44
  45 ;; Return true if OP is a constant operand for the umul instruction.  That
  46 ;; instruction sign-extends immediate values just like all other SPARC
  47 ;; instructions, but interprets the extended result as an unsigned number.
  48 (define_predicate "uns_small_int_operand"
  49   (match_code "const_int,const_double")
  50 {
  51 #if HOST_BITS_PER_WIDE_INT == 32
  52   return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
  53           || (GET_CODE (op) == CONST_DOUBLE
  54               && CONST_DOUBLE_HIGH (op) == 0
  55               && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
  56 #else
  57   return (GET_CODE (op) == CONST_INT
  58           && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
  59               || (INTVAL (op) >= 0xFFFFF000
  60                   && INTVAL (op) <= 0xFFFFFFFF)));
  61 #endif
  62 })
  63
  64 ;; Return true if OP is a constant that can be loaded by the sethi instruction.
  65 ;; The first test avoids emitting sethi to load zero for example.
  66 (define_predicate "const_high_operand"
  67   (and (match_code "const_int")
  68        (and (match_test "INTVAL (op) & ~(HOST_WIDE_INT)0x3ff")
  69             (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))"))))
  70
  71
  72 ;; Predicates for symbolic constants.
  73
  74 ;; Return true if OP is either a symbol reference or a sum of a symbol
  75 ;; reference and a constant.
  76 (define_predicate "symbolic_operand"
  77   (match_code "symbol_ref,label_ref,const")
  78 {
  79   enum machine_mode omode = GET_MODE (op);
  80
  81   if (omode != mode && omode != VOIDmode && mode != VOIDmode)
  82     return false;
  83
  84   switch (GET_CODE (op))
  85     {
  86     case SYMBOL_REF:
  87       return !SYMBOL_REF_TLS_MODEL (op);
  88
  89     case LABEL_REF:
  90       return true;
  91
  92     case CONST:
  93       op = XEXP (op, 0);
  94       return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
  95                 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
  96                || GET_CODE (XEXP (op, 0)) == LABEL_REF)
  97               && GET_CODE (XEXP (op, 1)) == CONST_INT);
  98
  99     default:
 100       gcc_unreachable ();
 101     }
 102 })
 103
 104 ;; Return true if OP is a symbolic operand for the TLS Global Dynamic model.
 105 (define_predicate "tgd_symbolic_operand"
 106   (and (match_code "symbol_ref")
 107        (match_test "tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC")))
 108
 109 ;; Return true if OP is a symbolic operand for the TLS Local Dynamic model.
 110 (define_predicate "tld_symbolic_operand"
 111   (and (match_code "symbol_ref")
 112        (match_test "tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC")))
 113
 114 ;; Return true if OP is a symbolic operand for the TLS Initial Exec model.
 115 (define_predicate "tie_symbolic_operand"
 116   (and (match_code "symbol_ref")
 117        (match_test "tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC")))
 118
 119 ;; Return true if OP is a symbolic operand for the TLS Local Exec model.
 120 (define_predicate "tle_symbolic_operand"
 121   (and (match_code "symbol_ref")
 122        (match_test "tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC")))
 123
 124 ;; Return true if the operand is an argument used in generating PIC references
 125 ;; in either the medium/low or embedded medium/anywhere code models on V9.
 126 ;; Check for (const (minus (symbol_ref:GOT)
 127 ;;                         (const (minus (label) (pc)))))
 128 (define_predicate "medium_pic_operand"
 129   (match_code "const")
 130 {
 131   /* Check for (const (minus (symbol_ref:GOT)
 132                              (const (minus (label) (pc))))).  */
 133   op = XEXP (op, 0);
 134   return GET_CODE (op) == MINUS
 135          && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 136          && GET_CODE (XEXP (op, 1)) == CONST
 137          && GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS;
 138 })
 139
 140 ;; Return true if OP is a LABEL_REF of mode MODE.
 141 (define_predicate "label_ref_operand"
 142   (and (match_code "label_ref")
 143        (match_test "GET_MODE (op) == mode")))
 144
 145 ;; Return true if OP is a data segment reference.  This includes the readonly
 146 ;; data segment or, in other words, anything but the text segment.
 147 ;; This is needed in the embedded medium/anywhere code model on V9.  These
 148 ;; values are accessed with EMBMEDANY_BASE_REG.  */
 149 (define_predicate "data_segment_operand"
 150   (match_code "symbol_ref,plus,const")
 151 {
 152   switch (GET_CODE (op))
 153     {
 154     case SYMBOL_REF :
 155       return ! SYMBOL_REF_FUNCTION_P (op);
 156     case PLUS :
 157       /* Assume canonical format of symbol + constant.
 158          Fall through.  */
 159     case CONST :
 160       return data_segment_operand (XEXP (op, 0), VOIDmode);
 161     default :
 162       gcc_unreachable ();
 163     }
 164 })
 165
 166 ;; Return true if OP is a text segment reference.
 167 ;; This is needed in the embedded medium/anywhere code model on V9.
 168 (define_predicate "text_segment_operand"
 169   (match_code "label_ref,symbol_ref,plus,const")
 170 {
 171   switch (GET_CODE (op))
 172     {
 173     case LABEL_REF :
 174       return true;
 175     case SYMBOL_REF :
 176       return SYMBOL_REF_FUNCTION_P (op);
 177     case PLUS :
 178       /* Assume canonical format of symbol + constant.
 179          Fall through.  */
 180     case CONST :
 181       return text_segment_operand (XEXP (op, 0), VOIDmode);
 182     default :
 183       gcc_unreachable ();
 184     }
 185 })
 186
 187
 188 ;; Predicates for registers.
 189
 190 ;; Return true if OP is either the zero constant or a register.
 191 (define_predicate "register_or_zero_operand"
 192   (ior (match_operand 0 "register_operand")
 193        (match_operand 0 "const_zero_operand")))
 194
 195 ;; Return true if OP is a register operand in a floating point register.
 196 (define_predicate "fp_register_operand"
 197   (match_operand 0 "register_operand")
 198 {
 199   if (GET_CODE (op) == SUBREG)
 200     op = SUBREG_REG (op); /* Possibly a MEM */
 201   return REG_P (op) && SPARC_FP_REG_P (REGNO (op));
 202 })
 203
 204 ;; Return true if OP is an integer register.
 205 (define_special_predicate "int_register_operand"
 206   (ior (match_test "register_operand (op, SImode)")
 207        (match_test "TARGET_ARCH64 && register_operand (op, DImode)")))
 208
 209 ;; Return true if OP is a floating point condition code register.
 210 (define_predicate "fcc_register_operand"
 211   (match_code "reg")
 212 {
 213   if (mode != VOIDmode && mode != GET_MODE (op))
 214     return false;
 215   if (mode == VOIDmode
 216       && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
 217     return false;
 218
 219 #if 0 /* ??? 1 when %fcc0-3 are pseudos first.  See gen_compare_reg().  */
 220   if (reg_renumber == 0)
 221     return REGNO (op) >= FIRST_PSEUDO_REGISTER;
 222   return REGNO_OK_FOR_CCFP_P (REGNO (op));
 223 #else
 224   return ((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4;
 225 #endif
 226 })
 227
 228 ;; Return true if OP is the floating point condition code register fcc0.
 229 (define_predicate "fcc0_register_operand"
 230   (match_code "reg")
 231 {
 232   if (mode != VOIDmode && mode != GET_MODE (op))
 233     return false;
 234   if (mode == VOIDmode
 235       && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
 236     return false;
 237
 238   return REGNO (op) == SPARC_FCC_REG;
 239 })
 240
 241 ;; Return true if OP is an integer or floating point condition code register.
 242 (define_predicate "icc_or_fcc_register_operand"
 243   (match_code "reg")
 244 {
 245   if (REGNO (op) == SPARC_ICC_REG)
 246     {
 247       if (mode != VOIDmode && mode != GET_MODE (op))
 248         return false;
 249       if (mode == VOIDmode
 250           && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
 251         return false;
 252
 253       return true;
 254     }
 255
 256   return fcc_register_operand (op, mode);
 257 })
 258
 259
 260 ;; Predicates for arithmetic instructions.
 261
 262 ;; Return true if OP is a register, or is a constant that is representable
 263 ;; by a 13-bit signed field.  This is an acceptable operand for most
 264 ;; 3-address instructions.
 265 (define_predicate "arith_operand"
 266   (ior (match_operand 0 "register_operand")
 267        (match_operand 0 "small_int_operand")))
 268
 269 ;; 64-bit: Same as above.
 270 ;; 32-bit: Return true if OP is a register, or is a constant that is
 271 ;; representable by a couple of 13-bit signed fields.  This is an
 272 ;; acceptable operand for most 3-address splitters.
 273 (define_predicate "arith_double_operand"
 274   (match_code "const_int,const_double,reg,subreg")
 275 {
 276   bool arith_simple_operand = arith_operand (op, mode);
 277   HOST_WIDE_INT m1, m2;
 278
 279   if (TARGET_ARCH64 || arith_simple_operand)
 280     return arith_simple_operand;
 281
 282 #if HOST_BITS_PER_WIDE_INT == 32
 283   if (GET_CODE (op) != CONST_DOUBLE)
 284     return false;
 285   m1 = CONST_DOUBLE_LOW (op);
 286   m2 = CONST_DOUBLE_HIGH (op);
 287 #else
 288   if (GET_CODE (op) != CONST_INT)
 289     return false;
 290   m1 = INTVAL (op) & 0xffffffff;
 291   m2 = INTVAL (op) >> 32;
 292 #endif
 293
 294   return SPARC_SIMM13_P (m1) && SPARC_SIMM13_P (m2);
 295 })
 296
 297 ;; Return true if OP is suitable as second operand for add/sub.
 298 (define_predicate "arith_add_operand"
 299   (ior (match_operand 0 "arith_operand")
 300        (match_operand 0 "const_4096_operand")))
 301
 302 ;; Return true if OP is suitable as second double operand for add/sub.
 303 (define_predicate "arith_double_add_operand"
 304   (match_code "const_int,const_double,reg,subreg")
 305 {
 306   bool _arith_double_operand = arith_double_operand (op, mode);
 307
 308   if (_arith_double_operand)
 309     return true;
 310
 311   return TARGET_ARCH64 && const_4096_operand (op, mode);
 312 })
 313
 314 ;; Return true if OP is a register, or is a CONST_INT that can fit in a
 315 ;; signed 10-bit immediate field.  This is an acceptable SImode operand for
 316 ;; the movrcc instructions.
 317 (define_predicate "arith10_operand"
 318   (ior (match_operand 0 "register_operand")
 319        (and (match_code "const_int")
 320             (match_test "SPARC_SIMM10_P (INTVAL (op))"))))
 321
 322 ;; Return true if OP is a register, or is a CONST_INT that can fit in a
 323 ;; signed 11-bit immediate field.  This is an acceptable SImode operand for
 324 ;; the movcc instructions.
 325 (define_predicate "arith11_operand"
 326   (ior (match_operand 0 "register_operand")
 327        (and (match_code "const_int")
 328             (match_test "SPARC_SIMM11_P (INTVAL (op))"))))
 329
 330 ;; Return true if OP is a register or a constant for the umul instruction.
 331 (define_predicate "uns_arith_operand"
 332   (ior (match_operand 0 "register_operand")
 333        (match_operand 0 "uns_small_int_operand")))
 334
 335
 336 ;; Predicates for miscellanous instructions.
 337
 338 ;; Return true if OP is valid for the lhs of a comparison insn.
 339 (define_predicate "compare_operand"
 340   (match_code "reg, subreg, zero_extract")
 341 {
 342   if (GET_CODE (op) == ZERO_EXTRACT)
 343     return (register_operand (XEXP (op, 0), mode)
 344             && small_int_operand (XEXP (op, 1), mode)
 345             && small_int_operand (XEXP (op, 2), mode)
 346             /* This matches cmp_zero_extract.  */
 347             && ((mode == SImode
 348                  && INTVAL (XEXP (op, 2)) > 19)
 349                 /* This matches cmp_zero_extract_sp64.  */
 350                 || (TARGET_ARCH64
 351                     && mode == DImode
 352                     && INTVAL (XEXP (op, 2)) > 51)));
 353   else
 354     return register_operand (op, mode);
 355 })
 356
 357 ;; Return true if OP is a valid operand for the source of a move insn.
 358 (define_predicate "input_operand"
 359   (match_code "const_int,const_double,const_vector,reg,subreg,mem")
 360 {
 361   enum mode_class mclass;
 362
 363   /* If both modes are non-void they must be the same.  */
 364   if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
 365     return false;
 366
 367   /* Allow any 1-instruction integer constant.  */
 368   if (GET_MODE_CLASS (mode) == MODE_INT
 369       && (small_int_operand (op, mode) || const_high_operand (op, mode)))
 370     return true;
 371
 372   /* If 32-bit mode and this is a DImode constant, allow it
 373      so that the splits can be generated.  */
 374   if (TARGET_ARCH32
 375       && mode == DImode
 376       && (GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT))
 377     return true;
 378
 379   if (register_operand (op, mode))
 380     return true;
 381
 382   mclass = GET_MODE_CLASS (mode);
 383   if ((mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
 384       || (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR))
 385     return true;
 386
 387   /* If this is a SUBREG, look inside so that we handle
 388      paradoxical ones.  */
 389   if (GET_CODE (op) == SUBREG)
 390     op = SUBREG_REG (op);
 391
 392   /* Check for valid MEM forms.  */
 393   if (GET_CODE (op) == MEM)
 394     return memory_address_p (mode, XEXP (op, 0));
 395
 396   return false;
 397 })
 398
 399 ;; Return true if OP is an address suitable for a call insn.
 400 ;; Call insn on SPARC can take a PC-relative constant address
 401 ;; or any regular memory address.
 402 (define_predicate "call_address_operand"
 403   (ior (match_operand 0 "symbolic_operand")
 404        (match_test "memory_address_p (Pmode, op)")))
 405
 406 ;; Return true if OP is an operand suitable for a call insn.
 407 (define_predicate "call_operand"
 408   (and (match_code "mem")
 409        (match_test "call_address_operand (XEXP (op, 0), mode)")))
 410
 411
 412 ;; Predicates for operators.
 413
 414 ;; Return true if OP is a comparison operator.  This allows the use of
 415 ;; MATCH_OPERATOR to recognize all the branch insns.
 416 (define_predicate "noov_compare_operator"
 417   (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu")
 418 {
 419   enum rtx_code code = GET_CODE (op);
 420   if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
 421       || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
 422     /* These are the only branches which work with CC_NOOVmode.  */
 423     return (code == EQ || code == NE || code == GE || code == LT);
 424   return true;
 425 })
 426
 427 ;; Return true if OP is a 64-bit comparison operator.  This allows the use of
 428 ;; MATCH_OPERATOR to recognize all the branch insns.
 429 (define_predicate "noov_compare64_operator"
 430   (and (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu")
 431        (match_test "TARGET_V9"))
 432 {
 433   enum rtx_code code = GET_CODE (op);
 434   if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
 435     /* These are the only branches which work with CCX_NOOVmode.  */
 436     return (code == EQ || code == NE || code == GE || code == LT);
 437   return (GET_MODE (XEXP (op, 0)) == CCXmode);
 438 })
 439
 440 ;; Return true if OP is a comparison operator suitable for use in V9
 441 ;; conditional move or branch on register contents instructions.
 442 (define_predicate "v9_register_compare_operator"
 443   (match_code "eq,ne,ge,lt,le,gt"))
 444
 445 ;; Return true if OP is an operator which can set the condition codes
 446 ;; explicitly.  We do not include PLUS and MINUS because these
 447 ;; require CC_NOOVmode, which we handle explicitly.
 448 (define_predicate "cc_arith_operator"
 449   (match_code "and,ior,xor"))
 450
 451 ;; Return true if OP is an operator which can bitwise complement its
 452 ;; second operand and set the condition codes explicitly.
 453 ;; XOR is not here because combine canonicalizes (xor (not ...) ...)
 454 ;; and (xor ... (not ...)) to (not (xor ...)).  */
 455 (define_predicate "cc_arith_not_operator"
 456   (match_code "and,ior"))