1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
53 #include "langhooks.h"
61 struct processor_costs
{
65 /* Integer signed load */
68 /* Integer zeroed load */
74 /* fmov, fneg, fabs */
78 const int float_plusminus
;
84 const int float_cmove
;
90 const int float_div_sf
;
93 const int float_div_df
;
96 const int float_sqrt_sf
;
99 const int float_sqrt_df
;
107 /* integer multiply cost for each bit set past the most
108 significant 3, so the formula for multiply cost becomes:
111 highest_bit = highest_clear_bit(rs1);
113 highest_bit = highest_set_bit(rs1);
116 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
118 A value of zero indicates that the multiply costs is fixed,
120 const int int_mul_bit_factor
;
131 /* penalty for shifts, due to scheduling rules etc. */
132 const int shift_penalty
;
136 struct processor_costs cypress_costs
= {
137 COSTS_N_INSNS (2), /* int load */
138 COSTS_N_INSNS (2), /* int signed load */
139 COSTS_N_INSNS (2), /* int zeroed load */
140 COSTS_N_INSNS (2), /* float load */
141 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
142 COSTS_N_INSNS (5), /* fadd, fsub */
143 COSTS_N_INSNS (1), /* fcmp */
144 COSTS_N_INSNS (1), /* fmov, fmovr */
145 COSTS_N_INSNS (7), /* fmul */
146 COSTS_N_INSNS (37), /* fdivs */
147 COSTS_N_INSNS (37), /* fdivd */
148 COSTS_N_INSNS (63), /* fsqrts */
149 COSTS_N_INSNS (63), /* fsqrtd */
150 COSTS_N_INSNS (1), /* imul */
151 COSTS_N_INSNS (1), /* imulX */
152 0, /* imul bit factor */
153 COSTS_N_INSNS (1), /* idiv */
154 COSTS_N_INSNS (1), /* idivX */
155 COSTS_N_INSNS (1), /* movcc/movr */
156 0, /* shift penalty */
160 struct processor_costs supersparc_costs
= {
161 COSTS_N_INSNS (1), /* int load */
162 COSTS_N_INSNS (1), /* int signed load */
163 COSTS_N_INSNS (1), /* int zeroed load */
164 COSTS_N_INSNS (0), /* float load */
165 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
166 COSTS_N_INSNS (3), /* fadd, fsub */
167 COSTS_N_INSNS (3), /* fcmp */
168 COSTS_N_INSNS (1), /* fmov, fmovr */
169 COSTS_N_INSNS (3), /* fmul */
170 COSTS_N_INSNS (6), /* fdivs */
171 COSTS_N_INSNS (9), /* fdivd */
172 COSTS_N_INSNS (12), /* fsqrts */
173 COSTS_N_INSNS (12), /* fsqrtd */
174 COSTS_N_INSNS (4), /* imul */
175 COSTS_N_INSNS (4), /* imulX */
176 0, /* imul bit factor */
177 COSTS_N_INSNS (4), /* idiv */
178 COSTS_N_INSNS (4), /* idivX */
179 COSTS_N_INSNS (1), /* movcc/movr */
180 1, /* shift penalty */
184 struct processor_costs hypersparc_costs
= {
185 COSTS_N_INSNS (1), /* int load */
186 COSTS_N_INSNS (1), /* int signed load */
187 COSTS_N_INSNS (1), /* int zeroed load */
188 COSTS_N_INSNS (1), /* float load */
189 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
190 COSTS_N_INSNS (1), /* fadd, fsub */
191 COSTS_N_INSNS (1), /* fcmp */
192 COSTS_N_INSNS (1), /* fmov, fmovr */
193 COSTS_N_INSNS (1), /* fmul */
194 COSTS_N_INSNS (8), /* fdivs */
195 COSTS_N_INSNS (12), /* fdivd */
196 COSTS_N_INSNS (17), /* fsqrts */
197 COSTS_N_INSNS (17), /* fsqrtd */
198 COSTS_N_INSNS (17), /* imul */
199 COSTS_N_INSNS (17), /* imulX */
200 0, /* imul bit factor */
201 COSTS_N_INSNS (17), /* idiv */
202 COSTS_N_INSNS (17), /* idivX */
203 COSTS_N_INSNS (1), /* movcc/movr */
204 0, /* shift penalty */
208 struct processor_costs leon_costs
= {
209 COSTS_N_INSNS (1), /* int load */
210 COSTS_N_INSNS (1), /* int signed load */
211 COSTS_N_INSNS (1), /* int zeroed load */
212 COSTS_N_INSNS (1), /* float load */
213 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
214 COSTS_N_INSNS (1), /* fadd, fsub */
215 COSTS_N_INSNS (1), /* fcmp */
216 COSTS_N_INSNS (1), /* fmov, fmovr */
217 COSTS_N_INSNS (1), /* fmul */
218 COSTS_N_INSNS (15), /* fdivs */
219 COSTS_N_INSNS (15), /* fdivd */
220 COSTS_N_INSNS (23), /* fsqrts */
221 COSTS_N_INSNS (23), /* fsqrtd */
222 COSTS_N_INSNS (5), /* imul */
223 COSTS_N_INSNS (5), /* imulX */
224 0, /* imul bit factor */
225 COSTS_N_INSNS (5), /* idiv */
226 COSTS_N_INSNS (5), /* idivX */
227 COSTS_N_INSNS (1), /* movcc/movr */
228 0, /* shift penalty */
232 struct processor_costs sparclet_costs
= {
233 COSTS_N_INSNS (3), /* int load */
234 COSTS_N_INSNS (3), /* int signed load */
235 COSTS_N_INSNS (1), /* int zeroed load */
236 COSTS_N_INSNS (1), /* float load */
237 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
238 COSTS_N_INSNS (1), /* fadd, fsub */
239 COSTS_N_INSNS (1), /* fcmp */
240 COSTS_N_INSNS (1), /* fmov, fmovr */
241 COSTS_N_INSNS (1), /* fmul */
242 COSTS_N_INSNS (1), /* fdivs */
243 COSTS_N_INSNS (1), /* fdivd */
244 COSTS_N_INSNS (1), /* fsqrts */
245 COSTS_N_INSNS (1), /* fsqrtd */
246 COSTS_N_INSNS (5), /* imul */
247 COSTS_N_INSNS (5), /* imulX */
248 0, /* imul bit factor */
249 COSTS_N_INSNS (5), /* idiv */
250 COSTS_N_INSNS (5), /* idivX */
251 COSTS_N_INSNS (1), /* movcc/movr */
252 0, /* shift penalty */
256 struct processor_costs ultrasparc_costs
= {
257 COSTS_N_INSNS (2), /* int load */
258 COSTS_N_INSNS (3), /* int signed load */
259 COSTS_N_INSNS (2), /* int zeroed load */
260 COSTS_N_INSNS (2), /* float load */
261 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
262 COSTS_N_INSNS (4), /* fadd, fsub */
263 COSTS_N_INSNS (1), /* fcmp */
264 COSTS_N_INSNS (2), /* fmov, fmovr */
265 COSTS_N_INSNS (4), /* fmul */
266 COSTS_N_INSNS (13), /* fdivs */
267 COSTS_N_INSNS (23), /* fdivd */
268 COSTS_N_INSNS (13), /* fsqrts */
269 COSTS_N_INSNS (23), /* fsqrtd */
270 COSTS_N_INSNS (4), /* imul */
271 COSTS_N_INSNS (4), /* imulX */
272 2, /* imul bit factor */
273 COSTS_N_INSNS (37), /* idiv */
274 COSTS_N_INSNS (68), /* idivX */
275 COSTS_N_INSNS (2), /* movcc/movr */
276 2, /* shift penalty */
280 struct processor_costs ultrasparc3_costs
= {
281 COSTS_N_INSNS (2), /* int load */
282 COSTS_N_INSNS (3), /* int signed load */
283 COSTS_N_INSNS (3), /* int zeroed load */
284 COSTS_N_INSNS (2), /* float load */
285 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
286 COSTS_N_INSNS (4), /* fadd, fsub */
287 COSTS_N_INSNS (5), /* fcmp */
288 COSTS_N_INSNS (3), /* fmov, fmovr */
289 COSTS_N_INSNS (4), /* fmul */
290 COSTS_N_INSNS (17), /* fdivs */
291 COSTS_N_INSNS (20), /* fdivd */
292 COSTS_N_INSNS (20), /* fsqrts */
293 COSTS_N_INSNS (29), /* fsqrtd */
294 COSTS_N_INSNS (6), /* imul */
295 COSTS_N_INSNS (6), /* imulX */
296 0, /* imul bit factor */
297 COSTS_N_INSNS (40), /* idiv */
298 COSTS_N_INSNS (71), /* idivX */
299 COSTS_N_INSNS (2), /* movcc/movr */
300 0, /* shift penalty */
304 struct processor_costs niagara_costs
= {
305 COSTS_N_INSNS (3), /* int load */
306 COSTS_N_INSNS (3), /* int signed load */
307 COSTS_N_INSNS (3), /* int zeroed load */
308 COSTS_N_INSNS (9), /* float load */
309 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
310 COSTS_N_INSNS (8), /* fadd, fsub */
311 COSTS_N_INSNS (26), /* fcmp */
312 COSTS_N_INSNS (8), /* fmov, fmovr */
313 COSTS_N_INSNS (29), /* fmul */
314 COSTS_N_INSNS (54), /* fdivs */
315 COSTS_N_INSNS (83), /* fdivd */
316 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
317 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
318 COSTS_N_INSNS (11), /* imul */
319 COSTS_N_INSNS (11), /* imulX */
320 0, /* imul bit factor */
321 COSTS_N_INSNS (72), /* idiv */
322 COSTS_N_INSNS (72), /* idivX */
323 COSTS_N_INSNS (1), /* movcc/movr */
324 0, /* shift penalty */
328 struct processor_costs niagara2_costs
= {
329 COSTS_N_INSNS (3), /* int load */
330 COSTS_N_INSNS (3), /* int signed load */
331 COSTS_N_INSNS (3), /* int zeroed load */
332 COSTS_N_INSNS (3), /* float load */
333 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
334 COSTS_N_INSNS (6), /* fadd, fsub */
335 COSTS_N_INSNS (6), /* fcmp */
336 COSTS_N_INSNS (6), /* fmov, fmovr */
337 COSTS_N_INSNS (6), /* fmul */
338 COSTS_N_INSNS (19), /* fdivs */
339 COSTS_N_INSNS (33), /* fdivd */
340 COSTS_N_INSNS (19), /* fsqrts */
341 COSTS_N_INSNS (33), /* fsqrtd */
342 COSTS_N_INSNS (5), /* imul */
343 COSTS_N_INSNS (5), /* imulX */
344 0, /* imul bit factor */
345 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
346 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
347 COSTS_N_INSNS (1), /* movcc/movr */
348 0, /* shift penalty */
352 struct processor_costs niagara3_costs
= {
353 COSTS_N_INSNS (3), /* int load */
354 COSTS_N_INSNS (3), /* int signed load */
355 COSTS_N_INSNS (3), /* int zeroed load */
356 COSTS_N_INSNS (3), /* float load */
357 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
358 COSTS_N_INSNS (9), /* fadd, fsub */
359 COSTS_N_INSNS (9), /* fcmp */
360 COSTS_N_INSNS (9), /* fmov, fmovr */
361 COSTS_N_INSNS (9), /* fmul */
362 COSTS_N_INSNS (23), /* fdivs */
363 COSTS_N_INSNS (37), /* fdivd */
364 COSTS_N_INSNS (23), /* fsqrts */
365 COSTS_N_INSNS (37), /* fsqrtd */
366 COSTS_N_INSNS (9), /* imul */
367 COSTS_N_INSNS (9), /* imulX */
368 0, /* imul bit factor */
369 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
370 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
371 COSTS_N_INSNS (1), /* movcc/movr */
372 0, /* shift penalty */
376 struct processor_costs niagara4_costs
= {
377 COSTS_N_INSNS (5), /* int load */
378 COSTS_N_INSNS (5), /* int signed load */
379 COSTS_N_INSNS (5), /* int zeroed load */
380 COSTS_N_INSNS (5), /* float load */
381 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
382 COSTS_N_INSNS (11), /* fadd, fsub */
383 COSTS_N_INSNS (11), /* fcmp */
384 COSTS_N_INSNS (11), /* fmov, fmovr */
385 COSTS_N_INSNS (11), /* fmul */
386 COSTS_N_INSNS (24), /* fdivs */
387 COSTS_N_INSNS (37), /* fdivd */
388 COSTS_N_INSNS (24), /* fsqrts */
389 COSTS_N_INSNS (37), /* fsqrtd */
390 COSTS_N_INSNS (12), /* imul */
391 COSTS_N_INSNS (12), /* imulX */
392 0, /* imul bit factor */
393 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
394 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
395 COSTS_N_INSNS (1), /* movcc/movr */
396 0, /* shift penalty */
399 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
401 #ifdef HAVE_AS_RELAX_OPTION
402 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
403 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
404 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
405 somebody does not branch between the sethi and jmp. */
406 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
408 #define LEAF_SIBCALL_SLOT_RESERVED_P \
409 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
412 /* Vector to say how input registers are mapped to output registers.
413 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
414 eliminate it. You must use -fomit-frame-pointer to get that. */
415 char leaf_reg_remap
[] =
416 { 0, 1, 2, 3, 4, 5, 6, 7,
417 -1, -1, -1, -1, -1, -1, 14, -1,
418 -1, -1, -1, -1, -1, -1, -1, -1,
419 8, 9, 10, 11, 12, 13, -1, 15,
421 32, 33, 34, 35, 36, 37, 38, 39,
422 40, 41, 42, 43, 44, 45, 46, 47,
423 48, 49, 50, 51, 52, 53, 54, 55,
424 56, 57, 58, 59, 60, 61, 62, 63,
425 64, 65, 66, 67, 68, 69, 70, 71,
426 72, 73, 74, 75, 76, 77, 78, 79,
427 80, 81, 82, 83, 84, 85, 86, 87,
428 88, 89, 90, 91, 92, 93, 94, 95,
429 96, 97, 98, 99, 100, 101, 102};
431 /* Vector, indexed by hard register number, which contains 1
432 for a register that is allowable in a candidate for leaf
433 function treatment. */
434 char sparc_leaf_regs
[] =
435 { 1, 1, 1, 1, 1, 1, 1, 1,
436 0, 0, 0, 0, 0, 0, 1, 0,
437 0, 0, 0, 0, 0, 0, 0, 0,
438 1, 1, 1, 1, 1, 1, 0, 1,
439 1, 1, 1, 1, 1, 1, 1, 1,
440 1, 1, 1, 1, 1, 1, 1, 1,
441 1, 1, 1, 1, 1, 1, 1, 1,
442 1, 1, 1, 1, 1, 1, 1, 1,
443 1, 1, 1, 1, 1, 1, 1, 1,
444 1, 1, 1, 1, 1, 1, 1, 1,
445 1, 1, 1, 1, 1, 1, 1, 1,
446 1, 1, 1, 1, 1, 1, 1, 1,
447 1, 1, 1, 1, 1, 1, 1};
449 struct GTY(()) machine_function
451 /* Size of the frame of the function. */
452 HOST_WIDE_INT frame_size
;
454 /* Size of the frame of the function minus the register window save area
455 and the outgoing argument area. */
456 HOST_WIDE_INT apparent_frame_size
;
458 /* Register we pretend the frame pointer is allocated to. Normally, this
459 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
460 record "offset" separately as it may be too big for (reg + disp). */
462 HOST_WIDE_INT frame_base_offset
;
464 /* Some local-dynamic TLS symbol name. */
465 const char *some_ld_name
;
467 /* Number of global or FP registers to be saved (as 4-byte quantities). */
468 int n_global_fp_regs
;
470 /* True if the current function is leaf and uses only leaf regs,
471 so that the SPARC leaf function optimization can be applied.
472 Private version of crtl->uses_only_leaf_regs, see
473 sparc_expand_prologue for the rationale. */
476 /* True if the prologue saves local or in registers. */
477 bool save_local_in_regs_p
;
479 /* True if the data calculated by sparc_expand_prologue are valid. */
480 bool prologue_data_valid_p
;
483 #define sparc_frame_size cfun->machine->frame_size
484 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
485 #define sparc_frame_base_reg cfun->machine->frame_base_reg
486 #define sparc_frame_base_offset cfun->machine->frame_base_offset
487 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
488 #define sparc_leaf_function_p cfun->machine->leaf_function_p
489 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
490 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
492 /* 1 if the next opcode is to be specially indented. */
493 int sparc_indent_opcode
= 0;
495 static void sparc_option_override (void);
496 static void sparc_init_modes (void);
497 static void scan_record_type (const_tree
, int *, int *, int *);
498 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
499 const_tree
, bool, bool, int *, int *);
501 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
502 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
504 static void sparc_emit_set_const32 (rtx
, rtx
);
505 static void sparc_emit_set_const64 (rtx
, rtx
);
506 static void sparc_output_addr_vec (rtx
);
507 static void sparc_output_addr_diff_vec (rtx
);
508 static void sparc_output_deferred_case_vectors (void);
509 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
510 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
511 static rtx
sparc_builtin_saveregs (void);
512 static int epilogue_renumber (rtx
*, int);
513 static bool sparc_assemble_integer (rtx
, unsigned int, int);
514 static int set_extends (rtx
);
515 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
516 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
517 #ifdef TARGET_SOLARIS
518 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
519 tree
) ATTRIBUTE_UNUSED
;
521 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
522 static int sparc_issue_rate (void);
523 static void sparc_sched_init (FILE *, int, int);
524 static int sparc_use_sched_lookahead (void);
526 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
527 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
528 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
529 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
530 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
532 static bool sparc_function_ok_for_sibcall (tree
, tree
);
533 static void sparc_init_libfuncs (void);
534 static void sparc_init_builtins (void);
535 static void sparc_vis_init_builtins (void);
536 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
537 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
538 static int sparc_vis_mul8x16 (int, int);
539 static void sparc_handle_vis_mul8x16 (tree
*, int, tree
, tree
, tree
);
540 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
541 HOST_WIDE_INT
, tree
);
542 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
543 HOST_WIDE_INT
, const_tree
);
544 static void sparc_reorg (void);
545 static struct machine_function
* sparc_init_machine_status (void);
546 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
547 static rtx
sparc_tls_get_addr (void);
548 static rtx
sparc_tls_got (void);
549 static const char *get_some_local_dynamic_name (void);
550 static int get_some_local_dynamic_name_1 (rtx
*, void *);
551 static int sparc_register_move_cost (enum machine_mode
,
552 reg_class_t
, reg_class_t
);
553 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
554 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
555 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
556 static bool sparc_function_value_regno_p (const unsigned int);
557 static rtx
sparc_struct_value_rtx (tree
, int);
558 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
559 int *, const_tree
, int);
560 static bool sparc_return_in_memory (const_tree
, const_tree
);
561 static bool sparc_strict_argument_naming (cumulative_args_t
);
562 static void sparc_va_start (tree
, rtx
);
563 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
564 static bool sparc_vector_mode_supported_p (enum machine_mode
);
565 static bool sparc_tls_referenced_p (rtx
);
566 static rtx
sparc_legitimize_tls_address (rtx
);
567 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
568 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
569 static rtx
sparc_delegitimize_address (rtx
);
570 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
571 static bool sparc_pass_by_reference (cumulative_args_t
,
572 enum machine_mode
, const_tree
, bool);
573 static void sparc_function_arg_advance (cumulative_args_t
,
574 enum machine_mode
, const_tree
, bool);
575 static rtx
sparc_function_arg_1 (cumulative_args_t
,
576 enum machine_mode
, const_tree
, bool, bool);
577 static rtx
sparc_function_arg (cumulative_args_t
,
578 enum machine_mode
, const_tree
, bool);
579 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
580 enum machine_mode
, const_tree
, bool);
581 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
583 static int sparc_arg_partial_bytes (cumulative_args_t
,
584 enum machine_mode
, tree
, bool);
585 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
586 static void sparc_file_end (void);
587 static bool sparc_frame_pointer_required (void);
588 static bool sparc_can_eliminate (const int, const int);
589 static rtx
sparc_builtin_setjmp_frame_value (void);
590 static void sparc_conditional_register_usage (void);
591 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
592 static const char *sparc_mangle_type (const_tree
);
594 static void sparc_trampoline_init (rtx
, tree
, rtx
);
595 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
596 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
597 static bool sparc_print_operand_punct_valid_p (unsigned char);
598 static void sparc_print_operand (FILE *, rtx
, int);
599 static void sparc_print_operand_address (FILE *, rtx
);
600 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
602 secondary_reload_info
*);
604 #ifdef SUBTARGET_ATTRIBUTE_TABLE
605 /* Table of valid machine attributes. */
606 static const struct attribute_spec sparc_attribute_table
[] =
608 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
610 SUBTARGET_ATTRIBUTE_TABLE
,
611 { NULL
, 0, 0, false, false, false, NULL
, false }
615 /* Option handling. */
618 enum cmodel sparc_cmodel
;
620 char sparc_hard_reg_printed
[8];
622 /* Initialize the GCC target structure. */
624 /* The default is to use .half rather than .short for aligned HI objects. */
625 #undef TARGET_ASM_ALIGNED_HI_OP
626 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
628 #undef TARGET_ASM_UNALIGNED_HI_OP
629 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
630 #undef TARGET_ASM_UNALIGNED_SI_OP
631 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
632 #undef TARGET_ASM_UNALIGNED_DI_OP
633 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
635 /* The target hook has to handle DI-mode values. */
636 #undef TARGET_ASM_INTEGER
637 #define TARGET_ASM_INTEGER sparc_assemble_integer
639 #undef TARGET_ASM_FUNCTION_PROLOGUE
640 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
641 #undef TARGET_ASM_FUNCTION_EPILOGUE
642 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
644 #undef TARGET_SCHED_ADJUST_COST
645 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
646 #undef TARGET_SCHED_ISSUE_RATE
647 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
648 #undef TARGET_SCHED_INIT
649 #define TARGET_SCHED_INIT sparc_sched_init
650 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
651 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
653 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
654 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
656 #undef TARGET_INIT_LIBFUNCS
657 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
658 #undef TARGET_INIT_BUILTINS
659 #define TARGET_INIT_BUILTINS sparc_init_builtins
661 #undef TARGET_LEGITIMIZE_ADDRESS
662 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
663 #undef TARGET_DELEGITIMIZE_ADDRESS
664 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
665 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
666 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
668 #undef TARGET_EXPAND_BUILTIN
669 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
670 #undef TARGET_FOLD_BUILTIN
671 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
674 #undef TARGET_HAVE_TLS
675 #define TARGET_HAVE_TLS true
678 #undef TARGET_CANNOT_FORCE_CONST_MEM
679 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
681 #undef TARGET_ASM_OUTPUT_MI_THUNK
682 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
683 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
684 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
686 #undef TARGET_MACHINE_DEPENDENT_REORG
687 #define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
689 #undef TARGET_RTX_COSTS
690 #define TARGET_RTX_COSTS sparc_rtx_costs
691 #undef TARGET_ADDRESS_COST
692 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
693 #undef TARGET_REGISTER_MOVE_COST
694 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
696 #undef TARGET_PROMOTE_FUNCTION_MODE
697 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
699 #undef TARGET_FUNCTION_VALUE
700 #define TARGET_FUNCTION_VALUE sparc_function_value
701 #undef TARGET_LIBCALL_VALUE
702 #define TARGET_LIBCALL_VALUE sparc_libcall_value
703 #undef TARGET_FUNCTION_VALUE_REGNO_P
704 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
706 #undef TARGET_STRUCT_VALUE_RTX
707 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
708 #undef TARGET_RETURN_IN_MEMORY
709 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
710 #undef TARGET_MUST_PASS_IN_STACK
711 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
712 #undef TARGET_PASS_BY_REFERENCE
713 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
714 #undef TARGET_ARG_PARTIAL_BYTES
715 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
716 #undef TARGET_FUNCTION_ARG_ADVANCE
717 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
718 #undef TARGET_FUNCTION_ARG
719 #define TARGET_FUNCTION_ARG sparc_function_arg
720 #undef TARGET_FUNCTION_INCOMING_ARG
721 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
722 #undef TARGET_FUNCTION_ARG_BOUNDARY
723 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
725 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
726 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
727 #undef TARGET_STRICT_ARGUMENT_NAMING
728 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
730 #undef TARGET_EXPAND_BUILTIN_VA_START
731 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
732 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
733 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
735 #undef TARGET_VECTOR_MODE_SUPPORTED_P
736 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
738 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
739 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
741 #ifdef SUBTARGET_INSERT_ATTRIBUTES
742 #undef TARGET_INSERT_ATTRIBUTES
743 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
746 #ifdef SUBTARGET_ATTRIBUTE_TABLE
747 #undef TARGET_ATTRIBUTE_TABLE
748 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
751 #undef TARGET_RELAXED_ORDERING
752 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
754 #undef TARGET_OPTION_OVERRIDE
755 #define TARGET_OPTION_OVERRIDE sparc_option_override
757 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
758 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
759 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
762 #undef TARGET_ASM_FILE_END
763 #define TARGET_ASM_FILE_END sparc_file_end
765 #undef TARGET_FRAME_POINTER_REQUIRED
766 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
768 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
769 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
771 #undef TARGET_CAN_ELIMINATE
772 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
774 #undef TARGET_PREFERRED_RELOAD_CLASS
775 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
777 #undef TARGET_SECONDARY_RELOAD
778 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
780 #undef TARGET_CONDITIONAL_REGISTER_USAGE
781 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
783 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
784 #undef TARGET_MANGLE_TYPE
785 #define TARGET_MANGLE_TYPE sparc_mangle_type
788 #undef TARGET_LEGITIMATE_ADDRESS_P
789 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
791 #undef TARGET_LEGITIMATE_CONSTANT_P
792 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
794 #undef TARGET_TRAMPOLINE_INIT
795 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
797 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
798 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
799 #undef TARGET_PRINT_OPERAND
800 #define TARGET_PRINT_OPERAND sparc_print_operand
801 #undef TARGET_PRINT_OPERAND_ADDRESS
802 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
804 /* The value stored by LDSTUB. */
805 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
806 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
808 struct gcc_target targetm
= TARGET_INITIALIZER
;
811 dump_target_flag_bits (const int flags
)
813 if (flags
& MASK_64BIT
)
814 fprintf (stderr
, "64BIT ");
815 if (flags
& MASK_APP_REGS
)
816 fprintf (stderr
, "APP_REGS ");
817 if (flags
& MASK_FASTER_STRUCTS
)
818 fprintf (stderr
, "FASTER_STRUCTS ");
819 if (flags
& MASK_FLAT
)
820 fprintf (stderr
, "FLAT ");
821 if (flags
& MASK_FMAF
)
822 fprintf (stderr
, "FMAF ");
823 if (flags
& MASK_FPU
)
824 fprintf (stderr
, "FPU ");
825 if (flags
& MASK_HARD_QUAD
)
826 fprintf (stderr
, "HARD_QUAD ");
827 if (flags
& MASK_POPC
)
828 fprintf (stderr
, "POPC ");
829 if (flags
& MASK_PTR64
)
830 fprintf (stderr
, "PTR64 ");
831 if (flags
& MASK_STACK_BIAS
)
832 fprintf (stderr
, "STACK_BIAS ");
833 if (flags
& MASK_UNALIGNED_DOUBLES
)
834 fprintf (stderr
, "UNALIGNED_DOUBLES ");
835 if (flags
& MASK_V8PLUS
)
836 fprintf (stderr
, "V8PLUS ");
837 if (flags
& MASK_VIS
)
838 fprintf (stderr
, "VIS ");
839 if (flags
& MASK_VIS2
)
840 fprintf (stderr
, "VIS2 ");
841 if (flags
& MASK_VIS3
)
842 fprintf (stderr
, "VIS3 ");
843 if (flags
& MASK_CBCOND
)
844 fprintf (stderr
, "CBCOND ");
845 if (flags
& MASK_DEPRECATED_V8_INSNS
)
846 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
847 if (flags
& MASK_SPARCLET
)
848 fprintf (stderr
, "SPARCLET ");
849 if (flags
& MASK_SPARCLITE
)
850 fprintf (stderr
, "SPARCLITE ");
852 fprintf (stderr
, "V8 ");
854 fprintf (stderr
, "V9 ");
858 dump_target_flags (const char *prefix
, const int flags
)
860 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
861 dump_target_flag_bits (flags
);
862 fprintf(stderr
, "]\n");
865 /* Validate and override various options, and do some machine dependent
869 sparc_option_override (void)
871 static struct code_model
{
872 const char *const name
;
873 const enum cmodel value
;
874 } const cmodels
[] = {
876 { "medlow", CM_MEDLOW
},
877 { "medmid", CM_MEDMID
},
878 { "medany", CM_MEDANY
},
879 { "embmedany", CM_EMBMEDANY
},
880 { NULL
, (enum cmodel
) 0 }
882 const struct code_model
*cmodel
;
883 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
884 static struct cpu_default
{
886 const enum processor_type processor
;
887 } const cpu_default
[] = {
888 /* There must be one entry here for each TARGET_CPU value. */
889 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
890 { TARGET_CPU_v8
, PROCESSOR_V8
},
891 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
892 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
893 { TARGET_CPU_leon
, PROCESSOR_LEON
},
894 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
895 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
896 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
897 { TARGET_CPU_v9
, PROCESSOR_V9
},
898 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
899 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
900 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
901 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
902 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
903 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
906 const struct cpu_default
*def
;
907 /* Table of values for -m{cpu,tune}=. This must match the order of
908 the PROCESSOR_* enumeration. */
909 static struct cpu_table
{
910 const char *const name
;
913 } const cpu_table
[] = {
914 { "v7", MASK_ISA
, 0 },
915 { "cypress", MASK_ISA
, 0 },
916 { "v8", MASK_ISA
, MASK_V8
},
917 /* TI TMS390Z55 supersparc */
918 { "supersparc", MASK_ISA
, MASK_V8
},
919 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
921 { "leon", MASK_ISA
, MASK_V8
|MASK_FPU
},
922 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
923 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
924 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
925 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
926 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
927 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
928 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
930 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
931 { "v9", MASK_ISA
, MASK_V9
},
932 /* UltraSPARC I, II, IIi */
933 { "ultrasparc", MASK_ISA
,
934 /* Although insns using %y are deprecated, it is a clear win. */
935 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
937 /* ??? Check if %y issue still holds true. */
938 { "ultrasparc3", MASK_ISA
,
939 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
941 { "niagara", MASK_ISA
,
942 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
944 { "niagara2", MASK_ISA
,
945 MASK_V9
|MASK_POPC
|MASK_VIS2
},
947 { "niagara3", MASK_ISA
,
948 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
950 { "niagara4", MASK_ISA
,
951 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
953 const struct cpu_table
*cpu
;
957 if (sparc_debug_string
!= NULL
)
962 p
= ASTRDUP (sparc_debug_string
);
963 while ((q
= strtok (p
, ",")) != NULL
)
977 if (! strcmp (q
, "all"))
978 mask
= MASK_DEBUG_ALL
;
979 else if (! strcmp (q
, "options"))
980 mask
= MASK_DEBUG_OPTIONS
;
982 error ("unknown -mdebug-%s switch", q
);
985 sparc_debug
&= ~mask
;
991 if (TARGET_DEBUG_OPTIONS
)
993 dump_target_flags("Initial target_flags", target_flags
);
994 dump_target_flags("target_flags_explicit", target_flags_explicit
);
997 #ifdef SUBTARGET_OVERRIDE_OPTIONS
998 SUBTARGET_OVERRIDE_OPTIONS
;
1001 #ifndef SPARC_BI_ARCH
1002 /* Check for unsupported architecture size. */
1003 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1004 error ("%s is not supported by this configuration",
1005 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1008 /* We force all 64bit archs to use 128 bit long double */
1009 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
1011 error ("-mlong-double-64 not allowed with -m64");
1012 target_flags
|= MASK_LONG_DOUBLE_128
;
1015 /* Code model selection. */
1016 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1018 #ifdef SPARC_BI_ARCH
1020 sparc_cmodel
= CM_32
;
1023 if (sparc_cmodel_string
!= NULL
)
1027 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1028 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1030 if (cmodel
->name
== NULL
)
1031 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1033 sparc_cmodel
= cmodel
->value
;
1036 error ("-mcmodel= is not supported on 32 bit systems");
1039 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1040 for (i
= 8; i
< 16; i
++)
1041 if (!call_used_regs
[i
])
1043 error ("-fcall-saved-REG is not supported for out registers");
1044 call_used_regs
[i
] = 1;
1047 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
1049 /* Set the default CPU. */
1050 if (!global_options_set
.x_sparc_cpu_and_features
)
1052 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1053 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1055 gcc_assert (def
->cpu
!= -1);
1056 sparc_cpu_and_features
= def
->processor
;
1059 if (!global_options_set
.x_sparc_cpu
)
1060 sparc_cpu
= sparc_cpu_and_features
;
1062 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1064 if (TARGET_DEBUG_OPTIONS
)
1066 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1067 fprintf (stderr
, "sparc_cpu: %s\n",
1068 cpu_table
[(int) sparc_cpu
].name
);
1069 dump_target_flags ("cpu->disable", cpu
->disable
);
1070 dump_target_flags ("cpu->enable", cpu
->enable
);
1073 target_flags
&= ~cpu
->disable
;
1074 target_flags
|= (cpu
->enable
1075 #ifndef HAVE_AS_FMAF_HPC_VIS3
1076 & ~(MASK_FMAF
| MASK_VIS3
)
1078 #ifndef HAVE_AS_SPARC4
1083 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1084 the processor default. */
1085 if (target_flags_explicit
& MASK_FPU
)
1086 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
1088 /* -mvis2 implies -mvis */
1090 target_flags
|= MASK_VIS
;
1092 /* -mvis3 implies -mvis2 and -mvis */
1094 target_flags
|= MASK_VIS2
| MASK_VIS
;
1096 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is
1099 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_FMAF
);
1101 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1103 -m64 also implies v9. */
1104 if (TARGET_VIS
|| TARGET_ARCH64
)
1106 target_flags
|= MASK_V9
;
1107 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1110 /* -mvis also implies -mv8plus on 32-bit */
1111 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1112 target_flags
|= MASK_V8PLUS
;
1114 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1115 if (TARGET_V9
&& TARGET_ARCH32
)
1116 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1118 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1119 if (! TARGET_V9
|| TARGET_ARCH64
)
1120 target_flags
&= ~MASK_V8PLUS
;
1122 /* Don't use stack biasing in 32 bit mode. */
1124 target_flags
&= ~MASK_STACK_BIAS
;
1126 /* Supply a default value for align_functions. */
1127 if (align_functions
== 0
1128 && (sparc_cpu
== PROCESSOR_ULTRASPARC
1129 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1130 || sparc_cpu
== PROCESSOR_NIAGARA
1131 || sparc_cpu
== PROCESSOR_NIAGARA2
1132 || sparc_cpu
== PROCESSOR_NIAGARA3
1133 || sparc_cpu
== PROCESSOR_NIAGARA4
))
1134 align_functions
= 32;
1136 /* Validate PCC_STRUCT_RETURN. */
1137 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1138 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1140 /* Only use .uaxword when compiling for a 64-bit target. */
1142 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1144 /* Do various machine dependent initializations. */
1145 sparc_init_modes ();
1147 /* Set up function hooks. */
1148 init_machine_status
= sparc_init_machine_status
;
1153 case PROCESSOR_CYPRESS
:
1154 sparc_costs
= &cypress_costs
;
1157 case PROCESSOR_SPARCLITE
:
1158 case PROCESSOR_SUPERSPARC
:
1159 sparc_costs
= &supersparc_costs
;
1161 case PROCESSOR_F930
:
1162 case PROCESSOR_F934
:
1163 case PROCESSOR_HYPERSPARC
:
1164 case PROCESSOR_SPARCLITE86X
:
1165 sparc_costs
= &hypersparc_costs
;
1167 case PROCESSOR_LEON
:
1168 sparc_costs
= &leon_costs
;
1170 case PROCESSOR_SPARCLET
:
1171 case PROCESSOR_TSC701
:
1172 sparc_costs
= &sparclet_costs
;
1175 case PROCESSOR_ULTRASPARC
:
1176 sparc_costs
= &ultrasparc_costs
;
1178 case PROCESSOR_ULTRASPARC3
:
1179 sparc_costs
= &ultrasparc3_costs
;
1181 case PROCESSOR_NIAGARA
:
1182 sparc_costs
= &niagara_costs
;
1184 case PROCESSOR_NIAGARA2
:
1185 sparc_costs
= &niagara2_costs
;
1187 case PROCESSOR_NIAGARA3
:
1188 sparc_costs
= &niagara3_costs
;
1190 case PROCESSOR_NIAGARA4
:
1191 sparc_costs
= &niagara4_costs
;
1193 case PROCESSOR_NATIVE
:
1197 if (sparc_memory_model
== SMM_DEFAULT
)
1199 /* Choose the memory model for the operating system. */
1200 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1201 if (os_default
!= SMM_DEFAULT
)
1202 sparc_memory_model
= os_default
;
1203 /* Choose the most relaxed model for the processor. */
1205 sparc_memory_model
= SMM_RMO
;
1207 sparc_memory_model
= SMM_PSO
;
1209 sparc_memory_model
= SMM_SC
;
1212 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1213 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1214 target_flags
|= MASK_LONG_DOUBLE_128
;
1217 if (TARGET_DEBUG_OPTIONS
)
1218 dump_target_flags ("Final target_flags", target_flags
);
1220 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1221 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1222 || sparc_cpu
== PROCESSOR_NIAGARA
1223 || sparc_cpu
== PROCESSOR_NIAGARA2
1224 || sparc_cpu
== PROCESSOR_NIAGARA3
1225 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1227 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1229 global_options
.x_param_values
,
1230 global_options_set
.x_param_values
);
1231 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1232 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1233 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1234 || sparc_cpu
== PROCESSOR_NIAGARA
1235 || sparc_cpu
== PROCESSOR_NIAGARA2
1236 || sparc_cpu
== PROCESSOR_NIAGARA3
1237 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1239 global_options
.x_param_values
,
1240 global_options_set
.x_param_values
);
1242 /* Disable save slot sharing for call-clobbered registers by default.
1243 The IRA sharing algorithm works on single registers only and this
1244 pessimizes for double floating-point registers. */
1245 if (!global_options_set
.x_flag_ira_share_save_slots
)
1246 flag_ira_share_save_slots
= 0;
1249 /* Miscellaneous utilities. */
1251 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1252 or branch on register contents instructions. */
1255 v9_regcmp_p (enum rtx_code code
)
1257 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1258 || code
== LE
|| code
== GT
);
1261 /* Nonzero if OP is a floating point constant which can
1262 be loaded into an integer register using a single
1263 sethi instruction. */
1268 if (GET_CODE (op
) == CONST_DOUBLE
)
1273 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1274 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1275 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1281 /* Nonzero if OP is a floating point constant which can
1282 be loaded into an integer register using a single
1288 if (GET_CODE (op
) == CONST_DOUBLE
)
1293 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1294 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1295 return SPARC_SIMM13_P (i
);
1301 /* Nonzero if OP is a floating point constant which can
1302 be loaded into an integer register using a high/losum
1303 instruction sequence. */
1306 fp_high_losum_p (rtx op
)
1308 /* The constraints calling this should only be in
1309 SFmode move insns, so any constant which cannot
1310 be moved using a single insn will do. */
1311 if (GET_CODE (op
) == CONST_DOUBLE
)
1316 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1317 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1318 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1324 /* Return true if the address of LABEL can be loaded by means of the
1325 mov{si,di}_pic_label_ref patterns in PIC mode. */
1328 can_use_mov_pic_label_ref (rtx label
)
1330 /* VxWorks does not impose a fixed gap between segments; the run-time
1331 gap can be different from the object-file gap. We therefore can't
1332 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1333 are absolutely sure that X is in the same segment as the GOT.
1334 Unfortunately, the flexibility of linker scripts means that we
1335 can't be sure of that in general, so assume that GOT-relative
1336 accesses are never valid on VxWorks. */
1337 if (TARGET_VXWORKS_RTP
)
1340 /* Similarly, if the label is non-local, it might end up being placed
1341 in a different section than the current one; now mov_pic_label_ref
1342 requires the label and the code to be in the same section. */
1343 if (LABEL_REF_NONLOCAL_P (label
))
1346 /* Finally, if we are reordering basic blocks and partition into hot
1347 and cold sections, this might happen for any label. */
1348 if (flag_reorder_blocks_and_partition
)
1354 /* Expand a move instruction. Return true if all work is done. */
1357 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1359 /* Handle sets of MEM first. */
1360 if (GET_CODE (operands
[0]) == MEM
)
1362 /* 0 is a register (or a pair of registers) on SPARC. */
1363 if (register_or_zero_operand (operands
[1], mode
))
1366 if (!reload_in_progress
)
1368 operands
[0] = validize_mem (operands
[0]);
1369 operands
[1] = force_reg (mode
, operands
[1]);
1373 /* Fixup TLS cases. */
1375 && CONSTANT_P (operands
[1])
1376 && sparc_tls_referenced_p (operands
[1]))
1378 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1382 /* Fixup PIC cases. */
1383 if (flag_pic
&& CONSTANT_P (operands
[1]))
1385 if (pic_address_needs_scratch (operands
[1]))
1386 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1388 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1389 if (GET_CODE (operands
[1]) == LABEL_REF
1390 && can_use_mov_pic_label_ref (operands
[1]))
1394 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1400 gcc_assert (TARGET_ARCH64
);
1401 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1406 if (symbolic_operand (operands
[1], mode
))
1409 = sparc_legitimize_pic_address (operands
[1],
1411 ? operands
[0] : NULL_RTX
);
1416 /* If we are trying to toss an integer constant into FP registers,
1417 or loading a FP or vector constant, force it into memory. */
1418 if (CONSTANT_P (operands
[1])
1419 && REG_P (operands
[0])
1420 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1421 || SCALAR_FLOAT_MODE_P (mode
)
1422 || VECTOR_MODE_P (mode
)))
1424 /* emit_group_store will send such bogosity to us when it is
1425 not storing directly into memory. So fix this up to avoid
1426 crashes in output_constant_pool. */
1427 if (operands
[1] == const0_rtx
)
1428 operands
[1] = CONST0_RTX (mode
);
1430 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1431 always other regs. */
1432 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1433 && (const_zero_operand (operands
[1], mode
)
1434 || const_all_ones_operand (operands
[1], mode
)))
1437 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1438 /* We are able to build any SF constant in integer registers
1439 with at most 2 instructions. */
1441 /* And any DF constant in integer registers. */
1443 && ! can_create_pseudo_p ())))
1446 operands
[1] = force_const_mem (mode
, operands
[1]);
1447 if (!reload_in_progress
)
1448 operands
[1] = validize_mem (operands
[1]);
1452 /* Accept non-constants and valid constants unmodified. */
1453 if (!CONSTANT_P (operands
[1])
1454 || GET_CODE (operands
[1]) == HIGH
1455 || input_operand (operands
[1], mode
))
1461 /* All QImode constants require only one insn, so proceed. */
1466 sparc_emit_set_const32 (operands
[0], operands
[1]);
1470 /* input_operand should have filtered out 32-bit mode. */
1471 sparc_emit_set_const64 (operands
[0], operands
[1]);
1477 /* TImode isn't available in 32-bit mode. */
1478 split_double (operands
[1], &high
, &low
);
1479 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
1481 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
1493 /* Load OP1, a 32-bit constant, into OP0, a register.
1494 We know it can't be done in one insn when we get
1495 here, the move expander guarantees this. */
1498 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1500 enum machine_mode mode
= GET_MODE (op0
);
1503 if (can_create_pseudo_p ())
1504 temp
= gen_reg_rtx (mode
);
1506 if (GET_CODE (op1
) == CONST_INT
)
1508 gcc_assert (!small_int_operand (op1
, mode
)
1509 && !const_high_operand (op1
, mode
));
1511 /* Emit them as real moves instead of a HIGH/LO_SUM,
1512 this way CSE can see everything and reuse intermediate
1513 values if it wants. */
1514 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1515 GEN_INT (INTVAL (op1
)
1516 & ~(HOST_WIDE_INT
)0x3ff)));
1518 emit_insn (gen_rtx_SET (VOIDmode
,
1520 gen_rtx_IOR (mode
, temp
,
1521 GEN_INT (INTVAL (op1
) & 0x3ff))));
1525 /* A symbol, emit in the traditional way. */
1526 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1527 gen_rtx_HIGH (mode
, op1
)));
1528 emit_insn (gen_rtx_SET (VOIDmode
,
1529 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1533 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1534 If TEMP is nonzero, we are forbidden to use any other scratch
1535 registers. Otherwise, we are allowed to generate them as needed.
1537 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1538 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1541 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1543 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1546 if (temp
&& GET_MODE (temp
) == TImode
)
1549 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1552 /* SPARC-V9 code-model support. */
1553 switch (sparc_cmodel
)
1556 /* The range spanned by all instructions in the object is less
1557 than 2^31 bytes (2GB) and the distance from any instruction
1558 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1559 than 2^31 bytes (2GB).
1561 The executable must be in the low 4TB of the virtual address
1564 sethi %hi(symbol), %temp1
1565 or %temp1, %lo(symbol), %reg */
1567 temp1
= temp
; /* op0 is allowed. */
1569 temp1
= gen_reg_rtx (DImode
);
1571 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1572 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1576 /* The range spanned by all instructions in the object is less
1577 than 2^31 bytes (2GB) and the distance from any instruction
1578 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1579 than 2^31 bytes (2GB).
1581 The executable must be in the low 16TB of the virtual address
1584 sethi %h44(symbol), %temp1
1585 or %temp1, %m44(symbol), %temp2
1586 sllx %temp2, 12, %temp3
1587 or %temp3, %l44(symbol), %reg */
1592 temp3
= temp
; /* op0 is allowed. */
1596 temp1
= gen_reg_rtx (DImode
);
1597 temp2
= gen_reg_rtx (DImode
);
1598 temp3
= gen_reg_rtx (DImode
);
1601 emit_insn (gen_seth44 (temp1
, op1
));
1602 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1603 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1604 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1605 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1609 /* The range spanned by all instructions in the object is less
1610 than 2^31 bytes (2GB) and the distance from any instruction
1611 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1612 than 2^31 bytes (2GB).
1614 The executable can be placed anywhere in the virtual address
1617 sethi %hh(symbol), %temp1
1618 sethi %lm(symbol), %temp2
1619 or %temp1, %hm(symbol), %temp3
1620 sllx %temp3, 32, %temp4
1621 or %temp4, %temp2, %temp5
1622 or %temp5, %lo(symbol), %reg */
1625 /* It is possible that one of the registers we got for operands[2]
1626 might coincide with that of operands[0] (which is why we made
1627 it TImode). Pick the other one to use as our scratch. */
1628 if (rtx_equal_p (temp
, op0
))
1630 gcc_assert (ti_temp
);
1631 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1634 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1641 temp1
= gen_reg_rtx (DImode
);
1642 temp2
= gen_reg_rtx (DImode
);
1643 temp3
= gen_reg_rtx (DImode
);
1644 temp4
= gen_reg_rtx (DImode
);
1645 temp5
= gen_reg_rtx (DImode
);
1648 emit_insn (gen_sethh (temp1
, op1
));
1649 emit_insn (gen_setlm (temp2
, op1
));
1650 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1651 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1652 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1653 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1654 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1655 emit_insn (gen_setlo (op0
, temp5
, op1
));
1659 /* Old old old backwards compatibility kruft here.
1660 Essentially it is MEDLOW with a fixed 64-bit
1661 virtual base added to all data segment addresses.
1662 Text-segment stuff is computed like MEDANY, we can't
1663 reuse the code above because the relocation knobs
1666 Data segment: sethi %hi(symbol), %temp1
1667 add %temp1, EMBMEDANY_BASE_REG, %temp2
1668 or %temp2, %lo(symbol), %reg */
1669 if (data_segment_operand (op1
, GET_MODE (op1
)))
1673 temp1
= temp
; /* op0 is allowed. */
1678 temp1
= gen_reg_rtx (DImode
);
1679 temp2
= gen_reg_rtx (DImode
);
1682 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1683 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1684 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1687 /* Text segment: sethi %uhi(symbol), %temp1
1688 sethi %hi(symbol), %temp2
1689 or %temp1, %ulo(symbol), %temp3
1690 sllx %temp3, 32, %temp4
1691 or %temp4, %temp2, %temp5
1692 or %temp5, %lo(symbol), %reg */
1697 /* It is possible that one of the registers we got for operands[2]
1698 might coincide with that of operands[0] (which is why we made
1699 it TImode). Pick the other one to use as our scratch. */
1700 if (rtx_equal_p (temp
, op0
))
1702 gcc_assert (ti_temp
);
1703 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1706 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1713 temp1
= gen_reg_rtx (DImode
);
1714 temp2
= gen_reg_rtx (DImode
);
1715 temp3
= gen_reg_rtx (DImode
);
1716 temp4
= gen_reg_rtx (DImode
);
1717 temp5
= gen_reg_rtx (DImode
);
1720 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1721 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1722 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1723 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1724 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1725 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1726 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1727 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1736 #if HOST_BITS_PER_WIDE_INT == 32
1738 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1743 /* These avoid problems when cross compiling. If we do not
1744 go through all this hair then the optimizer will see
1745 invalid REG_EQUAL notes or in some cases none at all. */
1746 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1747 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1748 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1749 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1751 /* The optimizer is not to assume anything about exactly
1752 which bits are set for a HIGH, they are unspecified.
1753 Unfortunately this leads to many missed optimizations
1754 during CSE. We mask out the non-HIGH bits, and matches
1755 a plain movdi, to alleviate this problem. */
1757 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1759 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1763 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1765 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1769 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1771 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1775 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1777 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1780 /* Worker routines for 64-bit constant formation on arch64.
1781 One of the key things to be doing in these emissions is
1782 to create as many temp REGs as possible. This makes it
1783 possible for half-built constants to be used later when
1784 such values are similar to something required later on.
1785 Without doing this, the optimizer cannot see such
1788 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1789 unsigned HOST_WIDE_INT
, int);
1792 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1793 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1795 unsigned HOST_WIDE_INT high_bits
;
1798 high_bits
= (~low_bits
) & 0xffffffff;
1800 high_bits
= low_bits
;
1802 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1805 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1806 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1810 /* If we are XOR'ing with -1, then we should emit a one's complement
1811 instead. This way the combiner will notice logical operations
1812 such as ANDN later on and substitute. */
1813 if ((low_bits
& 0x3ff) == 0x3ff)
1815 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1816 gen_rtx_NOT (DImode
, temp
)));
1820 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1821 gen_safe_XOR64 (temp
,
1822 (-(HOST_WIDE_INT
)0x400
1823 | (low_bits
& 0x3ff)))));
1828 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1829 unsigned HOST_WIDE_INT
, int);
1832 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1833 unsigned HOST_WIDE_INT high_bits
,
1834 unsigned HOST_WIDE_INT low_immediate
,
1839 if ((high_bits
& 0xfffffc00) != 0)
1841 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1842 if ((high_bits
& ~0xfffffc00) != 0)
1843 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1844 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1850 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1854 /* Now shift it up into place. */
1855 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1856 gen_rtx_ASHIFT (DImode
, temp2
,
1857 GEN_INT (shift_count
))));
1859 /* If there is a low immediate part piece, finish up by
1860 putting that in as well. */
1861 if (low_immediate
!= 0)
1862 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1863 gen_safe_OR64 (op0
, low_immediate
)));
1866 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1867 unsigned HOST_WIDE_INT
);
1869 /* Full 64-bit constant decomposition. Even though this is the
1870 'worst' case, we still optimize a few things away. */
1872 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1873 unsigned HOST_WIDE_INT high_bits
,
1874 unsigned HOST_WIDE_INT low_bits
)
1878 if (can_create_pseudo_p ())
1879 sub_temp
= gen_reg_rtx (DImode
);
1881 if ((high_bits
& 0xfffffc00) != 0)
1883 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1884 if ((high_bits
& ~0xfffffc00) != 0)
1885 emit_insn (gen_rtx_SET (VOIDmode
,
1887 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1893 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1897 if (can_create_pseudo_p ())
1899 rtx temp2
= gen_reg_rtx (DImode
);
1900 rtx temp3
= gen_reg_rtx (DImode
);
1901 rtx temp4
= gen_reg_rtx (DImode
);
1903 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1904 gen_rtx_ASHIFT (DImode
, sub_temp
,
1907 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1908 if ((low_bits
& ~0xfffffc00) != 0)
1910 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1911 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1912 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1913 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1917 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1918 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1923 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1924 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1925 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1928 /* We are in the middle of reload, so this is really
1929 painful. However we do still make an attempt to
1930 avoid emitting truly stupid code. */
1931 if (low1
!= const0_rtx
)
1933 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1934 gen_rtx_ASHIFT (DImode
, sub_temp
,
1935 GEN_INT (to_shift
))));
1936 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1937 gen_rtx_IOR (DImode
, op0
, low1
)));
1945 if (low2
!= const0_rtx
)
1947 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1948 gen_rtx_ASHIFT (DImode
, sub_temp
,
1949 GEN_INT (to_shift
))));
1950 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1951 gen_rtx_IOR (DImode
, op0
, low2
)));
1959 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1960 gen_rtx_ASHIFT (DImode
, sub_temp
,
1961 GEN_INT (to_shift
))));
1962 if (low3
!= const0_rtx
)
1963 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1964 gen_rtx_IOR (DImode
, op0
, low3
)));
1969 /* Analyze a 64-bit constant for certain properties. */
1970 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1971 unsigned HOST_WIDE_INT
,
1972 int *, int *, int *);
1975 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1976 unsigned HOST_WIDE_INT low_bits
,
1977 int *hbsp
, int *lbsp
, int *abbasp
)
1979 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1982 lowest_bit_set
= highest_bit_set
= -1;
1986 if ((lowest_bit_set
== -1)
1987 && ((low_bits
>> i
) & 1))
1989 if ((highest_bit_set
== -1)
1990 && ((high_bits
>> (32 - i
- 1)) & 1))
1991 highest_bit_set
= (64 - i
- 1);
1994 && ((highest_bit_set
== -1)
1995 || (lowest_bit_set
== -1)));
2001 if ((lowest_bit_set
== -1)
2002 && ((high_bits
>> i
) & 1))
2003 lowest_bit_set
= i
+ 32;
2004 if ((highest_bit_set
== -1)
2005 && ((low_bits
>> (32 - i
- 1)) & 1))
2006 highest_bit_set
= 32 - i
- 1;
2009 && ((highest_bit_set
== -1)
2010 || (lowest_bit_set
== -1)));
2012 /* If there are no bits set this should have gone out
2013 as one instruction! */
2014 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2015 all_bits_between_are_set
= 1;
2016 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2020 if ((low_bits
& (1 << i
)) != 0)
2025 if ((high_bits
& (1 << (i
- 32))) != 0)
2028 all_bits_between_are_set
= 0;
2031 *hbsp
= highest_bit_set
;
2032 *lbsp
= lowest_bit_set
;
2033 *abbasp
= all_bits_between_are_set
;
2036 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2039 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2040 unsigned HOST_WIDE_INT low_bits
)
2042 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2045 || high_bits
== 0xffffffff)
2048 analyze_64bit_constant (high_bits
, low_bits
,
2049 &highest_bit_set
, &lowest_bit_set
,
2050 &all_bits_between_are_set
);
2052 if ((highest_bit_set
== 63
2053 || lowest_bit_set
== 0)
2054 && all_bits_between_are_set
!= 0)
2057 if ((highest_bit_set
- lowest_bit_set
) < 21)
2063 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2064 unsigned HOST_WIDE_INT
,
2067 static unsigned HOST_WIDE_INT
2068 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2069 unsigned HOST_WIDE_INT low_bits
,
2070 int lowest_bit_set
, int shift
)
2072 HOST_WIDE_INT hi
, lo
;
2074 if (lowest_bit_set
< 32)
2076 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2077 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2082 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2084 gcc_assert (! (hi
& lo
));
2088 /* Here we are sure to be arch64 and this is an integer constant
2089 being loaded into a register. Emit the most efficient
2090 insn sequence possible. Detection of all the 1-insn cases
2091 has been done already. */
2093 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2095 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2096 int lowest_bit_set
, highest_bit_set
;
2097 int all_bits_between_are_set
;
2100 /* Sanity check that we know what we are working with. */
2101 gcc_assert (TARGET_ARCH64
2102 && (GET_CODE (op0
) == SUBREG
2103 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2105 if (! can_create_pseudo_p ())
2108 if (GET_CODE (op1
) != CONST_INT
)
2110 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2115 temp
= gen_reg_rtx (DImode
);
2117 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2118 low_bits
= (INTVAL (op1
) & 0xffffffff);
2120 /* low_bits bits 0 --> 31
2121 high_bits bits 32 --> 63 */
2123 analyze_64bit_constant (high_bits
, low_bits
,
2124 &highest_bit_set
, &lowest_bit_set
,
2125 &all_bits_between_are_set
);
2127 /* First try for a 2-insn sequence. */
2129 /* These situations are preferred because the optimizer can
2130 * do more things with them:
2132 * sllx %reg, shift, %reg
2134 * srlx %reg, shift, %reg
2135 * 3) mov some_small_const, %reg
2136 * sllx %reg, shift, %reg
2138 if (((highest_bit_set
== 63
2139 || lowest_bit_set
== 0)
2140 && all_bits_between_are_set
!= 0)
2141 || ((highest_bit_set
- lowest_bit_set
) < 12))
2143 HOST_WIDE_INT the_const
= -1;
2144 int shift
= lowest_bit_set
;
2146 if ((highest_bit_set
!= 63
2147 && lowest_bit_set
!= 0)
2148 || all_bits_between_are_set
== 0)
2151 create_simple_focus_bits (high_bits
, low_bits
,
2154 else if (lowest_bit_set
== 0)
2155 shift
= -(63 - highest_bit_set
);
2157 gcc_assert (SPARC_SIMM13_P (the_const
));
2158 gcc_assert (shift
!= 0);
2160 emit_insn (gen_safe_SET64 (temp
, the_const
));
2162 emit_insn (gen_rtx_SET (VOIDmode
,
2164 gen_rtx_ASHIFT (DImode
,
2168 emit_insn (gen_rtx_SET (VOIDmode
,
2170 gen_rtx_LSHIFTRT (DImode
,
2172 GEN_INT (-shift
))));
2176 /* Now a range of 22 or less bits set somewhere.
2177 * 1) sethi %hi(focus_bits), %reg
2178 * sllx %reg, shift, %reg
2179 * 2) sethi %hi(focus_bits), %reg
2180 * srlx %reg, shift, %reg
2182 if ((highest_bit_set
- lowest_bit_set
) < 21)
2184 unsigned HOST_WIDE_INT focus_bits
=
2185 create_simple_focus_bits (high_bits
, low_bits
,
2186 lowest_bit_set
, 10);
2188 gcc_assert (SPARC_SETHI_P (focus_bits
));
2189 gcc_assert (lowest_bit_set
!= 10);
2191 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2193 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2194 if (lowest_bit_set
< 10)
2195 emit_insn (gen_rtx_SET (VOIDmode
,
2197 gen_rtx_LSHIFTRT (DImode
, temp
,
2198 GEN_INT (10 - lowest_bit_set
))));
2199 else if (lowest_bit_set
> 10)
2200 emit_insn (gen_rtx_SET (VOIDmode
,
2202 gen_rtx_ASHIFT (DImode
, temp
,
2203 GEN_INT (lowest_bit_set
- 10))));
2207 /* 1) sethi %hi(low_bits), %reg
2208 * or %reg, %lo(low_bits), %reg
2209 * 2) sethi %hi(~low_bits), %reg
2210 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2213 || high_bits
== 0xffffffff)
2215 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2216 (high_bits
== 0xffffffff));
2220 /* Now, try 3-insn sequences. */
2222 /* 1) sethi %hi(high_bits), %reg
2223 * or %reg, %lo(high_bits), %reg
2224 * sllx %reg, 32, %reg
2228 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2232 /* We may be able to do something quick
2233 when the constant is negated, so try that. */
2234 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2235 (~low_bits
) & 0xfffffc00))
2237 /* NOTE: The trailing bits get XOR'd so we need the
2238 non-negated bits, not the negated ones. */
2239 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2241 if ((((~high_bits
) & 0xffffffff) == 0
2242 && ((~low_bits
) & 0x80000000) == 0)
2243 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2244 && ((~low_bits
) & 0x80000000) != 0))
2246 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2248 if ((SPARC_SETHI_P (fast_int
)
2249 && (~high_bits
& 0xffffffff) == 0)
2250 || SPARC_SIMM13_P (fast_int
))
2251 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2253 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2258 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2259 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2260 sparc_emit_set_const64 (temp
, negated_const
);
2263 /* If we are XOR'ing with -1, then we should emit a one's complement
2264 instead. This way the combiner will notice logical operations
2265 such as ANDN later on and substitute. */
2266 if (trailing_bits
== 0x3ff)
2268 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2269 gen_rtx_NOT (DImode
, temp
)));
2273 emit_insn (gen_rtx_SET (VOIDmode
,
2275 gen_safe_XOR64 (temp
,
2276 (-0x400 | trailing_bits
))));
2281 /* 1) sethi %hi(xxx), %reg
2282 * or %reg, %lo(xxx), %reg
2283 * sllx %reg, yyy, %reg
2285 * ??? This is just a generalized version of the low_bits==0
2286 * thing above, FIXME...
2288 if ((highest_bit_set
- lowest_bit_set
) < 32)
2290 unsigned HOST_WIDE_INT focus_bits
=
2291 create_simple_focus_bits (high_bits
, low_bits
,
2294 /* We can't get here in this state. */
2295 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2297 /* So what we know is that the set bits straddle the
2298 middle of the 64-bit word. */
2299 sparc_emit_set_const64_quick2 (op0
, temp
,
2305 /* 1) sethi %hi(high_bits), %reg
2306 * or %reg, %lo(high_bits), %reg
2307 * sllx %reg, 32, %reg
2308 * or %reg, low_bits, %reg
2310 if (SPARC_SIMM13_P(low_bits
)
2311 && ((int)low_bits
> 0))
2313 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2317 /* The easiest way when all else fails, is full decomposition. */
2318 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2320 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2322 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2323 return the mode to be used for the comparison. For floating-point,
2324 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2325 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2326 processing is needed. */
2329 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2331 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2357 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2358 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2360 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2361 return CCX_NOOVmode
;
2367 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2374 /* Emit the compare insn and return the CC reg for a CODE comparison
2375 with operands X and Y. */
2378 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2380 enum machine_mode mode
;
2383 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2386 mode
= SELECT_CC_MODE (code
, x
, y
);
2388 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2389 fcc regs (cse can't tell they're really call clobbered regs and will
2390 remove a duplicate comparison even if there is an intervening function
2391 call - it will then try to reload the cc reg via an int reg which is why
2392 we need the movcc patterns). It is possible to provide the movcc
2393 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2394 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2395 to tell cse that CCFPE mode registers (even pseudos) are call
2398 /* ??? This is an experiment. Rather than making changes to cse which may
2399 or may not be easy/clean, we do our own cse. This is possible because
2400 we will generate hard registers. Cse knows they're call clobbered (it
2401 doesn't know the same thing about pseudos). If we guess wrong, no big
2402 deal, but if we win, great! */
2404 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2405 #if 1 /* experiment */
2408 /* We cycle through the registers to ensure they're all exercised. */
2409 static int next_fcc_reg
= 0;
2410 /* Previous x,y for each fcc reg. */
2411 static rtx prev_args
[4][2];
2413 /* Scan prev_args for x,y. */
2414 for (reg
= 0; reg
< 4; reg
++)
2415 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2420 prev_args
[reg
][0] = x
;
2421 prev_args
[reg
][1] = y
;
2422 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2424 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2427 cc_reg
= gen_reg_rtx (mode
);
2428 #endif /* ! experiment */
2429 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2430 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2432 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2434 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2435 will only result in an unrecognizable insn so no point in asserting. */
2436 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2442 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2445 gen_compare_reg (rtx cmp
)
2447 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2450 /* This function is used for v9 only.
2451 DEST is the target of the Scc insn.
2452 CODE is the code for an Scc's comparison.
2453 X and Y are the values we compare.
2455 This function is needed to turn
2458 (gt (reg:CCX 100 %icc)
2462 (gt:DI (reg:CCX 100 %icc)
2465 IE: The instruction recognizer needs to see the mode of the comparison to
2466 find the right instruction. We could use "gt:DI" right in the
2467 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2470 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2473 && (GET_MODE (x
) == DImode
2474 || GET_MODE (dest
) == DImode
))
2477 /* Try to use the movrCC insns. */
2479 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2481 && v9_regcmp_p (compare_code
))
2486 /* Special case for op0 != 0. This can be done with one instruction if
2489 if (compare_code
== NE
2490 && GET_MODE (dest
) == DImode
2491 && rtx_equal_p (op0
, dest
))
2493 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2494 gen_rtx_IF_THEN_ELSE (DImode
,
2495 gen_rtx_fmt_ee (compare_code
, DImode
,
2502 if (reg_overlap_mentioned_p (dest
, op0
))
2504 /* Handle the case where dest == x.
2505 We "early clobber" the result. */
2506 op0
= gen_reg_rtx (GET_MODE (x
));
2507 emit_move_insn (op0
, x
);
2510 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2511 if (GET_MODE (op0
) != DImode
)
2513 temp
= gen_reg_rtx (DImode
);
2514 convert_move (temp
, op0
, 0);
2518 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2519 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2520 gen_rtx_fmt_ee (compare_code
, DImode
,
2528 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2531 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2532 && GET_MODE (x
) != CCX_NOOVmode
);
2534 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2535 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2536 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2537 gen_rtx_fmt_ee (compare_code
,
2538 GET_MODE (x
), x
, y
),
2539 const1_rtx
, dest
)));
2545 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2546 without jumps using the addx/subx instructions. */
2549 emit_scc_insn (rtx operands
[])
2556 /* The quad-word fp compare library routines all return nonzero to indicate
2557 true, which is different from the equivalent libgcc routines, so we must
2558 handle them specially here. */
2559 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2561 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2562 GET_CODE (operands
[1]));
2563 operands
[2] = XEXP (operands
[1], 0);
2564 operands
[3] = XEXP (operands
[1], 1);
2567 code
= GET_CODE (operands
[1]);
2571 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2572 more applications). The exception to this is "reg != 0" which can
2573 be done in one instruction on v9 (so we do it). */
2576 if (GET_MODE (x
) == SImode
)
2578 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2582 else if (GET_MODE (x
) == DImode
)
2584 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2592 if (GET_MODE (x
) == SImode
)
2594 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2598 else if (GET_MODE (x
) == DImode
)
2602 pat
= gen_snedi_special_vis3 (operands
[0], x
, y
);
2604 pat
= gen_snedi_special (operands
[0], x
, y
);
2612 && GET_MODE (x
) == DImode
2614 && (code
== GTU
|| code
== LTU
))
2615 && gen_v9_scc (operands
[0], code
, x
, y
))
2618 /* We can do LTU and GEU using the addx/subx instructions too. And
2619 for GTU/LEU, if both operands are registers swap them and fall
2620 back to the easy case. */
2621 if (code
== GTU
|| code
== LEU
)
2623 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2624 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2629 code
= swap_condition (code
);
2634 || (!TARGET_VIS3
&& code
== GEU
))
2636 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2637 gen_rtx_fmt_ee (code
, SImode
,
2638 gen_compare_reg_1 (code
, x
, y
),
2643 /* All the posibilities to use addx/subx based sequences has been
2644 exhausted, try for a 3 instruction sequence using v9 conditional
2646 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
2649 /* Nope, do branches. */
2653 /* Emit a conditional jump insn for the v9 architecture using comparison code
2654 CODE and jump target LABEL.
2655 This function exists to take advantage of the v9 brxx insns. */
2658 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2660 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2662 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2663 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2665 gen_rtx_LABEL_REF (VOIDmode
, label
),
2669 /* Emit a conditional jump insn for the UA2011 architecture using
2670 comparison code CODE and jump target LABEL. This function exists
2671 to take advantage of the UA2011 Compare and Branch insns. */
2674 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
2678 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
2679 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
2681 gen_rtx_LABEL_REF (VOIDmode
, label
),
2684 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_then_else
));
2688 emit_conditional_branch_insn (rtx operands
[])
2690 /* The quad-word fp compare library routines all return nonzero to indicate
2691 true, which is different from the equivalent libgcc routines, so we must
2692 handle them specially here. */
2693 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2695 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2696 GET_CODE (operands
[0]));
2697 operands
[1] = XEXP (operands
[0], 0);
2698 operands
[2] = XEXP (operands
[0], 1);
2701 /* If we can tell early on that the comparison is against a constant
2702 that won't fit in the 5-bit signed immediate field of a cbcond,
2703 use one of the other v9 conditional branch sequences. */
2705 && GET_CODE (operands
[1]) == REG
2706 && (GET_MODE (operands
[1]) == SImode
2707 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
2708 && (GET_CODE (operands
[2]) != CONST_INT
2709 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
2711 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
2715 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2716 && GET_CODE (operands
[1]) == REG
2717 && GET_MODE (operands
[1]) == DImode
)
2719 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2723 operands
[1] = gen_compare_reg (operands
[0]);
2724 operands
[2] = const0_rtx
;
2725 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2726 operands
[1], operands
[2]);
2727 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2732 /* Generate a DFmode part of a hard TFmode register.
2733 REG is the TFmode hard register, LOW is 1 for the
2734 low 64bit of the register and 0 otherwise.
2737 gen_df_reg (rtx reg
, int low
)
2739 int regno
= REGNO (reg
);
2741 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2742 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
2743 return gen_rtx_REG (DFmode
, regno
);
2746 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2747 Unlike normal calls, TFmode operands are passed by reference. It is
2748 assumed that no more than 3 operands are required. */
2751 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2753 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2756 /* We only expect to be called for conversions, unary, and binary ops. */
2757 gcc_assert (nargs
== 2 || nargs
== 3);
2759 for (i
= 0; i
< nargs
; ++i
)
2761 rtx this_arg
= operands
[i
];
2764 /* TFmode arguments and return values are passed by reference. */
2765 if (GET_MODE (this_arg
) == TFmode
)
2767 int force_stack_temp
;
2769 force_stack_temp
= 0;
2770 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2771 force_stack_temp
= 1;
2773 if (GET_CODE (this_arg
) == MEM
2774 && ! force_stack_temp
)
2776 tree expr
= MEM_EXPR (this_arg
);
2778 mark_addressable (expr
);
2779 this_arg
= XEXP (this_arg
, 0);
2781 else if (CONSTANT_P (this_arg
)
2782 && ! force_stack_temp
)
2784 this_slot
= force_const_mem (TFmode
, this_arg
);
2785 this_arg
= XEXP (this_slot
, 0);
2789 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
2791 /* Operand 0 is the return value. We'll copy it out later. */
2793 emit_move_insn (this_slot
, this_arg
);
2795 ret_slot
= this_slot
;
2797 this_arg
= XEXP (this_slot
, 0);
2804 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2806 if (GET_MODE (operands
[0]) == TFmode
)
2809 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2810 arg
[0], GET_MODE (arg
[0]),
2811 arg
[1], GET_MODE (arg
[1]));
2813 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2814 arg
[0], GET_MODE (arg
[0]),
2815 arg
[1], GET_MODE (arg
[1]),
2816 arg
[2], GET_MODE (arg
[2]));
2819 emit_move_insn (operands
[0], ret_slot
);
2825 gcc_assert (nargs
== 2);
2827 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2828 GET_MODE (operands
[0]), 1,
2829 arg
[1], GET_MODE (arg
[1]));
2831 if (ret
!= operands
[0])
2832 emit_move_insn (operands
[0], ret
);
2836 /* Expand soft-float TFmode calls to sparc abi routines. */
2839 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2861 emit_soft_tfmode_libcall (func
, 3, operands
);
2865 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2869 gcc_assert (code
== SQRT
);
2872 emit_soft_tfmode_libcall (func
, 2, operands
);
2876 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2883 switch (GET_MODE (operands
[1]))
2896 case FLOAT_TRUNCATE
:
2897 switch (GET_MODE (operands
[0]))
2911 switch (GET_MODE (operands
[1]))
2916 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2926 case UNSIGNED_FLOAT
:
2927 switch (GET_MODE (operands
[1]))
2932 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2943 switch (GET_MODE (operands
[0]))
2957 switch (GET_MODE (operands
[0]))
2974 emit_soft_tfmode_libcall (func
, 2, operands
);
2977 /* Expand a hard-float tfmode operation. All arguments must be in
2981 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2985 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2987 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2988 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2992 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2993 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2994 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2995 operands
[1], operands
[2]);
2998 if (register_operand (operands
[0], VOIDmode
))
3001 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3003 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
3005 if (dest
!= operands
[0])
3006 emit_move_insn (operands
[0], dest
);
3010 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3012 if (TARGET_HARD_QUAD
)
3013 emit_hard_tfmode_operation (code
, operands
);
3015 emit_soft_tfmode_binop (code
, operands
);
3019 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3021 if (TARGET_HARD_QUAD
)
3022 emit_hard_tfmode_operation (code
, operands
);
3024 emit_soft_tfmode_unop (code
, operands
);
3028 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3030 if (TARGET_HARD_QUAD
)
3031 emit_hard_tfmode_operation (code
, operands
);
3033 emit_soft_tfmode_cvt (code
, operands
);
3036 /* Return nonzero if a branch/jump/call instruction will be emitting
3037 nop into its delay slot. */
3040 empty_delay_slot (rtx insn
)
3044 /* If no previous instruction (should not happen), return true. */
3045 if (PREV_INSN (insn
) == NULL
)
3048 seq
= NEXT_INSN (PREV_INSN (insn
));
3049 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3055 /* Return nonzero if we should emit a nop after a cbcond instruction.
3056 The cbcond instruction does not have a delay slot, however there is
3057 a severe performance penalty if a control transfer appears right
3058 after a cbcond. Therefore we emit a nop when we detect this
3062 emit_cbcond_nop (rtx insn
)
3064 rtx next
= next_active_insn (insn
);
3069 if (GET_CODE (next
) == INSN
3070 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3071 next
= XVECEXP (PATTERN (next
), 0, 0);
3072 else if (GET_CODE (next
) == CALL_INSN
3073 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3075 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3077 if (GET_CODE (delay
) == RETURN
)
3079 /* It's a sibling call. Do not emit the nop if we're going
3080 to emit something other than the jump itself as the first
3081 instruction of the sibcall sequence. */
3082 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3087 if (NONJUMP_INSN_P (next
))
3093 /* Return nonzero if TRIAL can go into the call delay slot. */
3096 tls_call_delay (rtx trial
)
3101 call __tls_get_addr, %tgd_call (foo)
3102 add %l7, %o0, %o0, %tgd_add (foo)
3103 while Sun as/ld does not. */
3104 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3107 pat
= PATTERN (trial
);
3109 /* We must reject tgd_add{32|64}, i.e.
3110 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3111 and tldm_add{32|64}, i.e.
3112 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3114 if (GET_CODE (pat
) == SET
3115 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3117 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3119 if (GET_CODE (unspec
) == UNSPEC
3120 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3121 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3128 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3129 instruction. RETURN_P is true if the v9 variant 'return' is to be
3130 considered in the test too.
3132 TRIAL must be a SET whose destination is a REG appropriate for the
3133 'restore' instruction or, if RETURN_P is true, for the 'return'
3137 eligible_for_restore_insn (rtx trial
, bool return_p
)
3139 rtx pat
= PATTERN (trial
);
3140 rtx src
= SET_SRC (pat
);
3141 bool src_is_freg
= false;
3144 /* Since we now can do moves between float and integer registers when
3145 VIS3 is enabled, we have to catch this case. We can allow such
3146 moves when doing a 'return' however. */
3148 if (GET_CODE (src_reg
) == SUBREG
)
3149 src_reg
= SUBREG_REG (src_reg
);
3150 if (GET_CODE (src_reg
) == REG
3151 && SPARC_FP_REG_P (REGNO (src_reg
)))
3154 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3155 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3156 && arith_operand (src
, GET_MODE (src
))
3160 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3162 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3165 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3166 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3167 && arith_double_operand (src
, GET_MODE (src
))
3169 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3171 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3172 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3175 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3176 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3179 /* If we have the 'return' instruction, anything that does not use
3180 local or output registers and can go into a delay slot wins. */
3183 && !epilogue_renumber (&pat
, 1)
3184 && get_attr_in_uncond_branch_delay (trial
)
3185 == IN_UNCOND_BRANCH_DELAY_TRUE
)
3188 /* The 'restore src1,src2,dest' pattern for SImode. */
3189 else if (GET_CODE (src
) == PLUS
3190 && register_operand (XEXP (src
, 0), SImode
)
3191 && arith_operand (XEXP (src
, 1), SImode
))
3194 /* The 'restore src1,src2,dest' pattern for DImode. */
3195 else if (GET_CODE (src
) == PLUS
3196 && register_operand (XEXP (src
, 0), DImode
)
3197 && arith_double_operand (XEXP (src
, 1), DImode
))
3200 /* The 'restore src1,%lo(src2),dest' pattern. */
3201 else if (GET_CODE (src
) == LO_SUM
3202 && ! TARGET_CM_MEDMID
3203 && ((register_operand (XEXP (src
, 0), SImode
)
3204 && immediate_operand (XEXP (src
, 1), SImode
))
3206 && register_operand (XEXP (src
, 0), DImode
)
3207 && immediate_operand (XEXP (src
, 1), DImode
))))
3210 /* The 'restore src,src,dest' pattern. */
3211 else if (GET_CODE (src
) == ASHIFT
3212 && (register_operand (XEXP (src
, 0), SImode
)
3213 || register_operand (XEXP (src
, 0), DImode
))
3214 && XEXP (src
, 1) == const1_rtx
)
3220 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3223 eligible_for_return_delay (rtx trial
)
3228 if (GET_CODE (trial
) != INSN
)
3231 if (get_attr_length (trial
) != 1)
3234 /* If the function uses __builtin_eh_return, the eh_return machinery
3235 occupies the delay slot. */
3236 if (crtl
->calls_eh_return
)
3239 /* In the case of a leaf or flat function, anything can go into the slot. */
3240 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3242 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
3244 pat
= PATTERN (trial
);
3245 if (GET_CODE (pat
) == PARALLEL
)
3251 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3253 rtx expr
= XVECEXP (pat
, 0, i
);
3254 if (GET_CODE (expr
) != SET
)
3256 if (GET_CODE (SET_DEST (expr
)) != REG
)
3258 regno
= REGNO (SET_DEST (expr
));
3259 if (regno
>= 8 && regno
< 24)
3262 return !epilogue_renumber (&pat
, 1)
3263 && (get_attr_in_uncond_branch_delay (trial
)
3264 == IN_UNCOND_BRANCH_DELAY_TRUE
);
3267 if (GET_CODE (pat
) != SET
)
3270 if (GET_CODE (SET_DEST (pat
)) != REG
)
3273 regno
= REGNO (SET_DEST (pat
));
3275 /* Otherwise, only operations which can be done in tandem with
3276 a `restore' or `return' insn can go into the delay slot. */
3277 if (regno
>= 8 && regno
< 24)
3280 /* If this instruction sets up floating point register and we have a return
3281 instruction, it can probably go in. But restore will not work
3283 if (! SPARC_INT_REG_P (regno
))
3285 && !epilogue_renumber (&pat
, 1)
3286 && get_attr_in_uncond_branch_delay (trial
)
3287 == IN_UNCOND_BRANCH_DELAY_TRUE
);
3289 return eligible_for_restore_insn (trial
, true);
3292 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3295 eligible_for_sibcall_delay (rtx trial
)
3299 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
3302 if (get_attr_length (trial
) != 1)
3305 pat
= PATTERN (trial
);
3307 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3309 /* If the tail call is done using the call instruction,
3310 we have to restore %o7 in the delay slot. */
3311 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3314 /* %g1 is used to build the function address */
3315 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3321 /* Otherwise, only operations which can be done in tandem with
3322 a `restore' insn can go into the delay slot. */
3323 if (GET_CODE (SET_DEST (pat
)) != REG
3324 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3325 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3328 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3330 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3333 return eligible_for_restore_insn (trial
, false);
3336 /* Determine if it's legal to put X into the constant pool. This
3337 is not possible if X contains the address of a symbol that is
3338 not constant (TLS) or not known at final link time (PIC). */
3341 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
3343 switch (GET_CODE (x
))
3348 /* Accept all non-symbolic constants. */
3352 /* Labels are OK iff we are non-PIC. */
3353 return flag_pic
!= 0;
3356 /* 'Naked' TLS symbol references are never OK,
3357 non-TLS symbols are OK iff we are non-PIC. */
3358 if (SYMBOL_REF_TLS_MODEL (x
))
3361 return flag_pic
!= 0;
3364 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3367 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3368 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3376 /* Global Offset Table support. */
3377 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3378 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3380 /* Return the SYMBOL_REF for the Global Offset Table. */
3382 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3387 if (!sparc_got_symbol
)
3388 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3390 return sparc_got_symbol
;
3393 /* Ensure that we are not using patterns that are not OK with PIC. */
3403 op
= recog_data
.operand
[i
];
3404 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3405 && (GET_CODE (op
) != CONST
3406 || (GET_CODE (XEXP (op
, 0)) == MINUS
3407 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3408 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3415 /* Return true if X is an address which needs a temporary register when
3416 reloaded while generating PIC code. */
3419 pic_address_needs_scratch (rtx x
)
3421 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3422 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3423 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3424 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3425 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3431 /* Determine if a given RTX is a valid constant. We already know this
3432 satisfies CONSTANT_P. */
3435 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3437 switch (GET_CODE (x
))
3441 if (sparc_tls_referenced_p (x
))
3446 if (GET_MODE (x
) == VOIDmode
)
3449 /* Floating point constants are generally not ok.
3450 The only exception is 0.0 and all-ones in VIS. */
3452 && SCALAR_FLOAT_MODE_P (mode
)
3453 && (const_zero_operand (x
, mode
)
3454 || const_all_ones_operand (x
, mode
)))
3460 /* Vector constants are generally not ok.
3461 The only exception is 0 or -1 in VIS. */
3463 && (const_zero_operand (x
, mode
)
3464 || const_all_ones_operand (x
, mode
)))
3476 /* Determine if a given RTX is a valid constant address. */
3479 constant_address_p (rtx x
)
3481 switch (GET_CODE (x
))
3489 if (flag_pic
&& pic_address_needs_scratch (x
))
3491 return sparc_legitimate_constant_p (Pmode
, x
);
3494 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3501 /* Nonzero if the constant value X is a legitimate general operand
3502 when generating PIC code. It is given that flag_pic is on and
3503 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3506 legitimate_pic_operand_p (rtx x
)
3508 if (pic_address_needs_scratch (x
))
3510 if (sparc_tls_referenced_p (x
))
3515 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3517 && INTVAL (X) >= -0x1000 \
3518 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3520 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3522 && INTVAL (X) >= -0x1000 \
3523 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3525 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3527 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3528 ordinarily. This changes a bit when generating PIC. */
3531 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3533 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3535 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3537 else if (GET_CODE (addr
) == PLUS
)
3539 rs1
= XEXP (addr
, 0);
3540 rs2
= XEXP (addr
, 1);
3542 /* Canonicalize. REG comes first, if there are no regs,
3543 LO_SUM comes first. */
3545 && GET_CODE (rs1
) != SUBREG
3547 || GET_CODE (rs2
) == SUBREG
3548 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3550 rs1
= XEXP (addr
, 1);
3551 rs2
= XEXP (addr
, 0);
3555 && rs1
== pic_offset_table_rtx
3557 && GET_CODE (rs2
) != SUBREG
3558 && GET_CODE (rs2
) != LO_SUM
3559 && GET_CODE (rs2
) != MEM
3560 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3561 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3562 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3564 || GET_CODE (rs1
) == SUBREG
)
3565 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3570 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3571 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3573 /* We prohibit REG + REG for TFmode when there are no quad move insns
3574 and we consequently need to split. We do this because REG+REG
3575 is not an offsettable address. If we get the situation in reload
3576 where source and destination of a movtf pattern are both MEMs with
3577 REG+REG address, then only one of them gets converted to an
3578 offsettable address. */
3580 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3583 /* Likewise for TImode, but in all cases. */
3587 /* We prohibit REG + REG on ARCH32 if not optimizing for
3588 DFmode/DImode because then mem_min_alignment is likely to be zero
3589 after reload and the forced split would lack a matching splitter
3591 if (TARGET_ARCH32
&& !optimize
3592 && (mode
== DFmode
|| mode
== DImode
))
3595 else if (USE_AS_OFFSETABLE_LO10
3596 && GET_CODE (rs1
) == LO_SUM
3598 && ! TARGET_CM_MEDMID
3599 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3602 imm1
= XEXP (rs1
, 1);
3603 rs1
= XEXP (rs1
, 0);
3604 if (!CONSTANT_P (imm1
)
3605 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3609 else if (GET_CODE (addr
) == LO_SUM
)
3611 rs1
= XEXP (addr
, 0);
3612 imm1
= XEXP (addr
, 1);
3614 if (!CONSTANT_P (imm1
)
3615 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3618 /* We can't allow TFmode in 32-bit mode, because an offset greater
3619 than the alignment (8) may cause the LO_SUM to overflow. */
3620 if (mode
== TFmode
&& TARGET_ARCH32
)
3623 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3628 if (GET_CODE (rs1
) == SUBREG
)
3629 rs1
= SUBREG_REG (rs1
);
3635 if (GET_CODE (rs2
) == SUBREG
)
3636 rs2
= SUBREG_REG (rs2
);
3643 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3644 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3649 if ((! SPARC_INT_REG_P (REGNO (rs1
))
3650 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3651 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3653 && (! SPARC_INT_REG_P (REGNO (rs2
))
3654 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3655 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3661 /* Return the SYMBOL_REF for the tls_get_addr function. */
3663 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3666 sparc_tls_get_addr (void)
3668 if (!sparc_tls_symbol
)
3669 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3671 return sparc_tls_symbol
;
3674 /* Return the Global Offset Table to be used in TLS mode. */
3677 sparc_tls_got (void)
3679 /* In PIC mode, this is just the PIC offset table. */
3682 crtl
->uses_pic_offset_table
= 1;
3683 return pic_offset_table_rtx
;
3686 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3687 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3688 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3690 load_got_register ();
3691 return global_offset_table_rtx
;
3694 /* In all other cases, we load a new pseudo with the GOT symbol. */
3695 return copy_to_reg (sparc_got ());
3698 /* Return true if X contains a thread-local symbol. */
3701 sparc_tls_referenced_p (rtx x
)
3703 if (!TARGET_HAVE_TLS
)
3706 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3707 x
= XEXP (XEXP (x
, 0), 0);
3709 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3712 /* That's all we handle in sparc_legitimize_tls_address for now. */
3716 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3717 this (thread-local) address. */
3720 sparc_legitimize_tls_address (rtx addr
)
3722 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3724 gcc_assert (can_create_pseudo_p ());
3726 if (GET_CODE (addr
) == SYMBOL_REF
)
3727 switch (SYMBOL_REF_TLS_MODEL (addr
))
3729 case TLS_MODEL_GLOBAL_DYNAMIC
:
3731 temp1
= gen_reg_rtx (SImode
);
3732 temp2
= gen_reg_rtx (SImode
);
3733 ret
= gen_reg_rtx (Pmode
);
3734 o0
= gen_rtx_REG (Pmode
, 8);
3735 got
= sparc_tls_got ();
3736 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3737 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3740 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3741 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3746 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3747 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3750 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3751 insn
= get_insns ();
3753 emit_libcall_block (insn
, ret
, o0
, addr
);
3756 case TLS_MODEL_LOCAL_DYNAMIC
:
3758 temp1
= gen_reg_rtx (SImode
);
3759 temp2
= gen_reg_rtx (SImode
);
3760 temp3
= gen_reg_rtx (Pmode
);
3761 ret
= gen_reg_rtx (Pmode
);
3762 o0
= gen_rtx_REG (Pmode
, 8);
3763 got
= sparc_tls_got ();
3764 emit_insn (gen_tldm_hi22 (temp1
));
3765 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3768 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3769 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3774 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3775 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3778 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3779 insn
= get_insns ();
3781 emit_libcall_block (insn
, temp3
, o0
,
3782 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3783 UNSPEC_TLSLD_BASE
));
3784 temp1
= gen_reg_rtx (SImode
);
3785 temp2
= gen_reg_rtx (SImode
);
3786 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3787 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3789 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3791 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3794 case TLS_MODEL_INITIAL_EXEC
:
3795 temp1
= gen_reg_rtx (SImode
);
3796 temp2
= gen_reg_rtx (SImode
);
3797 temp3
= gen_reg_rtx (Pmode
);
3798 got
= sparc_tls_got ();
3799 emit_insn (gen_tie_hi22 (temp1
, addr
));
3800 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3802 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3804 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3807 ret
= gen_reg_rtx (Pmode
);
3809 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3812 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3816 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3819 case TLS_MODEL_LOCAL_EXEC
:
3820 temp1
= gen_reg_rtx (Pmode
);
3821 temp2
= gen_reg_rtx (Pmode
);
3824 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3825 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3829 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3830 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3832 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3839 else if (GET_CODE (addr
) == CONST
)
3843 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3845 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3846 offset
= XEXP (XEXP (addr
, 0), 1);
3848 base
= force_operand (base
, NULL_RTX
);
3849 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3850 offset
= force_reg (Pmode
, offset
);
3851 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3855 gcc_unreachable (); /* for now ... */
3860 /* Legitimize PIC addresses. If the address is already position-independent,
3861 we return ORIG. Newly generated position-independent addresses go into a
3862 reg. This is REG if nonzero, otherwise we allocate register(s) as
3866 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3868 bool gotdata_op
= false;
3870 if (GET_CODE (orig
) == SYMBOL_REF
3871 /* See the comment in sparc_expand_move. */
3872 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3874 rtx pic_ref
, address
;
3879 gcc_assert (can_create_pseudo_p ());
3880 reg
= gen_reg_rtx (Pmode
);
3885 /* If not during reload, allocate another temp reg here for loading
3886 in the address, so that these instructions can be optimized
3888 rtx temp_reg
= (! can_create_pseudo_p ()
3889 ? reg
: gen_reg_rtx (Pmode
));
3891 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3892 won't get confused into thinking that these two instructions
3893 are loading in the true address of the symbol. If in the
3894 future a PIC rtx exists, that should be used instead. */
3897 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3898 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3902 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3903 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3911 crtl
->uses_pic_offset_table
= 1;
3915 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3916 pic_offset_table_rtx
,
3919 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3920 pic_offset_table_rtx
,
3926 = gen_const_mem (Pmode
,
3927 gen_rtx_PLUS (Pmode
,
3928 pic_offset_table_rtx
, address
));
3929 insn
= emit_move_insn (reg
, pic_ref
);
3932 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3934 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3937 else if (GET_CODE (orig
) == CONST
)
3941 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3942 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3947 gcc_assert (can_create_pseudo_p ());
3948 reg
= gen_reg_rtx (Pmode
);
3951 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3952 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3953 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3954 base
== reg
? NULL_RTX
: reg
);
3956 if (GET_CODE (offset
) == CONST_INT
)
3958 if (SMALL_INT (offset
))
3959 return plus_constant (Pmode
, base
, INTVAL (offset
));
3960 else if (can_create_pseudo_p ())
3961 offset
= force_reg (Pmode
, offset
);
3963 /* If we reach here, then something is seriously wrong. */
3966 return gen_rtx_PLUS (Pmode
, base
, offset
);
3968 else if (GET_CODE (orig
) == LABEL_REF
)
3969 /* ??? We ought to be checking that the register is live instead, in case
3970 it is eliminated. */
3971 crtl
->uses_pic_offset_table
= 1;
3976 /* Try machine-dependent ways of modifying an illegitimate address X
3977 to be legitimate. If we find one, return the new, valid address.
3979 OLDX is the address as it was before break_out_memory_refs was called.
3980 In some cases it is useful to look at this to decide what needs to be done.
3982 MODE is the mode of the operand pointed to by X.
3984 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3987 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3988 enum machine_mode mode
)
3992 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3993 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3994 force_operand (XEXP (x
, 0), NULL_RTX
));
3995 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3996 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3997 force_operand (XEXP (x
, 1), NULL_RTX
));
3998 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3999 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4001 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4002 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4003 force_operand (XEXP (x
, 1), NULL_RTX
));
4005 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4008 if (sparc_tls_referenced_p (x
))
4009 x
= sparc_legitimize_tls_address (x
);
4011 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4012 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4013 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4014 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4015 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4016 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4017 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4018 else if (GET_CODE (x
) == SYMBOL_REF
4019 || GET_CODE (x
) == CONST
4020 || GET_CODE (x
) == LABEL_REF
)
4021 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4026 /* Delegitimize an address that was legitimized by the above function. */
4029 sparc_delegitimize_address (rtx x
)
4031 x
= delegitimize_mem_from_attrs (x
);
4033 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4034 switch (XINT (XEXP (x
, 1), 1))
4036 case UNSPEC_MOVE_PIC
:
4038 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4039 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4045 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4046 if (GET_CODE (x
) == MINUS
4047 && REG_P (XEXP (x
, 0))
4048 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4049 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4050 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4051 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4053 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4054 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4060 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4061 replace the input X, or the original X if no replacement is called for.
4062 The output parameter *WIN is 1 if the calling macro should goto WIN,
4065 For SPARC, we wish to handle addresses by splitting them into
4066 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4067 This cuts the number of extra insns by one.
4069 Do nothing when generating PIC code and the address is a symbolic
4070 operand or requires a scratch register. */
4073 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
4074 int opnum
, int type
,
4075 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4077 /* Decompose SImode constants into HIGH+LO_SUM. */
4079 && (mode
!= TFmode
|| TARGET_ARCH64
)
4080 && GET_MODE (x
) == SImode
4081 && GET_CODE (x
) != LO_SUM
4082 && GET_CODE (x
) != HIGH
4083 && sparc_cmodel
<= CM_MEDLOW
4085 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4087 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4088 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4089 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4090 opnum
, (enum reload_type
)type
);
4095 /* We have to recognize what we have already generated above. */
4096 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4098 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4099 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4100 opnum
, (enum reload_type
)type
);
4109 /* Return true if ADDR (a legitimate address expression)
4110 has an effect that depends on the machine mode it is used for.
4116 is not equivalent to
4118 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4120 because [%l7+a+1] is interpreted as the address of (a+1). */
4124 sparc_mode_dependent_address_p (const_rtx addr
,
4125 addr_space_t as ATTRIBUTE_UNUSED
)
4127 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4129 rtx op0
= XEXP (addr
, 0);
4130 rtx op1
= XEXP (addr
, 1);
4131 if (op0
== pic_offset_table_rtx
4132 && symbolic_operand (op1
, VOIDmode
))
4139 #ifdef HAVE_GAS_HIDDEN
4140 # define USE_HIDDEN_LINKONCE 1
4142 # define USE_HIDDEN_LINKONCE 0
4146 get_pc_thunk_name (char name
[32], unsigned int regno
)
4148 const char *reg_name
= reg_names
[regno
];
4150 /* Skip the leading '%' as that cannot be used in a
4154 if (USE_HIDDEN_LINKONCE
)
4155 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4157 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4160 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4163 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4165 int orig_flag_pic
= flag_pic
;
4168 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4171 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4173 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4174 flag_pic
= orig_flag_pic
;
4179 /* Emit code to load the GOT register. */
4182 load_got_register (void)
4184 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4185 if (!global_offset_table_rtx
)
4186 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4188 if (TARGET_VXWORKS_RTP
)
4189 emit_insn (gen_vxworks_load_got ());
4192 /* The GOT symbol is subject to a PC-relative relocation so we need a
4193 helper function to add the PC value and thus get the final value. */
4194 if (!got_helper_rtx
)
4197 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4198 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4201 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4203 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4206 /* Need to emit this whether or not we obey regdecls,
4207 since setjmp/longjmp can cause life info to screw up.
4208 ??? In the case where we don't obey regdecls, this is not sufficient
4209 since we may not fall out the bottom. */
4210 emit_use (global_offset_table_rtx
);
4213 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4214 address of the call target. */
4217 sparc_emit_call_insn (rtx pat
, rtx addr
)
4221 insn
= emit_call_insn (pat
);
4223 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4224 if (TARGET_VXWORKS_RTP
4226 && GET_CODE (addr
) == SYMBOL_REF
4227 && (SYMBOL_REF_DECL (addr
)
4228 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4229 : !SYMBOL_REF_LOCAL_P (addr
)))
4231 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4232 crtl
->uses_pic_offset_table
= 1;
4236 /* Return 1 if RTX is a MEM which is known to be aligned to at
4237 least a DESIRED byte boundary. */
4240 mem_min_alignment (rtx mem
, int desired
)
4242 rtx addr
, base
, offset
;
4244 /* If it's not a MEM we can't accept it. */
4245 if (GET_CODE (mem
) != MEM
)
4249 if (!TARGET_UNALIGNED_DOUBLES
4250 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4253 /* ??? The rest of the function predates MEM_ALIGN so
4254 there is probably a bit of redundancy. */
4255 addr
= XEXP (mem
, 0);
4256 base
= offset
= NULL_RTX
;
4257 if (GET_CODE (addr
) == PLUS
)
4259 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4261 base
= XEXP (addr
, 0);
4263 /* What we are saying here is that if the base
4264 REG is aligned properly, the compiler will make
4265 sure any REG based index upon it will be so
4267 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4268 offset
= XEXP (addr
, 1);
4270 offset
= const0_rtx
;
4273 else if (GET_CODE (addr
) == REG
)
4276 offset
= const0_rtx
;
4279 if (base
!= NULL_RTX
)
4281 int regno
= REGNO (base
);
4283 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4285 /* Check if the compiler has recorded some information
4286 about the alignment of the base REG. If reload has
4287 completed, we already matched with proper alignments.
4288 If not running global_alloc, reload might give us
4289 unaligned pointer to local stack though. */
4291 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4292 || (optimize
&& reload_completed
))
4293 && (INTVAL (offset
) & (desired
- 1)) == 0)
4298 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4302 else if (! TARGET_UNALIGNED_DOUBLES
4303 || CONSTANT_P (addr
)
4304 || GET_CODE (addr
) == LO_SUM
)
4306 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4307 is true, in which case we can only assume that an access is aligned if
4308 it is to a constant address, or the address involves a LO_SUM. */
4312 /* An obviously unaligned address. */
4317 /* Vectors to keep interesting information about registers where it can easily
4318 be got. We used to use the actual mode value as the bit number, but there
4319 are more than 32 modes now. Instead we use two tables: one indexed by
4320 hard register number, and one indexed by mode. */
4322 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4323 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4324 mapped into one sparc_mode_class mode. */
4326 enum sparc_mode_class
{
4327 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4328 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4332 /* Modes for single-word and smaller quantities. */
4333 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4335 /* Modes for double-word and smaller quantities. */
4336 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4338 /* Modes for quad-word and smaller quantities. */
4339 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4341 /* Modes for 8-word and smaller quantities. */
4342 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4344 /* Modes for single-float quantities. We must allow any single word or
4345 smaller quantity. This is because the fix/float conversion instructions
4346 take integer inputs/outputs from the float registers. */
4347 #define SF_MODES (S_MODES)
4349 /* Modes for double-float and smaller quantities. */
4350 #define DF_MODES (D_MODES)
4352 /* Modes for quad-float and smaller quantities. */
4353 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4355 /* Modes for quad-float pairs and smaller quantities. */
4356 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4358 /* Modes for double-float only quantities. */
4359 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4361 /* Modes for quad-float and double-float only quantities. */
4362 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4364 /* Modes for quad-float pairs and double-float only quantities. */
4365 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4367 /* Modes for condition codes. */
4368 #define CC_MODES (1 << (int) CC_MODE)
4369 #define CCFP_MODES (1 << (int) CCFP_MODE)
4371 /* Value is 1 if register/mode pair is acceptable on sparc.
4372 The funny mixture of D and T modes is because integer operations
4373 do not specially operate on tetra quantities, so non-quad-aligned
4374 registers can hold quadword quantities (except %o4 and %i4 because
4375 they cross fixed registers). */
4377 /* This points to either the 32 bit or the 64 bit version. */
4378 const int *hard_regno_mode_classes
;
4380 static const int hard_32bit_mode_classes
[] = {
4381 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4382 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4383 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4384 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4386 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4387 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4388 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4389 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4391 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4392 and none can hold SFmode/SImode values. */
4393 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4394 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4395 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4396 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4399 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4401 /* %icc, %sfp, %gsr */
4402 CC_MODES
, 0, D_MODES
4405 static const int hard_64bit_mode_classes
[] = {
4406 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4407 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4408 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4409 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4411 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4412 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4413 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4414 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4416 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4417 and none can hold SFmode/SImode values. */
4418 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4419 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4420 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4421 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4424 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4426 /* %icc, %sfp, %gsr */
4427 CC_MODES
, 0, D_MODES
4430 int sparc_mode_class
[NUM_MACHINE_MODES
];
4432 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4435 sparc_init_modes (void)
4439 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4441 switch (GET_MODE_CLASS (i
))
4444 case MODE_PARTIAL_INT
:
4445 case MODE_COMPLEX_INT
:
4446 if (GET_MODE_SIZE (i
) <= 4)
4447 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4448 else if (GET_MODE_SIZE (i
) == 8)
4449 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4450 else if (GET_MODE_SIZE (i
) == 16)
4451 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4452 else if (GET_MODE_SIZE (i
) == 32)
4453 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4455 sparc_mode_class
[i
] = 0;
4457 case MODE_VECTOR_INT
:
4458 if (GET_MODE_SIZE (i
) <= 4)
4459 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4460 else if (GET_MODE_SIZE (i
) == 8)
4461 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4464 case MODE_COMPLEX_FLOAT
:
4465 if (GET_MODE_SIZE (i
) <= 4)
4466 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4467 else if (GET_MODE_SIZE (i
) == 8)
4468 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4469 else if (GET_MODE_SIZE (i
) == 16)
4470 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4471 else if (GET_MODE_SIZE (i
) == 32)
4472 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4474 sparc_mode_class
[i
] = 0;
4477 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4478 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4480 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4483 sparc_mode_class
[i
] = 0;
4489 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4491 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4493 /* Initialize the array used by REGNO_REG_CLASS. */
4494 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4496 if (i
< 16 && TARGET_V8PLUS
)
4497 sparc_regno_reg_class
[i
] = I64_REGS
;
4498 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4499 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4501 sparc_regno_reg_class
[i
] = FP_REGS
;
4503 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4505 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4507 sparc_regno_reg_class
[i
] = NO_REGS
;
4511 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4514 save_global_or_fp_reg_p (unsigned int regno
,
4515 int leaf_function ATTRIBUTE_UNUSED
)
4517 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4520 /* Return whether the return address register (%i7) is needed. */
4523 return_addr_reg_needed_p (int leaf_function
)
4525 /* If it is live, for example because of __builtin_return_address (0). */
4526 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4529 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4531 /* Loading the GOT register clobbers %o7. */
4532 || crtl
->uses_pic_offset_table
4533 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4539 /* Return whether REGNO, a local or in register, must be saved/restored. */
4542 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4544 /* General case: call-saved registers live at some point. */
4545 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4548 /* Frame pointer register (%fp) if needed. */
4549 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4552 /* Return address register (%i7) if needed. */
4553 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4556 /* GOT register (%l7) if needed. */
4557 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4560 /* If the function accesses prior frames, the frame pointer and the return
4561 address of the previous frame must be saved on the stack. */
4562 if (crtl
->accesses_prior_frames
4563 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4569 /* Compute the frame size required by the function. This function is called
4570 during the reload pass and also by sparc_expand_prologue. */
4573 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4575 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4576 int args_size
, n_global_fp_regs
= 0;
4577 bool save_local_in_regs_p
= false;
4580 /* If the function allocates dynamic stack space, the dynamic offset is
4581 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4582 if (leaf_function
&& !cfun
->calls_alloca
)
4585 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4587 /* Calculate space needed for global registers. */
4589 for (i
= 0; i
< 8; i
++)
4590 if (save_global_or_fp_reg_p (i
, 0))
4591 n_global_fp_regs
+= 2;
4593 for (i
= 0; i
< 8; i
+= 2)
4594 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4595 n_global_fp_regs
+= 2;
4597 /* In the flat window model, find out which local and in registers need to
4598 be saved. We don't reserve space in the current frame for them as they
4599 will be spilled into the register window save area of the caller's frame.
4600 However, as soon as we use this register window save area, we must create
4601 that of the current frame to make it the live one. */
4603 for (i
= 16; i
< 32; i
++)
4604 if (save_local_or_in_reg_p (i
, leaf_function
))
4606 save_local_in_regs_p
= true;
4610 /* Calculate space needed for FP registers. */
4611 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4612 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4613 n_global_fp_regs
+= 2;
4616 && n_global_fp_regs
== 0
4618 && !save_local_in_regs_p
)
4619 frame_size
= apparent_frame_size
= 0;
4622 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4623 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4624 apparent_frame_size
+= n_global_fp_regs
* 4;
4626 /* We need to add the size of the outgoing argument area. */
4627 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4629 /* And that of the register window save area. */
4630 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4632 /* Finally, bump to the appropriate alignment. */
4633 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4636 /* Set up values for use in prologue and epilogue. */
4637 sparc_frame_size
= frame_size
;
4638 sparc_apparent_frame_size
= apparent_frame_size
;
4639 sparc_n_global_fp_regs
= n_global_fp_regs
;
4640 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4645 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
4648 sparc_initial_elimination_offset (int to
)
4652 if (to
== STACK_POINTER_REGNUM
)
4653 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
4657 offset
+= SPARC_STACK_BIAS
;
4661 /* Output any necessary .register pseudo-ops. */
4664 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4666 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4672 /* Check if %g[2367] were used without
4673 .register being printed for them already. */
4674 for (i
= 2; i
< 8; i
++)
4676 if (df_regs_ever_live_p (i
)
4677 && ! sparc_hard_reg_printed
[i
])
4679 sparc_hard_reg_printed
[i
] = 1;
4680 /* %g7 is used as TLS base register, use #ignore
4681 for it instead of #scratch. */
4682 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4683 i
== 7 ? "ignore" : "scratch");
4690 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4692 #if PROBE_INTERVAL > 4096
4693 #error Cannot use indexed addressing mode for stack probing
4696 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4697 inclusive. These are offsets from the current stack pointer.
4699 Note that we don't use the REG+REG addressing mode for the probes because
4700 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4701 so the advantages of having a single code win here. */
4704 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4706 rtx g1
= gen_rtx_REG (Pmode
, 1);
4708 /* See if we have a constant small number of probes to generate. If so,
4709 that's the easy case. */
4710 if (size
<= PROBE_INTERVAL
)
4712 emit_move_insn (g1
, GEN_INT (first
));
4713 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4714 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4715 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
4718 /* The run-time loop is made up of 10 insns in the generic case while the
4719 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4720 else if (size
<= 5 * PROBE_INTERVAL
)
4724 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4725 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4726 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4727 emit_stack_probe (g1
);
4729 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4730 it exceeds SIZE. If only two probes are needed, this will not
4731 generate any code. Then probe at FIRST + SIZE. */
4732 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4734 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4735 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
4736 emit_stack_probe (g1
);
4739 emit_stack_probe (plus_constant (Pmode
, g1
,
4740 (i
- PROBE_INTERVAL
) - size
));
4743 /* Otherwise, do the same as above, but in a loop. Note that we must be
4744 extra careful with variables wrapping around because we might be at
4745 the very top (or the very bottom) of the address space and we have
4746 to be able to handle this case properly; in particular, we use an
4747 equality test for the loop condition. */
4750 HOST_WIDE_INT rounded_size
;
4751 rtx g4
= gen_rtx_REG (Pmode
, 4);
4753 emit_move_insn (g1
, GEN_INT (first
));
4756 /* Step 1: round SIZE to the previous multiple of the interval. */
4758 rounded_size
= size
& -PROBE_INTERVAL
;
4759 emit_move_insn (g4
, GEN_INT (rounded_size
));
4762 /* Step 2: compute initial and final value of the loop counter. */
4764 /* TEST_ADDR = SP + FIRST. */
4765 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4766 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4768 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4769 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4774 while (TEST_ADDR != LAST_ADDR)
4776 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4780 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4781 until it is equal to ROUNDED_SIZE. */
4784 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4786 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4789 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4790 that SIZE is equal to ROUNDED_SIZE. */
4792 if (size
!= rounded_size
)
4793 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
4796 /* Make sure nothing is scheduled before we are done. */
4797 emit_insn (gen_blockage ());
4800 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4801 absolute addresses. */
4804 output_probe_stack_range (rtx reg1
, rtx reg2
)
4806 static int labelno
= 0;
4807 char loop_lab
[32], end_lab
[32];
4810 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4811 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4813 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4815 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4818 output_asm_insn ("cmp\t%0, %1", xops
);
4820 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4822 fputs ("\tbe\t", asm_out_file
);
4823 assemble_name_raw (asm_out_file
, end_lab
);
4824 fputc ('\n', asm_out_file
);
4826 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4827 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4828 output_asm_insn (" add\t%0, %1, %0", xops
);
4830 /* Probe at TEST_ADDR and branch. */
4832 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4834 fputs ("\tba\t", asm_out_file
);
4835 assemble_name_raw (asm_out_file
, loop_lab
);
4836 fputc ('\n', asm_out_file
);
4837 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4838 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4840 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4845 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4846 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4847 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4848 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4849 the action to be performed if it returns false. Return the new offset. */
4851 typedef bool (*sorr_pred_t
) (unsigned int, int);
4852 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4855 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4856 int offset
, int leaf_function
, sorr_pred_t save_p
,
4857 sorr_act_t action_true
, sorr_act_t action_false
)
4862 if (TARGET_ARCH64
&& high
<= 32)
4866 for (i
= low
; i
< high
; i
++)
4868 if (save_p (i
, leaf_function
))
4870 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
4872 if (action_true
== SORR_SAVE
)
4874 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4875 RTX_FRAME_RELATED_P (insn
) = 1;
4877 else /* action_true == SORR_RESTORE */
4879 /* The frame pointer must be restored last since its old
4880 value may be used as base address for the frame. This
4881 is problematic in 64-bit mode only because of the lack
4882 of double-word load instruction. */
4883 if (i
== HARD_FRAME_POINTER_REGNUM
)
4886 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4890 else if (action_false
== SORR_ADVANCE
)
4896 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
4897 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4902 for (i
= low
; i
< high
; i
+= 2)
4904 bool reg0
= save_p (i
, leaf_function
);
4905 bool reg1
= save_p (i
+ 1, leaf_function
);
4906 enum machine_mode mode
;
4911 mode
= SPARC_INT_REG_P (i
) ? DImode
: DFmode
;
4916 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
4921 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
4927 if (action_false
== SORR_ADVANCE
)
4932 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
4933 if (action_true
== SORR_SAVE
)
4935 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4936 RTX_FRAME_RELATED_P (insn
) = 1;
4940 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
4942 set1
= gen_rtx_SET (VOIDmode
, mem
,
4943 gen_rtx_REG (SImode
, regno
));
4944 RTX_FRAME_RELATED_P (set1
) = 1;
4946 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
4948 set2
= gen_rtx_SET (VOIDmode
, mem
,
4949 gen_rtx_REG (SImode
, regno
+ 1));
4950 RTX_FRAME_RELATED_P (set2
) = 1;
4951 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4952 gen_rtx_PARALLEL (VOIDmode
,
4953 gen_rtvec (2, set1
, set2
)));
4956 else /* action_true == SORR_RESTORE */
4957 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4959 /* Always preserve double-word alignment. */
4960 offset
= (offset
+ 8) & -8;
4967 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4970 emit_adjust_base_to_offset (rtx base
, int offset
)
4972 /* ??? This might be optimized a little as %g1 might already have a
4973 value close enough that a single add insn will do. */
4974 /* ??? Although, all of this is probably only a temporary fix because
4975 if %g1 can hold a function result, then sparc_expand_epilogue will
4976 lose (the result will be clobbered). */
4977 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4978 emit_move_insn (new_base
, GEN_INT (offset
));
4979 emit_insn (gen_rtx_SET (VOIDmode
,
4980 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4984 /* Emit code to save/restore call-saved global and FP registers. */
4987 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4989 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4991 base
= emit_adjust_base_to_offset (base
, offset
);
4996 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4997 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4998 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4999 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5002 /* Emit code to save/restore call-saved local and in registers. */
5005 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5007 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5009 base
= emit_adjust_base_to_offset (base
, offset
);
5013 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5014 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5017 /* Emit a window_save insn. */
5020 emit_window_save (rtx increment
)
5022 rtx insn
= emit_insn (gen_window_save (increment
));
5023 RTX_FRAME_RELATED_P (insn
) = 1;
5025 /* The incoming return address (%o7) is saved in %i7. */
5026 add_reg_note (insn
, REG_CFA_REGISTER
,
5027 gen_rtx_SET (VOIDmode
,
5028 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5030 INCOMING_RETURN_ADDR_REGNUM
)));
5032 /* The window save event. */
5033 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5035 /* The CFA is %fp, the hard frame pointer. */
5036 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5037 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5038 INCOMING_FRAME_SP_OFFSET
));
5043 /* Generate an increment for the stack pointer. */
5046 gen_stack_pointer_inc (rtx increment
)
5048 return gen_rtx_SET (VOIDmode
,
5050 gen_rtx_PLUS (Pmode
,
5055 /* Expand the function prologue. The prologue is responsible for reserving
5056 storage for the frame, saving the call-saved registers and loading the
5057 GOT register if needed. */
5060 sparc_expand_prologue (void)
5065 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5066 on the final value of the flag means deferring the prologue/epilogue
5067 expansion until just before the second scheduling pass, which is too
5068 late to emit multiple epilogues or return insns.
5070 Of course we are making the assumption that the value of the flag
5071 will not change between now and its final value. Of the three parts
5072 of the formula, only the last one can reasonably vary. Let's take a
5073 closer look, after assuming that the first two ones are set to true
5074 (otherwise the last value is effectively silenced).
5076 If only_leaf_regs_used returns false, the global predicate will also
5077 be false so the actual frame size calculated below will be positive.
5078 As a consequence, the save_register_window insn will be emitted in
5079 the instruction stream; now this insn explicitly references %fp
5080 which is not a leaf register so only_leaf_regs_used will always
5081 return false subsequently.
5083 If only_leaf_regs_used returns true, we hope that the subsequent
5084 optimization passes won't cause non-leaf registers to pop up. For
5085 example, the regrename pass has special provisions to not rename to
5086 non-leaf registers in a leaf function. */
5087 sparc_leaf_function_p
5088 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5090 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5092 if (flag_stack_usage_info
)
5093 current_function_static_stack_size
= size
;
5095 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
5096 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5100 else if (sparc_leaf_function_p
)
5102 rtx size_int_rtx
= GEN_INT (-size
);
5105 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5106 else if (size
<= 8192)
5108 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5109 RTX_FRAME_RELATED_P (insn
) = 1;
5111 /* %sp is still the CFA register. */
5112 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5116 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5117 emit_move_insn (size_rtx
, size_int_rtx
);
5118 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5119 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5120 gen_stack_pointer_inc (size_int_rtx
));
5123 RTX_FRAME_RELATED_P (insn
) = 1;
5127 rtx size_int_rtx
= GEN_INT (-size
);
5130 emit_window_save (size_int_rtx
);
5131 else if (size
<= 8192)
5133 emit_window_save (GEN_INT (-4096));
5135 /* %sp is not the CFA register anymore. */
5136 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5138 /* Make sure no %fp-based store is issued until after the frame is
5139 established. The offset between the frame pointer and the stack
5140 pointer is calculated relative to the value of the stack pointer
5141 at the end of the function prologue, and moving instructions that
5142 access the stack via the frame pointer between the instructions
5143 that decrement the stack pointer could result in accessing the
5144 register window save area, which is volatile. */
5145 emit_insn (gen_frame_blockage ());
5149 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5150 emit_move_insn (size_rtx
, size_int_rtx
);
5151 emit_window_save (size_rtx
);
5155 if (sparc_leaf_function_p
)
5157 sparc_frame_base_reg
= stack_pointer_rtx
;
5158 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5162 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5163 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5166 if (sparc_n_global_fp_regs
> 0)
5167 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5168 sparc_frame_base_offset
5169 - sparc_apparent_frame_size
,
5172 /* Load the GOT register if needed. */
5173 if (crtl
->uses_pic_offset_table
)
5174 load_got_register ();
5176 /* Advertise that the data calculated just above are now valid. */
5177 sparc_prologue_data_valid_p
= true;
5180 /* Expand the function prologue. The prologue is responsible for reserving
5181 storage for the frame, saving the call-saved registers and loading the
5182 GOT register if needed. */
5185 sparc_flat_expand_prologue (void)
5190 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5192 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5194 if (flag_stack_usage_info
)
5195 current_function_static_stack_size
= size
;
5197 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
5198 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5200 if (sparc_save_local_in_regs_p
)
5201 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5208 rtx size_int_rtx
, size_rtx
;
5210 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5212 /* We establish the frame (i.e. decrement the stack pointer) first, even
5213 if we use a frame pointer, because we cannot clobber any call-saved
5214 registers, including the frame pointer, if we haven't created a new
5215 register save area, for the sake of compatibility with the ABI. */
5217 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5218 else if (size
<= 8192 && !frame_pointer_needed
)
5220 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5221 RTX_FRAME_RELATED_P (insn
) = 1;
5222 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5226 size_rtx
= gen_rtx_REG (Pmode
, 1);
5227 emit_move_insn (size_rtx
, size_int_rtx
);
5228 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5229 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5230 gen_stack_pointer_inc (size_int_rtx
));
5232 RTX_FRAME_RELATED_P (insn
) = 1;
5234 /* Ensure nothing is scheduled until after the frame is established. */
5235 emit_insn (gen_blockage ());
5237 if (frame_pointer_needed
)
5239 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5240 gen_rtx_MINUS (Pmode
,
5243 RTX_FRAME_RELATED_P (insn
) = 1;
5245 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5246 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5247 plus_constant (Pmode
, stack_pointer_rtx
,
5251 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5253 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5254 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5256 insn
= emit_move_insn (i7
, o7
);
5257 RTX_FRAME_RELATED_P (insn
) = 1;
5259 add_reg_note (insn
, REG_CFA_REGISTER
,
5260 gen_rtx_SET (VOIDmode
, i7
, o7
));
5262 /* Prevent this instruction from ever being considered dead,
5263 even if this function has no epilogue. */
5268 if (frame_pointer_needed
)
5270 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5271 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5275 sparc_frame_base_reg
= stack_pointer_rtx
;
5276 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5279 if (sparc_n_global_fp_regs
> 0)
5280 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5281 sparc_frame_base_offset
5282 - sparc_apparent_frame_size
,
5285 /* Load the GOT register if needed. */
5286 if (crtl
->uses_pic_offset_table
)
5287 load_got_register ();
5289 /* Advertise that the data calculated just above are now valid. */
5290 sparc_prologue_data_valid_p
= true;
5293 /* This function generates the assembly code for function entry, which boils
5294 down to emitting the necessary .register directives. */
5297 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5299 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5301 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5303 sparc_output_scratch_registers (file
);
5306 /* Expand the function epilogue, either normal or part of a sibcall.
5307 We emit all the instructions except the return or the call. */
5310 sparc_expand_epilogue (bool for_eh
)
5312 HOST_WIDE_INT size
= sparc_frame_size
;
5314 if (sparc_n_global_fp_regs
> 0)
5315 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5316 sparc_frame_base_offset
5317 - sparc_apparent_frame_size
,
5320 if (size
== 0 || for_eh
)
5322 else if (sparc_leaf_function_p
)
5325 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5326 else if (size
<= 8192)
5328 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5329 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5333 rtx reg
= gen_rtx_REG (Pmode
, 1);
5334 emit_move_insn (reg
, GEN_INT (size
));
5335 emit_insn (gen_stack_pointer_inc (reg
));
5340 /* Expand the function epilogue, either normal or part of a sibcall.
5341 We emit all the instructions except the return or the call. */
5344 sparc_flat_expand_epilogue (bool for_eh
)
5346 HOST_WIDE_INT size
= sparc_frame_size
;
5348 if (sparc_n_global_fp_regs
> 0)
5349 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5350 sparc_frame_base_offset
5351 - sparc_apparent_frame_size
,
5354 /* If we have a frame pointer, we'll need both to restore it before the
5355 frame is destroyed and use its current value in destroying the frame.
5356 Since we don't have an atomic way to do that in the flat window model,
5357 we save the current value into a temporary register (%g1). */
5358 if (frame_pointer_needed
&& !for_eh
)
5359 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5361 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5362 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5363 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5365 if (sparc_save_local_in_regs_p
)
5366 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5367 sparc_frame_base_offset
,
5370 if (size
== 0 || for_eh
)
5372 else if (frame_pointer_needed
)
5374 /* Make sure the frame is destroyed after everything else is done. */
5375 emit_insn (gen_blockage ());
5377 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5382 emit_insn (gen_blockage ());
5385 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5386 else if (size
<= 8192)
5388 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5389 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5393 rtx reg
= gen_rtx_REG (Pmode
, 1);
5394 emit_move_insn (reg
, GEN_INT (size
));
5395 emit_insn (gen_stack_pointer_inc (reg
));
5400 /* Return true if it is appropriate to emit `return' instructions in the
5401 body of a function. */
5404 sparc_can_use_return_insn_p (void)
5406 return sparc_prologue_data_valid_p
5407 && sparc_n_global_fp_regs
== 0
5409 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5410 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5413 /* This function generates the assembly code for function exit. */
5416 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5418 /* If the last two instructions of a function are "call foo; dslot;"
5419 the return address might point to the first instruction in the next
5420 function and we have to output a dummy nop for the sake of sane
5421 backtraces in such cases. This is pointless for sibling calls since
5422 the return address is explicitly adjusted. */
5424 rtx insn
, last_real_insn
;
5426 insn
= get_last_insn ();
5428 last_real_insn
= prev_real_insn (insn
);
5430 && GET_CODE (last_real_insn
) == INSN
5431 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5432 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5435 && CALL_P (last_real_insn
)
5436 && !SIBLING_CALL_P (last_real_insn
))
5437 fputs("\tnop\n", file
);
5439 sparc_output_deferred_case_vectors ();
5442 /* Output a 'restore' instruction. */
5445 output_restore (rtx pat
)
5451 fputs ("\t restore\n", asm_out_file
);
5455 gcc_assert (GET_CODE (pat
) == SET
);
5457 operands
[0] = SET_DEST (pat
);
5458 pat
= SET_SRC (pat
);
5460 switch (GET_CODE (pat
))
5463 operands
[1] = XEXP (pat
, 0);
5464 operands
[2] = XEXP (pat
, 1);
5465 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5468 operands
[1] = XEXP (pat
, 0);
5469 operands
[2] = XEXP (pat
, 1);
5470 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5473 operands
[1] = XEXP (pat
, 0);
5474 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5475 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5479 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5484 /* Output a return. */
5487 output_return (rtx insn
)
5489 if (crtl
->calls_eh_return
)
5491 /* If the function uses __builtin_eh_return, the eh_return
5492 machinery occupies the delay slot. */
5493 gcc_assert (!final_sequence
);
5495 if (flag_delayed_branch
)
5497 if (!TARGET_FLAT
&& TARGET_V9
)
5498 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5502 fputs ("\trestore\n", asm_out_file
);
5504 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5507 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5512 fputs ("\trestore\n", asm_out_file
);
5514 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5515 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5518 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5520 /* This is a leaf or flat function so we don't have to bother restoring
5521 the register window, which frees us from dealing with the convoluted
5522 semantics of restore/return. We simply output the jump to the
5523 return address and the insn in the delay slot (if any). */
5525 return "jmp\t%%o7+%)%#";
5529 /* This is a regular function so we have to restore the register window.
5530 We may have a pending insn for the delay slot, which will be either
5531 combined with the 'restore' instruction or put in the delay slot of
5532 the 'return' instruction. */
5538 delay
= NEXT_INSN (insn
);
5541 pat
= PATTERN (delay
);
5543 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5545 epilogue_renumber (&pat
, 0);
5546 return "return\t%%i7+%)%#";
5550 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5551 output_restore (pat
);
5552 PATTERN (delay
) = gen_blockage ();
5553 INSN_CODE (delay
) = -1;
5558 /* The delay slot is empty. */
5560 return "return\t%%i7+%)\n\t nop";
5561 else if (flag_delayed_branch
)
5562 return "jmp\t%%i7+%)\n\t restore";
5564 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5571 /* Output a sibling call. */
5574 output_sibcall (rtx insn
, rtx call_operand
)
5578 gcc_assert (flag_delayed_branch
);
5580 operands
[0] = call_operand
;
5582 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5584 /* This is a leaf or flat function so we don't have to bother restoring
5585 the register window. We simply output the jump to the function and
5586 the insn in the delay slot (if any). */
5588 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5591 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5594 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5595 it into branch if possible. */
5596 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5601 /* This is a regular function so we have to restore the register window.
5602 We may have a pending insn for the delay slot, which will be combined
5603 with the 'restore' instruction. */
5605 output_asm_insn ("call\t%a0, 0", operands
);
5609 rtx delay
= NEXT_INSN (insn
);
5612 output_restore (PATTERN (delay
));
5614 PATTERN (delay
) = gen_blockage ();
5615 INSN_CODE (delay
) = -1;
5618 output_restore (NULL_RTX
);
5624 /* Functions for handling argument passing.
5626 For 32-bit, the first 6 args are normally in registers and the rest are
5627 pushed. Any arg that starts within the first 6 words is at least
5628 partially passed in a register unless its data type forbids.
5630 For 64-bit, the argument registers are laid out as an array of 16 elements
5631 and arguments are added sequentially. The first 6 int args and up to the
5632 first 16 fp args (depending on size) are passed in regs.
5634 Slot Stack Integral Float Float in structure Double Long Double
5635 ---- ----- -------- ----- ------------------ ------ -----------
5636 15 [SP+248] %f31 %f30,%f31 %d30
5637 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5638 13 [SP+232] %f27 %f26,%f27 %d26
5639 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5640 11 [SP+216] %f23 %f22,%f23 %d22
5641 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5642 9 [SP+200] %f19 %f18,%f19 %d18
5643 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5644 7 [SP+184] %f15 %f14,%f15 %d14
5645 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5646 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5647 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5648 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5649 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5650 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5651 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5653 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5655 Integral arguments are always passed as 64-bit quantities appropriately
5658 Passing of floating point values is handled as follows.
5659 If a prototype is in scope:
5660 If the value is in a named argument (i.e. not a stdarg function or a
5661 value not part of the `...') then the value is passed in the appropriate
5663 If the value is part of the `...' and is passed in one of the first 6
5664 slots then the value is passed in the appropriate int reg.
5665 If the value is part of the `...' and is not passed in one of the first 6
5666 slots then the value is passed in memory.
5667 If a prototype is not in scope:
5668 If the value is one of the first 6 arguments the value is passed in the
5669 appropriate integer reg and the appropriate fp reg.
5670 If the value is not one of the first 6 arguments the value is passed in
5671 the appropriate fp reg and in memory.
5674 Summary of the calling conventions implemented by GCC on the SPARC:
5677 size argument return value
5679 small integer <4 int. reg. int. reg.
5680 word 4 int. reg. int. reg.
5681 double word 8 int. reg. int. reg.
5683 _Complex small integer <8 int. reg. int. reg.
5684 _Complex word 8 int. reg. int. reg.
5685 _Complex double word 16 memory int. reg.
5687 vector integer <=8 int. reg. FP reg.
5688 vector integer >8 memory memory
5690 float 4 int. reg. FP reg.
5691 double 8 int. reg. FP reg.
5692 long double 16 memory memory
5694 _Complex float 8 memory FP reg.
5695 _Complex double 16 memory FP reg.
5696 _Complex long double 32 memory FP reg.
5698 vector float any memory memory
5700 aggregate any memory memory
5705 size argument return value
5707 small integer <8 int. reg. int. reg.
5708 word 8 int. reg. int. reg.
5709 double word 16 int. reg. int. reg.
5711 _Complex small integer <16 int. reg. int. reg.
5712 _Complex word 16 int. reg. int. reg.
5713 _Complex double word 32 memory int. reg.
5715 vector integer <=16 FP reg. FP reg.
5716 vector integer 16<s<=32 memory FP reg.
5717 vector integer >32 memory memory
5719 float 4 FP reg. FP reg.
5720 double 8 FP reg. FP reg.
5721 long double 16 FP reg. FP reg.
5723 _Complex float 8 FP reg. FP reg.
5724 _Complex double 16 FP reg. FP reg.
5725 _Complex long double 32 memory FP reg.
5727 vector float <=16 FP reg. FP reg.
5728 vector float 16<s<=32 memory FP reg.
5729 vector float >32 memory memory
5731 aggregate <=16 reg. reg.
5732 aggregate 16<s<=32 memory reg.
5733 aggregate >32 memory memory
5737 Note #1: complex floating-point types follow the extended SPARC ABIs as
5738 implemented by the Sun compiler.
5740 Note #2: integral vector types follow the scalar floating-point types
5741 conventions to match what is implemented by the Sun VIS SDK.
5743 Note #3: floating-point vector types follow the aggregate types
5747 /* Maximum number of int regs for args. */
5748 #define SPARC_INT_ARG_MAX 6
5749 /* Maximum number of fp regs for args. */
5750 #define SPARC_FP_ARG_MAX 16
5752 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5754 /* Handle the INIT_CUMULATIVE_ARGS macro.
5755 Initialize a variable CUM of type CUMULATIVE_ARGS
5756 for a call to a function whose data type is FNTYPE.
5757 For a library call, FNTYPE is 0. */
5760 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5761 rtx libname ATTRIBUTE_UNUSED
,
5762 tree fndecl ATTRIBUTE_UNUSED
)
5765 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5766 cum
->libcall_p
= fntype
== 0;
5769 /* Handle promotion of pointer and integer arguments. */
5771 static enum machine_mode
5772 sparc_promote_function_mode (const_tree type
,
5773 enum machine_mode mode
,
5775 const_tree fntype ATTRIBUTE_UNUSED
,
5776 int for_return ATTRIBUTE_UNUSED
)
5778 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5780 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5784 /* Integral arguments are passed as full words, as per the ABI. */
5785 if (GET_MODE_CLASS (mode
) == MODE_INT
5786 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5792 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5795 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5797 return TARGET_ARCH64
? true : false;
5800 /* Scan the record type TYPE and return the following predicates:
5801 - INTREGS_P: the record contains at least one field or sub-field
5802 that is eligible for promotion in integer registers.
5803 - FP_REGS_P: the record contains at least one field or sub-field
5804 that is eligible for promotion in floating-point registers.
5805 - PACKED_P: the record contains at least one field that is packed.
5807 Sub-fields are not taken into account for the PACKED_P predicate. */
5810 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5815 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5817 if (TREE_CODE (field
) == FIELD_DECL
)
5819 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5820 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5821 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5822 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5828 if (packed_p
&& DECL_PACKED (field
))
5834 /* Compute the slot number to pass an argument in.
5835 Return the slot number or -1 if passing on the stack.
5837 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5838 the preceding args and about the function being called.
5839 MODE is the argument's machine mode.
5840 TYPE is the data type of the argument (as a tree).
5841 This is null for libcalls where that information may
5843 NAMED is nonzero if this argument is a named parameter
5844 (otherwise it is an extra parameter matching an ellipsis).
5845 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5846 *PREGNO records the register number to use if scalar type.
5847 *PPADDING records the amount of padding needed in words. */
5850 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5851 const_tree type
, bool named
, bool incoming_p
,
5852 int *pregno
, int *ppadding
)
5854 int regbase
= (incoming_p
5855 ? SPARC_INCOMING_INT_ARG_FIRST
5856 : SPARC_OUTGOING_INT_ARG_FIRST
);
5857 int slotno
= cum
->words
;
5858 enum mode_class mclass
;
5863 if (type
&& TREE_ADDRESSABLE (type
))
5869 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5872 /* For SPARC64, objects requiring 16-byte alignment get it. */
5874 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5875 && (slotno
& 1) != 0)
5876 slotno
++, *ppadding
= 1;
5878 mclass
= GET_MODE_CLASS (mode
);
5879 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5881 /* Vector types deserve special treatment because they are
5882 polymorphic wrt their mode, depending upon whether VIS
5883 instructions are enabled. */
5884 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5886 /* The SPARC port defines no floating-point vector modes. */
5887 gcc_assert (mode
== BLKmode
);
5891 /* Integral vector types should either have a vector
5892 mode or an integral mode, because we are guaranteed
5893 by pass_by_reference that their size is not greater
5894 than 16 bytes and TImode is 16-byte wide. */
5895 gcc_assert (mode
!= BLKmode
);
5897 /* Vector integers are handled like floats according to
5899 mclass
= MODE_FLOAT
;
5906 case MODE_COMPLEX_FLOAT
:
5907 case MODE_VECTOR_INT
:
5908 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5910 if (slotno
>= SPARC_FP_ARG_MAX
)
5912 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5913 /* Arguments filling only one single FP register are
5914 right-justified in the outer double FP register. */
5915 if (GET_MODE_SIZE (mode
) <= 4)
5922 case MODE_COMPLEX_INT
:
5923 if (slotno
>= SPARC_INT_ARG_MAX
)
5925 regno
= regbase
+ slotno
;
5929 if (mode
== VOIDmode
)
5930 /* MODE is VOIDmode when generating the actual call. */
5933 gcc_assert (mode
== BLKmode
);
5937 || (TREE_CODE (type
) != VECTOR_TYPE
5938 && TREE_CODE (type
) != RECORD_TYPE
))
5940 if (slotno
>= SPARC_INT_ARG_MAX
)
5942 regno
= regbase
+ slotno
;
5944 else /* TARGET_ARCH64 && type */
5946 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5948 /* First see what kinds of registers we would need. */
5949 if (TREE_CODE (type
) == VECTOR_TYPE
)
5952 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5954 /* The ABI obviously doesn't specify how packed structures
5955 are passed. These are defined to be passed in int regs
5956 if possible, otherwise memory. */
5957 if (packed_p
|| !named
)
5958 fpregs_p
= 0, intregs_p
= 1;
5960 /* If all arg slots are filled, then must pass on stack. */
5961 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5964 /* If there are only int args and all int arg slots are filled,
5965 then must pass on stack. */
5966 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5969 /* Note that even if all int arg slots are filled, fp members may
5970 still be passed in regs if such regs are available.
5971 *PREGNO isn't set because there may be more than one, it's up
5972 to the caller to compute them. */
5985 /* Handle recursive register counting for structure field layout. */
5987 struct function_arg_record_value_parms
5989 rtx ret
; /* return expression being built. */
5990 int slotno
; /* slot number of the argument. */
5991 int named
; /* whether the argument is named. */
5992 int regbase
; /* regno of the base register. */
5993 int stack
; /* 1 if part of the argument is on the stack. */
5994 int intoffset
; /* offset of the first pending integer field. */
5995 unsigned int nregs
; /* number of words passed in registers. */
5998 static void function_arg_record_value_3
5999 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
6000 static void function_arg_record_value_2
6001 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6002 static void function_arg_record_value_1
6003 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6004 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
6005 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
6007 /* A subroutine of function_arg_record_value. Traverse the structure
6008 recursively and determine how many registers will be required. */
6011 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
6012 struct function_arg_record_value_parms
*parms
,
6017 /* We need to compute how many registers are needed so we can
6018 allocate the PARALLEL but before we can do that we need to know
6019 whether there are any packed fields. The ABI obviously doesn't
6020 specify how structures are passed in this case, so they are
6021 defined to be passed in int regs if possible, otherwise memory,
6022 regardless of whether there are fp values present. */
6025 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
6027 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6034 /* Compute how many registers we need. */
6035 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6037 if (TREE_CODE (field
) == FIELD_DECL
)
6039 HOST_WIDE_INT bitpos
= startbitpos
;
6041 if (DECL_SIZE (field
) != 0)
6043 if (integer_zerop (DECL_SIZE (field
)))
6046 if (host_integerp (bit_position (field
), 1))
6047 bitpos
+= int_bit_position (field
);
6050 /* ??? FIXME: else assume zero offset. */
6052 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6053 function_arg_record_value_1 (TREE_TYPE (field
),
6057 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6058 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6063 if (parms
->intoffset
!= -1)
6065 unsigned int startbit
, endbit
;
6066 int intslots
, this_slotno
;
6068 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
6069 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6071 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6072 this_slotno
= parms
->slotno
+ parms
->intoffset
6075 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6077 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6078 /* We need to pass this field on the stack. */
6082 parms
->nregs
+= intslots
;
6083 parms
->intoffset
= -1;
6086 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
6087 If it wasn't true we wouldn't be here. */
6088 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6089 && DECL_MODE (field
) == BLKmode
)
6090 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6091 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6098 if (parms
->intoffset
== -1)
6099 parms
->intoffset
= bitpos
;
6105 /* A subroutine of function_arg_record_value. Assign the bits of the
6106 structure between parms->intoffset and bitpos to integer registers. */
6109 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
6110 struct function_arg_record_value_parms
*parms
)
6112 enum machine_mode mode
;
6114 unsigned int startbit
, endbit
;
6115 int this_slotno
, intslots
, intoffset
;
6118 if (parms
->intoffset
== -1)
6121 intoffset
= parms
->intoffset
;
6122 parms
->intoffset
= -1;
6124 startbit
= intoffset
& -BITS_PER_WORD
;
6125 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6126 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6127 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
6129 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
6133 /* If this is the trailing part of a word, only load that much into
6134 the register. Otherwise load the whole register. Note that in
6135 the latter case we may pick up unwanted bits. It's not a problem
6136 at the moment but may wish to revisit. */
6138 if (intoffset
% BITS_PER_WORD
!= 0)
6139 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
6144 intoffset
/= BITS_PER_UNIT
;
6147 regno
= parms
->regbase
+ this_slotno
;
6148 reg
= gen_rtx_REG (mode
, regno
);
6149 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6150 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6153 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
6158 while (intslots
> 0);
6161 /* A subroutine of function_arg_record_value. Traverse the structure
6162 recursively and assign bits to floating point registers. Track which
6163 bits in between need integer registers; invoke function_arg_record_value_3
6164 to make that happen. */
6167 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
6168 struct function_arg_record_value_parms
*parms
,
6174 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6176 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6183 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6185 if (TREE_CODE (field
) == FIELD_DECL
)
6187 HOST_WIDE_INT bitpos
= startbitpos
;
6189 if (DECL_SIZE (field
) != 0)
6191 if (integer_zerop (DECL_SIZE (field
)))
6194 if (host_integerp (bit_position (field
), 1))
6195 bitpos
+= int_bit_position (field
);
6198 /* ??? FIXME: else assume zero offset. */
6200 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6201 function_arg_record_value_2 (TREE_TYPE (field
),
6205 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6206 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6211 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
6212 int regno
, nregs
, pos
;
6213 enum machine_mode mode
= DECL_MODE (field
);
6216 function_arg_record_value_3 (bitpos
, parms
);
6218 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6221 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6222 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6224 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6226 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6232 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6233 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6235 reg
= gen_rtx_REG (mode
, regno
);
6236 pos
= bitpos
/ BITS_PER_UNIT
;
6237 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6238 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6242 regno
+= GET_MODE_SIZE (mode
) / 4;
6243 reg
= gen_rtx_REG (mode
, regno
);
6244 pos
+= GET_MODE_SIZE (mode
);
6245 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6246 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6252 if (parms
->intoffset
== -1)
6253 parms
->intoffset
= bitpos
;
6259 /* Used by function_arg and sparc_function_value_1 to implement the complex
6260 conventions of the 64-bit ABI for passing and returning structures.
6261 Return an expression valid as a return value for the FUNCTION_ARG
6262 and TARGET_FUNCTION_VALUE.
6264 TYPE is the data type of the argument (as a tree).
6265 This is null for libcalls where that information may
6267 MODE is the argument's machine mode.
6268 SLOTNO is the index number of the argument's slot in the parameter array.
6269 NAMED is nonzero if this argument is a named parameter
6270 (otherwise it is an extra parameter matching an ellipsis).
6271 REGBASE is the regno of the base register for the parameter array. */
6274 function_arg_record_value (const_tree type
, enum machine_mode mode
,
6275 int slotno
, int named
, int regbase
)
6277 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6278 struct function_arg_record_value_parms parms
;
6281 parms
.ret
= NULL_RTX
;
6282 parms
.slotno
= slotno
;
6283 parms
.named
= named
;
6284 parms
.regbase
= regbase
;
6287 /* Compute how many registers we need. */
6289 parms
.intoffset
= 0;
6290 function_arg_record_value_1 (type
, 0, &parms
, false);
6292 /* Take into account pending integer fields. */
6293 if (parms
.intoffset
!= -1)
6295 unsigned int startbit
, endbit
;
6296 int intslots
, this_slotno
;
6298 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
6299 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6300 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6301 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
6303 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6305 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6306 /* We need to pass this field on the stack. */
6310 parms
.nregs
+= intslots
;
6312 nregs
= parms
.nregs
;
6314 /* Allocate the vector and handle some annoying special cases. */
6317 /* ??? Empty structure has no value? Duh? */
6320 /* Though there's nothing really to store, return a word register
6321 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6322 leads to breakage due to the fact that there are zero bytes to
6324 return gen_rtx_REG (mode
, regbase
);
6328 /* ??? C++ has structures with no fields, and yet a size. Give up
6329 for now and pass everything back in integer registers. */
6330 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6332 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6333 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6335 gcc_assert (nregs
!= 0);
6337 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
6339 /* If at least one field must be passed on the stack, generate
6340 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6341 also be passed on the stack. We can't do much better because the
6342 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6343 of structures for which the fields passed exclusively in registers
6344 are not at the beginning of the structure. */
6346 XVECEXP (parms
.ret
, 0, 0)
6347 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6349 /* Fill in the entries. */
6351 parms
.intoffset
= 0;
6352 function_arg_record_value_2 (type
, 0, &parms
, false);
6353 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6355 gcc_assert (parms
.nregs
== nregs
);
6360 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6361 of the 64-bit ABI for passing and returning unions.
6362 Return an expression valid as a return value for the FUNCTION_ARG
6363 and TARGET_FUNCTION_VALUE.
6365 SIZE is the size in bytes of the union.
6366 MODE is the argument's machine mode.
6367 REGNO is the hard register the union will be passed in. */
6370 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6373 int nwords
= ROUND_ADVANCE (size
), i
;
6376 /* See comment in previous function for empty structures. */
6378 return gen_rtx_REG (mode
, regno
);
6380 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6383 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6385 for (i
= 0; i
< nwords
; i
++)
6387 /* Unions are passed left-justified. */
6388 XVECEXP (regs
, 0, i
)
6389 = gen_rtx_EXPR_LIST (VOIDmode
,
6390 gen_rtx_REG (word_mode
, regno
),
6391 GEN_INT (UNITS_PER_WORD
* i
));
6398 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6399 for passing and returning large (BLKmode) vectors.
6400 Return an expression valid as a return value for the FUNCTION_ARG
6401 and TARGET_FUNCTION_VALUE.
6403 SIZE is the size in bytes of the vector (at least 8 bytes).
6404 REGNO is the FP hard register the vector will be passed in. */
6407 function_arg_vector_value (int size
, int regno
)
6409 int i
, nregs
= size
/ 8;
6412 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6414 for (i
= 0; i
< nregs
; i
++)
6416 XVECEXP (regs
, 0, i
)
6417 = gen_rtx_EXPR_LIST (VOIDmode
,
6418 gen_rtx_REG (DImode
, regno
+ 2*i
),
6425 /* Determine where to put an argument to a function.
6426 Value is zero to push the argument on the stack,
6427 or a hard register in which to store the argument.
6429 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6430 the preceding args and about the function being called.
6431 MODE is the argument's machine mode.
6432 TYPE is the data type of the argument (as a tree).
6433 This is null for libcalls where that information may
6435 NAMED is true if this argument is a named parameter
6436 (otherwise it is an extra parameter matching an ellipsis).
6437 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6438 TARGET_FUNCTION_INCOMING_ARG. */
6441 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6442 const_tree type
, bool named
, bool incoming_p
)
6444 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6446 int regbase
= (incoming_p
6447 ? SPARC_INCOMING_INT_ARG_FIRST
6448 : SPARC_OUTGOING_INT_ARG_FIRST
);
6449 int slotno
, regno
, padding
;
6450 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6452 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6457 /* Vector types deserve special treatment because they are polymorphic wrt
6458 their mode, depending upon whether VIS instructions are enabled. */
6459 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6461 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6462 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6463 || (TARGET_ARCH64
&& size
<= 16));
6465 if (mode
== BLKmode
)
6466 return function_arg_vector_value (size
,
6467 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6469 mclass
= MODE_FLOAT
;
6473 return gen_rtx_REG (mode
, regno
);
6475 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6476 and are promoted to registers if possible. */
6477 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6479 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6480 gcc_assert (size
<= 16);
6482 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6485 /* Unions up to 16 bytes in size are passed in integer registers. */
6486 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6488 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6489 gcc_assert (size
<= 16);
6491 return function_arg_union_value (size
, mode
, slotno
, regno
);
6494 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6495 but also have the slot allocated for them.
6496 If no prototype is in scope fp values in register slots get passed
6497 in two places, either fp regs and int regs or fp regs and memory. */
6498 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6499 && SPARC_FP_REG_P (regno
))
6501 rtx reg
= gen_rtx_REG (mode
, regno
);
6502 if (cum
->prototype_p
|| cum
->libcall_p
)
6504 /* "* 2" because fp reg numbers are recorded in 4 byte
6507 /* ??? This will cause the value to be passed in the fp reg and
6508 in the stack. When a prototype exists we want to pass the
6509 value in the reg but reserve space on the stack. That's an
6510 optimization, and is deferred [for a bit]. */
6511 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6512 return gen_rtx_PARALLEL (mode
,
6514 gen_rtx_EXPR_LIST (VOIDmode
,
6515 NULL_RTX
, const0_rtx
),
6516 gen_rtx_EXPR_LIST (VOIDmode
,
6520 /* ??? It seems that passing back a register even when past
6521 the area declared by REG_PARM_STACK_SPACE will allocate
6522 space appropriately, and will not copy the data onto the
6523 stack, exactly as we desire.
6525 This is due to locate_and_pad_parm being called in
6526 expand_call whenever reg_parm_stack_space > 0, which
6527 while beneficial to our example here, would seem to be
6528 in error from what had been intended. Ho hum... -- r~ */
6536 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6540 /* On incoming, we don't need to know that the value
6541 is passed in %f0 and %i0, and it confuses other parts
6542 causing needless spillage even on the simplest cases. */
6546 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6547 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6549 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6550 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6552 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6556 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6557 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6558 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6563 /* All other aggregate types are passed in an integer register in a mode
6564 corresponding to the size of the type. */
6565 else if (type
&& AGGREGATE_TYPE_P (type
))
6567 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6568 gcc_assert (size
<= 16);
6570 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6573 return gen_rtx_REG (mode
, regno
);
6576 /* Handle the TARGET_FUNCTION_ARG target hook. */
6579 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6580 const_tree type
, bool named
)
6582 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6585 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6588 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6589 const_tree type
, bool named
)
6591 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6594 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6597 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6599 return ((TARGET_ARCH64
6600 && (GET_MODE_ALIGNMENT (mode
) == 128
6601 || (type
&& TYPE_ALIGN (type
) == 128)))
6606 /* For an arg passed partly in registers and partly in memory,
6607 this is the number of bytes of registers used.
6608 For args passed entirely in registers or entirely in memory, zero.
6610 Any arg that starts in the first 6 regs but won't entirely fit in them
6611 needs partial registers on v8. On v9, structures with integer
6612 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6613 values that begin in the last fp reg [where "last fp reg" varies with the
6614 mode] will be split between that reg and memory. */
6617 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6618 tree type
, bool named
)
6620 int slotno
, regno
, padding
;
6622 /* We pass false for incoming_p here, it doesn't matter. */
6623 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6624 false, ®no
, &padding
);
6631 if ((slotno
+ (mode
== BLKmode
6632 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6633 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6634 > SPARC_INT_ARG_MAX
)
6635 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6639 /* We are guaranteed by pass_by_reference that the size of the
6640 argument is not greater than 16 bytes, so we only need to return
6641 one word if the argument is partially passed in registers. */
6643 if (type
&& AGGREGATE_TYPE_P (type
))
6645 int size
= int_size_in_bytes (type
);
6647 if (size
> UNITS_PER_WORD
6648 && slotno
== SPARC_INT_ARG_MAX
- 1)
6649 return UNITS_PER_WORD
;
6651 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6652 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6653 && ! (TARGET_FPU
&& named
)))
6655 /* The complex types are passed as packed types. */
6656 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6657 && slotno
== SPARC_INT_ARG_MAX
- 1)
6658 return UNITS_PER_WORD
;
6660 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6662 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6664 return UNITS_PER_WORD
;
6671 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6672 Specify whether to pass the argument by reference. */
6675 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6676 enum machine_mode mode
, const_tree type
,
6677 bool named ATTRIBUTE_UNUSED
)
6680 /* Original SPARC 32-bit ABI says that structures and unions,
6681 and quad-precision floats are passed by reference. For Pascal,
6682 also pass arrays by reference. All other base types are passed
6685 Extended ABI (as implemented by the Sun compiler) says that all
6686 complex floats are passed by reference. Pass complex integers
6687 in registers up to 8 bytes. More generally, enforce the 2-word
6688 cap for passing arguments in registers.
6690 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6691 integers are passed like floats of the same size, that is in
6692 registers up to 8 bytes. Pass all vector floats by reference
6693 like structure and unions. */
6694 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6696 /* Catch CDImode, TFmode, DCmode and TCmode. */
6697 || GET_MODE_SIZE (mode
) > 8
6699 && TREE_CODE (type
) == VECTOR_TYPE
6700 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6702 /* Original SPARC 64-bit ABI says that structures and unions
6703 smaller than 16 bytes are passed in registers, as well as
6704 all other base types.
6706 Extended ABI (as implemented by the Sun compiler) says that
6707 complex floats are passed in registers up to 16 bytes. Pass
6708 all complex integers in registers up to 16 bytes. More generally,
6709 enforce the 2-word cap for passing arguments in registers.
6711 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6712 integers are passed like floats of the same size, that is in
6713 registers (up to 16 bytes). Pass all vector floats like structure
6716 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6717 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6718 /* Catch CTImode and TCmode. */
6719 || GET_MODE_SIZE (mode
) > 16);
6722 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6723 Update the data in CUM to advance over an argument
6724 of mode MODE and data type TYPE.
6725 TYPE is null for libcalls where that information may not be available. */
6728 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6729 const_tree type
, bool named
)
6731 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6734 /* We pass false for incoming_p here, it doesn't matter. */
6735 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6737 /* If argument requires leading padding, add it. */
6738 cum
->words
+= padding
;
6742 cum
->words
+= (mode
!= BLKmode
6743 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6744 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6748 if (type
&& AGGREGATE_TYPE_P (type
))
6750 int size
= int_size_in_bytes (type
);
6754 else if (size
<= 16)
6756 else /* passed by reference */
6761 cum
->words
+= (mode
!= BLKmode
6762 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6763 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6768 /* Handle the FUNCTION_ARG_PADDING macro.
6769 For the 64 bit ABI structs are always stored left shifted in their
6773 function_arg_padding (enum machine_mode mode
, const_tree type
)
6775 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6778 /* Fall back to the default. */
6779 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6782 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6783 Specify whether to return the return value in memory. */
6786 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6789 /* Original SPARC 32-bit ABI says that structures and unions,
6790 and quad-precision floats are returned in memory. All other
6791 base types are returned in registers.
6793 Extended ABI (as implemented by the Sun compiler) says that
6794 all complex floats are returned in registers (8 FP registers
6795 at most for '_Complex long double'). Return all complex integers
6796 in registers (4 at most for '_Complex long long').
6798 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6799 integers are returned like floats of the same size, that is in
6800 registers up to 8 bytes and in memory otherwise. Return all
6801 vector floats in memory like structure and unions; note that
6802 they always have BLKmode like the latter. */
6803 return (TYPE_MODE (type
) == BLKmode
6804 || TYPE_MODE (type
) == TFmode
6805 || (TREE_CODE (type
) == VECTOR_TYPE
6806 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6808 /* Original SPARC 64-bit ABI says that structures and unions
6809 smaller than 32 bytes are returned in registers, as well as
6810 all other base types.
6812 Extended ABI (as implemented by the Sun compiler) says that all
6813 complex floats are returned in registers (8 FP registers at most
6814 for '_Complex long double'). Return all complex integers in
6815 registers (4 at most for '_Complex TItype').
6817 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6818 integers are returned like floats of the same size, that is in
6819 registers. Return all vector floats like structure and unions;
6820 note that they always have BLKmode like the latter. */
6821 return (TYPE_MODE (type
) == BLKmode
6822 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6825 /* Handle the TARGET_STRUCT_VALUE target hook.
6826 Return where to find the structure return value address. */
6829 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6838 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
6839 STRUCT_VALUE_OFFSET
));
6841 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
6842 STRUCT_VALUE_OFFSET
));
6844 /* Only follow the SPARC ABI for fixed-size structure returns.
6845 Variable size structure returns are handled per the normal
6846 procedures in GCC. This is enabled by -mstd-struct-return */
6848 && sparc_std_struct_return
6849 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6850 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6852 /* We must check and adjust the return address, as it is
6853 optional as to whether the return object is really
6855 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6856 rtx scratch
= gen_reg_rtx (SImode
);
6857 rtx endlab
= gen_label_rtx ();
6859 /* Calculate the return object size */
6860 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6861 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6862 /* Construct a temporary return value */
6864 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6866 /* Implement SPARC 32-bit psABI callee return struct checking:
6868 Fetch the instruction where we will return to and see if
6869 it's an unimp instruction (the most significant 10 bits
6871 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6872 plus_constant (Pmode
,
6874 /* Assume the size is valid and pre-adjust */
6875 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6876 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6878 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6879 /* Write the address of the memory pointed to by temp_val into
6880 the memory pointed to by mem */
6881 emit_move_insn (mem
, XEXP (temp_val
, 0));
6882 emit_label (endlab
);
6889 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6890 For v9, function return values are subject to the same rules as arguments,
6891 except that up to 32 bytes may be returned in registers. */
6894 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6897 /* Beware that the two values are swapped here wrt function_arg. */
6898 int regbase
= (outgoing
6899 ? SPARC_INCOMING_INT_ARG_FIRST
6900 : SPARC_OUTGOING_INT_ARG_FIRST
);
6901 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6904 /* Vector types deserve special treatment because they are polymorphic wrt
6905 their mode, depending upon whether VIS instructions are enabled. */
6906 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6908 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6909 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6910 || (TARGET_ARCH64
&& size
<= 32));
6912 if (mode
== BLKmode
)
6913 return function_arg_vector_value (size
,
6914 SPARC_FP_ARG_FIRST
);
6916 mclass
= MODE_FLOAT
;
6919 if (TARGET_ARCH64
&& type
)
6921 /* Structures up to 32 bytes in size are returned in registers. */
6922 if (TREE_CODE (type
) == RECORD_TYPE
)
6924 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6925 gcc_assert (size
<= 32);
6927 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6930 /* Unions up to 32 bytes in size are returned in integer registers. */
6931 else if (TREE_CODE (type
) == UNION_TYPE
)
6933 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6934 gcc_assert (size
<= 32);
6936 return function_arg_union_value (size
, mode
, 0, regbase
);
6939 /* Objects that require it are returned in FP registers. */
6940 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6943 /* All other aggregate types are returned in an integer register in a
6944 mode corresponding to the size of the type. */
6945 else if (AGGREGATE_TYPE_P (type
))
6947 /* All other aggregate types are passed in an integer register
6948 in a mode corresponding to the size of the type. */
6949 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6950 gcc_assert (size
<= 32);
6952 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6954 /* ??? We probably should have made the same ABI change in
6955 3.4.0 as the one we made for unions. The latter was
6956 required by the SCD though, while the former is not
6957 specified, so we favored compatibility and efficiency.
6959 Now we're stuck for aggregates larger than 16 bytes,
6960 because OImode vanished in the meantime. Let's not
6961 try to be unduly clever, and simply follow the ABI
6962 for unions in that case. */
6963 if (mode
== BLKmode
)
6964 return function_arg_union_value (size
, mode
, 0, regbase
);
6969 /* We should only have pointer and integer types at this point. This
6970 must match sparc_promote_function_mode. */
6971 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6975 /* We should only have pointer and integer types at this point. This must
6976 match sparc_promote_function_mode. */
6977 else if (TARGET_ARCH32
6978 && mclass
== MODE_INT
6979 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6982 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6983 regno
= SPARC_FP_ARG_FIRST
;
6987 return gen_rtx_REG (mode
, regno
);
6990 /* Handle TARGET_FUNCTION_VALUE.
6991 On the SPARC, the value is found in the first "output" register, but the
6992 called function leaves it in the first "input" register. */
6995 sparc_function_value (const_tree valtype
,
6996 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6999 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7002 /* Handle TARGET_LIBCALL_VALUE. */
7005 sparc_libcall_value (enum machine_mode mode
,
7006 const_rtx fun ATTRIBUTE_UNUSED
)
7008 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7011 /* Handle FUNCTION_VALUE_REGNO_P.
7012 On the SPARC, the first "output" reg is used for integer values, and the
7013 first floating point register is used for floating point values. */
7016 sparc_function_value_regno_p (const unsigned int regno
)
7018 return (regno
== 8 || regno
== 32);
7021 /* Do what is necessary for `va_start'. We look at the current function
7022 to determine if stdarg or varargs is used and return the address of
7023 the first unnamed parameter. */
7026 sparc_builtin_saveregs (void)
7028 int first_reg
= crtl
->args
.info
.words
;
7032 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7033 emit_move_insn (gen_rtx_MEM (word_mode
,
7034 gen_rtx_PLUS (Pmode
,
7036 GEN_INT (FIRST_PARM_OFFSET (0)
7039 gen_rtx_REG (word_mode
,
7040 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7042 address
= gen_rtx_PLUS (Pmode
,
7044 GEN_INT (FIRST_PARM_OFFSET (0)
7045 + UNITS_PER_WORD
* first_reg
));
7050 /* Implement `va_start' for stdarg. */
7053 sparc_va_start (tree valist
, rtx nextarg
)
7055 nextarg
= expand_builtin_saveregs ();
7056 std_expand_builtin_va_start (valist
, nextarg
);
7059 /* Implement `va_arg' for stdarg. */
7062 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7065 HOST_WIDE_INT size
, rsize
, align
;
7068 tree ptrtype
= build_pointer_type (type
);
7070 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7073 size
= rsize
= UNITS_PER_WORD
;
7079 size
= int_size_in_bytes (type
);
7080 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
7085 /* For SPARC64, objects requiring 16-byte alignment get it. */
7086 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7087 align
= 2 * UNITS_PER_WORD
;
7089 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7090 are left-justified in their slots. */
7091 if (AGGREGATE_TYPE_P (type
))
7094 size
= rsize
= UNITS_PER_WORD
;
7104 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7105 incr
= fold_convert (sizetype
, incr
);
7106 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7108 incr
= fold_convert (ptr_type_node
, incr
);
7111 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7114 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7115 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7119 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7120 addr
= build_va_arg_indirect_ref (addr
);
7123 /* If the address isn't aligned properly for the type, we need a temporary.
7124 FIXME: This is inefficient, usually we can do this in registers. */
7125 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7127 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7128 tree dest_addr
= build_fold_addr_expr (tmp
);
7129 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7130 3, dest_addr
, addr
, size_int (rsize
));
7131 TREE_ADDRESSABLE (tmp
) = 1;
7132 gimplify_and_add (copy
, pre_p
);
7137 addr
= fold_convert (ptrtype
, addr
);
7139 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7140 gimplify_assign (valist
, incr
, post_p
);
7142 return build_va_arg_indirect_ref (addr
);
7145 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7146 Specify whether the vector mode is supported by the hardware. */
7149 sparc_vector_mode_supported_p (enum machine_mode mode
)
7151 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7154 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7156 static enum machine_mode
7157 sparc_preferred_simd_mode (enum machine_mode mode
)
7175 /* Return the string to output an unconditional branch to LABEL, which is
7176 the operand number of the label.
7178 DEST is the destination insn (i.e. the label), INSN is the source. */
7181 output_ubranch (rtx dest
, rtx insn
)
7183 static char string
[64];
7184 bool v9_form
= false;
7188 /* Even if we are trying to use cbcond for this, evaluate
7189 whether we can use V9 branches as our backup plan. */
7192 if (INSN_ADDRESSES_SET_P ())
7193 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7194 - INSN_ADDRESSES (INSN_UID (insn
)));
7196 /* Leave some instructions for "slop". */
7197 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7202 bool emit_nop
= emit_cbcond_nop (insn
);
7206 if (delta
< -500 || delta
> 500)
7212 rval
= "ba,a,pt\t%%xcc, %l0";
7219 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7221 rval
= "cwbe\t%%g0, %%g0, %l0";
7227 strcpy (string
, "ba%*,pt\t%%xcc, ");
7229 strcpy (string
, "b%*\t");
7231 p
= strchr (string
, '\0');
7242 /* Return the string to output a conditional branch to LABEL, which is
7243 the operand number of the label. OP is the conditional expression.
7244 XEXP (OP, 0) is assumed to be a condition code register (integer or
7245 floating point) and its mode specifies what kind of comparison we made.
7247 DEST is the destination insn (i.e. the label), INSN is the source.
7249 REVERSED is nonzero if we should reverse the sense of the comparison.
7251 ANNUL is nonzero if we should generate an annulling branch. */
7254 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7257 static char string
[64];
7258 enum rtx_code code
= GET_CODE (op
);
7259 rtx cc_reg
= XEXP (op
, 0);
7260 enum machine_mode mode
= GET_MODE (cc_reg
);
7261 const char *labelno
, *branch
;
7262 int spaces
= 8, far
;
7265 /* v9 branches are limited to +-1MB. If it is too far away,
7278 fbne,a,pn %fcc2, .LC29
7286 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7289 /* Reversal of FP compares takes care -- an ordered compare
7290 becomes an unordered compare and vice versa. */
7291 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7292 code
= reverse_condition_maybe_unordered (code
);
7294 code
= reverse_condition (code
);
7297 /* Start by writing the branch condition. */
7298 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7349 /* ??? !v9: FP branches cannot be preceded by another floating point
7350 insn. Because there is currently no concept of pre-delay slots,
7351 we can fix this only by always emitting a nop before a floating
7356 strcpy (string
, "nop\n\t");
7357 strcat (string
, branch
);
7370 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7382 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7403 strcpy (string
, branch
);
7405 spaces
-= strlen (branch
);
7406 p
= strchr (string
, '\0');
7408 /* Now add the annulling, the label, and a possible noop. */
7421 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7423 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7424 - INSN_ADDRESSES (INSN_UID (insn
)));
7425 /* Leave some instructions for "slop". */
7426 if (delta
< -260000 || delta
>= 260000)
7430 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7432 static char v9_fcc_labelno
[] = "%%fccX, ";
7433 /* Set the char indicating the number of the fcc reg to use. */
7434 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7435 labelno
= v9_fcc_labelno
;
7438 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7442 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7444 labelno
= "%%xcc, ";
7449 labelno
= "%%icc, ";
7454 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7457 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7470 strcpy (p
, labelno
);
7471 p
= strchr (p
, '\0');
7474 strcpy (p
, ".+12\n\t nop\n\tb\t");
7475 /* Skip the next insn if requested or
7476 if we know that it will be a nop. */
7477 if (annul
|| ! final_sequence
)
7491 /* Emit a library call comparison between floating point X and Y.
7492 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7493 Return the new operator to be used in the comparison sequence.
7495 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7496 values as arguments instead of the TFmode registers themselves,
7497 that's why we cannot call emit_float_lib_cmp. */
7500 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7503 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7504 enum machine_mode mode
;
7505 enum rtx_code new_comparison
;
7510 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7514 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7518 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7522 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7526 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7530 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7541 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7552 tree expr
= MEM_EXPR (x
);
7554 mark_addressable (expr
);
7559 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7560 emit_move_insn (slot0
, x
);
7565 tree expr
= MEM_EXPR (y
);
7567 mark_addressable (expr
);
7572 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7573 emit_move_insn (slot1
, y
);
7576 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7577 emit_library_call (libfunc
, LCT_NORMAL
,
7579 XEXP (slot0
, 0), Pmode
,
7580 XEXP (slot1
, 0), Pmode
);
7585 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7586 emit_library_call (libfunc
, LCT_NORMAL
,
7588 x
, TFmode
, y
, TFmode
);
7593 /* Immediately move the result of the libcall into a pseudo
7594 register so reload doesn't clobber the value if it needs
7595 the return register for a spill reg. */
7596 result
= gen_reg_rtx (mode
);
7597 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7602 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7605 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7606 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7609 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7610 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7612 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7614 tem
= gen_reg_rtx (mode
);
7616 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7618 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7619 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7622 tem
= gen_reg_rtx (mode
);
7624 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7626 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7627 tem2
= gen_reg_rtx (mode
);
7629 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7631 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7632 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7633 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7639 /* Generate an unsigned DImode to FP conversion. This is the same code
7640 optabs would emit if we didn't have TFmode patterns. */
7643 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7645 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7648 in
= force_reg (DImode
, operands
[1]);
7649 neglab
= gen_label_rtx ();
7650 donelab
= gen_label_rtx ();
7651 i0
= gen_reg_rtx (DImode
);
7652 i1
= gen_reg_rtx (DImode
);
7653 f0
= gen_reg_rtx (mode
);
7655 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7657 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7658 emit_jump_insn (gen_jump (donelab
));
7661 emit_label (neglab
);
7663 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7664 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7665 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7666 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7667 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7669 emit_label (donelab
);
7672 /* Generate an FP to unsigned DImode conversion. This is the same code
7673 optabs would emit if we didn't have TFmode patterns. */
7676 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7678 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7681 in
= force_reg (mode
, operands
[1]);
7682 neglab
= gen_label_rtx ();
7683 donelab
= gen_label_rtx ();
7684 i0
= gen_reg_rtx (DImode
);
7685 i1
= gen_reg_rtx (DImode
);
7686 limit
= gen_reg_rtx (mode
);
7687 f0
= gen_reg_rtx (mode
);
7689 emit_move_insn (limit
,
7690 CONST_DOUBLE_FROM_REAL_VALUE (
7691 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7692 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7694 emit_insn (gen_rtx_SET (VOIDmode
,
7696 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7697 emit_jump_insn (gen_jump (donelab
));
7700 emit_label (neglab
);
7702 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7703 emit_insn (gen_rtx_SET (VOIDmode
,
7705 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7706 emit_insn (gen_movdi (i1
, const1_rtx
));
7707 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7708 emit_insn (gen_xordi3 (out
, i0
, i1
));
7710 emit_label (donelab
);
7713 /* Return the string to output a compare and branch instruction to DEST.
7714 DEST is the destination insn (i.e. the label), INSN is the source,
7715 and OP is the conditional expression. */
7718 output_cbcond (rtx op
, rtx dest
, rtx insn
)
7720 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7721 enum rtx_code code
= GET_CODE (op
);
7722 const char *cond_str
, *tmpl
;
7723 int far
, emit_nop
, len
;
7724 static char string
[64];
7727 /* Compare and Branch is limited to +-2KB. If it is too far away,
7739 len
= get_attr_length (insn
);
7742 emit_nop
= len
== 2;
7745 code
= reverse_condition (code
);
7747 size_char
= ((mode
== SImode
) ? 'w' : 'x');
7760 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7775 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7803 int veryfar
= 1, delta
;
7805 if (INSN_ADDRESSES_SET_P ())
7807 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7808 - INSN_ADDRESSES (INSN_UID (insn
)));
7809 /* Leave some instructions for "slop". */
7810 if (delta
>= -260000 && delta
< 260000)
7815 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
7817 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
7822 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
7824 tmpl
= "c%cb%s\t%%1, %%2, %%3";
7827 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
7832 /* Return the string to output a conditional branch to LABEL, testing
7833 register REG. LABEL is the operand number of the label; REG is the
7834 operand number of the reg. OP is the conditional expression. The mode
7835 of REG says what kind of comparison we made.
7837 DEST is the destination insn (i.e. the label), INSN is the source.
7839 REVERSED is nonzero if we should reverse the sense of the comparison.
7841 ANNUL is nonzero if we should generate an annulling branch. */
7844 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7845 int annul
, rtx insn
)
7847 static char string
[64];
7848 enum rtx_code code
= GET_CODE (op
);
7849 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7854 /* branch on register are limited to +-128KB. If it is too far away,
7867 brgez,a,pn %o1, .LC29
7873 ba,pt %xcc, .LC29 */
7875 far
= get_attr_length (insn
) >= 3;
7877 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7879 code
= reverse_condition (code
);
7881 /* Only 64 bit versions of these instructions exist. */
7882 gcc_assert (mode
== DImode
);
7884 /* Start by writing the branch condition. */
7889 strcpy (string
, "brnz");
7893 strcpy (string
, "brz");
7897 strcpy (string
, "brgez");
7901 strcpy (string
, "brlz");
7905 strcpy (string
, "brlez");
7909 strcpy (string
, "brgz");
7916 p
= strchr (string
, '\0');
7918 /* Now add the annulling, reg, label, and nop. */
7925 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7928 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7933 *p
= p
< string
+ 8 ? '\t' : ' ';
7941 int veryfar
= 1, delta
;
7943 if (INSN_ADDRESSES_SET_P ())
7945 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7946 - INSN_ADDRESSES (INSN_UID (insn
)));
7947 /* Leave some instructions for "slop". */
7948 if (delta
>= -260000 && delta
< 260000)
7952 strcpy (p
, ".+12\n\t nop\n\t");
7953 /* Skip the next insn if requested or
7954 if we know that it will be a nop. */
7955 if (annul
|| ! final_sequence
)
7965 strcpy (p
, "ba,pt\t%%xcc, ");
7979 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7980 Such instructions cannot be used in the delay slot of return insn on v9.
7981 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7985 epilogue_renumber (register rtx
*where
, int test
)
7987 register const char *fmt
;
7989 register enum rtx_code code
;
7994 code
= GET_CODE (*where
);
7999 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8001 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8002 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8010 /* Do not replace the frame pointer with the stack pointer because
8011 it can cause the delayed instruction to load below the stack.
8012 This occurs when instructions like:
8014 (set (reg/i:SI 24 %i0)
8015 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8016 (const_int -20 [0xffffffec])) 0))
8018 are in the return delayed slot. */
8020 if (GET_CODE (XEXP (*where
, 0)) == REG
8021 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8022 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8023 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8028 if (SPARC_STACK_BIAS
8029 && GET_CODE (XEXP (*where
, 0)) == REG
8030 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8038 fmt
= GET_RTX_FORMAT (code
);
8040 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8045 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8046 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8049 else if (fmt
[i
] == 'e'
8050 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8056 /* Leaf functions and non-leaf functions have different needs. */
8059 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8062 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8064 static const int *const reg_alloc_orders
[] = {
8065 reg_leaf_alloc_order
,
8066 reg_nonleaf_alloc_order
};
8069 order_regs_for_local_alloc (void)
8071 static int last_order_nonleaf
= 1;
8073 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8075 last_order_nonleaf
= !last_order_nonleaf
;
8076 memcpy ((char *) reg_alloc_order
,
8077 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8078 FIRST_PSEUDO_REGISTER
* sizeof (int));
8082 /* Return 1 if REG and MEM are legitimate enough to allow the various
8083 mem<-->reg splits to be run. */
8086 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
8088 /* Punt if we are here by mistake. */
8089 gcc_assert (reload_completed
);
8091 /* We must have an offsettable memory reference. */
8092 if (! offsettable_memref_p (mem
))
8095 /* If we have legitimate args for ldd/std, we do not want
8096 the split to happen. */
8097 if ((REGNO (reg
) % 2) == 0
8098 && mem_min_alignment (mem
, 8))
8105 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8108 sparc_split_regreg_legitimate (rtx reg1
, rtx reg2
)
8112 if (GET_CODE (reg1
) == SUBREG
)
8113 reg1
= SUBREG_REG (reg1
);
8114 if (GET_CODE (reg1
) != REG
)
8116 regno1
= REGNO (reg1
);
8118 if (GET_CODE (reg2
) == SUBREG
)
8119 reg2
= SUBREG_REG (reg2
);
8120 if (GET_CODE (reg2
) != REG
)
8122 regno2
= REGNO (reg2
);
8124 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8129 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8130 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8137 /* Return 1 if x and y are some kind of REG and they refer to
8138 different hard registers. This test is guaranteed to be
8139 run after reload. */
8142 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
8144 if (GET_CODE (x
) != REG
)
8146 if (GET_CODE (y
) != REG
)
8148 if (REGNO (x
) == REGNO (y
))
8153 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8154 This makes them candidates for using ldd and std insns.
8156 Note reg1 and reg2 *must* be hard registers. */
8159 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8161 /* We might have been passed a SUBREG. */
8162 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8165 if (REGNO (reg1
) % 2 != 0)
8168 /* Integer ldd is deprecated in SPARC V9 */
8169 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8172 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8175 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8178 This can only happen when addr1 and addr2, the addresses in mem1
8179 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8180 addr1 must also be aligned on a 64-bit boundary.
8182 Also iff dependent_reg_rtx is not null it should not be used to
8183 compute the address for mem1, i.e. we cannot optimize a sequence
8195 But, note that the transformation from:
8200 is perfectly fine. Thus, the peephole2 patterns always pass us
8201 the destination register of the first load, never the second one.
8203 For stores we don't have a similar problem, so dependent_reg_rtx is
8207 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8211 HOST_WIDE_INT offset1
;
8213 /* The mems cannot be volatile. */
8214 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8217 /* MEM1 should be aligned on a 64-bit boundary. */
8218 if (MEM_ALIGN (mem1
) < 64)
8221 addr1
= XEXP (mem1
, 0);
8222 addr2
= XEXP (mem2
, 0);
8224 /* Extract a register number and offset (if used) from the first addr. */
8225 if (GET_CODE (addr1
) == PLUS
)
8227 /* If not a REG, return zero. */
8228 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8232 reg1
= REGNO (XEXP (addr1
, 0));
8233 /* The offset must be constant! */
8234 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8236 offset1
= INTVAL (XEXP (addr1
, 1));
8239 else if (GET_CODE (addr1
) != REG
)
8243 reg1
= REGNO (addr1
);
8244 /* This was a simple (mem (reg)) expression. Offset is 0. */
8248 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8249 if (GET_CODE (addr2
) != PLUS
)
8252 if (GET_CODE (XEXP (addr2
, 0)) != REG
8253 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8256 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8259 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8262 /* The first offset must be evenly divisible by 8 to ensure the
8263 address is 64 bit aligned. */
8264 if (offset1
% 8 != 0)
8267 /* The offset for the second addr must be 4 more than the first addr. */
8268 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8271 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8276 /* Return 1 if reg is a pseudo, or is the first register in
8277 a hard register pair. This makes it suitable for use in
8278 ldd and std insns. */
8281 register_ok_for_ldd (rtx reg
)
8283 /* We might have been passed a SUBREG. */
8287 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8288 return (REGNO (reg
) % 2 == 0);
8293 /* Return 1 if OP, a MEM, has an address which is known to be
8294 aligned to an 8-byte boundary. */
8297 memory_ok_for_ldd (rtx op
)
8299 /* In 64-bit mode, we assume that the address is word-aligned. */
8300 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8303 if (! can_create_pseudo_p ()
8304 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8310 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8313 sparc_print_operand_punct_valid_p (unsigned char code
)
8326 /* Implement TARGET_PRINT_OPERAND.
8327 Print operand X (an rtx) in assembler syntax to file FILE.
8328 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8329 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8332 sparc_print_operand (FILE *file
, rtx x
, int code
)
8337 /* Output an insn in a delay slot. */
8339 sparc_indent_opcode
= 1;
8341 fputs ("\n\t nop", file
);
8344 /* Output an annul flag if there's nothing for the delay slot and we
8345 are optimizing. This is always used with '(' below.
8346 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8347 this is a dbx bug. So, we only do this when optimizing.
8348 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8349 Always emit a nop in case the next instruction is a branch. */
8350 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8354 /* Output a 'nop' if there's nothing for the delay slot and we are
8355 not optimizing. This is always used with '*' above. */
8356 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8357 fputs ("\n\t nop", file
);
8358 else if (final_sequence
)
8359 sparc_indent_opcode
= 1;
8362 /* Output the right displacement from the saved PC on function return.
8363 The caller may have placed an "unimp" insn immediately after the call
8364 so we have to account for it. This insn is used in the 32-bit ABI
8365 when calling a function that returns a non zero-sized structure. The
8366 64-bit ABI doesn't have it. Be careful to have this test be the same
8367 as that for the call. The exception is when sparc_std_struct_return
8368 is enabled, the psABI is followed exactly and the adjustment is made
8369 by the code in sparc_struct_value_rtx. The call emitted is the same
8370 when sparc_std_struct_return is enabled. */
8372 && cfun
->returns_struct
8373 && !sparc_std_struct_return
8374 && DECL_SIZE (DECL_RESULT (current_function_decl
))
8375 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
8377 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
8383 /* Output the Embedded Medium/Anywhere code model base register. */
8384 fputs (EMBMEDANY_BASE_REG
, file
);
8387 /* Print some local dynamic TLS name. */
8388 assemble_name (file
, get_some_local_dynamic_name ());
8392 /* Adjust the operand to take into account a RESTORE operation. */
8393 if (GET_CODE (x
) == CONST_INT
)
8395 else if (GET_CODE (x
) != REG
)
8396 output_operand_lossage ("invalid %%Y operand");
8397 else if (REGNO (x
) < 8)
8398 fputs (reg_names
[REGNO (x
)], file
);
8399 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
8400 fputs (reg_names
[REGNO (x
)-16], file
);
8402 output_operand_lossage ("invalid %%Y operand");
8405 /* Print out the low order register name of a register pair. */
8406 if (WORDS_BIG_ENDIAN
)
8407 fputs (reg_names
[REGNO (x
)+1], file
);
8409 fputs (reg_names
[REGNO (x
)], file
);
8412 /* Print out the high order register name of a register pair. */
8413 if (WORDS_BIG_ENDIAN
)
8414 fputs (reg_names
[REGNO (x
)], file
);
8416 fputs (reg_names
[REGNO (x
)+1], file
);
8419 /* Print out the second register name of a register pair or quad.
8420 I.e., R (%o0) => %o1. */
8421 fputs (reg_names
[REGNO (x
)+1], file
);
8424 /* Print out the third register name of a register quad.
8425 I.e., S (%o0) => %o2. */
8426 fputs (reg_names
[REGNO (x
)+2], file
);
8429 /* Print out the fourth register name of a register quad.
8430 I.e., T (%o0) => %o3. */
8431 fputs (reg_names
[REGNO (x
)+3], file
);
8434 /* Print a condition code register. */
8435 if (REGNO (x
) == SPARC_ICC_REG
)
8437 /* We don't handle CC[X]_NOOVmode because they're not supposed
8439 if (GET_MODE (x
) == CCmode
)
8440 fputs ("%icc", file
);
8441 else if (GET_MODE (x
) == CCXmode
)
8442 fputs ("%xcc", file
);
8447 /* %fccN register */
8448 fputs (reg_names
[REGNO (x
)], file
);
8451 /* Print the operand's address only. */
8452 output_address (XEXP (x
, 0));
8455 /* In this case we need a register. Use %g0 if the
8456 operand is const0_rtx. */
8458 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
8460 fputs ("%g0", file
);
8467 switch (GET_CODE (x
))
8469 case IOR
: fputs ("or", file
); break;
8470 case AND
: fputs ("and", file
); break;
8471 case XOR
: fputs ("xor", file
); break;
8472 default: output_operand_lossage ("invalid %%A operand");
8477 switch (GET_CODE (x
))
8479 case IOR
: fputs ("orn", file
); break;
8480 case AND
: fputs ("andn", file
); break;
8481 case XOR
: fputs ("xnor", file
); break;
8482 default: output_operand_lossage ("invalid %%B operand");
8486 /* This is used by the conditional move instructions. */
8489 enum rtx_code rc
= GET_CODE (x
);
8493 case NE
: fputs ("ne", file
); break;
8494 case EQ
: fputs ("e", file
); break;
8495 case GE
: fputs ("ge", file
); break;
8496 case GT
: fputs ("g", file
); break;
8497 case LE
: fputs ("le", file
); break;
8498 case LT
: fputs ("l", file
); break;
8499 case GEU
: fputs ("geu", file
); break;
8500 case GTU
: fputs ("gu", file
); break;
8501 case LEU
: fputs ("leu", file
); break;
8502 case LTU
: fputs ("lu", file
); break;
8503 case LTGT
: fputs ("lg", file
); break;
8504 case UNORDERED
: fputs ("u", file
); break;
8505 case ORDERED
: fputs ("o", file
); break;
8506 case UNLT
: fputs ("ul", file
); break;
8507 case UNLE
: fputs ("ule", file
); break;
8508 case UNGT
: fputs ("ug", file
); break;
8509 case UNGE
: fputs ("uge", file
); break;
8510 case UNEQ
: fputs ("ue", file
); break;
8511 default: output_operand_lossage ("invalid %%C operand");
8516 /* This are used by the movr instruction pattern. */
8519 enum rtx_code rc
= GET_CODE (x
);
8522 case NE
: fputs ("ne", file
); break;
8523 case EQ
: fputs ("e", file
); break;
8524 case GE
: fputs ("gez", file
); break;
8525 case LT
: fputs ("lz", file
); break;
8526 case LE
: fputs ("lez", file
); break;
8527 case GT
: fputs ("gz", file
); break;
8528 default: output_operand_lossage ("invalid %%D operand");
8535 /* Print a sign-extended character. */
8536 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8537 fprintf (file
, "%d", i
);
8542 /* Operand must be a MEM; write its address. */
8543 if (GET_CODE (x
) != MEM
)
8544 output_operand_lossage ("invalid %%f operand");
8545 output_address (XEXP (x
, 0));
8550 /* Print a sign-extended 32-bit value. */
8552 if (GET_CODE(x
) == CONST_INT
)
8554 else if (GET_CODE(x
) == CONST_DOUBLE
)
8555 i
= CONST_DOUBLE_LOW (x
);
8558 output_operand_lossage ("invalid %%s operand");
8561 i
= trunc_int_for_mode (i
, SImode
);
8562 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8567 /* Do nothing special. */
8571 /* Undocumented flag. */
8572 output_operand_lossage ("invalid operand output code");
8575 if (GET_CODE (x
) == REG
)
8576 fputs (reg_names
[REGNO (x
)], file
);
8577 else if (GET_CODE (x
) == MEM
)
8580 /* Poor Sun assembler doesn't understand absolute addressing. */
8581 if (CONSTANT_P (XEXP (x
, 0)))
8582 fputs ("%g0+", file
);
8583 output_address (XEXP (x
, 0));
8586 else if (GET_CODE (x
) == HIGH
)
8588 fputs ("%hi(", file
);
8589 output_addr_const (file
, XEXP (x
, 0));
8592 else if (GET_CODE (x
) == LO_SUM
)
8594 sparc_print_operand (file
, XEXP (x
, 0), 0);
8595 if (TARGET_CM_MEDMID
)
8596 fputs ("+%l44(", file
);
8598 fputs ("+%lo(", file
);
8599 output_addr_const (file
, XEXP (x
, 1));
8602 else if (GET_CODE (x
) == CONST_DOUBLE
8603 && (GET_MODE (x
) == VOIDmode
8604 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8606 if (CONST_DOUBLE_HIGH (x
) == 0)
8607 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8608 else if (CONST_DOUBLE_HIGH (x
) == -1
8609 && CONST_DOUBLE_LOW (x
) < 0)
8610 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8612 output_operand_lossage ("long long constant not a valid immediate operand");
8614 else if (GET_CODE (x
) == CONST_DOUBLE
)
8615 output_operand_lossage ("floating point constant not a valid immediate operand");
8616 else { output_addr_const (file
, x
); }
8619 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8622 sparc_print_operand_address (FILE *file
, rtx x
)
8624 register rtx base
, index
= 0;
8626 register rtx addr
= x
;
8629 fputs (reg_names
[REGNO (addr
)], file
);
8630 else if (GET_CODE (addr
) == PLUS
)
8632 if (CONST_INT_P (XEXP (addr
, 0)))
8633 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8634 else if (CONST_INT_P (XEXP (addr
, 1)))
8635 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8637 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8638 if (GET_CODE (base
) == LO_SUM
)
8640 gcc_assert (USE_AS_OFFSETABLE_LO10
8642 && ! TARGET_CM_MEDMID
);
8643 output_operand (XEXP (base
, 0), 0);
8644 fputs ("+%lo(", file
);
8645 output_address (XEXP (base
, 1));
8646 fprintf (file
, ")+%d", offset
);
8650 fputs (reg_names
[REGNO (base
)], file
);
8652 fprintf (file
, "%+d", offset
);
8653 else if (REG_P (index
))
8654 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8655 else if (GET_CODE (index
) == SYMBOL_REF
8656 || GET_CODE (index
) == LABEL_REF
8657 || GET_CODE (index
) == CONST
)
8658 fputc ('+', file
), output_addr_const (file
, index
);
8659 else gcc_unreachable ();
8662 else if (GET_CODE (addr
) == MINUS
8663 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8665 output_addr_const (file
, XEXP (addr
, 0));
8667 output_addr_const (file
, XEXP (addr
, 1));
8668 fputs ("-.)", file
);
8670 else if (GET_CODE (addr
) == LO_SUM
)
8672 output_operand (XEXP (addr
, 0), 0);
8673 if (TARGET_CM_MEDMID
)
8674 fputs ("+%l44(", file
);
8676 fputs ("+%lo(", file
);
8677 output_address (XEXP (addr
, 1));
8681 && GET_CODE (addr
) == CONST
8682 && GET_CODE (XEXP (addr
, 0)) == MINUS
8683 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8684 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8685 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8687 addr
= XEXP (addr
, 0);
8688 output_addr_const (file
, XEXP (addr
, 0));
8689 /* Group the args of the second CONST in parenthesis. */
8691 /* Skip past the second CONST--it does nothing for us. */
8692 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8693 /* Close the parenthesis. */
8698 output_addr_const (file
, addr
);
8702 /* Target hook for assembling integer objects. The sparc version has
8703 special handling for aligned DI-mode objects. */
8706 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8708 /* ??? We only output .xword's for symbols and only then in environments
8709 where the assembler can handle them. */
8710 if (aligned_p
&& size
== 8
8711 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8715 assemble_integer_with_op ("\t.xword\t", x
);
8720 assemble_aligned_integer (4, const0_rtx
);
8721 assemble_aligned_integer (4, x
);
8725 return default_assemble_integer (x
, size
, aligned_p
);
8728 /* Return the value of a code used in the .proc pseudo-op that says
8729 what kind of result this function returns. For non-C types, we pick
8730 the closest C type. */
8732 #ifndef SHORT_TYPE_SIZE
8733 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8736 #ifndef INT_TYPE_SIZE
8737 #define INT_TYPE_SIZE BITS_PER_WORD
8740 #ifndef LONG_TYPE_SIZE
8741 #define LONG_TYPE_SIZE BITS_PER_WORD
8744 #ifndef LONG_LONG_TYPE_SIZE
8745 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8748 #ifndef FLOAT_TYPE_SIZE
8749 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8752 #ifndef DOUBLE_TYPE_SIZE
8753 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8756 #ifndef LONG_DOUBLE_TYPE_SIZE
8757 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8761 sparc_type_code (register tree type
)
8763 register unsigned long qualifiers
= 0;
8764 register unsigned shift
;
8766 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8767 setting more, since some assemblers will give an error for this. Also,
8768 we must be careful to avoid shifts of 32 bits or more to avoid getting
8769 unpredictable results. */
8771 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8773 switch (TREE_CODE (type
))
8779 qualifiers
|= (3 << shift
);
8784 qualifiers
|= (2 << shift
);
8788 case REFERENCE_TYPE
:
8790 qualifiers
|= (1 << shift
);
8794 return (qualifiers
| 8);
8797 case QUAL_UNION_TYPE
:
8798 return (qualifiers
| 9);
8801 return (qualifiers
| 10);
8804 return (qualifiers
| 16);
8807 /* If this is a range type, consider it to be the underlying
8809 if (TREE_TYPE (type
) != 0)
8812 /* Carefully distinguish all the standard types of C,
8813 without messing up if the language is not C. We do this by
8814 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8815 look at both the names and the above fields, but that's redundant.
8816 Any type whose size is between two C types will be considered
8817 to be the wider of the two types. Also, we do not have a
8818 special code to use for "long long", so anything wider than
8819 long is treated the same. Note that we can't distinguish
8820 between "int" and "long" in this code if they are the same
8821 size, but that's fine, since neither can the assembler. */
8823 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8824 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8826 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8827 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8829 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8830 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8833 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8836 /* If this is a range type, consider it to be the underlying
8838 if (TREE_TYPE (type
) != 0)
8841 /* Carefully distinguish all the standard types of C,
8842 without messing up if the language is not C. */
8844 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8845 return (qualifiers
| 6);
8848 return (qualifiers
| 7);
8850 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8851 /* ??? We need to distinguish between double and float complex types,
8852 but I don't know how yet because I can't reach this code from
8853 existing front-ends. */
8854 return (qualifiers
| 7); /* Who knows? */
8857 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8863 gcc_unreachable (); /* Not a type! */
8870 /* Nested function support. */
8872 /* Emit RTL insns to initialize the variable parts of a trampoline.
8873 FNADDR is an RTX for the address of the function's pure code.
8874 CXT is an RTX for the static chain value for the function.
8876 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8877 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8878 (to store insns). This is a bit excessive. Perhaps a different
8879 mechanism would be better here.
8881 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8884 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8886 /* SPARC 32-bit trampoline:
8889 sethi %hi(static), %g2
8891 or %g2, %lo(static), %g2
8893 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8894 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8898 (adjust_address (m_tramp
, SImode
, 0),
8899 expand_binop (SImode
, ior_optab
,
8900 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8901 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8902 NULL_RTX
, 1, OPTAB_DIRECT
));
8905 (adjust_address (m_tramp
, SImode
, 4),
8906 expand_binop (SImode
, ior_optab
,
8907 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8908 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8909 NULL_RTX
, 1, OPTAB_DIRECT
));
8912 (adjust_address (m_tramp
, SImode
, 8),
8913 expand_binop (SImode
, ior_optab
,
8914 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8915 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8916 NULL_RTX
, 1, OPTAB_DIRECT
));
8919 (adjust_address (m_tramp
, SImode
, 12),
8920 expand_binop (SImode
, ior_optab
,
8921 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8922 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8923 NULL_RTX
, 1, OPTAB_DIRECT
));
8925 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8926 aligned on a 16 byte boundary so one flush clears it all. */
8927 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8928 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8929 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8930 && sparc_cpu
!= PROCESSOR_NIAGARA
8931 && sparc_cpu
!= PROCESSOR_NIAGARA2
8932 && sparc_cpu
!= PROCESSOR_NIAGARA3
8933 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8934 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8936 /* Call __enable_execute_stack after writing onto the stack to make sure
8937 the stack address is accessible. */
8938 #ifdef HAVE_ENABLE_EXECUTE_STACK
8939 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8940 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8945 /* The 64-bit version is simpler because it makes more sense to load the
8946 values as "immediate" data out of the trampoline. It's also easier since
8947 we can read the PC without clobbering a register. */
8950 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8952 /* SPARC 64-bit trampoline:
8961 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8962 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8963 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8964 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8965 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8966 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8967 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8968 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8969 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8970 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8971 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8973 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8974 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8975 && sparc_cpu
!= PROCESSOR_NIAGARA
8976 && sparc_cpu
!= PROCESSOR_NIAGARA2
8977 && sparc_cpu
!= PROCESSOR_NIAGARA3
8978 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8979 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8981 /* Call __enable_execute_stack after writing onto the stack to make sure
8982 the stack address is accessible. */
8983 #ifdef HAVE_ENABLE_EXECUTE_STACK
8984 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8985 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8989 /* Worker for TARGET_TRAMPOLINE_INIT. */
8992 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8994 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8995 cxt
= force_reg (Pmode
, cxt
);
8997 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8999 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9002 /* Adjust the cost of a scheduling dependency. Return the new cost of
9003 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9006 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
9008 enum attr_type insn_type
;
9010 if (! recog_memoized (insn
))
9013 insn_type
= get_attr_type (insn
);
9015 if (REG_NOTE_KIND (link
) == 0)
9017 /* Data dependency; DEP_INSN writes a register that INSN reads some
9020 /* if a load, then the dependence must be on the memory address;
9021 add an extra "cycle". Note that the cost could be two cycles
9022 if the reg was written late in an instruction group; we ca not tell
9024 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9027 /* Get the delay only if the address of the store is the dependence. */
9028 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9030 rtx pat
= PATTERN(insn
);
9031 rtx dep_pat
= PATTERN (dep_insn
);
9033 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9034 return cost
; /* This should not happen! */
9036 /* The dependency between the two instructions was on the data that
9037 is being stored. Assume that this implies that the address of the
9038 store is not dependent. */
9039 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9042 return cost
+ 3; /* An approximation. */
9045 /* A shift instruction cannot receive its data from an instruction
9046 in the same cycle; add a one cycle penalty. */
9047 if (insn_type
== TYPE_SHIFT
)
9048 return cost
+ 3; /* Split before cascade into shift. */
9052 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9053 INSN writes some cycles later. */
9055 /* These are only significant for the fpu unit; writing a fp reg before
9056 the fpu has finished with it stalls the processor. */
9058 /* Reusing an integer register causes no problems. */
9059 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9067 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
9069 enum attr_type insn_type
, dep_type
;
9070 rtx pat
= PATTERN(insn
);
9071 rtx dep_pat
= PATTERN (dep_insn
);
9073 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9076 insn_type
= get_attr_type (insn
);
9077 dep_type
= get_attr_type (dep_insn
);
9079 switch (REG_NOTE_KIND (link
))
9082 /* Data dependency; DEP_INSN writes a register that INSN reads some
9089 /* Get the delay iff the address of the store is the dependence. */
9090 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9093 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9100 /* If a load, then the dependence must be on the memory address. If
9101 the addresses aren't equal, then it might be a false dependency */
9102 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9104 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9105 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9106 || GET_CODE (SET_SRC (pat
)) != MEM
9107 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9108 XEXP (SET_SRC (pat
), 0)))
9116 /* Compare to branch latency is 0. There is no benefit from
9117 separating compare and branch. */
9118 if (dep_type
== TYPE_COMPARE
)
9120 /* Floating point compare to branch latency is less than
9121 compare to conditional move. */
9122 if (dep_type
== TYPE_FPCMP
)
9131 /* Anti-dependencies only penalize the fpu unit. */
9132 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9144 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
9148 case PROCESSOR_SUPERSPARC
:
9149 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
9151 case PROCESSOR_HYPERSPARC
:
9152 case PROCESSOR_SPARCLITE86X
:
9153 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
9162 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9163 int sched_verbose ATTRIBUTE_UNUSED
,
9164 int max_ready ATTRIBUTE_UNUSED
)
9168 sparc_use_sched_lookahead (void)
9170 if (sparc_cpu
== PROCESSOR_NIAGARA
9171 || sparc_cpu
== PROCESSOR_NIAGARA2
9172 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9174 if (sparc_cpu
== PROCESSOR_NIAGARA4
)
9176 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9177 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9179 if ((1 << sparc_cpu
) &
9180 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9181 (1 << PROCESSOR_SPARCLITE86X
)))
9187 sparc_issue_rate (void)
9191 case PROCESSOR_NIAGARA
:
9192 case PROCESSOR_NIAGARA2
:
9193 case PROCESSOR_NIAGARA3
:
9196 case PROCESSOR_NIAGARA4
:
9198 /* Assume V9 processors are capable of at least dual-issue. */
9200 case PROCESSOR_SUPERSPARC
:
9202 case PROCESSOR_HYPERSPARC
:
9203 case PROCESSOR_SPARCLITE86X
:
9205 case PROCESSOR_ULTRASPARC
:
9206 case PROCESSOR_ULTRASPARC3
:
9212 set_extends (rtx insn
)
9214 register rtx pat
= PATTERN (insn
);
9216 switch (GET_CODE (SET_SRC (pat
)))
9218 /* Load and some shift instructions zero extend. */
9221 /* sethi clears the high bits */
9223 /* LO_SUM is used with sethi. sethi cleared the high
9224 bits and the values used with lo_sum are positive */
9226 /* Store flag stores 0 or 1 */
9236 rtx op0
= XEXP (SET_SRC (pat
), 0);
9237 rtx op1
= XEXP (SET_SRC (pat
), 1);
9238 if (GET_CODE (op1
) == CONST_INT
)
9239 return INTVAL (op1
) >= 0;
9240 if (GET_CODE (op0
) != REG
)
9242 if (sparc_check_64 (op0
, insn
) == 1)
9244 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9249 rtx op0
= XEXP (SET_SRC (pat
), 0);
9250 rtx op1
= XEXP (SET_SRC (pat
), 1);
9251 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
9253 if (GET_CODE (op1
) == CONST_INT
)
9254 return INTVAL (op1
) >= 0;
9255 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9258 return GET_MODE (SET_SRC (pat
)) == SImode
;
9259 /* Positive integers leave the high bits zero. */
9261 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
9263 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
9266 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
9268 return sparc_check_64 (SET_SRC (pat
), insn
);
9274 /* We _ought_ to have only one kind per function, but... */
9275 static GTY(()) rtx sparc_addr_diff_list
;
9276 static GTY(()) rtx sparc_addr_list
;
9279 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
9281 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9283 sparc_addr_diff_list
9284 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
9286 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
9290 sparc_output_addr_vec (rtx vec
)
9292 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9293 int idx
, vlen
= XVECLEN (body
, 0);
9295 #ifdef ASM_OUTPUT_ADDR_VEC_START
9296 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9299 #ifdef ASM_OUTPUT_CASE_LABEL
9300 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9303 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9306 for (idx
= 0; idx
< vlen
; idx
++)
9308 ASM_OUTPUT_ADDR_VEC_ELT
9309 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9312 #ifdef ASM_OUTPUT_ADDR_VEC_END
9313 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9318 sparc_output_addr_diff_vec (rtx vec
)
9320 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9321 rtx base
= XEXP (XEXP (body
, 0), 0);
9322 int idx
, vlen
= XVECLEN (body
, 1);
9324 #ifdef ASM_OUTPUT_ADDR_VEC_START
9325 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9328 #ifdef ASM_OUTPUT_CASE_LABEL
9329 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9332 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9335 for (idx
= 0; idx
< vlen
; idx
++)
9337 ASM_OUTPUT_ADDR_DIFF_ELT
9340 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
9341 CODE_LABEL_NUMBER (base
));
9344 #ifdef ASM_OUTPUT_ADDR_VEC_END
9345 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9350 sparc_output_deferred_case_vectors (void)
9355 if (sparc_addr_list
== NULL_RTX
9356 && sparc_addr_diff_list
== NULL_RTX
)
9359 /* Align to cache line in the function's code section. */
9360 switch_to_section (current_function_section ());
9362 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9364 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
9366 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
9367 sparc_output_addr_vec (XEXP (t
, 0));
9368 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
9369 sparc_output_addr_diff_vec (XEXP (t
, 0));
9371 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
9374 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9375 unknown. Return 1 if the high bits are zero, -1 if the register is
9378 sparc_check_64 (rtx x
, rtx insn
)
9380 /* If a register is set only once it is safe to ignore insns this
9381 code does not know how to handle. The loop will either recognize
9382 the single set and return the correct value or fail to recognize
9387 gcc_assert (GET_CODE (x
) == REG
);
9389 if (GET_MODE (x
) == DImode
)
9390 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
9392 if (flag_expensive_optimizations
9393 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
9399 insn
= get_last_insn_anywhere ();
9404 while ((insn
= PREV_INSN (insn
)))
9406 switch (GET_CODE (insn
))
9419 rtx pat
= PATTERN (insn
);
9420 if (GET_CODE (pat
) != SET
)
9422 if (rtx_equal_p (x
, SET_DEST (pat
)))
9423 return set_extends (insn
);
9424 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
9425 return set_extends (insn
);
9426 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
9434 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9435 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9438 output_v8plus_shift (rtx insn
, rtx
*operands
, const char *opcode
)
9440 static char asm_code
[60];
9442 /* The scratch register is only required when the destination
9443 register is not a 64-bit global or out register. */
9444 if (which_alternative
!= 2)
9445 operands
[3] = operands
[0];
9447 /* We can only shift by constants <= 63. */
9448 if (GET_CODE (operands
[2]) == CONST_INT
)
9449 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
9451 if (GET_CODE (operands
[1]) == CONST_INT
)
9453 output_asm_insn ("mov\t%1, %3", operands
);
9457 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
9458 if (sparc_check_64 (operands
[1], insn
) <= 0)
9459 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
9460 output_asm_insn ("or\t%L1, %3, %3", operands
);
9463 strcpy (asm_code
, opcode
);
9465 if (which_alternative
!= 2)
9466 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9469 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9472 /* Output rtl to increment the profiler label LABELNO
9473 for profiling a function entry. */
9476 sparc_profile_hook (int labelno
)
9481 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
9482 if (NO_PROFILE_COUNTERS
)
9484 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
9488 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
9489 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
9490 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
9494 #ifdef TARGET_SOLARIS
9495 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9498 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9499 tree decl ATTRIBUTE_UNUSED
)
9501 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9503 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9507 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9509 if (!(flags
& SECTION_DEBUG
))
9510 fputs (",#alloc", asm_out_file
);
9511 if (flags
& SECTION_WRITE
)
9512 fputs (",#write", asm_out_file
);
9513 if (flags
& SECTION_TLS
)
9514 fputs (",#tls", asm_out_file
);
9515 if (flags
& SECTION_CODE
)
9516 fputs (",#execinstr", asm_out_file
);
9518 /* ??? Handle SECTION_BSS. */
9520 fputc ('\n', asm_out_file
);
9522 #endif /* TARGET_SOLARIS */
9524 /* We do not allow indirect calls to be optimized into sibling calls.
9526 We cannot use sibling calls when delayed branches are disabled
9527 because they will likely require the call delay slot to be filled.
9529 Also, on SPARC 32-bit we cannot emit a sibling call when the
9530 current function returns a structure. This is because the "unimp
9531 after call" convention would cause the callee to return to the
9532 wrong place. The generic code already disallows cases where the
9533 function being called returns a structure.
9535 It may seem strange how this last case could occur. Usually there
9536 is code after the call which jumps to epilogue code which dumps the
9537 return value into the struct return area. That ought to invalidate
9538 the sibling call right? Well, in the C++ case we can end up passing
9539 the pointer to the struct return area to a constructor (which returns
9540 void) and then nothing else happens. Such a sibling call would look
9541 valid without the added check here.
9543 VxWorks PIC PLT entries require the global pointer to be initialized
9544 on entry. We therefore can't emit sibling calls to them. */
9546 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9549 && flag_delayed_branch
9550 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9551 && !(TARGET_VXWORKS_RTP
9553 && !targetm
.binds_local_p (decl
)));
9556 /* libfunc renaming. */
9559 sparc_init_libfuncs (void)
9563 /* Use the subroutines that Sun's library provides for integer
9564 multiply and divide. The `*' prevents an underscore from
9565 being prepended by the compiler. .umul is a little faster
9567 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9568 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9569 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9570 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9571 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9573 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9574 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9575 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9576 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9577 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9578 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9580 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9581 is because with soft-float, the SFmode and DFmode sqrt
9582 instructions will be absent, and the compiler will notice and
9583 try to use the TFmode sqrt instruction for calls to the
9584 builtin function sqrt, but this fails. */
9586 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9588 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9589 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9590 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9591 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9592 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9593 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9595 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9596 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9597 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9598 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9600 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9601 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9602 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9603 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9605 if (DITF_CONVERSION_LIBFUNCS
)
9607 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9608 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9609 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9610 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9613 if (SUN_CONVERSION_LIBFUNCS
)
9615 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9616 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9617 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9618 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9623 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9624 do not exist in the library. Make sure the compiler does not
9625 emit calls to them by accident. (It should always use the
9626 hardware instructions.) */
9627 set_optab_libfunc (smul_optab
, SImode
, 0);
9628 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9629 set_optab_libfunc (udiv_optab
, SImode
, 0);
9630 set_optab_libfunc (smod_optab
, SImode
, 0);
9631 set_optab_libfunc (umod_optab
, SImode
, 0);
9633 if (SUN_INTEGER_MULTIPLY_64
)
9635 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9636 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9637 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9638 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9639 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9642 if (SUN_CONVERSION_LIBFUNCS
)
9644 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9645 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9646 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9647 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9652 static tree
def_builtin(const char *name
, int code
, tree type
)
9654 return add_builtin_function(name
, type
, code
, BUILT_IN_MD
, NULL
,
9658 static tree
def_builtin_const(const char *name
, int code
, tree type
)
9660 tree t
= def_builtin(name
, code
, type
);
9663 TREE_READONLY (t
) = 1;
9668 /* Implement the TARGET_INIT_BUILTINS target hook.
9669 Create builtin functions for special SPARC instructions. */
9672 sparc_init_builtins (void)
9675 sparc_vis_init_builtins ();
9678 /* Create builtin functions for VIS 1.0 instructions. */
9681 sparc_vis_init_builtins (void)
9683 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9684 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9685 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9686 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9687 tree v2si
= build_vector_type (intSI_type_node
, 2);
9688 tree v1si
= build_vector_type (intSI_type_node
, 1);
9690 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9691 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9692 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9693 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9694 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9695 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9696 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9697 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9698 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9699 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9700 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9701 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9702 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
9703 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
9704 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9706 intDI_type_node
, 0);
9707 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
9709 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
9711 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9713 intDI_type_node
, 0);
9714 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
9716 intSI_type_node
, 0);
9717 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9719 intSI_type_node
, 0);
9720 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9722 intDI_type_node
, 0);
9723 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
9726 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
9729 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
9731 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
9733 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
9735 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
9737 tree void_ftype_di
= build_function_type_list (void_type_node
,
9738 intDI_type_node
, 0);
9739 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
9741 tree void_ftype_si
= build_function_type_list (void_type_node
,
9742 intSI_type_node
, 0);
9743 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
9745 float_type_node
, 0);
9746 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
9748 double_type_node
, 0);
9750 /* Packing and expanding vectors. */
9751 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
9753 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9754 v8qi_ftype_v2si_v8qi
);
9755 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9757 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
9759 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9760 v8qi_ftype_v4qi_v4qi
);
9762 /* Multiplications. */
9763 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9764 v4hi_ftype_v4qi_v4hi
);
9765 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9766 v4hi_ftype_v4qi_v2hi
);
9767 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9768 v4hi_ftype_v4qi_v2hi
);
9769 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9770 v4hi_ftype_v8qi_v4hi
);
9771 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9772 v4hi_ftype_v8qi_v4hi
);
9773 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9774 v2si_ftype_v4qi_v2hi
);
9775 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9776 v2si_ftype_v4qi_v2hi
);
9778 /* Data aligning. */
9779 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9780 v4hi_ftype_v4hi_v4hi
);
9781 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9782 v8qi_ftype_v8qi_v8qi
);
9783 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9784 v2si_ftype_v2si_v2si
);
9785 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
9788 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
9790 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
9795 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9797 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
9802 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9804 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
9808 /* Pixel distance. */
9809 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9810 di_ftype_v8qi_v8qi_di
);
9812 /* Edge handling. */
9815 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
9817 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
9819 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
9821 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
9823 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
9825 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
9829 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
9831 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
9833 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
9835 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
9837 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
9839 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
9845 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
9847 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
9849 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
9851 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
9853 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
9855 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
9859 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
9861 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
9863 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
9865 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
9867 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
9869 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
9874 /* Pixel compare. */
9877 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
9878 di_ftype_v4hi_v4hi
);
9879 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
9880 di_ftype_v2si_v2si
);
9881 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
9882 di_ftype_v4hi_v4hi
);
9883 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
9884 di_ftype_v2si_v2si
);
9885 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
9886 di_ftype_v4hi_v4hi
);
9887 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
9888 di_ftype_v2si_v2si
);
9889 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
9890 di_ftype_v4hi_v4hi
);
9891 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
9892 di_ftype_v2si_v2si
);
9896 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
9897 si_ftype_v4hi_v4hi
);
9898 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
9899 si_ftype_v2si_v2si
);
9900 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
9901 si_ftype_v4hi_v4hi
);
9902 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
9903 si_ftype_v2si_v2si
);
9904 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
9905 si_ftype_v4hi_v4hi
);
9906 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
9907 si_ftype_v2si_v2si
);
9908 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
9909 si_ftype_v4hi_v4hi
);
9910 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
9911 si_ftype_v2si_v2si
);
9914 /* Addition and subtraction. */
9915 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
9916 v4hi_ftype_v4hi_v4hi
);
9917 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
9918 v2hi_ftype_v2hi_v2hi
);
9919 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
9920 v2si_ftype_v2si_v2si
);
9921 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
9922 v1si_ftype_v1si_v1si
);
9923 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
9924 v4hi_ftype_v4hi_v4hi
);
9925 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
9926 v2hi_ftype_v2hi_v2hi
);
9927 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
9928 v2si_ftype_v2si_v2si
);
9929 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
9930 v1si_ftype_v1si_v1si
);
9932 /* Three-dimensional array addressing. */
9935 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
9937 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
9939 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
9944 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
9946 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
9948 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
9954 /* Byte mask and shuffle */
9956 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
9959 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
9961 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
9962 v4hi_ftype_v4hi_v4hi
);
9963 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
9964 v8qi_ftype_v8qi_v8qi
);
9965 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
9966 v2si_ftype_v2si_v2si
);
9967 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
9975 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
9977 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
9979 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
9984 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
9986 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
9988 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
9992 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
9993 v4hi_ftype_v4hi_v4hi
);
9995 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
9996 v4hi_ftype_v4hi_v4hi
);
9997 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
9998 v4hi_ftype_v4hi_v4hi
);
9999 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
10000 v4hi_ftype_v4hi_v4hi
);
10001 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
10002 v4hi_ftype_v4hi_v4hi
);
10003 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
10004 v2si_ftype_v2si_v2si
);
10005 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
10006 v2si_ftype_v2si_v2si
);
10007 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
10008 v2si_ftype_v2si_v2si
);
10009 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
10010 v2si_ftype_v2si_v2si
);
10013 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
10014 di_ftype_v8qi_v8qi
);
10016 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
10017 si_ftype_v8qi_v8qi
);
10019 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
10020 v4hi_ftype_v4hi_v4hi
);
10021 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
10023 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
10026 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
10027 v4hi_ftype_v4hi_v4hi
);
10028 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
10029 v2hi_ftype_v2hi_v2hi
);
10030 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
10031 v4hi_ftype_v4hi_v4hi
);
10032 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
10033 v2hi_ftype_v2hi_v2hi
);
10034 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
10035 v2si_ftype_v2si_v2si
);
10036 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
10037 v1si_ftype_v1si_v1si
);
10038 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
10039 v2si_ftype_v2si_v2si
);
10040 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
10041 v1si_ftype_v1si_v1si
);
10045 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
10046 di_ftype_v8qi_v8qi
);
10047 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
10048 di_ftype_v8qi_v8qi
);
10049 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
10050 di_ftype_v8qi_v8qi
);
10051 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
10052 di_ftype_v8qi_v8qi
);
10056 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
10057 si_ftype_v8qi_v8qi
);
10058 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
10059 si_ftype_v8qi_v8qi
);
10060 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
10061 si_ftype_v8qi_v8qi
);
10062 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
10063 si_ftype_v8qi_v8qi
);
10066 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
10068 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
10070 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
10072 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
10074 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
10076 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
10079 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
10081 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
10083 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
10088 /* Handle TARGET_EXPAND_BUILTIN target hook.
10089 Expand builtin functions for sparc intrinsics. */
10092 sparc_expand_builtin (tree exp
, rtx target
,
10093 rtx subtarget ATTRIBUTE_UNUSED
,
10094 enum machine_mode tmode ATTRIBUTE_UNUSED
,
10095 int ignore ATTRIBUTE_UNUSED
)
10098 call_expr_arg_iterator iter
;
10099 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10100 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
10105 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10109 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10111 || GET_MODE (target
) != tmode
10112 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10113 op
[0] = gen_reg_rtx (tmode
);
10117 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10119 const struct insn_operand_data
*insn_op
;
10122 if (arg
== error_mark_node
)
10126 idx
= arg_count
- !nonvoid
;
10127 insn_op
= &insn_data
[icode
].operand
[idx
];
10128 op
[arg_count
] = expand_normal (arg
);
10130 if (insn_op
->mode
== V1DImode
10131 && GET_MODE (op
[arg_count
]) == DImode
)
10132 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
10133 else if (insn_op
->mode
== V1SImode
10134 && GET_MODE (op
[arg_count
]) == SImode
)
10135 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
10137 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
10139 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
10145 pat
= GEN_FCN (icode
) (op
[0]);
10149 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10151 pat
= GEN_FCN (icode
) (op
[1]);
10154 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
10157 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
10160 gcc_unreachable ();
10175 sparc_vis_mul8x16 (int e8
, int e16
)
10177 return (e8
* e16
+ 128) / 256;
10180 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10181 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10184 sparc_handle_vis_mul8x16 (tree
*n_elts
, int fncode
, tree inner_type
,
10185 tree cst0
, tree cst1
)
10187 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
10192 case CODE_FOR_fmul8x16_vis
:
10193 for (i
= 0; i
< num
; ++i
)
10196 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10197 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
10198 n_elts
[i
] = build_int_cst (inner_type
, val
);
10202 case CODE_FOR_fmul8x16au_vis
:
10203 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
10205 for (i
= 0; i
< num
; ++i
)
10208 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10210 n_elts
[i
] = build_int_cst (inner_type
, val
);
10214 case CODE_FOR_fmul8x16al_vis
:
10215 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
10217 for (i
= 0; i
< num
; ++i
)
10220 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10222 n_elts
[i
] = build_int_cst (inner_type
, val
);
10227 gcc_unreachable ();
10231 /* Handle TARGET_FOLD_BUILTIN target hook.
10232 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10233 result of the function call is ignored. NULL_TREE is returned if the
10234 function could not be folded. */
10237 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
10238 tree
*args
, bool ignore
)
10240 tree arg0
, arg1
, arg2
;
10241 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
10242 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
10246 /* Note that a switch statement instead of the sequence of tests would
10247 be incorrect as many of the CODE_FOR values could be CODE_FOR_nothing
10248 and that would yield multiple alternatives with identical values. */
10249 if (icode
== CODE_FOR_alignaddrsi_vis
10250 || icode
== CODE_FOR_alignaddrdi_vis
10251 || icode
== CODE_FOR_wrgsr_vis
10252 || icode
== CODE_FOR_bmasksi_vis
10253 || icode
== CODE_FOR_bmaskdi_vis
10254 || icode
== CODE_FOR_cmask8si_vis
10255 || icode
== CODE_FOR_cmask8di_vis
10256 || icode
== CODE_FOR_cmask16si_vis
10257 || icode
== CODE_FOR_cmask16di_vis
10258 || icode
== CODE_FOR_cmask32si_vis
10259 || icode
== CODE_FOR_cmask32di_vis
)
10262 return build_zero_cst (rtype
);
10267 case CODE_FOR_fexpand_vis
:
10271 if (TREE_CODE (arg0
) == VECTOR_CST
)
10273 tree inner_type
= TREE_TYPE (rtype
);
10277 n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10278 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10279 n_elts
[i
] = build_int_cst (inner_type
,
10281 (VECTOR_CST_ELT (arg0
, i
)) << 4);
10282 return build_vector (rtype
, n_elts
);
10286 case CODE_FOR_fmul8x16_vis
:
10287 case CODE_FOR_fmul8x16au_vis
:
10288 case CODE_FOR_fmul8x16al_vis
:
10294 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10296 tree inner_type
= TREE_TYPE (rtype
);
10297 tree
*n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10298 sparc_handle_vis_mul8x16 (n_elts
, icode
, inner_type
, arg0
, arg1
);
10299 return build_vector (rtype
, n_elts
);
10303 case CODE_FOR_fpmerge_vis
:
10309 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10311 tree
*n_elts
= XALLOCAVEC (tree
, 2 * VECTOR_CST_NELTS (arg0
));
10313 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10315 n_elts
[2*i
] = VECTOR_CST_ELT (arg0
, i
);
10316 n_elts
[2*i
+1] = VECTOR_CST_ELT (arg1
, i
);
10319 return build_vector (rtype
, n_elts
);
10323 case CODE_FOR_pdist_vis
:
10331 if (TREE_CODE (arg0
) == VECTOR_CST
10332 && TREE_CODE (arg1
) == VECTOR_CST
10333 && TREE_CODE (arg2
) == INTEGER_CST
)
10335 bool overflow
= false;
10336 double_int result
= TREE_INT_CST (arg2
);
10340 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10342 double_int e0
= TREE_INT_CST (VECTOR_CST_ELT (arg0
, i
));
10343 double_int e1
= TREE_INT_CST (VECTOR_CST_ELT (arg1
, i
));
10345 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
10347 tmp
= e1
.neg_with_overflow (&neg1_ovf
);
10348 tmp
= e0
.add_with_sign (tmp
, false, &add1_ovf
);
10349 if (tmp
.is_negative ())
10350 tmp
= tmp
.neg_with_overflow (&neg2_ovf
);
10352 result
= result
.add_with_sign (tmp
, false, &add2_ovf
);
10353 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
10356 gcc_assert (!overflow
);
10358 return build_int_cst_wide (rtype
, result
.low
, result
.high
);
10368 /* ??? This duplicates information provided to the compiler by the
10369 ??? scheduler description. Some day, teach genautomata to output
10370 ??? the latencies and then CSE will just use that. */
10373 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
10374 int *total
, bool speed ATTRIBUTE_UNUSED
)
10376 enum machine_mode mode
= GET_MODE (x
);
10377 bool float_mode_p
= FLOAT_MODE_P (mode
);
10382 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
10400 if (GET_MODE (x
) == VOIDmode
10401 && ((CONST_DOUBLE_HIGH (x
) == 0
10402 && CONST_DOUBLE_LOW (x
) < 0x1000)
10403 || (CONST_DOUBLE_HIGH (x
) == -1
10404 && CONST_DOUBLE_LOW (x
) < 0
10405 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
10412 /* If outer-code was a sign or zero extension, a cost
10413 of COSTS_N_INSNS (1) was already added in. This is
10414 why we are subtracting it back out. */
10415 if (outer_code
== ZERO_EXTEND
)
10417 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
10419 else if (outer_code
== SIGN_EXTEND
)
10421 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
10423 else if (float_mode_p
)
10425 *total
= sparc_costs
->float_load
;
10429 *total
= sparc_costs
->int_load
;
10437 *total
= sparc_costs
->float_plusminus
;
10439 *total
= COSTS_N_INSNS (1);
10446 gcc_assert (float_mode_p
);
10447 *total
= sparc_costs
->float_mul
;
10450 if (GET_CODE (sub
) == NEG
)
10451 sub
= XEXP (sub
, 0);
10452 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
10455 if (GET_CODE (sub
) == NEG
)
10456 sub
= XEXP (sub
, 0);
10457 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
10463 *total
= sparc_costs
->float_mul
;
10464 else if (! TARGET_HARD_MUL
)
10465 *total
= COSTS_N_INSNS (25);
10471 if (sparc_costs
->int_mul_bit_factor
)
10475 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
10477 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
10478 for (nbits
= 0; value
!= 0; value
&= value
- 1)
10481 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
10482 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
10484 rtx x1
= XEXP (x
, 1);
10485 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
10486 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
10488 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
10490 for (; value2
!= 0; value2
&= value2
- 1)
10498 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
10499 bit_cost
= COSTS_N_INSNS (bit_cost
);
10502 if (mode
== DImode
)
10503 *total
= sparc_costs
->int_mulX
+ bit_cost
;
10505 *total
= sparc_costs
->int_mul
+ bit_cost
;
10512 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
10521 if (mode
== DFmode
)
10522 *total
= sparc_costs
->float_div_df
;
10524 *total
= sparc_costs
->float_div_sf
;
10528 if (mode
== DImode
)
10529 *total
= sparc_costs
->int_divX
;
10531 *total
= sparc_costs
->int_div
;
10536 if (! float_mode_p
)
10538 *total
= COSTS_N_INSNS (1);
10545 case UNSIGNED_FLOAT
:
10549 case FLOAT_TRUNCATE
:
10550 *total
= sparc_costs
->float_move
;
10554 if (mode
== DFmode
)
10555 *total
= sparc_costs
->float_sqrt_df
;
10557 *total
= sparc_costs
->float_sqrt_sf
;
10562 *total
= sparc_costs
->float_cmp
;
10564 *total
= COSTS_N_INSNS (1);
10569 *total
= sparc_costs
->float_cmove
;
10571 *total
= sparc_costs
->int_cmove
;
10575 /* Handle the NAND vector patterns. */
10576 if (sparc_vector_mode_supported_p (GET_MODE (x
))
10577 && GET_CODE (XEXP (x
, 0)) == NOT
10578 && GET_CODE (XEXP (x
, 1)) == NOT
)
10580 *total
= COSTS_N_INSNS (1);
10591 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
10594 general_or_i64_p (reg_class_t rclass
)
10596 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
10599 /* Implement TARGET_REGISTER_MOVE_COST. */
10602 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10603 reg_class_t from
, reg_class_t to
)
10605 bool need_memory
= false;
10607 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
10608 need_memory
= true;
10609 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
10610 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
10614 int size
= GET_MODE_SIZE (mode
);
10615 if (size
== 8 || size
== 4)
10617 if (! TARGET_ARCH32
|| size
== 4)
10623 need_memory
= true;
10628 if (sparc_cpu
== PROCESSOR_ULTRASPARC
10629 || sparc_cpu
== PROCESSOR_ULTRASPARC3
10630 || sparc_cpu
== PROCESSOR_NIAGARA
10631 || sparc_cpu
== PROCESSOR_NIAGARA2
10632 || sparc_cpu
== PROCESSOR_NIAGARA3
10633 || sparc_cpu
== PROCESSOR_NIAGARA4
)
10642 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
10643 This is achieved by means of a manual dynamic stack space allocation in
10644 the current frame. We make the assumption that SEQ doesn't contain any
10645 function calls, with the possible exception of calls to the GOT helper. */
10648 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
10650 /* We must preserve the lowest 16 words for the register save area. */
10651 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
10652 /* We really need only 2 words of fresh stack space. */
10653 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
10656 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10657 SPARC_STACK_BIAS
+ offset
));
10659 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
10660 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
10662 emit_insn (gen_rtx_SET (VOIDmode
,
10663 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
10667 emit_insn (gen_rtx_SET (VOIDmode
,
10669 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
10670 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
10671 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
10674 /* Output the assembler code for a thunk function. THUNK_DECL is the
10675 declaration for the thunk function itself, FUNCTION is the decl for
10676 the target function. DELTA is an immediate constant offset to be
10677 added to THIS. If VCALL_OFFSET is nonzero, the word at address
10678 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
10681 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
10682 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10685 rtx this_rtx
, insn
, funexp
;
10686 unsigned int int_arg_first
;
10688 reload_completed
= 1;
10689 epilogue_completed
= 1;
10691 emit_note (NOTE_INSN_PROLOGUE_END
);
10695 sparc_leaf_function_p
= 1;
10697 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10699 else if (flag_delayed_branch
)
10701 /* We will emit a regular sibcall below, so we need to instruct
10702 output_sibcall that we are in a leaf function. */
10703 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
10705 /* This will cause final.c to invoke leaf_renumber_regs so we
10706 must behave as if we were in a not-yet-leafified function. */
10707 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
10711 /* We will emit the sibcall manually below, so we will need to
10712 manually spill non-leaf registers. */
10713 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
10715 /* We really are in a leaf function. */
10716 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10719 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
10720 returns a structure, the structure return pointer is there instead. */
10722 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
10723 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
10725 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
10727 /* Add DELTA. When possible use a plain add, otherwise load it into
10728 a register first. */
10731 rtx delta_rtx
= GEN_INT (delta
);
10733 if (! SPARC_SIMM13_P (delta
))
10735 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10736 emit_move_insn (scratch
, delta_rtx
);
10737 delta_rtx
= scratch
;
10740 /* THIS_RTX += DELTA. */
10741 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
10744 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
10747 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10748 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10750 gcc_assert (vcall_offset
< 0);
10752 /* SCRATCH = *THIS_RTX. */
10753 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
10755 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10756 may not have any available scratch register at this point. */
10757 if (SPARC_SIMM13_P (vcall_offset
))
10759 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10760 else if (! fixed_regs
[5]
10761 /* The below sequence is made up of at least 2 insns,
10762 while the default method may need only one. */
10763 && vcall_offset
< -8192)
10765 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
10766 emit_move_insn (scratch2
, vcall_offset_rtx
);
10767 vcall_offset_rtx
= scratch2
;
10771 rtx increment
= GEN_INT (-4096);
10773 /* VCALL_OFFSET is a negative number whose typical range can be
10774 estimated as -32768..0 in 32-bit mode. In almost all cases
10775 it is therefore cheaper to emit multiple add insns than
10776 spilling and loading the constant into a register (at least
10778 while (! SPARC_SIMM13_P (vcall_offset
))
10780 emit_insn (gen_add2_insn (scratch
, increment
));
10781 vcall_offset
+= 4096;
10783 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
10786 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10787 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
10788 gen_rtx_PLUS (Pmode
,
10790 vcall_offset_rtx
)));
10792 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10793 emit_insn (gen_add2_insn (this_rtx
, scratch
));
10796 /* Generate a tail call to the target function. */
10797 if (! TREE_USED (function
))
10799 assemble_external (function
);
10800 TREE_USED (function
) = 1;
10802 funexp
= XEXP (DECL_RTL (function
), 0);
10804 if (flag_delayed_branch
)
10806 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10807 insn
= emit_call_insn (gen_sibcall (funexp
));
10808 SIBLING_CALL_P (insn
) = 1;
10812 /* The hoops we have to jump through in order to generate a sibcall
10813 without using delay slots... */
10814 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
10818 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
10820 load_got_register (); /* clobbers %o7 */
10821 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
10822 seq
= get_insns ();
10824 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
10826 else if (TARGET_ARCH32
)
10828 emit_insn (gen_rtx_SET (VOIDmode
,
10830 gen_rtx_HIGH (SImode
, funexp
)));
10831 emit_insn (gen_rtx_SET (VOIDmode
,
10833 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
10835 else /* TARGET_ARCH64 */
10837 switch (sparc_cmodel
)
10841 /* The destination can serve as a temporary. */
10842 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
10847 /* The destination cannot serve as a temporary. */
10848 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
10850 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
10851 seq
= get_insns ();
10853 emit_and_preserve (seq
, spill_reg
, 0);
10857 gcc_unreachable ();
10861 emit_jump_insn (gen_indirect_jump (scratch
));
10866 /* Run just enough of rest_of_compilation to get the insns emitted.
10867 There's not really enough bulk here to make other passes such as
10868 instruction scheduling worth while. Note that use_thunk calls
10869 assemble_start_function and assemble_end_function. */
10870 insn
= get_insns ();
10871 shorten_branches (insn
);
10872 final_start_function (insn
, file
, 1);
10873 final (insn
, file
, 1);
10874 final_end_function ();
10876 reload_completed
= 0;
10877 epilogue_completed
= 0;
10880 /* Return true if sparc_output_mi_thunk would be able to output the
10881 assembler code for the thunk function specified by the arguments
10882 it is passed, and false otherwise. */
10884 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
10885 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
10886 HOST_WIDE_INT vcall_offset
,
10887 const_tree function ATTRIBUTE_UNUSED
)
10889 /* Bound the loop used in the default method above. */
10890 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
10893 /* We use the machine specific reorg pass to enable workarounds for errata. */
10900 /* The only erratum we handle for now is that of the AT697F processor. */
10901 if (!sparc_fix_at697f
)
10904 /* We need to have the (essentially) final form of the insn stream in order
10905 to properly detect the various hazards. Run delay slot scheduling. */
10906 if (optimize
> 0 && flag_delayed_branch
)
10908 cleanup_barriers ();
10909 dbr_schedule (get_insns ());
10912 /* Now look for specific patterns in the insn stream. */
10913 for (insn
= get_insns (); insn
; insn
= next
)
10915 bool insert_nop
= false;
10918 /* Look for a single-word load into an odd-numbered FP register. */
10919 if (NONJUMP_INSN_P (insn
)
10920 && (set
= single_set (insn
)) != NULL_RTX
10921 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
10922 && MEM_P (SET_SRC (set
))
10923 && REG_P (SET_DEST (set
))
10924 && REGNO (SET_DEST (set
)) > 31
10925 && REGNO (SET_DEST (set
)) % 2 != 0)
10927 /* The wrong dependency is on the enclosing double register. */
10928 unsigned int x
= REGNO (SET_DEST (set
)) - 1;
10929 unsigned int src1
, src2
, dest
;
10932 /* If the insn has a delay slot, then it cannot be problematic. */
10933 next
= next_active_insn (insn
);
10934 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
10938 extract_insn (next
);
10939 code
= INSN_CODE (next
);
10944 case CODE_FOR_adddf3
:
10945 case CODE_FOR_subdf3
:
10946 case CODE_FOR_muldf3
:
10947 case CODE_FOR_divdf3
:
10948 dest
= REGNO (recog_data
.operand
[0]);
10949 src1
= REGNO (recog_data
.operand
[1]);
10950 src2
= REGNO (recog_data
.operand
[2]);
10954 ld [address], %fx+1
10955 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
10956 if ((src1
== x
|| src2
== x
)
10957 && (dest
== src1
|| dest
== src2
))
10963 ld [address], %fx+1
10964 FPOPd %fx, %fx, %fx */
10967 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
10972 case CODE_FOR_sqrtdf2
:
10973 dest
= REGNO (recog_data
.operand
[0]);
10974 src1
= REGNO (recog_data
.operand
[1]);
10976 ld [address], %fx+1
10978 if (src1
== x
&& dest
== src1
)
10987 next
= NEXT_INSN (insn
);
10990 emit_insn_after (gen_nop (), insn
);
10994 /* How to allocate a 'struct machine_function'. */
10996 static struct machine_function
*
10997 sparc_init_machine_status (void)
10999 return ggc_alloc_cleared_machine_function ();
11002 /* Locate some local-dynamic symbol still in use by this function
11003 so that we can print its name in local-dynamic base patterns. */
11005 static const char *
11006 get_some_local_dynamic_name (void)
11010 if (cfun
->machine
->some_ld_name
)
11011 return cfun
->machine
->some_ld_name
;
11013 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11015 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
11016 return cfun
->machine
->some_ld_name
;
11018 gcc_unreachable ();
11022 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
11027 && GET_CODE (x
) == SYMBOL_REF
11028 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
11030 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
11037 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11038 We need to emit DTP-relative relocations. */
11041 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
11046 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
11049 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
11052 gcc_unreachable ();
11054 output_addr_const (file
, x
);
11058 /* Do whatever processing is required at the end of a file. */
11061 sparc_file_end (void)
11063 /* If we need to emit the special GOT helper function, do so now. */
11064 if (got_helper_rtx
)
11066 const char *name
= XSTR (got_helper_rtx
, 0);
11067 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
11068 #ifdef DWARF2_UNWIND_INFO
11072 if (USE_HIDDEN_LINKONCE
)
11074 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
11075 get_identifier (name
),
11076 build_function_type_list (void_type_node
,
11078 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
11079 NULL_TREE
, void_type_node
);
11080 TREE_PUBLIC (decl
) = 1;
11081 TREE_STATIC (decl
) = 1;
11082 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
11083 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
11084 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
11085 resolve_unique_section (decl
, 0, flag_function_sections
);
11086 allocate_struct_function (decl
, true);
11087 cfun
->is_thunk
= 1;
11088 current_function_decl
= decl
;
11089 init_varasm_status ();
11090 assemble_start_function (decl
, name
);
11094 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
11095 switch_to_section (text_section
);
11097 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
11098 ASM_OUTPUT_LABEL (asm_out_file
, name
);
11101 #ifdef DWARF2_UNWIND_INFO
11102 do_cfi
= dwarf2out_do_cfi_asm ();
11104 fprintf (asm_out_file
, "\t.cfi_startproc\n");
11106 if (flag_delayed_branch
)
11107 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11108 reg_name
, reg_name
);
11110 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11111 reg_name
, reg_name
);
11112 #ifdef DWARF2_UNWIND_INFO
11114 fprintf (asm_out_file
, "\t.cfi_endproc\n");
11118 if (NEED_INDICATE_EXEC_STACK
)
11119 file_end_indicate_exec_stack ();
11121 #ifdef TARGET_SOLARIS
11122 solaris_file_end ();
11126 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11127 /* Implement TARGET_MANGLE_TYPE. */
11129 static const char *
11130 sparc_mangle_type (const_tree type
)
11133 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
11134 && TARGET_LONG_DOUBLE_128
)
11137 /* For all other types, use normal C++ mangling. */
11142 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11143 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11144 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11147 sparc_emit_membar_for_model (enum memmodel model
,
11148 int load_store
, int before_after
)
11150 /* Bits for the MEMBAR mmask field. */
11151 const int LoadLoad
= 1;
11152 const int StoreLoad
= 2;
11153 const int LoadStore
= 4;
11154 const int StoreStore
= 8;
11156 int mm
= 0, implied
= 0;
11158 switch (sparc_memory_model
)
11161 /* Sequential Consistency. All memory transactions are immediately
11162 visible in sequential execution order. No barriers needed. */
11163 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
11167 /* Total Store Ordering: all memory transactions with store semantics
11168 are followed by an implied StoreStore. */
11169 implied
|= StoreStore
;
11173 /* Partial Store Ordering: all memory transactions with load semantics
11174 are followed by an implied LoadLoad | LoadStore. */
11175 implied
|= LoadLoad
| LoadStore
;
11177 /* If we're not looking for a raw barrer (before+after), then atomic
11178 operations get the benefit of being both load and store. */
11179 if (load_store
== 3 && before_after
== 2)
11180 implied
|= StoreLoad
| StoreStore
;
11184 /* Relaxed Memory Ordering: no implicit bits. */
11188 gcc_unreachable ();
11191 if (before_after
& 1)
11193 if (model
== MEMMODEL_RELEASE
11194 || model
== MEMMODEL_ACQ_REL
11195 || model
== MEMMODEL_SEQ_CST
)
11197 if (load_store
& 1)
11198 mm
|= LoadLoad
| StoreLoad
;
11199 if (load_store
& 2)
11200 mm
|= LoadStore
| StoreStore
;
11203 if (before_after
& 2)
11205 if (model
== MEMMODEL_ACQUIRE
11206 || model
== MEMMODEL_ACQ_REL
11207 || model
== MEMMODEL_SEQ_CST
)
11209 if (load_store
& 1)
11210 mm
|= LoadLoad
| LoadStore
;
11211 if (load_store
& 2)
11212 mm
|= StoreLoad
| StoreStore
;
11216 /* Remove the bits implied by the system memory model. */
11219 /* For raw barriers (before+after), always emit a barrier.
11220 This will become a compile-time barrier if needed. */
11221 if (mm
|| before_after
== 3)
11222 emit_insn (gen_membar (GEN_INT (mm
)));
11225 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11226 compare and swap on the word containing the byte or half-word. */
11229 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
11230 rtx oldval
, rtx newval
)
11232 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
11233 rtx addr
= gen_reg_rtx (Pmode
);
11234 rtx off
= gen_reg_rtx (SImode
);
11235 rtx oldv
= gen_reg_rtx (SImode
);
11236 rtx newv
= gen_reg_rtx (SImode
);
11237 rtx oldvalue
= gen_reg_rtx (SImode
);
11238 rtx newvalue
= gen_reg_rtx (SImode
);
11239 rtx res
= gen_reg_rtx (SImode
);
11240 rtx resv
= gen_reg_rtx (SImode
);
11241 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
11243 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
11244 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
11246 if (Pmode
!= SImode
)
11247 addr1
= gen_lowpart (SImode
, addr1
);
11248 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11249 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
11251 memsi
= gen_rtx_MEM (SImode
, addr
);
11252 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
11253 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
11255 val
= copy_to_reg (memsi
);
11257 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11258 gen_rtx_XOR (SImode
, off
,
11259 GEN_INT (GET_MODE (mem
) == QImode
11262 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11263 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
11265 if (GET_MODE (mem
) == QImode
)
11266 mask
= force_reg (SImode
, GEN_INT (0xff));
11268 mask
= force_reg (SImode
, GEN_INT (0xffff));
11270 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
11271 gen_rtx_ASHIFT (SImode
, mask
, off
)));
11273 emit_insn (gen_rtx_SET (VOIDmode
, val
,
11274 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11277 oldval
= gen_lowpart (SImode
, oldval
);
11278 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11279 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
11281 newval
= gen_lowpart_common (SImode
, newval
);
11282 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11283 gen_rtx_ASHIFT (SImode
, newval
, off
)));
11285 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11286 gen_rtx_AND (SImode
, oldv
, mask
)));
11288 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11289 gen_rtx_AND (SImode
, newv
, mask
)));
11291 end_label
= gen_label_rtx ();
11292 loop_label
= gen_label_rtx ();
11293 emit_label (loop_label
);
11295 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
11296 gen_rtx_IOR (SImode
, oldv
, val
)));
11298 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
11299 gen_rtx_IOR (SImode
, newv
, val
)));
11301 emit_move_insn (bool_result
, const1_rtx
);
11303 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
11305 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
11307 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
11308 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11311 emit_move_insn (bool_result
, const0_rtx
);
11313 cc
= gen_compare_reg_1 (NE
, resv
, val
);
11314 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
11316 /* Use cbranchcc4 to separate the compare and branch! */
11317 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
11318 cc
, const0_rtx
, loop_label
));
11320 emit_label (end_label
);
11322 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11323 gen_rtx_AND (SImode
, res
, mask
)));
11325 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11326 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
11328 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
11331 /* Expand code to perform a compare-and-swap. */
11334 sparc_expand_compare_and_swap (rtx operands
[])
11336 rtx bval
, retval
, mem
, oldval
, newval
;
11337 enum machine_mode mode
;
11338 enum memmodel model
;
11340 bval
= operands
[0];
11341 retval
= operands
[1];
11343 oldval
= operands
[3];
11344 newval
= operands
[4];
11345 model
= (enum memmodel
) INTVAL (operands
[6]);
11346 mode
= GET_MODE (mem
);
11348 sparc_emit_membar_for_model (model
, 3, 1);
11350 if (reg_overlap_mentioned_p (retval
, oldval
))
11351 oldval
= copy_to_reg (oldval
);
11353 if (mode
== QImode
|| mode
== HImode
)
11354 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
11357 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
11360 if (mode
== SImode
)
11361 gen
= gen_atomic_compare_and_swapsi_1
;
11363 gen
= gen_atomic_compare_and_swapdi_1
;
11364 emit_insn (gen (retval
, mem
, oldval
, newval
));
11366 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
11368 convert_move (bval
, x
, 1);
11371 sparc_emit_membar_for_model (model
, 3, 2);
11375 sparc_expand_vec_perm_bmask (enum machine_mode vmode
, rtx sel
)
11379 sel
= gen_lowpart (DImode
, sel
);
11383 /* inp = xxxxxxxAxxxxxxxB */
11384 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11385 NULL_RTX
, 1, OPTAB_DIRECT
);
11386 /* t_1 = ....xxxxxxxAxxx. */
11387 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11388 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
11389 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11390 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
11391 /* sel = .......B */
11392 /* t_1 = ...A.... */
11393 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11394 /* sel = ...A...B */
11395 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
11396 /* sel = AAAABBBB * 4 */
11397 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
11398 /* sel = { A*4, A*4+1, A*4+2, ... } */
11402 /* inp = xxxAxxxBxxxCxxxD */
11403 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11404 NULL_RTX
, 1, OPTAB_DIRECT
);
11405 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11406 NULL_RTX
, 1, OPTAB_DIRECT
);
11407 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
11408 NULL_RTX
, 1, OPTAB_DIRECT
);
11409 /* t_1 = ..xxxAxxxBxxxCxx */
11410 /* t_2 = ....xxxAxxxBxxxC */
11411 /* t_3 = ......xxxAxxxBxx */
11412 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11414 NULL_RTX
, 1, OPTAB_DIRECT
);
11415 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11417 NULL_RTX
, 1, OPTAB_DIRECT
);
11418 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
11419 GEN_INT (0x070000),
11420 NULL_RTX
, 1, OPTAB_DIRECT
);
11421 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
11422 GEN_INT (0x07000000),
11423 NULL_RTX
, 1, OPTAB_DIRECT
);
11424 /* sel = .......D */
11425 /* t_1 = .....C.. */
11426 /* t_2 = ...B.... */
11427 /* t_3 = .A...... */
11428 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11429 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
11430 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
11431 /* sel = .A.B.C.D */
11432 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
11433 /* sel = AABBCCDD * 2 */
11434 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
11435 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11439 /* input = xAxBxCxDxExFxGxH */
11440 sel
= expand_simple_binop (DImode
, AND
, sel
,
11441 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
11443 NULL_RTX
, 1, OPTAB_DIRECT
);
11444 /* sel = .A.B.C.D.E.F.G.H */
11445 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
11446 NULL_RTX
, 1, OPTAB_DIRECT
);
11447 /* t_1 = ..A.B.C.D.E.F.G. */
11448 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11449 NULL_RTX
, 1, OPTAB_DIRECT
);
11450 /* sel = .AABBCCDDEEFFGGH */
11451 sel
= expand_simple_binop (DImode
, AND
, sel
,
11452 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
11454 NULL_RTX
, 1, OPTAB_DIRECT
);
11455 /* sel = ..AB..CD..EF..GH */
11456 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11457 NULL_RTX
, 1, OPTAB_DIRECT
);
11458 /* t_1 = ....AB..CD..EF.. */
11459 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11460 NULL_RTX
, 1, OPTAB_DIRECT
);
11461 /* sel = ..ABABCDCDEFEFGH */
11462 sel
= expand_simple_binop (DImode
, AND
, sel
,
11463 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
11464 NULL_RTX
, 1, OPTAB_DIRECT
);
11465 /* sel = ....ABCD....EFGH */
11466 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11467 NULL_RTX
, 1, OPTAB_DIRECT
);
11468 /* t_1 = ........ABCD.... */
11469 sel
= gen_lowpart (SImode
, sel
);
11470 t_1
= gen_lowpart (SImode
, t_1
);
11474 gcc_unreachable ();
11477 /* Always perform the final addition/merge within the bmask insn. */
11478 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, t_1
));
11481 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11484 sparc_frame_pointer_required (void)
11486 /* If the stack pointer is dynamically modified in the function, it cannot
11487 serve as the frame pointer. */
11488 if (cfun
->calls_alloca
)
11491 /* If the function receives nonlocal gotos, it needs to save the frame
11492 pointer in the nonlocal_goto_save_area object. */
11493 if (cfun
->has_nonlocal_label
)
11496 /* In flat mode, that's it. */
11500 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11501 return !(crtl
->is_leaf
&& only_leaf_regs_used ());
11504 /* The way this is structured, we can't eliminate SFP in favor of SP
11505 if the frame pointer is required: we want to use the SFP->HFP elimination
11506 in that case. But the test in update_eliminables doesn't know we are
11507 assuming below that we only do the former elimination. */
11510 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
11512 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
11515 /* Return the hard frame pointer directly to bypass the stack bias. */
11518 sparc_builtin_setjmp_frame_value (void)
11520 return hard_frame_pointer_rtx
;
11523 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
11524 they won't be allocated. */
11527 sparc_conditional_register_usage (void)
11529 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
11531 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
11532 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
11534 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
11535 /* then honor it. */
11536 if (TARGET_ARCH32
&& fixed_regs
[5])
11538 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
11543 for (regno
= SPARC_FIRST_V9_FP_REG
;
11544 regno
<= SPARC_LAST_V9_FP_REG
;
11546 fixed_regs
[regno
] = 1;
11547 /* %fcc0 is used by v8 and v9. */
11548 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
11549 regno
<= SPARC_LAST_V9_FCC_REG
;
11551 fixed_regs
[regno
] = 1;
11556 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
11557 fixed_regs
[regno
] = 1;
11559 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
11560 /* then honor it. Likewise with g3 and g4. */
11561 if (fixed_regs
[2] == 2)
11562 fixed_regs
[2] = ! TARGET_APP_REGS
;
11563 if (fixed_regs
[3] == 2)
11564 fixed_regs
[3] = ! TARGET_APP_REGS
;
11565 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
11566 fixed_regs
[4] = ! TARGET_APP_REGS
;
11567 else if (TARGET_CM_EMBMEDANY
)
11569 else if (fixed_regs
[4] == 2)
11574 /* Disable leaf functions. */
11575 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
11576 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
11577 leaf_reg_remap
[regno
] = regno
;
11580 global_regs
[SPARC_GSR_REG
] = 1;
11583 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
11585 - We can't load constants into FP registers.
11586 - We can't load FP constants into integer registers when soft-float,
11587 because there is no soft-float pattern with a r/F constraint.
11588 - We can't load FP constants into integer registers for TFmode unless
11589 it is 0.0L, because there is no movtf pattern with a r/F constraint.
11590 - Try and reload integer constants (symbolic or otherwise) back into
11591 registers directly, rather than having them dumped to memory. */
11594 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
11596 enum machine_mode mode
= GET_MODE (x
);
11597 if (CONSTANT_P (x
))
11599 if (FP_REG_CLASS_P (rclass
)
11600 || rclass
== GENERAL_OR_FP_REGS
11601 || rclass
== GENERAL_OR_EXTRA_FP_REGS
11602 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
11603 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
11606 if (GET_MODE_CLASS (mode
) == MODE_INT
)
11607 return GENERAL_REGS
;
11609 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
11611 if (! FP_REG_CLASS_P (rclass
)
11612 || !(const_zero_operand (x
, mode
)
11613 || const_all_ones_operand (x
, mode
)))
11620 && (rclass
== EXTRA_FP_REGS
11621 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
11623 int regno
= true_regnum (x
);
11625 if (SPARC_INT_REG_P (regno
))
11626 return (rclass
== EXTRA_FP_REGS
11627 ? FP_REGS
: GENERAL_OR_FP_REGS
);
11633 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
11634 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
11637 output_v8plus_mult (rtx insn
, rtx
*operands
, const char *opcode
)
11641 gcc_assert (! TARGET_ARCH64
);
11643 if (sparc_check_64 (operands
[1], insn
) <= 0)
11644 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
11645 if (which_alternative
== 1)
11646 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
11647 if (GET_CODE (operands
[2]) == CONST_INT
)
11649 if (which_alternative
== 1)
11651 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
11652 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
11653 output_asm_insn (mulstr
, operands
);
11654 return "srlx\t%L0, 32, %H0";
11658 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
11659 output_asm_insn ("or\t%L1, %3, %3", operands
);
11660 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
11661 output_asm_insn (mulstr
, operands
);
11662 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
11663 return "mov\t%3, %L0";
11666 else if (rtx_equal_p (operands
[1], operands
[2]))
11668 if (which_alternative
== 1)
11670 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
11671 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
11672 output_asm_insn (mulstr
, operands
);
11673 return "srlx\t%L0, 32, %H0";
11677 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
11678 output_asm_insn ("or\t%L1, %3, %3", operands
);
11679 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
11680 output_asm_insn (mulstr
, operands
);
11681 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
11682 return "mov\t%3, %L0";
11685 if (sparc_check_64 (operands
[2], insn
) <= 0)
11686 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
11687 if (which_alternative
== 1)
11689 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
11690 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
11691 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
11692 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
11693 output_asm_insn (mulstr
, operands
);
11694 return "srlx\t%L0, 32, %H0";
11698 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
11699 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
11700 output_asm_insn ("or\t%L1, %3, %3", operands
);
11701 output_asm_insn ("or\t%L2, %4, %4", operands
);
11702 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
11703 output_asm_insn (mulstr
, operands
);
11704 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
11705 return "mov\t%3, %L0";
11709 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
11710 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
11711 and INNER_MODE are the modes describing TARGET. */
11714 vector_init_bshuffle (rtx target
, rtx elt
, enum machine_mode mode
,
11715 enum machine_mode inner_mode
)
11717 rtx t1
, final_insn
;
11720 t1
= gen_reg_rtx (mode
);
11722 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
11723 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
11728 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
11729 bmask
= 0x45674567;
11732 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
11733 bmask
= 0x67676767;
11736 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
11737 bmask
= 0x77777777;
11740 gcc_unreachable ();
11743 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), CONST0_RTX (SImode
),
11744 force_reg (SImode
, GEN_INT (bmask
))));
11745 emit_insn (final_insn
);
11748 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
11749 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
11752 vector_init_fpmerge (rtx target
, rtx elt
)
11754 rtx t1
, t2
, t2_low
, t3
, t3_low
;
11756 t1
= gen_reg_rtx (V4QImode
);
11757 elt
= convert_modes (SImode
, QImode
, elt
, true);
11758 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
11760 t2
= gen_reg_rtx (V8QImode
);
11761 t2_low
= gen_lowpart (V4QImode
, t2
);
11762 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
11764 t3
= gen_reg_rtx (V8QImode
);
11765 t3_low
= gen_lowpart (V4QImode
, t3
);
11766 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
11768 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
11771 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
11772 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
11775 vector_init_faligndata (rtx target
, rtx elt
)
11777 rtx t1
= gen_reg_rtx (V4HImode
);
11780 elt
= convert_modes (SImode
, HImode
, elt
, true);
11781 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
11783 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
11784 force_reg (SImode
, GEN_INT (6)),
11787 for (i
= 0; i
< 4; i
++)
11788 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
11791 /* Emit code to initialize TARGET to values for individual fields VALS. */
11794 sparc_expand_vector_init (rtx target
, rtx vals
)
11796 const enum machine_mode mode
= GET_MODE (target
);
11797 const enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
11798 const int n_elts
= GET_MODE_NUNITS (mode
);
11804 for (i
= 0; i
< n_elts
; i
++)
11806 rtx x
= XVECEXP (vals
, 0, i
);
11807 if (!CONSTANT_P (x
))
11810 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
11816 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
11820 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
11822 if (GET_MODE_SIZE (inner_mode
) == 4)
11824 emit_move_insn (gen_lowpart (SImode
, target
),
11825 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
11828 else if (GET_MODE_SIZE (inner_mode
) == 8)
11830 emit_move_insn (gen_lowpart (DImode
, target
),
11831 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
11835 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
11836 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
11838 emit_move_insn (gen_highpart (word_mode
, target
),
11839 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
11840 emit_move_insn (gen_lowpart (word_mode
, target
),
11841 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
11845 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
11849 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
11852 if (mode
== V8QImode
)
11854 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
11857 if (mode
== V4HImode
)
11859 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
11864 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
11865 for (i
= 0; i
< n_elts
; i
++)
11866 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
11867 i
* GET_MODE_SIZE (inner_mode
)),
11868 XVECEXP (vals
, 0, i
));
11869 emit_move_insn (target
, mem
);
11872 /* Implement TARGET_SECONDARY_RELOAD. */
11875 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
11876 enum machine_mode mode
, secondary_reload_info
*sri
)
11878 enum reg_class rclass
= (enum reg_class
) rclass_i
;
11880 sri
->icode
= CODE_FOR_nothing
;
11881 sri
->extra_cost
= 0;
11883 /* We need a temporary when loading/storing a HImode/QImode value
11884 between memory and the FPU registers. This can happen when combine puts
11885 a paradoxical subreg in a float/fix conversion insn. */
11886 if (FP_REG_CLASS_P (rclass
)
11887 && (mode
== HImode
|| mode
== QImode
)
11888 && (GET_CODE (x
) == MEM
11889 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
11890 && true_regnum (x
) == -1)))
11891 return GENERAL_REGS
;
11893 /* On 32-bit we need a temporary when loading/storing a DFmode value
11894 between unaligned memory and the upper FPU registers. */
11896 && rclass
== EXTRA_FP_REGS
11898 && GET_CODE (x
) == MEM
11899 && ! mem_min_alignment (x
, 8))
11902 if (((TARGET_CM_MEDANY
11903 && symbolic_operand (x
, mode
))
11904 || (TARGET_CM_EMBMEDANY
11905 && text_segment_operand (x
, mode
)))
11909 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
11911 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
11915 if (TARGET_VIS3
&& TARGET_ARCH32
)
11917 int regno
= true_regnum (x
);
11919 /* When using VIS3 fp<-->int register moves, on 32-bit we have
11920 to move 8-byte values in 4-byte pieces. This only works via
11921 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
11922 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
11923 an FP_REGS intermediate move. */
11924 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
11925 || ((general_or_i64_p (rclass
)
11926 || rclass
== GENERAL_OR_FP_REGS
)
11927 && SPARC_FP_REG_P (regno
)))
11929 sri
->extra_cost
= 2;
11937 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
11938 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
11941 sparc_expand_conditional_move (enum machine_mode mode
, rtx
*operands
)
11943 enum rtx_code rc
= GET_CODE (operands
[1]);
11944 enum machine_mode cmp_mode
;
11945 rtx cc_reg
, dst
, cmp
;
11948 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
11951 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
11952 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
11954 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
11955 rc
= GET_CODE (cmp
);
11958 if (! rtx_equal_p (operands
[2], dst
)
11959 && ! rtx_equal_p (operands
[3], dst
))
11961 if (reg_overlap_mentioned_p (dst
, cmp
))
11962 dst
= gen_reg_rtx (mode
);
11964 emit_move_insn (dst
, operands
[3]);
11966 else if (operands
[2] == dst
)
11968 operands
[2] = operands
[3];
11970 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
11971 rc
= reverse_condition_maybe_unordered (rc
);
11973 rc
= reverse_condition (rc
);
11976 if (XEXP (cmp
, 1) == const0_rtx
11977 && GET_CODE (XEXP (cmp
, 0)) == REG
11978 && cmp_mode
== DImode
11979 && v9_regcmp_p (rc
))
11980 cc_reg
= XEXP (cmp
, 0);
11982 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
11984 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
11986 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
11987 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
11989 if (dst
!= operands
[0])
11990 emit_move_insn (operands
[0], dst
);
11995 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
11996 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
11997 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
11998 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
11999 code to be used for the condition mask. */
12002 sparc_expand_vcond (enum machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
12004 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
12005 enum rtx_code code
= GET_CODE (operands
[3]);
12007 mask
= gen_reg_rtx (Pmode
);
12008 cop0
= operands
[4];
12009 cop1
= operands
[5];
12010 if (code
== LT
|| code
== GE
)
12014 code
= swap_condition (code
);
12015 t
= cop0
; cop0
= cop1
; cop1
= t
;
12018 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
12020 fcmp
= gen_rtx_UNSPEC (Pmode
,
12021 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
12024 cmask
= gen_rtx_UNSPEC (DImode
,
12025 gen_rtvec (2, mask
, gsr
),
12028 bshuf
= gen_rtx_UNSPEC (mode
,
12029 gen_rtvec (3, operands
[1], operands
[2], gsr
),
12032 emit_insn (gen_rtx_SET (VOIDmode
, mask
, fcmp
));
12033 emit_insn (gen_rtx_SET (VOIDmode
, gsr
, cmask
));
12035 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], bshuf
));
12038 /* On sparc, any mode which naturally allocates into the float
12039 registers should return 4 here. */
12042 sparc_regmode_natural_size (enum machine_mode mode
)
12044 int size
= UNITS_PER_WORD
;
12048 enum mode_class mclass
= GET_MODE_CLASS (mode
);
12050 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
12057 /* Return TRUE if it is a good idea to tie two pseudo registers
12058 when one has mode MODE1 and one has mode MODE2.
12059 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12060 for any hard reg, then this must be FALSE for correct output.
12062 For V9 we have to deal with the fact that only the lower 32 floating
12063 point registers are 32-bit addressable. */
12066 sparc_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
12068 enum mode_class mclass1
, mclass2
;
12069 unsigned short size1
, size2
;
12071 if (mode1
== mode2
)
12074 mclass1
= GET_MODE_CLASS (mode1
);
12075 mclass2
= GET_MODE_CLASS (mode2
);
12076 if (mclass1
!= mclass2
)
12082 /* Classes are the same and we are V9 so we have to deal with upper
12083 vs. lower floating point registers. If one of the modes is a
12084 4-byte mode, and the other is not, we have to mark them as not
12085 tieable because only the lower 32 floating point register are
12086 addressable 32-bits at a time.
12088 We can't just test explicitly for SFmode, otherwise we won't
12089 cover the vector mode cases properly. */
12091 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
12094 size1
= GET_MODE_SIZE (mode1
);
12095 size2
= GET_MODE_SIZE (mode2
);
12096 if ((size1
> 4 && size2
== 4)
12097 || (size2
> 4 && size1
== 4))
12103 #include "gt-sparc.h"