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[gcc.git] / gcc / config / sparc / sparc.c
1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21 #include <stdio.h>
22 #include "config.h"
23 #include "tree.h"
24 #include "rtl.h"
25 #include "regs.h"
26 #include "hard-reg-set.h"
27 #include "real.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
31 #include "output.h"
32 #include "insn-attr.h"
33 #include "flags.h"
34 #include "expr.h"
35 #include "recog.h"
36
37 /* Global variables for machine-dependent things. */
38
39 /* Save the operands last given to a compare for use when we
40 generate a scc or bcc insn. */
41
42 rtx sparc_compare_op0, sparc_compare_op1;
43
44 /* We may need an epilogue if we spill too many registers.
45 If this is non-zero, then we branch here for the epilogue. */
46 static rtx leaf_label;
47
48 #ifdef LEAF_REGISTERS
49
50 /* Vector to say how input registers are mapped to output
51 registers. FRAME_POINTER_REGNUM cannot be remapped by
52 this function to eliminate it. You must use -fomit-frame-pointer
53 to get that. */
54 char leaf_reg_remap[] =
55 { 0, 1, 2, 3, 4, 5, 6, 7,
56 -1, -1, -1, -1, -1, -1, 14, -1,
57 -1, -1, -1, -1, -1, -1, -1, -1,
58 8, 9, 10, 11, 12, 13, -1, 15,
59
60 32, 33, 34, 35, 36, 37, 38, 39,
61 40, 41, 42, 43, 44, 45, 46, 47,
62 48, 49, 50, 51, 52, 53, 54, 55,
63 56, 57, 58, 59, 60, 61, 62, 63};
64
65 char leaf_reg_backmap[] =
66 { 0, 1, 2, 3, 4, 5, 6, 7,
67 24, 25, 26, 27, 28, 29, 14, 31,
68 -1, -1, -1, -1, -1, -1, -1, -1,
69 -1, -1, -1, -1, -1, -1, -1, -1,
70
71 32, 33, 34, 35, 36, 37, 38, 39,
72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63};
75 #endif
76
77 /* Global variables set by FUNCTION_PROLOGUE. */
78 /* Size of frame. Need to know this to emit return insns from
79 leaf procedures. */
80 int apparent_fsize;
81 int actual_fsize;
82
83 /* Name of where we pretend to think the frame pointer points.
84 Normally, this is "%fp", but if we are in a leaf procedure,
85 this is "%sp+something". */
86 char *frame_base_name;
87
88 static rtx find_addr_reg ();
89
90 /* Return non-zero only if OP is a register of mode MODE,
91 or const0_rtx. */
92 int
93 reg_or_0_operand (op, mode)
94 rtx op;
95 enum machine_mode mode;
96 {
97 if (op == const0_rtx || register_operand (op, mode))
98 return 1;
99 if (GET_CODE (op) == CONST_DOUBLE
100 && CONST_DOUBLE_HIGH (op) == 0
101 && CONST_DOUBLE_LOW (op) == 0)
102 return 1;
103 return 0;
104 }
105
106 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
107 int
108 restore_operand (op, mode)
109 rtx op;
110 enum machine_mode mode;
111 {
112 return (GET_CODE (op) == REG && GET_MODE (op) == mode
113 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
114 }
115
116 /* Call insn on SPARC can take a PC-relative constant address, or any regular
117 memory address. */
118
119 int
120 call_operand (op, mode)
121 rtx op;
122 enum machine_mode mode;
123 {
124 if (GET_CODE (op) != MEM)
125 abort ();
126 op = XEXP (op, 0);
127 return (CONSTANT_P (op) || memory_address_p (Pmode, op));
128 }
129
130 int
131 call_operand_address (op, mode)
132 rtx op;
133 enum machine_mode mode;
134 {
135 return (CONSTANT_P (op) || memory_address_p (Pmode, op));
136 }
137
138 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
139 reference and a constant. */
140
141 int
142 symbolic_operand (op, mode)
143 register rtx op;
144 enum machine_mode mode;
145 {
146 switch (GET_CODE (op))
147 {
148 case SYMBOL_REF:
149 case LABEL_REF:
150 return 1;
151
152 case CONST:
153 op = XEXP (op, 0);
154 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
155 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
156 && GET_CODE (XEXP (op, 1)) == CONST_INT);
157
158 /* ??? This clause seems to be irrelevant. */
159 case CONST_DOUBLE:
160 return GET_MODE (op) == mode;
161
162 default:
163 return 0;
164 }
165 }
166
167 /* Return truth value of statement that OP is a symbolic memory
168 operand of mode MODE. */
169
170 int
171 symbolic_memory_operand (op, mode)
172 rtx op;
173 enum machine_mode mode;
174 {
175 if (GET_CODE (op) == SUBREG)
176 op = SUBREG_REG (op);
177 if (GET_CODE (op) != MEM)
178 return 0;
179 op = XEXP (op, 0);
180 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
181 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
182 }
183
184 /* Return 1 if the operand is either a register or a memory operand that is
185 not symbolic. */
186
187 int
188 reg_or_nonsymb_mem_operand (op, mode)
189 register rtx op;
190 enum machine_mode mode;
191 {
192 if (register_operand (op, mode))
193 return 1;
194
195 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
196 return 1;
197
198 return 0;
199 }
200
201 int
202 sparc_operand (op, mode)
203 rtx op;
204 enum machine_mode mode;
205 {
206 if (register_operand (op, mode))
207 return 1;
208 if (GET_CODE (op) == CONST_INT)
209 return SMALL_INT (op);
210 if (GET_MODE (op) != mode)
211 return 0;
212 if (GET_CODE (op) == SUBREG)
213 op = SUBREG_REG (op);
214 if (GET_CODE (op) != MEM)
215 return 0;
216
217 op = XEXP (op, 0);
218 if (GET_CODE (op) == LO_SUM)
219 return (GET_CODE (XEXP (op, 0)) == REG
220 && symbolic_operand (XEXP (op, 1), Pmode));
221 return memory_address_p (mode, op);
222 }
223
224 int
225 move_operand (op, mode)
226 rtx op;
227 enum machine_mode mode;
228 {
229 if (mode == DImode && arith_double_operand (op, mode))
230 return 1;
231 if (register_operand (op, mode))
232 return 1;
233 if (GET_CODE (op) == CONST_INT)
234 return (SMALL_INT (op) || (INTVAL (op) & 0x3ff) == 0);
235
236 if (GET_MODE (op) != mode)
237 return 0;
238 if (GET_CODE (op) == SUBREG)
239 op = SUBREG_REG (op);
240 if (GET_CODE (op) != MEM)
241 return 0;
242 op = XEXP (op, 0);
243 if (GET_CODE (op) == LO_SUM)
244 return (register_operand (XEXP (op, 0), Pmode)
245 && CONSTANT_P (XEXP (op, 1)));
246 return memory_address_p (mode, op);
247 }
248
249 int
250 move_pic_label (op, mode)
251 rtx op;
252 enum machine_mode mode;
253 {
254 /* Special case for PIC. */
255 if (flag_pic && GET_CODE (op) == LABEL_REF)
256 return 1;
257 return 0;
258 }
259 \f
260 /* The rtx for the global offset table which is a special form
261 that *is* a position independent symbolic constant. */
262 rtx pic_pc_rtx;
263
264 /* Ensure that we are not using patterns that are not OK with PIC. */
265
266 int
267 check_pic (i)
268 int i;
269 {
270 switch (flag_pic)
271 {
272 case 1:
273 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
274 || (GET_CODE (recog_operand[i]) == CONST
275 && ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
276 abort ();
277 case 2:
278 default:
279 return 1;
280 }
281 }
282
283 /* Return true if X is an address which needs a temporary register when
284 reloaded while generating PIC code. */
285
286 int
287 pic_address_needs_scratch (x)
288 rtx x;
289 {
290 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
291 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
292 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
293 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
294 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
295 return 1;
296
297 return 0;
298 }
299
300 int
301 memop (op, mode)
302 rtx op;
303 enum machine_mode mode;
304 {
305 if (GET_CODE (op) == MEM)
306 return (mode == VOIDmode || mode == GET_MODE (op));
307 return 0;
308 }
309
310 /* Return truth value of whether OP is EQ or NE. */
311
312 int
313 eq_or_neq (op, mode)
314 rtx op;
315 enum machine_mode mode;
316 {
317 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
318 }
319
320 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
321 or LTU for non-floating-point. We handle those specially. */
322
323 int
324 normal_comp_operator (op, mode)
325 rtx op;
326 enum machine_mode mode;
327 {
328 enum rtx_code code = GET_CODE (op);
329
330 if (GET_RTX_CLASS (code) != '<')
331 return 0;
332
333 if (GET_MODE (XEXP (op, 0)) == CCFPmode
334 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
335 return 1;
336
337 return (code != NE && code != EQ && code != GEU && code != LTU);
338 }
339
340 /* Return 1 if this is a comparison operator. This allows the use of
341 MATCH_OPERATOR to recognize all the branch insns. */
342
343 int
344 noov_compare_op (op, mode)
345 register rtx op;
346 enum machine_mode mode;
347 {
348 enum rtx_code code = GET_CODE (op);
349
350 if (GET_RTX_CLASS (code) != '<')
351 return 0;
352
353 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
354 /* These are the only branches which work with CC_NOOVmode. */
355 return (code == EQ || code == NE || code == GE || code == LT);
356 return 1;
357 }
358
359 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
360
361 int
362 extend_op (op, mode)
363 rtx op;
364 enum machine_mode mode;
365 {
366 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
367 }
368
369 /* Return nonzero if OP is an operator of mode MODE which can set
370 the condition codes explicitly. We do not include PLUS and MINUS
371 because these require CC_NOOVmode, which we handle explicitly. */
372
373 int
374 cc_arithop (op, mode)
375 rtx op;
376 enum machine_mode mode;
377 {
378 if (GET_CODE (op) == AND
379 || GET_CODE (op) == IOR
380 || GET_CODE (op) == XOR)
381 return 1;
382
383 return 0;
384 }
385
386 /* Return nonzero if OP is an operator of mode MODE which can bitwise
387 complement its second operand and set the condition codes explicitly. */
388
389 int
390 cc_arithopn (op, mode)
391 rtx op;
392 enum machine_mode mode;
393 {
394 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
395 and (xor ... (not ...)) to (not (xor ...)). */
396 return (GET_CODE (op) == AND
397 || GET_CODE (op) == IOR);
398 }
399 \f
400 /* Return true if OP is a register, or is a CONST_INT that can fit in a 13
401 bit immediate field. This is an acceptable SImode operand for most 3
402 address instructions. */
403
404 int
405 arith_operand (op, mode)
406 rtx op;
407 enum machine_mode mode;
408 {
409 return (register_operand (op, mode)
410 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
411 }
412
413 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
414 can fit in a 13 bit immediate field. This is an acceptable DImode operand
415 for most 3 address instructions. */
416
417 int
418 arith_double_operand (op, mode)
419 rtx op;
420 enum machine_mode mode;
421 {
422 return (register_operand (op, mode)
423 || (GET_CODE (op) == CONST_DOUBLE
424 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
425 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
426 && ((CONST_DOUBLE_HIGH (op) == -1
427 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
428 || (CONST_DOUBLE_HIGH (op) == 0
429 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))
430 || (GET_CODE (op) == CONST_INT
431 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
432 && (unsigned) (INTVAL (op) + 0x1000) < 0x2000));
433 }
434
435 /* Return truth value of whether OP is a integer which fits the
436 range constraining immediate operands in most three-address insns,
437 which have a 13 bit immediate field. */
438
439 int
440 small_int (op, mode)
441 rtx op;
442 enum machine_mode mode;
443 {
444 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
445 }
446
447 /* Return truth value of statement that OP is a call-clobbered register. */
448 int
449 clobbered_register (op, mode)
450 rtx op;
451 enum machine_mode mode;
452 {
453 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
454 }
455 \f
456 /* X and Y are two things to compare using CODE. Emit the compare insn and
457 return the rtx for register 0 in the proper mode. */
458
459 rtx
460 gen_compare_reg (code, x, y)
461 enum rtx_code code;
462 rtx x, y;
463 {
464 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
465 rtx cc_reg = gen_rtx (REG, mode, 0);
466
467 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
468 gen_rtx (COMPARE, mode, x, y)));
469
470 return cc_reg;
471 }
472 \f
473 /* Return nonzero if a return peephole merging return with
474 setting of output register is ok. */
475 int
476 leaf_return_peephole_ok ()
477 {
478 return (actual_fsize == 0);
479 }
480
481 /* Return nonzero if TRIAL can go into the function epilogue's
482 delay slot. SLOT is the slot we are trying to fill. */
483
484 int
485 eligible_for_epilogue_delay (trial, slot)
486 rtx trial;
487 int slot;
488 {
489 rtx pat, src;
490
491 if (slot >= 1)
492 return 0;
493 if (GET_CODE (trial) != INSN
494 || GET_CODE (PATTERN (trial)) != SET)
495 return 0;
496 if (get_attr_length (trial) != 1)
497 return 0;
498
499 /* In the case of a true leaf function, anything can go into the delay slot.
500 A delay slot only exists however if the frame size is zero, otherwise
501 we will put an insn to adjust the stack after the return. */
502 if (leaf_function)
503 {
504 if (leaf_return_peephole_ok ())
505 return (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE);
506 return 0;
507 }
508
509 /* Otherwise, only operations which can be done in tandem with
510 a `restore' insn can go into the delay slot. */
511 pat = PATTERN (trial);
512 if (GET_CODE (SET_DEST (pat)) != REG
513 || REGNO (SET_DEST (pat)) == 0
514 || REGNO (SET_DEST (pat)) >= 32
515 || REGNO (SET_DEST (pat)) < 24)
516 return 0;
517
518 src = SET_SRC (pat);
519 if (arith_operand (src, GET_MODE (src)))
520 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
521 if (arith_double_operand (src, GET_MODE (src)))
522 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
523 if (GET_CODE (src) == PLUS)
524 {
525 if (register_operand (XEXP (src, 0), SImode)
526 && arith_operand (XEXP (src, 1), SImode))
527 return 1;
528 if (register_operand (XEXP (src, 1), SImode)
529 && arith_operand (XEXP (src, 0), SImode))
530 return 1;
531 if (register_operand (XEXP (src, 0), DImode)
532 && arith_double_operand (XEXP (src, 1), DImode))
533 return 1;
534 if (register_operand (XEXP (src, 1), DImode)
535 && arith_double_operand (XEXP (src, 0), DImode))
536 return 1;
537 }
538 if (GET_CODE (src) == MINUS
539 && register_operand (XEXP (src, 0), SImode)
540 && small_int (XEXP (src, 1), VOIDmode))
541 return 1;
542 if (GET_CODE (src) == MINUS
543 && register_operand (XEXP (src, 0), DImode)
544 && !register_operand (XEXP (src, 1), DImode)
545 && arith_double_operand (XEXP (src, 1), DImode))
546 return 1;
547 return 0;
548 }
549
550 int
551 short_branch (uid1, uid2)
552 int uid1, uid2;
553 {
554 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
555 if (delta + 1024 < 2048)
556 return 1;
557 /* warning ("long branch, distance %d", delta); */
558 return 0;
559 }
560
561 /* Return non-zero if REG is not used after INSN.
562 We assume REG is a reload reg, and therefore does
563 not live past labels or calls or jumps. */
564 int
565 reg_unused_after (reg, insn)
566 rtx reg;
567 rtx insn;
568 {
569 enum rtx_code code, prev_code = UNKNOWN;
570
571 while (insn = NEXT_INSN (insn))
572 {
573 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
574 return 1;
575
576 code = GET_CODE (insn);
577 if (GET_CODE (insn) == CODE_LABEL)
578 return 1;
579
580 if (GET_RTX_CLASS (code) == 'i')
581 {
582 rtx set = single_set (insn);
583 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
584 if (set && in_src)
585 return 0;
586 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
587 return 1;
588 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
589 return 0;
590 }
591 prev_code = code;
592 }
593 return 1;
594 }
595 \f
596 /* Legitimize PIC addresses. If the address is already position-independent,
597 we return ORIG. Newly generated position-independent addresses go into a
598 reg. This is REG if non zero, otherwise we allocate register(s) as
599 necessary. If this is called during reload, and we need a second temp
600 register, then we use SCRATCH, which is provided via the
601 SECONDARY_INPUT_RELOAD_CLASS mechanism. */
602
603 rtx
604 legitimize_pic_address (orig, mode, reg, scratch)
605 rtx orig;
606 enum machine_mode mode;
607 rtx reg, scratch;
608 {
609 if (GET_CODE (orig) == SYMBOL_REF)
610 {
611 rtx pic_ref, address;
612 rtx insn;
613
614 if (reg == 0)
615 {
616 if (reload_in_progress || reload_completed)
617 abort ();
618 else
619 reg = gen_reg_rtx (Pmode);
620 }
621
622 if (flag_pic == 2)
623 {
624 /* If not during reload, allocate another temp reg here for loading
625 in the address, so that these instructions can be optimized
626 properly. */
627 rtx temp_reg = ((reload_in_progress || reload_completed)
628 ? reg : gen_reg_rtx (Pmode));
629
630 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
631 won't get confused into thinking that these two instructions
632 are loading in the true address of the symbol. If in the
633 future a PIC rtx exists, that should be used instead. */
634 emit_insn (gen_rtx (SET, VOIDmode, temp_reg,
635 gen_rtx (HIGH, Pmode,
636 gen_rtx (UNSPEC, Pmode,
637 gen_rtvec (1, orig),
638 0))));
639 emit_insn (gen_rtx (SET, VOIDmode, temp_reg,
640 gen_rtx (LO_SUM, Pmode, temp_reg,
641 gen_rtx (UNSPEC, Pmode,
642 gen_rtvec (1, orig),
643 0))));
644 address = temp_reg;
645 }
646 else
647 address = orig;
648
649 pic_ref = gen_rtx (MEM, Pmode,
650 gen_rtx (PLUS, Pmode,
651 pic_offset_table_rtx, address));
652 current_function_uses_pic_offset_table = 1;
653 RTX_UNCHANGING_P (pic_ref) = 1;
654 insn = emit_move_insn (reg, pic_ref);
655 /* Put a REG_EQUAL note on this insn, so that it can be optimized
656 by loop. */
657 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
658 REG_NOTES (insn));
659 return reg;
660 }
661 else if (GET_CODE (orig) == CONST)
662 {
663 rtx base, offset;
664
665 if (GET_CODE (XEXP (orig, 0)) == PLUS
666 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
667 return orig;
668
669 if (reg == 0)
670 {
671 if (reload_in_progress || reload_completed)
672 abort ();
673 else
674 reg = gen_reg_rtx (Pmode);
675 }
676
677 if (GET_CODE (XEXP (orig, 0)) == PLUS)
678 {
679 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode,
680 reg, 0);
681 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
682 base == reg ? 0 : reg, 0);
683 }
684 else
685 abort ();
686
687 if (GET_CODE (offset) == CONST_INT)
688 {
689 if (SMALL_INT (offset))
690 return plus_constant_for_output (base, INTVAL (offset));
691 else if (! reload_in_progress && ! reload_completed)
692 offset = force_reg (Pmode, offset);
693 /* We can't create any new registers during reload, so use the
694 SCRATCH reg provided by the reload_insi pattern. */
695 else if (scratch)
696 {
697 emit_move_insn (scratch, offset);
698 offset = scratch;
699 }
700 else
701 /* If we reach here, then the SECONDARY_INPUT_RELOAD_CLASS
702 macro needs to be adjusted so that a scratch reg is provided
703 for this address. */
704 abort ();
705 }
706 return gen_rtx (PLUS, Pmode, base, offset);
707 }
708 else if (GET_CODE (orig) == LABEL_REF)
709 current_function_uses_pic_offset_table = 1;
710
711 return orig;
712 }
713
714 /* Set up PIC-specific rtl. This should not cause any insns
715 to be emitted. */
716
717 void
718 initialize_pic ()
719 {
720 }
721
722 /* Emit special PIC prologues and epilogues. */
723
724 void
725 finalize_pic ()
726 {
727 /* The table we use to reference PIC data. */
728 rtx global_offset_table;
729 /* Labels to get the PC in the prologue of this function. */
730 rtx l1, l2;
731 rtx seq;
732 int orig_flag_pic = flag_pic;
733
734 if (current_function_uses_pic_offset_table == 0)
735 return;
736
737 if (! flag_pic)
738 abort ();
739
740 flag_pic = 0;
741 l1 = gen_label_rtx ();
742 l2 = gen_label_rtx ();
743
744 start_sequence ();
745
746 emit_label (l1);
747 /* Note that we pun calls and jumps here! */
748 emit_jump_insn (gen_rtx (PARALLEL, VOIDmode,
749 gen_rtvec (2,
750 gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, l2)),
751 gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 15), gen_rtx (LABEL_REF, VOIDmode, l2)))));
752 emit_label (l2);
753
754 /* Initialize every time through, since we can't easily
755 know this to be permanent. */
756 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
757 pic_pc_rtx = gen_rtx (CONST, Pmode,
758 gen_rtx (MINUS, Pmode,
759 global_offset_table,
760 gen_rtx (CONST, Pmode,
761 gen_rtx (MINUS, Pmode,
762 gen_rtx (LABEL_REF, VOIDmode, l1),
763 pc_rtx))));
764
765 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
766 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
767 emit_insn (gen_rtx (SET, VOIDmode,
768 pic_offset_table_rtx,
769 gen_rtx (LO_SUM, Pmode,
770 pic_offset_table_rtx, pic_pc_rtx)));
771 emit_insn (gen_rtx (SET, VOIDmode,
772 pic_offset_table_rtx,
773 gen_rtx (PLUS, Pmode,
774 pic_offset_table_rtx, gen_rtx (REG, Pmode, 15))));
775 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
776 LABEL_PRESERVE_P (l1) = 1;
777 LABEL_PRESERVE_P (l2) = 1;
778 flag_pic = orig_flag_pic;
779
780 seq = gen_sequence ();
781 end_sequence ();
782 emit_insn_after (seq, get_insns ());
783
784 /* Need to emit this whether or not we obey regdecls,
785 since setjmp/longjmp can cause life info to screw up. */
786 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
787 }
788 \f
789 /* For the SPARC, REG and REG+CONST is cost 0, REG+REG is cost 1,
790 and addresses involving symbolic constants are cost 2.
791
792 We make REG+REG slightly more expensive because it might keep
793 a register live for longer than we might like.
794
795 PIC addresses are very expensive.
796
797 It is no coincidence that this has the same structure
798 as GO_IF_LEGITIMATE_ADDRESS. */
799 int
800 sparc_address_cost (X)
801 rtx X;
802 {
803 #if 0
804 /* Handled before calling here. */
805 if (GET_CODE (X) == REG)
806 { return 1; }
807 #endif
808 if (GET_CODE (X) == PLUS)
809 {
810 if (GET_CODE (XEXP (X, 0)) == REG
811 && GET_CODE (XEXP (X, 1)) == REG)
812 return 2;
813 return 1;
814 }
815 else if (GET_CODE (X) == LO_SUM)
816 return 1;
817 else if (GET_CODE (X) == HIGH)
818 return 2;
819 return 4;
820 }
821 \f
822 /* Emit insns to move operands[1] into operands[0].
823
824 Return 1 if we have written out everything that needs to be done to
825 do the move. Otherwise, return 0 and the caller will emit the move
826 normally.
827
828 SCRATCH_REG if non zero can be used as a scratch register for the move
829 operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */
830
831 int
832 emit_move_sequence (operands, mode, scratch_reg)
833 rtx *operands;
834 enum machine_mode mode;
835 rtx scratch_reg;
836 {
837 register rtx operand0 = operands[0];
838 register rtx operand1 = operands[1];
839
840 /* Handle most common case first: storing into a register. */
841 if (register_operand (operand0, mode))
842 {
843 if (register_operand (operand1, mode)
844 || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1))
845 || (GET_CODE (operand1) == CONST_DOUBLE
846 && arith_double_operand (operand1, DImode))
847 || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode)
848 /* Only `general_operands' can come here, so MEM is ok. */
849 || GET_CODE (operand1) == MEM)
850 {
851 /* Run this case quickly. */
852 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
853 return 1;
854 }
855 }
856 else if (GET_CODE (operand0) == MEM)
857 {
858 if (register_operand (operand1, mode) || operand1 == const0_rtx)
859 {
860 /* Run this case quickly. */
861 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
862 return 1;
863 }
864 if (! reload_in_progress)
865 {
866 operands[0] = validize_mem (operand0);
867 operands[1] = operand1 = force_reg (mode, operand1);
868 }
869 }
870
871 /* Simplify the source if we need to. Must handle DImode HIGH operators
872 here because such a move needs a clobber added. */
873 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
874 || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode))
875 {
876 if (flag_pic && symbolic_operand (operand1, mode))
877 {
878 rtx temp_reg = reload_in_progress ? operand0 : 0;
879
880 operands[1] = legitimize_pic_address (operand1, mode, temp_reg,
881 scratch_reg);
882 }
883 else if (GET_CODE (operand1) == CONST_INT
884 ? (! SMALL_INT (operand1)
885 && (INTVAL (operand1) & 0x3ff) != 0)
886 : (GET_CODE (operand1) == CONST_DOUBLE
887 ? ! arith_double_operand (operand1, DImode)
888 : 1))
889 {
890 /* For DImode values, temp must be operand0 because of the way
891 HI and LO_SUM work. The LO_SUM operator only copies half of
892 the LSW from the dest of the HI operator. If the LO_SUM dest is
893 not the same as the HI dest, then the MSW of the LO_SUM dest will
894 never be set.
895
896 ??? The real problem here is that the ...(HI:DImode pattern emits
897 multiple instructions, and the ...(LO_SUM:DImode pattern emits
898 one instruction. This fails, because the compiler assumes that
899 LO_SUM copies all bits of the first operand to its dest. Better
900 would be to have the HI pattern emit one instruction and the
901 LO_SUM pattern multiple instructions. Even better would be
902 to use four rtl insns. */
903 rtx temp = ((reload_in_progress || mode == DImode)
904 ? operand0 : gen_reg_rtx (mode));
905
906 emit_insn (gen_rtx (SET, VOIDmode, temp,
907 gen_rtx (HIGH, mode, operand1)));
908 operands[1] = gen_rtx (LO_SUM, mode, temp, operand1);
909 }
910 }
911
912 if (GET_CODE (operand1) == LABEL_REF && flag_pic)
913 {
914 /* The procedure for doing this involves using a call instruction to
915 get the pc into o7. We need to indicate this explicitly because
916 the tablejump pattern assumes that it can use this value also. */
917 emit_insn (gen_rtx (PARALLEL, VOIDmode,
918 gen_rtvec (2,
919 gen_rtx (SET, VOIDmode, operand0,
920 operand1),
921 gen_rtx (SET, VOIDmode,
922 gen_rtx (REG, mode, 15),
923 pc_rtx))));
924 return 1;
925 }
926
927 /* Now have insn-emit do whatever it normally does. */
928 return 0;
929 }
930 \f
931 /* Return the best assembler insn template
932 for moving operands[1] into operands[0] as a fullword. */
933
934 char *
935 singlemove_string (operands)
936 rtx *operands;
937 {
938 if (GET_CODE (operands[0]) == MEM)
939 {
940 if (GET_CODE (operands[1]) != MEM)
941 return "st %r1,%0";
942 else
943 abort ();
944 }
945 else if (GET_CODE (operands[1]) == MEM)
946 return "ld %1,%0";
947 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
948 {
949 int i;
950 union real_extract u;
951 union float_extract { float f; int i; } v;
952
953 /* Must be SFmode, otherwise this doesn't make sense. */
954 if (GET_MODE (operands[1]) != SFmode)
955 abort ();
956
957 bcopy (&CONST_DOUBLE_LOW (operands[1]), &u, sizeof u);
958 v.f = REAL_VALUE_TRUNCATE (SFmode, u.d);
959 i = v.i;
960
961 operands[1] = gen_rtx (CONST_INT, VOIDmode, i);
962
963 if (CONST_OK_FOR_LETTER_P (i, 'I'))
964 return "mov %1,%0";
965 else if ((i & 0x000003FF) != 0)
966 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
967 else
968 return "sethi %%hi(%a1),%0";
969 }
970 else if (GET_CODE (operands[1]) == CONST_INT
971 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I'))
972 {
973 int i = INTVAL (operands[1]);
974
975 /* If all low order 10 bits are clear, then we only need a single
976 sethi insn to load the constant. */
977 if ((i & 0x000003FF) != 0)
978 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
979 else
980 return "sethi %%hi(%a1),%0";
981 }
982 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
983 return "mov %1,%0";
984 }
985 \f
986 /* Return non-zero if it is OK to assume that the given memory operand is
987 aligned at least to a 8-byte boundary. This should only be called
988 for memory accesses whose size is 8 bytes or larger. */
989
990 int
991 mem_aligned_8 (mem)
992 register rtx mem;
993 {
994 register rtx addr;
995 register rtx base;
996 register rtx offset;
997
998 if (GET_CODE (mem) != MEM)
999 return 0; /* It's gotta be a MEM! */
1000
1001 addr = XEXP (mem, 0);
1002
1003 /* Now that all misaligned double parms are copied on function entry,
1004 we can assume any 64-bit object is 64-bit aligned except those which
1005 are at unaligned offsets from the stack or frame pointer. If the
1006 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1007 assumption. */
1008
1009 /* See what register we use in the address. */
1010 base = 0;
1011 if (GET_CODE (addr) == PLUS)
1012 {
1013 if (GET_CODE (XEXP (addr, 0)) == REG
1014 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
1015 {
1016 base = XEXP (addr, 0);
1017 offset = XEXP (addr, 1);
1018 }
1019 }
1020 else if (GET_CODE (addr) == REG)
1021 {
1022 base = addr;
1023 offset = const0_rtx;
1024 }
1025
1026 /* If it's the stack or frame pointer, check offset alignment.
1027 We can have improper alignment in the function entry code. */
1028 if (base
1029 && (REGNO (base) == FRAME_POINTER_REGNUM
1030 || REGNO (base) == STACK_POINTER_REGNUM))
1031 {
1032 if ((INTVAL (offset) & 0x7) == 0)
1033 return 1;
1034 }
1035 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1036 is true, in which case we can only assume that an access is aligned if
1037 it is to an aggregate, it is to a constant address, or the address
1038 involves a LO_SUM. */
1039 else if (! TARGET_UNALIGNED_DOUBLES || MEM_IN_STRUCT_P (mem)
1040 || CONSTANT_P (addr) || GET_CODE (addr) == LO_SUM)
1041 return 1;
1042
1043 /* An obviously unaligned address. */
1044 return 0;
1045 }
1046
1047 enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP };
1048
1049 /* Output assembler code to perform a doubleword move insn
1050 with operands OPERANDS. This is very similar to the following
1051 output_move_quad function. */
1052
1053 char *
1054 output_move_double (operands)
1055 rtx *operands;
1056 {
1057 register rtx op0 = operands[0];
1058 register rtx op1 = operands[1];
1059 register enum optype optype0;
1060 register enum optype optype1;
1061 rtx latehalf[2];
1062 rtx addreg0 = 0;
1063 rtx addreg1 = 0;
1064
1065 /* First classify both operands. */
1066
1067 if (REG_P (op0))
1068 optype0 = REGOP;
1069 else if (offsettable_memref_p (op0))
1070 optype0 = OFFSOP;
1071 else if (GET_CODE (op0) == MEM)
1072 optype0 = MEMOP;
1073 else
1074 optype0 = RNDOP;
1075
1076 if (REG_P (op1))
1077 optype1 = REGOP;
1078 else if (CONSTANT_P (op1))
1079 optype1 = CNSTOP;
1080 else if (offsettable_memref_p (op1))
1081 optype1 = OFFSOP;
1082 else if (GET_CODE (op1) == MEM)
1083 optype1 = MEMOP;
1084 else
1085 optype1 = RNDOP;
1086
1087 /* Check for the cases that the operand constraints are not
1088 supposed to allow to happen. Abort if we get one,
1089 because generating code for these cases is painful. */
1090
1091 if (optype0 == RNDOP || optype1 == RNDOP
1092 || (optype0 == MEM && optype1 == MEM))
1093 abort ();
1094
1095 /* If an operand is an unoffsettable memory ref, find a register
1096 we can increment temporarily to make it refer to the second word. */
1097
1098 if (optype0 == MEMOP)
1099 addreg0 = find_addr_reg (XEXP (op0, 0));
1100
1101 if (optype1 == MEMOP)
1102 addreg1 = find_addr_reg (XEXP (op1, 0));
1103
1104 /* Ok, we can do one word at a time.
1105 Set up in LATEHALF the operands to use for the
1106 high-numbered (least significant) word and in some cases alter the
1107 operands in OPERANDS to be suitable for the low-numbered word. */
1108
1109 if (optype0 == REGOP)
1110 latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
1111 else if (optype0 == OFFSOP)
1112 latehalf[0] = adj_offsettable_operand (op0, 4);
1113 else
1114 latehalf[0] = op0;
1115
1116 if (optype1 == REGOP)
1117 latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
1118 else if (optype1 == OFFSOP)
1119 latehalf[1] = adj_offsettable_operand (op1, 4);
1120 else if (optype1 == CNSTOP)
1121 split_double (op1, &operands[1], &latehalf[1]);
1122 else
1123 latehalf[1] = op1;
1124
1125 /* Easy case: try moving both words at once. Check for moving between
1126 an even/odd register pair and a memory location. */
1127 if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP
1128 && (REGNO (op0) & 1) == 0)
1129 || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP
1130 && (REGNO (op1) & 1) == 0))
1131 {
1132 register rtx mem;
1133
1134 if (optype0 == REGOP)
1135 mem = op1;
1136 else
1137 mem = op0;
1138
1139 if (mem_aligned_8 (mem))
1140 return (mem == op1 ? "ldd %1,%0" : "std %1,%0");
1141 }
1142
1143 /* If the first move would clobber the source of the second one,
1144 do them in the other order. */
1145
1146 /* Overlapping registers. */
1147 if (optype0 == REGOP && optype1 == REGOP
1148 && REGNO (op0) == REGNO (latehalf[1]))
1149 {
1150 /* Do that word. */
1151 output_asm_insn (singlemove_string (latehalf), latehalf);
1152 /* Do low-numbered word. */
1153 return singlemove_string (operands);
1154 }
1155 /* Loading into a register which overlaps a register used in the address. */
1156 else if (optype0 == REGOP && optype1 != REGOP
1157 && reg_overlap_mentioned_p (op0, op1))
1158 {
1159 if (reg_mentioned_p (op0, XEXP (op1, 0))
1160 && reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
1161 {
1162 /* If both halves of dest are used in the src memory address,
1163 add the two regs and put them in the low reg (op0).
1164 Then it works to load latehalf first. */
1165 rtx xops[2];
1166 xops[0] = latehalf[0];
1167 xops[1] = op0;
1168 output_asm_insn ("add %1,%0,%1", xops);
1169 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
1170 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1171 }
1172 /* Do the late half first. */
1173 output_asm_insn (singlemove_string (latehalf), latehalf);
1174 /* Then clobber. */
1175 return singlemove_string (operands);
1176 }
1177
1178 /* Normal case: do the two words, low-numbered first. */
1179
1180 output_asm_insn (singlemove_string (operands), operands);
1181
1182 /* Make any unoffsettable addresses point at high-numbered word. */
1183 if (addreg0)
1184 output_asm_insn ("add %0,0x4,%0", &addreg0);
1185 if (addreg1)
1186 output_asm_insn ("add %0,0x4,%0", &addreg1);
1187
1188 /* Do that word. */
1189 output_asm_insn (singlemove_string (latehalf), latehalf);
1190
1191 /* Undo the adds we just did. */
1192 if (addreg0)
1193 output_asm_insn ("add %0,-0x4,%0", &addreg0);
1194 if (addreg1)
1195 output_asm_insn ("add %0,-0x4,%0", &addreg1);
1196
1197 return "";
1198 }
1199
1200 /* Output assembler code to perform a quadword move insn
1201 with operands OPERANDS. This is very similar to the preceding
1202 output_move_double function. */
1203
1204 char *
1205 output_move_quad (operands)
1206 rtx *operands;
1207 {
1208 register rtx op0 = operands[0];
1209 register rtx op1 = operands[1];
1210 register enum optype optype0;
1211 register enum optype optype1;
1212 rtx wordpart[4][2];
1213 rtx addreg0 = 0;
1214 rtx addreg1 = 0;
1215
1216 /* First classify both operands. */
1217
1218 if (REG_P (op0))
1219 optype0 = REGOP;
1220 else if (offsettable_memref_p (op0))
1221 optype0 = OFFSOP;
1222 else if (GET_CODE (op0) == MEM)
1223 optype0 = MEMOP;
1224 else
1225 optype0 = RNDOP;
1226
1227 if (REG_P (op1))
1228 optype1 = REGOP;
1229 else if (CONSTANT_P (op1))
1230 optype1 = CNSTOP;
1231 else if (offsettable_memref_p (op1))
1232 optype1 = OFFSOP;
1233 else if (GET_CODE (op1) == MEM)
1234 optype1 = MEMOP;
1235 else
1236 optype1 = RNDOP;
1237
1238 /* Check for the cases that the operand constraints are not
1239 supposed to allow to happen. Abort if we get one,
1240 because generating code for these cases is painful. */
1241
1242 if (optype0 == RNDOP || optype1 == RNDOP
1243 || (optype0 == MEM && optype1 == MEM))
1244 abort ();
1245
1246 /* If an operand is an unoffsettable memory ref, find a register
1247 we can increment temporarily to make it refer to the later words. */
1248
1249 if (optype0 == MEMOP)
1250 addreg0 = find_addr_reg (XEXP (op0, 0));
1251
1252 if (optype1 == MEMOP)
1253 addreg1 = find_addr_reg (XEXP (op1, 0));
1254
1255 /* Ok, we can do one word at a time.
1256 Set up in wordpart the operands to use for each word of the arguments. */
1257
1258 if (optype0 == REGOP)
1259 {
1260 wordpart[0][0] = gen_rtx (REG, SImode, REGNO (op0) + 0);
1261 wordpart[1][0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
1262 wordpart[2][0] = gen_rtx (REG, SImode, REGNO (op0) + 2);
1263 wordpart[3][0] = gen_rtx (REG, SImode, REGNO (op0) + 3);
1264 }
1265 else if (optype0 == OFFSOP)
1266 {
1267 wordpart[0][0] = adj_offsettable_operand (op0, 0);
1268 wordpart[1][0] = adj_offsettable_operand (op0, 4);
1269 wordpart[2][0] = adj_offsettable_operand (op0, 8);
1270 wordpart[3][0] = adj_offsettable_operand (op0, 12);
1271 }
1272 else
1273 {
1274 wordpart[0][0] = op0;
1275 wordpart[1][0] = op0;
1276 wordpart[2][0] = op0;
1277 wordpart[3][0] = op0;
1278 }
1279
1280 if (optype1 == REGOP)
1281 {
1282 wordpart[0][1] = gen_rtx (REG, SImode, REGNO (op1) + 0);
1283 wordpart[1][1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
1284 wordpart[2][1] = gen_rtx (REG, SImode, REGNO (op1) + 2);
1285 wordpart[3][1] = gen_rtx (REG, SImode, REGNO (op1) + 3);
1286 }
1287 else if (optype1 == OFFSOP)
1288 {
1289 wordpart[0][1] = adj_offsettable_operand (op1, 0);
1290 wordpart[1][1] = adj_offsettable_operand (op1, 4);
1291 wordpart[2][1] = adj_offsettable_operand (op1, 8);
1292 wordpart[3][1] = adj_offsettable_operand (op1, 12);
1293 }
1294 else if (optype1 == CNSTOP)
1295 {
1296 /* This case isn't implemented yet, because there is no internal
1297 representation for quad-word constants, and there is no split_quad
1298 function. */
1299 #if 0
1300 split_quad (op1, &wordpart[0][1], &wordpart[1][1],
1301 &wordpart[2][1], &wordpart[3][1]);
1302 #else
1303 abort ();
1304 #endif
1305 }
1306 else
1307 {
1308 wordpart[0][1] = op1;
1309 wordpart[1][1] = op1;
1310 wordpart[2][1] = op1;
1311 wordpart[3][1] = op1;
1312 }
1313
1314 /* Easy case: try moving the quad as two pairs. Check for moving between
1315 an even/odd register pair and a memory location. */
1316 /* ??? Should also handle the case of non-offsettable addresses here.
1317 We can at least do the first pair as a ldd/std, and then do the third
1318 and fourth words individually. */
1319 if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0)
1320 || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0))
1321 {
1322 rtx mem;
1323
1324 if (optype0 == REGOP)
1325 mem = op1;
1326 else
1327 mem = op0;
1328
1329 if (mem_aligned_8 (mem))
1330 {
1331 operands[2] = adj_offsettable_operand (mem, 8);
1332 if (mem == op1)
1333 return "ldd %1,%0;ldd %2,%S0";
1334 else
1335 return "std %1,%0;std %S1,%2";
1336 }
1337 }
1338
1339 /* If the first move would clobber the source of the second one,
1340 do them in the other order. */
1341
1342 /* Overlapping registers. */
1343 if (optype0 == REGOP && optype1 == REGOP
1344 && (REGNO (op0) == REGNO (wordpart[1][3])
1345 || REGNO (op0) == REGNO (wordpart[1][2])
1346 || REGNO (op0) == REGNO (wordpart[1][1])))
1347 {
1348 /* Do fourth word. */
1349 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
1350 /* Do the third word. */
1351 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
1352 /* Do the second word. */
1353 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
1354 /* Do lowest-numbered word. */
1355 return singlemove_string (wordpart[0]);
1356 }
1357 /* Loading into a register which overlaps a register used in the address. */
1358 if (optype0 == REGOP && optype1 != REGOP
1359 && reg_overlap_mentioned_p (op0, op1))
1360 {
1361 /* ??? Not implemented yet. This is a bit complicated, because we
1362 must load which ever part overlaps the address last. If the address
1363 is a double-reg address, then there are two parts which need to
1364 be done last, which is impossible. We would need a scratch register
1365 in that case. */
1366 abort ();
1367 }
1368
1369 /* Normal case: move the four words in lowest to higest address order. */
1370
1371 output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
1372
1373 /* Make any unoffsettable addresses point at the second word. */
1374 if (addreg0)
1375 output_asm_insn ("add %0,0x4,%0", &addreg0);
1376 if (addreg1)
1377 output_asm_insn ("add %0,0x4,%0", &addreg1);
1378
1379 /* Do the second word. */
1380 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
1381
1382 /* Make any unoffsettable addresses point at the third word. */
1383 if (addreg0)
1384 output_asm_insn ("add %0,0x4,%0", &addreg0);
1385 if (addreg1)
1386 output_asm_insn ("add %0,0x4,%0", &addreg1);
1387
1388 /* Do the third word. */
1389 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
1390
1391 /* Make any unoffsettable addresses point at the fourth word. */
1392 if (addreg0)
1393 output_asm_insn ("add %0,0x4,%0", &addreg0);
1394 if (addreg1)
1395 output_asm_insn ("add %0,0x4,%0", &addreg1);
1396
1397 /* Do the fourth word. */
1398 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
1399
1400 /* Undo the adds we just did. */
1401 if (addreg0)
1402 output_asm_insn ("add %0,-0xc,%0", &addreg0);
1403 if (addreg1)
1404 output_asm_insn ("add %0,-0xc,%0", &addreg1);
1405
1406 return "";
1407 }
1408 \f
1409 /* Output assembler code to perform a doubleword move insn with operands
1410 OPERANDS, one of which must be a floating point register. */
1411
1412 char *
1413 output_fp_move_double (operands)
1414 rtx *operands;
1415 {
1416 if (FP_REG_P (operands[0]))
1417 {
1418 if (FP_REG_P (operands[1]))
1419 return "fmovs %1,%0\n\tfmovs %R1,%R0";
1420 else if (GET_CODE (operands[1]) == REG)
1421 abort ();
1422 else
1423 return output_move_double (operands);
1424 }
1425 else if (FP_REG_P (operands[1]))
1426 {
1427 if (GET_CODE (operands[0]) == REG)
1428 abort ();
1429 else
1430 return output_move_double (operands);
1431 }
1432 else abort ();
1433 }
1434
1435 /* Output assembler code to perform a quadword move insn with operands
1436 OPERANDS, one of which must be a floating point register. */
1437
1438 char *
1439 output_fp_move_quad (operands)
1440 rtx *operands;
1441 {
1442 register rtx op0 = operands[0];
1443 register rtx op1 = operands[1];
1444
1445 if (FP_REG_P (op0))
1446 {
1447 if (FP_REG_P (op1))
1448 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
1449 else if (GET_CODE (op1) == REG)
1450 abort ();
1451 else
1452 return output_move_quad (operands);
1453 }
1454 else if (FP_REG_P (op1))
1455 {
1456 if (GET_CODE (op0) == REG)
1457 abort ();
1458 else
1459 return output_move_quad (operands);
1460 }
1461 else
1462 abort ();
1463 }
1464 \f
1465 /* Return a REG that occurs in ADDR with coefficient 1.
1466 ADDR can be effectively incremented by incrementing REG. */
1467
1468 static rtx
1469 find_addr_reg (addr)
1470 rtx addr;
1471 {
1472 while (GET_CODE (addr) == PLUS)
1473 {
1474 /* We absolutely can not fudge the frame pointer here, because the
1475 frame pointer must always be 8 byte aligned. It also confuses
1476 debuggers. */
1477 if (GET_CODE (XEXP (addr, 0)) == REG
1478 && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM)
1479 addr = XEXP (addr, 0);
1480 else if (GET_CODE (XEXP (addr, 1)) == REG
1481 && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM)
1482 addr = XEXP (addr, 1);
1483 else if (CONSTANT_P (XEXP (addr, 0)))
1484 addr = XEXP (addr, 1);
1485 else if (CONSTANT_P (XEXP (addr, 1)))
1486 addr = XEXP (addr, 0);
1487 else
1488 abort ();
1489 }
1490 if (GET_CODE (addr) == REG)
1491 return addr;
1492 abort ();
1493 }
1494
1495 void
1496 output_sized_memop (opname, mode, signedp)
1497 char *opname;
1498 enum machine_mode mode;
1499 int signedp;
1500 {
1501 static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" };
1502 static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" };
1503 static char *st_size_suffix[] = { "b", "h", "", "?", "d" };
1504 char **opnametab, *modename;
1505
1506 if (opname[0] == 'l')
1507 if (signedp)
1508 opnametab = ld_size_suffix_s;
1509 else
1510 opnametab = ld_size_suffix_u;
1511 else
1512 opnametab = st_size_suffix;
1513 modename = opnametab[GET_MODE_SIZE (mode) >> 1];
1514
1515 fprintf (asm_out_file, "\t%s%s", opname, modename);
1516 }
1517 \f
1518 void
1519 output_move_with_extension (operands)
1520 rtx *operands;
1521 {
1522 if (GET_MODE (operands[2]) == HImode)
1523 output_asm_insn ("sll %2,0x10,%0", operands);
1524 else if (GET_MODE (operands[2]) == QImode)
1525 output_asm_insn ("sll %2,0x18,%0", operands);
1526 else
1527 abort ();
1528 }
1529 \f
1530 #if 0
1531 /* ??? These are only used by the movstrsi pattern, but we get better code
1532 in general without that, because emit_block_move can do just as good a
1533 job as this function does when alignment and size are known. When they
1534 aren't known, a call to strcpy may be faster anyways, because it is
1535 likely to be carefully crafted assembly language code, and below we just
1536 do a byte-wise copy.
1537
1538 Also, emit_block_move expands into multiple read/write RTL insns, which
1539 can then be optimized, whereas our movstrsi pattern can not be optimized
1540 at all. */
1541
1542 /* Load the address specified by OPERANDS[3] into the register
1543 specified by OPERANDS[0].
1544
1545 OPERANDS[3] may be the result of a sum, hence it could either be:
1546
1547 (1) CONST
1548 (2) REG
1549 (2) REG + CONST_INT
1550 (3) REG + REG + CONST_INT
1551 (4) REG + REG (special case of 3).
1552
1553 Note that (3) is not a legitimate address.
1554 All cases are handled here. */
1555
1556 void
1557 output_load_address (operands)
1558 rtx *operands;
1559 {
1560 rtx base, offset;
1561
1562 if (CONSTANT_P (operands[3]))
1563 {
1564 output_asm_insn ("set %3,%0", operands);
1565 return;
1566 }
1567
1568 if (REG_P (operands[3]))
1569 {
1570 if (REGNO (operands[0]) != REGNO (operands[3]))
1571 output_asm_insn ("mov %3,%0", operands);
1572 return;
1573 }
1574
1575 if (GET_CODE (operands[3]) != PLUS)
1576 abort ();
1577
1578 base = XEXP (operands[3], 0);
1579 offset = XEXP (operands[3], 1);
1580
1581 if (GET_CODE (base) == CONST_INT)
1582 {
1583 rtx tmp = base;
1584 base = offset;
1585 offset = tmp;
1586 }
1587
1588 if (GET_CODE (offset) != CONST_INT)
1589 {
1590 /* Operand is (PLUS (REG) (REG)). */
1591 base = operands[3];
1592 offset = const0_rtx;
1593 }
1594
1595 if (REG_P (base))
1596 {
1597 operands[6] = base;
1598 operands[7] = offset;
1599 if (SMALL_INT (offset))
1600 output_asm_insn ("add %6,%7,%0", operands);
1601 else
1602 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands);
1603 }
1604 else if (GET_CODE (base) == PLUS)
1605 {
1606 operands[6] = XEXP (base, 0);
1607 operands[7] = XEXP (base, 1);
1608 operands[8] = offset;
1609
1610 if (SMALL_INT (offset))
1611 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands);
1612 else
1613 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands);
1614 }
1615 else
1616 abort ();
1617 }
1618
1619 /* Output code to place a size count SIZE in register REG.
1620 ALIGN is the size of the unit of transfer.
1621
1622 Because block moves are pipelined, we don't include the
1623 first element in the transfer of SIZE to REG. */
1624
1625 static void
1626 output_size_for_block_move (size, reg, align)
1627 rtx size, reg;
1628 rtx align;
1629 {
1630 rtx xoperands[3];
1631
1632 xoperands[0] = reg;
1633 xoperands[1] = size;
1634 xoperands[2] = align;
1635 if (GET_CODE (size) == REG)
1636 output_asm_insn ("sub %1,%2,%0", xoperands);
1637 else
1638 {
1639 xoperands[1]
1640 = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
1641 output_asm_insn ("set %1,%0", xoperands);
1642 }
1643 }
1644
1645 /* Emit code to perform a block move.
1646
1647 OPERANDS[0] is the destination.
1648 OPERANDS[1] is the source.
1649 OPERANDS[2] is the size.
1650 OPERANDS[3] is the alignment safe to use.
1651 OPERANDS[4] is a register we can safely clobber as a temp. */
1652
1653 char *
1654 output_block_move (operands)
1655 rtx *operands;
1656 {
1657 /* A vector for our computed operands. Note that load_output_address
1658 makes use of (and can clobber) up to the 8th element of this vector. */
1659 rtx xoperands[10];
1660 rtx zoperands[10];
1661 static int movstrsi_label = 0;
1662 int i;
1663 rtx temp1 = operands[4];
1664 rtx sizertx = operands[2];
1665 rtx alignrtx = operands[3];
1666 int align = INTVAL (alignrtx);
1667 char label3[30], label5[30];
1668
1669 xoperands[0] = operands[0];
1670 xoperands[1] = operands[1];
1671 xoperands[2] = temp1;
1672
1673 /* We can't move more than this many bytes at a time because we have only
1674 one register, %g1, to move them through. */
1675 if (align > UNITS_PER_WORD)
1676 {
1677 align = UNITS_PER_WORD;
1678 alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD);
1679 }
1680
1681 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
1682 reasonable here. (Actually will emit a maximum of 18 inline insns for
1683 the case of size == 31 and align == 4). */
1684
1685 if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8
1686 && memory_address_p (QImode, plus_constant_for_output (xoperands[0],
1687 INTVAL (sizertx)))
1688 && memory_address_p (QImode, plus_constant_for_output (xoperands[1],
1689 INTVAL (sizertx))))
1690 {
1691 int size = INTVAL (sizertx);
1692 int offset = 0;
1693
1694 /* We will store different integers into this particular RTX. */
1695 xoperands[2] = rtx_alloc (CONST_INT);
1696 PUT_MODE (xoperands[2], VOIDmode);
1697
1698 /* This case is currently not handled. Abort instead of generating
1699 bad code. */
1700 if (align > 4)
1701 abort ();
1702
1703 if (align >= 4)
1704 {
1705 for (i = (size >> 2) - 1; i >= 0; i--)
1706 {
1707 INTVAL (xoperands[2]) = (i << 2) + offset;
1708 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
1709 xoperands);
1710 }
1711 offset += (size & ~0x3);
1712 size = size & 0x3;
1713 if (size == 0)
1714 return "";
1715 }
1716
1717 if (align >= 2)
1718 {
1719 for (i = (size >> 1) - 1; i >= 0; i--)
1720 {
1721 INTVAL (xoperands[2]) = (i << 1) + offset;
1722 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
1723 xoperands);
1724 }
1725 offset += (size & ~0x1);
1726 size = size & 0x1;
1727 if (size == 0)
1728 return "";
1729 }
1730
1731 if (align >= 1)
1732 {
1733 for (i = size - 1; i >= 0; i--)
1734 {
1735 INTVAL (xoperands[2]) = i + offset;
1736 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
1737 xoperands);
1738 }
1739 return "";
1740 }
1741
1742 /* We should never reach here. */
1743 abort ();
1744 }
1745
1746 /* If the size isn't known to be a multiple of the alignment,
1747 we have to do it in smaller pieces. If we could determine that
1748 the size was a multiple of 2 (or whatever), we could be smarter
1749 about this. */
1750 if (GET_CODE (sizertx) != CONST_INT)
1751 align = 1;
1752 else
1753 {
1754 int size = INTVAL (sizertx);
1755 while (size % align)
1756 align >>= 1;
1757 }
1758
1759 if (align != INTVAL (alignrtx))
1760 alignrtx = gen_rtx (CONST_INT, VOIDmode, align);
1761
1762 xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
1763 xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align);
1764 xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
1765
1766 ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3]));
1767 ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5]));
1768
1769 /* This is the size of the transfer. Emit code to decrement the size
1770 value by ALIGN, and store the result in the temp1 register. */
1771 output_size_for_block_move (sizertx, temp1, alignrtx);
1772
1773 /* Must handle the case when the size is zero or negative, so the first thing
1774 we do is compare the size against zero, and only copy bytes if it is
1775 zero or greater. Note that we have already subtracted off the alignment
1776 once, so we must copy 1 alignment worth of bytes if the size is zero
1777 here.
1778
1779 The SUN assembler complains about labels in branch delay slots, so we
1780 do this before outputting the load address, so that there will always
1781 be a harmless insn between the branch here and the next label emitted
1782 below. */
1783
1784 {
1785 char pattern[100];
1786
1787 sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]);
1788 output_asm_insn (pattern, xoperands);
1789 }
1790
1791 zoperands[0] = operands[0];
1792 zoperands[3] = plus_constant_for_output (operands[0], align);
1793 output_load_address (zoperands);
1794
1795 /* ??? This might be much faster if the loops below were preconditioned
1796 and unrolled.
1797
1798 That is, at run time, copy enough bytes one at a time to ensure that the
1799 target and source addresses are aligned to the the largest possible
1800 alignment. Then use a preconditioned unrolled loop to copy say 16
1801 bytes at a time. Then copy bytes one at a time until finish the rest. */
1802
1803 /* Output the first label separately, so that it is spaced properly. */
1804
1805 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3]));
1806
1807 {
1808 char pattern[200];
1809 register char *ld_suffix = (align == 1) ? "ub" : (align == 2) ? "uh" : "";
1810 register char *st_suffix = (align == 1) ? "b" : (align == 2) ? "h" : "";
1811
1812 sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]);
1813 output_asm_insn (pattern, xoperands);
1814 }
1815
1816 return "";
1817 }
1818 #endif
1819 \f
1820 /* Output reasonable peephole for set-on-condition-code insns.
1821 Note that these insns assume a particular way of defining
1822 labels. Therefore, *both* sparc.h and this function must
1823 be changed if a new syntax is needed. */
1824
1825 char *
1826 output_scc_insn (operands, insn)
1827 rtx operands[];
1828 rtx insn;
1829 {
1830 static char string[100];
1831 rtx label = 0, next = insn;
1832 int need_label = 0;
1833
1834 /* Try doing a jump optimization which jump.c can't do for us
1835 because we did not expose that setcc works by using branches.
1836
1837 If this scc insn is followed by an unconditional branch, then have
1838 the jump insn emitted here jump to that location, instead of to
1839 the end of the scc sequence as usual. */
1840
1841 do
1842 {
1843 if (GET_CODE (next) == CODE_LABEL)
1844 label = next;
1845 next = NEXT_INSN (next);
1846 if (next == 0)
1847 break;
1848 }
1849 while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL);
1850
1851 /* If we are in a sequence, and the following insn is a sequence also,
1852 then just following the current insn's next field will take us to the
1853 first insn of the next sequence, which is the wrong place. We don't
1854 want to optimize with a branch that has had its delay slot filled.
1855 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
1856 which fails only if NEXT is such a branch. */
1857
1858 if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next)
1859 && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next))
1860 label = JUMP_LABEL (next);
1861 /* If not optimizing, jump label fields are not set. To be safe, always
1862 check here to whether label is still zero. */
1863 if (label == 0)
1864 {
1865 label = gen_label_rtx ();
1866 need_label = 1;
1867 }
1868
1869 LABEL_NUSES (label) += 1;
1870
1871 operands[2] = label;
1872
1873 /* If we are in a delay slot, assume it is the delay slot of an fpcc
1874 insn since our type isn't allowed anywhere else. */
1875
1876 /* ??? Fpcc instructions no longer have delay slots, so this code is
1877 probably obsolete. */
1878
1879 /* The fastest way to emit code for this is an annulled branch followed
1880 by two move insns. This will take two cycles if the branch is taken,
1881 and three cycles if the branch is not taken.
1882
1883 However, if we are in the delay slot of another branch, this won't work,
1884 because we can't put a branch in the delay slot of another branch.
1885 The above sequence would effectively take 3 or 4 cycles respectively
1886 since a no op would have be inserted between the two branches.
1887 In this case, we want to emit a move, annulled branch, and then the
1888 second move. This sequence always takes 3 cycles, and hence is faster
1889 when we are in a branch delay slot. */
1890
1891 if (final_sequence)
1892 {
1893 strcpy (string, "mov 0,%0\n\t");
1894 strcat (string, output_cbranch (operands[1], 2, 0, 1, 0));
1895 strcat (string, "\n\tmov 1,%0");
1896 }
1897 else
1898 {
1899 strcpy (string, output_cbranch (operands[1], 2, 0, 1, 0));
1900 strcat (string, "\n\tmov 1,%0\n\tmov 0,%0");
1901 }
1902
1903 if (need_label)
1904 strcat (string, "\n%l2:");
1905
1906 return string;
1907 }
1908 \f
1909 /* Vectors to keep interesting information about registers where
1910 it can easily be got. */
1911
1912 /* Modes for condition codes. */
1913 #define C_MODES \
1914 ((1 << (int) CCmode) | (1 << (int) CC_NOOVmode) \
1915 | (1 << (int) CCFPmode) | (1 << (int) CCFPEmode))
1916
1917 /* Modes for single-word (and smaller) quantities. */
1918 #define S_MODES \
1919 ((1 << (int) QImode) | (1 << (int) HImode) | (1 << (int) SImode) \
1920 | (1 << (int) QFmode) | (1 << (int) HFmode) | (1 << (int) SFmode) \
1921 | (1 << (int) CQImode) | (1 << (int) CHImode))
1922
1923 /* Modes for double-word (and smaller) quantities. */
1924 #define D_MODES \
1925 (S_MODES | (1 << (int) DImode) | (1 << (int) DFmode) \
1926 | (1 << (int) CSImode) | (1 << (int) SCmode))
1927
1928 /* Modes for quad-word quantities. */
1929 #define T_MODES \
1930 (D_MODES | (1 << (int) TImode) | (1 << (int) TFmode) \
1931 | (1 << (int) DCmode) | (1 << (int) CDImode))
1932
1933 /* Modes for single-float quantities. We must allow any single word or
1934 smaller quantity. This is because the fix/float conversion instructions
1935 take integer inputs/outputs from the float registers. */
1936 #define SF_MODES (S_MODES)
1937
1938 /* Modes for double-float quantities. */
1939 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1940
1941 /* Modes for quad-float quantities. */
1942 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1943
1944 /* Value is 1 if register/mode pair is acceptable on sparc.
1945 The funny mixture of D and T modes is because integer operations
1946 do not specially operate on tetra quantities, so non-quad-aligned
1947 registers can hold quadword quantities (except %o4 and %i4 because
1948 they cross fixed registers. */
1949
1950 int hard_regno_mode_ok[] = {
1951 C_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1952 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
1953 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1954 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
1955
1956 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
1957 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
1958 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
1959 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES};
1960 \f
1961 #ifdef __GNUC__
1962 inline
1963 #endif
1964 static int
1965 save_regs (file, low, high, base, offset, n_fregs)
1966 FILE *file;
1967 int low, high;
1968 char *base;
1969 int offset;
1970 int n_fregs;
1971 {
1972 int i;
1973
1974 for (i = low; i < high; i += 2)
1975 {
1976 if (regs_ever_live[i] && ! call_used_regs[i])
1977 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
1978 fprintf (file, "\tstd %s,[%s+%d]\n",
1979 reg_names[i], base, offset + 4 * n_fregs),
1980 n_fregs += 2;
1981 else
1982 fprintf (file, "\tst %s,[%s+%d]\n",
1983 reg_names[i], base, offset + 4 * n_fregs),
1984 n_fregs += 2;
1985 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
1986 fprintf (file, "\tst %s,[%s+%d]\n",
1987 reg_names[i+1], base, offset + 4 * n_fregs),
1988 n_fregs += 2;
1989 }
1990 return n_fregs;
1991 }
1992
1993 #ifdef __GNUC__
1994 inline
1995 #endif
1996 static int
1997 restore_regs (file, low, high, base, offset, n_fregs)
1998 FILE *file;
1999 int low, high;
2000 char *base;
2001 int offset;
2002 {
2003 int i;
2004
2005 for (i = low; i < high; i += 2)
2006 {
2007 if (regs_ever_live[i] && ! call_used_regs[i])
2008 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2009 fprintf (file, "\tldd [%s+%d], %s\n",
2010 base, offset + 4 * n_fregs, reg_names[i]),
2011 n_fregs += 2;
2012 else
2013 fprintf (file, "\tld [%s+%d],%s\n",
2014 base, offset + 4 * n_fregs, reg_names[i]),
2015 n_fregs += 2;
2016 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2017 fprintf (file, "\tld [%s+%d],%s\n",
2018 base, offset + 4 * n_fregs, reg_names[i+1]),
2019 n_fregs += 2;
2020 }
2021 return n_fregs;
2022 }
2023
2024 /* Static variables we want to share between prologue and epilogue. */
2025
2026 /* Number of live floating point registers needed to be saved. */
2027 static int num_fregs;
2028
2029 int
2030 compute_frame_size (size, leaf_function)
2031 int size;
2032 int leaf_function;
2033 {
2034 int fregs_ever_live = 0;
2035 int n_fregs = 0, i;
2036 int outgoing_args_size = (current_function_outgoing_args_size
2037 + REG_PARM_STACK_SPACE (current_function_decl));
2038
2039 apparent_fsize = ((size) + 7 - STARTING_FRAME_OFFSET) & -8;
2040 for (i = 32; i < FIRST_PSEUDO_REGISTER; i += 2)
2041 fregs_ever_live |= regs_ever_live[i]|regs_ever_live[i+1];
2042
2043 if (TARGET_EPILOGUE && fregs_ever_live)
2044 {
2045 for (i = 32; i < FIRST_PSEUDO_REGISTER; i += 2)
2046 if ((regs_ever_live[i] && ! call_used_regs[i])
2047 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
2048 n_fregs += 2;
2049 }
2050
2051 /* Set up values for use in `function_epilogue'. */
2052 num_fregs = n_fregs;
2053
2054 apparent_fsize += (outgoing_args_size+7) & -8;
2055 if (leaf_function && n_fregs == 0
2056 && apparent_fsize == (REG_PARM_STACK_SPACE (current_function_decl)
2057 - STARTING_FRAME_OFFSET))
2058 apparent_fsize = 0;
2059
2060 actual_fsize = apparent_fsize + n_fregs*4;
2061
2062 /* Make sure nothing can clobber our register windows.
2063 If a SAVE must be done, or there is a stack-local variable,
2064 the register window area must be allocated. */
2065 if (leaf_function == 0 || size > 0)
2066 actual_fsize += (16 * UNITS_PER_WORD)+8;
2067
2068 return actual_fsize;
2069 }
2070
2071 /* Output code for the function prologue. */
2072
2073 void
2074 output_function_prologue (file, size, leaf_function)
2075 FILE *file;
2076 int size;
2077 int leaf_function;
2078 {
2079 /* ??? This should be %sp+actual_fsize for a leaf function. I think it
2080 works only because it is never used. */
2081 if (leaf_function)
2082 frame_base_name = "%sp+80";
2083 else
2084 frame_base_name = "%fp";
2085
2086 /* Need to use actual_fsize, since we are also allocating
2087 space for our callee (and our own register save area). */
2088 actual_fsize = compute_frame_size (size, leaf_function);
2089
2090 fprintf (file, "\t!#PROLOGUE# 0\n");
2091 if (actual_fsize == 0)
2092 /* do nothing. */ ;
2093 else if (actual_fsize <= 4096)
2094 {
2095 if (! leaf_function)
2096 fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize);
2097 else
2098 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize);
2099 }
2100 else if (actual_fsize <= 8192)
2101 {
2102 /* For frames in the range 4097..8192, we can use just two insns. */
2103 if (! leaf_function)
2104 {
2105 fprintf (file, "\tsave %%sp,-4096,%%sp\n");
2106 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
2107 }
2108 else
2109 {
2110 fprintf (file, "\tadd %%sp,-4096,%%sp\n");
2111 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
2112 }
2113 }
2114 else
2115 {
2116 if (! leaf_function)
2117 {
2118 fprintf (file, "\tsethi %%hi(-%d),%%g1\n", actual_fsize);
2119 if ((actual_fsize & 0x3ff) != 0)
2120 fprintf (file, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize);
2121 fprintf (file, "\tsave %%sp,%%g1,%%sp\n");
2122 }
2123 else
2124 {
2125 fprintf (file, "\tsethi %%hi(-%d),%%g1\n", actual_fsize);
2126 if ((actual_fsize & 0x3ff) != 0)
2127 fprintf (file, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize);
2128 fprintf (file, "\tadd %%sp,%%g1,%%sp\n");
2129 }
2130 }
2131
2132 /* If doing anything with PIC, do it now. */
2133 if (! flag_pic)
2134 fprintf (file, "\t!#PROLOGUE# 1\n");
2135
2136 /* Figure out where to save any special registers. */
2137 if (num_fregs)
2138 {
2139 int offset, n_fregs = num_fregs;
2140
2141 /* ??? This should always be -apparent_fsize. */
2142 if (! leaf_function)
2143 offset = -apparent_fsize;
2144 else
2145 offset = 0;
2146
2147 if (TARGET_EPILOGUE && ! leaf_function)
2148 n_fregs = save_regs (file, 0, 16, frame_base_name, offset, 0);
2149 else if (leaf_function)
2150 n_fregs = save_regs (file, 0, 32, frame_base_name, offset, 0);
2151 if (TARGET_EPILOGUE)
2152 save_regs (file, 32, FIRST_PSEUDO_REGISTER,
2153 frame_base_name, offset, n_fregs);
2154 }
2155
2156 leaf_label = 0;
2157 if (leaf_function && actual_fsize != 0)
2158 {
2159 /* warning ("leaf procedure with frame size %d", actual_fsize); */
2160 if (! TARGET_EPILOGUE)
2161 leaf_label = gen_label_rtx ();
2162 }
2163 }
2164
2165 /* Output code for the function epilogue. */
2166
2167 void
2168 output_function_epilogue (file, size, leaf_function)
2169 FILE *file;
2170 int size;
2171 int leaf_function;
2172 {
2173 char *ret;
2174
2175 if (leaf_label)
2176 {
2177 emit_label_after (leaf_label, get_last_insn ());
2178 final_scan_insn (get_last_insn (), file, 0, 0, 1);
2179 }
2180
2181 if (num_fregs)
2182 {
2183 int offset, n_fregs = num_fregs;
2184
2185 /* ??? This should always be -apparent_fsize. */
2186 if (! leaf_function)
2187 offset = -apparent_fsize;
2188 else
2189 offset = 0;
2190
2191 if (TARGET_EPILOGUE && ! leaf_function)
2192 n_fregs = restore_regs (file, 0, 16, frame_base_name, offset, 0);
2193 else if (leaf_function)
2194 n_fregs = restore_regs (file, 0, 32, frame_base_name, offset, 0);
2195 if (TARGET_EPILOGUE)
2196 restore_regs (file, 32, FIRST_PSEUDO_REGISTER,
2197 frame_base_name, offset, n_fregs);
2198 }
2199
2200 /* Work out how to skip the caller's unimp instruction if required. */
2201 if (leaf_function)
2202 ret = (current_function_returns_struct ? "jmp %o7+12" : "retl");
2203 else
2204 ret = (current_function_returns_struct ? "jmp %i7+12" : "ret");
2205
2206 if (TARGET_EPILOGUE || leaf_label)
2207 {
2208 int old_target_epilogue = TARGET_EPILOGUE;
2209 target_flags &= ~old_target_epilogue;
2210
2211 if (! leaf_function)
2212 {
2213 /* If we wound up with things in our delay slot, flush them here. */
2214 if (current_function_epilogue_delay_list)
2215 {
2216 rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode),
2217 get_last_insn ());
2218 PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode,
2219 gen_rtvec (2,
2220 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
2221 PATTERN (insn)));
2222 final_scan_insn (insn, file, 1, 0, 1);
2223 }
2224 else
2225 fprintf (file, "\t%s\n\trestore\n", ret);
2226 }
2227 /* All of the following cases are for leaf functions. */
2228 else if (current_function_epilogue_delay_list)
2229 {
2230 /* eligible_for_epilogue_delay_slot ensures that if this is a
2231 leaf function, then we will only have insn in the delay slot
2232 if the frame size is zero, thus no adjust for the stack is
2233 needed here. */
2234 if (actual_fsize != 0)
2235 abort ();
2236 fprintf (file, "\t%s\n", ret);
2237 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
2238 file, 1, 0, 1);
2239 }
2240 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
2241 avoid generating confusing assembly language output. */
2242 else if (actual_fsize == 0)
2243 fprintf (file, "\t%s\n\tnop\n", ret);
2244 else if (actual_fsize <= 4096)
2245 fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize);
2246 else if (actual_fsize <= 8192)
2247 fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
2248 ret, actual_fsize - 4096);
2249 else if ((actual_fsize & 0x3ff) == 0)
2250 fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
2251 actual_fsize, ret);
2252 else
2253 fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
2254 actual_fsize, actual_fsize, ret);
2255 target_flags |= old_target_epilogue;
2256 }
2257 }
2258
2259 /* Do what is necessary for `va_start'. The argument is ignored;
2260 We look at the current function to determine if stdarg or varargs
2261 is used and return the address of the first unnamed parameter. */
2262
2263 rtx
2264 sparc_builtin_saveregs (arglist)
2265 tree arglist;
2266 {
2267 tree fntype = TREE_TYPE (current_function_decl);
2268 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
2269 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
2270 != void_type_node));
2271 int first_reg = current_function_args_info;
2272 rtx address;
2273 int regno;
2274
2275 #if 0 /* This code seemed to have no effect except to make
2276 varargs not work right when va_list wasn't the first arg. */
2277 if (! stdarg)
2278 first_reg = 0;
2279 #endif
2280
2281 for (regno = first_reg; regno < NPARM_REGS; regno++)
2282 emit_move_insn (gen_rtx (MEM, word_mode,
2283 gen_rtx (PLUS, Pmode,
2284 frame_pointer_rtx,
2285 GEN_INT (STACK_POINTER_OFFSET
2286 + UNITS_PER_WORD * regno))),
2287 gen_rtx (REG, word_mode, BASE_INCOMING_ARG_REG (word_mode)
2288 + regno));
2289
2290 address = gen_rtx (PLUS, Pmode,
2291 frame_pointer_rtx,
2292 GEN_INT (STACK_POINTER_OFFSET
2293 + UNITS_PER_WORD * first_reg));
2294
2295 return address;
2296 }
2297 \f
2298 /* Return the string to output a conditional branch to LABEL, which is
2299 the operand number of the label. OP is the conditional expression. The
2300 mode of register 0 says what kind of comparison we made.
2301
2302 REVERSED is non-zero if we should reverse the sense of the comparison.
2303
2304 ANNUL is non-zero if we should generate an annulling branch.
2305
2306 NOOP is non-zero if we have to follow this branch by a noop. */
2307
2308 char *
2309 output_cbranch (op, label, reversed, annul, noop)
2310 rtx op;
2311 int label;
2312 int reversed, annul, noop;
2313 {
2314 static char string[20];
2315 enum rtx_code code = GET_CODE (op);
2316 enum machine_mode mode = GET_MODE (XEXP (op, 0));
2317 static char labelno[] = " %lX";
2318
2319 /* ??? FP branches can not be preceded by another floating point insn.
2320 Because there is currently no concept of pre-delay slots, we can fix
2321 this only by always emitting a nop before a floating point branch. */
2322
2323 if (mode == CCFPmode || mode == CCFPEmode)
2324 strcpy (string, "nop\n\t");
2325
2326 /* If not floating-point or if EQ or NE, we can just reverse the code. */
2327 if (reversed
2328 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
2329 code = reverse_condition (code), reversed = 0;
2330
2331 /* Start by writing the branch condition. */
2332 switch (code)
2333 {
2334 case NE:
2335 if (mode == CCFPmode || mode == CCFPEmode)
2336 strcat (string, "fbne");
2337 else
2338 strcpy (string, "bne");
2339 break;
2340
2341 case EQ:
2342 if (mode == CCFPmode || mode == CCFPEmode)
2343 strcat (string, "fbe");
2344 else
2345 strcpy (string, "be");
2346 break;
2347
2348 case GE:
2349 if (mode == CCFPmode || mode == CCFPEmode)
2350 {
2351 if (reversed)
2352 strcat (string, "fbul");
2353 else
2354 strcat (string, "fbge");
2355 }
2356 else if (mode == CC_NOOVmode)
2357 strcpy (string, "bpos");
2358 else
2359 strcpy (string, "bge");
2360 break;
2361
2362 case GT:
2363 if (mode == CCFPmode || mode == CCFPEmode)
2364 {
2365 if (reversed)
2366 strcat (string, "fbule");
2367 else
2368 strcat (string, "fbg");
2369 }
2370 else
2371 strcpy (string, "bg");
2372 break;
2373
2374 case LE:
2375 if (mode == CCFPmode || mode == CCFPEmode)
2376 {
2377 if (reversed)
2378 strcat (string, "fbug");
2379 else
2380 strcat (string, "fble");
2381 }
2382 else
2383 strcpy (string, "ble");
2384 break;
2385
2386 case LT:
2387 if (mode == CCFPmode || mode == CCFPEmode)
2388 {
2389 if (reversed)
2390 strcat (string, "fbuge");
2391 else
2392 strcat (string, "fbl");
2393 }
2394 else if (mode == CC_NOOVmode)
2395 strcpy (string, "bneg");
2396 else
2397 strcpy (string, "bl");
2398 break;
2399
2400 case GEU:
2401 strcpy (string, "bgeu");
2402 break;
2403
2404 case GTU:
2405 strcpy (string, "bgu");
2406 break;
2407
2408 case LEU:
2409 strcpy (string, "bleu");
2410 break;
2411
2412 case LTU:
2413 strcpy (string, "blu");
2414 break;
2415 }
2416
2417 /* Now add the annulling, the label, and a possible noop. */
2418 if (annul)
2419 strcat (string, ",a");
2420
2421 labelno[3] = label + '0';
2422 strcat (string, labelno);
2423
2424 if (noop)
2425 strcat (string, "\n\tnop");
2426
2427 return string;
2428 }
2429
2430 /* Output assembler code to return from a function. */
2431
2432 char *
2433 output_return (operands)
2434 rtx *operands;
2435 {
2436 if (leaf_label)
2437 {
2438 operands[0] = leaf_label;
2439 return "b,a %l0";
2440 }
2441 else if (leaf_function)
2442 {
2443 /* If we didn't allocate a frame pointer for the current function,
2444 the stack pointer might have been adjusted. Output code to
2445 restore it now. */
2446
2447 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize);
2448
2449 /* Use sub of negated value in first two cases instead of add to
2450 allow actual_fsize == 4096. */
2451
2452 if (actual_fsize <= 4096)
2453 {
2454 if (current_function_returns_struct)
2455 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
2456 else
2457 return "retl\n\tsub %%sp,-%0,%%sp";
2458 }
2459 else if (actual_fsize <= 8192)
2460 {
2461 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096);
2462 if (current_function_returns_struct)
2463 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
2464 else
2465 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
2466 }
2467 else if (current_function_returns_struct)
2468 {
2469 if ((actual_fsize & 0x3ff) != 0)
2470 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
2471 else
2472 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
2473 }
2474 else
2475 {
2476 if ((actual_fsize & 0x3ff) != 0)
2477 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
2478 else
2479 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
2480 }
2481 }
2482 else
2483 {
2484 if (current_function_returns_struct)
2485 return "jmp %%i7+12\n\trestore";
2486 else
2487 return "ret\n\trestore";
2488 }
2489 }
2490 \f
2491 /* Leaf functions and non-leaf functions have different needs. */
2492
2493 static int
2494 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
2495
2496 static int
2497 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
2498
2499 static int *reg_alloc_orders[] = {
2500 reg_leaf_alloc_order,
2501 reg_nonleaf_alloc_order};
2502
2503 void
2504 order_regs_for_local_alloc ()
2505 {
2506 static int last_order_nonleaf = 1;
2507
2508 if (regs_ever_live[15] != last_order_nonleaf)
2509 {
2510 last_order_nonleaf = !last_order_nonleaf;
2511 bcopy (reg_alloc_orders[last_order_nonleaf], reg_alloc_order,
2512 FIRST_PSEUDO_REGISTER * sizeof (int));
2513 }
2514 }
2515 \f
2516 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
2517 This makes them candidates for using ldd and std insns.
2518
2519 Note reg1 and reg2 *must* be hard registers. To be sure we will
2520 abort if we are passed pseudo registers. */
2521
2522 int
2523 registers_ok_for_ldd_peep (reg1, reg2)
2524 rtx reg1, reg2;
2525 {
2526
2527 /* We might have been passed a SUBREG. */
2528 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
2529 return 0;
2530
2531 if (REGNO (reg1) % 2 != 0)
2532 return 0;
2533
2534 return (REGNO (reg1) == REGNO (reg2) - 1);
2535
2536 }
2537
2538 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
2539 std insn.
2540
2541 This can only happen when addr1 and addr2 are consecutive memory
2542 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
2543 64 bit boundary (addr1 % 8 == 0).
2544
2545 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
2546 registers are assumed to *never* be properly aligned and are
2547 rejected.
2548
2549 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
2550 need only check that the offset for addr1 % 8 == 0. */
2551
2552 int
2553 addrs_ok_for_ldd_peep (addr1, addr2)
2554 rtx addr1, addr2;
2555 {
2556 int reg1, offset1;
2557
2558 /* Extract a register number and offset (if used) from the first addr. */
2559 if (GET_CODE (addr1) == PLUS)
2560 {
2561 /* If not a REG, return zero. */
2562 if (GET_CODE (XEXP (addr1, 0)) != REG)
2563 return 0;
2564 else
2565 {
2566 reg1 = REGNO (XEXP (addr1, 0));
2567 /* The offset must be constant! */
2568 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
2569 return 0;
2570 offset1 = INTVAL (XEXP (addr1, 1));
2571 }
2572 }
2573 else if (GET_CODE (addr1) != REG)
2574 return 0;
2575 else
2576 {
2577 reg1 = REGNO (addr1);
2578 /* This was a simple (mem (reg)) expression. Offset is 0. */
2579 offset1 = 0;
2580 }
2581
2582 /* Make sure the second address is a (mem (plus (reg) (const_int). */
2583 if (GET_CODE (addr2) != PLUS)
2584 return 0;
2585
2586 if (GET_CODE (XEXP (addr2, 0)) != REG
2587 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
2588 return 0;
2589
2590 /* Only %fp and %sp are allowed. Additionally both addresses must
2591 use the same register. */
2592 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
2593 return 0;
2594
2595 if (reg1 != REGNO (XEXP (addr2, 0)))
2596 return 0;
2597
2598 /* The first offset must be evenly divisible by 8 to ensure the
2599 address is 64 bit aligned. */
2600 if (offset1 % 8 != 0)
2601 return 0;
2602
2603 /* The offset for the second addr must be 4 more than the first addr. */
2604 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
2605 return 0;
2606
2607 /* All the tests passed. addr1 and addr2 are valid for ldd and std
2608 instructions. */
2609 return 1;
2610 }
2611
2612 /* Return 1 if reg is a pseudo, or is the first register in
2613 a hard register pair. This makes it a candidate for use in
2614 ldd and std insns. */
2615
2616 int
2617 register_ok_for_ldd (reg)
2618 rtx reg;
2619 {
2620
2621 /* We might have been passed a SUBREG. */
2622 if (GET_CODE (reg) != REG)
2623 return 0;
2624
2625 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
2626 return (REGNO (reg) % 2 == 0);
2627 else
2628 return 1;
2629
2630 }
2631 \f
2632 /* Print operand X (an rtx) in assembler syntax to file FILE.
2633 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2634 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2635
2636 void
2637 print_operand (file, x, code)
2638 FILE *file;
2639 rtx x;
2640 int code;
2641 {
2642 switch (code)
2643 {
2644 case '#':
2645 /* Output a 'nop' if there's nothing for the delay slot. */
2646 if (dbr_sequence_length () == 0)
2647 fputs ("\n\tnop", file);
2648 return;
2649 case '*':
2650 /* Output an annul flag if there's nothing for the delay slot and we
2651 are optimizing. This is always used with '(' below. */
2652 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
2653 this is a dbx bug. So, we only do this when optimizing. */
2654 if (dbr_sequence_length () == 0 && optimize)
2655 fputs (",a", file);
2656 return;
2657 case '(':
2658 /* Output a 'nop' if there's nothing for the delay slot and we are
2659 not optimizing. This is always used with '*' above. */
2660 if (dbr_sequence_length () == 0 && ! optimize)
2661 fputs ("\n\tnop", file);
2662 return;
2663 case 'Y':
2664 /* Adjust the operand to take into account a RESTORE operation. */
2665 if (GET_CODE (x) != REG)
2666 output_operand_lossage ("Invalid %%Y operand");
2667 else if (REGNO (x) < 8)
2668 fputs (reg_names[REGNO (x)], file);
2669 else if (REGNO (x) >= 24 && REGNO (x) < 32)
2670 fputs (reg_names[REGNO (x)-16], file);
2671 else
2672 output_operand_lossage ("Invalid %%Y operand");
2673 return;
2674 case 'R':
2675 /* Print out the second register name of a register pair or quad.
2676 I.e., R (%o0) => %o1. */
2677 fputs (reg_names[REGNO (x)+1], file);
2678 return;
2679 case 'S':
2680 /* Print out the third register name of a register quad.
2681 I.e., S (%o0) => %o2. */
2682 fputs (reg_names[REGNO (x)+2], file);
2683 return;
2684 case 'T':
2685 /* Print out the fourth register name of a register quad.
2686 I.e., T (%o0) => %o3. */
2687 fputs (reg_names[REGNO (x)+3], file);
2688 return;
2689 case 'm':
2690 /* Print the operand's address only. */
2691 output_address (XEXP (x, 0));
2692 return;
2693 case 'r':
2694 /* In this case we need a register. Use %g0 if the
2695 operand is const0_rtx. */
2696 if (x == const0_rtx
2697 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
2698 {
2699 fputs ("%g0", file);
2700 return;
2701 }
2702 else
2703 break;
2704
2705 case 'A':
2706 switch (GET_CODE (x))
2707 {
2708 case IOR: fputs ("or", file); break;
2709 case AND: fputs ("and", file); break;
2710 case XOR: fputs ("xor", file); break;
2711 default: output_operand_lossage ("Invalid %%A operand");
2712 }
2713 return;
2714
2715 case 'B':
2716 switch (GET_CODE (x))
2717 {
2718 case IOR: fputs ("orn", file); break;
2719 case AND: fputs ("andn", file); break;
2720 case XOR: fputs ("xnor", file); break;
2721 default: output_operand_lossage ("Invalid %%B operand");
2722 }
2723 return;
2724
2725 case 'b':
2726 {
2727 /* Print a sign-extended character. */
2728 int i = INTVAL (x) & 0xff;
2729 if (i & 0x80)
2730 i |= 0xffffff00;
2731 fprintf (file, "%d", i);
2732 return;
2733 }
2734
2735 case 0:
2736 /* Do nothing special. */
2737 break;
2738
2739 default:
2740 /* Undocumented flag. */
2741 output_operand_lossage ("invalid operand output code");
2742 }
2743
2744 if (GET_CODE (x) == REG)
2745 fputs (reg_names[REGNO (x)], file);
2746 else if (GET_CODE (x) == MEM)
2747 {
2748 fputc ('[', file);
2749 if (CONSTANT_P (XEXP (x, 0)))
2750 /* Poor Sun assembler doesn't understand absolute addressing. */
2751 fputs ("%g0+", file);
2752 output_address (XEXP (x, 0));
2753 fputc (']', file);
2754 }
2755 else if (GET_CODE (x) == HIGH)
2756 {
2757 fputs ("%hi(", file);
2758 output_addr_const (file, XEXP (x, 0));
2759 fputc (')', file);
2760 }
2761 else if (GET_CODE (x) == LO_SUM)
2762 {
2763 print_operand (file, XEXP (x, 0), 0);
2764 fputs ("+%lo(", file);
2765 output_addr_const (file, XEXP (x, 1));
2766 fputc (')', file);
2767 }
2768 else if (GET_CODE (x) == CONST_DOUBLE
2769 && (GET_MODE (x) == VOIDmode
2770 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
2771 {
2772 if (CONST_DOUBLE_HIGH (x) == 0)
2773 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
2774 else if (CONST_DOUBLE_HIGH (x) == -1
2775 && CONST_DOUBLE_LOW (x) < 0)
2776 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
2777 else
2778 output_operand_lossage ("long long constant not a valid immediate operand");
2779 }
2780 else if (GET_CODE (x) == CONST_DOUBLE)
2781 output_operand_lossage ("floating point constant not a valid immediate operand");
2782 else { output_addr_const (file, x); }
2783 }
2784 \f
2785 /* This function outputs assembler code for VALUE to FILE, where VALUE is
2786 a 64 bit (DImode) value. */
2787
2788 /* ??? If there is a 64 bit counterpart to .word that the assembler
2789 understands, then using that would simply this code greatly. */
2790
2791 void
2792 output_double_int (file, value)
2793 FILE *file;
2794 rtx value;
2795 {
2796 if (GET_CODE (value) == CONST_INT)
2797 {
2798 if (INTVAL (value) < 0)
2799 ASM_OUTPUT_INT (file, constm1_rtx);
2800 else
2801 ASM_OUTPUT_INT (file, const0_rtx);
2802 ASM_OUTPUT_INT (file, value);
2803 }
2804 else if (GET_CODE (value) == CONST_DOUBLE)
2805 {
2806 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
2807 CONST_DOUBLE_HIGH (value)));
2808 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
2809 CONST_DOUBLE_LOW (value)));
2810 }
2811 else if (GET_CODE (value) == SYMBOL_REF
2812 || GET_CODE (value) == CONST
2813 || GET_CODE (value) == PLUS)
2814 {
2815 /* Addresses are only 32 bits. */
2816 ASM_OUTPUT_INT (file, const0_rtx);
2817 ASM_OUTPUT_INT (file, value);
2818 }
2819 else
2820 abort ();
2821 }
2822 \f
2823 #ifndef CHAR_TYPE_SIZE
2824 #define CHAR_TYPE_SIZE BITS_PER_UNIT
2825 #endif
2826
2827 #ifndef SHORT_TYPE_SIZE
2828 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
2829 #endif
2830
2831 #ifndef INT_TYPE_SIZE
2832 #define INT_TYPE_SIZE BITS_PER_WORD
2833 #endif
2834
2835 #ifndef LONG_TYPE_SIZE
2836 #define LONG_TYPE_SIZE BITS_PER_WORD
2837 #endif
2838
2839 #ifndef LONG_LONG_TYPE_SIZE
2840 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
2841 #endif
2842
2843 #ifndef FLOAT_TYPE_SIZE
2844 #define FLOAT_TYPE_SIZE BITS_PER_WORD
2845 #endif
2846
2847 #ifndef DOUBLE_TYPE_SIZE
2848 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
2849 #endif
2850
2851 #ifndef LONG_DOUBLE_TYPE_SIZE
2852 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
2853 #endif
2854
2855 unsigned long
2856 sparc_type_code (type)
2857 register tree type;
2858 {
2859 register unsigned long qualifiers = 0;
2860 register unsigned shift = 6;
2861
2862 for (;;)
2863 {
2864 switch (TREE_CODE (type))
2865 {
2866 case ERROR_MARK:
2867 return qualifiers;
2868
2869 case ARRAY_TYPE:
2870 qualifiers |= (3 << shift);
2871 shift += 2;
2872 type = TREE_TYPE (type);
2873 break;
2874
2875 case FUNCTION_TYPE:
2876 case METHOD_TYPE:
2877 qualifiers |= (2 << shift);
2878 shift += 2;
2879 type = TREE_TYPE (type);
2880 break;
2881
2882 case POINTER_TYPE:
2883 case REFERENCE_TYPE:
2884 case OFFSET_TYPE:
2885 qualifiers |= (1 << shift);
2886 shift += 2;
2887 type = TREE_TYPE (type);
2888 break;
2889
2890 case RECORD_TYPE:
2891 return (qualifiers | 8);
2892
2893 case UNION_TYPE:
2894 return (qualifiers | 9);
2895
2896 case ENUMERAL_TYPE:
2897 return (qualifiers | 10);
2898
2899 case VOID_TYPE:
2900 return (qualifiers | 16);
2901
2902 case INTEGER_TYPE:
2903 /* Carefully distinguish all the standard types of C,
2904 without messing up if the language is not C.
2905 Note that we check only for the names that contain spaces;
2906 other names might occur by coincidence in other languages. */
2907 if (TYPE_NAME (type) != 0
2908 && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
2909 && DECL_NAME (TYPE_NAME (type)) != 0
2910 && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE)
2911 {
2912 char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
2913
2914 if (!strcmp (name, "unsigned char"))
2915 return (qualifiers | 12);
2916 if (!strcmp (name, "signed char"))
2917 return (qualifiers | 2);
2918 if (!strcmp (name, "unsigned int"))
2919 return (qualifiers | 14);
2920 if (!strcmp (name, "short int"))
2921 return (qualifiers | 3);
2922 if (!strcmp (name, "short unsigned int"))
2923 return (qualifiers | 13);
2924 if (!strcmp (name, "long int"))
2925 return (qualifiers | 5);
2926 if (!strcmp (name, "long unsigned int"))
2927 return (qualifiers | 15);
2928 if (!strcmp (name, "long long int"))
2929 return (qualifiers | 5); /* Who knows? */
2930 if (!strcmp (name, "long long unsigned int"))
2931 return (qualifiers | 15); /* Who knows? */
2932 }
2933
2934 /* Most integer types will be sorted out above, however, for the
2935 sake of special `array index' integer types, the following code
2936 is also provided. */
2937
2938 if (TYPE_PRECISION (type) == INT_TYPE_SIZE)
2939 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
2940
2941 if (TYPE_PRECISION (type) == LONG_TYPE_SIZE)
2942 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
2943
2944 if (TYPE_PRECISION (type) == LONG_LONG_TYPE_SIZE)
2945 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
2946
2947 if (TYPE_PRECISION (type) == SHORT_TYPE_SIZE)
2948 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
2949
2950 if (TYPE_PRECISION (type) == CHAR_TYPE_SIZE)
2951 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
2952
2953 abort ();
2954
2955 case REAL_TYPE:
2956 /* Carefully distinguish all the standard types of C,
2957 without messing up if the language is not C. */
2958 if (TYPE_NAME (type) != 0
2959 && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
2960 && DECL_NAME (TYPE_NAME (type)) != 0
2961 && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE)
2962 {
2963 char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
2964
2965 if (!strcmp (name, "long double"))
2966 return (qualifiers | 7); /* Who knows? */
2967 }
2968
2969 if (TYPE_PRECISION (type) == DOUBLE_TYPE_SIZE)
2970 return (qualifiers | 7);
2971 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
2972 return (qualifiers | 6);
2973 if (TYPE_PRECISION (type) == LONG_DOUBLE_TYPE_SIZE)
2974 return (qualifiers | 7); /* Who knows? */
2975 abort ();
2976
2977 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
2978 /* ??? We need to distinguish between double and float complex types,
2979 but I don't know how yet because I can't reach this code from
2980 existing front-ends. */
2981 return (qualifiers | 7); /* Who knows? */
2982
2983 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
2984 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
2985 case FILE_TYPE: /* GNU Pascal FILE type. */
2986 case STRING_TYPE: /* GNU Fortran STRING type. */
2987 case LANG_TYPE: /* ? */
2988 abort ();
2989
2990 default:
2991 abort (); /* Not a type! */
2992 }
2993 }
2994 }
2995 \f
2996 /* Subroutines to support a flat (single) register window calling
2997 convention. */
2998
2999 /* Single-register window sparc stack frames look like:
3000
3001 Before call After call
3002 +-----------------------+ +-----------------------+
3003 high | | | |
3004 mem. | | | |
3005 | caller's temps. | | caller's temps. |
3006 | | | |
3007 +-----------------------+ +-----------------------+
3008 | | | |
3009 | arguments on stack. | | arguments on stack. |
3010 | |FP+92->| |
3011 +-----------------------+ +-----------------------+
3012 | 6 words to save | | 6 words to save |
3013 | arguments passed | | arguments passed |
3014 | in registers, even | | in registers, even |
3015 SP+68->| if not passed. |FP+68->| if not passed. |
3016 +-----------------------+ +-----------------------+
3017 | 1 word struct addr |FP+64->| 1 word struct addr |
3018 +-----------------------+ +-----------------------+
3019 | | | |
3020 | 16 word reg save area | | 16 word reg save area |
3021 SP->| | FP->| |
3022 +-----------------------+ +-----------------------+
3023 | 4 word area for |
3024 FP-16->| fp/alu reg moves |
3025 +-----------------------+
3026 | |
3027 | local variables |
3028 | |
3029 +-----------------------+
3030 | |
3031 | fp register save |
3032 | |
3033 +-----------------------+
3034 | |
3035 | gp register save |
3036 | |
3037 +-----------------------+
3038 | |
3039 | alloca allocations |
3040 | |
3041 +-----------------------+
3042 | |
3043 | arguments on stack |
3044 SP+92->| |
3045 +-----------------------+
3046 | 6 words to save |
3047 | arguments passed |
3048 | in registers, even |
3049 low SP+68->| if not passed. |
3050 memory +-----------------------+
3051 SP+64->| 1 word struct addr |
3052 +-----------------------+
3053 | |
3054 I 16 word reg save area |
3055 SP->| |
3056 +-----------------------+ */
3057
3058 /* Structure to be filled in by sparc_frw_compute_frame_size with register
3059 save masks, and offsets for the current function. */
3060
3061 struct sparc_frame_info
3062 {
3063 unsigned long total_size; /* # bytes that the entire frame takes up. */
3064 unsigned long var_size; /* # bytes that variables take up. */
3065 unsigned long args_size; /* # bytes that outgoing arguments take up. */
3066 unsigned long extra_size; /* # bytes of extra gunk. */
3067 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
3068 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
3069 unsigned long mask; /* Mask of saved gp registers. */
3070 unsigned long fmask; /* Mask of saved fp registers. */
3071 unsigned long gp_sp_offset; /* Offset from new sp to store gp regs. */
3072 unsigned long fp_sp_offset; /* Offset from new sp to store fp regs. */
3073 int initialized; /* Nonzero if frame size already calculated. */
3074 };
3075
3076 /* Current frame information calculated by sparc_frw_compute_frame_size. */
3077 struct sparc_frame_info current_frame_info;
3078
3079 /* Zero structure to initialize current_frame_info. */
3080 struct sparc_frame_info zero_frame_info;
3081
3082 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
3083
3084 #define MUST_SAVE_REGISTER(regno) \
3085 ((regs_ever_live[regno] && !call_used_regs[regno]) \
3086 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
3087 || (regno == 15 && regs_ever_live[15]))
3088
3089 /* Return the bytes needed to compute the frame pointer from the current
3090 stack pointer. */
3091
3092 unsigned long
3093 sparc_frw_compute_frame_size (size)
3094 int size; /* # of var. bytes allocated. */
3095 {
3096 int regno;
3097 unsigned long total_size; /* # bytes that the entire frame takes up. */
3098 unsigned long var_size; /* # bytes that variables take up. */
3099 unsigned long args_size; /* # bytes that outgoing arguments take up. */
3100 unsigned long extra_size; /* # extra bytes. */
3101 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
3102 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
3103 unsigned long mask; /* Mask of saved gp registers. */
3104 unsigned long fmask; /* Mask of saved fp registers. */
3105
3106 /* This is the size of the 16 word reg save area, 1 word struct addr
3107 area, and 4 word fp/alu register copy area. */
3108 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
3109 var_size = size;
3110 /* Also include the size needed for the 6 parameter registers. */
3111 args_size = current_function_outgoing_args_size + 24;
3112 total_size = var_size + args_size + extra_size;
3113 gp_reg_size = 0;
3114 fp_reg_size = 0;
3115 mask = 0;
3116 fmask = 0;
3117
3118 /* Calculate space needed for gp registers. */
3119 for (regno = 1; regno <= 31; regno++)
3120 {
3121 if (MUST_SAVE_REGISTER (regno))
3122 {
3123 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
3124 {
3125 if (gp_reg_size % 8 != 0)
3126 gp_reg_size += UNITS_PER_WORD;
3127 gp_reg_size += 2 * UNITS_PER_WORD;
3128 mask |= 3 << regno;
3129 regno++;
3130 }
3131 else
3132 {
3133 gp_reg_size += UNITS_PER_WORD;
3134 mask |= 1 << regno;
3135 }
3136 }
3137 }
3138 /* Add extra word in case we have to align the space to a double word
3139 boundary. */
3140 if (gp_reg_size != 0)
3141 gp_reg_size += UNITS_PER_WORD;
3142
3143 /* Calculate space needed for fp registers. */
3144 for (regno = 32; regno <= 63; regno++)
3145 {
3146 if (regs_ever_live[regno] && !call_used_regs[regno])
3147 {
3148 fp_reg_size += UNITS_PER_WORD;
3149 fmask |= 1 << (regno - 32);
3150 }
3151 }
3152
3153 total_size += gp_reg_size + fp_reg_size;
3154
3155 if (total_size == extra_size)
3156 total_size = extra_size = 0;
3157
3158 total_size = SPARC_STACK_ALIGN (total_size);
3159
3160 /* Save other computed information. */
3161 current_frame_info.total_size = total_size;
3162 current_frame_info.var_size = var_size;
3163 current_frame_info.args_size = args_size;
3164 current_frame_info.extra_size = extra_size;
3165 current_frame_info.gp_reg_size = gp_reg_size;
3166 current_frame_info.fp_reg_size = fp_reg_size;
3167 current_frame_info.mask = mask;
3168 current_frame_info.fmask = fmask;
3169 current_frame_info.initialized = reload_completed;
3170
3171 if (mask)
3172 {
3173 unsigned long offset = args_size;
3174 if (extra_size)
3175 offset += FIRST_PARM_OFFSET(0);
3176 current_frame_info.gp_sp_offset = offset;
3177 }
3178
3179 if (fmask)
3180 {
3181 unsigned long offset = args_size + gp_reg_size;
3182 if (extra_size)
3183 offset += FIRST_PARM_OFFSET(0);
3184 current_frame_info.fp_sp_offset = offset;
3185 }
3186
3187 /* Ok, we're done. */
3188 return total_size;
3189 }
3190 \f
3191 /* Common code to save/restore registers. */
3192
3193 void
3194 sparc_frw_save_restore (file, word_op, doubleword_op)
3195 FILE *file; /* Stream to write to. */
3196 char *word_op; /* Operation to do for one word. */
3197 char *doubleword_op; /* Operation to do for doubleword. */
3198 {
3199 int regno;
3200 unsigned long mask = current_frame_info.mask;
3201 unsigned long fmask = current_frame_info.fmask;
3202 unsigned long gp_offset;
3203 unsigned long fp_offset;
3204 unsigned long max_offset;
3205 char *base_reg;
3206
3207 if (mask == 0 && fmask == 0)
3208 return;
3209
3210 base_reg = reg_names[STACK_POINTER_REGNUM];
3211 gp_offset = current_frame_info.gp_sp_offset;
3212 fp_offset = current_frame_info.fp_sp_offset;
3213 max_offset = (gp_offset > fp_offset) ? gp_offset : fp_offset;
3214
3215 /* Deal with calling functions with a large structure. */
3216 if (max_offset >= 4096)
3217 {
3218 char *temp = "%g2";
3219 fprintf (file, "\tset %ld,%s\n", max_offset, temp);
3220 fprintf (file, "\tadd %s,%s,%s\n", temp, base_reg, temp);
3221 base_reg = temp;
3222 gp_offset = max_offset - gp_offset;
3223 fp_offset = max_offset - fp_offset;
3224 }
3225
3226 /* Save registers starting from high to low. The debuggers prefer
3227 at least the return register be stored at func+4, and also it
3228 allows us not to need a nop in the epilog if at least one
3229 register is reloaded in addition to return address. */
3230
3231 if (mask || frame_pointer_needed)
3232 {
3233 for (regno = 1; regno <= 31; regno++)
3234 {
3235 if ((mask & (1L << regno)) != 0
3236 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed))
3237 {
3238 if ((regno & 0x1) == 0 && ((mask & (1L << regno+1)) != 0))
3239 {
3240 if (gp_offset % 8 != 0)
3241 gp_offset += UNITS_PER_WORD;
3242
3243 if (word_op[0] == 's')
3244 fprintf (file, "\t%s %s,[%s+%d]\n",
3245 doubleword_op, reg_names[regno],
3246 base_reg, gp_offset);
3247 else
3248 fprintf (file, "\t%s [%s+%d],%s\n",
3249 doubleword_op, base_reg, gp_offset,
3250 reg_names[regno]);
3251
3252 gp_offset += 2 * UNITS_PER_WORD;
3253 regno++;
3254 }
3255 else
3256 {
3257 if (word_op[0] == 's')
3258 fprintf (file, "\t%s %s,[%s+%d]\n",
3259 word_op, reg_names[regno],
3260 base_reg, gp_offset);
3261 else
3262 fprintf (file, "\t%s [%s+%d],%s\n",
3263 word_op, base_reg, gp_offset, reg_names[regno]);
3264
3265 gp_offset += UNITS_PER_WORD;
3266 }
3267 }
3268 }
3269 }
3270
3271 if (fmask)
3272 {
3273 for (regno = 32; regno <= 63; regno++)
3274 {
3275 if ((fmask & (1L << (regno - 32))) != 0)
3276 {
3277 if (word_op[0] == 's')
3278 fprintf (file, "\t%s %s,[%s+%d]\n",
3279 word_op, reg_names[regno],
3280 base_reg, gp_offset);
3281 else
3282 fprintf (file, "\t%s [%s+%d],%s\n",
3283 word_op, base_reg, gp_offset, reg_names[regno]);
3284
3285 fp_offset += UNITS_PER_WORD;
3286 }
3287 }
3288 }
3289 }
3290 \f
3291 /* Set up the stack and frame (if desired) for the function. */
3292
3293 void
3294 sparc_frw_output_function_prologue (file, size, ignored)
3295 FILE *file;
3296 int size;
3297 {
3298 extern char call_used_regs[];
3299 int tsize;
3300 char *sp_str = reg_names[STACK_POINTER_REGNUM];
3301
3302 /* ??? This should be %sp+actual_fsize for a leaf function. I think it
3303 works only because it is never used. */
3304 frame_base_name
3305 = (!frame_pointer_needed) ? "%sp+80" : reg_names[FRAME_POINTER_REGNUM];
3306
3307 fprintf (file, "\t!#PROLOGUE# 0\n");
3308
3309 size = SPARC_STACK_ALIGN (size);
3310 tsize = (! current_frame_info.initialized
3311 ? sparc_frw_compute_frame_size (size)
3312 : current_frame_info.total_size);
3313
3314 if (tsize > 0)
3315 {
3316 if (tsize <= 4095)
3317 fprintf (file,
3318 "\tsub %s,%d,%s\t\t!# vars= %d, regs= %d/%d, args = %d, extra= %d\n",
3319 sp_str, tsize, sp_str, current_frame_info.var_size,
3320 current_frame_info.gp_reg_size / 4,
3321 current_frame_info.fp_reg_size / 8,
3322 current_function_outgoing_args_size,
3323 current_frame_info.extra_size);
3324 else
3325 fprintf (file,
3326 "\tset %d,%s\n\tsub\t%s,%s,%s\t\t!# vars= %d, regs= %d/%d, args = %d, sfo= %d\n",
3327 tsize, "%g1", sp_str, "%g1",
3328 sp_str, current_frame_info.var_size,
3329 current_frame_info.gp_reg_size / 4,
3330 current_frame_info.fp_reg_size / 8,
3331 current_function_outgoing_args_size,
3332 current_frame_info.extra_size);
3333 }
3334
3335 sparc_frw_save_restore (file, "st", "std");
3336
3337 if (frame_pointer_needed)
3338 {
3339 if (tsize <= 4095)
3340 fprintf (file, "\tadd %s,%d,%s\t!# set up frame pointer\n", sp_str,
3341 tsize, frame_base_name);
3342 else
3343 fprintf (file, "\tadd %s,%s,%s\t!# set up frame pointer\n", sp_str,
3344 "%g1", frame_base_name);
3345 }
3346 }
3347 \f
3348 /* Do any necessary cleanup after a function to restore stack, frame,
3349 and regs. */
3350
3351 void
3352 sparc_frw_output_function_epilogue (file, size, ignored1, ignored2)
3353 FILE *file;
3354 int size;
3355 {
3356 extern FILE *asm_out_data_file, *asm_out_file;
3357 extern char call_used_regs[];
3358 extern int frame_pointer_needed;
3359 int tsize;
3360 char *sp_str = reg_names[STACK_POINTER_REGNUM];
3361 char *t1_str = "%g1";
3362 rtx epilogue_delay = current_function_epilogue_delay_list;
3363 int noepilogue = FALSE;
3364
3365 /* The epilogue does not depend on any registers, but the stack
3366 registers, so we assume that if we have 1 pending nop, it can be
3367 ignored, and 2 it must be filled (2 nops occur for integer
3368 multiply and divide). */
3369
3370 size = SPARC_STACK_ALIGN (size);
3371 tsize = (!current_frame_info.initialized
3372 ? sparc_frw_compute_frame_size (size)
3373 : current_frame_info.total_size);
3374
3375 if (tsize == 0 && epilogue_delay == 0)
3376 {
3377 rtx insn = get_last_insn ();
3378
3379 /* If the last insn was a BARRIER, we don't have to write any code
3380 because a jump (aka return) was put there. */
3381 if (GET_CODE (insn) == NOTE)
3382 insn = prev_nonnote_insn (insn);
3383 if (insn && GET_CODE (insn) == BARRIER)
3384 noepilogue = TRUE;
3385 }
3386
3387 if (!noepilogue)
3388 {
3389 /* In the reload sequence, we don't need to fill the load delay
3390 slots for most of the loads, also see if we can fill the final
3391 delay slot if not otherwise filled by the reload sequence. */
3392
3393 if (tsize > 4095)
3394 fprintf (file, "\tset %d,%s\n", tsize, t1_str);
3395
3396 if (frame_pointer_needed)
3397 {
3398 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
3399 if (tsize > 4095)
3400 fprintf (file,"\tsub %s,%s,%s\t\t!# sp not trusted here\n",
3401 fp_str, t1_str, sp_str);
3402 else
3403 fprintf (file,"\tsub %s,%d,%s\t\t!# sp not trusted here\n",
3404 fp_str, tsize, sp_str);
3405 }
3406
3407 sparc_frw_save_restore (file, "ld", "ldd");
3408
3409 if (current_function_returns_struct)
3410 fprintf (file, "\tjmp %%o7+12\n");
3411 else
3412 fprintf (file, "\tretl\n");
3413
3414 /* If the only register saved is the return address, we need a
3415 nop, unless we have an instruction to put into it. Otherwise
3416 we don't since reloading multiple registers doesn't reference
3417 the register being loaded. */
3418
3419 if (epilogue_delay)
3420 {
3421 if (tsize)
3422 abort ();
3423 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
3424 }
3425
3426 else if (tsize > 4095)
3427 fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str);
3428
3429 else if (tsize > 0)
3430 fprintf (file, "\tadd %s,%d,%s\n", sp_str, tsize, sp_str);
3431
3432 else
3433 fprintf (file, "\tnop\n");
3434 }
3435
3436 /* Reset state info for each function. */
3437 current_frame_info = zero_frame_info;
3438 }
3439 \f
3440 /* Define the number of delay slots needed for the function epilogue.
3441
3442 On the sparc, we need a slot if either no stack has been allocated,
3443 or the only register saved is the return register. */
3444
3445 int
3446 sparc_frw_epilogue_delay_slots ()
3447 {
3448 if (!current_frame_info.initialized)
3449 (void) sparc_frw_compute_frame_size (get_frame_size ());
3450
3451 if (current_frame_info.total_size == 0)
3452 return 1;
3453
3454 return 0;
3455 }
3456
3457 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
3458 Any single length instruction which doesn't reference the stack or frame
3459 pointer is OK. */
3460
3461 int
3462 sparc_frw_eligible_for_epilogue_delay (trial, slot)
3463 rtx trial;
3464 int slot;
3465 {
3466 if (get_attr_length (trial) == 1
3467 && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (trial))
3468 && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (trial)))
3469 return 1;
3470 return 0;
3471 }