1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Michael Tiemann (tiemann@cygnus.com)
6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
52 #include "langhooks.h"
55 #include "dwarf2out.h"
59 struct processor_costs cypress_costs
= {
60 COSTS_N_INSNS (2), /* int load */
61 COSTS_N_INSNS (2), /* int signed load */
62 COSTS_N_INSNS (2), /* int zeroed load */
63 COSTS_N_INSNS (2), /* float load */
64 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
65 COSTS_N_INSNS (5), /* fadd, fsub */
66 COSTS_N_INSNS (1), /* fcmp */
67 COSTS_N_INSNS (1), /* fmov, fmovr */
68 COSTS_N_INSNS (7), /* fmul */
69 COSTS_N_INSNS (37), /* fdivs */
70 COSTS_N_INSNS (37), /* fdivd */
71 COSTS_N_INSNS (63), /* fsqrts */
72 COSTS_N_INSNS (63), /* fsqrtd */
73 COSTS_N_INSNS (1), /* imul */
74 COSTS_N_INSNS (1), /* imulX */
75 0, /* imul bit factor */
76 COSTS_N_INSNS (1), /* idiv */
77 COSTS_N_INSNS (1), /* idivX */
78 COSTS_N_INSNS (1), /* movcc/movr */
79 0, /* shift penalty */
83 struct processor_costs supersparc_costs
= {
84 COSTS_N_INSNS (1), /* int load */
85 COSTS_N_INSNS (1), /* int signed load */
86 COSTS_N_INSNS (1), /* int zeroed load */
87 COSTS_N_INSNS (0), /* float load */
88 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
89 COSTS_N_INSNS (3), /* fadd, fsub */
90 COSTS_N_INSNS (3), /* fcmp */
91 COSTS_N_INSNS (1), /* fmov, fmovr */
92 COSTS_N_INSNS (3), /* fmul */
93 COSTS_N_INSNS (6), /* fdivs */
94 COSTS_N_INSNS (9), /* fdivd */
95 COSTS_N_INSNS (12), /* fsqrts */
96 COSTS_N_INSNS (12), /* fsqrtd */
97 COSTS_N_INSNS (4), /* imul */
98 COSTS_N_INSNS (4), /* imulX */
99 0, /* imul bit factor */
100 COSTS_N_INSNS (4), /* idiv */
101 COSTS_N_INSNS (4), /* idivX */
102 COSTS_N_INSNS (1), /* movcc/movr */
103 1, /* shift penalty */
107 struct processor_costs hypersparc_costs
= {
108 COSTS_N_INSNS (1), /* int load */
109 COSTS_N_INSNS (1), /* int signed load */
110 COSTS_N_INSNS (1), /* int zeroed load */
111 COSTS_N_INSNS (1), /* float load */
112 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
113 COSTS_N_INSNS (1), /* fadd, fsub */
114 COSTS_N_INSNS (1), /* fcmp */
115 COSTS_N_INSNS (1), /* fmov, fmovr */
116 COSTS_N_INSNS (1), /* fmul */
117 COSTS_N_INSNS (8), /* fdivs */
118 COSTS_N_INSNS (12), /* fdivd */
119 COSTS_N_INSNS (17), /* fsqrts */
120 COSTS_N_INSNS (17), /* fsqrtd */
121 COSTS_N_INSNS (17), /* imul */
122 COSTS_N_INSNS (17), /* imulX */
123 0, /* imul bit factor */
124 COSTS_N_INSNS (17), /* idiv */
125 COSTS_N_INSNS (17), /* idivX */
126 COSTS_N_INSNS (1), /* movcc/movr */
127 0, /* shift penalty */
131 struct processor_costs sparclet_costs
= {
132 COSTS_N_INSNS (3), /* int load */
133 COSTS_N_INSNS (3), /* int signed load */
134 COSTS_N_INSNS (1), /* int zeroed load */
135 COSTS_N_INSNS (1), /* float load */
136 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
137 COSTS_N_INSNS (1), /* fadd, fsub */
138 COSTS_N_INSNS (1), /* fcmp */
139 COSTS_N_INSNS (1), /* fmov, fmovr */
140 COSTS_N_INSNS (1), /* fmul */
141 COSTS_N_INSNS (1), /* fdivs */
142 COSTS_N_INSNS (1), /* fdivd */
143 COSTS_N_INSNS (1), /* fsqrts */
144 COSTS_N_INSNS (1), /* fsqrtd */
145 COSTS_N_INSNS (5), /* imul */
146 COSTS_N_INSNS (5), /* imulX */
147 0, /* imul bit factor */
148 COSTS_N_INSNS (5), /* idiv */
149 COSTS_N_INSNS (5), /* idivX */
150 COSTS_N_INSNS (1), /* movcc/movr */
151 0, /* shift penalty */
155 struct processor_costs ultrasparc_costs
= {
156 COSTS_N_INSNS (2), /* int load */
157 COSTS_N_INSNS (3), /* int signed load */
158 COSTS_N_INSNS (2), /* int zeroed load */
159 COSTS_N_INSNS (2), /* float load */
160 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
161 COSTS_N_INSNS (4), /* fadd, fsub */
162 COSTS_N_INSNS (1), /* fcmp */
163 COSTS_N_INSNS (2), /* fmov, fmovr */
164 COSTS_N_INSNS (4), /* fmul */
165 COSTS_N_INSNS (13), /* fdivs */
166 COSTS_N_INSNS (23), /* fdivd */
167 COSTS_N_INSNS (13), /* fsqrts */
168 COSTS_N_INSNS (23), /* fsqrtd */
169 COSTS_N_INSNS (4), /* imul */
170 COSTS_N_INSNS (4), /* imulX */
171 2, /* imul bit factor */
172 COSTS_N_INSNS (37), /* idiv */
173 COSTS_N_INSNS (68), /* idivX */
174 COSTS_N_INSNS (2), /* movcc/movr */
175 2, /* shift penalty */
179 struct processor_costs ultrasparc3_costs
= {
180 COSTS_N_INSNS (2), /* int load */
181 COSTS_N_INSNS (3), /* int signed load */
182 COSTS_N_INSNS (3), /* int zeroed load */
183 COSTS_N_INSNS (2), /* float load */
184 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
185 COSTS_N_INSNS (4), /* fadd, fsub */
186 COSTS_N_INSNS (5), /* fcmp */
187 COSTS_N_INSNS (3), /* fmov, fmovr */
188 COSTS_N_INSNS (4), /* fmul */
189 COSTS_N_INSNS (17), /* fdivs */
190 COSTS_N_INSNS (20), /* fdivd */
191 COSTS_N_INSNS (20), /* fsqrts */
192 COSTS_N_INSNS (29), /* fsqrtd */
193 COSTS_N_INSNS (6), /* imul */
194 COSTS_N_INSNS (6), /* imulX */
195 0, /* imul bit factor */
196 COSTS_N_INSNS (40), /* idiv */
197 COSTS_N_INSNS (71), /* idivX */
198 COSTS_N_INSNS (2), /* movcc/movr */
199 0, /* shift penalty */
203 struct processor_costs niagara_costs
= {
204 COSTS_N_INSNS (3), /* int load */
205 COSTS_N_INSNS (3), /* int signed load */
206 COSTS_N_INSNS (3), /* int zeroed load */
207 COSTS_N_INSNS (9), /* float load */
208 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
209 COSTS_N_INSNS (8), /* fadd, fsub */
210 COSTS_N_INSNS (26), /* fcmp */
211 COSTS_N_INSNS (8), /* fmov, fmovr */
212 COSTS_N_INSNS (29), /* fmul */
213 COSTS_N_INSNS (54), /* fdivs */
214 COSTS_N_INSNS (83), /* fdivd */
215 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
216 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
217 COSTS_N_INSNS (11), /* imul */
218 COSTS_N_INSNS (11), /* imulX */
219 0, /* imul bit factor */
220 COSTS_N_INSNS (72), /* idiv */
221 COSTS_N_INSNS (72), /* idivX */
222 COSTS_N_INSNS (1), /* movcc/movr */
223 0, /* shift penalty */
227 struct processor_costs niagara2_costs
= {
228 COSTS_N_INSNS (3), /* int load */
229 COSTS_N_INSNS (3), /* int signed load */
230 COSTS_N_INSNS (3), /* int zeroed load */
231 COSTS_N_INSNS (3), /* float load */
232 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
233 COSTS_N_INSNS (6), /* fadd, fsub */
234 COSTS_N_INSNS (6), /* fcmp */
235 COSTS_N_INSNS (6), /* fmov, fmovr */
236 COSTS_N_INSNS (6), /* fmul */
237 COSTS_N_INSNS (19), /* fdivs */
238 COSTS_N_INSNS (33), /* fdivd */
239 COSTS_N_INSNS (19), /* fsqrts */
240 COSTS_N_INSNS (33), /* fsqrtd */
241 COSTS_N_INSNS (5), /* imul */
242 COSTS_N_INSNS (5), /* imulX */
243 0, /* imul bit factor */
244 COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
245 COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
246 COSTS_N_INSNS (1), /* movcc/movr */
247 0, /* shift penalty */
250 const struct processor_costs
*sparc_costs
= &cypress_costs
;
252 #ifdef HAVE_AS_RELAX_OPTION
253 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
254 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
255 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
256 somebody does not branch between the sethi and jmp. */
257 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
259 #define LEAF_SIBCALL_SLOT_RESERVED_P \
260 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
263 /* Global variables for machine-dependent things. */
265 /* Size of frame. Need to know this to emit return insns from leaf procedures.
266 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
267 reload pass. This is important as the value is later used for scheduling
268 (to see what can go in a delay slot).
269 APPARENT_FSIZE is the size of the stack less the register save area and less
270 the outgoing argument area. It is used when saving call preserved regs. */
271 static HOST_WIDE_INT apparent_fsize
;
272 static HOST_WIDE_INT actual_fsize
;
274 /* Number of live general or floating point registers needed to be
275 saved (as 4-byte quantities). */
276 static int num_gfregs
;
278 /* The alias set for prologue/epilogue register save/restore. */
279 static GTY(()) alias_set_type sparc_sr_alias_set
;
281 /* The alias set for the structure return value. */
282 static GTY(()) alias_set_type struct_value_alias_set
;
284 /* Vector to say how input registers are mapped to output registers.
285 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
286 eliminate it. You must use -fomit-frame-pointer to get that. */
287 char leaf_reg_remap
[] =
288 { 0, 1, 2, 3, 4, 5, 6, 7,
289 -1, -1, -1, -1, -1, -1, 14, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 8, 9, 10, 11, 12, 13, -1, 15,
293 32, 33, 34, 35, 36, 37, 38, 39,
294 40, 41, 42, 43, 44, 45, 46, 47,
295 48, 49, 50, 51, 52, 53, 54, 55,
296 56, 57, 58, 59, 60, 61, 62, 63,
297 64, 65, 66, 67, 68, 69, 70, 71,
298 72, 73, 74, 75, 76, 77, 78, 79,
299 80, 81, 82, 83, 84, 85, 86, 87,
300 88, 89, 90, 91, 92, 93, 94, 95,
301 96, 97, 98, 99, 100};
303 /* Vector, indexed by hard register number, which contains 1
304 for a register that is allowable in a candidate for leaf
305 function treatment. */
306 char sparc_leaf_regs
[] =
307 { 1, 1, 1, 1, 1, 1, 1, 1,
308 0, 0, 0, 0, 0, 0, 1, 0,
309 0, 0, 0, 0, 0, 0, 0, 0,
310 1, 1, 1, 1, 1, 1, 0, 1,
311 1, 1, 1, 1, 1, 1, 1, 1,
312 1, 1, 1, 1, 1, 1, 1, 1,
313 1, 1, 1, 1, 1, 1, 1, 1,
314 1, 1, 1, 1, 1, 1, 1, 1,
315 1, 1, 1, 1, 1, 1, 1, 1,
316 1, 1, 1, 1, 1, 1, 1, 1,
317 1, 1, 1, 1, 1, 1, 1, 1,
318 1, 1, 1, 1, 1, 1, 1, 1,
321 struct GTY(()) machine_function
323 /* Some local-dynamic TLS symbol name. */
324 const char *some_ld_name
;
326 /* True if the current function is leaf and uses only leaf regs,
327 so that the SPARC leaf function optimization can be applied.
328 Private version of current_function_uses_only_leaf_regs, see
329 sparc_expand_prologue for the rationale. */
332 /* True if the data calculated by sparc_expand_prologue are valid. */
333 bool prologue_data_valid_p
;
336 #define sparc_leaf_function_p cfun->machine->leaf_function_p
337 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
339 /* Register we pretend to think the frame pointer is allocated to.
340 Normally, this is %fp, but if we are in a leaf procedure, this
341 is %sp+"something". We record "something" separately as it may
342 be too big for reg+constant addressing. */
343 static rtx frame_base_reg
;
344 static HOST_WIDE_INT frame_base_offset
;
346 /* 1 if the next opcode is to be specially indented. */
347 int sparc_indent_opcode
= 0;
349 static bool sparc_handle_option (size_t, const char *, int);
350 static void sparc_init_modes (void);
351 static void scan_record_type (tree
, int *, int *, int *);
352 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
353 tree
, int, int, int *, int *);
355 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
356 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
358 static void sparc_output_addr_vec (rtx
);
359 static void sparc_output_addr_diff_vec (rtx
);
360 static void sparc_output_deferred_case_vectors (void);
361 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
362 static rtx
sparc_builtin_saveregs (void);
363 static int epilogue_renumber (rtx
*, int);
364 static bool sparc_assemble_integer (rtx
, unsigned int, int);
365 static int set_extends (rtx
);
366 static void load_pic_register (void);
367 static int save_or_restore_regs (int, int, rtx
, int, int);
368 static void emit_save_or_restore_regs (int);
369 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
370 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
371 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
372 tree
) ATTRIBUTE_UNUSED
;
373 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
374 static int sparc_issue_rate (void);
375 static void sparc_sched_init (FILE *, int, int);
376 static int sparc_use_sched_lookahead (void);
378 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
379 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
380 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
381 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
382 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
384 static bool sparc_function_ok_for_sibcall (tree
, tree
);
385 static void sparc_init_libfuncs (void);
386 static void sparc_init_builtins (void);
387 static void sparc_vis_init_builtins (void);
388 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
389 static tree
sparc_fold_builtin (tree
, tree
, bool);
390 static int sparc_vis_mul8x16 (int, int);
391 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
392 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
393 HOST_WIDE_INT
, tree
);
394 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
395 HOST_WIDE_INT
, const_tree
);
396 static struct machine_function
* sparc_init_machine_status (void);
397 static bool sparc_cannot_force_const_mem (rtx
);
398 static rtx
sparc_tls_get_addr (void);
399 static rtx
sparc_tls_got (void);
400 static const char *get_some_local_dynamic_name (void);
401 static int get_some_local_dynamic_name_1 (rtx
*, void *);
402 static bool sparc_rtx_costs (rtx
, int, int, int *, bool);
403 static bool sparc_promote_prototypes (const_tree
);
404 static rtx
sparc_struct_value_rtx (tree
, int);
405 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
406 int *, const_tree
, int);
407 static bool sparc_return_in_memory (const_tree
, const_tree
);
408 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS
*);
409 static void sparc_va_start (tree
, rtx
);
410 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
411 static bool sparc_vector_mode_supported_p (enum machine_mode
);
412 static bool sparc_tls_referenced_p (rtx
);
413 static rtx
legitimize_tls_address (rtx
);
414 static rtx
legitimize_pic_address (rtx
, rtx
);
415 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
416 static bool sparc_pass_by_reference (CUMULATIVE_ARGS
*,
417 enum machine_mode
, const_tree
, bool);
418 static int sparc_arg_partial_bytes (CUMULATIVE_ARGS
*,
419 enum machine_mode
, tree
, bool);
420 static void sparc_dwarf_handle_frame_unspec (const char *, rtx
, int);
421 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
422 static void sparc_file_end (void);
423 static bool sparc_frame_pointer_required (void);
424 static bool sparc_can_eliminate (const int, const int);
425 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
426 static const char *sparc_mangle_type (const_tree
);
428 static void sparc_trampoline_init (rtx
, tree
, rtx
);
430 #ifdef SUBTARGET_ATTRIBUTE_TABLE
431 /* Table of valid machine attributes. */
432 static const struct attribute_spec sparc_attribute_table
[] =
434 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
435 SUBTARGET_ATTRIBUTE_TABLE
,
436 { NULL
, 0, 0, false, false, false, NULL
}
440 /* Option handling. */
443 enum cmodel sparc_cmodel
;
445 char sparc_hard_reg_printed
[8];
447 struct sparc_cpu_select sparc_select
[] =
449 /* switch name, tune arch */
450 { (char *)0, "default", 1, 1 },
451 { (char *)0, "-mcpu=", 1, 1 },
452 { (char *)0, "-mtune=", 1, 0 },
456 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
457 enum processor_type sparc_cpu
;
459 /* Whether\fan FPU option was specified. */
460 static bool fpu_option_set
= false;
462 /* Initialize the GCC target structure. */
464 /* The default is to use .half rather than .short for aligned HI objects. */
465 #undef TARGET_ASM_ALIGNED_HI_OP
466 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
468 #undef TARGET_ASM_UNALIGNED_HI_OP
469 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
470 #undef TARGET_ASM_UNALIGNED_SI_OP
471 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
472 #undef TARGET_ASM_UNALIGNED_DI_OP
473 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
475 /* The target hook has to handle DI-mode values. */
476 #undef TARGET_ASM_INTEGER
477 #define TARGET_ASM_INTEGER sparc_assemble_integer
479 #undef TARGET_ASM_FUNCTION_PROLOGUE
480 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
481 #undef TARGET_ASM_FUNCTION_EPILOGUE
482 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
484 #undef TARGET_SCHED_ADJUST_COST
485 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
486 #undef TARGET_SCHED_ISSUE_RATE
487 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
488 #undef TARGET_SCHED_INIT
489 #define TARGET_SCHED_INIT sparc_sched_init
490 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
491 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
493 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
494 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
496 #undef TARGET_INIT_LIBFUNCS
497 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
498 #undef TARGET_INIT_BUILTINS
499 #define TARGET_INIT_BUILTINS sparc_init_builtins
501 #undef TARGET_LEGITIMIZE_ADDRESS
502 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
504 #undef TARGET_EXPAND_BUILTIN
505 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
506 #undef TARGET_FOLD_BUILTIN
507 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
510 #undef TARGET_HAVE_TLS
511 #define TARGET_HAVE_TLS true
514 #undef TARGET_CANNOT_FORCE_CONST_MEM
515 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
517 #undef TARGET_ASM_OUTPUT_MI_THUNK
518 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
519 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
520 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
522 #undef TARGET_RTX_COSTS
523 #define TARGET_RTX_COSTS sparc_rtx_costs
524 #undef TARGET_ADDRESS_COST
525 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
527 #undef TARGET_PROMOTE_FUNCTION_MODE
528 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
530 #undef TARGET_PROMOTE_PROTOTYPES
531 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
533 #undef TARGET_STRUCT_VALUE_RTX
534 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
535 #undef TARGET_RETURN_IN_MEMORY
536 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
537 #undef TARGET_MUST_PASS_IN_STACK
538 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
539 #undef TARGET_PASS_BY_REFERENCE
540 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
541 #undef TARGET_ARG_PARTIAL_BYTES
542 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
544 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
545 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
546 #undef TARGET_STRICT_ARGUMENT_NAMING
547 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
549 #undef TARGET_EXPAND_BUILTIN_VA_START
550 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
551 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
552 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
554 #undef TARGET_VECTOR_MODE_SUPPORTED_P
555 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
557 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
558 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
560 #ifdef SUBTARGET_INSERT_ATTRIBUTES
561 #undef TARGET_INSERT_ATTRIBUTES
562 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
565 #ifdef SUBTARGET_ATTRIBUTE_TABLE
566 #undef TARGET_ATTRIBUTE_TABLE
567 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
570 #undef TARGET_RELAXED_ORDERING
571 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
573 #undef TARGET_DEFAULT_TARGET_FLAGS
574 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
575 #undef TARGET_HANDLE_OPTION
576 #define TARGET_HANDLE_OPTION sparc_handle_option
578 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
579 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
580 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
583 #undef TARGET_ASM_FILE_END
584 #define TARGET_ASM_FILE_END sparc_file_end
586 #undef TARGET_FRAME_POINTER_REQUIRED
587 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
589 #undef TARGET_CAN_ELIMINATE
590 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
592 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
593 #undef TARGET_MANGLE_TYPE
594 #define TARGET_MANGLE_TYPE sparc_mangle_type
597 #undef TARGET_LEGITIMATE_ADDRESS_P
598 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
600 #undef TARGET_TRAMPOLINE_INIT
601 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
603 struct gcc_target targetm
= TARGET_INITIALIZER
;
605 /* Implement TARGET_HANDLE_OPTION. */
608 sparc_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
613 case OPT_mhard_float
:
614 case OPT_msoft_float
:
615 fpu_option_set
= true;
619 sparc_select
[1].string
= arg
;
623 sparc_select
[2].string
= arg
;
630 /* Validate and override various options, and do some machine dependent
634 sparc_override_options (void)
636 static struct code_model
{
637 const char *const name
;
638 const enum cmodel value
;
639 } const cmodels
[] = {
641 { "medlow", CM_MEDLOW
},
642 { "medmid", CM_MEDMID
},
643 { "medany", CM_MEDANY
},
644 { "embmedany", CM_EMBMEDANY
},
645 { NULL
, (enum cmodel
) 0 }
647 const struct code_model
*cmodel
;
648 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
649 static struct cpu_default
{
651 const char *const name
;
652 } const cpu_default
[] = {
653 /* There must be one entry here for each TARGET_CPU value. */
654 { TARGET_CPU_sparc
, "cypress" },
655 { TARGET_CPU_sparclet
, "tsc701" },
656 { TARGET_CPU_sparclite
, "f930" },
657 { TARGET_CPU_v8
, "v8" },
658 { TARGET_CPU_hypersparc
, "hypersparc" },
659 { TARGET_CPU_sparclite86x
, "sparclite86x" },
660 { TARGET_CPU_supersparc
, "supersparc" },
661 { TARGET_CPU_v9
, "v9" },
662 { TARGET_CPU_ultrasparc
, "ultrasparc" },
663 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
664 { TARGET_CPU_niagara
, "niagara" },
665 { TARGET_CPU_niagara2
, "niagara2" },
668 const struct cpu_default
*def
;
669 /* Table of values for -m{cpu,tune}=. */
670 static struct cpu_table
{
671 const char *const name
;
672 const enum processor_type processor
;
675 } const cpu_table
[] = {
676 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
677 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
678 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
679 /* TI TMS390Z55 supersparc */
680 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
681 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
682 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
683 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
684 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
685 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
686 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
687 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
689 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
691 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
692 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
693 /* TI ultrasparc I, II, IIi */
694 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
695 /* Although insns using %y are deprecated, it is a clear win on current
697 |MASK_DEPRECATED_V8_INSNS
},
698 /* TI ultrasparc III */
699 /* ??? Check if %y issue still holds true in ultra3. */
700 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
702 { "niagara", PROCESSOR_NIAGARA
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
703 { "niagara2", PROCESSOR_NIAGARA
, MASK_ISA
, MASK_V9
},
704 { 0, (enum processor_type
) 0, 0, 0 }
706 const struct cpu_table
*cpu
;
707 const struct sparc_cpu_select
*sel
;
710 #ifndef SPARC_BI_ARCH
711 /* Check for unsupported architecture size. */
712 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
713 error ("%s is not supported by this configuration",
714 DEFAULT_ARCH32_P
? "-m64" : "-m32");
717 /* We force all 64bit archs to use 128 bit long double */
718 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
720 error ("-mlong-double-64 not allowed with -m64");
721 target_flags
|= MASK_LONG_DOUBLE_128
;
724 /* Code model selection. */
725 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
729 sparc_cmodel
= CM_32
;
732 if (sparc_cmodel_string
!= NULL
)
736 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
737 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
739 if (cmodel
->name
== NULL
)
740 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
742 sparc_cmodel
= cmodel
->value
;
745 error ("-mcmodel= is not supported on 32 bit systems");
748 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
750 /* Set the default CPU. */
751 for (def
= &cpu_default
[0]; def
->name
; ++def
)
752 if (def
->cpu
== TARGET_CPU_DEFAULT
)
754 gcc_assert (def
->name
);
755 sparc_select
[0].string
= def
->name
;
757 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
761 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
762 if (! strcmp (sel
->string
, cpu
->name
))
765 sparc_cpu
= cpu
->processor
;
769 target_flags
&= ~cpu
->disable
;
770 target_flags
|= cpu
->enable
;
776 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
780 /* If -mfpu or -mno-fpu was explicitly used, don't override with
781 the processor default. */
783 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
785 /* Don't allow -mvis if FPU is disabled. */
787 target_flags
&= ~MASK_VIS
;
789 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
791 -m64 also implies v9. */
792 if (TARGET_VIS
|| TARGET_ARCH64
)
794 target_flags
|= MASK_V9
;
795 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
798 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
799 if (TARGET_V9
&& TARGET_ARCH32
)
800 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
802 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
803 if (! TARGET_V9
|| TARGET_ARCH64
)
804 target_flags
&= ~MASK_V8PLUS
;
806 /* Don't use stack biasing in 32 bit mode. */
808 target_flags
&= ~MASK_STACK_BIAS
;
810 /* Supply a default value for align_functions. */
811 if (align_functions
== 0
812 && (sparc_cpu
== PROCESSOR_ULTRASPARC
813 || sparc_cpu
== PROCESSOR_ULTRASPARC3
814 || sparc_cpu
== PROCESSOR_NIAGARA
815 || sparc_cpu
== PROCESSOR_NIAGARA2
))
816 align_functions
= 32;
818 /* Validate PCC_STRUCT_RETURN. */
819 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
820 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
822 /* Only use .uaxword when compiling for a 64-bit target. */
824 targetm
.asm_out
.unaligned_op
.di
= NULL
;
826 /* Do various machine dependent initializations. */
829 /* Acquire unique alias sets for our private stuff. */
830 sparc_sr_alias_set
= new_alias_set ();
831 struct_value_alias_set
= new_alias_set ();
833 /* Set up function hooks. */
834 init_machine_status
= sparc_init_machine_status
;
839 case PROCESSOR_CYPRESS
:
840 sparc_costs
= &cypress_costs
;
843 case PROCESSOR_SPARCLITE
:
844 case PROCESSOR_SUPERSPARC
:
845 sparc_costs
= &supersparc_costs
;
849 case PROCESSOR_HYPERSPARC
:
850 case PROCESSOR_SPARCLITE86X
:
851 sparc_costs
= &hypersparc_costs
;
853 case PROCESSOR_SPARCLET
:
854 case PROCESSOR_TSC701
:
855 sparc_costs
= &sparclet_costs
;
858 case PROCESSOR_ULTRASPARC
:
859 sparc_costs
= &ultrasparc_costs
;
861 case PROCESSOR_ULTRASPARC3
:
862 sparc_costs
= &ultrasparc3_costs
;
864 case PROCESSOR_NIAGARA
:
865 sparc_costs
= &niagara_costs
;
867 case PROCESSOR_NIAGARA2
:
868 sparc_costs
= &niagara2_costs
;
872 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
873 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
874 target_flags
|= MASK_LONG_DOUBLE_128
;
877 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
878 set_param_value ("simultaneous-prefetches",
879 ((sparc_cpu
== PROCESSOR_ULTRASPARC
880 || sparc_cpu
== PROCESSOR_NIAGARA
881 || sparc_cpu
== PROCESSOR_NIAGARA2
)
883 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
885 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE
))
886 set_param_value ("l1-cache-line-size",
887 ((sparc_cpu
== PROCESSOR_ULTRASPARC
888 || sparc_cpu
== PROCESSOR_ULTRASPARC3
889 || sparc_cpu
== PROCESSOR_NIAGARA
890 || sparc_cpu
== PROCESSOR_NIAGARA2
)
894 /* Miscellaneous utilities. */
896 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
897 or branch on register contents instructions. */
900 v9_regcmp_p (enum rtx_code code
)
902 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
903 || code
== LE
|| code
== GT
);
906 /* Nonzero if OP is a floating point constant which can
907 be loaded into an integer register using a single
908 sethi instruction. */
913 if (GET_CODE (op
) == CONST_DOUBLE
)
918 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
919 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
920 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
926 /* Nonzero if OP is a floating point constant which can
927 be loaded into an integer register using a single
933 if (GET_CODE (op
) == CONST_DOUBLE
)
938 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
939 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
940 return SPARC_SIMM13_P (i
);
946 /* Nonzero if OP is a floating point constant which can
947 be loaded into an integer register using a high/losum
948 instruction sequence. */
951 fp_high_losum_p (rtx op
)
953 /* The constraints calling this should only be in
954 SFmode move insns, so any constant which cannot
955 be moved using a single insn will do. */
956 if (GET_CODE (op
) == CONST_DOUBLE
)
961 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
962 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
963 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
969 /* Expand a move instruction. Return true if all work is done. */
972 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
974 /* Handle sets of MEM first. */
975 if (GET_CODE (operands
[0]) == MEM
)
977 /* 0 is a register (or a pair of registers) on SPARC. */
978 if (register_or_zero_operand (operands
[1], mode
))
981 if (!reload_in_progress
)
983 operands
[0] = validize_mem (operands
[0]);
984 operands
[1] = force_reg (mode
, operands
[1]);
988 /* Fixup TLS cases. */
990 && CONSTANT_P (operands
[1])
991 && sparc_tls_referenced_p (operands
[1]))
993 operands
[1] = legitimize_tls_address (operands
[1]);
997 /* Fixup PIC cases. */
998 if (flag_pic
&& CONSTANT_P (operands
[1]))
1000 if (pic_address_needs_scratch (operands
[1]))
1001 operands
[1] = legitimize_pic_address (operands
[1], NULL_RTX
);
1003 /* VxWorks does not impose a fixed gap between segments; the run-time
1004 gap can be different from the object-file gap. We therefore can't
1005 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1006 are absolutely sure that X is in the same segment as the GOT.
1007 Unfortunately, the flexibility of linker scripts means that we
1008 can't be sure of that in general, so assume that _G_O_T_-relative
1009 accesses are never valid on VxWorks. */
1010 if (GET_CODE (operands
[1]) == LABEL_REF
&& !TARGET_VXWORKS_RTP
)
1014 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1020 gcc_assert (TARGET_ARCH64
);
1021 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1026 if (symbolic_operand (operands
[1], mode
))
1028 operands
[1] = legitimize_pic_address (operands
[1],
1030 ? operands
[0] : NULL_RTX
);
1035 /* If we are trying to toss an integer constant into FP registers,
1036 or loading a FP or vector constant, force it into memory. */
1037 if (CONSTANT_P (operands
[1])
1038 && REG_P (operands
[0])
1039 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1040 || SCALAR_FLOAT_MODE_P (mode
)
1041 || VECTOR_MODE_P (mode
)))
1043 /* emit_group_store will send such bogosity to us when it is
1044 not storing directly into memory. So fix this up to avoid
1045 crashes in output_constant_pool. */
1046 if (operands
[1] == const0_rtx
)
1047 operands
[1] = CONST0_RTX (mode
);
1049 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1050 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1051 && const_zero_operand (operands
[1], mode
))
1054 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1055 /* We are able to build any SF constant in integer registers
1056 with at most 2 instructions. */
1058 /* And any DF constant in integer registers. */
1060 && (reload_completed
|| reload_in_progress
))))
1063 operands
[1] = force_const_mem (mode
, operands
[1]);
1064 if (!reload_in_progress
)
1065 operands
[1] = validize_mem (operands
[1]);
1069 /* Accept non-constants and valid constants unmodified. */
1070 if (!CONSTANT_P (operands
[1])
1071 || GET_CODE (operands
[1]) == HIGH
1072 || input_operand (operands
[1], mode
))
1078 /* All QImode constants require only one insn, so proceed. */
1083 sparc_emit_set_const32 (operands
[0], operands
[1]);
1087 /* input_operand should have filtered out 32-bit mode. */
1088 sparc_emit_set_const64 (operands
[0], operands
[1]);
1098 /* Load OP1, a 32-bit constant, into OP0, a register.
1099 We know it can't be done in one insn when we get
1100 here, the move expander guarantees this. */
1103 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1105 enum machine_mode mode
= GET_MODE (op0
);
1108 if (reload_in_progress
|| reload_completed
)
1111 temp
= gen_reg_rtx (mode
);
1113 if (GET_CODE (op1
) == CONST_INT
)
1115 gcc_assert (!small_int_operand (op1
, mode
)
1116 && !const_high_operand (op1
, mode
));
1118 /* Emit them as real moves instead of a HIGH/LO_SUM,
1119 this way CSE can see everything and reuse intermediate
1120 values if it wants. */
1121 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1122 GEN_INT (INTVAL (op1
)
1123 & ~(HOST_WIDE_INT
)0x3ff)));
1125 emit_insn (gen_rtx_SET (VOIDmode
,
1127 gen_rtx_IOR (mode
, temp
,
1128 GEN_INT (INTVAL (op1
) & 0x3ff))));
1132 /* A symbol, emit in the traditional way. */
1133 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1134 gen_rtx_HIGH (mode
, op1
)));
1135 emit_insn (gen_rtx_SET (VOIDmode
,
1136 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1140 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1141 If TEMP is nonzero, we are forbidden to use any other scratch
1142 registers. Otherwise, we are allowed to generate them as needed.
1144 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1145 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1148 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1150 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1153 if (temp
&& GET_MODE (temp
) == TImode
)
1156 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1159 /* SPARC-V9 code-model support. */
1160 switch (sparc_cmodel
)
1163 /* The range spanned by all instructions in the object is less
1164 than 2^31 bytes (2GB) and the distance from any instruction
1165 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1166 than 2^31 bytes (2GB).
1168 The executable must be in the low 4TB of the virtual address
1171 sethi %hi(symbol), %temp1
1172 or %temp1, %lo(symbol), %reg */
1174 temp1
= temp
; /* op0 is allowed. */
1176 temp1
= gen_reg_rtx (DImode
);
1178 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1179 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1183 /* The range spanned by all instructions in the object is less
1184 than 2^31 bytes (2GB) and the distance from any instruction
1185 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1186 than 2^31 bytes (2GB).
1188 The executable must be in the low 16TB of the virtual address
1191 sethi %h44(symbol), %temp1
1192 or %temp1, %m44(symbol), %temp2
1193 sllx %temp2, 12, %temp3
1194 or %temp3, %l44(symbol), %reg */
1199 temp3
= temp
; /* op0 is allowed. */
1203 temp1
= gen_reg_rtx (DImode
);
1204 temp2
= gen_reg_rtx (DImode
);
1205 temp3
= gen_reg_rtx (DImode
);
1208 emit_insn (gen_seth44 (temp1
, op1
));
1209 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1210 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1211 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1212 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1216 /* The range spanned by all instructions in the object is less
1217 than 2^31 bytes (2GB) and the distance from any instruction
1218 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1219 than 2^31 bytes (2GB).
1221 The executable can be placed anywhere in the virtual address
1224 sethi %hh(symbol), %temp1
1225 sethi %lm(symbol), %temp2
1226 or %temp1, %hm(symbol), %temp3
1227 sllx %temp3, 32, %temp4
1228 or %temp4, %temp2, %temp5
1229 or %temp5, %lo(symbol), %reg */
1232 /* It is possible that one of the registers we got for operands[2]
1233 might coincide with that of operands[0] (which is why we made
1234 it TImode). Pick the other one to use as our scratch. */
1235 if (rtx_equal_p (temp
, op0
))
1237 gcc_assert (ti_temp
);
1238 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1241 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1248 temp1
= gen_reg_rtx (DImode
);
1249 temp2
= gen_reg_rtx (DImode
);
1250 temp3
= gen_reg_rtx (DImode
);
1251 temp4
= gen_reg_rtx (DImode
);
1252 temp5
= gen_reg_rtx (DImode
);
1255 emit_insn (gen_sethh (temp1
, op1
));
1256 emit_insn (gen_setlm (temp2
, op1
));
1257 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1258 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1259 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1260 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1261 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1262 emit_insn (gen_setlo (op0
, temp5
, op1
));
1266 /* Old old old backwards compatibility kruft here.
1267 Essentially it is MEDLOW with a fixed 64-bit
1268 virtual base added to all data segment addresses.
1269 Text-segment stuff is computed like MEDANY, we can't
1270 reuse the code above because the relocation knobs
1273 Data segment: sethi %hi(symbol), %temp1
1274 add %temp1, EMBMEDANY_BASE_REG, %temp2
1275 or %temp2, %lo(symbol), %reg */
1276 if (data_segment_operand (op1
, GET_MODE (op1
)))
1280 temp1
= temp
; /* op0 is allowed. */
1285 temp1
= gen_reg_rtx (DImode
);
1286 temp2
= gen_reg_rtx (DImode
);
1289 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1290 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1291 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1294 /* Text segment: sethi %uhi(symbol), %temp1
1295 sethi %hi(symbol), %temp2
1296 or %temp1, %ulo(symbol), %temp3
1297 sllx %temp3, 32, %temp4
1298 or %temp4, %temp2, %temp5
1299 or %temp5, %lo(symbol), %reg */
1304 /* It is possible that one of the registers we got for operands[2]
1305 might coincide with that of operands[0] (which is why we made
1306 it TImode). Pick the other one to use as our scratch. */
1307 if (rtx_equal_p (temp
, op0
))
1309 gcc_assert (ti_temp
);
1310 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1313 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1320 temp1
= gen_reg_rtx (DImode
);
1321 temp2
= gen_reg_rtx (DImode
);
1322 temp3
= gen_reg_rtx (DImode
);
1323 temp4
= gen_reg_rtx (DImode
);
1324 temp5
= gen_reg_rtx (DImode
);
1327 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1328 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1329 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1330 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1331 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1332 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1333 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1334 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1343 #if HOST_BITS_PER_WIDE_INT == 32
1345 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1350 /* These avoid problems when cross compiling. If we do not
1351 go through all this hair then the optimizer will see
1352 invalid REG_EQUAL notes or in some cases none at all. */
1353 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1354 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1355 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1356 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1358 /* The optimizer is not to assume anything about exactly
1359 which bits are set for a HIGH, they are unspecified.
1360 Unfortunately this leads to many missed optimizations
1361 during CSE. We mask out the non-HIGH bits, and matches
1362 a plain movdi, to alleviate this problem. */
1364 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1366 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1370 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1372 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1376 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1378 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1382 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1384 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1387 /* Worker routines for 64-bit constant formation on arch64.
1388 One of the key things to be doing in these emissions is
1389 to create as many temp REGs as possible. This makes it
1390 possible for half-built constants to be used later when
1391 such values are similar to something required later on.
1392 Without doing this, the optimizer cannot see such
1395 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1396 unsigned HOST_WIDE_INT
, int);
1399 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1400 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1402 unsigned HOST_WIDE_INT high_bits
;
1405 high_bits
= (~low_bits
) & 0xffffffff;
1407 high_bits
= low_bits
;
1409 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1412 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1413 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1417 /* If we are XOR'ing with -1, then we should emit a one's complement
1418 instead. This way the combiner will notice logical operations
1419 such as ANDN later on and substitute. */
1420 if ((low_bits
& 0x3ff) == 0x3ff)
1422 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1423 gen_rtx_NOT (DImode
, temp
)));
1427 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1428 gen_safe_XOR64 (temp
,
1429 (-(HOST_WIDE_INT
)0x400
1430 | (low_bits
& 0x3ff)))));
1435 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1436 unsigned HOST_WIDE_INT
, int);
1439 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1440 unsigned HOST_WIDE_INT high_bits
,
1441 unsigned HOST_WIDE_INT low_immediate
,
1446 if ((high_bits
& 0xfffffc00) != 0)
1448 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1449 if ((high_bits
& ~0xfffffc00) != 0)
1450 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1451 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1457 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1461 /* Now shift it up into place. */
1462 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1463 gen_rtx_ASHIFT (DImode
, temp2
,
1464 GEN_INT (shift_count
))));
1466 /* If there is a low immediate part piece, finish up by
1467 putting that in as well. */
1468 if (low_immediate
!= 0)
1469 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1470 gen_safe_OR64 (op0
, low_immediate
)));
1473 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1474 unsigned HOST_WIDE_INT
);
1476 /* Full 64-bit constant decomposition. Even though this is the
1477 'worst' case, we still optimize a few things away. */
1479 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1480 unsigned HOST_WIDE_INT high_bits
,
1481 unsigned HOST_WIDE_INT low_bits
)
1485 if (reload_in_progress
|| reload_completed
)
1488 sub_temp
= gen_reg_rtx (DImode
);
1490 if ((high_bits
& 0xfffffc00) != 0)
1492 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1493 if ((high_bits
& ~0xfffffc00) != 0)
1494 emit_insn (gen_rtx_SET (VOIDmode
,
1496 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1502 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1506 if (!reload_in_progress
&& !reload_completed
)
1508 rtx temp2
= gen_reg_rtx (DImode
);
1509 rtx temp3
= gen_reg_rtx (DImode
);
1510 rtx temp4
= gen_reg_rtx (DImode
);
1512 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1513 gen_rtx_ASHIFT (DImode
, sub_temp
,
1516 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1517 if ((low_bits
& ~0xfffffc00) != 0)
1519 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1520 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1521 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1522 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1526 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1527 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1532 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1533 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1534 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1537 /* We are in the middle of reload, so this is really
1538 painful. However we do still make an attempt to
1539 avoid emitting truly stupid code. */
1540 if (low1
!= const0_rtx
)
1542 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1543 gen_rtx_ASHIFT (DImode
, sub_temp
,
1544 GEN_INT (to_shift
))));
1545 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1546 gen_rtx_IOR (DImode
, op0
, low1
)));
1554 if (low2
!= const0_rtx
)
1556 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1557 gen_rtx_ASHIFT (DImode
, sub_temp
,
1558 GEN_INT (to_shift
))));
1559 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1560 gen_rtx_IOR (DImode
, op0
, low2
)));
1568 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1569 gen_rtx_ASHIFT (DImode
, sub_temp
,
1570 GEN_INT (to_shift
))));
1571 if (low3
!= const0_rtx
)
1572 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1573 gen_rtx_IOR (DImode
, op0
, low3
)));
1578 /* Analyze a 64-bit constant for certain properties. */
1579 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1580 unsigned HOST_WIDE_INT
,
1581 int *, int *, int *);
1584 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1585 unsigned HOST_WIDE_INT low_bits
,
1586 int *hbsp
, int *lbsp
, int *abbasp
)
1588 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1591 lowest_bit_set
= highest_bit_set
= -1;
1595 if ((lowest_bit_set
== -1)
1596 && ((low_bits
>> i
) & 1))
1598 if ((highest_bit_set
== -1)
1599 && ((high_bits
>> (32 - i
- 1)) & 1))
1600 highest_bit_set
= (64 - i
- 1);
1603 && ((highest_bit_set
== -1)
1604 || (lowest_bit_set
== -1)));
1610 if ((lowest_bit_set
== -1)
1611 && ((high_bits
>> i
) & 1))
1612 lowest_bit_set
= i
+ 32;
1613 if ((highest_bit_set
== -1)
1614 && ((low_bits
>> (32 - i
- 1)) & 1))
1615 highest_bit_set
= 32 - i
- 1;
1618 && ((highest_bit_set
== -1)
1619 || (lowest_bit_set
== -1)));
1621 /* If there are no bits set this should have gone out
1622 as one instruction! */
1623 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1624 all_bits_between_are_set
= 1;
1625 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1629 if ((low_bits
& (1 << i
)) != 0)
1634 if ((high_bits
& (1 << (i
- 32))) != 0)
1637 all_bits_between_are_set
= 0;
1640 *hbsp
= highest_bit_set
;
1641 *lbsp
= lowest_bit_set
;
1642 *abbasp
= all_bits_between_are_set
;
1645 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1648 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1649 unsigned HOST_WIDE_INT low_bits
)
1651 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1654 || high_bits
== 0xffffffff)
1657 analyze_64bit_constant (high_bits
, low_bits
,
1658 &highest_bit_set
, &lowest_bit_set
,
1659 &all_bits_between_are_set
);
1661 if ((highest_bit_set
== 63
1662 || lowest_bit_set
== 0)
1663 && all_bits_between_are_set
!= 0)
1666 if ((highest_bit_set
- lowest_bit_set
) < 21)
1672 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1673 unsigned HOST_WIDE_INT
,
1676 static unsigned HOST_WIDE_INT
1677 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1678 unsigned HOST_WIDE_INT low_bits
,
1679 int lowest_bit_set
, int shift
)
1681 HOST_WIDE_INT hi
, lo
;
1683 if (lowest_bit_set
< 32)
1685 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1686 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1691 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1693 gcc_assert (! (hi
& lo
));
1697 /* Here we are sure to be arch64 and this is an integer constant
1698 being loaded into a register. Emit the most efficient
1699 insn sequence possible. Detection of all the 1-insn cases
1700 has been done already. */
1702 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1704 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1705 int lowest_bit_set
, highest_bit_set
;
1706 int all_bits_between_are_set
;
1709 /* Sanity check that we know what we are working with. */
1710 gcc_assert (TARGET_ARCH64
1711 && (GET_CODE (op0
) == SUBREG
1712 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1714 if (reload_in_progress
|| reload_completed
)
1717 if (GET_CODE (op1
) != CONST_INT
)
1719 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1724 temp
= gen_reg_rtx (DImode
);
1726 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1727 low_bits
= (INTVAL (op1
) & 0xffffffff);
1729 /* low_bits bits 0 --> 31
1730 high_bits bits 32 --> 63 */
1732 analyze_64bit_constant (high_bits
, low_bits
,
1733 &highest_bit_set
, &lowest_bit_set
,
1734 &all_bits_between_are_set
);
1736 /* First try for a 2-insn sequence. */
1738 /* These situations are preferred because the optimizer can
1739 * do more things with them:
1741 * sllx %reg, shift, %reg
1743 * srlx %reg, shift, %reg
1744 * 3) mov some_small_const, %reg
1745 * sllx %reg, shift, %reg
1747 if (((highest_bit_set
== 63
1748 || lowest_bit_set
== 0)
1749 && all_bits_between_are_set
!= 0)
1750 || ((highest_bit_set
- lowest_bit_set
) < 12))
1752 HOST_WIDE_INT the_const
= -1;
1753 int shift
= lowest_bit_set
;
1755 if ((highest_bit_set
!= 63
1756 && lowest_bit_set
!= 0)
1757 || all_bits_between_are_set
== 0)
1760 create_simple_focus_bits (high_bits
, low_bits
,
1763 else if (lowest_bit_set
== 0)
1764 shift
= -(63 - highest_bit_set
);
1766 gcc_assert (SPARC_SIMM13_P (the_const
));
1767 gcc_assert (shift
!= 0);
1769 emit_insn (gen_safe_SET64 (temp
, the_const
));
1771 emit_insn (gen_rtx_SET (VOIDmode
,
1773 gen_rtx_ASHIFT (DImode
,
1777 emit_insn (gen_rtx_SET (VOIDmode
,
1779 gen_rtx_LSHIFTRT (DImode
,
1781 GEN_INT (-shift
))));
1785 /* Now a range of 22 or less bits set somewhere.
1786 * 1) sethi %hi(focus_bits), %reg
1787 * sllx %reg, shift, %reg
1788 * 2) sethi %hi(focus_bits), %reg
1789 * srlx %reg, shift, %reg
1791 if ((highest_bit_set
- lowest_bit_set
) < 21)
1793 unsigned HOST_WIDE_INT focus_bits
=
1794 create_simple_focus_bits (high_bits
, low_bits
,
1795 lowest_bit_set
, 10);
1797 gcc_assert (SPARC_SETHI_P (focus_bits
));
1798 gcc_assert (lowest_bit_set
!= 10);
1800 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1802 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1803 if (lowest_bit_set
< 10)
1804 emit_insn (gen_rtx_SET (VOIDmode
,
1806 gen_rtx_LSHIFTRT (DImode
, temp
,
1807 GEN_INT (10 - lowest_bit_set
))));
1808 else if (lowest_bit_set
> 10)
1809 emit_insn (gen_rtx_SET (VOIDmode
,
1811 gen_rtx_ASHIFT (DImode
, temp
,
1812 GEN_INT (lowest_bit_set
- 10))));
1816 /* 1) sethi %hi(low_bits), %reg
1817 * or %reg, %lo(low_bits), %reg
1818 * 2) sethi %hi(~low_bits), %reg
1819 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1822 || high_bits
== 0xffffffff)
1824 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1825 (high_bits
== 0xffffffff));
1829 /* Now, try 3-insn sequences. */
1831 /* 1) sethi %hi(high_bits), %reg
1832 * or %reg, %lo(high_bits), %reg
1833 * sllx %reg, 32, %reg
1837 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1841 /* We may be able to do something quick
1842 when the constant is negated, so try that. */
1843 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1844 (~low_bits
) & 0xfffffc00))
1846 /* NOTE: The trailing bits get XOR'd so we need the
1847 non-negated bits, not the negated ones. */
1848 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1850 if ((((~high_bits
) & 0xffffffff) == 0
1851 && ((~low_bits
) & 0x80000000) == 0)
1852 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1853 && ((~low_bits
) & 0x80000000) != 0))
1855 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1857 if ((SPARC_SETHI_P (fast_int
)
1858 && (~high_bits
& 0xffffffff) == 0)
1859 || SPARC_SIMM13_P (fast_int
))
1860 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1862 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
1867 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1868 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1869 sparc_emit_set_const64 (temp
, negated_const
);
1872 /* If we are XOR'ing with -1, then we should emit a one's complement
1873 instead. This way the combiner will notice logical operations
1874 such as ANDN later on and substitute. */
1875 if (trailing_bits
== 0x3ff)
1877 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1878 gen_rtx_NOT (DImode
, temp
)));
1882 emit_insn (gen_rtx_SET (VOIDmode
,
1884 gen_safe_XOR64 (temp
,
1885 (-0x400 | trailing_bits
))));
1890 /* 1) sethi %hi(xxx), %reg
1891 * or %reg, %lo(xxx), %reg
1892 * sllx %reg, yyy, %reg
1894 * ??? This is just a generalized version of the low_bits==0
1895 * thing above, FIXME...
1897 if ((highest_bit_set
- lowest_bit_set
) < 32)
1899 unsigned HOST_WIDE_INT focus_bits
=
1900 create_simple_focus_bits (high_bits
, low_bits
,
1903 /* We can't get here in this state. */
1904 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
1906 /* So what we know is that the set bits straddle the
1907 middle of the 64-bit word. */
1908 sparc_emit_set_const64_quick2 (op0
, temp
,
1914 /* 1) sethi %hi(high_bits), %reg
1915 * or %reg, %lo(high_bits), %reg
1916 * sllx %reg, 32, %reg
1917 * or %reg, low_bits, %reg
1919 if (SPARC_SIMM13_P(low_bits
)
1920 && ((int)low_bits
> 0))
1922 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
1926 /* The easiest way when all else fails, is full decomposition. */
1928 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1929 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
1931 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
1933 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
1935 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1936 return the mode to be used for the comparison. For floating-point,
1937 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1938 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1939 processing is needed. */
1942 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
1944 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1970 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
1971 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
1973 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
1974 return CCX_NOOVmode
;
1980 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
1987 /* Emit the compare insn and return the CC reg for a CODE comparison
1988 with operands X and Y. */
1991 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
1993 enum machine_mode mode
;
1996 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
1999 mode
= SELECT_CC_MODE (code
, x
, y
);
2001 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2002 fcc regs (cse can't tell they're really call clobbered regs and will
2003 remove a duplicate comparison even if there is an intervening function
2004 call - it will then try to reload the cc reg via an int reg which is why
2005 we need the movcc patterns). It is possible to provide the movcc
2006 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2007 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2008 to tell cse that CCFPE mode registers (even pseudos) are call
2011 /* ??? This is an experiment. Rather than making changes to cse which may
2012 or may not be easy/clean, we do our own cse. This is possible because
2013 we will generate hard registers. Cse knows they're call clobbered (it
2014 doesn't know the same thing about pseudos). If we guess wrong, no big
2015 deal, but if we win, great! */
2017 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2018 #if 1 /* experiment */
2021 /* We cycle through the registers to ensure they're all exercised. */
2022 static int next_fcc_reg
= 0;
2023 /* Previous x,y for each fcc reg. */
2024 static rtx prev_args
[4][2];
2026 /* Scan prev_args for x,y. */
2027 for (reg
= 0; reg
< 4; reg
++)
2028 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2033 prev_args
[reg
][0] = x
;
2034 prev_args
[reg
][1] = y
;
2035 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2037 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2040 cc_reg
= gen_reg_rtx (mode
);
2041 #endif /* ! experiment */
2042 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2043 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2045 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2047 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2048 will only result in an unrecognizable insn so no point in asserting. */
2049 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2055 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2058 gen_compare_reg (rtx cmp
)
2060 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2063 /* This function is used for v9 only.
2064 DEST is the target of the Scc insn.
2065 CODE is the code for an Scc's comparison.
2066 X and Y are the values we compare.
2068 This function is needed to turn
2071 (gt (reg:CCX 100 %icc)
2075 (gt:DI (reg:CCX 100 %icc)
2078 IE: The instruction recognizer needs to see the mode of the comparison to
2079 find the right instruction. We could use "gt:DI" right in the
2080 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2083 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2086 && (GET_MODE (x
) == DImode
2087 || GET_MODE (dest
) == DImode
))
2090 /* Try to use the movrCC insns. */
2092 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2094 && v9_regcmp_p (compare_code
))
2099 /* Special case for op0 != 0. This can be done with one instruction if
2102 if (compare_code
== NE
2103 && GET_MODE (dest
) == DImode
2104 && rtx_equal_p (op0
, dest
))
2106 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2107 gen_rtx_IF_THEN_ELSE (DImode
,
2108 gen_rtx_fmt_ee (compare_code
, DImode
,
2115 if (reg_overlap_mentioned_p (dest
, op0
))
2117 /* Handle the case where dest == x.
2118 We "early clobber" the result. */
2119 op0
= gen_reg_rtx (GET_MODE (x
));
2120 emit_move_insn (op0
, x
);
2123 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2124 if (GET_MODE (op0
) != DImode
)
2126 temp
= gen_reg_rtx (DImode
);
2127 convert_move (temp
, op0
, 0);
2131 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2132 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2133 gen_rtx_fmt_ee (compare_code
, DImode
,
2141 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2144 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2145 && GET_MODE (x
) != CCX_NOOVmode
);
2147 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2148 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2149 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2150 gen_rtx_fmt_ee (compare_code
,
2151 GET_MODE (x
), x
, y
),
2152 const1_rtx
, dest
)));
2158 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2159 without jumps using the addx/subx instructions. */
2162 emit_scc_insn (rtx operands
[])
2169 /* The quad-word fp compare library routines all return nonzero to indicate
2170 true, which is different from the equivalent libgcc routines, so we must
2171 handle them specially here. */
2172 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2174 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2175 GET_CODE (operands
[1]));
2176 operands
[2] = XEXP (operands
[1], 0);
2177 operands
[3] = XEXP (operands
[1], 1);
2180 code
= GET_CODE (operands
[1]);
2184 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2185 more applications). The exception to this is "reg != 0" which can
2186 be done in one instruction on v9 (so we do it). */
2189 if (GET_MODE (x
) == SImode
)
2191 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2195 else if (GET_MODE (x
) == DImode
)
2197 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2205 if (GET_MODE (x
) == SImode
)
2207 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2211 else if (GET_MODE (x
) == DImode
)
2213 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2219 /* For the rest, on v9 we can use conditional moves. */
2223 if (gen_v9_scc (operands
[0], code
, x
, y
))
2227 /* We can do LTU and GEU using the addx/subx instructions too. And
2228 for GTU/LEU, if both operands are registers swap them and fall
2229 back to the easy case. */
2230 if (code
== GTU
|| code
== LEU
)
2232 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2233 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2238 code
= swap_condition (code
);
2242 if (code
== LTU
|| code
== GEU
)
2244 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2245 gen_rtx_fmt_ee (code
, SImode
,
2246 gen_compare_reg_1 (code
, x
, y
),
2251 /* Nope, do branches. */
2255 /* Emit a conditional jump insn for the v9 architecture using comparison code
2256 CODE and jump target LABEL.
2257 This function exists to take advantage of the v9 brxx insns. */
2260 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2262 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2264 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2265 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2267 gen_rtx_LABEL_REF (VOIDmode
, label
),
2272 emit_conditional_branch_insn (rtx operands
[])
2274 /* The quad-word fp compare library routines all return nonzero to indicate
2275 true, which is different from the equivalent libgcc routines, so we must
2276 handle them specially here. */
2277 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2279 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2280 GET_CODE (operands
[0]));
2281 operands
[1] = XEXP (operands
[0], 0);
2282 operands
[2] = XEXP (operands
[0], 1);
2285 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2286 && GET_CODE (operands
[1]) == REG
2287 && GET_MODE (operands
[1]) == DImode
)
2289 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2293 operands
[1] = gen_compare_reg (operands
[0]);
2294 operands
[2] = const0_rtx
;
2295 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2296 operands
[1], operands
[2]);
2297 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2302 /* Generate a DFmode part of a hard TFmode register.
2303 REG is the TFmode hard register, LOW is 1 for the
2304 low 64bit of the register and 0 otherwise.
2307 gen_df_reg (rtx reg
, int low
)
2309 int regno
= REGNO (reg
);
2311 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2312 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2313 return gen_rtx_REG (DFmode
, regno
);
2316 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2317 Unlike normal calls, TFmode operands are passed by reference. It is
2318 assumed that no more than 3 operands are required. */
2321 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2323 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2326 /* We only expect to be called for conversions, unary, and binary ops. */
2327 gcc_assert (nargs
== 2 || nargs
== 3);
2329 for (i
= 0; i
< nargs
; ++i
)
2331 rtx this_arg
= operands
[i
];
2334 /* TFmode arguments and return values are passed by reference. */
2335 if (GET_MODE (this_arg
) == TFmode
)
2337 int force_stack_temp
;
2339 force_stack_temp
= 0;
2340 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2341 force_stack_temp
= 1;
2343 if (GET_CODE (this_arg
) == MEM
2344 && ! force_stack_temp
)
2345 this_arg
= XEXP (this_arg
, 0);
2346 else if (CONSTANT_P (this_arg
)
2347 && ! force_stack_temp
)
2349 this_slot
= force_const_mem (TFmode
, this_arg
);
2350 this_arg
= XEXP (this_slot
, 0);
2354 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2356 /* Operand 0 is the return value. We'll copy it out later. */
2358 emit_move_insn (this_slot
, this_arg
);
2360 ret_slot
= this_slot
;
2362 this_arg
= XEXP (this_slot
, 0);
2369 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2371 if (GET_MODE (operands
[0]) == TFmode
)
2374 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2375 arg
[0], GET_MODE (arg
[0]),
2376 arg
[1], GET_MODE (arg
[1]));
2378 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2379 arg
[0], GET_MODE (arg
[0]),
2380 arg
[1], GET_MODE (arg
[1]),
2381 arg
[2], GET_MODE (arg
[2]));
2384 emit_move_insn (operands
[0], ret_slot
);
2390 gcc_assert (nargs
== 2);
2392 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2393 GET_MODE (operands
[0]), 1,
2394 arg
[1], GET_MODE (arg
[1]));
2396 if (ret
!= operands
[0])
2397 emit_move_insn (operands
[0], ret
);
2401 /* Expand soft-float TFmode calls to sparc abi routines. */
2404 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2426 emit_soft_tfmode_libcall (func
, 3, operands
);
2430 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2434 gcc_assert (code
== SQRT
);
2437 emit_soft_tfmode_libcall (func
, 2, operands
);
2441 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2448 switch (GET_MODE (operands
[1]))
2461 case FLOAT_TRUNCATE
:
2462 switch (GET_MODE (operands
[0]))
2476 switch (GET_MODE (operands
[1]))
2481 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2491 case UNSIGNED_FLOAT
:
2492 switch (GET_MODE (operands
[1]))
2497 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2508 switch (GET_MODE (operands
[0]))
2522 switch (GET_MODE (operands
[0]))
2539 emit_soft_tfmode_libcall (func
, 2, operands
);
2542 /* Expand a hard-float tfmode operation. All arguments must be in
2546 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2550 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2552 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2553 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2557 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2558 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2559 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2560 operands
[1], operands
[2]);
2563 if (register_operand (operands
[0], VOIDmode
))
2566 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2568 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2570 if (dest
!= operands
[0])
2571 emit_move_insn (operands
[0], dest
);
2575 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2577 if (TARGET_HARD_QUAD
)
2578 emit_hard_tfmode_operation (code
, operands
);
2580 emit_soft_tfmode_binop (code
, operands
);
2584 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2586 if (TARGET_HARD_QUAD
)
2587 emit_hard_tfmode_operation (code
, operands
);
2589 emit_soft_tfmode_unop (code
, operands
);
2593 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2595 if (TARGET_HARD_QUAD
)
2596 emit_hard_tfmode_operation (code
, operands
);
2598 emit_soft_tfmode_cvt (code
, operands
);
2601 /* Return nonzero if a branch/jump/call instruction will be emitting
2602 nop into its delay slot. */
2605 empty_delay_slot (rtx insn
)
2609 /* If no previous instruction (should not happen), return true. */
2610 if (PREV_INSN (insn
) == NULL
)
2613 seq
= NEXT_INSN (PREV_INSN (insn
));
2614 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2620 /* Return nonzero if TRIAL can go into the call delay slot. */
2623 tls_call_delay (rtx trial
)
2628 call __tls_get_addr, %tgd_call (foo)
2629 add %l7, %o0, %o0, %tgd_add (foo)
2630 while Sun as/ld does not. */
2631 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2634 pat
= PATTERN (trial
);
2636 /* We must reject tgd_add{32|64}, i.e.
2637 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2638 and tldm_add{32|64}, i.e.
2639 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2641 if (GET_CODE (pat
) == SET
2642 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2644 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2646 if (GET_CODE (unspec
) == UNSPEC
2647 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2648 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2655 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2656 instruction. RETURN_P is true if the v9 variant 'return' is to be
2657 considered in the test too.
2659 TRIAL must be a SET whose destination is a REG appropriate for the
2660 'restore' instruction or, if RETURN_P is true, for the 'return'
2664 eligible_for_restore_insn (rtx trial
, bool return_p
)
2666 rtx pat
= PATTERN (trial
);
2667 rtx src
= SET_SRC (pat
);
2669 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2670 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2671 && arith_operand (src
, GET_MODE (src
)))
2674 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2676 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2679 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2680 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2681 && arith_double_operand (src
, GET_MODE (src
)))
2682 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2684 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2685 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2688 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2689 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2692 /* If we have the 'return' instruction, anything that does not use
2693 local or output registers and can go into a delay slot wins. */
2694 else if (return_p
&& TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2695 && (get_attr_in_uncond_branch_delay (trial
)
2696 == IN_UNCOND_BRANCH_DELAY_TRUE
))
2699 /* The 'restore src1,src2,dest' pattern for SImode. */
2700 else if (GET_CODE (src
) == PLUS
2701 && register_operand (XEXP (src
, 0), SImode
)
2702 && arith_operand (XEXP (src
, 1), SImode
))
2705 /* The 'restore src1,src2,dest' pattern for DImode. */
2706 else if (GET_CODE (src
) == PLUS
2707 && register_operand (XEXP (src
, 0), DImode
)
2708 && arith_double_operand (XEXP (src
, 1), DImode
))
2711 /* The 'restore src1,%lo(src2),dest' pattern. */
2712 else if (GET_CODE (src
) == LO_SUM
2713 && ! TARGET_CM_MEDMID
2714 && ((register_operand (XEXP (src
, 0), SImode
)
2715 && immediate_operand (XEXP (src
, 1), SImode
))
2717 && register_operand (XEXP (src
, 0), DImode
)
2718 && immediate_operand (XEXP (src
, 1), DImode
))))
2721 /* The 'restore src,src,dest' pattern. */
2722 else if (GET_CODE (src
) == ASHIFT
2723 && (register_operand (XEXP (src
, 0), SImode
)
2724 || register_operand (XEXP (src
, 0), DImode
))
2725 && XEXP (src
, 1) == const1_rtx
)
2731 /* Return nonzero if TRIAL can go into the function return's
2735 eligible_for_return_delay (rtx trial
)
2739 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2742 if (get_attr_length (trial
) != 1)
2745 /* If there are any call-saved registers, we should scan TRIAL if it
2746 does not reference them. For now just make it easy. */
2750 /* If the function uses __builtin_eh_return, the eh_return machinery
2751 occupies the delay slot. */
2752 if (crtl
->calls_eh_return
)
2755 /* In the case of a true leaf function, anything can go into the slot. */
2756 if (sparc_leaf_function_p
)
2757 return get_attr_in_uncond_branch_delay (trial
)
2758 == IN_UNCOND_BRANCH_DELAY_TRUE
;
2760 pat
= PATTERN (trial
);
2762 /* Otherwise, only operations which can be done in tandem with
2763 a `restore' or `return' insn can go into the delay slot. */
2764 if (GET_CODE (SET_DEST (pat
)) != REG
2765 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24))
2768 /* If this instruction sets up floating point register and we have a return
2769 instruction, it can probably go in. But restore will not work
2771 if (REGNO (SET_DEST (pat
)) >= 32)
2773 && ! epilogue_renumber (&pat
, 1)
2774 && (get_attr_in_uncond_branch_delay (trial
)
2775 == IN_UNCOND_BRANCH_DELAY_TRUE
));
2777 return eligible_for_restore_insn (trial
, true);
2780 /* Return nonzero if TRIAL can go into the sibling call's
2784 eligible_for_sibcall_delay (rtx trial
)
2788 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2791 if (get_attr_length (trial
) != 1)
2794 pat
= PATTERN (trial
);
2796 if (sparc_leaf_function_p
)
2798 /* If the tail call is done using the call instruction,
2799 we have to restore %o7 in the delay slot. */
2800 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2803 /* %g1 is used to build the function address */
2804 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2810 /* Otherwise, only operations which can be done in tandem with
2811 a `restore' insn can go into the delay slot. */
2812 if (GET_CODE (SET_DEST (pat
)) != REG
2813 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2814 || REGNO (SET_DEST (pat
)) >= 32)
2817 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2819 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2822 return eligible_for_restore_insn (trial
, false);
2826 short_branch (int uid1
, int uid2
)
2828 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2830 /* Leave a few words of "slop". */
2831 if (delta
>= -1023 && delta
<= 1022)
2837 /* Return nonzero if REG is not used after INSN.
2838 We assume REG is a reload reg, and therefore does
2839 not live past labels or calls or jumps. */
2841 reg_unused_after (rtx reg
, rtx insn
)
2843 enum rtx_code code
, prev_code
= UNKNOWN
;
2845 while ((insn
= NEXT_INSN (insn
)))
2847 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2850 code
= GET_CODE (insn
);
2851 if (GET_CODE (insn
) == CODE_LABEL
)
2856 rtx set
= single_set (insn
);
2857 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2860 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2862 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2870 /* Determine if it's legal to put X into the constant pool. This
2871 is not possible if X contains the address of a symbol that is
2872 not constant (TLS) or not known at final link time (PIC). */
2875 sparc_cannot_force_const_mem (rtx x
)
2877 switch (GET_CODE (x
))
2882 /* Accept all non-symbolic constants. */
2886 /* Labels are OK iff we are non-PIC. */
2887 return flag_pic
!= 0;
2890 /* 'Naked' TLS symbol references are never OK,
2891 non-TLS symbols are OK iff we are non-PIC. */
2892 if (SYMBOL_REF_TLS_MODEL (x
))
2895 return flag_pic
!= 0;
2898 return sparc_cannot_force_const_mem (XEXP (x
, 0));
2901 return sparc_cannot_force_const_mem (XEXP (x
, 0))
2902 || sparc_cannot_force_const_mem (XEXP (x
, 1));
2911 static GTY(()) bool pic_helper_needed
= false;
2912 static GTY(()) rtx pic_helper_symbol
;
2913 static GTY(()) rtx global_offset_table
;
2915 /* Ensure that we are not using patterns that are not OK with PIC. */
2923 gcc_assert (GET_CODE (recog_data
.operand
[i
]) != SYMBOL_REF
2924 && (GET_CODE (recog_data
.operand
[i
]) != CONST
2925 || (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
2926 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
2927 == global_offset_table
)
2928 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
2936 /* Return true if X is an address which needs a temporary register when
2937 reloaded while generating PIC code. */
2940 pic_address_needs_scratch (rtx x
)
2942 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2943 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
2944 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2945 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2946 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
2952 /* Determine if a given RTX is a valid constant. We already know this
2953 satisfies CONSTANT_P. */
2956 legitimate_constant_p (rtx x
)
2958 switch (GET_CODE (x
))
2962 if (sparc_tls_referenced_p (x
))
2967 if (GET_MODE (x
) == VOIDmode
)
2970 /* Floating point constants are generally not ok.
2971 The only exception is 0.0 in VIS. */
2973 && SCALAR_FLOAT_MODE_P (GET_MODE (x
))
2974 && const_zero_operand (x
, GET_MODE (x
)))
2980 /* Vector constants are generally not ok.
2981 The only exception is 0 in VIS. */
2983 && const_zero_operand (x
, GET_MODE (x
)))
2995 /* Determine if a given RTX is a valid constant address. */
2998 constant_address_p (rtx x
)
3000 switch (GET_CODE (x
))
3008 if (flag_pic
&& pic_address_needs_scratch (x
))
3010 return legitimate_constant_p (x
);
3013 return !flag_pic
&& legitimate_constant_p (x
);
3020 /* Nonzero if the constant value X is a legitimate general operand
3021 when generating PIC code. It is given that flag_pic is on and
3022 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3025 legitimate_pic_operand_p (rtx x
)
3027 if (pic_address_needs_scratch (x
))
3029 if (sparc_tls_referenced_p (x
))
3034 /* Return nonzero if ADDR is a valid memory address.
3035 STRICT specifies whether strict register checking applies. */
3038 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3040 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3042 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3044 else if (GET_CODE (addr
) == PLUS
)
3046 rs1
= XEXP (addr
, 0);
3047 rs2
= XEXP (addr
, 1);
3049 /* Canonicalize. REG comes first, if there are no regs,
3050 LO_SUM comes first. */
3052 && GET_CODE (rs1
) != SUBREG
3054 || GET_CODE (rs2
) == SUBREG
3055 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3057 rs1
= XEXP (addr
, 1);
3058 rs2
= XEXP (addr
, 0);
3062 && rs1
== pic_offset_table_rtx
3064 && GET_CODE (rs2
) != SUBREG
3065 && GET_CODE (rs2
) != LO_SUM
3066 && GET_CODE (rs2
) != MEM
3067 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3068 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3069 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3071 || GET_CODE (rs1
) == SUBREG
)
3072 && RTX_OK_FOR_OFFSET_P (rs2
)))
3077 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3078 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3080 /* We prohibit REG + REG for TFmode when there are no quad move insns
3081 and we consequently need to split. We do this because REG+REG
3082 is not an offsettable address. If we get the situation in reload
3083 where source and destination of a movtf pattern are both MEMs with
3084 REG+REG address, then only one of them gets converted to an
3085 offsettable address. */
3087 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3090 /* We prohibit REG + REG on ARCH32 if not optimizing for
3091 DFmode/DImode because then mem_min_alignment is likely to be zero
3092 after reload and the forced split would lack a matching splitter
3094 if (TARGET_ARCH32
&& !optimize
3095 && (mode
== DFmode
|| mode
== DImode
))
3098 else if (USE_AS_OFFSETABLE_LO10
3099 && GET_CODE (rs1
) == LO_SUM
3101 && ! TARGET_CM_MEDMID
3102 && RTX_OK_FOR_OLO10_P (rs2
))
3105 imm1
= XEXP (rs1
, 1);
3106 rs1
= XEXP (rs1
, 0);
3107 if (!CONSTANT_P (imm1
)
3108 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3112 else if (GET_CODE (addr
) == LO_SUM
)
3114 rs1
= XEXP (addr
, 0);
3115 imm1
= XEXP (addr
, 1);
3117 if (!CONSTANT_P (imm1
)
3118 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3121 /* We can't allow TFmode in 32-bit mode, because an offset greater
3122 than the alignment (8) may cause the LO_SUM to overflow. */
3123 if (mode
== TFmode
&& TARGET_ARCH32
)
3126 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3131 if (GET_CODE (rs1
) == SUBREG
)
3132 rs1
= SUBREG_REG (rs1
);
3138 if (GET_CODE (rs2
) == SUBREG
)
3139 rs2
= SUBREG_REG (rs2
);
3146 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3147 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3152 if ((REGNO (rs1
) >= 32
3153 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3154 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3156 && (REGNO (rs2
) >= 32
3157 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3158 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3164 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3166 static GTY(()) rtx sparc_tls_symbol
;
3169 sparc_tls_get_addr (void)
3171 if (!sparc_tls_symbol
)
3172 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3174 return sparc_tls_symbol
;
3178 sparc_tls_got (void)
3183 crtl
->uses_pic_offset_table
= 1;
3184 return pic_offset_table_rtx
;
3187 if (!global_offset_table
)
3188 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3189 temp
= gen_reg_rtx (Pmode
);
3190 emit_move_insn (temp
, global_offset_table
);
3194 /* Return true if X contains a thread-local symbol. */
3197 sparc_tls_referenced_p (rtx x
)
3199 if (!TARGET_HAVE_TLS
)
3202 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3203 x
= XEXP (XEXP (x
, 0), 0);
3205 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3208 /* That's all we handle in legitimize_tls_address for now. */
3212 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3213 this (thread-local) address. */
3216 legitimize_tls_address (rtx addr
)
3218 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3220 gcc_assert (can_create_pseudo_p ());
3222 if (GET_CODE (addr
) == SYMBOL_REF
)
3223 switch (SYMBOL_REF_TLS_MODEL (addr
))
3225 case TLS_MODEL_GLOBAL_DYNAMIC
:
3227 temp1
= gen_reg_rtx (SImode
);
3228 temp2
= gen_reg_rtx (SImode
);
3229 ret
= gen_reg_rtx (Pmode
);
3230 o0
= gen_rtx_REG (Pmode
, 8);
3231 got
= sparc_tls_got ();
3232 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3233 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3236 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3237 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3242 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3243 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3246 CALL_INSN_FUNCTION_USAGE (insn
)
3247 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3248 CALL_INSN_FUNCTION_USAGE (insn
));
3249 insn
= get_insns ();
3251 emit_libcall_block (insn
, ret
, o0
, addr
);
3254 case TLS_MODEL_LOCAL_DYNAMIC
:
3256 temp1
= gen_reg_rtx (SImode
);
3257 temp2
= gen_reg_rtx (SImode
);
3258 temp3
= gen_reg_rtx (Pmode
);
3259 ret
= gen_reg_rtx (Pmode
);
3260 o0
= gen_rtx_REG (Pmode
, 8);
3261 got
= sparc_tls_got ();
3262 emit_insn (gen_tldm_hi22 (temp1
));
3263 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3266 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3267 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3272 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3273 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3276 CALL_INSN_FUNCTION_USAGE (insn
)
3277 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3278 CALL_INSN_FUNCTION_USAGE (insn
));
3279 insn
= get_insns ();
3281 emit_libcall_block (insn
, temp3
, o0
,
3282 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3283 UNSPEC_TLSLD_BASE
));
3284 temp1
= gen_reg_rtx (SImode
);
3285 temp2
= gen_reg_rtx (SImode
);
3286 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3287 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3289 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3291 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3294 case TLS_MODEL_INITIAL_EXEC
:
3295 temp1
= gen_reg_rtx (SImode
);
3296 temp2
= gen_reg_rtx (SImode
);
3297 temp3
= gen_reg_rtx (Pmode
);
3298 got
= sparc_tls_got ();
3299 emit_insn (gen_tie_hi22 (temp1
, addr
));
3300 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3302 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3304 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3307 ret
= gen_reg_rtx (Pmode
);
3309 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3312 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3316 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3319 case TLS_MODEL_LOCAL_EXEC
:
3320 temp1
= gen_reg_rtx (Pmode
);
3321 temp2
= gen_reg_rtx (Pmode
);
3324 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3325 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3329 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3330 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3332 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3339 else if (GET_CODE (addr
) == CONST
)
3343 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3345 base
= legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3346 offset
= XEXP (XEXP (addr
, 0), 1);
3348 base
= force_operand (base
, NULL_RTX
);
3349 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3350 offset
= force_reg (Pmode
, offset
);
3351 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3355 gcc_unreachable (); /* for now ... */
3360 /* Legitimize PIC addresses. If the address is already position-independent,
3361 we return ORIG. Newly generated position-independent addresses go into a
3362 reg. This is REG if nonzero, otherwise we allocate register(s) as
3366 legitimize_pic_address (rtx orig
, rtx reg
)
3368 bool gotdata_op
= false;
3370 if (GET_CODE (orig
) == SYMBOL_REF
3371 /* See the comment in sparc_expand_move. */
3372 || (TARGET_VXWORKS_RTP
&& GET_CODE (orig
) == LABEL_REF
))
3374 rtx pic_ref
, address
;
3379 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3380 reg
= gen_reg_rtx (Pmode
);
3385 /* If not during reload, allocate another temp reg here for loading
3386 in the address, so that these instructions can be optimized
3388 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3389 ? reg
: gen_reg_rtx (Pmode
));
3391 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3392 won't get confused into thinking that these two instructions
3393 are loading in the true address of the symbol. If in the
3394 future a PIC rtx exists, that should be used instead. */
3397 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3398 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3402 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3403 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3411 crtl
->uses_pic_offset_table
= 1;
3415 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
, pic_offset_table_rtx
,
3418 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
, pic_offset_table_rtx
,
3423 pic_ref
= gen_const_mem (Pmode
,
3424 gen_rtx_PLUS (Pmode
,
3425 pic_offset_table_rtx
, address
));
3426 insn
= emit_move_insn (reg
, pic_ref
);
3428 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3430 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3433 else if (GET_CODE (orig
) == CONST
)
3437 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3438 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3443 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3444 reg
= gen_reg_rtx (Pmode
);
3447 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3448 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3449 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3450 base
== reg
? NULL_RTX
: reg
);
3452 if (GET_CODE (offset
) == CONST_INT
)
3454 if (SMALL_INT (offset
))
3455 return plus_constant (base
, INTVAL (offset
));
3456 else if (! reload_in_progress
&& ! reload_completed
)
3457 offset
= force_reg (Pmode
, offset
);
3459 /* If we reach here, then something is seriously wrong. */
3462 return gen_rtx_PLUS (Pmode
, base
, offset
);
3464 else if (GET_CODE (orig
) == LABEL_REF
)
3465 /* ??? Why do we do this? */
3466 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3467 the register is live instead, in case it is eliminated. */
3468 crtl
->uses_pic_offset_table
= 1;
3473 /* Try machine-dependent ways of modifying an illegitimate address X
3474 to be legitimate. If we find one, return the new, valid address.
3476 OLDX is the address as it was before break_out_memory_refs was called.
3477 In some cases it is useful to look at this to decide what needs to be done.
3479 MODE is the mode of the operand pointed to by X.
3481 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3484 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3485 enum machine_mode mode
)
3489 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3490 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3491 force_operand (XEXP (x
, 0), NULL_RTX
));
3492 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3493 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3494 force_operand (XEXP (x
, 1), NULL_RTX
));
3495 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3496 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3498 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3499 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3500 force_operand (XEXP (x
, 1), NULL_RTX
));
3502 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3505 if (sparc_tls_referenced_p (x
))
3506 x
= legitimize_tls_address (x
);
3508 x
= legitimize_pic_address (x
, NULL_RTX
);
3509 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3510 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3511 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3512 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3513 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3514 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3515 else if (GET_CODE (x
) == SYMBOL_REF
3516 || GET_CODE (x
) == CONST
3517 || GET_CODE (x
) == LABEL_REF
)
3518 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3523 #ifdef HAVE_GAS_HIDDEN
3524 # define USE_HIDDEN_LINKONCE 1
3526 # define USE_HIDDEN_LINKONCE 0
3530 get_pc_thunk_name (char name
[32], unsigned int regno
)
3532 const char *pic_name
= reg_names
[regno
];
3534 /* Skip the leading '%' as that cannot be used in a
3538 if (USE_HIDDEN_LINKONCE
)
3539 sprintf (name
, "__sparc_get_pc_thunk.%s", pic_name
);
3541 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3544 /* Emit code to load the PIC register. */
3547 load_pic_register (void)
3549 int orig_flag_pic
= flag_pic
;
3551 if (TARGET_VXWORKS_RTP
)
3553 emit_insn (gen_vxworks_load_got ());
3554 emit_use (pic_offset_table_rtx
);
3558 /* If we haven't initialized the special PIC symbols, do so now. */
3559 if (!pic_helper_needed
)
3563 pic_helper_needed
= true;
3565 get_pc_thunk_name (name
, REGNO (pic_offset_table_rtx
));
3566 pic_helper_symbol
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3568 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3573 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx
, global_offset_table
,
3574 pic_helper_symbol
));
3576 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx
, global_offset_table
,
3577 pic_helper_symbol
));
3578 flag_pic
= orig_flag_pic
;
3580 /* Need to emit this whether or not we obey regdecls,
3581 since setjmp/longjmp can cause life info to screw up.
3582 ??? In the case where we don't obey regdecls, this is not sufficient
3583 since we may not fall out the bottom. */
3584 emit_use (pic_offset_table_rtx
);
3587 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3588 address of the call target. */
3591 sparc_emit_call_insn (rtx pat
, rtx addr
)
3595 insn
= emit_call_insn (pat
);
3597 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3598 if (TARGET_VXWORKS_RTP
3600 && GET_CODE (addr
) == SYMBOL_REF
3601 && (SYMBOL_REF_DECL (addr
)
3602 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
3603 : !SYMBOL_REF_LOCAL_P (addr
)))
3605 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3606 crtl
->uses_pic_offset_table
= 1;
3610 /* Return 1 if RTX is a MEM which is known to be aligned to at
3611 least a DESIRED byte boundary. */
3614 mem_min_alignment (rtx mem
, int desired
)
3616 rtx addr
, base
, offset
;
3618 /* If it's not a MEM we can't accept it. */
3619 if (GET_CODE (mem
) != MEM
)
3623 if (!TARGET_UNALIGNED_DOUBLES
3624 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3627 /* ??? The rest of the function predates MEM_ALIGN so
3628 there is probably a bit of redundancy. */
3629 addr
= XEXP (mem
, 0);
3630 base
= offset
= NULL_RTX
;
3631 if (GET_CODE (addr
) == PLUS
)
3633 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3635 base
= XEXP (addr
, 0);
3637 /* What we are saying here is that if the base
3638 REG is aligned properly, the compiler will make
3639 sure any REG based index upon it will be so
3641 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3642 offset
= XEXP (addr
, 1);
3644 offset
= const0_rtx
;
3647 else if (GET_CODE (addr
) == REG
)
3650 offset
= const0_rtx
;
3653 if (base
!= NULL_RTX
)
3655 int regno
= REGNO (base
);
3657 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3659 /* Check if the compiler has recorded some information
3660 about the alignment of the base REG. If reload has
3661 completed, we already matched with proper alignments.
3662 If not running global_alloc, reload might give us
3663 unaligned pointer to local stack though. */
3665 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3666 || (optimize
&& reload_completed
))
3667 && (INTVAL (offset
) & (desired
- 1)) == 0)
3672 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3676 else if (! TARGET_UNALIGNED_DOUBLES
3677 || CONSTANT_P (addr
)
3678 || GET_CODE (addr
) == LO_SUM
)
3680 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3681 is true, in which case we can only assume that an access is aligned if
3682 it is to a constant address, or the address involves a LO_SUM. */
3686 /* An obviously unaligned address. */
3691 /* Vectors to keep interesting information about registers where it can easily
3692 be got. We used to use the actual mode value as the bit number, but there
3693 are more than 32 modes now. Instead we use two tables: one indexed by
3694 hard register number, and one indexed by mode. */
3696 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3697 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
3698 mapped into one sparc_mode_class mode. */
3700 enum sparc_mode_class
{
3701 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3702 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3706 /* Modes for single-word and smaller quantities. */
3707 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3709 /* Modes for double-word and smaller quantities. */
3710 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3712 /* Modes for quad-word and smaller quantities. */
3713 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3715 /* Modes for 8-word and smaller quantities. */
3716 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3718 /* Modes for single-float quantities. We must allow any single word or
3719 smaller quantity. This is because the fix/float conversion instructions
3720 take integer inputs/outputs from the float registers. */
3721 #define SF_MODES (S_MODES)
3723 /* Modes for double-float and smaller quantities. */
3724 #define DF_MODES (D_MODES)
3726 /* Modes for quad-float and smaller quantities. */
3727 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
3729 /* Modes for quad-float pairs and smaller quantities. */
3730 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
3732 /* Modes for double-float only quantities. */
3733 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3735 /* Modes for quad-float and double-float only quantities. */
3736 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
3738 /* Modes for quad-float pairs and double-float only quantities. */
3739 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
3741 /* Modes for condition codes. */
3742 #define CC_MODES (1 << (int) CC_MODE)
3743 #define CCFP_MODES (1 << (int) CCFP_MODE)
3745 /* Value is 1 if register/mode pair is acceptable on sparc.
3746 The funny mixture of D and T modes is because integer operations
3747 do not specially operate on tetra quantities, so non-quad-aligned
3748 registers can hold quadword quantities (except %o4 and %i4 because
3749 they cross fixed registers). */
3751 /* This points to either the 32 bit or the 64 bit version. */
3752 const int *hard_regno_mode_classes
;
3754 static const int hard_32bit_mode_classes
[] = {
3755 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3756 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3757 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3758 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3760 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3761 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3762 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3763 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3765 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3766 and none can hold SFmode/SImode values. */
3767 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3768 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3769 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3770 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3773 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3779 static const int hard_64bit_mode_classes
[] = {
3780 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3781 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3782 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3783 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3785 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3786 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3787 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3788 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3790 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3791 and none can hold SFmode/SImode values. */
3792 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3793 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3794 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3795 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3798 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3804 int sparc_mode_class
[NUM_MACHINE_MODES
];
3806 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3809 sparc_init_modes (void)
3813 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3815 switch (GET_MODE_CLASS (i
))
3818 case MODE_PARTIAL_INT
:
3819 case MODE_COMPLEX_INT
:
3820 if (GET_MODE_SIZE (i
) <= 4)
3821 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3822 else if (GET_MODE_SIZE (i
) == 8)
3823 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3824 else if (GET_MODE_SIZE (i
) == 16)
3825 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3826 else if (GET_MODE_SIZE (i
) == 32)
3827 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3829 sparc_mode_class
[i
] = 0;
3831 case MODE_VECTOR_INT
:
3832 if (GET_MODE_SIZE (i
) <= 4)
3833 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
3834 else if (GET_MODE_SIZE (i
) == 8)
3835 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
3838 case MODE_COMPLEX_FLOAT
:
3839 if (GET_MODE_SIZE (i
) <= 4)
3840 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3841 else if (GET_MODE_SIZE (i
) == 8)
3842 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3843 else if (GET_MODE_SIZE (i
) == 16)
3844 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3845 else if (GET_MODE_SIZE (i
) == 32)
3846 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3848 sparc_mode_class
[i
] = 0;
3851 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3852 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3854 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3857 sparc_mode_class
[i
] = 0;
3863 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3865 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3867 /* Initialize the array used by REGNO_REG_CLASS. */
3868 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3870 if (i
< 16 && TARGET_V8PLUS
)
3871 sparc_regno_reg_class
[i
] = I64_REGS
;
3872 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
3873 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3875 sparc_regno_reg_class
[i
] = FP_REGS
;
3877 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3879 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3881 sparc_regno_reg_class
[i
] = NO_REGS
;
3885 /* Compute the frame size required by the function. This function is called
3886 during the reload pass and also by sparc_expand_prologue. */
3889 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function_p
)
3891 int outgoing_args_size
= (crtl
->outgoing_args_size
3892 + REG_PARM_STACK_SPACE (current_function_decl
));
3893 int n_regs
= 0; /* N_REGS is the number of 4-byte regs saved thus far. */
3898 for (i
= 0; i
< 8; i
++)
3899 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
3904 for (i
= 0; i
< 8; i
+= 2)
3905 if ((df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
3906 || (df_regs_ever_live_p (i
+1) && ! call_used_regs
[i
+1]))
3910 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3911 if ((df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
3912 || (df_regs_ever_live_p (i
+1) && ! call_used_regs
[i
+1]))
3915 /* Set up values for use in prologue and epilogue. */
3916 num_gfregs
= n_regs
;
3921 && crtl
->outgoing_args_size
== 0)
3922 actual_fsize
= apparent_fsize
= 0;
3925 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3926 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
3927 apparent_fsize
+= n_regs
* 4;
3928 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3931 /* Make sure nothing can clobber our register windows.
3932 If a SAVE must be done, or there is a stack-local variable,
3933 the register window area must be allocated. */
3934 if (! leaf_function_p
|| size
> 0)
3935 actual_fsize
+= FIRST_PARM_OFFSET (current_function_decl
);
3937 return SPARC_STACK_ALIGN (actual_fsize
);
3940 /* Output any necessary .register pseudo-ops. */
3943 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
3945 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3951 /* Check if %g[2367] were used without
3952 .register being printed for them already. */
3953 for (i
= 2; i
< 8; i
++)
3955 if (df_regs_ever_live_p (i
)
3956 && ! sparc_hard_reg_printed
[i
])
3958 sparc_hard_reg_printed
[i
] = 1;
3959 /* %g7 is used as TLS base register, use #ignore
3960 for it instead of #scratch. */
3961 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
3962 i
== 7 ? "ignore" : "scratch");
3969 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
3970 as needed. LOW should be double-word aligned for 32-bit registers.
3971 Return the new OFFSET. */
3974 #define SORR_RESTORE 1
3977 save_or_restore_regs (int low
, int high
, rtx base
, int offset
, int action
)
3982 if (TARGET_ARCH64
&& high
<= 32)
3984 for (i
= low
; i
< high
; i
++)
3986 if (df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
3988 mem
= gen_rtx_MEM (DImode
, plus_constant (base
, offset
));
3989 set_mem_alias_set (mem
, sparc_sr_alias_set
);
3990 if (action
== SORR_SAVE
)
3992 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
3993 RTX_FRAME_RELATED_P (insn
) = 1;
3995 else /* action == SORR_RESTORE */
3996 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4003 for (i
= low
; i
< high
; i
+= 2)
4005 bool reg0
= df_regs_ever_live_p (i
) && ! call_used_regs
[i
];
4006 bool reg1
= df_regs_ever_live_p (i
+1) && ! call_used_regs
[i
+1];
4007 enum machine_mode mode
;
4012 mode
= i
< 32 ? DImode
: DFmode
;
4017 mode
= i
< 32 ? SImode
: SFmode
;
4022 mode
= i
< 32 ? SImode
: SFmode
;
4029 mem
= gen_rtx_MEM (mode
, plus_constant (base
, offset
));
4030 set_mem_alias_set (mem
, sparc_sr_alias_set
);
4031 if (action
== SORR_SAVE
)
4033 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4034 RTX_FRAME_RELATED_P (insn
) = 1;
4036 else /* action == SORR_RESTORE */
4037 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4039 /* Always preserve double-word alignment. */
4040 offset
= (offset
+ 7) & -8;
4047 /* Emit code to save call-saved registers. */
4050 emit_save_or_restore_regs (int action
)
4052 HOST_WIDE_INT offset
;
4055 offset
= frame_base_offset
- apparent_fsize
;
4057 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4095)
4059 /* ??? This might be optimized a little as %g1 might already have a
4060 value close enough that a single add insn will do. */
4061 /* ??? Although, all of this is probably only a temporary fix
4062 because if %g1 can hold a function result, then
4063 sparc_expand_epilogue will lose (the result will be
4065 base
= gen_rtx_REG (Pmode
, 1);
4066 emit_move_insn (base
, GEN_INT (offset
));
4067 emit_insn (gen_rtx_SET (VOIDmode
,
4069 gen_rtx_PLUS (Pmode
, frame_base_reg
, base
)));
4073 base
= frame_base_reg
;
4075 offset
= save_or_restore_regs (0, 8, base
, offset
, action
);
4076 save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, action
);
4079 /* Generate a save_register_window insn. */
4082 gen_save_register_window (rtx increment
)
4085 return gen_save_register_windowdi (increment
);
4087 return gen_save_register_windowsi (increment
);
4090 /* Generate an increment for the stack pointer. */
4093 gen_stack_pointer_inc (rtx increment
)
4095 return gen_rtx_SET (VOIDmode
,
4097 gen_rtx_PLUS (Pmode
,
4102 /* Generate a decrement for the stack pointer. */
4105 gen_stack_pointer_dec (rtx decrement
)
4107 return gen_rtx_SET (VOIDmode
,
4109 gen_rtx_MINUS (Pmode
,
4114 /* Expand the function prologue. The prologue is responsible for reserving
4115 storage for the frame, saving the call-saved registers and loading the
4116 PIC register if needed. */
4119 sparc_expand_prologue (void)
4124 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4125 on the final value of the flag means deferring the prologue/epilogue
4126 expansion until just before the second scheduling pass, which is too
4127 late to emit multiple epilogues or return insns.
4129 Of course we are making the assumption that the value of the flag
4130 will not change between now and its final value. Of the three parts
4131 of the formula, only the last one can reasonably vary. Let's take a
4132 closer look, after assuming that the first two ones are set to true
4133 (otherwise the last value is effectively silenced).
4135 If only_leaf_regs_used returns false, the global predicate will also
4136 be false so the actual frame size calculated below will be positive.
4137 As a consequence, the save_register_window insn will be emitted in
4138 the instruction stream; now this insn explicitly references %fp
4139 which is not a leaf register so only_leaf_regs_used will always
4140 return false subsequently.
4142 If only_leaf_regs_used returns true, we hope that the subsequent
4143 optimization passes won't cause non-leaf registers to pop up. For
4144 example, the regrename pass has special provisions to not rename to
4145 non-leaf registers in a leaf function. */
4146 sparc_leaf_function_p
4147 = optimize
> 0 && leaf_function_p () && only_leaf_regs_used ();
4149 /* Need to use actual_fsize, since we are also allocating
4150 space for our callee (and our own register save area). */
4152 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4154 /* Advertise that the data calculated just above are now valid. */
4155 sparc_prologue_data_valid_p
= true;
4157 if (sparc_leaf_function_p
)
4159 frame_base_reg
= stack_pointer_rtx
;
4160 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
4164 frame_base_reg
= hard_frame_pointer_rtx
;
4165 frame_base_offset
= SPARC_STACK_BIAS
;
4168 if (actual_fsize
== 0)
4170 else if (sparc_leaf_function_p
)
4172 if (actual_fsize
<= 4096)
4173 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize
)));
4174 else if (actual_fsize
<= 8192)
4176 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4177 /* %sp is still the CFA register. */
4178 RTX_FRAME_RELATED_P (insn
) = 1;
4180 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
4184 rtx reg
= gen_rtx_REG (Pmode
, 1);
4185 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
4186 insn
= emit_insn (gen_stack_pointer_inc (reg
));
4187 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4188 gen_stack_pointer_inc (GEN_INT (-actual_fsize
)));
4191 RTX_FRAME_RELATED_P (insn
) = 1;
4195 if (actual_fsize
<= 4096)
4196 insn
= emit_insn (gen_save_register_window (GEN_INT (-actual_fsize
)));
4197 else if (actual_fsize
<= 8192)
4199 insn
= emit_insn (gen_save_register_window (GEN_INT (-4096)));
4200 /* %sp is not the CFA register anymore. */
4201 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
4205 rtx reg
= gen_rtx_REG (Pmode
, 1);
4206 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
4207 insn
= emit_insn (gen_save_register_window (reg
));
4210 RTX_FRAME_RELATED_P (insn
) = 1;
4211 for (i
=0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
4212 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, i
)) = 1;
4216 emit_save_or_restore_regs (SORR_SAVE
);
4218 /* Load the PIC register if needed. */
4219 if (flag_pic
&& crtl
->uses_pic_offset_table
)
4220 load_pic_register ();
4223 /* This function generates the assembly code for function entry, which boils
4224 down to emitting the necessary .register directives. */
4227 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4229 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4230 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
4232 sparc_output_scratch_registers (file
);
4235 /* Expand the function epilogue, either normal or part of a sibcall.
4236 We emit all the instructions except the return or the call. */
4239 sparc_expand_epilogue (void)
4242 emit_save_or_restore_regs (SORR_RESTORE
);
4244 if (actual_fsize
== 0)
4246 else if (sparc_leaf_function_p
)
4248 if (actual_fsize
<= 4096)
4249 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize
)));
4250 else if (actual_fsize
<= 8192)
4252 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4253 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize
)));
4257 rtx reg
= gen_rtx_REG (Pmode
, 1);
4258 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
4259 emit_insn (gen_stack_pointer_dec (reg
));
4264 /* Return true if it is appropriate to emit `return' instructions in the
4265 body of a function. */
4268 sparc_can_use_return_insn_p (void)
4270 return sparc_prologue_data_valid_p
4271 && (actual_fsize
== 0 || !sparc_leaf_function_p
);
4274 /* This function generates the assembly code for function exit. */
4277 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4279 /* If code does not drop into the epilogue, we have to still output
4280 a dummy nop for the sake of sane backtraces. Otherwise, if the
4281 last two instructions of a function were "call foo; dslot;" this
4282 can make the return PC of foo (i.e. address of call instruction
4283 plus 8) point to the first instruction in the next function. */
4285 rtx insn
, last_real_insn
;
4287 insn
= get_last_insn ();
4289 last_real_insn
= prev_real_insn (insn
);
4291 && GET_CODE (last_real_insn
) == INSN
4292 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
4293 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
4295 if (last_real_insn
&& GET_CODE (last_real_insn
) == CALL_INSN
)
4296 fputs("\tnop\n", file
);
4298 sparc_output_deferred_case_vectors ();
4301 /* Output a 'restore' instruction. */
4304 output_restore (rtx pat
)
4310 fputs ("\t restore\n", asm_out_file
);
4314 gcc_assert (GET_CODE (pat
) == SET
);
4316 operands
[0] = SET_DEST (pat
);
4317 pat
= SET_SRC (pat
);
4319 switch (GET_CODE (pat
))
4322 operands
[1] = XEXP (pat
, 0);
4323 operands
[2] = XEXP (pat
, 1);
4324 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4327 operands
[1] = XEXP (pat
, 0);
4328 operands
[2] = XEXP (pat
, 1);
4329 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4332 operands
[1] = XEXP (pat
, 0);
4333 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
4334 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4338 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4343 /* Output a return. */
4346 output_return (rtx insn
)
4348 if (sparc_leaf_function_p
)
4350 /* This is a leaf function so we don't have to bother restoring the
4351 register window, which frees us from dealing with the convoluted
4352 semantics of restore/return. We simply output the jump to the
4353 return address and the insn in the delay slot (if any). */
4355 gcc_assert (! crtl
->calls_eh_return
);
4357 return "jmp\t%%o7+%)%#";
4361 /* This is a regular function so we have to restore the register window.
4362 We may have a pending insn for the delay slot, which will be either
4363 combined with the 'restore' instruction or put in the delay slot of
4364 the 'return' instruction. */
4366 if (crtl
->calls_eh_return
)
4368 /* If the function uses __builtin_eh_return, the eh_return
4369 machinery occupies the delay slot. */
4370 gcc_assert (! final_sequence
);
4372 if (! flag_delayed_branch
)
4373 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file
);
4376 fputs ("\treturn\t%i7+8\n", asm_out_file
);
4378 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file
);
4380 if (flag_delayed_branch
)
4381 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
4383 fputs ("\t nop\n", asm_out_file
);
4385 else if (final_sequence
)
4389 delay
= NEXT_INSN (insn
);
4392 pat
= PATTERN (delay
);
4394 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
4396 epilogue_renumber (&pat
, 0);
4397 return "return\t%%i7+%)%#";
4401 output_asm_insn ("jmp\t%%i7+%)", NULL
);
4402 output_restore (pat
);
4403 PATTERN (delay
) = gen_blockage ();
4404 INSN_CODE (delay
) = -1;
4409 /* The delay slot is empty. */
4411 return "return\t%%i7+%)\n\t nop";
4412 else if (flag_delayed_branch
)
4413 return "jmp\t%%i7+%)\n\t restore";
4415 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4422 /* Output a sibling call. */
4425 output_sibcall (rtx insn
, rtx call_operand
)
4429 gcc_assert (flag_delayed_branch
);
4431 operands
[0] = call_operand
;
4433 if (sparc_leaf_function_p
)
4435 /* This is a leaf function so we don't have to bother restoring the
4436 register window. We simply output the jump to the function and
4437 the insn in the delay slot (if any). */
4439 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
4442 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4445 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4446 it into branch if possible. */
4447 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4452 /* This is a regular function so we have to restore the register window.
4453 We may have a pending insn for the delay slot, which will be combined
4454 with the 'restore' instruction. */
4456 output_asm_insn ("call\t%a0, 0", operands
);
4460 rtx delay
= NEXT_INSN (insn
);
4463 output_restore (PATTERN (delay
));
4465 PATTERN (delay
) = gen_blockage ();
4466 INSN_CODE (delay
) = -1;
4469 output_restore (NULL_RTX
);
4475 /* Functions for handling argument passing.
4477 For 32-bit, the first 6 args are normally in registers and the rest are
4478 pushed. Any arg that starts within the first 6 words is at least
4479 partially passed in a register unless its data type forbids.
4481 For 64-bit, the argument registers are laid out as an array of 16 elements
4482 and arguments are added sequentially. The first 6 int args and up to the
4483 first 16 fp args (depending on size) are passed in regs.
4485 Slot Stack Integral Float Float in structure Double Long Double
4486 ---- ----- -------- ----- ------------------ ------ -----------
4487 15 [SP+248] %f31 %f30,%f31 %d30
4488 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4489 13 [SP+232] %f27 %f26,%f27 %d26
4490 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4491 11 [SP+216] %f23 %f22,%f23 %d22
4492 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4493 9 [SP+200] %f19 %f18,%f19 %d18
4494 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4495 7 [SP+184] %f15 %f14,%f15 %d14
4496 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4497 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4498 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4499 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4500 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4501 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4502 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4504 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4506 Integral arguments are always passed as 64-bit quantities appropriately
4509 Passing of floating point values is handled as follows.
4510 If a prototype is in scope:
4511 If the value is in a named argument (i.e. not a stdarg function or a
4512 value not part of the `...') then the value is passed in the appropriate
4514 If the value is part of the `...' and is passed in one of the first 6
4515 slots then the value is passed in the appropriate int reg.
4516 If the value is part of the `...' and is not passed in one of the first 6
4517 slots then the value is passed in memory.
4518 If a prototype is not in scope:
4519 If the value is one of the first 6 arguments the value is passed in the
4520 appropriate integer reg and the appropriate fp reg.
4521 If the value is not one of the first 6 arguments the value is passed in
4522 the appropriate fp reg and in memory.
4525 Summary of the calling conventions implemented by GCC on the SPARC:
4528 size argument return value
4530 small integer <4 int. reg. int. reg.
4531 word 4 int. reg. int. reg.
4532 double word 8 int. reg. int. reg.
4534 _Complex small integer <8 int. reg. int. reg.
4535 _Complex word 8 int. reg. int. reg.
4536 _Complex double word 16 memory int. reg.
4538 vector integer <=8 int. reg. FP reg.
4539 vector integer >8 memory memory
4541 float 4 int. reg. FP reg.
4542 double 8 int. reg. FP reg.
4543 long double 16 memory memory
4545 _Complex float 8 memory FP reg.
4546 _Complex double 16 memory FP reg.
4547 _Complex long double 32 memory FP reg.
4549 vector float any memory memory
4551 aggregate any memory memory
4556 size argument return value
4558 small integer <8 int. reg. int. reg.
4559 word 8 int. reg. int. reg.
4560 double word 16 int. reg. int. reg.
4562 _Complex small integer <16 int. reg. int. reg.
4563 _Complex word 16 int. reg. int. reg.
4564 _Complex double word 32 memory int. reg.
4566 vector integer <=16 FP reg. FP reg.
4567 vector integer 16<s<=32 memory FP reg.
4568 vector integer >32 memory memory
4570 float 4 FP reg. FP reg.
4571 double 8 FP reg. FP reg.
4572 long double 16 FP reg. FP reg.
4574 _Complex float 8 FP reg. FP reg.
4575 _Complex double 16 FP reg. FP reg.
4576 _Complex long double 32 memory FP reg.
4578 vector float <=16 FP reg. FP reg.
4579 vector float 16<s<=32 memory FP reg.
4580 vector float >32 memory memory
4582 aggregate <=16 reg. reg.
4583 aggregate 16<s<=32 memory reg.
4584 aggregate >32 memory memory
4588 Note #1: complex floating-point types follow the extended SPARC ABIs as
4589 implemented by the Sun compiler.
4591 Note #2: integral vector types follow the scalar floating-point types
4592 conventions to match what is implemented by the Sun VIS SDK.
4594 Note #3: floating-point vector types follow the aggregate types
4598 /* Maximum number of int regs for args. */
4599 #define SPARC_INT_ARG_MAX 6
4600 /* Maximum number of fp regs for args. */
4601 #define SPARC_FP_ARG_MAX 16
4603 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4605 /* Handle the INIT_CUMULATIVE_ARGS macro.
4606 Initialize a variable CUM of type CUMULATIVE_ARGS
4607 for a call to a function whose data type is FNTYPE.
4608 For a library call, FNTYPE is 0. */
4611 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
4612 rtx libname ATTRIBUTE_UNUSED
,
4613 tree fndecl ATTRIBUTE_UNUSED
)
4616 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4617 cum
->libcall_p
= fntype
== 0;
4620 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4621 When a prototype says `char' or `short', really pass an `int'. */
4624 sparc_promote_prototypes (const_tree fntype ATTRIBUTE_UNUSED
)
4626 return TARGET_ARCH32
? true : false;
4629 /* Handle promotion of pointer and integer arguments. */
4631 static enum machine_mode
4632 sparc_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4633 enum machine_mode mode
,
4634 int *punsignedp ATTRIBUTE_UNUSED
,
4635 const_tree fntype ATTRIBUTE_UNUSED
,
4636 int for_return ATTRIBUTE_UNUSED
)
4638 if (POINTER_TYPE_P (type
))
4640 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
4644 /* For TARGET_ARCH64 we need this, as we don't have instructions
4645 for arithmetic operations which do zero/sign extension at the same time,
4646 so without this we end up with a srl/sra after every assignment to an
4647 user variable, which means very very bad code. */
4649 && GET_MODE_CLASS (mode
) == MODE_INT
4650 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
4656 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4659 sparc_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4661 return TARGET_ARCH64
? true : false;
4664 /* Scan the record type TYPE and return the following predicates:
4665 - INTREGS_P: the record contains at least one field or sub-field
4666 that is eligible for promotion in integer registers.
4667 - FP_REGS_P: the record contains at least one field or sub-field
4668 that is eligible for promotion in floating-point registers.
4669 - PACKED_P: the record contains at least one field that is packed.
4671 Sub-fields are not taken into account for the PACKED_P predicate. */
4674 scan_record_type (tree type
, int *intregs_p
, int *fpregs_p
, int *packed_p
)
4678 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4680 if (TREE_CODE (field
) == FIELD_DECL
)
4682 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4683 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
4684 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4685 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4691 if (packed_p
&& DECL_PACKED (field
))
4697 /* Compute the slot number to pass an argument in.
4698 Return the slot number or -1 if passing on the stack.
4700 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4701 the preceding args and about the function being called.
4702 MODE is the argument's machine mode.
4703 TYPE is the data type of the argument (as a tree).
4704 This is null for libcalls where that information may
4706 NAMED is nonzero if this argument is a named parameter
4707 (otherwise it is an extra parameter matching an ellipsis).
4708 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4709 *PREGNO records the register number to use if scalar type.
4710 *PPADDING records the amount of padding needed in words. */
4713 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
4714 tree type
, int named
, int incoming_p
,
4715 int *pregno
, int *ppadding
)
4717 int regbase
= (incoming_p
4718 ? SPARC_INCOMING_INT_ARG_FIRST
4719 : SPARC_OUTGOING_INT_ARG_FIRST
);
4720 int slotno
= cum
->words
;
4721 enum mode_class mclass
;
4726 if (type
&& TREE_ADDRESSABLE (type
))
4732 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4735 /* For SPARC64, objects requiring 16-byte alignment get it. */
4737 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
4738 && (slotno
& 1) != 0)
4739 slotno
++, *ppadding
= 1;
4741 mclass
= GET_MODE_CLASS (mode
);
4742 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
4744 /* Vector types deserve special treatment because they are
4745 polymorphic wrt their mode, depending upon whether VIS
4746 instructions are enabled. */
4747 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
4749 /* The SPARC port defines no floating-point vector modes. */
4750 gcc_assert (mode
== BLKmode
);
4754 /* Integral vector types should either have a vector
4755 mode or an integral mode, because we are guaranteed
4756 by pass_by_reference that their size is not greater
4757 than 16 bytes and TImode is 16-byte wide. */
4758 gcc_assert (mode
!= BLKmode
);
4760 /* Vector integers are handled like floats according to
4762 mclass
= MODE_FLOAT
;
4769 case MODE_COMPLEX_FLOAT
:
4770 case MODE_VECTOR_INT
:
4771 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
4773 if (slotno
>= SPARC_FP_ARG_MAX
)
4775 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
4776 /* Arguments filling only one single FP register are
4777 right-justified in the outer double FP register. */
4778 if (GET_MODE_SIZE (mode
) <= 4)
4785 case MODE_COMPLEX_INT
:
4786 if (slotno
>= SPARC_INT_ARG_MAX
)
4788 regno
= regbase
+ slotno
;
4792 if (mode
== VOIDmode
)
4793 /* MODE is VOIDmode when generating the actual call. */
4796 gcc_assert (mode
== BLKmode
);
4800 || (TREE_CODE (type
) != VECTOR_TYPE
4801 && TREE_CODE (type
) != RECORD_TYPE
))
4803 if (slotno
>= SPARC_INT_ARG_MAX
)
4805 regno
= regbase
+ slotno
;
4807 else /* TARGET_ARCH64 && type */
4809 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
4811 /* First see what kinds of registers we would need. */
4812 if (TREE_CODE (type
) == VECTOR_TYPE
)
4815 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
4817 /* The ABI obviously doesn't specify how packed structures
4818 are passed. These are defined to be passed in int regs
4819 if possible, otherwise memory. */
4820 if (packed_p
|| !named
)
4821 fpregs_p
= 0, intregs_p
= 1;
4823 /* If all arg slots are filled, then must pass on stack. */
4824 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4827 /* If there are only int args and all int arg slots are filled,
4828 then must pass on stack. */
4829 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4832 /* Note that even if all int arg slots are filled, fp members may
4833 still be passed in regs if such regs are available.
4834 *PREGNO isn't set because there may be more than one, it's up
4835 to the caller to compute them. */
4848 /* Handle recursive register counting for structure field layout. */
4850 struct function_arg_record_value_parms
4852 rtx ret
; /* return expression being built. */
4853 int slotno
; /* slot number of the argument. */
4854 int named
; /* whether the argument is named. */
4855 int regbase
; /* regno of the base register. */
4856 int stack
; /* 1 if part of the argument is on the stack. */
4857 int intoffset
; /* offset of the first pending integer field. */
4858 unsigned int nregs
; /* number of words passed in registers. */
4861 static void function_arg_record_value_3
4862 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
4863 static void function_arg_record_value_2
4864 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
4865 static void function_arg_record_value_1
4866 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
4867 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
4868 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
4870 /* A subroutine of function_arg_record_value. Traverse the structure
4871 recursively and determine how many registers will be required. */
4874 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
4875 struct function_arg_record_value_parms
*parms
,
4880 /* We need to compute how many registers are needed so we can
4881 allocate the PARALLEL but before we can do that we need to know
4882 whether there are any packed fields. The ABI obviously doesn't
4883 specify how structures are passed in this case, so they are
4884 defined to be passed in int regs if possible, otherwise memory,
4885 regardless of whether there are fp values present. */
4888 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4890 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4897 /* Compute how many registers we need. */
4898 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4900 if (TREE_CODE (field
) == FIELD_DECL
)
4902 HOST_WIDE_INT bitpos
= startbitpos
;
4904 if (DECL_SIZE (field
) != 0)
4906 if (integer_zerop (DECL_SIZE (field
)))
4909 if (host_integerp (bit_position (field
), 1))
4910 bitpos
+= int_bit_position (field
);
4913 /* ??? FIXME: else assume zero offset. */
4915 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4916 function_arg_record_value_1 (TREE_TYPE (field
),
4920 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4921 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4926 if (parms
->intoffset
!= -1)
4928 unsigned int startbit
, endbit
;
4929 int intslots
, this_slotno
;
4931 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
4932 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4934 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4935 this_slotno
= parms
->slotno
+ parms
->intoffset
4938 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
4940 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
4941 /* We need to pass this field on the stack. */
4945 parms
->nregs
+= intslots
;
4946 parms
->intoffset
= -1;
4949 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4950 If it wasn't true we wouldn't be here. */
4951 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
4952 && DECL_MODE (field
) == BLKmode
)
4953 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
4954 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4961 if (parms
->intoffset
== -1)
4962 parms
->intoffset
= bitpos
;
4968 /* A subroutine of function_arg_record_value. Assign the bits of the
4969 structure between parms->intoffset and bitpos to integer registers. */
4972 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
4973 struct function_arg_record_value_parms
*parms
)
4975 enum machine_mode mode
;
4977 unsigned int startbit
, endbit
;
4978 int this_slotno
, intslots
, intoffset
;
4981 if (parms
->intoffset
== -1)
4984 intoffset
= parms
->intoffset
;
4985 parms
->intoffset
= -1;
4987 startbit
= intoffset
& -BITS_PER_WORD
;
4988 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4989 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4990 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4992 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4996 /* If this is the trailing part of a word, only load that much into
4997 the register. Otherwise load the whole register. Note that in
4998 the latter case we may pick up unwanted bits. It's not a problem
4999 at the moment but may wish to revisit. */
5001 if (intoffset
% BITS_PER_WORD
!= 0)
5002 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5007 intoffset
/= BITS_PER_UNIT
;
5010 regno
= parms
->regbase
+ this_slotno
;
5011 reg
= gen_rtx_REG (mode
, regno
);
5012 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5013 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5016 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5021 while (intslots
> 0);
5024 /* A subroutine of function_arg_record_value. Traverse the structure
5025 recursively and assign bits to floating point registers. Track which
5026 bits in between need integer registers; invoke function_arg_record_value_3
5027 to make that happen. */
5030 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5031 struct function_arg_record_value_parms
*parms
,
5037 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5039 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5046 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5048 if (TREE_CODE (field
) == FIELD_DECL
)
5050 HOST_WIDE_INT bitpos
= startbitpos
;
5052 if (DECL_SIZE (field
) != 0)
5054 if (integer_zerop (DECL_SIZE (field
)))
5057 if (host_integerp (bit_position (field
), 1))
5058 bitpos
+= int_bit_position (field
);
5061 /* ??? FIXME: else assume zero offset. */
5063 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5064 function_arg_record_value_2 (TREE_TYPE (field
),
5068 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5069 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5074 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5075 int regno
, nregs
, pos
;
5076 enum machine_mode mode
= DECL_MODE (field
);
5079 function_arg_record_value_3 (bitpos
, parms
);
5081 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5084 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5085 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5087 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5089 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5095 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5096 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5098 reg
= gen_rtx_REG (mode
, regno
);
5099 pos
= bitpos
/ BITS_PER_UNIT
;
5100 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5101 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5105 regno
+= GET_MODE_SIZE (mode
) / 4;
5106 reg
= gen_rtx_REG (mode
, regno
);
5107 pos
+= GET_MODE_SIZE (mode
);
5108 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5109 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5115 if (parms
->intoffset
== -1)
5116 parms
->intoffset
= bitpos
;
5122 /* Used by function_arg and function_value to implement the complex
5123 conventions of the 64-bit ABI for passing and returning structures.
5124 Return an expression valid as a return value for the two macros
5125 FUNCTION_ARG and FUNCTION_VALUE.
5127 TYPE is the data type of the argument (as a tree).
5128 This is null for libcalls where that information may
5130 MODE is the argument's machine mode.
5131 SLOTNO is the index number of the argument's slot in the parameter array.
5132 NAMED is nonzero if this argument is a named parameter
5133 (otherwise it is an extra parameter matching an ellipsis).
5134 REGBASE is the regno of the base register for the parameter array. */
5137 function_arg_record_value (const_tree type
, enum machine_mode mode
,
5138 int slotno
, int named
, int regbase
)
5140 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5141 struct function_arg_record_value_parms parms
;
5144 parms
.ret
= NULL_RTX
;
5145 parms
.slotno
= slotno
;
5146 parms
.named
= named
;
5147 parms
.regbase
= regbase
;
5150 /* Compute how many registers we need. */
5152 parms
.intoffset
= 0;
5153 function_arg_record_value_1 (type
, 0, &parms
, false);
5155 /* Take into account pending integer fields. */
5156 if (parms
.intoffset
!= -1)
5158 unsigned int startbit
, endbit
;
5159 int intslots
, this_slotno
;
5161 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5162 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5163 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5164 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5166 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5168 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5169 /* We need to pass this field on the stack. */
5173 parms
.nregs
+= intslots
;
5175 nregs
= parms
.nregs
;
5177 /* Allocate the vector and handle some annoying special cases. */
5180 /* ??? Empty structure has no value? Duh? */
5183 /* Though there's nothing really to store, return a word register
5184 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5185 leads to breakage due to the fact that there are zero bytes to
5187 return gen_rtx_REG (mode
, regbase
);
5191 /* ??? C++ has structures with no fields, and yet a size. Give up
5192 for now and pass everything back in integer registers. */
5193 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5195 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5196 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5198 gcc_assert (nregs
!= 0);
5200 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
5202 /* If at least one field must be passed on the stack, generate
5203 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5204 also be passed on the stack. We can't do much better because the
5205 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5206 of structures for which the fields passed exclusively in registers
5207 are not at the beginning of the structure. */
5209 XVECEXP (parms
.ret
, 0, 0)
5210 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5212 /* Fill in the entries. */
5214 parms
.intoffset
= 0;
5215 function_arg_record_value_2 (type
, 0, &parms
, false);
5216 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
5218 gcc_assert (parms
.nregs
== nregs
);
5223 /* Used by function_arg and function_value to implement the conventions
5224 of the 64-bit ABI for passing and returning unions.
5225 Return an expression valid as a return value for the two macros
5226 FUNCTION_ARG and FUNCTION_VALUE.
5228 SIZE is the size in bytes of the union.
5229 MODE is the argument's machine mode.
5230 REGNO is the hard register the union will be passed in. */
5233 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
5236 int nwords
= ROUND_ADVANCE (size
), i
;
5239 /* See comment in previous function for empty structures. */
5241 return gen_rtx_REG (mode
, regno
);
5243 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5246 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
5248 for (i
= 0; i
< nwords
; i
++)
5250 /* Unions are passed left-justified. */
5251 XVECEXP (regs
, 0, i
)
5252 = gen_rtx_EXPR_LIST (VOIDmode
,
5253 gen_rtx_REG (word_mode
, regno
),
5254 GEN_INT (UNITS_PER_WORD
* i
));
5261 /* Used by function_arg and function_value to implement the conventions
5262 for passing and returning large (BLKmode) vectors.
5263 Return an expression valid as a return value for the two macros
5264 FUNCTION_ARG and FUNCTION_VALUE.
5266 SIZE is the size in bytes of the vector (at least 8 bytes).
5267 REGNO is the FP hard register the vector will be passed in. */
5270 function_arg_vector_value (int size
, int regno
)
5272 int i
, nregs
= size
/ 8;
5275 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
5277 for (i
= 0; i
< nregs
; i
++)
5279 XVECEXP (regs
, 0, i
)
5280 = gen_rtx_EXPR_LIST (VOIDmode
,
5281 gen_rtx_REG (DImode
, regno
+ 2*i
),
5288 /* Handle the FUNCTION_ARG macro.
5289 Determine where to put an argument to a function.
5290 Value is zero to push the argument on the stack,
5291 or a hard register in which to store the argument.
5293 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5294 the preceding args and about the function being called.
5295 MODE is the argument's machine mode.
5296 TYPE is the data type of the argument (as a tree).
5297 This is null for libcalls where that information may
5299 NAMED is nonzero if this argument is a named parameter
5300 (otherwise it is an extra parameter matching an ellipsis).
5301 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5304 function_arg (const struct sparc_args
*cum
, enum machine_mode mode
,
5305 tree type
, int named
, int incoming_p
)
5307 int regbase
= (incoming_p
5308 ? SPARC_INCOMING_INT_ARG_FIRST
5309 : SPARC_OUTGOING_INT_ARG_FIRST
);
5310 int slotno
, regno
, padding
;
5311 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5313 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
5318 /* Vector types deserve special treatment because they are polymorphic wrt
5319 their mode, depending upon whether VIS instructions are enabled. */
5320 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5322 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5323 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
5324 || (TARGET_ARCH64
&& size
<= 16));
5326 if (mode
== BLKmode
)
5327 return function_arg_vector_value (size
,
5328 SPARC_FP_ARG_FIRST
+ 2*slotno
);
5330 mclass
= MODE_FLOAT
;
5334 return gen_rtx_REG (mode
, regno
);
5336 /* Structures up to 16 bytes in size are passed in arg slots on the stack
5337 and are promoted to registers if possible. */
5338 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
5340 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5341 gcc_assert (size
<= 16);
5343 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
5346 /* Unions up to 16 bytes in size are passed in integer registers. */
5347 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
5349 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5350 gcc_assert (size
<= 16);
5352 return function_arg_union_value (size
, mode
, slotno
, regno
);
5355 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5356 but also have the slot allocated for them.
5357 If no prototype is in scope fp values in register slots get passed
5358 in two places, either fp regs and int regs or fp regs and memory. */
5359 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5360 && SPARC_FP_REG_P (regno
))
5362 rtx reg
= gen_rtx_REG (mode
, regno
);
5363 if (cum
->prototype_p
|| cum
->libcall_p
)
5365 /* "* 2" because fp reg numbers are recorded in 4 byte
5368 /* ??? This will cause the value to be passed in the fp reg and
5369 in the stack. When a prototype exists we want to pass the
5370 value in the reg but reserve space on the stack. That's an
5371 optimization, and is deferred [for a bit]. */
5372 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
5373 return gen_rtx_PARALLEL (mode
,
5375 gen_rtx_EXPR_LIST (VOIDmode
,
5376 NULL_RTX
, const0_rtx
),
5377 gen_rtx_EXPR_LIST (VOIDmode
,
5381 /* ??? It seems that passing back a register even when past
5382 the area declared by REG_PARM_STACK_SPACE will allocate
5383 space appropriately, and will not copy the data onto the
5384 stack, exactly as we desire.
5386 This is due to locate_and_pad_parm being called in
5387 expand_call whenever reg_parm_stack_space > 0, which
5388 while beneficial to our example here, would seem to be
5389 in error from what had been intended. Ho hum... -- r~ */
5397 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
5401 /* On incoming, we don't need to know that the value
5402 is passed in %f0 and %i0, and it confuses other parts
5403 causing needless spillage even on the simplest cases. */
5407 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
5408 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
5410 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5411 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
5413 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5417 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5418 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5419 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5424 /* All other aggregate types are passed in an integer register in a mode
5425 corresponding to the size of the type. */
5426 else if (type
&& AGGREGATE_TYPE_P (type
))
5428 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5429 gcc_assert (size
<= 16);
5431 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5434 return gen_rtx_REG (mode
, regno
);
5437 /* For an arg passed partly in registers and partly in memory,
5438 this is the number of bytes of registers used.
5439 For args passed entirely in registers or entirely in memory, zero.
5441 Any arg that starts in the first 6 regs but won't entirely fit in them
5442 needs partial registers on v8. On v9, structures with integer
5443 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5444 values that begin in the last fp reg [where "last fp reg" varies with the
5445 mode] will be split between that reg and memory. */
5448 sparc_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5449 tree type
, bool named
)
5451 int slotno
, regno
, padding
;
5453 /* We pass 0 for incoming_p here, it doesn't matter. */
5454 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5461 if ((slotno
+ (mode
== BLKmode
5462 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5463 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5464 > SPARC_INT_ARG_MAX
)
5465 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
5469 /* We are guaranteed by pass_by_reference that the size of the
5470 argument is not greater than 16 bytes, so we only need to return
5471 one word if the argument is partially passed in registers. */
5473 if (type
&& AGGREGATE_TYPE_P (type
))
5475 int size
= int_size_in_bytes (type
);
5477 if (size
> UNITS_PER_WORD
5478 && slotno
== SPARC_INT_ARG_MAX
- 1)
5479 return UNITS_PER_WORD
;
5481 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5482 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5483 && ! (TARGET_FPU
&& named
)))
5485 /* The complex types are passed as packed types. */
5486 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
5487 && slotno
== SPARC_INT_ARG_MAX
- 1)
5488 return UNITS_PER_WORD
;
5490 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5492 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5494 return UNITS_PER_WORD
;
5501 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5502 Specify whether to pass the argument by reference. */
5505 sparc_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5506 enum machine_mode mode
, const_tree type
,
5507 bool named ATTRIBUTE_UNUSED
)
5510 /* Original SPARC 32-bit ABI says that structures and unions,
5511 and quad-precision floats are passed by reference. For Pascal,
5512 also pass arrays by reference. All other base types are passed
5515 Extended ABI (as implemented by the Sun compiler) says that all
5516 complex floats are passed by reference. Pass complex integers
5517 in registers up to 8 bytes. More generally, enforce the 2-word
5518 cap for passing arguments in registers.
5520 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5521 integers are passed like floats of the same size, that is in
5522 registers up to 8 bytes. Pass all vector floats by reference
5523 like structure and unions. */
5524 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
5526 /* Catch CDImode, TFmode, DCmode and TCmode. */
5527 || GET_MODE_SIZE (mode
) > 8
5529 && TREE_CODE (type
) == VECTOR_TYPE
5530 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
5532 /* Original SPARC 64-bit ABI says that structures and unions
5533 smaller than 16 bytes are passed in registers, as well as
5534 all other base types.
5536 Extended ABI (as implemented by the Sun compiler) says that
5537 complex floats are passed in registers up to 16 bytes. Pass
5538 all complex integers in registers up to 16 bytes. More generally,
5539 enforce the 2-word cap for passing arguments in registers.
5541 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5542 integers are passed like floats of the same size, that is in
5543 registers (up to 16 bytes). Pass all vector floats like structure
5546 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
5547 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
5548 /* Catch CTImode and TCmode. */
5549 || GET_MODE_SIZE (mode
) > 16);
5552 /* Handle the FUNCTION_ARG_ADVANCE macro.
5553 Update the data in CUM to advance over an argument
5554 of mode MODE and data type TYPE.
5555 TYPE is null for libcalls where that information may not be available. */
5558 function_arg_advance (struct sparc_args
*cum
, enum machine_mode mode
,
5559 tree type
, int named
)
5561 int slotno
, regno
, padding
;
5563 /* We pass 0 for incoming_p here, it doesn't matter. */
5564 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5566 /* If register required leading padding, add it. */
5568 cum
->words
+= padding
;
5572 cum
->words
+= (mode
!= BLKmode
5573 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5574 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5578 if (type
&& AGGREGATE_TYPE_P (type
))
5580 int size
= int_size_in_bytes (type
);
5584 else if (size
<= 16)
5586 else /* passed by reference */
5591 cum
->words
+= (mode
!= BLKmode
5592 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5593 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5598 /* Handle the FUNCTION_ARG_PADDING macro.
5599 For the 64 bit ABI structs are always stored left shifted in their
5603 function_arg_padding (enum machine_mode mode
, const_tree type
)
5605 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5608 /* Fall back to the default. */
5609 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5612 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5613 Specify whether to return the return value in memory. */
5616 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5619 /* Original SPARC 32-bit ABI says that structures and unions,
5620 and quad-precision floats are returned in memory. All other
5621 base types are returned in registers.
5623 Extended ABI (as implemented by the Sun compiler) says that
5624 all complex floats are returned in registers (8 FP registers
5625 at most for '_Complex long double'). Return all complex integers
5626 in registers (4 at most for '_Complex long long').
5628 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5629 integers are returned like floats of the same size, that is in
5630 registers up to 8 bytes and in memory otherwise. Return all
5631 vector floats in memory like structure and unions; note that
5632 they always have BLKmode like the latter. */
5633 return (TYPE_MODE (type
) == BLKmode
5634 || TYPE_MODE (type
) == TFmode
5635 || (TREE_CODE (type
) == VECTOR_TYPE
5636 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
5638 /* Original SPARC 64-bit ABI says that structures and unions
5639 smaller than 32 bytes are returned in registers, as well as
5640 all other base types.
5642 Extended ABI (as implemented by the Sun compiler) says that all
5643 complex floats are returned in registers (8 FP registers at most
5644 for '_Complex long double'). Return all complex integers in
5645 registers (4 at most for '_Complex TItype').
5647 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5648 integers are returned like floats of the same size, that is in
5649 registers. Return all vector floats like structure and unions;
5650 note that they always have BLKmode like the latter. */
5651 return ((TYPE_MODE (type
) == BLKmode
5652 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32));
5655 /* Handle the TARGET_STRUCT_VALUE target hook.
5656 Return where to find the structure return value address. */
5659 sparc_struct_value_rtx (tree fndecl
, int incoming
)
5668 mem
= gen_rtx_MEM (Pmode
, plus_constant (frame_pointer_rtx
,
5669 STRUCT_VALUE_OFFSET
));
5671 mem
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
,
5672 STRUCT_VALUE_OFFSET
));
5674 /* Only follow the SPARC ABI for fixed-size structure returns.
5675 Variable size structure returns are handled per the normal
5676 procedures in GCC. This is enabled by -mstd-struct-return */
5678 && sparc_std_struct_return
5679 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
5680 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
5682 /* We must check and adjust the return address, as it is
5683 optional as to whether the return object is really
5685 rtx ret_rtx
= gen_rtx_REG (Pmode
, 31);
5686 rtx scratch
= gen_reg_rtx (SImode
);
5687 rtx endlab
= gen_label_rtx ();
5689 /* Calculate the return object size */
5690 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
5691 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
5692 /* Construct a temporary return value */
5693 rtx temp_val
= assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
5695 /* Implement SPARC 32-bit psABI callee returns struck checking
5698 Fetch the instruction where we will return to and see if
5699 it's an unimp instruction (the most significant 10 bits
5701 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
5702 plus_constant (ret_rtx
, 8)));
5703 /* Assume the size is valid and pre-adjust */
5704 emit_insn (gen_add3_insn (ret_rtx
, ret_rtx
, GEN_INT (4)));
5705 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
, 0, endlab
);
5706 emit_insn (gen_sub3_insn (ret_rtx
, ret_rtx
, GEN_INT (4)));
5707 /* Assign stack temp:
5708 Write the address of the memory pointed to by temp_val into
5709 the memory pointed to by mem */
5710 emit_move_insn (mem
, XEXP (temp_val
, 0));
5711 emit_label (endlab
);
5714 set_mem_alias_set (mem
, struct_value_alias_set
);
5719 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5720 For v9, function return values are subject to the same rules as arguments,
5721 except that up to 32 bytes may be returned in registers. */
5724 function_value (const_tree type
, enum machine_mode mode
, int incoming_p
)
5726 /* Beware that the two values are swapped here wrt function_arg. */
5727 int regbase
= (incoming_p
5728 ? SPARC_OUTGOING_INT_ARG_FIRST
5729 : SPARC_INCOMING_INT_ARG_FIRST
);
5730 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5733 /* Vector types deserve special treatment because they are polymorphic wrt
5734 their mode, depending upon whether VIS instructions are enabled. */
5735 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5737 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5738 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
5739 || (TARGET_ARCH64
&& size
<= 32));
5741 if (mode
== BLKmode
)
5742 return function_arg_vector_value (size
,
5743 SPARC_FP_ARG_FIRST
);
5745 mclass
= MODE_FLOAT
;
5748 if (TARGET_ARCH64
&& type
)
5750 /* Structures up to 32 bytes in size are returned in registers. */
5751 if (TREE_CODE (type
) == RECORD_TYPE
)
5753 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5754 gcc_assert (size
<= 32);
5756 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5759 /* Unions up to 32 bytes in size are returned in integer registers. */
5760 else if (TREE_CODE (type
) == UNION_TYPE
)
5762 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5763 gcc_assert (size
<= 32);
5765 return function_arg_union_value (size
, mode
, 0, regbase
);
5768 /* Objects that require it are returned in FP registers. */
5769 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5772 /* All other aggregate types are returned in an integer register in a
5773 mode corresponding to the size of the type. */
5774 else if (AGGREGATE_TYPE_P (type
))
5776 /* All other aggregate types are passed in an integer register
5777 in a mode corresponding to the size of the type. */
5778 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5779 gcc_assert (size
<= 32);
5781 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5783 /* ??? We probably should have made the same ABI change in
5784 3.4.0 as the one we made for unions. The latter was
5785 required by the SCD though, while the former is not
5786 specified, so we favored compatibility and efficiency.
5788 Now we're stuck for aggregates larger than 16 bytes,
5789 because OImode vanished in the meantime. Let's not
5790 try to be unduly clever, and simply follow the ABI
5791 for unions in that case. */
5792 if (mode
== BLKmode
)
5793 return function_arg_union_value (size
, mode
, 0, regbase
);
5798 /* This must match sparc_promote_function_mode.
5799 ??? Maybe 32-bit pointers should actually remain in Pmode? */
5800 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5804 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
5805 regno
= SPARC_FP_ARG_FIRST
;
5809 return gen_rtx_REG (mode
, regno
);
5812 /* Do what is necessary for `va_start'. We look at the current function
5813 to determine if stdarg or varargs is used and return the address of
5814 the first unnamed parameter. */
5817 sparc_builtin_saveregs (void)
5819 int first_reg
= crtl
->args
.info
.words
;
5823 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
5824 emit_move_insn (gen_rtx_MEM (word_mode
,
5825 gen_rtx_PLUS (Pmode
,
5827 GEN_INT (FIRST_PARM_OFFSET (0)
5830 gen_rtx_REG (word_mode
,
5831 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
5833 address
= gen_rtx_PLUS (Pmode
,
5835 GEN_INT (FIRST_PARM_OFFSET (0)
5836 + UNITS_PER_WORD
* first_reg
));
5841 /* Implement `va_start' for stdarg. */
5844 sparc_va_start (tree valist
, rtx nextarg
)
5846 nextarg
= expand_builtin_saveregs ();
5847 std_expand_builtin_va_start (valist
, nextarg
);
5850 /* Implement `va_arg' for stdarg. */
5853 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
5856 HOST_WIDE_INT size
, rsize
, align
;
5859 tree ptrtype
= build_pointer_type (type
);
5861 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5864 size
= rsize
= UNITS_PER_WORD
;
5870 size
= int_size_in_bytes (type
);
5871 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5876 /* For SPARC64, objects requiring 16-byte alignment get it. */
5877 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5878 align
= 2 * UNITS_PER_WORD
;
5880 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5881 are left-justified in their slots. */
5882 if (AGGREGATE_TYPE_P (type
))
5885 size
= rsize
= UNITS_PER_WORD
;
5895 incr
= fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, incr
,
5896 size_int (align
- 1));
5897 incr
= fold_convert (sizetype
, incr
);
5898 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
5900 incr
= fold_convert (ptr_type_node
, incr
);
5903 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5906 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5907 addr
= fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, incr
,
5908 size_int (rsize
- size
));
5912 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
5913 addr
= build_va_arg_indirect_ref (addr
);
5916 /* If the address isn't aligned properly for the type, we need a temporary.
5917 FIXME: This is inefficient, usually we can do this in registers. */
5918 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
5920 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
5921 tree dest_addr
= build_fold_addr_expr (tmp
);
5922 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
5923 3, dest_addr
, addr
, size_int (rsize
));
5924 TREE_ADDRESSABLE (tmp
) = 1;
5925 gimplify_and_add (copy
, pre_p
);
5930 addr
= fold_convert (ptrtype
, addr
);
5933 = fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, incr
, size_int (rsize
));
5934 gimplify_assign (valist
, incr
, post_p
);
5936 return build_va_arg_indirect_ref (addr
);
5939 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
5940 Specify whether the vector mode is supported by the hardware. */
5943 sparc_vector_mode_supported_p (enum machine_mode mode
)
5945 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
5948 /* Return the string to output an unconditional branch to LABEL, which is
5949 the operand number of the label.
5951 DEST is the destination insn (i.e. the label), INSN is the source. */
5954 output_ubranch (rtx dest
, int label
, rtx insn
)
5956 static char string
[64];
5957 bool v9_form
= false;
5960 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
5962 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5963 - INSN_ADDRESSES (INSN_UID (insn
)));
5964 /* Leave some instructions for "slop". */
5965 if (delta
>= -260000 && delta
< 260000)
5970 strcpy (string
, "ba%*,pt\t%%xcc, ");
5972 strcpy (string
, "b%*\t");
5974 p
= strchr (string
, '\0');
5985 /* Return the string to output a conditional branch to LABEL, which is
5986 the operand number of the label. OP is the conditional expression.
5987 XEXP (OP, 0) is assumed to be a condition code register (integer or
5988 floating point) and its mode specifies what kind of comparison we made.
5990 DEST is the destination insn (i.e. the label), INSN is the source.
5992 REVERSED is nonzero if we should reverse the sense of the comparison.
5994 ANNUL is nonzero if we should generate an annulling branch. */
5997 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6000 static char string
[64];
6001 enum rtx_code code
= GET_CODE (op
);
6002 rtx cc_reg
= XEXP (op
, 0);
6003 enum machine_mode mode
= GET_MODE (cc_reg
);
6004 const char *labelno
, *branch
;
6005 int spaces
= 8, far
;
6008 /* v9 branches are limited to +-1MB. If it is too far away,
6021 fbne,a,pn %fcc2, .LC29
6029 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6032 /* Reversal of FP compares takes care -- an ordered compare
6033 becomes an unordered compare and vice versa. */
6034 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6035 code
= reverse_condition_maybe_unordered (code
);
6037 code
= reverse_condition (code
);
6040 /* Start by writing the branch condition. */
6041 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6092 /* ??? !v9: FP branches cannot be preceded by another floating point
6093 insn. Because there is currently no concept of pre-delay slots,
6094 we can fix this only by always emitting a nop before a floating
6099 strcpy (string
, "nop\n\t");
6100 strcat (string
, branch
);
6113 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6125 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6146 strcpy (string
, branch
);
6148 spaces
-= strlen (branch
);
6149 p
= strchr (string
, '\0');
6151 /* Now add the annulling, the label, and a possible noop. */
6164 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
6166 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6167 - INSN_ADDRESSES (INSN_UID (insn
)));
6168 /* Leave some instructions for "slop". */
6169 if (delta
< -260000 || delta
>= 260000)
6173 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6175 static char v9_fcc_labelno
[] = "%%fccX, ";
6176 /* Set the char indicating the number of the fcc reg to use. */
6177 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
6178 labelno
= v9_fcc_labelno
;
6181 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
6185 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
6187 labelno
= "%%xcc, ";
6192 labelno
= "%%icc, ";
6197 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6200 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6213 strcpy (p
, labelno
);
6214 p
= strchr (p
, '\0');
6217 strcpy (p
, ".+12\n\t nop\n\tb\t");
6218 /* Skip the next insn if requested or
6219 if we know that it will be a nop. */
6220 if (annul
|| ! final_sequence
)
6234 /* Emit a library call comparison between floating point X and Y.
6235 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
6236 Return the new operator to be used in the comparison sequence.
6238 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6239 values as arguments instead of the TFmode registers themselves,
6240 that's why we cannot call emit_float_lib_cmp. */
6243 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
6246 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
6247 enum machine_mode mode
;
6248 enum rtx_code new_comparison
;
6253 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
6257 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
6261 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
6265 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
6269 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
6273 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
6284 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
6297 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
6298 emit_move_insn (slot0
, x
);
6305 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
6306 emit_move_insn (slot1
, y
);
6309 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
6310 emit_library_call (libfunc
, LCT_NORMAL
,
6312 XEXP (slot0
, 0), Pmode
,
6313 XEXP (slot1
, 0), Pmode
);
6318 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
6319 emit_library_call (libfunc
, LCT_NORMAL
,
6321 x
, TFmode
, y
, TFmode
);
6326 /* Immediately move the result of the libcall into a pseudo
6327 register so reload doesn't clobber the value if it needs
6328 the return register for a spill reg. */
6329 result
= gen_reg_rtx (mode
);
6330 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
6335 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
6338 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
6339 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
6342 new_comparison
= (comparison
== UNGT
? GT
: NE
);
6343 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
6345 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
6347 tem
= gen_reg_rtx (mode
);
6349 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
6351 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
6352 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
6355 tem
= gen_reg_rtx (mode
);
6357 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
6359 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
6360 tem2
= gen_reg_rtx (mode
);
6362 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
6364 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
6365 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
6366 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
6372 /* Generate an unsigned DImode to FP conversion. This is the same code
6373 optabs would emit if we didn't have TFmode patterns. */
6376 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
6378 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
6381 in
= force_reg (DImode
, operands
[1]);
6382 neglab
= gen_label_rtx ();
6383 donelab
= gen_label_rtx ();
6384 i0
= gen_reg_rtx (DImode
);
6385 i1
= gen_reg_rtx (DImode
);
6386 f0
= gen_reg_rtx (mode
);
6388 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
6390 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
6391 emit_jump_insn (gen_jump (donelab
));
6394 emit_label (neglab
);
6396 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
6397 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
6398 emit_insn (gen_iordi3 (i0
, i0
, i1
));
6399 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
6400 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
6402 emit_label (donelab
);
6405 /* Generate an FP to unsigned DImode conversion. This is the same code
6406 optabs would emit if we didn't have TFmode patterns. */
6409 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
6411 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
6414 in
= force_reg (mode
, operands
[1]);
6415 neglab
= gen_label_rtx ();
6416 donelab
= gen_label_rtx ();
6417 i0
= gen_reg_rtx (DImode
);
6418 i1
= gen_reg_rtx (DImode
);
6419 limit
= gen_reg_rtx (mode
);
6420 f0
= gen_reg_rtx (mode
);
6422 emit_move_insn (limit
,
6423 CONST_DOUBLE_FROM_REAL_VALUE (
6424 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
6425 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
6427 emit_insn (gen_rtx_SET (VOIDmode
,
6429 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
6430 emit_jump_insn (gen_jump (donelab
));
6433 emit_label (neglab
);
6435 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
6436 emit_insn (gen_rtx_SET (VOIDmode
,
6438 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
6439 emit_insn (gen_movdi (i1
, const1_rtx
));
6440 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
6441 emit_insn (gen_xordi3 (out
, i0
, i1
));
6443 emit_label (donelab
);
6446 /* Return the string to output a conditional branch to LABEL, testing
6447 register REG. LABEL is the operand number of the label; REG is the
6448 operand number of the reg. OP is the conditional expression. The mode
6449 of REG says what kind of comparison we made.
6451 DEST is the destination insn (i.e. the label), INSN is the source.
6453 REVERSED is nonzero if we should reverse the sense of the comparison.
6455 ANNUL is nonzero if we should generate an annulling branch. */
6458 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
6459 int annul
, rtx insn
)
6461 static char string
[64];
6462 enum rtx_code code
= GET_CODE (op
);
6463 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
6468 /* branch on register are limited to +-128KB. If it is too far away,
6481 brgez,a,pn %o1, .LC29
6487 ba,pt %xcc, .LC29 */
6489 far
= get_attr_length (insn
) >= 3;
6491 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6493 code
= reverse_condition (code
);
6495 /* Only 64 bit versions of these instructions exist. */
6496 gcc_assert (mode
== DImode
);
6498 /* Start by writing the branch condition. */
6503 strcpy (string
, "brnz");
6507 strcpy (string
, "brz");
6511 strcpy (string
, "brgez");
6515 strcpy (string
, "brlz");
6519 strcpy (string
, "brlez");
6523 strcpy (string
, "brgz");
6530 p
= strchr (string
, '\0');
6532 /* Now add the annulling, reg, label, and nop. */
6539 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6542 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6547 *p
= p
< string
+ 8 ? '\t' : ' ';
6555 int veryfar
= 1, delta
;
6557 if (INSN_ADDRESSES_SET_P ())
6559 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6560 - INSN_ADDRESSES (INSN_UID (insn
)));
6561 /* Leave some instructions for "slop". */
6562 if (delta
>= -260000 && delta
< 260000)
6566 strcpy (p
, ".+12\n\t nop\n\t");
6567 /* Skip the next insn if requested or
6568 if we know that it will be a nop. */
6569 if (annul
|| ! final_sequence
)
6579 strcpy (p
, "ba,pt\t%%xcc, ");
6593 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6594 Such instructions cannot be used in the delay slot of return insn on v9.
6595 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6599 epilogue_renumber (register rtx
*where
, int test
)
6601 register const char *fmt
;
6603 register enum rtx_code code
;
6608 code
= GET_CODE (*where
);
6613 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
6615 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
6616 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
6624 /* Do not replace the frame pointer with the stack pointer because
6625 it can cause the delayed instruction to load below the stack.
6626 This occurs when instructions like:
6628 (set (reg/i:SI 24 %i0)
6629 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6630 (const_int -20 [0xffffffec])) 0))
6632 are in the return delayed slot. */
6634 if (GET_CODE (XEXP (*where
, 0)) == REG
6635 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
6636 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
6637 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
6642 if (SPARC_STACK_BIAS
6643 && GET_CODE (XEXP (*where
, 0)) == REG
6644 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6652 fmt
= GET_RTX_FORMAT (code
);
6654 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6659 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6660 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6663 else if (fmt
[i
] == 'e'
6664 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6670 /* Leaf functions and non-leaf functions have different needs. */
6673 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6676 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6678 static const int *const reg_alloc_orders
[] = {
6679 reg_leaf_alloc_order
,
6680 reg_nonleaf_alloc_order
};
6683 order_regs_for_local_alloc (void)
6685 static int last_order_nonleaf
= 1;
6687 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
6689 last_order_nonleaf
= !last_order_nonleaf
;
6690 memcpy ((char *) reg_alloc_order
,
6691 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6692 FIRST_PSEUDO_REGISTER
* sizeof (int));
6696 /* Return 1 if REG and MEM are legitimate enough to allow the various
6697 mem<-->reg splits to be run. */
6700 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
6702 /* Punt if we are here by mistake. */
6703 gcc_assert (reload_completed
);
6705 /* We must have an offsettable memory reference. */
6706 if (! offsettable_memref_p (mem
))
6709 /* If we have legitimate args for ldd/std, we do not want
6710 the split to happen. */
6711 if ((REGNO (reg
) % 2) == 0
6712 && mem_min_alignment (mem
, 8))
6719 /* Return 1 if x and y are some kind of REG and they refer to
6720 different hard registers. This test is guaranteed to be
6721 run after reload. */
6724 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
6726 if (GET_CODE (x
) != REG
)
6728 if (GET_CODE (y
) != REG
)
6730 if (REGNO (x
) == REGNO (y
))
6735 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6736 This makes them candidates for using ldd and std insns.
6738 Note reg1 and reg2 *must* be hard registers. */
6741 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
6743 /* We might have been passed a SUBREG. */
6744 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6747 if (REGNO (reg1
) % 2 != 0)
6750 /* Integer ldd is deprecated in SPARC V9 */
6751 if (TARGET_V9
&& REGNO (reg1
) < 32)
6754 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6757 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6760 This can only happen when addr1 and addr2, the addresses in mem1
6761 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6762 addr1 must also be aligned on a 64-bit boundary.
6764 Also iff dependent_reg_rtx is not null it should not be used to
6765 compute the address for mem1, i.e. we cannot optimize a sequence
6777 But, note that the transformation from:
6782 is perfectly fine. Thus, the peephole2 patterns always pass us
6783 the destination register of the first load, never the second one.
6785 For stores we don't have a similar problem, so dependent_reg_rtx is
6789 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
6793 HOST_WIDE_INT offset1
;
6795 /* The mems cannot be volatile. */
6796 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6799 /* MEM1 should be aligned on a 64-bit boundary. */
6800 if (MEM_ALIGN (mem1
) < 64)
6803 addr1
= XEXP (mem1
, 0);
6804 addr2
= XEXP (mem2
, 0);
6806 /* Extract a register number and offset (if used) from the first addr. */
6807 if (GET_CODE (addr1
) == PLUS
)
6809 /* If not a REG, return zero. */
6810 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6814 reg1
= REGNO (XEXP (addr1
, 0));
6815 /* The offset must be constant! */
6816 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6818 offset1
= INTVAL (XEXP (addr1
, 1));
6821 else if (GET_CODE (addr1
) != REG
)
6825 reg1
= REGNO (addr1
);
6826 /* This was a simple (mem (reg)) expression. Offset is 0. */
6830 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6831 if (GET_CODE (addr2
) != PLUS
)
6834 if (GET_CODE (XEXP (addr2
, 0)) != REG
6835 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6838 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6841 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6844 /* The first offset must be evenly divisible by 8 to ensure the
6845 address is 64 bit aligned. */
6846 if (offset1
% 8 != 0)
6849 /* The offset for the second addr must be 4 more than the first addr. */
6850 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6853 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6858 /* Return 1 if reg is a pseudo, or is the first register in
6859 a hard register pair. This makes it suitable for use in
6860 ldd and std insns. */
6863 register_ok_for_ldd (rtx reg
)
6865 /* We might have been passed a SUBREG. */
6869 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6870 return (REGNO (reg
) % 2 == 0);
6875 /* Return 1 if OP is a memory whose address is known to be
6876 aligned to 8-byte boundary, or a pseudo during reload.
6877 This makes it suitable for use in ldd and std insns. */
6880 memory_ok_for_ldd (rtx op
)
6884 /* In 64-bit mode, we assume that the address is word-aligned. */
6885 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
6888 if ((reload_in_progress
|| reload_completed
)
6889 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
6892 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
6894 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
6903 /* Print operand X (an rtx) in assembler syntax to file FILE.
6904 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6905 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6908 print_operand (FILE *file
, rtx x
, int code
)
6913 /* Output an insn in a delay slot. */
6915 sparc_indent_opcode
= 1;
6917 fputs ("\n\t nop", file
);
6920 /* Output an annul flag if there's nothing for the delay slot and we
6921 are optimizing. This is always used with '(' below.
6922 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6923 this is a dbx bug. So, we only do this when optimizing.
6924 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6925 Always emit a nop in case the next instruction is a branch. */
6926 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6930 /* Output a 'nop' if there's nothing for the delay slot and we are
6931 not optimizing. This is always used with '*' above. */
6932 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6933 fputs ("\n\t nop", file
);
6934 else if (final_sequence
)
6935 sparc_indent_opcode
= 1;
6938 /* Output the right displacement from the saved PC on function return.
6939 The caller may have placed an "unimp" insn immediately after the call
6940 so we have to account for it. This insn is used in the 32-bit ABI
6941 when calling a function that returns a non zero-sized structure. The
6942 64-bit ABI doesn't have it. Be careful to have this test be the same
6943 as that for the call. The exception is when sparc_std_struct_return
6944 is enabled, the psABI is followed exactly and the adjustment is made
6945 by the code in sparc_struct_value_rtx. The call emitted is the same
6946 when sparc_std_struct_return is enabled. */
6948 && cfun
->returns_struct
6949 && !sparc_std_struct_return
6950 && DECL_SIZE (DECL_RESULT (current_function_decl
))
6951 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
6953 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
6959 /* Output the Embedded Medium/Anywhere code model base register. */
6960 fputs (EMBMEDANY_BASE_REG
, file
);
6963 /* Print some local dynamic TLS name. */
6964 assemble_name (file
, get_some_local_dynamic_name ());
6968 /* Adjust the operand to take into account a RESTORE operation. */
6969 if (GET_CODE (x
) == CONST_INT
)
6971 else if (GET_CODE (x
) != REG
)
6972 output_operand_lossage ("invalid %%Y operand");
6973 else if (REGNO (x
) < 8)
6974 fputs (reg_names
[REGNO (x
)], file
);
6975 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6976 fputs (reg_names
[REGNO (x
)-16], file
);
6978 output_operand_lossage ("invalid %%Y operand");
6981 /* Print out the low order register name of a register pair. */
6982 if (WORDS_BIG_ENDIAN
)
6983 fputs (reg_names
[REGNO (x
)+1], file
);
6985 fputs (reg_names
[REGNO (x
)], file
);
6988 /* Print out the high order register name of a register pair. */
6989 if (WORDS_BIG_ENDIAN
)
6990 fputs (reg_names
[REGNO (x
)], file
);
6992 fputs (reg_names
[REGNO (x
)+1], file
);
6995 /* Print out the second register name of a register pair or quad.
6996 I.e., R (%o0) => %o1. */
6997 fputs (reg_names
[REGNO (x
)+1], file
);
7000 /* Print out the third register name of a register quad.
7001 I.e., S (%o0) => %o2. */
7002 fputs (reg_names
[REGNO (x
)+2], file
);
7005 /* Print out the fourth register name of a register quad.
7006 I.e., T (%o0) => %o3. */
7007 fputs (reg_names
[REGNO (x
)+3], file
);
7010 /* Print a condition code register. */
7011 if (REGNO (x
) == SPARC_ICC_REG
)
7013 /* We don't handle CC[X]_NOOVmode because they're not supposed
7015 if (GET_MODE (x
) == CCmode
)
7016 fputs ("%icc", file
);
7017 else if (GET_MODE (x
) == CCXmode
)
7018 fputs ("%xcc", file
);
7023 /* %fccN register */
7024 fputs (reg_names
[REGNO (x
)], file
);
7027 /* Print the operand's address only. */
7028 output_address (XEXP (x
, 0));
7031 /* In this case we need a register. Use %g0 if the
7032 operand is const0_rtx. */
7034 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7036 fputs ("%g0", file
);
7043 switch (GET_CODE (x
))
7045 case IOR
: fputs ("or", file
); break;
7046 case AND
: fputs ("and", file
); break;
7047 case XOR
: fputs ("xor", file
); break;
7048 default: output_operand_lossage ("invalid %%A operand");
7053 switch (GET_CODE (x
))
7055 case IOR
: fputs ("orn", file
); break;
7056 case AND
: fputs ("andn", file
); break;
7057 case XOR
: fputs ("xnor", file
); break;
7058 default: output_operand_lossage ("invalid %%B operand");
7062 /* These are used by the conditional move instructions. */
7066 enum rtx_code rc
= GET_CODE (x
);
7070 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7071 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7072 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7074 rc
= reverse_condition (GET_CODE (x
));
7078 case NE
: fputs ("ne", file
); break;
7079 case EQ
: fputs ("e", file
); break;
7080 case GE
: fputs ("ge", file
); break;
7081 case GT
: fputs ("g", file
); break;
7082 case LE
: fputs ("le", file
); break;
7083 case LT
: fputs ("l", file
); break;
7084 case GEU
: fputs ("geu", file
); break;
7085 case GTU
: fputs ("gu", file
); break;
7086 case LEU
: fputs ("leu", file
); break;
7087 case LTU
: fputs ("lu", file
); break;
7088 case LTGT
: fputs ("lg", file
); break;
7089 case UNORDERED
: fputs ("u", file
); break;
7090 case ORDERED
: fputs ("o", file
); break;
7091 case UNLT
: fputs ("ul", file
); break;
7092 case UNLE
: fputs ("ule", file
); break;
7093 case UNGT
: fputs ("ug", file
); break;
7094 case UNGE
: fputs ("uge", file
); break;
7095 case UNEQ
: fputs ("ue", file
); break;
7096 default: output_operand_lossage (code
== 'c'
7097 ? "invalid %%c operand"
7098 : "invalid %%C operand");
7103 /* These are used by the movr instruction pattern. */
7107 enum rtx_code rc
= (code
== 'd'
7108 ? reverse_condition (GET_CODE (x
))
7112 case NE
: fputs ("ne", file
); break;
7113 case EQ
: fputs ("e", file
); break;
7114 case GE
: fputs ("gez", file
); break;
7115 case LT
: fputs ("lz", file
); break;
7116 case LE
: fputs ("lez", file
); break;
7117 case GT
: fputs ("gz", file
); break;
7118 default: output_operand_lossage (code
== 'd'
7119 ? "invalid %%d operand"
7120 : "invalid %%D operand");
7127 /* Print a sign-extended character. */
7128 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
7129 fprintf (file
, "%d", i
);
7134 /* Operand must be a MEM; write its address. */
7135 if (GET_CODE (x
) != MEM
)
7136 output_operand_lossage ("invalid %%f operand");
7137 output_address (XEXP (x
, 0));
7142 /* Print a sign-extended 32-bit value. */
7144 if (GET_CODE(x
) == CONST_INT
)
7146 else if (GET_CODE(x
) == CONST_DOUBLE
)
7147 i
= CONST_DOUBLE_LOW (x
);
7150 output_operand_lossage ("invalid %%s operand");
7153 i
= trunc_int_for_mode (i
, SImode
);
7154 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
7159 /* Do nothing special. */
7163 /* Undocumented flag. */
7164 output_operand_lossage ("invalid operand output code");
7167 if (GET_CODE (x
) == REG
)
7168 fputs (reg_names
[REGNO (x
)], file
);
7169 else if (GET_CODE (x
) == MEM
)
7172 /* Poor Sun assembler doesn't understand absolute addressing. */
7173 if (CONSTANT_P (XEXP (x
, 0)))
7174 fputs ("%g0+", file
);
7175 output_address (XEXP (x
, 0));
7178 else if (GET_CODE (x
) == HIGH
)
7180 fputs ("%hi(", file
);
7181 output_addr_const (file
, XEXP (x
, 0));
7184 else if (GET_CODE (x
) == LO_SUM
)
7186 print_operand (file
, XEXP (x
, 0), 0);
7187 if (TARGET_CM_MEDMID
)
7188 fputs ("+%l44(", file
);
7190 fputs ("+%lo(", file
);
7191 output_addr_const (file
, XEXP (x
, 1));
7194 else if (GET_CODE (x
) == CONST_DOUBLE
7195 && (GET_MODE (x
) == VOIDmode
7196 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
7198 if (CONST_DOUBLE_HIGH (x
) == 0)
7199 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
7200 else if (CONST_DOUBLE_HIGH (x
) == -1
7201 && CONST_DOUBLE_LOW (x
) < 0)
7202 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
7204 output_operand_lossage ("long long constant not a valid immediate operand");
7206 else if (GET_CODE (x
) == CONST_DOUBLE
)
7207 output_operand_lossage ("floating point constant not a valid immediate operand");
7208 else { output_addr_const (file
, x
); }
7211 /* Target hook for assembling integer objects. The sparc version has
7212 special handling for aligned DI-mode objects. */
7215 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
7217 /* ??? We only output .xword's for symbols and only then in environments
7218 where the assembler can handle them. */
7219 if (aligned_p
&& size
== 8
7220 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
7224 assemble_integer_with_op ("\t.xword\t", x
);
7229 assemble_aligned_integer (4, const0_rtx
);
7230 assemble_aligned_integer (4, x
);
7234 return default_assemble_integer (x
, size
, aligned_p
);
7237 /* Return the value of a code used in the .proc pseudo-op that says
7238 what kind of result this function returns. For non-C types, we pick
7239 the closest C type. */
7241 #ifndef SHORT_TYPE_SIZE
7242 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7245 #ifndef INT_TYPE_SIZE
7246 #define INT_TYPE_SIZE BITS_PER_WORD
7249 #ifndef LONG_TYPE_SIZE
7250 #define LONG_TYPE_SIZE BITS_PER_WORD
7253 #ifndef LONG_LONG_TYPE_SIZE
7254 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7257 #ifndef FLOAT_TYPE_SIZE
7258 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7261 #ifndef DOUBLE_TYPE_SIZE
7262 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7265 #ifndef LONG_DOUBLE_TYPE_SIZE
7266 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7270 sparc_type_code (register tree type
)
7272 register unsigned long qualifiers
= 0;
7273 register unsigned shift
;
7275 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7276 setting more, since some assemblers will give an error for this. Also,
7277 we must be careful to avoid shifts of 32 bits or more to avoid getting
7278 unpredictable results. */
7280 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
7282 switch (TREE_CODE (type
))
7288 qualifiers
|= (3 << shift
);
7293 qualifiers
|= (2 << shift
);
7297 case REFERENCE_TYPE
:
7299 qualifiers
|= (1 << shift
);
7303 return (qualifiers
| 8);
7306 case QUAL_UNION_TYPE
:
7307 return (qualifiers
| 9);
7310 return (qualifiers
| 10);
7313 return (qualifiers
| 16);
7316 /* If this is a range type, consider it to be the underlying
7318 if (TREE_TYPE (type
) != 0)
7321 /* Carefully distinguish all the standard types of C,
7322 without messing up if the language is not C. We do this by
7323 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7324 look at both the names and the above fields, but that's redundant.
7325 Any type whose size is between two C types will be considered
7326 to be the wider of the two types. Also, we do not have a
7327 special code to use for "long long", so anything wider than
7328 long is treated the same. Note that we can't distinguish
7329 between "int" and "long" in this code if they are the same
7330 size, but that's fine, since neither can the assembler. */
7332 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
7333 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
7335 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
7336 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
7338 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
7339 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
7342 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
7345 /* If this is a range type, consider it to be the underlying
7347 if (TREE_TYPE (type
) != 0)
7350 /* Carefully distinguish all the standard types of C,
7351 without messing up if the language is not C. */
7353 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
7354 return (qualifiers
| 6);
7357 return (qualifiers
| 7);
7359 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
7360 /* ??? We need to distinguish between double and float complex types,
7361 but I don't know how yet because I can't reach this code from
7362 existing front-ends. */
7363 return (qualifiers
| 7); /* Who knows? */
7366 case BOOLEAN_TYPE
: /* Boolean truth value type. */
7367 case LANG_TYPE
: /* ? */
7371 gcc_unreachable (); /* Not a type! */
7378 /* Nested function support. */
7380 /* Emit RTL insns to initialize the variable parts of a trampoline.
7381 FNADDR is an RTX for the address of the function's pure code.
7382 CXT is an RTX for the static chain value for the function.
7384 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7385 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7386 (to store insns). This is a bit excessive. Perhaps a different
7387 mechanism would be better here.
7389 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7392 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
7394 /* SPARC 32-bit trampoline:
7397 sethi %hi(static), %g2
7399 or %g2, %lo(static), %g2
7401 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7402 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7406 (adjust_address (m_tramp
, SImode
, 0),
7407 expand_binop (SImode
, ior_optab
,
7408 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
7409 size_int (10), 0, 1),
7410 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
7411 NULL_RTX
, 1, OPTAB_DIRECT
));
7414 (adjust_address (m_tramp
, SImode
, 4),
7415 expand_binop (SImode
, ior_optab
,
7416 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
7417 size_int (10), 0, 1),
7418 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
7419 NULL_RTX
, 1, OPTAB_DIRECT
));
7422 (adjust_address (m_tramp
, SImode
, 8),
7423 expand_binop (SImode
, ior_optab
,
7424 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
7425 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
7426 NULL_RTX
, 1, OPTAB_DIRECT
));
7429 (adjust_address (m_tramp
, SImode
, 12),
7430 expand_binop (SImode
, ior_optab
,
7431 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
7432 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
7433 NULL_RTX
, 1, OPTAB_DIRECT
));
7435 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7436 aligned on a 16 byte boundary so one flush clears it all. */
7437 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
7438 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7439 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
7440 && sparc_cpu
!= PROCESSOR_NIAGARA
7441 && sparc_cpu
!= PROCESSOR_NIAGARA2
)
7442 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
7444 /* Call __enable_execute_stack after writing onto the stack to make sure
7445 the stack address is accessible. */
7446 #ifdef ENABLE_EXECUTE_STACK
7447 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7448 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
7453 /* The 64-bit version is simpler because it makes more sense to load the
7454 values as "immediate" data out of the trampoline. It's also easier since
7455 we can read the PC without clobbering a register. */
7458 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
7460 /* SPARC 64-bit trampoline:
7469 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
7470 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
7471 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
7472 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
7473 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
7474 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
7475 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
7476 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
7477 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
7478 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
7479 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
7481 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7482 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
7483 && sparc_cpu
!= PROCESSOR_NIAGARA
7484 && sparc_cpu
!= PROCESSOR_NIAGARA2
)
7485 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
7487 /* Call __enable_execute_stack after writing onto the stack to make sure
7488 the stack address is accessible. */
7489 #ifdef ENABLE_EXECUTE_STACK
7490 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7491 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
7495 /* Worker for TARGET_TRAMPOLINE_INIT. */
7498 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
7500 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
7501 cxt
= force_reg (Pmode
, cxt
);
7503 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
7505 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
7508 /* Adjust the cost of a scheduling dependency. Return the new cost of
7509 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7512 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7514 enum attr_type insn_type
;
7516 if (! recog_memoized (insn
))
7519 insn_type
= get_attr_type (insn
);
7521 if (REG_NOTE_KIND (link
) == 0)
7523 /* Data dependency; DEP_INSN writes a register that INSN reads some
7526 /* if a load, then the dependence must be on the memory address;
7527 add an extra "cycle". Note that the cost could be two cycles
7528 if the reg was written late in an instruction group; we ca not tell
7530 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7533 /* Get the delay only if the address of the store is the dependence. */
7534 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7536 rtx pat
= PATTERN(insn
);
7537 rtx dep_pat
= PATTERN (dep_insn
);
7539 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7540 return cost
; /* This should not happen! */
7542 /* The dependency between the two instructions was on the data that
7543 is being stored. Assume that this implies that the address of the
7544 store is not dependent. */
7545 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7548 return cost
+ 3; /* An approximation. */
7551 /* A shift instruction cannot receive its data from an instruction
7552 in the same cycle; add a one cycle penalty. */
7553 if (insn_type
== TYPE_SHIFT
)
7554 return cost
+ 3; /* Split before cascade into shift. */
7558 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7559 INSN writes some cycles later. */
7561 /* These are only significant for the fpu unit; writing a fp reg before
7562 the fpu has finished with it stalls the processor. */
7564 /* Reusing an integer register causes no problems. */
7565 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7573 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7575 enum attr_type insn_type
, dep_type
;
7576 rtx pat
= PATTERN(insn
);
7577 rtx dep_pat
= PATTERN (dep_insn
);
7579 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7582 insn_type
= get_attr_type (insn
);
7583 dep_type
= get_attr_type (dep_insn
);
7585 switch (REG_NOTE_KIND (link
))
7588 /* Data dependency; DEP_INSN writes a register that INSN reads some
7595 /* Get the delay iff the address of the store is the dependence. */
7596 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7599 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7606 /* If a load, then the dependence must be on the memory address. If
7607 the addresses aren't equal, then it might be a false dependency */
7608 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7610 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7611 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7612 || GET_CODE (SET_SRC (pat
)) != MEM
7613 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7614 XEXP (SET_SRC (pat
), 0)))
7622 /* Compare to branch latency is 0. There is no benefit from
7623 separating compare and branch. */
7624 if (dep_type
== TYPE_COMPARE
)
7626 /* Floating point compare to branch latency is less than
7627 compare to conditional move. */
7628 if (dep_type
== TYPE_FPCMP
)
7637 /* Anti-dependencies only penalize the fpu unit. */
7638 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7650 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
7654 case PROCESSOR_SUPERSPARC
:
7655 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7657 case PROCESSOR_HYPERSPARC
:
7658 case PROCESSOR_SPARCLITE86X
:
7659 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7668 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
7669 int sched_verbose ATTRIBUTE_UNUSED
,
7670 int max_ready ATTRIBUTE_UNUSED
)
7674 sparc_use_sched_lookahead (void)
7676 if (sparc_cpu
== PROCESSOR_NIAGARA
7677 || sparc_cpu
== PROCESSOR_NIAGARA2
)
7679 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7680 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7682 if ((1 << sparc_cpu
) &
7683 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7684 (1 << PROCESSOR_SPARCLITE86X
)))
7690 sparc_issue_rate (void)
7694 case PROCESSOR_NIAGARA
:
7695 case PROCESSOR_NIAGARA2
:
7699 /* Assume V9 processors are capable of at least dual-issue. */
7701 case PROCESSOR_SUPERSPARC
:
7703 case PROCESSOR_HYPERSPARC
:
7704 case PROCESSOR_SPARCLITE86X
:
7706 case PROCESSOR_ULTRASPARC
:
7707 case PROCESSOR_ULTRASPARC3
:
7713 set_extends (rtx insn
)
7715 register rtx pat
= PATTERN (insn
);
7717 switch (GET_CODE (SET_SRC (pat
)))
7719 /* Load and some shift instructions zero extend. */
7722 /* sethi clears the high bits */
7724 /* LO_SUM is used with sethi. sethi cleared the high
7725 bits and the values used with lo_sum are positive */
7727 /* Store flag stores 0 or 1 */
7737 rtx op0
= XEXP (SET_SRC (pat
), 0);
7738 rtx op1
= XEXP (SET_SRC (pat
), 1);
7739 if (GET_CODE (op1
) == CONST_INT
)
7740 return INTVAL (op1
) >= 0;
7741 if (GET_CODE (op0
) != REG
)
7743 if (sparc_check_64 (op0
, insn
) == 1)
7745 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7750 rtx op0
= XEXP (SET_SRC (pat
), 0);
7751 rtx op1
= XEXP (SET_SRC (pat
), 1);
7752 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7754 if (GET_CODE (op1
) == CONST_INT
)
7755 return INTVAL (op1
) >= 0;
7756 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7759 return GET_MODE (SET_SRC (pat
)) == SImode
;
7760 /* Positive integers leave the high bits zero. */
7762 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7764 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7767 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7769 return sparc_check_64 (SET_SRC (pat
), insn
);
7775 /* We _ought_ to have only one kind per function, but... */
7776 static GTY(()) rtx sparc_addr_diff_list
;
7777 static GTY(()) rtx sparc_addr_list
;
7780 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
7782 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7784 sparc_addr_diff_list
7785 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7787 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7791 sparc_output_addr_vec (rtx vec
)
7793 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7794 int idx
, vlen
= XVECLEN (body
, 0);
7796 #ifdef ASM_OUTPUT_ADDR_VEC_START
7797 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7800 #ifdef ASM_OUTPUT_CASE_LABEL
7801 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7804 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7807 for (idx
= 0; idx
< vlen
; idx
++)
7809 ASM_OUTPUT_ADDR_VEC_ELT
7810 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7813 #ifdef ASM_OUTPUT_ADDR_VEC_END
7814 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7819 sparc_output_addr_diff_vec (rtx vec
)
7821 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7822 rtx base
= XEXP (XEXP (body
, 0), 0);
7823 int idx
, vlen
= XVECLEN (body
, 1);
7825 #ifdef ASM_OUTPUT_ADDR_VEC_START
7826 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7829 #ifdef ASM_OUTPUT_CASE_LABEL
7830 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7833 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7836 for (idx
= 0; idx
< vlen
; idx
++)
7838 ASM_OUTPUT_ADDR_DIFF_ELT
7841 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7842 CODE_LABEL_NUMBER (base
));
7845 #ifdef ASM_OUTPUT_ADDR_VEC_END
7846 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7851 sparc_output_deferred_case_vectors (void)
7856 if (sparc_addr_list
== NULL_RTX
7857 && sparc_addr_diff_list
== NULL_RTX
)
7860 /* Align to cache line in the function's code section. */
7861 switch_to_section (current_function_section ());
7863 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7865 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7867 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7868 sparc_output_addr_vec (XEXP (t
, 0));
7869 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7870 sparc_output_addr_diff_vec (XEXP (t
, 0));
7872 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7875 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7876 unknown. Return 1 if the high bits are zero, -1 if the register is
7879 sparc_check_64 (rtx x
, rtx insn
)
7881 /* If a register is set only once it is safe to ignore insns this
7882 code does not know how to handle. The loop will either recognize
7883 the single set and return the correct value or fail to recognize
7888 gcc_assert (GET_CODE (x
) == REG
);
7890 if (GET_MODE (x
) == DImode
)
7891 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7893 if (flag_expensive_optimizations
7894 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
7900 insn
= get_last_insn_anywhere ();
7905 while ((insn
= PREV_INSN (insn
)))
7907 switch (GET_CODE (insn
))
7920 rtx pat
= PATTERN (insn
);
7921 if (GET_CODE (pat
) != SET
)
7923 if (rtx_equal_p (x
, SET_DEST (pat
)))
7924 return set_extends (insn
);
7925 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7926 return set_extends (insn
);
7927 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
7935 /* Returns assembly code to perform a DImode shift using
7936 a 64-bit global or out register on SPARC-V8+. */
7938 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
7940 static char asm_code
[60];
7942 /* The scratch register is only required when the destination
7943 register is not a 64-bit global or out register. */
7944 if (which_alternative
!= 2)
7945 operands
[3] = operands
[0];
7947 /* We can only shift by constants <= 63. */
7948 if (GET_CODE (operands
[2]) == CONST_INT
)
7949 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
7951 if (GET_CODE (operands
[1]) == CONST_INT
)
7953 output_asm_insn ("mov\t%1, %3", operands
);
7957 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
7958 if (sparc_check_64 (operands
[1], insn
) <= 0)
7959 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
7960 output_asm_insn ("or\t%L1, %3, %3", operands
);
7963 strcpy(asm_code
, opcode
);
7965 if (which_alternative
!= 2)
7966 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7968 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7971 /* Output rtl to increment the profiler label LABELNO
7972 for profiling a function entry. */
7975 sparc_profile_hook (int labelno
)
7980 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
7981 if (NO_PROFILE_COUNTERS
)
7983 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
7987 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
7988 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
7989 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
7993 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
7996 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
7997 tree decl ATTRIBUTE_UNUSED
)
7999 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8001 if (!(flags
& SECTION_DEBUG
))
8002 fputs (",#alloc", asm_out_file
);
8003 if (flags
& SECTION_WRITE
)
8004 fputs (",#write", asm_out_file
);
8005 if (flags
& SECTION_TLS
)
8006 fputs (",#tls", asm_out_file
);
8007 if (flags
& SECTION_CODE
)
8008 fputs (",#execinstr", asm_out_file
);
8010 /* ??? Handle SECTION_BSS. */
8012 fputc ('\n', asm_out_file
);
8015 /* We do not allow indirect calls to be optimized into sibling calls.
8017 We cannot use sibling calls when delayed branches are disabled
8018 because they will likely require the call delay slot to be filled.
8020 Also, on SPARC 32-bit we cannot emit a sibling call when the
8021 current function returns a structure. This is because the "unimp
8022 after call" convention would cause the callee to return to the
8023 wrong place. The generic code already disallows cases where the
8024 function being called returns a structure.
8026 It may seem strange how this last case could occur. Usually there
8027 is code after the call which jumps to epilogue code which dumps the
8028 return value into the struct return area. That ought to invalidate
8029 the sibling call right? Well, in the C++ case we can end up passing
8030 the pointer to the struct return area to a constructor (which returns
8031 void) and then nothing else happens. Such a sibling call would look
8032 valid without the added check here.
8034 VxWorks PIC PLT entries require the global pointer to be initialized
8035 on entry. We therefore can't emit sibling calls to them. */
8037 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
8040 && flag_delayed_branch
8041 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
8042 && !(TARGET_VXWORKS_RTP
8044 && !targetm
.binds_local_p (decl
)));
8047 /* libfunc renaming. */
8048 #include "config/gofast.h"
8051 sparc_init_libfuncs (void)
8055 /* Use the subroutines that Sun's library provides for integer
8056 multiply and divide. The `*' prevents an underscore from
8057 being prepended by the compiler. .umul is a little faster
8059 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
8060 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
8061 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
8062 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
8063 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
8065 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8066 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
8067 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
8068 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
8069 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
8070 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
8072 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8073 is because with soft-float, the SFmode and DFmode sqrt
8074 instructions will be absent, and the compiler will notice and
8075 try to use the TFmode sqrt instruction for calls to the
8076 builtin function sqrt, but this fails. */
8078 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
8080 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
8081 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
8082 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
8083 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
8084 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
8085 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
8087 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
8088 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
8089 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
8090 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
8092 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
8093 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
8094 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
8095 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
8097 if (DITF_CONVERSION_LIBFUNCS
)
8099 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
8100 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
8101 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
8102 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
8105 if (SUN_CONVERSION_LIBFUNCS
)
8107 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8108 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8109 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8110 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8115 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8116 do not exist in the library. Make sure the compiler does not
8117 emit calls to them by accident. (It should always use the
8118 hardware instructions.) */
8119 set_optab_libfunc (smul_optab
, SImode
, 0);
8120 set_optab_libfunc (sdiv_optab
, SImode
, 0);
8121 set_optab_libfunc (udiv_optab
, SImode
, 0);
8122 set_optab_libfunc (smod_optab
, SImode
, 0);
8123 set_optab_libfunc (umod_optab
, SImode
, 0);
8125 if (SUN_INTEGER_MULTIPLY_64
)
8127 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
8128 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
8129 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
8130 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
8131 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
8134 if (SUN_CONVERSION_LIBFUNCS
)
8136 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
8137 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
8138 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
8139 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
8143 gofast_maybe_init_libfuncs ();
8146 #define def_builtin(NAME, CODE, TYPE) \
8147 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
8150 /* Implement the TARGET_INIT_BUILTINS target hook.
8151 Create builtin functions for special SPARC instructions. */
8154 sparc_init_builtins (void)
8157 sparc_vis_init_builtins ();
8160 /* Create builtin functions for VIS 1.0 instructions. */
8163 sparc_vis_init_builtins (void)
8165 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
8166 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
8167 tree v4hi
= build_vector_type (intHI_type_node
, 4);
8168 tree v2hi
= build_vector_type (intHI_type_node
, 2);
8169 tree v2si
= build_vector_type (intSI_type_node
, 2);
8171 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
8172 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
8173 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
8174 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
8175 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
8176 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
8177 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
8178 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
8179 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
8180 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
8181 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
8182 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
8183 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
8185 intDI_type_node
, 0);
8186 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
8188 intDI_type_node
, 0);
8189 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
8191 intSI_type_node
, 0);
8192 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
8194 intDI_type_node
, 0);
8196 /* Packing and expanding vectors. */
8197 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
, v4qi_ftype_v4hi
);
8198 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
8199 v8qi_ftype_v2si_v8qi
);
8200 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
8202 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
, v4hi_ftype_v4qi
);
8203 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
8204 v8qi_ftype_v4qi_v4qi
);
8206 /* Multiplications. */
8207 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
8208 v4hi_ftype_v4qi_v4hi
);
8209 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
8210 v4hi_ftype_v4qi_v2hi
);
8211 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
8212 v4hi_ftype_v4qi_v2hi
);
8213 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
8214 v4hi_ftype_v8qi_v4hi
);
8215 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
8216 v4hi_ftype_v8qi_v4hi
);
8217 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
8218 v2si_ftype_v4qi_v2hi
);
8219 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
8220 v2si_ftype_v4qi_v2hi
);
8222 /* Data aligning. */
8223 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
8224 v4hi_ftype_v4hi_v4hi
);
8225 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
8226 v8qi_ftype_v8qi_v8qi
);
8227 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
8228 v2si_ftype_v2si_v2si
);
8229 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
8232 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
8235 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
8238 /* Pixel distance. */
8239 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
8240 di_ftype_v8qi_v8qi_di
);
8243 /* Handle TARGET_EXPAND_BUILTIN target hook.
8244 Expand builtin functions for sparc intrinsics. */
8247 sparc_expand_builtin (tree exp
, rtx target
,
8248 rtx subtarget ATTRIBUTE_UNUSED
,
8249 enum machine_mode tmode ATTRIBUTE_UNUSED
,
8250 int ignore ATTRIBUTE_UNUSED
)
8253 call_expr_arg_iterator iter
;
8254 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8255 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
8257 enum machine_mode mode
[4];
8260 mode
[0] = insn_data
[icode
].operand
[0].mode
;
8262 || GET_MODE (target
) != mode
[0]
8263 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
[0]))
8264 op
[0] = gen_reg_rtx (mode
[0]);
8268 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
8271 mode
[arg_count
] = insn_data
[icode
].operand
[arg_count
].mode
;
8272 op
[arg_count
] = expand_normal (arg
);
8274 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
8276 op
[arg_count
] = copy_to_mode_reg (mode
[arg_count
], op
[arg_count
]);
8282 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
8285 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
8288 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
8303 sparc_vis_mul8x16 (int e8
, int e16
)
8305 return (e8
* e16
+ 128) / 256;
8308 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
8309 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
8310 constants. A tree list with the results of the multiplications is returned,
8311 and each element in the list is of INNER_TYPE. */
8314 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
8316 tree n_elts
= NULL_TREE
;
8321 case CODE_FOR_fmul8x16_vis
:
8322 for (; elts0
&& elts1
;
8323 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
8326 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
8327 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
8328 n_elts
= tree_cons (NULL_TREE
,
8329 build_int_cst (inner_type
, val
),
8334 case CODE_FOR_fmul8x16au_vis
:
8335 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
8337 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
8340 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
8342 n_elts
= tree_cons (NULL_TREE
,
8343 build_int_cst (inner_type
, val
),
8348 case CODE_FOR_fmul8x16al_vis
:
8349 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
8351 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
8354 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
8356 n_elts
= tree_cons (NULL_TREE
,
8357 build_int_cst (inner_type
, val
),
8366 return nreverse (n_elts
);
8369 /* Handle TARGET_FOLD_BUILTIN target hook.
8370 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
8371 result of the function call is ignored. NULL_TREE is returned if the
8372 function could not be folded. */
8375 sparc_fold_builtin (tree fndecl
, tree arglist
, bool ignore
)
8377 tree arg0
, arg1
, arg2
;
8378 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
8379 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
8382 && icode
!= CODE_FOR_alignaddrsi_vis
8383 && icode
!= CODE_FOR_alignaddrdi_vis
)
8384 return fold_convert (rtype
, integer_zero_node
);
8388 case CODE_FOR_fexpand_vis
:
8389 arg0
= TREE_VALUE (arglist
);
8392 if (TREE_CODE (arg0
) == VECTOR_CST
)
8394 tree inner_type
= TREE_TYPE (rtype
);
8395 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
8396 tree n_elts
= NULL_TREE
;
8398 for (; elts
; elts
= TREE_CHAIN (elts
))
8400 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
8401 n_elts
= tree_cons (NULL_TREE
,
8402 build_int_cst (inner_type
, val
),
8405 return build_vector (rtype
, nreverse (n_elts
));
8409 case CODE_FOR_fmul8x16_vis
:
8410 case CODE_FOR_fmul8x16au_vis
:
8411 case CODE_FOR_fmul8x16al_vis
:
8412 arg0
= TREE_VALUE (arglist
);
8413 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8417 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
8419 tree inner_type
= TREE_TYPE (rtype
);
8420 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8421 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8422 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
8425 return build_vector (rtype
, n_elts
);
8429 case CODE_FOR_fpmerge_vis
:
8430 arg0
= TREE_VALUE (arglist
);
8431 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8435 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
8437 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8438 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8439 tree n_elts
= NULL_TREE
;
8441 for (; elts0
&& elts1
;
8442 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
8444 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
8445 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
8448 return build_vector (rtype
, nreverse (n_elts
));
8452 case CODE_FOR_pdist_vis
:
8453 arg0
= TREE_VALUE (arglist
);
8454 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8455 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8460 if (TREE_CODE (arg0
) == VECTOR_CST
8461 && TREE_CODE (arg1
) == VECTOR_CST
8462 && TREE_CODE (arg2
) == INTEGER_CST
)
8465 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
8466 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
8467 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8468 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8470 for (; elts0
&& elts1
;
8471 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
8473 unsigned HOST_WIDE_INT
8474 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
8475 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
8476 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
8477 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
8479 unsigned HOST_WIDE_INT l
;
8482 overflow
|= neg_double (low1
, high1
, &l
, &h
);
8483 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
8485 overflow
|= neg_double (l
, h
, &l
, &h
);
8487 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
8490 gcc_assert (overflow
== 0);
8492 return build_int_cst_wide (rtype
, low
, high
);
8502 /* ??? This duplicates information provided to the compiler by the
8503 ??? scheduler description. Some day, teach genautomata to output
8504 ??? the latencies and then CSE will just use that. */
8507 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
8508 bool speed ATTRIBUTE_UNUSED
)
8510 enum machine_mode mode
= GET_MODE (x
);
8511 bool float_mode_p
= FLOAT_MODE_P (mode
);
8516 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8534 if (GET_MODE (x
) == VOIDmode
8535 && ((CONST_DOUBLE_HIGH (x
) == 0
8536 && CONST_DOUBLE_LOW (x
) < 0x1000)
8537 || (CONST_DOUBLE_HIGH (x
) == -1
8538 && CONST_DOUBLE_LOW (x
) < 0
8539 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
8546 /* If outer-code was a sign or zero extension, a cost
8547 of COSTS_N_INSNS (1) was already added in. This is
8548 why we are subtracting it back out. */
8549 if (outer_code
== ZERO_EXTEND
)
8551 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
8553 else if (outer_code
== SIGN_EXTEND
)
8555 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
8557 else if (float_mode_p
)
8559 *total
= sparc_costs
->float_load
;
8563 *total
= sparc_costs
->int_load
;
8571 *total
= sparc_costs
->float_plusminus
;
8573 *total
= COSTS_N_INSNS (1);
8578 *total
= sparc_costs
->float_mul
;
8579 else if (! TARGET_HARD_MUL
)
8580 *total
= COSTS_N_INSNS (25);
8586 if (sparc_costs
->int_mul_bit_factor
)
8590 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8592 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
8593 for (nbits
= 0; value
!= 0; value
&= value
- 1)
8596 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
8597 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
8599 rtx x1
= XEXP (x
, 1);
8600 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
8601 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
8603 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
8605 for (; value2
!= 0; value2
&= value2
- 1)
8613 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
8614 bit_cost
= COSTS_N_INSNS (bit_cost
);
8618 *total
= sparc_costs
->int_mulX
+ bit_cost
;
8620 *total
= sparc_costs
->int_mul
+ bit_cost
;
8627 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
8637 *total
= sparc_costs
->float_div_df
;
8639 *total
= sparc_costs
->float_div_sf
;
8644 *total
= sparc_costs
->int_divX
;
8646 *total
= sparc_costs
->int_div
;
8653 *total
= COSTS_N_INSNS (1);
8660 case UNSIGNED_FLOAT
:
8664 case FLOAT_TRUNCATE
:
8665 *total
= sparc_costs
->float_move
;
8670 *total
= sparc_costs
->float_sqrt_df
;
8672 *total
= sparc_costs
->float_sqrt_sf
;
8677 *total
= sparc_costs
->float_cmp
;
8679 *total
= COSTS_N_INSNS (1);
8684 *total
= sparc_costs
->float_cmove
;
8686 *total
= sparc_costs
->int_cmove
;
8690 /* Handle the NAND vector patterns. */
8691 if (sparc_vector_mode_supported_p (GET_MODE (x
))
8692 && GET_CODE (XEXP (x
, 0)) == NOT
8693 && GET_CODE (XEXP (x
, 1)) == NOT
)
8695 *total
= COSTS_N_INSNS (1);
8706 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
8707 This is achieved by means of a manual dynamic stack space allocation in
8708 the current frame. We make the assumption that SEQ doesn't contain any
8709 function calls, with the possible exception of calls to the PIC helper. */
8712 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
8714 /* We must preserve the lowest 16 words for the register save area. */
8715 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
8716 /* We really need only 2 words of fresh stack space. */
8717 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
8720 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
8721 SPARC_STACK_BIAS
+ offset
));
8723 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
8724 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
8726 emit_insn (gen_rtx_SET (VOIDmode
,
8727 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
8731 emit_insn (gen_rtx_SET (VOIDmode
,
8733 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
8734 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
8735 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
8738 /* Output the assembler code for a thunk function. THUNK_DECL is the
8739 declaration for the thunk function itself, FUNCTION is the decl for
8740 the target function. DELTA is an immediate constant offset to be
8741 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8742 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
8745 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8746 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8749 rtx this_rtx
, insn
, funexp
;
8750 unsigned int int_arg_first
;
8752 reload_completed
= 1;
8753 epilogue_completed
= 1;
8755 emit_note (NOTE_INSN_PROLOGUE_END
);
8757 if (flag_delayed_branch
)
8759 /* We will emit a regular sibcall below, so we need to instruct
8760 output_sibcall that we are in a leaf function. */
8761 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
8763 /* This will cause final.c to invoke leaf_renumber_regs so we
8764 must behave as if we were in a not-yet-leafified function. */
8765 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
8769 /* We will emit the sibcall manually below, so we will need to
8770 manually spill non-leaf registers. */
8771 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
8773 /* We really are in a leaf function. */
8774 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
8777 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8778 returns a structure, the structure return pointer is there instead. */
8780 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8781 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
8783 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
8785 /* Add DELTA. When possible use a plain add, otherwise load it into
8786 a register first. */
8789 rtx delta_rtx
= GEN_INT (delta
);
8791 if (! SPARC_SIMM13_P (delta
))
8793 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8794 emit_move_insn (scratch
, delta_rtx
);
8795 delta_rtx
= scratch
;
8798 /* THIS_RTX += DELTA. */
8799 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
8802 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
8805 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8806 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8808 gcc_assert (vcall_offset
< 0);
8810 /* SCRATCH = *THIS_RTX. */
8811 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
8813 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8814 may not have any available scratch register at this point. */
8815 if (SPARC_SIMM13_P (vcall_offset
))
8817 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8818 else if (! fixed_regs
[5]
8819 /* The below sequence is made up of at least 2 insns,
8820 while the default method may need only one. */
8821 && vcall_offset
< -8192)
8823 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
8824 emit_move_insn (scratch2
, vcall_offset_rtx
);
8825 vcall_offset_rtx
= scratch2
;
8829 rtx increment
= GEN_INT (-4096);
8831 /* VCALL_OFFSET is a negative number whose typical range can be
8832 estimated as -32768..0 in 32-bit mode. In almost all cases
8833 it is therefore cheaper to emit multiple add insns than
8834 spilling and loading the constant into a register (at least
8836 while (! SPARC_SIMM13_P (vcall_offset
))
8838 emit_insn (gen_add2_insn (scratch
, increment
));
8839 vcall_offset
+= 4096;
8841 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
8844 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
8845 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
8846 gen_rtx_PLUS (Pmode
,
8848 vcall_offset_rtx
)));
8850 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
8851 emit_insn (gen_add2_insn (this_rtx
, scratch
));
8854 /* Generate a tail call to the target function. */
8855 if (! TREE_USED (function
))
8857 assemble_external (function
);
8858 TREE_USED (function
) = 1;
8860 funexp
= XEXP (DECL_RTL (function
), 0);
8862 if (flag_delayed_branch
)
8864 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8865 insn
= emit_call_insn (gen_sibcall (funexp
));
8866 SIBLING_CALL_P (insn
) = 1;
8870 /* The hoops we have to jump through in order to generate a sibcall
8871 without using delay slots... */
8872 rtx spill_reg
, spill_reg2
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
8876 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
8877 spill_reg2
= gen_rtx_REG (word_mode
, PIC_OFFSET_TABLE_REGNUM
);
8879 /* Delay emitting the PIC helper function because it needs to
8880 change the section and we are emitting assembly code. */
8881 load_pic_register (); /* clobbers %o7 */
8882 scratch
= legitimize_pic_address (funexp
, scratch
);
8885 emit_and_preserve (seq
, spill_reg
, spill_reg2
);
8887 else if (TARGET_ARCH32
)
8889 emit_insn (gen_rtx_SET (VOIDmode
,
8891 gen_rtx_HIGH (SImode
, funexp
)));
8892 emit_insn (gen_rtx_SET (VOIDmode
,
8894 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
8896 else /* TARGET_ARCH64 */
8898 switch (sparc_cmodel
)
8902 /* The destination can serve as a temporary. */
8903 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
8908 /* The destination cannot serve as a temporary. */
8909 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
8911 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
8914 emit_and_preserve (seq
, spill_reg
, 0);
8922 emit_jump_insn (gen_indirect_jump (scratch
));
8927 /* Run just enough of rest_of_compilation to get the insns emitted.
8928 There's not really enough bulk here to make other passes such as
8929 instruction scheduling worth while. Note that use_thunk calls
8930 assemble_start_function and assemble_end_function. */
8931 insn
= get_insns ();
8932 insn_locators_alloc ();
8933 shorten_branches (insn
);
8934 final_start_function (insn
, file
, 1);
8935 final (insn
, file
, 1);
8936 final_end_function ();
8938 reload_completed
= 0;
8939 epilogue_completed
= 0;
8942 /* Return true if sparc_output_mi_thunk would be able to output the
8943 assembler code for the thunk function specified by the arguments
8944 it is passed, and false otherwise. */
8946 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
8947 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
8948 HOST_WIDE_INT vcall_offset
,
8949 const_tree function ATTRIBUTE_UNUSED
)
8951 /* Bound the loop used in the default method above. */
8952 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
8955 /* How to allocate a 'struct machine_function'. */
8957 static struct machine_function
*
8958 sparc_init_machine_status (void)
8960 return GGC_CNEW (struct machine_function
);
8963 /* Locate some local-dynamic symbol still in use by this function
8964 so that we can print its name in local-dynamic base patterns. */
8967 get_some_local_dynamic_name (void)
8971 if (cfun
->machine
->some_ld_name
)
8972 return cfun
->machine
->some_ld_name
;
8974 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8976 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
8977 return cfun
->machine
->some_ld_name
;
8983 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
8988 && GET_CODE (x
) == SYMBOL_REF
8989 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
8991 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
8998 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8999 This is called from dwarf2out.c to emit call frame instructions
9000 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
9002 sparc_dwarf_handle_frame_unspec (const char *label
,
9003 rtx pattern ATTRIBUTE_UNUSED
,
9004 int index ATTRIBUTE_UNUSED
)
9006 gcc_assert (index
== UNSPECV_SAVEW
);
9007 dwarf2out_window_save (label
);
9010 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9011 We need to emit DTP-relative relocations. */
9014 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9019 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
9022 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
9027 output_addr_const (file
, x
);
9031 /* Do whatever processing is required at the end of a file. */
9034 sparc_file_end (void)
9036 /* If need to emit the special PIC helper function, do so now. */
9037 if (pic_helper_needed
)
9039 unsigned int regno
= REGNO (pic_offset_table_rtx
);
9040 const char *pic_name
= reg_names
[regno
];
9042 #ifdef DWARF2_UNWIND_INFO
9046 get_pc_thunk_name (name
, regno
);
9047 if (USE_HIDDEN_LINKONCE
)
9049 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
9050 get_identifier (name
),
9051 build_function_type (void_type_node
,
9053 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
9054 NULL_TREE
, void_type_node
);
9055 TREE_STATIC (decl
) = 1;
9056 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
9057 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
9058 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
9059 allocate_struct_function (decl
, true);
9060 current_function_decl
= decl
;
9061 init_varasm_status ();
9062 assemble_start_function (decl
, name
);
9066 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9067 switch_to_section (text_section
);
9069 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
9070 ASM_OUTPUT_LABEL (asm_out_file
, name
);
9073 #ifdef DWARF2_UNWIND_INFO
9074 do_cfi
= dwarf2out_do_cfi_asm ();
9076 fprintf (asm_out_file
, "\t.cfi_startproc\n");
9078 if (flag_delayed_branch
)
9079 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
9080 pic_name
, pic_name
);
9082 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
9083 pic_name
, pic_name
);
9084 #ifdef DWARF2_UNWIND_INFO
9086 fprintf (asm_out_file
, "\t.cfi_endproc\n");
9090 if (NEED_INDICATE_EXEC_STACK
)
9091 file_end_indicate_exec_stack ();
9094 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9095 /* Implement TARGET_MANGLE_TYPE. */
9098 sparc_mangle_type (const_tree type
)
9101 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
9102 && TARGET_LONG_DOUBLE_128
)
9105 /* For all other types, use normal C++ mangling. */
9110 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
9111 compare and swap on the word containing the byte or half-word. */
9114 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
9116 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
9117 rtx addr
= gen_reg_rtx (Pmode
);
9118 rtx off
= gen_reg_rtx (SImode
);
9119 rtx oldv
= gen_reg_rtx (SImode
);
9120 rtx newv
= gen_reg_rtx (SImode
);
9121 rtx oldvalue
= gen_reg_rtx (SImode
);
9122 rtx newvalue
= gen_reg_rtx (SImode
);
9123 rtx res
= gen_reg_rtx (SImode
);
9124 rtx resv
= gen_reg_rtx (SImode
);
9125 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
9127 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
9128 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
9130 if (Pmode
!= SImode
)
9131 addr1
= gen_lowpart (SImode
, addr1
);
9132 emit_insn (gen_rtx_SET (VOIDmode
, off
,
9133 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
9135 memsi
= gen_rtx_MEM (SImode
, addr
);
9136 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
9137 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
9139 val
= force_reg (SImode
, memsi
);
9141 emit_insn (gen_rtx_SET (VOIDmode
, off
,
9142 gen_rtx_XOR (SImode
, off
,
9143 GEN_INT (GET_MODE (mem
) == QImode
9146 emit_insn (gen_rtx_SET (VOIDmode
, off
,
9147 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
9149 if (GET_MODE (mem
) == QImode
)
9150 mask
= force_reg (SImode
, GEN_INT (0xff));
9152 mask
= force_reg (SImode
, GEN_INT (0xffff));
9154 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
9155 gen_rtx_ASHIFT (SImode
, mask
, off
)));
9157 emit_insn (gen_rtx_SET (VOIDmode
, val
,
9158 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
9161 oldval
= gen_lowpart (SImode
, oldval
);
9162 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
9163 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
9165 newval
= gen_lowpart_common (SImode
, newval
);
9166 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
9167 gen_rtx_ASHIFT (SImode
, newval
, off
)));
9169 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
9170 gen_rtx_AND (SImode
, oldv
, mask
)));
9172 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
9173 gen_rtx_AND (SImode
, newv
, mask
)));
9175 end_label
= gen_label_rtx ();
9176 loop_label
= gen_label_rtx ();
9177 emit_label (loop_label
);
9179 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
9180 gen_rtx_IOR (SImode
, oldv
, val
)));
9182 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
9183 gen_rtx_IOR (SImode
, newv
, val
)));
9185 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
9187 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
9189 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
9190 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
9193 cc
= gen_compare_reg_1 (NE
, resv
, val
);
9194 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
9196 /* Use cbranchcc4 to separate the compare and branch! */
9197 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
9198 cc
, const0_rtx
, loop_label
));
9200 emit_label (end_label
);
9202 emit_insn (gen_rtx_SET (VOIDmode
, res
,
9203 gen_rtx_AND (SImode
, res
, mask
)));
9205 emit_insn (gen_rtx_SET (VOIDmode
, res
,
9206 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
9208 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
9211 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9214 sparc_frame_pointer_required (void)
9216 return !(leaf_function_p () && only_leaf_regs_used ());
9219 /* The way this is structured, we can't eliminate SFP in favor of SP
9220 if the frame pointer is required: we want to use the SFP->HFP elimination
9221 in that case. But the test in update_eliminables doesn't know we are
9222 assuming below that we only do the former elimination. */
9225 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
9227 return (to
== HARD_FRAME_POINTER_REGNUM
9228 || !targetm
.frame_pointer_required ());
9231 #include "gt-sparc.h"