1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs
= {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs
= {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs
= {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs
= {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs
= {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs
= {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs
= {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs
= {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs
= {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
279 struct processor_costs niagara3_costs
= {
280 COSTS_N_INSNS (3), /* int load */
281 COSTS_N_INSNS (3), /* int signed load */
282 COSTS_N_INSNS (3), /* int zeroed load */
283 COSTS_N_INSNS (3), /* float load */
284 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
285 COSTS_N_INSNS (9), /* fadd, fsub */
286 COSTS_N_INSNS (9), /* fcmp */
287 COSTS_N_INSNS (9), /* fmov, fmovr */
288 COSTS_N_INSNS (9), /* fmul */
289 COSTS_N_INSNS (23), /* fdivs */
290 COSTS_N_INSNS (37), /* fdivd */
291 COSTS_N_INSNS (23), /* fsqrts */
292 COSTS_N_INSNS (37), /* fsqrtd */
293 COSTS_N_INSNS (9), /* imul */
294 COSTS_N_INSNS (9), /* imulX */
295 0, /* imul bit factor */
296 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
297 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
298 COSTS_N_INSNS (1), /* movcc/movr */
299 0, /* shift penalty */
302 const struct processor_costs
*sparc_costs
= &cypress_costs
;
304 #ifdef HAVE_AS_RELAX_OPTION
305 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
306 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
307 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
308 somebody does not branch between the sethi and jmp. */
309 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
311 #define LEAF_SIBCALL_SLOT_RESERVED_P \
312 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
315 /* Vector to say how input registers are mapped to output registers.
316 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
317 eliminate it. You must use -fomit-frame-pointer to get that. */
318 char leaf_reg_remap
[] =
319 { 0, 1, 2, 3, 4, 5, 6, 7,
320 -1, -1, -1, -1, -1, -1, 14, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1,
322 8, 9, 10, 11, 12, 13, -1, 15,
324 32, 33, 34, 35, 36, 37, 38, 39,
325 40, 41, 42, 43, 44, 45, 46, 47,
326 48, 49, 50, 51, 52, 53, 54, 55,
327 56, 57, 58, 59, 60, 61, 62, 63,
328 64, 65, 66, 67, 68, 69, 70, 71,
329 72, 73, 74, 75, 76, 77, 78, 79,
330 80, 81, 82, 83, 84, 85, 86, 87,
331 88, 89, 90, 91, 92, 93, 94, 95,
332 96, 97, 98, 99, 100, 101, 102};
334 /* Vector, indexed by hard register number, which contains 1
335 for a register that is allowable in a candidate for leaf
336 function treatment. */
337 char sparc_leaf_regs
[] =
338 { 1, 1, 1, 1, 1, 1, 1, 1,
339 0, 0, 0, 0, 0, 0, 1, 0,
340 0, 0, 0, 0, 0, 0, 0, 0,
341 1, 1, 1, 1, 1, 1, 0, 1,
342 1, 1, 1, 1, 1, 1, 1, 1,
343 1, 1, 1, 1, 1, 1, 1, 1,
344 1, 1, 1, 1, 1, 1, 1, 1,
345 1, 1, 1, 1, 1, 1, 1, 1,
346 1, 1, 1, 1, 1, 1, 1, 1,
347 1, 1, 1, 1, 1, 1, 1, 1,
348 1, 1, 1, 1, 1, 1, 1, 1,
349 1, 1, 1, 1, 1, 1, 1, 1,
350 1, 1, 1, 1, 1, 1, 1};
352 struct GTY(()) machine_function
354 /* Size of the frame of the function. */
355 HOST_WIDE_INT frame_size
;
357 /* Size of the frame of the function minus the register window save area
358 and the outgoing argument area. */
359 HOST_WIDE_INT apparent_frame_size
;
361 /* Register we pretend the frame pointer is allocated to. Normally, this
362 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
363 record "offset" separately as it may be too big for (reg + disp). */
365 HOST_WIDE_INT frame_base_offset
;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name
;
370 /* Number of global or FP registers to be saved (as 4-byte quantities). */
371 int n_global_fp_regs
;
373 /* True if the current function is leaf and uses only leaf regs,
374 so that the SPARC leaf function optimization can be applied.
375 Private version of current_function_uses_only_leaf_regs, see
376 sparc_expand_prologue for the rationale. */
379 /* True if the prologue saves local or in registers. */
380 bool save_local_in_regs_p
;
382 /* True if the data calculated by sparc_expand_prologue are valid. */
383 bool prologue_data_valid_p
;
386 #define sparc_frame_size cfun->machine->frame_size
387 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
388 #define sparc_frame_base_reg cfun->machine->frame_base_reg
389 #define sparc_frame_base_offset cfun->machine->frame_base_offset
390 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
391 #define sparc_leaf_function_p cfun->machine->leaf_function_p
392 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
393 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
395 /* 1 if the next opcode is to be specially indented. */
396 int sparc_indent_opcode
= 0;
398 static void sparc_option_override (void);
399 static void sparc_init_modes (void);
400 static void scan_record_type (const_tree
, int *, int *, int *);
401 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
402 const_tree
, bool, bool, int *, int *);
404 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
405 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
407 static void sparc_emit_set_const32 (rtx
, rtx
);
408 static void sparc_emit_set_const64 (rtx
, rtx
);
409 static void sparc_output_addr_vec (rtx
);
410 static void sparc_output_addr_diff_vec (rtx
);
411 static void sparc_output_deferred_case_vectors (void);
412 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
413 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
414 static rtx
sparc_builtin_saveregs (void);
415 static int epilogue_renumber (rtx
*, int);
416 static bool sparc_assemble_integer (rtx
, unsigned int, int);
417 static int set_extends (rtx
);
418 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
419 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
420 #ifdef TARGET_SOLARIS
421 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
422 tree
) ATTRIBUTE_UNUSED
;
424 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
425 static int sparc_issue_rate (void);
426 static void sparc_sched_init (FILE *, int, int);
427 static int sparc_use_sched_lookahead (void);
429 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
430 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
431 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
432 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
433 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
435 static bool sparc_function_ok_for_sibcall (tree
, tree
);
436 static void sparc_init_libfuncs (void);
437 static void sparc_init_builtins (void);
438 static void sparc_vis_init_builtins (void);
439 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
440 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
441 static int sparc_vis_mul8x16 (int, int);
442 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
443 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
444 HOST_WIDE_INT
, tree
);
445 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
446 HOST_WIDE_INT
, const_tree
);
447 static struct machine_function
* sparc_init_machine_status (void);
448 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
449 static rtx
sparc_tls_get_addr (void);
450 static rtx
sparc_tls_got (void);
451 static const char *get_some_local_dynamic_name (void);
452 static int get_some_local_dynamic_name_1 (rtx
*, void *);
453 static int sparc_register_move_cost (enum machine_mode
,
454 reg_class_t
, reg_class_t
);
455 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
456 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
457 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
458 static bool sparc_function_value_regno_p (const unsigned int);
459 static rtx
sparc_struct_value_rtx (tree
, int);
460 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
461 int *, const_tree
, int);
462 static bool sparc_return_in_memory (const_tree
, const_tree
);
463 static bool sparc_strict_argument_naming (cumulative_args_t
);
464 static void sparc_va_start (tree
, rtx
);
465 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
466 static bool sparc_vector_mode_supported_p (enum machine_mode
);
467 static bool sparc_tls_referenced_p (rtx
);
468 static rtx
sparc_legitimize_tls_address (rtx
);
469 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
470 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
471 static rtx
sparc_delegitimize_address (rtx
);
472 static bool sparc_mode_dependent_address_p (const_rtx
);
473 static bool sparc_pass_by_reference (cumulative_args_t
,
474 enum machine_mode
, const_tree
, bool);
475 static void sparc_function_arg_advance (cumulative_args_t
,
476 enum machine_mode
, const_tree
, bool);
477 static rtx
sparc_function_arg_1 (cumulative_args_t
,
478 enum machine_mode
, const_tree
, bool, bool);
479 static rtx
sparc_function_arg (cumulative_args_t
,
480 enum machine_mode
, const_tree
, bool);
481 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
482 enum machine_mode
, const_tree
, bool);
483 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
485 static int sparc_arg_partial_bytes (cumulative_args_t
,
486 enum machine_mode
, tree
, bool);
487 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
488 static void sparc_file_end (void);
489 static bool sparc_frame_pointer_required (void);
490 static bool sparc_can_eliminate (const int, const int);
491 static rtx
sparc_builtin_setjmp_frame_value (void);
492 static void sparc_conditional_register_usage (void);
493 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
494 static const char *sparc_mangle_type (const_tree
);
496 static void sparc_trampoline_init (rtx
, tree
, rtx
);
497 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
498 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
499 static bool sparc_print_operand_punct_valid_p (unsigned char);
500 static void sparc_print_operand (FILE *, rtx
, int);
501 static void sparc_print_operand_address (FILE *, rtx
);
503 #ifdef SUBTARGET_ATTRIBUTE_TABLE
504 /* Table of valid machine attributes. */
505 static const struct attribute_spec sparc_attribute_table
[] =
507 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
509 SUBTARGET_ATTRIBUTE_TABLE
,
510 { NULL
, 0, 0, false, false, false, NULL
, false }
514 /* Option handling. */
517 enum cmodel sparc_cmodel
;
519 char sparc_hard_reg_printed
[8];
521 /* Initialize the GCC target structure. */
523 /* The default is to use .half rather than .short for aligned HI objects. */
524 #undef TARGET_ASM_ALIGNED_HI_OP
525 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
527 #undef TARGET_ASM_UNALIGNED_HI_OP
528 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
529 #undef TARGET_ASM_UNALIGNED_SI_OP
530 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
531 #undef TARGET_ASM_UNALIGNED_DI_OP
532 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
534 /* The target hook has to handle DI-mode values. */
535 #undef TARGET_ASM_INTEGER
536 #define TARGET_ASM_INTEGER sparc_assemble_integer
538 #undef TARGET_ASM_FUNCTION_PROLOGUE
539 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
540 #undef TARGET_ASM_FUNCTION_EPILOGUE
541 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
543 #undef TARGET_SCHED_ADJUST_COST
544 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
545 #undef TARGET_SCHED_ISSUE_RATE
546 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
547 #undef TARGET_SCHED_INIT
548 #define TARGET_SCHED_INIT sparc_sched_init
549 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
550 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
552 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
553 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
555 #undef TARGET_INIT_LIBFUNCS
556 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
557 #undef TARGET_INIT_BUILTINS
558 #define TARGET_INIT_BUILTINS sparc_init_builtins
560 #undef TARGET_LEGITIMIZE_ADDRESS
561 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
562 #undef TARGET_DELEGITIMIZE_ADDRESS
563 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
564 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
565 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
567 #undef TARGET_EXPAND_BUILTIN
568 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
569 #undef TARGET_FOLD_BUILTIN
570 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
573 #undef TARGET_HAVE_TLS
574 #define TARGET_HAVE_TLS true
577 #undef TARGET_CANNOT_FORCE_CONST_MEM
578 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
580 #undef TARGET_ASM_OUTPUT_MI_THUNK
581 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
582 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
583 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
585 #undef TARGET_RTX_COSTS
586 #define TARGET_RTX_COSTS sparc_rtx_costs
587 #undef TARGET_ADDRESS_COST
588 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
589 #undef TARGET_REGISTER_MOVE_COST
590 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
592 #undef TARGET_PROMOTE_FUNCTION_MODE
593 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
595 #undef TARGET_FUNCTION_VALUE
596 #define TARGET_FUNCTION_VALUE sparc_function_value
597 #undef TARGET_LIBCALL_VALUE
598 #define TARGET_LIBCALL_VALUE sparc_libcall_value
599 #undef TARGET_FUNCTION_VALUE_REGNO_P
600 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
602 #undef TARGET_STRUCT_VALUE_RTX
603 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
604 #undef TARGET_RETURN_IN_MEMORY
605 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
606 #undef TARGET_MUST_PASS_IN_STACK
607 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
608 #undef TARGET_PASS_BY_REFERENCE
609 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
610 #undef TARGET_ARG_PARTIAL_BYTES
611 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
612 #undef TARGET_FUNCTION_ARG_ADVANCE
613 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
614 #undef TARGET_FUNCTION_ARG
615 #define TARGET_FUNCTION_ARG sparc_function_arg
616 #undef TARGET_FUNCTION_INCOMING_ARG
617 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
618 #undef TARGET_FUNCTION_ARG_BOUNDARY
619 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
621 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
622 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
623 #undef TARGET_STRICT_ARGUMENT_NAMING
624 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
626 #undef TARGET_EXPAND_BUILTIN_VA_START
627 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
628 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
629 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
631 #undef TARGET_VECTOR_MODE_SUPPORTED_P
632 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
634 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
635 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
637 #ifdef SUBTARGET_INSERT_ATTRIBUTES
638 #undef TARGET_INSERT_ATTRIBUTES
639 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
642 #ifdef SUBTARGET_ATTRIBUTE_TABLE
643 #undef TARGET_ATTRIBUTE_TABLE
644 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
647 #undef TARGET_RELAXED_ORDERING
648 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
650 #undef TARGET_OPTION_OVERRIDE
651 #define TARGET_OPTION_OVERRIDE sparc_option_override
653 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
654 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
655 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
658 #undef TARGET_ASM_FILE_END
659 #define TARGET_ASM_FILE_END sparc_file_end
661 #undef TARGET_FRAME_POINTER_REQUIRED
662 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
664 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
665 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
667 #undef TARGET_CAN_ELIMINATE
668 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
670 #undef TARGET_PREFERRED_RELOAD_CLASS
671 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
673 #undef TARGET_CONDITIONAL_REGISTER_USAGE
674 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
676 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
677 #undef TARGET_MANGLE_TYPE
678 #define TARGET_MANGLE_TYPE sparc_mangle_type
681 #undef TARGET_LEGITIMATE_ADDRESS_P
682 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
684 #undef TARGET_LEGITIMATE_CONSTANT_P
685 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
687 #undef TARGET_TRAMPOLINE_INIT
688 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
690 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
691 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
692 #undef TARGET_PRINT_OPERAND
693 #define TARGET_PRINT_OPERAND sparc_print_operand
694 #undef TARGET_PRINT_OPERAND_ADDRESS
695 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
697 struct gcc_target targetm
= TARGET_INITIALIZER
;
699 /* Validate and override various options, and do some machine dependent
703 sparc_option_override (void)
705 static struct code_model
{
706 const char *const name
;
707 const enum cmodel value
;
708 } const cmodels
[] = {
710 { "medlow", CM_MEDLOW
},
711 { "medmid", CM_MEDMID
},
712 { "medany", CM_MEDANY
},
713 { "embmedany", CM_EMBMEDANY
},
714 { NULL
, (enum cmodel
) 0 }
716 const struct code_model
*cmodel
;
717 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
718 static struct cpu_default
{
720 const enum processor_type processor
;
721 } const cpu_default
[] = {
722 /* There must be one entry here for each TARGET_CPU value. */
723 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
724 { TARGET_CPU_v8
, PROCESSOR_V8
},
725 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
726 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
727 { TARGET_CPU_leon
, PROCESSOR_LEON
},
728 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
729 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
730 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
731 { TARGET_CPU_v9
, PROCESSOR_V9
},
732 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
733 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
734 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
735 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
736 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
737 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
740 const struct cpu_default
*def
;
741 /* Table of values for -m{cpu,tune}=. This must match the order of
742 the PROCESSOR_* enumeration. */
743 static struct cpu_table
{
746 } const cpu_table
[] = {
749 { MASK_ISA
, MASK_V8
},
750 /* TI TMS390Z55 supersparc */
751 { MASK_ISA
, MASK_V8
},
752 { MASK_ISA
, MASK_V8
|MASK_FPU
},
754 { MASK_ISA
, MASK_V8
|MASK_FPU
},
755 { MASK_ISA
, MASK_SPARCLITE
},
756 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
757 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
758 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
759 { MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
760 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
761 { MASK_ISA
, MASK_SPARCLET
},
763 { MASK_ISA
, MASK_SPARCLET
},
764 { MASK_ISA
, MASK_V9
},
765 /* UltraSPARC I, II, IIi */
767 /* Although insns using %y are deprecated, it is a clear win. */
768 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
770 /* ??? Check if %y issue still holds true. */
772 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
775 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
777 { MASK_ISA
, MASK_V9
|MASK_VIS2
},
779 { MASK_ISA
, MASK_V9
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
781 { MASK_ISA
, MASK_V9
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
783 const struct cpu_table
*cpu
;
787 #ifdef SUBTARGET_OVERRIDE_OPTIONS
788 SUBTARGET_OVERRIDE_OPTIONS
;
791 #ifndef SPARC_BI_ARCH
792 /* Check for unsupported architecture size. */
793 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
794 error ("%s is not supported by this configuration",
795 DEFAULT_ARCH32_P
? "-m64" : "-m32");
798 /* We force all 64bit archs to use 128 bit long double */
799 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
801 error ("-mlong-double-64 not allowed with -m64");
802 target_flags
|= MASK_LONG_DOUBLE_128
;
805 /* Code model selection. */
806 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
810 sparc_cmodel
= CM_32
;
813 if (sparc_cmodel_string
!= NULL
)
817 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
818 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
820 if (cmodel
->name
== NULL
)
821 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
823 sparc_cmodel
= cmodel
->value
;
826 error ("-mcmodel= is not supported on 32 bit systems");
829 /* Check that -fcall-saved-REG wasn't specified for out registers. */
830 for (i
= 8; i
< 16; i
++)
831 if (!call_used_regs
[i
])
833 error ("-fcall-saved-REG is not supported for out registers");
834 call_used_regs
[i
] = 1;
837 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
839 /* Set the default CPU. */
840 if (!global_options_set
.x_sparc_cpu_and_features
)
842 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
843 if (def
->cpu
== TARGET_CPU_DEFAULT
)
845 gcc_assert (def
->cpu
!= -1);
846 sparc_cpu_and_features
= def
->processor
;
848 if (!global_options_set
.x_sparc_cpu
)
849 sparc_cpu
= sparc_cpu_and_features
;
851 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
852 target_flags
&= ~cpu
->disable
;
853 target_flags
|= cpu
->enable
;
855 /* If -mfpu or -mno-fpu was explicitly used, don't override with
856 the processor default. */
857 if (target_flags_explicit
& MASK_FPU
)
858 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
860 /* -mvis2 implies -mvis */
862 target_flags
|= MASK_VIS
;
864 /* -mvis3 implies -mvis2 and -mvis */
866 target_flags
|= MASK_VIS2
| MASK_VIS
;
868 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
870 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_FMAF
);
872 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
874 -m64 also implies v9. */
875 if (TARGET_VIS
|| TARGET_ARCH64
)
877 target_flags
|= MASK_V9
;
878 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
881 /* -mvis also implies -mv8plus on 32-bit */
882 if (TARGET_VIS
&& ! TARGET_ARCH64
)
883 target_flags
|= MASK_V8PLUS
;
885 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
886 if (TARGET_V9
&& TARGET_ARCH32
)
887 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
889 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
890 if (! TARGET_V9
|| TARGET_ARCH64
)
891 target_flags
&= ~MASK_V8PLUS
;
893 /* Don't use stack biasing in 32 bit mode. */
895 target_flags
&= ~MASK_STACK_BIAS
;
897 /* Supply a default value for align_functions. */
898 if (align_functions
== 0
899 && (sparc_cpu
== PROCESSOR_ULTRASPARC
900 || sparc_cpu
== PROCESSOR_ULTRASPARC3
901 || sparc_cpu
== PROCESSOR_NIAGARA
902 || sparc_cpu
== PROCESSOR_NIAGARA2
903 || sparc_cpu
== PROCESSOR_NIAGARA3
904 || sparc_cpu
== PROCESSOR_NIAGARA4
))
905 align_functions
= 32;
907 /* Validate PCC_STRUCT_RETURN. */
908 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
909 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
911 /* Only use .uaxword when compiling for a 64-bit target. */
913 targetm
.asm_out
.unaligned_op
.di
= NULL
;
915 /* Do various machine dependent initializations. */
918 /* Set up function hooks. */
919 init_machine_status
= sparc_init_machine_status
;
924 case PROCESSOR_CYPRESS
:
925 sparc_costs
= &cypress_costs
;
928 case PROCESSOR_SPARCLITE
:
929 case PROCESSOR_SUPERSPARC
:
930 sparc_costs
= &supersparc_costs
;
934 case PROCESSOR_HYPERSPARC
:
935 case PROCESSOR_SPARCLITE86X
:
936 sparc_costs
= &hypersparc_costs
;
939 sparc_costs
= &leon_costs
;
941 case PROCESSOR_SPARCLET
:
942 case PROCESSOR_TSC701
:
943 sparc_costs
= &sparclet_costs
;
946 case PROCESSOR_ULTRASPARC
:
947 sparc_costs
= &ultrasparc_costs
;
949 case PROCESSOR_ULTRASPARC3
:
950 sparc_costs
= &ultrasparc3_costs
;
952 case PROCESSOR_NIAGARA
:
953 sparc_costs
= &niagara_costs
;
955 case PROCESSOR_NIAGARA2
:
956 sparc_costs
= &niagara2_costs
;
958 case PROCESSOR_NIAGARA3
:
959 case PROCESSOR_NIAGARA4
:
960 sparc_costs
= &niagara3_costs
;
962 case PROCESSOR_NATIVE
:
966 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
967 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
968 target_flags
|= MASK_LONG_DOUBLE_128
;
971 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
972 ((sparc_cpu
== PROCESSOR_ULTRASPARC
973 || sparc_cpu
== PROCESSOR_NIAGARA
974 || sparc_cpu
== PROCESSOR_NIAGARA2
975 || sparc_cpu
== PROCESSOR_NIAGARA3
976 || sparc_cpu
== PROCESSOR_NIAGARA4
)
978 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
980 global_options
.x_param_values
,
981 global_options_set
.x_param_values
);
982 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
983 ((sparc_cpu
== PROCESSOR_ULTRASPARC
984 || sparc_cpu
== PROCESSOR_ULTRASPARC3
985 || sparc_cpu
== PROCESSOR_NIAGARA
986 || sparc_cpu
== PROCESSOR_NIAGARA2
987 || sparc_cpu
== PROCESSOR_NIAGARA3
988 || sparc_cpu
== PROCESSOR_NIAGARA4
)
990 global_options
.x_param_values
,
991 global_options_set
.x_param_values
);
993 /* Disable save slot sharing for call-clobbered registers by default.
994 The IRA sharing algorithm works on single registers only and this
995 pessimizes for double floating-point registers. */
996 if (!global_options_set
.x_flag_ira_share_save_slots
)
997 flag_ira_share_save_slots
= 0;
1000 /* Miscellaneous utilities. */
1002 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1003 or branch on register contents instructions. */
1006 v9_regcmp_p (enum rtx_code code
)
1008 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1009 || code
== LE
|| code
== GT
);
1012 /* Nonzero if OP is a floating point constant which can
1013 be loaded into an integer register using a single
1014 sethi instruction. */
1019 if (GET_CODE (op
) == CONST_DOUBLE
)
1024 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1025 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1026 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1032 /* Nonzero if OP is a floating point constant which can
1033 be loaded into an integer register using a single
1039 if (GET_CODE (op
) == CONST_DOUBLE
)
1044 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1045 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1046 return SPARC_SIMM13_P (i
);
1052 /* Nonzero if OP is a floating point constant which can
1053 be loaded into an integer register using a high/losum
1054 instruction sequence. */
1057 fp_high_losum_p (rtx op
)
1059 /* The constraints calling this should only be in
1060 SFmode move insns, so any constant which cannot
1061 be moved using a single insn will do. */
1062 if (GET_CODE (op
) == CONST_DOUBLE
)
1067 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1068 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1069 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1075 /* Return true if the address of LABEL can be loaded by means of the
1076 mov{si,di}_pic_label_ref patterns in PIC mode. */
1079 can_use_mov_pic_label_ref (rtx label
)
1081 /* VxWorks does not impose a fixed gap between segments; the run-time
1082 gap can be different from the object-file gap. We therefore can't
1083 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1084 are absolutely sure that X is in the same segment as the GOT.
1085 Unfortunately, the flexibility of linker scripts means that we
1086 can't be sure of that in general, so assume that GOT-relative
1087 accesses are never valid on VxWorks. */
1088 if (TARGET_VXWORKS_RTP
)
1091 /* Similarly, if the label is non-local, it might end up being placed
1092 in a different section than the current one; now mov_pic_label_ref
1093 requires the label and the code to be in the same section. */
1094 if (LABEL_REF_NONLOCAL_P (label
))
1097 /* Finally, if we are reordering basic blocks and partition into hot
1098 and cold sections, this might happen for any label. */
1099 if (flag_reorder_blocks_and_partition
)
1105 /* Expand a move instruction. Return true if all work is done. */
1108 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1110 /* Handle sets of MEM first. */
1111 if (GET_CODE (operands
[0]) == MEM
)
1113 /* 0 is a register (or a pair of registers) on SPARC. */
1114 if (register_or_zero_operand (operands
[1], mode
))
1117 if (!reload_in_progress
)
1119 operands
[0] = validize_mem (operands
[0]);
1120 operands
[1] = force_reg (mode
, operands
[1]);
1124 /* Fixup TLS cases. */
1126 && CONSTANT_P (operands
[1])
1127 && sparc_tls_referenced_p (operands
[1]))
1129 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1133 /* Fixup PIC cases. */
1134 if (flag_pic
&& CONSTANT_P (operands
[1]))
1136 if (pic_address_needs_scratch (operands
[1]))
1137 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1139 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1140 if (GET_CODE (operands
[1]) == LABEL_REF
1141 && can_use_mov_pic_label_ref (operands
[1]))
1145 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1151 gcc_assert (TARGET_ARCH64
);
1152 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1157 if (symbolic_operand (operands
[1], mode
))
1160 = sparc_legitimize_pic_address (operands
[1],
1162 ? operands
[0] : NULL_RTX
);
1167 /* If we are trying to toss an integer constant into FP registers,
1168 or loading a FP or vector constant, force it into memory. */
1169 if (CONSTANT_P (operands
[1])
1170 && REG_P (operands
[0])
1171 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1172 || SCALAR_FLOAT_MODE_P (mode
)
1173 || VECTOR_MODE_P (mode
)))
1175 /* emit_group_store will send such bogosity to us when it is
1176 not storing directly into memory. So fix this up to avoid
1177 crashes in output_constant_pool. */
1178 if (operands
[1] == const0_rtx
)
1179 operands
[1] = CONST0_RTX (mode
);
1181 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1182 always other regs. */
1183 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1184 && (const_zero_operand (operands
[1], mode
)
1185 || const_all_ones_operand (operands
[1], mode
)))
1188 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1189 /* We are able to build any SF constant in integer registers
1190 with at most 2 instructions. */
1192 /* And any DF constant in integer registers. */
1194 && (reload_completed
|| reload_in_progress
))))
1197 operands
[1] = force_const_mem (mode
, operands
[1]);
1198 if (!reload_in_progress
)
1199 operands
[1] = validize_mem (operands
[1]);
1203 /* Accept non-constants and valid constants unmodified. */
1204 if (!CONSTANT_P (operands
[1])
1205 || GET_CODE (operands
[1]) == HIGH
1206 || input_operand (operands
[1], mode
))
1212 /* All QImode constants require only one insn, so proceed. */
1217 sparc_emit_set_const32 (operands
[0], operands
[1]);
1221 /* input_operand should have filtered out 32-bit mode. */
1222 sparc_emit_set_const64 (operands
[0], operands
[1]);
1232 /* Load OP1, a 32-bit constant, into OP0, a register.
1233 We know it can't be done in one insn when we get
1234 here, the move expander guarantees this. */
1237 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1239 enum machine_mode mode
= GET_MODE (op0
);
1242 if (reload_in_progress
|| reload_completed
)
1245 temp
= gen_reg_rtx (mode
);
1247 if (GET_CODE (op1
) == CONST_INT
)
1249 gcc_assert (!small_int_operand (op1
, mode
)
1250 && !const_high_operand (op1
, mode
));
1252 /* Emit them as real moves instead of a HIGH/LO_SUM,
1253 this way CSE can see everything and reuse intermediate
1254 values if it wants. */
1255 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1256 GEN_INT (INTVAL (op1
)
1257 & ~(HOST_WIDE_INT
)0x3ff)));
1259 emit_insn (gen_rtx_SET (VOIDmode
,
1261 gen_rtx_IOR (mode
, temp
,
1262 GEN_INT (INTVAL (op1
) & 0x3ff))));
1266 /* A symbol, emit in the traditional way. */
1267 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1268 gen_rtx_HIGH (mode
, op1
)));
1269 emit_insn (gen_rtx_SET (VOIDmode
,
1270 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1274 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1275 If TEMP is nonzero, we are forbidden to use any other scratch
1276 registers. Otherwise, we are allowed to generate them as needed.
1278 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1279 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1282 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1284 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1287 if (temp
&& GET_MODE (temp
) == TImode
)
1290 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1293 /* SPARC-V9 code-model support. */
1294 switch (sparc_cmodel
)
1297 /* The range spanned by all instructions in the object is less
1298 than 2^31 bytes (2GB) and the distance from any instruction
1299 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1300 than 2^31 bytes (2GB).
1302 The executable must be in the low 4TB of the virtual address
1305 sethi %hi(symbol), %temp1
1306 or %temp1, %lo(symbol), %reg */
1308 temp1
= temp
; /* op0 is allowed. */
1310 temp1
= gen_reg_rtx (DImode
);
1312 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1313 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1317 /* The range spanned by all instructions in the object is less
1318 than 2^31 bytes (2GB) and the distance from any instruction
1319 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1320 than 2^31 bytes (2GB).
1322 The executable must be in the low 16TB of the virtual address
1325 sethi %h44(symbol), %temp1
1326 or %temp1, %m44(symbol), %temp2
1327 sllx %temp2, 12, %temp3
1328 or %temp3, %l44(symbol), %reg */
1333 temp3
= temp
; /* op0 is allowed. */
1337 temp1
= gen_reg_rtx (DImode
);
1338 temp2
= gen_reg_rtx (DImode
);
1339 temp3
= gen_reg_rtx (DImode
);
1342 emit_insn (gen_seth44 (temp1
, op1
));
1343 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1344 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1345 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1346 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1350 /* The range spanned by all instructions in the object is less
1351 than 2^31 bytes (2GB) and the distance from any instruction
1352 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1353 than 2^31 bytes (2GB).
1355 The executable can be placed anywhere in the virtual address
1358 sethi %hh(symbol), %temp1
1359 sethi %lm(symbol), %temp2
1360 or %temp1, %hm(symbol), %temp3
1361 sllx %temp3, 32, %temp4
1362 or %temp4, %temp2, %temp5
1363 or %temp5, %lo(symbol), %reg */
1366 /* It is possible that one of the registers we got for operands[2]
1367 might coincide with that of operands[0] (which is why we made
1368 it TImode). Pick the other one to use as our scratch. */
1369 if (rtx_equal_p (temp
, op0
))
1371 gcc_assert (ti_temp
);
1372 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1375 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1382 temp1
= gen_reg_rtx (DImode
);
1383 temp2
= gen_reg_rtx (DImode
);
1384 temp3
= gen_reg_rtx (DImode
);
1385 temp4
= gen_reg_rtx (DImode
);
1386 temp5
= gen_reg_rtx (DImode
);
1389 emit_insn (gen_sethh (temp1
, op1
));
1390 emit_insn (gen_setlm (temp2
, op1
));
1391 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1392 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1393 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1394 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1395 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1396 emit_insn (gen_setlo (op0
, temp5
, op1
));
1400 /* Old old old backwards compatibility kruft here.
1401 Essentially it is MEDLOW with a fixed 64-bit
1402 virtual base added to all data segment addresses.
1403 Text-segment stuff is computed like MEDANY, we can't
1404 reuse the code above because the relocation knobs
1407 Data segment: sethi %hi(symbol), %temp1
1408 add %temp1, EMBMEDANY_BASE_REG, %temp2
1409 or %temp2, %lo(symbol), %reg */
1410 if (data_segment_operand (op1
, GET_MODE (op1
)))
1414 temp1
= temp
; /* op0 is allowed. */
1419 temp1
= gen_reg_rtx (DImode
);
1420 temp2
= gen_reg_rtx (DImode
);
1423 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1424 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1425 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1428 /* Text segment: sethi %uhi(symbol), %temp1
1429 sethi %hi(symbol), %temp2
1430 or %temp1, %ulo(symbol), %temp3
1431 sllx %temp3, 32, %temp4
1432 or %temp4, %temp2, %temp5
1433 or %temp5, %lo(symbol), %reg */
1438 /* It is possible that one of the registers we got for operands[2]
1439 might coincide with that of operands[0] (which is why we made
1440 it TImode). Pick the other one to use as our scratch. */
1441 if (rtx_equal_p (temp
, op0
))
1443 gcc_assert (ti_temp
);
1444 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1447 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1454 temp1
= gen_reg_rtx (DImode
);
1455 temp2
= gen_reg_rtx (DImode
);
1456 temp3
= gen_reg_rtx (DImode
);
1457 temp4
= gen_reg_rtx (DImode
);
1458 temp5
= gen_reg_rtx (DImode
);
1461 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1462 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1463 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1464 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1465 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1466 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1467 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1468 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1477 #if HOST_BITS_PER_WIDE_INT == 32
1479 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1484 /* These avoid problems when cross compiling. If we do not
1485 go through all this hair then the optimizer will see
1486 invalid REG_EQUAL notes or in some cases none at all. */
1487 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1488 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1489 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1490 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1492 /* The optimizer is not to assume anything about exactly
1493 which bits are set for a HIGH, they are unspecified.
1494 Unfortunately this leads to many missed optimizations
1495 during CSE. We mask out the non-HIGH bits, and matches
1496 a plain movdi, to alleviate this problem. */
1498 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1500 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1504 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1506 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1510 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1512 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1516 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1518 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1521 /* Worker routines for 64-bit constant formation on arch64.
1522 One of the key things to be doing in these emissions is
1523 to create as many temp REGs as possible. This makes it
1524 possible for half-built constants to be used later when
1525 such values are similar to something required later on.
1526 Without doing this, the optimizer cannot see such
1529 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1530 unsigned HOST_WIDE_INT
, int);
1533 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1534 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1536 unsigned HOST_WIDE_INT high_bits
;
1539 high_bits
= (~low_bits
) & 0xffffffff;
1541 high_bits
= low_bits
;
1543 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1546 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1547 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1551 /* If we are XOR'ing with -1, then we should emit a one's complement
1552 instead. This way the combiner will notice logical operations
1553 such as ANDN later on and substitute. */
1554 if ((low_bits
& 0x3ff) == 0x3ff)
1556 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1557 gen_rtx_NOT (DImode
, temp
)));
1561 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1562 gen_safe_XOR64 (temp
,
1563 (-(HOST_WIDE_INT
)0x400
1564 | (low_bits
& 0x3ff)))));
1569 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1570 unsigned HOST_WIDE_INT
, int);
1573 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1574 unsigned HOST_WIDE_INT high_bits
,
1575 unsigned HOST_WIDE_INT low_immediate
,
1580 if ((high_bits
& 0xfffffc00) != 0)
1582 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1583 if ((high_bits
& ~0xfffffc00) != 0)
1584 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1585 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1591 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1595 /* Now shift it up into place. */
1596 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1597 gen_rtx_ASHIFT (DImode
, temp2
,
1598 GEN_INT (shift_count
))));
1600 /* If there is a low immediate part piece, finish up by
1601 putting that in as well. */
1602 if (low_immediate
!= 0)
1603 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1604 gen_safe_OR64 (op0
, low_immediate
)));
1607 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1608 unsigned HOST_WIDE_INT
);
1610 /* Full 64-bit constant decomposition. Even though this is the
1611 'worst' case, we still optimize a few things away. */
1613 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1614 unsigned HOST_WIDE_INT high_bits
,
1615 unsigned HOST_WIDE_INT low_bits
)
1619 if (reload_in_progress
|| reload_completed
)
1622 sub_temp
= gen_reg_rtx (DImode
);
1624 if ((high_bits
& 0xfffffc00) != 0)
1626 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1627 if ((high_bits
& ~0xfffffc00) != 0)
1628 emit_insn (gen_rtx_SET (VOIDmode
,
1630 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1636 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1640 if (!reload_in_progress
&& !reload_completed
)
1642 rtx temp2
= gen_reg_rtx (DImode
);
1643 rtx temp3
= gen_reg_rtx (DImode
);
1644 rtx temp4
= gen_reg_rtx (DImode
);
1646 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1647 gen_rtx_ASHIFT (DImode
, sub_temp
,
1650 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1651 if ((low_bits
& ~0xfffffc00) != 0)
1653 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1654 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1655 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1656 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1660 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1661 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1666 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1667 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1668 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1671 /* We are in the middle of reload, so this is really
1672 painful. However we do still make an attempt to
1673 avoid emitting truly stupid code. */
1674 if (low1
!= const0_rtx
)
1676 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1677 gen_rtx_ASHIFT (DImode
, sub_temp
,
1678 GEN_INT (to_shift
))));
1679 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1680 gen_rtx_IOR (DImode
, op0
, low1
)));
1688 if (low2
!= const0_rtx
)
1690 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1691 gen_rtx_ASHIFT (DImode
, sub_temp
,
1692 GEN_INT (to_shift
))));
1693 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1694 gen_rtx_IOR (DImode
, op0
, low2
)));
1702 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1703 gen_rtx_ASHIFT (DImode
, sub_temp
,
1704 GEN_INT (to_shift
))));
1705 if (low3
!= const0_rtx
)
1706 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1707 gen_rtx_IOR (DImode
, op0
, low3
)));
1712 /* Analyze a 64-bit constant for certain properties. */
1713 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1714 unsigned HOST_WIDE_INT
,
1715 int *, int *, int *);
1718 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1719 unsigned HOST_WIDE_INT low_bits
,
1720 int *hbsp
, int *lbsp
, int *abbasp
)
1722 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1725 lowest_bit_set
= highest_bit_set
= -1;
1729 if ((lowest_bit_set
== -1)
1730 && ((low_bits
>> i
) & 1))
1732 if ((highest_bit_set
== -1)
1733 && ((high_bits
>> (32 - i
- 1)) & 1))
1734 highest_bit_set
= (64 - i
- 1);
1737 && ((highest_bit_set
== -1)
1738 || (lowest_bit_set
== -1)));
1744 if ((lowest_bit_set
== -1)
1745 && ((high_bits
>> i
) & 1))
1746 lowest_bit_set
= i
+ 32;
1747 if ((highest_bit_set
== -1)
1748 && ((low_bits
>> (32 - i
- 1)) & 1))
1749 highest_bit_set
= 32 - i
- 1;
1752 && ((highest_bit_set
== -1)
1753 || (lowest_bit_set
== -1)));
1755 /* If there are no bits set this should have gone out
1756 as one instruction! */
1757 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1758 all_bits_between_are_set
= 1;
1759 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1763 if ((low_bits
& (1 << i
)) != 0)
1768 if ((high_bits
& (1 << (i
- 32))) != 0)
1771 all_bits_between_are_set
= 0;
1774 *hbsp
= highest_bit_set
;
1775 *lbsp
= lowest_bit_set
;
1776 *abbasp
= all_bits_between_are_set
;
1779 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1782 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1783 unsigned HOST_WIDE_INT low_bits
)
1785 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1788 || high_bits
== 0xffffffff)
1791 analyze_64bit_constant (high_bits
, low_bits
,
1792 &highest_bit_set
, &lowest_bit_set
,
1793 &all_bits_between_are_set
);
1795 if ((highest_bit_set
== 63
1796 || lowest_bit_set
== 0)
1797 && all_bits_between_are_set
!= 0)
1800 if ((highest_bit_set
- lowest_bit_set
) < 21)
1806 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1807 unsigned HOST_WIDE_INT
,
1810 static unsigned HOST_WIDE_INT
1811 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1812 unsigned HOST_WIDE_INT low_bits
,
1813 int lowest_bit_set
, int shift
)
1815 HOST_WIDE_INT hi
, lo
;
1817 if (lowest_bit_set
< 32)
1819 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1820 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1825 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1827 gcc_assert (! (hi
& lo
));
1831 /* Here we are sure to be arch64 and this is an integer constant
1832 being loaded into a register. Emit the most efficient
1833 insn sequence possible. Detection of all the 1-insn cases
1834 has been done already. */
1836 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1838 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1839 int lowest_bit_set
, highest_bit_set
;
1840 int all_bits_between_are_set
;
1843 /* Sanity check that we know what we are working with. */
1844 gcc_assert (TARGET_ARCH64
1845 && (GET_CODE (op0
) == SUBREG
1846 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1848 if (reload_in_progress
|| reload_completed
)
1851 if (GET_CODE (op1
) != CONST_INT
)
1853 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1858 temp
= gen_reg_rtx (DImode
);
1860 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1861 low_bits
= (INTVAL (op1
) & 0xffffffff);
1863 /* low_bits bits 0 --> 31
1864 high_bits bits 32 --> 63 */
1866 analyze_64bit_constant (high_bits
, low_bits
,
1867 &highest_bit_set
, &lowest_bit_set
,
1868 &all_bits_between_are_set
);
1870 /* First try for a 2-insn sequence. */
1872 /* These situations are preferred because the optimizer can
1873 * do more things with them:
1875 * sllx %reg, shift, %reg
1877 * srlx %reg, shift, %reg
1878 * 3) mov some_small_const, %reg
1879 * sllx %reg, shift, %reg
1881 if (((highest_bit_set
== 63
1882 || lowest_bit_set
== 0)
1883 && all_bits_between_are_set
!= 0)
1884 || ((highest_bit_set
- lowest_bit_set
) < 12))
1886 HOST_WIDE_INT the_const
= -1;
1887 int shift
= lowest_bit_set
;
1889 if ((highest_bit_set
!= 63
1890 && lowest_bit_set
!= 0)
1891 || all_bits_between_are_set
== 0)
1894 create_simple_focus_bits (high_bits
, low_bits
,
1897 else if (lowest_bit_set
== 0)
1898 shift
= -(63 - highest_bit_set
);
1900 gcc_assert (SPARC_SIMM13_P (the_const
));
1901 gcc_assert (shift
!= 0);
1903 emit_insn (gen_safe_SET64 (temp
, the_const
));
1905 emit_insn (gen_rtx_SET (VOIDmode
,
1907 gen_rtx_ASHIFT (DImode
,
1911 emit_insn (gen_rtx_SET (VOIDmode
,
1913 gen_rtx_LSHIFTRT (DImode
,
1915 GEN_INT (-shift
))));
1919 /* Now a range of 22 or less bits set somewhere.
1920 * 1) sethi %hi(focus_bits), %reg
1921 * sllx %reg, shift, %reg
1922 * 2) sethi %hi(focus_bits), %reg
1923 * srlx %reg, shift, %reg
1925 if ((highest_bit_set
- lowest_bit_set
) < 21)
1927 unsigned HOST_WIDE_INT focus_bits
=
1928 create_simple_focus_bits (high_bits
, low_bits
,
1929 lowest_bit_set
, 10);
1931 gcc_assert (SPARC_SETHI_P (focus_bits
));
1932 gcc_assert (lowest_bit_set
!= 10);
1934 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1936 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1937 if (lowest_bit_set
< 10)
1938 emit_insn (gen_rtx_SET (VOIDmode
,
1940 gen_rtx_LSHIFTRT (DImode
, temp
,
1941 GEN_INT (10 - lowest_bit_set
))));
1942 else if (lowest_bit_set
> 10)
1943 emit_insn (gen_rtx_SET (VOIDmode
,
1945 gen_rtx_ASHIFT (DImode
, temp
,
1946 GEN_INT (lowest_bit_set
- 10))));
1950 /* 1) sethi %hi(low_bits), %reg
1951 * or %reg, %lo(low_bits), %reg
1952 * 2) sethi %hi(~low_bits), %reg
1953 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1956 || high_bits
== 0xffffffff)
1958 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1959 (high_bits
== 0xffffffff));
1963 /* Now, try 3-insn sequences. */
1965 /* 1) sethi %hi(high_bits), %reg
1966 * or %reg, %lo(high_bits), %reg
1967 * sllx %reg, 32, %reg
1971 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1975 /* We may be able to do something quick
1976 when the constant is negated, so try that. */
1977 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1978 (~low_bits
) & 0xfffffc00))
1980 /* NOTE: The trailing bits get XOR'd so we need the
1981 non-negated bits, not the negated ones. */
1982 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1984 if ((((~high_bits
) & 0xffffffff) == 0
1985 && ((~low_bits
) & 0x80000000) == 0)
1986 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1987 && ((~low_bits
) & 0x80000000) != 0))
1989 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1991 if ((SPARC_SETHI_P (fast_int
)
1992 && (~high_bits
& 0xffffffff) == 0)
1993 || SPARC_SIMM13_P (fast_int
))
1994 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1996 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2001 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2002 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2003 sparc_emit_set_const64 (temp
, negated_const
);
2006 /* If we are XOR'ing with -1, then we should emit a one's complement
2007 instead. This way the combiner will notice logical operations
2008 such as ANDN later on and substitute. */
2009 if (trailing_bits
== 0x3ff)
2011 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2012 gen_rtx_NOT (DImode
, temp
)));
2016 emit_insn (gen_rtx_SET (VOIDmode
,
2018 gen_safe_XOR64 (temp
,
2019 (-0x400 | trailing_bits
))));
2024 /* 1) sethi %hi(xxx), %reg
2025 * or %reg, %lo(xxx), %reg
2026 * sllx %reg, yyy, %reg
2028 * ??? This is just a generalized version of the low_bits==0
2029 * thing above, FIXME...
2031 if ((highest_bit_set
- lowest_bit_set
) < 32)
2033 unsigned HOST_WIDE_INT focus_bits
=
2034 create_simple_focus_bits (high_bits
, low_bits
,
2037 /* We can't get here in this state. */
2038 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2040 /* So what we know is that the set bits straddle the
2041 middle of the 64-bit word. */
2042 sparc_emit_set_const64_quick2 (op0
, temp
,
2048 /* 1) sethi %hi(high_bits), %reg
2049 * or %reg, %lo(high_bits), %reg
2050 * sllx %reg, 32, %reg
2051 * or %reg, low_bits, %reg
2053 if (SPARC_SIMM13_P(low_bits
)
2054 && ((int)low_bits
> 0))
2056 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2060 /* The easiest way when all else fails, is full decomposition. */
2061 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2063 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2065 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2066 return the mode to be used for the comparison. For floating-point,
2067 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2068 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2069 processing is needed. */
2072 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2074 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2100 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2101 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2103 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2104 return CCX_NOOVmode
;
2110 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2117 /* Emit the compare insn and return the CC reg for a CODE comparison
2118 with operands X and Y. */
2121 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2123 enum machine_mode mode
;
2126 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2129 mode
= SELECT_CC_MODE (code
, x
, y
);
2131 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2132 fcc regs (cse can't tell they're really call clobbered regs and will
2133 remove a duplicate comparison even if there is an intervening function
2134 call - it will then try to reload the cc reg via an int reg which is why
2135 we need the movcc patterns). It is possible to provide the movcc
2136 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2137 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2138 to tell cse that CCFPE mode registers (even pseudos) are call
2141 /* ??? This is an experiment. Rather than making changes to cse which may
2142 or may not be easy/clean, we do our own cse. This is possible because
2143 we will generate hard registers. Cse knows they're call clobbered (it
2144 doesn't know the same thing about pseudos). If we guess wrong, no big
2145 deal, but if we win, great! */
2147 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2148 #if 1 /* experiment */
2151 /* We cycle through the registers to ensure they're all exercised. */
2152 static int next_fcc_reg
= 0;
2153 /* Previous x,y for each fcc reg. */
2154 static rtx prev_args
[4][2];
2156 /* Scan prev_args for x,y. */
2157 for (reg
= 0; reg
< 4; reg
++)
2158 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2163 prev_args
[reg
][0] = x
;
2164 prev_args
[reg
][1] = y
;
2165 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2167 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2170 cc_reg
= gen_reg_rtx (mode
);
2171 #endif /* ! experiment */
2172 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2173 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2175 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2177 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2178 will only result in an unrecognizable insn so no point in asserting. */
2179 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2185 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2188 gen_compare_reg (rtx cmp
)
2190 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2193 /* This function is used for v9 only.
2194 DEST is the target of the Scc insn.
2195 CODE is the code for an Scc's comparison.
2196 X and Y are the values we compare.
2198 This function is needed to turn
2201 (gt (reg:CCX 100 %icc)
2205 (gt:DI (reg:CCX 100 %icc)
2208 IE: The instruction recognizer needs to see the mode of the comparison to
2209 find the right instruction. We could use "gt:DI" right in the
2210 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2213 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2216 && (GET_MODE (x
) == DImode
2217 || GET_MODE (dest
) == DImode
))
2220 /* Try to use the movrCC insns. */
2222 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2224 && v9_regcmp_p (compare_code
))
2229 /* Special case for op0 != 0. This can be done with one instruction if
2232 if (compare_code
== NE
2233 && GET_MODE (dest
) == DImode
2234 && rtx_equal_p (op0
, dest
))
2236 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2237 gen_rtx_IF_THEN_ELSE (DImode
,
2238 gen_rtx_fmt_ee (compare_code
, DImode
,
2245 if (reg_overlap_mentioned_p (dest
, op0
))
2247 /* Handle the case where dest == x.
2248 We "early clobber" the result. */
2249 op0
= gen_reg_rtx (GET_MODE (x
));
2250 emit_move_insn (op0
, x
);
2253 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2254 if (GET_MODE (op0
) != DImode
)
2256 temp
= gen_reg_rtx (DImode
);
2257 convert_move (temp
, op0
, 0);
2261 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2262 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2263 gen_rtx_fmt_ee (compare_code
, DImode
,
2271 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2274 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2275 && GET_MODE (x
) != CCX_NOOVmode
);
2277 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2278 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2279 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2280 gen_rtx_fmt_ee (compare_code
,
2281 GET_MODE (x
), x
, y
),
2282 const1_rtx
, dest
)));
2288 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2289 without jumps using the addx/subx instructions. */
2292 emit_scc_insn (rtx operands
[])
2299 /* The quad-word fp compare library routines all return nonzero to indicate
2300 true, which is different from the equivalent libgcc routines, so we must
2301 handle them specially here. */
2302 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2304 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2305 GET_CODE (operands
[1]));
2306 operands
[2] = XEXP (operands
[1], 0);
2307 operands
[3] = XEXP (operands
[1], 1);
2310 code
= GET_CODE (operands
[1]);
2314 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2315 more applications). The exception to this is "reg != 0" which can
2316 be done in one instruction on v9 (so we do it). */
2319 if (GET_MODE (x
) == SImode
)
2321 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2325 else if (GET_MODE (x
) == DImode
)
2327 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2335 if (GET_MODE (x
) == SImode
)
2337 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2341 else if (GET_MODE (x
) == DImode
)
2343 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2349 /* For the rest, on v9 we can use conditional moves. */
2353 if (gen_v9_scc (operands
[0], code
, x
, y
))
2357 /* We can do LTU and GEU using the addx/subx instructions too. And
2358 for GTU/LEU, if both operands are registers swap them and fall
2359 back to the easy case. */
2360 if (code
== GTU
|| code
== LEU
)
2362 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2363 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2368 code
= swap_condition (code
);
2372 if (code
== LTU
|| code
== GEU
)
2374 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2375 gen_rtx_fmt_ee (code
, SImode
,
2376 gen_compare_reg_1 (code
, x
, y
),
2381 /* Nope, do branches. */
2385 /* Emit a conditional jump insn for the v9 architecture using comparison code
2386 CODE and jump target LABEL.
2387 This function exists to take advantage of the v9 brxx insns. */
2390 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2392 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2394 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2395 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2397 gen_rtx_LABEL_REF (VOIDmode
, label
),
2402 emit_conditional_branch_insn (rtx operands
[])
2404 /* The quad-word fp compare library routines all return nonzero to indicate
2405 true, which is different from the equivalent libgcc routines, so we must
2406 handle them specially here. */
2407 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2409 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2410 GET_CODE (operands
[0]));
2411 operands
[1] = XEXP (operands
[0], 0);
2412 operands
[2] = XEXP (operands
[0], 1);
2415 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2416 && GET_CODE (operands
[1]) == REG
2417 && GET_MODE (operands
[1]) == DImode
)
2419 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2423 operands
[1] = gen_compare_reg (operands
[0]);
2424 operands
[2] = const0_rtx
;
2425 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2426 operands
[1], operands
[2]);
2427 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2432 /* Generate a DFmode part of a hard TFmode register.
2433 REG is the TFmode hard register, LOW is 1 for the
2434 low 64bit of the register and 0 otherwise.
2437 gen_df_reg (rtx reg
, int low
)
2439 int regno
= REGNO (reg
);
2441 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2442 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2443 return gen_rtx_REG (DFmode
, regno
);
2446 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2447 Unlike normal calls, TFmode operands are passed by reference. It is
2448 assumed that no more than 3 operands are required. */
2451 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2453 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2456 /* We only expect to be called for conversions, unary, and binary ops. */
2457 gcc_assert (nargs
== 2 || nargs
== 3);
2459 for (i
= 0; i
< nargs
; ++i
)
2461 rtx this_arg
= operands
[i
];
2464 /* TFmode arguments and return values are passed by reference. */
2465 if (GET_MODE (this_arg
) == TFmode
)
2467 int force_stack_temp
;
2469 force_stack_temp
= 0;
2470 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2471 force_stack_temp
= 1;
2473 if (GET_CODE (this_arg
) == MEM
2474 && ! force_stack_temp
)
2475 this_arg
= XEXP (this_arg
, 0);
2476 else if (CONSTANT_P (this_arg
)
2477 && ! force_stack_temp
)
2479 this_slot
= force_const_mem (TFmode
, this_arg
);
2480 this_arg
= XEXP (this_slot
, 0);
2484 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2486 /* Operand 0 is the return value. We'll copy it out later. */
2488 emit_move_insn (this_slot
, this_arg
);
2490 ret_slot
= this_slot
;
2492 this_arg
= XEXP (this_slot
, 0);
2499 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2501 if (GET_MODE (operands
[0]) == TFmode
)
2504 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2505 arg
[0], GET_MODE (arg
[0]),
2506 arg
[1], GET_MODE (arg
[1]));
2508 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2509 arg
[0], GET_MODE (arg
[0]),
2510 arg
[1], GET_MODE (arg
[1]),
2511 arg
[2], GET_MODE (arg
[2]));
2514 emit_move_insn (operands
[0], ret_slot
);
2520 gcc_assert (nargs
== 2);
2522 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2523 GET_MODE (operands
[0]), 1,
2524 arg
[1], GET_MODE (arg
[1]));
2526 if (ret
!= operands
[0])
2527 emit_move_insn (operands
[0], ret
);
2531 /* Expand soft-float TFmode calls to sparc abi routines. */
2534 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2556 emit_soft_tfmode_libcall (func
, 3, operands
);
2560 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2564 gcc_assert (code
== SQRT
);
2567 emit_soft_tfmode_libcall (func
, 2, operands
);
2571 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2578 switch (GET_MODE (operands
[1]))
2591 case FLOAT_TRUNCATE
:
2592 switch (GET_MODE (operands
[0]))
2606 switch (GET_MODE (operands
[1]))
2611 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2621 case UNSIGNED_FLOAT
:
2622 switch (GET_MODE (operands
[1]))
2627 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2638 switch (GET_MODE (operands
[0]))
2652 switch (GET_MODE (operands
[0]))
2669 emit_soft_tfmode_libcall (func
, 2, operands
);
2672 /* Expand a hard-float tfmode operation. All arguments must be in
2676 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2680 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2682 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2683 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2687 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2688 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2689 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2690 operands
[1], operands
[2]);
2693 if (register_operand (operands
[0], VOIDmode
))
2696 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2698 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2700 if (dest
!= operands
[0])
2701 emit_move_insn (operands
[0], dest
);
2705 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2707 if (TARGET_HARD_QUAD
)
2708 emit_hard_tfmode_operation (code
, operands
);
2710 emit_soft_tfmode_binop (code
, operands
);
2714 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2716 if (TARGET_HARD_QUAD
)
2717 emit_hard_tfmode_operation (code
, operands
);
2719 emit_soft_tfmode_unop (code
, operands
);
2723 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2725 if (TARGET_HARD_QUAD
)
2726 emit_hard_tfmode_operation (code
, operands
);
2728 emit_soft_tfmode_cvt (code
, operands
);
2731 /* Return nonzero if a branch/jump/call instruction will be emitting
2732 nop into its delay slot. */
2735 empty_delay_slot (rtx insn
)
2739 /* If no previous instruction (should not happen), return true. */
2740 if (PREV_INSN (insn
) == NULL
)
2743 seq
= NEXT_INSN (PREV_INSN (insn
));
2744 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2750 /* Return nonzero if TRIAL can go into the call delay slot. */
2753 tls_call_delay (rtx trial
)
2758 call __tls_get_addr, %tgd_call (foo)
2759 add %l7, %o0, %o0, %tgd_add (foo)
2760 while Sun as/ld does not. */
2761 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2764 pat
= PATTERN (trial
);
2766 /* We must reject tgd_add{32|64}, i.e.
2767 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2768 and tldm_add{32|64}, i.e.
2769 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2771 if (GET_CODE (pat
) == SET
2772 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2774 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2776 if (GET_CODE (unspec
) == UNSPEC
2777 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2778 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2785 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2786 instruction. RETURN_P is true if the v9 variant 'return' is to be
2787 considered in the test too.
2789 TRIAL must be a SET whose destination is a REG appropriate for the
2790 'restore' instruction or, if RETURN_P is true, for the 'return'
2794 eligible_for_restore_insn (rtx trial
, bool return_p
)
2796 rtx pat
= PATTERN (trial
);
2797 rtx src
= SET_SRC (pat
);
2799 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2800 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2801 && arith_operand (src
, GET_MODE (src
)))
2804 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2806 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2809 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2810 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2811 && arith_double_operand (src
, GET_MODE (src
)))
2812 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2814 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2815 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2818 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2819 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2822 /* If we have the 'return' instruction, anything that does not use
2823 local or output registers and can go into a delay slot wins. */
2826 && !epilogue_renumber (&pat
, 1)
2827 && get_attr_in_uncond_branch_delay (trial
)
2828 == IN_UNCOND_BRANCH_DELAY_TRUE
)
2831 /* The 'restore src1,src2,dest' pattern for SImode. */
2832 else if (GET_CODE (src
) == PLUS
2833 && register_operand (XEXP (src
, 0), SImode
)
2834 && arith_operand (XEXP (src
, 1), SImode
))
2837 /* The 'restore src1,src2,dest' pattern for DImode. */
2838 else if (GET_CODE (src
) == PLUS
2839 && register_operand (XEXP (src
, 0), DImode
)
2840 && arith_double_operand (XEXP (src
, 1), DImode
))
2843 /* The 'restore src1,%lo(src2),dest' pattern. */
2844 else if (GET_CODE (src
) == LO_SUM
2845 && ! TARGET_CM_MEDMID
2846 && ((register_operand (XEXP (src
, 0), SImode
)
2847 && immediate_operand (XEXP (src
, 1), SImode
))
2849 && register_operand (XEXP (src
, 0), DImode
)
2850 && immediate_operand (XEXP (src
, 1), DImode
))))
2853 /* The 'restore src,src,dest' pattern. */
2854 else if (GET_CODE (src
) == ASHIFT
2855 && (register_operand (XEXP (src
, 0), SImode
)
2856 || register_operand (XEXP (src
, 0), DImode
))
2857 && XEXP (src
, 1) == const1_rtx
)
2863 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2866 eligible_for_return_delay (rtx trial
)
2871 if (GET_CODE (trial
) != INSN
)
2874 if (get_attr_length (trial
) != 1)
2877 /* If the function uses __builtin_eh_return, the eh_return machinery
2878 occupies the delay slot. */
2879 if (crtl
->calls_eh_return
)
2882 /* In the case of a leaf or flat function, anything can go into the slot. */
2883 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2885 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
2887 pat
= PATTERN (trial
);
2888 if (GET_CODE (pat
) == PARALLEL
)
2894 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
2896 rtx expr
= XVECEXP (pat
, 0, i
);
2897 if (GET_CODE (expr
) != SET
)
2899 if (GET_CODE (SET_DEST (expr
)) != REG
)
2901 regno
= REGNO (SET_DEST (expr
));
2902 if (regno
>= 8 && regno
< 24)
2905 return !epilogue_renumber (&pat
, 1)
2906 && (get_attr_in_uncond_branch_delay (trial
)
2907 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2910 if (GET_CODE (pat
) != SET
)
2913 if (GET_CODE (SET_DEST (pat
)) != REG
)
2916 regno
= REGNO (SET_DEST (pat
));
2918 /* Otherwise, only operations which can be done in tandem with
2919 a `restore' or `return' insn can go into the delay slot. */
2920 if (regno
>= 8 && regno
< 24)
2923 /* If this instruction sets up floating point register and we have a return
2924 instruction, it can probably go in. But restore will not work
2928 && !epilogue_renumber (&pat
, 1)
2929 && get_attr_in_uncond_branch_delay (trial
)
2930 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2932 return eligible_for_restore_insn (trial
, true);
2935 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
2938 eligible_for_sibcall_delay (rtx trial
)
2942 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2945 if (get_attr_length (trial
) != 1)
2948 pat
= PATTERN (trial
);
2950 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2952 /* If the tail call is done using the call instruction,
2953 we have to restore %o7 in the delay slot. */
2954 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2957 /* %g1 is used to build the function address */
2958 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2964 /* Otherwise, only operations which can be done in tandem with
2965 a `restore' insn can go into the delay slot. */
2966 if (GET_CODE (SET_DEST (pat
)) != REG
2967 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2968 || REGNO (SET_DEST (pat
)) >= 32)
2971 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2973 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2976 return eligible_for_restore_insn (trial
, false);
2980 short_branch (int uid1
, int uid2
)
2982 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2984 /* Leave a few words of "slop". */
2985 if (delta
>= -1023 && delta
<= 1022)
2991 /* Return nonzero if REG is not used after INSN.
2992 We assume REG is a reload reg, and therefore does
2993 not live past labels or calls or jumps. */
2995 reg_unused_after (rtx reg
, rtx insn
)
2997 enum rtx_code code
, prev_code
= UNKNOWN
;
2999 while ((insn
= NEXT_INSN (insn
)))
3001 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3004 code
= GET_CODE (insn
);
3005 if (GET_CODE (insn
) == CODE_LABEL
)
3010 rtx set
= single_set (insn
);
3011 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3014 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3016 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3024 /* Determine if it's legal to put X into the constant pool. This
3025 is not possible if X contains the address of a symbol that is
3026 not constant (TLS) or not known at final link time (PIC). */
3029 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
3031 switch (GET_CODE (x
))
3036 /* Accept all non-symbolic constants. */
3040 /* Labels are OK iff we are non-PIC. */
3041 return flag_pic
!= 0;
3044 /* 'Naked' TLS symbol references are never OK,
3045 non-TLS symbols are OK iff we are non-PIC. */
3046 if (SYMBOL_REF_TLS_MODEL (x
))
3049 return flag_pic
!= 0;
3052 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3055 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3056 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3064 /* Global Offset Table support. */
3065 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3066 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3068 /* Return the SYMBOL_REF for the Global Offset Table. */
3070 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3075 if (!sparc_got_symbol
)
3076 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3078 return sparc_got_symbol
;
3081 /* Ensure that we are not using patterns that are not OK with PIC. */
3091 op
= recog_data
.operand
[i
];
3092 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3093 && (GET_CODE (op
) != CONST
3094 || (GET_CODE (XEXP (op
, 0)) == MINUS
3095 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3096 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3103 /* Return true if X is an address which needs a temporary register when
3104 reloaded while generating PIC code. */
3107 pic_address_needs_scratch (rtx x
)
3109 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3110 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3111 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3112 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3113 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3119 /* Determine if a given RTX is a valid constant. We already know this
3120 satisfies CONSTANT_P. */
3123 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3125 switch (GET_CODE (x
))
3129 if (sparc_tls_referenced_p (x
))
3134 if (GET_MODE (x
) == VOIDmode
)
3137 /* Floating point constants are generally not ok.
3138 The only exception is 0.0 and all-ones in VIS. */
3140 && SCALAR_FLOAT_MODE_P (mode
)
3141 && (const_zero_operand (x
, mode
)
3142 || const_all_ones_operand (x
, mode
)))
3148 /* Vector constants are generally not ok.
3149 The only exception is 0 or -1 in VIS. */
3151 && (const_zero_operand (x
, mode
)
3152 || const_all_ones_operand (x
, mode
)))
3164 /* Determine if a given RTX is a valid constant address. */
3167 constant_address_p (rtx x
)
3169 switch (GET_CODE (x
))
3177 if (flag_pic
&& pic_address_needs_scratch (x
))
3179 return sparc_legitimate_constant_p (Pmode
, x
);
3182 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3189 /* Nonzero if the constant value X is a legitimate general operand
3190 when generating PIC code. It is given that flag_pic is on and
3191 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3194 legitimate_pic_operand_p (rtx x
)
3196 if (pic_address_needs_scratch (x
))
3198 if (sparc_tls_referenced_p (x
))
3203 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3205 && INTVAL (X) >= -0x1000 \
3206 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3208 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3210 && INTVAL (X) >= -0x1000 \
3211 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3213 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3215 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3216 ordinarily. This changes a bit when generating PIC. */
3219 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3221 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3223 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3225 else if (GET_CODE (addr
) == PLUS
)
3227 rs1
= XEXP (addr
, 0);
3228 rs2
= XEXP (addr
, 1);
3230 /* Canonicalize. REG comes first, if there are no regs,
3231 LO_SUM comes first. */
3233 && GET_CODE (rs1
) != SUBREG
3235 || GET_CODE (rs2
) == SUBREG
3236 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3238 rs1
= XEXP (addr
, 1);
3239 rs2
= XEXP (addr
, 0);
3243 && rs1
== pic_offset_table_rtx
3245 && GET_CODE (rs2
) != SUBREG
3246 && GET_CODE (rs2
) != LO_SUM
3247 && GET_CODE (rs2
) != MEM
3248 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3249 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3250 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3252 || GET_CODE (rs1
) == SUBREG
)
3253 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3258 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3259 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3261 /* We prohibit REG + REG for TFmode when there are no quad move insns
3262 and we consequently need to split. We do this because REG+REG
3263 is not an offsettable address. If we get the situation in reload
3264 where source and destination of a movtf pattern are both MEMs with
3265 REG+REG address, then only one of them gets converted to an
3266 offsettable address. */
3268 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3271 /* We prohibit REG + REG on ARCH32 if not optimizing for
3272 DFmode/DImode because then mem_min_alignment is likely to be zero
3273 after reload and the forced split would lack a matching splitter
3275 if (TARGET_ARCH32
&& !optimize
3276 && (mode
== DFmode
|| mode
== DImode
))
3279 else if (USE_AS_OFFSETABLE_LO10
3280 && GET_CODE (rs1
) == LO_SUM
3282 && ! TARGET_CM_MEDMID
3283 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3286 imm1
= XEXP (rs1
, 1);
3287 rs1
= XEXP (rs1
, 0);
3288 if (!CONSTANT_P (imm1
)
3289 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3293 else if (GET_CODE (addr
) == LO_SUM
)
3295 rs1
= XEXP (addr
, 0);
3296 imm1
= XEXP (addr
, 1);
3298 if (!CONSTANT_P (imm1
)
3299 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3302 /* We can't allow TFmode in 32-bit mode, because an offset greater
3303 than the alignment (8) may cause the LO_SUM to overflow. */
3304 if (mode
== TFmode
&& TARGET_ARCH32
)
3307 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3312 if (GET_CODE (rs1
) == SUBREG
)
3313 rs1
= SUBREG_REG (rs1
);
3319 if (GET_CODE (rs2
) == SUBREG
)
3320 rs2
= SUBREG_REG (rs2
);
3327 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3328 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3333 if ((REGNO (rs1
) >= 32
3334 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3335 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3337 && (REGNO (rs2
) >= 32
3338 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3339 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3345 /* Return the SYMBOL_REF for the tls_get_addr function. */
3347 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3350 sparc_tls_get_addr (void)
3352 if (!sparc_tls_symbol
)
3353 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3355 return sparc_tls_symbol
;
3358 /* Return the Global Offset Table to be used in TLS mode. */
3361 sparc_tls_got (void)
3363 /* In PIC mode, this is just the PIC offset table. */
3366 crtl
->uses_pic_offset_table
= 1;
3367 return pic_offset_table_rtx
;
3370 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3371 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3372 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3374 load_got_register ();
3375 return global_offset_table_rtx
;
3378 /* In all other cases, we load a new pseudo with the GOT symbol. */
3379 return copy_to_reg (sparc_got ());
3382 /* Return true if X contains a thread-local symbol. */
3385 sparc_tls_referenced_p (rtx x
)
3387 if (!TARGET_HAVE_TLS
)
3390 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3391 x
= XEXP (XEXP (x
, 0), 0);
3393 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3396 /* That's all we handle in sparc_legitimize_tls_address for now. */
3400 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3401 this (thread-local) address. */
3404 sparc_legitimize_tls_address (rtx addr
)
3406 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3408 gcc_assert (can_create_pseudo_p ());
3410 if (GET_CODE (addr
) == SYMBOL_REF
)
3411 switch (SYMBOL_REF_TLS_MODEL (addr
))
3413 case TLS_MODEL_GLOBAL_DYNAMIC
:
3415 temp1
= gen_reg_rtx (SImode
);
3416 temp2
= gen_reg_rtx (SImode
);
3417 ret
= gen_reg_rtx (Pmode
);
3418 o0
= gen_rtx_REG (Pmode
, 8);
3419 got
= sparc_tls_got ();
3420 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3421 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3424 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3425 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3430 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3431 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3434 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3435 insn
= get_insns ();
3437 emit_libcall_block (insn
, ret
, o0
, addr
);
3440 case TLS_MODEL_LOCAL_DYNAMIC
:
3442 temp1
= gen_reg_rtx (SImode
);
3443 temp2
= gen_reg_rtx (SImode
);
3444 temp3
= gen_reg_rtx (Pmode
);
3445 ret
= gen_reg_rtx (Pmode
);
3446 o0
= gen_rtx_REG (Pmode
, 8);
3447 got
= sparc_tls_got ();
3448 emit_insn (gen_tldm_hi22 (temp1
));
3449 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3452 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3453 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3458 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3459 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3462 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3463 insn
= get_insns ();
3465 emit_libcall_block (insn
, temp3
, o0
,
3466 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3467 UNSPEC_TLSLD_BASE
));
3468 temp1
= gen_reg_rtx (SImode
);
3469 temp2
= gen_reg_rtx (SImode
);
3470 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3471 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3473 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3475 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3478 case TLS_MODEL_INITIAL_EXEC
:
3479 temp1
= gen_reg_rtx (SImode
);
3480 temp2
= gen_reg_rtx (SImode
);
3481 temp3
= gen_reg_rtx (Pmode
);
3482 got
= sparc_tls_got ();
3483 emit_insn (gen_tie_hi22 (temp1
, addr
));
3484 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3486 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3488 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3491 ret
= gen_reg_rtx (Pmode
);
3493 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3496 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3500 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3503 case TLS_MODEL_LOCAL_EXEC
:
3504 temp1
= gen_reg_rtx (Pmode
);
3505 temp2
= gen_reg_rtx (Pmode
);
3508 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3509 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3513 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3514 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3516 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3523 else if (GET_CODE (addr
) == CONST
)
3527 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3529 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3530 offset
= XEXP (XEXP (addr
, 0), 1);
3532 base
= force_operand (base
, NULL_RTX
);
3533 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3534 offset
= force_reg (Pmode
, offset
);
3535 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3539 gcc_unreachable (); /* for now ... */
3544 /* Legitimize PIC addresses. If the address is already position-independent,
3545 we return ORIG. Newly generated position-independent addresses go into a
3546 reg. This is REG if nonzero, otherwise we allocate register(s) as
3550 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3552 bool gotdata_op
= false;
3554 if (GET_CODE (orig
) == SYMBOL_REF
3555 /* See the comment in sparc_expand_move. */
3556 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3558 rtx pic_ref
, address
;
3563 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3564 reg
= gen_reg_rtx (Pmode
);
3569 /* If not during reload, allocate another temp reg here for loading
3570 in the address, so that these instructions can be optimized
3572 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3573 ? reg
: gen_reg_rtx (Pmode
));
3575 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3576 won't get confused into thinking that these two instructions
3577 are loading in the true address of the symbol. If in the
3578 future a PIC rtx exists, that should be used instead. */
3581 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3582 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3586 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3587 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3595 crtl
->uses_pic_offset_table
= 1;
3599 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3600 pic_offset_table_rtx
,
3603 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3604 pic_offset_table_rtx
,
3610 = gen_const_mem (Pmode
,
3611 gen_rtx_PLUS (Pmode
,
3612 pic_offset_table_rtx
, address
));
3613 insn
= emit_move_insn (reg
, pic_ref
);
3616 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3618 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3621 else if (GET_CODE (orig
) == CONST
)
3625 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3626 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3631 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3632 reg
= gen_reg_rtx (Pmode
);
3635 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3636 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3637 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3638 base
== reg
? NULL_RTX
: reg
);
3640 if (GET_CODE (offset
) == CONST_INT
)
3642 if (SMALL_INT (offset
))
3643 return plus_constant (base
, INTVAL (offset
));
3644 else if (! reload_in_progress
&& ! reload_completed
)
3645 offset
= force_reg (Pmode
, offset
);
3647 /* If we reach here, then something is seriously wrong. */
3650 return gen_rtx_PLUS (Pmode
, base
, offset
);
3652 else if (GET_CODE (orig
) == LABEL_REF
)
3653 /* ??? We ought to be checking that the register is live instead, in case
3654 it is eliminated. */
3655 crtl
->uses_pic_offset_table
= 1;
3660 /* Try machine-dependent ways of modifying an illegitimate address X
3661 to be legitimate. If we find one, return the new, valid address.
3663 OLDX is the address as it was before break_out_memory_refs was called.
3664 In some cases it is useful to look at this to decide what needs to be done.
3666 MODE is the mode of the operand pointed to by X.
3668 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3671 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3672 enum machine_mode mode
)
3676 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3677 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3678 force_operand (XEXP (x
, 0), NULL_RTX
));
3679 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3680 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3681 force_operand (XEXP (x
, 1), NULL_RTX
));
3682 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3683 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3685 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3686 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3687 force_operand (XEXP (x
, 1), NULL_RTX
));
3689 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3692 if (sparc_tls_referenced_p (x
))
3693 x
= sparc_legitimize_tls_address (x
);
3695 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
3696 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3697 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3698 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3699 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3700 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3701 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3702 else if (GET_CODE (x
) == SYMBOL_REF
3703 || GET_CODE (x
) == CONST
3704 || GET_CODE (x
) == LABEL_REF
)
3705 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3710 /* Delegitimize an address that was legitimized by the above function. */
3713 sparc_delegitimize_address (rtx x
)
3715 x
= delegitimize_mem_from_attrs (x
);
3717 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
3718 switch (XINT (XEXP (x
, 1), 1))
3720 case UNSPEC_MOVE_PIC
:
3722 x
= XVECEXP (XEXP (x
, 1), 0, 0);
3723 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3729 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3730 if (GET_CODE (x
) == MINUS
3731 && REG_P (XEXP (x
, 0))
3732 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
3733 && GET_CODE (XEXP (x
, 1)) == LO_SUM
3734 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
3735 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
3737 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
3738 gcc_assert (GET_CODE (x
) == LABEL_REF
);
3744 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3745 replace the input X, or the original X if no replacement is called for.
3746 The output parameter *WIN is 1 if the calling macro should goto WIN,
3749 For SPARC, we wish to handle addresses by splitting them into
3750 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3751 This cuts the number of extra insns by one.
3753 Do nothing when generating PIC code and the address is a symbolic
3754 operand or requires a scratch register. */
3757 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3758 int opnum
, int type
,
3759 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3761 /* Decompose SImode constants into HIGH+LO_SUM. */
3763 && (mode
!= TFmode
|| TARGET_ARCH64
)
3764 && GET_MODE (x
) == SImode
3765 && GET_CODE (x
) != LO_SUM
3766 && GET_CODE (x
) != HIGH
3767 && sparc_cmodel
<= CM_MEDLOW
3769 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
3771 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
3772 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3773 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3774 opnum
, (enum reload_type
)type
);
3779 /* We have to recognize what we have already generated above. */
3780 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
3782 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3783 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3784 opnum
, (enum reload_type
)type
);
3793 /* Return true if ADDR (a legitimate address expression)
3794 has an effect that depends on the machine mode it is used for.
3800 is not equivalent to
3802 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3804 because [%l7+a+1] is interpreted as the address of (a+1). */
3808 sparc_mode_dependent_address_p (const_rtx addr
)
3810 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
3812 rtx op0
= XEXP (addr
, 0);
3813 rtx op1
= XEXP (addr
, 1);
3814 if (op0
== pic_offset_table_rtx
3815 && symbolic_operand (op1
, VOIDmode
))
3822 #ifdef HAVE_GAS_HIDDEN
3823 # define USE_HIDDEN_LINKONCE 1
3825 # define USE_HIDDEN_LINKONCE 0
3829 get_pc_thunk_name (char name
[32], unsigned int regno
)
3831 const char *reg_name
= reg_names
[regno
];
3833 /* Skip the leading '%' as that cannot be used in a
3837 if (USE_HIDDEN_LINKONCE
)
3838 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
3840 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3843 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3846 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
3848 int orig_flag_pic
= flag_pic
;
3851 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3854 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
3856 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
3857 flag_pic
= orig_flag_pic
;
3862 /* Emit code to load the GOT register. */
3865 load_got_register (void)
3867 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3868 if (!global_offset_table_rtx
)
3869 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
3871 if (TARGET_VXWORKS_RTP
)
3872 emit_insn (gen_vxworks_load_got ());
3875 /* The GOT symbol is subject to a PC-relative relocation so we need a
3876 helper function to add the PC value and thus get the final value. */
3877 if (!got_helper_rtx
)
3880 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
3881 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3884 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
3886 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
3889 /* Need to emit this whether or not we obey regdecls,
3890 since setjmp/longjmp can cause life info to screw up.
3891 ??? In the case where we don't obey regdecls, this is not sufficient
3892 since we may not fall out the bottom. */
3893 emit_use (global_offset_table_rtx
);
3896 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3897 address of the call target. */
3900 sparc_emit_call_insn (rtx pat
, rtx addr
)
3904 insn
= emit_call_insn (pat
);
3906 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3907 if (TARGET_VXWORKS_RTP
3909 && GET_CODE (addr
) == SYMBOL_REF
3910 && (SYMBOL_REF_DECL (addr
)
3911 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
3912 : !SYMBOL_REF_LOCAL_P (addr
)))
3914 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3915 crtl
->uses_pic_offset_table
= 1;
3919 /* Return 1 if RTX is a MEM which is known to be aligned to at
3920 least a DESIRED byte boundary. */
3923 mem_min_alignment (rtx mem
, int desired
)
3925 rtx addr
, base
, offset
;
3927 /* If it's not a MEM we can't accept it. */
3928 if (GET_CODE (mem
) != MEM
)
3932 if (!TARGET_UNALIGNED_DOUBLES
3933 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3936 /* ??? The rest of the function predates MEM_ALIGN so
3937 there is probably a bit of redundancy. */
3938 addr
= XEXP (mem
, 0);
3939 base
= offset
= NULL_RTX
;
3940 if (GET_CODE (addr
) == PLUS
)
3942 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3944 base
= XEXP (addr
, 0);
3946 /* What we are saying here is that if the base
3947 REG is aligned properly, the compiler will make
3948 sure any REG based index upon it will be so
3950 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3951 offset
= XEXP (addr
, 1);
3953 offset
= const0_rtx
;
3956 else if (GET_CODE (addr
) == REG
)
3959 offset
= const0_rtx
;
3962 if (base
!= NULL_RTX
)
3964 int regno
= REGNO (base
);
3966 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3968 /* Check if the compiler has recorded some information
3969 about the alignment of the base REG. If reload has
3970 completed, we already matched with proper alignments.
3971 If not running global_alloc, reload might give us
3972 unaligned pointer to local stack though. */
3974 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3975 || (optimize
&& reload_completed
))
3976 && (INTVAL (offset
) & (desired
- 1)) == 0)
3981 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3985 else if (! TARGET_UNALIGNED_DOUBLES
3986 || CONSTANT_P (addr
)
3987 || GET_CODE (addr
) == LO_SUM
)
3989 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3990 is true, in which case we can only assume that an access is aligned if
3991 it is to a constant address, or the address involves a LO_SUM. */
3995 /* An obviously unaligned address. */
4000 /* Vectors to keep interesting information about registers where it can easily
4001 be got. We used to use the actual mode value as the bit number, but there
4002 are more than 32 modes now. Instead we use two tables: one indexed by
4003 hard register number, and one indexed by mode. */
4005 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4006 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4007 mapped into one sparc_mode_class mode. */
4009 enum sparc_mode_class
{
4010 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4011 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4015 /* Modes for single-word and smaller quantities. */
4016 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4018 /* Modes for double-word and smaller quantities. */
4019 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4021 /* Modes for quad-word and smaller quantities. */
4022 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4024 /* Modes for 8-word and smaller quantities. */
4025 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4027 /* Modes for single-float quantities. We must allow any single word or
4028 smaller quantity. This is because the fix/float conversion instructions
4029 take integer inputs/outputs from the float registers. */
4030 #define SF_MODES (S_MODES)
4032 /* Modes for double-float and smaller quantities. */
4033 #define DF_MODES (D_MODES)
4035 /* Modes for quad-float and smaller quantities. */
4036 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4038 /* Modes for quad-float pairs and smaller quantities. */
4039 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4041 /* Modes for double-float only quantities. */
4042 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4044 /* Modes for quad-float and double-float only quantities. */
4045 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4047 /* Modes for quad-float pairs and double-float only quantities. */
4048 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4050 /* Modes for condition codes. */
4051 #define CC_MODES (1 << (int) CC_MODE)
4052 #define CCFP_MODES (1 << (int) CCFP_MODE)
4054 /* Value is 1 if register/mode pair is acceptable on sparc.
4055 The funny mixture of D and T modes is because integer operations
4056 do not specially operate on tetra quantities, so non-quad-aligned
4057 registers can hold quadword quantities (except %o4 and %i4 because
4058 they cross fixed registers). */
4060 /* This points to either the 32 bit or the 64 bit version. */
4061 const int *hard_regno_mode_classes
;
4063 static const int hard_32bit_mode_classes
[] = {
4064 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4065 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4066 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4067 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4069 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4070 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4071 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4072 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4074 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4075 and none can hold SFmode/SImode values. */
4076 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4077 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4078 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4079 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4082 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4084 /* %icc, %sfp, %gsr */
4085 CC_MODES
, 0, D_MODES
4088 static const int hard_64bit_mode_classes
[] = {
4089 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4090 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4091 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4092 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4094 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4095 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4096 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4097 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4099 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4100 and none can hold SFmode/SImode values. */
4101 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4102 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4103 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4104 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4107 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4109 /* %icc, %sfp, %gsr */
4110 CC_MODES
, 0, D_MODES
4113 int sparc_mode_class
[NUM_MACHINE_MODES
];
4115 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4118 sparc_init_modes (void)
4122 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4124 switch (GET_MODE_CLASS (i
))
4127 case MODE_PARTIAL_INT
:
4128 case MODE_COMPLEX_INT
:
4129 if (GET_MODE_SIZE (i
) <= 4)
4130 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4131 else if (GET_MODE_SIZE (i
) == 8)
4132 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4133 else if (GET_MODE_SIZE (i
) == 16)
4134 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4135 else if (GET_MODE_SIZE (i
) == 32)
4136 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4138 sparc_mode_class
[i
] = 0;
4140 case MODE_VECTOR_INT
:
4141 if (GET_MODE_SIZE (i
) <= 4)
4142 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4143 else if (GET_MODE_SIZE (i
) == 8)
4144 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4147 case MODE_COMPLEX_FLOAT
:
4148 if (GET_MODE_SIZE (i
) <= 4)
4149 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4150 else if (GET_MODE_SIZE (i
) == 8)
4151 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4152 else if (GET_MODE_SIZE (i
) == 16)
4153 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4154 else if (GET_MODE_SIZE (i
) == 32)
4155 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4157 sparc_mode_class
[i
] = 0;
4160 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4161 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4163 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4166 sparc_mode_class
[i
] = 0;
4172 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4174 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4176 /* Initialize the array used by REGNO_REG_CLASS. */
4177 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4179 if (i
< 16 && TARGET_V8PLUS
)
4180 sparc_regno_reg_class
[i
] = I64_REGS
;
4181 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4182 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4184 sparc_regno_reg_class
[i
] = FP_REGS
;
4186 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4188 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4190 sparc_regno_reg_class
[i
] = NO_REGS
;
4194 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4197 save_global_or_fp_reg_p (unsigned int regno
,
4198 int leaf_function ATTRIBUTE_UNUSED
)
4200 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4203 /* Return whether the return address register (%i7) is needed. */
4206 return_addr_reg_needed_p (int leaf_function
)
4208 /* If it is live, for example because of __builtin_return_address (0). */
4209 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4212 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4214 /* Loading the GOT register clobbers %o7. */
4215 || crtl
->uses_pic_offset_table
4216 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4222 /* Return whether REGNO, a local or in register, must be saved/restored. */
4225 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4227 /* General case: call-saved registers live at some point. */
4228 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4231 /* Frame pointer register (%fp) if needed. */
4232 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4235 /* Return address register (%i7) if needed. */
4236 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4239 /* GOT register (%l7) if needed. */
4240 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4243 /* If the function accesses prior frames, the frame pointer and the return
4244 address of the previous frame must be saved on the stack. */
4245 if (crtl
->accesses_prior_frames
4246 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4252 /* Compute the frame size required by the function. This function is called
4253 during the reload pass and also by sparc_expand_prologue. */
4256 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4258 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4259 int args_size
, n_global_fp_regs
= 0;
4260 bool save_local_in_regs_p
= false;
4263 /* If the function allocates dynamic stack space, the dynamic offset is
4264 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4265 if (leaf_function
&& !cfun
->calls_alloca
)
4268 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4270 /* Calculate space needed for global registers. */
4272 for (i
= 0; i
< 8; i
++)
4273 if (save_global_or_fp_reg_p (i
, 0))
4274 n_global_fp_regs
+= 2;
4276 for (i
= 0; i
< 8; i
+= 2)
4277 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4278 n_global_fp_regs
+= 2;
4280 /* In the flat window model, find out which local and in registers need to
4281 be saved. We don't reserve space in the current frame for them as they
4282 will be spilled into the register window save area of the caller's frame.
4283 However, as soon as we use this register window save area, we must create
4284 that of the current frame to make it the live one. */
4286 for (i
= 16; i
< 32; i
++)
4287 if (save_local_or_in_reg_p (i
, leaf_function
))
4289 save_local_in_regs_p
= true;
4293 /* Calculate space needed for FP registers. */
4294 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4295 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4296 n_global_fp_regs
+= 2;
4299 && n_global_fp_regs
== 0
4301 && !save_local_in_regs_p
)
4302 frame_size
= apparent_frame_size
= 0;
4305 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4306 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4307 apparent_frame_size
+= n_global_fp_regs
* 4;
4309 /* We need to add the size of the outgoing argument area. */
4310 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4312 /* And that of the register window save area. */
4313 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4315 /* Finally, bump to the appropriate alignment. */
4316 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4319 /* Set up values for use in prologue and epilogue. */
4320 sparc_frame_size
= frame_size
;
4321 sparc_apparent_frame_size
= apparent_frame_size
;
4322 sparc_n_global_fp_regs
= n_global_fp_regs
;
4323 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4328 /* Output any necessary .register pseudo-ops. */
4331 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4333 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4339 /* Check if %g[2367] were used without
4340 .register being printed for them already. */
4341 for (i
= 2; i
< 8; i
++)
4343 if (df_regs_ever_live_p (i
)
4344 && ! sparc_hard_reg_printed
[i
])
4346 sparc_hard_reg_printed
[i
] = 1;
4347 /* %g7 is used as TLS base register, use #ignore
4348 for it instead of #scratch. */
4349 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4350 i
== 7 ? "ignore" : "scratch");
4357 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4359 #if PROBE_INTERVAL > 4096
4360 #error Cannot use indexed addressing mode for stack probing
4363 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4364 inclusive. These are offsets from the current stack pointer.
4366 Note that we don't use the REG+REG addressing mode for the probes because
4367 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4368 so the advantages of having a single code win here. */
4371 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4373 rtx g1
= gen_rtx_REG (Pmode
, 1);
4375 /* See if we have a constant small number of probes to generate. If so,
4376 that's the easy case. */
4377 if (size
<= PROBE_INTERVAL
)
4379 emit_move_insn (g1
, GEN_INT (first
));
4380 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4381 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4382 emit_stack_probe (plus_constant (g1
, -size
));
4385 /* The run-time loop is made up of 10 insns in the generic case while the
4386 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4387 else if (size
<= 5 * PROBE_INTERVAL
)
4391 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4392 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4393 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4394 emit_stack_probe (g1
);
4396 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4397 it exceeds SIZE. If only two probes are needed, this will not
4398 generate any code. Then probe at FIRST + SIZE. */
4399 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4401 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4402 plus_constant (g1
, -PROBE_INTERVAL
)));
4403 emit_stack_probe (g1
);
4406 emit_stack_probe (plus_constant (g1
, (i
- PROBE_INTERVAL
) - size
));
4409 /* Otherwise, do the same as above, but in a loop. Note that we must be
4410 extra careful with variables wrapping around because we might be at
4411 the very top (or the very bottom) of the address space and we have
4412 to be able to handle this case properly; in particular, we use an
4413 equality test for the loop condition. */
4416 HOST_WIDE_INT rounded_size
;
4417 rtx g4
= gen_rtx_REG (Pmode
, 4);
4419 emit_move_insn (g1
, GEN_INT (first
));
4422 /* Step 1: round SIZE to the previous multiple of the interval. */
4424 rounded_size
= size
& -PROBE_INTERVAL
;
4425 emit_move_insn (g4
, GEN_INT (rounded_size
));
4428 /* Step 2: compute initial and final value of the loop counter. */
4430 /* TEST_ADDR = SP + FIRST. */
4431 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4432 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4434 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4435 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4440 while (TEST_ADDR != LAST_ADDR)
4442 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4446 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4447 until it is equal to ROUNDED_SIZE. */
4450 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4452 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4455 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4456 that SIZE is equal to ROUNDED_SIZE. */
4458 if (size
!= rounded_size
)
4459 emit_stack_probe (plus_constant (g4
, rounded_size
- size
));
4462 /* Make sure nothing is scheduled before we are done. */
4463 emit_insn (gen_blockage ());
4466 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4467 absolute addresses. */
4470 output_probe_stack_range (rtx reg1
, rtx reg2
)
4472 static int labelno
= 0;
4473 char loop_lab
[32], end_lab
[32];
4476 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4477 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4479 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4481 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4484 output_asm_insn ("cmp\t%0, %1", xops
);
4486 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4488 fputs ("\tbe\t", asm_out_file
);
4489 assemble_name_raw (asm_out_file
, end_lab
);
4490 fputc ('\n', asm_out_file
);
4492 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4493 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4494 output_asm_insn (" add\t%0, %1, %0", xops
);
4496 /* Probe at TEST_ADDR and branch. */
4498 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4500 fputs ("\tba\t", asm_out_file
);
4501 assemble_name_raw (asm_out_file
, loop_lab
);
4502 fputc ('\n', asm_out_file
);
4503 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4504 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4506 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4511 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4512 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4513 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4514 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4515 the action to be performed if it returns false. Return the new offset. */
4517 typedef bool (*sorr_pred_t
) (unsigned int, int);
4518 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4521 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4522 int offset
, int leaf_function
, sorr_pred_t save_p
,
4523 sorr_act_t action_true
, sorr_act_t action_false
)
4528 if (TARGET_ARCH64
&& high
<= 32)
4532 for (i
= low
; i
< high
; i
++)
4534 if (save_p (i
, leaf_function
))
4536 mem
= gen_frame_mem (DImode
, plus_constant (base
, offset
));
4537 if (action_true
== SORR_SAVE
)
4539 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4540 RTX_FRAME_RELATED_P (insn
) = 1;
4542 else /* action_true == SORR_RESTORE */
4544 /* The frame pointer must be restored last since its old
4545 value may be used as base address for the frame. This
4546 is problematic in 64-bit mode only because of the lack
4547 of double-word load instruction. */
4548 if (i
== HARD_FRAME_POINTER_REGNUM
)
4551 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4555 else if (action_false
== SORR_ADVANCE
)
4561 mem
= gen_frame_mem (DImode
, plus_constant (base
, fp_offset
));
4562 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4567 for (i
= low
; i
< high
; i
+= 2)
4569 bool reg0
= save_p (i
, leaf_function
);
4570 bool reg1
= save_p (i
+ 1, leaf_function
);
4571 enum machine_mode mode
;
4576 mode
= i
< 32 ? DImode
: DFmode
;
4581 mode
= i
< 32 ? SImode
: SFmode
;
4586 mode
= i
< 32 ? SImode
: SFmode
;
4592 if (action_false
== SORR_ADVANCE
)
4597 mem
= gen_frame_mem (mode
, plus_constant (base
, offset
));
4598 if (action_true
== SORR_SAVE
)
4600 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4601 RTX_FRAME_RELATED_P (insn
) = 1;
4605 mem
= gen_frame_mem (SImode
, plus_constant (base
, offset
));
4606 set1
= gen_rtx_SET (VOIDmode
, mem
,
4607 gen_rtx_REG (SImode
, regno
));
4608 RTX_FRAME_RELATED_P (set1
) = 1;
4610 = gen_frame_mem (SImode
, plus_constant (base
, offset
+ 4));
4611 set2
= gen_rtx_SET (VOIDmode
, mem
,
4612 gen_rtx_REG (SImode
, regno
+ 1));
4613 RTX_FRAME_RELATED_P (set2
) = 1;
4614 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4615 gen_rtx_PARALLEL (VOIDmode
,
4616 gen_rtvec (2, set1
, set2
)));
4619 else /* action_true == SORR_RESTORE */
4620 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4622 /* Always preserve double-word alignment. */
4623 offset
= (offset
+ 8) & -8;
4630 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4633 emit_adjust_base_to_offset (rtx base
, int offset
)
4635 /* ??? This might be optimized a little as %g1 might already have a
4636 value close enough that a single add insn will do. */
4637 /* ??? Although, all of this is probably only a temporary fix because
4638 if %g1 can hold a function result, then sparc_expand_epilogue will
4639 lose (the result will be clobbered). */
4640 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4641 emit_move_insn (new_base
, GEN_INT (offset
));
4642 emit_insn (gen_rtx_SET (VOIDmode
,
4643 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4647 /* Emit code to save/restore call-saved global and FP registers. */
4650 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4652 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4654 base
= emit_adjust_base_to_offset (base
, offset
);
4659 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4660 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4661 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4662 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4665 /* Emit code to save/restore call-saved local and in registers. */
4668 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
4670 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
4672 base
= emit_adjust_base_to_offset (base
, offset
);
4676 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
4677 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
4680 /* Emit a window_save insn. */
4683 emit_window_save (rtx increment
)
4685 rtx insn
= emit_insn (gen_window_save (increment
));
4686 RTX_FRAME_RELATED_P (insn
) = 1;
4688 /* The incoming return address (%o7) is saved in %i7. */
4689 add_reg_note (insn
, REG_CFA_REGISTER
,
4690 gen_rtx_SET (VOIDmode
,
4691 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
4693 INCOMING_RETURN_ADDR_REGNUM
)));
4695 /* The window save event. */
4696 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
4698 /* The CFA is %fp, the hard frame pointer. */
4699 add_reg_note (insn
, REG_CFA_DEF_CFA
,
4700 plus_constant (hard_frame_pointer_rtx
,
4701 INCOMING_FRAME_SP_OFFSET
));
4706 /* Generate an increment for the stack pointer. */
4709 gen_stack_pointer_inc (rtx increment
)
4711 return gen_rtx_SET (VOIDmode
,
4713 gen_rtx_PLUS (Pmode
,
4718 /* Generate a decrement for the stack pointer. */
4721 gen_stack_pointer_dec (rtx decrement
)
4723 return gen_rtx_SET (VOIDmode
,
4725 gen_rtx_MINUS (Pmode
,
4730 /* Expand the function prologue. The prologue is responsible for reserving
4731 storage for the frame, saving the call-saved registers and loading the
4732 GOT register if needed. */
4735 sparc_expand_prologue (void)
4740 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4741 on the final value of the flag means deferring the prologue/epilogue
4742 expansion until just before the second scheduling pass, which is too
4743 late to emit multiple epilogues or return insns.
4745 Of course we are making the assumption that the value of the flag
4746 will not change between now and its final value. Of the three parts
4747 of the formula, only the last one can reasonably vary. Let's take a
4748 closer look, after assuming that the first two ones are set to true
4749 (otherwise the last value is effectively silenced).
4751 If only_leaf_regs_used returns false, the global predicate will also
4752 be false so the actual frame size calculated below will be positive.
4753 As a consequence, the save_register_window insn will be emitted in
4754 the instruction stream; now this insn explicitly references %fp
4755 which is not a leaf register so only_leaf_regs_used will always
4756 return false subsequently.
4758 If only_leaf_regs_used returns true, we hope that the subsequent
4759 optimization passes won't cause non-leaf registers to pop up. For
4760 example, the regrename pass has special provisions to not rename to
4761 non-leaf registers in a leaf function. */
4762 sparc_leaf_function_p
4763 = optimize
> 0 && current_function_is_leaf
&& only_leaf_regs_used ();
4765 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4767 if (flag_stack_usage_info
)
4768 current_function_static_stack_size
= size
;
4770 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4771 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4775 else if (sparc_leaf_function_p
)
4777 rtx size_int_rtx
= GEN_INT (-size
);
4780 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4781 else if (size
<= 8192)
4783 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4784 /* %sp is still the CFA register. */
4785 RTX_FRAME_RELATED_P (insn
) = 1;
4786 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4790 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4791 emit_move_insn (size_rtx
, size_int_rtx
);
4792 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4793 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4794 gen_stack_pointer_inc (size_int_rtx
));
4797 RTX_FRAME_RELATED_P (insn
) = 1;
4801 rtx size_int_rtx
= GEN_INT (-size
);
4804 emit_window_save (size_int_rtx
);
4805 else if (size
<= 8192)
4807 emit_window_save (GEN_INT (-4096));
4808 /* %sp is not the CFA register anymore. */
4809 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4813 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4814 emit_move_insn (size_rtx
, size_int_rtx
);
4815 emit_window_save (size_rtx
);
4819 if (sparc_leaf_function_p
)
4821 sparc_frame_base_reg
= stack_pointer_rtx
;
4822 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4826 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4827 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4830 if (sparc_n_global_fp_regs
> 0)
4831 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4832 sparc_frame_base_offset
4833 - sparc_apparent_frame_size
,
4836 /* Load the GOT register if needed. */
4837 if (crtl
->uses_pic_offset_table
)
4838 load_got_register ();
4840 /* Advertise that the data calculated just above are now valid. */
4841 sparc_prologue_data_valid_p
= true;
4844 /* Expand the function prologue. The prologue is responsible for reserving
4845 storage for the frame, saving the call-saved registers and loading the
4846 GOT register if needed. */
4849 sparc_flat_expand_prologue (void)
4854 sparc_leaf_function_p
= optimize
> 0 && current_function_is_leaf
;
4856 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4858 if (flag_stack_usage_info
)
4859 current_function_static_stack_size
= size
;
4861 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4862 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4864 if (sparc_save_local_in_regs_p
)
4865 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
4872 rtx size_int_rtx
, size_rtx
;
4874 size_rtx
= size_int_rtx
= GEN_INT (-size
);
4876 /* We establish the frame (i.e. decrement the stack pointer) first, even
4877 if we use a frame pointer, because we cannot clobber any call-saved
4878 registers, including the frame pointer, if we haven't created a new
4879 register save area, for the sake of compatibility with the ABI. */
4881 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4882 else if (size
<= 8192 && !frame_pointer_needed
)
4884 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4885 RTX_FRAME_RELATED_P (insn
) = 1;
4886 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4890 size_rtx
= gen_rtx_REG (Pmode
, 1);
4891 emit_move_insn (size_rtx
, size_int_rtx
);
4892 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4893 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4894 gen_stack_pointer_inc (size_int_rtx
));
4896 RTX_FRAME_RELATED_P (insn
) = 1;
4898 /* Ensure nothing is scheduled until after the frame is established. */
4899 emit_insn (gen_blockage ());
4901 if (frame_pointer_needed
)
4903 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4904 gen_rtx_MINUS (Pmode
,
4907 RTX_FRAME_RELATED_P (insn
) = 1;
4909 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4910 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4911 plus_constant (stack_pointer_rtx
,
4915 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4917 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
4918 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4920 insn
= emit_move_insn (i7
, o7
);
4921 RTX_FRAME_RELATED_P (insn
) = 1;
4923 add_reg_note (insn
, REG_CFA_REGISTER
,
4924 gen_rtx_SET (VOIDmode
, i7
, o7
));
4926 /* Prevent this instruction from ever being considered dead,
4927 even if this function has no epilogue. */
4928 emit_insn (gen_rtx_USE (VOIDmode
, i7
));
4932 if (frame_pointer_needed
)
4934 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4935 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4939 sparc_frame_base_reg
= stack_pointer_rtx
;
4940 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4943 if (sparc_n_global_fp_regs
> 0)
4944 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4945 sparc_frame_base_offset
4946 - sparc_apparent_frame_size
,
4949 /* Load the GOT register if needed. */
4950 if (crtl
->uses_pic_offset_table
)
4951 load_got_register ();
4953 /* Advertise that the data calculated just above are now valid. */
4954 sparc_prologue_data_valid_p
= true;
4957 /* This function generates the assembly code for function entry, which boils
4958 down to emitting the necessary .register directives. */
4961 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4963 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4965 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
4967 sparc_output_scratch_registers (file
);
4970 /* Expand the function epilogue, either normal or part of a sibcall.
4971 We emit all the instructions except the return or the call. */
4974 sparc_expand_epilogue (bool for_eh
)
4976 HOST_WIDE_INT size
= sparc_frame_size
;
4978 if (sparc_n_global_fp_regs
> 0)
4979 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4980 sparc_frame_base_offset
4981 - sparc_apparent_frame_size
,
4984 if (size
== 0 || for_eh
)
4986 else if (sparc_leaf_function_p
)
4989 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
4990 else if (size
<= 8192)
4992 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4993 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
4997 rtx reg
= gen_rtx_REG (Pmode
, 1);
4998 emit_move_insn (reg
, GEN_INT (-size
));
4999 emit_insn (gen_stack_pointer_dec (reg
));
5004 /* Expand the function epilogue, either normal or part of a sibcall.
5005 We emit all the instructions except the return or the call. */
5008 sparc_flat_expand_epilogue (bool for_eh
)
5010 HOST_WIDE_INT size
= sparc_frame_size
;
5012 if (sparc_n_global_fp_regs
> 0)
5013 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5014 sparc_frame_base_offset
5015 - sparc_apparent_frame_size
,
5018 /* If we have a frame pointer, we'll need both to restore it before the
5019 frame is destroyed and use its current value in destroying the frame.
5020 Since we don't have an atomic way to do that in the flat window model,
5021 we save the current value into a temporary register (%g1). */
5022 if (frame_pointer_needed
&& !for_eh
)
5023 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5025 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5026 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5027 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5029 if (sparc_save_local_in_regs_p
)
5030 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5031 sparc_frame_base_offset
,
5034 if (size
== 0 || for_eh
)
5036 else if (frame_pointer_needed
)
5038 /* Make sure the frame is destroyed after everything else is done. */
5039 emit_insn (gen_blockage ());
5041 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5046 emit_insn (gen_blockage ());
5049 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
5050 else if (size
<= 8192)
5052 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5053 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5057 rtx reg
= gen_rtx_REG (Pmode
, 1);
5058 emit_move_insn (reg
, GEN_INT (-size
));
5059 emit_insn (gen_stack_pointer_dec (reg
));
5064 /* Return true if it is appropriate to emit `return' instructions in the
5065 body of a function. */
5068 sparc_can_use_return_insn_p (void)
5070 return sparc_prologue_data_valid_p
5071 && sparc_n_global_fp_regs
== 0
5073 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5074 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5077 /* This function generates the assembly code for function exit. */
5080 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5082 /* If the last two instructions of a function are "call foo; dslot;"
5083 the return address might point to the first instruction in the next
5084 function and we have to output a dummy nop for the sake of sane
5085 backtraces in such cases. This is pointless for sibling calls since
5086 the return address is explicitly adjusted. */
5088 rtx insn
, last_real_insn
;
5090 insn
= get_last_insn ();
5092 last_real_insn
= prev_real_insn (insn
);
5094 && GET_CODE (last_real_insn
) == INSN
5095 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5096 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5099 && CALL_P (last_real_insn
)
5100 && !SIBLING_CALL_P (last_real_insn
))
5101 fputs("\tnop\n", file
);
5103 sparc_output_deferred_case_vectors ();
5106 /* Output a 'restore' instruction. */
5109 output_restore (rtx pat
)
5115 fputs ("\t restore\n", asm_out_file
);
5119 gcc_assert (GET_CODE (pat
) == SET
);
5121 operands
[0] = SET_DEST (pat
);
5122 pat
= SET_SRC (pat
);
5124 switch (GET_CODE (pat
))
5127 operands
[1] = XEXP (pat
, 0);
5128 operands
[2] = XEXP (pat
, 1);
5129 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5132 operands
[1] = XEXP (pat
, 0);
5133 operands
[2] = XEXP (pat
, 1);
5134 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5137 operands
[1] = XEXP (pat
, 0);
5138 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5139 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5143 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5148 /* Output a return. */
5151 output_return (rtx insn
)
5153 if (crtl
->calls_eh_return
)
5155 /* If the function uses __builtin_eh_return, the eh_return
5156 machinery occupies the delay slot. */
5157 gcc_assert (!final_sequence
);
5159 if (flag_delayed_branch
)
5161 if (!TARGET_FLAT
&& TARGET_V9
)
5162 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5166 fputs ("\trestore\n", asm_out_file
);
5168 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5171 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5176 fputs ("\trestore\n", asm_out_file
);
5178 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5179 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5182 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5184 /* This is a leaf or flat function so we don't have to bother restoring
5185 the register window, which frees us from dealing with the convoluted
5186 semantics of restore/return. We simply output the jump to the
5187 return address and the insn in the delay slot (if any). */
5189 return "jmp\t%%o7+%)%#";
5193 /* This is a regular function so we have to restore the register window.
5194 We may have a pending insn for the delay slot, which will be either
5195 combined with the 'restore' instruction or put in the delay slot of
5196 the 'return' instruction. */
5202 delay
= NEXT_INSN (insn
);
5205 pat
= PATTERN (delay
);
5207 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5209 epilogue_renumber (&pat
, 0);
5210 return "return\t%%i7+%)%#";
5214 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5215 output_restore (pat
);
5216 PATTERN (delay
) = gen_blockage ();
5217 INSN_CODE (delay
) = -1;
5222 /* The delay slot is empty. */
5224 return "return\t%%i7+%)\n\t nop";
5225 else if (flag_delayed_branch
)
5226 return "jmp\t%%i7+%)\n\t restore";
5228 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5235 /* Output a sibling call. */
5238 output_sibcall (rtx insn
, rtx call_operand
)
5242 gcc_assert (flag_delayed_branch
);
5244 operands
[0] = call_operand
;
5246 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5248 /* This is a leaf or flat function so we don't have to bother restoring
5249 the register window. We simply output the jump to the function and
5250 the insn in the delay slot (if any). */
5252 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5255 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5258 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5259 it into branch if possible. */
5260 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5265 /* This is a regular function so we have to restore the register window.
5266 We may have a pending insn for the delay slot, which will be combined
5267 with the 'restore' instruction. */
5269 output_asm_insn ("call\t%a0, 0", operands
);
5273 rtx delay
= NEXT_INSN (insn
);
5276 output_restore (PATTERN (delay
));
5278 PATTERN (delay
) = gen_blockage ();
5279 INSN_CODE (delay
) = -1;
5282 output_restore (NULL_RTX
);
5288 /* Functions for handling argument passing.
5290 For 32-bit, the first 6 args are normally in registers and the rest are
5291 pushed. Any arg that starts within the first 6 words is at least
5292 partially passed in a register unless its data type forbids.
5294 For 64-bit, the argument registers are laid out as an array of 16 elements
5295 and arguments are added sequentially. The first 6 int args and up to the
5296 first 16 fp args (depending on size) are passed in regs.
5298 Slot Stack Integral Float Float in structure Double Long Double
5299 ---- ----- -------- ----- ------------------ ------ -----------
5300 15 [SP+248] %f31 %f30,%f31 %d30
5301 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5302 13 [SP+232] %f27 %f26,%f27 %d26
5303 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5304 11 [SP+216] %f23 %f22,%f23 %d22
5305 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5306 9 [SP+200] %f19 %f18,%f19 %d18
5307 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5308 7 [SP+184] %f15 %f14,%f15 %d14
5309 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5310 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5311 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5312 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5313 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5314 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5315 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5317 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5319 Integral arguments are always passed as 64-bit quantities appropriately
5322 Passing of floating point values is handled as follows.
5323 If a prototype is in scope:
5324 If the value is in a named argument (i.e. not a stdarg function or a
5325 value not part of the `...') then the value is passed in the appropriate
5327 If the value is part of the `...' and is passed in one of the first 6
5328 slots then the value is passed in the appropriate int reg.
5329 If the value is part of the `...' and is not passed in one of the first 6
5330 slots then the value is passed in memory.
5331 If a prototype is not in scope:
5332 If the value is one of the first 6 arguments the value is passed in the
5333 appropriate integer reg and the appropriate fp reg.
5334 If the value is not one of the first 6 arguments the value is passed in
5335 the appropriate fp reg and in memory.
5338 Summary of the calling conventions implemented by GCC on the SPARC:
5341 size argument return value
5343 small integer <4 int. reg. int. reg.
5344 word 4 int. reg. int. reg.
5345 double word 8 int. reg. int. reg.
5347 _Complex small integer <8 int. reg. int. reg.
5348 _Complex word 8 int. reg. int. reg.
5349 _Complex double word 16 memory int. reg.
5351 vector integer <=8 int. reg. FP reg.
5352 vector integer >8 memory memory
5354 float 4 int. reg. FP reg.
5355 double 8 int. reg. FP reg.
5356 long double 16 memory memory
5358 _Complex float 8 memory FP reg.
5359 _Complex double 16 memory FP reg.
5360 _Complex long double 32 memory FP reg.
5362 vector float any memory memory
5364 aggregate any memory memory
5369 size argument return value
5371 small integer <8 int. reg. int. reg.
5372 word 8 int. reg. int. reg.
5373 double word 16 int. reg. int. reg.
5375 _Complex small integer <16 int. reg. int. reg.
5376 _Complex word 16 int. reg. int. reg.
5377 _Complex double word 32 memory int. reg.
5379 vector integer <=16 FP reg. FP reg.
5380 vector integer 16<s<=32 memory FP reg.
5381 vector integer >32 memory memory
5383 float 4 FP reg. FP reg.
5384 double 8 FP reg. FP reg.
5385 long double 16 FP reg. FP reg.
5387 _Complex float 8 FP reg. FP reg.
5388 _Complex double 16 FP reg. FP reg.
5389 _Complex long double 32 memory FP reg.
5391 vector float <=16 FP reg. FP reg.
5392 vector float 16<s<=32 memory FP reg.
5393 vector float >32 memory memory
5395 aggregate <=16 reg. reg.
5396 aggregate 16<s<=32 memory reg.
5397 aggregate >32 memory memory
5401 Note #1: complex floating-point types follow the extended SPARC ABIs as
5402 implemented by the Sun compiler.
5404 Note #2: integral vector types follow the scalar floating-point types
5405 conventions to match what is implemented by the Sun VIS SDK.
5407 Note #3: floating-point vector types follow the aggregate types
5411 /* Maximum number of int regs for args. */
5412 #define SPARC_INT_ARG_MAX 6
5413 /* Maximum number of fp regs for args. */
5414 #define SPARC_FP_ARG_MAX 16
5416 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5418 /* Handle the INIT_CUMULATIVE_ARGS macro.
5419 Initialize a variable CUM of type CUMULATIVE_ARGS
5420 for a call to a function whose data type is FNTYPE.
5421 For a library call, FNTYPE is 0. */
5424 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5425 rtx libname ATTRIBUTE_UNUSED
,
5426 tree fndecl ATTRIBUTE_UNUSED
)
5429 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5430 cum
->libcall_p
= fntype
== 0;
5433 /* Handle promotion of pointer and integer arguments. */
5435 static enum machine_mode
5436 sparc_promote_function_mode (const_tree type
,
5437 enum machine_mode mode
,
5439 const_tree fntype ATTRIBUTE_UNUSED
,
5440 int for_return ATTRIBUTE_UNUSED
)
5442 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5444 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5448 /* Integral arguments are passed as full words, as per the ABI. */
5449 if (GET_MODE_CLASS (mode
) == MODE_INT
5450 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5456 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5459 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5461 return TARGET_ARCH64
? true : false;
5464 /* Scan the record type TYPE and return the following predicates:
5465 - INTREGS_P: the record contains at least one field or sub-field
5466 that is eligible for promotion in integer registers.
5467 - FP_REGS_P: the record contains at least one field or sub-field
5468 that is eligible for promotion in floating-point registers.
5469 - PACKED_P: the record contains at least one field that is packed.
5471 Sub-fields are not taken into account for the PACKED_P predicate. */
5474 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5479 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5481 if (TREE_CODE (field
) == FIELD_DECL
)
5483 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5484 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5485 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5486 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5492 if (packed_p
&& DECL_PACKED (field
))
5498 /* Compute the slot number to pass an argument in.
5499 Return the slot number or -1 if passing on the stack.
5501 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5502 the preceding args and about the function being called.
5503 MODE is the argument's machine mode.
5504 TYPE is the data type of the argument (as a tree).
5505 This is null for libcalls where that information may
5507 NAMED is nonzero if this argument is a named parameter
5508 (otherwise it is an extra parameter matching an ellipsis).
5509 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5510 *PREGNO records the register number to use if scalar type.
5511 *PPADDING records the amount of padding needed in words. */
5514 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5515 const_tree type
, bool named
, bool incoming_p
,
5516 int *pregno
, int *ppadding
)
5518 int regbase
= (incoming_p
5519 ? SPARC_INCOMING_INT_ARG_FIRST
5520 : SPARC_OUTGOING_INT_ARG_FIRST
);
5521 int slotno
= cum
->words
;
5522 enum mode_class mclass
;
5527 if (type
&& TREE_ADDRESSABLE (type
))
5533 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5536 /* For SPARC64, objects requiring 16-byte alignment get it. */
5538 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5539 && (slotno
& 1) != 0)
5540 slotno
++, *ppadding
= 1;
5542 mclass
= GET_MODE_CLASS (mode
);
5543 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5545 /* Vector types deserve special treatment because they are
5546 polymorphic wrt their mode, depending upon whether VIS
5547 instructions are enabled. */
5548 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5550 /* The SPARC port defines no floating-point vector modes. */
5551 gcc_assert (mode
== BLKmode
);
5555 /* Integral vector types should either have a vector
5556 mode or an integral mode, because we are guaranteed
5557 by pass_by_reference that their size is not greater
5558 than 16 bytes and TImode is 16-byte wide. */
5559 gcc_assert (mode
!= BLKmode
);
5561 /* Vector integers are handled like floats according to
5563 mclass
= MODE_FLOAT
;
5570 case MODE_COMPLEX_FLOAT
:
5571 case MODE_VECTOR_INT
:
5572 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5574 if (slotno
>= SPARC_FP_ARG_MAX
)
5576 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5577 /* Arguments filling only one single FP register are
5578 right-justified in the outer double FP register. */
5579 if (GET_MODE_SIZE (mode
) <= 4)
5586 case MODE_COMPLEX_INT
:
5587 if (slotno
>= SPARC_INT_ARG_MAX
)
5589 regno
= regbase
+ slotno
;
5593 if (mode
== VOIDmode
)
5594 /* MODE is VOIDmode when generating the actual call. */
5597 gcc_assert (mode
== BLKmode
);
5601 || (TREE_CODE (type
) != VECTOR_TYPE
5602 && TREE_CODE (type
) != RECORD_TYPE
))
5604 if (slotno
>= SPARC_INT_ARG_MAX
)
5606 regno
= regbase
+ slotno
;
5608 else /* TARGET_ARCH64 && type */
5610 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5612 /* First see what kinds of registers we would need. */
5613 if (TREE_CODE (type
) == VECTOR_TYPE
)
5616 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5618 /* The ABI obviously doesn't specify how packed structures
5619 are passed. These are defined to be passed in int regs
5620 if possible, otherwise memory. */
5621 if (packed_p
|| !named
)
5622 fpregs_p
= 0, intregs_p
= 1;
5624 /* If all arg slots are filled, then must pass on stack. */
5625 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5628 /* If there are only int args and all int arg slots are filled,
5629 then must pass on stack. */
5630 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5633 /* Note that even if all int arg slots are filled, fp members may
5634 still be passed in regs if such regs are available.
5635 *PREGNO isn't set because there may be more than one, it's up
5636 to the caller to compute them. */
5649 /* Handle recursive register counting for structure field layout. */
5651 struct function_arg_record_value_parms
5653 rtx ret
; /* return expression being built. */
5654 int slotno
; /* slot number of the argument. */
5655 int named
; /* whether the argument is named. */
5656 int regbase
; /* regno of the base register. */
5657 int stack
; /* 1 if part of the argument is on the stack. */
5658 int intoffset
; /* offset of the first pending integer field. */
5659 unsigned int nregs
; /* number of words passed in registers. */
5662 static void function_arg_record_value_3
5663 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5664 static void function_arg_record_value_2
5665 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5666 static void function_arg_record_value_1
5667 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5668 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
5669 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5671 /* A subroutine of function_arg_record_value. Traverse the structure
5672 recursively and determine how many registers will be required. */
5675 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
5676 struct function_arg_record_value_parms
*parms
,
5681 /* We need to compute how many registers are needed so we can
5682 allocate the PARALLEL but before we can do that we need to know
5683 whether there are any packed fields. The ABI obviously doesn't
5684 specify how structures are passed in this case, so they are
5685 defined to be passed in int regs if possible, otherwise memory,
5686 regardless of whether there are fp values present. */
5689 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5691 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5698 /* Compute how many registers we need. */
5699 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5701 if (TREE_CODE (field
) == FIELD_DECL
)
5703 HOST_WIDE_INT bitpos
= startbitpos
;
5705 if (DECL_SIZE (field
) != 0)
5707 if (integer_zerop (DECL_SIZE (field
)))
5710 if (host_integerp (bit_position (field
), 1))
5711 bitpos
+= int_bit_position (field
);
5714 /* ??? FIXME: else assume zero offset. */
5716 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5717 function_arg_record_value_1 (TREE_TYPE (field
),
5721 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5722 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5727 if (parms
->intoffset
!= -1)
5729 unsigned int startbit
, endbit
;
5730 int intslots
, this_slotno
;
5732 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5733 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5735 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5736 this_slotno
= parms
->slotno
+ parms
->intoffset
5739 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5741 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5742 /* We need to pass this field on the stack. */
5746 parms
->nregs
+= intslots
;
5747 parms
->intoffset
= -1;
5750 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5751 If it wasn't true we wouldn't be here. */
5752 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5753 && DECL_MODE (field
) == BLKmode
)
5754 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5755 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5762 if (parms
->intoffset
== -1)
5763 parms
->intoffset
= bitpos
;
5769 /* A subroutine of function_arg_record_value. Assign the bits of the
5770 structure between parms->intoffset and bitpos to integer registers. */
5773 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5774 struct function_arg_record_value_parms
*parms
)
5776 enum machine_mode mode
;
5778 unsigned int startbit
, endbit
;
5779 int this_slotno
, intslots
, intoffset
;
5782 if (parms
->intoffset
== -1)
5785 intoffset
= parms
->intoffset
;
5786 parms
->intoffset
= -1;
5788 startbit
= intoffset
& -BITS_PER_WORD
;
5789 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5790 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5791 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5793 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5797 /* If this is the trailing part of a word, only load that much into
5798 the register. Otherwise load the whole register. Note that in
5799 the latter case we may pick up unwanted bits. It's not a problem
5800 at the moment but may wish to revisit. */
5802 if (intoffset
% BITS_PER_WORD
!= 0)
5803 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5808 intoffset
/= BITS_PER_UNIT
;
5811 regno
= parms
->regbase
+ this_slotno
;
5812 reg
= gen_rtx_REG (mode
, regno
);
5813 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5814 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5817 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5822 while (intslots
> 0);
5825 /* A subroutine of function_arg_record_value. Traverse the structure
5826 recursively and assign bits to floating point registers. Track which
5827 bits in between need integer registers; invoke function_arg_record_value_3
5828 to make that happen. */
5831 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5832 struct function_arg_record_value_parms
*parms
,
5838 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5840 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5847 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5849 if (TREE_CODE (field
) == FIELD_DECL
)
5851 HOST_WIDE_INT bitpos
= startbitpos
;
5853 if (DECL_SIZE (field
) != 0)
5855 if (integer_zerop (DECL_SIZE (field
)))
5858 if (host_integerp (bit_position (field
), 1))
5859 bitpos
+= int_bit_position (field
);
5862 /* ??? FIXME: else assume zero offset. */
5864 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5865 function_arg_record_value_2 (TREE_TYPE (field
),
5869 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5870 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5875 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5876 int regno
, nregs
, pos
;
5877 enum machine_mode mode
= DECL_MODE (field
);
5880 function_arg_record_value_3 (bitpos
, parms
);
5882 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5885 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5886 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5888 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5890 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5896 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5897 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5899 reg
= gen_rtx_REG (mode
, regno
);
5900 pos
= bitpos
/ BITS_PER_UNIT
;
5901 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5902 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5906 regno
+= GET_MODE_SIZE (mode
) / 4;
5907 reg
= gen_rtx_REG (mode
, regno
);
5908 pos
+= GET_MODE_SIZE (mode
);
5909 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5910 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5916 if (parms
->intoffset
== -1)
5917 parms
->intoffset
= bitpos
;
5923 /* Used by function_arg and sparc_function_value_1 to implement the complex
5924 conventions of the 64-bit ABI for passing and returning structures.
5925 Return an expression valid as a return value for the FUNCTION_ARG
5926 and TARGET_FUNCTION_VALUE.
5928 TYPE is the data type of the argument (as a tree).
5929 This is null for libcalls where that information may
5931 MODE is the argument's machine mode.
5932 SLOTNO is the index number of the argument's slot in the parameter array.
5933 NAMED is nonzero if this argument is a named parameter
5934 (otherwise it is an extra parameter matching an ellipsis).
5935 REGBASE is the regno of the base register for the parameter array. */
5938 function_arg_record_value (const_tree type
, enum machine_mode mode
,
5939 int slotno
, int named
, int regbase
)
5941 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5942 struct function_arg_record_value_parms parms
;
5945 parms
.ret
= NULL_RTX
;
5946 parms
.slotno
= slotno
;
5947 parms
.named
= named
;
5948 parms
.regbase
= regbase
;
5951 /* Compute how many registers we need. */
5953 parms
.intoffset
= 0;
5954 function_arg_record_value_1 (type
, 0, &parms
, false);
5956 /* Take into account pending integer fields. */
5957 if (parms
.intoffset
!= -1)
5959 unsigned int startbit
, endbit
;
5960 int intslots
, this_slotno
;
5962 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5963 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5964 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5965 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5967 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5969 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5970 /* We need to pass this field on the stack. */
5974 parms
.nregs
+= intslots
;
5976 nregs
= parms
.nregs
;
5978 /* Allocate the vector and handle some annoying special cases. */
5981 /* ??? Empty structure has no value? Duh? */
5984 /* Though there's nothing really to store, return a word register
5985 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5986 leads to breakage due to the fact that there are zero bytes to
5988 return gen_rtx_REG (mode
, regbase
);
5992 /* ??? C++ has structures with no fields, and yet a size. Give up
5993 for now and pass everything back in integer registers. */
5994 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5996 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5997 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5999 gcc_assert (nregs
!= 0);
6001 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
6003 /* If at least one field must be passed on the stack, generate
6004 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6005 also be passed on the stack. We can't do much better because the
6006 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6007 of structures for which the fields passed exclusively in registers
6008 are not at the beginning of the structure. */
6010 XVECEXP (parms
.ret
, 0, 0)
6011 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6013 /* Fill in the entries. */
6015 parms
.intoffset
= 0;
6016 function_arg_record_value_2 (type
, 0, &parms
, false);
6017 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6019 gcc_assert (parms
.nregs
== nregs
);
6024 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6025 of the 64-bit ABI for passing and returning unions.
6026 Return an expression valid as a return value for the FUNCTION_ARG
6027 and TARGET_FUNCTION_VALUE.
6029 SIZE is the size in bytes of the union.
6030 MODE is the argument's machine mode.
6031 REGNO is the hard register the union will be passed in. */
6034 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6037 int nwords
= ROUND_ADVANCE (size
), i
;
6040 /* See comment in previous function for empty structures. */
6042 return gen_rtx_REG (mode
, regno
);
6044 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6047 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6049 for (i
= 0; i
< nwords
; i
++)
6051 /* Unions are passed left-justified. */
6052 XVECEXP (regs
, 0, i
)
6053 = gen_rtx_EXPR_LIST (VOIDmode
,
6054 gen_rtx_REG (word_mode
, regno
),
6055 GEN_INT (UNITS_PER_WORD
* i
));
6062 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6063 for passing and returning large (BLKmode) vectors.
6064 Return an expression valid as a return value for the FUNCTION_ARG
6065 and TARGET_FUNCTION_VALUE.
6067 SIZE is the size in bytes of the vector (at least 8 bytes).
6068 REGNO is the FP hard register the vector will be passed in. */
6071 function_arg_vector_value (int size
, int regno
)
6073 int i
, nregs
= size
/ 8;
6076 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6078 for (i
= 0; i
< nregs
; i
++)
6080 XVECEXP (regs
, 0, i
)
6081 = gen_rtx_EXPR_LIST (VOIDmode
,
6082 gen_rtx_REG (DImode
, regno
+ 2*i
),
6089 /* Determine where to put an argument to a function.
6090 Value is zero to push the argument on the stack,
6091 or a hard register in which to store the argument.
6093 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6094 the preceding args and about the function being called.
6095 MODE is the argument's machine mode.
6096 TYPE is the data type of the argument (as a tree).
6097 This is null for libcalls where that information may
6099 NAMED is true if this argument is a named parameter
6100 (otherwise it is an extra parameter matching an ellipsis).
6101 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6102 TARGET_FUNCTION_INCOMING_ARG. */
6105 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6106 const_tree type
, bool named
, bool incoming_p
)
6108 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6110 int regbase
= (incoming_p
6111 ? SPARC_INCOMING_INT_ARG_FIRST
6112 : SPARC_OUTGOING_INT_ARG_FIRST
);
6113 int slotno
, regno
, padding
;
6114 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6116 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6121 /* Vector types deserve special treatment because they are polymorphic wrt
6122 their mode, depending upon whether VIS instructions are enabled. */
6123 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6125 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6126 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6127 || (TARGET_ARCH64
&& size
<= 16));
6129 if (mode
== BLKmode
)
6130 return function_arg_vector_value (size
,
6131 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6133 mclass
= MODE_FLOAT
;
6137 return gen_rtx_REG (mode
, regno
);
6139 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6140 and are promoted to registers if possible. */
6141 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6143 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6144 gcc_assert (size
<= 16);
6146 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6149 /* Unions up to 16 bytes in size are passed in integer registers. */
6150 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6152 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6153 gcc_assert (size
<= 16);
6155 return function_arg_union_value (size
, mode
, slotno
, regno
);
6158 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6159 but also have the slot allocated for them.
6160 If no prototype is in scope fp values in register slots get passed
6161 in two places, either fp regs and int regs or fp regs and memory. */
6162 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6163 && SPARC_FP_REG_P (regno
))
6165 rtx reg
= gen_rtx_REG (mode
, regno
);
6166 if (cum
->prototype_p
|| cum
->libcall_p
)
6168 /* "* 2" because fp reg numbers are recorded in 4 byte
6171 /* ??? This will cause the value to be passed in the fp reg and
6172 in the stack. When a prototype exists we want to pass the
6173 value in the reg but reserve space on the stack. That's an
6174 optimization, and is deferred [for a bit]. */
6175 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6176 return gen_rtx_PARALLEL (mode
,
6178 gen_rtx_EXPR_LIST (VOIDmode
,
6179 NULL_RTX
, const0_rtx
),
6180 gen_rtx_EXPR_LIST (VOIDmode
,
6184 /* ??? It seems that passing back a register even when past
6185 the area declared by REG_PARM_STACK_SPACE will allocate
6186 space appropriately, and will not copy the data onto the
6187 stack, exactly as we desire.
6189 This is due to locate_and_pad_parm being called in
6190 expand_call whenever reg_parm_stack_space > 0, which
6191 while beneficial to our example here, would seem to be
6192 in error from what had been intended. Ho hum... -- r~ */
6200 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6204 /* On incoming, we don't need to know that the value
6205 is passed in %f0 and %i0, and it confuses other parts
6206 causing needless spillage even on the simplest cases. */
6210 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6211 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6213 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6214 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6216 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6220 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6221 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6222 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6227 /* All other aggregate types are passed in an integer register in a mode
6228 corresponding to the size of the type. */
6229 else if (type
&& AGGREGATE_TYPE_P (type
))
6231 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6232 gcc_assert (size
<= 16);
6234 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6237 return gen_rtx_REG (mode
, regno
);
6240 /* Handle the TARGET_FUNCTION_ARG target hook. */
6243 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6244 const_tree type
, bool named
)
6246 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6249 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6252 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6253 const_tree type
, bool named
)
6255 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6258 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6261 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6263 return ((TARGET_ARCH64
6264 && (GET_MODE_ALIGNMENT (mode
) == 128
6265 || (type
&& TYPE_ALIGN (type
) == 128)))
6270 /* For an arg passed partly in registers and partly in memory,
6271 this is the number of bytes of registers used.
6272 For args passed entirely in registers or entirely in memory, zero.
6274 Any arg that starts in the first 6 regs but won't entirely fit in them
6275 needs partial registers on v8. On v9, structures with integer
6276 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6277 values that begin in the last fp reg [where "last fp reg" varies with the
6278 mode] will be split between that reg and memory. */
6281 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6282 tree type
, bool named
)
6284 int slotno
, regno
, padding
;
6286 /* We pass false for incoming_p here, it doesn't matter. */
6287 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6288 false, ®no
, &padding
);
6295 if ((slotno
+ (mode
== BLKmode
6296 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6297 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6298 > SPARC_INT_ARG_MAX
)
6299 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6303 /* We are guaranteed by pass_by_reference that the size of the
6304 argument is not greater than 16 bytes, so we only need to return
6305 one word if the argument is partially passed in registers. */
6307 if (type
&& AGGREGATE_TYPE_P (type
))
6309 int size
= int_size_in_bytes (type
);
6311 if (size
> UNITS_PER_WORD
6312 && slotno
== SPARC_INT_ARG_MAX
- 1)
6313 return UNITS_PER_WORD
;
6315 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6316 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6317 && ! (TARGET_FPU
&& named
)))
6319 /* The complex types are passed as packed types. */
6320 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6321 && slotno
== SPARC_INT_ARG_MAX
- 1)
6322 return UNITS_PER_WORD
;
6324 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6326 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6328 return UNITS_PER_WORD
;
6335 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6336 Specify whether to pass the argument by reference. */
6339 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6340 enum machine_mode mode
, const_tree type
,
6341 bool named ATTRIBUTE_UNUSED
)
6344 /* Original SPARC 32-bit ABI says that structures and unions,
6345 and quad-precision floats are passed by reference. For Pascal,
6346 also pass arrays by reference. All other base types are passed
6349 Extended ABI (as implemented by the Sun compiler) says that all
6350 complex floats are passed by reference. Pass complex integers
6351 in registers up to 8 bytes. More generally, enforce the 2-word
6352 cap for passing arguments in registers.
6354 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6355 integers are passed like floats of the same size, that is in
6356 registers up to 8 bytes. Pass all vector floats by reference
6357 like structure and unions. */
6358 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6360 /* Catch CDImode, TFmode, DCmode and TCmode. */
6361 || GET_MODE_SIZE (mode
) > 8
6363 && TREE_CODE (type
) == VECTOR_TYPE
6364 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6366 /* Original SPARC 64-bit ABI says that structures and unions
6367 smaller than 16 bytes are passed in registers, as well as
6368 all other base types.
6370 Extended ABI (as implemented by the Sun compiler) says that
6371 complex floats are passed in registers up to 16 bytes. Pass
6372 all complex integers in registers up to 16 bytes. More generally,
6373 enforce the 2-word cap for passing arguments in registers.
6375 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6376 integers are passed like floats of the same size, that is in
6377 registers (up to 16 bytes). Pass all vector floats like structure
6380 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6381 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6382 /* Catch CTImode and TCmode. */
6383 || GET_MODE_SIZE (mode
) > 16);
6386 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6387 Update the data in CUM to advance over an argument
6388 of mode MODE and data type TYPE.
6389 TYPE is null for libcalls where that information may not be available. */
6392 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6393 const_tree type
, bool named
)
6395 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6398 /* We pass false for incoming_p here, it doesn't matter. */
6399 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6401 /* If argument requires leading padding, add it. */
6402 cum
->words
+= padding
;
6406 cum
->words
+= (mode
!= BLKmode
6407 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6408 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6412 if (type
&& AGGREGATE_TYPE_P (type
))
6414 int size
= int_size_in_bytes (type
);
6418 else if (size
<= 16)
6420 else /* passed by reference */
6425 cum
->words
+= (mode
!= BLKmode
6426 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6427 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6432 /* Handle the FUNCTION_ARG_PADDING macro.
6433 For the 64 bit ABI structs are always stored left shifted in their
6437 function_arg_padding (enum machine_mode mode
, const_tree type
)
6439 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6442 /* Fall back to the default. */
6443 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6446 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6447 Specify whether to return the return value in memory. */
6450 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6453 /* Original SPARC 32-bit ABI says that structures and unions,
6454 and quad-precision floats are returned in memory. All other
6455 base types are returned in registers.
6457 Extended ABI (as implemented by the Sun compiler) says that
6458 all complex floats are returned in registers (8 FP registers
6459 at most for '_Complex long double'). Return all complex integers
6460 in registers (4 at most for '_Complex long long').
6462 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6463 integers are returned like floats of the same size, that is in
6464 registers up to 8 bytes and in memory otherwise. Return all
6465 vector floats in memory like structure and unions; note that
6466 they always have BLKmode like the latter. */
6467 return (TYPE_MODE (type
) == BLKmode
6468 || TYPE_MODE (type
) == TFmode
6469 || (TREE_CODE (type
) == VECTOR_TYPE
6470 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6472 /* Original SPARC 64-bit ABI says that structures and unions
6473 smaller than 32 bytes are returned in registers, as well as
6474 all other base types.
6476 Extended ABI (as implemented by the Sun compiler) says that all
6477 complex floats are returned in registers (8 FP registers at most
6478 for '_Complex long double'). Return all complex integers in
6479 registers (4 at most for '_Complex TItype').
6481 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6482 integers are returned like floats of the same size, that is in
6483 registers. Return all vector floats like structure and unions;
6484 note that they always have BLKmode like the latter. */
6485 return (TYPE_MODE (type
) == BLKmode
6486 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6489 /* Handle the TARGET_STRUCT_VALUE target hook.
6490 Return where to find the structure return value address. */
6493 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6502 mem
= gen_frame_mem (Pmode
, plus_constant (frame_pointer_rtx
,
6503 STRUCT_VALUE_OFFSET
));
6505 mem
= gen_frame_mem (Pmode
, plus_constant (stack_pointer_rtx
,
6506 STRUCT_VALUE_OFFSET
));
6508 /* Only follow the SPARC ABI for fixed-size structure returns.
6509 Variable size structure returns are handled per the normal
6510 procedures in GCC. This is enabled by -mstd-struct-return */
6512 && sparc_std_struct_return
6513 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6514 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6516 /* We must check and adjust the return address, as it is
6517 optional as to whether the return object is really
6519 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6520 rtx scratch
= gen_reg_rtx (SImode
);
6521 rtx endlab
= gen_label_rtx ();
6523 /* Calculate the return object size */
6524 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6525 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6526 /* Construct a temporary return value */
6528 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6530 /* Implement SPARC 32-bit psABI callee return struct checking:
6532 Fetch the instruction where we will return to and see if
6533 it's an unimp instruction (the most significant 10 bits
6535 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6536 plus_constant (ret_reg
, 8)));
6537 /* Assume the size is valid and pre-adjust */
6538 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6539 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6541 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6542 /* Write the address of the memory pointed to by temp_val into
6543 the memory pointed to by mem */
6544 emit_move_insn (mem
, XEXP (temp_val
, 0));
6545 emit_label (endlab
);
6552 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6553 For v9, function return values are subject to the same rules as arguments,
6554 except that up to 32 bytes may be returned in registers. */
6557 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6560 /* Beware that the two values are swapped here wrt function_arg. */
6561 int regbase
= (outgoing
6562 ? SPARC_INCOMING_INT_ARG_FIRST
6563 : SPARC_OUTGOING_INT_ARG_FIRST
);
6564 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6567 /* Vector types deserve special treatment because they are polymorphic wrt
6568 their mode, depending upon whether VIS instructions are enabled. */
6569 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6571 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6572 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6573 || (TARGET_ARCH64
&& size
<= 32));
6575 if (mode
== BLKmode
)
6576 return function_arg_vector_value (size
,
6577 SPARC_FP_ARG_FIRST
);
6579 mclass
= MODE_FLOAT
;
6582 if (TARGET_ARCH64
&& type
)
6584 /* Structures up to 32 bytes in size are returned in registers. */
6585 if (TREE_CODE (type
) == RECORD_TYPE
)
6587 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6588 gcc_assert (size
<= 32);
6590 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6593 /* Unions up to 32 bytes in size are returned in integer registers. */
6594 else if (TREE_CODE (type
) == UNION_TYPE
)
6596 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6597 gcc_assert (size
<= 32);
6599 return function_arg_union_value (size
, mode
, 0, regbase
);
6602 /* Objects that require it are returned in FP registers. */
6603 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6606 /* All other aggregate types are returned in an integer register in a
6607 mode corresponding to the size of the type. */
6608 else if (AGGREGATE_TYPE_P (type
))
6610 /* All other aggregate types are passed in an integer register
6611 in a mode corresponding to the size of the type. */
6612 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6613 gcc_assert (size
<= 32);
6615 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6617 /* ??? We probably should have made the same ABI change in
6618 3.4.0 as the one we made for unions. The latter was
6619 required by the SCD though, while the former is not
6620 specified, so we favored compatibility and efficiency.
6622 Now we're stuck for aggregates larger than 16 bytes,
6623 because OImode vanished in the meantime. Let's not
6624 try to be unduly clever, and simply follow the ABI
6625 for unions in that case. */
6626 if (mode
== BLKmode
)
6627 return function_arg_union_value (size
, mode
, 0, regbase
);
6632 /* We should only have pointer and integer types at this point. This
6633 must match sparc_promote_function_mode. */
6634 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6638 /* We should only have pointer and integer types at this point. This must
6639 match sparc_promote_function_mode. */
6640 else if (TARGET_ARCH32
6641 && mclass
== MODE_INT
6642 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6645 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6646 regno
= SPARC_FP_ARG_FIRST
;
6650 return gen_rtx_REG (mode
, regno
);
6653 /* Handle TARGET_FUNCTION_VALUE.
6654 On the SPARC, the value is found in the first "output" register, but the
6655 called function leaves it in the first "input" register. */
6658 sparc_function_value (const_tree valtype
,
6659 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6662 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
6665 /* Handle TARGET_LIBCALL_VALUE. */
6668 sparc_libcall_value (enum machine_mode mode
,
6669 const_rtx fun ATTRIBUTE_UNUSED
)
6671 return sparc_function_value_1 (NULL_TREE
, mode
, false);
6674 /* Handle FUNCTION_VALUE_REGNO_P.
6675 On the SPARC, the first "output" reg is used for integer values, and the
6676 first floating point register is used for floating point values. */
6679 sparc_function_value_regno_p (const unsigned int regno
)
6681 return (regno
== 8 || regno
== 32);
6684 /* Do what is necessary for `va_start'. We look at the current function
6685 to determine if stdarg or varargs is used and return the address of
6686 the first unnamed parameter. */
6689 sparc_builtin_saveregs (void)
6691 int first_reg
= crtl
->args
.info
.words
;
6695 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6696 emit_move_insn (gen_rtx_MEM (word_mode
,
6697 gen_rtx_PLUS (Pmode
,
6699 GEN_INT (FIRST_PARM_OFFSET (0)
6702 gen_rtx_REG (word_mode
,
6703 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6705 address
= gen_rtx_PLUS (Pmode
,
6707 GEN_INT (FIRST_PARM_OFFSET (0)
6708 + UNITS_PER_WORD
* first_reg
));
6713 /* Implement `va_start' for stdarg. */
6716 sparc_va_start (tree valist
, rtx nextarg
)
6718 nextarg
= expand_builtin_saveregs ();
6719 std_expand_builtin_va_start (valist
, nextarg
);
6722 /* Implement `va_arg' for stdarg. */
6725 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6728 HOST_WIDE_INT size
, rsize
, align
;
6731 tree ptrtype
= build_pointer_type (type
);
6733 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6736 size
= rsize
= UNITS_PER_WORD
;
6742 size
= int_size_in_bytes (type
);
6743 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6748 /* For SPARC64, objects requiring 16-byte alignment get it. */
6749 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6750 align
= 2 * UNITS_PER_WORD
;
6752 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6753 are left-justified in their slots. */
6754 if (AGGREGATE_TYPE_P (type
))
6757 size
= rsize
= UNITS_PER_WORD
;
6767 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
6768 incr
= fold_convert (sizetype
, incr
);
6769 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
6771 incr
= fold_convert (ptr_type_node
, incr
);
6774 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6777 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6778 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
6782 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6783 addr
= build_va_arg_indirect_ref (addr
);
6786 /* If the address isn't aligned properly for the type, we need a temporary.
6787 FIXME: This is inefficient, usually we can do this in registers. */
6788 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6790 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6791 tree dest_addr
= build_fold_addr_expr (tmp
);
6792 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6793 3, dest_addr
, addr
, size_int (rsize
));
6794 TREE_ADDRESSABLE (tmp
) = 1;
6795 gimplify_and_add (copy
, pre_p
);
6800 addr
= fold_convert (ptrtype
, addr
);
6802 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
6803 gimplify_assign (valist
, incr
, post_p
);
6805 return build_va_arg_indirect_ref (addr
);
6808 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6809 Specify whether the vector mode is supported by the hardware. */
6812 sparc_vector_mode_supported_p (enum machine_mode mode
)
6814 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6817 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6819 static enum machine_mode
6820 sparc_preferred_simd_mode (enum machine_mode mode
)
6838 /* Return the string to output an unconditional branch to LABEL, which is
6839 the operand number of the label.
6841 DEST is the destination insn (i.e. the label), INSN is the source. */
6844 output_ubranch (rtx dest
, int label
, rtx insn
)
6846 static char string
[64];
6847 bool v9_form
= false;
6850 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6852 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6853 - INSN_ADDRESSES (INSN_UID (insn
)));
6854 /* Leave some instructions for "slop". */
6855 if (delta
>= -260000 && delta
< 260000)
6860 strcpy (string
, "ba%*,pt\t%%xcc, ");
6862 strcpy (string
, "b%*\t");
6864 p
= strchr (string
, '\0');
6875 /* Return the string to output a conditional branch to LABEL, which is
6876 the operand number of the label. OP is the conditional expression.
6877 XEXP (OP, 0) is assumed to be a condition code register (integer or
6878 floating point) and its mode specifies what kind of comparison we made.
6880 DEST is the destination insn (i.e. the label), INSN is the source.
6882 REVERSED is nonzero if we should reverse the sense of the comparison.
6884 ANNUL is nonzero if we should generate an annulling branch. */
6887 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6890 static char string
[64];
6891 enum rtx_code code
= GET_CODE (op
);
6892 rtx cc_reg
= XEXP (op
, 0);
6893 enum machine_mode mode
= GET_MODE (cc_reg
);
6894 const char *labelno
, *branch
;
6895 int spaces
= 8, far
;
6898 /* v9 branches are limited to +-1MB. If it is too far away,
6911 fbne,a,pn %fcc2, .LC29
6919 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6922 /* Reversal of FP compares takes care -- an ordered compare
6923 becomes an unordered compare and vice versa. */
6924 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6925 code
= reverse_condition_maybe_unordered (code
);
6927 code
= reverse_condition (code
);
6930 /* Start by writing the branch condition. */
6931 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6982 /* ??? !v9: FP branches cannot be preceded by another floating point
6983 insn. Because there is currently no concept of pre-delay slots,
6984 we can fix this only by always emitting a nop before a floating
6989 strcpy (string
, "nop\n\t");
6990 strcat (string
, branch
);
7003 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7015 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7036 strcpy (string
, branch
);
7038 spaces
-= strlen (branch
);
7039 p
= strchr (string
, '\0');
7041 /* Now add the annulling, the label, and a possible noop. */
7054 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7056 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7057 - INSN_ADDRESSES (INSN_UID (insn
)));
7058 /* Leave some instructions for "slop". */
7059 if (delta
< -260000 || delta
>= 260000)
7063 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7065 static char v9_fcc_labelno
[] = "%%fccX, ";
7066 /* Set the char indicating the number of the fcc reg to use. */
7067 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7068 labelno
= v9_fcc_labelno
;
7071 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7075 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7077 labelno
= "%%xcc, ";
7082 labelno
= "%%icc, ";
7087 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7090 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7103 strcpy (p
, labelno
);
7104 p
= strchr (p
, '\0');
7107 strcpy (p
, ".+12\n\t nop\n\tb\t");
7108 /* Skip the next insn if requested or
7109 if we know that it will be a nop. */
7110 if (annul
|| ! final_sequence
)
7124 /* Emit a library call comparison between floating point X and Y.
7125 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7126 Return the new operator to be used in the comparison sequence.
7128 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7129 values as arguments instead of the TFmode registers themselves,
7130 that's why we cannot call emit_float_lib_cmp. */
7133 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7136 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7137 enum machine_mode mode
;
7138 enum rtx_code new_comparison
;
7143 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7147 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7151 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7155 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7159 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7163 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7174 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7187 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7188 emit_move_insn (slot0
, x
);
7195 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7196 emit_move_insn (slot1
, y
);
7199 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7200 emit_library_call (libfunc
, LCT_NORMAL
,
7202 XEXP (slot0
, 0), Pmode
,
7203 XEXP (slot1
, 0), Pmode
);
7208 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7209 emit_library_call (libfunc
, LCT_NORMAL
,
7211 x
, TFmode
, y
, TFmode
);
7216 /* Immediately move the result of the libcall into a pseudo
7217 register so reload doesn't clobber the value if it needs
7218 the return register for a spill reg. */
7219 result
= gen_reg_rtx (mode
);
7220 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7225 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7228 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7229 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7232 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7233 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7235 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7237 tem
= gen_reg_rtx (mode
);
7239 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7241 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7242 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7245 tem
= gen_reg_rtx (mode
);
7247 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7249 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7250 tem2
= gen_reg_rtx (mode
);
7252 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7254 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7255 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7256 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7262 /* Generate an unsigned DImode to FP conversion. This is the same code
7263 optabs would emit if we didn't have TFmode patterns. */
7266 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7268 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7271 in
= force_reg (DImode
, operands
[1]);
7272 neglab
= gen_label_rtx ();
7273 donelab
= gen_label_rtx ();
7274 i0
= gen_reg_rtx (DImode
);
7275 i1
= gen_reg_rtx (DImode
);
7276 f0
= gen_reg_rtx (mode
);
7278 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7280 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7281 emit_jump_insn (gen_jump (donelab
));
7284 emit_label (neglab
);
7286 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7287 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7288 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7289 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7290 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7292 emit_label (donelab
);
7295 /* Generate an FP to unsigned DImode conversion. This is the same code
7296 optabs would emit if we didn't have TFmode patterns. */
7299 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7301 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7304 in
= force_reg (mode
, operands
[1]);
7305 neglab
= gen_label_rtx ();
7306 donelab
= gen_label_rtx ();
7307 i0
= gen_reg_rtx (DImode
);
7308 i1
= gen_reg_rtx (DImode
);
7309 limit
= gen_reg_rtx (mode
);
7310 f0
= gen_reg_rtx (mode
);
7312 emit_move_insn (limit
,
7313 CONST_DOUBLE_FROM_REAL_VALUE (
7314 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7315 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7317 emit_insn (gen_rtx_SET (VOIDmode
,
7319 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7320 emit_jump_insn (gen_jump (donelab
));
7323 emit_label (neglab
);
7325 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7326 emit_insn (gen_rtx_SET (VOIDmode
,
7328 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7329 emit_insn (gen_movdi (i1
, const1_rtx
));
7330 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7331 emit_insn (gen_xordi3 (out
, i0
, i1
));
7333 emit_label (donelab
);
7336 /* Return the string to output a conditional branch to LABEL, testing
7337 register REG. LABEL is the operand number of the label; REG is the
7338 operand number of the reg. OP is the conditional expression. The mode
7339 of REG says what kind of comparison we made.
7341 DEST is the destination insn (i.e. the label), INSN is the source.
7343 REVERSED is nonzero if we should reverse the sense of the comparison.
7345 ANNUL is nonzero if we should generate an annulling branch. */
7348 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7349 int annul
, rtx insn
)
7351 static char string
[64];
7352 enum rtx_code code
= GET_CODE (op
);
7353 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7358 /* branch on register are limited to +-128KB. If it is too far away,
7371 brgez,a,pn %o1, .LC29
7377 ba,pt %xcc, .LC29 */
7379 far
= get_attr_length (insn
) >= 3;
7381 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7383 code
= reverse_condition (code
);
7385 /* Only 64 bit versions of these instructions exist. */
7386 gcc_assert (mode
== DImode
);
7388 /* Start by writing the branch condition. */
7393 strcpy (string
, "brnz");
7397 strcpy (string
, "brz");
7401 strcpy (string
, "brgez");
7405 strcpy (string
, "brlz");
7409 strcpy (string
, "brlez");
7413 strcpy (string
, "brgz");
7420 p
= strchr (string
, '\0');
7422 /* Now add the annulling, reg, label, and nop. */
7429 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7432 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7437 *p
= p
< string
+ 8 ? '\t' : ' ';
7445 int veryfar
= 1, delta
;
7447 if (INSN_ADDRESSES_SET_P ())
7449 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7450 - INSN_ADDRESSES (INSN_UID (insn
)));
7451 /* Leave some instructions for "slop". */
7452 if (delta
>= -260000 && delta
< 260000)
7456 strcpy (p
, ".+12\n\t nop\n\t");
7457 /* Skip the next insn if requested or
7458 if we know that it will be a nop. */
7459 if (annul
|| ! final_sequence
)
7469 strcpy (p
, "ba,pt\t%%xcc, ");
7483 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7484 Such instructions cannot be used in the delay slot of return insn on v9.
7485 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7489 epilogue_renumber (register rtx
*where
, int test
)
7491 register const char *fmt
;
7493 register enum rtx_code code
;
7498 code
= GET_CODE (*where
);
7503 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7505 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7506 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7514 /* Do not replace the frame pointer with the stack pointer because
7515 it can cause the delayed instruction to load below the stack.
7516 This occurs when instructions like:
7518 (set (reg/i:SI 24 %i0)
7519 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7520 (const_int -20 [0xffffffec])) 0))
7522 are in the return delayed slot. */
7524 if (GET_CODE (XEXP (*where
, 0)) == REG
7525 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7526 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7527 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7532 if (SPARC_STACK_BIAS
7533 && GET_CODE (XEXP (*where
, 0)) == REG
7534 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7542 fmt
= GET_RTX_FORMAT (code
);
7544 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7549 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7550 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7553 else if (fmt
[i
] == 'e'
7554 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7560 /* Leaf functions and non-leaf functions have different needs. */
7563 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7566 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7568 static const int *const reg_alloc_orders
[] = {
7569 reg_leaf_alloc_order
,
7570 reg_nonleaf_alloc_order
};
7573 order_regs_for_local_alloc (void)
7575 static int last_order_nonleaf
= 1;
7577 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
7579 last_order_nonleaf
= !last_order_nonleaf
;
7580 memcpy ((char *) reg_alloc_order
,
7581 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7582 FIRST_PSEUDO_REGISTER
* sizeof (int));
7586 /* Return 1 if REG and MEM are legitimate enough to allow the various
7587 mem<-->reg splits to be run. */
7590 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7592 /* Punt if we are here by mistake. */
7593 gcc_assert (reload_completed
);
7595 /* We must have an offsettable memory reference. */
7596 if (! offsettable_memref_p (mem
))
7599 /* If we have legitimate args for ldd/std, we do not want
7600 the split to happen. */
7601 if ((REGNO (reg
) % 2) == 0
7602 && mem_min_alignment (mem
, 8))
7609 /* Return 1 if x and y are some kind of REG and they refer to
7610 different hard registers. This test is guaranteed to be
7611 run after reload. */
7614 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7616 if (GET_CODE (x
) != REG
)
7618 if (GET_CODE (y
) != REG
)
7620 if (REGNO (x
) == REGNO (y
))
7625 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7626 This makes them candidates for using ldd and std insns.
7628 Note reg1 and reg2 *must* be hard registers. */
7631 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7633 /* We might have been passed a SUBREG. */
7634 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7637 if (REGNO (reg1
) % 2 != 0)
7640 /* Integer ldd is deprecated in SPARC V9 */
7641 if (TARGET_V9
&& REGNO (reg1
) < 32)
7644 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7647 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7650 This can only happen when addr1 and addr2, the addresses in mem1
7651 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7652 addr1 must also be aligned on a 64-bit boundary.
7654 Also iff dependent_reg_rtx is not null it should not be used to
7655 compute the address for mem1, i.e. we cannot optimize a sequence
7667 But, note that the transformation from:
7672 is perfectly fine. Thus, the peephole2 patterns always pass us
7673 the destination register of the first load, never the second one.
7675 For stores we don't have a similar problem, so dependent_reg_rtx is
7679 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7683 HOST_WIDE_INT offset1
;
7685 /* The mems cannot be volatile. */
7686 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7689 /* MEM1 should be aligned on a 64-bit boundary. */
7690 if (MEM_ALIGN (mem1
) < 64)
7693 addr1
= XEXP (mem1
, 0);
7694 addr2
= XEXP (mem2
, 0);
7696 /* Extract a register number and offset (if used) from the first addr. */
7697 if (GET_CODE (addr1
) == PLUS
)
7699 /* If not a REG, return zero. */
7700 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7704 reg1
= REGNO (XEXP (addr1
, 0));
7705 /* The offset must be constant! */
7706 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7708 offset1
= INTVAL (XEXP (addr1
, 1));
7711 else if (GET_CODE (addr1
) != REG
)
7715 reg1
= REGNO (addr1
);
7716 /* This was a simple (mem (reg)) expression. Offset is 0. */
7720 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7721 if (GET_CODE (addr2
) != PLUS
)
7724 if (GET_CODE (XEXP (addr2
, 0)) != REG
7725 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7728 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7731 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7734 /* The first offset must be evenly divisible by 8 to ensure the
7735 address is 64 bit aligned. */
7736 if (offset1
% 8 != 0)
7739 /* The offset for the second addr must be 4 more than the first addr. */
7740 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7743 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7748 /* Return 1 if reg is a pseudo, or is the first register in
7749 a hard register pair. This makes it suitable for use in
7750 ldd and std insns. */
7753 register_ok_for_ldd (rtx reg
)
7755 /* We might have been passed a SUBREG. */
7759 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7760 return (REGNO (reg
) % 2 == 0);
7765 /* Return 1 if OP is a memory whose address is known to be
7766 aligned to 8-byte boundary, or a pseudo during reload.
7767 This makes it suitable for use in ldd and std insns. */
7770 memory_ok_for_ldd (rtx op
)
7774 /* In 64-bit mode, we assume that the address is word-aligned. */
7775 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
7778 if ((reload_in_progress
|| reload_completed
)
7779 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
7782 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7784 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
7793 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7796 sparc_print_operand_punct_valid_p (unsigned char code
)
7809 /* Implement TARGET_PRINT_OPERAND.
7810 Print operand X (an rtx) in assembler syntax to file FILE.
7811 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7812 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7815 sparc_print_operand (FILE *file
, rtx x
, int code
)
7820 /* Output an insn in a delay slot. */
7822 sparc_indent_opcode
= 1;
7824 fputs ("\n\t nop", file
);
7827 /* Output an annul flag if there's nothing for the delay slot and we
7828 are optimizing. This is always used with '(' below.
7829 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7830 this is a dbx bug. So, we only do this when optimizing.
7831 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7832 Always emit a nop in case the next instruction is a branch. */
7833 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7837 /* Output a 'nop' if there's nothing for the delay slot and we are
7838 not optimizing. This is always used with '*' above. */
7839 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7840 fputs ("\n\t nop", file
);
7841 else if (final_sequence
)
7842 sparc_indent_opcode
= 1;
7845 /* Output the right displacement from the saved PC on function return.
7846 The caller may have placed an "unimp" insn immediately after the call
7847 so we have to account for it. This insn is used in the 32-bit ABI
7848 when calling a function that returns a non zero-sized structure. The
7849 64-bit ABI doesn't have it. Be careful to have this test be the same
7850 as that for the call. The exception is when sparc_std_struct_return
7851 is enabled, the psABI is followed exactly and the adjustment is made
7852 by the code in sparc_struct_value_rtx. The call emitted is the same
7853 when sparc_std_struct_return is enabled. */
7855 && cfun
->returns_struct
7856 && !sparc_std_struct_return
7857 && DECL_SIZE (DECL_RESULT (current_function_decl
))
7858 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7860 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7866 /* Output the Embedded Medium/Anywhere code model base register. */
7867 fputs (EMBMEDANY_BASE_REG
, file
);
7870 /* Print some local dynamic TLS name. */
7871 assemble_name (file
, get_some_local_dynamic_name ());
7875 /* Adjust the operand to take into account a RESTORE operation. */
7876 if (GET_CODE (x
) == CONST_INT
)
7878 else if (GET_CODE (x
) != REG
)
7879 output_operand_lossage ("invalid %%Y operand");
7880 else if (REGNO (x
) < 8)
7881 fputs (reg_names
[REGNO (x
)], file
);
7882 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
7883 fputs (reg_names
[REGNO (x
)-16], file
);
7885 output_operand_lossage ("invalid %%Y operand");
7888 /* Print out the low order register name of a register pair. */
7889 if (WORDS_BIG_ENDIAN
)
7890 fputs (reg_names
[REGNO (x
)+1], file
);
7892 fputs (reg_names
[REGNO (x
)], file
);
7895 /* Print out the high order register name of a register pair. */
7896 if (WORDS_BIG_ENDIAN
)
7897 fputs (reg_names
[REGNO (x
)], file
);
7899 fputs (reg_names
[REGNO (x
)+1], file
);
7902 /* Print out the second register name of a register pair or quad.
7903 I.e., R (%o0) => %o1. */
7904 fputs (reg_names
[REGNO (x
)+1], file
);
7907 /* Print out the third register name of a register quad.
7908 I.e., S (%o0) => %o2. */
7909 fputs (reg_names
[REGNO (x
)+2], file
);
7912 /* Print out the fourth register name of a register quad.
7913 I.e., T (%o0) => %o3. */
7914 fputs (reg_names
[REGNO (x
)+3], file
);
7917 /* Print a condition code register. */
7918 if (REGNO (x
) == SPARC_ICC_REG
)
7920 /* We don't handle CC[X]_NOOVmode because they're not supposed
7922 if (GET_MODE (x
) == CCmode
)
7923 fputs ("%icc", file
);
7924 else if (GET_MODE (x
) == CCXmode
)
7925 fputs ("%xcc", file
);
7930 /* %fccN register */
7931 fputs (reg_names
[REGNO (x
)], file
);
7934 /* Print the operand's address only. */
7935 output_address (XEXP (x
, 0));
7938 /* In this case we need a register. Use %g0 if the
7939 operand is const0_rtx. */
7941 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7943 fputs ("%g0", file
);
7950 switch (GET_CODE (x
))
7952 case IOR
: fputs ("or", file
); break;
7953 case AND
: fputs ("and", file
); break;
7954 case XOR
: fputs ("xor", file
); break;
7955 default: output_operand_lossage ("invalid %%A operand");
7960 switch (GET_CODE (x
))
7962 case IOR
: fputs ("orn", file
); break;
7963 case AND
: fputs ("andn", file
); break;
7964 case XOR
: fputs ("xnor", file
); break;
7965 default: output_operand_lossage ("invalid %%B operand");
7969 /* These are used by the conditional move instructions. */
7973 enum rtx_code rc
= GET_CODE (x
);
7977 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7978 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7979 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7981 rc
= reverse_condition (GET_CODE (x
));
7985 case NE
: fputs ("ne", file
); break;
7986 case EQ
: fputs ("e", file
); break;
7987 case GE
: fputs ("ge", file
); break;
7988 case GT
: fputs ("g", file
); break;
7989 case LE
: fputs ("le", file
); break;
7990 case LT
: fputs ("l", file
); break;
7991 case GEU
: fputs ("geu", file
); break;
7992 case GTU
: fputs ("gu", file
); break;
7993 case LEU
: fputs ("leu", file
); break;
7994 case LTU
: fputs ("lu", file
); break;
7995 case LTGT
: fputs ("lg", file
); break;
7996 case UNORDERED
: fputs ("u", file
); break;
7997 case ORDERED
: fputs ("o", file
); break;
7998 case UNLT
: fputs ("ul", file
); break;
7999 case UNLE
: fputs ("ule", file
); break;
8000 case UNGT
: fputs ("ug", file
); break;
8001 case UNGE
: fputs ("uge", file
); break;
8002 case UNEQ
: fputs ("ue", file
); break;
8003 default: output_operand_lossage (code
== 'c'
8004 ? "invalid %%c operand"
8005 : "invalid %%C operand");
8010 /* These are used by the movr instruction pattern. */
8014 enum rtx_code rc
= (code
== 'd'
8015 ? reverse_condition (GET_CODE (x
))
8019 case NE
: fputs ("ne", file
); break;
8020 case EQ
: fputs ("e", file
); break;
8021 case GE
: fputs ("gez", file
); break;
8022 case LT
: fputs ("lz", file
); break;
8023 case LE
: fputs ("lez", file
); break;
8024 case GT
: fputs ("gz", file
); break;
8025 default: output_operand_lossage (code
== 'd'
8026 ? "invalid %%d operand"
8027 : "invalid %%D operand");
8034 /* Print a sign-extended character. */
8035 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8036 fprintf (file
, "%d", i
);
8041 /* Operand must be a MEM; write its address. */
8042 if (GET_CODE (x
) != MEM
)
8043 output_operand_lossage ("invalid %%f operand");
8044 output_address (XEXP (x
, 0));
8049 /* Print a sign-extended 32-bit value. */
8051 if (GET_CODE(x
) == CONST_INT
)
8053 else if (GET_CODE(x
) == CONST_DOUBLE
)
8054 i
= CONST_DOUBLE_LOW (x
);
8057 output_operand_lossage ("invalid %%s operand");
8060 i
= trunc_int_for_mode (i
, SImode
);
8061 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8066 /* Do nothing special. */
8070 /* Undocumented flag. */
8071 output_operand_lossage ("invalid operand output code");
8074 if (GET_CODE (x
) == REG
)
8075 fputs (reg_names
[REGNO (x
)], file
);
8076 else if (GET_CODE (x
) == MEM
)
8079 /* Poor Sun assembler doesn't understand absolute addressing. */
8080 if (CONSTANT_P (XEXP (x
, 0)))
8081 fputs ("%g0+", file
);
8082 output_address (XEXP (x
, 0));
8085 else if (GET_CODE (x
) == HIGH
)
8087 fputs ("%hi(", file
);
8088 output_addr_const (file
, XEXP (x
, 0));
8091 else if (GET_CODE (x
) == LO_SUM
)
8093 sparc_print_operand (file
, XEXP (x
, 0), 0);
8094 if (TARGET_CM_MEDMID
)
8095 fputs ("+%l44(", file
);
8097 fputs ("+%lo(", file
);
8098 output_addr_const (file
, XEXP (x
, 1));
8101 else if (GET_CODE (x
) == CONST_DOUBLE
8102 && (GET_MODE (x
) == VOIDmode
8103 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8105 if (CONST_DOUBLE_HIGH (x
) == 0)
8106 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8107 else if (CONST_DOUBLE_HIGH (x
) == -1
8108 && CONST_DOUBLE_LOW (x
) < 0)
8109 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8111 output_operand_lossage ("long long constant not a valid immediate operand");
8113 else if (GET_CODE (x
) == CONST_DOUBLE
)
8114 output_operand_lossage ("floating point constant not a valid immediate operand");
8115 else { output_addr_const (file
, x
); }
8118 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8121 sparc_print_operand_address (FILE *file
, rtx x
)
8123 register rtx base
, index
= 0;
8125 register rtx addr
= x
;
8128 fputs (reg_names
[REGNO (addr
)], file
);
8129 else if (GET_CODE (addr
) == PLUS
)
8131 if (CONST_INT_P (XEXP (addr
, 0)))
8132 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8133 else if (CONST_INT_P (XEXP (addr
, 1)))
8134 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8136 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8137 if (GET_CODE (base
) == LO_SUM
)
8139 gcc_assert (USE_AS_OFFSETABLE_LO10
8141 && ! TARGET_CM_MEDMID
);
8142 output_operand (XEXP (base
, 0), 0);
8143 fputs ("+%lo(", file
);
8144 output_address (XEXP (base
, 1));
8145 fprintf (file
, ")+%d", offset
);
8149 fputs (reg_names
[REGNO (base
)], file
);
8151 fprintf (file
, "%+d", offset
);
8152 else if (REG_P (index
))
8153 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8154 else if (GET_CODE (index
) == SYMBOL_REF
8155 || GET_CODE (index
) == LABEL_REF
8156 || GET_CODE (index
) == CONST
)
8157 fputc ('+', file
), output_addr_const (file
, index
);
8158 else gcc_unreachable ();
8161 else if (GET_CODE (addr
) == MINUS
8162 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8164 output_addr_const (file
, XEXP (addr
, 0));
8166 output_addr_const (file
, XEXP (addr
, 1));
8167 fputs ("-.)", file
);
8169 else if (GET_CODE (addr
) == LO_SUM
)
8171 output_operand (XEXP (addr
, 0), 0);
8172 if (TARGET_CM_MEDMID
)
8173 fputs ("+%l44(", file
);
8175 fputs ("+%lo(", file
);
8176 output_address (XEXP (addr
, 1));
8180 && GET_CODE (addr
) == CONST
8181 && GET_CODE (XEXP (addr
, 0)) == MINUS
8182 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8183 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8184 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8186 addr
= XEXP (addr
, 0);
8187 output_addr_const (file
, XEXP (addr
, 0));
8188 /* Group the args of the second CONST in parenthesis. */
8190 /* Skip past the second CONST--it does nothing for us. */
8191 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8192 /* Close the parenthesis. */
8197 output_addr_const (file
, addr
);
8201 /* Target hook for assembling integer objects. The sparc version has
8202 special handling for aligned DI-mode objects. */
8205 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8207 /* ??? We only output .xword's for symbols and only then in environments
8208 where the assembler can handle them. */
8209 if (aligned_p
&& size
== 8
8210 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8214 assemble_integer_with_op ("\t.xword\t", x
);
8219 assemble_aligned_integer (4, const0_rtx
);
8220 assemble_aligned_integer (4, x
);
8224 return default_assemble_integer (x
, size
, aligned_p
);
8227 /* Return the value of a code used in the .proc pseudo-op that says
8228 what kind of result this function returns. For non-C types, we pick
8229 the closest C type. */
8231 #ifndef SHORT_TYPE_SIZE
8232 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8235 #ifndef INT_TYPE_SIZE
8236 #define INT_TYPE_SIZE BITS_PER_WORD
8239 #ifndef LONG_TYPE_SIZE
8240 #define LONG_TYPE_SIZE BITS_PER_WORD
8243 #ifndef LONG_LONG_TYPE_SIZE
8244 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8247 #ifndef FLOAT_TYPE_SIZE
8248 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8251 #ifndef DOUBLE_TYPE_SIZE
8252 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8255 #ifndef LONG_DOUBLE_TYPE_SIZE
8256 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8260 sparc_type_code (register tree type
)
8262 register unsigned long qualifiers
= 0;
8263 register unsigned shift
;
8265 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8266 setting more, since some assemblers will give an error for this. Also,
8267 we must be careful to avoid shifts of 32 bits or more to avoid getting
8268 unpredictable results. */
8270 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8272 switch (TREE_CODE (type
))
8278 qualifiers
|= (3 << shift
);
8283 qualifiers
|= (2 << shift
);
8287 case REFERENCE_TYPE
:
8289 qualifiers
|= (1 << shift
);
8293 return (qualifiers
| 8);
8296 case QUAL_UNION_TYPE
:
8297 return (qualifiers
| 9);
8300 return (qualifiers
| 10);
8303 return (qualifiers
| 16);
8306 /* If this is a range type, consider it to be the underlying
8308 if (TREE_TYPE (type
) != 0)
8311 /* Carefully distinguish all the standard types of C,
8312 without messing up if the language is not C. We do this by
8313 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8314 look at both the names and the above fields, but that's redundant.
8315 Any type whose size is between two C types will be considered
8316 to be the wider of the two types. Also, we do not have a
8317 special code to use for "long long", so anything wider than
8318 long is treated the same. Note that we can't distinguish
8319 between "int" and "long" in this code if they are the same
8320 size, but that's fine, since neither can the assembler. */
8322 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8323 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8325 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8326 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8328 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8329 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8332 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8335 /* If this is a range type, consider it to be the underlying
8337 if (TREE_TYPE (type
) != 0)
8340 /* Carefully distinguish all the standard types of C,
8341 without messing up if the language is not C. */
8343 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8344 return (qualifiers
| 6);
8347 return (qualifiers
| 7);
8349 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8350 /* ??? We need to distinguish between double and float complex types,
8351 but I don't know how yet because I can't reach this code from
8352 existing front-ends. */
8353 return (qualifiers
| 7); /* Who knows? */
8356 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8362 gcc_unreachable (); /* Not a type! */
8369 /* Nested function support. */
8371 /* Emit RTL insns to initialize the variable parts of a trampoline.
8372 FNADDR is an RTX for the address of the function's pure code.
8373 CXT is an RTX for the static chain value for the function.
8375 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8376 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8377 (to store insns). This is a bit excessive. Perhaps a different
8378 mechanism would be better here.
8380 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8383 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8385 /* SPARC 32-bit trampoline:
8388 sethi %hi(static), %g2
8390 or %g2, %lo(static), %g2
8392 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8393 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8397 (adjust_address (m_tramp
, SImode
, 0),
8398 expand_binop (SImode
, ior_optab
,
8399 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8400 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8401 NULL_RTX
, 1, OPTAB_DIRECT
));
8404 (adjust_address (m_tramp
, SImode
, 4),
8405 expand_binop (SImode
, ior_optab
,
8406 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8407 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8408 NULL_RTX
, 1, OPTAB_DIRECT
));
8411 (adjust_address (m_tramp
, SImode
, 8),
8412 expand_binop (SImode
, ior_optab
,
8413 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8414 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8415 NULL_RTX
, 1, OPTAB_DIRECT
));
8418 (adjust_address (m_tramp
, SImode
, 12),
8419 expand_binop (SImode
, ior_optab
,
8420 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8421 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8422 NULL_RTX
, 1, OPTAB_DIRECT
));
8424 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8425 aligned on a 16 byte boundary so one flush clears it all. */
8426 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8427 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8428 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8429 && sparc_cpu
!= PROCESSOR_NIAGARA
8430 && sparc_cpu
!= PROCESSOR_NIAGARA2
8431 && sparc_cpu
!= PROCESSOR_NIAGARA3
8432 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8433 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8435 /* Call __enable_execute_stack after writing onto the stack to make sure
8436 the stack address is accessible. */
8437 #ifdef HAVE_ENABLE_EXECUTE_STACK
8438 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8439 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8444 /* The 64-bit version is simpler because it makes more sense to load the
8445 values as "immediate" data out of the trampoline. It's also easier since
8446 we can read the PC without clobbering a register. */
8449 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8451 /* SPARC 64-bit trampoline:
8460 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8461 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8462 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8463 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8464 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8465 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8466 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8467 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8468 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8469 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8470 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8472 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8473 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8474 && sparc_cpu
!= PROCESSOR_NIAGARA
8475 && sparc_cpu
!= PROCESSOR_NIAGARA2
8476 && sparc_cpu
!= PROCESSOR_NIAGARA3
8477 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8478 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8480 /* Call __enable_execute_stack after writing onto the stack to make sure
8481 the stack address is accessible. */
8482 #ifdef HAVE_ENABLE_EXECUTE_STACK
8483 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8484 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8488 /* Worker for TARGET_TRAMPOLINE_INIT. */
8491 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8493 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8494 cxt
= force_reg (Pmode
, cxt
);
8496 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8498 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8501 /* Adjust the cost of a scheduling dependency. Return the new cost of
8502 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8505 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8507 enum attr_type insn_type
;
8509 if (! recog_memoized (insn
))
8512 insn_type
= get_attr_type (insn
);
8514 if (REG_NOTE_KIND (link
) == 0)
8516 /* Data dependency; DEP_INSN writes a register that INSN reads some
8519 /* if a load, then the dependence must be on the memory address;
8520 add an extra "cycle". Note that the cost could be two cycles
8521 if the reg was written late in an instruction group; we ca not tell
8523 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
8526 /* Get the delay only if the address of the store is the dependence. */
8527 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
8529 rtx pat
= PATTERN(insn
);
8530 rtx dep_pat
= PATTERN (dep_insn
);
8532 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8533 return cost
; /* This should not happen! */
8535 /* The dependency between the two instructions was on the data that
8536 is being stored. Assume that this implies that the address of the
8537 store is not dependent. */
8538 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8541 return cost
+ 3; /* An approximation. */
8544 /* A shift instruction cannot receive its data from an instruction
8545 in the same cycle; add a one cycle penalty. */
8546 if (insn_type
== TYPE_SHIFT
)
8547 return cost
+ 3; /* Split before cascade into shift. */
8551 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8552 INSN writes some cycles later. */
8554 /* These are only significant for the fpu unit; writing a fp reg before
8555 the fpu has finished with it stalls the processor. */
8557 /* Reusing an integer register causes no problems. */
8558 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8566 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8568 enum attr_type insn_type
, dep_type
;
8569 rtx pat
= PATTERN(insn
);
8570 rtx dep_pat
= PATTERN (dep_insn
);
8572 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
8575 insn_type
= get_attr_type (insn
);
8576 dep_type
= get_attr_type (dep_insn
);
8578 switch (REG_NOTE_KIND (link
))
8581 /* Data dependency; DEP_INSN writes a register that INSN reads some
8588 /* Get the delay iff the address of the store is the dependence. */
8589 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8592 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8599 /* If a load, then the dependence must be on the memory address. If
8600 the addresses aren't equal, then it might be a false dependency */
8601 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
8603 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
8604 || GET_CODE (SET_DEST (dep_pat
)) != MEM
8605 || GET_CODE (SET_SRC (pat
)) != MEM
8606 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
8607 XEXP (SET_SRC (pat
), 0)))
8615 /* Compare to branch latency is 0. There is no benefit from
8616 separating compare and branch. */
8617 if (dep_type
== TYPE_COMPARE
)
8619 /* Floating point compare to branch latency is less than
8620 compare to conditional move. */
8621 if (dep_type
== TYPE_FPCMP
)
8630 /* Anti-dependencies only penalize the fpu unit. */
8631 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8643 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
8647 case PROCESSOR_SUPERSPARC
:
8648 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
8650 case PROCESSOR_HYPERSPARC
:
8651 case PROCESSOR_SPARCLITE86X
:
8652 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8661 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8662 int sched_verbose ATTRIBUTE_UNUSED
,
8663 int max_ready ATTRIBUTE_UNUSED
)
8667 sparc_use_sched_lookahead (void)
8669 if (sparc_cpu
== PROCESSOR_NIAGARA
8670 || sparc_cpu
== PROCESSOR_NIAGARA2
8671 || sparc_cpu
== PROCESSOR_NIAGARA3
8672 || sparc_cpu
== PROCESSOR_NIAGARA4
)
8674 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8675 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8677 if ((1 << sparc_cpu
) &
8678 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8679 (1 << PROCESSOR_SPARCLITE86X
)))
8685 sparc_issue_rate (void)
8689 case PROCESSOR_NIAGARA
:
8690 case PROCESSOR_NIAGARA2
:
8691 case PROCESSOR_NIAGARA3
:
8692 case PROCESSOR_NIAGARA4
:
8696 /* Assume V9 processors are capable of at least dual-issue. */
8698 case PROCESSOR_SUPERSPARC
:
8700 case PROCESSOR_HYPERSPARC
:
8701 case PROCESSOR_SPARCLITE86X
:
8703 case PROCESSOR_ULTRASPARC
:
8704 case PROCESSOR_ULTRASPARC3
:
8710 set_extends (rtx insn
)
8712 register rtx pat
= PATTERN (insn
);
8714 switch (GET_CODE (SET_SRC (pat
)))
8716 /* Load and some shift instructions zero extend. */
8719 /* sethi clears the high bits */
8721 /* LO_SUM is used with sethi. sethi cleared the high
8722 bits and the values used with lo_sum are positive */
8724 /* Store flag stores 0 or 1 */
8734 rtx op0
= XEXP (SET_SRC (pat
), 0);
8735 rtx op1
= XEXP (SET_SRC (pat
), 1);
8736 if (GET_CODE (op1
) == CONST_INT
)
8737 return INTVAL (op1
) >= 0;
8738 if (GET_CODE (op0
) != REG
)
8740 if (sparc_check_64 (op0
, insn
) == 1)
8742 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8747 rtx op0
= XEXP (SET_SRC (pat
), 0);
8748 rtx op1
= XEXP (SET_SRC (pat
), 1);
8749 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8751 if (GET_CODE (op1
) == CONST_INT
)
8752 return INTVAL (op1
) >= 0;
8753 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8756 return GET_MODE (SET_SRC (pat
)) == SImode
;
8757 /* Positive integers leave the high bits zero. */
8759 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8761 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8764 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8766 return sparc_check_64 (SET_SRC (pat
), insn
);
8772 /* We _ought_ to have only one kind per function, but... */
8773 static GTY(()) rtx sparc_addr_diff_list
;
8774 static GTY(()) rtx sparc_addr_list
;
8777 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8779 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8781 sparc_addr_diff_list
8782 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8784 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8788 sparc_output_addr_vec (rtx vec
)
8790 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8791 int idx
, vlen
= XVECLEN (body
, 0);
8793 #ifdef ASM_OUTPUT_ADDR_VEC_START
8794 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8797 #ifdef ASM_OUTPUT_CASE_LABEL
8798 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8801 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8804 for (idx
= 0; idx
< vlen
; idx
++)
8806 ASM_OUTPUT_ADDR_VEC_ELT
8807 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8810 #ifdef ASM_OUTPUT_ADDR_VEC_END
8811 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8816 sparc_output_addr_diff_vec (rtx vec
)
8818 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8819 rtx base
= XEXP (XEXP (body
, 0), 0);
8820 int idx
, vlen
= XVECLEN (body
, 1);
8822 #ifdef ASM_OUTPUT_ADDR_VEC_START
8823 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8826 #ifdef ASM_OUTPUT_CASE_LABEL
8827 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8830 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8833 for (idx
= 0; idx
< vlen
; idx
++)
8835 ASM_OUTPUT_ADDR_DIFF_ELT
8838 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8839 CODE_LABEL_NUMBER (base
));
8842 #ifdef ASM_OUTPUT_ADDR_VEC_END
8843 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8848 sparc_output_deferred_case_vectors (void)
8853 if (sparc_addr_list
== NULL_RTX
8854 && sparc_addr_diff_list
== NULL_RTX
)
8857 /* Align to cache line in the function's code section. */
8858 switch_to_section (current_function_section ());
8860 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8862 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8864 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8865 sparc_output_addr_vec (XEXP (t
, 0));
8866 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8867 sparc_output_addr_diff_vec (XEXP (t
, 0));
8869 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8872 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8873 unknown. Return 1 if the high bits are zero, -1 if the register is
8876 sparc_check_64 (rtx x
, rtx insn
)
8878 /* If a register is set only once it is safe to ignore insns this
8879 code does not know how to handle. The loop will either recognize
8880 the single set and return the correct value or fail to recognize
8885 gcc_assert (GET_CODE (x
) == REG
);
8887 if (GET_MODE (x
) == DImode
)
8888 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
8890 if (flag_expensive_optimizations
8891 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
8897 insn
= get_last_insn_anywhere ();
8902 while ((insn
= PREV_INSN (insn
)))
8904 switch (GET_CODE (insn
))
8917 rtx pat
= PATTERN (insn
);
8918 if (GET_CODE (pat
) != SET
)
8920 if (rtx_equal_p (x
, SET_DEST (pat
)))
8921 return set_extends (insn
);
8922 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
8923 return set_extends (insn
);
8924 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8932 /* Returns assembly code to perform a DImode shift using
8933 a 64-bit global or out register on SPARC-V8+. */
8935 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
8937 static char asm_code
[60];
8939 /* The scratch register is only required when the destination
8940 register is not a 64-bit global or out register. */
8941 if (which_alternative
!= 2)
8942 operands
[3] = operands
[0];
8944 /* We can only shift by constants <= 63. */
8945 if (GET_CODE (operands
[2]) == CONST_INT
)
8946 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
8948 if (GET_CODE (operands
[1]) == CONST_INT
)
8950 output_asm_insn ("mov\t%1, %3", operands
);
8954 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8955 if (sparc_check_64 (operands
[1], insn
) <= 0)
8956 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8957 output_asm_insn ("or\t%L1, %3, %3", operands
);
8960 strcpy(asm_code
, opcode
);
8962 if (which_alternative
!= 2)
8963 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8965 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8968 /* Output rtl to increment the profiler label LABELNO
8969 for profiling a function entry. */
8972 sparc_profile_hook (int labelno
)
8977 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8978 if (NO_PROFILE_COUNTERS
)
8980 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
8984 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8985 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8986 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8990 #ifdef TARGET_SOLARIS
8991 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8994 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
8995 tree decl ATTRIBUTE_UNUSED
)
8997 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
8999 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9003 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9005 if (!(flags
& SECTION_DEBUG
))
9006 fputs (",#alloc", asm_out_file
);
9007 if (flags
& SECTION_WRITE
)
9008 fputs (",#write", asm_out_file
);
9009 if (flags
& SECTION_TLS
)
9010 fputs (",#tls", asm_out_file
);
9011 if (flags
& SECTION_CODE
)
9012 fputs (",#execinstr", asm_out_file
);
9014 /* ??? Handle SECTION_BSS. */
9016 fputc ('\n', asm_out_file
);
9018 #endif /* TARGET_SOLARIS */
9020 /* We do not allow indirect calls to be optimized into sibling calls.
9022 We cannot use sibling calls when delayed branches are disabled
9023 because they will likely require the call delay slot to be filled.
9025 Also, on SPARC 32-bit we cannot emit a sibling call when the
9026 current function returns a structure. This is because the "unimp
9027 after call" convention would cause the callee to return to the
9028 wrong place. The generic code already disallows cases where the
9029 function being called returns a structure.
9031 It may seem strange how this last case could occur. Usually there
9032 is code after the call which jumps to epilogue code which dumps the
9033 return value into the struct return area. That ought to invalidate
9034 the sibling call right? Well, in the C++ case we can end up passing
9035 the pointer to the struct return area to a constructor (which returns
9036 void) and then nothing else happens. Such a sibling call would look
9037 valid without the added check here.
9039 VxWorks PIC PLT entries require the global pointer to be initialized
9040 on entry. We therefore can't emit sibling calls to them. */
9042 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9045 && flag_delayed_branch
9046 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9047 && !(TARGET_VXWORKS_RTP
9049 && !targetm
.binds_local_p (decl
)));
9052 /* libfunc renaming. */
9055 sparc_init_libfuncs (void)
9059 /* Use the subroutines that Sun's library provides for integer
9060 multiply and divide. The `*' prevents an underscore from
9061 being prepended by the compiler. .umul is a little faster
9063 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9064 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9065 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9066 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9067 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9069 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9070 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9071 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9072 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9073 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9074 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9076 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9077 is because with soft-float, the SFmode and DFmode sqrt
9078 instructions will be absent, and the compiler will notice and
9079 try to use the TFmode sqrt instruction for calls to the
9080 builtin function sqrt, but this fails. */
9082 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9084 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9085 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9086 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9087 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9088 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9089 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9091 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9092 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9093 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9094 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9096 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9097 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9098 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9099 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9101 if (DITF_CONVERSION_LIBFUNCS
)
9103 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9104 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9105 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9106 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9109 if (SUN_CONVERSION_LIBFUNCS
)
9111 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9112 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9113 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9114 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9119 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9120 do not exist in the library. Make sure the compiler does not
9121 emit calls to them by accident. (It should always use the
9122 hardware instructions.) */
9123 set_optab_libfunc (smul_optab
, SImode
, 0);
9124 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9125 set_optab_libfunc (udiv_optab
, SImode
, 0);
9126 set_optab_libfunc (smod_optab
, SImode
, 0);
9127 set_optab_libfunc (umod_optab
, SImode
, 0);
9129 if (SUN_INTEGER_MULTIPLY_64
)
9131 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9132 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9133 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9134 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9135 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9138 if (SUN_CONVERSION_LIBFUNCS
)
9140 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9141 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9142 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9143 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9148 static tree
def_builtin(const char *name
, int code
, tree type
)
9150 return add_builtin_function(name
, type
, code
, BUILT_IN_MD
, NULL
,
9154 static tree
def_builtin_const(const char *name
, int code
, tree type
)
9156 tree t
= def_builtin(name
, code
, type
);
9159 TREE_READONLY (t
) = 1;
9164 /* Implement the TARGET_INIT_BUILTINS target hook.
9165 Create builtin functions for special SPARC instructions. */
9168 sparc_init_builtins (void)
9171 sparc_vis_init_builtins ();
9174 /* Create builtin functions for VIS 1.0 instructions. */
9177 sparc_vis_init_builtins (void)
9179 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9180 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9181 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9182 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9183 tree v2si
= build_vector_type (intSI_type_node
, 2);
9184 tree v1si
= build_vector_type (intSI_type_node
, 1);
9186 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9187 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9188 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9189 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9190 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9191 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9192 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9193 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9194 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9195 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9196 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9197 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9198 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
9199 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
9200 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9202 intDI_type_node
, 0);
9203 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
9205 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
9207 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9209 intDI_type_node
, 0);
9210 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
9212 intSI_type_node
, 0);
9213 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9215 intSI_type_node
, 0);
9216 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9218 intDI_type_node
, 0);
9219 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
9222 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
9225 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
9227 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
9229 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
9231 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
9233 tree void_ftype_di
= build_function_type_list (void_type_node
,
9234 intDI_type_node
, 0);
9235 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
9237 tree void_ftype_si
= build_function_type_list (void_type_node
,
9238 intSI_type_node
, 0);
9240 /* Packing and expanding vectors. */
9241 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
9243 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9244 v8qi_ftype_v2si_v8qi
);
9245 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9247 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
9249 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9250 v8qi_ftype_v4qi_v4qi
);
9252 /* Multiplications. */
9253 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9254 v4hi_ftype_v4qi_v4hi
);
9255 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9256 v4hi_ftype_v4qi_v2hi
);
9257 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9258 v4hi_ftype_v4qi_v2hi
);
9259 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9260 v4hi_ftype_v8qi_v4hi
);
9261 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9262 v4hi_ftype_v8qi_v4hi
);
9263 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9264 v2si_ftype_v4qi_v2hi
);
9265 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9266 v2si_ftype_v4qi_v2hi
);
9268 /* Data aligning. */
9269 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9270 v4hi_ftype_v4hi_v4hi
);
9271 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9272 v8qi_ftype_v8qi_v8qi
);
9273 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9274 v2si_ftype_v2si_v2si
);
9275 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
9278 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
9280 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
9285 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9287 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
9292 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9294 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
9298 /* Pixel distance. */
9299 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9300 di_ftype_v8qi_v8qi_di
);
9302 /* Edge handling. */
9305 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
9307 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
9309 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
9311 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
9313 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
9315 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
9319 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
9321 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
9323 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
9325 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
9327 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
9329 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
9335 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
9337 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
9339 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
9341 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
9343 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
9345 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
9349 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
9351 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
9353 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
9355 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
9357 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
9359 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
9364 /* Pixel compare. */
9367 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
9368 di_ftype_v4hi_v4hi
);
9369 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
9370 di_ftype_v2si_v2si
);
9371 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
9372 di_ftype_v4hi_v4hi
);
9373 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
9374 di_ftype_v2si_v2si
);
9375 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
9376 di_ftype_v4hi_v4hi
);
9377 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
9378 di_ftype_v2si_v2si
);
9379 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
9380 di_ftype_v4hi_v4hi
);
9381 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
9382 di_ftype_v2si_v2si
);
9386 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
9387 si_ftype_v4hi_v4hi
);
9388 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
9389 si_ftype_v2si_v2si
);
9390 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
9391 si_ftype_v4hi_v4hi
);
9392 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
9393 si_ftype_v2si_v2si
);
9394 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
9395 si_ftype_v4hi_v4hi
);
9396 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
9397 si_ftype_v2si_v2si
);
9398 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
9399 si_ftype_v4hi_v4hi
);
9400 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
9401 si_ftype_v2si_v2si
);
9404 /* Addition and subtraction. */
9405 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
9406 v4hi_ftype_v4hi_v4hi
);
9407 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
9408 v2hi_ftype_v2hi_v2hi
);
9409 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
9410 v2si_ftype_v2si_v2si
);
9411 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addsi3
,
9412 v1si_ftype_v1si_v1si
);
9413 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
9414 v4hi_ftype_v4hi_v4hi
);
9415 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
9416 v2hi_ftype_v2hi_v2hi
);
9417 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
9418 v2si_ftype_v2si_v2si
);
9419 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subsi3
,
9420 v1si_ftype_v1si_v1si
);
9422 /* Three-dimensional array addressing. */
9425 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
9427 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
9429 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
9434 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
9436 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
9438 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
9444 /* Byte mask and shuffle */
9446 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
9449 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
9451 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
9452 v4hi_ftype_v4hi_v4hi
);
9453 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
9454 v8qi_ftype_v8qi_v8qi
);
9455 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
9456 v2si_ftype_v2si_v2si
);
9457 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshuffledi_vis
,
9465 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
9467 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
9469 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
9474 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
9476 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
9478 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
9482 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
9483 v4hi_ftype_v4hi_v4hi
);
9485 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_fsll16_vis
,
9486 v4hi_ftype_v4hi_v4hi
);
9487 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_fslas16_vis
,
9488 v4hi_ftype_v4hi_v4hi
);
9489 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_fsrl16_vis
,
9490 v4hi_ftype_v4hi_v4hi
);
9491 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_fsra16_vis
,
9492 v4hi_ftype_v4hi_v4hi
);
9493 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_fsll32_vis
,
9494 v2si_ftype_v2si_v2si
);
9495 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_fslas32_vis
,
9496 v2si_ftype_v2si_v2si
);
9497 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_fsrl32_vis
,
9498 v2si_ftype_v2si_v2si
);
9499 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_fsra32_vis
,
9500 v2si_ftype_v2si_v2si
);
9503 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
9504 di_ftype_v8qi_v8qi
);
9506 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
9507 si_ftype_v8qi_v8qi
);
9509 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
9510 v4hi_ftype_v4hi_v4hi
);
9511 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
9513 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
9516 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_fpadds16_vis
,
9517 v4hi_ftype_v4hi_v4hi
);
9518 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_fpadds16s_vis
,
9519 v2hi_ftype_v2hi_v2hi
);
9520 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_fpsubs16_vis
,
9521 v4hi_ftype_v4hi_v4hi
);
9522 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_fpsubs16s_vis
,
9523 v2hi_ftype_v2hi_v2hi
);
9524 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_fpadds32_vis
,
9525 v2si_ftype_v2si_v2si
);
9526 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_fpadds32s_vis
,
9527 v1si_ftype_v1si_v1si
);
9528 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_fpsubs32_vis
,
9529 v2si_ftype_v2si_v2si
);
9530 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_fpsubs32s_vis
,
9531 v1si_ftype_v1si_v1si
);
9535 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
9536 di_ftype_v8qi_v8qi
);
9537 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
9538 di_ftype_v8qi_v8qi
);
9539 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
9540 di_ftype_v8qi_v8qi
);
9541 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
9542 di_ftype_v8qi_v8qi
);
9546 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
9547 si_ftype_v8qi_v8qi
);
9548 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
9549 si_ftype_v8qi_v8qi
);
9550 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
9551 si_ftype_v8qi_v8qi
);
9552 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
9553 si_ftype_v8qi_v8qi
);
9558 /* Handle TARGET_EXPAND_BUILTIN target hook.
9559 Expand builtin functions for sparc intrinsics. */
9562 sparc_expand_builtin (tree exp
, rtx target
,
9563 rtx subtarget ATTRIBUTE_UNUSED
,
9564 enum machine_mode tmode ATTRIBUTE_UNUSED
,
9565 int ignore ATTRIBUTE_UNUSED
)
9568 call_expr_arg_iterator iter
;
9569 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9570 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
9575 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9579 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9581 || GET_MODE (target
) != tmode
9582 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9583 op
[0] = gen_reg_rtx (tmode
);
9587 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9589 const struct insn_operand_data
*insn_op
;
9592 if (arg
== error_mark_node
)
9596 idx
= arg_count
- !nonvoid
;
9597 insn_op
= &insn_data
[icode
].operand
[idx
];
9598 op
[arg_count
] = expand_normal (arg
);
9600 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
9602 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
9608 pat
= GEN_FCN (icode
) (op
[0]);
9612 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
9614 pat
= GEN_FCN (icode
) (op
[1]);
9617 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
9620 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
9638 sparc_vis_mul8x16 (int e8
, int e16
)
9640 return (e8
* e16
+ 128) / 256;
9643 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9644 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9645 constants. A tree list with the results of the multiplications is returned,
9646 and each element in the list is of INNER_TYPE. */
9649 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
9651 tree n_elts
= NULL_TREE
;
9656 case CODE_FOR_fmul8x16_vis
:
9657 for (; elts0
&& elts1
;
9658 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9661 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9662 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
9663 n_elts
= tree_cons (NULL_TREE
,
9664 build_int_cst (inner_type
, val
),
9669 case CODE_FOR_fmul8x16au_vis
:
9670 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9672 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9675 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9677 n_elts
= tree_cons (NULL_TREE
,
9678 build_int_cst (inner_type
, val
),
9683 case CODE_FOR_fmul8x16al_vis
:
9684 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
9686 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9689 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9691 n_elts
= tree_cons (NULL_TREE
,
9692 build_int_cst (inner_type
, val
),
9701 return nreverse (n_elts
);
9704 /* Handle TARGET_FOLD_BUILTIN target hook.
9705 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9706 result of the function call is ignored. NULL_TREE is returned if the
9707 function could not be folded. */
9710 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
9711 tree
*args
, bool ignore
)
9713 tree arg0
, arg1
, arg2
;
9714 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
9715 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
9719 /* Note that a switch statement instead of the sequence of tests would
9720 be incorrect as many of the CODE_FOR values could be CODE_FOR_nothing
9721 and that would yield multiple alternatives with identical values. */
9722 if (icode
== CODE_FOR_alignaddrsi_vis
9723 || icode
== CODE_FOR_alignaddrdi_vis
9724 || icode
== CODE_FOR_wrgsr_vis
9725 || icode
== CODE_FOR_bmasksi_vis
9726 || icode
== CODE_FOR_bmaskdi_vis
9727 || icode
== CODE_FOR_cmask8si_vis
9728 || icode
== CODE_FOR_cmask8di_vis
9729 || icode
== CODE_FOR_cmask16si_vis
9730 || icode
== CODE_FOR_cmask16di_vis
9731 || icode
== CODE_FOR_cmask32si_vis
9732 || icode
== CODE_FOR_cmask32di_vis
)
9735 return build_zero_cst (rtype
);
9740 case CODE_FOR_fexpand_vis
:
9744 if (TREE_CODE (arg0
) == VECTOR_CST
)
9746 tree inner_type
= TREE_TYPE (rtype
);
9747 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
9748 tree n_elts
= NULL_TREE
;
9750 for (; elts
; elts
= TREE_CHAIN (elts
))
9752 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
9753 n_elts
= tree_cons (NULL_TREE
,
9754 build_int_cst (inner_type
, val
),
9757 return build_vector (rtype
, nreverse (n_elts
));
9761 case CODE_FOR_fmul8x16_vis
:
9762 case CODE_FOR_fmul8x16au_vis
:
9763 case CODE_FOR_fmul8x16al_vis
:
9769 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9771 tree inner_type
= TREE_TYPE (rtype
);
9772 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9773 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9774 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
9777 return build_vector (rtype
, n_elts
);
9781 case CODE_FOR_fpmerge_vis
:
9787 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9789 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9790 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9791 tree n_elts
= NULL_TREE
;
9793 for (; elts0
&& elts1
;
9794 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9796 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
9797 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
9800 return build_vector (rtype
, nreverse (n_elts
));
9804 case CODE_FOR_pdist_vis
:
9812 if (TREE_CODE (arg0
) == VECTOR_CST
9813 && TREE_CODE (arg1
) == VECTOR_CST
9814 && TREE_CODE (arg2
) == INTEGER_CST
)
9817 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
9818 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
9819 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9820 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9822 for (; elts0
&& elts1
;
9823 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9825 unsigned HOST_WIDE_INT
9826 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9827 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9828 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
9829 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
9831 unsigned HOST_WIDE_INT l
;
9834 overflow
|= neg_double (low1
, high1
, &l
, &h
);
9835 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
9837 overflow
|= neg_double (l
, h
, &l
, &h
);
9839 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
9842 gcc_assert (overflow
== 0);
9844 return build_int_cst_wide (rtype
, low
, high
);
9854 /* ??? This duplicates information provided to the compiler by the
9855 ??? scheduler description. Some day, teach genautomata to output
9856 ??? the latencies and then CSE will just use that. */
9859 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
9860 int *total
, bool speed ATTRIBUTE_UNUSED
)
9862 enum machine_mode mode
= GET_MODE (x
);
9863 bool float_mode_p
= FLOAT_MODE_P (mode
);
9868 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
9886 if (GET_MODE (x
) == VOIDmode
9887 && ((CONST_DOUBLE_HIGH (x
) == 0
9888 && CONST_DOUBLE_LOW (x
) < 0x1000)
9889 || (CONST_DOUBLE_HIGH (x
) == -1
9890 && CONST_DOUBLE_LOW (x
) < 0
9891 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
9898 /* If outer-code was a sign or zero extension, a cost
9899 of COSTS_N_INSNS (1) was already added in. This is
9900 why we are subtracting it back out. */
9901 if (outer_code
== ZERO_EXTEND
)
9903 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
9905 else if (outer_code
== SIGN_EXTEND
)
9907 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
9909 else if (float_mode_p
)
9911 *total
= sparc_costs
->float_load
;
9915 *total
= sparc_costs
->int_load
;
9923 *total
= sparc_costs
->float_plusminus
;
9925 *total
= COSTS_N_INSNS (1);
9932 gcc_assert (float_mode_p
);
9933 *total
= sparc_costs
->float_mul
;
9936 if (GET_CODE (sub
) == NEG
)
9937 sub
= XEXP (sub
, 0);
9938 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
9941 if (GET_CODE (sub
) == NEG
)
9942 sub
= XEXP (sub
, 0);
9943 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
9949 *total
= sparc_costs
->float_mul
;
9950 else if (! TARGET_HARD_MUL
)
9951 *total
= COSTS_N_INSNS (25);
9957 if (sparc_costs
->int_mul_bit_factor
)
9961 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9963 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
9964 for (nbits
= 0; value
!= 0; value
&= value
- 1)
9967 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
9968 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
9970 rtx x1
= XEXP (x
, 1);
9971 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
9972 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
9974 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
9976 for (; value2
!= 0; value2
&= value2
- 1)
9984 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
9985 bit_cost
= COSTS_N_INSNS (bit_cost
);
9989 *total
= sparc_costs
->int_mulX
+ bit_cost
;
9991 *total
= sparc_costs
->int_mul
+ bit_cost
;
9998 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
10007 if (mode
== DFmode
)
10008 *total
= sparc_costs
->float_div_df
;
10010 *total
= sparc_costs
->float_div_sf
;
10014 if (mode
== DImode
)
10015 *total
= sparc_costs
->int_divX
;
10017 *total
= sparc_costs
->int_div
;
10022 if (! float_mode_p
)
10024 *total
= COSTS_N_INSNS (1);
10031 case UNSIGNED_FLOAT
:
10035 case FLOAT_TRUNCATE
:
10036 *total
= sparc_costs
->float_move
;
10040 if (mode
== DFmode
)
10041 *total
= sparc_costs
->float_sqrt_df
;
10043 *total
= sparc_costs
->float_sqrt_sf
;
10048 *total
= sparc_costs
->float_cmp
;
10050 *total
= COSTS_N_INSNS (1);
10055 *total
= sparc_costs
->float_cmove
;
10057 *total
= sparc_costs
->int_cmove
;
10061 /* Handle the NAND vector patterns. */
10062 if (sparc_vector_mode_supported_p (GET_MODE (x
))
10063 && GET_CODE (XEXP (x
, 0)) == NOT
10064 && GET_CODE (XEXP (x
, 1)) == NOT
)
10066 *total
= COSTS_N_INSNS (1);
10077 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
10080 general_or_i64_p (reg_class_t rclass
)
10082 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
10085 /* Implement TARGET_REGISTER_MOVE_COST. */
10088 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10089 reg_class_t from
, reg_class_t to
)
10091 if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
10092 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
))
10093 || from
== FPCC_REGS
10094 || to
== FPCC_REGS
)
10096 if (sparc_cpu
== PROCESSOR_ULTRASPARC
10097 || sparc_cpu
== PROCESSOR_ULTRASPARC3
10098 || sparc_cpu
== PROCESSOR_NIAGARA
10099 || sparc_cpu
== PROCESSOR_NIAGARA2
10100 || sparc_cpu
== PROCESSOR_NIAGARA3
10101 || sparc_cpu
== PROCESSOR_NIAGARA4
)
10110 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
10111 This is achieved by means of a manual dynamic stack space allocation in
10112 the current frame. We make the assumption that SEQ doesn't contain any
10113 function calls, with the possible exception of calls to the GOT helper. */
10116 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
10118 /* We must preserve the lowest 16 words for the register save area. */
10119 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
10120 /* We really need only 2 words of fresh stack space. */
10121 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
10124 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
10125 SPARC_STACK_BIAS
+ offset
));
10127 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
10128 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
10130 emit_insn (gen_rtx_SET (VOIDmode
,
10131 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
10135 emit_insn (gen_rtx_SET (VOIDmode
,
10137 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
10138 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
10139 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
10142 /* Output the assembler code for a thunk function. THUNK_DECL is the
10143 declaration for the thunk function itself, FUNCTION is the decl for
10144 the target function. DELTA is an immediate constant offset to be
10145 added to THIS. If VCALL_OFFSET is nonzero, the word at address
10146 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
10149 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
10150 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10153 rtx this_rtx
, insn
, funexp
;
10154 unsigned int int_arg_first
;
10156 reload_completed
= 1;
10157 epilogue_completed
= 1;
10159 emit_note (NOTE_INSN_PROLOGUE_END
);
10163 sparc_leaf_function_p
= 1;
10165 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10167 else if (flag_delayed_branch
)
10169 /* We will emit a regular sibcall below, so we need to instruct
10170 output_sibcall that we are in a leaf function. */
10171 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
10173 /* This will cause final.c to invoke leaf_renumber_regs so we
10174 must behave as if we were in a not-yet-leafified function. */
10175 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
10179 /* We will emit the sibcall manually below, so we will need to
10180 manually spill non-leaf registers. */
10181 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
10183 /* We really are in a leaf function. */
10184 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10187 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
10188 returns a structure, the structure return pointer is there instead. */
10190 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
10191 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
10193 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
10195 /* Add DELTA. When possible use a plain add, otherwise load it into
10196 a register first. */
10199 rtx delta_rtx
= GEN_INT (delta
);
10201 if (! SPARC_SIMM13_P (delta
))
10203 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10204 emit_move_insn (scratch
, delta_rtx
);
10205 delta_rtx
= scratch
;
10208 /* THIS_RTX += DELTA. */
10209 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
10212 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
10215 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10216 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10218 gcc_assert (vcall_offset
< 0);
10220 /* SCRATCH = *THIS_RTX. */
10221 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
10223 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10224 may not have any available scratch register at this point. */
10225 if (SPARC_SIMM13_P (vcall_offset
))
10227 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10228 else if (! fixed_regs
[5]
10229 /* The below sequence is made up of at least 2 insns,
10230 while the default method may need only one. */
10231 && vcall_offset
< -8192)
10233 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
10234 emit_move_insn (scratch2
, vcall_offset_rtx
);
10235 vcall_offset_rtx
= scratch2
;
10239 rtx increment
= GEN_INT (-4096);
10241 /* VCALL_OFFSET is a negative number whose typical range can be
10242 estimated as -32768..0 in 32-bit mode. In almost all cases
10243 it is therefore cheaper to emit multiple add insns than
10244 spilling and loading the constant into a register (at least
10246 while (! SPARC_SIMM13_P (vcall_offset
))
10248 emit_insn (gen_add2_insn (scratch
, increment
));
10249 vcall_offset
+= 4096;
10251 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
10254 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10255 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
10256 gen_rtx_PLUS (Pmode
,
10258 vcall_offset_rtx
)));
10260 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10261 emit_insn (gen_add2_insn (this_rtx
, scratch
));
10264 /* Generate a tail call to the target function. */
10265 if (! TREE_USED (function
))
10267 assemble_external (function
);
10268 TREE_USED (function
) = 1;
10270 funexp
= XEXP (DECL_RTL (function
), 0);
10272 if (flag_delayed_branch
)
10274 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10275 insn
= emit_call_insn (gen_sibcall (funexp
));
10276 SIBLING_CALL_P (insn
) = 1;
10280 /* The hoops we have to jump through in order to generate a sibcall
10281 without using delay slots... */
10282 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
10286 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
10288 load_got_register (); /* clobbers %o7 */
10289 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
10290 seq
= get_insns ();
10292 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
10294 else if (TARGET_ARCH32
)
10296 emit_insn (gen_rtx_SET (VOIDmode
,
10298 gen_rtx_HIGH (SImode
, funexp
)));
10299 emit_insn (gen_rtx_SET (VOIDmode
,
10301 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
10303 else /* TARGET_ARCH64 */
10305 switch (sparc_cmodel
)
10309 /* The destination can serve as a temporary. */
10310 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
10315 /* The destination cannot serve as a temporary. */
10316 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
10318 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
10319 seq
= get_insns ();
10321 emit_and_preserve (seq
, spill_reg
, 0);
10325 gcc_unreachable ();
10329 emit_jump_insn (gen_indirect_jump (scratch
));
10334 /* Run just enough of rest_of_compilation to get the insns emitted.
10335 There's not really enough bulk here to make other passes such as
10336 instruction scheduling worth while. Note that use_thunk calls
10337 assemble_start_function and assemble_end_function. */
10338 insn
= get_insns ();
10339 insn_locators_alloc ();
10340 shorten_branches (insn
);
10341 final_start_function (insn
, file
, 1);
10342 final (insn
, file
, 1);
10343 final_end_function ();
10345 reload_completed
= 0;
10346 epilogue_completed
= 0;
10349 /* Return true if sparc_output_mi_thunk would be able to output the
10350 assembler code for the thunk function specified by the arguments
10351 it is passed, and false otherwise. */
10353 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
10354 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
10355 HOST_WIDE_INT vcall_offset
,
10356 const_tree function ATTRIBUTE_UNUSED
)
10358 /* Bound the loop used in the default method above. */
10359 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
10362 /* How to allocate a 'struct machine_function'. */
10364 static struct machine_function
*
10365 sparc_init_machine_status (void)
10367 return ggc_alloc_cleared_machine_function ();
10370 /* Locate some local-dynamic symbol still in use by this function
10371 so that we can print its name in local-dynamic base patterns. */
10373 static const char *
10374 get_some_local_dynamic_name (void)
10378 if (cfun
->machine
->some_ld_name
)
10379 return cfun
->machine
->some_ld_name
;
10381 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10383 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
10384 return cfun
->machine
->some_ld_name
;
10386 gcc_unreachable ();
10390 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10395 && GET_CODE (x
) == SYMBOL_REF
10396 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10398 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
10405 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10406 We need to emit DTP-relative relocations. */
10409 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
10414 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
10417 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
10420 gcc_unreachable ();
10422 output_addr_const (file
, x
);
10426 /* Do whatever processing is required at the end of a file. */
10429 sparc_file_end (void)
10431 /* If we need to emit the special GOT helper function, do so now. */
10432 if (got_helper_rtx
)
10434 const char *name
= XSTR (got_helper_rtx
, 0);
10435 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
10436 #ifdef DWARF2_UNWIND_INFO
10440 if (USE_HIDDEN_LINKONCE
)
10442 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
10443 get_identifier (name
),
10444 build_function_type_list (void_type_node
,
10446 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
10447 NULL_TREE
, void_type_node
);
10448 TREE_STATIC (decl
) = 1;
10449 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
10450 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
10451 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
10452 resolve_unique_section (decl
, 0, flag_function_sections
);
10453 allocate_struct_function (decl
, true);
10454 cfun
->is_thunk
= 1;
10455 current_function_decl
= decl
;
10456 init_varasm_status ();
10457 assemble_start_function (decl
, name
);
10461 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10462 switch_to_section (text_section
);
10464 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10465 ASM_OUTPUT_LABEL (asm_out_file
, name
);
10468 #ifdef DWARF2_UNWIND_INFO
10469 do_cfi
= dwarf2out_do_cfi_asm ();
10471 fprintf (asm_out_file
, "\t.cfi_startproc\n");
10473 if (flag_delayed_branch
)
10474 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10475 reg_name
, reg_name
);
10477 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10478 reg_name
, reg_name
);
10479 #ifdef DWARF2_UNWIND_INFO
10481 fprintf (asm_out_file
, "\t.cfi_endproc\n");
10485 if (NEED_INDICATE_EXEC_STACK
)
10486 file_end_indicate_exec_stack ();
10488 #ifdef TARGET_SOLARIS
10489 solaris_file_end ();
10493 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10494 /* Implement TARGET_MANGLE_TYPE. */
10496 static const char *
10497 sparc_mangle_type (const_tree type
)
10500 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
10501 && TARGET_LONG_DOUBLE_128
)
10504 /* For all other types, use normal C++ mangling. */
10509 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10510 compare and swap on the word containing the byte or half-word. */
10513 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
10515 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10516 rtx addr
= gen_reg_rtx (Pmode
);
10517 rtx off
= gen_reg_rtx (SImode
);
10518 rtx oldv
= gen_reg_rtx (SImode
);
10519 rtx newv
= gen_reg_rtx (SImode
);
10520 rtx oldvalue
= gen_reg_rtx (SImode
);
10521 rtx newvalue
= gen_reg_rtx (SImode
);
10522 rtx res
= gen_reg_rtx (SImode
);
10523 rtx resv
= gen_reg_rtx (SImode
);
10524 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
10526 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
10527 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10529 if (Pmode
!= SImode
)
10530 addr1
= gen_lowpart (SImode
, addr1
);
10531 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10532 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10534 memsi
= gen_rtx_MEM (SImode
, addr
);
10535 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10536 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10538 val
= force_reg (SImode
, memsi
);
10540 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10541 gen_rtx_XOR (SImode
, off
,
10542 GEN_INT (GET_MODE (mem
) == QImode
10545 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10546 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10548 if (GET_MODE (mem
) == QImode
)
10549 mask
= force_reg (SImode
, GEN_INT (0xff));
10551 mask
= force_reg (SImode
, GEN_INT (0xffff));
10553 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10554 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10556 emit_insn (gen_rtx_SET (VOIDmode
, val
,
10557 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10560 oldval
= gen_lowpart (SImode
, oldval
);
10561 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10562 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10564 newval
= gen_lowpart_common (SImode
, newval
);
10565 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10566 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10568 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10569 gen_rtx_AND (SImode
, oldv
, mask
)));
10571 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10572 gen_rtx_AND (SImode
, newv
, mask
)));
10574 end_label
= gen_label_rtx ();
10575 loop_label
= gen_label_rtx ();
10576 emit_label (loop_label
);
10578 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
10579 gen_rtx_IOR (SImode
, oldv
, val
)));
10581 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
10582 gen_rtx_IOR (SImode
, newv
, val
)));
10584 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
10586 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
10588 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
10589 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10592 cc
= gen_compare_reg_1 (NE
, resv
, val
);
10593 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
10595 /* Use cbranchcc4 to separate the compare and branch! */
10596 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
10597 cc
, const0_rtx
, loop_label
));
10599 emit_label (end_label
);
10601 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10602 gen_rtx_AND (SImode
, res
, mask
)));
10604 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10605 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10607 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10610 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10613 sparc_frame_pointer_required (void)
10615 /* If the stack pointer is dynamically modified in the function, it cannot
10616 serve as the frame pointer. */
10617 if (cfun
->calls_alloca
)
10620 /* If the function receives nonlocal gotos, it needs to save the frame
10621 pointer in the nonlocal_goto_save_area object. */
10622 if (cfun
->has_nonlocal_label
)
10625 /* In flat mode, that's it. */
10629 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10630 return !(current_function_is_leaf
&& only_leaf_regs_used ());
10633 /* The way this is structured, we can't eliminate SFP in favor of SP
10634 if the frame pointer is required: we want to use the SFP->HFP elimination
10635 in that case. But the test in update_eliminables doesn't know we are
10636 assuming below that we only do the former elimination. */
10639 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10641 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
10644 /* Return the hard frame pointer directly to bypass the stack bias. */
10647 sparc_builtin_setjmp_frame_value (void)
10649 return hard_frame_pointer_rtx
;
10652 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10653 they won't be allocated. */
10656 sparc_conditional_register_usage (void)
10658 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
10660 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10661 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10663 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10664 /* then honor it. */
10665 if (TARGET_ARCH32
&& fixed_regs
[5])
10667 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
10672 for (regno
= SPARC_FIRST_V9_FP_REG
;
10673 regno
<= SPARC_LAST_V9_FP_REG
;
10675 fixed_regs
[regno
] = 1;
10676 /* %fcc0 is used by v8 and v9. */
10677 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
10678 regno
<= SPARC_LAST_V9_FCC_REG
;
10680 fixed_regs
[regno
] = 1;
10685 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
10686 fixed_regs
[regno
] = 1;
10688 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10689 /* then honor it. Likewise with g3 and g4. */
10690 if (fixed_regs
[2] == 2)
10691 fixed_regs
[2] = ! TARGET_APP_REGS
;
10692 if (fixed_regs
[3] == 2)
10693 fixed_regs
[3] = ! TARGET_APP_REGS
;
10694 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
10695 fixed_regs
[4] = ! TARGET_APP_REGS
;
10696 else if (TARGET_CM_EMBMEDANY
)
10698 else if (fixed_regs
[4] == 2)
10703 /* Disable leaf functions. */
10704 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
10705 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
10706 leaf_reg_remap
[regno
] = regno
;
10709 global_regs
[SPARC_GSR_REG
] = 1;
10712 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10714 - We can't load constants into FP registers.
10715 - We can't load FP constants into integer registers when soft-float,
10716 because there is no soft-float pattern with a r/F constraint.
10717 - We can't load FP constants into integer registers for TFmode unless
10718 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10719 - Try and reload integer constants (symbolic or otherwise) back into
10720 registers directly, rather than having them dumped to memory. */
10723 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
10725 if (CONSTANT_P (x
))
10727 if (FP_REG_CLASS_P (rclass
)
10728 || rclass
== GENERAL_OR_FP_REGS
10729 || rclass
== GENERAL_OR_EXTRA_FP_REGS
10730 || (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
&& ! TARGET_FPU
)
10731 || (GET_MODE (x
) == TFmode
&& ! const_zero_operand (x
, TFmode
)))
10734 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
10735 return GENERAL_REGS
;
10741 #include "gt-sparc.h"