1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
52 /* 1 if the caller has placed an "unimp" insn immediately after the call.
53 This is used in v8 code when calling a function that returns a structure.
54 v9 doesn't have this. Be careful to have this test be the same as that
57 #define SKIP_CALLERS_UNIMP_P \
58 (!TARGET_ARCH64 && current_function_returns_struct \
59 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
63 /* Global variables for machine-dependent things. */
65 /* Size of frame. Need to know this to emit return insns from leaf procedures.
66 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
67 reload pass. This is important as the value is later used in insn
68 scheduling (to see what can go in a delay slot).
69 APPARENT_FSIZE is the size of the stack less the register save area and less
70 the outgoing argument area. It is used when saving call preserved regs. */
71 static int apparent_fsize
;
72 static int actual_fsize
;
74 /* Number of live general or floating point registers needed to be
75 saved (as 4-byte quantities). */
76 static int num_gfregs
;
78 /* Save the operands last given to a compare for use when we
79 generate a scc or bcc insn. */
80 rtx sparc_compare_op0
, sparc_compare_op1
;
82 /* Coordinate with the md file wrt special insns created by
83 sparc_nonflat_function_epilogue. */
84 bool sparc_emitting_epilogue
;
86 /* Vector to say how input registers are mapped to output registers.
87 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
88 eliminate it. You must use -fomit-frame-pointer to get that. */
89 char leaf_reg_remap
[] =
90 { 0, 1, 2, 3, 4, 5, 6, 7,
91 -1, -1, -1, -1, -1, -1, 14, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1,
93 8, 9, 10, 11, 12, 13, -1, 15,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 40, 41, 42, 43, 44, 45, 46, 47,
97 48, 49, 50, 51, 52, 53, 54, 55,
98 56, 57, 58, 59, 60, 61, 62, 63,
99 64, 65, 66, 67, 68, 69, 70, 71,
100 72, 73, 74, 75, 76, 77, 78, 79,
101 80, 81, 82, 83, 84, 85, 86, 87,
102 88, 89, 90, 91, 92, 93, 94, 95,
103 96, 97, 98, 99, 100};
105 /* Vector, indexed by hard register number, which contains 1
106 for a register that is allowable in a candidate for leaf
107 function treatment. */
108 char sparc_leaf_regs
[] =
109 { 1, 1, 1, 1, 1, 1, 1, 1,
110 0, 0, 0, 0, 0, 0, 1, 0,
111 0, 0, 0, 0, 0, 0, 0, 0,
112 1, 1, 1, 1, 1, 1, 0, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
120 1, 1, 1, 1, 1, 1, 1, 1,
123 /* Name of where we pretend to think the frame pointer points.
124 Normally, this is "%fp", but if we are in a leaf procedure,
125 this is "%sp+something". We record "something" separately as it may be
126 too big for reg+constant addressing. */
128 static const char *frame_base_name
;
129 static int frame_base_offset
;
131 static void sparc_init_modes
PARAMS ((void));
132 static int save_regs
PARAMS ((FILE *, int, int, const char *,
134 static int restore_regs
PARAMS ((FILE *, int, int, const char *, int, int));
135 static void build_big_number
PARAMS ((FILE *, int, const char *));
136 static int function_arg_slotno
PARAMS ((const CUMULATIVE_ARGS
*,
137 enum machine_mode
, tree
, int, int,
140 static int supersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
141 static int hypersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
143 static void sparc_output_addr_vec
PARAMS ((rtx
));
144 static void sparc_output_addr_diff_vec
PARAMS ((rtx
));
145 static void sparc_output_deferred_case_vectors
PARAMS ((void));
146 static int check_return_regs
PARAMS ((rtx
));
147 static int epilogue_renumber
PARAMS ((rtx
*, int));
148 static bool sparc_assemble_integer
PARAMS ((rtx
, unsigned int, int));
149 static int set_extends
PARAMS ((rtx
));
150 static void output_restore_regs
PARAMS ((FILE *, int));
151 static void sparc_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
152 static void sparc_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
153 static void sparc_flat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
154 static void sparc_flat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
155 static void sparc_nonflat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
,
157 static void sparc_nonflat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
,
159 #ifdef OBJECT_FORMAT_ELF
160 static void sparc_elf_asm_named_section
PARAMS ((const char *, unsigned int));
162 static void sparc_aout_select_section
PARAMS ((tree
, int,
163 unsigned HOST_WIDE_INT
))
165 static void sparc_aout_select_rtx_section
PARAMS ((enum machine_mode
, rtx
,
166 unsigned HOST_WIDE_INT
))
169 static int sparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
170 static int sparc_issue_rate
PARAMS ((void));
171 static void sparc_sched_init
PARAMS ((FILE *, int, int));
172 static int sparc_use_dfa_pipeline_interface
PARAMS ((void));
173 static int sparc_use_sched_lookahead
PARAMS ((void));
175 static void emit_soft_tfmode_libcall
PARAMS ((const char *, int, rtx
*));
176 static void emit_soft_tfmode_binop
PARAMS ((enum rtx_code
, rtx
*));
177 static void emit_soft_tfmode_unop
PARAMS ((enum rtx_code
, rtx
*));
178 static void emit_soft_tfmode_cvt
PARAMS ((enum rtx_code
, rtx
*));
179 static void emit_hard_tfmode_operation
PARAMS ((enum rtx_code
, rtx
*));
181 static bool sparc_function_ok_for_sibcall
PARAMS ((tree
, tree
));
182 static void sparc_output_mi_thunk
PARAMS ((FILE *, tree
, HOST_WIDE_INT
,
183 HOST_WIDE_INT
, tree
));
184 static bool sparc_rtx_costs
PARAMS ((rtx
, int, int, int *));
186 /* Option handling. */
188 /* Code model option as passed by user. */
189 const char *sparc_cmodel_string
;
191 enum cmodel sparc_cmodel
;
193 char sparc_hard_reg_printed
[8];
195 struct sparc_cpu_select sparc_select
[] =
197 /* switch name, tune arch */
198 { (char *)0, "default", 1, 1 },
199 { (char *)0, "-mcpu=", 1, 1 },
200 { (char *)0, "-mtune=", 1, 0 },
204 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
205 enum processor_type sparc_cpu
;
207 /* Initialize the GCC target structure. */
209 /* The sparc default is to use .half rather than .short for aligned
210 HI objects. Use .word instead of .long on non-ELF systems. */
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
213 #ifndef OBJECT_FORMAT_ELF
214 #undef TARGET_ASM_ALIGNED_SI_OP
215 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
218 #undef TARGET_ASM_UNALIGNED_HI_OP
219 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
220 #undef TARGET_ASM_UNALIGNED_SI_OP
221 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
222 #undef TARGET_ASM_UNALIGNED_DI_OP
223 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
225 /* The target hook has to handle DI-mode values. */
226 #undef TARGET_ASM_INTEGER
227 #define TARGET_ASM_INTEGER sparc_assemble_integer
229 #undef TARGET_ASM_FUNCTION_PROLOGUE
230 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
231 #undef TARGET_ASM_FUNCTION_EPILOGUE
232 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
234 #undef TARGET_SCHED_ADJUST_COST
235 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
236 #undef TARGET_SCHED_ISSUE_RATE
237 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
238 #undef TARGET_SCHED_INIT
239 #define TARGET_SCHED_INIT sparc_sched_init
240 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
241 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
242 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
243 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
245 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
246 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
248 #undef TARGET_ASM_OUTPUT_MI_THUNK
249 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
250 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
251 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
253 #undef TARGET_RTX_COSTS
254 #define TARGET_RTX_COSTS sparc_rtx_costs
255 #undef TARGET_ADDRESS_COST
256 #define TARGET_ADDRESS_COST hook_int_rtx_0
258 struct gcc_target targetm
= TARGET_INITIALIZER
;
260 /* Validate and override various options, and do some machine dependent
264 sparc_override_options ()
266 static struct code_model
{
267 const char *const name
;
269 } const cmodels
[] = {
271 { "medlow", CM_MEDLOW
},
272 { "medmid", CM_MEDMID
},
273 { "medany", CM_MEDANY
},
274 { "embmedany", CM_EMBMEDANY
},
277 const struct code_model
*cmodel
;
278 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
279 static struct cpu_default
{
281 const char *const name
;
282 } const cpu_default
[] = {
283 /* There must be one entry here for each TARGET_CPU value. */
284 { TARGET_CPU_sparc
, "cypress" },
285 { TARGET_CPU_sparclet
, "tsc701" },
286 { TARGET_CPU_sparclite
, "f930" },
287 { TARGET_CPU_v8
, "v8" },
288 { TARGET_CPU_hypersparc
, "hypersparc" },
289 { TARGET_CPU_sparclite86x
, "sparclite86x" },
290 { TARGET_CPU_supersparc
, "supersparc" },
291 { TARGET_CPU_v9
, "v9" },
292 { TARGET_CPU_ultrasparc
, "ultrasparc" },
293 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
296 const struct cpu_default
*def
;
297 /* Table of values for -m{cpu,tune}=. */
298 static struct cpu_table
{
299 const char *const name
;
300 const enum processor_type processor
;
303 } const cpu_table
[] = {
304 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
305 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
306 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
307 /* TI TMS390Z55 supersparc */
308 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
309 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
310 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
311 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
312 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
313 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
314 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
315 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
317 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
319 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
320 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
321 /* TI ultrasparc I, II, IIi */
322 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
323 /* Although insns using %y are deprecated, it is a clear win on current
325 |MASK_DEPRECATED_V8_INSNS
},
326 /* TI ultrasparc III */
327 /* ??? Check if %y issue still holds true in ultra3. */
328 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
331 const struct cpu_table
*cpu
;
332 const struct sparc_cpu_select
*sel
;
335 #ifndef SPARC_BI_ARCH
336 /* Check for unsupported architecture size. */
337 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
338 error ("%s is not supported by this configuration",
339 DEFAULT_ARCH32_P
? "-m64" : "-m32");
342 /* We force all 64bit archs to use 128 bit long double */
343 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
345 error ("-mlong-double-64 not allowed with -m64");
346 target_flags
|= MASK_LONG_DOUBLE_128
;
349 /* Code model selection. */
350 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
354 sparc_cmodel
= CM_32
;
357 if (sparc_cmodel_string
!= NULL
)
361 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
362 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
364 if (cmodel
->name
== NULL
)
365 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
367 sparc_cmodel
= cmodel
->value
;
370 error ("-mcmodel= is not supported on 32 bit systems");
373 fpu
= TARGET_FPU
; /* save current -mfpu status */
375 /* Set the default CPU. */
376 for (def
= &cpu_default
[0]; def
->name
; ++def
)
377 if (def
->cpu
== TARGET_CPU_DEFAULT
)
381 sparc_select
[0].string
= def
->name
;
383 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
387 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
388 if (! strcmp (sel
->string
, cpu
->name
))
391 sparc_cpu
= cpu
->processor
;
395 target_flags
&= ~cpu
->disable
;
396 target_flags
|= cpu
->enable
;
402 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
406 /* If -mfpu or -mno-fpu was explicitly used, don't override with
407 the processor default. Clear MASK_FPU_SET to avoid confusing
408 the reverse mapping from switch values to names. */
411 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
412 target_flags
&= ~MASK_FPU_SET
;
415 /* Don't allow -mvis if FPU is disabled. */
417 target_flags
&= ~MASK_VIS
;
419 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
421 -m64 also implies v9. */
422 if (TARGET_VIS
|| TARGET_ARCH64
)
424 target_flags
|= MASK_V9
;
425 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
428 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
429 if (TARGET_V9
&& TARGET_ARCH32
)
430 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
432 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
433 if (! TARGET_V9
|| TARGET_ARCH64
)
434 target_flags
&= ~MASK_V8PLUS
;
436 /* Don't use stack biasing in 32 bit mode. */
438 target_flags
&= ~MASK_STACK_BIAS
;
440 /* Supply a default value for align_functions. */
441 if (align_functions
== 0
442 && (sparc_cpu
== PROCESSOR_ULTRASPARC
443 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
444 align_functions
= 32;
446 /* Validate PCC_STRUCT_RETURN. */
447 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
448 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
450 /* Only use .uaxword when compiling for a 64-bit target. */
452 targetm
.asm_out
.unaligned_op
.di
= NULL
;
454 /* Do various machine dependent initializations. */
458 /* Miscellaneous utilities. */
460 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
461 or branch on register contents instructions. */
467 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
468 || code
== LE
|| code
== GT
);
472 /* Operand constraints. */
474 /* Return nonzero only if OP is a register of mode MODE,
478 reg_or_0_operand (op
, mode
)
480 enum machine_mode mode
;
482 if (register_operand (op
, mode
))
484 if (op
== const0_rtx
)
486 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
487 && CONST_DOUBLE_HIGH (op
) == 0
488 && CONST_DOUBLE_LOW (op
) == 0)
490 if (fp_zero_operand (op
, mode
))
495 /* Return nonzero only if OP is const1_rtx. */
498 const1_operand (op
, mode
)
500 enum machine_mode mode ATTRIBUTE_UNUSED
;
502 return op
== const1_rtx
;
505 /* Nonzero if OP is a floating point value with value 0.0. */
508 fp_zero_operand (op
, mode
)
510 enum machine_mode mode
;
512 if (GET_MODE_CLASS (GET_MODE (op
)) != MODE_FLOAT
)
514 return op
== CONST0_RTX (mode
);
517 /* Nonzero if OP is a register operand in floating point register. */
520 fp_register_operand (op
, mode
)
522 enum machine_mode mode
;
524 if (! register_operand (op
, mode
))
526 if (GET_CODE (op
) == SUBREG
)
527 op
= SUBREG_REG (op
);
528 return GET_CODE (op
) == REG
&& SPARC_FP_REG_P (REGNO (op
));
531 /* Nonzero if OP is a floating point constant which can
532 be loaded into an integer register using a single
533 sethi instruction. */
539 if (GET_CODE (op
) == CONST_DOUBLE
)
544 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
545 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
546 ! REAL_VALUE_MINUS_ZERO (r
))
548 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
549 if (SPARC_SETHI_P (i
))
556 /* Nonzero if OP is a floating point constant which can
557 be loaded into an integer register using a single
564 if (GET_CODE (op
) == CONST_DOUBLE
)
569 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
570 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
571 ! REAL_VALUE_MINUS_ZERO (r
))
573 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
574 if (SPARC_SIMM13_P (i
))
581 /* Nonzero if OP is a floating point constant which can
582 be loaded into an integer register using a high/losum
583 instruction sequence. */
589 /* The constraints calling this should only be in
590 SFmode move insns, so any constant which cannot
591 be moved using a single insn will do. */
592 if (GET_CODE (op
) == CONST_DOUBLE
)
597 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
598 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
599 ! REAL_VALUE_MINUS_ZERO (r
))
601 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
602 if (! SPARC_SETHI_P (i
)
603 && ! SPARC_SIMM13_P (i
))
610 /* Nonzero if OP is an integer register. */
613 intreg_operand (op
, mode
)
615 enum machine_mode mode ATTRIBUTE_UNUSED
;
617 return (register_operand (op
, SImode
)
618 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
621 /* Nonzero if OP is a floating point condition code register. */
624 fcc_reg_operand (op
, mode
)
626 enum machine_mode mode
;
628 /* This can happen when recog is called from combine. Op may be a MEM.
629 Fail instead of calling abort in this case. */
630 if (GET_CODE (op
) != REG
)
633 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
636 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
639 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
640 if (reg_renumber
== 0)
641 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
642 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
644 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
648 /* Nonzero if OP is a floating point condition code fcc0 register. */
651 fcc0_reg_operand (op
, mode
)
653 enum machine_mode mode
;
655 /* This can happen when recog is called from combine. Op may be a MEM.
656 Fail instead of calling abort in this case. */
657 if (GET_CODE (op
) != REG
)
660 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
663 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
666 return REGNO (op
) == SPARC_FCC_REG
;
669 /* Nonzero if OP is an integer or floating point condition code register. */
672 icc_or_fcc_reg_operand (op
, mode
)
674 enum machine_mode mode
;
676 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
678 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
681 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
686 return fcc_reg_operand (op
, mode
);
689 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
691 restore_operand (op
, mode
)
693 enum machine_mode mode
;
695 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
696 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
699 /* Call insn on SPARC can take a PC-relative constant address, or any regular
703 call_operand (op
, mode
)
705 enum machine_mode mode
;
707 if (GET_CODE (op
) != MEM
)
710 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
714 call_operand_address (op
, mode
)
716 enum machine_mode mode
;
718 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
721 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
722 reference and a constant. */
725 symbolic_operand (op
, mode
)
727 enum machine_mode mode
;
729 enum machine_mode omode
= GET_MODE (op
);
731 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
734 switch (GET_CODE (op
))
742 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
743 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
744 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
751 /* Return truth value of statement that OP is a symbolic memory
752 operand of mode MODE. */
755 symbolic_memory_operand (op
, mode
)
757 enum machine_mode mode ATTRIBUTE_UNUSED
;
759 if (GET_CODE (op
) == SUBREG
)
760 op
= SUBREG_REG (op
);
761 if (GET_CODE (op
) != MEM
)
764 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
765 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
768 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
771 label_ref_operand (op
, mode
)
773 enum machine_mode mode
;
775 if (GET_CODE (op
) != LABEL_REF
)
777 if (GET_MODE (op
) != mode
)
782 /* Return 1 if the operand is an argument used in generating pic references
783 in either the medium/low or medium/anywhere code models of sparc64. */
786 sp64_medium_pic_operand (op
, mode
)
788 enum machine_mode mode ATTRIBUTE_UNUSED
;
790 /* Check for (const (minus (symbol_ref:GOT)
791 (const (minus (label) (pc))))). */
792 if (GET_CODE (op
) != CONST
)
795 if (GET_CODE (op
) != MINUS
)
797 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
799 /* ??? Ensure symbol is GOT. */
800 if (GET_CODE (XEXP (op
, 1)) != CONST
)
802 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
807 /* Return 1 if the operand is a data segment reference. This includes
808 the readonly data segment, or in other words anything but the text segment.
809 This is needed in the medium/anywhere code model on v9. These values
810 are accessed with EMBMEDANY_BASE_REG. */
813 data_segment_operand (op
, mode
)
815 enum machine_mode mode ATTRIBUTE_UNUSED
;
817 switch (GET_CODE (op
))
820 return ! SYMBOL_REF_FUNCTION_P (op
);
822 /* Assume canonical format of symbol + constant.
825 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
831 /* Return 1 if the operand is a text segment reference.
832 This is needed in the medium/anywhere code model on v9. */
835 text_segment_operand (op
, mode
)
837 enum machine_mode mode ATTRIBUTE_UNUSED
;
839 switch (GET_CODE (op
))
844 return SYMBOL_REF_FUNCTION_P (op
);
846 /* Assume canonical format of symbol + constant.
849 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
855 /* Return 1 if the operand is either a register or a memory operand that is
859 reg_or_nonsymb_mem_operand (op
, mode
)
861 enum machine_mode mode
;
863 if (register_operand (op
, mode
))
866 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
873 splittable_symbolic_memory_operand (op
, mode
)
875 enum machine_mode mode ATTRIBUTE_UNUSED
;
877 if (GET_CODE (op
) != MEM
)
879 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
885 splittable_immediate_memory_operand (op
, mode
)
887 enum machine_mode mode ATTRIBUTE_UNUSED
;
889 if (GET_CODE (op
) != MEM
)
891 if (! immediate_operand (XEXP (op
, 0), Pmode
))
896 /* Return truth value of whether OP is EQ or NE. */
901 enum machine_mode mode ATTRIBUTE_UNUSED
;
903 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
906 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
907 or LTU for non-floating-point. We handle those specially. */
910 normal_comp_operator (op
, mode
)
912 enum machine_mode mode ATTRIBUTE_UNUSED
;
914 enum rtx_code code
= GET_CODE (op
);
916 if (GET_RTX_CLASS (code
) != '<')
919 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
920 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
923 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
926 /* Return 1 if this is a comparison operator. This allows the use of
927 MATCH_OPERATOR to recognize all the branch insns. */
930 noov_compare_op (op
, mode
)
932 enum machine_mode mode ATTRIBUTE_UNUSED
;
934 enum rtx_code code
= GET_CODE (op
);
936 if (GET_RTX_CLASS (code
) != '<')
939 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
940 || GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
941 /* These are the only branches which work with CC_NOOVmode. */
942 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
946 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
947 MATCH_OPERATOR to recognize all the branch insns. */
950 noov_compare64_op (op
, mode
)
952 enum machine_mode mode ATTRIBUTE_UNUSED
;
954 enum rtx_code code
= GET_CODE (op
);
959 if (GET_RTX_CLASS (code
) != '<')
962 if (GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
963 /* These are the only branches which work with CCX_NOOVmode. */
964 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
965 return (GET_MODE (XEXP (op
, 0)) == CCXmode
);
968 /* Nonzero if OP is a comparison operator suitable for use in v9
969 conditional move or branch on register contents instructions. */
972 v9_regcmp_op (op
, mode
)
974 enum machine_mode mode ATTRIBUTE_UNUSED
;
976 enum rtx_code code
= GET_CODE (op
);
978 if (GET_RTX_CLASS (code
) != '<')
981 return v9_regcmp_p (code
);
984 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
989 enum machine_mode mode ATTRIBUTE_UNUSED
;
991 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
994 /* Return nonzero if OP is an operator of mode MODE which can set
995 the condition codes explicitly. We do not include PLUS and MINUS
996 because these require CC_NOOVmode, which we handle explicitly. */
999 cc_arithop (op
, mode
)
1001 enum machine_mode mode ATTRIBUTE_UNUSED
;
1003 if (GET_CODE (op
) == AND
1004 || GET_CODE (op
) == IOR
1005 || GET_CODE (op
) == XOR
)
1011 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1012 complement its second operand and set the condition codes explicitly. */
1015 cc_arithopn (op
, mode
)
1017 enum machine_mode mode ATTRIBUTE_UNUSED
;
1019 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1020 and (xor ... (not ...)) to (not (xor ...)). */
1021 return (GET_CODE (op
) == AND
1022 || GET_CODE (op
) == IOR
);
1025 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1026 signed 13 bit immediate field. This is an acceptable SImode operand for
1027 most 3 address instructions. */
1030 arith_operand (op
, mode
)
1032 enum machine_mode mode
;
1034 if (register_operand (op
, mode
))
1036 if (GET_CODE (op
) != CONST_INT
)
1038 return SMALL_INT32 (op
);
1041 /* Return true if OP is a constant 4096 */
1044 arith_4096_operand (op
, mode
)
1046 enum machine_mode mode ATTRIBUTE_UNUSED
;
1048 if (GET_CODE (op
) != CONST_INT
)
1051 return INTVAL (op
) == 4096;
1054 /* Return true if OP is suitable as second operand for add/sub */
1057 arith_add_operand (op
, mode
)
1059 enum machine_mode mode
;
1061 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
1064 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1065 immediate field of OR and XOR instructions. Used for 64-bit
1066 constant formation patterns. */
1068 const64_operand (op
, mode
)
1070 enum machine_mode mode ATTRIBUTE_UNUSED
;
1072 return ((GET_CODE (op
) == CONST_INT
1073 && SPARC_SIMM13_P (INTVAL (op
)))
1074 #if HOST_BITS_PER_WIDE_INT != 64
1075 || (GET_CODE (op
) == CONST_DOUBLE
1076 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1077 && (CONST_DOUBLE_HIGH (op
) ==
1078 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
1079 (HOST_WIDE_INT
)-1 : 0)))
1084 /* The same, but only for sethi instructions. */
1086 const64_high_operand (op
, mode
)
1088 enum machine_mode mode
;
1090 return ((GET_CODE (op
) == CONST_INT
1091 && (INTVAL (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1092 && SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1094 || (GET_CODE (op
) == CONST_DOUBLE
1095 && CONST_DOUBLE_HIGH (op
) == 0
1096 && (CONST_DOUBLE_LOW (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1097 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
1100 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1101 signed 11 bit immediate field. This is an acceptable SImode operand for
1102 the movcc instructions. */
1105 arith11_operand (op
, mode
)
1107 enum machine_mode mode
;
1109 return (register_operand (op
, mode
)
1110 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
1113 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1114 signed 10 bit immediate field. This is an acceptable SImode operand for
1115 the movrcc instructions. */
1118 arith10_operand (op
, mode
)
1120 enum machine_mode mode
;
1122 return (register_operand (op
, mode
)
1123 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
1126 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1127 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1129 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1130 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1131 for most 3 address instructions. */
1134 arith_double_operand (op
, mode
)
1136 enum machine_mode mode
;
1138 return (register_operand (op
, mode
)
1139 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1141 && GET_CODE (op
) == CONST_DOUBLE
1142 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1143 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
1145 && GET_CODE (op
) == CONST_DOUBLE
1146 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1147 && ((CONST_DOUBLE_HIGH (op
) == -1
1148 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
1149 || (CONST_DOUBLE_HIGH (op
) == 0
1150 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
1153 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1156 arith_double_4096_operand (op
, mode
)
1158 enum machine_mode mode ATTRIBUTE_UNUSED
;
1160 return (TARGET_ARCH64
&&
1161 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
1162 (GET_CODE (op
) == CONST_DOUBLE
&&
1163 CONST_DOUBLE_LOW (op
) == 4096 &&
1164 CONST_DOUBLE_HIGH (op
) == 0)));
1167 /* Return true if OP is suitable as second operand for add/sub in DImode */
1170 arith_double_add_operand (op
, mode
)
1172 enum machine_mode mode
;
1174 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
1177 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1178 can fit in an 11 bit immediate field. This is an acceptable DImode
1179 operand for the movcc instructions. */
1180 /* ??? Replace with arith11_operand? */
1183 arith11_double_operand (op
, mode
)
1185 enum machine_mode mode
;
1187 return (register_operand (op
, mode
)
1188 || (GET_CODE (op
) == CONST_DOUBLE
1189 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1190 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
1191 && ((CONST_DOUBLE_HIGH (op
) == -1
1192 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
1193 || (CONST_DOUBLE_HIGH (op
) == 0
1194 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
1195 || (GET_CODE (op
) == CONST_INT
1196 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1197 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
1200 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1201 can fit in an 10 bit immediate field. This is an acceptable DImode
1202 operand for the movrcc instructions. */
1203 /* ??? Replace with arith10_operand? */
1206 arith10_double_operand (op
, mode
)
1208 enum machine_mode mode
;
1210 return (register_operand (op
, mode
)
1211 || (GET_CODE (op
) == CONST_DOUBLE
1212 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1213 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
1214 && ((CONST_DOUBLE_HIGH (op
) == -1
1215 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
1216 || (CONST_DOUBLE_HIGH (op
) == 0
1217 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
1218 || (GET_CODE (op
) == CONST_INT
1219 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1220 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
1223 /* Return truth value of whether OP is an integer which fits the
1224 range constraining immediate operands in most three-address insns,
1225 which have a 13 bit immediate field. */
1228 small_int (op
, mode
)
1230 enum machine_mode mode ATTRIBUTE_UNUSED
;
1232 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1236 small_int_or_double (op
, mode
)
1238 enum machine_mode mode ATTRIBUTE_UNUSED
;
1240 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1241 || (GET_CODE (op
) == CONST_DOUBLE
1242 && CONST_DOUBLE_HIGH (op
) == 0
1243 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1246 /* Recognize operand values for the umul instruction. That instruction sign
1247 extends immediate values just like all other sparc instructions, but
1248 interprets the extended result as an unsigned number. */
1251 uns_small_int (op
, mode
)
1253 enum machine_mode mode ATTRIBUTE_UNUSED
;
1255 #if HOST_BITS_PER_WIDE_INT > 32
1256 /* All allowed constants will fit a CONST_INT. */
1257 return (GET_CODE (op
) == CONST_INT
1258 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1259 || (INTVAL (op
) >= 0xFFFFF000
1260 && INTVAL (op
) <= 0xFFFFFFFF)));
1262 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1263 || (GET_CODE (op
) == CONST_DOUBLE
1264 && CONST_DOUBLE_HIGH (op
) == 0
1265 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1270 uns_arith_operand (op
, mode
)
1272 enum machine_mode mode
;
1274 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1277 /* Return truth value of statement that OP is a call-clobbered register. */
1279 clobbered_register (op
, mode
)
1281 enum machine_mode mode ATTRIBUTE_UNUSED
;
1283 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1286 /* Return 1 if OP is a valid operand for the source of a move insn. */
1289 input_operand (op
, mode
)
1291 enum machine_mode mode
;
1293 /* If both modes are non-void they must be the same. */
1294 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1297 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1298 if (GET_CODE (op
) == CONSTANT_P_RTX
)
1301 /* Allow any one instruction integer constant, and all CONST_INT
1302 variants when we are working in DImode and !arch64. */
1303 if (GET_MODE_CLASS (mode
) == MODE_INT
1304 && ((GET_CODE (op
) == CONST_INT
1305 && (SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1306 || SPARC_SIMM13_P (INTVAL (op
))
1308 && ! TARGET_ARCH64
)))
1310 && GET_CODE (op
) == CONST_DOUBLE
1311 && ((CONST_DOUBLE_HIGH (op
) == 0
1312 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1314 #if HOST_BITS_PER_WIDE_INT == 64
1315 (CONST_DOUBLE_HIGH (op
) == 0
1316 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1318 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1319 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1320 && CONST_DOUBLE_HIGH (op
) == 0)
1321 || (CONST_DOUBLE_HIGH (op
) == -1
1322 && CONST_DOUBLE_LOW (op
) & 0x80000000) != 0))
1327 /* If !arch64 and this is a DImode const, allow it so that
1328 the splits can be generated. */
1331 && GET_CODE (op
) == CONST_DOUBLE
)
1334 if (register_operand (op
, mode
))
1337 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1338 && GET_CODE (op
) == CONST_DOUBLE
)
1341 /* If this is a SUBREG, look inside so that we handle
1342 paradoxical ones. */
1343 if (GET_CODE (op
) == SUBREG
)
1344 op
= SUBREG_REG (op
);
1346 /* Check for valid MEM forms. */
1347 if (GET_CODE (op
) == MEM
)
1349 rtx inside
= XEXP (op
, 0);
1351 if (GET_CODE (inside
) == LO_SUM
)
1353 /* We can't allow these because all of the splits
1354 (eventually as they trickle down into DFmode
1355 splits) require offsettable memory references. */
1357 && GET_MODE (op
) == TFmode
)
1360 return (register_operand (XEXP (inside
, 0), Pmode
)
1361 && CONSTANT_P (XEXP (inside
, 1)));
1363 return memory_address_p (mode
, inside
);
1370 /* We know it can't be done in one insn when we get here,
1371 the movsi expander guarantees this. */
1373 sparc_emit_set_const32 (op0
, op1
)
1377 enum machine_mode mode
= GET_MODE (op0
);
1380 if (GET_CODE (op1
) == CONST_INT
)
1382 HOST_WIDE_INT value
= INTVAL (op1
);
1384 if (SPARC_SETHI_P (value
& GET_MODE_MASK (mode
))
1385 || SPARC_SIMM13_P (value
))
1389 /* Full 2-insn decomposition is needed. */
1390 if (reload_in_progress
|| reload_completed
)
1393 temp
= gen_reg_rtx (mode
);
1395 if (GET_CODE (op1
) == CONST_INT
)
1397 /* Emit them as real moves instead of a HIGH/LO_SUM,
1398 this way CSE can see everything and reuse intermediate
1399 values if it wants. */
1401 && HOST_BITS_PER_WIDE_INT
!= 64
1402 && (INTVAL (op1
) & 0x80000000) != 0)
1403 emit_insn (gen_rtx_SET
1405 immed_double_const (INTVAL (op1
) & ~(HOST_WIDE_INT
)0x3ff,
1408 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1409 GEN_INT (INTVAL (op1
)
1410 & ~(HOST_WIDE_INT
)0x3ff)));
1412 emit_insn (gen_rtx_SET (VOIDmode
,
1414 gen_rtx_IOR (mode
, temp
,
1415 GEN_INT (INTVAL (op1
) & 0x3ff))));
1419 /* A symbol, emit in the traditional way. */
1420 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1421 gen_rtx_HIGH (mode
, op1
)));
1422 emit_insn (gen_rtx_SET (VOIDmode
,
1423 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1429 /* SPARC-v9 code-model support. */
1431 sparc_emit_set_symbolic_const64 (op0
, op1
, temp1
)
1438 if (temp1
&& GET_MODE (temp1
) == TImode
)
1441 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
));
1444 switch (sparc_cmodel
)
1447 /* The range spanned by all instructions in the object is less
1448 than 2^31 bytes (2GB) and the distance from any instruction
1449 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1450 than 2^31 bytes (2GB).
1452 The executable must be in the low 4TB of the virtual address
1455 sethi %hi(symbol), %temp
1456 or %temp, %lo(symbol), %reg */
1457 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1458 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1462 /* The range spanned by all instructions in the object is less
1463 than 2^31 bytes (2GB) and the distance from any instruction
1464 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1465 than 2^31 bytes (2GB).
1467 The executable must be in the low 16TB of the virtual address
1470 sethi %h44(symbol), %temp1
1471 or %temp1, %m44(symbol), %temp2
1472 sllx %temp2, 12, %temp3
1473 or %temp3, %l44(symbol), %reg */
1474 emit_insn (gen_seth44 (op0
, op1
));
1475 emit_insn (gen_setm44 (op0
, op0
, op1
));
1476 emit_insn (gen_rtx_SET (VOIDmode
, temp1
,
1477 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (12))));
1478 emit_insn (gen_setl44 (op0
, temp1
, op1
));
1482 /* The range spanned by all instructions in the object is less
1483 than 2^31 bytes (2GB) and the distance from any instruction
1484 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1485 than 2^31 bytes (2GB).
1487 The executable can be placed anywhere in the virtual address
1490 sethi %hh(symbol), %temp1
1491 sethi %lm(symbol), %temp2
1492 or %temp1, %hm(symbol), %temp3
1493 or %temp2, %lo(symbol), %temp4
1494 sllx %temp3, 32, %temp5
1495 or %temp4, %temp5, %reg */
1497 /* It is possible that one of the registers we got for operands[2]
1498 might coincide with that of operands[0] (which is why we made
1499 it TImode). Pick the other one to use as our scratch. */
1500 if (rtx_equal_p (temp1
, op0
))
1503 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1508 emit_insn (gen_sethh (op0
, op1
));
1509 emit_insn (gen_setlm (temp1
, op1
));
1510 emit_insn (gen_sethm (op0
, op0
, op1
));
1511 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1512 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1513 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1514 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1515 emit_insn (gen_setlo (op0
, op0
, op1
));
1519 /* Old old old backwards compatibility kruft here.
1520 Essentially it is MEDLOW with a fixed 64-bit
1521 virtual base added to all data segment addresses.
1522 Text-segment stuff is computed like MEDANY, we can't
1523 reuse the code above because the relocation knobs
1526 Data segment: sethi %hi(symbol), %temp1
1527 or %temp1, %lo(symbol), %temp2
1528 add %temp2, EMBMEDANY_BASE_REG, %reg
1530 Text segment: sethi %uhi(symbol), %temp1
1531 sethi %hi(symbol), %temp2
1532 or %temp1, %ulo(symbol), %temp3
1533 or %temp2, %lo(symbol), %temp4
1534 sllx %temp3, 32, %temp5
1535 or %temp4, %temp5, %reg */
1536 if (data_segment_operand (op1
, GET_MODE (op1
)))
1538 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1539 emit_insn (gen_embmedany_brsum (op0
, temp1
));
1540 emit_insn (gen_embmedany_losum (op0
, op0
, op1
));
1544 /* It is possible that one of the registers we got for operands[2]
1545 might coincide with that of operands[0] (which is why we made
1546 it TImode). Pick the other one to use as our scratch. */
1547 if (rtx_equal_p (temp1
, op0
))
1550 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1555 emit_insn (gen_embmedany_textuhi (op0
, op1
));
1556 emit_insn (gen_embmedany_texthi (temp1
, op1
));
1557 emit_insn (gen_embmedany_textulo (op0
, op0
, op1
));
1558 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1559 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1560 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1561 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1562 emit_insn (gen_embmedany_textlo (op0
, op0
, op1
));
1571 /* These avoid problems when cross compiling. If we do not
1572 go through all this hair then the optimizer will see
1573 invalid REG_EQUAL notes or in some cases none at all. */
1574 static void sparc_emit_set_safe_HIGH64
PARAMS ((rtx
, HOST_WIDE_INT
));
1575 static rtx gen_safe_SET64
PARAMS ((rtx
, HOST_WIDE_INT
));
1576 static rtx gen_safe_OR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1577 static rtx gen_safe_XOR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1579 #if HOST_BITS_PER_WIDE_INT == 64
1580 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1581 #define GEN_INT64(__x) GEN_INT (__x)
1583 #define GEN_HIGHINT64(__x) \
1584 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1585 #define GEN_INT64(__x) \
1586 immed_double_const ((__x) & 0xffffffff, \
1587 ((__x) & 0x80000000 ? -1 : 0), DImode)
1590 /* The optimizer is not to assume anything about exactly
1591 which bits are set for a HIGH, they are unspecified.
1592 Unfortunately this leads to many missed optimizations
1593 during CSE. We mask out the non-HIGH bits, and matches
1594 a plain movdi, to alleviate this problem. */
1596 sparc_emit_set_safe_HIGH64 (dest
, val
)
1600 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1604 gen_safe_SET64 (dest
, val
)
1608 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1612 gen_safe_OR64 (src
, val
)
1616 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1620 gen_safe_XOR64 (src
, val
)
1624 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1627 /* Worker routines for 64-bit constant formation on arch64.
1628 One of the key things to be doing in these emissions is
1629 to create as many temp REGs as possible. This makes it
1630 possible for half-built constants to be used later when
1631 such values are similar to something required later on.
1632 Without doing this, the optimizer cannot see such
1635 static void sparc_emit_set_const64_quick1
1636 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, int));
1639 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
, is_neg
)
1642 unsigned HOST_WIDE_INT low_bits
;
1645 unsigned HOST_WIDE_INT high_bits
;
1648 high_bits
= (~low_bits
) & 0xffffffff;
1650 high_bits
= low_bits
;
1652 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1655 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1656 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1660 /* If we are XOR'ing with -1, then we should emit a one's complement
1661 instead. This way the combiner will notice logical operations
1662 such as ANDN later on and substitute. */
1663 if ((low_bits
& 0x3ff) == 0x3ff)
1665 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1666 gen_rtx_NOT (DImode
, temp
)));
1670 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1671 gen_safe_XOR64 (temp
,
1672 (-(HOST_WIDE_INT
)0x400
1673 | (low_bits
& 0x3ff)))));
1678 static void sparc_emit_set_const64_quick2
1679 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
,
1680 unsigned HOST_WIDE_INT
, int));
1683 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_immediate
, shift_count
)
1686 unsigned HOST_WIDE_INT high_bits
;
1687 unsigned HOST_WIDE_INT low_immediate
;
1692 if ((high_bits
& 0xfffffc00) != 0)
1694 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1695 if ((high_bits
& ~0xfffffc00) != 0)
1696 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1697 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1703 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1707 /* Now shift it up into place. */
1708 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1709 gen_rtx_ASHIFT (DImode
, temp2
,
1710 GEN_INT (shift_count
))));
1712 /* If there is a low immediate part piece, finish up by
1713 putting that in as well. */
1714 if (low_immediate
!= 0)
1715 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1716 gen_safe_OR64 (op0
, low_immediate
)));
1719 static void sparc_emit_set_const64_longway
1720 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1722 /* Full 64-bit constant decomposition. Even though this is the
1723 'worst' case, we still optimize a few things away. */
1725 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
)
1728 unsigned HOST_WIDE_INT high_bits
;
1729 unsigned HOST_WIDE_INT low_bits
;
1733 if (reload_in_progress
|| reload_completed
)
1736 sub_temp
= gen_reg_rtx (DImode
);
1738 if ((high_bits
& 0xfffffc00) != 0)
1740 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1741 if ((high_bits
& ~0xfffffc00) != 0)
1742 emit_insn (gen_rtx_SET (VOIDmode
,
1744 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1750 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1754 if (!reload_in_progress
&& !reload_completed
)
1756 rtx temp2
= gen_reg_rtx (DImode
);
1757 rtx temp3
= gen_reg_rtx (DImode
);
1758 rtx temp4
= gen_reg_rtx (DImode
);
1760 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1761 gen_rtx_ASHIFT (DImode
, sub_temp
,
1764 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
1765 if ((low_bits
& ~0xfffffc00) != 0)
1767 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1768 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1769 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1770 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1774 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1775 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1780 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1781 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1782 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1785 /* We are in the middle of reload, so this is really
1786 painful. However we do still make an attempt to
1787 avoid emitting truly stupid code. */
1788 if (low1
!= const0_rtx
)
1790 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1791 gen_rtx_ASHIFT (DImode
, sub_temp
,
1792 GEN_INT (to_shift
))));
1793 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1794 gen_rtx_IOR (DImode
, op0
, low1
)));
1802 if (low2
!= const0_rtx
)
1804 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1805 gen_rtx_ASHIFT (DImode
, sub_temp
,
1806 GEN_INT (to_shift
))));
1807 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1808 gen_rtx_IOR (DImode
, op0
, low2
)));
1816 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1817 gen_rtx_ASHIFT (DImode
, sub_temp
,
1818 GEN_INT (to_shift
))));
1819 if (low3
!= const0_rtx
)
1820 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1821 gen_rtx_IOR (DImode
, op0
, low3
)));
1826 /* Analyze a 64-bit constant for certain properties. */
1827 static void analyze_64bit_constant
1828 PARAMS ((unsigned HOST_WIDE_INT
,
1829 unsigned HOST_WIDE_INT
,
1830 int *, int *, int *));
1833 analyze_64bit_constant (high_bits
, low_bits
, hbsp
, lbsp
, abbasp
)
1834 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1835 int *hbsp
, *lbsp
, *abbasp
;
1837 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1840 lowest_bit_set
= highest_bit_set
= -1;
1844 if ((lowest_bit_set
== -1)
1845 && ((low_bits
>> i
) & 1))
1847 if ((highest_bit_set
== -1)
1848 && ((high_bits
>> (32 - i
- 1)) & 1))
1849 highest_bit_set
= (64 - i
- 1);
1852 && ((highest_bit_set
== -1)
1853 || (lowest_bit_set
== -1)));
1859 if ((lowest_bit_set
== -1)
1860 && ((high_bits
>> i
) & 1))
1861 lowest_bit_set
= i
+ 32;
1862 if ((highest_bit_set
== -1)
1863 && ((low_bits
>> (32 - i
- 1)) & 1))
1864 highest_bit_set
= 32 - i
- 1;
1867 && ((highest_bit_set
== -1)
1868 || (lowest_bit_set
== -1)));
1870 /* If there are no bits set this should have gone out
1871 as one instruction! */
1872 if (lowest_bit_set
== -1
1873 || highest_bit_set
== -1)
1875 all_bits_between_are_set
= 1;
1876 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1880 if ((low_bits
& (1 << i
)) != 0)
1885 if ((high_bits
& (1 << (i
- 32))) != 0)
1888 all_bits_between_are_set
= 0;
1891 *hbsp
= highest_bit_set
;
1892 *lbsp
= lowest_bit_set
;
1893 *abbasp
= all_bits_between_are_set
;
1896 static int const64_is_2insns
1897 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1900 const64_is_2insns (high_bits
, low_bits
)
1901 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1903 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1906 || high_bits
== 0xffffffff)
1909 analyze_64bit_constant (high_bits
, low_bits
,
1910 &highest_bit_set
, &lowest_bit_set
,
1911 &all_bits_between_are_set
);
1913 if ((highest_bit_set
== 63
1914 || lowest_bit_set
== 0)
1915 && all_bits_between_are_set
!= 0)
1918 if ((highest_bit_set
- lowest_bit_set
) < 21)
1924 static unsigned HOST_WIDE_INT create_simple_focus_bits
1925 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
,
1928 static unsigned HOST_WIDE_INT
1929 create_simple_focus_bits (high_bits
, low_bits
, lowest_bit_set
, shift
)
1930 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1931 int lowest_bit_set
, shift
;
1933 HOST_WIDE_INT hi
, lo
;
1935 if (lowest_bit_set
< 32)
1937 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1938 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1943 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1950 /* Here we are sure to be arch64 and this is an integer constant
1951 being loaded into a register. Emit the most efficient
1952 insn sequence possible. Detection of all the 1-insn cases
1953 has been done already. */
1955 sparc_emit_set_const64 (op0
, op1
)
1959 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1960 int lowest_bit_set
, highest_bit_set
;
1961 int all_bits_between_are_set
;
1964 /* Sanity check that we know what we are working with. */
1965 if (! TARGET_ARCH64
)
1968 if (GET_CODE (op0
) != SUBREG
)
1970 if (GET_CODE (op0
) != REG
1971 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
1972 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
1976 if (reload_in_progress
|| reload_completed
)
1979 temp
= gen_reg_rtx (DImode
);
1981 if (GET_CODE (op1
) != CONST_DOUBLE
1982 && GET_CODE (op1
) != CONST_INT
)
1984 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1988 if (GET_CODE (op1
) == CONST_DOUBLE
)
1990 #if HOST_BITS_PER_WIDE_INT == 64
1991 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
1992 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
1994 high_bits
= CONST_DOUBLE_HIGH (op1
);
1995 low_bits
= CONST_DOUBLE_LOW (op1
);
2000 #if HOST_BITS_PER_WIDE_INT == 64
2001 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2002 low_bits
= (INTVAL (op1
) & 0xffffffff);
2004 high_bits
= ((INTVAL (op1
) < 0) ?
2007 low_bits
= INTVAL (op1
);
2011 /* low_bits bits 0 --> 31
2012 high_bits bits 32 --> 63 */
2014 analyze_64bit_constant (high_bits
, low_bits
,
2015 &highest_bit_set
, &lowest_bit_set
,
2016 &all_bits_between_are_set
);
2018 /* First try for a 2-insn sequence. */
2020 /* These situations are preferred because the optimizer can
2021 * do more things with them:
2023 * sllx %reg, shift, %reg
2025 * srlx %reg, shift, %reg
2026 * 3) mov some_small_const, %reg
2027 * sllx %reg, shift, %reg
2029 if (((highest_bit_set
== 63
2030 || lowest_bit_set
== 0)
2031 && all_bits_between_are_set
!= 0)
2032 || ((highest_bit_set
- lowest_bit_set
) < 12))
2034 HOST_WIDE_INT the_const
= -1;
2035 int shift
= lowest_bit_set
;
2037 if ((highest_bit_set
!= 63
2038 && lowest_bit_set
!= 0)
2039 || all_bits_between_are_set
== 0)
2042 create_simple_focus_bits (high_bits
, low_bits
,
2045 else if (lowest_bit_set
== 0)
2046 shift
= -(63 - highest_bit_set
);
2048 if (! SPARC_SIMM13_P (the_const
))
2051 emit_insn (gen_safe_SET64 (temp
, the_const
));
2053 emit_insn (gen_rtx_SET (VOIDmode
,
2055 gen_rtx_ASHIFT (DImode
,
2059 emit_insn (gen_rtx_SET (VOIDmode
,
2061 gen_rtx_LSHIFTRT (DImode
,
2063 GEN_INT (-shift
))));
2069 /* Now a range of 22 or less bits set somewhere.
2070 * 1) sethi %hi(focus_bits), %reg
2071 * sllx %reg, shift, %reg
2072 * 2) sethi %hi(focus_bits), %reg
2073 * srlx %reg, shift, %reg
2075 if ((highest_bit_set
- lowest_bit_set
) < 21)
2077 unsigned HOST_WIDE_INT focus_bits
=
2078 create_simple_focus_bits (high_bits
, low_bits
,
2079 lowest_bit_set
, 10);
2081 if (! SPARC_SETHI_P (focus_bits
))
2084 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
2086 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2087 if (lowest_bit_set
< 10)
2088 emit_insn (gen_rtx_SET (VOIDmode
,
2090 gen_rtx_LSHIFTRT (DImode
, temp
,
2091 GEN_INT (10 - lowest_bit_set
))));
2092 else if (lowest_bit_set
> 10)
2093 emit_insn (gen_rtx_SET (VOIDmode
,
2095 gen_rtx_ASHIFT (DImode
, temp
,
2096 GEN_INT (lowest_bit_set
- 10))));
2102 /* 1) sethi %hi(low_bits), %reg
2103 * or %reg, %lo(low_bits), %reg
2104 * 2) sethi %hi(~low_bits), %reg
2105 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2108 || high_bits
== 0xffffffff)
2110 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2111 (high_bits
== 0xffffffff));
2115 /* Now, try 3-insn sequences. */
2117 /* 1) sethi %hi(high_bits), %reg
2118 * or %reg, %lo(high_bits), %reg
2119 * sllx %reg, 32, %reg
2123 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2127 /* We may be able to do something quick
2128 when the constant is negated, so try that. */
2129 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2130 (~low_bits
) & 0xfffffc00))
2132 /* NOTE: The trailing bits get XOR'd so we need the
2133 non-negated bits, not the negated ones. */
2134 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2136 if ((((~high_bits
) & 0xffffffff) == 0
2137 && ((~low_bits
) & 0x80000000) == 0)
2138 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2139 && ((~low_bits
) & 0x80000000) != 0))
2141 int fast_int
= (~low_bits
& 0xffffffff);
2143 if ((SPARC_SETHI_P (fast_int
)
2144 && (~high_bits
& 0xffffffff) == 0)
2145 || SPARC_SIMM13_P (fast_int
))
2146 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2148 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
2153 #if HOST_BITS_PER_WIDE_INT == 64
2154 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2155 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2157 negated_const
= immed_double_const ((~low_bits
) & 0xfffffc00,
2158 (~high_bits
) & 0xffffffff,
2161 sparc_emit_set_const64 (temp
, negated_const
);
2164 /* If we are XOR'ing with -1, then we should emit a one's complement
2165 instead. This way the combiner will notice logical operations
2166 such as ANDN later on and substitute. */
2167 if (trailing_bits
== 0x3ff)
2169 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2170 gen_rtx_NOT (DImode
, temp
)));
2174 emit_insn (gen_rtx_SET (VOIDmode
,
2176 gen_safe_XOR64 (temp
,
2177 (-0x400 | trailing_bits
))));
2182 /* 1) sethi %hi(xxx), %reg
2183 * or %reg, %lo(xxx), %reg
2184 * sllx %reg, yyy, %reg
2186 * ??? This is just a generalized version of the low_bits==0
2187 * thing above, FIXME...
2189 if ((highest_bit_set
- lowest_bit_set
) < 32)
2191 unsigned HOST_WIDE_INT focus_bits
=
2192 create_simple_focus_bits (high_bits
, low_bits
,
2195 /* We can't get here in this state. */
2196 if (highest_bit_set
< 32
2197 || lowest_bit_set
>= 32)
2200 /* So what we know is that the set bits straddle the
2201 middle of the 64-bit word. */
2202 sparc_emit_set_const64_quick2 (op0
, temp
,
2208 /* 1) sethi %hi(high_bits), %reg
2209 * or %reg, %lo(high_bits), %reg
2210 * sllx %reg, 32, %reg
2211 * or %reg, low_bits, %reg
2213 if (SPARC_SIMM13_P(low_bits
)
2214 && ((int)low_bits
> 0))
2216 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2220 /* The easiest way when all else fails, is full decomposition. */
2222 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2223 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
2225 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2228 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2229 return the mode to be used for the comparison. For floating-point,
2230 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2231 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2232 processing is needed. */
2235 select_cc_mode (op
, x
, y
)
2238 rtx y ATTRIBUTE_UNUSED
;
2240 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2266 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2267 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2269 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2270 return CCX_NOOVmode
;
2276 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2283 /* X and Y are two things to compare using CODE. Emit the compare insn and
2284 return the rtx for the cc reg in the proper mode. */
2287 gen_compare_reg (code
, x
, y
)
2291 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2294 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2295 fcc regs (cse can't tell they're really call clobbered regs and will
2296 remove a duplicate comparison even if there is an intervening function
2297 call - it will then try to reload the cc reg via an int reg which is why
2298 we need the movcc patterns). It is possible to provide the movcc
2299 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2300 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2301 to tell cse that CCFPE mode registers (even pseudos) are call
2304 /* ??? This is an experiment. Rather than making changes to cse which may
2305 or may not be easy/clean, we do our own cse. This is possible because
2306 we will generate hard registers. Cse knows they're call clobbered (it
2307 doesn't know the same thing about pseudos). If we guess wrong, no big
2308 deal, but if we win, great! */
2310 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2311 #if 1 /* experiment */
2314 /* We cycle through the registers to ensure they're all exercised. */
2315 static int next_fcc_reg
= 0;
2316 /* Previous x,y for each fcc reg. */
2317 static rtx prev_args
[4][2];
2319 /* Scan prev_args for x,y. */
2320 for (reg
= 0; reg
< 4; reg
++)
2321 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2326 prev_args
[reg
][0] = x
;
2327 prev_args
[reg
][1] = y
;
2328 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2330 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2333 cc_reg
= gen_reg_rtx (mode
);
2334 #endif /* ! experiment */
2335 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2336 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2338 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2340 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2341 gen_rtx_COMPARE (mode
, x
, y
)));
2346 /* This function is used for v9 only.
2347 CODE is the code for an Scc's comparison.
2348 OPERANDS[0] is the target of the Scc insn.
2349 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2350 been generated yet).
2352 This function is needed to turn
2355 (gt (reg:CCX 100 %icc)
2359 (gt:DI (reg:CCX 100 %icc)
2362 IE: The instruction recognizer needs to see the mode of the comparison to
2363 find the right instruction. We could use "gt:DI" right in the
2364 define_expand, but leaving it out allows us to handle DI, SI, etc.
2366 We refer to the global sparc compare operands sparc_compare_op0 and
2367 sparc_compare_op1. */
2370 gen_v9_scc (compare_code
, operands
)
2371 enum rtx_code compare_code
;
2372 register rtx
*operands
;
2377 && (GET_MODE (sparc_compare_op0
) == DImode
2378 || GET_MODE (operands
[0]) == DImode
))
2381 op0
= sparc_compare_op0
;
2382 op1
= sparc_compare_op1
;
2384 /* Try to use the movrCC insns. */
2386 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2387 && op1
== const0_rtx
2388 && v9_regcmp_p (compare_code
))
2390 /* Special case for op0 != 0. This can be done with one instruction if
2391 operands[0] == sparc_compare_op0. */
2393 if (compare_code
== NE
2394 && GET_MODE (operands
[0]) == DImode
2395 && rtx_equal_p (op0
, operands
[0]))
2397 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2398 gen_rtx_IF_THEN_ELSE (DImode
,
2399 gen_rtx_fmt_ee (compare_code
, DImode
,
2406 if (reg_overlap_mentioned_p (operands
[0], op0
))
2408 /* Handle the case where operands[0] == sparc_compare_op0.
2409 We "early clobber" the result. */
2410 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2411 emit_move_insn (op0
, sparc_compare_op0
);
2414 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2415 if (GET_MODE (op0
) != DImode
)
2417 temp
= gen_reg_rtx (DImode
);
2418 convert_move (temp
, op0
, 0);
2422 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2423 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2424 gen_rtx_fmt_ee (compare_code
, DImode
,
2432 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2434 switch (GET_MODE (operands
[1]))
2444 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2445 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2446 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2447 gen_rtx_fmt_ee (compare_code
,
2448 GET_MODE (operands
[1]),
2449 operands
[1], const0_rtx
),
2450 const1_rtx
, operands
[0])));
2455 /* Emit a conditional jump insn for the v9 architecture using comparison code
2456 CODE and jump target LABEL.
2457 This function exists to take advantage of the v9 brxx insns. */
2460 emit_v9_brxx_insn (code
, op0
, label
)
2464 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2466 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2467 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2469 gen_rtx_LABEL_REF (VOIDmode
, label
),
2473 /* Generate a DFmode part of a hard TFmode register.
2474 REG is the TFmode hard register, LOW is 1 for the
2475 low 64bit of the register and 0 otherwise.
2478 gen_df_reg (reg
, low
)
2482 int regno
= REGNO (reg
);
2484 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2485 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2486 return gen_rtx_REG (DFmode
, regno
);
2489 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2490 Unlike normal calls, TFmode operands are passed by reference. It is
2491 assumed that no more than 3 operands are required. */
2494 emit_soft_tfmode_libcall (func_name
, nargs
, operands
)
2495 const char *func_name
;
2499 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2502 /* We only expect to be called for conversions, unary, and binary ops. */
2503 if (nargs
< 2 || nargs
> 3)
2506 for (i
= 0; i
< nargs
; ++i
)
2508 rtx this_arg
= operands
[i
];
2511 /* TFmode arguments and return values are passed by reference. */
2512 if (GET_MODE (this_arg
) == TFmode
)
2514 int force_stack_temp
;
2516 force_stack_temp
= 0;
2517 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2518 force_stack_temp
= 1;
2520 if (GET_CODE (this_arg
) == MEM
2521 && ! force_stack_temp
)
2522 this_arg
= XEXP (this_arg
, 0);
2523 else if (CONSTANT_P (this_arg
)
2524 && ! force_stack_temp
)
2526 this_slot
= force_const_mem (TFmode
, this_arg
);
2527 this_arg
= XEXP (this_slot
, 0);
2531 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2533 /* Operand 0 is the return value. We'll copy it out later. */
2535 emit_move_insn (this_slot
, this_arg
);
2537 ret_slot
= this_slot
;
2539 this_arg
= XEXP (this_slot
, 0);
2546 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2548 if (GET_MODE (operands
[0]) == TFmode
)
2551 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2552 arg
[0], GET_MODE (arg
[0]),
2553 arg
[1], GET_MODE (arg
[1]));
2555 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2556 arg
[0], GET_MODE (arg
[0]),
2557 arg
[1], GET_MODE (arg
[1]),
2558 arg
[2], GET_MODE (arg
[2]));
2561 emit_move_insn (operands
[0], ret_slot
);
2570 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2571 GET_MODE (operands
[0]), 1,
2572 arg
[1], GET_MODE (arg
[1]));
2574 if (ret
!= operands
[0])
2575 emit_move_insn (operands
[0], ret
);
2579 /* Expand soft-float TFmode calls to sparc abi routines. */
2582 emit_soft_tfmode_binop (code
, operands
)
2606 emit_soft_tfmode_libcall (func
, 3, operands
);
2610 emit_soft_tfmode_unop (code
, operands
)
2625 emit_soft_tfmode_libcall (func
, 2, operands
);
2629 emit_soft_tfmode_cvt (code
, operands
)
2638 switch (GET_MODE (operands
[1]))
2651 case FLOAT_TRUNCATE
:
2652 switch (GET_MODE (operands
[0]))
2666 switch (GET_MODE (operands
[1]))
2679 case UNSIGNED_FLOAT
:
2680 switch (GET_MODE (operands
[1]))
2694 switch (GET_MODE (operands
[0]))
2708 switch (GET_MODE (operands
[0]))
2725 emit_soft_tfmode_libcall (func
, 2, operands
);
2728 /* Expand a hard-float tfmode operation. All arguments must be in
2732 emit_hard_tfmode_operation (code
, operands
)
2738 if (GET_RTX_CLASS (code
) == '1')
2740 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2741 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2745 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2746 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2747 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2748 operands
[1], operands
[2]);
2751 if (register_operand (operands
[0], VOIDmode
))
2754 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2756 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2758 if (dest
!= operands
[0])
2759 emit_move_insn (operands
[0], dest
);
2763 emit_tfmode_binop (code
, operands
)
2767 if (TARGET_HARD_QUAD
)
2768 emit_hard_tfmode_operation (code
, operands
);
2770 emit_soft_tfmode_binop (code
, operands
);
2774 emit_tfmode_unop (code
, operands
)
2778 if (TARGET_HARD_QUAD
)
2779 emit_hard_tfmode_operation (code
, operands
);
2781 emit_soft_tfmode_unop (code
, operands
);
2785 emit_tfmode_cvt (code
, operands
)
2789 if (TARGET_HARD_QUAD
)
2790 emit_hard_tfmode_operation (code
, operands
);
2792 emit_soft_tfmode_cvt (code
, operands
);
2795 /* Return nonzero if a return peephole merging return with
2796 setting of output register is ok. */
2798 leaf_return_peephole_ok ()
2800 return (actual_fsize
== 0);
2803 /* Return nonzero if a branch/jump/call instruction will be emitting
2804 nop into its delay slot. */
2807 empty_delay_slot (insn
)
2812 /* If no previous instruction (should not happen), return true. */
2813 if (PREV_INSN (insn
) == NULL
)
2816 seq
= NEXT_INSN (PREV_INSN (insn
));
2817 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2823 /* Return nonzero if TRIAL can go into the function epilogue's
2824 delay slot. SLOT is the slot we are trying to fill. */
2827 eligible_for_epilogue_delay (trial
, slot
)
2836 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2839 if (get_attr_length (trial
) != 1)
2842 /* If there are any call-saved registers, we should scan TRIAL if it
2843 does not reference them. For now just make it easy. */
2847 /* If the function uses __builtin_eh_return, the eh_return machinery
2848 occupies the delay slot. */
2849 if (current_function_calls_eh_return
)
2852 /* In the case of a true leaf function, anything can go into the delay slot.
2853 A delay slot only exists however if the frame size is zero, otherwise
2854 we will put an insn to adjust the stack after the return. */
2855 if (current_function_uses_only_leaf_regs
)
2857 if (leaf_return_peephole_ok ())
2858 return ((get_attr_in_uncond_branch_delay (trial
)
2859 == IN_BRANCH_DELAY_TRUE
));
2863 pat
= PATTERN (trial
);
2865 /* Otherwise, only operations which can be done in tandem with
2866 a `restore' or `return' insn can go into the delay slot. */
2867 if (GET_CODE (SET_DEST (pat
)) != REG
2868 || REGNO (SET_DEST (pat
)) < 24)
2871 /* If this instruction sets up floating point register and we have a return
2872 instruction, it can probably go in. But restore will not work
2874 if (REGNO (SET_DEST (pat
)) >= 32)
2876 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2877 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2882 /* The set of insns matched here must agree precisely with the set of
2883 patterns paired with a RETURN in sparc.md. */
2885 src
= SET_SRC (pat
);
2887 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2888 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2889 && arith_operand (src
, GET_MODE (src
)))
2892 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2894 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2897 /* This matches "*return_di". */
2898 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2899 && arith_double_operand (src
, GET_MODE (src
)))
2900 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2902 /* This matches "*return_sf_no_fpu". */
2903 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2904 && register_operand (src
, SFmode
))
2907 /* If we have return instruction, anything that does not use
2908 local or output registers and can go into a delay slot wins. */
2909 else if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2910 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2913 /* This matches "*return_addsi". */
2914 else if (GET_CODE (src
) == PLUS
2915 && arith_operand (XEXP (src
, 0), SImode
)
2916 && arith_operand (XEXP (src
, 1), SImode
)
2917 && (register_operand (XEXP (src
, 0), SImode
)
2918 || register_operand (XEXP (src
, 1), SImode
)))
2921 /* This matches "*return_adddi". */
2922 else if (GET_CODE (src
) == PLUS
2923 && arith_double_operand (XEXP (src
, 0), DImode
)
2924 && arith_double_operand (XEXP (src
, 1), DImode
)
2925 && (register_operand (XEXP (src
, 0), DImode
)
2926 || register_operand (XEXP (src
, 1), DImode
)))
2929 /* This can match "*return_losum_[sd]i".
2930 Catch only some cases, so that return_losum* don't have
2932 else if (GET_CODE (src
) == LO_SUM
2933 && ! TARGET_CM_MEDMID
2934 && ((register_operand (XEXP (src
, 0), SImode
)
2935 && immediate_operand (XEXP (src
, 1), SImode
))
2937 && register_operand (XEXP (src
, 0), DImode
)
2938 && immediate_operand (XEXP (src
, 1), DImode
))))
2941 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2942 else if (GET_CODE (src
) == ASHIFT
2943 && (register_operand (XEXP (src
, 0), SImode
)
2944 || register_operand (XEXP (src
, 0), DImode
))
2945 && XEXP (src
, 1) == const1_rtx
)
2951 /* Return nonzero if TRIAL can go into the sibling call
2955 eligible_for_sibcall_delay (trial
)
2960 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2963 if (get_attr_length (trial
) != 1)
2966 pat
= PATTERN (trial
);
2968 if (current_function_uses_only_leaf_regs
)
2970 /* If the tail call is done using the call instruction,
2971 we have to restore %o7 in the delay slot. */
2972 if ((TARGET_ARCH64
&& ! TARGET_CM_MEDLOW
) || flag_pic
)
2975 /* %g1 is used to build the function address */
2976 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2982 /* Otherwise, only operations which can be done in tandem with
2983 a `restore' insn can go into the delay slot. */
2984 if (GET_CODE (SET_DEST (pat
)) != REG
2985 || REGNO (SET_DEST (pat
)) < 24
2986 || REGNO (SET_DEST (pat
)) >= 32)
2989 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2991 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2994 src
= SET_SRC (pat
);
2996 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2997 && arith_operand (src
, GET_MODE (src
)))
3000 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3002 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3005 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3006 && arith_double_operand (src
, GET_MODE (src
)))
3007 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3009 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
3010 && register_operand (src
, SFmode
))
3013 else if (GET_CODE (src
) == PLUS
3014 && arith_operand (XEXP (src
, 0), SImode
)
3015 && arith_operand (XEXP (src
, 1), SImode
)
3016 && (register_operand (XEXP (src
, 0), SImode
)
3017 || register_operand (XEXP (src
, 1), SImode
)))
3020 else if (GET_CODE (src
) == PLUS
3021 && arith_double_operand (XEXP (src
, 0), DImode
)
3022 && arith_double_operand (XEXP (src
, 1), DImode
)
3023 && (register_operand (XEXP (src
, 0), DImode
)
3024 || register_operand (XEXP (src
, 1), DImode
)))
3027 else if (GET_CODE (src
) == LO_SUM
3028 && ! TARGET_CM_MEDMID
3029 && ((register_operand (XEXP (src
, 0), SImode
)
3030 && immediate_operand (XEXP (src
, 1), SImode
))
3032 && register_operand (XEXP (src
, 0), DImode
)
3033 && immediate_operand (XEXP (src
, 1), DImode
))))
3036 else if (GET_CODE (src
) == ASHIFT
3037 && (register_operand (XEXP (src
, 0), SImode
)
3038 || register_operand (XEXP (src
, 0), DImode
))
3039 && XEXP (src
, 1) == const1_rtx
)
3046 check_return_regs (x
)
3049 switch (GET_CODE (x
))
3052 return IN_OR_GLOBAL_P (x
);
3067 if (check_return_regs (XEXP (x
, 1)) == 0)
3072 return check_return_regs (XEXP (x
, 0));
3081 short_branch (uid1
, uid2
)
3084 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
3086 /* Leave a few words of "slop". */
3087 if (delta
>= -1023 && delta
<= 1022)
3093 /* Return nonzero if REG is not used after INSN.
3094 We assume REG is a reload reg, and therefore does
3095 not live past labels or calls or jumps. */
3097 reg_unused_after (reg
, insn
)
3101 enum rtx_code code
, prev_code
= UNKNOWN
;
3103 while ((insn
= NEXT_INSN (insn
)))
3105 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3108 code
= GET_CODE (insn
);
3109 if (GET_CODE (insn
) == CODE_LABEL
)
3112 if (GET_RTX_CLASS (code
) == 'i')
3114 rtx set
= single_set (insn
);
3115 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3118 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3120 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3128 /* The table we use to reference PIC data. */
3129 static GTY(()) rtx global_offset_table
;
3131 /* The function we use to get at it. */
3132 static GTY(()) rtx get_pc_symbol
;
3133 static char get_pc_symbol_name
[256];
3135 /* Ensure that we are not using patterns that are not OK with PIC. */
3144 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
3145 || (GET_CODE (recog_data
.operand
[i
]) == CONST
3146 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
3147 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
3148 == global_offset_table
)
3149 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
3158 /* Return true if X is an address which needs a temporary register when
3159 reloaded while generating PIC code. */
3162 pic_address_needs_scratch (x
)
3165 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3166 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3167 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3168 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3169 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3175 /* Legitimize PIC addresses. If the address is already position-independent,
3176 we return ORIG. Newly generated position-independent addresses go into a
3177 reg. This is REG if nonzero, otherwise we allocate register(s) as
3181 legitimize_pic_address (orig
, mode
, reg
)
3183 enum machine_mode mode ATTRIBUTE_UNUSED
;
3186 if (GET_CODE (orig
) == SYMBOL_REF
)
3188 rtx pic_ref
, address
;
3193 if (reload_in_progress
|| reload_completed
)
3196 reg
= gen_reg_rtx (Pmode
);
3201 /* If not during reload, allocate another temp reg here for loading
3202 in the address, so that these instructions can be optimized
3204 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3205 ? reg
: gen_reg_rtx (Pmode
));
3207 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3208 won't get confused into thinking that these two instructions
3209 are loading in the true address of the symbol. If in the
3210 future a PIC rtx exists, that should be used instead. */
3211 if (Pmode
== SImode
)
3213 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3214 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3218 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3219 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3226 pic_ref
= gen_rtx_MEM (Pmode
,
3227 gen_rtx_PLUS (Pmode
,
3228 pic_offset_table_rtx
, address
));
3229 current_function_uses_pic_offset_table
= 1;
3230 RTX_UNCHANGING_P (pic_ref
) = 1;
3231 insn
= emit_move_insn (reg
, pic_ref
);
3232 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3234 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3238 else if (GET_CODE (orig
) == CONST
)
3242 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3243 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3248 if (reload_in_progress
|| reload_completed
)
3251 reg
= gen_reg_rtx (Pmode
);
3254 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
3256 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3257 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3258 base
== reg
? 0 : reg
);
3263 if (GET_CODE (offset
) == CONST_INT
)
3265 if (SMALL_INT (offset
))
3266 return plus_constant (base
, INTVAL (offset
));
3267 else if (! reload_in_progress
&& ! reload_completed
)
3268 offset
= force_reg (Pmode
, offset
);
3270 /* If we reach here, then something is seriously wrong. */
3273 return gen_rtx_PLUS (Pmode
, base
, offset
);
3275 else if (GET_CODE (orig
) == LABEL_REF
)
3276 /* ??? Why do we do this? */
3277 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3278 the register is live instead, in case it is eliminated. */
3279 current_function_uses_pic_offset_table
= 1;
3284 /* Emit special PIC prologues. */
3287 load_pic_register ()
3289 /* Labels to get the PC in the prologue of this function. */
3290 int orig_flag_pic
= flag_pic
;
3295 /* If we haven't emitted the special get_pc helper function, do so now. */
3296 if (get_pc_symbol_name
[0] == 0)
3300 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name
, "LGETPC", 0);
3303 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3305 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3306 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LGETPC", 0);
3307 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file
);
3310 /* Initialize every time through, since we can't easily
3311 know this to be permanent. */
3312 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3313 get_pc_symbol
= gen_rtx_SYMBOL_REF (Pmode
, get_pc_symbol_name
);
3316 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
3319 flag_pic
= orig_flag_pic
;
3321 /* Need to emit this whether or not we obey regdecls,
3322 since setjmp/longjmp can cause life info to screw up.
3323 ??? In the case where we don't obey regdecls, this is not sufficient
3324 since we may not fall out the bottom. */
3325 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3328 /* Return 1 if RTX is a MEM which is known to be aligned to at
3329 least a DESIRED byte boundary. */
3332 mem_min_alignment (mem
, desired
)
3336 rtx addr
, base
, offset
;
3338 /* If it's not a MEM we can't accept it. */
3339 if (GET_CODE (mem
) != MEM
)
3342 addr
= XEXP (mem
, 0);
3343 base
= offset
= NULL_RTX
;
3344 if (GET_CODE (addr
) == PLUS
)
3346 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3348 base
= XEXP (addr
, 0);
3350 /* What we are saying here is that if the base
3351 REG is aligned properly, the compiler will make
3352 sure any REG based index upon it will be so
3354 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3355 offset
= XEXP (addr
, 1);
3357 offset
= const0_rtx
;
3360 else if (GET_CODE (addr
) == REG
)
3363 offset
= const0_rtx
;
3366 if (base
!= NULL_RTX
)
3368 int regno
= REGNO (base
);
3370 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3372 /* Check if the compiler has recorded some information
3373 about the alignment of the base REG. If reload has
3374 completed, we already matched with proper alignments.
3375 If not running global_alloc, reload might give us
3376 unaligned pointer to local stack though. */
3378 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3379 || (optimize
&& reload_completed
))
3380 && (INTVAL (offset
) & (desired
- 1)) == 0)
3385 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3389 else if (! TARGET_UNALIGNED_DOUBLES
3390 || CONSTANT_P (addr
)
3391 || GET_CODE (addr
) == LO_SUM
)
3393 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3394 is true, in which case we can only assume that an access is aligned if
3395 it is to a constant address, or the address involves a LO_SUM. */
3399 /* An obviously unaligned address. */
3404 /* Vectors to keep interesting information about registers where it can easily
3405 be got. We used to use the actual mode value as the bit number, but there
3406 are more than 32 modes now. Instead we use two tables: one indexed by
3407 hard register number, and one indexed by mode. */
3409 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3410 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3411 mapped into one sparc_mode_class mode. */
3413 enum sparc_mode_class
{
3414 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3415 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3419 /* Modes for single-word and smaller quantities. */
3420 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3422 /* Modes for double-word and smaller quantities. */
3423 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3425 /* Modes for quad-word and smaller quantities. */
3426 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3428 /* Modes for 8-word and smaller quantities. */
3429 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3431 /* Modes for single-float quantities. We must allow any single word or
3432 smaller quantity. This is because the fix/float conversion instructions
3433 take integer inputs/outputs from the float registers. */
3434 #define SF_MODES (S_MODES)
3436 /* Modes for double-float and smaller quantities. */
3437 #define DF_MODES (S_MODES | D_MODES)
3439 /* Modes for double-float only quantities. */
3440 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3442 /* Modes for quad-float only quantities. */
3443 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3445 /* Modes for quad-float and smaller quantities. */
3446 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3448 /* Modes for quad-float and double-float quantities. */
3449 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3451 /* Modes for quad-float pair only quantities. */
3452 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3454 /* Modes for quad-float pairs and smaller quantities. */
3455 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3457 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3459 /* Modes for condition codes. */
3460 #define CC_MODES (1 << (int) CC_MODE)
3461 #define CCFP_MODES (1 << (int) CCFP_MODE)
3463 /* Value is 1 if register/mode pair is acceptable on sparc.
3464 The funny mixture of D and T modes is because integer operations
3465 do not specially operate on tetra quantities, so non-quad-aligned
3466 registers can hold quadword quantities (except %o4 and %i4 because
3467 they cross fixed registers). */
3469 /* This points to either the 32 bit or the 64 bit version. */
3470 const int *hard_regno_mode_classes
;
3472 static const int hard_32bit_mode_classes
[] = {
3473 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3474 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3475 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3476 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3478 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3479 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3480 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3481 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3483 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3484 and none can hold SFmode/SImode values. */
3485 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3486 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3487 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3488 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3491 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3497 static const int hard_64bit_mode_classes
[] = {
3498 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3499 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3500 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3501 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3503 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3504 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3505 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3506 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3508 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3509 and none can hold SFmode/SImode values. */
3510 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3511 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3512 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3513 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3516 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3522 int sparc_mode_class
[NUM_MACHINE_MODES
];
3524 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3531 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3533 switch (GET_MODE_CLASS (i
))
3536 case MODE_PARTIAL_INT
:
3537 case MODE_COMPLEX_INT
:
3538 if (GET_MODE_SIZE (i
) <= 4)
3539 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3540 else if (GET_MODE_SIZE (i
) == 8)
3541 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3542 else if (GET_MODE_SIZE (i
) == 16)
3543 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3544 else if (GET_MODE_SIZE (i
) == 32)
3545 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3547 sparc_mode_class
[i
] = 0;
3550 case MODE_COMPLEX_FLOAT
:
3551 if (GET_MODE_SIZE (i
) <= 4)
3552 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3553 else if (GET_MODE_SIZE (i
) == 8)
3554 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3555 else if (GET_MODE_SIZE (i
) == 16)
3556 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3557 else if (GET_MODE_SIZE (i
) == 32)
3558 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3560 sparc_mode_class
[i
] = 0;
3564 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3565 we must explicitly check for them here. */
3566 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3567 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3568 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
3569 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
3570 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3572 sparc_mode_class
[i
] = 0;
3578 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3580 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3582 /* Initialize the array used by REGNO_REG_CLASS. */
3583 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3585 if (i
< 16 && TARGET_V8PLUS
)
3586 sparc_regno_reg_class
[i
] = I64_REGS
;
3587 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
3588 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3590 sparc_regno_reg_class
[i
] = FP_REGS
;
3592 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3594 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3596 sparc_regno_reg_class
[i
] = NO_REGS
;
3600 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3601 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3602 v9 int regs as it simplifies the code. */
3605 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
3615 if (TARGET_ARCH64
&& high
<= 32)
3617 for (i
= low
; i
< high
; i
++)
3619 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3621 fprintf (file
, "\tstx\t%s, [%s+%d]\n",
3622 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3623 if (dwarf2out_do_frame ())
3624 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3631 for (i
= low
; i
< high
; i
+= 2)
3633 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3635 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3637 fprintf (file
, "\tstd\t%s, [%s+%d]\n",
3638 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3639 if (dwarf2out_do_frame ())
3641 char *l
= dwarf2out_cfi_label ();
3642 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
3643 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
3649 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3650 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3651 if (dwarf2out_do_frame ())
3652 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3658 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3660 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3661 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
3662 if (dwarf2out_do_frame ())
3663 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
3672 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3674 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3675 v9 int regs as it simplifies the code. */
3678 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
3687 if (TARGET_ARCH64
&& high
<= 32)
3689 for (i
= low
; i
< high
; i
++)
3691 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3692 fprintf (file
, "\tldx\t[%s+%d], %s\n",
3693 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3699 for (i
= low
; i
< high
; i
+= 2)
3701 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3702 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3703 fprintf (file
, "\tldd\t[%s+%d], %s\n",
3704 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3707 fprintf (file
, "\tld\t[%s+%d], %s\n",
3708 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3710 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3711 fprintf (file
, "\tld\t[%s+%d], %s\n",
3712 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3719 /* Compute the frame size required by the function. This function is called
3720 during the reload pass and also by output_function_prologue(). */
3723 compute_frame_size (size
, leaf_function
)
3728 int outgoing_args_size
= (current_function_outgoing_args_size
3729 + REG_PARM_STACK_SPACE (current_function_decl
));
3731 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3732 even to v9 int regs to be consistent with save_regs/restore_regs. */
3736 for (i
= 0; i
< 8; i
++)
3737 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3742 for (i
= 0; i
< 8; i
+= 2)
3743 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3744 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3748 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3749 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3750 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3753 /* Set up values for use in `function_epilogue'. */
3754 num_gfregs
= n_regs
;
3756 if (leaf_function
&& n_regs
== 0
3757 && size
== 0 && current_function_outgoing_args_size
== 0)
3759 actual_fsize
= apparent_fsize
= 0;
3763 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3764 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
3765 apparent_fsize
+= n_regs
* 4;
3766 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3769 /* Make sure nothing can clobber our register windows.
3770 If a SAVE must be done, or there is a stack-local variable,
3771 the register window area must be allocated.
3772 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3773 if (leaf_function
== 0 || size
> 0)
3774 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3776 return SPARC_STACK_ALIGN (actual_fsize
);
3779 /* Build a (32 bit) big number in a register. */
3780 /* ??? We may be able to use the set macro here too. */
3783 build_big_number (file
, num
, reg
)
3788 if (num
>= 0 || ! TARGET_ARCH64
)
3790 fprintf (file
, "\tsethi\t%%hi(%d), %s\n", num
, reg
);
3791 if ((num
& 0x3ff) != 0)
3792 fprintf (file
, "\tor\t%s, %%lo(%d), %s\n", reg
, num
, reg
);
3794 else /* num < 0 && TARGET_ARCH64 */
3796 /* Sethi does not sign extend, so we must use a little trickery
3797 to use it for negative numbers. Invert the constant before
3798 loading it in, then use xor immediate to invert the loaded bits
3799 (along with the upper 32 bits) to the desired constant. This
3800 works because the sethi and immediate fields overlap. */
3803 int low
= -0x400 + (asize
& 0x3FF);
3805 fprintf (file
, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3806 inv
, reg
, reg
, low
, reg
);
3810 /* Output any necessary .register pseudo-ops. */
3812 sparc_output_scratch_registers (file
)
3813 FILE *file ATTRIBUTE_UNUSED
;
3815 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3821 /* Check if %g[2367] were used without
3822 .register being printed for them already. */
3823 for (i
= 2; i
< 8; i
++)
3825 if (regs_ever_live
[i
]
3826 && ! sparc_hard_reg_printed
[i
])
3828 sparc_hard_reg_printed
[i
] = 1;
3829 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
3836 /* This function generates the assembly code for function entry.
3837 FILE is a stdio stream to output the code to.
3838 SIZE is an int: how many units of temporary storage to allocate.
3839 Refer to the array `regs_ever_live' to determine which registers
3840 to save; `regs_ever_live[I]' is nonzero if register number I
3841 is ever used in the function. This macro is responsible for
3842 knowing which registers should not be saved even if used. */
3844 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3845 of memory. If any fpu reg is used in the function, we allocate
3846 such a block here, at the bottom of the frame, just in case it's needed.
3848 If this function is a leaf procedure, then we may choose not
3849 to do a "save" insn. The decision about whether or not
3850 to do this is made in regclass.c. */
3853 sparc_output_function_prologue (file
, size
)
3858 sparc_flat_function_prologue (file
, size
);
3860 sparc_nonflat_function_prologue (file
, size
,
3861 current_function_uses_only_leaf_regs
);
3864 /* Output code for the function prologue. */
3867 sparc_nonflat_function_prologue (file
, size
, leaf_function
)
3872 sparc_output_scratch_registers (file
);
3874 /* Need to use actual_fsize, since we are also allocating
3875 space for our callee (and our own register save area). */
3876 actual_fsize
= compute_frame_size (size
, leaf_function
);
3880 frame_base_name
= "%sp";
3881 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3885 frame_base_name
= "%fp";
3886 frame_base_offset
= SPARC_STACK_BIAS
;
3889 /* This is only for the human reader. */
3890 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3892 if (actual_fsize
== 0)
3894 else if (! leaf_function
)
3896 if (actual_fsize
<= 4096)
3897 fprintf (file
, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize
);
3898 else if (actual_fsize
<= 8192)
3900 fprintf (file
, "\tsave\t%%sp, -4096, %%sp\n");
3901 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3905 build_big_number (file
, -actual_fsize
, "%g1");
3906 fprintf (file
, "\tsave\t%%sp, %%g1, %%sp\n");
3909 else /* leaf function */
3911 if (actual_fsize
<= 4096)
3912 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
);
3913 else if (actual_fsize
<= 8192)
3915 fprintf (file
, "\tadd\t%%sp, -4096, %%sp\n");
3916 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3920 build_big_number (file
, -actual_fsize
, "%g1");
3921 fprintf (file
, "\tadd\t%%sp, %%g1, %%sp\n");
3925 if (dwarf2out_do_frame () && actual_fsize
)
3927 char *label
= dwarf2out_cfi_label ();
3929 /* The canonical frame address refers to the top of the frame. */
3930 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3931 : HARD_FRAME_POINTER_REGNUM
),
3934 if (! leaf_function
)
3936 /* Note the register window save. This tells the unwinder that
3937 it needs to restore the window registers from the previous
3938 frame's window save area at 0(cfa). */
3939 dwarf2out_window_save (label
);
3941 /* The return address (-8) is now in %i7. */
3942 dwarf2out_return_reg (label
, 31);
3946 /* If doing anything with PIC, do it now. */
3948 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3950 /* Call saved registers are saved just above the outgoing argument area. */
3953 int offset
, real_offset
, n_regs
;
3956 real_offset
= -apparent_fsize
;
3957 offset
= -apparent_fsize
+ frame_base_offset
;
3958 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3960 /* ??? This might be optimized a little as %g1 might already have a
3961 value close enough that a single add insn will do. */
3962 /* ??? Although, all of this is probably only a temporary fix
3963 because if %g1 can hold a function result, then
3964 output_function_epilogue will lose (the result will get
3966 build_big_number (file
, offset
, "%g1");
3967 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3973 base
= frame_base_name
;
3976 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3977 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3982 /* Output code to restore any call saved registers. */
3985 output_restore_regs (file
, leaf_function
)
3987 int leaf_function ATTRIBUTE_UNUSED
;
3992 offset
= -apparent_fsize
+ frame_base_offset
;
3993 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3995 build_big_number (file
, offset
, "%g1");
3996 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
4002 base
= frame_base_name
;
4005 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
4006 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
4009 /* This function generates the assembly code for function exit,
4010 on machines that need it.
4012 The function epilogue should not depend on the current stack pointer!
4013 It should use the frame pointer only. This is mandatory because
4014 of alloca; we also take advantage of it to omit stack adjustments
4015 before returning. */
4018 sparc_output_function_epilogue (file
, size
)
4023 sparc_flat_function_epilogue (file
, size
);
4025 sparc_nonflat_function_epilogue (file
, size
,
4026 current_function_uses_only_leaf_regs
);
4029 /* Output code for the function epilogue. */
4032 sparc_nonflat_function_epilogue (file
, size
, leaf_function
)
4034 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
4039 if (current_function_epilogue_delay_list
== 0)
4041 /* If code does not drop into the epilogue, we need
4042 do nothing except output pending case vectors.
4044 We have to still output a dummy nop for the sake of
4045 sane backtraces. Otherwise, if the last two instructions
4046 of a function were call foo; dslot; this can make the return
4047 PC of foo (ie. address of call instruction plus 8) point to
4048 the first instruction in the next function. */
4051 fputs("\tnop\n", file
);
4053 insn
= get_last_insn ();
4054 if (GET_CODE (insn
) == NOTE
)
4055 insn
= prev_nonnote_insn (insn
);
4056 if (insn
&& GET_CODE (insn
) == BARRIER
)
4057 goto output_vectors
;
4061 output_restore_regs (file
, leaf_function
);
4063 /* Work out how to skip the caller's unimp instruction if required. */
4065 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%o7+12" : "retl");
4067 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%i7+12" : "ret");
4069 if (! leaf_function
)
4071 if (current_function_calls_eh_return
)
4073 if (current_function_epilogue_delay_list
)
4075 if (SKIP_CALLERS_UNIMP_P
)
4078 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file
);
4080 /* If we wound up with things in our delay slot, flush them here. */
4081 else if (current_function_epilogue_delay_list
)
4083 rtx delay
= PATTERN (XEXP (current_function_epilogue_delay_list
, 0));
4085 if (TARGET_V9
&& ! epilogue_renumber (&delay
, 1))
4087 epilogue_renumber (&delay
, 0);
4088 fputs (SKIP_CALLERS_UNIMP_P
4089 ? "\treturn\t%i7+12\n"
4090 : "\treturn\t%i7+8\n", file
);
4091 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4098 if (GET_CODE (delay
) != SET
)
4101 src
= SET_SRC (delay
);
4102 if (GET_CODE (src
) == ASHIFT
)
4104 if (XEXP (src
, 1) != const1_rtx
)
4107 = gen_rtx_PLUS (GET_MODE (src
), XEXP (src
, 0),
4111 insn
= gen_rtx_PARALLEL (VOIDmode
,
4112 gen_rtvec (2, delay
,
4113 gen_rtx_RETURN (VOIDmode
)));
4114 insn
= emit_jump_insn (insn
);
4116 sparc_emitting_epilogue
= true;
4117 final_scan_insn (insn
, file
, 1, 0, 1);
4118 sparc_emitting_epilogue
= false;
4121 else if (TARGET_V9
&& ! SKIP_CALLERS_UNIMP_P
)
4122 fputs ("\treturn\t%i7+8\n\tnop\n", file
);
4124 fprintf (file
, "\t%s\n\trestore\n", ret
);
4126 /* All of the following cases are for leaf functions. */
4127 else if (current_function_calls_eh_return
)
4129 else if (current_function_epilogue_delay_list
)
4131 /* eligible_for_epilogue_delay_slot ensures that if this is a
4132 leaf function, then we will only have insn in the delay slot
4133 if the frame size is zero, thus no adjust for the stack is
4135 if (actual_fsize
!= 0)
4137 fprintf (file
, "\t%s\n", ret
);
4138 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4141 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4142 avoid generating confusing assembly language output. */
4143 else if (actual_fsize
== 0)
4144 fprintf (file
, "\t%s\n\tnop\n", ret
);
4145 else if (actual_fsize
<= 4096)
4146 fprintf (file
, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret
, actual_fsize
);
4147 else if (actual_fsize
<= 8192)
4148 fprintf (file
, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4149 ret
, actual_fsize
- 4096);
4150 else if ((actual_fsize
& 0x3ff) == 0)
4151 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4154 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4155 actual_fsize
, actual_fsize
, ret
);
4158 sparc_output_deferred_case_vectors ();
4161 /* Output a sibling call. */
4164 output_sibcall (insn
, call_operand
)
4165 rtx insn
, call_operand
;
4167 int leaf_regs
= current_function_uses_only_leaf_regs
;
4169 int delay_slot
= dbr_sequence_length () > 0;
4173 /* Call to restore global regs might clobber
4174 the delay slot. Instead of checking for this
4175 output the delay slot now. */
4178 rtx delay
= NEXT_INSN (insn
);
4183 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4184 PATTERN (delay
) = gen_blockage ();
4185 INSN_CODE (delay
) = -1;
4188 output_restore_regs (asm_out_file
, leaf_regs
);
4191 operands
[0] = call_operand
;
4195 #ifdef HAVE_AS_RELAX_OPTION
4196 /* If as and ld are relaxing tail call insns into branch always,
4197 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4198 be optimized. With sethi/jmpl as nor ld has no easy way how to
4199 find out if somebody does not branch between the sethi and jmpl. */
4202 int spare_slot
= ((TARGET_ARCH32
|| TARGET_CM_MEDLOW
) && ! flag_pic
);
4206 if ((actual_fsize
|| ! spare_slot
) && delay_slot
)
4208 rtx delay
= NEXT_INSN (insn
);
4213 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4214 PATTERN (delay
) = gen_blockage ();
4215 INSN_CODE (delay
) = -1;
4220 if (actual_fsize
<= 4096)
4221 size
= actual_fsize
;
4222 else if (actual_fsize
<= 8192)
4224 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file
);
4225 size
= actual_fsize
- 4096;
4227 else if ((actual_fsize
& 0x3ff) == 0)
4228 fprintf (asm_out_file
,
4229 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4233 fprintf (asm_out_file
,
4234 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4235 actual_fsize
, actual_fsize
);
4236 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file
);
4241 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands
);
4242 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands
);
4244 fprintf (asm_out_file
, "\t sub\t%%sp, -%d, %%sp\n", size
);
4245 else if (! delay_slot
)
4246 fputs ("\t nop\n", asm_out_file
);
4251 fprintf (asm_out_file
, "\tsub\t%%sp, -%d, %%sp\n", size
);
4252 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4253 it into branch if possible. */
4254 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands
);
4255 output_asm_insn ("call\t%a0, 0", operands
);
4256 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands
);
4261 output_asm_insn ("call\t%a0, 0", operands
);
4264 rtx delay
= NEXT_INSN (insn
), pat
;
4269 pat
= PATTERN (delay
);
4270 if (GET_CODE (pat
) != SET
)
4273 operands
[0] = SET_DEST (pat
);
4274 pat
= SET_SRC (pat
);
4275 switch (GET_CODE (pat
))
4278 operands
[1] = XEXP (pat
, 0);
4279 operands
[2] = XEXP (pat
, 1);
4280 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4283 operands
[1] = XEXP (pat
, 0);
4284 operands
[2] = XEXP (pat
, 1);
4285 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4288 operands
[1] = XEXP (pat
, 0);
4289 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4293 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4296 PATTERN (delay
) = gen_blockage ();
4297 INSN_CODE (delay
) = -1;
4300 fputs ("\t restore\n", asm_out_file
);
4304 /* Functions for handling argument passing.
4306 For v8 the first six args are normally in registers and the rest are
4307 pushed. Any arg that starts within the first 6 words is at least
4308 partially passed in a register unless its data type forbids.
4310 For v9, the argument registers are laid out as an array of 16 elements
4311 and arguments are added sequentially. The first 6 int args and up to the
4312 first 16 fp args (depending on size) are passed in regs.
4314 Slot Stack Integral Float Float in structure Double Long Double
4315 ---- ----- -------- ----- ------------------ ------ -----------
4316 15 [SP+248] %f31 %f30,%f31 %d30
4317 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4318 13 [SP+232] %f27 %f26,%f27 %d26
4319 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4320 11 [SP+216] %f23 %f22,%f23 %d22
4321 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4322 9 [SP+200] %f19 %f18,%f19 %d18
4323 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4324 7 [SP+184] %f15 %f14,%f15 %d14
4325 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4326 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4327 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4328 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4329 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4330 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4331 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4333 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4335 Integral arguments are always passed as 64 bit quantities appropriately
4338 Passing of floating point values is handled as follows.
4339 If a prototype is in scope:
4340 If the value is in a named argument (i.e. not a stdarg function or a
4341 value not part of the `...') then the value is passed in the appropriate
4343 If the value is part of the `...' and is passed in one of the first 6
4344 slots then the value is passed in the appropriate int reg.
4345 If the value is part of the `...' and is not passed in one of the first 6
4346 slots then the value is passed in memory.
4347 If a prototype is not in scope:
4348 If the value is one of the first 6 arguments the value is passed in the
4349 appropriate integer reg and the appropriate fp reg.
4350 If the value is not one of the first 6 arguments the value is passed in
4351 the appropriate fp reg and in memory.
4354 /* Maximum number of int regs for args. */
4355 #define SPARC_INT_ARG_MAX 6
4356 /* Maximum number of fp regs for args. */
4357 #define SPARC_FP_ARG_MAX 16
4359 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4361 /* Handle the INIT_CUMULATIVE_ARGS macro.
4362 Initialize a variable CUM of type CUMULATIVE_ARGS
4363 for a call to a function whose data type is FNTYPE.
4364 For a library call, FNTYPE is 0. */
4367 init_cumulative_args (cum
, fntype
, libname
, fndecl
)
4368 CUMULATIVE_ARGS
*cum
;
4370 rtx libname ATTRIBUTE_UNUSED
;
4371 tree fndecl ATTRIBUTE_UNUSED
;
4374 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4375 cum
->libcall_p
= fntype
== 0;
4378 /* Compute the slot number to pass an argument in.
4379 Returns the slot number or -1 if passing on the stack.
4381 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4382 the preceding args and about the function being called.
4383 MODE is the argument's machine mode.
4384 TYPE is the data type of the argument (as a tree).
4385 This is null for libcalls where that information may
4387 NAMED is nonzero if this argument is a named parameter
4388 (otherwise it is an extra parameter matching an ellipsis).
4389 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4390 *PREGNO records the register number to use if scalar type.
4391 *PPADDING records the amount of padding needed in words. */
4394 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
4395 const CUMULATIVE_ARGS
*cum
;
4396 enum machine_mode mode
;
4403 int regbase
= (incoming_p
4404 ? SPARC_INCOMING_INT_ARG_FIRST
4405 : SPARC_OUTGOING_INT_ARG_FIRST
);
4406 int slotno
= cum
->words
;
4411 if (type
!= 0 && TREE_ADDRESSABLE (type
))
4414 && type
!= 0 && mode
== BLKmode
4415 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4421 /* MODE is VOIDmode when generating the actual call.
4425 case QImode
: case CQImode
:
4426 case HImode
: case CHImode
:
4427 case SImode
: case CSImode
:
4428 case DImode
: case CDImode
:
4429 case TImode
: case CTImode
:
4430 if (slotno
>= SPARC_INT_ARG_MAX
)
4432 regno
= regbase
+ slotno
;
4435 case SFmode
: case SCmode
:
4436 case DFmode
: case DCmode
:
4437 case TFmode
: case TCmode
:
4440 if (slotno
>= SPARC_INT_ARG_MAX
)
4442 regno
= regbase
+ slotno
;
4446 if ((mode
== TFmode
|| mode
== TCmode
)
4447 && (slotno
& 1) != 0)
4448 slotno
++, *ppadding
= 1;
4449 if (TARGET_FPU
&& named
)
4451 if (slotno
>= SPARC_FP_ARG_MAX
)
4453 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
4459 if (slotno
>= SPARC_INT_ARG_MAX
)
4461 regno
= regbase
+ slotno
;
4467 /* For sparc64, objects requiring 16 byte alignment get it. */
4470 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
4471 slotno
++, *ppadding
= 1;
4475 || (type
&& TREE_CODE (type
) == UNION_TYPE
))
4477 if (slotno
>= SPARC_INT_ARG_MAX
)
4479 regno
= regbase
+ slotno
;
4484 int intregs_p
= 0, fpregs_p
= 0;
4485 /* The ABI obviously doesn't specify how packed
4486 structures are passed. These are defined to be passed
4487 in int regs if possible, otherwise memory. */
4490 /* First see what kinds of registers we need. */
4491 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4493 if (TREE_CODE (field
) == FIELD_DECL
)
4495 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4500 if (DECL_PACKED (field
))
4504 if (packed_p
|| !named
)
4505 fpregs_p
= 0, intregs_p
= 1;
4507 /* If all arg slots are filled, then must pass on stack. */
4508 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4510 /* If there are only int args and all int arg slots are filled,
4511 then must pass on stack. */
4512 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4514 /* Note that even if all int arg slots are filled, fp members may
4515 still be passed in regs if such regs are available.
4516 *PREGNO isn't set because there may be more than one, it's up
4517 to the caller to compute them. */
4530 /* Handle recursive register counting for structure field layout. */
4532 struct function_arg_record_value_parms
4534 rtx ret
; /* return expression being built. */
4535 int slotno
; /* slot number of the argument. */
4536 int named
; /* whether the argument is named. */
4537 int regbase
; /* regno of the base register. */
4538 int stack
; /* 1 if part of the argument is on the stack. */
4539 int intoffset
; /* offset of the pending integer field. */
4540 unsigned int nregs
; /* number of words passed in registers. */
4543 static void function_arg_record_value_3
4544 PARAMS ((HOST_WIDE_INT
, struct function_arg_record_value_parms
*));
4545 static void function_arg_record_value_2
4546 PARAMS ((tree
, HOST_WIDE_INT
,
4547 struct function_arg_record_value_parms
*));
4548 static void function_arg_record_value_1
4549 PARAMS ((tree
, HOST_WIDE_INT
,
4550 struct function_arg_record_value_parms
*));
4551 static rtx function_arg_record_value
4552 PARAMS ((tree
, enum machine_mode
, int, int, int));
4554 /* A subroutine of function_arg_record_value. Traverse the structure
4555 recursively and determine how many registers will be required. */
4558 function_arg_record_value_1 (type
, startbitpos
, parms
)
4560 HOST_WIDE_INT startbitpos
;
4561 struct function_arg_record_value_parms
*parms
;
4565 /* The ABI obviously doesn't specify how packed structures are
4566 passed. These are defined to be passed in int regs if possible,
4567 otherwise memory. */
4570 /* We need to compute how many registers are needed so we can
4571 allocate the PARALLEL but before we can do that we need to know
4572 whether there are any packed fields. If there are, int regs are
4573 used regardless of whether there are fp values present. */
4574 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4576 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4583 /* Compute how many registers we need. */
4584 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4586 if (TREE_CODE (field
) == FIELD_DECL
)
4588 HOST_WIDE_INT bitpos
= startbitpos
;
4590 if (DECL_SIZE (field
) != 0
4591 && host_integerp (bit_position (field
), 1))
4592 bitpos
+= int_bit_position (field
);
4594 /* ??? FIXME: else assume zero offset. */
4596 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4597 function_arg_record_value_1 (TREE_TYPE (field
), bitpos
, parms
);
4598 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4599 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4600 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4606 if (parms
->intoffset
!= -1)
4608 int intslots
, this_slotno
;
4610 intslots
= (bitpos
- parms
->intoffset
+ BITS_PER_WORD
- 1)
4612 this_slotno
= parms
->slotno
+ parms
->intoffset
4615 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
4617 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
4618 /* We need to pass this field on the stack. */
4622 parms
->nregs
+= intslots
;
4623 parms
->intoffset
= -1;
4626 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4627 If it wasn't true we wouldn't be here. */
4629 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4634 if (parms
->intoffset
== -1)
4635 parms
->intoffset
= bitpos
;
4641 /* A subroutine of function_arg_record_value. Assign the bits of the
4642 structure between parms->intoffset and bitpos to integer registers. */
4645 function_arg_record_value_3 (bitpos
, parms
)
4646 HOST_WIDE_INT bitpos
;
4647 struct function_arg_record_value_parms
*parms
;
4649 enum machine_mode mode
;
4651 unsigned int startbit
, endbit
;
4652 int this_slotno
, intslots
, intoffset
;
4655 if (parms
->intoffset
== -1)
4658 intoffset
= parms
->intoffset
;
4659 parms
->intoffset
= -1;
4661 startbit
= intoffset
& -BITS_PER_WORD
;
4662 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4663 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4664 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4666 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4670 /* If this is the trailing part of a word, only load that much into
4671 the register. Otherwise load the whole register. Note that in
4672 the latter case we may pick up unwanted bits. It's not a problem
4673 at the moment but may wish to revisit. */
4675 if (intoffset
% BITS_PER_WORD
!= 0)
4676 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4681 intoffset
/= BITS_PER_UNIT
;
4684 regno
= parms
->regbase
+ this_slotno
;
4685 reg
= gen_rtx_REG (mode
, regno
);
4686 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4687 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4690 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4694 while (intslots
> 0);
4697 /* A subroutine of function_arg_record_value. Traverse the structure
4698 recursively and assign bits to floating point registers. Track which
4699 bits in between need integer registers; invoke function_arg_record_value_3
4700 to make that happen. */
4703 function_arg_record_value_2 (type
, startbitpos
, parms
)
4705 HOST_WIDE_INT startbitpos
;
4706 struct function_arg_record_value_parms
*parms
;
4711 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4713 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4720 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4722 if (TREE_CODE (field
) == FIELD_DECL
)
4724 HOST_WIDE_INT bitpos
= startbitpos
;
4726 if (DECL_SIZE (field
) != 0
4727 && host_integerp (bit_position (field
), 1))
4728 bitpos
+= int_bit_position (field
);
4730 /* ??? FIXME: else assume zero offset. */
4732 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4733 function_arg_record_value_2 (TREE_TYPE (field
), bitpos
, parms
);
4734 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4735 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4736 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4742 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
4744 enum machine_mode mode
= DECL_MODE (field
);
4747 function_arg_record_value_3 (bitpos
, parms
);
4748 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2
4749 + ((mode
== SFmode
|| mode
== SCmode
)
4750 && (bitpos
& 32) != 0);
4753 case SCmode
: mode
= SFmode
; break;
4754 case DCmode
: mode
= DFmode
; break;
4755 case TCmode
: mode
= TFmode
; break;
4758 reg
= gen_rtx_REG (mode
, regno
);
4759 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4760 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4761 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4763 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4765 regno
+= GET_MODE_SIZE (mode
) / 4;
4766 reg
= gen_rtx_REG (mode
, regno
);
4767 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4768 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4769 GEN_INT ((bitpos
+ GET_MODE_BITSIZE (mode
))
4776 if (parms
->intoffset
== -1)
4777 parms
->intoffset
= bitpos
;
4783 /* Used by function_arg and function_value to implement the complex
4784 conventions of the 64-bit ABI for passing and returning structures.
4785 Return an expression valid as a return value for the two macros
4786 FUNCTION_ARG and FUNCTION_VALUE.
4788 TYPE is the data type of the argument (as a tree).
4789 This is null for libcalls where that information may
4791 MODE is the argument's machine mode.
4792 SLOTNO is the index number of the argument's slot in the parameter array.
4793 NAMED is nonzero if this argument is a named parameter
4794 (otherwise it is an extra parameter matching an ellipsis).
4795 REGBASE is the regno of the base register for the parameter array. */
4798 function_arg_record_value (type
, mode
, slotno
, named
, regbase
)
4800 enum machine_mode mode
;
4801 int slotno
, named
, regbase
;
4803 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4804 struct function_arg_record_value_parms parms
;
4807 parms
.ret
= NULL_RTX
;
4808 parms
.slotno
= slotno
;
4809 parms
.named
= named
;
4810 parms
.regbase
= regbase
;
4813 /* Compute how many registers we need. */
4815 parms
.intoffset
= 0;
4816 function_arg_record_value_1 (type
, 0, &parms
);
4818 if (parms
.intoffset
!= -1)
4820 unsigned int startbit
, endbit
;
4821 int intslots
, this_slotno
;
4823 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
4824 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4825 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4826 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
4828 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
4830 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
4831 /* We need to pass this field on the stack. */
4835 parms
.nregs
+= intslots
;
4837 nregs
= parms
.nregs
;
4839 /* Allocate the vector and handle some annoying special cases. */
4842 /* ??? Empty structure has no value? Duh? */
4845 /* Though there's nothing really to store, return a word register
4846 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4847 leads to breakage due to the fact that there are zero bytes to
4849 return gen_rtx_REG (mode
, regbase
);
4853 /* ??? C++ has structures with no fields, and yet a size. Give up
4854 for now and pass everything back in integer registers. */
4855 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4857 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
4858 nregs
= SPARC_INT_ARG_MAX
- slotno
;
4863 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
4865 /* If at least one field must be passed on the stack, generate
4866 (parallel [(expr_list (nil) ...) ...]) so that all fields will
4867 also be passed on the stack. We can't do much better because the
4868 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
4869 of structures for which the fields passed exclusively in registers
4870 are not at the beginning of the structure. */
4872 XVECEXP (parms
.ret
, 0, 0)
4873 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4875 /* Fill in the entries. */
4877 parms
.intoffset
= 0;
4878 function_arg_record_value_2 (type
, 0, &parms
);
4879 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
4881 if (parms
.nregs
!= nregs
)
4887 /* Handle the FUNCTION_ARG macro.
4888 Determine where to put an argument to a function.
4889 Value is zero to push the argument on the stack,
4890 or a hard register in which to store the argument.
4892 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4893 the preceding args and about the function being called.
4894 MODE is the argument's machine mode.
4895 TYPE is the data type of the argument (as a tree).
4896 This is null for libcalls where that information may
4898 NAMED is nonzero if this argument is a named parameter
4899 (otherwise it is an extra parameter matching an ellipsis).
4900 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4903 function_arg (cum
, mode
, type
, named
, incoming_p
)
4904 const CUMULATIVE_ARGS
*cum
;
4905 enum machine_mode mode
;
4910 int regbase
= (incoming_p
4911 ? SPARC_INCOMING_INT_ARG_FIRST
4912 : SPARC_OUTGOING_INT_ARG_FIRST
);
4913 int slotno
, regno
, padding
;
4916 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
4924 reg
= gen_rtx_REG (mode
, regno
);
4928 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4929 but also have the slot allocated for them.
4930 If no prototype is in scope fp values in register slots get passed
4931 in two places, either fp regs and int regs or fp regs and memory. */
4932 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4933 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4934 && SPARC_FP_REG_P (regno
))
4936 reg
= gen_rtx_REG (mode
, regno
);
4937 if (cum
->prototype_p
|| cum
->libcall_p
)
4939 /* "* 2" because fp reg numbers are recorded in 4 byte
4942 /* ??? This will cause the value to be passed in the fp reg and
4943 in the stack. When a prototype exists we want to pass the
4944 value in the reg but reserve space on the stack. That's an
4945 optimization, and is deferred [for a bit]. */
4946 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
4947 return gen_rtx_PARALLEL (mode
,
4949 gen_rtx_EXPR_LIST (VOIDmode
,
4950 NULL_RTX
, const0_rtx
),
4951 gen_rtx_EXPR_LIST (VOIDmode
,
4955 /* ??? It seems that passing back a register even when past
4956 the area declared by REG_PARM_STACK_SPACE will allocate
4957 space appropriately, and will not copy the data onto the
4958 stack, exactly as we desire.
4960 This is due to locate_and_pad_parm being called in
4961 expand_call whenever reg_parm_stack_space > 0, which
4962 while beneficial to our example here, would seem to be
4963 in error from what had been intended. Ho hum... -- r~ */
4971 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
4975 /* On incoming, we don't need to know that the value
4976 is passed in %f0 and %i0, and it confuses other parts
4977 causing needless spillage even on the simplest cases. */
4981 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
4982 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
4984 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4985 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
4987 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4991 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4992 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4993 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4997 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
4999 /* Structures up to 16 bytes in size are passed in arg slots on the
5000 stack and are promoted to registers where possible. */
5002 if (int_size_in_bytes (type
) > 16)
5003 abort (); /* shouldn't get here */
5005 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
5007 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
5009 enum machine_mode mode
;
5010 int bytes
= int_size_in_bytes (type
);
5015 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5016 reg
= gen_rtx_REG (mode
, regno
);
5020 /* Scalar or complex int. */
5021 reg
= gen_rtx_REG (mode
, regno
);
5027 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5028 For an arg passed partly in registers and partly in memory,
5029 this is the number of registers used.
5030 For args passed entirely in registers or entirely in memory, zero.
5032 Any arg that starts in the first 6 regs but won't entirely fit in them
5033 needs partial registers on v8. On v9, structures with integer
5034 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5035 values that begin in the last fp reg [where "last fp reg" varies with the
5036 mode] will be split between that reg and memory. */
5039 function_arg_partial_nregs (cum
, mode
, type
, named
)
5040 const CUMULATIVE_ARGS
*cum
;
5041 enum machine_mode mode
;
5045 int slotno
, regno
, padding
;
5047 /* We pass 0 for incoming_p here, it doesn't matter. */
5048 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5055 if ((slotno
+ (mode
== BLKmode
5056 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5057 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5058 > NPARM_REGS (SImode
))
5059 return NPARM_REGS (SImode
) - slotno
;
5064 if (type
&& AGGREGATE_TYPE_P (type
))
5066 int size
= int_size_in_bytes (type
);
5067 int align
= TYPE_ALIGN (type
);
5070 slotno
+= slotno
& 1;
5071 if (size
> 8 && size
<= 16
5072 && slotno
== SPARC_INT_ARG_MAX
- 1)
5075 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5076 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5077 && ! (TARGET_FPU
&& named
)))
5079 if (GET_MODE_ALIGNMENT (mode
) == 128)
5081 slotno
+= slotno
& 1;
5082 if (slotno
== SPARC_INT_ARG_MAX
- 2)
5087 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5091 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5093 if (GET_MODE_ALIGNMENT (mode
) == 128)
5094 slotno
+= slotno
& 1;
5095 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5103 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5104 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5105 quad-precision floats by invisible reference.
5106 v9: Aggregates greater than 16 bytes are passed by reference.
5107 For Pascal, also pass arrays by reference. */
5110 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5111 const CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
5112 enum machine_mode mode
;
5114 int named ATTRIBUTE_UNUSED
;
5118 return ((type
&& AGGREGATE_TYPE_P (type
))
5119 || mode
== TFmode
|| mode
== TCmode
);
5123 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5124 /* Consider complex values as aggregates, so care for TCmode. */
5125 || GET_MODE_SIZE (mode
) > 16
5127 && AGGREGATE_TYPE_P (type
)
5128 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16));
5132 /* Handle the FUNCTION_ARG_ADVANCE macro.
5133 Update the data in CUM to advance over an argument
5134 of mode MODE and data type TYPE.
5135 TYPE is null for libcalls where that information may not be available. */
5138 function_arg_advance (cum
, mode
, type
, named
)
5139 CUMULATIVE_ARGS
*cum
;
5140 enum machine_mode mode
;
5144 int slotno
, regno
, padding
;
5146 /* We pass 0 for incoming_p here, it doesn't matter. */
5147 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5149 /* If register required leading padding, add it. */
5151 cum
->words
+= padding
;
5155 cum
->words
+= (mode
!= BLKmode
5156 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5157 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5161 if (type
&& AGGREGATE_TYPE_P (type
))
5163 int size
= int_size_in_bytes (type
);
5167 else if (size
<= 16)
5169 else /* passed by reference */
5172 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
5176 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5178 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
5182 cum
->words
+= (mode
!= BLKmode
5183 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5184 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5189 /* Handle the FUNCTION_ARG_PADDING macro.
5190 For the 64 bit ABI structs are always stored left shifted in their
5194 function_arg_padding (mode
, type
)
5195 enum machine_mode mode
;
5198 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5201 /* This is the default definition. */
5202 return (! BYTES_BIG_ENDIAN
5205 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
5206 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
5207 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
5208 ? downward
: upward
));
5211 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5212 For v9, function return values are subject to the same rules as arguments,
5213 except that up to 32-bytes may be returned in registers. */
5216 function_value (type
, mode
, incoming_p
)
5218 enum machine_mode mode
;
5222 int regbase
= (incoming_p
5223 ? SPARC_OUTGOING_INT_ARG_FIRST
5224 : SPARC_INCOMING_INT_ARG_FIRST
);
5226 if (TARGET_ARCH64
&& type
)
5228 if (TREE_CODE (type
) == RECORD_TYPE
)
5230 /* Structures up to 32 bytes in size are passed in registers,
5231 promoted to fp registers where possible. */
5233 if (int_size_in_bytes (type
) > 32)
5234 abort (); /* shouldn't get here */
5236 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5238 else if (AGGREGATE_TYPE_P (type
))
5240 /* All other aggregate types are passed in an integer register
5241 in a mode corresponding to the size of the type. */
5242 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
5247 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5252 && GET_MODE_CLASS (mode
) == MODE_INT
5253 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5254 && type
&& ! AGGREGATE_TYPE_P (type
))
5258 regno
= BASE_RETURN_VALUE_REG (mode
);
5260 regno
= BASE_OUTGOING_VALUE_REG (mode
);
5262 return gen_rtx_REG (mode
, regno
);
5265 /* Do what is necessary for `va_start'. We look at the current function
5266 to determine if stdarg or varargs is used and return the address of
5267 the first unnamed parameter. */
5270 sparc_builtin_saveregs ()
5272 int first_reg
= current_function_args_info
.words
;
5276 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
5277 emit_move_insn (gen_rtx_MEM (word_mode
,
5278 gen_rtx_PLUS (Pmode
,
5280 GEN_INT (FIRST_PARM_OFFSET (0)
5283 gen_rtx_REG (word_mode
,
5284 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
5286 address
= gen_rtx_PLUS (Pmode
,
5288 GEN_INT (FIRST_PARM_OFFSET (0)
5289 + UNITS_PER_WORD
* first_reg
));
5294 /* Implement `va_start' for varargs and stdarg. */
5297 sparc_va_start (valist
, nextarg
)
5301 nextarg
= expand_builtin_saveregs ();
5302 std_expand_builtin_va_start (valist
, nextarg
);
5305 /* Implement `va_arg'. */
5308 sparc_va_arg (valist
, type
)
5311 HOST_WIDE_INT size
, rsize
, align
;
5316 /* Round up sizeof(type) to a word. */
5317 size
= int_size_in_bytes (type
);
5318 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5323 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5324 align
= 2 * UNITS_PER_WORD
;
5326 if (AGGREGATE_TYPE_P (type
))
5328 if ((unsigned HOST_WIDE_INT
) size
> 16)
5331 size
= rsize
= UNITS_PER_WORD
;
5334 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5335 given one 8 byte slot. */
5337 size
= rsize
= UNITS_PER_WORD
;
5344 if (AGGREGATE_TYPE_P (type
)
5345 || TYPE_MODE (type
) == TFmode
5346 || TYPE_MODE (type
) == TCmode
)
5349 size
= rsize
= UNITS_PER_WORD
;
5356 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5357 build_int_2 (align
- 1, 0)));
5358 incr
= fold (build (BIT_AND_EXPR
, ptr_type_node
, incr
,
5359 build_int_2 (-align
, -1)));
5362 addr
= incr
= save_expr (incr
);
5363 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5365 addr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5366 build_int_2 (rsize
- size
, 0)));
5368 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5369 build_int_2 (rsize
, 0)));
5371 incr
= build (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
5372 TREE_SIDE_EFFECTS (incr
) = 1;
5373 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5375 addr_rtx
= expand_expr (addr
, NULL
, Pmode
, EXPAND_NORMAL
);
5377 /* If the address isn't aligned properly for the type,
5378 we may need to copy to a temporary.
5379 FIXME: This is inefficient. Usually we can do this
5382 && TYPE_ALIGN (type
) > BITS_PER_WORD
5385 /* FIXME: We really need to specify that the temporary is live
5386 for the whole function because expand_builtin_va_arg wants
5387 the alias set to be get_varargs_alias_set (), but in this
5388 case the alias set is that for TYPE and if the memory gets
5389 reused it will be reused with alias set TYPE. */
5390 rtx tmp
= assign_temp (type
, 0, 1, 0);
5393 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5394 addr_rtx
= gen_rtx_MEM (BLKmode
, addr_rtx
);
5395 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5396 set_mem_align (addr_rtx
, BITS_PER_WORD
);
5397 tmp
= shallow_copy_rtx (tmp
);
5398 PUT_MODE (tmp
, BLKmode
);
5399 set_mem_alias_set (tmp
, 0);
5401 dest_addr
= emit_block_move (tmp
, addr_rtx
, GEN_INT (rsize
),
5403 if (dest_addr
!= NULL_RTX
)
5404 addr_rtx
= dest_addr
;
5406 addr_rtx
= XCEXP (tmp
, 0, MEM
);
5411 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5412 addr_rtx
= gen_rtx_MEM (Pmode
, addr_rtx
);
5413 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5419 /* Return the string to output a conditional branch to LABEL, which is
5420 the operand number of the label. OP is the conditional expression.
5421 XEXP (OP, 0) is assumed to be a condition code register (integer or
5422 floating point) and its mode specifies what kind of comparison we made.
5424 REVERSED is nonzero if we should reverse the sense of the comparison.
5426 ANNUL is nonzero if we should generate an annulling branch.
5428 NOOP is nonzero if we have to follow this branch by a noop.
5430 INSN, if set, is the insn. */
5433 output_cbranch (op
, dest
, label
, reversed
, annul
, noop
, insn
)
5436 int reversed
, annul
, noop
;
5439 static char string
[50];
5440 enum rtx_code code
= GET_CODE (op
);
5441 rtx cc_reg
= XEXP (op
, 0);
5442 enum machine_mode mode
= GET_MODE (cc_reg
);
5443 const char *labelno
, *branch
;
5444 int spaces
= 8, far
;
5447 /* v9 branches are limited to +-1MB. If it is too far away,
5460 fbne,a,pn %fcc2, .LC29
5468 far
= get_attr_length (insn
) >= 3;
5471 /* Reversal of FP compares takes care -- an ordered compare
5472 becomes an unordered compare and vice versa. */
5473 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5474 code
= reverse_condition_maybe_unordered (code
);
5476 code
= reverse_condition (code
);
5479 /* Start by writing the branch condition. */
5480 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5531 /* ??? !v9: FP branches cannot be preceded by another floating point
5532 insn. Because there is currently no concept of pre-delay slots,
5533 we can fix this only by always emitting a nop before a floating
5538 strcpy (string
, "nop\n\t");
5539 strcat (string
, branch
);
5552 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5564 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5585 strcpy (string
, branch
);
5587 spaces
-= strlen (branch
);
5588 p
= strchr (string
, '\0');
5590 /* Now add the annulling, the label, and a possible noop. */
5605 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
5607 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5608 - INSN_ADDRESSES (INSN_UID (insn
)));
5609 /* Leave some instructions for "slop". */
5610 if (delta
< -260000 || delta
>= 260000)
5614 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5616 static char v9_fcc_labelno
[] = "%%fccX, ";
5617 /* Set the char indicating the number of the fcc reg to use. */
5618 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
5619 labelno
= v9_fcc_labelno
;
5622 if (REGNO (cc_reg
) == SPARC_FCC_REG
)
5628 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
5630 labelno
= "%%xcc, ";
5636 labelno
= "%%icc, ";
5641 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5644 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5654 strcpy (p
, labelno
);
5655 p
= strchr (p
, '\0');
5658 strcpy (p
, ".+12\n\tnop\n\tb\t");
5665 /* Set the char indicating the number of the operand containing the
5670 strcpy (p
, "\n\tnop");
5675 /* Emit a library call comparison between floating point X and Y.
5676 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5677 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5678 values as arguments instead of the TFmode registers themselves,
5679 that's why we cannot call emit_float_lib_cmp. */
5681 sparc_emit_float_lib_cmp (x
, y
, comparison
)
5683 enum rtx_code comparison
;
5686 rtx slot0
, slot1
, result
, tem
, tem2
;
5687 enum machine_mode mode
;
5692 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
5696 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
5700 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
5704 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
5708 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
5712 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
5723 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
5733 if (GET_CODE (x
) != MEM
)
5735 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5736 emit_insn (gen_rtx_SET (VOIDmode
, slot0
, x
));
5741 if (GET_CODE (y
) != MEM
)
5743 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5744 emit_insn (gen_rtx_SET (VOIDmode
, slot1
, y
));
5749 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5751 XEXP (slot0
, 0), Pmode
,
5752 XEXP (slot1
, 0), Pmode
);
5758 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5760 x
, TFmode
, y
, TFmode
);
5766 /* Immediately move the result of the libcall into a pseudo
5767 register so reload doesn't clobber the value if it needs
5768 the return register for a spill reg. */
5769 result
= gen_reg_rtx (mode
);
5770 emit_move_insn (result
, hard_libcall_value (mode
));
5775 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5779 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
5784 emit_cmp_insn (result
, const1_rtx
,
5785 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
5788 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
5791 tem
= gen_reg_rtx (mode
);
5793 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
5795 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
5796 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5800 tem
= gen_reg_rtx (mode
);
5802 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
5804 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
5805 tem2
= gen_reg_rtx (mode
);
5807 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
5809 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
5810 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
5816 /* Generate an unsigned DImode to FP conversion. This is the same code
5817 optabs would emit if we didn't have TFmode patterns. */
5820 sparc_emit_floatunsdi (operands
)
5823 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
5824 enum machine_mode mode
;
5827 in
= force_reg (DImode
, operands
[1]);
5828 mode
= GET_MODE (out
);
5829 neglab
= gen_label_rtx ();
5830 donelab
= gen_label_rtx ();
5831 i0
= gen_reg_rtx (DImode
);
5832 i1
= gen_reg_rtx (DImode
);
5833 f0
= gen_reg_rtx (mode
);
5835 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
5837 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
5838 emit_jump_insn (gen_jump (donelab
));
5841 emit_label (neglab
);
5843 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
5844 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
5845 emit_insn (gen_iordi3 (i0
, i0
, i1
));
5846 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
5847 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
5849 emit_label (donelab
);
5852 /* Return the string to output a conditional branch to LABEL, testing
5853 register REG. LABEL is the operand number of the label; REG is the
5854 operand number of the reg. OP is the conditional expression. The mode
5855 of REG says what kind of comparison we made.
5857 REVERSED is nonzero if we should reverse the sense of the comparison.
5859 ANNUL is nonzero if we should generate an annulling branch.
5861 NOOP is nonzero if we have to follow this branch by a noop. */
5864 output_v9branch (op
, dest
, reg
, label
, reversed
, annul
, noop
, insn
)
5867 int reversed
, annul
, noop
;
5870 static char string
[50];
5871 enum rtx_code code
= GET_CODE (op
);
5872 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
5877 /* branch on register are limited to +-128KB. If it is too far away,
5890 brgez,a,pn %o1, .LC29
5896 ba,pt %xcc, .LC29 */
5898 far
= get_attr_length (insn
) >= 3;
5900 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5902 code
= reverse_condition (code
);
5904 /* Only 64 bit versions of these instructions exist. */
5908 /* Start by writing the branch condition. */
5913 strcpy (string
, "brnz");
5917 strcpy (string
, "brz");
5921 strcpy (string
, "brgez");
5925 strcpy (string
, "brlz");
5929 strcpy (string
, "brlez");
5933 strcpy (string
, "brgz");
5940 p
= strchr (string
, '\0');
5942 /* Now add the annulling, reg, label, and nop. */
5949 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5952 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5957 *p
= p
< string
+ 8 ? '\t' : ' ';
5965 int veryfar
= 1, delta
;
5967 if (INSN_ADDRESSES_SET_P ())
5969 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5970 - INSN_ADDRESSES (INSN_UID (insn
)));
5971 /* Leave some instructions for "slop". */
5972 if (delta
>= -260000 && delta
< 260000)
5976 strcpy (p
, ".+12\n\tnop\n\t");
5987 strcpy (p
, "ba,pt\t%%xcc, ");
5997 strcpy (p
, "\n\tnop");
6002 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6003 Such instructions cannot be used in the delay slot of return insn on v9.
6004 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6008 epilogue_renumber (where
, test
)
6009 register rtx
*where
;
6012 register const char *fmt
;
6014 register enum rtx_code code
;
6019 code
= GET_CODE (*where
);
6024 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
6026 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
6027 *where
= gen_rtx (REG
, GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
6035 /* Do not replace the frame pointer with the stack pointer because
6036 it can cause the delayed instruction to load below the stack.
6037 This occurs when instructions like:
6039 (set (reg/i:SI 24 %i0)
6040 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6041 (const_int -20 [0xffffffec])) 0))
6043 are in the return delayed slot. */
6045 if (GET_CODE (XEXP (*where
, 0)) == REG
6046 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
6047 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
6048 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
6053 if (SPARC_STACK_BIAS
6054 && GET_CODE (XEXP (*where
, 0)) == REG
6055 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6063 fmt
= GET_RTX_FORMAT (code
);
6065 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6070 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6071 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6074 else if (fmt
[i
] == 'e'
6075 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6081 /* Leaf functions and non-leaf functions have different needs. */
6084 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6087 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6089 static const int *const reg_alloc_orders
[] = {
6090 reg_leaf_alloc_order
,
6091 reg_nonleaf_alloc_order
};
6094 order_regs_for_local_alloc ()
6096 static int last_order_nonleaf
= 1;
6098 if (regs_ever_live
[15] != last_order_nonleaf
)
6100 last_order_nonleaf
= !last_order_nonleaf
;
6101 memcpy ((char *) reg_alloc_order
,
6102 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6103 FIRST_PSEUDO_REGISTER
* sizeof (int));
6107 /* Return 1 if REG and MEM are legitimate enough to allow the various
6108 mem<-->reg splits to be run. */
6111 sparc_splitdi_legitimate (reg
, mem
)
6115 /* Punt if we are here by mistake. */
6116 if (! reload_completed
)
6119 /* We must have an offsettable memory reference. */
6120 if (! offsettable_memref_p (mem
))
6123 /* If we have legitimate args for ldd/std, we do not want
6124 the split to happen. */
6125 if ((REGNO (reg
) % 2) == 0
6126 && mem_min_alignment (mem
, 8))
6133 /* Return 1 if x and y are some kind of REG and they refer to
6134 different hard registers. This test is guaranteed to be
6135 run after reload. */
6138 sparc_absnegfloat_split_legitimate (x
, y
)
6141 if (GET_CODE (x
) != REG
)
6143 if (GET_CODE (y
) != REG
)
6145 if (REGNO (x
) == REGNO (y
))
6150 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6151 This makes them candidates for using ldd and std insns.
6153 Note reg1 and reg2 *must* be hard registers. */
6156 registers_ok_for_ldd_peep (reg1
, reg2
)
6159 /* We might have been passed a SUBREG. */
6160 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6163 if (REGNO (reg1
) % 2 != 0)
6166 /* Integer ldd is deprecated in SPARC V9 */
6167 if (TARGET_V9
&& REGNO (reg1
) < 32)
6170 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6173 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6176 This can only happen when addr1 and addr2, the addresses in mem1
6177 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6178 addr1 must also be aligned on a 64-bit boundary.
6180 Also iff dependent_reg_rtx is not null it should not be used to
6181 compute the address for mem1, i.e. we cannot optimize a sequence
6193 But, note that the transformation from:
6198 is perfectly fine. Thus, the peephole2 patterns always pass us
6199 the destination register of the first load, never the second one.
6201 For stores we don't have a similar problem, so dependent_reg_rtx is
6205 mems_ok_for_ldd_peep (mem1
, mem2
, dependent_reg_rtx
)
6206 rtx mem1
, mem2
, dependent_reg_rtx
;
6212 /* The mems cannot be volatile. */
6213 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6216 /* MEM1 should be aligned on a 64-bit boundary. */
6217 if (MEM_ALIGN (mem1
) < 64)
6220 addr1
= XEXP (mem1
, 0);
6221 addr2
= XEXP (mem2
, 0);
6223 /* Extract a register number and offset (if used) from the first addr. */
6224 if (GET_CODE (addr1
) == PLUS
)
6226 /* If not a REG, return zero. */
6227 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6231 reg1
= REGNO (XEXP (addr1
, 0));
6232 /* The offset must be constant! */
6233 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6235 offset1
= INTVAL (XEXP (addr1
, 1));
6238 else if (GET_CODE (addr1
) != REG
)
6242 reg1
= REGNO (addr1
);
6243 /* This was a simple (mem (reg)) expression. Offset is 0. */
6247 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6248 if (GET_CODE (addr2
) != PLUS
)
6251 if (GET_CODE (XEXP (addr2
, 0)) != REG
6252 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6255 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6258 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6261 /* The first offset must be evenly divisible by 8 to ensure the
6262 address is 64 bit aligned. */
6263 if (offset1
% 8 != 0)
6266 /* The offset for the second addr must be 4 more than the first addr. */
6267 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6270 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6275 /* Return 1 if reg is a pseudo, or is the first register in
6276 a hard register pair. This makes it a candidate for use in
6277 ldd and std insns. */
6280 register_ok_for_ldd (reg
)
6283 /* We might have been passed a SUBREG. */
6284 if (GET_CODE (reg
) != REG
)
6287 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6288 return (REGNO (reg
) % 2 == 0);
6293 /* Print operand X (an rtx) in assembler syntax to file FILE.
6294 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6295 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6298 print_operand (file
, x
, code
)
6306 /* Output a 'nop' if there's nothing for the delay slot. */
6307 if (dbr_sequence_length () == 0)
6308 fputs ("\n\t nop", file
);
6311 /* Output an annul flag if there's nothing for the delay slot and we
6312 are optimizing. This is always used with '(' below. */
6313 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6314 this is a dbx bug. So, we only do this when optimizing. */
6315 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6316 Always emit a nop in case the next instruction is a branch. */
6317 if (dbr_sequence_length () == 0
6318 && (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6322 /* Output a 'nop' if there's nothing for the delay slot and we are
6323 not optimizing. This is always used with '*' above. */
6324 if (dbr_sequence_length () == 0
6325 && ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6326 fputs ("\n\t nop", file
);
6329 /* Output the Embedded Medium/Anywhere code model base register. */
6330 fputs (EMBMEDANY_BASE_REG
, file
);
6333 /* Print out what we are using as the frame pointer. This might
6334 be %fp, or might be %sp+offset. */
6335 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6336 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
6339 /* Adjust the operand to take into account a RESTORE operation. */
6340 if (GET_CODE (x
) == CONST_INT
)
6342 else if (GET_CODE (x
) != REG
)
6343 output_operand_lossage ("invalid %%Y operand");
6344 else if (REGNO (x
) < 8)
6345 fputs (reg_names
[REGNO (x
)], file
);
6346 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6347 fputs (reg_names
[REGNO (x
)-16], file
);
6349 output_operand_lossage ("invalid %%Y operand");
6352 /* Print out the low order register name of a register pair. */
6353 if (WORDS_BIG_ENDIAN
)
6354 fputs (reg_names
[REGNO (x
)+1], file
);
6356 fputs (reg_names
[REGNO (x
)], file
);
6359 /* Print out the high order register name of a register pair. */
6360 if (WORDS_BIG_ENDIAN
)
6361 fputs (reg_names
[REGNO (x
)], file
);
6363 fputs (reg_names
[REGNO (x
)+1], file
);
6366 /* Print out the second register name of a register pair or quad.
6367 I.e., R (%o0) => %o1. */
6368 fputs (reg_names
[REGNO (x
)+1], file
);
6371 /* Print out the third register name of a register quad.
6372 I.e., S (%o0) => %o2. */
6373 fputs (reg_names
[REGNO (x
)+2], file
);
6376 /* Print out the fourth register name of a register quad.
6377 I.e., T (%o0) => %o3. */
6378 fputs (reg_names
[REGNO (x
)+3], file
);
6381 /* Print a condition code register. */
6382 if (REGNO (x
) == SPARC_ICC_REG
)
6384 /* We don't handle CC[X]_NOOVmode because they're not supposed
6386 if (GET_MODE (x
) == CCmode
)
6387 fputs ("%icc", file
);
6388 else if (GET_MODE (x
) == CCXmode
)
6389 fputs ("%xcc", file
);
6394 /* %fccN register */
6395 fputs (reg_names
[REGNO (x
)], file
);
6398 /* Print the operand's address only. */
6399 output_address (XEXP (x
, 0));
6402 /* In this case we need a register. Use %g0 if the
6403 operand is const0_rtx. */
6405 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
6407 fputs ("%g0", file
);
6414 switch (GET_CODE (x
))
6416 case IOR
: fputs ("or", file
); break;
6417 case AND
: fputs ("and", file
); break;
6418 case XOR
: fputs ("xor", file
); break;
6419 default: output_operand_lossage ("invalid %%A operand");
6424 switch (GET_CODE (x
))
6426 case IOR
: fputs ("orn", file
); break;
6427 case AND
: fputs ("andn", file
); break;
6428 case XOR
: fputs ("xnor", file
); break;
6429 default: output_operand_lossage ("invalid %%B operand");
6433 /* These are used by the conditional move instructions. */
6437 enum rtx_code rc
= GET_CODE (x
);
6441 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
6442 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6443 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
6445 rc
= reverse_condition (GET_CODE (x
));
6449 case NE
: fputs ("ne", file
); break;
6450 case EQ
: fputs ("e", file
); break;
6451 case GE
: fputs ("ge", file
); break;
6452 case GT
: fputs ("g", file
); break;
6453 case LE
: fputs ("le", file
); break;
6454 case LT
: fputs ("l", file
); break;
6455 case GEU
: fputs ("geu", file
); break;
6456 case GTU
: fputs ("gu", file
); break;
6457 case LEU
: fputs ("leu", file
); break;
6458 case LTU
: fputs ("lu", file
); break;
6459 case LTGT
: fputs ("lg", file
); break;
6460 case UNORDERED
: fputs ("u", file
); break;
6461 case ORDERED
: fputs ("o", file
); break;
6462 case UNLT
: fputs ("ul", file
); break;
6463 case UNLE
: fputs ("ule", file
); break;
6464 case UNGT
: fputs ("ug", file
); break;
6465 case UNGE
: fputs ("uge", file
); break;
6466 case UNEQ
: fputs ("ue", file
); break;
6467 default: output_operand_lossage (code
== 'c'
6468 ? "invalid %%c operand"
6469 : "invalid %%C operand");
6474 /* These are used by the movr instruction pattern. */
6478 enum rtx_code rc
= (code
== 'd'
6479 ? reverse_condition (GET_CODE (x
))
6483 case NE
: fputs ("ne", file
); break;
6484 case EQ
: fputs ("e", file
); break;
6485 case GE
: fputs ("gez", file
); break;
6486 case LT
: fputs ("lz", file
); break;
6487 case LE
: fputs ("lez", file
); break;
6488 case GT
: fputs ("gz", file
); break;
6489 default: output_operand_lossage (code
== 'd'
6490 ? "invalid %%d operand"
6491 : "invalid %%D operand");
6498 /* Print a sign-extended character. */
6499 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
6500 fprintf (file
, "%d", i
);
6505 /* Operand must be a MEM; write its address. */
6506 if (GET_CODE (x
) != MEM
)
6507 output_operand_lossage ("invalid %%f operand");
6508 output_address (XEXP (x
, 0));
6513 /* Print a sign-extended 32-bit value. */
6515 if (GET_CODE(x
) == CONST_INT
)
6517 else if (GET_CODE(x
) == CONST_DOUBLE
)
6518 i
= CONST_DOUBLE_LOW (x
);
6521 output_operand_lossage ("invalid %%s operand");
6524 i
= trunc_int_for_mode (i
, SImode
);
6525 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
6530 /* Do nothing special. */
6534 /* Undocumented flag. */
6535 output_operand_lossage ("invalid operand output code");
6538 if (GET_CODE (x
) == REG
)
6539 fputs (reg_names
[REGNO (x
)], file
);
6540 else if (GET_CODE (x
) == MEM
)
6543 /* Poor Sun assembler doesn't understand absolute addressing. */
6544 if (CONSTANT_P (XEXP (x
, 0)))
6545 fputs ("%g0+", file
);
6546 output_address (XEXP (x
, 0));
6549 else if (GET_CODE (x
) == HIGH
)
6551 fputs ("%hi(", file
);
6552 output_addr_const (file
, XEXP (x
, 0));
6555 else if (GET_CODE (x
) == LO_SUM
)
6557 print_operand (file
, XEXP (x
, 0), 0);
6558 if (TARGET_CM_MEDMID
)
6559 fputs ("+%l44(", file
);
6561 fputs ("+%lo(", file
);
6562 output_addr_const (file
, XEXP (x
, 1));
6565 else if (GET_CODE (x
) == CONST_DOUBLE
6566 && (GET_MODE (x
) == VOIDmode
6567 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
6569 if (CONST_DOUBLE_HIGH (x
) == 0)
6570 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
6571 else if (CONST_DOUBLE_HIGH (x
) == -1
6572 && CONST_DOUBLE_LOW (x
) < 0)
6573 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
6575 output_operand_lossage ("long long constant not a valid immediate operand");
6577 else if (GET_CODE (x
) == CONST_DOUBLE
)
6578 output_operand_lossage ("floating point constant not a valid immediate operand");
6579 else { output_addr_const (file
, x
); }
6582 /* Target hook for assembling integer objects. The sparc version has
6583 special handling for aligned DI-mode objects. */
6586 sparc_assemble_integer (x
, size
, aligned_p
)
6591 /* ??? We only output .xword's for symbols and only then in environments
6592 where the assembler can handle them. */
6593 if (aligned_p
&& size
== 8
6594 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
6598 assemble_integer_with_op ("\t.xword\t", x
);
6603 assemble_aligned_integer (4, const0_rtx
);
6604 assemble_aligned_integer (4, x
);
6608 return default_assemble_integer (x
, size
, aligned_p
);
6611 /* Return the value of a code used in the .proc pseudo-op that says
6612 what kind of result this function returns. For non-C types, we pick
6613 the closest C type. */
6615 #ifndef SHORT_TYPE_SIZE
6616 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6619 #ifndef INT_TYPE_SIZE
6620 #define INT_TYPE_SIZE BITS_PER_WORD
6623 #ifndef LONG_TYPE_SIZE
6624 #define LONG_TYPE_SIZE BITS_PER_WORD
6627 #ifndef LONG_LONG_TYPE_SIZE
6628 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6631 #ifndef FLOAT_TYPE_SIZE
6632 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6635 #ifndef DOUBLE_TYPE_SIZE
6636 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6639 #ifndef LONG_DOUBLE_TYPE_SIZE
6640 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6644 sparc_type_code (type
)
6647 register unsigned long qualifiers
= 0;
6648 register unsigned shift
;
6650 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6651 setting more, since some assemblers will give an error for this. Also,
6652 we must be careful to avoid shifts of 32 bits or more to avoid getting
6653 unpredictable results. */
6655 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
6657 switch (TREE_CODE (type
))
6663 qualifiers
|= (3 << shift
);
6668 qualifiers
|= (2 << shift
);
6672 case REFERENCE_TYPE
:
6674 qualifiers
|= (1 << shift
);
6678 return (qualifiers
| 8);
6681 case QUAL_UNION_TYPE
:
6682 return (qualifiers
| 9);
6685 return (qualifiers
| 10);
6688 return (qualifiers
| 16);
6691 /* If this is a range type, consider it to be the underlying
6693 if (TREE_TYPE (type
) != 0)
6696 /* Carefully distinguish all the standard types of C,
6697 without messing up if the language is not C. We do this by
6698 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6699 look at both the names and the above fields, but that's redundant.
6700 Any type whose size is between two C types will be considered
6701 to be the wider of the two types. Also, we do not have a
6702 special code to use for "long long", so anything wider than
6703 long is treated the same. Note that we can't distinguish
6704 between "int" and "long" in this code if they are the same
6705 size, but that's fine, since neither can the assembler. */
6707 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
6708 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
6710 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
6711 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
6713 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
6714 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
6717 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
6720 /* If this is a range type, consider it to be the underlying
6722 if (TREE_TYPE (type
) != 0)
6725 /* Carefully distinguish all the standard types of C,
6726 without messing up if the language is not C. */
6728 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
6729 return (qualifiers
| 6);
6732 return (qualifiers
| 7);
6734 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
6735 /* ??? We need to distinguish between double and float complex types,
6736 but I don't know how yet because I can't reach this code from
6737 existing front-ends. */
6738 return (qualifiers
| 7); /* Who knows? */
6740 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
6741 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
6742 case FILE_TYPE
: /* GNU Pascal FILE type. */
6743 case SET_TYPE
: /* GNU Pascal SET type. */
6744 case LANG_TYPE
: /* ? */
6748 abort (); /* Not a type! */
6755 /* Nested function support. */
6757 /* Emit RTL insns to initialize the variable parts of a trampoline.
6758 FNADDR is an RTX for the address of the function's pure code.
6759 CXT is an RTX for the static chain value for the function.
6761 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6762 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6763 (to store insns). This is a bit excessive. Perhaps a different
6764 mechanism would be better here.
6766 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6769 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
6770 rtx tramp
, fnaddr
, cxt
;
6772 /* SPARC 32 bit trampoline:
6775 sethi %hi(static), %g2
6777 or %g2, %lo(static), %g2
6779 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6780 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6782 #ifdef TRANSFER_FROM_TRAMPOLINE
6783 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6784 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6788 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
6789 expand_binop (SImode
, ior_optab
,
6790 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
6791 size_int (10), 0, 1),
6792 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
6793 NULL_RTX
, 1, OPTAB_DIRECT
));
6796 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6797 expand_binop (SImode
, ior_optab
,
6798 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
6799 size_int (10), 0, 1),
6800 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
6801 NULL_RTX
, 1, OPTAB_DIRECT
));
6804 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6805 expand_binop (SImode
, ior_optab
,
6806 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
6807 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
6808 NULL_RTX
, 1, OPTAB_DIRECT
));
6811 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6812 expand_binop (SImode
, ior_optab
,
6813 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
6814 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
6815 NULL_RTX
, 1, OPTAB_DIRECT
));
6817 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6818 aligned on a 16 byte boundary so one flush clears it all. */
6819 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
6820 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6821 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6822 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
6823 plus_constant (tramp
, 8)))));
6826 /* The 64 bit version is simpler because it makes more sense to load the
6827 values as "immediate" data out of the trampoline. It's also easier since
6828 we can read the PC without clobbering a register. */
6831 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
6832 rtx tramp
, fnaddr
, cxt
;
6834 #ifdef TRANSFER_FROM_TRAMPOLINE
6835 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6836 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6847 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
6848 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
6849 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6850 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
6851 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6852 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
6853 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6854 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
6855 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
6856 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
6857 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
6859 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6860 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6861 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
6864 /* Subroutines to support a flat (single) register window calling
6867 /* Single-register window sparc stack frames look like:
6869 Before call After call
6870 +-----------------------+ +-----------------------+
6872 mem | caller's temps. | | caller's temps. |
6874 +-----------------------+ +-----------------------+
6876 | arguments on stack. | | arguments on stack. |
6878 +-----------------------+FP+92->+-----------------------+
6879 | 6 words to save | | 6 words to save |
6880 | arguments passed | | arguments passed |
6881 | in registers, even | | in registers, even |
6882 | if not passed. | | if not passed. |
6883 SP+68->+-----------------------+FP+68->+-----------------------+
6884 | 1 word struct addr | | 1 word struct addr |
6885 +-----------------------+FP+64->+-----------------------+
6887 | 16 word reg save area | | 16 word reg save area |
6889 SP->+-----------------------+ FP->+-----------------------+
6891 | fp/alu reg moves |
6892 FP-16->+-----------------------+
6896 +-----------------------+
6898 | fp register save |
6900 +-----------------------+
6902 | gp register save |
6904 +-----------------------+
6906 | alloca allocations |
6908 +-----------------------+
6910 | arguments on stack |
6912 SP+92->+-----------------------+
6914 | arguments passed |
6915 | in registers, even |
6916 low | if not passed. |
6917 memory SP+68->+-----------------------+
6918 | 1 word struct addr |
6919 SP+64->+-----------------------+
6921 I 16 word reg save area |
6923 SP->+-----------------------+ */
6925 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6926 save masks, and offsets for the current function. */
6928 struct sparc_frame_info
6930 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6931 unsigned long var_size
; /* # bytes that variables take up. */
6932 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6933 unsigned long extra_size
; /* # bytes of extra gunk. */
6934 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6935 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6936 unsigned long gmask
; /* Mask of saved gp registers. */
6937 unsigned long fmask
; /* Mask of saved fp registers. */
6938 unsigned long reg_offset
; /* Offset from new sp to store regs. */
6939 int initialized
; /* Nonzero if frame size already calculated. */
6942 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6943 struct sparc_frame_info current_frame_info
;
6945 /* Zero structure to initialize current_frame_info. */
6946 struct sparc_frame_info zero_frame_info
;
6948 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6950 #define RETURN_ADDR_REGNUM 15
6951 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6952 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6954 #define MUST_SAVE_REGISTER(regno) \
6955 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6956 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6957 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6959 /* Return the bytes needed to compute the frame pointer from the current
6963 sparc_flat_compute_frame_size (size
)
6964 int size
; /* # of var. bytes allocated. */
6967 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6968 unsigned long var_size
; /* # bytes that variables take up. */
6969 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6970 unsigned long extra_size
; /* # extra bytes. */
6971 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6972 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6973 unsigned long gmask
; /* Mask of saved gp registers. */
6974 unsigned long fmask
; /* Mask of saved fp registers. */
6975 unsigned long reg_offset
; /* Offset to register save area. */
6976 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
6978 /* This is the size of the 16 word reg save area, 1 word struct addr
6979 area, and 4 word fp/alu register copy area. */
6980 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
6990 if (!leaf_function_p ())
6992 /* Also include the size needed for the 6 parameter registers. */
6993 args_size
= current_function_outgoing_args_size
+ 24;
6995 total_size
= var_size
+ args_size
;
6997 /* Calculate space needed for gp registers. */
6998 for (regno
= 1; regno
<= 31; regno
++)
7000 if (MUST_SAVE_REGISTER (regno
))
7002 /* If we need to save two regs in a row, ensure there's room to bump
7003 up the address to align it to a doubleword boundary. */
7004 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
7006 if (gp_reg_size
% 8 != 0)
7008 gp_reg_size
+= 2 * UNITS_PER_WORD
;
7009 gmask
|= 3 << regno
;
7015 gp_reg_size
+= UNITS_PER_WORD
;
7016 gmask
|= 1 << regno
;
7021 /* Calculate space needed for fp registers. */
7022 for (regno
= 32; regno
<= 63; regno
++)
7024 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
7026 fp_reg_size
+= UNITS_PER_WORD
;
7027 fmask
|= 1 << (regno
- 32);
7034 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
7035 /* Ensure save area is 8 byte aligned if we need it. */
7037 if (need_aligned_p
&& n
!= 0)
7039 total_size
+= 8 - n
;
7040 reg_offset
+= 8 - n
;
7042 total_size
+= gp_reg_size
+ fp_reg_size
;
7045 /* If we must allocate a stack frame at all, we must also allocate
7046 room for register window spillage, so as to be binary compatible
7047 with libraries and operating systems that do not use -mflat. */
7049 total_size
+= extra_size
;
7053 total_size
= SPARC_STACK_ALIGN (total_size
);
7055 /* Save other computed information. */
7056 current_frame_info
.total_size
= total_size
;
7057 current_frame_info
.var_size
= var_size
;
7058 current_frame_info
.args_size
= args_size
;
7059 current_frame_info
.extra_size
= extra_size
;
7060 current_frame_info
.gp_reg_size
= gp_reg_size
;
7061 current_frame_info
.fp_reg_size
= fp_reg_size
;
7062 current_frame_info
.gmask
= gmask
;
7063 current_frame_info
.fmask
= fmask
;
7064 current_frame_info
.reg_offset
= reg_offset
;
7065 current_frame_info
.initialized
= reload_completed
;
7067 /* Ok, we're done. */
7071 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7074 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7075 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7076 [BASE_REG+OFFSET] will always be a valid address.
7078 WORD_OP is either "st" for save, "ld" for restore.
7079 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7082 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
7083 doubleword_op
, base_offset
)
7085 const char *base_reg
;
7086 unsigned int offset
;
7087 unsigned long gmask
;
7088 unsigned long fmask
;
7089 const char *word_op
;
7090 const char *doubleword_op
;
7091 unsigned long base_offset
;
7095 if (gmask
== 0 && fmask
== 0)
7098 /* Save registers starting from high to low. We've already saved the
7099 previous frame pointer and previous return address for the debugger's
7100 sake. The debugger allows us to not need a nop in the epilog if at least
7101 one register is reloaded in addition to return address. */
7105 for (regno
= 1; regno
<= 31; regno
++)
7107 if ((gmask
& (1L << regno
)) != 0)
7109 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
7111 /* We can save two registers in a row. If we're not at a
7112 double word boundary, move to one.
7113 sparc_flat_compute_frame_size ensures there's room to do
7115 if (offset
% 8 != 0)
7116 offset
+= UNITS_PER_WORD
;
7118 if (word_op
[0] == 's')
7120 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7121 doubleword_op
, reg_names
[regno
],
7123 if (dwarf2out_do_frame ())
7125 char *l
= dwarf2out_cfi_label ();
7126 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
7128 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
7132 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7133 doubleword_op
, base_reg
, offset
,
7136 offset
+= 2 * UNITS_PER_WORD
;
7141 if (word_op
[0] == 's')
7143 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7144 word_op
, reg_names
[regno
],
7146 if (dwarf2out_do_frame ())
7147 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7150 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7151 word_op
, base_reg
, offset
, reg_names
[regno
]);
7153 offset
+= UNITS_PER_WORD
;
7161 for (regno
= 32; regno
<= 63; regno
++)
7163 if ((fmask
& (1L << (regno
- 32))) != 0)
7165 if (word_op
[0] == 's')
7167 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7168 word_op
, reg_names
[regno
],
7170 if (dwarf2out_do_frame ())
7171 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7174 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7175 word_op
, base_reg
, offset
, reg_names
[regno
]);
7177 offset
+= UNITS_PER_WORD
;
7183 /* Set up the stack and frame (if desired) for the function. */
7186 sparc_flat_function_prologue (file
, size
)
7190 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7191 unsigned long gmask
= current_frame_info
.gmask
;
7193 sparc_output_scratch_registers (file
);
7195 /* This is only for the human reader. */
7196 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
7197 fprintf (file
, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7199 current_frame_info
.var_size
,
7200 current_frame_info
.gp_reg_size
/ 4,
7201 current_frame_info
.fp_reg_size
/ 4,
7202 current_function_outgoing_args_size
,
7203 current_frame_info
.extra_size
);
7205 size
= SPARC_STACK_ALIGN (size
);
7206 size
= (! current_frame_info
.initialized
7207 ? sparc_flat_compute_frame_size (size
)
7208 : current_frame_info
.total_size
);
7210 /* These cases shouldn't happen. Catch them now. */
7211 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
7214 /* Allocate our stack frame by decrementing %sp.
7215 At present, the only algorithm gdb can use to determine if this is a
7216 flat frame is if we always set %i7 if we set %sp. This can be optimized
7217 in the future by putting in some sort of debugging information that says
7218 this is a `flat' function. However, there is still the case of debugging
7219 code without such debugging information (including cases where most fns
7220 have such info, but there is one that doesn't). So, always do this now
7221 so we don't get a lot of code out there that gdb can't handle.
7222 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7223 distinguish us from a non-flat function but there won't (and shouldn't)
7224 be any differences anyway. The return pc is saved (if necessary) right
7225 after %i7 so gdb won't have to look too far to find it. */
7228 unsigned int reg_offset
= current_frame_info
.reg_offset
;
7229 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7230 static const char *const t1_str
= "%g1";
7232 /* Things get a little tricky if local variables take up more than ~4096
7233 bytes and outgoing arguments take up more than ~4096 bytes. When that
7234 happens, the register save area can't be accessed from either end of
7235 the frame. Handle this by decrementing %sp to the start of the gp
7236 register save area, save the regs, update %i7, and then set %sp to its
7237 final value. Given that we only have one scratch register to play
7238 with it is the cheapest solution, and it helps gdb out as it won't
7239 slow down recognition of flat functions.
7240 Don't change the order of insns emitted here without checking with
7241 the gdb folk first. */
7243 /* Is the entire register save area offsettable from %sp? */
7244 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7248 fprintf (file
, "\tadd\t%s, %d, %s\n",
7249 sp_str
, (int) -size
, sp_str
);
7250 if (gmask
& HARD_FRAME_POINTER_MASK
)
7252 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7253 fp_str
, sp_str
, reg_offset
);
7254 fprintf (file
, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7255 sp_str
, (int) -size
, fp_str
, ASM_COMMENT_START
);
7261 fprintf (file
, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7262 ", %s\n\tsub\t%s, %s, %s\n",
7263 size
, t1_str
, sp_str
, t1_str
, sp_str
);
7264 if (gmask
& HARD_FRAME_POINTER_MASK
)
7266 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7267 fp_str
, sp_str
, reg_offset
);
7268 fprintf (file
, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7269 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
7273 if (dwarf2out_do_frame ())
7275 char *l
= dwarf2out_cfi_label ();
7276 if (gmask
& HARD_FRAME_POINTER_MASK
)
7278 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7279 reg_offset
- 4 - size
);
7280 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7283 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
7285 if (gmask
& RETURN_ADDR_MASK
)
7287 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7288 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
7289 if (dwarf2out_do_frame ())
7290 dwarf2out_return_save ("", reg_offset
- size
);
7293 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7294 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7295 current_frame_info
.fmask
,
7296 "st", "std", -size
);
7300 /* Subtract %sp in two steps, but make sure there is always a
7301 64 byte register save area, and %sp is properly aligned. */
7302 /* Amount to decrement %sp by, the first time. */
7303 unsigned HOST_WIDE_INT size1
= ((size
- reg_offset
+ 64) + 15) & -16;
7304 /* Offset to register save area from %sp. */
7305 unsigned HOST_WIDE_INT offset
= size1
- (size
- reg_offset
);
7309 fprintf (file
, "\tadd\t%s, %d, %s\n",
7310 sp_str
, (int) -size1
, sp_str
);
7311 if (gmask
& HARD_FRAME_POINTER_MASK
)
7313 fprintf (file
, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7314 fp_str
, sp_str
, (int) offset
, sp_str
, (int) -size1
,
7315 fp_str
, ASM_COMMENT_START
);
7321 fprintf (file
, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7322 ", %s\n\tsub\t%s, %s, %s\n",
7323 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
7324 if (gmask
& HARD_FRAME_POINTER_MASK
)
7326 fprintf (file
, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7327 fp_str
, sp_str
, (int) offset
, sp_str
, t1_str
,
7328 fp_str
, ASM_COMMENT_START
);
7332 if (dwarf2out_do_frame ())
7334 char *l
= dwarf2out_cfi_label ();
7335 if (gmask
& HARD_FRAME_POINTER_MASK
)
7337 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7338 offset
- 4 - size1
);
7339 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7342 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
7344 if (gmask
& RETURN_ADDR_MASK
)
7346 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7347 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, (int) offset
);
7348 if (dwarf2out_do_frame ())
7349 /* offset - size1 == reg_offset - size
7350 if reg_offset were updated above like offset. */
7351 dwarf2out_return_save ("", offset
- size1
);
7354 sparc_flat_save_restore (file
, sp_str
, offset
,
7355 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7356 current_frame_info
.fmask
,
7357 "st", "std", -size1
);
7358 fprintf (file
, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7359 ", %s\n\tsub\t%s, %s, %s\n",
7360 size
- size1
, t1_str
, sp_str
, t1_str
, sp_str
);
7361 if (dwarf2out_do_frame ())
7362 if (! (gmask
& HARD_FRAME_POINTER_MASK
))
7363 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
7367 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
7370 /* Do any necessary cleanup after a function to restore stack, frame,
7374 sparc_flat_function_epilogue (file
, size
)
7378 rtx epilogue_delay
= current_function_epilogue_delay_list
;
7379 int noepilogue
= FALSE
;
7381 /* This is only for the human reader. */
7382 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
7384 /* The epilogue does not depend on any registers, but the stack
7385 registers, so we assume that if we have 1 pending nop, it can be
7386 ignored, and 2 it must be filled (2 nops occur for integer
7387 multiply and divide). */
7389 size
= SPARC_STACK_ALIGN (size
);
7390 size
= (!current_frame_info
.initialized
7391 ? sparc_flat_compute_frame_size (size
)
7392 : current_frame_info
.total_size
);
7394 if (size
== 0 && epilogue_delay
== 0)
7396 rtx insn
= get_last_insn ();
7398 /* If the last insn was a BARRIER, we don't have to write any code
7399 because a jump (aka return) was put there. */
7400 if (GET_CODE (insn
) == NOTE
)
7401 insn
= prev_nonnote_insn (insn
);
7402 if (insn
&& GET_CODE (insn
) == BARRIER
)
7408 unsigned HOST_WIDE_INT reg_offset
= current_frame_info
.reg_offset
;
7409 unsigned HOST_WIDE_INT size1
;
7410 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7411 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7412 static const char *const t1_str
= "%g1";
7414 /* In the reload sequence, we don't need to fill the load delay
7415 slots for most of the loads, also see if we can fill the final
7416 delay slot if not otherwise filled by the reload sequence. */
7419 fprintf (file
, "\tset\t" HOST_WIDE_INT_PRINT_DEC
", %s\n",
7422 if (frame_pointer_needed
)
7425 fprintf (file
,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7426 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
7428 fprintf (file
,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7429 fp_str
, (int) size
, sp_str
, ASM_COMMENT_START
);
7432 /* Is the entire register save area offsettable from %sp? */
7433 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7439 /* Restore %sp in two steps, but make sure there is always a
7440 64 byte register save area, and %sp is properly aligned. */
7441 /* Amount to increment %sp by, the first time. */
7442 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
7443 /* Offset to register save area from %sp. */
7444 reg_offset
= size1
- reg_offset
;
7446 fprintf (file
, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7447 ", %s\n\tadd\t%s, %s, %s\n",
7448 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
7451 /* We must restore the frame pointer and return address reg first
7452 because they are treated specially by the prologue output code. */
7453 if (current_frame_info
.gmask
& HARD_FRAME_POINTER_MASK
)
7455 fprintf (file
, "\tld\t[%s+%d], %s\n",
7456 sp_str
, (int) reg_offset
, fp_str
);
7459 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
7461 fprintf (file
, "\tld\t[%s+%d], %s\n",
7462 sp_str
, (int) reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
7466 /* Restore any remaining saved registers. */
7467 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7468 current_frame_info
.gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7469 current_frame_info
.fmask
,
7472 /* If we had to increment %sp in two steps, record it so the second
7473 restoration in the epilogue finishes up. */
7478 fprintf (file
, "\tset\t" HOST_WIDE_INT_PRINT_DEC
", %s\n",
7482 if (current_function_returns_struct
)
7483 fprintf (file
, "\tjmp\t%%o7+12\n");
7485 fprintf (file
, "\tretl\n");
7487 /* If the only register saved is the return address, we need a
7488 nop, unless we have an instruction to put into it. Otherwise
7489 we don't since reloading multiple registers doesn't reference
7490 the register being loaded. */
7496 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
7499 else if (size
> 4095)
7500 fprintf (file
, "\tadd\t%s, %s, %s\n", sp_str
, t1_str
, sp_str
);
7503 fprintf (file
, "\tadd\t%s, %d, %s\n", sp_str
, (int) size
, sp_str
);
7506 fprintf (file
, "\tnop\n");
7509 /* Reset state info for each function. */
7510 current_frame_info
= zero_frame_info
;
7512 sparc_output_deferred_case_vectors ();
7515 /* Define the number of delay slots needed for the function epilogue.
7517 On the sparc, we need a slot if either no stack has been allocated,
7518 or the only register saved is the return register. */
7521 sparc_flat_epilogue_delay_slots ()
7523 if (!current_frame_info
.initialized
)
7524 (void) sparc_flat_compute_frame_size (get_frame_size ());
7526 if (current_frame_info
.total_size
== 0)
7532 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7533 Any single length instruction which doesn't reference the stack or frame
7537 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
7539 int slot ATTRIBUTE_UNUSED
;
7541 rtx pat
= PATTERN (trial
);
7543 if (get_attr_length (trial
) != 1)
7546 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
7547 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
7553 /* Adjust the cost of a scheduling dependency. Return the new cost of
7554 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7557 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7563 enum attr_type insn_type
;
7565 if (! recog_memoized (insn
))
7568 insn_type
= get_attr_type (insn
);
7570 if (REG_NOTE_KIND (link
) == 0)
7572 /* Data dependency; DEP_INSN writes a register that INSN reads some
7575 /* if a load, then the dependence must be on the memory address;
7576 add an extra "cycle". Note that the cost could be two cycles
7577 if the reg was written late in an instruction group; we ca not tell
7579 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7582 /* Get the delay only if the address of the store is the dependence. */
7583 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7585 rtx pat
= PATTERN(insn
);
7586 rtx dep_pat
= PATTERN (dep_insn
);
7588 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7589 return cost
; /* This should not happen! */
7591 /* The dependency between the two instructions was on the data that
7592 is being stored. Assume that this implies that the address of the
7593 store is not dependent. */
7594 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7597 return cost
+ 3; /* An approximation. */
7600 /* A shift instruction cannot receive its data from an instruction
7601 in the same cycle; add a one cycle penalty. */
7602 if (insn_type
== TYPE_SHIFT
)
7603 return cost
+ 3; /* Split before cascade into shift. */
7607 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7608 INSN writes some cycles later. */
7610 /* These are only significant for the fpu unit; writing a fp reg before
7611 the fpu has finished with it stalls the processor. */
7613 /* Reusing an integer register causes no problems. */
7614 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7622 hypersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7628 enum attr_type insn_type
, dep_type
;
7629 rtx pat
= PATTERN(insn
);
7630 rtx dep_pat
= PATTERN (dep_insn
);
7632 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7635 insn_type
= get_attr_type (insn
);
7636 dep_type
= get_attr_type (dep_insn
);
7638 switch (REG_NOTE_KIND (link
))
7641 /* Data dependency; DEP_INSN writes a register that INSN reads some
7648 /* Get the delay iff the address of the store is the dependence. */
7649 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7652 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7659 /* If a load, then the dependence must be on the memory address. If
7660 the addresses aren't equal, then it might be a false dependency */
7661 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7663 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7664 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7665 || GET_CODE (SET_SRC (pat
)) != MEM
7666 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7667 XEXP (SET_SRC (pat
), 0)))
7675 /* Compare to branch latency is 0. There is no benefit from
7676 separating compare and branch. */
7677 if (dep_type
== TYPE_COMPARE
)
7679 /* Floating point compare to branch latency is less than
7680 compare to conditional move. */
7681 if (dep_type
== TYPE_FPCMP
)
7690 /* Anti-dependencies only penalize the fpu unit. */
7691 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7703 sparc_adjust_cost(insn
, link
, dep
, cost
)
7711 case PROCESSOR_SUPERSPARC
:
7712 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7714 case PROCESSOR_HYPERSPARC
:
7715 case PROCESSOR_SPARCLITE86X
:
7716 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7725 sparc_sched_init (dump
, sched_verbose
, max_ready
)
7726 FILE *dump ATTRIBUTE_UNUSED
;
7727 int sched_verbose ATTRIBUTE_UNUSED
;
7728 int max_ready ATTRIBUTE_UNUSED
;
7733 sparc_use_dfa_pipeline_interface ()
7735 if ((1 << sparc_cpu
) &
7736 ((1 << PROCESSOR_ULTRASPARC
) | (1 << PROCESSOR_CYPRESS
) |
7737 (1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7738 (1 << PROCESSOR_SPARCLITE86X
) | (1 << PROCESSOR_TSC701
) |
7739 (1 << PROCESSOR_ULTRASPARC3
)))
7745 sparc_use_sched_lookahead ()
7747 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7748 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7750 if ((1 << sparc_cpu
) &
7751 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7752 (1 << PROCESSOR_SPARCLITE86X
)))
7765 /* Assume V9 processors are capable of at least dual-issue. */
7767 case PROCESSOR_SUPERSPARC
:
7769 case PROCESSOR_HYPERSPARC
:
7770 case PROCESSOR_SPARCLITE86X
:
7772 case PROCESSOR_ULTRASPARC
:
7773 case PROCESSOR_ULTRASPARC3
:
7782 register rtx pat
= PATTERN (insn
);
7784 switch (GET_CODE (SET_SRC (pat
)))
7786 /* Load and some shift instructions zero extend. */
7789 /* sethi clears the high bits */
7791 /* LO_SUM is used with sethi. sethi cleared the high
7792 bits and the values used with lo_sum are positive */
7794 /* Store flag stores 0 or 1 */
7804 rtx op0
= XEXP (SET_SRC (pat
), 0);
7805 rtx op1
= XEXP (SET_SRC (pat
), 1);
7806 if (GET_CODE (op1
) == CONST_INT
)
7807 return INTVAL (op1
) >= 0;
7808 if (GET_CODE (op0
) != REG
)
7810 if (sparc_check_64 (op0
, insn
) == 1)
7812 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7817 rtx op0
= XEXP (SET_SRC (pat
), 0);
7818 rtx op1
= XEXP (SET_SRC (pat
), 1);
7819 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7821 if (GET_CODE (op1
) == CONST_INT
)
7822 return INTVAL (op1
) >= 0;
7823 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7826 return GET_MODE (SET_SRC (pat
)) == SImode
;
7827 /* Positive integers leave the high bits zero. */
7829 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7831 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7834 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7836 return sparc_check_64 (SET_SRC (pat
), insn
);
7842 /* We _ought_ to have only one kind per function, but... */
7843 static GTY(()) rtx sparc_addr_diff_list
;
7844 static GTY(()) rtx sparc_addr_list
;
7847 sparc_defer_case_vector (lab
, vec
, diff
)
7851 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7853 sparc_addr_diff_list
7854 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7856 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7860 sparc_output_addr_vec (vec
)
7863 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7864 int idx
, vlen
= XVECLEN (body
, 0);
7866 #ifdef ASM_OUTPUT_ADDR_VEC_START
7867 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7870 #ifdef ASM_OUTPUT_CASE_LABEL
7871 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7874 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7877 for (idx
= 0; idx
< vlen
; idx
++)
7879 ASM_OUTPUT_ADDR_VEC_ELT
7880 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7883 #ifdef ASM_OUTPUT_ADDR_VEC_END
7884 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7889 sparc_output_addr_diff_vec (vec
)
7892 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7893 rtx base
= XEXP (XEXP (body
, 0), 0);
7894 int idx
, vlen
= XVECLEN (body
, 1);
7896 #ifdef ASM_OUTPUT_ADDR_VEC_START
7897 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7900 #ifdef ASM_OUTPUT_CASE_LABEL
7901 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7904 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7907 for (idx
= 0; idx
< vlen
; idx
++)
7909 ASM_OUTPUT_ADDR_DIFF_ELT
7912 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7913 CODE_LABEL_NUMBER (base
));
7916 #ifdef ASM_OUTPUT_ADDR_VEC_END
7917 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7922 sparc_output_deferred_case_vectors ()
7927 if (sparc_addr_list
== NULL_RTX
7928 && sparc_addr_diff_list
== NULL_RTX
)
7931 /* Align to cache line in the function's code section. */
7932 function_section (current_function_decl
);
7934 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7936 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7938 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7939 sparc_output_addr_vec (XEXP (t
, 0));
7940 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7941 sparc_output_addr_diff_vec (XEXP (t
, 0));
7943 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7946 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7947 unknown. Return 1 if the high bits are zero, -1 if the register is
7950 sparc_check_64 (x
, insn
)
7953 /* If a register is set only once it is safe to ignore insns this
7954 code does not know how to handle. The loop will either recognize
7955 the single set and return the correct value or fail to recognize
7960 if (GET_CODE (x
) != REG
)
7963 if (GET_MODE (x
) == DImode
)
7964 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7966 if (flag_expensive_optimizations
7967 && REG_N_SETS (REGNO (y
)) == 1)
7973 insn
= get_last_insn_anywhere ();
7978 while ((insn
= PREV_INSN (insn
)))
7980 switch (GET_CODE (insn
))
7993 rtx pat
= PATTERN (insn
);
7994 if (GET_CODE (pat
) != SET
)
7996 if (rtx_equal_p (x
, SET_DEST (pat
)))
7997 return set_extends (insn
);
7998 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7999 return set_extends (insn
);
8000 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8008 /* Returns assembly code to perform a DImode shift using
8009 a 64-bit global or out register on SPARC-V8+. */
8011 sparc_v8plus_shift (operands
, insn
, opcode
)
8016 static char asm_code
[60];
8018 /* The scratch register is only required when the destination
8019 register is not a 64-bit global or out register. */
8020 if (which_alternative
!= 2)
8021 operands
[3] = operands
[0];
8023 if (GET_CODE (operands
[1]) == CONST_INT
)
8025 output_asm_insn ("mov\t%1, %3", operands
);
8029 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8030 if (sparc_check_64 (operands
[1], insn
) <= 0)
8031 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8032 output_asm_insn ("or\t%L1, %3, %3", operands
);
8035 strcpy(asm_code
, opcode
);
8037 if (which_alternative
!= 2)
8038 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8040 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8043 /* Output rtl to increment the profiler label LABELNO
8044 for profiling a function entry. */
8047 sparc_profile_hook (labelno
)
8053 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8054 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8055 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8057 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8060 #ifdef OBJECT_FORMAT_ELF
8062 sparc_elf_asm_named_section (name
, flags
)
8066 if (flags
& SECTION_MERGE
)
8068 /* entsize cannot be expressed in this section attributes
8070 default_elf_asm_named_section (name
, flags
);
8074 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8076 if (!(flags
& SECTION_DEBUG
))
8077 fputs (",#alloc", asm_out_file
);
8078 if (flags
& SECTION_WRITE
)
8079 fputs (",#write", asm_out_file
);
8080 if (flags
& SECTION_CODE
)
8081 fputs (",#execinstr", asm_out_file
);
8083 /* ??? Handle SECTION_BSS. */
8085 fputc ('\n', asm_out_file
);
8087 #endif /* OBJECT_FORMAT_ELF */
8089 /* We do not allow sibling calls if -mflat, nor
8090 we do not allow indirect calls to be optimized into sibling calls.
8092 Also, on sparc 32-bit we cannot emit a sibling call when the
8093 current function returns a structure. This is because the "unimp
8094 after call" convention would cause the callee to return to the
8095 wrong place. The generic code already disallows cases where the
8096 function being called returns a structure.
8098 It may seem strange how this last case could occur. Usually there
8099 is code after the call which jumps to epilogue code which dumps the
8100 return value into the struct return area. That ought to invalidate
8101 the sibling call right? Well, in the c++ case we can end up passing
8102 the pointer to the struct return area to a constructor (which returns
8103 void) and then nothing else happens. Such a sibling call would look
8104 valid without the added check here. */
8106 sparc_function_ok_for_sibcall (decl
, exp
)
8108 tree exp ATTRIBUTE_UNUSED
;
8112 && (TARGET_ARCH64
|| ! current_function_returns_struct
));
8115 /* ??? Similar to the standard section selection, but force reloc-y-ness
8116 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8117 pretending PIC always on), but that's what the old code did. */
8120 sparc_aout_select_section (t
, reloc
, align
)
8123 unsigned HOST_WIDE_INT align
;
8125 default_select_section (t
, reloc
| SUNOS4_SHARED_LIBRARIES
, align
);
8128 /* Use text section for a constant unless we need more alignment than
8132 sparc_aout_select_rtx_section (mode
, x
, align
)
8133 enum machine_mode mode
;
8135 unsigned HOST_WIDE_INT align
;
8137 if (align
<= MAX_TEXT_ALIGN
8138 && ! (flag_pic
&& (symbolic_operand (x
, mode
)
8139 || SUNOS4_SHARED_LIBRARIES
)))
8140 readonly_data_section ();
8146 sparc_extra_constraint_check (op
, c
, strict
)
8154 && (c
== 'T' || c
== 'U'))
8160 return fp_sethi_p (op
);
8163 return fp_mov_p (op
);
8166 return fp_high_losum_p (op
);
8170 || (GET_CODE (op
) == REG
8171 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8172 || reg_renumber
[REGNO (op
)] >= 0)))
8173 return register_ok_for_ldd (op
);
8185 /* Our memory extra constraints have to emulate the
8186 behavior of 'm' and 'o' in order for reload to work
8188 if (GET_CODE (op
) == MEM
)
8191 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8193 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8198 reload_ok_mem
= (reload_in_progress
8199 && GET_CODE (op
) == REG
8200 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8201 && reg_renumber
[REGNO (op
)] < 0);
8204 return reload_ok_mem
;
8207 /* ??? This duplicates information provided to the compiler by the
8208 ??? scheduler description. Some day, teach genautomata to output
8209 ??? the latencies and then CSE will just use that. */
8212 sparc_rtx_costs (x
, code
, outer_code
, total
)
8214 int code
, outer_code
, *total
;
8218 case PLUS
: case MINUS
: case ABS
: case NEG
:
8219 case FLOAT
: case UNSIGNED_FLOAT
:
8220 case FIX
: case UNSIGNED_FIX
:
8221 case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
8222 if (FLOAT_MODE_P (GET_MODE (x
)))
8226 case PROCESSOR_ULTRASPARC
:
8227 case PROCESSOR_ULTRASPARC3
:
8228 *total
= COSTS_N_INSNS (4);
8231 case PROCESSOR_SUPERSPARC
:
8232 *total
= COSTS_N_INSNS (3);
8235 case PROCESSOR_CYPRESS
:
8236 *total
= COSTS_N_INSNS (5);
8239 case PROCESSOR_HYPERSPARC
:
8240 case PROCESSOR_SPARCLITE86X
:
8242 *total
= COSTS_N_INSNS (1);
8247 *total
= COSTS_N_INSNS (1);
8253 case PROCESSOR_ULTRASPARC
:
8254 if (GET_MODE (x
) == SFmode
)
8255 *total
= COSTS_N_INSNS (13);
8257 *total
= COSTS_N_INSNS (23);
8260 case PROCESSOR_ULTRASPARC3
:
8261 if (GET_MODE (x
) == SFmode
)
8262 *total
= COSTS_N_INSNS (20);
8264 *total
= COSTS_N_INSNS (29);
8267 case PROCESSOR_SUPERSPARC
:
8268 *total
= COSTS_N_INSNS (12);
8271 case PROCESSOR_CYPRESS
:
8272 *total
= COSTS_N_INSNS (63);
8275 case PROCESSOR_HYPERSPARC
:
8276 case PROCESSOR_SPARCLITE86X
:
8277 *total
= COSTS_N_INSNS (17);
8281 *total
= COSTS_N_INSNS (30);
8286 if (FLOAT_MODE_P (GET_MODE (x
)))
8290 case PROCESSOR_ULTRASPARC
:
8291 case PROCESSOR_ULTRASPARC3
:
8292 *total
= COSTS_N_INSNS (1);
8295 case PROCESSOR_SUPERSPARC
:
8296 *total
= COSTS_N_INSNS (3);
8299 case PROCESSOR_CYPRESS
:
8300 *total
= COSTS_N_INSNS (5);
8303 case PROCESSOR_HYPERSPARC
:
8304 case PROCESSOR_SPARCLITE86X
:
8306 *total
= COSTS_N_INSNS (1);
8311 /* ??? Maybe mark integer compares as zero cost on
8312 ??? all UltraSPARC processors because the result
8313 ??? can be bypassed to a branch in the same group. */
8315 *total
= COSTS_N_INSNS (1);
8319 if (FLOAT_MODE_P (GET_MODE (x
)))
8323 case PROCESSOR_ULTRASPARC
:
8324 case PROCESSOR_ULTRASPARC3
:
8325 *total
= COSTS_N_INSNS (4);
8328 case PROCESSOR_SUPERSPARC
:
8329 *total
= COSTS_N_INSNS (3);
8332 case PROCESSOR_CYPRESS
:
8333 *total
= COSTS_N_INSNS (7);
8336 case PROCESSOR_HYPERSPARC
:
8337 case PROCESSOR_SPARCLITE86X
:
8338 *total
= COSTS_N_INSNS (1);
8342 *total
= COSTS_N_INSNS (5);
8347 /* The latency is actually variable for Ultra-I/II
8348 And if one of the inputs have a known constant
8349 value, we could calculate this precisely.
8351 However, for that to be useful we would need to
8352 add some machine description changes which would
8353 make sure small constants ended up in rs1 of the
8354 multiply instruction. This is because the multiply
8355 latency is determined by the number of clear (or
8356 set if the value is negative) bits starting from
8357 the most significant bit of the first input.
8359 The algorithm for computing num_cycles of a multiply
8363 highest_bit = highest_clear_bit(rs1);
8365 highest_bit = highest_set_bit(rs1);
8368 num_cycles = 4 + ((highest_bit - 3) / 2);
8370 If we did that we would have to also consider register
8371 allocation issues that would result from forcing such
8372 a value into a register.
8374 There are other similar tricks we could play if we
8375 knew, for example, that one input was an array index.
8377 Since we do not play any such tricks currently the
8378 safest thing to do is report the worst case latency. */
8379 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8381 *total
= (GET_MODE (x
) == DImode
8382 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8386 /* Multiply latency on Ultra-III, fortunately, is constant. */
8387 if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8389 *total
= COSTS_N_INSNS (6);
8393 if (sparc_cpu
== PROCESSOR_HYPERSPARC
8394 || sparc_cpu
== PROCESSOR_SPARCLITE86X
)
8396 *total
= COSTS_N_INSNS (17);
8400 *total
= (TARGET_HARD_MUL
? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8407 if (FLOAT_MODE_P (GET_MODE (x
)))
8411 case PROCESSOR_ULTRASPARC
:
8412 if (GET_MODE (x
) == SFmode
)
8413 *total
= COSTS_N_INSNS (13);
8415 *total
= COSTS_N_INSNS (23);
8418 case PROCESSOR_ULTRASPARC3
:
8419 if (GET_MODE (x
) == SFmode
)
8420 *total
= COSTS_N_INSNS (17);
8422 *total
= COSTS_N_INSNS (20);
8425 case PROCESSOR_SUPERSPARC
:
8426 if (GET_MODE (x
) == SFmode
)
8427 *total
= COSTS_N_INSNS (6);
8429 *total
= COSTS_N_INSNS (9);
8432 case PROCESSOR_HYPERSPARC
:
8433 case PROCESSOR_SPARCLITE86X
:
8434 if (GET_MODE (x
) == SFmode
)
8435 *total
= COSTS_N_INSNS (8);
8437 *total
= COSTS_N_INSNS (12);
8441 *total
= COSTS_N_INSNS (7);
8446 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8447 *total
= (GET_MODE (x
) == DImode
8448 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8449 else if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8450 *total
= (GET_MODE (x
) == DImode
8451 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8453 *total
= COSTS_N_INSNS (25);
8457 /* Conditional moves. */
8460 case PROCESSOR_ULTRASPARC
:
8461 *total
= COSTS_N_INSNS (2);
8464 case PROCESSOR_ULTRASPARC3
:
8465 if (FLOAT_MODE_P (GET_MODE (x
)))
8466 *total
= COSTS_N_INSNS (3);
8468 *total
= COSTS_N_INSNS (2);
8472 *total
= COSTS_N_INSNS (1);
8477 /* If outer-code is SIGN/ZERO extension we have to subtract
8478 out COSTS_N_INSNS (1) from whatever we return in determining
8482 case PROCESSOR_ULTRASPARC
:
8483 if (outer_code
== ZERO_EXTEND
)
8484 *total
= COSTS_N_INSNS (1);
8486 *total
= COSTS_N_INSNS (2);
8489 case PROCESSOR_ULTRASPARC3
:
8490 if (outer_code
== ZERO_EXTEND
)
8492 if (GET_MODE (x
) == QImode
8493 || GET_MODE (x
) == HImode
8494 || outer_code
== SIGN_EXTEND
)
8495 *total
= COSTS_N_INSNS (2);
8497 *total
= COSTS_N_INSNS (1);
8501 /* This handles sign extension (3 cycles)
8502 and everything else (2 cycles). */
8503 *total
= COSTS_N_INSNS (2);
8507 case PROCESSOR_SUPERSPARC
:
8508 if (FLOAT_MODE_P (GET_MODE (x
))
8509 || outer_code
== ZERO_EXTEND
8510 || outer_code
== SIGN_EXTEND
)
8511 *total
= COSTS_N_INSNS (0);
8513 *total
= COSTS_N_INSNS (1);
8516 case PROCESSOR_TSC701
:
8517 if (outer_code
== ZERO_EXTEND
8518 || outer_code
== SIGN_EXTEND
)
8519 *total
= COSTS_N_INSNS (2);
8521 *total
= COSTS_N_INSNS (3);
8524 case PROCESSOR_CYPRESS
:
8525 if (outer_code
== ZERO_EXTEND
8526 || outer_code
== SIGN_EXTEND
)
8527 *total
= COSTS_N_INSNS (1);
8529 *total
= COSTS_N_INSNS (2);
8532 case PROCESSOR_HYPERSPARC
:
8533 case PROCESSOR_SPARCLITE86X
:
8535 if (outer_code
== ZERO_EXTEND
8536 || outer_code
== SIGN_EXTEND
)
8537 *total
= COSTS_N_INSNS (0);
8539 *total
= COSTS_N_INSNS (1);
8544 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8562 if (GET_MODE (x
) == DImode
8563 && ((XINT (x
, 3) == 0
8564 && (unsigned HOST_WIDE_INT
) XINT (x
, 2) < 0x1000)
8565 || (XINT (x
, 3) == -1
8567 && XINT (x
, 2) >= -0x1000)))
8578 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8579 Used for C++ multiple inheritance. */
8582 sparc_output_mi_thunk (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
8584 tree thunk_fndecl ATTRIBUTE_UNUSED
;
8585 HOST_WIDE_INT delta
;
8586 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
;
8589 rtx
this, insn
, funexp
, delta_rtx
, tmp
;
8591 reload_completed
= 1;
8592 epilogue_completed
= 1;
8594 current_function_uses_only_leaf_regs
= 1;
8596 emit_note (NOTE_INSN_PROLOGUE_END
);
8598 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8599 returns a structure, the structure return pointer is there instead. */
8600 if (TARGET_ARCH64
&& aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
8601 this = gen_rtx_REG (Pmode
, SPARC_INCOMING_INT_ARG_FIRST
+ 1);
8603 this = gen_rtx_REG (Pmode
, SPARC_INCOMING_INT_ARG_FIRST
);
8605 /* Add DELTA. When possible use a plain add, otherwise load it into
8606 a register first. */
8607 delta_rtx
= GEN_INT (delta
);
8608 if (!SPARC_SIMM13_P (delta
))
8610 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8612 sparc_emit_set_const64 (scratch
, delta_rtx
);
8614 sparc_emit_set_const32 (scratch
, delta_rtx
);
8615 delta_rtx
= scratch
;
8618 tmp
= gen_rtx_PLUS (Pmode
, this, delta_rtx
);
8619 emit_insn (gen_rtx_SET (VOIDmode
, this, tmp
));
8621 /* Generate a tail call to the target function. */
8622 if (! TREE_USED (function
))
8624 assemble_external (function
);
8625 TREE_USED (function
) = 1;
8627 funexp
= XEXP (DECL_RTL (function
), 0);
8628 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8629 insn
= emit_call_insn (gen_sibcall (funexp
));
8630 SIBLING_CALL_P (insn
) = 1;
8633 /* Run just enough of rest_of_compilation to get the insns emitted.
8634 There's not really enough bulk here to make other passes such as
8635 instruction scheduling worth while. Note that use_thunk calls
8636 assemble_start_function and assemble_end_function. */
8637 insn
= get_insns ();
8638 insn_locators_initialize ();
8639 shorten_branches (insn
);
8640 final_start_function (insn
, file
, 1);
8641 final (insn
, file
, 1, 0);
8642 final_end_function ();
8644 reload_completed
= 0;
8645 epilogue_completed
= 0;
8649 #include "gt-sparc.h"