1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs
= {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs
= {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs
= {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs
= {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs
= {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs
= {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs
= {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs
= {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs
= {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
279 struct processor_costs niagara3_costs
= {
280 COSTS_N_INSNS (3), /* int load */
281 COSTS_N_INSNS (3), /* int signed load */
282 COSTS_N_INSNS (3), /* int zeroed load */
283 COSTS_N_INSNS (3), /* float load */
284 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
285 COSTS_N_INSNS (9), /* fadd, fsub */
286 COSTS_N_INSNS (9), /* fcmp */
287 COSTS_N_INSNS (9), /* fmov, fmovr */
288 COSTS_N_INSNS (9), /* fmul */
289 COSTS_N_INSNS (23), /* fdivs */
290 COSTS_N_INSNS (37), /* fdivd */
291 COSTS_N_INSNS (23), /* fsqrts */
292 COSTS_N_INSNS (37), /* fsqrtd */
293 COSTS_N_INSNS (9), /* imul */
294 COSTS_N_INSNS (9), /* imulX */
295 0, /* imul bit factor */
296 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
297 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
298 COSTS_N_INSNS (1), /* movcc/movr */
299 0, /* shift penalty */
302 const struct processor_costs
*sparc_costs
= &cypress_costs
;
304 #ifdef HAVE_AS_RELAX_OPTION
305 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
306 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
307 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
308 somebody does not branch between the sethi and jmp. */
309 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
311 #define LEAF_SIBCALL_SLOT_RESERVED_P \
312 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
315 /* Vector to say how input registers are mapped to output registers.
316 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
317 eliminate it. You must use -fomit-frame-pointer to get that. */
318 char leaf_reg_remap
[] =
319 { 0, 1, 2, 3, 4, 5, 6, 7,
320 -1, -1, -1, -1, -1, -1, 14, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1,
322 8, 9, 10, 11, 12, 13, -1, 15,
324 32, 33, 34, 35, 36, 37, 38, 39,
325 40, 41, 42, 43, 44, 45, 46, 47,
326 48, 49, 50, 51, 52, 53, 54, 55,
327 56, 57, 58, 59, 60, 61, 62, 63,
328 64, 65, 66, 67, 68, 69, 70, 71,
329 72, 73, 74, 75, 76, 77, 78, 79,
330 80, 81, 82, 83, 84, 85, 86, 87,
331 88, 89, 90, 91, 92, 93, 94, 95,
332 96, 97, 98, 99, 100};
334 /* Vector, indexed by hard register number, which contains 1
335 for a register that is allowable in a candidate for leaf
336 function treatment. */
337 char sparc_leaf_regs
[] =
338 { 1, 1, 1, 1, 1, 1, 1, 1,
339 0, 0, 0, 0, 0, 0, 1, 0,
340 0, 0, 0, 0, 0, 0, 0, 0,
341 1, 1, 1, 1, 1, 1, 0, 1,
342 1, 1, 1, 1, 1, 1, 1, 1,
343 1, 1, 1, 1, 1, 1, 1, 1,
344 1, 1, 1, 1, 1, 1, 1, 1,
345 1, 1, 1, 1, 1, 1, 1, 1,
346 1, 1, 1, 1, 1, 1, 1, 1,
347 1, 1, 1, 1, 1, 1, 1, 1,
348 1, 1, 1, 1, 1, 1, 1, 1,
349 1, 1, 1, 1, 1, 1, 1, 1,
352 struct GTY(()) machine_function
354 /* Size of the frame of the function. */
355 HOST_WIDE_INT frame_size
;
357 /* Size of the frame of the function minus the register window save area
358 and the outgoing argument area. */
359 HOST_WIDE_INT apparent_frame_size
;
361 /* Register we pretend the frame pointer is allocated to. Normally, this
362 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
363 record "offset" separately as it may be too big for (reg + disp). */
365 HOST_WIDE_INT frame_base_offset
;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name
;
370 /* Number of global or FP registers to be saved (as 4-byte quantities). */
371 int n_global_fp_regs
;
373 /* True if the current function is leaf and uses only leaf regs,
374 so that the SPARC leaf function optimization can be applied.
375 Private version of current_function_uses_only_leaf_regs, see
376 sparc_expand_prologue for the rationale. */
379 /* True if the prologue saves local or in registers. */
380 bool save_local_in_regs_p
;
382 /* True if the data calculated by sparc_expand_prologue are valid. */
383 bool prologue_data_valid_p
;
386 #define sparc_frame_size cfun->machine->frame_size
387 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
388 #define sparc_frame_base_reg cfun->machine->frame_base_reg
389 #define sparc_frame_base_offset cfun->machine->frame_base_offset
390 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
391 #define sparc_leaf_function_p cfun->machine->leaf_function_p
392 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
393 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
395 /* 1 if the next opcode is to be specially indented. */
396 int sparc_indent_opcode
= 0;
398 static void sparc_option_override (void);
399 static void sparc_init_modes (void);
400 static void scan_record_type (const_tree
, int *, int *, int *);
401 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
402 const_tree
, bool, bool, int *, int *);
404 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
405 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
407 static void sparc_emit_set_const32 (rtx
, rtx
);
408 static void sparc_emit_set_const64 (rtx
, rtx
);
409 static void sparc_output_addr_vec (rtx
);
410 static void sparc_output_addr_diff_vec (rtx
);
411 static void sparc_output_deferred_case_vectors (void);
412 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
413 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
414 static rtx
sparc_builtin_saveregs (void);
415 static int epilogue_renumber (rtx
*, int);
416 static bool sparc_assemble_integer (rtx
, unsigned int, int);
417 static int set_extends (rtx
);
418 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
419 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
420 #ifdef TARGET_SOLARIS
421 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
422 tree
) ATTRIBUTE_UNUSED
;
424 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
425 static int sparc_issue_rate (void);
426 static void sparc_sched_init (FILE *, int, int);
427 static int sparc_use_sched_lookahead (void);
429 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
430 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
431 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
432 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
433 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
435 static bool sparc_function_ok_for_sibcall (tree
, tree
);
436 static void sparc_init_libfuncs (void);
437 static void sparc_init_builtins (void);
438 static void sparc_vis_init_builtins (void);
439 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
440 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
441 static int sparc_vis_mul8x16 (int, int);
442 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
443 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
444 HOST_WIDE_INT
, tree
);
445 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
446 HOST_WIDE_INT
, const_tree
);
447 static struct machine_function
* sparc_init_machine_status (void);
448 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
449 static rtx
sparc_tls_get_addr (void);
450 static rtx
sparc_tls_got (void);
451 static const char *get_some_local_dynamic_name (void);
452 static int get_some_local_dynamic_name_1 (rtx
*, void *);
453 static int sparc_register_move_cost (enum machine_mode
,
454 reg_class_t
, reg_class_t
);
455 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
456 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
457 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
458 static bool sparc_function_value_regno_p (const unsigned int);
459 static rtx
sparc_struct_value_rtx (tree
, int);
460 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
461 int *, const_tree
, int);
462 static bool sparc_return_in_memory (const_tree
, const_tree
);
463 static bool sparc_strict_argument_naming (cumulative_args_t
);
464 static void sparc_va_start (tree
, rtx
);
465 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
466 static bool sparc_vector_mode_supported_p (enum machine_mode
);
467 static bool sparc_tls_referenced_p (rtx
);
468 static rtx
sparc_legitimize_tls_address (rtx
);
469 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
470 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
471 static rtx
sparc_delegitimize_address (rtx
);
472 static bool sparc_mode_dependent_address_p (const_rtx
);
473 static bool sparc_pass_by_reference (cumulative_args_t
,
474 enum machine_mode
, const_tree
, bool);
475 static void sparc_function_arg_advance (cumulative_args_t
,
476 enum machine_mode
, const_tree
, bool);
477 static rtx
sparc_function_arg_1 (cumulative_args_t
,
478 enum machine_mode
, const_tree
, bool, bool);
479 static rtx
sparc_function_arg (cumulative_args_t
,
480 enum machine_mode
, const_tree
, bool);
481 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
482 enum machine_mode
, const_tree
, bool);
483 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
485 static int sparc_arg_partial_bytes (cumulative_args_t
,
486 enum machine_mode
, tree
, bool);
487 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
488 static void sparc_file_end (void);
489 static bool sparc_frame_pointer_required (void);
490 static bool sparc_can_eliminate (const int, const int);
491 static rtx
sparc_builtin_setjmp_frame_value (void);
492 static void sparc_conditional_register_usage (void);
493 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
494 static const char *sparc_mangle_type (const_tree
);
496 static void sparc_trampoline_init (rtx
, tree
, rtx
);
497 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
498 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
499 static bool sparc_print_operand_punct_valid_p (unsigned char);
500 static void sparc_print_operand (FILE *, rtx
, int);
501 static void sparc_print_operand_address (FILE *, rtx
);
503 #ifdef SUBTARGET_ATTRIBUTE_TABLE
504 /* Table of valid machine attributes. */
505 static const struct attribute_spec sparc_attribute_table
[] =
507 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
509 SUBTARGET_ATTRIBUTE_TABLE
,
510 { NULL
, 0, 0, false, false, false, NULL
, false }
514 /* Option handling. */
517 enum cmodel sparc_cmodel
;
519 char sparc_hard_reg_printed
[8];
521 /* Initialize the GCC target structure. */
523 /* The default is to use .half rather than .short for aligned HI objects. */
524 #undef TARGET_ASM_ALIGNED_HI_OP
525 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
527 #undef TARGET_ASM_UNALIGNED_HI_OP
528 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
529 #undef TARGET_ASM_UNALIGNED_SI_OP
530 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
531 #undef TARGET_ASM_UNALIGNED_DI_OP
532 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
534 /* The target hook has to handle DI-mode values. */
535 #undef TARGET_ASM_INTEGER
536 #define TARGET_ASM_INTEGER sparc_assemble_integer
538 #undef TARGET_ASM_FUNCTION_PROLOGUE
539 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
540 #undef TARGET_ASM_FUNCTION_EPILOGUE
541 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
543 #undef TARGET_SCHED_ADJUST_COST
544 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
545 #undef TARGET_SCHED_ISSUE_RATE
546 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
547 #undef TARGET_SCHED_INIT
548 #define TARGET_SCHED_INIT sparc_sched_init
549 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
550 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
552 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
553 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
555 #undef TARGET_INIT_LIBFUNCS
556 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
557 #undef TARGET_INIT_BUILTINS
558 #define TARGET_INIT_BUILTINS sparc_init_builtins
560 #undef TARGET_LEGITIMIZE_ADDRESS
561 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
562 #undef TARGET_DELEGITIMIZE_ADDRESS
563 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
564 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
565 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
567 #undef TARGET_EXPAND_BUILTIN
568 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
569 #undef TARGET_FOLD_BUILTIN
570 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
573 #undef TARGET_HAVE_TLS
574 #define TARGET_HAVE_TLS true
577 #undef TARGET_CANNOT_FORCE_CONST_MEM
578 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
580 #undef TARGET_ASM_OUTPUT_MI_THUNK
581 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
582 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
583 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
585 #undef TARGET_RTX_COSTS
586 #define TARGET_RTX_COSTS sparc_rtx_costs
587 #undef TARGET_ADDRESS_COST
588 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
589 #undef TARGET_REGISTER_MOVE_COST
590 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
592 #undef TARGET_PROMOTE_FUNCTION_MODE
593 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
595 #undef TARGET_FUNCTION_VALUE
596 #define TARGET_FUNCTION_VALUE sparc_function_value
597 #undef TARGET_LIBCALL_VALUE
598 #define TARGET_LIBCALL_VALUE sparc_libcall_value
599 #undef TARGET_FUNCTION_VALUE_REGNO_P
600 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
602 #undef TARGET_STRUCT_VALUE_RTX
603 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
604 #undef TARGET_RETURN_IN_MEMORY
605 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
606 #undef TARGET_MUST_PASS_IN_STACK
607 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
608 #undef TARGET_PASS_BY_REFERENCE
609 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
610 #undef TARGET_ARG_PARTIAL_BYTES
611 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
612 #undef TARGET_FUNCTION_ARG_ADVANCE
613 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
614 #undef TARGET_FUNCTION_ARG
615 #define TARGET_FUNCTION_ARG sparc_function_arg
616 #undef TARGET_FUNCTION_INCOMING_ARG
617 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
618 #undef TARGET_FUNCTION_ARG_BOUNDARY
619 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
621 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
622 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
623 #undef TARGET_STRICT_ARGUMENT_NAMING
624 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
626 #undef TARGET_EXPAND_BUILTIN_VA_START
627 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
628 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
629 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
631 #undef TARGET_VECTOR_MODE_SUPPORTED_P
632 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
634 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
635 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
637 #ifdef SUBTARGET_INSERT_ATTRIBUTES
638 #undef TARGET_INSERT_ATTRIBUTES
639 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
642 #ifdef SUBTARGET_ATTRIBUTE_TABLE
643 #undef TARGET_ATTRIBUTE_TABLE
644 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
647 #undef TARGET_RELAXED_ORDERING
648 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
650 #undef TARGET_OPTION_OVERRIDE
651 #define TARGET_OPTION_OVERRIDE sparc_option_override
653 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
654 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
655 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
658 #undef TARGET_ASM_FILE_END
659 #define TARGET_ASM_FILE_END sparc_file_end
661 #undef TARGET_FRAME_POINTER_REQUIRED
662 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
664 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
665 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
667 #undef TARGET_CAN_ELIMINATE
668 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
670 #undef TARGET_PREFERRED_RELOAD_CLASS
671 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
673 #undef TARGET_CONDITIONAL_REGISTER_USAGE
674 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
676 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
677 #undef TARGET_MANGLE_TYPE
678 #define TARGET_MANGLE_TYPE sparc_mangle_type
681 #undef TARGET_LEGITIMATE_ADDRESS_P
682 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
684 #undef TARGET_LEGITIMATE_CONSTANT_P
685 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
687 #undef TARGET_TRAMPOLINE_INIT
688 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
690 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
691 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
692 #undef TARGET_PRINT_OPERAND
693 #define TARGET_PRINT_OPERAND sparc_print_operand
694 #undef TARGET_PRINT_OPERAND_ADDRESS
695 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
697 struct gcc_target targetm
= TARGET_INITIALIZER
;
699 /* Validate and override various options, and do some machine dependent
703 sparc_option_override (void)
705 static struct code_model
{
706 const char *const name
;
707 const enum cmodel value
;
708 } const cmodels
[] = {
710 { "medlow", CM_MEDLOW
},
711 { "medmid", CM_MEDMID
},
712 { "medany", CM_MEDANY
},
713 { "embmedany", CM_EMBMEDANY
},
714 { NULL
, (enum cmodel
) 0 }
716 const struct code_model
*cmodel
;
717 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
718 static struct cpu_default
{
720 const enum processor_type processor
;
721 } const cpu_default
[] = {
722 /* There must be one entry here for each TARGET_CPU value. */
723 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
724 { TARGET_CPU_v8
, PROCESSOR_V8
},
725 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
726 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
727 { TARGET_CPU_leon
, PROCESSOR_LEON
},
728 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
729 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
730 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
731 { TARGET_CPU_v9
, PROCESSOR_V9
},
732 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
733 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
734 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
735 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
736 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
737 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
740 const struct cpu_default
*def
;
741 /* Table of values for -m{cpu,tune}=. This must match the order of
742 the PROCESSOR_* enumeration. */
743 static struct cpu_table
{
746 } const cpu_table
[] = {
749 { MASK_ISA
, MASK_V8
},
750 /* TI TMS390Z55 supersparc */
751 { MASK_ISA
, MASK_V8
},
752 { MASK_ISA
, MASK_V8
|MASK_FPU
},
754 { MASK_ISA
, MASK_V8
|MASK_FPU
},
755 { MASK_ISA
, MASK_SPARCLITE
},
756 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
757 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
758 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
759 { MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
760 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
761 { MASK_ISA
, MASK_SPARCLET
},
763 { MASK_ISA
, MASK_SPARCLET
},
764 { MASK_ISA
, MASK_V9
},
765 /* UltraSPARC I, II, IIi */
767 /* Although insns using %y are deprecated, it is a clear win. */
768 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
770 /* ??? Check if %y issue still holds true. */
772 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
775 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
777 { MASK_ISA
, MASK_V9
},
779 { MASK_ISA
, MASK_V9
},
781 { MASK_ISA
, MASK_V9
},
783 const struct cpu_table
*cpu
;
787 #ifdef SUBTARGET_OVERRIDE_OPTIONS
788 SUBTARGET_OVERRIDE_OPTIONS
;
791 #ifndef SPARC_BI_ARCH
792 /* Check for unsupported architecture size. */
793 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
794 error ("%s is not supported by this configuration",
795 DEFAULT_ARCH32_P
? "-m64" : "-m32");
798 /* We force all 64bit archs to use 128 bit long double */
799 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
801 error ("-mlong-double-64 not allowed with -m64");
802 target_flags
|= MASK_LONG_DOUBLE_128
;
805 /* Code model selection. */
806 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
810 sparc_cmodel
= CM_32
;
813 if (sparc_cmodel_string
!= NULL
)
817 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
818 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
820 if (cmodel
->name
== NULL
)
821 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
823 sparc_cmodel
= cmodel
->value
;
826 error ("-mcmodel= is not supported on 32 bit systems");
829 /* Check that -fcall-saved-REG wasn't specified for out registers. */
830 for (i
= 8; i
< 16; i
++)
831 if (!call_used_regs
[i
])
833 error ("-fcall-saved-REG is not supported for out registers");
834 call_used_regs
[i
] = 1;
837 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
839 /* Set the default CPU. */
840 if (!global_options_set
.x_sparc_cpu_and_features
)
842 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
843 if (def
->cpu
== TARGET_CPU_DEFAULT
)
845 gcc_assert (def
->cpu
!= -1);
846 sparc_cpu_and_features
= def
->processor
;
848 if (!global_options_set
.x_sparc_cpu
)
849 sparc_cpu
= sparc_cpu_and_features
;
851 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
852 target_flags
&= ~cpu
->disable
;
853 target_flags
|= cpu
->enable
;
855 /* If -mfpu or -mno-fpu was explicitly used, don't override with
856 the processor default. */
857 if (target_flags_explicit
& MASK_FPU
)
858 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
860 /* Don't allow -mvis if FPU is disabled. */
862 target_flags
&= ~MASK_VIS
;
864 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
866 -m64 also implies v9. */
867 if (TARGET_VIS
|| TARGET_ARCH64
)
869 target_flags
|= MASK_V9
;
870 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
873 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
874 if (TARGET_V9
&& TARGET_ARCH32
)
875 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
877 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
878 if (! TARGET_V9
|| TARGET_ARCH64
)
879 target_flags
&= ~MASK_V8PLUS
;
881 /* Don't use stack biasing in 32 bit mode. */
883 target_flags
&= ~MASK_STACK_BIAS
;
885 /* Supply a default value for align_functions. */
886 if (align_functions
== 0
887 && (sparc_cpu
== PROCESSOR_ULTRASPARC
888 || sparc_cpu
== PROCESSOR_ULTRASPARC3
889 || sparc_cpu
== PROCESSOR_NIAGARA
890 || sparc_cpu
== PROCESSOR_NIAGARA2
891 || sparc_cpu
== PROCESSOR_NIAGARA3
892 || sparc_cpu
== PROCESSOR_NIAGARA4
))
893 align_functions
= 32;
895 /* Validate PCC_STRUCT_RETURN. */
896 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
897 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
899 /* Only use .uaxword when compiling for a 64-bit target. */
901 targetm
.asm_out
.unaligned_op
.di
= NULL
;
903 /* Do various machine dependent initializations. */
906 /* Set up function hooks. */
907 init_machine_status
= sparc_init_machine_status
;
912 case PROCESSOR_CYPRESS
:
913 sparc_costs
= &cypress_costs
;
916 case PROCESSOR_SPARCLITE
:
917 case PROCESSOR_SUPERSPARC
:
918 sparc_costs
= &supersparc_costs
;
922 case PROCESSOR_HYPERSPARC
:
923 case PROCESSOR_SPARCLITE86X
:
924 sparc_costs
= &hypersparc_costs
;
927 sparc_costs
= &leon_costs
;
929 case PROCESSOR_SPARCLET
:
930 case PROCESSOR_TSC701
:
931 sparc_costs
= &sparclet_costs
;
934 case PROCESSOR_ULTRASPARC
:
935 sparc_costs
= &ultrasparc_costs
;
937 case PROCESSOR_ULTRASPARC3
:
938 sparc_costs
= &ultrasparc3_costs
;
940 case PROCESSOR_NIAGARA
:
941 sparc_costs
= &niagara_costs
;
943 case PROCESSOR_NIAGARA2
:
944 sparc_costs
= &niagara2_costs
;
946 case PROCESSOR_NIAGARA3
:
947 case PROCESSOR_NIAGARA4
:
948 sparc_costs
= &niagara3_costs
;
950 case PROCESSOR_NATIVE
:
954 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
955 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
956 target_flags
|= MASK_LONG_DOUBLE_128
;
959 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
960 ((sparc_cpu
== PROCESSOR_ULTRASPARC
961 || sparc_cpu
== PROCESSOR_NIAGARA
962 || sparc_cpu
== PROCESSOR_NIAGARA2
963 || sparc_cpu
== PROCESSOR_NIAGARA3
964 || sparc_cpu
== PROCESSOR_NIAGARA4
)
966 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
968 global_options
.x_param_values
,
969 global_options_set
.x_param_values
);
970 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
971 ((sparc_cpu
== PROCESSOR_ULTRASPARC
972 || sparc_cpu
== PROCESSOR_ULTRASPARC3
973 || sparc_cpu
== PROCESSOR_NIAGARA
974 || sparc_cpu
== PROCESSOR_NIAGARA2
975 || sparc_cpu
== PROCESSOR_NIAGARA3
976 || sparc_cpu
== PROCESSOR_NIAGARA4
)
978 global_options
.x_param_values
,
979 global_options_set
.x_param_values
);
981 /* Disable save slot sharing for call-clobbered registers by default.
982 The IRA sharing algorithm works on single registers only and this
983 pessimizes for double floating-point registers. */
984 if (!global_options_set
.x_flag_ira_share_save_slots
)
985 flag_ira_share_save_slots
= 0;
988 /* Miscellaneous utilities. */
990 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
991 or branch on register contents instructions. */
994 v9_regcmp_p (enum rtx_code code
)
996 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
997 || code
== LE
|| code
== GT
);
1000 /* Nonzero if OP is a floating point constant which can
1001 be loaded into an integer register using a single
1002 sethi instruction. */
1007 if (GET_CODE (op
) == CONST_DOUBLE
)
1012 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1013 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1014 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1020 /* Nonzero if OP is a floating point constant which can
1021 be loaded into an integer register using a single
1027 if (GET_CODE (op
) == CONST_DOUBLE
)
1032 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1033 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1034 return SPARC_SIMM13_P (i
);
1040 /* Nonzero if OP is a floating point constant which can
1041 be loaded into an integer register using a high/losum
1042 instruction sequence. */
1045 fp_high_losum_p (rtx op
)
1047 /* The constraints calling this should only be in
1048 SFmode move insns, so any constant which cannot
1049 be moved using a single insn will do. */
1050 if (GET_CODE (op
) == CONST_DOUBLE
)
1055 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1056 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1057 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1063 /* Return true if the address of LABEL can be loaded by means of the
1064 mov{si,di}_pic_label_ref patterns in PIC mode. */
1067 can_use_mov_pic_label_ref (rtx label
)
1069 /* VxWorks does not impose a fixed gap between segments; the run-time
1070 gap can be different from the object-file gap. We therefore can't
1071 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1072 are absolutely sure that X is in the same segment as the GOT.
1073 Unfortunately, the flexibility of linker scripts means that we
1074 can't be sure of that in general, so assume that GOT-relative
1075 accesses are never valid on VxWorks. */
1076 if (TARGET_VXWORKS_RTP
)
1079 /* Similarly, if the label is non-local, it might end up being placed
1080 in a different section than the current one; now mov_pic_label_ref
1081 requires the label and the code to be in the same section. */
1082 if (LABEL_REF_NONLOCAL_P (label
))
1085 /* Finally, if we are reordering basic blocks and partition into hot
1086 and cold sections, this might happen for any label. */
1087 if (flag_reorder_blocks_and_partition
)
1093 /* Expand a move instruction. Return true if all work is done. */
1096 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1098 /* Handle sets of MEM first. */
1099 if (GET_CODE (operands
[0]) == MEM
)
1101 /* 0 is a register (or a pair of registers) on SPARC. */
1102 if (register_or_zero_operand (operands
[1], mode
))
1105 if (!reload_in_progress
)
1107 operands
[0] = validize_mem (operands
[0]);
1108 operands
[1] = force_reg (mode
, operands
[1]);
1112 /* Fixup TLS cases. */
1114 && CONSTANT_P (operands
[1])
1115 && sparc_tls_referenced_p (operands
[1]))
1117 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1121 /* Fixup PIC cases. */
1122 if (flag_pic
&& CONSTANT_P (operands
[1]))
1124 if (pic_address_needs_scratch (operands
[1]))
1125 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1127 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1128 if (GET_CODE (operands
[1]) == LABEL_REF
1129 && can_use_mov_pic_label_ref (operands
[1]))
1133 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1139 gcc_assert (TARGET_ARCH64
);
1140 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1145 if (symbolic_operand (operands
[1], mode
))
1148 = sparc_legitimize_pic_address (operands
[1],
1150 ? operands
[0] : NULL_RTX
);
1155 /* If we are trying to toss an integer constant into FP registers,
1156 or loading a FP or vector constant, force it into memory. */
1157 if (CONSTANT_P (operands
[1])
1158 && REG_P (operands
[0])
1159 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1160 || SCALAR_FLOAT_MODE_P (mode
)
1161 || VECTOR_MODE_P (mode
)))
1163 /* emit_group_store will send such bogosity to us when it is
1164 not storing directly into memory. So fix this up to avoid
1165 crashes in output_constant_pool. */
1166 if (operands
[1] == const0_rtx
)
1167 operands
[1] = CONST0_RTX (mode
);
1169 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1170 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1171 && const_zero_operand (operands
[1], mode
))
1174 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1175 /* We are able to build any SF constant in integer registers
1176 with at most 2 instructions. */
1178 /* And any DF constant in integer registers. */
1180 && (reload_completed
|| reload_in_progress
))))
1183 operands
[1] = force_const_mem (mode
, operands
[1]);
1184 if (!reload_in_progress
)
1185 operands
[1] = validize_mem (operands
[1]);
1189 /* Accept non-constants and valid constants unmodified. */
1190 if (!CONSTANT_P (operands
[1])
1191 || GET_CODE (operands
[1]) == HIGH
1192 || input_operand (operands
[1], mode
))
1198 /* All QImode constants require only one insn, so proceed. */
1203 sparc_emit_set_const32 (operands
[0], operands
[1]);
1207 /* input_operand should have filtered out 32-bit mode. */
1208 sparc_emit_set_const64 (operands
[0], operands
[1]);
1218 /* Load OP1, a 32-bit constant, into OP0, a register.
1219 We know it can't be done in one insn when we get
1220 here, the move expander guarantees this. */
1223 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1225 enum machine_mode mode
= GET_MODE (op0
);
1228 if (reload_in_progress
|| reload_completed
)
1231 temp
= gen_reg_rtx (mode
);
1233 if (GET_CODE (op1
) == CONST_INT
)
1235 gcc_assert (!small_int_operand (op1
, mode
)
1236 && !const_high_operand (op1
, mode
));
1238 /* Emit them as real moves instead of a HIGH/LO_SUM,
1239 this way CSE can see everything and reuse intermediate
1240 values if it wants. */
1241 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1242 GEN_INT (INTVAL (op1
)
1243 & ~(HOST_WIDE_INT
)0x3ff)));
1245 emit_insn (gen_rtx_SET (VOIDmode
,
1247 gen_rtx_IOR (mode
, temp
,
1248 GEN_INT (INTVAL (op1
) & 0x3ff))));
1252 /* A symbol, emit in the traditional way. */
1253 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1254 gen_rtx_HIGH (mode
, op1
)));
1255 emit_insn (gen_rtx_SET (VOIDmode
,
1256 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1260 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1261 If TEMP is nonzero, we are forbidden to use any other scratch
1262 registers. Otherwise, we are allowed to generate them as needed.
1264 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1265 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1268 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1270 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1273 if (temp
&& GET_MODE (temp
) == TImode
)
1276 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1279 /* SPARC-V9 code-model support. */
1280 switch (sparc_cmodel
)
1283 /* The range spanned by all instructions in the object is less
1284 than 2^31 bytes (2GB) and the distance from any instruction
1285 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1286 than 2^31 bytes (2GB).
1288 The executable must be in the low 4TB of the virtual address
1291 sethi %hi(symbol), %temp1
1292 or %temp1, %lo(symbol), %reg */
1294 temp1
= temp
; /* op0 is allowed. */
1296 temp1
= gen_reg_rtx (DImode
);
1298 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1299 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1303 /* The range spanned by all instructions in the object is less
1304 than 2^31 bytes (2GB) and the distance from any instruction
1305 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1306 than 2^31 bytes (2GB).
1308 The executable must be in the low 16TB of the virtual address
1311 sethi %h44(symbol), %temp1
1312 or %temp1, %m44(symbol), %temp2
1313 sllx %temp2, 12, %temp3
1314 or %temp3, %l44(symbol), %reg */
1319 temp3
= temp
; /* op0 is allowed. */
1323 temp1
= gen_reg_rtx (DImode
);
1324 temp2
= gen_reg_rtx (DImode
);
1325 temp3
= gen_reg_rtx (DImode
);
1328 emit_insn (gen_seth44 (temp1
, op1
));
1329 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1330 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1331 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1332 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1336 /* The range spanned by all instructions in the object is less
1337 than 2^31 bytes (2GB) and the distance from any instruction
1338 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1339 than 2^31 bytes (2GB).
1341 The executable can be placed anywhere in the virtual address
1344 sethi %hh(symbol), %temp1
1345 sethi %lm(symbol), %temp2
1346 or %temp1, %hm(symbol), %temp3
1347 sllx %temp3, 32, %temp4
1348 or %temp4, %temp2, %temp5
1349 or %temp5, %lo(symbol), %reg */
1352 /* It is possible that one of the registers we got for operands[2]
1353 might coincide with that of operands[0] (which is why we made
1354 it TImode). Pick the other one to use as our scratch. */
1355 if (rtx_equal_p (temp
, op0
))
1357 gcc_assert (ti_temp
);
1358 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1361 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1368 temp1
= gen_reg_rtx (DImode
);
1369 temp2
= gen_reg_rtx (DImode
);
1370 temp3
= gen_reg_rtx (DImode
);
1371 temp4
= gen_reg_rtx (DImode
);
1372 temp5
= gen_reg_rtx (DImode
);
1375 emit_insn (gen_sethh (temp1
, op1
));
1376 emit_insn (gen_setlm (temp2
, op1
));
1377 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1378 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1379 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1380 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1381 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1382 emit_insn (gen_setlo (op0
, temp5
, op1
));
1386 /* Old old old backwards compatibility kruft here.
1387 Essentially it is MEDLOW with a fixed 64-bit
1388 virtual base added to all data segment addresses.
1389 Text-segment stuff is computed like MEDANY, we can't
1390 reuse the code above because the relocation knobs
1393 Data segment: sethi %hi(symbol), %temp1
1394 add %temp1, EMBMEDANY_BASE_REG, %temp2
1395 or %temp2, %lo(symbol), %reg */
1396 if (data_segment_operand (op1
, GET_MODE (op1
)))
1400 temp1
= temp
; /* op0 is allowed. */
1405 temp1
= gen_reg_rtx (DImode
);
1406 temp2
= gen_reg_rtx (DImode
);
1409 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1410 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1411 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1414 /* Text segment: sethi %uhi(symbol), %temp1
1415 sethi %hi(symbol), %temp2
1416 or %temp1, %ulo(symbol), %temp3
1417 sllx %temp3, 32, %temp4
1418 or %temp4, %temp2, %temp5
1419 or %temp5, %lo(symbol), %reg */
1424 /* It is possible that one of the registers we got for operands[2]
1425 might coincide with that of operands[0] (which is why we made
1426 it TImode). Pick the other one to use as our scratch. */
1427 if (rtx_equal_p (temp
, op0
))
1429 gcc_assert (ti_temp
);
1430 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1433 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1440 temp1
= gen_reg_rtx (DImode
);
1441 temp2
= gen_reg_rtx (DImode
);
1442 temp3
= gen_reg_rtx (DImode
);
1443 temp4
= gen_reg_rtx (DImode
);
1444 temp5
= gen_reg_rtx (DImode
);
1447 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1448 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1449 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1450 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1451 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1452 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1453 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1454 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1463 #if HOST_BITS_PER_WIDE_INT == 32
1465 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1470 /* These avoid problems when cross compiling. If we do not
1471 go through all this hair then the optimizer will see
1472 invalid REG_EQUAL notes or in some cases none at all. */
1473 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1474 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1475 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1476 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1478 /* The optimizer is not to assume anything about exactly
1479 which bits are set for a HIGH, they are unspecified.
1480 Unfortunately this leads to many missed optimizations
1481 during CSE. We mask out the non-HIGH bits, and matches
1482 a plain movdi, to alleviate this problem. */
1484 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1486 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1490 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1492 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1496 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1498 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1502 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1504 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1507 /* Worker routines for 64-bit constant formation on arch64.
1508 One of the key things to be doing in these emissions is
1509 to create as many temp REGs as possible. This makes it
1510 possible for half-built constants to be used later when
1511 such values are similar to something required later on.
1512 Without doing this, the optimizer cannot see such
1515 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1516 unsigned HOST_WIDE_INT
, int);
1519 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1520 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1522 unsigned HOST_WIDE_INT high_bits
;
1525 high_bits
= (~low_bits
) & 0xffffffff;
1527 high_bits
= low_bits
;
1529 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1532 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1533 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1537 /* If we are XOR'ing with -1, then we should emit a one's complement
1538 instead. This way the combiner will notice logical operations
1539 such as ANDN later on and substitute. */
1540 if ((low_bits
& 0x3ff) == 0x3ff)
1542 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1543 gen_rtx_NOT (DImode
, temp
)));
1547 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1548 gen_safe_XOR64 (temp
,
1549 (-(HOST_WIDE_INT
)0x400
1550 | (low_bits
& 0x3ff)))));
1555 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1556 unsigned HOST_WIDE_INT
, int);
1559 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1560 unsigned HOST_WIDE_INT high_bits
,
1561 unsigned HOST_WIDE_INT low_immediate
,
1566 if ((high_bits
& 0xfffffc00) != 0)
1568 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1569 if ((high_bits
& ~0xfffffc00) != 0)
1570 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1571 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1577 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1581 /* Now shift it up into place. */
1582 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1583 gen_rtx_ASHIFT (DImode
, temp2
,
1584 GEN_INT (shift_count
))));
1586 /* If there is a low immediate part piece, finish up by
1587 putting that in as well. */
1588 if (low_immediate
!= 0)
1589 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1590 gen_safe_OR64 (op0
, low_immediate
)));
1593 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1594 unsigned HOST_WIDE_INT
);
1596 /* Full 64-bit constant decomposition. Even though this is the
1597 'worst' case, we still optimize a few things away. */
1599 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1600 unsigned HOST_WIDE_INT high_bits
,
1601 unsigned HOST_WIDE_INT low_bits
)
1605 if (reload_in_progress
|| reload_completed
)
1608 sub_temp
= gen_reg_rtx (DImode
);
1610 if ((high_bits
& 0xfffffc00) != 0)
1612 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1613 if ((high_bits
& ~0xfffffc00) != 0)
1614 emit_insn (gen_rtx_SET (VOIDmode
,
1616 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1622 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1626 if (!reload_in_progress
&& !reload_completed
)
1628 rtx temp2
= gen_reg_rtx (DImode
);
1629 rtx temp3
= gen_reg_rtx (DImode
);
1630 rtx temp4
= gen_reg_rtx (DImode
);
1632 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1633 gen_rtx_ASHIFT (DImode
, sub_temp
,
1636 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1637 if ((low_bits
& ~0xfffffc00) != 0)
1639 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1640 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1641 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1642 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1646 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1647 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1652 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1653 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1654 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1657 /* We are in the middle of reload, so this is really
1658 painful. However we do still make an attempt to
1659 avoid emitting truly stupid code. */
1660 if (low1
!= const0_rtx
)
1662 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1663 gen_rtx_ASHIFT (DImode
, sub_temp
,
1664 GEN_INT (to_shift
))));
1665 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1666 gen_rtx_IOR (DImode
, op0
, low1
)));
1674 if (low2
!= const0_rtx
)
1676 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1677 gen_rtx_ASHIFT (DImode
, sub_temp
,
1678 GEN_INT (to_shift
))));
1679 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1680 gen_rtx_IOR (DImode
, op0
, low2
)));
1688 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1689 gen_rtx_ASHIFT (DImode
, sub_temp
,
1690 GEN_INT (to_shift
))));
1691 if (low3
!= const0_rtx
)
1692 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1693 gen_rtx_IOR (DImode
, op0
, low3
)));
1698 /* Analyze a 64-bit constant for certain properties. */
1699 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1700 unsigned HOST_WIDE_INT
,
1701 int *, int *, int *);
1704 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1705 unsigned HOST_WIDE_INT low_bits
,
1706 int *hbsp
, int *lbsp
, int *abbasp
)
1708 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1711 lowest_bit_set
= highest_bit_set
= -1;
1715 if ((lowest_bit_set
== -1)
1716 && ((low_bits
>> i
) & 1))
1718 if ((highest_bit_set
== -1)
1719 && ((high_bits
>> (32 - i
- 1)) & 1))
1720 highest_bit_set
= (64 - i
- 1);
1723 && ((highest_bit_set
== -1)
1724 || (lowest_bit_set
== -1)));
1730 if ((lowest_bit_set
== -1)
1731 && ((high_bits
>> i
) & 1))
1732 lowest_bit_set
= i
+ 32;
1733 if ((highest_bit_set
== -1)
1734 && ((low_bits
>> (32 - i
- 1)) & 1))
1735 highest_bit_set
= 32 - i
- 1;
1738 && ((highest_bit_set
== -1)
1739 || (lowest_bit_set
== -1)));
1741 /* If there are no bits set this should have gone out
1742 as one instruction! */
1743 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1744 all_bits_between_are_set
= 1;
1745 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1749 if ((low_bits
& (1 << i
)) != 0)
1754 if ((high_bits
& (1 << (i
- 32))) != 0)
1757 all_bits_between_are_set
= 0;
1760 *hbsp
= highest_bit_set
;
1761 *lbsp
= lowest_bit_set
;
1762 *abbasp
= all_bits_between_are_set
;
1765 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1768 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1769 unsigned HOST_WIDE_INT low_bits
)
1771 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1774 || high_bits
== 0xffffffff)
1777 analyze_64bit_constant (high_bits
, low_bits
,
1778 &highest_bit_set
, &lowest_bit_set
,
1779 &all_bits_between_are_set
);
1781 if ((highest_bit_set
== 63
1782 || lowest_bit_set
== 0)
1783 && all_bits_between_are_set
!= 0)
1786 if ((highest_bit_set
- lowest_bit_set
) < 21)
1792 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1793 unsigned HOST_WIDE_INT
,
1796 static unsigned HOST_WIDE_INT
1797 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1798 unsigned HOST_WIDE_INT low_bits
,
1799 int lowest_bit_set
, int shift
)
1801 HOST_WIDE_INT hi
, lo
;
1803 if (lowest_bit_set
< 32)
1805 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1806 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1811 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1813 gcc_assert (! (hi
& lo
));
1817 /* Here we are sure to be arch64 and this is an integer constant
1818 being loaded into a register. Emit the most efficient
1819 insn sequence possible. Detection of all the 1-insn cases
1820 has been done already. */
1822 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1824 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1825 int lowest_bit_set
, highest_bit_set
;
1826 int all_bits_between_are_set
;
1829 /* Sanity check that we know what we are working with. */
1830 gcc_assert (TARGET_ARCH64
1831 && (GET_CODE (op0
) == SUBREG
1832 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1834 if (reload_in_progress
|| reload_completed
)
1837 if (GET_CODE (op1
) != CONST_INT
)
1839 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1844 temp
= gen_reg_rtx (DImode
);
1846 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1847 low_bits
= (INTVAL (op1
) & 0xffffffff);
1849 /* low_bits bits 0 --> 31
1850 high_bits bits 32 --> 63 */
1852 analyze_64bit_constant (high_bits
, low_bits
,
1853 &highest_bit_set
, &lowest_bit_set
,
1854 &all_bits_between_are_set
);
1856 /* First try for a 2-insn sequence. */
1858 /* These situations are preferred because the optimizer can
1859 * do more things with them:
1861 * sllx %reg, shift, %reg
1863 * srlx %reg, shift, %reg
1864 * 3) mov some_small_const, %reg
1865 * sllx %reg, shift, %reg
1867 if (((highest_bit_set
== 63
1868 || lowest_bit_set
== 0)
1869 && all_bits_between_are_set
!= 0)
1870 || ((highest_bit_set
- lowest_bit_set
) < 12))
1872 HOST_WIDE_INT the_const
= -1;
1873 int shift
= lowest_bit_set
;
1875 if ((highest_bit_set
!= 63
1876 && lowest_bit_set
!= 0)
1877 || all_bits_between_are_set
== 0)
1880 create_simple_focus_bits (high_bits
, low_bits
,
1883 else if (lowest_bit_set
== 0)
1884 shift
= -(63 - highest_bit_set
);
1886 gcc_assert (SPARC_SIMM13_P (the_const
));
1887 gcc_assert (shift
!= 0);
1889 emit_insn (gen_safe_SET64 (temp
, the_const
));
1891 emit_insn (gen_rtx_SET (VOIDmode
,
1893 gen_rtx_ASHIFT (DImode
,
1897 emit_insn (gen_rtx_SET (VOIDmode
,
1899 gen_rtx_LSHIFTRT (DImode
,
1901 GEN_INT (-shift
))));
1905 /* Now a range of 22 or less bits set somewhere.
1906 * 1) sethi %hi(focus_bits), %reg
1907 * sllx %reg, shift, %reg
1908 * 2) sethi %hi(focus_bits), %reg
1909 * srlx %reg, shift, %reg
1911 if ((highest_bit_set
- lowest_bit_set
) < 21)
1913 unsigned HOST_WIDE_INT focus_bits
=
1914 create_simple_focus_bits (high_bits
, low_bits
,
1915 lowest_bit_set
, 10);
1917 gcc_assert (SPARC_SETHI_P (focus_bits
));
1918 gcc_assert (lowest_bit_set
!= 10);
1920 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1922 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1923 if (lowest_bit_set
< 10)
1924 emit_insn (gen_rtx_SET (VOIDmode
,
1926 gen_rtx_LSHIFTRT (DImode
, temp
,
1927 GEN_INT (10 - lowest_bit_set
))));
1928 else if (lowest_bit_set
> 10)
1929 emit_insn (gen_rtx_SET (VOIDmode
,
1931 gen_rtx_ASHIFT (DImode
, temp
,
1932 GEN_INT (lowest_bit_set
- 10))));
1936 /* 1) sethi %hi(low_bits), %reg
1937 * or %reg, %lo(low_bits), %reg
1938 * 2) sethi %hi(~low_bits), %reg
1939 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1942 || high_bits
== 0xffffffff)
1944 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1945 (high_bits
== 0xffffffff));
1949 /* Now, try 3-insn sequences. */
1951 /* 1) sethi %hi(high_bits), %reg
1952 * or %reg, %lo(high_bits), %reg
1953 * sllx %reg, 32, %reg
1957 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1961 /* We may be able to do something quick
1962 when the constant is negated, so try that. */
1963 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1964 (~low_bits
) & 0xfffffc00))
1966 /* NOTE: The trailing bits get XOR'd so we need the
1967 non-negated bits, not the negated ones. */
1968 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1970 if ((((~high_bits
) & 0xffffffff) == 0
1971 && ((~low_bits
) & 0x80000000) == 0)
1972 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1973 && ((~low_bits
) & 0x80000000) != 0))
1975 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1977 if ((SPARC_SETHI_P (fast_int
)
1978 && (~high_bits
& 0xffffffff) == 0)
1979 || SPARC_SIMM13_P (fast_int
))
1980 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1982 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
1987 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1988 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1989 sparc_emit_set_const64 (temp
, negated_const
);
1992 /* If we are XOR'ing with -1, then we should emit a one's complement
1993 instead. This way the combiner will notice logical operations
1994 such as ANDN later on and substitute. */
1995 if (trailing_bits
== 0x3ff)
1997 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1998 gen_rtx_NOT (DImode
, temp
)));
2002 emit_insn (gen_rtx_SET (VOIDmode
,
2004 gen_safe_XOR64 (temp
,
2005 (-0x400 | trailing_bits
))));
2010 /* 1) sethi %hi(xxx), %reg
2011 * or %reg, %lo(xxx), %reg
2012 * sllx %reg, yyy, %reg
2014 * ??? This is just a generalized version of the low_bits==0
2015 * thing above, FIXME...
2017 if ((highest_bit_set
- lowest_bit_set
) < 32)
2019 unsigned HOST_WIDE_INT focus_bits
=
2020 create_simple_focus_bits (high_bits
, low_bits
,
2023 /* We can't get here in this state. */
2024 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2026 /* So what we know is that the set bits straddle the
2027 middle of the 64-bit word. */
2028 sparc_emit_set_const64_quick2 (op0
, temp
,
2034 /* 1) sethi %hi(high_bits), %reg
2035 * or %reg, %lo(high_bits), %reg
2036 * sllx %reg, 32, %reg
2037 * or %reg, low_bits, %reg
2039 if (SPARC_SIMM13_P(low_bits
)
2040 && ((int)low_bits
> 0))
2042 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2046 /* The easiest way when all else fails, is full decomposition. */
2047 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2049 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2051 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2052 return the mode to be used for the comparison. For floating-point,
2053 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2054 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2055 processing is needed. */
2058 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2060 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2086 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2087 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2089 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2090 return CCX_NOOVmode
;
2096 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2103 /* Emit the compare insn and return the CC reg for a CODE comparison
2104 with operands X and Y. */
2107 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2109 enum machine_mode mode
;
2112 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2115 mode
= SELECT_CC_MODE (code
, x
, y
);
2117 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2118 fcc regs (cse can't tell they're really call clobbered regs and will
2119 remove a duplicate comparison even if there is an intervening function
2120 call - it will then try to reload the cc reg via an int reg which is why
2121 we need the movcc patterns). It is possible to provide the movcc
2122 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2123 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2124 to tell cse that CCFPE mode registers (even pseudos) are call
2127 /* ??? This is an experiment. Rather than making changes to cse which may
2128 or may not be easy/clean, we do our own cse. This is possible because
2129 we will generate hard registers. Cse knows they're call clobbered (it
2130 doesn't know the same thing about pseudos). If we guess wrong, no big
2131 deal, but if we win, great! */
2133 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2134 #if 1 /* experiment */
2137 /* We cycle through the registers to ensure they're all exercised. */
2138 static int next_fcc_reg
= 0;
2139 /* Previous x,y for each fcc reg. */
2140 static rtx prev_args
[4][2];
2142 /* Scan prev_args for x,y. */
2143 for (reg
= 0; reg
< 4; reg
++)
2144 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2149 prev_args
[reg
][0] = x
;
2150 prev_args
[reg
][1] = y
;
2151 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2153 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2156 cc_reg
= gen_reg_rtx (mode
);
2157 #endif /* ! experiment */
2158 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2159 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2161 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2163 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2164 will only result in an unrecognizable insn so no point in asserting. */
2165 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2171 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2174 gen_compare_reg (rtx cmp
)
2176 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2179 /* This function is used for v9 only.
2180 DEST is the target of the Scc insn.
2181 CODE is the code for an Scc's comparison.
2182 X and Y are the values we compare.
2184 This function is needed to turn
2187 (gt (reg:CCX 100 %icc)
2191 (gt:DI (reg:CCX 100 %icc)
2194 IE: The instruction recognizer needs to see the mode of the comparison to
2195 find the right instruction. We could use "gt:DI" right in the
2196 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2199 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2202 && (GET_MODE (x
) == DImode
2203 || GET_MODE (dest
) == DImode
))
2206 /* Try to use the movrCC insns. */
2208 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2210 && v9_regcmp_p (compare_code
))
2215 /* Special case for op0 != 0. This can be done with one instruction if
2218 if (compare_code
== NE
2219 && GET_MODE (dest
) == DImode
2220 && rtx_equal_p (op0
, dest
))
2222 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2223 gen_rtx_IF_THEN_ELSE (DImode
,
2224 gen_rtx_fmt_ee (compare_code
, DImode
,
2231 if (reg_overlap_mentioned_p (dest
, op0
))
2233 /* Handle the case where dest == x.
2234 We "early clobber" the result. */
2235 op0
= gen_reg_rtx (GET_MODE (x
));
2236 emit_move_insn (op0
, x
);
2239 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2240 if (GET_MODE (op0
) != DImode
)
2242 temp
= gen_reg_rtx (DImode
);
2243 convert_move (temp
, op0
, 0);
2247 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2248 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2249 gen_rtx_fmt_ee (compare_code
, DImode
,
2257 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2260 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2261 && GET_MODE (x
) != CCX_NOOVmode
);
2263 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2264 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2265 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2266 gen_rtx_fmt_ee (compare_code
,
2267 GET_MODE (x
), x
, y
),
2268 const1_rtx
, dest
)));
2274 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2275 without jumps using the addx/subx instructions. */
2278 emit_scc_insn (rtx operands
[])
2285 /* The quad-word fp compare library routines all return nonzero to indicate
2286 true, which is different from the equivalent libgcc routines, so we must
2287 handle them specially here. */
2288 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2290 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2291 GET_CODE (operands
[1]));
2292 operands
[2] = XEXP (operands
[1], 0);
2293 operands
[3] = XEXP (operands
[1], 1);
2296 code
= GET_CODE (operands
[1]);
2300 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2301 more applications). The exception to this is "reg != 0" which can
2302 be done in one instruction on v9 (so we do it). */
2305 if (GET_MODE (x
) == SImode
)
2307 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2311 else if (GET_MODE (x
) == DImode
)
2313 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2321 if (GET_MODE (x
) == SImode
)
2323 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2327 else if (GET_MODE (x
) == DImode
)
2329 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2335 /* For the rest, on v9 we can use conditional moves. */
2339 if (gen_v9_scc (operands
[0], code
, x
, y
))
2343 /* We can do LTU and GEU using the addx/subx instructions too. And
2344 for GTU/LEU, if both operands are registers swap them and fall
2345 back to the easy case. */
2346 if (code
== GTU
|| code
== LEU
)
2348 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2349 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2354 code
= swap_condition (code
);
2358 if (code
== LTU
|| code
== GEU
)
2360 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2361 gen_rtx_fmt_ee (code
, SImode
,
2362 gen_compare_reg_1 (code
, x
, y
),
2367 /* Nope, do branches. */
2371 /* Emit a conditional jump insn for the v9 architecture using comparison code
2372 CODE and jump target LABEL.
2373 This function exists to take advantage of the v9 brxx insns. */
2376 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2378 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2380 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2381 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2383 gen_rtx_LABEL_REF (VOIDmode
, label
),
2388 emit_conditional_branch_insn (rtx operands
[])
2390 /* The quad-word fp compare library routines all return nonzero to indicate
2391 true, which is different from the equivalent libgcc routines, so we must
2392 handle them specially here. */
2393 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2395 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2396 GET_CODE (operands
[0]));
2397 operands
[1] = XEXP (operands
[0], 0);
2398 operands
[2] = XEXP (operands
[0], 1);
2401 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2402 && GET_CODE (operands
[1]) == REG
2403 && GET_MODE (operands
[1]) == DImode
)
2405 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2409 operands
[1] = gen_compare_reg (operands
[0]);
2410 operands
[2] = const0_rtx
;
2411 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2412 operands
[1], operands
[2]);
2413 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2418 /* Generate a DFmode part of a hard TFmode register.
2419 REG is the TFmode hard register, LOW is 1 for the
2420 low 64bit of the register and 0 otherwise.
2423 gen_df_reg (rtx reg
, int low
)
2425 int regno
= REGNO (reg
);
2427 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2428 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2429 return gen_rtx_REG (DFmode
, regno
);
2432 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2433 Unlike normal calls, TFmode operands are passed by reference. It is
2434 assumed that no more than 3 operands are required. */
2437 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2439 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2442 /* We only expect to be called for conversions, unary, and binary ops. */
2443 gcc_assert (nargs
== 2 || nargs
== 3);
2445 for (i
= 0; i
< nargs
; ++i
)
2447 rtx this_arg
= operands
[i
];
2450 /* TFmode arguments and return values are passed by reference. */
2451 if (GET_MODE (this_arg
) == TFmode
)
2453 int force_stack_temp
;
2455 force_stack_temp
= 0;
2456 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2457 force_stack_temp
= 1;
2459 if (GET_CODE (this_arg
) == MEM
2460 && ! force_stack_temp
)
2461 this_arg
= XEXP (this_arg
, 0);
2462 else if (CONSTANT_P (this_arg
)
2463 && ! force_stack_temp
)
2465 this_slot
= force_const_mem (TFmode
, this_arg
);
2466 this_arg
= XEXP (this_slot
, 0);
2470 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2472 /* Operand 0 is the return value. We'll copy it out later. */
2474 emit_move_insn (this_slot
, this_arg
);
2476 ret_slot
= this_slot
;
2478 this_arg
= XEXP (this_slot
, 0);
2485 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2487 if (GET_MODE (operands
[0]) == TFmode
)
2490 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2491 arg
[0], GET_MODE (arg
[0]),
2492 arg
[1], GET_MODE (arg
[1]));
2494 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2495 arg
[0], GET_MODE (arg
[0]),
2496 arg
[1], GET_MODE (arg
[1]),
2497 arg
[2], GET_MODE (arg
[2]));
2500 emit_move_insn (operands
[0], ret_slot
);
2506 gcc_assert (nargs
== 2);
2508 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2509 GET_MODE (operands
[0]), 1,
2510 arg
[1], GET_MODE (arg
[1]));
2512 if (ret
!= operands
[0])
2513 emit_move_insn (operands
[0], ret
);
2517 /* Expand soft-float TFmode calls to sparc abi routines. */
2520 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2542 emit_soft_tfmode_libcall (func
, 3, operands
);
2546 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2550 gcc_assert (code
== SQRT
);
2553 emit_soft_tfmode_libcall (func
, 2, operands
);
2557 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2564 switch (GET_MODE (operands
[1]))
2577 case FLOAT_TRUNCATE
:
2578 switch (GET_MODE (operands
[0]))
2592 switch (GET_MODE (operands
[1]))
2597 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2607 case UNSIGNED_FLOAT
:
2608 switch (GET_MODE (operands
[1]))
2613 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2624 switch (GET_MODE (operands
[0]))
2638 switch (GET_MODE (operands
[0]))
2655 emit_soft_tfmode_libcall (func
, 2, operands
);
2658 /* Expand a hard-float tfmode operation. All arguments must be in
2662 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2666 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2668 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2669 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2673 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2674 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2675 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2676 operands
[1], operands
[2]);
2679 if (register_operand (operands
[0], VOIDmode
))
2682 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2684 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2686 if (dest
!= operands
[0])
2687 emit_move_insn (operands
[0], dest
);
2691 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2693 if (TARGET_HARD_QUAD
)
2694 emit_hard_tfmode_operation (code
, operands
);
2696 emit_soft_tfmode_binop (code
, operands
);
2700 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2702 if (TARGET_HARD_QUAD
)
2703 emit_hard_tfmode_operation (code
, operands
);
2705 emit_soft_tfmode_unop (code
, operands
);
2709 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2711 if (TARGET_HARD_QUAD
)
2712 emit_hard_tfmode_operation (code
, operands
);
2714 emit_soft_tfmode_cvt (code
, operands
);
2717 /* Return nonzero if a branch/jump/call instruction will be emitting
2718 nop into its delay slot. */
2721 empty_delay_slot (rtx insn
)
2725 /* If no previous instruction (should not happen), return true. */
2726 if (PREV_INSN (insn
) == NULL
)
2729 seq
= NEXT_INSN (PREV_INSN (insn
));
2730 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2736 /* Return nonzero if TRIAL can go into the call delay slot. */
2739 tls_call_delay (rtx trial
)
2744 call __tls_get_addr, %tgd_call (foo)
2745 add %l7, %o0, %o0, %tgd_add (foo)
2746 while Sun as/ld does not. */
2747 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2750 pat
= PATTERN (trial
);
2752 /* We must reject tgd_add{32|64}, i.e.
2753 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2754 and tldm_add{32|64}, i.e.
2755 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2757 if (GET_CODE (pat
) == SET
2758 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2760 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2762 if (GET_CODE (unspec
) == UNSPEC
2763 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2764 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2771 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2772 instruction. RETURN_P is true if the v9 variant 'return' is to be
2773 considered in the test too.
2775 TRIAL must be a SET whose destination is a REG appropriate for the
2776 'restore' instruction or, if RETURN_P is true, for the 'return'
2780 eligible_for_restore_insn (rtx trial
, bool return_p
)
2782 rtx pat
= PATTERN (trial
);
2783 rtx src
= SET_SRC (pat
);
2785 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2786 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2787 && arith_operand (src
, GET_MODE (src
)))
2790 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2792 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2795 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2796 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2797 && arith_double_operand (src
, GET_MODE (src
)))
2798 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2800 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2801 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2804 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2805 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2808 /* If we have the 'return' instruction, anything that does not use
2809 local or output registers and can go into a delay slot wins. */
2812 && !epilogue_renumber (&pat
, 1)
2813 && get_attr_in_uncond_branch_delay (trial
)
2814 == IN_UNCOND_BRANCH_DELAY_TRUE
)
2817 /* The 'restore src1,src2,dest' pattern for SImode. */
2818 else if (GET_CODE (src
) == PLUS
2819 && register_operand (XEXP (src
, 0), SImode
)
2820 && arith_operand (XEXP (src
, 1), SImode
))
2823 /* The 'restore src1,src2,dest' pattern for DImode. */
2824 else if (GET_CODE (src
) == PLUS
2825 && register_operand (XEXP (src
, 0), DImode
)
2826 && arith_double_operand (XEXP (src
, 1), DImode
))
2829 /* The 'restore src1,%lo(src2),dest' pattern. */
2830 else if (GET_CODE (src
) == LO_SUM
2831 && ! TARGET_CM_MEDMID
2832 && ((register_operand (XEXP (src
, 0), SImode
)
2833 && immediate_operand (XEXP (src
, 1), SImode
))
2835 && register_operand (XEXP (src
, 0), DImode
)
2836 && immediate_operand (XEXP (src
, 1), DImode
))))
2839 /* The 'restore src,src,dest' pattern. */
2840 else if (GET_CODE (src
) == ASHIFT
2841 && (register_operand (XEXP (src
, 0), SImode
)
2842 || register_operand (XEXP (src
, 0), DImode
))
2843 && XEXP (src
, 1) == const1_rtx
)
2849 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2852 eligible_for_return_delay (rtx trial
)
2856 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2859 if (get_attr_length (trial
) != 1)
2862 /* If the function uses __builtin_eh_return, the eh_return machinery
2863 occupies the delay slot. */
2864 if (crtl
->calls_eh_return
)
2867 /* In the case of a leaf or flat function, anything can go into the slot. */
2868 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2870 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
2872 pat
= PATTERN (trial
);
2874 /* Otherwise, only operations which can be done in tandem with
2875 a `restore' or `return' insn can go into the delay slot. */
2876 if (GET_CODE (SET_DEST (pat
)) != REG
2877 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24))
2880 /* If this instruction sets up floating point register and we have a return
2881 instruction, it can probably go in. But restore will not work
2883 if (REGNO (SET_DEST (pat
)) >= 32)
2885 && !epilogue_renumber (&pat
, 1)
2886 && get_attr_in_uncond_branch_delay (trial
)
2887 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2889 return eligible_for_restore_insn (trial
, true);
2892 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
2895 eligible_for_sibcall_delay (rtx trial
)
2899 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2902 if (get_attr_length (trial
) != 1)
2905 pat
= PATTERN (trial
);
2907 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2909 /* If the tail call is done using the call instruction,
2910 we have to restore %o7 in the delay slot. */
2911 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2914 /* %g1 is used to build the function address */
2915 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2921 /* Otherwise, only operations which can be done in tandem with
2922 a `restore' insn can go into the delay slot. */
2923 if (GET_CODE (SET_DEST (pat
)) != REG
2924 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2925 || REGNO (SET_DEST (pat
)) >= 32)
2928 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2930 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2933 return eligible_for_restore_insn (trial
, false);
2937 short_branch (int uid1
, int uid2
)
2939 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2941 /* Leave a few words of "slop". */
2942 if (delta
>= -1023 && delta
<= 1022)
2948 /* Return nonzero if REG is not used after INSN.
2949 We assume REG is a reload reg, and therefore does
2950 not live past labels or calls or jumps. */
2952 reg_unused_after (rtx reg
, rtx insn
)
2954 enum rtx_code code
, prev_code
= UNKNOWN
;
2956 while ((insn
= NEXT_INSN (insn
)))
2958 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2961 code
= GET_CODE (insn
);
2962 if (GET_CODE (insn
) == CODE_LABEL
)
2967 rtx set
= single_set (insn
);
2968 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2971 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2973 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2981 /* Determine if it's legal to put X into the constant pool. This
2982 is not possible if X contains the address of a symbol that is
2983 not constant (TLS) or not known at final link time (PIC). */
2986 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2988 switch (GET_CODE (x
))
2993 /* Accept all non-symbolic constants. */
2997 /* Labels are OK iff we are non-PIC. */
2998 return flag_pic
!= 0;
3001 /* 'Naked' TLS symbol references are never OK,
3002 non-TLS symbols are OK iff we are non-PIC. */
3003 if (SYMBOL_REF_TLS_MODEL (x
))
3006 return flag_pic
!= 0;
3009 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3012 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3013 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3021 /* Global Offset Table support. */
3022 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3023 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3025 /* Return the SYMBOL_REF for the Global Offset Table. */
3027 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3032 if (!sparc_got_symbol
)
3033 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3035 return sparc_got_symbol
;
3038 /* Ensure that we are not using patterns that are not OK with PIC. */
3048 op
= recog_data
.operand
[i
];
3049 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3050 && (GET_CODE (op
) != CONST
3051 || (GET_CODE (XEXP (op
, 0)) == MINUS
3052 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3053 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3060 /* Return true if X is an address which needs a temporary register when
3061 reloaded while generating PIC code. */
3064 pic_address_needs_scratch (rtx x
)
3066 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3067 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3068 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3069 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3070 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3076 /* Determine if a given RTX is a valid constant. We already know this
3077 satisfies CONSTANT_P. */
3080 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3082 switch (GET_CODE (x
))
3086 if (sparc_tls_referenced_p (x
))
3091 if (GET_MODE (x
) == VOIDmode
)
3094 /* Floating point constants are generally not ok.
3095 The only exception is 0.0 in VIS. */
3097 && SCALAR_FLOAT_MODE_P (mode
)
3098 && const_zero_operand (x
, mode
))
3104 /* Vector constants are generally not ok.
3105 The only exception is 0 in VIS. */
3107 && const_zero_operand (x
, mode
))
3119 /* Determine if a given RTX is a valid constant address. */
3122 constant_address_p (rtx x
)
3124 switch (GET_CODE (x
))
3132 if (flag_pic
&& pic_address_needs_scratch (x
))
3134 return sparc_legitimate_constant_p (Pmode
, x
);
3137 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3144 /* Nonzero if the constant value X is a legitimate general operand
3145 when generating PIC code. It is given that flag_pic is on and
3146 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3149 legitimate_pic_operand_p (rtx x
)
3151 if (pic_address_needs_scratch (x
))
3153 if (sparc_tls_referenced_p (x
))
3158 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3160 && INTVAL (X) >= -0x1000 \
3161 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3163 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3165 && INTVAL (X) >= -0x1000 \
3166 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3168 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3170 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3171 ordinarily. This changes a bit when generating PIC. */
3174 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3176 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3178 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3180 else if (GET_CODE (addr
) == PLUS
)
3182 rs1
= XEXP (addr
, 0);
3183 rs2
= XEXP (addr
, 1);
3185 /* Canonicalize. REG comes first, if there are no regs,
3186 LO_SUM comes first. */
3188 && GET_CODE (rs1
) != SUBREG
3190 || GET_CODE (rs2
) == SUBREG
3191 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3193 rs1
= XEXP (addr
, 1);
3194 rs2
= XEXP (addr
, 0);
3198 && rs1
== pic_offset_table_rtx
3200 && GET_CODE (rs2
) != SUBREG
3201 && GET_CODE (rs2
) != LO_SUM
3202 && GET_CODE (rs2
) != MEM
3203 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3204 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3205 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3207 || GET_CODE (rs1
) == SUBREG
)
3208 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3213 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3214 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3216 /* We prohibit REG + REG for TFmode when there are no quad move insns
3217 and we consequently need to split. We do this because REG+REG
3218 is not an offsettable address. If we get the situation in reload
3219 where source and destination of a movtf pattern are both MEMs with
3220 REG+REG address, then only one of them gets converted to an
3221 offsettable address. */
3223 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3226 /* We prohibit REG + REG on ARCH32 if not optimizing for
3227 DFmode/DImode because then mem_min_alignment is likely to be zero
3228 after reload and the forced split would lack a matching splitter
3230 if (TARGET_ARCH32
&& !optimize
3231 && (mode
== DFmode
|| mode
== DImode
))
3234 else if (USE_AS_OFFSETABLE_LO10
3235 && GET_CODE (rs1
) == LO_SUM
3237 && ! TARGET_CM_MEDMID
3238 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3241 imm1
= XEXP (rs1
, 1);
3242 rs1
= XEXP (rs1
, 0);
3243 if (!CONSTANT_P (imm1
)
3244 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3248 else if (GET_CODE (addr
) == LO_SUM
)
3250 rs1
= XEXP (addr
, 0);
3251 imm1
= XEXP (addr
, 1);
3253 if (!CONSTANT_P (imm1
)
3254 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3257 /* We can't allow TFmode in 32-bit mode, because an offset greater
3258 than the alignment (8) may cause the LO_SUM to overflow. */
3259 if (mode
== TFmode
&& TARGET_ARCH32
)
3262 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3267 if (GET_CODE (rs1
) == SUBREG
)
3268 rs1
= SUBREG_REG (rs1
);
3274 if (GET_CODE (rs2
) == SUBREG
)
3275 rs2
= SUBREG_REG (rs2
);
3282 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3283 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3288 if ((REGNO (rs1
) >= 32
3289 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3290 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3292 && (REGNO (rs2
) >= 32
3293 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3294 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3300 /* Return the SYMBOL_REF for the tls_get_addr function. */
3302 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3305 sparc_tls_get_addr (void)
3307 if (!sparc_tls_symbol
)
3308 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3310 return sparc_tls_symbol
;
3313 /* Return the Global Offset Table to be used in TLS mode. */
3316 sparc_tls_got (void)
3318 /* In PIC mode, this is just the PIC offset table. */
3321 crtl
->uses_pic_offset_table
= 1;
3322 return pic_offset_table_rtx
;
3325 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3326 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3327 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3329 load_got_register ();
3330 return global_offset_table_rtx
;
3333 /* In all other cases, we load a new pseudo with the GOT symbol. */
3334 return copy_to_reg (sparc_got ());
3337 /* Return true if X contains a thread-local symbol. */
3340 sparc_tls_referenced_p (rtx x
)
3342 if (!TARGET_HAVE_TLS
)
3345 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3346 x
= XEXP (XEXP (x
, 0), 0);
3348 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3351 /* That's all we handle in sparc_legitimize_tls_address for now. */
3355 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3356 this (thread-local) address. */
3359 sparc_legitimize_tls_address (rtx addr
)
3361 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3363 gcc_assert (can_create_pseudo_p ());
3365 if (GET_CODE (addr
) == SYMBOL_REF
)
3366 switch (SYMBOL_REF_TLS_MODEL (addr
))
3368 case TLS_MODEL_GLOBAL_DYNAMIC
:
3370 temp1
= gen_reg_rtx (SImode
);
3371 temp2
= gen_reg_rtx (SImode
);
3372 ret
= gen_reg_rtx (Pmode
);
3373 o0
= gen_rtx_REG (Pmode
, 8);
3374 got
= sparc_tls_got ();
3375 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3376 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3379 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3380 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3385 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3386 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3389 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3390 insn
= get_insns ();
3392 emit_libcall_block (insn
, ret
, o0
, addr
);
3395 case TLS_MODEL_LOCAL_DYNAMIC
:
3397 temp1
= gen_reg_rtx (SImode
);
3398 temp2
= gen_reg_rtx (SImode
);
3399 temp3
= gen_reg_rtx (Pmode
);
3400 ret
= gen_reg_rtx (Pmode
);
3401 o0
= gen_rtx_REG (Pmode
, 8);
3402 got
= sparc_tls_got ();
3403 emit_insn (gen_tldm_hi22 (temp1
));
3404 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3407 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3408 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3413 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3414 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3417 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3418 insn
= get_insns ();
3420 emit_libcall_block (insn
, temp3
, o0
,
3421 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3422 UNSPEC_TLSLD_BASE
));
3423 temp1
= gen_reg_rtx (SImode
);
3424 temp2
= gen_reg_rtx (SImode
);
3425 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3426 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3428 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3430 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3433 case TLS_MODEL_INITIAL_EXEC
:
3434 temp1
= gen_reg_rtx (SImode
);
3435 temp2
= gen_reg_rtx (SImode
);
3436 temp3
= gen_reg_rtx (Pmode
);
3437 got
= sparc_tls_got ();
3438 emit_insn (gen_tie_hi22 (temp1
, addr
));
3439 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3441 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3443 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3446 ret
= gen_reg_rtx (Pmode
);
3448 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3451 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3455 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3458 case TLS_MODEL_LOCAL_EXEC
:
3459 temp1
= gen_reg_rtx (Pmode
);
3460 temp2
= gen_reg_rtx (Pmode
);
3463 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3464 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3468 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3469 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3471 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3478 else if (GET_CODE (addr
) == CONST
)
3482 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3484 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3485 offset
= XEXP (XEXP (addr
, 0), 1);
3487 base
= force_operand (base
, NULL_RTX
);
3488 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3489 offset
= force_reg (Pmode
, offset
);
3490 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3494 gcc_unreachable (); /* for now ... */
3499 /* Legitimize PIC addresses. If the address is already position-independent,
3500 we return ORIG. Newly generated position-independent addresses go into a
3501 reg. This is REG if nonzero, otherwise we allocate register(s) as
3505 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3507 bool gotdata_op
= false;
3509 if (GET_CODE (orig
) == SYMBOL_REF
3510 /* See the comment in sparc_expand_move. */
3511 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3513 rtx pic_ref
, address
;
3518 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3519 reg
= gen_reg_rtx (Pmode
);
3524 /* If not during reload, allocate another temp reg here for loading
3525 in the address, so that these instructions can be optimized
3527 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3528 ? reg
: gen_reg_rtx (Pmode
));
3530 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3531 won't get confused into thinking that these two instructions
3532 are loading in the true address of the symbol. If in the
3533 future a PIC rtx exists, that should be used instead. */
3536 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3537 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3541 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3542 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3550 crtl
->uses_pic_offset_table
= 1;
3554 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3555 pic_offset_table_rtx
,
3558 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3559 pic_offset_table_rtx
,
3565 = gen_const_mem (Pmode
,
3566 gen_rtx_PLUS (Pmode
,
3567 pic_offset_table_rtx
, address
));
3568 insn
= emit_move_insn (reg
, pic_ref
);
3571 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3573 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3576 else if (GET_CODE (orig
) == CONST
)
3580 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3581 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3586 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3587 reg
= gen_reg_rtx (Pmode
);
3590 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3591 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3592 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3593 base
== reg
? NULL_RTX
: reg
);
3595 if (GET_CODE (offset
) == CONST_INT
)
3597 if (SMALL_INT (offset
))
3598 return plus_constant (base
, INTVAL (offset
));
3599 else if (! reload_in_progress
&& ! reload_completed
)
3600 offset
= force_reg (Pmode
, offset
);
3602 /* If we reach here, then something is seriously wrong. */
3605 return gen_rtx_PLUS (Pmode
, base
, offset
);
3607 else if (GET_CODE (orig
) == LABEL_REF
)
3608 /* ??? We ought to be checking that the register is live instead, in case
3609 it is eliminated. */
3610 crtl
->uses_pic_offset_table
= 1;
3615 /* Try machine-dependent ways of modifying an illegitimate address X
3616 to be legitimate. If we find one, return the new, valid address.
3618 OLDX is the address as it was before break_out_memory_refs was called.
3619 In some cases it is useful to look at this to decide what needs to be done.
3621 MODE is the mode of the operand pointed to by X.
3623 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3626 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3627 enum machine_mode mode
)
3631 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3632 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3633 force_operand (XEXP (x
, 0), NULL_RTX
));
3634 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3635 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3636 force_operand (XEXP (x
, 1), NULL_RTX
));
3637 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3638 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3640 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3641 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3642 force_operand (XEXP (x
, 1), NULL_RTX
));
3644 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3647 if (sparc_tls_referenced_p (x
))
3648 x
= sparc_legitimize_tls_address (x
);
3650 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
3651 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3652 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3653 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3654 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3655 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3656 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3657 else if (GET_CODE (x
) == SYMBOL_REF
3658 || GET_CODE (x
) == CONST
3659 || GET_CODE (x
) == LABEL_REF
)
3660 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3665 /* Delegitimize an address that was legitimized by the above function. */
3668 sparc_delegitimize_address (rtx x
)
3670 x
= delegitimize_mem_from_attrs (x
);
3672 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
3673 switch (XINT (XEXP (x
, 1), 1))
3675 case UNSPEC_MOVE_PIC
:
3677 x
= XVECEXP (XEXP (x
, 1), 0, 0);
3678 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3684 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3685 if (GET_CODE (x
) == MINUS
3686 && REG_P (XEXP (x
, 0))
3687 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
3688 && GET_CODE (XEXP (x
, 1)) == LO_SUM
3689 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
3690 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
3692 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
3693 gcc_assert (GET_CODE (x
) == LABEL_REF
);
3699 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3700 replace the input X, or the original X if no replacement is called for.
3701 The output parameter *WIN is 1 if the calling macro should goto WIN,
3704 For SPARC, we wish to handle addresses by splitting them into
3705 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3706 This cuts the number of extra insns by one.
3708 Do nothing when generating PIC code and the address is a symbolic
3709 operand or requires a scratch register. */
3712 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3713 int opnum
, int type
,
3714 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3716 /* Decompose SImode constants into HIGH+LO_SUM. */
3718 && (mode
!= TFmode
|| TARGET_ARCH64
)
3719 && GET_MODE (x
) == SImode
3720 && GET_CODE (x
) != LO_SUM
3721 && GET_CODE (x
) != HIGH
3722 && sparc_cmodel
<= CM_MEDLOW
3724 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
3726 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
3727 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3728 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3729 opnum
, (enum reload_type
)type
);
3734 /* We have to recognize what we have already generated above. */
3735 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
3737 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3738 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3739 opnum
, (enum reload_type
)type
);
3748 /* Return true if ADDR (a legitimate address expression)
3749 has an effect that depends on the machine mode it is used for.
3755 is not equivalent to
3757 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3759 because [%l7+a+1] is interpreted as the address of (a+1). */
3763 sparc_mode_dependent_address_p (const_rtx addr
)
3765 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
3767 rtx op0
= XEXP (addr
, 0);
3768 rtx op1
= XEXP (addr
, 1);
3769 if (op0
== pic_offset_table_rtx
3770 && symbolic_operand (op1
, VOIDmode
))
3777 #ifdef HAVE_GAS_HIDDEN
3778 # define USE_HIDDEN_LINKONCE 1
3780 # define USE_HIDDEN_LINKONCE 0
3784 get_pc_thunk_name (char name
[32], unsigned int regno
)
3786 const char *reg_name
= reg_names
[regno
];
3788 /* Skip the leading '%' as that cannot be used in a
3792 if (USE_HIDDEN_LINKONCE
)
3793 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
3795 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3798 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3801 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
3803 int orig_flag_pic
= flag_pic
;
3806 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3809 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
3811 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
3812 flag_pic
= orig_flag_pic
;
3817 /* Emit code to load the GOT register. */
3820 load_got_register (void)
3822 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3823 if (!global_offset_table_rtx
)
3824 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
3826 if (TARGET_VXWORKS_RTP
)
3827 emit_insn (gen_vxworks_load_got ());
3830 /* The GOT symbol is subject to a PC-relative relocation so we need a
3831 helper function to add the PC value and thus get the final value. */
3832 if (!got_helper_rtx
)
3835 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
3836 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3839 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
3841 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
3844 /* Need to emit this whether or not we obey regdecls,
3845 since setjmp/longjmp can cause life info to screw up.
3846 ??? In the case where we don't obey regdecls, this is not sufficient
3847 since we may not fall out the bottom. */
3848 emit_use (global_offset_table_rtx
);
3851 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3852 address of the call target. */
3855 sparc_emit_call_insn (rtx pat
, rtx addr
)
3859 insn
= emit_call_insn (pat
);
3861 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3862 if (TARGET_VXWORKS_RTP
3864 && GET_CODE (addr
) == SYMBOL_REF
3865 && (SYMBOL_REF_DECL (addr
)
3866 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
3867 : !SYMBOL_REF_LOCAL_P (addr
)))
3869 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3870 crtl
->uses_pic_offset_table
= 1;
3874 /* Return 1 if RTX is a MEM which is known to be aligned to at
3875 least a DESIRED byte boundary. */
3878 mem_min_alignment (rtx mem
, int desired
)
3880 rtx addr
, base
, offset
;
3882 /* If it's not a MEM we can't accept it. */
3883 if (GET_CODE (mem
) != MEM
)
3887 if (!TARGET_UNALIGNED_DOUBLES
3888 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3891 /* ??? The rest of the function predates MEM_ALIGN so
3892 there is probably a bit of redundancy. */
3893 addr
= XEXP (mem
, 0);
3894 base
= offset
= NULL_RTX
;
3895 if (GET_CODE (addr
) == PLUS
)
3897 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3899 base
= XEXP (addr
, 0);
3901 /* What we are saying here is that if the base
3902 REG is aligned properly, the compiler will make
3903 sure any REG based index upon it will be so
3905 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3906 offset
= XEXP (addr
, 1);
3908 offset
= const0_rtx
;
3911 else if (GET_CODE (addr
) == REG
)
3914 offset
= const0_rtx
;
3917 if (base
!= NULL_RTX
)
3919 int regno
= REGNO (base
);
3921 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3923 /* Check if the compiler has recorded some information
3924 about the alignment of the base REG. If reload has
3925 completed, we already matched with proper alignments.
3926 If not running global_alloc, reload might give us
3927 unaligned pointer to local stack though. */
3929 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3930 || (optimize
&& reload_completed
))
3931 && (INTVAL (offset
) & (desired
- 1)) == 0)
3936 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3940 else if (! TARGET_UNALIGNED_DOUBLES
3941 || CONSTANT_P (addr
)
3942 || GET_CODE (addr
) == LO_SUM
)
3944 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3945 is true, in which case we can only assume that an access is aligned if
3946 it is to a constant address, or the address involves a LO_SUM. */
3950 /* An obviously unaligned address. */
3955 /* Vectors to keep interesting information about registers where it can easily
3956 be got. We used to use the actual mode value as the bit number, but there
3957 are more than 32 modes now. Instead we use two tables: one indexed by
3958 hard register number, and one indexed by mode. */
3960 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3961 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
3962 mapped into one sparc_mode_class mode. */
3964 enum sparc_mode_class
{
3965 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3966 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3970 /* Modes for single-word and smaller quantities. */
3971 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3973 /* Modes for double-word and smaller quantities. */
3974 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3976 /* Modes for quad-word and smaller quantities. */
3977 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3979 /* Modes for 8-word and smaller quantities. */
3980 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3982 /* Modes for single-float quantities. We must allow any single word or
3983 smaller quantity. This is because the fix/float conversion instructions
3984 take integer inputs/outputs from the float registers. */
3985 #define SF_MODES (S_MODES)
3987 /* Modes for double-float and smaller quantities. */
3988 #define DF_MODES (D_MODES)
3990 /* Modes for quad-float and smaller quantities. */
3991 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
3993 /* Modes for quad-float pairs and smaller quantities. */
3994 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
3996 /* Modes for double-float only quantities. */
3997 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3999 /* Modes for quad-float and double-float only quantities. */
4000 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4002 /* Modes for quad-float pairs and double-float only quantities. */
4003 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4005 /* Modes for condition codes. */
4006 #define CC_MODES (1 << (int) CC_MODE)
4007 #define CCFP_MODES (1 << (int) CCFP_MODE)
4009 /* Value is 1 if register/mode pair is acceptable on sparc.
4010 The funny mixture of D and T modes is because integer operations
4011 do not specially operate on tetra quantities, so non-quad-aligned
4012 registers can hold quadword quantities (except %o4 and %i4 because
4013 they cross fixed registers). */
4015 /* This points to either the 32 bit or the 64 bit version. */
4016 const int *hard_regno_mode_classes
;
4018 static const int hard_32bit_mode_classes
[] = {
4019 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4020 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4021 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4022 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4024 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4025 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4026 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4027 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4029 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4030 and none can hold SFmode/SImode values. */
4031 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4032 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4033 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4034 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4037 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4043 static const int hard_64bit_mode_classes
[] = {
4044 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4045 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4046 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4047 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4049 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4050 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4051 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4052 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4054 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4055 and none can hold SFmode/SImode values. */
4056 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4057 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4058 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4059 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4062 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4068 int sparc_mode_class
[NUM_MACHINE_MODES
];
4070 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4073 sparc_init_modes (void)
4077 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4079 switch (GET_MODE_CLASS (i
))
4082 case MODE_PARTIAL_INT
:
4083 case MODE_COMPLEX_INT
:
4084 if (GET_MODE_SIZE (i
) <= 4)
4085 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4086 else if (GET_MODE_SIZE (i
) == 8)
4087 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4088 else if (GET_MODE_SIZE (i
) == 16)
4089 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4090 else if (GET_MODE_SIZE (i
) == 32)
4091 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4093 sparc_mode_class
[i
] = 0;
4095 case MODE_VECTOR_INT
:
4096 if (GET_MODE_SIZE (i
) <= 4)
4097 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4098 else if (GET_MODE_SIZE (i
) == 8)
4099 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4102 case MODE_COMPLEX_FLOAT
:
4103 if (GET_MODE_SIZE (i
) <= 4)
4104 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4105 else if (GET_MODE_SIZE (i
) == 8)
4106 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4107 else if (GET_MODE_SIZE (i
) == 16)
4108 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4109 else if (GET_MODE_SIZE (i
) == 32)
4110 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4112 sparc_mode_class
[i
] = 0;
4115 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4116 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4118 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4121 sparc_mode_class
[i
] = 0;
4127 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4129 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4131 /* Initialize the array used by REGNO_REG_CLASS. */
4132 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4134 if (i
< 16 && TARGET_V8PLUS
)
4135 sparc_regno_reg_class
[i
] = I64_REGS
;
4136 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4137 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4139 sparc_regno_reg_class
[i
] = FP_REGS
;
4141 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4143 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4145 sparc_regno_reg_class
[i
] = NO_REGS
;
4149 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4152 save_global_or_fp_reg_p (unsigned int regno
,
4153 int leaf_function ATTRIBUTE_UNUSED
)
4155 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4158 /* Return whether the return address register (%i7) is needed. */
4161 return_addr_reg_needed_p (int leaf_function
)
4163 /* If it is live, for example because of __builtin_return_address (0). */
4164 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4167 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4169 /* Loading the GOT register clobbers %o7. */
4170 || crtl
->uses_pic_offset_table
4171 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4177 /* Return whether REGNO, a local or in register, must be saved/restored. */
4180 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4182 /* General case: call-saved registers live at some point. */
4183 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4186 /* Frame pointer register (%fp) if needed. */
4187 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4190 /* Return address register (%i7) if needed. */
4191 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4194 /* GOT register (%l7) if needed. */
4195 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4198 /* If the function accesses prior frames, the frame pointer and the return
4199 address of the previous frame must be saved on the stack. */
4200 if (crtl
->accesses_prior_frames
4201 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4207 /* Compute the frame size required by the function. This function is called
4208 during the reload pass and also by sparc_expand_prologue. */
4211 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4213 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4214 int args_size
, n_global_fp_regs
= 0;
4215 bool save_local_in_regs_p
= false;
4218 /* If the function allocates dynamic stack space, the dynamic offset is
4219 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4220 if (leaf_function
&& !cfun
->calls_alloca
)
4223 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4225 /* Calculate space needed for global registers. */
4227 for (i
= 0; i
< 8; i
++)
4228 if (save_global_or_fp_reg_p (i
, 0))
4229 n_global_fp_regs
+= 2;
4231 for (i
= 0; i
< 8; i
+= 2)
4232 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4233 n_global_fp_regs
+= 2;
4235 /* In the flat window model, find out which local and in registers need to
4236 be saved. We don't reserve space in the current frame for them as they
4237 will be spilled into the register window save area of the caller's frame.
4238 However, as soon as we use this register window save area, we must create
4239 that of the current frame to make it the live one. */
4241 for (i
= 16; i
< 32; i
++)
4242 if (save_local_or_in_reg_p (i
, leaf_function
))
4244 save_local_in_regs_p
= true;
4248 /* Calculate space needed for FP registers. */
4249 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4250 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4251 n_global_fp_regs
+= 2;
4254 && n_global_fp_regs
== 0
4256 && !save_local_in_regs_p
)
4257 frame_size
= apparent_frame_size
= 0;
4260 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4261 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4262 apparent_frame_size
+= n_global_fp_regs
* 4;
4264 /* We need to add the size of the outgoing argument area. */
4265 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4267 /* And that of the register window save area. */
4268 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4270 /* Finally, bump to the appropriate alignment. */
4271 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4274 /* Set up values for use in prologue and epilogue. */
4275 sparc_frame_size
= frame_size
;
4276 sparc_apparent_frame_size
= apparent_frame_size
;
4277 sparc_n_global_fp_regs
= n_global_fp_regs
;
4278 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4283 /* Output any necessary .register pseudo-ops. */
4286 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4288 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4294 /* Check if %g[2367] were used without
4295 .register being printed for them already. */
4296 for (i
= 2; i
< 8; i
++)
4298 if (df_regs_ever_live_p (i
)
4299 && ! sparc_hard_reg_printed
[i
])
4301 sparc_hard_reg_printed
[i
] = 1;
4302 /* %g7 is used as TLS base register, use #ignore
4303 for it instead of #scratch. */
4304 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4305 i
== 7 ? "ignore" : "scratch");
4312 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4314 #if PROBE_INTERVAL > 4096
4315 #error Cannot use indexed addressing mode for stack probing
4318 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4319 inclusive. These are offsets from the current stack pointer.
4321 Note that we don't use the REG+REG addressing mode for the probes because
4322 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4323 so the advantages of having a single code win here. */
4326 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4328 rtx g1
= gen_rtx_REG (Pmode
, 1);
4330 /* See if we have a constant small number of probes to generate. If so,
4331 that's the easy case. */
4332 if (size
<= PROBE_INTERVAL
)
4334 emit_move_insn (g1
, GEN_INT (first
));
4335 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4336 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4337 emit_stack_probe (plus_constant (g1
, -size
));
4340 /* The run-time loop is made up of 10 insns in the generic case while the
4341 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4342 else if (size
<= 5 * PROBE_INTERVAL
)
4346 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4347 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4348 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4349 emit_stack_probe (g1
);
4351 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4352 it exceeds SIZE. If only two probes are needed, this will not
4353 generate any code. Then probe at FIRST + SIZE. */
4354 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4356 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4357 plus_constant (g1
, -PROBE_INTERVAL
)));
4358 emit_stack_probe (g1
);
4361 emit_stack_probe (plus_constant (g1
, (i
- PROBE_INTERVAL
) - size
));
4364 /* Otherwise, do the same as above, but in a loop. Note that we must be
4365 extra careful with variables wrapping around because we might be at
4366 the very top (or the very bottom) of the address space and we have
4367 to be able to handle this case properly; in particular, we use an
4368 equality test for the loop condition. */
4371 HOST_WIDE_INT rounded_size
;
4372 rtx g4
= gen_rtx_REG (Pmode
, 4);
4374 emit_move_insn (g1
, GEN_INT (first
));
4377 /* Step 1: round SIZE to the previous multiple of the interval. */
4379 rounded_size
= size
& -PROBE_INTERVAL
;
4380 emit_move_insn (g4
, GEN_INT (rounded_size
));
4383 /* Step 2: compute initial and final value of the loop counter. */
4385 /* TEST_ADDR = SP + FIRST. */
4386 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4387 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4389 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4390 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4395 while (TEST_ADDR != LAST_ADDR)
4397 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4401 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4402 until it is equal to ROUNDED_SIZE. */
4405 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4407 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4410 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4411 that SIZE is equal to ROUNDED_SIZE. */
4413 if (size
!= rounded_size
)
4414 emit_stack_probe (plus_constant (g4
, rounded_size
- size
));
4417 /* Make sure nothing is scheduled before we are done. */
4418 emit_insn (gen_blockage ());
4421 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4422 absolute addresses. */
4425 output_probe_stack_range (rtx reg1
, rtx reg2
)
4427 static int labelno
= 0;
4428 char loop_lab
[32], end_lab
[32];
4431 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4432 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4434 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4436 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4439 output_asm_insn ("cmp\t%0, %1", xops
);
4441 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4443 fputs ("\tbe\t", asm_out_file
);
4444 assemble_name_raw (asm_out_file
, end_lab
);
4445 fputc ('\n', asm_out_file
);
4447 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4448 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4449 output_asm_insn (" add\t%0, %1, %0", xops
);
4451 /* Probe at TEST_ADDR and branch. */
4453 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4455 fputs ("\tba\t", asm_out_file
);
4456 assemble_name_raw (asm_out_file
, loop_lab
);
4457 fputc ('\n', asm_out_file
);
4458 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4459 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4461 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4466 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4467 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4468 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4469 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4470 the action to be performed if it returns false. Return the new offset. */
4472 typedef bool (*sorr_pred_t
) (unsigned int, int);
4473 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4476 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4477 int offset
, int leaf_function
, sorr_pred_t save_p
,
4478 sorr_act_t action_true
, sorr_act_t action_false
)
4483 if (TARGET_ARCH64
&& high
<= 32)
4487 for (i
= low
; i
< high
; i
++)
4489 if (save_p (i
, leaf_function
))
4491 mem
= gen_frame_mem (DImode
, plus_constant (base
, offset
));
4492 if (action_true
== SORR_SAVE
)
4494 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4495 RTX_FRAME_RELATED_P (insn
) = 1;
4497 else /* action_true == SORR_RESTORE */
4499 /* The frame pointer must be restored last since its old
4500 value may be used as base address for the frame. This
4501 is problematic in 64-bit mode only because of the lack
4502 of double-word load instruction. */
4503 if (i
== HARD_FRAME_POINTER_REGNUM
)
4506 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4510 else if (action_false
== SORR_ADVANCE
)
4516 mem
= gen_frame_mem (DImode
, plus_constant (base
, fp_offset
));
4517 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4522 for (i
= low
; i
< high
; i
+= 2)
4524 bool reg0
= save_p (i
, leaf_function
);
4525 bool reg1
= save_p (i
+ 1, leaf_function
);
4526 enum machine_mode mode
;
4531 mode
= i
< 32 ? DImode
: DFmode
;
4536 mode
= i
< 32 ? SImode
: SFmode
;
4541 mode
= i
< 32 ? SImode
: SFmode
;
4547 if (action_false
== SORR_ADVANCE
)
4552 mem
= gen_frame_mem (mode
, plus_constant (base
, offset
));
4553 if (action_true
== SORR_SAVE
)
4555 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4556 RTX_FRAME_RELATED_P (insn
) = 1;
4560 mem
= gen_frame_mem (SImode
, plus_constant (base
, offset
));
4561 set1
= gen_rtx_SET (VOIDmode
, mem
,
4562 gen_rtx_REG (SImode
, regno
));
4563 RTX_FRAME_RELATED_P (set1
) = 1;
4565 = gen_frame_mem (SImode
, plus_constant (base
, offset
+ 4));
4566 set2
= gen_rtx_SET (VOIDmode
, mem
,
4567 gen_rtx_REG (SImode
, regno
+ 1));
4568 RTX_FRAME_RELATED_P (set2
) = 1;
4569 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4570 gen_rtx_PARALLEL (VOIDmode
,
4571 gen_rtvec (2, set1
, set2
)));
4574 else /* action_true == SORR_RESTORE */
4575 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4577 /* Always preserve double-word alignment. */
4578 offset
= (offset
+ 8) & -8;
4585 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4588 emit_adjust_base_to_offset (rtx base
, int offset
)
4590 /* ??? This might be optimized a little as %g1 might already have a
4591 value close enough that a single add insn will do. */
4592 /* ??? Although, all of this is probably only a temporary fix because
4593 if %g1 can hold a function result, then sparc_expand_epilogue will
4594 lose (the result will be clobbered). */
4595 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4596 emit_move_insn (new_base
, GEN_INT (offset
));
4597 emit_insn (gen_rtx_SET (VOIDmode
,
4598 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4602 /* Emit code to save/restore call-saved global and FP registers. */
4605 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4607 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4609 base
= emit_adjust_base_to_offset (base
, offset
);
4614 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4615 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4616 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4617 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4620 /* Emit code to save/restore call-saved local and in registers. */
4623 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
4625 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
4627 base
= emit_adjust_base_to_offset (base
, offset
);
4631 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
4632 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
4635 /* Emit a window_save insn. */
4638 emit_window_save (rtx increment
)
4640 rtx insn
= emit_insn (gen_window_save (increment
));
4641 RTX_FRAME_RELATED_P (insn
) = 1;
4643 /* The incoming return address (%o7) is saved in %i7. */
4644 add_reg_note (insn
, REG_CFA_REGISTER
,
4645 gen_rtx_SET (VOIDmode
,
4646 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
4648 INCOMING_RETURN_ADDR_REGNUM
)));
4650 /* The window save event. */
4651 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
4653 /* The CFA is %fp, the hard frame pointer. */
4654 add_reg_note (insn
, REG_CFA_DEF_CFA
,
4655 plus_constant (hard_frame_pointer_rtx
,
4656 INCOMING_FRAME_SP_OFFSET
));
4661 /* Generate an increment for the stack pointer. */
4664 gen_stack_pointer_inc (rtx increment
)
4666 return gen_rtx_SET (VOIDmode
,
4668 gen_rtx_PLUS (Pmode
,
4673 /* Generate a decrement for the stack pointer. */
4676 gen_stack_pointer_dec (rtx decrement
)
4678 return gen_rtx_SET (VOIDmode
,
4680 gen_rtx_MINUS (Pmode
,
4685 /* Expand the function prologue. The prologue is responsible for reserving
4686 storage for the frame, saving the call-saved registers and loading the
4687 GOT register if needed. */
4690 sparc_expand_prologue (void)
4695 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4696 on the final value of the flag means deferring the prologue/epilogue
4697 expansion until just before the second scheduling pass, which is too
4698 late to emit multiple epilogues or return insns.
4700 Of course we are making the assumption that the value of the flag
4701 will not change between now and its final value. Of the three parts
4702 of the formula, only the last one can reasonably vary. Let's take a
4703 closer look, after assuming that the first two ones are set to true
4704 (otherwise the last value is effectively silenced).
4706 If only_leaf_regs_used returns false, the global predicate will also
4707 be false so the actual frame size calculated below will be positive.
4708 As a consequence, the save_register_window insn will be emitted in
4709 the instruction stream; now this insn explicitly references %fp
4710 which is not a leaf register so only_leaf_regs_used will always
4711 return false subsequently.
4713 If only_leaf_regs_used returns true, we hope that the subsequent
4714 optimization passes won't cause non-leaf registers to pop up. For
4715 example, the regrename pass has special provisions to not rename to
4716 non-leaf registers in a leaf function. */
4717 sparc_leaf_function_p
4718 = optimize
> 0 && current_function_is_leaf
&& only_leaf_regs_used ();
4720 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4722 if (flag_stack_usage_info
)
4723 current_function_static_stack_size
= size
;
4725 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4726 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4730 else if (sparc_leaf_function_p
)
4732 rtx size_int_rtx
= GEN_INT (-size
);
4735 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4736 else if (size
<= 8192)
4738 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4739 /* %sp is still the CFA register. */
4740 RTX_FRAME_RELATED_P (insn
) = 1;
4741 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4745 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4746 emit_move_insn (size_rtx
, size_int_rtx
);
4747 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4748 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4749 gen_stack_pointer_inc (size_int_rtx
));
4752 RTX_FRAME_RELATED_P (insn
) = 1;
4756 rtx size_int_rtx
= GEN_INT (-size
);
4759 emit_window_save (size_int_rtx
);
4760 else if (size
<= 8192)
4762 emit_window_save (GEN_INT (-4096));
4763 /* %sp is not the CFA register anymore. */
4764 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4768 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4769 emit_move_insn (size_rtx
, size_int_rtx
);
4770 emit_window_save (size_rtx
);
4774 if (sparc_leaf_function_p
)
4776 sparc_frame_base_reg
= stack_pointer_rtx
;
4777 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4781 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4782 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4785 if (sparc_n_global_fp_regs
> 0)
4786 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4787 sparc_frame_base_offset
4788 - sparc_apparent_frame_size
,
4791 /* Load the GOT register if needed. */
4792 if (crtl
->uses_pic_offset_table
)
4793 load_got_register ();
4795 /* Advertise that the data calculated just above are now valid. */
4796 sparc_prologue_data_valid_p
= true;
4799 /* Expand the function prologue. The prologue is responsible for reserving
4800 storage for the frame, saving the call-saved registers and loading the
4801 GOT register if needed. */
4804 sparc_flat_expand_prologue (void)
4809 sparc_leaf_function_p
= optimize
> 0 && current_function_is_leaf
;
4811 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4813 if (flag_stack_usage_info
)
4814 current_function_static_stack_size
= size
;
4816 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4817 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4819 if (sparc_save_local_in_regs_p
)
4820 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
4827 rtx size_int_rtx
, size_rtx
;
4829 size_rtx
= size_int_rtx
= GEN_INT (-size
);
4831 /* We establish the frame (i.e. decrement the stack pointer) first, even
4832 if we use a frame pointer, because we cannot clobber any call-saved
4833 registers, including the frame pointer, if we haven't created a new
4834 register save area, for the sake of compatibility with the ABI. */
4836 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4837 else if (size
<= 8192 && !frame_pointer_needed
)
4839 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4840 RTX_FRAME_RELATED_P (insn
) = 1;
4841 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4845 size_rtx
= gen_rtx_REG (Pmode
, 1);
4846 emit_move_insn (size_rtx
, size_int_rtx
);
4847 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4848 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4849 gen_stack_pointer_inc (size_int_rtx
));
4851 RTX_FRAME_RELATED_P (insn
) = 1;
4853 /* Ensure nothing is scheduled until after the frame is established. */
4854 emit_insn (gen_blockage ());
4856 if (frame_pointer_needed
)
4858 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4859 gen_rtx_MINUS (Pmode
,
4862 RTX_FRAME_RELATED_P (insn
) = 1;
4864 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4865 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4866 plus_constant (stack_pointer_rtx
,
4870 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4872 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
4873 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4875 insn
= emit_move_insn (i7
, o7
);
4876 RTX_FRAME_RELATED_P (insn
) = 1;
4878 add_reg_note (insn
, REG_CFA_REGISTER
,
4879 gen_rtx_SET (VOIDmode
, i7
, o7
));
4881 /* Prevent this instruction from ever being considered dead,
4882 even if this function has no epilogue. */
4883 emit_insn (gen_rtx_USE (VOIDmode
, i7
));
4887 if (frame_pointer_needed
)
4889 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4890 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4894 sparc_frame_base_reg
= stack_pointer_rtx
;
4895 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4898 if (sparc_n_global_fp_regs
> 0)
4899 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4900 sparc_frame_base_offset
4901 - sparc_apparent_frame_size
,
4904 /* Load the GOT register if needed. */
4905 if (crtl
->uses_pic_offset_table
)
4906 load_got_register ();
4908 /* Advertise that the data calculated just above are now valid. */
4909 sparc_prologue_data_valid_p
= true;
4912 /* This function generates the assembly code for function entry, which boils
4913 down to emitting the necessary .register directives. */
4916 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4918 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4920 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
4922 sparc_output_scratch_registers (file
);
4925 /* Expand the function epilogue, either normal or part of a sibcall.
4926 We emit all the instructions except the return or the call. */
4929 sparc_expand_epilogue (bool for_eh
)
4931 HOST_WIDE_INT size
= sparc_frame_size
;
4933 if (sparc_n_global_fp_regs
> 0)
4934 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4935 sparc_frame_base_offset
4936 - sparc_apparent_frame_size
,
4939 if (size
== 0 || for_eh
)
4941 else if (sparc_leaf_function_p
)
4944 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
4945 else if (size
<= 8192)
4947 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4948 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
4952 rtx reg
= gen_rtx_REG (Pmode
, 1);
4953 emit_move_insn (reg
, GEN_INT (-size
));
4954 emit_insn (gen_stack_pointer_dec (reg
));
4959 /* Expand the function epilogue, either normal or part of a sibcall.
4960 We emit all the instructions except the return or the call. */
4963 sparc_flat_expand_epilogue (bool for_eh
)
4965 HOST_WIDE_INT size
= sparc_frame_size
;
4967 if (sparc_n_global_fp_regs
> 0)
4968 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4969 sparc_frame_base_offset
4970 - sparc_apparent_frame_size
,
4973 /* If we have a frame pointer, we'll need both to restore it before the
4974 frame is destroyed and use its current value in destroying the frame.
4975 Since we don't have an atomic way to do that in the flat window model,
4976 we save the current value into a temporary register (%g1). */
4977 if (frame_pointer_needed
&& !for_eh
)
4978 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
4980 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4981 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
4982 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
4984 if (sparc_save_local_in_regs_p
)
4985 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
4986 sparc_frame_base_offset
,
4989 if (size
== 0 || for_eh
)
4991 else if (frame_pointer_needed
)
4993 /* Make sure the frame is destroyed after everything else is done. */
4994 emit_insn (gen_blockage ());
4996 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5001 emit_insn (gen_blockage ());
5004 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
5005 else if (size
<= 8192)
5007 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5008 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5012 rtx reg
= gen_rtx_REG (Pmode
, 1);
5013 emit_move_insn (reg
, GEN_INT (-size
));
5014 emit_insn (gen_stack_pointer_dec (reg
));
5019 /* Return true if it is appropriate to emit `return' instructions in the
5020 body of a function. */
5023 sparc_can_use_return_insn_p (void)
5025 return sparc_prologue_data_valid_p
5026 && sparc_n_global_fp_regs
== 0
5028 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5029 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5032 /* This function generates the assembly code for function exit. */
5035 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5037 /* If the last two instructions of a function are "call foo; dslot;"
5038 the return address might point to the first instruction in the next
5039 function and we have to output a dummy nop for the sake of sane
5040 backtraces in such cases. This is pointless for sibling calls since
5041 the return address is explicitly adjusted. */
5043 rtx insn
, last_real_insn
;
5045 insn
= get_last_insn ();
5047 last_real_insn
= prev_real_insn (insn
);
5049 && GET_CODE (last_real_insn
) == INSN
5050 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5051 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5054 && CALL_P (last_real_insn
)
5055 && !SIBLING_CALL_P (last_real_insn
))
5056 fputs("\tnop\n", file
);
5058 sparc_output_deferred_case_vectors ();
5061 /* Output a 'restore' instruction. */
5064 output_restore (rtx pat
)
5070 fputs ("\t restore\n", asm_out_file
);
5074 gcc_assert (GET_CODE (pat
) == SET
);
5076 operands
[0] = SET_DEST (pat
);
5077 pat
= SET_SRC (pat
);
5079 switch (GET_CODE (pat
))
5082 operands
[1] = XEXP (pat
, 0);
5083 operands
[2] = XEXP (pat
, 1);
5084 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5087 operands
[1] = XEXP (pat
, 0);
5088 operands
[2] = XEXP (pat
, 1);
5089 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5092 operands
[1] = XEXP (pat
, 0);
5093 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5094 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5098 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5103 /* Output a return. */
5106 output_return (rtx insn
)
5108 if (crtl
->calls_eh_return
)
5110 /* If the function uses __builtin_eh_return, the eh_return
5111 machinery occupies the delay slot. */
5112 gcc_assert (!final_sequence
);
5114 if (flag_delayed_branch
)
5116 if (!TARGET_FLAT
&& TARGET_V9
)
5117 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5121 fputs ("\trestore\n", asm_out_file
);
5123 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5126 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5131 fputs ("\trestore\n", asm_out_file
);
5133 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5134 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5137 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5139 /* This is a leaf or flat function so we don't have to bother restoring
5140 the register window, which frees us from dealing with the convoluted
5141 semantics of restore/return. We simply output the jump to the
5142 return address and the insn in the delay slot (if any). */
5144 return "jmp\t%%o7+%)%#";
5148 /* This is a regular function so we have to restore the register window.
5149 We may have a pending insn for the delay slot, which will be either
5150 combined with the 'restore' instruction or put in the delay slot of
5151 the 'return' instruction. */
5157 delay
= NEXT_INSN (insn
);
5160 pat
= PATTERN (delay
);
5162 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5164 epilogue_renumber (&pat
, 0);
5165 return "return\t%%i7+%)%#";
5169 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5170 output_restore (pat
);
5171 PATTERN (delay
) = gen_blockage ();
5172 INSN_CODE (delay
) = -1;
5177 /* The delay slot is empty. */
5179 return "return\t%%i7+%)\n\t nop";
5180 else if (flag_delayed_branch
)
5181 return "jmp\t%%i7+%)\n\t restore";
5183 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5190 /* Output a sibling call. */
5193 output_sibcall (rtx insn
, rtx call_operand
)
5197 gcc_assert (flag_delayed_branch
);
5199 operands
[0] = call_operand
;
5201 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5203 /* This is a leaf or flat function so we don't have to bother restoring
5204 the register window. We simply output the jump to the function and
5205 the insn in the delay slot (if any). */
5207 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5210 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5213 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5214 it into branch if possible. */
5215 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5220 /* This is a regular function so we have to restore the register window.
5221 We may have a pending insn for the delay slot, which will be combined
5222 with the 'restore' instruction. */
5224 output_asm_insn ("call\t%a0, 0", operands
);
5228 rtx delay
= NEXT_INSN (insn
);
5231 output_restore (PATTERN (delay
));
5233 PATTERN (delay
) = gen_blockage ();
5234 INSN_CODE (delay
) = -1;
5237 output_restore (NULL_RTX
);
5243 /* Functions for handling argument passing.
5245 For 32-bit, the first 6 args are normally in registers and the rest are
5246 pushed. Any arg that starts within the first 6 words is at least
5247 partially passed in a register unless its data type forbids.
5249 For 64-bit, the argument registers are laid out as an array of 16 elements
5250 and arguments are added sequentially. The first 6 int args and up to the
5251 first 16 fp args (depending on size) are passed in regs.
5253 Slot Stack Integral Float Float in structure Double Long Double
5254 ---- ----- -------- ----- ------------------ ------ -----------
5255 15 [SP+248] %f31 %f30,%f31 %d30
5256 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5257 13 [SP+232] %f27 %f26,%f27 %d26
5258 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5259 11 [SP+216] %f23 %f22,%f23 %d22
5260 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5261 9 [SP+200] %f19 %f18,%f19 %d18
5262 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5263 7 [SP+184] %f15 %f14,%f15 %d14
5264 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5265 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5266 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5267 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5268 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5269 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5270 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5272 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5274 Integral arguments are always passed as 64-bit quantities appropriately
5277 Passing of floating point values is handled as follows.
5278 If a prototype is in scope:
5279 If the value is in a named argument (i.e. not a stdarg function or a
5280 value not part of the `...') then the value is passed in the appropriate
5282 If the value is part of the `...' and is passed in one of the first 6
5283 slots then the value is passed in the appropriate int reg.
5284 If the value is part of the `...' and is not passed in one of the first 6
5285 slots then the value is passed in memory.
5286 If a prototype is not in scope:
5287 If the value is one of the first 6 arguments the value is passed in the
5288 appropriate integer reg and the appropriate fp reg.
5289 If the value is not one of the first 6 arguments the value is passed in
5290 the appropriate fp reg and in memory.
5293 Summary of the calling conventions implemented by GCC on the SPARC:
5296 size argument return value
5298 small integer <4 int. reg. int. reg.
5299 word 4 int. reg. int. reg.
5300 double word 8 int. reg. int. reg.
5302 _Complex small integer <8 int. reg. int. reg.
5303 _Complex word 8 int. reg. int. reg.
5304 _Complex double word 16 memory int. reg.
5306 vector integer <=8 int. reg. FP reg.
5307 vector integer >8 memory memory
5309 float 4 int. reg. FP reg.
5310 double 8 int. reg. FP reg.
5311 long double 16 memory memory
5313 _Complex float 8 memory FP reg.
5314 _Complex double 16 memory FP reg.
5315 _Complex long double 32 memory FP reg.
5317 vector float any memory memory
5319 aggregate any memory memory
5324 size argument return value
5326 small integer <8 int. reg. int. reg.
5327 word 8 int. reg. int. reg.
5328 double word 16 int. reg. int. reg.
5330 _Complex small integer <16 int. reg. int. reg.
5331 _Complex word 16 int. reg. int. reg.
5332 _Complex double word 32 memory int. reg.
5334 vector integer <=16 FP reg. FP reg.
5335 vector integer 16<s<=32 memory FP reg.
5336 vector integer >32 memory memory
5338 float 4 FP reg. FP reg.
5339 double 8 FP reg. FP reg.
5340 long double 16 FP reg. FP reg.
5342 _Complex float 8 FP reg. FP reg.
5343 _Complex double 16 FP reg. FP reg.
5344 _Complex long double 32 memory FP reg.
5346 vector float <=16 FP reg. FP reg.
5347 vector float 16<s<=32 memory FP reg.
5348 vector float >32 memory memory
5350 aggregate <=16 reg. reg.
5351 aggregate 16<s<=32 memory reg.
5352 aggregate >32 memory memory
5356 Note #1: complex floating-point types follow the extended SPARC ABIs as
5357 implemented by the Sun compiler.
5359 Note #2: integral vector types follow the scalar floating-point types
5360 conventions to match what is implemented by the Sun VIS SDK.
5362 Note #3: floating-point vector types follow the aggregate types
5366 /* Maximum number of int regs for args. */
5367 #define SPARC_INT_ARG_MAX 6
5368 /* Maximum number of fp regs for args. */
5369 #define SPARC_FP_ARG_MAX 16
5371 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5373 /* Handle the INIT_CUMULATIVE_ARGS macro.
5374 Initialize a variable CUM of type CUMULATIVE_ARGS
5375 for a call to a function whose data type is FNTYPE.
5376 For a library call, FNTYPE is 0. */
5379 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5380 rtx libname ATTRIBUTE_UNUSED
,
5381 tree fndecl ATTRIBUTE_UNUSED
)
5384 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5385 cum
->libcall_p
= fntype
== 0;
5388 /* Handle promotion of pointer and integer arguments. */
5390 static enum machine_mode
5391 sparc_promote_function_mode (const_tree type
,
5392 enum machine_mode mode
,
5394 const_tree fntype ATTRIBUTE_UNUSED
,
5395 int for_return ATTRIBUTE_UNUSED
)
5397 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5399 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5403 /* Integral arguments are passed as full words, as per the ABI. */
5404 if (GET_MODE_CLASS (mode
) == MODE_INT
5405 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5411 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5414 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5416 return TARGET_ARCH64
? true : false;
5419 /* Scan the record type TYPE and return the following predicates:
5420 - INTREGS_P: the record contains at least one field or sub-field
5421 that is eligible for promotion in integer registers.
5422 - FP_REGS_P: the record contains at least one field or sub-field
5423 that is eligible for promotion in floating-point registers.
5424 - PACKED_P: the record contains at least one field that is packed.
5426 Sub-fields are not taken into account for the PACKED_P predicate. */
5429 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5434 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5436 if (TREE_CODE (field
) == FIELD_DECL
)
5438 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5439 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5440 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5441 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5447 if (packed_p
&& DECL_PACKED (field
))
5453 /* Compute the slot number to pass an argument in.
5454 Return the slot number or -1 if passing on the stack.
5456 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5457 the preceding args and about the function being called.
5458 MODE is the argument's machine mode.
5459 TYPE is the data type of the argument (as a tree).
5460 This is null for libcalls where that information may
5462 NAMED is nonzero if this argument is a named parameter
5463 (otherwise it is an extra parameter matching an ellipsis).
5464 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5465 *PREGNO records the register number to use if scalar type.
5466 *PPADDING records the amount of padding needed in words. */
5469 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5470 const_tree type
, bool named
, bool incoming_p
,
5471 int *pregno
, int *ppadding
)
5473 int regbase
= (incoming_p
5474 ? SPARC_INCOMING_INT_ARG_FIRST
5475 : SPARC_OUTGOING_INT_ARG_FIRST
);
5476 int slotno
= cum
->words
;
5477 enum mode_class mclass
;
5482 if (type
&& TREE_ADDRESSABLE (type
))
5488 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5491 /* For SPARC64, objects requiring 16-byte alignment get it. */
5493 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5494 && (slotno
& 1) != 0)
5495 slotno
++, *ppadding
= 1;
5497 mclass
= GET_MODE_CLASS (mode
);
5498 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5500 /* Vector types deserve special treatment because they are
5501 polymorphic wrt their mode, depending upon whether VIS
5502 instructions are enabled. */
5503 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5505 /* The SPARC port defines no floating-point vector modes. */
5506 gcc_assert (mode
== BLKmode
);
5510 /* Integral vector types should either have a vector
5511 mode or an integral mode, because we are guaranteed
5512 by pass_by_reference that their size is not greater
5513 than 16 bytes and TImode is 16-byte wide. */
5514 gcc_assert (mode
!= BLKmode
);
5516 /* Vector integers are handled like floats according to
5518 mclass
= MODE_FLOAT
;
5525 case MODE_COMPLEX_FLOAT
:
5526 case MODE_VECTOR_INT
:
5527 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5529 if (slotno
>= SPARC_FP_ARG_MAX
)
5531 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5532 /* Arguments filling only one single FP register are
5533 right-justified in the outer double FP register. */
5534 if (GET_MODE_SIZE (mode
) <= 4)
5541 case MODE_COMPLEX_INT
:
5542 if (slotno
>= SPARC_INT_ARG_MAX
)
5544 regno
= regbase
+ slotno
;
5548 if (mode
== VOIDmode
)
5549 /* MODE is VOIDmode when generating the actual call. */
5552 gcc_assert (mode
== BLKmode
);
5556 || (TREE_CODE (type
) != VECTOR_TYPE
5557 && TREE_CODE (type
) != RECORD_TYPE
))
5559 if (slotno
>= SPARC_INT_ARG_MAX
)
5561 regno
= regbase
+ slotno
;
5563 else /* TARGET_ARCH64 && type */
5565 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5567 /* First see what kinds of registers we would need. */
5568 if (TREE_CODE (type
) == VECTOR_TYPE
)
5571 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5573 /* The ABI obviously doesn't specify how packed structures
5574 are passed. These are defined to be passed in int regs
5575 if possible, otherwise memory. */
5576 if (packed_p
|| !named
)
5577 fpregs_p
= 0, intregs_p
= 1;
5579 /* If all arg slots are filled, then must pass on stack. */
5580 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5583 /* If there are only int args and all int arg slots are filled,
5584 then must pass on stack. */
5585 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5588 /* Note that even if all int arg slots are filled, fp members may
5589 still be passed in regs if such regs are available.
5590 *PREGNO isn't set because there may be more than one, it's up
5591 to the caller to compute them. */
5604 /* Handle recursive register counting for structure field layout. */
5606 struct function_arg_record_value_parms
5608 rtx ret
; /* return expression being built. */
5609 int slotno
; /* slot number of the argument. */
5610 int named
; /* whether the argument is named. */
5611 int regbase
; /* regno of the base register. */
5612 int stack
; /* 1 if part of the argument is on the stack. */
5613 int intoffset
; /* offset of the first pending integer field. */
5614 unsigned int nregs
; /* number of words passed in registers. */
5617 static void function_arg_record_value_3
5618 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5619 static void function_arg_record_value_2
5620 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5621 static void function_arg_record_value_1
5622 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5623 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
5624 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5626 /* A subroutine of function_arg_record_value. Traverse the structure
5627 recursively and determine how many registers will be required. */
5630 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
5631 struct function_arg_record_value_parms
*parms
,
5636 /* We need to compute how many registers are needed so we can
5637 allocate the PARALLEL but before we can do that we need to know
5638 whether there are any packed fields. The ABI obviously doesn't
5639 specify how structures are passed in this case, so they are
5640 defined to be passed in int regs if possible, otherwise memory,
5641 regardless of whether there are fp values present. */
5644 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5646 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5653 /* Compute how many registers we need. */
5654 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5656 if (TREE_CODE (field
) == FIELD_DECL
)
5658 HOST_WIDE_INT bitpos
= startbitpos
;
5660 if (DECL_SIZE (field
) != 0)
5662 if (integer_zerop (DECL_SIZE (field
)))
5665 if (host_integerp (bit_position (field
), 1))
5666 bitpos
+= int_bit_position (field
);
5669 /* ??? FIXME: else assume zero offset. */
5671 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5672 function_arg_record_value_1 (TREE_TYPE (field
),
5676 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5677 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5682 if (parms
->intoffset
!= -1)
5684 unsigned int startbit
, endbit
;
5685 int intslots
, this_slotno
;
5687 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5688 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5690 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5691 this_slotno
= parms
->slotno
+ parms
->intoffset
5694 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5696 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5697 /* We need to pass this field on the stack. */
5701 parms
->nregs
+= intslots
;
5702 parms
->intoffset
= -1;
5705 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5706 If it wasn't true we wouldn't be here. */
5707 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5708 && DECL_MODE (field
) == BLKmode
)
5709 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5710 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5717 if (parms
->intoffset
== -1)
5718 parms
->intoffset
= bitpos
;
5724 /* A subroutine of function_arg_record_value. Assign the bits of the
5725 structure between parms->intoffset and bitpos to integer registers. */
5728 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5729 struct function_arg_record_value_parms
*parms
)
5731 enum machine_mode mode
;
5733 unsigned int startbit
, endbit
;
5734 int this_slotno
, intslots
, intoffset
;
5737 if (parms
->intoffset
== -1)
5740 intoffset
= parms
->intoffset
;
5741 parms
->intoffset
= -1;
5743 startbit
= intoffset
& -BITS_PER_WORD
;
5744 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5745 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5746 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5748 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5752 /* If this is the trailing part of a word, only load that much into
5753 the register. Otherwise load the whole register. Note that in
5754 the latter case we may pick up unwanted bits. It's not a problem
5755 at the moment but may wish to revisit. */
5757 if (intoffset
% BITS_PER_WORD
!= 0)
5758 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5763 intoffset
/= BITS_PER_UNIT
;
5766 regno
= parms
->regbase
+ this_slotno
;
5767 reg
= gen_rtx_REG (mode
, regno
);
5768 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5769 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5772 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5777 while (intslots
> 0);
5780 /* A subroutine of function_arg_record_value. Traverse the structure
5781 recursively and assign bits to floating point registers. Track which
5782 bits in between need integer registers; invoke function_arg_record_value_3
5783 to make that happen. */
5786 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5787 struct function_arg_record_value_parms
*parms
,
5793 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5795 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5802 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5804 if (TREE_CODE (field
) == FIELD_DECL
)
5806 HOST_WIDE_INT bitpos
= startbitpos
;
5808 if (DECL_SIZE (field
) != 0)
5810 if (integer_zerop (DECL_SIZE (field
)))
5813 if (host_integerp (bit_position (field
), 1))
5814 bitpos
+= int_bit_position (field
);
5817 /* ??? FIXME: else assume zero offset. */
5819 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5820 function_arg_record_value_2 (TREE_TYPE (field
),
5824 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5825 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5830 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5831 int regno
, nregs
, pos
;
5832 enum machine_mode mode
= DECL_MODE (field
);
5835 function_arg_record_value_3 (bitpos
, parms
);
5837 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5840 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5841 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5843 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5845 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5851 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5852 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5854 reg
= gen_rtx_REG (mode
, regno
);
5855 pos
= bitpos
/ BITS_PER_UNIT
;
5856 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5857 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5861 regno
+= GET_MODE_SIZE (mode
) / 4;
5862 reg
= gen_rtx_REG (mode
, regno
);
5863 pos
+= GET_MODE_SIZE (mode
);
5864 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5865 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5871 if (parms
->intoffset
== -1)
5872 parms
->intoffset
= bitpos
;
5878 /* Used by function_arg and sparc_function_value_1 to implement the complex
5879 conventions of the 64-bit ABI for passing and returning structures.
5880 Return an expression valid as a return value for the FUNCTION_ARG
5881 and TARGET_FUNCTION_VALUE.
5883 TYPE is the data type of the argument (as a tree).
5884 This is null for libcalls where that information may
5886 MODE is the argument's machine mode.
5887 SLOTNO is the index number of the argument's slot in the parameter array.
5888 NAMED is nonzero if this argument is a named parameter
5889 (otherwise it is an extra parameter matching an ellipsis).
5890 REGBASE is the regno of the base register for the parameter array. */
5893 function_arg_record_value (const_tree type
, enum machine_mode mode
,
5894 int slotno
, int named
, int regbase
)
5896 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5897 struct function_arg_record_value_parms parms
;
5900 parms
.ret
= NULL_RTX
;
5901 parms
.slotno
= slotno
;
5902 parms
.named
= named
;
5903 parms
.regbase
= regbase
;
5906 /* Compute how many registers we need. */
5908 parms
.intoffset
= 0;
5909 function_arg_record_value_1 (type
, 0, &parms
, false);
5911 /* Take into account pending integer fields. */
5912 if (parms
.intoffset
!= -1)
5914 unsigned int startbit
, endbit
;
5915 int intslots
, this_slotno
;
5917 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5918 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5919 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5920 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5922 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5924 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5925 /* We need to pass this field on the stack. */
5929 parms
.nregs
+= intslots
;
5931 nregs
= parms
.nregs
;
5933 /* Allocate the vector and handle some annoying special cases. */
5936 /* ??? Empty structure has no value? Duh? */
5939 /* Though there's nothing really to store, return a word register
5940 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5941 leads to breakage due to the fact that there are zero bytes to
5943 return gen_rtx_REG (mode
, regbase
);
5947 /* ??? C++ has structures with no fields, and yet a size. Give up
5948 for now and pass everything back in integer registers. */
5949 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5951 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5952 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5954 gcc_assert (nregs
!= 0);
5956 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
5958 /* If at least one field must be passed on the stack, generate
5959 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5960 also be passed on the stack. We can't do much better because the
5961 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5962 of structures for which the fields passed exclusively in registers
5963 are not at the beginning of the structure. */
5965 XVECEXP (parms
.ret
, 0, 0)
5966 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5968 /* Fill in the entries. */
5970 parms
.intoffset
= 0;
5971 function_arg_record_value_2 (type
, 0, &parms
, false);
5972 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
5974 gcc_assert (parms
.nregs
== nregs
);
5979 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5980 of the 64-bit ABI for passing and returning unions.
5981 Return an expression valid as a return value for the FUNCTION_ARG
5982 and TARGET_FUNCTION_VALUE.
5984 SIZE is the size in bytes of the union.
5985 MODE is the argument's machine mode.
5986 REGNO is the hard register the union will be passed in. */
5989 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
5992 int nwords
= ROUND_ADVANCE (size
), i
;
5995 /* See comment in previous function for empty structures. */
5997 return gen_rtx_REG (mode
, regno
);
5999 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6002 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6004 for (i
= 0; i
< nwords
; i
++)
6006 /* Unions are passed left-justified. */
6007 XVECEXP (regs
, 0, i
)
6008 = gen_rtx_EXPR_LIST (VOIDmode
,
6009 gen_rtx_REG (word_mode
, regno
),
6010 GEN_INT (UNITS_PER_WORD
* i
));
6017 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6018 for passing and returning large (BLKmode) vectors.
6019 Return an expression valid as a return value for the FUNCTION_ARG
6020 and TARGET_FUNCTION_VALUE.
6022 SIZE is the size in bytes of the vector (at least 8 bytes).
6023 REGNO is the FP hard register the vector will be passed in. */
6026 function_arg_vector_value (int size
, int regno
)
6028 int i
, nregs
= size
/ 8;
6031 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6033 for (i
= 0; i
< nregs
; i
++)
6035 XVECEXP (regs
, 0, i
)
6036 = gen_rtx_EXPR_LIST (VOIDmode
,
6037 gen_rtx_REG (DImode
, regno
+ 2*i
),
6044 /* Determine where to put an argument to a function.
6045 Value is zero to push the argument on the stack,
6046 or a hard register in which to store the argument.
6048 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6049 the preceding args and about the function being called.
6050 MODE is the argument's machine mode.
6051 TYPE is the data type of the argument (as a tree).
6052 This is null for libcalls where that information may
6054 NAMED is true if this argument is a named parameter
6055 (otherwise it is an extra parameter matching an ellipsis).
6056 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6057 TARGET_FUNCTION_INCOMING_ARG. */
6060 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6061 const_tree type
, bool named
, bool incoming_p
)
6063 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6065 int regbase
= (incoming_p
6066 ? SPARC_INCOMING_INT_ARG_FIRST
6067 : SPARC_OUTGOING_INT_ARG_FIRST
);
6068 int slotno
, regno
, padding
;
6069 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6071 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6076 /* Vector types deserve special treatment because they are polymorphic wrt
6077 their mode, depending upon whether VIS instructions are enabled. */
6078 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6080 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6081 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6082 || (TARGET_ARCH64
&& size
<= 16));
6084 if (mode
== BLKmode
)
6085 return function_arg_vector_value (size
,
6086 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6088 mclass
= MODE_FLOAT
;
6092 return gen_rtx_REG (mode
, regno
);
6094 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6095 and are promoted to registers if possible. */
6096 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6098 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6099 gcc_assert (size
<= 16);
6101 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6104 /* Unions up to 16 bytes in size are passed in integer registers. */
6105 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6107 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6108 gcc_assert (size
<= 16);
6110 return function_arg_union_value (size
, mode
, slotno
, regno
);
6113 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6114 but also have the slot allocated for them.
6115 If no prototype is in scope fp values in register slots get passed
6116 in two places, either fp regs and int regs or fp regs and memory. */
6117 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6118 && SPARC_FP_REG_P (regno
))
6120 rtx reg
= gen_rtx_REG (mode
, regno
);
6121 if (cum
->prototype_p
|| cum
->libcall_p
)
6123 /* "* 2" because fp reg numbers are recorded in 4 byte
6126 /* ??? This will cause the value to be passed in the fp reg and
6127 in the stack. When a prototype exists we want to pass the
6128 value in the reg but reserve space on the stack. That's an
6129 optimization, and is deferred [for a bit]. */
6130 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6131 return gen_rtx_PARALLEL (mode
,
6133 gen_rtx_EXPR_LIST (VOIDmode
,
6134 NULL_RTX
, const0_rtx
),
6135 gen_rtx_EXPR_LIST (VOIDmode
,
6139 /* ??? It seems that passing back a register even when past
6140 the area declared by REG_PARM_STACK_SPACE will allocate
6141 space appropriately, and will not copy the data onto the
6142 stack, exactly as we desire.
6144 This is due to locate_and_pad_parm being called in
6145 expand_call whenever reg_parm_stack_space > 0, which
6146 while beneficial to our example here, would seem to be
6147 in error from what had been intended. Ho hum... -- r~ */
6155 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6159 /* On incoming, we don't need to know that the value
6160 is passed in %f0 and %i0, and it confuses other parts
6161 causing needless spillage even on the simplest cases. */
6165 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6166 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6168 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6169 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6171 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6175 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6176 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6177 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6182 /* All other aggregate types are passed in an integer register in a mode
6183 corresponding to the size of the type. */
6184 else if (type
&& AGGREGATE_TYPE_P (type
))
6186 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6187 gcc_assert (size
<= 16);
6189 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6192 return gen_rtx_REG (mode
, regno
);
6195 /* Handle the TARGET_FUNCTION_ARG target hook. */
6198 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6199 const_tree type
, bool named
)
6201 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6204 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6207 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6208 const_tree type
, bool named
)
6210 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6213 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6216 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6218 return ((TARGET_ARCH64
6219 && (GET_MODE_ALIGNMENT (mode
) == 128
6220 || (type
&& TYPE_ALIGN (type
) == 128)))
6225 /* For an arg passed partly in registers and partly in memory,
6226 this is the number of bytes of registers used.
6227 For args passed entirely in registers or entirely in memory, zero.
6229 Any arg that starts in the first 6 regs but won't entirely fit in them
6230 needs partial registers on v8. On v9, structures with integer
6231 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6232 values that begin in the last fp reg [where "last fp reg" varies with the
6233 mode] will be split between that reg and memory. */
6236 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6237 tree type
, bool named
)
6239 int slotno
, regno
, padding
;
6241 /* We pass false for incoming_p here, it doesn't matter. */
6242 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6243 false, ®no
, &padding
);
6250 if ((slotno
+ (mode
== BLKmode
6251 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6252 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6253 > SPARC_INT_ARG_MAX
)
6254 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6258 /* We are guaranteed by pass_by_reference that the size of the
6259 argument is not greater than 16 bytes, so we only need to return
6260 one word if the argument is partially passed in registers. */
6262 if (type
&& AGGREGATE_TYPE_P (type
))
6264 int size
= int_size_in_bytes (type
);
6266 if (size
> UNITS_PER_WORD
6267 && slotno
== SPARC_INT_ARG_MAX
- 1)
6268 return UNITS_PER_WORD
;
6270 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6271 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6272 && ! (TARGET_FPU
&& named
)))
6274 /* The complex types are passed as packed types. */
6275 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6276 && slotno
== SPARC_INT_ARG_MAX
- 1)
6277 return UNITS_PER_WORD
;
6279 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6281 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6283 return UNITS_PER_WORD
;
6290 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6291 Specify whether to pass the argument by reference. */
6294 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6295 enum machine_mode mode
, const_tree type
,
6296 bool named ATTRIBUTE_UNUSED
)
6299 /* Original SPARC 32-bit ABI says that structures and unions,
6300 and quad-precision floats are passed by reference. For Pascal,
6301 also pass arrays by reference. All other base types are passed
6304 Extended ABI (as implemented by the Sun compiler) says that all
6305 complex floats are passed by reference. Pass complex integers
6306 in registers up to 8 bytes. More generally, enforce the 2-word
6307 cap for passing arguments in registers.
6309 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6310 integers are passed like floats of the same size, that is in
6311 registers up to 8 bytes. Pass all vector floats by reference
6312 like structure and unions. */
6313 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6315 /* Catch CDImode, TFmode, DCmode and TCmode. */
6316 || GET_MODE_SIZE (mode
) > 8
6318 && TREE_CODE (type
) == VECTOR_TYPE
6319 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6321 /* Original SPARC 64-bit ABI says that structures and unions
6322 smaller than 16 bytes are passed in registers, as well as
6323 all other base types.
6325 Extended ABI (as implemented by the Sun compiler) says that
6326 complex floats are passed in registers up to 16 bytes. Pass
6327 all complex integers in registers up to 16 bytes. More generally,
6328 enforce the 2-word cap for passing arguments in registers.
6330 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6331 integers are passed like floats of the same size, that is in
6332 registers (up to 16 bytes). Pass all vector floats like structure
6335 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6336 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6337 /* Catch CTImode and TCmode. */
6338 || GET_MODE_SIZE (mode
) > 16);
6341 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6342 Update the data in CUM to advance over an argument
6343 of mode MODE and data type TYPE.
6344 TYPE is null for libcalls where that information may not be available. */
6347 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6348 const_tree type
, bool named
)
6350 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6353 /* We pass false for incoming_p here, it doesn't matter. */
6354 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6356 /* If argument requires leading padding, add it. */
6357 cum
->words
+= padding
;
6361 cum
->words
+= (mode
!= BLKmode
6362 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6363 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6367 if (type
&& AGGREGATE_TYPE_P (type
))
6369 int size
= int_size_in_bytes (type
);
6373 else if (size
<= 16)
6375 else /* passed by reference */
6380 cum
->words
+= (mode
!= BLKmode
6381 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6382 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6387 /* Handle the FUNCTION_ARG_PADDING macro.
6388 For the 64 bit ABI structs are always stored left shifted in their
6392 function_arg_padding (enum machine_mode mode
, const_tree type
)
6394 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6397 /* Fall back to the default. */
6398 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6401 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6402 Specify whether to return the return value in memory. */
6405 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6408 /* Original SPARC 32-bit ABI says that structures and unions,
6409 and quad-precision floats are returned in memory. All other
6410 base types are returned in registers.
6412 Extended ABI (as implemented by the Sun compiler) says that
6413 all complex floats are returned in registers (8 FP registers
6414 at most for '_Complex long double'). Return all complex integers
6415 in registers (4 at most for '_Complex long long').
6417 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6418 integers are returned like floats of the same size, that is in
6419 registers up to 8 bytes and in memory otherwise. Return all
6420 vector floats in memory like structure and unions; note that
6421 they always have BLKmode like the latter. */
6422 return (TYPE_MODE (type
) == BLKmode
6423 || TYPE_MODE (type
) == TFmode
6424 || (TREE_CODE (type
) == VECTOR_TYPE
6425 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6427 /* Original SPARC 64-bit ABI says that structures and unions
6428 smaller than 32 bytes are returned in registers, as well as
6429 all other base types.
6431 Extended ABI (as implemented by the Sun compiler) says that all
6432 complex floats are returned in registers (8 FP registers at most
6433 for '_Complex long double'). Return all complex integers in
6434 registers (4 at most for '_Complex TItype').
6436 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6437 integers are returned like floats of the same size, that is in
6438 registers. Return all vector floats like structure and unions;
6439 note that they always have BLKmode like the latter. */
6440 return (TYPE_MODE (type
) == BLKmode
6441 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6444 /* Handle the TARGET_STRUCT_VALUE target hook.
6445 Return where to find the structure return value address. */
6448 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6457 mem
= gen_frame_mem (Pmode
, plus_constant (frame_pointer_rtx
,
6458 STRUCT_VALUE_OFFSET
));
6460 mem
= gen_frame_mem (Pmode
, plus_constant (stack_pointer_rtx
,
6461 STRUCT_VALUE_OFFSET
));
6463 /* Only follow the SPARC ABI for fixed-size structure returns.
6464 Variable size structure returns are handled per the normal
6465 procedures in GCC. This is enabled by -mstd-struct-return */
6467 && sparc_std_struct_return
6468 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6469 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6471 /* We must check and adjust the return address, as it is
6472 optional as to whether the return object is really
6474 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6475 rtx scratch
= gen_reg_rtx (SImode
);
6476 rtx endlab
= gen_label_rtx ();
6478 /* Calculate the return object size */
6479 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6480 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6481 /* Construct a temporary return value */
6483 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6485 /* Implement SPARC 32-bit psABI callee return struct checking:
6487 Fetch the instruction where we will return to and see if
6488 it's an unimp instruction (the most significant 10 bits
6490 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6491 plus_constant (ret_reg
, 8)));
6492 /* Assume the size is valid and pre-adjust */
6493 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6494 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6496 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6497 /* Write the address of the memory pointed to by temp_val into
6498 the memory pointed to by mem */
6499 emit_move_insn (mem
, XEXP (temp_val
, 0));
6500 emit_label (endlab
);
6507 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6508 For v9, function return values are subject to the same rules as arguments,
6509 except that up to 32 bytes may be returned in registers. */
6512 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6515 /* Beware that the two values are swapped here wrt function_arg. */
6516 int regbase
= (outgoing
6517 ? SPARC_INCOMING_INT_ARG_FIRST
6518 : SPARC_OUTGOING_INT_ARG_FIRST
);
6519 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6522 /* Vector types deserve special treatment because they are polymorphic wrt
6523 their mode, depending upon whether VIS instructions are enabled. */
6524 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6526 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6527 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6528 || (TARGET_ARCH64
&& size
<= 32));
6530 if (mode
== BLKmode
)
6531 return function_arg_vector_value (size
,
6532 SPARC_FP_ARG_FIRST
);
6534 mclass
= MODE_FLOAT
;
6537 if (TARGET_ARCH64
&& type
)
6539 /* Structures up to 32 bytes in size are returned in registers. */
6540 if (TREE_CODE (type
) == RECORD_TYPE
)
6542 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6543 gcc_assert (size
<= 32);
6545 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6548 /* Unions up to 32 bytes in size are returned in integer registers. */
6549 else if (TREE_CODE (type
) == UNION_TYPE
)
6551 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6552 gcc_assert (size
<= 32);
6554 return function_arg_union_value (size
, mode
, 0, regbase
);
6557 /* Objects that require it are returned in FP registers. */
6558 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6561 /* All other aggregate types are returned in an integer register in a
6562 mode corresponding to the size of the type. */
6563 else if (AGGREGATE_TYPE_P (type
))
6565 /* All other aggregate types are passed in an integer register
6566 in a mode corresponding to the size of the type. */
6567 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6568 gcc_assert (size
<= 32);
6570 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6572 /* ??? We probably should have made the same ABI change in
6573 3.4.0 as the one we made for unions. The latter was
6574 required by the SCD though, while the former is not
6575 specified, so we favored compatibility and efficiency.
6577 Now we're stuck for aggregates larger than 16 bytes,
6578 because OImode vanished in the meantime. Let's not
6579 try to be unduly clever, and simply follow the ABI
6580 for unions in that case. */
6581 if (mode
== BLKmode
)
6582 return function_arg_union_value (size
, mode
, 0, regbase
);
6587 /* We should only have pointer and integer types at this point. This
6588 must match sparc_promote_function_mode. */
6589 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6593 /* We should only have pointer and integer types at this point. This must
6594 match sparc_promote_function_mode. */
6595 else if (TARGET_ARCH32
6596 && mclass
== MODE_INT
6597 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6600 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6601 regno
= SPARC_FP_ARG_FIRST
;
6605 return gen_rtx_REG (mode
, regno
);
6608 /* Handle TARGET_FUNCTION_VALUE.
6609 On the SPARC, the value is found in the first "output" register, but the
6610 called function leaves it in the first "input" register. */
6613 sparc_function_value (const_tree valtype
,
6614 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6617 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
6620 /* Handle TARGET_LIBCALL_VALUE. */
6623 sparc_libcall_value (enum machine_mode mode
,
6624 const_rtx fun ATTRIBUTE_UNUSED
)
6626 return sparc_function_value_1 (NULL_TREE
, mode
, false);
6629 /* Handle FUNCTION_VALUE_REGNO_P.
6630 On the SPARC, the first "output" reg is used for integer values, and the
6631 first floating point register is used for floating point values. */
6634 sparc_function_value_regno_p (const unsigned int regno
)
6636 return (regno
== 8 || regno
== 32);
6639 /* Do what is necessary for `va_start'. We look at the current function
6640 to determine if stdarg or varargs is used and return the address of
6641 the first unnamed parameter. */
6644 sparc_builtin_saveregs (void)
6646 int first_reg
= crtl
->args
.info
.words
;
6650 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6651 emit_move_insn (gen_rtx_MEM (word_mode
,
6652 gen_rtx_PLUS (Pmode
,
6654 GEN_INT (FIRST_PARM_OFFSET (0)
6657 gen_rtx_REG (word_mode
,
6658 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6660 address
= gen_rtx_PLUS (Pmode
,
6662 GEN_INT (FIRST_PARM_OFFSET (0)
6663 + UNITS_PER_WORD
* first_reg
));
6668 /* Implement `va_start' for stdarg. */
6671 sparc_va_start (tree valist
, rtx nextarg
)
6673 nextarg
= expand_builtin_saveregs ();
6674 std_expand_builtin_va_start (valist
, nextarg
);
6677 /* Implement `va_arg' for stdarg. */
6680 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6683 HOST_WIDE_INT size
, rsize
, align
;
6686 tree ptrtype
= build_pointer_type (type
);
6688 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6691 size
= rsize
= UNITS_PER_WORD
;
6697 size
= int_size_in_bytes (type
);
6698 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6703 /* For SPARC64, objects requiring 16-byte alignment get it. */
6704 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6705 align
= 2 * UNITS_PER_WORD
;
6707 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6708 are left-justified in their slots. */
6709 if (AGGREGATE_TYPE_P (type
))
6712 size
= rsize
= UNITS_PER_WORD
;
6722 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
6723 incr
= fold_convert (sizetype
, incr
);
6724 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
6726 incr
= fold_convert (ptr_type_node
, incr
);
6729 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6732 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6733 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
6737 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6738 addr
= build_va_arg_indirect_ref (addr
);
6741 /* If the address isn't aligned properly for the type, we need a temporary.
6742 FIXME: This is inefficient, usually we can do this in registers. */
6743 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6745 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6746 tree dest_addr
= build_fold_addr_expr (tmp
);
6747 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6748 3, dest_addr
, addr
, size_int (rsize
));
6749 TREE_ADDRESSABLE (tmp
) = 1;
6750 gimplify_and_add (copy
, pre_p
);
6755 addr
= fold_convert (ptrtype
, addr
);
6757 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
6758 gimplify_assign (valist
, incr
, post_p
);
6760 return build_va_arg_indirect_ref (addr
);
6763 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6764 Specify whether the vector mode is supported by the hardware. */
6767 sparc_vector_mode_supported_p (enum machine_mode mode
)
6769 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6772 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6774 static enum machine_mode
6775 sparc_preferred_simd_mode (enum machine_mode mode
)
6793 /* Return the string to output an unconditional branch to LABEL, which is
6794 the operand number of the label.
6796 DEST is the destination insn (i.e. the label), INSN is the source. */
6799 output_ubranch (rtx dest
, int label
, rtx insn
)
6801 static char string
[64];
6802 bool v9_form
= false;
6805 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6807 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6808 - INSN_ADDRESSES (INSN_UID (insn
)));
6809 /* Leave some instructions for "slop". */
6810 if (delta
>= -260000 && delta
< 260000)
6815 strcpy (string
, "ba%*,pt\t%%xcc, ");
6817 strcpy (string
, "b%*\t");
6819 p
= strchr (string
, '\0');
6830 /* Return the string to output a conditional branch to LABEL, which is
6831 the operand number of the label. OP is the conditional expression.
6832 XEXP (OP, 0) is assumed to be a condition code register (integer or
6833 floating point) and its mode specifies what kind of comparison we made.
6835 DEST is the destination insn (i.e. the label), INSN is the source.
6837 REVERSED is nonzero if we should reverse the sense of the comparison.
6839 ANNUL is nonzero if we should generate an annulling branch. */
6842 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6845 static char string
[64];
6846 enum rtx_code code
= GET_CODE (op
);
6847 rtx cc_reg
= XEXP (op
, 0);
6848 enum machine_mode mode
= GET_MODE (cc_reg
);
6849 const char *labelno
, *branch
;
6850 int spaces
= 8, far
;
6853 /* v9 branches are limited to +-1MB. If it is too far away,
6866 fbne,a,pn %fcc2, .LC29
6874 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6877 /* Reversal of FP compares takes care -- an ordered compare
6878 becomes an unordered compare and vice versa. */
6879 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6880 code
= reverse_condition_maybe_unordered (code
);
6882 code
= reverse_condition (code
);
6885 /* Start by writing the branch condition. */
6886 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6937 /* ??? !v9: FP branches cannot be preceded by another floating point
6938 insn. Because there is currently no concept of pre-delay slots,
6939 we can fix this only by always emitting a nop before a floating
6944 strcpy (string
, "nop\n\t");
6945 strcat (string
, branch
);
6958 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6970 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6991 strcpy (string
, branch
);
6993 spaces
-= strlen (branch
);
6994 p
= strchr (string
, '\0');
6996 /* Now add the annulling, the label, and a possible noop. */
7009 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7011 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7012 - INSN_ADDRESSES (INSN_UID (insn
)));
7013 /* Leave some instructions for "slop". */
7014 if (delta
< -260000 || delta
>= 260000)
7018 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7020 static char v9_fcc_labelno
[] = "%%fccX, ";
7021 /* Set the char indicating the number of the fcc reg to use. */
7022 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7023 labelno
= v9_fcc_labelno
;
7026 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7030 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7032 labelno
= "%%xcc, ";
7037 labelno
= "%%icc, ";
7042 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7045 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7058 strcpy (p
, labelno
);
7059 p
= strchr (p
, '\0');
7062 strcpy (p
, ".+12\n\t nop\n\tb\t");
7063 /* Skip the next insn if requested or
7064 if we know that it will be a nop. */
7065 if (annul
|| ! final_sequence
)
7079 /* Emit a library call comparison between floating point X and Y.
7080 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7081 Return the new operator to be used in the comparison sequence.
7083 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7084 values as arguments instead of the TFmode registers themselves,
7085 that's why we cannot call emit_float_lib_cmp. */
7088 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7091 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7092 enum machine_mode mode
;
7093 enum rtx_code new_comparison
;
7098 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7102 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7106 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7110 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7114 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7118 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7129 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7142 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7143 emit_move_insn (slot0
, x
);
7150 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7151 emit_move_insn (slot1
, y
);
7154 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7155 emit_library_call (libfunc
, LCT_NORMAL
,
7157 XEXP (slot0
, 0), Pmode
,
7158 XEXP (slot1
, 0), Pmode
);
7163 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7164 emit_library_call (libfunc
, LCT_NORMAL
,
7166 x
, TFmode
, y
, TFmode
);
7171 /* Immediately move the result of the libcall into a pseudo
7172 register so reload doesn't clobber the value if it needs
7173 the return register for a spill reg. */
7174 result
= gen_reg_rtx (mode
);
7175 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7180 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7183 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7184 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7187 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7188 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7190 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7192 tem
= gen_reg_rtx (mode
);
7194 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7196 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7197 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7200 tem
= gen_reg_rtx (mode
);
7202 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7204 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7205 tem2
= gen_reg_rtx (mode
);
7207 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7209 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7210 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7211 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7217 /* Generate an unsigned DImode to FP conversion. This is the same code
7218 optabs would emit if we didn't have TFmode patterns. */
7221 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7223 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7226 in
= force_reg (DImode
, operands
[1]);
7227 neglab
= gen_label_rtx ();
7228 donelab
= gen_label_rtx ();
7229 i0
= gen_reg_rtx (DImode
);
7230 i1
= gen_reg_rtx (DImode
);
7231 f0
= gen_reg_rtx (mode
);
7233 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7235 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7236 emit_jump_insn (gen_jump (donelab
));
7239 emit_label (neglab
);
7241 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7242 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7243 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7244 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7245 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7247 emit_label (donelab
);
7250 /* Generate an FP to unsigned DImode conversion. This is the same code
7251 optabs would emit if we didn't have TFmode patterns. */
7254 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7256 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7259 in
= force_reg (mode
, operands
[1]);
7260 neglab
= gen_label_rtx ();
7261 donelab
= gen_label_rtx ();
7262 i0
= gen_reg_rtx (DImode
);
7263 i1
= gen_reg_rtx (DImode
);
7264 limit
= gen_reg_rtx (mode
);
7265 f0
= gen_reg_rtx (mode
);
7267 emit_move_insn (limit
,
7268 CONST_DOUBLE_FROM_REAL_VALUE (
7269 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7270 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7272 emit_insn (gen_rtx_SET (VOIDmode
,
7274 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7275 emit_jump_insn (gen_jump (donelab
));
7278 emit_label (neglab
);
7280 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7281 emit_insn (gen_rtx_SET (VOIDmode
,
7283 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7284 emit_insn (gen_movdi (i1
, const1_rtx
));
7285 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7286 emit_insn (gen_xordi3 (out
, i0
, i1
));
7288 emit_label (donelab
);
7291 /* Return the string to output a conditional branch to LABEL, testing
7292 register REG. LABEL is the operand number of the label; REG is the
7293 operand number of the reg. OP is the conditional expression. The mode
7294 of REG says what kind of comparison we made.
7296 DEST is the destination insn (i.e. the label), INSN is the source.
7298 REVERSED is nonzero if we should reverse the sense of the comparison.
7300 ANNUL is nonzero if we should generate an annulling branch. */
7303 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7304 int annul
, rtx insn
)
7306 static char string
[64];
7307 enum rtx_code code
= GET_CODE (op
);
7308 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7313 /* branch on register are limited to +-128KB. If it is too far away,
7326 brgez,a,pn %o1, .LC29
7332 ba,pt %xcc, .LC29 */
7334 far
= get_attr_length (insn
) >= 3;
7336 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7338 code
= reverse_condition (code
);
7340 /* Only 64 bit versions of these instructions exist. */
7341 gcc_assert (mode
== DImode
);
7343 /* Start by writing the branch condition. */
7348 strcpy (string
, "brnz");
7352 strcpy (string
, "brz");
7356 strcpy (string
, "brgez");
7360 strcpy (string
, "brlz");
7364 strcpy (string
, "brlez");
7368 strcpy (string
, "brgz");
7375 p
= strchr (string
, '\0');
7377 /* Now add the annulling, reg, label, and nop. */
7384 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7387 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7392 *p
= p
< string
+ 8 ? '\t' : ' ';
7400 int veryfar
= 1, delta
;
7402 if (INSN_ADDRESSES_SET_P ())
7404 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7405 - INSN_ADDRESSES (INSN_UID (insn
)));
7406 /* Leave some instructions for "slop". */
7407 if (delta
>= -260000 && delta
< 260000)
7411 strcpy (p
, ".+12\n\t nop\n\t");
7412 /* Skip the next insn if requested or
7413 if we know that it will be a nop. */
7414 if (annul
|| ! final_sequence
)
7424 strcpy (p
, "ba,pt\t%%xcc, ");
7438 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7439 Such instructions cannot be used in the delay slot of return insn on v9.
7440 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7444 epilogue_renumber (register rtx
*where
, int test
)
7446 register const char *fmt
;
7448 register enum rtx_code code
;
7453 code
= GET_CODE (*where
);
7458 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7460 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7461 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7469 /* Do not replace the frame pointer with the stack pointer because
7470 it can cause the delayed instruction to load below the stack.
7471 This occurs when instructions like:
7473 (set (reg/i:SI 24 %i0)
7474 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7475 (const_int -20 [0xffffffec])) 0))
7477 are in the return delayed slot. */
7479 if (GET_CODE (XEXP (*where
, 0)) == REG
7480 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7481 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7482 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7487 if (SPARC_STACK_BIAS
7488 && GET_CODE (XEXP (*where
, 0)) == REG
7489 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7497 fmt
= GET_RTX_FORMAT (code
);
7499 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7504 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7505 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7508 else if (fmt
[i
] == 'e'
7509 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7515 /* Leaf functions and non-leaf functions have different needs. */
7518 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7521 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7523 static const int *const reg_alloc_orders
[] = {
7524 reg_leaf_alloc_order
,
7525 reg_nonleaf_alloc_order
};
7528 order_regs_for_local_alloc (void)
7530 static int last_order_nonleaf
= 1;
7532 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
7534 last_order_nonleaf
= !last_order_nonleaf
;
7535 memcpy ((char *) reg_alloc_order
,
7536 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7537 FIRST_PSEUDO_REGISTER
* sizeof (int));
7541 /* Return 1 if REG and MEM are legitimate enough to allow the various
7542 mem<-->reg splits to be run. */
7545 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7547 /* Punt if we are here by mistake. */
7548 gcc_assert (reload_completed
);
7550 /* We must have an offsettable memory reference. */
7551 if (! offsettable_memref_p (mem
))
7554 /* If we have legitimate args for ldd/std, we do not want
7555 the split to happen. */
7556 if ((REGNO (reg
) % 2) == 0
7557 && mem_min_alignment (mem
, 8))
7564 /* Return 1 if x and y are some kind of REG and they refer to
7565 different hard registers. This test is guaranteed to be
7566 run after reload. */
7569 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7571 if (GET_CODE (x
) != REG
)
7573 if (GET_CODE (y
) != REG
)
7575 if (REGNO (x
) == REGNO (y
))
7580 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7581 This makes them candidates for using ldd and std insns.
7583 Note reg1 and reg2 *must* be hard registers. */
7586 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7588 /* We might have been passed a SUBREG. */
7589 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7592 if (REGNO (reg1
) % 2 != 0)
7595 /* Integer ldd is deprecated in SPARC V9 */
7596 if (TARGET_V9
&& REGNO (reg1
) < 32)
7599 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7602 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7605 This can only happen when addr1 and addr2, the addresses in mem1
7606 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7607 addr1 must also be aligned on a 64-bit boundary.
7609 Also iff dependent_reg_rtx is not null it should not be used to
7610 compute the address for mem1, i.e. we cannot optimize a sequence
7622 But, note that the transformation from:
7627 is perfectly fine. Thus, the peephole2 patterns always pass us
7628 the destination register of the first load, never the second one.
7630 For stores we don't have a similar problem, so dependent_reg_rtx is
7634 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7638 HOST_WIDE_INT offset1
;
7640 /* The mems cannot be volatile. */
7641 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7644 /* MEM1 should be aligned on a 64-bit boundary. */
7645 if (MEM_ALIGN (mem1
) < 64)
7648 addr1
= XEXP (mem1
, 0);
7649 addr2
= XEXP (mem2
, 0);
7651 /* Extract a register number and offset (if used) from the first addr. */
7652 if (GET_CODE (addr1
) == PLUS
)
7654 /* If not a REG, return zero. */
7655 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7659 reg1
= REGNO (XEXP (addr1
, 0));
7660 /* The offset must be constant! */
7661 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7663 offset1
= INTVAL (XEXP (addr1
, 1));
7666 else if (GET_CODE (addr1
) != REG
)
7670 reg1
= REGNO (addr1
);
7671 /* This was a simple (mem (reg)) expression. Offset is 0. */
7675 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7676 if (GET_CODE (addr2
) != PLUS
)
7679 if (GET_CODE (XEXP (addr2
, 0)) != REG
7680 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7683 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7686 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7689 /* The first offset must be evenly divisible by 8 to ensure the
7690 address is 64 bit aligned. */
7691 if (offset1
% 8 != 0)
7694 /* The offset for the second addr must be 4 more than the first addr. */
7695 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7698 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7703 /* Return 1 if reg is a pseudo, or is the first register in
7704 a hard register pair. This makes it suitable for use in
7705 ldd and std insns. */
7708 register_ok_for_ldd (rtx reg
)
7710 /* We might have been passed a SUBREG. */
7714 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7715 return (REGNO (reg
) % 2 == 0);
7720 /* Return 1 if OP is a memory whose address is known to be
7721 aligned to 8-byte boundary, or a pseudo during reload.
7722 This makes it suitable for use in ldd and std insns. */
7725 memory_ok_for_ldd (rtx op
)
7729 /* In 64-bit mode, we assume that the address is word-aligned. */
7730 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
7733 if ((reload_in_progress
|| reload_completed
)
7734 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
7737 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7739 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
7748 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7751 sparc_print_operand_punct_valid_p (unsigned char code
)
7764 /* Implement TARGET_PRINT_OPERAND.
7765 Print operand X (an rtx) in assembler syntax to file FILE.
7766 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7767 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7770 sparc_print_operand (FILE *file
, rtx x
, int code
)
7775 /* Output an insn in a delay slot. */
7777 sparc_indent_opcode
= 1;
7779 fputs ("\n\t nop", file
);
7782 /* Output an annul flag if there's nothing for the delay slot and we
7783 are optimizing. This is always used with '(' below.
7784 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7785 this is a dbx bug. So, we only do this when optimizing.
7786 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7787 Always emit a nop in case the next instruction is a branch. */
7788 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7792 /* Output a 'nop' if there's nothing for the delay slot and we are
7793 not optimizing. This is always used with '*' above. */
7794 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7795 fputs ("\n\t nop", file
);
7796 else if (final_sequence
)
7797 sparc_indent_opcode
= 1;
7800 /* Output the right displacement from the saved PC on function return.
7801 The caller may have placed an "unimp" insn immediately after the call
7802 so we have to account for it. This insn is used in the 32-bit ABI
7803 when calling a function that returns a non zero-sized structure. The
7804 64-bit ABI doesn't have it. Be careful to have this test be the same
7805 as that for the call. The exception is when sparc_std_struct_return
7806 is enabled, the psABI is followed exactly and the adjustment is made
7807 by the code in sparc_struct_value_rtx. The call emitted is the same
7808 when sparc_std_struct_return is enabled. */
7810 && cfun
->returns_struct
7811 && !sparc_std_struct_return
7812 && DECL_SIZE (DECL_RESULT (current_function_decl
))
7813 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7815 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7821 /* Output the Embedded Medium/Anywhere code model base register. */
7822 fputs (EMBMEDANY_BASE_REG
, file
);
7825 /* Print some local dynamic TLS name. */
7826 assemble_name (file
, get_some_local_dynamic_name ());
7830 /* Adjust the operand to take into account a RESTORE operation. */
7831 if (GET_CODE (x
) == CONST_INT
)
7833 else if (GET_CODE (x
) != REG
)
7834 output_operand_lossage ("invalid %%Y operand");
7835 else if (REGNO (x
) < 8)
7836 fputs (reg_names
[REGNO (x
)], file
);
7837 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
7838 fputs (reg_names
[REGNO (x
)-16], file
);
7840 output_operand_lossage ("invalid %%Y operand");
7843 /* Print out the low order register name of a register pair. */
7844 if (WORDS_BIG_ENDIAN
)
7845 fputs (reg_names
[REGNO (x
)+1], file
);
7847 fputs (reg_names
[REGNO (x
)], file
);
7850 /* Print out the high order register name of a register pair. */
7851 if (WORDS_BIG_ENDIAN
)
7852 fputs (reg_names
[REGNO (x
)], file
);
7854 fputs (reg_names
[REGNO (x
)+1], file
);
7857 /* Print out the second register name of a register pair or quad.
7858 I.e., R (%o0) => %o1. */
7859 fputs (reg_names
[REGNO (x
)+1], file
);
7862 /* Print out the third register name of a register quad.
7863 I.e., S (%o0) => %o2. */
7864 fputs (reg_names
[REGNO (x
)+2], file
);
7867 /* Print out the fourth register name of a register quad.
7868 I.e., T (%o0) => %o3. */
7869 fputs (reg_names
[REGNO (x
)+3], file
);
7872 /* Print a condition code register. */
7873 if (REGNO (x
) == SPARC_ICC_REG
)
7875 /* We don't handle CC[X]_NOOVmode because they're not supposed
7877 if (GET_MODE (x
) == CCmode
)
7878 fputs ("%icc", file
);
7879 else if (GET_MODE (x
) == CCXmode
)
7880 fputs ("%xcc", file
);
7885 /* %fccN register */
7886 fputs (reg_names
[REGNO (x
)], file
);
7889 /* Print the operand's address only. */
7890 output_address (XEXP (x
, 0));
7893 /* In this case we need a register. Use %g0 if the
7894 operand is const0_rtx. */
7896 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7898 fputs ("%g0", file
);
7905 switch (GET_CODE (x
))
7907 case IOR
: fputs ("or", file
); break;
7908 case AND
: fputs ("and", file
); break;
7909 case XOR
: fputs ("xor", file
); break;
7910 default: output_operand_lossage ("invalid %%A operand");
7915 switch (GET_CODE (x
))
7917 case IOR
: fputs ("orn", file
); break;
7918 case AND
: fputs ("andn", file
); break;
7919 case XOR
: fputs ("xnor", file
); break;
7920 default: output_operand_lossage ("invalid %%B operand");
7924 /* These are used by the conditional move instructions. */
7928 enum rtx_code rc
= GET_CODE (x
);
7932 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7933 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7934 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7936 rc
= reverse_condition (GET_CODE (x
));
7940 case NE
: fputs ("ne", file
); break;
7941 case EQ
: fputs ("e", file
); break;
7942 case GE
: fputs ("ge", file
); break;
7943 case GT
: fputs ("g", file
); break;
7944 case LE
: fputs ("le", file
); break;
7945 case LT
: fputs ("l", file
); break;
7946 case GEU
: fputs ("geu", file
); break;
7947 case GTU
: fputs ("gu", file
); break;
7948 case LEU
: fputs ("leu", file
); break;
7949 case LTU
: fputs ("lu", file
); break;
7950 case LTGT
: fputs ("lg", file
); break;
7951 case UNORDERED
: fputs ("u", file
); break;
7952 case ORDERED
: fputs ("o", file
); break;
7953 case UNLT
: fputs ("ul", file
); break;
7954 case UNLE
: fputs ("ule", file
); break;
7955 case UNGT
: fputs ("ug", file
); break;
7956 case UNGE
: fputs ("uge", file
); break;
7957 case UNEQ
: fputs ("ue", file
); break;
7958 default: output_operand_lossage (code
== 'c'
7959 ? "invalid %%c operand"
7960 : "invalid %%C operand");
7965 /* These are used by the movr instruction pattern. */
7969 enum rtx_code rc
= (code
== 'd'
7970 ? reverse_condition (GET_CODE (x
))
7974 case NE
: fputs ("ne", file
); break;
7975 case EQ
: fputs ("e", file
); break;
7976 case GE
: fputs ("gez", file
); break;
7977 case LT
: fputs ("lz", file
); break;
7978 case LE
: fputs ("lez", file
); break;
7979 case GT
: fputs ("gz", file
); break;
7980 default: output_operand_lossage (code
== 'd'
7981 ? "invalid %%d operand"
7982 : "invalid %%D operand");
7989 /* Print a sign-extended character. */
7990 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
7991 fprintf (file
, "%d", i
);
7996 /* Operand must be a MEM; write its address. */
7997 if (GET_CODE (x
) != MEM
)
7998 output_operand_lossage ("invalid %%f operand");
7999 output_address (XEXP (x
, 0));
8004 /* Print a sign-extended 32-bit value. */
8006 if (GET_CODE(x
) == CONST_INT
)
8008 else if (GET_CODE(x
) == CONST_DOUBLE
)
8009 i
= CONST_DOUBLE_LOW (x
);
8012 output_operand_lossage ("invalid %%s operand");
8015 i
= trunc_int_for_mode (i
, SImode
);
8016 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8021 /* Do nothing special. */
8025 /* Undocumented flag. */
8026 output_operand_lossage ("invalid operand output code");
8029 if (GET_CODE (x
) == REG
)
8030 fputs (reg_names
[REGNO (x
)], file
);
8031 else if (GET_CODE (x
) == MEM
)
8034 /* Poor Sun assembler doesn't understand absolute addressing. */
8035 if (CONSTANT_P (XEXP (x
, 0)))
8036 fputs ("%g0+", file
);
8037 output_address (XEXP (x
, 0));
8040 else if (GET_CODE (x
) == HIGH
)
8042 fputs ("%hi(", file
);
8043 output_addr_const (file
, XEXP (x
, 0));
8046 else if (GET_CODE (x
) == LO_SUM
)
8048 sparc_print_operand (file
, XEXP (x
, 0), 0);
8049 if (TARGET_CM_MEDMID
)
8050 fputs ("+%l44(", file
);
8052 fputs ("+%lo(", file
);
8053 output_addr_const (file
, XEXP (x
, 1));
8056 else if (GET_CODE (x
) == CONST_DOUBLE
8057 && (GET_MODE (x
) == VOIDmode
8058 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8060 if (CONST_DOUBLE_HIGH (x
) == 0)
8061 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8062 else if (CONST_DOUBLE_HIGH (x
) == -1
8063 && CONST_DOUBLE_LOW (x
) < 0)
8064 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8066 output_operand_lossage ("long long constant not a valid immediate operand");
8068 else if (GET_CODE (x
) == CONST_DOUBLE
)
8069 output_operand_lossage ("floating point constant not a valid immediate operand");
8070 else { output_addr_const (file
, x
); }
8073 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8076 sparc_print_operand_address (FILE *file
, rtx x
)
8078 register rtx base
, index
= 0;
8080 register rtx addr
= x
;
8083 fputs (reg_names
[REGNO (addr
)], file
);
8084 else if (GET_CODE (addr
) == PLUS
)
8086 if (CONST_INT_P (XEXP (addr
, 0)))
8087 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8088 else if (CONST_INT_P (XEXP (addr
, 1)))
8089 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8091 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8092 if (GET_CODE (base
) == LO_SUM
)
8094 gcc_assert (USE_AS_OFFSETABLE_LO10
8096 && ! TARGET_CM_MEDMID
);
8097 output_operand (XEXP (base
, 0), 0);
8098 fputs ("+%lo(", file
);
8099 output_address (XEXP (base
, 1));
8100 fprintf (file
, ")+%d", offset
);
8104 fputs (reg_names
[REGNO (base
)], file
);
8106 fprintf (file
, "%+d", offset
);
8107 else if (REG_P (index
))
8108 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8109 else if (GET_CODE (index
) == SYMBOL_REF
8110 || GET_CODE (index
) == LABEL_REF
8111 || GET_CODE (index
) == CONST
)
8112 fputc ('+', file
), output_addr_const (file
, index
);
8113 else gcc_unreachable ();
8116 else if (GET_CODE (addr
) == MINUS
8117 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8119 output_addr_const (file
, XEXP (addr
, 0));
8121 output_addr_const (file
, XEXP (addr
, 1));
8122 fputs ("-.)", file
);
8124 else if (GET_CODE (addr
) == LO_SUM
)
8126 output_operand (XEXP (addr
, 0), 0);
8127 if (TARGET_CM_MEDMID
)
8128 fputs ("+%l44(", file
);
8130 fputs ("+%lo(", file
);
8131 output_address (XEXP (addr
, 1));
8135 && GET_CODE (addr
) == CONST
8136 && GET_CODE (XEXP (addr
, 0)) == MINUS
8137 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8138 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8139 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8141 addr
= XEXP (addr
, 0);
8142 output_addr_const (file
, XEXP (addr
, 0));
8143 /* Group the args of the second CONST in parenthesis. */
8145 /* Skip past the second CONST--it does nothing for us. */
8146 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8147 /* Close the parenthesis. */
8152 output_addr_const (file
, addr
);
8156 /* Target hook for assembling integer objects. The sparc version has
8157 special handling for aligned DI-mode objects. */
8160 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8162 /* ??? We only output .xword's for symbols and only then in environments
8163 where the assembler can handle them. */
8164 if (aligned_p
&& size
== 8
8165 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8169 assemble_integer_with_op ("\t.xword\t", x
);
8174 assemble_aligned_integer (4, const0_rtx
);
8175 assemble_aligned_integer (4, x
);
8179 return default_assemble_integer (x
, size
, aligned_p
);
8182 /* Return the value of a code used in the .proc pseudo-op that says
8183 what kind of result this function returns. For non-C types, we pick
8184 the closest C type. */
8186 #ifndef SHORT_TYPE_SIZE
8187 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8190 #ifndef INT_TYPE_SIZE
8191 #define INT_TYPE_SIZE BITS_PER_WORD
8194 #ifndef LONG_TYPE_SIZE
8195 #define LONG_TYPE_SIZE BITS_PER_WORD
8198 #ifndef LONG_LONG_TYPE_SIZE
8199 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8202 #ifndef FLOAT_TYPE_SIZE
8203 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8206 #ifndef DOUBLE_TYPE_SIZE
8207 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8210 #ifndef LONG_DOUBLE_TYPE_SIZE
8211 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8215 sparc_type_code (register tree type
)
8217 register unsigned long qualifiers
= 0;
8218 register unsigned shift
;
8220 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8221 setting more, since some assemblers will give an error for this. Also,
8222 we must be careful to avoid shifts of 32 bits or more to avoid getting
8223 unpredictable results. */
8225 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8227 switch (TREE_CODE (type
))
8233 qualifiers
|= (3 << shift
);
8238 qualifiers
|= (2 << shift
);
8242 case REFERENCE_TYPE
:
8244 qualifiers
|= (1 << shift
);
8248 return (qualifiers
| 8);
8251 case QUAL_UNION_TYPE
:
8252 return (qualifiers
| 9);
8255 return (qualifiers
| 10);
8258 return (qualifiers
| 16);
8261 /* If this is a range type, consider it to be the underlying
8263 if (TREE_TYPE (type
) != 0)
8266 /* Carefully distinguish all the standard types of C,
8267 without messing up if the language is not C. We do this by
8268 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8269 look at both the names and the above fields, but that's redundant.
8270 Any type whose size is between two C types will be considered
8271 to be the wider of the two types. Also, we do not have a
8272 special code to use for "long long", so anything wider than
8273 long is treated the same. Note that we can't distinguish
8274 between "int" and "long" in this code if they are the same
8275 size, but that's fine, since neither can the assembler. */
8277 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8278 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8280 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8281 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8283 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8284 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8287 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8290 /* If this is a range type, consider it to be the underlying
8292 if (TREE_TYPE (type
) != 0)
8295 /* Carefully distinguish all the standard types of C,
8296 without messing up if the language is not C. */
8298 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8299 return (qualifiers
| 6);
8302 return (qualifiers
| 7);
8304 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8305 /* ??? We need to distinguish between double and float complex types,
8306 but I don't know how yet because I can't reach this code from
8307 existing front-ends. */
8308 return (qualifiers
| 7); /* Who knows? */
8311 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8317 gcc_unreachable (); /* Not a type! */
8324 /* Nested function support. */
8326 /* Emit RTL insns to initialize the variable parts of a trampoline.
8327 FNADDR is an RTX for the address of the function's pure code.
8328 CXT is an RTX for the static chain value for the function.
8330 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8331 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8332 (to store insns). This is a bit excessive. Perhaps a different
8333 mechanism would be better here.
8335 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8338 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8340 /* SPARC 32-bit trampoline:
8343 sethi %hi(static), %g2
8345 or %g2, %lo(static), %g2
8347 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8348 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8352 (adjust_address (m_tramp
, SImode
, 0),
8353 expand_binop (SImode
, ior_optab
,
8354 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8355 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8356 NULL_RTX
, 1, OPTAB_DIRECT
));
8359 (adjust_address (m_tramp
, SImode
, 4),
8360 expand_binop (SImode
, ior_optab
,
8361 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8362 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8363 NULL_RTX
, 1, OPTAB_DIRECT
));
8366 (adjust_address (m_tramp
, SImode
, 8),
8367 expand_binop (SImode
, ior_optab
,
8368 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8369 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8370 NULL_RTX
, 1, OPTAB_DIRECT
));
8373 (adjust_address (m_tramp
, SImode
, 12),
8374 expand_binop (SImode
, ior_optab
,
8375 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8376 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8377 NULL_RTX
, 1, OPTAB_DIRECT
));
8379 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8380 aligned on a 16 byte boundary so one flush clears it all. */
8381 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8382 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8383 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8384 && sparc_cpu
!= PROCESSOR_NIAGARA
8385 && sparc_cpu
!= PROCESSOR_NIAGARA2
8386 && sparc_cpu
!= PROCESSOR_NIAGARA3
8387 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8388 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8390 /* Call __enable_execute_stack after writing onto the stack to make sure
8391 the stack address is accessible. */
8392 #ifdef HAVE_ENABLE_EXECUTE_STACK
8393 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8394 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8399 /* The 64-bit version is simpler because it makes more sense to load the
8400 values as "immediate" data out of the trampoline. It's also easier since
8401 we can read the PC without clobbering a register. */
8404 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8406 /* SPARC 64-bit trampoline:
8415 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8416 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8417 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8418 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8419 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8420 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8421 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8422 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8423 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8424 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8425 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8427 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8428 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8429 && sparc_cpu
!= PROCESSOR_NIAGARA
8430 && sparc_cpu
!= PROCESSOR_NIAGARA2
8431 && sparc_cpu
!= PROCESSOR_NIAGARA3
8432 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8433 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8435 /* Call __enable_execute_stack after writing onto the stack to make sure
8436 the stack address is accessible. */
8437 #ifdef HAVE_ENABLE_EXECUTE_STACK
8438 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8439 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8443 /* Worker for TARGET_TRAMPOLINE_INIT. */
8446 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8448 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8449 cxt
= force_reg (Pmode
, cxt
);
8451 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8453 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8456 /* Adjust the cost of a scheduling dependency. Return the new cost of
8457 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8460 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8462 enum attr_type insn_type
;
8464 if (! recog_memoized (insn
))
8467 insn_type
= get_attr_type (insn
);
8469 if (REG_NOTE_KIND (link
) == 0)
8471 /* Data dependency; DEP_INSN writes a register that INSN reads some
8474 /* if a load, then the dependence must be on the memory address;
8475 add an extra "cycle". Note that the cost could be two cycles
8476 if the reg was written late in an instruction group; we ca not tell
8478 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
8481 /* Get the delay only if the address of the store is the dependence. */
8482 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
8484 rtx pat
= PATTERN(insn
);
8485 rtx dep_pat
= PATTERN (dep_insn
);
8487 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8488 return cost
; /* This should not happen! */
8490 /* The dependency between the two instructions was on the data that
8491 is being stored. Assume that this implies that the address of the
8492 store is not dependent. */
8493 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8496 return cost
+ 3; /* An approximation. */
8499 /* A shift instruction cannot receive its data from an instruction
8500 in the same cycle; add a one cycle penalty. */
8501 if (insn_type
== TYPE_SHIFT
)
8502 return cost
+ 3; /* Split before cascade into shift. */
8506 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8507 INSN writes some cycles later. */
8509 /* These are only significant for the fpu unit; writing a fp reg before
8510 the fpu has finished with it stalls the processor. */
8512 /* Reusing an integer register causes no problems. */
8513 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8521 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8523 enum attr_type insn_type
, dep_type
;
8524 rtx pat
= PATTERN(insn
);
8525 rtx dep_pat
= PATTERN (dep_insn
);
8527 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
8530 insn_type
= get_attr_type (insn
);
8531 dep_type
= get_attr_type (dep_insn
);
8533 switch (REG_NOTE_KIND (link
))
8536 /* Data dependency; DEP_INSN writes a register that INSN reads some
8543 /* Get the delay iff the address of the store is the dependence. */
8544 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8547 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8554 /* If a load, then the dependence must be on the memory address. If
8555 the addresses aren't equal, then it might be a false dependency */
8556 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
8558 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
8559 || GET_CODE (SET_DEST (dep_pat
)) != MEM
8560 || GET_CODE (SET_SRC (pat
)) != MEM
8561 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
8562 XEXP (SET_SRC (pat
), 0)))
8570 /* Compare to branch latency is 0. There is no benefit from
8571 separating compare and branch. */
8572 if (dep_type
== TYPE_COMPARE
)
8574 /* Floating point compare to branch latency is less than
8575 compare to conditional move. */
8576 if (dep_type
== TYPE_FPCMP
)
8585 /* Anti-dependencies only penalize the fpu unit. */
8586 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8598 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
8602 case PROCESSOR_SUPERSPARC
:
8603 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
8605 case PROCESSOR_HYPERSPARC
:
8606 case PROCESSOR_SPARCLITE86X
:
8607 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8616 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8617 int sched_verbose ATTRIBUTE_UNUSED
,
8618 int max_ready ATTRIBUTE_UNUSED
)
8622 sparc_use_sched_lookahead (void)
8624 if (sparc_cpu
== PROCESSOR_NIAGARA
8625 || sparc_cpu
== PROCESSOR_NIAGARA2
8626 || sparc_cpu
== PROCESSOR_NIAGARA3
8627 || sparc_cpu
== PROCESSOR_NIAGARA4
)
8629 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8630 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8632 if ((1 << sparc_cpu
) &
8633 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8634 (1 << PROCESSOR_SPARCLITE86X
)))
8640 sparc_issue_rate (void)
8644 case PROCESSOR_NIAGARA
:
8645 case PROCESSOR_NIAGARA2
:
8646 case PROCESSOR_NIAGARA3
:
8647 case PROCESSOR_NIAGARA4
:
8651 /* Assume V9 processors are capable of at least dual-issue. */
8653 case PROCESSOR_SUPERSPARC
:
8655 case PROCESSOR_HYPERSPARC
:
8656 case PROCESSOR_SPARCLITE86X
:
8658 case PROCESSOR_ULTRASPARC
:
8659 case PROCESSOR_ULTRASPARC3
:
8665 set_extends (rtx insn
)
8667 register rtx pat
= PATTERN (insn
);
8669 switch (GET_CODE (SET_SRC (pat
)))
8671 /* Load and some shift instructions zero extend. */
8674 /* sethi clears the high bits */
8676 /* LO_SUM is used with sethi. sethi cleared the high
8677 bits and the values used with lo_sum are positive */
8679 /* Store flag stores 0 or 1 */
8689 rtx op0
= XEXP (SET_SRC (pat
), 0);
8690 rtx op1
= XEXP (SET_SRC (pat
), 1);
8691 if (GET_CODE (op1
) == CONST_INT
)
8692 return INTVAL (op1
) >= 0;
8693 if (GET_CODE (op0
) != REG
)
8695 if (sparc_check_64 (op0
, insn
) == 1)
8697 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8702 rtx op0
= XEXP (SET_SRC (pat
), 0);
8703 rtx op1
= XEXP (SET_SRC (pat
), 1);
8704 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8706 if (GET_CODE (op1
) == CONST_INT
)
8707 return INTVAL (op1
) >= 0;
8708 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8711 return GET_MODE (SET_SRC (pat
)) == SImode
;
8712 /* Positive integers leave the high bits zero. */
8714 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8716 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8719 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8721 return sparc_check_64 (SET_SRC (pat
), insn
);
8727 /* We _ought_ to have only one kind per function, but... */
8728 static GTY(()) rtx sparc_addr_diff_list
;
8729 static GTY(()) rtx sparc_addr_list
;
8732 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8734 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8736 sparc_addr_diff_list
8737 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8739 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8743 sparc_output_addr_vec (rtx vec
)
8745 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8746 int idx
, vlen
= XVECLEN (body
, 0);
8748 #ifdef ASM_OUTPUT_ADDR_VEC_START
8749 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8752 #ifdef ASM_OUTPUT_CASE_LABEL
8753 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8756 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8759 for (idx
= 0; idx
< vlen
; idx
++)
8761 ASM_OUTPUT_ADDR_VEC_ELT
8762 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8765 #ifdef ASM_OUTPUT_ADDR_VEC_END
8766 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8771 sparc_output_addr_diff_vec (rtx vec
)
8773 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8774 rtx base
= XEXP (XEXP (body
, 0), 0);
8775 int idx
, vlen
= XVECLEN (body
, 1);
8777 #ifdef ASM_OUTPUT_ADDR_VEC_START
8778 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8781 #ifdef ASM_OUTPUT_CASE_LABEL
8782 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8785 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8788 for (idx
= 0; idx
< vlen
; idx
++)
8790 ASM_OUTPUT_ADDR_DIFF_ELT
8793 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8794 CODE_LABEL_NUMBER (base
));
8797 #ifdef ASM_OUTPUT_ADDR_VEC_END
8798 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8803 sparc_output_deferred_case_vectors (void)
8808 if (sparc_addr_list
== NULL_RTX
8809 && sparc_addr_diff_list
== NULL_RTX
)
8812 /* Align to cache line in the function's code section. */
8813 switch_to_section (current_function_section ());
8815 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8817 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8819 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8820 sparc_output_addr_vec (XEXP (t
, 0));
8821 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8822 sparc_output_addr_diff_vec (XEXP (t
, 0));
8824 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8827 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8828 unknown. Return 1 if the high bits are zero, -1 if the register is
8831 sparc_check_64 (rtx x
, rtx insn
)
8833 /* If a register is set only once it is safe to ignore insns this
8834 code does not know how to handle. The loop will either recognize
8835 the single set and return the correct value or fail to recognize
8840 gcc_assert (GET_CODE (x
) == REG
);
8842 if (GET_MODE (x
) == DImode
)
8843 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
8845 if (flag_expensive_optimizations
8846 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
8852 insn
= get_last_insn_anywhere ();
8857 while ((insn
= PREV_INSN (insn
)))
8859 switch (GET_CODE (insn
))
8872 rtx pat
= PATTERN (insn
);
8873 if (GET_CODE (pat
) != SET
)
8875 if (rtx_equal_p (x
, SET_DEST (pat
)))
8876 return set_extends (insn
);
8877 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
8878 return set_extends (insn
);
8879 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8887 /* Returns assembly code to perform a DImode shift using
8888 a 64-bit global or out register on SPARC-V8+. */
8890 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
8892 static char asm_code
[60];
8894 /* The scratch register is only required when the destination
8895 register is not a 64-bit global or out register. */
8896 if (which_alternative
!= 2)
8897 operands
[3] = operands
[0];
8899 /* We can only shift by constants <= 63. */
8900 if (GET_CODE (operands
[2]) == CONST_INT
)
8901 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
8903 if (GET_CODE (operands
[1]) == CONST_INT
)
8905 output_asm_insn ("mov\t%1, %3", operands
);
8909 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8910 if (sparc_check_64 (operands
[1], insn
) <= 0)
8911 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8912 output_asm_insn ("or\t%L1, %3, %3", operands
);
8915 strcpy(asm_code
, opcode
);
8917 if (which_alternative
!= 2)
8918 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8920 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8923 /* Output rtl to increment the profiler label LABELNO
8924 for profiling a function entry. */
8927 sparc_profile_hook (int labelno
)
8932 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8933 if (NO_PROFILE_COUNTERS
)
8935 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
8939 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8940 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8941 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8945 #ifdef TARGET_SOLARIS
8946 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8949 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
8950 tree decl ATTRIBUTE_UNUSED
)
8952 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
8954 solaris_elf_asm_comdat_section (name
, flags
, decl
);
8958 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8960 if (!(flags
& SECTION_DEBUG
))
8961 fputs (",#alloc", asm_out_file
);
8962 if (flags
& SECTION_WRITE
)
8963 fputs (",#write", asm_out_file
);
8964 if (flags
& SECTION_TLS
)
8965 fputs (",#tls", asm_out_file
);
8966 if (flags
& SECTION_CODE
)
8967 fputs (",#execinstr", asm_out_file
);
8969 /* ??? Handle SECTION_BSS. */
8971 fputc ('\n', asm_out_file
);
8973 #endif /* TARGET_SOLARIS */
8975 /* We do not allow indirect calls to be optimized into sibling calls.
8977 We cannot use sibling calls when delayed branches are disabled
8978 because they will likely require the call delay slot to be filled.
8980 Also, on SPARC 32-bit we cannot emit a sibling call when the
8981 current function returns a structure. This is because the "unimp
8982 after call" convention would cause the callee to return to the
8983 wrong place. The generic code already disallows cases where the
8984 function being called returns a structure.
8986 It may seem strange how this last case could occur. Usually there
8987 is code after the call which jumps to epilogue code which dumps the
8988 return value into the struct return area. That ought to invalidate
8989 the sibling call right? Well, in the C++ case we can end up passing
8990 the pointer to the struct return area to a constructor (which returns
8991 void) and then nothing else happens. Such a sibling call would look
8992 valid without the added check here.
8994 VxWorks PIC PLT entries require the global pointer to be initialized
8995 on entry. We therefore can't emit sibling calls to them. */
8997 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9000 && flag_delayed_branch
9001 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9002 && !(TARGET_VXWORKS_RTP
9004 && !targetm
.binds_local_p (decl
)));
9007 /* libfunc renaming. */
9010 sparc_init_libfuncs (void)
9014 /* Use the subroutines that Sun's library provides for integer
9015 multiply and divide. The `*' prevents an underscore from
9016 being prepended by the compiler. .umul is a little faster
9018 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9019 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9020 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9021 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9022 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9024 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9025 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9026 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9027 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9028 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9029 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9031 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9032 is because with soft-float, the SFmode and DFmode sqrt
9033 instructions will be absent, and the compiler will notice and
9034 try to use the TFmode sqrt instruction for calls to the
9035 builtin function sqrt, but this fails. */
9037 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9039 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9040 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9041 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9042 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9043 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9044 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9046 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9047 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9048 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9049 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9051 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9052 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9053 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9054 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9056 if (DITF_CONVERSION_LIBFUNCS
)
9058 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9059 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9060 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9061 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9064 if (SUN_CONVERSION_LIBFUNCS
)
9066 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9067 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9068 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9069 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9074 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9075 do not exist in the library. Make sure the compiler does not
9076 emit calls to them by accident. (It should always use the
9077 hardware instructions.) */
9078 set_optab_libfunc (smul_optab
, SImode
, 0);
9079 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9080 set_optab_libfunc (udiv_optab
, SImode
, 0);
9081 set_optab_libfunc (smod_optab
, SImode
, 0);
9082 set_optab_libfunc (umod_optab
, SImode
, 0);
9084 if (SUN_INTEGER_MULTIPLY_64
)
9086 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9087 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9088 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9089 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9090 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9093 if (SUN_CONVERSION_LIBFUNCS
)
9095 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9096 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9097 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9098 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9103 #define def_builtin(NAME, CODE, TYPE) \
9104 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
9107 /* Implement the TARGET_INIT_BUILTINS target hook.
9108 Create builtin functions for special SPARC instructions. */
9111 sparc_init_builtins (void)
9114 sparc_vis_init_builtins ();
9117 /* Create builtin functions for VIS 1.0 instructions. */
9120 sparc_vis_init_builtins (void)
9122 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9123 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9124 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9125 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9126 tree v2si
= build_vector_type (intSI_type_node
, 2);
9128 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9129 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9130 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9131 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9132 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9133 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9134 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9135 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9136 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9137 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9138 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9139 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9140 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9142 intDI_type_node
, 0);
9143 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9145 intDI_type_node
, 0);
9146 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9148 intSI_type_node
, 0);
9149 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9151 intDI_type_node
, 0);
9152 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
9156 /* Packing and expanding vectors. */
9157 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
, v4qi_ftype_v4hi
);
9158 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9159 v8qi_ftype_v2si_v8qi
);
9160 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9162 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
, v4hi_ftype_v4qi
);
9163 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9164 v8qi_ftype_v4qi_v4qi
);
9166 /* Multiplications. */
9167 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9168 v4hi_ftype_v4qi_v4hi
);
9169 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9170 v4hi_ftype_v4qi_v2hi
);
9171 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9172 v4hi_ftype_v4qi_v2hi
);
9173 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9174 v4hi_ftype_v8qi_v4hi
);
9175 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9176 v4hi_ftype_v8qi_v4hi
);
9177 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9178 v2si_ftype_v4qi_v2hi
);
9179 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9180 v2si_ftype_v4qi_v2hi
);
9182 /* Data aligning. */
9183 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9184 v4hi_ftype_v4hi_v4hi
);
9185 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9186 v8qi_ftype_v8qi_v8qi
);
9187 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9188 v2si_ftype_v2si_v2si
);
9189 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
9193 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9195 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
9200 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9202 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
9206 /* Pixel distance. */
9207 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9208 di_ftype_v8qi_v8qi_di
);
9210 /* Edge handling. */
9213 def_builtin ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
9215 def_builtin ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
9217 def_builtin ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
9219 def_builtin ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
9221 def_builtin ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
9223 def_builtin ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
9228 def_builtin ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
9230 def_builtin ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
9232 def_builtin ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
9234 def_builtin ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
9236 def_builtin ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
9238 def_builtin ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
9243 /* Handle TARGET_EXPAND_BUILTIN target hook.
9244 Expand builtin functions for sparc intrinsics. */
9247 sparc_expand_builtin (tree exp
, rtx target
,
9248 rtx subtarget ATTRIBUTE_UNUSED
,
9249 enum machine_mode tmode ATTRIBUTE_UNUSED
,
9250 int ignore ATTRIBUTE_UNUSED
)
9253 call_expr_arg_iterator iter
;
9254 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9255 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
9257 enum machine_mode mode
[4];
9260 mode
[0] = insn_data
[icode
].operand
[0].mode
;
9262 || GET_MODE (target
) != mode
[0]
9263 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
[0]))
9264 op
[0] = gen_reg_rtx (mode
[0]);
9268 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9271 mode
[arg_count
] = insn_data
[icode
].operand
[arg_count
].mode
;
9272 op
[arg_count
] = expand_normal (arg
);
9274 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
9276 op
[arg_count
] = copy_to_mode_reg (mode
[arg_count
], op
[arg_count
]);
9282 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
9285 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
9288 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
9303 sparc_vis_mul8x16 (int e8
, int e16
)
9305 return (e8
* e16
+ 128) / 256;
9308 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9309 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9310 constants. A tree list with the results of the multiplications is returned,
9311 and each element in the list is of INNER_TYPE. */
9314 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
9316 tree n_elts
= NULL_TREE
;
9321 case CODE_FOR_fmul8x16_vis
:
9322 for (; elts0
&& elts1
;
9323 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9326 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9327 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
9328 n_elts
= tree_cons (NULL_TREE
,
9329 build_int_cst (inner_type
, val
),
9334 case CODE_FOR_fmul8x16au_vis
:
9335 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9337 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9340 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9342 n_elts
= tree_cons (NULL_TREE
,
9343 build_int_cst (inner_type
, val
),
9348 case CODE_FOR_fmul8x16al_vis
:
9349 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
9351 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9354 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9356 n_elts
= tree_cons (NULL_TREE
,
9357 build_int_cst (inner_type
, val
),
9366 return nreverse (n_elts
);
9369 /* Handle TARGET_FOLD_BUILTIN target hook.
9370 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9371 result of the function call is ignored. NULL_TREE is returned if the
9372 function could not be folded. */
9375 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
9376 tree
*args
, bool ignore
)
9378 tree arg0
, arg1
, arg2
;
9379 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
9380 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
9383 && icode
!= CODE_FOR_alignaddrsi_vis
9384 && icode
!= CODE_FOR_alignaddrdi_vis
)
9385 return build_zero_cst (rtype
);
9389 case CODE_FOR_fexpand_vis
:
9393 if (TREE_CODE (arg0
) == VECTOR_CST
)
9395 tree inner_type
= TREE_TYPE (rtype
);
9396 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
9397 tree n_elts
= NULL_TREE
;
9399 for (; elts
; elts
= TREE_CHAIN (elts
))
9401 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
9402 n_elts
= tree_cons (NULL_TREE
,
9403 build_int_cst (inner_type
, val
),
9406 return build_vector (rtype
, nreverse (n_elts
));
9410 case CODE_FOR_fmul8x16_vis
:
9411 case CODE_FOR_fmul8x16au_vis
:
9412 case CODE_FOR_fmul8x16al_vis
:
9418 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9420 tree inner_type
= TREE_TYPE (rtype
);
9421 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9422 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9423 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
9426 return build_vector (rtype
, n_elts
);
9430 case CODE_FOR_fpmerge_vis
:
9436 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9438 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9439 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9440 tree n_elts
= NULL_TREE
;
9442 for (; elts0
&& elts1
;
9443 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9445 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
9446 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
9449 return build_vector (rtype
, nreverse (n_elts
));
9453 case CODE_FOR_pdist_vis
:
9461 if (TREE_CODE (arg0
) == VECTOR_CST
9462 && TREE_CODE (arg1
) == VECTOR_CST
9463 && TREE_CODE (arg2
) == INTEGER_CST
)
9466 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
9467 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
9468 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9469 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9471 for (; elts0
&& elts1
;
9472 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9474 unsigned HOST_WIDE_INT
9475 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9476 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9477 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
9478 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
9480 unsigned HOST_WIDE_INT l
;
9483 overflow
|= neg_double (low1
, high1
, &l
, &h
);
9484 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
9486 overflow
|= neg_double (l
, h
, &l
, &h
);
9488 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
9491 gcc_assert (overflow
== 0);
9493 return build_int_cst_wide (rtype
, low
, high
);
9503 /* ??? This duplicates information provided to the compiler by the
9504 ??? scheduler description. Some day, teach genautomata to output
9505 ??? the latencies and then CSE will just use that. */
9508 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
9509 int *total
, bool speed ATTRIBUTE_UNUSED
)
9511 enum machine_mode mode
= GET_MODE (x
);
9512 bool float_mode_p
= FLOAT_MODE_P (mode
);
9517 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
9535 if (GET_MODE (x
) == VOIDmode
9536 && ((CONST_DOUBLE_HIGH (x
) == 0
9537 && CONST_DOUBLE_LOW (x
) < 0x1000)
9538 || (CONST_DOUBLE_HIGH (x
) == -1
9539 && CONST_DOUBLE_LOW (x
) < 0
9540 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
9547 /* If outer-code was a sign or zero extension, a cost
9548 of COSTS_N_INSNS (1) was already added in. This is
9549 why we are subtracting it back out. */
9550 if (outer_code
== ZERO_EXTEND
)
9552 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
9554 else if (outer_code
== SIGN_EXTEND
)
9556 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
9558 else if (float_mode_p
)
9560 *total
= sparc_costs
->float_load
;
9564 *total
= sparc_costs
->int_load
;
9572 *total
= sparc_costs
->float_plusminus
;
9574 *total
= COSTS_N_INSNS (1);
9579 *total
= sparc_costs
->float_mul
;
9580 else if (! TARGET_HARD_MUL
)
9581 *total
= COSTS_N_INSNS (25);
9587 if (sparc_costs
->int_mul_bit_factor
)
9591 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9593 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
9594 for (nbits
= 0; value
!= 0; value
&= value
- 1)
9597 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
9598 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
9600 rtx x1
= XEXP (x
, 1);
9601 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
9602 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
9604 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
9606 for (; value2
!= 0; value2
&= value2
- 1)
9614 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
9615 bit_cost
= COSTS_N_INSNS (bit_cost
);
9619 *total
= sparc_costs
->int_mulX
+ bit_cost
;
9621 *total
= sparc_costs
->int_mul
+ bit_cost
;
9628 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
9638 *total
= sparc_costs
->float_div_df
;
9640 *total
= sparc_costs
->float_div_sf
;
9645 *total
= sparc_costs
->int_divX
;
9647 *total
= sparc_costs
->int_div
;
9654 *total
= COSTS_N_INSNS (1);
9661 case UNSIGNED_FLOAT
:
9665 case FLOAT_TRUNCATE
:
9666 *total
= sparc_costs
->float_move
;
9671 *total
= sparc_costs
->float_sqrt_df
;
9673 *total
= sparc_costs
->float_sqrt_sf
;
9678 *total
= sparc_costs
->float_cmp
;
9680 *total
= COSTS_N_INSNS (1);
9685 *total
= sparc_costs
->float_cmove
;
9687 *total
= sparc_costs
->int_cmove
;
9691 /* Handle the NAND vector patterns. */
9692 if (sparc_vector_mode_supported_p (GET_MODE (x
))
9693 && GET_CODE (XEXP (x
, 0)) == NOT
9694 && GET_CODE (XEXP (x
, 1)) == NOT
)
9696 *total
= COSTS_N_INSNS (1);
9707 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
9710 general_or_i64_p (reg_class_t rclass
)
9712 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
9715 /* Implement TARGET_REGISTER_MOVE_COST. */
9718 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
9719 reg_class_t from
, reg_class_t to
)
9721 if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
9722 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
))
9723 || from
== FPCC_REGS
9726 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9727 || sparc_cpu
== PROCESSOR_ULTRASPARC3
9728 || sparc_cpu
== PROCESSOR_NIAGARA
9729 || sparc_cpu
== PROCESSOR_NIAGARA2
9730 || sparc_cpu
== PROCESSOR_NIAGARA3
9731 || sparc_cpu
== PROCESSOR_NIAGARA4
)
9740 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
9741 This is achieved by means of a manual dynamic stack space allocation in
9742 the current frame. We make the assumption that SEQ doesn't contain any
9743 function calls, with the possible exception of calls to the GOT helper. */
9746 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
9748 /* We must preserve the lowest 16 words for the register save area. */
9749 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
9750 /* We really need only 2 words of fresh stack space. */
9751 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
9754 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
9755 SPARC_STACK_BIAS
+ offset
));
9757 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
9758 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
9760 emit_insn (gen_rtx_SET (VOIDmode
,
9761 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
9765 emit_insn (gen_rtx_SET (VOIDmode
,
9767 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
9768 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
9769 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
9772 /* Output the assembler code for a thunk function. THUNK_DECL is the
9773 declaration for the thunk function itself, FUNCTION is the decl for
9774 the target function. DELTA is an immediate constant offset to be
9775 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9776 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9779 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
9780 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9783 rtx this_rtx
, insn
, funexp
;
9784 unsigned int int_arg_first
;
9786 reload_completed
= 1;
9787 epilogue_completed
= 1;
9789 emit_note (NOTE_INSN_PROLOGUE_END
);
9793 sparc_leaf_function_p
= 1;
9795 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9797 else if (flag_delayed_branch
)
9799 /* We will emit a regular sibcall below, so we need to instruct
9800 output_sibcall that we are in a leaf function. */
9801 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
9803 /* This will cause final.c to invoke leaf_renumber_regs so we
9804 must behave as if we were in a not-yet-leafified function. */
9805 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
9809 /* We will emit the sibcall manually below, so we will need to
9810 manually spill non-leaf registers. */
9811 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
9813 /* We really are in a leaf function. */
9814 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9817 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9818 returns a structure, the structure return pointer is there instead. */
9820 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9821 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
9823 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
9825 /* Add DELTA. When possible use a plain add, otherwise load it into
9826 a register first. */
9829 rtx delta_rtx
= GEN_INT (delta
);
9831 if (! SPARC_SIMM13_P (delta
))
9833 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9834 emit_move_insn (scratch
, delta_rtx
);
9835 delta_rtx
= scratch
;
9838 /* THIS_RTX += DELTA. */
9839 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
9842 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
9845 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
9846 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9848 gcc_assert (vcall_offset
< 0);
9850 /* SCRATCH = *THIS_RTX. */
9851 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
9853 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9854 may not have any available scratch register at this point. */
9855 if (SPARC_SIMM13_P (vcall_offset
))
9857 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9858 else if (! fixed_regs
[5]
9859 /* The below sequence is made up of at least 2 insns,
9860 while the default method may need only one. */
9861 && vcall_offset
< -8192)
9863 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
9864 emit_move_insn (scratch2
, vcall_offset_rtx
);
9865 vcall_offset_rtx
= scratch2
;
9869 rtx increment
= GEN_INT (-4096);
9871 /* VCALL_OFFSET is a negative number whose typical range can be
9872 estimated as -32768..0 in 32-bit mode. In almost all cases
9873 it is therefore cheaper to emit multiple add insns than
9874 spilling and loading the constant into a register (at least
9876 while (! SPARC_SIMM13_P (vcall_offset
))
9878 emit_insn (gen_add2_insn (scratch
, increment
));
9879 vcall_offset
+= 4096;
9881 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
9884 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
9885 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
9886 gen_rtx_PLUS (Pmode
,
9888 vcall_offset_rtx
)));
9890 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
9891 emit_insn (gen_add2_insn (this_rtx
, scratch
));
9894 /* Generate a tail call to the target function. */
9895 if (! TREE_USED (function
))
9897 assemble_external (function
);
9898 TREE_USED (function
) = 1;
9900 funexp
= XEXP (DECL_RTL (function
), 0);
9902 if (flag_delayed_branch
)
9904 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
9905 insn
= emit_call_insn (gen_sibcall (funexp
));
9906 SIBLING_CALL_P (insn
) = 1;
9910 /* The hoops we have to jump through in order to generate a sibcall
9911 without using delay slots... */
9912 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
9916 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
9918 load_got_register (); /* clobbers %o7 */
9919 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
9922 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
9924 else if (TARGET_ARCH32
)
9926 emit_insn (gen_rtx_SET (VOIDmode
,
9928 gen_rtx_HIGH (SImode
, funexp
)));
9929 emit_insn (gen_rtx_SET (VOIDmode
,
9931 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
9933 else /* TARGET_ARCH64 */
9935 switch (sparc_cmodel
)
9939 /* The destination can serve as a temporary. */
9940 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
9945 /* The destination cannot serve as a temporary. */
9946 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
9948 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
9951 emit_and_preserve (seq
, spill_reg
, 0);
9959 emit_jump_insn (gen_indirect_jump (scratch
));
9964 /* Run just enough of rest_of_compilation to get the insns emitted.
9965 There's not really enough bulk here to make other passes such as
9966 instruction scheduling worth while. Note that use_thunk calls
9967 assemble_start_function and assemble_end_function. */
9968 insn
= get_insns ();
9969 insn_locators_alloc ();
9970 shorten_branches (insn
);
9971 final_start_function (insn
, file
, 1);
9972 final (insn
, file
, 1);
9973 final_end_function ();
9975 reload_completed
= 0;
9976 epilogue_completed
= 0;
9979 /* Return true if sparc_output_mi_thunk would be able to output the
9980 assembler code for the thunk function specified by the arguments
9981 it is passed, and false otherwise. */
9983 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
9984 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
9985 HOST_WIDE_INT vcall_offset
,
9986 const_tree function ATTRIBUTE_UNUSED
)
9988 /* Bound the loop used in the default method above. */
9989 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
9992 /* How to allocate a 'struct machine_function'. */
9994 static struct machine_function
*
9995 sparc_init_machine_status (void)
9997 return ggc_alloc_cleared_machine_function ();
10000 /* Locate some local-dynamic symbol still in use by this function
10001 so that we can print its name in local-dynamic base patterns. */
10003 static const char *
10004 get_some_local_dynamic_name (void)
10008 if (cfun
->machine
->some_ld_name
)
10009 return cfun
->machine
->some_ld_name
;
10011 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10013 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
10014 return cfun
->machine
->some_ld_name
;
10016 gcc_unreachable ();
10020 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10025 && GET_CODE (x
) == SYMBOL_REF
10026 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10028 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
10035 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10036 We need to emit DTP-relative relocations. */
10039 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
10044 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
10047 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
10050 gcc_unreachable ();
10052 output_addr_const (file
, x
);
10056 /* Do whatever processing is required at the end of a file. */
10059 sparc_file_end (void)
10061 /* If we need to emit the special GOT helper function, do so now. */
10062 if (got_helper_rtx
)
10064 const char *name
= XSTR (got_helper_rtx
, 0);
10065 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
10066 #ifdef DWARF2_UNWIND_INFO
10070 if (USE_HIDDEN_LINKONCE
)
10072 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
10073 get_identifier (name
),
10074 build_function_type_list (void_type_node
,
10076 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
10077 NULL_TREE
, void_type_node
);
10078 TREE_STATIC (decl
) = 1;
10079 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
10080 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
10081 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
10082 resolve_unique_section (decl
, 0, flag_function_sections
);
10083 allocate_struct_function (decl
, true);
10084 cfun
->is_thunk
= 1;
10085 current_function_decl
= decl
;
10086 init_varasm_status ();
10087 assemble_start_function (decl
, name
);
10091 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10092 switch_to_section (text_section
);
10094 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10095 ASM_OUTPUT_LABEL (asm_out_file
, name
);
10098 #ifdef DWARF2_UNWIND_INFO
10099 do_cfi
= dwarf2out_do_cfi_asm ();
10101 fprintf (asm_out_file
, "\t.cfi_startproc\n");
10103 if (flag_delayed_branch
)
10104 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10105 reg_name
, reg_name
);
10107 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10108 reg_name
, reg_name
);
10109 #ifdef DWARF2_UNWIND_INFO
10111 fprintf (asm_out_file
, "\t.cfi_endproc\n");
10115 if (NEED_INDICATE_EXEC_STACK
)
10116 file_end_indicate_exec_stack ();
10118 #ifdef TARGET_SOLARIS
10119 solaris_file_end ();
10123 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10124 /* Implement TARGET_MANGLE_TYPE. */
10126 static const char *
10127 sparc_mangle_type (const_tree type
)
10130 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
10131 && TARGET_LONG_DOUBLE_128
)
10134 /* For all other types, use normal C++ mangling. */
10139 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10140 compare and swap on the word containing the byte or half-word. */
10143 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
10145 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10146 rtx addr
= gen_reg_rtx (Pmode
);
10147 rtx off
= gen_reg_rtx (SImode
);
10148 rtx oldv
= gen_reg_rtx (SImode
);
10149 rtx newv
= gen_reg_rtx (SImode
);
10150 rtx oldvalue
= gen_reg_rtx (SImode
);
10151 rtx newvalue
= gen_reg_rtx (SImode
);
10152 rtx res
= gen_reg_rtx (SImode
);
10153 rtx resv
= gen_reg_rtx (SImode
);
10154 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
10156 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
10157 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10159 if (Pmode
!= SImode
)
10160 addr1
= gen_lowpart (SImode
, addr1
);
10161 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10162 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10164 memsi
= gen_rtx_MEM (SImode
, addr
);
10165 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10166 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10168 val
= force_reg (SImode
, memsi
);
10170 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10171 gen_rtx_XOR (SImode
, off
,
10172 GEN_INT (GET_MODE (mem
) == QImode
10175 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10176 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10178 if (GET_MODE (mem
) == QImode
)
10179 mask
= force_reg (SImode
, GEN_INT (0xff));
10181 mask
= force_reg (SImode
, GEN_INT (0xffff));
10183 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10184 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10186 emit_insn (gen_rtx_SET (VOIDmode
, val
,
10187 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10190 oldval
= gen_lowpart (SImode
, oldval
);
10191 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10192 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10194 newval
= gen_lowpart_common (SImode
, newval
);
10195 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10196 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10198 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10199 gen_rtx_AND (SImode
, oldv
, mask
)));
10201 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10202 gen_rtx_AND (SImode
, newv
, mask
)));
10204 end_label
= gen_label_rtx ();
10205 loop_label
= gen_label_rtx ();
10206 emit_label (loop_label
);
10208 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
10209 gen_rtx_IOR (SImode
, oldv
, val
)));
10211 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
10212 gen_rtx_IOR (SImode
, newv
, val
)));
10214 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
10216 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
10218 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
10219 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10222 cc
= gen_compare_reg_1 (NE
, resv
, val
);
10223 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
10225 /* Use cbranchcc4 to separate the compare and branch! */
10226 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
10227 cc
, const0_rtx
, loop_label
));
10229 emit_label (end_label
);
10231 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10232 gen_rtx_AND (SImode
, res
, mask
)));
10234 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10235 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10237 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10240 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10243 sparc_frame_pointer_required (void)
10245 /* If the stack pointer is dynamically modified in the function, it cannot
10246 serve as the frame pointer. */
10247 if (cfun
->calls_alloca
)
10250 /* If the function receives nonlocal gotos, it needs to save the frame
10251 pointer in the nonlocal_goto_save_area object. */
10252 if (cfun
->has_nonlocal_label
)
10255 /* In flat mode, that's it. */
10259 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10260 return !(current_function_is_leaf
&& only_leaf_regs_used ());
10263 /* The way this is structured, we can't eliminate SFP in favor of SP
10264 if the frame pointer is required: we want to use the SFP->HFP elimination
10265 in that case. But the test in update_eliminables doesn't know we are
10266 assuming below that we only do the former elimination. */
10269 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10271 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
10274 /* Return the hard frame pointer directly to bypass the stack bias. */
10277 sparc_builtin_setjmp_frame_value (void)
10279 return hard_frame_pointer_rtx
;
10282 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10283 they won't be allocated. */
10286 sparc_conditional_register_usage (void)
10288 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
10290 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10291 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10293 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10294 /* then honor it. */
10295 if (TARGET_ARCH32
&& fixed_regs
[5])
10297 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
10302 for (regno
= SPARC_FIRST_V9_FP_REG
;
10303 regno
<= SPARC_LAST_V9_FP_REG
;
10305 fixed_regs
[regno
] = 1;
10306 /* %fcc0 is used by v8 and v9. */
10307 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
10308 regno
<= SPARC_LAST_V9_FCC_REG
;
10310 fixed_regs
[regno
] = 1;
10315 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
10316 fixed_regs
[regno
] = 1;
10318 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10319 /* then honor it. Likewise with g3 and g4. */
10320 if (fixed_regs
[2] == 2)
10321 fixed_regs
[2] = ! TARGET_APP_REGS
;
10322 if (fixed_regs
[3] == 2)
10323 fixed_regs
[3] = ! TARGET_APP_REGS
;
10324 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
10325 fixed_regs
[4] = ! TARGET_APP_REGS
;
10326 else if (TARGET_CM_EMBMEDANY
)
10328 else if (fixed_regs
[4] == 2)
10333 /* Disable leaf functions. */
10334 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
10335 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
10336 leaf_reg_remap
[regno
] = regno
;
10340 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10342 - We can't load constants into FP registers.
10343 - We can't load FP constants into integer registers when soft-float,
10344 because there is no soft-float pattern with a r/F constraint.
10345 - We can't load FP constants into integer registers for TFmode unless
10346 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10347 - Try and reload integer constants (symbolic or otherwise) back into
10348 registers directly, rather than having them dumped to memory. */
10351 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
10353 if (CONSTANT_P (x
))
10355 if (FP_REG_CLASS_P (rclass
)
10356 || rclass
== GENERAL_OR_FP_REGS
10357 || rclass
== GENERAL_OR_EXTRA_FP_REGS
10358 || (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
&& ! TARGET_FPU
)
10359 || (GET_MODE (x
) == TFmode
&& ! const_zero_operand (x
, TFmode
)))
10362 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
10363 return GENERAL_REGS
;
10369 #include "gt-sparc.h"