1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
51 #include "tree-gimple.h"
52 #include "langhooks.h"
56 struct processor_costs cypress_costs
= {
57 COSTS_N_INSNS (2), /* int load */
58 COSTS_N_INSNS (2), /* int signed load */
59 COSTS_N_INSNS (2), /* int zeroed load */
60 COSTS_N_INSNS (2), /* float load */
61 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
62 COSTS_N_INSNS (5), /* fadd, fsub */
63 COSTS_N_INSNS (1), /* fcmp */
64 COSTS_N_INSNS (1), /* fmov, fmovr */
65 COSTS_N_INSNS (7), /* fmul */
66 COSTS_N_INSNS (37), /* fdivs */
67 COSTS_N_INSNS (37), /* fdivd */
68 COSTS_N_INSNS (63), /* fsqrts */
69 COSTS_N_INSNS (63), /* fsqrtd */
70 COSTS_N_INSNS (1), /* imul */
71 COSTS_N_INSNS (1), /* imulX */
72 0, /* imul bit factor */
73 COSTS_N_INSNS (1), /* idiv */
74 COSTS_N_INSNS (1), /* idivX */
75 COSTS_N_INSNS (1), /* movcc/movr */
76 0, /* shift penalty */
80 struct processor_costs supersparc_costs
= {
81 COSTS_N_INSNS (1), /* int load */
82 COSTS_N_INSNS (1), /* int signed load */
83 COSTS_N_INSNS (1), /* int zeroed load */
84 COSTS_N_INSNS (0), /* float load */
85 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
86 COSTS_N_INSNS (3), /* fadd, fsub */
87 COSTS_N_INSNS (3), /* fcmp */
88 COSTS_N_INSNS (1), /* fmov, fmovr */
89 COSTS_N_INSNS (3), /* fmul */
90 COSTS_N_INSNS (6), /* fdivs */
91 COSTS_N_INSNS (9), /* fdivd */
92 COSTS_N_INSNS (12), /* fsqrts */
93 COSTS_N_INSNS (12), /* fsqrtd */
94 COSTS_N_INSNS (4), /* imul */
95 COSTS_N_INSNS (4), /* imulX */
96 0, /* imul bit factor */
97 COSTS_N_INSNS (4), /* idiv */
98 COSTS_N_INSNS (4), /* idivX */
99 COSTS_N_INSNS (1), /* movcc/movr */
100 1, /* shift penalty */
104 struct processor_costs hypersparc_costs
= {
105 COSTS_N_INSNS (1), /* int load */
106 COSTS_N_INSNS (1), /* int signed load */
107 COSTS_N_INSNS (1), /* int zeroed load */
108 COSTS_N_INSNS (1), /* float load */
109 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
110 COSTS_N_INSNS (1), /* fadd, fsub */
111 COSTS_N_INSNS (1), /* fcmp */
112 COSTS_N_INSNS (1), /* fmov, fmovr */
113 COSTS_N_INSNS (1), /* fmul */
114 COSTS_N_INSNS (8), /* fdivs */
115 COSTS_N_INSNS (12), /* fdivd */
116 COSTS_N_INSNS (17), /* fsqrts */
117 COSTS_N_INSNS (17), /* fsqrtd */
118 COSTS_N_INSNS (17), /* imul */
119 COSTS_N_INSNS (17), /* imulX */
120 0, /* imul bit factor */
121 COSTS_N_INSNS (17), /* idiv */
122 COSTS_N_INSNS (17), /* idivX */
123 COSTS_N_INSNS (1), /* movcc/movr */
124 0, /* shift penalty */
128 struct processor_costs sparclet_costs
= {
129 COSTS_N_INSNS (3), /* int load */
130 COSTS_N_INSNS (3), /* int signed load */
131 COSTS_N_INSNS (1), /* int zeroed load */
132 COSTS_N_INSNS (1), /* float load */
133 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
134 COSTS_N_INSNS (1), /* fadd, fsub */
135 COSTS_N_INSNS (1), /* fcmp */
136 COSTS_N_INSNS (1), /* fmov, fmovr */
137 COSTS_N_INSNS (1), /* fmul */
138 COSTS_N_INSNS (1), /* fdivs */
139 COSTS_N_INSNS (1), /* fdivd */
140 COSTS_N_INSNS (1), /* fsqrts */
141 COSTS_N_INSNS (1), /* fsqrtd */
142 COSTS_N_INSNS (5), /* imul */
143 COSTS_N_INSNS (5), /* imulX */
144 0, /* imul bit factor */
145 COSTS_N_INSNS (5), /* idiv */
146 COSTS_N_INSNS (5), /* idivX */
147 COSTS_N_INSNS (1), /* movcc/movr */
148 0, /* shift penalty */
152 struct processor_costs ultrasparc_costs
= {
153 COSTS_N_INSNS (2), /* int load */
154 COSTS_N_INSNS (3), /* int signed load */
155 COSTS_N_INSNS (2), /* int zeroed load */
156 COSTS_N_INSNS (2), /* float load */
157 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
158 COSTS_N_INSNS (4), /* fadd, fsub */
159 COSTS_N_INSNS (1), /* fcmp */
160 COSTS_N_INSNS (2), /* fmov, fmovr */
161 COSTS_N_INSNS (4), /* fmul */
162 COSTS_N_INSNS (13), /* fdivs */
163 COSTS_N_INSNS (23), /* fdivd */
164 COSTS_N_INSNS (13), /* fsqrts */
165 COSTS_N_INSNS (23), /* fsqrtd */
166 COSTS_N_INSNS (4), /* imul */
167 COSTS_N_INSNS (4), /* imulX */
168 2, /* imul bit factor */
169 COSTS_N_INSNS (37), /* idiv */
170 COSTS_N_INSNS (68), /* idivX */
171 COSTS_N_INSNS (2), /* movcc/movr */
172 2, /* shift penalty */
176 struct processor_costs ultrasparc3_costs
= {
177 COSTS_N_INSNS (2), /* int load */
178 COSTS_N_INSNS (3), /* int signed load */
179 COSTS_N_INSNS (3), /* int zeroed load */
180 COSTS_N_INSNS (2), /* float load */
181 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
182 COSTS_N_INSNS (4), /* fadd, fsub */
183 COSTS_N_INSNS (5), /* fcmp */
184 COSTS_N_INSNS (3), /* fmov, fmovr */
185 COSTS_N_INSNS (4), /* fmul */
186 COSTS_N_INSNS (17), /* fdivs */
187 COSTS_N_INSNS (20), /* fdivd */
188 COSTS_N_INSNS (20), /* fsqrts */
189 COSTS_N_INSNS (29), /* fsqrtd */
190 COSTS_N_INSNS (6), /* imul */
191 COSTS_N_INSNS (6), /* imulX */
192 0, /* imul bit factor */
193 COSTS_N_INSNS (40), /* idiv */
194 COSTS_N_INSNS (71), /* idivX */
195 COSTS_N_INSNS (2), /* movcc/movr */
196 0, /* shift penalty */
199 const struct processor_costs
*sparc_costs
= &cypress_costs
;
201 #ifdef HAVE_AS_RELAX_OPTION
202 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
203 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
204 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
205 somebody does not branch between the sethi and jmp. */
206 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
208 #define LEAF_SIBCALL_SLOT_RESERVED_P \
209 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
212 /* Global variables for machine-dependent things. */
214 /* Size of frame. Need to know this to emit return insns from leaf procedures.
215 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
216 reload pass. This is important as the value is later used for scheduling
217 (to see what can go in a delay slot).
218 APPARENT_FSIZE is the size of the stack less the register save area and less
219 the outgoing argument area. It is used when saving call preserved regs. */
220 static HOST_WIDE_INT apparent_fsize
;
221 static HOST_WIDE_INT actual_fsize
;
223 /* Number of live general or floating point registers needed to be
224 saved (as 4-byte quantities). */
225 static int num_gfregs
;
227 /* The alias set for prologue/epilogue register save/restore. */
228 static GTY(()) int sparc_sr_alias_set
;
230 /* The alias set for the structure return value. */
231 static GTY(()) int struct_value_alias_set
;
233 /* Save the operands last given to a compare for use when we
234 generate a scc or bcc insn. */
235 rtx sparc_compare_op0
, sparc_compare_op1
, sparc_compare_emitted
;
237 /* Vector to say how input registers are mapped to output registers.
238 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
239 eliminate it. You must use -fomit-frame-pointer to get that. */
240 char leaf_reg_remap
[] =
241 { 0, 1, 2, 3, 4, 5, 6, 7,
242 -1, -1, -1, -1, -1, -1, 14, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1,
244 8, 9, 10, 11, 12, 13, -1, 15,
246 32, 33, 34, 35, 36, 37, 38, 39,
247 40, 41, 42, 43, 44, 45, 46, 47,
248 48, 49, 50, 51, 52, 53, 54, 55,
249 56, 57, 58, 59, 60, 61, 62, 63,
250 64, 65, 66, 67, 68, 69, 70, 71,
251 72, 73, 74, 75, 76, 77, 78, 79,
252 80, 81, 82, 83, 84, 85, 86, 87,
253 88, 89, 90, 91, 92, 93, 94, 95,
254 96, 97, 98, 99, 100};
256 /* Vector, indexed by hard register number, which contains 1
257 for a register that is allowable in a candidate for leaf
258 function treatment. */
259 char sparc_leaf_regs
[] =
260 { 1, 1, 1, 1, 1, 1, 1, 1,
261 0, 0, 0, 0, 0, 0, 1, 0,
262 0, 0, 0, 0, 0, 0, 0, 0,
263 1, 1, 1, 1, 1, 1, 0, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1, 1, 1, 1,
268 1, 1, 1, 1, 1, 1, 1, 1,
269 1, 1, 1, 1, 1, 1, 1, 1,
270 1, 1, 1, 1, 1, 1, 1, 1,
271 1, 1, 1, 1, 1, 1, 1, 1,
274 struct machine_function
GTY(())
276 /* Some local-dynamic TLS symbol name. */
277 const char *some_ld_name
;
279 /* True if the current function is leaf and uses only leaf regs,
280 so that the SPARC leaf function optimization can be applied.
281 Private version of current_function_uses_only_leaf_regs, see
282 sparc_expand_prologue for the rationale. */
285 /* True if the data calculated by sparc_expand_prologue are valid. */
286 bool prologue_data_valid_p
;
289 #define sparc_leaf_function_p cfun->machine->leaf_function_p
290 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
292 /* Register we pretend to think the frame pointer is allocated to.
293 Normally, this is %fp, but if we are in a leaf procedure, this
294 is %sp+"something". We record "something" separately as it may
295 be too big for reg+constant addressing. */
296 static rtx frame_base_reg
;
297 static HOST_WIDE_INT frame_base_offset
;
299 /* 1 if the next opcode is to be specially indented. */
300 int sparc_indent_opcode
= 0;
302 static bool sparc_handle_option (size_t, const char *, int);
303 static void sparc_init_modes (void);
304 static void scan_record_type (tree
, int *, int *, int *);
305 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
306 tree
, int, int, int *, int *);
308 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
309 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
311 static void sparc_output_addr_vec (rtx
);
312 static void sparc_output_addr_diff_vec (rtx
);
313 static void sparc_output_deferred_case_vectors (void);
314 static rtx
sparc_builtin_saveregs (void);
315 static int epilogue_renumber (rtx
*, int);
316 static bool sparc_assemble_integer (rtx
, unsigned int, int);
317 static int set_extends (rtx
);
318 static void emit_pic_helper (void);
319 static void load_pic_register (bool);
320 static int save_or_restore_regs (int, int, rtx
, int, int);
321 static void emit_save_or_restore_regs (int);
322 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
323 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
324 #ifdef OBJECT_FORMAT_ELF
325 static void sparc_elf_asm_named_section (const char *, unsigned int, tree
);
328 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
329 static int sparc_issue_rate (void);
330 static void sparc_sched_init (FILE *, int, int);
331 static int sparc_use_sched_lookahead (void);
333 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
334 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
335 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
336 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
337 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
339 static bool sparc_function_ok_for_sibcall (tree
, tree
);
340 static void sparc_init_libfuncs (void);
341 static void sparc_init_builtins (void);
342 static void sparc_vis_init_builtins (void);
343 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
344 static tree
sparc_fold_builtin (tree
, tree
, bool);
345 static int sparc_vis_mul8x16 (int, int);
346 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
347 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
348 HOST_WIDE_INT
, tree
);
349 static bool sparc_can_output_mi_thunk (tree
, HOST_WIDE_INT
,
350 HOST_WIDE_INT
, tree
);
351 static struct machine_function
* sparc_init_machine_status (void);
352 static bool sparc_cannot_force_const_mem (rtx
);
353 static rtx
sparc_tls_get_addr (void);
354 static rtx
sparc_tls_got (void);
355 static const char *get_some_local_dynamic_name (void);
356 static int get_some_local_dynamic_name_1 (rtx
*, void *);
357 static bool sparc_rtx_costs (rtx
, int, int, int *);
358 static bool sparc_promote_prototypes (tree
);
359 static rtx
sparc_struct_value_rtx (tree
, int);
360 static bool sparc_return_in_memory (tree
, tree
);
361 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS
*);
362 static tree
sparc_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
363 static bool sparc_vector_mode_supported_p (enum machine_mode
);
364 static bool sparc_pass_by_reference (CUMULATIVE_ARGS
*,
365 enum machine_mode
, tree
, bool);
366 static int sparc_arg_partial_bytes (CUMULATIVE_ARGS
*,
367 enum machine_mode
, tree
, bool);
368 static void sparc_dwarf_handle_frame_unspec (const char *, rtx
, int);
369 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
370 static void sparc_file_end (void);
371 #ifdef SUBTARGET_ATTRIBUTE_TABLE
372 const struct attribute_spec sparc_attribute_table
[];
375 /* Option handling. */
378 enum cmodel sparc_cmodel
;
380 char sparc_hard_reg_printed
[8];
382 struct sparc_cpu_select sparc_select
[] =
384 /* switch name, tune arch */
385 { (char *)0, "default", 1, 1 },
386 { (char *)0, "-mcpu=", 1, 1 },
387 { (char *)0, "-mtune=", 1, 0 },
391 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
392 enum processor_type sparc_cpu
;
394 /* Whether\fan FPU option was specified. */
395 static bool fpu_option_set
= false;
397 /* Initialize the GCC target structure. */
399 /* The sparc default is to use .half rather than .short for aligned
400 HI objects. Use .word instead of .long on non-ELF systems. */
401 #undef TARGET_ASM_ALIGNED_HI_OP
402 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
403 #ifndef OBJECT_FORMAT_ELF
404 #undef TARGET_ASM_ALIGNED_SI_OP
405 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
408 #undef TARGET_ASM_UNALIGNED_HI_OP
409 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
410 #undef TARGET_ASM_UNALIGNED_SI_OP
411 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
412 #undef TARGET_ASM_UNALIGNED_DI_OP
413 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
415 /* The target hook has to handle DI-mode values. */
416 #undef TARGET_ASM_INTEGER
417 #define TARGET_ASM_INTEGER sparc_assemble_integer
419 #undef TARGET_ASM_FUNCTION_PROLOGUE
420 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
421 #undef TARGET_ASM_FUNCTION_EPILOGUE
422 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
424 #undef TARGET_SCHED_ADJUST_COST
425 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
426 #undef TARGET_SCHED_ISSUE_RATE
427 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
428 #undef TARGET_SCHED_INIT
429 #define TARGET_SCHED_INIT sparc_sched_init
430 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
431 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
433 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
434 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
436 #undef TARGET_INIT_LIBFUNCS
437 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
438 #undef TARGET_INIT_BUILTINS
439 #define TARGET_INIT_BUILTINS sparc_init_builtins
441 #undef TARGET_EXPAND_BUILTIN
442 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
443 #undef TARGET_FOLD_BUILTIN
444 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
447 #undef TARGET_HAVE_TLS
448 #define TARGET_HAVE_TLS true
451 #undef TARGET_CANNOT_FORCE_CONST_MEM
452 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
454 #undef TARGET_ASM_OUTPUT_MI_THUNK
455 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
456 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
457 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
459 #undef TARGET_RTX_COSTS
460 #define TARGET_RTX_COSTS sparc_rtx_costs
461 #undef TARGET_ADDRESS_COST
462 #define TARGET_ADDRESS_COST hook_int_rtx_0
464 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
465 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
466 test for this value. */
467 #undef TARGET_PROMOTE_FUNCTION_ARGS
468 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
470 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
471 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
472 test for this value. */
473 #undef TARGET_PROMOTE_FUNCTION_RETURN
474 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
476 #undef TARGET_PROMOTE_PROTOTYPES
477 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
479 #undef TARGET_STRUCT_VALUE_RTX
480 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
481 #undef TARGET_RETURN_IN_MEMORY
482 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
483 #undef TARGET_MUST_PASS_IN_STACK
484 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
485 #undef TARGET_PASS_BY_REFERENCE
486 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
487 #undef TARGET_ARG_PARTIAL_BYTES
488 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
490 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
491 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
492 #undef TARGET_STRICT_ARGUMENT_NAMING
493 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
495 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
496 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
498 #undef TARGET_VECTOR_MODE_SUPPORTED_P
499 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
501 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
502 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
504 #ifdef SUBTARGET_INSERT_ATTRIBUTES
505 #undef TARGET_INSERT_ATTRIBUTES
506 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
509 #ifdef SUBTARGET_ATTRIBUTE_TABLE
510 #undef TARGET_ATTRIBUTE_TABLE
511 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
514 #undef TARGET_RELAXED_ORDERING
515 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
517 #undef TARGET_DEFAULT_TARGET_FLAGS
518 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
519 #undef TARGET_HANDLE_OPTION
520 #define TARGET_HANDLE_OPTION sparc_handle_option
523 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
524 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
527 #undef TARGET_ASM_FILE_END
528 #define TARGET_ASM_FILE_END sparc_file_end
530 struct gcc_target targetm
= TARGET_INITIALIZER
;
532 /* Implement TARGET_HANDLE_OPTION. */
535 sparc_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
540 case OPT_mhard_float
:
541 case OPT_msoft_float
:
542 fpu_option_set
= true;
546 sparc_select
[1].string
= arg
;
550 sparc_select
[2].string
= arg
;
557 /* Validate and override various options, and do some machine dependent
561 sparc_override_options (void)
563 static struct code_model
{
564 const char *const name
;
566 } const cmodels
[] = {
568 { "medlow", CM_MEDLOW
},
569 { "medmid", CM_MEDMID
},
570 { "medany", CM_MEDANY
},
571 { "embmedany", CM_EMBMEDANY
},
574 const struct code_model
*cmodel
;
575 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
576 static struct cpu_default
{
578 const char *const name
;
579 } const cpu_default
[] = {
580 /* There must be one entry here for each TARGET_CPU value. */
581 { TARGET_CPU_sparc
, "cypress" },
582 { TARGET_CPU_sparclet
, "tsc701" },
583 { TARGET_CPU_sparclite
, "f930" },
584 { TARGET_CPU_v8
, "v8" },
585 { TARGET_CPU_hypersparc
, "hypersparc" },
586 { TARGET_CPU_sparclite86x
, "sparclite86x" },
587 { TARGET_CPU_supersparc
, "supersparc" },
588 { TARGET_CPU_v9
, "v9" },
589 { TARGET_CPU_ultrasparc
, "ultrasparc" },
590 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
593 const struct cpu_default
*def
;
594 /* Table of values for -m{cpu,tune}=. */
595 static struct cpu_table
{
596 const char *const name
;
597 const enum processor_type processor
;
600 } const cpu_table
[] = {
601 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
602 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
603 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
604 /* TI TMS390Z55 supersparc */
605 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
606 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
607 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
608 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
609 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
610 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
611 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
612 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
614 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
616 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
617 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
618 /* TI ultrasparc I, II, IIi */
619 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
620 /* Although insns using %y are deprecated, it is a clear win on current
622 |MASK_DEPRECATED_V8_INSNS
},
623 /* TI ultrasparc III */
624 /* ??? Check if %y issue still holds true in ultra3. */
625 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
628 const struct cpu_table
*cpu
;
629 const struct sparc_cpu_select
*sel
;
632 #ifndef SPARC_BI_ARCH
633 /* Check for unsupported architecture size. */
634 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
635 error ("%s is not supported by this configuration",
636 DEFAULT_ARCH32_P
? "-m64" : "-m32");
639 /* We force all 64bit archs to use 128 bit long double */
640 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
642 error ("-mlong-double-64 not allowed with -m64");
643 target_flags
|= MASK_LONG_DOUBLE_128
;
646 /* Code model selection. */
647 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
651 sparc_cmodel
= CM_32
;
654 if (sparc_cmodel_string
!= NULL
)
658 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
659 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
661 if (cmodel
->name
== NULL
)
662 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
664 sparc_cmodel
= cmodel
->value
;
667 error ("-mcmodel= is not supported on 32 bit systems");
670 fpu
= TARGET_FPU
; /* save current -mfpu status */
672 /* Set the default CPU. */
673 for (def
= &cpu_default
[0]; def
->name
; ++def
)
674 if (def
->cpu
== TARGET_CPU_DEFAULT
)
676 gcc_assert (def
->name
);
677 sparc_select
[0].string
= def
->name
;
679 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
683 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
684 if (! strcmp (sel
->string
, cpu
->name
))
687 sparc_cpu
= cpu
->processor
;
691 target_flags
&= ~cpu
->disable
;
692 target_flags
|= cpu
->enable
;
698 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
702 /* If -mfpu or -mno-fpu was explicitly used, don't override with
703 the processor default. */
705 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
707 /* Don't allow -mvis if FPU is disabled. */
709 target_flags
&= ~MASK_VIS
;
711 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
713 -m64 also implies v9. */
714 if (TARGET_VIS
|| TARGET_ARCH64
)
716 target_flags
|= MASK_V9
;
717 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
720 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
721 if (TARGET_V9
&& TARGET_ARCH32
)
722 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
724 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
725 if (! TARGET_V9
|| TARGET_ARCH64
)
726 target_flags
&= ~MASK_V8PLUS
;
728 /* Don't use stack biasing in 32 bit mode. */
730 target_flags
&= ~MASK_STACK_BIAS
;
732 /* Supply a default value for align_functions. */
733 if (align_functions
== 0
734 && (sparc_cpu
== PROCESSOR_ULTRASPARC
735 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
736 align_functions
= 32;
738 /* Validate PCC_STRUCT_RETURN. */
739 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
740 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
742 /* Only use .uaxword when compiling for a 64-bit target. */
744 targetm
.asm_out
.unaligned_op
.di
= NULL
;
746 /* Do various machine dependent initializations. */
749 /* Acquire unique alias sets for our private stuff. */
750 sparc_sr_alias_set
= new_alias_set ();
751 struct_value_alias_set
= new_alias_set ();
753 /* Set up function hooks. */
754 init_machine_status
= sparc_init_machine_status
;
759 case PROCESSOR_CYPRESS
:
760 sparc_costs
= &cypress_costs
;
763 case PROCESSOR_SPARCLITE
:
764 case PROCESSOR_SUPERSPARC
:
765 sparc_costs
= &supersparc_costs
;
769 case PROCESSOR_HYPERSPARC
:
770 case PROCESSOR_SPARCLITE86X
:
771 sparc_costs
= &hypersparc_costs
;
773 case PROCESSOR_SPARCLET
:
774 case PROCESSOR_TSC701
:
775 sparc_costs
= &sparclet_costs
;
778 case PROCESSOR_ULTRASPARC
:
779 sparc_costs
= &ultrasparc_costs
;
781 case PROCESSOR_ULTRASPARC3
:
782 sparc_costs
= &ultrasparc3_costs
;
787 #ifdef SUBTARGET_ATTRIBUTE_TABLE
788 /* Table of valid machine attributes. */
789 const struct attribute_spec sparc_attribute_table
[] =
791 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
792 SUBTARGET_ATTRIBUTE_TABLE
,
793 { NULL
, 0, 0, false, false, false, NULL
}
797 /* Miscellaneous utilities. */
799 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
800 or branch on register contents instructions. */
803 v9_regcmp_p (enum rtx_code code
)
805 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
806 || code
== LE
|| code
== GT
);
809 /* Nonzero if OP is a floating point constant which can
810 be loaded into an integer register using a single
811 sethi instruction. */
816 if (GET_CODE (op
) == CONST_DOUBLE
)
821 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
822 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
823 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
829 /* Nonzero if OP is a floating point constant which can
830 be loaded into an integer register using a single
836 if (GET_CODE (op
) == CONST_DOUBLE
)
841 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
842 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
843 return SPARC_SIMM13_P (i
);
849 /* Nonzero if OP is a floating point constant which can
850 be loaded into an integer register using a high/losum
851 instruction sequence. */
854 fp_high_losum_p (rtx op
)
856 /* The constraints calling this should only be in
857 SFmode move insns, so any constant which cannot
858 be moved using a single insn will do. */
859 if (GET_CODE (op
) == CONST_DOUBLE
)
864 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
865 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
866 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
872 /* Expand a move instruction. Return true if all work is done. */
875 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
877 /* Handle sets of MEM first. */
878 if (GET_CODE (operands
[0]) == MEM
)
880 /* 0 is a register (or a pair of registers) on SPARC. */
881 if (register_or_zero_operand (operands
[1], mode
))
884 if (!reload_in_progress
)
886 operands
[0] = validize_mem (operands
[0]);
887 operands
[1] = force_reg (mode
, operands
[1]);
891 /* Fixup TLS cases. */
893 && CONSTANT_P (operands
[1])
894 && GET_CODE (operands
[1]) != HIGH
895 && sparc_tls_referenced_p (operands
[1]))
897 rtx sym
= operands
[1];
900 if (GET_CODE (sym
) == CONST
&& GET_CODE (XEXP (sym
, 0)) == PLUS
)
902 addend
= XEXP (XEXP (sym
, 0), 1);
903 sym
= XEXP (XEXP (sym
, 0), 0);
906 gcc_assert (SPARC_SYMBOL_REF_TLS_P (sym
));
908 sym
= legitimize_tls_address (sym
);
911 sym
= gen_rtx_PLUS (mode
, sym
, addend
);
912 sym
= force_operand (sym
, operands
[0]);
917 /* Fixup PIC cases. */
918 if (flag_pic
&& CONSTANT_P (operands
[1]))
920 if (pic_address_needs_scratch (operands
[1]))
921 operands
[1] = legitimize_pic_address (operands
[1], mode
, 0);
923 if (GET_CODE (operands
[1]) == LABEL_REF
&& mode
== SImode
)
925 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
929 if (GET_CODE (operands
[1]) == LABEL_REF
&& mode
== DImode
)
931 gcc_assert (TARGET_ARCH64
);
932 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
936 if (symbolic_operand (operands
[1], mode
))
938 operands
[1] = legitimize_pic_address (operands
[1],
940 (reload_in_progress
?
947 /* If we are trying to toss an integer constant into FP registers,
948 or loading a FP or vector constant, force it into memory. */
949 if (CONSTANT_P (operands
[1])
950 && REG_P (operands
[0])
951 && (SPARC_FP_REG_P (REGNO (operands
[0]))
952 || SCALAR_FLOAT_MODE_P (mode
)
953 || VECTOR_MODE_P (mode
)))
955 /* emit_group_store will send such bogosity to us when it is
956 not storing directly into memory. So fix this up to avoid
957 crashes in output_constant_pool. */
958 if (operands
[1] == const0_rtx
)
959 operands
[1] = CONST0_RTX (mode
);
961 /* We can clear FP registers if TARGET_VIS, and always other regs. */
962 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
963 && const_zero_operand (operands
[1], mode
))
966 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
967 /* We are able to build any SF constant in integer registers
968 with at most 2 instructions. */
970 /* And any DF constant in integer registers. */
972 && (reload_completed
|| reload_in_progress
))))
975 operands
[1] = force_const_mem (mode
, operands
[1]);
976 if (!reload_in_progress
)
977 operands
[1] = validize_mem (operands
[1]);
981 /* Accept non-constants and valid constants unmodified. */
982 if (!CONSTANT_P (operands
[1])
983 || GET_CODE (operands
[1]) == HIGH
984 || input_operand (operands
[1], mode
))
990 /* All QImode constants require only one insn, so proceed. */
995 sparc_emit_set_const32 (operands
[0], operands
[1]);
999 /* input_operand should have filtered out 32-bit mode. */
1000 sparc_emit_set_const64 (operands
[0], operands
[1]);
1010 /* Load OP1, a 32-bit constant, into OP0, a register.
1011 We know it can't be done in one insn when we get
1012 here, the move expander guarantees this. */
1015 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1017 enum machine_mode mode
= GET_MODE (op0
);
1020 if (reload_in_progress
|| reload_completed
)
1023 temp
= gen_reg_rtx (mode
);
1025 if (GET_CODE (op1
) == CONST_INT
)
1027 gcc_assert (!small_int_operand (op1
, mode
)
1028 && !const_high_operand (op1
, mode
));
1030 /* Emit them as real moves instead of a HIGH/LO_SUM,
1031 this way CSE can see everything and reuse intermediate
1032 values if it wants. */
1033 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1034 GEN_INT (INTVAL (op1
)
1035 & ~(HOST_WIDE_INT
)0x3ff)));
1037 emit_insn (gen_rtx_SET (VOIDmode
,
1039 gen_rtx_IOR (mode
, temp
,
1040 GEN_INT (INTVAL (op1
) & 0x3ff))));
1044 /* A symbol, emit in the traditional way. */
1045 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1046 gen_rtx_HIGH (mode
, op1
)));
1047 emit_insn (gen_rtx_SET (VOIDmode
,
1048 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1052 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1053 If TEMP is nonzero, we are forbidden to use any other scratch
1054 registers. Otherwise, we are allowed to generate them as needed.
1056 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1057 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1060 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1062 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1065 if (temp
&& GET_MODE (temp
) == TImode
)
1068 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1071 /* SPARC-V9 code-model support. */
1072 switch (sparc_cmodel
)
1075 /* The range spanned by all instructions in the object is less
1076 than 2^31 bytes (2GB) and the distance from any instruction
1077 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1078 than 2^31 bytes (2GB).
1080 The executable must be in the low 4TB of the virtual address
1083 sethi %hi(symbol), %temp1
1084 or %temp1, %lo(symbol), %reg */
1086 temp1
= temp
; /* op0 is allowed. */
1088 temp1
= gen_reg_rtx (DImode
);
1090 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1091 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1095 /* The range spanned by all instructions in the object is less
1096 than 2^31 bytes (2GB) and the distance from any instruction
1097 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1098 than 2^31 bytes (2GB).
1100 The executable must be in the low 16TB of the virtual address
1103 sethi %h44(symbol), %temp1
1104 or %temp1, %m44(symbol), %temp2
1105 sllx %temp2, 12, %temp3
1106 or %temp3, %l44(symbol), %reg */
1111 temp3
= temp
; /* op0 is allowed. */
1115 temp1
= gen_reg_rtx (DImode
);
1116 temp2
= gen_reg_rtx (DImode
);
1117 temp3
= gen_reg_rtx (DImode
);
1120 emit_insn (gen_seth44 (temp1
, op1
));
1121 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1122 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1123 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1124 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1128 /* The range spanned by all instructions in the object is less
1129 than 2^31 bytes (2GB) and the distance from any instruction
1130 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1131 than 2^31 bytes (2GB).
1133 The executable can be placed anywhere in the virtual address
1136 sethi %hh(symbol), %temp1
1137 sethi %lm(symbol), %temp2
1138 or %temp1, %hm(symbol), %temp3
1139 sllx %temp3, 32, %temp4
1140 or %temp4, %temp2, %temp5
1141 or %temp5, %lo(symbol), %reg */
1144 /* It is possible that one of the registers we got for operands[2]
1145 might coincide with that of operands[0] (which is why we made
1146 it TImode). Pick the other one to use as our scratch. */
1147 if (rtx_equal_p (temp
, op0
))
1149 gcc_assert (ti_temp
);
1150 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1153 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1160 temp1
= gen_reg_rtx (DImode
);
1161 temp2
= gen_reg_rtx (DImode
);
1162 temp3
= gen_reg_rtx (DImode
);
1163 temp4
= gen_reg_rtx (DImode
);
1164 temp5
= gen_reg_rtx (DImode
);
1167 emit_insn (gen_sethh (temp1
, op1
));
1168 emit_insn (gen_setlm (temp2
, op1
));
1169 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1170 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1171 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1172 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1173 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1174 emit_insn (gen_setlo (op0
, temp5
, op1
));
1178 /* Old old old backwards compatibility kruft here.
1179 Essentially it is MEDLOW with a fixed 64-bit
1180 virtual base added to all data segment addresses.
1181 Text-segment stuff is computed like MEDANY, we can't
1182 reuse the code above because the relocation knobs
1185 Data segment: sethi %hi(symbol), %temp1
1186 add %temp1, EMBMEDANY_BASE_REG, %temp2
1187 or %temp2, %lo(symbol), %reg */
1188 if (data_segment_operand (op1
, GET_MODE (op1
)))
1192 temp1
= temp
; /* op0 is allowed. */
1197 temp1
= gen_reg_rtx (DImode
);
1198 temp2
= gen_reg_rtx (DImode
);
1201 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1202 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1203 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1206 /* Text segment: sethi %uhi(symbol), %temp1
1207 sethi %hi(symbol), %temp2
1208 or %temp1, %ulo(symbol), %temp3
1209 sllx %temp3, 32, %temp4
1210 or %temp4, %temp2, %temp5
1211 or %temp5, %lo(symbol), %reg */
1216 /* It is possible that one of the registers we got for operands[2]
1217 might coincide with that of operands[0] (which is why we made
1218 it TImode). Pick the other one to use as our scratch. */
1219 if (rtx_equal_p (temp
, op0
))
1221 gcc_assert (ti_temp
);
1222 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1225 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1232 temp1
= gen_reg_rtx (DImode
);
1233 temp2
= gen_reg_rtx (DImode
);
1234 temp3
= gen_reg_rtx (DImode
);
1235 temp4
= gen_reg_rtx (DImode
);
1236 temp5
= gen_reg_rtx (DImode
);
1239 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1240 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1241 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1242 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1243 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1244 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1245 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1246 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1255 #if HOST_BITS_PER_WIDE_INT == 32
1257 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1262 /* These avoid problems when cross compiling. If we do not
1263 go through all this hair then the optimizer will see
1264 invalid REG_EQUAL notes or in some cases none at all. */
1265 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1266 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1267 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1268 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1270 /* The optimizer is not to assume anything about exactly
1271 which bits are set for a HIGH, they are unspecified.
1272 Unfortunately this leads to many missed optimizations
1273 during CSE. We mask out the non-HIGH bits, and matches
1274 a plain movdi, to alleviate this problem. */
1276 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1278 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1282 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1284 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1288 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1290 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1294 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1296 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1299 /* Worker routines for 64-bit constant formation on arch64.
1300 One of the key things to be doing in these emissions is
1301 to create as many temp REGs as possible. This makes it
1302 possible for half-built constants to be used later when
1303 such values are similar to something required later on.
1304 Without doing this, the optimizer cannot see such
1307 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1308 unsigned HOST_WIDE_INT
, int);
1311 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1312 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1314 unsigned HOST_WIDE_INT high_bits
;
1317 high_bits
= (~low_bits
) & 0xffffffff;
1319 high_bits
= low_bits
;
1321 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1324 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1325 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1329 /* If we are XOR'ing with -1, then we should emit a one's complement
1330 instead. This way the combiner will notice logical operations
1331 such as ANDN later on and substitute. */
1332 if ((low_bits
& 0x3ff) == 0x3ff)
1334 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1335 gen_rtx_NOT (DImode
, temp
)));
1339 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1340 gen_safe_XOR64 (temp
,
1341 (-(HOST_WIDE_INT
)0x400
1342 | (low_bits
& 0x3ff)))));
1347 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1348 unsigned HOST_WIDE_INT
, int);
1351 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1352 unsigned HOST_WIDE_INT high_bits
,
1353 unsigned HOST_WIDE_INT low_immediate
,
1358 if ((high_bits
& 0xfffffc00) != 0)
1360 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1361 if ((high_bits
& ~0xfffffc00) != 0)
1362 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1363 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1369 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1373 /* Now shift it up into place. */
1374 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1375 gen_rtx_ASHIFT (DImode
, temp2
,
1376 GEN_INT (shift_count
))));
1378 /* If there is a low immediate part piece, finish up by
1379 putting that in as well. */
1380 if (low_immediate
!= 0)
1381 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1382 gen_safe_OR64 (op0
, low_immediate
)));
1385 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1386 unsigned HOST_WIDE_INT
);
1388 /* Full 64-bit constant decomposition. Even though this is the
1389 'worst' case, we still optimize a few things away. */
1391 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1392 unsigned HOST_WIDE_INT high_bits
,
1393 unsigned HOST_WIDE_INT low_bits
)
1397 if (reload_in_progress
|| reload_completed
)
1400 sub_temp
= gen_reg_rtx (DImode
);
1402 if ((high_bits
& 0xfffffc00) != 0)
1404 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1405 if ((high_bits
& ~0xfffffc00) != 0)
1406 emit_insn (gen_rtx_SET (VOIDmode
,
1408 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1414 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1418 if (!reload_in_progress
&& !reload_completed
)
1420 rtx temp2
= gen_reg_rtx (DImode
);
1421 rtx temp3
= gen_reg_rtx (DImode
);
1422 rtx temp4
= gen_reg_rtx (DImode
);
1424 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1425 gen_rtx_ASHIFT (DImode
, sub_temp
,
1428 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1429 if ((low_bits
& ~0xfffffc00) != 0)
1431 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1432 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1433 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1434 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1438 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1439 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1444 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1445 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1446 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1449 /* We are in the middle of reload, so this is really
1450 painful. However we do still make an attempt to
1451 avoid emitting truly stupid code. */
1452 if (low1
!= const0_rtx
)
1454 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1455 gen_rtx_ASHIFT (DImode
, sub_temp
,
1456 GEN_INT (to_shift
))));
1457 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1458 gen_rtx_IOR (DImode
, op0
, low1
)));
1466 if (low2
!= const0_rtx
)
1468 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1469 gen_rtx_ASHIFT (DImode
, sub_temp
,
1470 GEN_INT (to_shift
))));
1471 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1472 gen_rtx_IOR (DImode
, op0
, low2
)));
1480 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1481 gen_rtx_ASHIFT (DImode
, sub_temp
,
1482 GEN_INT (to_shift
))));
1483 if (low3
!= const0_rtx
)
1484 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1485 gen_rtx_IOR (DImode
, op0
, low3
)));
1490 /* Analyze a 64-bit constant for certain properties. */
1491 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1492 unsigned HOST_WIDE_INT
,
1493 int *, int *, int *);
1496 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1497 unsigned HOST_WIDE_INT low_bits
,
1498 int *hbsp
, int *lbsp
, int *abbasp
)
1500 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1503 lowest_bit_set
= highest_bit_set
= -1;
1507 if ((lowest_bit_set
== -1)
1508 && ((low_bits
>> i
) & 1))
1510 if ((highest_bit_set
== -1)
1511 && ((high_bits
>> (32 - i
- 1)) & 1))
1512 highest_bit_set
= (64 - i
- 1);
1515 && ((highest_bit_set
== -1)
1516 || (lowest_bit_set
== -1)));
1522 if ((lowest_bit_set
== -1)
1523 && ((high_bits
>> i
) & 1))
1524 lowest_bit_set
= i
+ 32;
1525 if ((highest_bit_set
== -1)
1526 && ((low_bits
>> (32 - i
- 1)) & 1))
1527 highest_bit_set
= 32 - i
- 1;
1530 && ((highest_bit_set
== -1)
1531 || (lowest_bit_set
== -1)));
1533 /* If there are no bits set this should have gone out
1534 as one instruction! */
1535 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1536 all_bits_between_are_set
= 1;
1537 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1541 if ((low_bits
& (1 << i
)) != 0)
1546 if ((high_bits
& (1 << (i
- 32))) != 0)
1549 all_bits_between_are_set
= 0;
1552 *hbsp
= highest_bit_set
;
1553 *lbsp
= lowest_bit_set
;
1554 *abbasp
= all_bits_between_are_set
;
1557 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1560 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1561 unsigned HOST_WIDE_INT low_bits
)
1563 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1566 || high_bits
== 0xffffffff)
1569 analyze_64bit_constant (high_bits
, low_bits
,
1570 &highest_bit_set
, &lowest_bit_set
,
1571 &all_bits_between_are_set
);
1573 if ((highest_bit_set
== 63
1574 || lowest_bit_set
== 0)
1575 && all_bits_between_are_set
!= 0)
1578 if ((highest_bit_set
- lowest_bit_set
) < 21)
1584 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1585 unsigned HOST_WIDE_INT
,
1588 static unsigned HOST_WIDE_INT
1589 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1590 unsigned HOST_WIDE_INT low_bits
,
1591 int lowest_bit_set
, int shift
)
1593 HOST_WIDE_INT hi
, lo
;
1595 if (lowest_bit_set
< 32)
1597 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1598 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1603 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1605 gcc_assert (! (hi
& lo
));
1609 /* Here we are sure to be arch64 and this is an integer constant
1610 being loaded into a register. Emit the most efficient
1611 insn sequence possible. Detection of all the 1-insn cases
1612 has been done already. */
1614 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1616 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1617 int lowest_bit_set
, highest_bit_set
;
1618 int all_bits_between_are_set
;
1621 /* Sanity check that we know what we are working with. */
1622 gcc_assert (TARGET_ARCH64
1623 && (GET_CODE (op0
) == SUBREG
1624 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1626 if (reload_in_progress
|| reload_completed
)
1629 if (GET_CODE (op1
) != CONST_INT
)
1631 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1636 temp
= gen_reg_rtx (DImode
);
1638 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1639 low_bits
= (INTVAL (op1
) & 0xffffffff);
1641 /* low_bits bits 0 --> 31
1642 high_bits bits 32 --> 63 */
1644 analyze_64bit_constant (high_bits
, low_bits
,
1645 &highest_bit_set
, &lowest_bit_set
,
1646 &all_bits_between_are_set
);
1648 /* First try for a 2-insn sequence. */
1650 /* These situations are preferred because the optimizer can
1651 * do more things with them:
1653 * sllx %reg, shift, %reg
1655 * srlx %reg, shift, %reg
1656 * 3) mov some_small_const, %reg
1657 * sllx %reg, shift, %reg
1659 if (((highest_bit_set
== 63
1660 || lowest_bit_set
== 0)
1661 && all_bits_between_are_set
!= 0)
1662 || ((highest_bit_set
- lowest_bit_set
) < 12))
1664 HOST_WIDE_INT the_const
= -1;
1665 int shift
= lowest_bit_set
;
1667 if ((highest_bit_set
!= 63
1668 && lowest_bit_set
!= 0)
1669 || all_bits_between_are_set
== 0)
1672 create_simple_focus_bits (high_bits
, low_bits
,
1675 else if (lowest_bit_set
== 0)
1676 shift
= -(63 - highest_bit_set
);
1678 gcc_assert (SPARC_SIMM13_P (the_const
));
1679 gcc_assert (shift
!= 0);
1681 emit_insn (gen_safe_SET64 (temp
, the_const
));
1683 emit_insn (gen_rtx_SET (VOIDmode
,
1685 gen_rtx_ASHIFT (DImode
,
1689 emit_insn (gen_rtx_SET (VOIDmode
,
1691 gen_rtx_LSHIFTRT (DImode
,
1693 GEN_INT (-shift
))));
1697 /* Now a range of 22 or less bits set somewhere.
1698 * 1) sethi %hi(focus_bits), %reg
1699 * sllx %reg, shift, %reg
1700 * 2) sethi %hi(focus_bits), %reg
1701 * srlx %reg, shift, %reg
1703 if ((highest_bit_set
- lowest_bit_set
) < 21)
1705 unsigned HOST_WIDE_INT focus_bits
=
1706 create_simple_focus_bits (high_bits
, low_bits
,
1707 lowest_bit_set
, 10);
1709 gcc_assert (SPARC_SETHI_P (focus_bits
));
1710 gcc_assert (lowest_bit_set
!= 10);
1712 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1714 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1715 if (lowest_bit_set
< 10)
1716 emit_insn (gen_rtx_SET (VOIDmode
,
1718 gen_rtx_LSHIFTRT (DImode
, temp
,
1719 GEN_INT (10 - lowest_bit_set
))));
1720 else if (lowest_bit_set
> 10)
1721 emit_insn (gen_rtx_SET (VOIDmode
,
1723 gen_rtx_ASHIFT (DImode
, temp
,
1724 GEN_INT (lowest_bit_set
- 10))));
1728 /* 1) sethi %hi(low_bits), %reg
1729 * or %reg, %lo(low_bits), %reg
1730 * 2) sethi %hi(~low_bits), %reg
1731 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1734 || high_bits
== 0xffffffff)
1736 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1737 (high_bits
== 0xffffffff));
1741 /* Now, try 3-insn sequences. */
1743 /* 1) sethi %hi(high_bits), %reg
1744 * or %reg, %lo(high_bits), %reg
1745 * sllx %reg, 32, %reg
1749 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1753 /* We may be able to do something quick
1754 when the constant is negated, so try that. */
1755 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1756 (~low_bits
) & 0xfffffc00))
1758 /* NOTE: The trailing bits get XOR'd so we need the
1759 non-negated bits, not the negated ones. */
1760 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1762 if ((((~high_bits
) & 0xffffffff) == 0
1763 && ((~low_bits
) & 0x80000000) == 0)
1764 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1765 && ((~low_bits
) & 0x80000000) != 0))
1767 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1769 if ((SPARC_SETHI_P (fast_int
)
1770 && (~high_bits
& 0xffffffff) == 0)
1771 || SPARC_SIMM13_P (fast_int
))
1772 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1774 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
1779 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1780 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1781 sparc_emit_set_const64 (temp
, negated_const
);
1784 /* If we are XOR'ing with -1, then we should emit a one's complement
1785 instead. This way the combiner will notice logical operations
1786 such as ANDN later on and substitute. */
1787 if (trailing_bits
== 0x3ff)
1789 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1790 gen_rtx_NOT (DImode
, temp
)));
1794 emit_insn (gen_rtx_SET (VOIDmode
,
1796 gen_safe_XOR64 (temp
,
1797 (-0x400 | trailing_bits
))));
1802 /* 1) sethi %hi(xxx), %reg
1803 * or %reg, %lo(xxx), %reg
1804 * sllx %reg, yyy, %reg
1806 * ??? This is just a generalized version of the low_bits==0
1807 * thing above, FIXME...
1809 if ((highest_bit_set
- lowest_bit_set
) < 32)
1811 unsigned HOST_WIDE_INT focus_bits
=
1812 create_simple_focus_bits (high_bits
, low_bits
,
1815 /* We can't get here in this state. */
1816 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
1818 /* So what we know is that the set bits straddle the
1819 middle of the 64-bit word. */
1820 sparc_emit_set_const64_quick2 (op0
, temp
,
1826 /* 1) sethi %hi(high_bits), %reg
1827 * or %reg, %lo(high_bits), %reg
1828 * sllx %reg, 32, %reg
1829 * or %reg, low_bits, %reg
1831 if (SPARC_SIMM13_P(low_bits
)
1832 && ((int)low_bits
> 0))
1834 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
1838 /* The easiest way when all else fails, is full decomposition. */
1840 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1841 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
1843 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
1845 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
1847 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1848 return the mode to be used for the comparison. For floating-point,
1849 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1850 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1851 processing is needed. */
1854 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
1856 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1882 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
1883 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
1885 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
1886 return CCX_NOOVmode
;
1892 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
1899 /* X and Y are two things to compare using CODE. Emit the compare insn and
1900 return the rtx for the cc reg in the proper mode. */
1903 gen_compare_reg (enum rtx_code code
)
1905 rtx x
= sparc_compare_op0
;
1906 rtx y
= sparc_compare_op1
;
1907 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
1910 if (sparc_compare_emitted
!= NULL_RTX
)
1912 cc_reg
= sparc_compare_emitted
;
1913 sparc_compare_emitted
= NULL_RTX
;
1917 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1918 fcc regs (cse can't tell they're really call clobbered regs and will
1919 remove a duplicate comparison even if there is an intervening function
1920 call - it will then try to reload the cc reg via an int reg which is why
1921 we need the movcc patterns). It is possible to provide the movcc
1922 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1923 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1924 to tell cse that CCFPE mode registers (even pseudos) are call
1927 /* ??? This is an experiment. Rather than making changes to cse which may
1928 or may not be easy/clean, we do our own cse. This is possible because
1929 we will generate hard registers. Cse knows they're call clobbered (it
1930 doesn't know the same thing about pseudos). If we guess wrong, no big
1931 deal, but if we win, great! */
1933 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1934 #if 1 /* experiment */
1937 /* We cycle through the registers to ensure they're all exercised. */
1938 static int next_fcc_reg
= 0;
1939 /* Previous x,y for each fcc reg. */
1940 static rtx prev_args
[4][2];
1942 /* Scan prev_args for x,y. */
1943 for (reg
= 0; reg
< 4; reg
++)
1944 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
1949 prev_args
[reg
][0] = x
;
1950 prev_args
[reg
][1] = y
;
1951 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
1953 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
1956 cc_reg
= gen_reg_rtx (mode
);
1957 #endif /* ! experiment */
1958 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1959 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
1961 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
1963 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
1964 gen_rtx_COMPARE (mode
, x
, y
)));
1969 /* This function is used for v9 only.
1970 CODE is the code for an Scc's comparison.
1971 OPERANDS[0] is the target of the Scc insn.
1972 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1973 been generated yet).
1975 This function is needed to turn
1978 (gt (reg:CCX 100 %icc)
1982 (gt:DI (reg:CCX 100 %icc)
1985 IE: The instruction recognizer needs to see the mode of the comparison to
1986 find the right instruction. We could use "gt:DI" right in the
1987 define_expand, but leaving it out allows us to handle DI, SI, etc.
1989 We refer to the global sparc compare operands sparc_compare_op0 and
1990 sparc_compare_op1. */
1993 gen_v9_scc (enum rtx_code compare_code
, register rtx
*operands
)
1996 && (GET_MODE (sparc_compare_op0
) == DImode
1997 || GET_MODE (operands
[0]) == DImode
))
2000 /* Try to use the movrCC insns. */
2002 && GET_MODE_CLASS (GET_MODE (sparc_compare_op0
)) == MODE_INT
2003 && sparc_compare_op1
== const0_rtx
2004 && v9_regcmp_p (compare_code
))
2006 rtx op0
= sparc_compare_op0
;
2009 /* Special case for op0 != 0. This can be done with one instruction if
2010 operands[0] == sparc_compare_op0. */
2012 if (compare_code
== NE
2013 && GET_MODE (operands
[0]) == DImode
2014 && rtx_equal_p (op0
, operands
[0]))
2016 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2017 gen_rtx_IF_THEN_ELSE (DImode
,
2018 gen_rtx_fmt_ee (compare_code
, DImode
,
2025 if (reg_overlap_mentioned_p (operands
[0], op0
))
2027 /* Handle the case where operands[0] == sparc_compare_op0.
2028 We "early clobber" the result. */
2029 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2030 emit_move_insn (op0
, sparc_compare_op0
);
2033 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2034 if (GET_MODE (op0
) != DImode
)
2036 temp
= gen_reg_rtx (DImode
);
2037 convert_move (temp
, op0
, 0);
2041 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2042 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2043 gen_rtx_fmt_ee (compare_code
, DImode
,
2051 operands
[1] = gen_compare_reg (compare_code
);
2053 switch (GET_MODE (operands
[1]))
2063 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2064 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2065 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2066 gen_rtx_fmt_ee (compare_code
,
2067 GET_MODE (operands
[1]),
2068 operands
[1], const0_rtx
),
2069 const1_rtx
, operands
[0])));
2074 /* Emit a conditional jump insn for the v9 architecture using comparison code
2075 CODE and jump target LABEL.
2076 This function exists to take advantage of the v9 brxx insns. */
2079 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2081 gcc_assert (sparc_compare_emitted
== NULL_RTX
);
2082 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2084 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2085 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2087 gen_rtx_LABEL_REF (VOIDmode
, label
),
2091 /* Generate a DFmode part of a hard TFmode register.
2092 REG is the TFmode hard register, LOW is 1 for the
2093 low 64bit of the register and 0 otherwise.
2096 gen_df_reg (rtx reg
, int low
)
2098 int regno
= REGNO (reg
);
2100 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2101 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2102 return gen_rtx_REG (DFmode
, regno
);
2105 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2106 Unlike normal calls, TFmode operands are passed by reference. It is
2107 assumed that no more than 3 operands are required. */
2110 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2112 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2115 /* We only expect to be called for conversions, unary, and binary ops. */
2116 gcc_assert (nargs
== 2 || nargs
== 3);
2118 for (i
= 0; i
< nargs
; ++i
)
2120 rtx this_arg
= operands
[i
];
2123 /* TFmode arguments and return values are passed by reference. */
2124 if (GET_MODE (this_arg
) == TFmode
)
2126 int force_stack_temp
;
2128 force_stack_temp
= 0;
2129 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2130 force_stack_temp
= 1;
2132 if (GET_CODE (this_arg
) == MEM
2133 && ! force_stack_temp
)
2134 this_arg
= XEXP (this_arg
, 0);
2135 else if (CONSTANT_P (this_arg
)
2136 && ! force_stack_temp
)
2138 this_slot
= force_const_mem (TFmode
, this_arg
);
2139 this_arg
= XEXP (this_slot
, 0);
2143 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2145 /* Operand 0 is the return value. We'll copy it out later. */
2147 emit_move_insn (this_slot
, this_arg
);
2149 ret_slot
= this_slot
;
2151 this_arg
= XEXP (this_slot
, 0);
2158 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2160 if (GET_MODE (operands
[0]) == TFmode
)
2163 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2164 arg
[0], GET_MODE (arg
[0]),
2165 arg
[1], GET_MODE (arg
[1]));
2167 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2168 arg
[0], GET_MODE (arg
[0]),
2169 arg
[1], GET_MODE (arg
[1]),
2170 arg
[2], GET_MODE (arg
[2]));
2173 emit_move_insn (operands
[0], ret_slot
);
2179 gcc_assert (nargs
== 2);
2181 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2182 GET_MODE (operands
[0]), 1,
2183 arg
[1], GET_MODE (arg
[1]));
2185 if (ret
!= operands
[0])
2186 emit_move_insn (operands
[0], ret
);
2190 /* Expand soft-float TFmode calls to sparc abi routines. */
2193 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2215 emit_soft_tfmode_libcall (func
, 3, operands
);
2219 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2223 gcc_assert (code
== SQRT
);
2226 emit_soft_tfmode_libcall (func
, 2, operands
);
2230 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2237 switch (GET_MODE (operands
[1]))
2250 case FLOAT_TRUNCATE
:
2251 switch (GET_MODE (operands
[0]))
2265 switch (GET_MODE (operands
[1]))
2278 case UNSIGNED_FLOAT
:
2279 switch (GET_MODE (operands
[1]))
2293 switch (GET_MODE (operands
[0]))
2307 switch (GET_MODE (operands
[0]))
2324 emit_soft_tfmode_libcall (func
, 2, operands
);
2327 /* Expand a hard-float tfmode operation. All arguments must be in
2331 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2335 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2337 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2338 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2342 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2343 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2344 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2345 operands
[1], operands
[2]);
2348 if (register_operand (operands
[0], VOIDmode
))
2351 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2353 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2355 if (dest
!= operands
[0])
2356 emit_move_insn (operands
[0], dest
);
2360 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2362 if (TARGET_HARD_QUAD
)
2363 emit_hard_tfmode_operation (code
, operands
);
2365 emit_soft_tfmode_binop (code
, operands
);
2369 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2371 if (TARGET_HARD_QUAD
)
2372 emit_hard_tfmode_operation (code
, operands
);
2374 emit_soft_tfmode_unop (code
, operands
);
2378 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2380 if (TARGET_HARD_QUAD
)
2381 emit_hard_tfmode_operation (code
, operands
);
2383 emit_soft_tfmode_cvt (code
, operands
);
2386 /* Return nonzero if a branch/jump/call instruction will be emitting
2387 nop into its delay slot. */
2390 empty_delay_slot (rtx insn
)
2394 /* If no previous instruction (should not happen), return true. */
2395 if (PREV_INSN (insn
) == NULL
)
2398 seq
= NEXT_INSN (PREV_INSN (insn
));
2399 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2405 /* Return nonzero if TRIAL can go into the call delay slot. */
2408 tls_call_delay (rtx trial
)
2413 call __tls_get_addr, %tgd_call (foo)
2414 add %l7, %o0, %o0, %tgd_add (foo)
2415 while Sun as/ld does not. */
2416 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2419 pat
= PATTERN (trial
);
2420 if (GET_CODE (pat
) != SET
|| GET_CODE (SET_DEST (pat
)) != PLUS
)
2423 unspec
= XEXP (SET_DEST (pat
), 1);
2424 if (GET_CODE (unspec
) != UNSPEC
2425 || (XINT (unspec
, 1) != UNSPEC_TLSGD
2426 && XINT (unspec
, 1) != UNSPEC_TLSLDM
))
2432 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2433 instruction. RETURN_P is true if the v9 variant 'return' is to be
2434 considered in the test too.
2436 TRIAL must be a SET whose destination is a REG appropriate for the
2437 'restore' instruction or, if RETURN_P is true, for the 'return'
2441 eligible_for_restore_insn (rtx trial
, bool return_p
)
2443 rtx pat
= PATTERN (trial
);
2444 rtx src
= SET_SRC (pat
);
2446 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2447 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2448 && arith_operand (src
, GET_MODE (src
)))
2451 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2453 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2456 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2457 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2458 && arith_double_operand (src
, GET_MODE (src
)))
2459 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2461 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2462 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2465 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2466 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2469 /* If we have the 'return' instruction, anything that does not use
2470 local or output registers and can go into a delay slot wins. */
2471 else if (return_p
&& TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2472 && (get_attr_in_uncond_branch_delay (trial
)
2473 == IN_UNCOND_BRANCH_DELAY_TRUE
))
2476 /* The 'restore src1,src2,dest' pattern for SImode. */
2477 else if (GET_CODE (src
) == PLUS
2478 && register_operand (XEXP (src
, 0), SImode
)
2479 && arith_operand (XEXP (src
, 1), SImode
))
2482 /* The 'restore src1,src2,dest' pattern for DImode. */
2483 else if (GET_CODE (src
) == PLUS
2484 && register_operand (XEXP (src
, 0), DImode
)
2485 && arith_double_operand (XEXP (src
, 1), DImode
))
2488 /* The 'restore src1,%lo(src2),dest' pattern. */
2489 else if (GET_CODE (src
) == LO_SUM
2490 && ! TARGET_CM_MEDMID
2491 && ((register_operand (XEXP (src
, 0), SImode
)
2492 && immediate_operand (XEXP (src
, 1), SImode
))
2494 && register_operand (XEXP (src
, 0), DImode
)
2495 && immediate_operand (XEXP (src
, 1), DImode
))))
2498 /* The 'restore src,src,dest' pattern. */
2499 else if (GET_CODE (src
) == ASHIFT
2500 && (register_operand (XEXP (src
, 0), SImode
)
2501 || register_operand (XEXP (src
, 0), DImode
))
2502 && XEXP (src
, 1) == const1_rtx
)
2508 /* Return nonzero if TRIAL can go into the function return's
2512 eligible_for_return_delay (rtx trial
)
2516 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2519 if (get_attr_length (trial
) != 1)
2522 /* If there are any call-saved registers, we should scan TRIAL if it
2523 does not reference them. For now just make it easy. */
2527 /* If the function uses __builtin_eh_return, the eh_return machinery
2528 occupies the delay slot. */
2529 if (current_function_calls_eh_return
)
2532 /* In the case of a true leaf function, anything can go into the slot. */
2533 if (sparc_leaf_function_p
)
2534 return get_attr_in_uncond_branch_delay (trial
)
2535 == IN_UNCOND_BRANCH_DELAY_TRUE
;
2537 pat
= PATTERN (trial
);
2539 /* Otherwise, only operations which can be done in tandem with
2540 a `restore' or `return' insn can go into the delay slot. */
2541 if (GET_CODE (SET_DEST (pat
)) != REG
2542 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24))
2545 /* If this instruction sets up floating point register and we have a return
2546 instruction, it can probably go in. But restore will not work
2548 if (REGNO (SET_DEST (pat
)) >= 32)
2550 && ! epilogue_renumber (&pat
, 1)
2551 && (get_attr_in_uncond_branch_delay (trial
)
2552 == IN_UNCOND_BRANCH_DELAY_TRUE
));
2554 return eligible_for_restore_insn (trial
, true);
2557 /* Return nonzero if TRIAL can go into the sibling call's
2561 eligible_for_sibcall_delay (rtx trial
)
2565 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2568 if (get_attr_length (trial
) != 1)
2571 pat
= PATTERN (trial
);
2573 if (sparc_leaf_function_p
)
2575 /* If the tail call is done using the call instruction,
2576 we have to restore %o7 in the delay slot. */
2577 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2580 /* %g1 is used to build the function address */
2581 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2587 /* Otherwise, only operations which can be done in tandem with
2588 a `restore' insn can go into the delay slot. */
2589 if (GET_CODE (SET_DEST (pat
)) != REG
2590 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2591 || REGNO (SET_DEST (pat
)) >= 32)
2594 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2596 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2599 return eligible_for_restore_insn (trial
, false);
2603 short_branch (int uid1
, int uid2
)
2605 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2607 /* Leave a few words of "slop". */
2608 if (delta
>= -1023 && delta
<= 1022)
2614 /* Return nonzero if REG is not used after INSN.
2615 We assume REG is a reload reg, and therefore does
2616 not live past labels or calls or jumps. */
2618 reg_unused_after (rtx reg
, rtx insn
)
2620 enum rtx_code code
, prev_code
= UNKNOWN
;
2622 while ((insn
= NEXT_INSN (insn
)))
2624 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2627 code
= GET_CODE (insn
);
2628 if (GET_CODE (insn
) == CODE_LABEL
)
2633 rtx set
= single_set (insn
);
2634 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2637 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2639 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2647 /* Determine if it's legal to put X into the constant pool. This
2648 is not possible if X contains the address of a symbol that is
2649 not constant (TLS) or not known at final link time (PIC). */
2652 sparc_cannot_force_const_mem (rtx x
)
2654 switch (GET_CODE (x
))
2659 /* Accept all non-symbolic constants. */
2663 /* Labels are OK iff we are non-PIC. */
2664 return flag_pic
!= 0;
2667 /* 'Naked' TLS symbol references are never OK,
2668 non-TLS symbols are OK iff we are non-PIC. */
2669 if (SYMBOL_REF_TLS_MODEL (x
))
2672 return flag_pic
!= 0;
2675 return sparc_cannot_force_const_mem (XEXP (x
, 0));
2678 return sparc_cannot_force_const_mem (XEXP (x
, 0))
2679 || sparc_cannot_force_const_mem (XEXP (x
, 1));
2688 static GTY(()) char pic_helper_symbol_name
[256];
2689 static GTY(()) rtx pic_helper_symbol
;
2690 static GTY(()) bool pic_helper_emitted_p
= false;
2691 static GTY(()) rtx global_offset_table
;
2693 /* Ensure that we are not using patterns that are not OK with PIC. */
2701 gcc_assert (GET_CODE (recog_data
.operand
[i
]) != SYMBOL_REF
2702 && (GET_CODE (recog_data
.operand
[i
]) != CONST
2703 || (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
2704 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
2705 == global_offset_table
)
2706 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
2714 /* Return true if X is an address which needs a temporary register when
2715 reloaded while generating PIC code. */
2718 pic_address_needs_scratch (rtx x
)
2720 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2721 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
2722 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2723 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2724 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
2730 /* Determine if a given RTX is a valid constant. We already know this
2731 satisfies CONSTANT_P. */
2734 legitimate_constant_p (rtx x
)
2738 switch (GET_CODE (x
))
2741 /* TLS symbols are not constant. */
2742 if (SYMBOL_REF_TLS_MODEL (x
))
2747 inner
= XEXP (x
, 0);
2749 /* Offsets of TLS symbols are never valid.
2750 Discourage CSE from creating them. */
2751 if (GET_CODE (inner
) == PLUS
2752 && SPARC_SYMBOL_REF_TLS_P (XEXP (inner
, 0)))
2757 if (GET_MODE (x
) == VOIDmode
)
2760 /* Floating point constants are generally not ok.
2761 The only exception is 0.0 in VIS. */
2763 && SCALAR_FLOAT_MODE_P (GET_MODE (x
))
2764 && const_zero_operand (x
, GET_MODE (x
)))
2770 /* Vector constants are generally not ok.
2771 The only exception is 0 in VIS. */
2773 && const_zero_operand (x
, GET_MODE (x
)))
2785 /* Determine if a given RTX is a valid constant address. */
2788 constant_address_p (rtx x
)
2790 switch (GET_CODE (x
))
2798 if (flag_pic
&& pic_address_needs_scratch (x
))
2800 return legitimate_constant_p (x
);
2803 return !flag_pic
&& legitimate_constant_p (x
);
2810 /* Nonzero if the constant value X is a legitimate general operand
2811 when generating PIC code. It is given that flag_pic is on and
2812 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2815 legitimate_pic_operand_p (rtx x
)
2817 if (pic_address_needs_scratch (x
))
2819 if (SPARC_SYMBOL_REF_TLS_P (x
)
2820 || (GET_CODE (x
) == CONST
2821 && GET_CODE (XEXP (x
, 0)) == PLUS
2822 && SPARC_SYMBOL_REF_TLS_P (XEXP (XEXP (x
, 0), 0))))
2827 /* Return nonzero if ADDR is a valid memory address.
2828 STRICT specifies whether strict register checking applies. */
2831 legitimate_address_p (enum machine_mode mode
, rtx addr
, int strict
)
2833 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
2835 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
2837 else if (GET_CODE (addr
) == PLUS
)
2839 rs1
= XEXP (addr
, 0);
2840 rs2
= XEXP (addr
, 1);
2842 /* Canonicalize. REG comes first, if there are no regs,
2843 LO_SUM comes first. */
2845 && GET_CODE (rs1
) != SUBREG
2847 || GET_CODE (rs2
) == SUBREG
2848 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
2850 rs1
= XEXP (addr
, 1);
2851 rs2
= XEXP (addr
, 0);
2855 && rs1
== pic_offset_table_rtx
2857 && GET_CODE (rs2
) != SUBREG
2858 && GET_CODE (rs2
) != LO_SUM
2859 && GET_CODE (rs2
) != MEM
2860 && ! SPARC_SYMBOL_REF_TLS_P (rs2
)
2861 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
2862 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
2864 || GET_CODE (rs1
) == SUBREG
)
2865 && RTX_OK_FOR_OFFSET_P (rs2
)))
2870 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
2871 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
2873 /* We prohibit REG + REG for TFmode when there are no quad move insns
2874 and we consequently need to split. We do this because REG+REG
2875 is not an offsettable address. If we get the situation in reload
2876 where source and destination of a movtf pattern are both MEMs with
2877 REG+REG address, then only one of them gets converted to an
2878 offsettable address. */
2880 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
2883 /* We prohibit REG + REG on ARCH32 if not optimizing for
2884 DFmode/DImode because then mem_min_alignment is likely to be zero
2885 after reload and the forced split would lack a matching splitter
2887 if (TARGET_ARCH32
&& !optimize
2888 && (mode
== DFmode
|| mode
== DImode
))
2891 else if (USE_AS_OFFSETABLE_LO10
2892 && GET_CODE (rs1
) == LO_SUM
2894 && ! TARGET_CM_MEDMID
2895 && RTX_OK_FOR_OLO10_P (rs2
))
2898 imm1
= XEXP (rs1
, 1);
2899 rs1
= XEXP (rs1
, 0);
2900 if (! CONSTANT_P (imm1
) || SPARC_SYMBOL_REF_TLS_P (rs1
))
2904 else if (GET_CODE (addr
) == LO_SUM
)
2906 rs1
= XEXP (addr
, 0);
2907 imm1
= XEXP (addr
, 1);
2909 if (! CONSTANT_P (imm1
) || SPARC_SYMBOL_REF_TLS_P (rs1
))
2912 /* We can't allow TFmode in 32-bit mode, because an offset greater
2913 than the alignment (8) may cause the LO_SUM to overflow. */
2914 if (mode
== TFmode
&& TARGET_ARCH32
)
2917 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
2922 if (GET_CODE (rs1
) == SUBREG
)
2923 rs1
= SUBREG_REG (rs1
);
2929 if (GET_CODE (rs2
) == SUBREG
)
2930 rs2
= SUBREG_REG (rs2
);
2937 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
2938 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
2943 if ((REGNO (rs1
) >= 32
2944 && REGNO (rs1
) != FRAME_POINTER_REGNUM
2945 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
2947 && (REGNO (rs2
) >= 32
2948 && REGNO (rs2
) != FRAME_POINTER_REGNUM
2949 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
2955 /* Construct the SYMBOL_REF for the tls_get_offset function. */
2957 static GTY(()) rtx sparc_tls_symbol
;
2960 sparc_tls_get_addr (void)
2962 if (!sparc_tls_symbol
)
2963 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2965 return sparc_tls_symbol
;
2969 sparc_tls_got (void)
2974 current_function_uses_pic_offset_table
= 1;
2975 return pic_offset_table_rtx
;
2978 if (!global_offset_table
)
2979 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2980 temp
= gen_reg_rtx (Pmode
);
2981 emit_move_insn (temp
, global_offset_table
);
2985 /* Return 1 if *X is a thread-local symbol. */
2988 sparc_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2990 return SPARC_SYMBOL_REF_TLS_P (*x
);
2993 /* Return 1 if X contains a thread-local symbol. */
2996 sparc_tls_referenced_p (rtx x
)
2998 if (!TARGET_HAVE_TLS
)
3001 return for_each_rtx (&x
, &sparc_tls_symbol_ref_1
, 0);
3004 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3005 this (thread-local) address. */
3008 legitimize_tls_address (rtx addr
)
3010 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3012 gcc_assert (! no_new_pseudos
);
3014 if (GET_CODE (addr
) == SYMBOL_REF
)
3015 switch (SYMBOL_REF_TLS_MODEL (addr
))
3017 case TLS_MODEL_GLOBAL_DYNAMIC
:
3019 temp1
= gen_reg_rtx (SImode
);
3020 temp2
= gen_reg_rtx (SImode
);
3021 ret
= gen_reg_rtx (Pmode
);
3022 o0
= gen_rtx_REG (Pmode
, 8);
3023 got
= sparc_tls_got ();
3024 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3025 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3028 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3029 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3034 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3035 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3038 CALL_INSN_FUNCTION_USAGE (insn
)
3039 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3040 CALL_INSN_FUNCTION_USAGE (insn
));
3041 insn
= get_insns ();
3043 emit_libcall_block (insn
, ret
, o0
, addr
);
3046 case TLS_MODEL_LOCAL_DYNAMIC
:
3048 temp1
= gen_reg_rtx (SImode
);
3049 temp2
= gen_reg_rtx (SImode
);
3050 temp3
= gen_reg_rtx (Pmode
);
3051 ret
= gen_reg_rtx (Pmode
);
3052 o0
= gen_rtx_REG (Pmode
, 8);
3053 got
= sparc_tls_got ();
3054 emit_insn (gen_tldm_hi22 (temp1
));
3055 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3058 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3059 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3064 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3065 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3068 CALL_INSN_FUNCTION_USAGE (insn
)
3069 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3070 CALL_INSN_FUNCTION_USAGE (insn
));
3071 insn
= get_insns ();
3073 emit_libcall_block (insn
, temp3
, o0
,
3074 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3075 UNSPEC_TLSLD_BASE
));
3076 temp1
= gen_reg_rtx (SImode
);
3077 temp2
= gen_reg_rtx (SImode
);
3078 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3079 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3081 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3083 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3086 case TLS_MODEL_INITIAL_EXEC
:
3087 temp1
= gen_reg_rtx (SImode
);
3088 temp2
= gen_reg_rtx (SImode
);
3089 temp3
= gen_reg_rtx (Pmode
);
3090 got
= sparc_tls_got ();
3091 emit_insn (gen_tie_hi22 (temp1
, addr
));
3092 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3094 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3096 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3099 ret
= gen_reg_rtx (Pmode
);
3101 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3104 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3108 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3111 case TLS_MODEL_LOCAL_EXEC
:
3112 temp1
= gen_reg_rtx (Pmode
);
3113 temp2
= gen_reg_rtx (Pmode
);
3116 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3117 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3121 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3122 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3124 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3132 gcc_unreachable (); /* for now ... */
3138 /* Legitimize PIC addresses. If the address is already position-independent,
3139 we return ORIG. Newly generated position-independent addresses go into a
3140 reg. This is REG if nonzero, otherwise we allocate register(s) as
3144 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3147 if (GET_CODE (orig
) == SYMBOL_REF
)
3149 rtx pic_ref
, address
;
3154 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3155 reg
= gen_reg_rtx (Pmode
);
3160 /* If not during reload, allocate another temp reg here for loading
3161 in the address, so that these instructions can be optimized
3163 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3164 ? reg
: gen_reg_rtx (Pmode
));
3166 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3167 won't get confused into thinking that these two instructions
3168 are loading in the true address of the symbol. If in the
3169 future a PIC rtx exists, that should be used instead. */
3172 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3173 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3177 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3178 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3185 pic_ref
= gen_const_mem (Pmode
,
3186 gen_rtx_PLUS (Pmode
,
3187 pic_offset_table_rtx
, address
));
3188 current_function_uses_pic_offset_table
= 1;
3189 insn
= emit_move_insn (reg
, pic_ref
);
3190 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3192 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3196 else if (GET_CODE (orig
) == CONST
)
3200 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3201 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3206 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3207 reg
= gen_reg_rtx (Pmode
);
3210 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3211 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3212 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3213 base
== reg
? 0 : reg
);
3215 if (GET_CODE (offset
) == CONST_INT
)
3217 if (SMALL_INT (offset
))
3218 return plus_constant (base
, INTVAL (offset
));
3219 else if (! reload_in_progress
&& ! reload_completed
)
3220 offset
= force_reg (Pmode
, offset
);
3222 /* If we reach here, then something is seriously wrong. */
3225 return gen_rtx_PLUS (Pmode
, base
, offset
);
3227 else if (GET_CODE (orig
) == LABEL_REF
)
3228 /* ??? Why do we do this? */
3229 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3230 the register is live instead, in case it is eliminated. */
3231 current_function_uses_pic_offset_table
= 1;
3236 /* Try machine-dependent ways of modifying an illegitimate address X
3237 to be legitimate. If we find one, return the new, valid address.
3239 OLDX is the address as it was before break_out_memory_refs was called.
3240 In some cases it is useful to look at this to decide what needs to be done.
3242 MODE is the mode of the operand pointed to by X. */
3245 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
, enum machine_mode mode
)
3249 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3250 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3251 force_operand (XEXP (x
, 0), NULL_RTX
));
3252 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3253 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3254 force_operand (XEXP (x
, 1), NULL_RTX
));
3255 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3256 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3258 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3259 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3260 force_operand (XEXP (x
, 1), NULL_RTX
));
3262 if (x
!= orig_x
&& legitimate_address_p (mode
, x
, FALSE
))
3265 if (SPARC_SYMBOL_REF_TLS_P (x
))
3266 x
= legitimize_tls_address (x
);
3268 x
= legitimize_pic_address (x
, mode
, 0);
3269 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3270 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3271 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3272 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3273 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3274 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3275 else if (GET_CODE (x
) == SYMBOL_REF
3276 || GET_CODE (x
) == CONST
3277 || GET_CODE (x
) == LABEL_REF
)
3278 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3282 /* Emit the special PIC helper function. */
3285 emit_pic_helper (void)
3287 const char *pic_name
= reg_names
[REGNO (pic_offset_table_rtx
)];
3292 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3294 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3295 ASM_OUTPUT_LABEL (asm_out_file
, pic_helper_symbol_name
);
3296 if (flag_delayed_branch
)
3297 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
3298 pic_name
, pic_name
);
3300 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
3301 pic_name
, pic_name
);
3303 pic_helper_emitted_p
= true;
3306 /* Emit code to load the PIC register. */
3309 load_pic_register (bool delay_pic_helper
)
3311 int orig_flag_pic
= flag_pic
;
3313 /* If we haven't initialized the special PIC symbols, do so now. */
3314 if (!pic_helper_symbol_name
[0])
3316 ASM_GENERATE_INTERNAL_LABEL (pic_helper_symbol_name
, "LADDPC", 0);
3317 pic_helper_symbol
= gen_rtx_SYMBOL_REF (Pmode
, pic_helper_symbol_name
);
3318 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3321 /* If we haven't emitted the special PIC helper function, do so now unless
3322 we are requested to delay it. */
3323 if (!delay_pic_helper
&& !pic_helper_emitted_p
)
3328 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx
, global_offset_table
,
3329 pic_helper_symbol
));
3331 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx
, global_offset_table
,
3332 pic_helper_symbol
));
3333 flag_pic
= orig_flag_pic
;
3335 /* Need to emit this whether or not we obey regdecls,
3336 since setjmp/longjmp can cause life info to screw up.
3337 ??? In the case where we don't obey regdecls, this is not sufficient
3338 since we may not fall out the bottom. */
3339 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3342 /* Return 1 if RTX is a MEM which is known to be aligned to at
3343 least a DESIRED byte boundary. */
3346 mem_min_alignment (rtx mem
, int desired
)
3348 rtx addr
, base
, offset
;
3350 /* If it's not a MEM we can't accept it. */
3351 if (GET_CODE (mem
) != MEM
)
3355 if (!TARGET_UNALIGNED_DOUBLES
3356 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3359 /* ??? The rest of the function predates MEM_ALIGN so
3360 there is probably a bit of redundancy. */
3361 addr
= XEXP (mem
, 0);
3362 base
= offset
= NULL_RTX
;
3363 if (GET_CODE (addr
) == PLUS
)
3365 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3367 base
= XEXP (addr
, 0);
3369 /* What we are saying here is that if the base
3370 REG is aligned properly, the compiler will make
3371 sure any REG based index upon it will be so
3373 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3374 offset
= XEXP (addr
, 1);
3376 offset
= const0_rtx
;
3379 else if (GET_CODE (addr
) == REG
)
3382 offset
= const0_rtx
;
3385 if (base
!= NULL_RTX
)
3387 int regno
= REGNO (base
);
3389 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3391 /* Check if the compiler has recorded some information
3392 about the alignment of the base REG. If reload has
3393 completed, we already matched with proper alignments.
3394 If not running global_alloc, reload might give us
3395 unaligned pointer to local stack though. */
3397 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3398 || (optimize
&& reload_completed
))
3399 && (INTVAL (offset
) & (desired
- 1)) == 0)
3404 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3408 else if (! TARGET_UNALIGNED_DOUBLES
3409 || CONSTANT_P (addr
)
3410 || GET_CODE (addr
) == LO_SUM
)
3412 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3413 is true, in which case we can only assume that an access is aligned if
3414 it is to a constant address, or the address involves a LO_SUM. */
3418 /* An obviously unaligned address. */
3423 /* Vectors to keep interesting information about registers where it can easily
3424 be got. We used to use the actual mode value as the bit number, but there
3425 are more than 32 modes now. Instead we use two tables: one indexed by
3426 hard register number, and one indexed by mode. */
3428 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3429 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3430 mapped into one sparc_mode_class mode. */
3432 enum sparc_mode_class
{
3433 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3434 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3438 /* Modes for single-word and smaller quantities. */
3439 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3441 /* Modes for double-word and smaller quantities. */
3442 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3444 /* Modes for quad-word and smaller quantities. */
3445 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3447 /* Modes for 8-word and smaller quantities. */
3448 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3450 /* Modes for single-float quantities. We must allow any single word or
3451 smaller quantity. This is because the fix/float conversion instructions
3452 take integer inputs/outputs from the float registers. */
3453 #define SF_MODES (S_MODES)
3455 /* Modes for double-float and smaller quantities. */
3456 #define DF_MODES (S_MODES | D_MODES)
3458 /* Modes for double-float only quantities. */
3459 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3461 /* Modes for quad-float only quantities. */
3462 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3464 /* Modes for quad-float and smaller quantities. */
3465 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3467 /* Modes for quad-float and double-float quantities. */
3468 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3470 /* Modes for quad-float pair only quantities. */
3471 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3473 /* Modes for quad-float pairs and smaller quantities. */
3474 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3476 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3478 /* Modes for condition codes. */
3479 #define CC_MODES (1 << (int) CC_MODE)
3480 #define CCFP_MODES (1 << (int) CCFP_MODE)
3482 /* Value is 1 if register/mode pair is acceptable on sparc.
3483 The funny mixture of D and T modes is because integer operations
3484 do not specially operate on tetra quantities, so non-quad-aligned
3485 registers can hold quadword quantities (except %o4 and %i4 because
3486 they cross fixed registers). */
3488 /* This points to either the 32 bit or the 64 bit version. */
3489 const int *hard_regno_mode_classes
;
3491 static const int hard_32bit_mode_classes
[] = {
3492 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3493 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3494 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3495 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3497 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3498 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3499 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3500 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3502 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3503 and none can hold SFmode/SImode values. */
3504 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3505 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3506 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3507 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3510 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3516 static const int hard_64bit_mode_classes
[] = {
3517 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3518 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3519 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3520 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3522 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3523 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3524 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3525 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3527 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3528 and none can hold SFmode/SImode values. */
3529 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3530 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3531 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3532 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3535 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3541 int sparc_mode_class
[NUM_MACHINE_MODES
];
3543 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3546 sparc_init_modes (void)
3550 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3552 switch (GET_MODE_CLASS (i
))
3555 case MODE_PARTIAL_INT
:
3556 case MODE_COMPLEX_INT
:
3557 if (GET_MODE_SIZE (i
) <= 4)
3558 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3559 else if (GET_MODE_SIZE (i
) == 8)
3560 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3561 else if (GET_MODE_SIZE (i
) == 16)
3562 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3563 else if (GET_MODE_SIZE (i
) == 32)
3564 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3566 sparc_mode_class
[i
] = 0;
3568 case MODE_VECTOR_INT
:
3569 if (GET_MODE_SIZE (i
) <= 4)
3570 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
3571 else if (GET_MODE_SIZE (i
) == 8)
3572 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
3575 case MODE_COMPLEX_FLOAT
:
3576 if (GET_MODE_SIZE (i
) <= 4)
3577 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3578 else if (GET_MODE_SIZE (i
) == 8)
3579 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3580 else if (GET_MODE_SIZE (i
) == 16)
3581 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3582 else if (GET_MODE_SIZE (i
) == 32)
3583 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3585 sparc_mode_class
[i
] = 0;
3588 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3589 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3591 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3594 sparc_mode_class
[i
] = 0;
3600 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3602 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3604 /* Initialize the array used by REGNO_REG_CLASS. */
3605 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3607 if (i
< 16 && TARGET_V8PLUS
)
3608 sparc_regno_reg_class
[i
] = I64_REGS
;
3609 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
3610 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3612 sparc_regno_reg_class
[i
] = FP_REGS
;
3614 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3616 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3618 sparc_regno_reg_class
[i
] = NO_REGS
;
3622 /* Compute the frame size required by the function. This function is called
3623 during the reload pass and also by sparc_expand_prologue. */
3626 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function_p
)
3628 int outgoing_args_size
= (current_function_outgoing_args_size
3629 + REG_PARM_STACK_SPACE (current_function_decl
));
3630 int n_regs
= 0; /* N_REGS is the number of 4-byte regs saved thus far. */
3635 for (i
= 0; i
< 8; i
++)
3636 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3641 for (i
= 0; i
< 8; i
+= 2)
3642 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3643 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3647 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3648 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3649 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3652 /* Set up values for use in prologue and epilogue. */
3653 num_gfregs
= n_regs
;
3658 && current_function_outgoing_args_size
== 0)
3659 actual_fsize
= apparent_fsize
= 0;
3662 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3663 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
3664 apparent_fsize
+= n_regs
* 4;
3665 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3668 /* Make sure nothing can clobber our register windows.
3669 If a SAVE must be done, or there is a stack-local variable,
3670 the register window area must be allocated. */
3671 if (! leaf_function_p
|| size
> 0)
3672 actual_fsize
+= FIRST_PARM_OFFSET (current_function_decl
);
3674 return SPARC_STACK_ALIGN (actual_fsize
);
3677 /* Output any necessary .register pseudo-ops. */
3680 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
3682 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3688 /* Check if %g[2367] were used without
3689 .register being printed for them already. */
3690 for (i
= 2; i
< 8; i
++)
3692 if (regs_ever_live
[i
]
3693 && ! sparc_hard_reg_printed
[i
])
3695 sparc_hard_reg_printed
[i
] = 1;
3696 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
3703 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
3704 as needed. LOW should be double-word aligned for 32-bit registers.
3705 Return the new OFFSET. */
3708 #define SORR_RESTORE 1
3711 save_or_restore_regs (int low
, int high
, rtx base
, int offset
, int action
)
3716 if (TARGET_ARCH64
&& high
<= 32)
3718 for (i
= low
; i
< high
; i
++)
3720 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3722 mem
= gen_rtx_MEM (DImode
, plus_constant (base
, offset
));
3723 set_mem_alias_set (mem
, sparc_sr_alias_set
);
3724 if (action
== SORR_SAVE
)
3726 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
3727 RTX_FRAME_RELATED_P (insn
) = 1;
3729 else /* action == SORR_RESTORE */
3730 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
3737 for (i
= low
; i
< high
; i
+= 2)
3739 bool reg0
= regs_ever_live
[i
] && ! call_used_regs
[i
];
3740 bool reg1
= regs_ever_live
[i
+1] && ! call_used_regs
[i
+1];
3741 enum machine_mode mode
;
3746 mode
= i
< 32 ? DImode
: DFmode
;
3751 mode
= i
< 32 ? SImode
: SFmode
;
3756 mode
= i
< 32 ? SImode
: SFmode
;
3763 mem
= gen_rtx_MEM (mode
, plus_constant (base
, offset
));
3764 set_mem_alias_set (mem
, sparc_sr_alias_set
);
3765 if (action
== SORR_SAVE
)
3767 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
3768 RTX_FRAME_RELATED_P (insn
) = 1;
3770 else /* action == SORR_RESTORE */
3771 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
3773 /* Always preserve double-word alignment. */
3774 offset
= (offset
+ 7) & -8;
3781 /* Emit code to save call-saved registers. */
3784 emit_save_or_restore_regs (int action
)
3786 HOST_WIDE_INT offset
;
3789 offset
= frame_base_offset
- apparent_fsize
;
3791 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4095)
3793 /* ??? This might be optimized a little as %g1 might already have a
3794 value close enough that a single add insn will do. */
3795 /* ??? Although, all of this is probably only a temporary fix
3796 because if %g1 can hold a function result, then
3797 sparc_expand_epilogue will lose (the result will be
3799 base
= gen_rtx_REG (Pmode
, 1);
3800 emit_move_insn (base
, GEN_INT (offset
));
3801 emit_insn (gen_rtx_SET (VOIDmode
,
3803 gen_rtx_PLUS (Pmode
, frame_base_reg
, base
)));
3807 base
= frame_base_reg
;
3809 offset
= save_or_restore_regs (0, 8, base
, offset
, action
);
3810 save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, action
);
3813 /* Generate a save_register_window insn. */
3816 gen_save_register_window (rtx increment
)
3819 return gen_save_register_windowdi (increment
);
3821 return gen_save_register_windowsi (increment
);
3824 /* Generate an increment for the stack pointer. */
3827 gen_stack_pointer_inc (rtx increment
)
3829 return gen_rtx_SET (VOIDmode
,
3831 gen_rtx_PLUS (Pmode
,
3836 /* Generate a decrement for the stack pointer. */
3839 gen_stack_pointer_dec (rtx decrement
)
3841 return gen_rtx_SET (VOIDmode
,
3843 gen_rtx_MINUS (Pmode
,
3848 /* Expand the function prologue. The prologue is responsible for reserving
3849 storage for the frame, saving the call-saved registers and loading the
3850 PIC register if needed. */
3853 sparc_expand_prologue (void)
3858 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
3859 on the final value of the flag means deferring the prologue/epilogue
3860 expansion until just before the second scheduling pass, which is too
3861 late to emit multiple epilogues or return insns.
3863 Of course we are making the assumption that the value of the flag
3864 will not change between now and its final value. Of the three parts
3865 of the formula, only the last one can reasonably vary. Let's take a
3866 closer look, after assuming that the first two ones are set to true
3867 (otherwise the last value is effectively silenced).
3869 If only_leaf_regs_used returns false, the global predicate will also
3870 be false so the actual frame size calculated below will be positive.
3871 As a consequence, the save_register_window insn will be emitted in
3872 the instruction stream; now this insn explicitly references %fp
3873 which is not a leaf register so only_leaf_regs_used will always
3874 return false subsequently.
3876 If only_leaf_regs_used returns true, we hope that the subsequent
3877 optimization passes won't cause non-leaf registers to pop up. For
3878 example, the regrename pass has special provisions to not rename to
3879 non-leaf registers in a leaf function. */
3880 sparc_leaf_function_p
3881 = optimize
> 0 && leaf_function_p () && only_leaf_regs_used ();
3883 /* Need to use actual_fsize, since we are also allocating
3884 space for our callee (and our own register save area). */
3886 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
3888 /* Advertise that the data calculated just above are now valid. */
3889 sparc_prologue_data_valid_p
= true;
3891 if (sparc_leaf_function_p
)
3893 frame_base_reg
= stack_pointer_rtx
;
3894 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3898 frame_base_reg
= hard_frame_pointer_rtx
;
3899 frame_base_offset
= SPARC_STACK_BIAS
;
3902 if (actual_fsize
== 0)
3904 else if (sparc_leaf_function_p
)
3906 if (actual_fsize
<= 4096)
3907 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize
)));
3908 else if (actual_fsize
<= 8192)
3910 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
3911 /* %sp is still the CFA register. */
3912 RTX_FRAME_RELATED_P (insn
) = 1;
3914 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
3918 rtx reg
= gen_rtx_REG (Pmode
, 1);
3919 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
3920 insn
= emit_insn (gen_stack_pointer_inc (reg
));
3922 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3923 gen_stack_pointer_inc (GEN_INT (-actual_fsize
)),
3927 RTX_FRAME_RELATED_P (insn
) = 1;
3931 if (actual_fsize
<= 4096)
3932 insn
= emit_insn (gen_save_register_window (GEN_INT (-actual_fsize
)));
3933 else if (actual_fsize
<= 8192)
3935 insn
= emit_insn (gen_save_register_window (GEN_INT (-4096)));
3936 /* %sp is not the CFA register anymore. */
3937 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
3941 rtx reg
= gen_rtx_REG (Pmode
, 1);
3942 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
3943 insn
= emit_insn (gen_save_register_window (reg
));
3946 RTX_FRAME_RELATED_P (insn
) = 1;
3947 for (i
=0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
3948 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, i
)) = 1;
3952 emit_save_or_restore_regs (SORR_SAVE
);
3954 /* Load the PIC register if needed. */
3955 if (flag_pic
&& current_function_uses_pic_offset_table
)
3956 load_pic_register (false);
3959 /* This function generates the assembly code for function entry, which boils
3960 down to emitting the necessary .register directives. */
3963 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3965 /* Check that the assumption we made in sparc_expand_prologue is valid. */
3966 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
3968 sparc_output_scratch_registers (file
);
3971 /* Expand the function epilogue, either normal or part of a sibcall.
3972 We emit all the instructions except the return or the call. */
3975 sparc_expand_epilogue (void)
3978 emit_save_or_restore_regs (SORR_RESTORE
);
3980 if (actual_fsize
== 0)
3982 else if (sparc_leaf_function_p
)
3984 if (actual_fsize
<= 4096)
3985 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize
)));
3986 else if (actual_fsize
<= 8192)
3988 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
3989 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize
)));
3993 rtx reg
= gen_rtx_REG (Pmode
, 1);
3994 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
3995 emit_insn (gen_stack_pointer_dec (reg
));
4000 /* Return true if it is appropriate to emit `return' instructions in the
4001 body of a function. */
4004 sparc_can_use_return_insn_p (void)
4006 return sparc_prologue_data_valid_p
4007 && (actual_fsize
== 0 || !sparc_leaf_function_p
);
4010 /* This function generates the assembly code for function exit. */
4013 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4015 /* If code does not drop into the epilogue, we have to still output
4016 a dummy nop for the sake of sane backtraces. Otherwise, if the
4017 last two instructions of a function were "call foo; dslot;" this
4018 can make the return PC of foo (i.e. address of call instruction
4019 plus 8) point to the first instruction in the next function. */
4021 rtx insn
, last_real_insn
;
4023 insn
= get_last_insn ();
4025 last_real_insn
= prev_real_insn (insn
);
4027 && GET_CODE (last_real_insn
) == INSN
4028 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
4029 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
4031 if (last_real_insn
&& GET_CODE (last_real_insn
) == CALL_INSN
)
4032 fputs("\tnop\n", file
);
4034 sparc_output_deferred_case_vectors ();
4037 /* Output a 'restore' instruction. */
4040 output_restore (rtx pat
)
4046 fputs ("\t restore\n", asm_out_file
);
4050 gcc_assert (GET_CODE (pat
) == SET
);
4052 operands
[0] = SET_DEST (pat
);
4053 pat
= SET_SRC (pat
);
4055 switch (GET_CODE (pat
))
4058 operands
[1] = XEXP (pat
, 0);
4059 operands
[2] = XEXP (pat
, 1);
4060 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4063 operands
[1] = XEXP (pat
, 0);
4064 operands
[2] = XEXP (pat
, 1);
4065 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4068 operands
[1] = XEXP (pat
, 0);
4069 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
4070 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4074 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4079 /* Output a return. */
4082 output_return (rtx insn
)
4084 if (sparc_leaf_function_p
)
4086 /* This is a leaf function so we don't have to bother restoring the
4087 register window, which frees us from dealing with the convoluted
4088 semantics of restore/return. We simply output the jump to the
4089 return address and the insn in the delay slot (if any). */
4091 gcc_assert (! current_function_calls_eh_return
);
4093 return "jmp\t%%o7+%)%#";
4097 /* This is a regular function so we have to restore the register window.
4098 We may have a pending insn for the delay slot, which will be either
4099 combined with the 'restore' instruction or put in the delay slot of
4100 the 'return' instruction. */
4102 if (current_function_calls_eh_return
)
4104 /* If the function uses __builtin_eh_return, the eh_return
4105 machinery occupies the delay slot. */
4106 gcc_assert (! final_sequence
);
4108 if (! flag_delayed_branch
)
4109 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file
);
4112 fputs ("\treturn\t%i7+8\n", asm_out_file
);
4114 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file
);
4116 if (flag_delayed_branch
)
4117 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
4119 fputs ("\t nop\n", asm_out_file
);
4121 else if (final_sequence
)
4125 delay
= NEXT_INSN (insn
);
4128 pat
= PATTERN (delay
);
4130 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
4132 epilogue_renumber (&pat
, 0);
4133 return "return\t%%i7+%)%#";
4137 output_asm_insn ("jmp\t%%i7+%)", NULL
);
4138 output_restore (pat
);
4139 PATTERN (delay
) = gen_blockage ();
4140 INSN_CODE (delay
) = -1;
4145 /* The delay slot is empty. */
4147 return "return\t%%i7+%)\n\t nop";
4148 else if (flag_delayed_branch
)
4149 return "jmp\t%%i7+%)\n\t restore";
4151 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4158 /* Output a sibling call. */
4161 output_sibcall (rtx insn
, rtx call_operand
)
4165 gcc_assert (flag_delayed_branch
);
4167 operands
[0] = call_operand
;
4169 if (sparc_leaf_function_p
)
4171 /* This is a leaf function so we don't have to bother restoring the
4172 register window. We simply output the jump to the function and
4173 the insn in the delay slot (if any). */
4175 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
4178 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4181 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4182 it into branch if possible. */
4183 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4188 /* This is a regular function so we have to restore the register window.
4189 We may have a pending insn for the delay slot, which will be combined
4190 with the 'restore' instruction. */
4192 output_asm_insn ("call\t%a0, 0", operands
);
4196 rtx delay
= NEXT_INSN (insn
);
4199 output_restore (PATTERN (delay
));
4201 PATTERN (delay
) = gen_blockage ();
4202 INSN_CODE (delay
) = -1;
4205 output_restore (NULL_RTX
);
4211 /* Functions for handling argument passing.
4213 For 32-bit, the first 6 args are normally in registers and the rest are
4214 pushed. Any arg that starts within the first 6 words is at least
4215 partially passed in a register unless its data type forbids.
4217 For 64-bit, the argument registers are laid out as an array of 16 elements
4218 and arguments are added sequentially. The first 6 int args and up to the
4219 first 16 fp args (depending on size) are passed in regs.
4221 Slot Stack Integral Float Float in structure Double Long Double
4222 ---- ----- -------- ----- ------------------ ------ -----------
4223 15 [SP+248] %f31 %f30,%f31 %d30
4224 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4225 13 [SP+232] %f27 %f26,%f27 %d26
4226 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4227 11 [SP+216] %f23 %f22,%f23 %d22
4228 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4229 9 [SP+200] %f19 %f18,%f19 %d18
4230 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4231 7 [SP+184] %f15 %f14,%f15 %d14
4232 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4233 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4234 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4235 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4236 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4237 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4238 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4240 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4242 Integral arguments are always passed as 64-bit quantities appropriately
4245 Passing of floating point values is handled as follows.
4246 If a prototype is in scope:
4247 If the value is in a named argument (i.e. not a stdarg function or a
4248 value not part of the `...') then the value is passed in the appropriate
4250 If the value is part of the `...' and is passed in one of the first 6
4251 slots then the value is passed in the appropriate int reg.
4252 If the value is part of the `...' and is not passed in one of the first 6
4253 slots then the value is passed in memory.
4254 If a prototype is not in scope:
4255 If the value is one of the first 6 arguments the value is passed in the
4256 appropriate integer reg and the appropriate fp reg.
4257 If the value is not one of the first 6 arguments the value is passed in
4258 the appropriate fp reg and in memory.
4261 Summary of the calling conventions implemented by GCC on SPARC:
4264 size argument return value
4266 small integer <4 int. reg. int. reg.
4267 word 4 int. reg. int. reg.
4268 double word 8 int. reg. int. reg.
4270 _Complex small integer <8 int. reg. int. reg.
4271 _Complex word 8 int. reg. int. reg.
4272 _Complex double word 16 memory int. reg.
4274 vector integer <=8 int. reg. FP reg.
4275 vector integer >8 memory memory
4277 float 4 int. reg. FP reg.
4278 double 8 int. reg. FP reg.
4279 long double 16 memory memory
4281 _Complex float 8 memory FP reg.
4282 _Complex double 16 memory FP reg.
4283 _Complex long double 32 memory FP reg.
4285 vector float any memory memory
4287 aggregate any memory memory
4292 size argument return value
4294 small integer <8 int. reg. int. reg.
4295 word 8 int. reg. int. reg.
4296 double word 16 int. reg. int. reg.
4298 _Complex small integer <16 int. reg. int. reg.
4299 _Complex word 16 int. reg. int. reg.
4300 _Complex double word 32 memory int. reg.
4302 vector integer <=16 FP reg. FP reg.
4303 vector integer 16<s<=32 memory FP reg.
4304 vector integer >32 memory memory
4306 float 4 FP reg. FP reg.
4307 double 8 FP reg. FP reg.
4308 long double 16 FP reg. FP reg.
4310 _Complex float 8 FP reg. FP reg.
4311 _Complex double 16 FP reg. FP reg.
4312 _Complex long double 32 memory FP reg.
4314 vector float <=16 FP reg. FP reg.
4315 vector float 16<s<=32 memory FP reg.
4316 vector float >32 memory memory
4318 aggregate <=16 reg. reg.
4319 aggregate 16<s<=32 memory reg.
4320 aggregate >32 memory memory
4324 Note #1: complex floating-point types follow the extended SPARC ABIs as
4325 implemented by the Sun compiler.
4327 Note #2: integral vector types follow the scalar floating-point types
4328 conventions to match what is implemented by the Sun VIS SDK.
4330 Note #3: floating-point vector types follow the aggregate types
4334 /* Maximum number of int regs for args. */
4335 #define SPARC_INT_ARG_MAX 6
4336 /* Maximum number of fp regs for args. */
4337 #define SPARC_FP_ARG_MAX 16
4339 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4341 /* Handle the INIT_CUMULATIVE_ARGS macro.
4342 Initialize a variable CUM of type CUMULATIVE_ARGS
4343 for a call to a function whose data type is FNTYPE.
4344 For a library call, FNTYPE is 0. */
4347 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
4348 rtx libname ATTRIBUTE_UNUSED
,
4349 tree fndecl ATTRIBUTE_UNUSED
)
4352 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4353 cum
->libcall_p
= fntype
== 0;
4356 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4357 When a prototype says `char' or `short', really pass an `int'. */
4360 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED
)
4362 return TARGET_ARCH32
? true : false;
4365 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4368 sparc_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4370 return TARGET_ARCH64
? true : false;
4373 /* Scan the record type TYPE and return the following predicates:
4374 - INTREGS_P: the record contains at least one field or sub-field
4375 that is eligible for promotion in integer registers.
4376 - FP_REGS_P: the record contains at least one field or sub-field
4377 that is eligible for promotion in floating-point registers.
4378 - PACKED_P: the record contains at least one field that is packed.
4380 Sub-fields are not taken into account for the PACKED_P predicate. */
4383 scan_record_type (tree type
, int *intregs_p
, int *fpregs_p
, int *packed_p
)
4387 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4389 if (TREE_CODE (field
) == FIELD_DECL
)
4391 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4392 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
4393 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4394 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4400 if (packed_p
&& DECL_PACKED (field
))
4406 /* Compute the slot number to pass an argument in.
4407 Return the slot number or -1 if passing on the stack.
4409 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4410 the preceding args and about the function being called.
4411 MODE is the argument's machine mode.
4412 TYPE is the data type of the argument (as a tree).
4413 This is null for libcalls where that information may
4415 NAMED is nonzero if this argument is a named parameter
4416 (otherwise it is an extra parameter matching an ellipsis).
4417 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4418 *PREGNO records the register number to use if scalar type.
4419 *PPADDING records the amount of padding needed in words. */
4422 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
4423 tree type
, int named
, int incoming_p
,
4424 int *pregno
, int *ppadding
)
4426 int regbase
= (incoming_p
4427 ? SPARC_INCOMING_INT_ARG_FIRST
4428 : SPARC_OUTGOING_INT_ARG_FIRST
);
4429 int slotno
= cum
->words
;
4430 enum mode_class mclass
;
4435 if (type
&& TREE_ADDRESSABLE (type
))
4441 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4444 /* For SPARC64, objects requiring 16-byte alignment get it. */
4446 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
4447 && (slotno
& 1) != 0)
4448 slotno
++, *ppadding
= 1;
4450 mclass
= GET_MODE_CLASS (mode
);
4451 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
4453 /* Vector types deserve special treatment because they are
4454 polymorphic wrt their mode, depending upon whether VIS
4455 instructions are enabled. */
4456 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
4458 /* The SPARC port defines no floating-point vector modes. */
4459 gcc_assert (mode
== BLKmode
);
4463 /* Integral vector types should either have a vector
4464 mode or an integral mode, because we are guaranteed
4465 by pass_by_reference that their size is not greater
4466 than 16 bytes and TImode is 16-byte wide. */
4467 gcc_assert (mode
!= BLKmode
);
4469 /* Vector integers are handled like floats according to
4471 mclass
= MODE_FLOAT
;
4478 case MODE_COMPLEX_FLOAT
:
4479 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
4481 if (slotno
>= SPARC_FP_ARG_MAX
)
4483 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
4484 /* Arguments filling only one single FP register are
4485 right-justified in the outer double FP register. */
4486 if (GET_MODE_SIZE (mode
) <= 4)
4493 case MODE_COMPLEX_INT
:
4494 if (slotno
>= SPARC_INT_ARG_MAX
)
4496 regno
= regbase
+ slotno
;
4500 if (mode
== VOIDmode
)
4501 /* MODE is VOIDmode when generating the actual call. */
4504 gcc_assert (mode
== BLKmode
);
4506 if (TARGET_ARCH32
|| !type
|| (TREE_CODE (type
) == UNION_TYPE
))
4508 if (slotno
>= SPARC_INT_ARG_MAX
)
4510 regno
= regbase
+ slotno
;
4512 else /* TARGET_ARCH64 && type */
4514 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
4516 /* First see what kinds of registers we would need. */
4517 if (TREE_CODE (type
) == VECTOR_TYPE
)
4520 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
4522 /* The ABI obviously doesn't specify how packed structures
4523 are passed. These are defined to be passed in int regs
4524 if possible, otherwise memory. */
4525 if (packed_p
|| !named
)
4526 fpregs_p
= 0, intregs_p
= 1;
4528 /* If all arg slots are filled, then must pass on stack. */
4529 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4532 /* If there are only int args and all int arg slots are filled,
4533 then must pass on stack. */
4534 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4537 /* Note that even if all int arg slots are filled, fp members may
4538 still be passed in regs if such regs are available.
4539 *PREGNO isn't set because there may be more than one, it's up
4540 to the caller to compute them. */
4553 /* Handle recursive register counting for structure field layout. */
4555 struct function_arg_record_value_parms
4557 rtx ret
; /* return expression being built. */
4558 int slotno
; /* slot number of the argument. */
4559 int named
; /* whether the argument is named. */
4560 int regbase
; /* regno of the base register. */
4561 int stack
; /* 1 if part of the argument is on the stack. */
4562 int intoffset
; /* offset of the first pending integer field. */
4563 unsigned int nregs
; /* number of words passed in registers. */
4566 static void function_arg_record_value_3
4567 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
4568 static void function_arg_record_value_2
4569 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
4570 static void function_arg_record_value_1
4571 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
4572 static rtx
function_arg_record_value (tree
, enum machine_mode
, int, int, int);
4573 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
4575 /* A subroutine of function_arg_record_value. Traverse the structure
4576 recursively and determine how many registers will be required. */
4579 function_arg_record_value_1 (tree type
, HOST_WIDE_INT startbitpos
,
4580 struct function_arg_record_value_parms
*parms
,
4585 /* We need to compute how many registers are needed so we can
4586 allocate the PARALLEL but before we can do that we need to know
4587 whether there are any packed fields. The ABI obviously doesn't
4588 specify how structures are passed in this case, so they are
4589 defined to be passed in int regs if possible, otherwise memory,
4590 regardless of whether there are fp values present. */
4593 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4595 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4602 /* Compute how many registers we need. */
4603 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4605 if (TREE_CODE (field
) == FIELD_DECL
)
4607 HOST_WIDE_INT bitpos
= startbitpos
;
4609 if (DECL_SIZE (field
) != 0)
4611 if (integer_zerop (DECL_SIZE (field
)))
4614 if (host_integerp (bit_position (field
), 1))
4615 bitpos
+= int_bit_position (field
);
4618 /* ??? FIXME: else assume zero offset. */
4620 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4621 function_arg_record_value_1 (TREE_TYPE (field
),
4625 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4626 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4631 if (parms
->intoffset
!= -1)
4633 unsigned int startbit
, endbit
;
4634 int intslots
, this_slotno
;
4636 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
4637 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4639 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4640 this_slotno
= parms
->slotno
+ parms
->intoffset
4643 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
4645 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
4646 /* We need to pass this field on the stack. */
4650 parms
->nregs
+= intslots
;
4651 parms
->intoffset
= -1;
4654 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4655 If it wasn't true we wouldn't be here. */
4656 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
4657 && DECL_MODE (field
) == BLKmode
)
4658 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
4659 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4666 if (parms
->intoffset
== -1)
4667 parms
->intoffset
= bitpos
;
4673 /* A subroutine of function_arg_record_value. Assign the bits of the
4674 structure between parms->intoffset and bitpos to integer registers. */
4677 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
4678 struct function_arg_record_value_parms
*parms
)
4680 enum machine_mode mode
;
4682 unsigned int startbit
, endbit
;
4683 int this_slotno
, intslots
, intoffset
;
4686 if (parms
->intoffset
== -1)
4689 intoffset
= parms
->intoffset
;
4690 parms
->intoffset
= -1;
4692 startbit
= intoffset
& -BITS_PER_WORD
;
4693 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4694 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4695 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4697 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4701 /* If this is the trailing part of a word, only load that much into
4702 the register. Otherwise load the whole register. Note that in
4703 the latter case we may pick up unwanted bits. It's not a problem
4704 at the moment but may wish to revisit. */
4706 if (intoffset
% BITS_PER_WORD
!= 0)
4707 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4712 intoffset
/= BITS_PER_UNIT
;
4715 regno
= parms
->regbase
+ this_slotno
;
4716 reg
= gen_rtx_REG (mode
, regno
);
4717 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4718 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4721 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4726 while (intslots
> 0);
4729 /* A subroutine of function_arg_record_value. Traverse the structure
4730 recursively and assign bits to floating point registers. Track which
4731 bits in between need integer registers; invoke function_arg_record_value_3
4732 to make that happen. */
4735 function_arg_record_value_2 (tree type
, HOST_WIDE_INT startbitpos
,
4736 struct function_arg_record_value_parms
*parms
,
4742 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4744 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4751 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4753 if (TREE_CODE (field
) == FIELD_DECL
)
4755 HOST_WIDE_INT bitpos
= startbitpos
;
4757 if (DECL_SIZE (field
) != 0)
4759 if (integer_zerop (DECL_SIZE (field
)))
4762 if (host_integerp (bit_position (field
), 1))
4763 bitpos
+= int_bit_position (field
);
4766 /* ??? FIXME: else assume zero offset. */
4768 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4769 function_arg_record_value_2 (TREE_TYPE (field
),
4773 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4774 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4779 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
4780 int regno
, nregs
, pos
;
4781 enum machine_mode mode
= DECL_MODE (field
);
4784 function_arg_record_value_3 (bitpos
, parms
);
4786 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
4789 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
4790 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
4792 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4794 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
4800 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
4801 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
4803 reg
= gen_rtx_REG (mode
, regno
);
4804 pos
= bitpos
/ BITS_PER_UNIT
;
4805 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4806 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
4810 regno
+= GET_MODE_SIZE (mode
) / 4;
4811 reg
= gen_rtx_REG (mode
, regno
);
4812 pos
+= GET_MODE_SIZE (mode
);
4813 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4814 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
4820 if (parms
->intoffset
== -1)
4821 parms
->intoffset
= bitpos
;
4827 /* Used by function_arg and function_value to implement the complex
4828 conventions of the 64-bit ABI for passing and returning structures.
4829 Return an expression valid as a return value for the two macros
4830 FUNCTION_ARG and FUNCTION_VALUE.
4832 TYPE is the data type of the argument (as a tree).
4833 This is null for libcalls where that information may
4835 MODE is the argument's machine mode.
4836 SLOTNO is the index number of the argument's slot in the parameter array.
4837 NAMED is nonzero if this argument is a named parameter
4838 (otherwise it is an extra parameter matching an ellipsis).
4839 REGBASE is the regno of the base register for the parameter array. */
4842 function_arg_record_value (tree type
, enum machine_mode mode
,
4843 int slotno
, int named
, int regbase
)
4845 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4846 struct function_arg_record_value_parms parms
;
4849 parms
.ret
= NULL_RTX
;
4850 parms
.slotno
= slotno
;
4851 parms
.named
= named
;
4852 parms
.regbase
= regbase
;
4855 /* Compute how many registers we need. */
4857 parms
.intoffset
= 0;
4858 function_arg_record_value_1 (type
, 0, &parms
, false);
4860 /* Take into account pending integer fields. */
4861 if (parms
.intoffset
!= -1)
4863 unsigned int startbit
, endbit
;
4864 int intslots
, this_slotno
;
4866 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
4867 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4868 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4869 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
4871 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
4873 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
4874 /* We need to pass this field on the stack. */
4878 parms
.nregs
+= intslots
;
4880 nregs
= parms
.nregs
;
4882 /* Allocate the vector and handle some annoying special cases. */
4885 /* ??? Empty structure has no value? Duh? */
4888 /* Though there's nothing really to store, return a word register
4889 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4890 leads to breakage due to the fact that there are zero bytes to
4892 return gen_rtx_REG (mode
, regbase
);
4896 /* ??? C++ has structures with no fields, and yet a size. Give up
4897 for now and pass everything back in integer registers. */
4898 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4900 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
4901 nregs
= SPARC_INT_ARG_MAX
- slotno
;
4903 gcc_assert (nregs
!= 0);
4905 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
4907 /* If at least one field must be passed on the stack, generate
4908 (parallel [(expr_list (nil) ...) ...]) so that all fields will
4909 also be passed on the stack. We can't do much better because the
4910 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
4911 of structures for which the fields passed exclusively in registers
4912 are not at the beginning of the structure. */
4914 XVECEXP (parms
.ret
, 0, 0)
4915 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4917 /* Fill in the entries. */
4919 parms
.intoffset
= 0;
4920 function_arg_record_value_2 (type
, 0, &parms
, false);
4921 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
4923 gcc_assert (parms
.nregs
== nregs
);
4928 /* Used by function_arg and function_value to implement the conventions
4929 of the 64-bit ABI for passing and returning unions.
4930 Return an expression valid as a return value for the two macros
4931 FUNCTION_ARG and FUNCTION_VALUE.
4933 SIZE is the size in bytes of the union.
4934 MODE is the argument's machine mode.
4935 REGNO is the hard register the union will be passed in. */
4938 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
4941 int nwords
= ROUND_ADVANCE (size
), i
;
4944 /* See comment in previous function for empty structures. */
4946 return gen_rtx_REG (mode
, regno
);
4948 if (slotno
== SPARC_INT_ARG_MAX
- 1)
4951 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
4953 for (i
= 0; i
< nwords
; i
++)
4955 /* Unions are passed left-justified. */
4956 XVECEXP (regs
, 0, i
)
4957 = gen_rtx_EXPR_LIST (VOIDmode
,
4958 gen_rtx_REG (word_mode
, regno
),
4959 GEN_INT (UNITS_PER_WORD
* i
));
4966 /* Used by function_arg and function_value to implement the conventions
4967 for passing and returning large (BLKmode) vectors.
4968 Return an expression valid as a return value for the two macros
4969 FUNCTION_ARG and FUNCTION_VALUE.
4971 SIZE is the size in bytes of the vector.
4972 BASE_MODE is the argument's base machine mode.
4973 REGNO is the FP hard register the vector will be passed in. */
4976 function_arg_vector_value (int size
, enum machine_mode base_mode
, int regno
)
4978 unsigned short base_mode_size
= GET_MODE_SIZE (base_mode
);
4979 int nregs
= size
/ base_mode_size
, i
;
4982 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
4984 for (i
= 0; i
< nregs
; i
++)
4986 XVECEXP (regs
, 0, i
)
4987 = gen_rtx_EXPR_LIST (VOIDmode
,
4988 gen_rtx_REG (base_mode
, regno
),
4989 GEN_INT (base_mode_size
* i
));
4990 regno
+= base_mode_size
/ 4;
4996 /* Handle the FUNCTION_ARG macro.
4997 Determine where to put an argument to a function.
4998 Value is zero to push the argument on the stack,
4999 or a hard register in which to store the argument.
5001 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5002 the preceding args and about the function being called.
5003 MODE is the argument's machine mode.
5004 TYPE is the data type of the argument (as a tree).
5005 This is null for libcalls where that information may
5007 NAMED is nonzero if this argument is a named parameter
5008 (otherwise it is an extra parameter matching an ellipsis).
5009 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5012 function_arg (const struct sparc_args
*cum
, enum machine_mode mode
,
5013 tree type
, int named
, int incoming_p
)
5015 int regbase
= (incoming_p
5016 ? SPARC_INCOMING_INT_ARG_FIRST
5017 : SPARC_OUTGOING_INT_ARG_FIRST
);
5018 int slotno
, regno
, padding
;
5019 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5022 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
5030 reg
= gen_rtx_REG (mode
, regno
);
5034 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
5036 /* Structures up to 16 bytes in size are passed in arg slots on the
5037 stack and are promoted to registers where possible. */
5039 gcc_assert (int_size_in_bytes (type
) <= 16);
5041 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
5043 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
5045 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5047 gcc_assert (size
<= 16);
5049 return function_arg_union_value (size
, mode
, slotno
, regno
);
5051 else if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5053 /* Vector types deserve special treatment because they are
5054 polymorphic wrt their mode, depending upon whether VIS
5055 instructions are enabled. */
5056 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5058 gcc_assert (size
<= 16);
5060 if (mode
== BLKmode
)
5061 return function_arg_vector_value (size
,
5062 TYPE_MODE (TREE_TYPE (type
)),
5063 SPARC_FP_ARG_FIRST
+ 2*slotno
);
5065 mclass
= MODE_FLOAT
;
5068 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5069 but also have the slot allocated for them.
5070 If no prototype is in scope fp values in register slots get passed
5071 in two places, either fp regs and int regs or fp regs and memory. */
5072 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5073 && SPARC_FP_REG_P (regno
))
5075 reg
= gen_rtx_REG (mode
, regno
);
5076 if (cum
->prototype_p
|| cum
->libcall_p
)
5078 /* "* 2" because fp reg numbers are recorded in 4 byte
5081 /* ??? This will cause the value to be passed in the fp reg and
5082 in the stack. When a prototype exists we want to pass the
5083 value in the reg but reserve space on the stack. That's an
5084 optimization, and is deferred [for a bit]. */
5085 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
5086 return gen_rtx_PARALLEL (mode
,
5088 gen_rtx_EXPR_LIST (VOIDmode
,
5089 NULL_RTX
, const0_rtx
),
5090 gen_rtx_EXPR_LIST (VOIDmode
,
5094 /* ??? It seems that passing back a register even when past
5095 the area declared by REG_PARM_STACK_SPACE will allocate
5096 space appropriately, and will not copy the data onto the
5097 stack, exactly as we desire.
5099 This is due to locate_and_pad_parm being called in
5100 expand_call whenever reg_parm_stack_space > 0, which
5101 while beneficial to our example here, would seem to be
5102 in error from what had been intended. Ho hum... -- r~ */
5110 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
5114 /* On incoming, we don't need to know that the value
5115 is passed in %f0 and %i0, and it confuses other parts
5116 causing needless spillage even on the simplest cases. */
5120 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
5121 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
5123 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5124 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
5126 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5130 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5131 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5132 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5138 /* Scalar or complex int. */
5139 reg
= gen_rtx_REG (mode
, regno
);
5145 /* For an arg passed partly in registers and partly in memory,
5146 this is the number of bytes of registers used.
5147 For args passed entirely in registers or entirely in memory, zero.
5149 Any arg that starts in the first 6 regs but won't entirely fit in them
5150 needs partial registers on v8. On v9, structures with integer
5151 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5152 values that begin in the last fp reg [where "last fp reg" varies with the
5153 mode] will be split between that reg and memory. */
5156 sparc_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5157 tree type
, bool named
)
5159 int slotno
, regno
, padding
;
5161 /* We pass 0 for incoming_p here, it doesn't matter. */
5162 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5169 if ((slotno
+ (mode
== BLKmode
5170 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5171 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5172 > SPARC_INT_ARG_MAX
)
5173 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
5177 /* We are guaranteed by pass_by_reference that the size of the
5178 argument is not greater than 16 bytes, so we only need to return
5179 one word if the argument is partially passed in registers. */
5181 if (type
&& AGGREGATE_TYPE_P (type
))
5183 int size
= int_size_in_bytes (type
);
5185 if (size
> UNITS_PER_WORD
5186 && slotno
== SPARC_INT_ARG_MAX
- 1)
5187 return UNITS_PER_WORD
;
5189 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5190 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5191 && ! (TARGET_FPU
&& named
)))
5193 /* The complex types are passed as packed types. */
5194 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
5195 && slotno
== SPARC_INT_ARG_MAX
- 1)
5196 return UNITS_PER_WORD
;
5198 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5200 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5202 return UNITS_PER_WORD
;
5209 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5210 Specify whether to pass the argument by reference. */
5213 sparc_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5214 enum machine_mode mode
, tree type
,
5215 bool named ATTRIBUTE_UNUSED
)
5219 /* Original SPARC 32-bit ABI says that structures and unions,
5220 and quad-precision floats are passed by reference. For Pascal,
5221 also pass arrays by reference. All other base types are passed
5224 Extended ABI (as implemented by the Sun compiler) says that all
5225 complex floats are passed by reference. Pass complex integers
5226 in registers up to 8 bytes. More generally, enforce the 2-word
5227 cap for passing arguments in registers.
5229 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5230 integers are passed like floats of the same size, that is in
5231 registers up to 8 bytes. Pass all vector floats by reference
5232 like structure and unions. */
5233 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
5235 /* Catch CDImode, TFmode, DCmode and TCmode. */
5236 || GET_MODE_SIZE (mode
) > 8
5238 && TREE_CODE (type
) == VECTOR_TYPE
5239 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
5243 /* Original SPARC 64-bit ABI says that structures and unions
5244 smaller than 16 bytes are passed in registers, as well as
5245 all other base types. For Pascal, pass arrays by reference.
5247 Extended ABI (as implemented by the Sun compiler) says that
5248 complex floats are passed in registers up to 16 bytes. Pass
5249 all complex integers in registers up to 16 bytes. More generally,
5250 enforce the 2-word cap for passing arguments in registers.
5252 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5253 integers are passed like floats of the same size, that is in
5254 registers (up to 16 bytes). Pass all vector floats like structure
5256 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5258 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
5259 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
5260 /* Catch CTImode and TCmode. */
5261 || GET_MODE_SIZE (mode
) > 16);
5265 /* Handle the FUNCTION_ARG_ADVANCE macro.
5266 Update the data in CUM to advance over an argument
5267 of mode MODE and data type TYPE.
5268 TYPE is null for libcalls where that information may not be available. */
5271 function_arg_advance (struct sparc_args
*cum
, enum machine_mode mode
,
5272 tree type
, int named
)
5274 int slotno
, regno
, padding
;
5276 /* We pass 0 for incoming_p here, it doesn't matter. */
5277 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5279 /* If register required leading padding, add it. */
5281 cum
->words
+= padding
;
5285 cum
->words
+= (mode
!= BLKmode
5286 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5287 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5291 if (type
&& AGGREGATE_TYPE_P (type
))
5293 int size
= int_size_in_bytes (type
);
5297 else if (size
<= 16)
5299 else /* passed by reference */
5304 cum
->words
+= (mode
!= BLKmode
5305 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5306 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5311 /* Handle the FUNCTION_ARG_PADDING macro.
5312 For the 64 bit ABI structs are always stored left shifted in their
5316 function_arg_padding (enum machine_mode mode
, tree type
)
5318 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5321 /* Fall back to the default. */
5322 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5325 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5326 Specify whether to return the return value in memory. */
5329 sparc_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
5332 /* Original SPARC 32-bit ABI says that structures and unions,
5333 and quad-precision floats are returned in memory. All other
5334 base types are returned in registers.
5336 Extended ABI (as implemented by the Sun compiler) says that
5337 all complex floats are returned in registers (8 FP registers
5338 at most for '_Complex long double'). Return all complex integers
5339 in registers (4 at most for '_Complex long long').
5341 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5342 integers are returned like floats of the same size, that is in
5343 registers up to 8 bytes and in memory otherwise. Return all
5344 vector floats in memory like structure and unions; note that
5345 they always have BLKmode like the latter. */
5346 return (TYPE_MODE (type
) == BLKmode
5347 || TYPE_MODE (type
) == TFmode
5348 || (TREE_CODE (type
) == VECTOR_TYPE
5349 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
5351 /* Original SPARC 64-bit ABI says that structures and unions
5352 smaller than 32 bytes are returned in registers, as well as
5353 all other base types.
5355 Extended ABI (as implemented by the Sun compiler) says that all
5356 complex floats are returned in registers (8 FP registers at most
5357 for '_Complex long double'). Return all complex integers in
5358 registers (4 at most for '_Complex TItype').
5360 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5361 integers are returned like floats of the same size, that is in
5362 registers. Return all vector floats like structure and unions;
5363 note that they always have BLKmode like the latter. */
5364 return ((TYPE_MODE (type
) == BLKmode
5365 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32));
5368 /* Handle the TARGET_STRUCT_VALUE target hook.
5369 Return where to find the structure return value address. */
5372 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
, int incoming
)
5381 mem
= gen_rtx_MEM (Pmode
, plus_constant (frame_pointer_rtx
,
5382 STRUCT_VALUE_OFFSET
));
5384 mem
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
,
5385 STRUCT_VALUE_OFFSET
));
5387 set_mem_alias_set (mem
, struct_value_alias_set
);
5392 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5393 For v9, function return values are subject to the same rules as arguments,
5394 except that up to 32 bytes may be returned in registers. */
5397 function_value (tree type
, enum machine_mode mode
, int incoming_p
)
5399 /* Beware that the two values are swapped here wrt function_arg. */
5400 int regbase
= (incoming_p
5401 ? SPARC_OUTGOING_INT_ARG_FIRST
5402 : SPARC_INCOMING_INT_ARG_FIRST
);
5403 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5406 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5408 /* Vector types deserve special treatment because they are
5409 polymorphic wrt their mode, depending upon whether VIS
5410 instructions are enabled. */
5411 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5413 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
5414 || (TARGET_ARCH64
&& size
<= 32));
5416 if (mode
== BLKmode
)
5417 return function_arg_vector_value (size
,
5418 TYPE_MODE (TREE_TYPE (type
)),
5419 SPARC_FP_ARG_FIRST
);
5421 mclass
= MODE_FLOAT
;
5423 else if (type
&& TARGET_ARCH64
)
5425 if (TREE_CODE (type
) == RECORD_TYPE
)
5427 /* Structures up to 32 bytes in size are passed in registers,
5428 promoted to fp registers where possible. */
5430 gcc_assert (int_size_in_bytes (type
) <= 32);
5432 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5434 else if (TREE_CODE (type
) == UNION_TYPE
)
5436 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5438 gcc_assert (size
<= 32);
5440 return function_arg_union_value (size
, mode
, 0, regbase
);
5442 else if (AGGREGATE_TYPE_P (type
))
5444 /* All other aggregate types are passed in an integer register
5445 in a mode corresponding to the size of the type. */
5446 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
5448 gcc_assert (bytes
<= 32);
5450 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5452 /* ??? We probably should have made the same ABI change in
5453 3.4.0 as the one we made for unions. The latter was
5454 required by the SCD though, while the former is not
5455 specified, so we favored compatibility and efficiency.
5457 Now we're stuck for aggregates larger than 16 bytes,
5458 because OImode vanished in the meantime. Let's not
5459 try to be unduly clever, and simply follow the ABI
5460 for unions in that case. */
5461 if (mode
== BLKmode
)
5462 return function_arg_union_value (bytes
, mode
, 0, regbase
);
5466 else if (mclass
== MODE_INT
5467 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5471 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5473 regno
= SPARC_FP_ARG_FIRST
;
5477 return gen_rtx_REG (mode
, regno
);
5480 /* Do what is necessary for `va_start'. We look at the current function
5481 to determine if stdarg or varargs is used and return the address of
5482 the first unnamed parameter. */
5485 sparc_builtin_saveregs (void)
5487 int first_reg
= current_function_args_info
.words
;
5491 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
5492 emit_move_insn (gen_rtx_MEM (word_mode
,
5493 gen_rtx_PLUS (Pmode
,
5495 GEN_INT (FIRST_PARM_OFFSET (0)
5498 gen_rtx_REG (word_mode
,
5499 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
5501 address
= gen_rtx_PLUS (Pmode
,
5503 GEN_INT (FIRST_PARM_OFFSET (0)
5504 + UNITS_PER_WORD
* first_reg
));
5509 /* Implement `va_start' for stdarg. */
5512 sparc_va_start (tree valist
, rtx nextarg
)
5514 nextarg
= expand_builtin_saveregs ();
5515 std_expand_builtin_va_start (valist
, nextarg
);
5518 /* Implement `va_arg' for stdarg. */
5521 sparc_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
5523 HOST_WIDE_INT size
, rsize
, align
;
5526 tree ptrtype
= build_pointer_type (type
);
5528 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5531 size
= rsize
= UNITS_PER_WORD
;
5537 size
= int_size_in_bytes (type
);
5538 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5543 /* For SPARC64, objects requiring 16-byte alignment get it. */
5544 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5545 align
= 2 * UNITS_PER_WORD
;
5547 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5548 are left-justified in their slots. */
5549 if (AGGREGATE_TYPE_P (type
))
5552 size
= rsize
= UNITS_PER_WORD
;
5562 incr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
,
5563 ssize_int (align
- 1)));
5564 incr
= fold (build2 (BIT_AND_EXPR
, ptr_type_node
, incr
,
5565 ssize_int (-align
)));
5568 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5571 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5572 addr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
,
5573 ssize_int (rsize
- size
)));
5577 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
5578 addr
= build_va_arg_indirect_ref (addr
);
5580 /* If the address isn't aligned properly for the type,
5581 we may need to copy to a temporary.
5582 FIXME: This is inefficient. Usually we can do this
5585 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
5587 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
5588 tree dest_addr
= build_fold_addr_expr (tmp
);
5590 tree copy
= build_function_call_expr
5591 (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
5592 tree_cons (NULL_TREE
, dest_addr
,
5593 tree_cons (NULL_TREE
, addr
,
5594 tree_cons (NULL_TREE
, size_int (rsize
),
5597 gimplify_and_add (copy
, pre_p
);
5601 addr
= fold_convert (ptrtype
, addr
);
5603 incr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
, ssize_int (rsize
)));
5604 incr
= build2 (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
5605 gimplify_and_add (incr
, post_p
);
5607 return build_va_arg_indirect_ref (addr
);
5610 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
5611 Specify whether the vector mode is supported by the hardware. */
5614 sparc_vector_mode_supported_p (enum machine_mode mode
)
5616 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
5619 /* Return the string to output an unconditional branch to LABEL, which is
5620 the operand number of the label.
5622 DEST is the destination insn (i.e. the label), INSN is the source. */
5625 output_ubranch (rtx dest
, int label
, rtx insn
)
5627 static char string
[64];
5628 bool v9_form
= false;
5631 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
5633 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5634 - INSN_ADDRESSES (INSN_UID (insn
)));
5635 /* Leave some instructions for "slop". */
5636 if (delta
>= -260000 && delta
< 260000)
5641 strcpy (string
, "ba%*,pt\t%%xcc, ");
5643 strcpy (string
, "b%*\t");
5645 p
= strchr (string
, '\0');
5656 /* Return the string to output a conditional branch to LABEL, which is
5657 the operand number of the label. OP is the conditional expression.
5658 XEXP (OP, 0) is assumed to be a condition code register (integer or
5659 floating point) and its mode specifies what kind of comparison we made.
5661 DEST is the destination insn (i.e. the label), INSN is the source.
5663 REVERSED is nonzero if we should reverse the sense of the comparison.
5665 ANNUL is nonzero if we should generate an annulling branch. */
5668 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
5671 static char string
[64];
5672 enum rtx_code code
= GET_CODE (op
);
5673 rtx cc_reg
= XEXP (op
, 0);
5674 enum machine_mode mode
= GET_MODE (cc_reg
);
5675 const char *labelno
, *branch
;
5676 int spaces
= 8, far
;
5679 /* v9 branches are limited to +-1MB. If it is too far away,
5692 fbne,a,pn %fcc2, .LC29
5700 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
5703 /* Reversal of FP compares takes care -- an ordered compare
5704 becomes an unordered compare and vice versa. */
5705 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5706 code
= reverse_condition_maybe_unordered (code
);
5708 code
= reverse_condition (code
);
5711 /* Start by writing the branch condition. */
5712 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5763 /* ??? !v9: FP branches cannot be preceded by another floating point
5764 insn. Because there is currently no concept of pre-delay slots,
5765 we can fix this only by always emitting a nop before a floating
5770 strcpy (string
, "nop\n\t");
5771 strcat (string
, branch
);
5784 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5796 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5817 strcpy (string
, branch
);
5819 spaces
-= strlen (branch
);
5820 p
= strchr (string
, '\0');
5822 /* Now add the annulling, the label, and a possible noop. */
5835 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
5837 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5838 - INSN_ADDRESSES (INSN_UID (insn
)));
5839 /* Leave some instructions for "slop". */
5840 if (delta
< -260000 || delta
>= 260000)
5844 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5846 static char v9_fcc_labelno
[] = "%%fccX, ";
5847 /* Set the char indicating the number of the fcc reg to use. */
5848 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
5849 labelno
= v9_fcc_labelno
;
5852 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
5856 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
5858 labelno
= "%%xcc, ";
5863 labelno
= "%%icc, ";
5868 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5871 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5884 strcpy (p
, labelno
);
5885 p
= strchr (p
, '\0');
5888 strcpy (p
, ".+12\n\t nop\n\tb\t");
5889 /* Skip the next insn if requested or
5890 if we know that it will be a nop. */
5891 if (annul
|| ! final_sequence
)
5905 /* Emit a library call comparison between floating point X and Y.
5906 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5907 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5908 values as arguments instead of the TFmode registers themselves,
5909 that's why we cannot call emit_float_lib_cmp. */
5911 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
5914 rtx slot0
, slot1
, result
, tem
, tem2
;
5915 enum machine_mode mode
;
5920 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
5924 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
5928 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
5932 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
5936 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
5940 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
5951 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
5960 if (GET_CODE (x
) != MEM
)
5962 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5963 emit_move_insn (slot0
, x
);
5968 if (GET_CODE (y
) != MEM
)
5970 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5971 emit_move_insn (slot1
, y
);
5976 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5978 XEXP (slot0
, 0), Pmode
,
5979 XEXP (slot1
, 0), Pmode
);
5985 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5987 x
, TFmode
, y
, TFmode
);
5993 /* Immediately move the result of the libcall into a pseudo
5994 register so reload doesn't clobber the value if it needs
5995 the return register for a spill reg. */
5996 result
= gen_reg_rtx (mode
);
5997 emit_move_insn (result
, hard_libcall_value (mode
));
6002 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6006 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
6011 emit_cmp_insn (result
, const1_rtx
,
6012 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
6015 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
6018 tem
= gen_reg_rtx (mode
);
6020 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
6022 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
6023 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6027 tem
= gen_reg_rtx (mode
);
6029 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
6031 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
6032 tem2
= gen_reg_rtx (mode
);
6034 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
6036 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
6037 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
6043 /* Generate an unsigned DImode to FP conversion. This is the same code
6044 optabs would emit if we didn't have TFmode patterns. */
6047 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
6049 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
6052 in
= force_reg (DImode
, operands
[1]);
6053 neglab
= gen_label_rtx ();
6054 donelab
= gen_label_rtx ();
6055 i0
= gen_reg_rtx (DImode
);
6056 i1
= gen_reg_rtx (DImode
);
6057 f0
= gen_reg_rtx (mode
);
6059 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
6061 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
6062 emit_jump_insn (gen_jump (donelab
));
6065 emit_label (neglab
);
6067 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
6068 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
6069 emit_insn (gen_iordi3 (i0
, i0
, i1
));
6070 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
6071 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
6073 emit_label (donelab
);
6076 /* Generate an FP to unsigned DImode conversion. This is the same code
6077 optabs would emit if we didn't have TFmode patterns. */
6080 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
6082 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
6085 in
= force_reg (mode
, operands
[1]);
6086 neglab
= gen_label_rtx ();
6087 donelab
= gen_label_rtx ();
6088 i0
= gen_reg_rtx (DImode
);
6089 i1
= gen_reg_rtx (DImode
);
6090 limit
= gen_reg_rtx (mode
);
6091 f0
= gen_reg_rtx (mode
);
6093 emit_move_insn (limit
,
6094 CONST_DOUBLE_FROM_REAL_VALUE (
6095 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
6096 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
6098 emit_insn (gen_rtx_SET (VOIDmode
,
6100 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
6101 emit_jump_insn (gen_jump (donelab
));
6104 emit_label (neglab
);
6106 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
6107 emit_insn (gen_rtx_SET (VOIDmode
,
6109 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
6110 emit_insn (gen_movdi (i1
, const1_rtx
));
6111 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
6112 emit_insn (gen_xordi3 (out
, i0
, i1
));
6114 emit_label (donelab
);
6117 /* Return the string to output a conditional branch to LABEL, testing
6118 register REG. LABEL is the operand number of the label; REG is the
6119 operand number of the reg. OP is the conditional expression. The mode
6120 of REG says what kind of comparison we made.
6122 DEST is the destination insn (i.e. the label), INSN is the source.
6124 REVERSED is nonzero if we should reverse the sense of the comparison.
6126 ANNUL is nonzero if we should generate an annulling branch. */
6129 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
6130 int annul
, rtx insn
)
6132 static char string
[64];
6133 enum rtx_code code
= GET_CODE (op
);
6134 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
6139 /* branch on register are limited to +-128KB. If it is too far away,
6152 brgez,a,pn %o1, .LC29
6158 ba,pt %xcc, .LC29 */
6160 far
= get_attr_length (insn
) >= 3;
6162 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6164 code
= reverse_condition (code
);
6166 /* Only 64 bit versions of these instructions exist. */
6167 gcc_assert (mode
== DImode
);
6169 /* Start by writing the branch condition. */
6174 strcpy (string
, "brnz");
6178 strcpy (string
, "brz");
6182 strcpy (string
, "brgez");
6186 strcpy (string
, "brlz");
6190 strcpy (string
, "brlez");
6194 strcpy (string
, "brgz");
6201 p
= strchr (string
, '\0');
6203 /* Now add the annulling, reg, label, and nop. */
6210 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6213 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6218 *p
= p
< string
+ 8 ? '\t' : ' ';
6226 int veryfar
= 1, delta
;
6228 if (INSN_ADDRESSES_SET_P ())
6230 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6231 - INSN_ADDRESSES (INSN_UID (insn
)));
6232 /* Leave some instructions for "slop". */
6233 if (delta
>= -260000 && delta
< 260000)
6237 strcpy (p
, ".+12\n\t nop\n\t");
6238 /* Skip the next insn if requested or
6239 if we know that it will be a nop. */
6240 if (annul
|| ! final_sequence
)
6250 strcpy (p
, "ba,pt\t%%xcc, ");
6264 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6265 Such instructions cannot be used in the delay slot of return insn on v9.
6266 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6270 epilogue_renumber (register rtx
*where
, int test
)
6272 register const char *fmt
;
6274 register enum rtx_code code
;
6279 code
= GET_CODE (*where
);
6284 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
6286 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
6287 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
6295 /* Do not replace the frame pointer with the stack pointer because
6296 it can cause the delayed instruction to load below the stack.
6297 This occurs when instructions like:
6299 (set (reg/i:SI 24 %i0)
6300 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6301 (const_int -20 [0xffffffec])) 0))
6303 are in the return delayed slot. */
6305 if (GET_CODE (XEXP (*where
, 0)) == REG
6306 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
6307 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
6308 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
6313 if (SPARC_STACK_BIAS
6314 && GET_CODE (XEXP (*where
, 0)) == REG
6315 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6323 fmt
= GET_RTX_FORMAT (code
);
6325 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6330 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6331 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6334 else if (fmt
[i
] == 'e'
6335 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6341 /* Leaf functions and non-leaf functions have different needs. */
6344 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6347 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6349 static const int *const reg_alloc_orders
[] = {
6350 reg_leaf_alloc_order
,
6351 reg_nonleaf_alloc_order
};
6354 order_regs_for_local_alloc (void)
6356 static int last_order_nonleaf
= 1;
6358 if (regs_ever_live
[15] != last_order_nonleaf
)
6360 last_order_nonleaf
= !last_order_nonleaf
;
6361 memcpy ((char *) reg_alloc_order
,
6362 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6363 FIRST_PSEUDO_REGISTER
* sizeof (int));
6367 /* Return 1 if REG and MEM are legitimate enough to allow the various
6368 mem<-->reg splits to be run. */
6371 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
6373 /* Punt if we are here by mistake. */
6374 gcc_assert (reload_completed
);
6376 /* We must have an offsettable memory reference. */
6377 if (! offsettable_memref_p (mem
))
6380 /* If we have legitimate args for ldd/std, we do not want
6381 the split to happen. */
6382 if ((REGNO (reg
) % 2) == 0
6383 && mem_min_alignment (mem
, 8))
6390 /* Return 1 if x and y are some kind of REG and they refer to
6391 different hard registers. This test is guaranteed to be
6392 run after reload. */
6395 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
6397 if (GET_CODE (x
) != REG
)
6399 if (GET_CODE (y
) != REG
)
6401 if (REGNO (x
) == REGNO (y
))
6406 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6407 This makes them candidates for using ldd and std insns.
6409 Note reg1 and reg2 *must* be hard registers. */
6412 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
6414 /* We might have been passed a SUBREG. */
6415 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6418 if (REGNO (reg1
) % 2 != 0)
6421 /* Integer ldd is deprecated in SPARC V9 */
6422 if (TARGET_V9
&& REGNO (reg1
) < 32)
6425 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6428 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6431 This can only happen when addr1 and addr2, the addresses in mem1
6432 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6433 addr1 must also be aligned on a 64-bit boundary.
6435 Also iff dependent_reg_rtx is not null it should not be used to
6436 compute the address for mem1, i.e. we cannot optimize a sequence
6448 But, note that the transformation from:
6453 is perfectly fine. Thus, the peephole2 patterns always pass us
6454 the destination register of the first load, never the second one.
6456 For stores we don't have a similar problem, so dependent_reg_rtx is
6460 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
6464 HOST_WIDE_INT offset1
;
6466 /* The mems cannot be volatile. */
6467 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6470 /* MEM1 should be aligned on a 64-bit boundary. */
6471 if (MEM_ALIGN (mem1
) < 64)
6474 addr1
= XEXP (mem1
, 0);
6475 addr2
= XEXP (mem2
, 0);
6477 /* Extract a register number and offset (if used) from the first addr. */
6478 if (GET_CODE (addr1
) == PLUS
)
6480 /* If not a REG, return zero. */
6481 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6485 reg1
= REGNO (XEXP (addr1
, 0));
6486 /* The offset must be constant! */
6487 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6489 offset1
= INTVAL (XEXP (addr1
, 1));
6492 else if (GET_CODE (addr1
) != REG
)
6496 reg1
= REGNO (addr1
);
6497 /* This was a simple (mem (reg)) expression. Offset is 0. */
6501 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6502 if (GET_CODE (addr2
) != PLUS
)
6505 if (GET_CODE (XEXP (addr2
, 0)) != REG
6506 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6509 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6512 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6515 /* The first offset must be evenly divisible by 8 to ensure the
6516 address is 64 bit aligned. */
6517 if (offset1
% 8 != 0)
6520 /* The offset for the second addr must be 4 more than the first addr. */
6521 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6524 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6529 /* Return 1 if reg is a pseudo, or is the first register in
6530 a hard register pair. This makes it a candidate for use in
6531 ldd and std insns. */
6534 register_ok_for_ldd (rtx reg
)
6536 /* We might have been passed a SUBREG. */
6537 if (GET_CODE (reg
) != REG
)
6540 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6541 return (REGNO (reg
) % 2 == 0);
6546 /* Print operand X (an rtx) in assembler syntax to file FILE.
6547 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6548 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6551 print_operand (FILE *file
, rtx x
, int code
)
6556 /* Output an insn in a delay slot. */
6558 sparc_indent_opcode
= 1;
6560 fputs ("\n\t nop", file
);
6563 /* Output an annul flag if there's nothing for the delay slot and we
6564 are optimizing. This is always used with '(' below.
6565 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6566 this is a dbx bug. So, we only do this when optimizing.
6567 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6568 Always emit a nop in case the next instruction is a branch. */
6569 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6573 /* Output a 'nop' if there's nothing for the delay slot and we are
6574 not optimizing. This is always used with '*' above. */
6575 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6576 fputs ("\n\t nop", file
);
6577 else if (final_sequence
)
6578 sparc_indent_opcode
= 1;
6581 /* Output the right displacement from the saved PC on function return.
6582 The caller may have placed an "unimp" insn immediately after the call
6583 so we have to account for it. This insn is used in the 32-bit ABI
6584 when calling a function that returns a non zero-sized structure. The
6585 64-bit ABI doesn't have it. Be careful to have this test be the same
6586 as that used on the call. */
6588 && current_function_returns_struct
6589 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
6591 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
6597 /* Output the Embedded Medium/Anywhere code model base register. */
6598 fputs (EMBMEDANY_BASE_REG
, file
);
6601 /* Print some local dynamic TLS name. */
6602 assemble_name (file
, get_some_local_dynamic_name ());
6606 /* Adjust the operand to take into account a RESTORE operation. */
6607 if (GET_CODE (x
) == CONST_INT
)
6609 else if (GET_CODE (x
) != REG
)
6610 output_operand_lossage ("invalid %%Y operand");
6611 else if (REGNO (x
) < 8)
6612 fputs (reg_names
[REGNO (x
)], file
);
6613 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6614 fputs (reg_names
[REGNO (x
)-16], file
);
6616 output_operand_lossage ("invalid %%Y operand");
6619 /* Print out the low order register name of a register pair. */
6620 if (WORDS_BIG_ENDIAN
)
6621 fputs (reg_names
[REGNO (x
)+1], file
);
6623 fputs (reg_names
[REGNO (x
)], file
);
6626 /* Print out the high order register name of a register pair. */
6627 if (WORDS_BIG_ENDIAN
)
6628 fputs (reg_names
[REGNO (x
)], file
);
6630 fputs (reg_names
[REGNO (x
)+1], file
);
6633 /* Print out the second register name of a register pair or quad.
6634 I.e., R (%o0) => %o1. */
6635 fputs (reg_names
[REGNO (x
)+1], file
);
6638 /* Print out the third register name of a register quad.
6639 I.e., S (%o0) => %o2. */
6640 fputs (reg_names
[REGNO (x
)+2], file
);
6643 /* Print out the fourth register name of a register quad.
6644 I.e., T (%o0) => %o3. */
6645 fputs (reg_names
[REGNO (x
)+3], file
);
6648 /* Print a condition code register. */
6649 if (REGNO (x
) == SPARC_ICC_REG
)
6651 /* We don't handle CC[X]_NOOVmode because they're not supposed
6653 if (GET_MODE (x
) == CCmode
)
6654 fputs ("%icc", file
);
6655 else if (GET_MODE (x
) == CCXmode
)
6656 fputs ("%xcc", file
);
6661 /* %fccN register */
6662 fputs (reg_names
[REGNO (x
)], file
);
6665 /* Print the operand's address only. */
6666 output_address (XEXP (x
, 0));
6669 /* In this case we need a register. Use %g0 if the
6670 operand is const0_rtx. */
6672 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
6674 fputs ("%g0", file
);
6681 switch (GET_CODE (x
))
6683 case IOR
: fputs ("or", file
); break;
6684 case AND
: fputs ("and", file
); break;
6685 case XOR
: fputs ("xor", file
); break;
6686 default: output_operand_lossage ("invalid %%A operand");
6691 switch (GET_CODE (x
))
6693 case IOR
: fputs ("orn", file
); break;
6694 case AND
: fputs ("andn", file
); break;
6695 case XOR
: fputs ("xnor", file
); break;
6696 default: output_operand_lossage ("invalid %%B operand");
6700 /* These are used by the conditional move instructions. */
6704 enum rtx_code rc
= GET_CODE (x
);
6708 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
6709 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6710 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
6712 rc
= reverse_condition (GET_CODE (x
));
6716 case NE
: fputs ("ne", file
); break;
6717 case EQ
: fputs ("e", file
); break;
6718 case GE
: fputs ("ge", file
); break;
6719 case GT
: fputs ("g", file
); break;
6720 case LE
: fputs ("le", file
); break;
6721 case LT
: fputs ("l", file
); break;
6722 case GEU
: fputs ("geu", file
); break;
6723 case GTU
: fputs ("gu", file
); break;
6724 case LEU
: fputs ("leu", file
); break;
6725 case LTU
: fputs ("lu", file
); break;
6726 case LTGT
: fputs ("lg", file
); break;
6727 case UNORDERED
: fputs ("u", file
); break;
6728 case ORDERED
: fputs ("o", file
); break;
6729 case UNLT
: fputs ("ul", file
); break;
6730 case UNLE
: fputs ("ule", file
); break;
6731 case UNGT
: fputs ("ug", file
); break;
6732 case UNGE
: fputs ("uge", file
); break;
6733 case UNEQ
: fputs ("ue", file
); break;
6734 default: output_operand_lossage (code
== 'c'
6735 ? "invalid %%c operand"
6736 : "invalid %%C operand");
6741 /* These are used by the movr instruction pattern. */
6745 enum rtx_code rc
= (code
== 'd'
6746 ? reverse_condition (GET_CODE (x
))
6750 case NE
: fputs ("ne", file
); break;
6751 case EQ
: fputs ("e", file
); break;
6752 case GE
: fputs ("gez", file
); break;
6753 case LT
: fputs ("lz", file
); break;
6754 case LE
: fputs ("lez", file
); break;
6755 case GT
: fputs ("gz", file
); break;
6756 default: output_operand_lossage (code
== 'd'
6757 ? "invalid %%d operand"
6758 : "invalid %%D operand");
6765 /* Print a sign-extended character. */
6766 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
6767 fprintf (file
, "%d", i
);
6772 /* Operand must be a MEM; write its address. */
6773 if (GET_CODE (x
) != MEM
)
6774 output_operand_lossage ("invalid %%f operand");
6775 output_address (XEXP (x
, 0));
6780 /* Print a sign-extended 32-bit value. */
6782 if (GET_CODE(x
) == CONST_INT
)
6784 else if (GET_CODE(x
) == CONST_DOUBLE
)
6785 i
= CONST_DOUBLE_LOW (x
);
6788 output_operand_lossage ("invalid %%s operand");
6791 i
= trunc_int_for_mode (i
, SImode
);
6792 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
6797 /* Do nothing special. */
6801 /* Undocumented flag. */
6802 output_operand_lossage ("invalid operand output code");
6805 if (GET_CODE (x
) == REG
)
6806 fputs (reg_names
[REGNO (x
)], file
);
6807 else if (GET_CODE (x
) == MEM
)
6810 /* Poor Sun assembler doesn't understand absolute addressing. */
6811 if (CONSTANT_P (XEXP (x
, 0)))
6812 fputs ("%g0+", file
);
6813 output_address (XEXP (x
, 0));
6816 else if (GET_CODE (x
) == HIGH
)
6818 fputs ("%hi(", file
);
6819 output_addr_const (file
, XEXP (x
, 0));
6822 else if (GET_CODE (x
) == LO_SUM
)
6824 print_operand (file
, XEXP (x
, 0), 0);
6825 if (TARGET_CM_MEDMID
)
6826 fputs ("+%l44(", file
);
6828 fputs ("+%lo(", file
);
6829 output_addr_const (file
, XEXP (x
, 1));
6832 else if (GET_CODE (x
) == CONST_DOUBLE
6833 && (GET_MODE (x
) == VOIDmode
6834 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
6836 if (CONST_DOUBLE_HIGH (x
) == 0)
6837 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
6838 else if (CONST_DOUBLE_HIGH (x
) == -1
6839 && CONST_DOUBLE_LOW (x
) < 0)
6840 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
6842 output_operand_lossage ("long long constant not a valid immediate operand");
6844 else if (GET_CODE (x
) == CONST_DOUBLE
)
6845 output_operand_lossage ("floating point constant not a valid immediate operand");
6846 else { output_addr_const (file
, x
); }
6849 /* Target hook for assembling integer objects. The sparc version has
6850 special handling for aligned DI-mode objects. */
6853 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
6855 /* ??? We only output .xword's for symbols and only then in environments
6856 where the assembler can handle them. */
6857 if (aligned_p
&& size
== 8
6858 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
6862 assemble_integer_with_op ("\t.xword\t", x
);
6867 assemble_aligned_integer (4, const0_rtx
);
6868 assemble_aligned_integer (4, x
);
6872 return default_assemble_integer (x
, size
, aligned_p
);
6875 /* Return the value of a code used in the .proc pseudo-op that says
6876 what kind of result this function returns. For non-C types, we pick
6877 the closest C type. */
6879 #ifndef SHORT_TYPE_SIZE
6880 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6883 #ifndef INT_TYPE_SIZE
6884 #define INT_TYPE_SIZE BITS_PER_WORD
6887 #ifndef LONG_TYPE_SIZE
6888 #define LONG_TYPE_SIZE BITS_PER_WORD
6891 #ifndef LONG_LONG_TYPE_SIZE
6892 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6895 #ifndef FLOAT_TYPE_SIZE
6896 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6899 #ifndef DOUBLE_TYPE_SIZE
6900 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6903 #ifndef LONG_DOUBLE_TYPE_SIZE
6904 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6908 sparc_type_code (register tree type
)
6910 register unsigned long qualifiers
= 0;
6911 register unsigned shift
;
6913 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6914 setting more, since some assemblers will give an error for this. Also,
6915 we must be careful to avoid shifts of 32 bits or more to avoid getting
6916 unpredictable results. */
6918 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
6920 switch (TREE_CODE (type
))
6926 qualifiers
|= (3 << shift
);
6931 qualifiers
|= (2 << shift
);
6935 case REFERENCE_TYPE
:
6937 qualifiers
|= (1 << shift
);
6941 return (qualifiers
| 8);
6944 case QUAL_UNION_TYPE
:
6945 return (qualifiers
| 9);
6948 return (qualifiers
| 10);
6951 return (qualifiers
| 16);
6954 /* If this is a range type, consider it to be the underlying
6956 if (TREE_TYPE (type
) != 0)
6959 /* Carefully distinguish all the standard types of C,
6960 without messing up if the language is not C. We do this by
6961 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
6962 look at both the names and the above fields, but that's redundant.
6963 Any type whose size is between two C types will be considered
6964 to be the wider of the two types. Also, we do not have a
6965 special code to use for "long long", so anything wider than
6966 long is treated the same. Note that we can't distinguish
6967 between "int" and "long" in this code if they are the same
6968 size, but that's fine, since neither can the assembler. */
6970 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
6971 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
6973 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
6974 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
6976 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
6977 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
6980 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
6983 /* If this is a range type, consider it to be the underlying
6985 if (TREE_TYPE (type
) != 0)
6988 /* Carefully distinguish all the standard types of C,
6989 without messing up if the language is not C. */
6991 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
6992 return (qualifiers
| 6);
6995 return (qualifiers
| 7);
6997 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
6998 /* ??? We need to distinguish between double and float complex types,
6999 but I don't know how yet because I can't reach this code from
7000 existing front-ends. */
7001 return (qualifiers
| 7); /* Who knows? */
7004 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
7005 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
7006 case LANG_TYPE
: /* ? */
7010 gcc_unreachable (); /* Not a type! */
7017 /* Nested function support. */
7019 /* Emit RTL insns to initialize the variable parts of a trampoline.
7020 FNADDR is an RTX for the address of the function's pure code.
7021 CXT is an RTX for the static chain value for the function.
7023 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7024 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7025 (to store insns). This is a bit excessive. Perhaps a different
7026 mechanism would be better here.
7028 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7031 sparc_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7033 /* SPARC 32-bit trampoline:
7036 sethi %hi(static), %g2
7038 or %g2, %lo(static), %g2
7040 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7041 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7045 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
7046 expand_binop (SImode
, ior_optab
,
7047 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
7048 size_int (10), 0, 1),
7049 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
7050 NULL_RTX
, 1, OPTAB_DIRECT
));
7053 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7054 expand_binop (SImode
, ior_optab
,
7055 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
7056 size_int (10), 0, 1),
7057 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
7058 NULL_RTX
, 1, OPTAB_DIRECT
));
7061 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7062 expand_binop (SImode
, ior_optab
,
7063 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
7064 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
7065 NULL_RTX
, 1, OPTAB_DIRECT
));
7068 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7069 expand_binop (SImode
, ior_optab
,
7070 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
7071 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
7072 NULL_RTX
, 1, OPTAB_DIRECT
));
7074 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7075 aligned on a 16 byte boundary so one flush clears it all. */
7076 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
7077 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7078 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7079 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
7080 plus_constant (tramp
, 8)))));
7082 /* Call __enable_execute_stack after writing onto the stack to make sure
7083 the stack address is accessible. */
7084 #ifdef ENABLE_EXECUTE_STACK
7085 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7086 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7091 /* The 64-bit version is simpler because it makes more sense to load the
7092 values as "immediate" data out of the trampoline. It's also easier since
7093 we can read the PC without clobbering a register. */
7096 sparc64_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7098 /* SPARC 64-bit trampoline:
7107 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
7108 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
7109 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7110 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
7111 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7112 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
7113 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7114 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
7115 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
7116 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
7117 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
7119 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7120 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7121 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
7123 /* Call __enable_execute_stack after writing onto the stack to make sure
7124 the stack address is accessible. */
7125 #ifdef ENABLE_EXECUTE_STACK
7126 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7127 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7131 /* Adjust the cost of a scheduling dependency. Return the new cost of
7132 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7135 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7137 enum attr_type insn_type
;
7139 if (! recog_memoized (insn
))
7142 insn_type
= get_attr_type (insn
);
7144 if (REG_NOTE_KIND (link
) == 0)
7146 /* Data dependency; DEP_INSN writes a register that INSN reads some
7149 /* if a load, then the dependence must be on the memory address;
7150 add an extra "cycle". Note that the cost could be two cycles
7151 if the reg was written late in an instruction group; we ca not tell
7153 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7156 /* Get the delay only if the address of the store is the dependence. */
7157 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7159 rtx pat
= PATTERN(insn
);
7160 rtx dep_pat
= PATTERN (dep_insn
);
7162 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7163 return cost
; /* This should not happen! */
7165 /* The dependency between the two instructions was on the data that
7166 is being stored. Assume that this implies that the address of the
7167 store is not dependent. */
7168 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7171 return cost
+ 3; /* An approximation. */
7174 /* A shift instruction cannot receive its data from an instruction
7175 in the same cycle; add a one cycle penalty. */
7176 if (insn_type
== TYPE_SHIFT
)
7177 return cost
+ 3; /* Split before cascade into shift. */
7181 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7182 INSN writes some cycles later. */
7184 /* These are only significant for the fpu unit; writing a fp reg before
7185 the fpu has finished with it stalls the processor. */
7187 /* Reusing an integer register causes no problems. */
7188 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7196 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7198 enum attr_type insn_type
, dep_type
;
7199 rtx pat
= PATTERN(insn
);
7200 rtx dep_pat
= PATTERN (dep_insn
);
7202 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7205 insn_type
= get_attr_type (insn
);
7206 dep_type
= get_attr_type (dep_insn
);
7208 switch (REG_NOTE_KIND (link
))
7211 /* Data dependency; DEP_INSN writes a register that INSN reads some
7218 /* Get the delay iff the address of the store is the dependence. */
7219 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7222 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7229 /* If a load, then the dependence must be on the memory address. If
7230 the addresses aren't equal, then it might be a false dependency */
7231 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7233 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7234 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7235 || GET_CODE (SET_SRC (pat
)) != MEM
7236 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7237 XEXP (SET_SRC (pat
), 0)))
7245 /* Compare to branch latency is 0. There is no benefit from
7246 separating compare and branch. */
7247 if (dep_type
== TYPE_COMPARE
)
7249 /* Floating point compare to branch latency is less than
7250 compare to conditional move. */
7251 if (dep_type
== TYPE_FPCMP
)
7260 /* Anti-dependencies only penalize the fpu unit. */
7261 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7273 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
7277 case PROCESSOR_SUPERSPARC
:
7278 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7280 case PROCESSOR_HYPERSPARC
:
7281 case PROCESSOR_SPARCLITE86X
:
7282 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7291 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
7292 int sched_verbose ATTRIBUTE_UNUSED
,
7293 int max_ready ATTRIBUTE_UNUSED
)
7298 sparc_use_sched_lookahead (void)
7300 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7301 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7303 if ((1 << sparc_cpu
) &
7304 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7305 (1 << PROCESSOR_SPARCLITE86X
)))
7311 sparc_issue_rate (void)
7318 /* Assume V9 processors are capable of at least dual-issue. */
7320 case PROCESSOR_SUPERSPARC
:
7322 case PROCESSOR_HYPERSPARC
:
7323 case PROCESSOR_SPARCLITE86X
:
7325 case PROCESSOR_ULTRASPARC
:
7326 case PROCESSOR_ULTRASPARC3
:
7332 set_extends (rtx insn
)
7334 register rtx pat
= PATTERN (insn
);
7336 switch (GET_CODE (SET_SRC (pat
)))
7338 /* Load and some shift instructions zero extend. */
7341 /* sethi clears the high bits */
7343 /* LO_SUM is used with sethi. sethi cleared the high
7344 bits and the values used with lo_sum are positive */
7346 /* Store flag stores 0 or 1 */
7356 rtx op0
= XEXP (SET_SRC (pat
), 0);
7357 rtx op1
= XEXP (SET_SRC (pat
), 1);
7358 if (GET_CODE (op1
) == CONST_INT
)
7359 return INTVAL (op1
) >= 0;
7360 if (GET_CODE (op0
) != REG
)
7362 if (sparc_check_64 (op0
, insn
) == 1)
7364 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7369 rtx op0
= XEXP (SET_SRC (pat
), 0);
7370 rtx op1
= XEXP (SET_SRC (pat
), 1);
7371 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7373 if (GET_CODE (op1
) == CONST_INT
)
7374 return INTVAL (op1
) >= 0;
7375 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7378 return GET_MODE (SET_SRC (pat
)) == SImode
;
7379 /* Positive integers leave the high bits zero. */
7381 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7383 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7386 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7388 return sparc_check_64 (SET_SRC (pat
), insn
);
7394 /* We _ought_ to have only one kind per function, but... */
7395 static GTY(()) rtx sparc_addr_diff_list
;
7396 static GTY(()) rtx sparc_addr_list
;
7399 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
7401 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7403 sparc_addr_diff_list
7404 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7406 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7410 sparc_output_addr_vec (rtx vec
)
7412 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7413 int idx
, vlen
= XVECLEN (body
, 0);
7415 #ifdef ASM_OUTPUT_ADDR_VEC_START
7416 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7419 #ifdef ASM_OUTPUT_CASE_LABEL
7420 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7423 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7426 for (idx
= 0; idx
< vlen
; idx
++)
7428 ASM_OUTPUT_ADDR_VEC_ELT
7429 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7432 #ifdef ASM_OUTPUT_ADDR_VEC_END
7433 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7438 sparc_output_addr_diff_vec (rtx vec
)
7440 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7441 rtx base
= XEXP (XEXP (body
, 0), 0);
7442 int idx
, vlen
= XVECLEN (body
, 1);
7444 #ifdef ASM_OUTPUT_ADDR_VEC_START
7445 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7448 #ifdef ASM_OUTPUT_CASE_LABEL
7449 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7452 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7455 for (idx
= 0; idx
< vlen
; idx
++)
7457 ASM_OUTPUT_ADDR_DIFF_ELT
7460 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7461 CODE_LABEL_NUMBER (base
));
7464 #ifdef ASM_OUTPUT_ADDR_VEC_END
7465 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7470 sparc_output_deferred_case_vectors (void)
7475 if (sparc_addr_list
== NULL_RTX
7476 && sparc_addr_diff_list
== NULL_RTX
)
7479 /* Align to cache line in the function's code section. */
7480 current_function_section (current_function_decl
);
7482 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7484 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7486 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7487 sparc_output_addr_vec (XEXP (t
, 0));
7488 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7489 sparc_output_addr_diff_vec (XEXP (t
, 0));
7491 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7494 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7495 unknown. Return 1 if the high bits are zero, -1 if the register is
7498 sparc_check_64 (rtx x
, rtx insn
)
7500 /* If a register is set only once it is safe to ignore insns this
7501 code does not know how to handle. The loop will either recognize
7502 the single set and return the correct value or fail to recognize
7507 gcc_assert (GET_CODE (x
) == REG
);
7509 if (GET_MODE (x
) == DImode
)
7510 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7512 if (flag_expensive_optimizations
7513 && REG_N_SETS (REGNO (y
)) == 1)
7519 insn
= get_last_insn_anywhere ();
7524 while ((insn
= PREV_INSN (insn
)))
7526 switch (GET_CODE (insn
))
7539 rtx pat
= PATTERN (insn
);
7540 if (GET_CODE (pat
) != SET
)
7542 if (rtx_equal_p (x
, SET_DEST (pat
)))
7543 return set_extends (insn
);
7544 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7545 return set_extends (insn
);
7546 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
7554 /* Returns assembly code to perform a DImode shift using
7555 a 64-bit global or out register on SPARC-V8+. */
7557 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
7559 static char asm_code
[60];
7561 /* The scratch register is only required when the destination
7562 register is not a 64-bit global or out register. */
7563 if (which_alternative
!= 2)
7564 operands
[3] = operands
[0];
7566 /* We can only shift by constants <= 63. */
7567 if (GET_CODE (operands
[2]) == CONST_INT
)
7568 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
7570 if (GET_CODE (operands
[1]) == CONST_INT
)
7572 output_asm_insn ("mov\t%1, %3", operands
);
7576 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
7577 if (sparc_check_64 (operands
[1], insn
) <= 0)
7578 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
7579 output_asm_insn ("or\t%L1, %3, %3", operands
);
7582 strcpy(asm_code
, opcode
);
7584 if (which_alternative
!= 2)
7585 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7587 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7590 /* Output rtl to increment the profiler label LABELNO
7591 for profiling a function entry. */
7594 sparc_profile_hook (int labelno
)
7599 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
7600 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
7601 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
7603 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
7606 #ifdef OBJECT_FORMAT_ELF
7608 sparc_elf_asm_named_section (const char *name
, unsigned int flags
,
7611 if (flags
& SECTION_MERGE
)
7613 /* entsize cannot be expressed in this section attributes
7615 default_elf_asm_named_section (name
, flags
, decl
);
7619 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
7621 if (!(flags
& SECTION_DEBUG
))
7622 fputs (",#alloc", asm_out_file
);
7623 if (flags
& SECTION_WRITE
)
7624 fputs (",#write", asm_out_file
);
7625 if (flags
& SECTION_TLS
)
7626 fputs (",#tls", asm_out_file
);
7627 if (flags
& SECTION_CODE
)
7628 fputs (",#execinstr", asm_out_file
);
7630 /* ??? Handle SECTION_BSS. */
7632 fputc ('\n', asm_out_file
);
7634 #endif /* OBJECT_FORMAT_ELF */
7636 /* We do not allow indirect calls to be optimized into sibling calls.
7638 We cannot use sibling calls when delayed branches are disabled
7639 because they will likely require the call delay slot to be filled.
7641 Also, on SPARC 32-bit we cannot emit a sibling call when the
7642 current function returns a structure. This is because the "unimp
7643 after call" convention would cause the callee to return to the
7644 wrong place. The generic code already disallows cases where the
7645 function being called returns a structure.
7647 It may seem strange how this last case could occur. Usually there
7648 is code after the call which jumps to epilogue code which dumps the
7649 return value into the struct return area. That ought to invalidate
7650 the sibling call right? Well, in the C++ case we can end up passing
7651 the pointer to the struct return area to a constructor (which returns
7652 void) and then nothing else happens. Such a sibling call would look
7653 valid without the added check here. */
7655 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7658 && flag_delayed_branch
7659 && (TARGET_ARCH64
|| ! current_function_returns_struct
));
7662 /* libfunc renaming. */
7663 #include "config/gofast.h"
7666 sparc_init_libfuncs (void)
7670 /* Use the subroutines that Sun's library provides for integer
7671 multiply and divide. The `*' prevents an underscore from
7672 being prepended by the compiler. .umul is a little faster
7674 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
7675 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
7676 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
7677 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
7678 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
7680 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
7681 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
7682 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
7683 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
7684 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
7685 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
7687 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
7688 is because with soft-float, the SFmode and DFmode sqrt
7689 instructions will be absent, and the compiler will notice and
7690 try to use the TFmode sqrt instruction for calls to the
7691 builtin function sqrt, but this fails. */
7693 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
7695 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
7696 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
7697 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
7698 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
7699 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
7700 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
7702 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
7703 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
7704 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
7705 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
7707 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
7708 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
7709 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
7710 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
7712 if (DITF_CONVERSION_LIBFUNCS
)
7714 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
7715 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
7716 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
7717 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
7720 if (SUN_CONVERSION_LIBFUNCS
)
7722 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
7723 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
7724 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
7725 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
7730 /* In the SPARC 64bit ABI, SImode multiply and divide functions
7731 do not exist in the library. Make sure the compiler does not
7732 emit calls to them by accident. (It should always use the
7733 hardware instructions.) */
7734 set_optab_libfunc (smul_optab
, SImode
, 0);
7735 set_optab_libfunc (sdiv_optab
, SImode
, 0);
7736 set_optab_libfunc (udiv_optab
, SImode
, 0);
7737 set_optab_libfunc (smod_optab
, SImode
, 0);
7738 set_optab_libfunc (umod_optab
, SImode
, 0);
7740 if (SUN_INTEGER_MULTIPLY_64
)
7742 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
7743 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
7744 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
7745 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
7746 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
7749 if (SUN_CONVERSION_LIBFUNCS
)
7751 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
7752 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
7753 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
7754 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
7758 gofast_maybe_init_libfuncs ();
7761 #define def_builtin(NAME, CODE, TYPE) \
7762 lang_hooks.builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
7765 /* Implement the TARGET_INIT_BUILTINS target hook.
7766 Create builtin functions for special SPARC instructions. */
7769 sparc_init_builtins (void)
7772 sparc_vis_init_builtins ();
7775 /* Create builtin functions for VIS 1.0 instructions. */
7778 sparc_vis_init_builtins (void)
7780 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
7781 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
7782 tree v4hi
= build_vector_type (intHI_type_node
, 4);
7783 tree v2hi
= build_vector_type (intHI_type_node
, 2);
7784 tree v2si
= build_vector_type (intSI_type_node
, 2);
7786 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
7787 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
7788 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
7789 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
7790 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
7791 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
7792 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
7793 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
7794 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
7795 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
7796 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
7797 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
7798 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
7800 intDI_type_node
, 0);
7801 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
7803 intDI_type_node
, 0);
7804 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
7806 intSI_type_node
, 0);
7807 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
7809 intDI_type_node
, 0);
7811 /* Packing and expanding vectors. */
7812 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
, v4qi_ftype_v4hi
);
7813 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
7814 v8qi_ftype_v2si_v8qi
);
7815 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
7817 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
, v4hi_ftype_v4qi
);
7818 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
7819 v8qi_ftype_v4qi_v4qi
);
7821 /* Multiplications. */
7822 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
7823 v4hi_ftype_v4qi_v4hi
);
7824 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
7825 v4hi_ftype_v4qi_v2hi
);
7826 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
7827 v4hi_ftype_v4qi_v2hi
);
7828 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
7829 v4hi_ftype_v8qi_v4hi
);
7830 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
7831 v4hi_ftype_v8qi_v4hi
);
7832 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
7833 v2si_ftype_v4qi_v2hi
);
7834 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
7835 v2si_ftype_v4qi_v2hi
);
7837 /* Data aligning. */
7838 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
7839 v4hi_ftype_v4hi_v4hi
);
7840 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
7841 v8qi_ftype_v8qi_v8qi
);
7842 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
7843 v2si_ftype_v2si_v2si
);
7844 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
7847 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
7850 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
7853 /* Pixel distance. */
7854 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
7855 di_ftype_v8qi_v8qi_di
);
7858 /* Handle TARGET_EXPAND_BUILTIN target hook.
7859 Expand builtin functions for sparc intrinsics. */
7862 sparc_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
7863 enum machine_mode tmode
, int ignore ATTRIBUTE_UNUSED
)
7866 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7867 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
7869 enum machine_mode mode
[4];
7872 mode
[arg_count
] = tmode
;
7875 || GET_MODE (target
) != tmode
7876 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7877 op
[arg_count
] = gen_reg_rtx (tmode
);
7879 op
[arg_count
] = target
;
7881 for (arglist
= TREE_OPERAND (exp
, 1); arglist
;
7882 arglist
= TREE_CHAIN (arglist
))
7884 tree arg
= TREE_VALUE (arglist
);
7887 mode
[arg_count
] = insn_data
[icode
].operand
[arg_count
].mode
;
7888 op
[arg_count
] = expand_expr (arg
, NULL_RTX
, VOIDmode
, 0);
7890 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
7892 op
[arg_count
] = copy_to_mode_reg (mode
[arg_count
], op
[arg_count
]);
7898 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
7901 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
7904 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
7919 sparc_vis_mul8x16 (int e8
, int e16
)
7921 return (e8
* e16
+ 128) / 256;
7924 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
7925 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
7926 constants. A tree list with the results of the multiplications is returned,
7927 and each element in the list is of INNER_TYPE. */
7930 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
7932 tree n_elts
= NULL_TREE
;
7937 case CODE_FOR_fmul8x16_vis
:
7938 for (; elts0
&& elts1
;
7939 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
7942 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
7943 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
7944 n_elts
= tree_cons (NULL_TREE
,
7945 build_int_cst (inner_type
, val
),
7950 case CODE_FOR_fmul8x16au_vis
:
7951 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
7953 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
7956 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
7958 n_elts
= tree_cons (NULL_TREE
,
7959 build_int_cst (inner_type
, val
),
7964 case CODE_FOR_fmul8x16al_vis
:
7965 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
7967 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
7970 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
7972 n_elts
= tree_cons (NULL_TREE
,
7973 build_int_cst (inner_type
, val
),
7982 return nreverse (n_elts
);
7985 /* Handle TARGET_FOLD_BUILTIN target hook.
7986 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
7987 result of the function call is ignored. NULL_TREE is returned if the
7988 function could not be folded. */
7991 sparc_fold_builtin (tree fndecl
, tree arglist
, bool ignore
)
7993 tree arg0
, arg1
, arg2
;
7994 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
7997 if (ignore
&& DECL_FUNCTION_CODE (fndecl
) != CODE_FOR_alignaddrsi_vis
7998 && DECL_FUNCTION_CODE (fndecl
) != CODE_FOR_alignaddrdi_vis
)
7999 return build_int_cst (rtype
, 0);
8001 switch (DECL_FUNCTION_CODE (fndecl
))
8003 case CODE_FOR_fexpand_vis
:
8004 arg0
= TREE_VALUE (arglist
);
8007 if (TREE_CODE (arg0
) == VECTOR_CST
)
8009 tree inner_type
= TREE_TYPE (rtype
);
8010 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
8011 tree n_elts
= NULL_TREE
;
8013 for (; elts
; elts
= TREE_CHAIN (elts
))
8015 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
8016 n_elts
= tree_cons (NULL_TREE
,
8017 build_int_cst (inner_type
, val
),
8020 return build_vector (rtype
, nreverse (n_elts
));
8024 case CODE_FOR_fmul8x16_vis
:
8025 case CODE_FOR_fmul8x16au_vis
:
8026 case CODE_FOR_fmul8x16al_vis
:
8027 arg0
= TREE_VALUE (arglist
);
8028 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8032 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
8034 tree inner_type
= TREE_TYPE (rtype
);
8035 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8036 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8037 tree n_elts
= sparc_handle_vis_mul8x16 (DECL_FUNCTION_CODE (fndecl
),
8038 inner_type
, elts0
, elts1
);
8040 return build_vector (rtype
, n_elts
);
8044 case CODE_FOR_fpmerge_vis
:
8045 arg0
= TREE_VALUE (arglist
);
8046 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8050 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
8052 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8053 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8054 tree n_elts
= NULL_TREE
;
8056 for (; elts0
&& elts1
;
8057 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
8059 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
8060 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
8063 return build_vector (rtype
, nreverse (n_elts
));
8067 case CODE_FOR_pdist_vis
:
8068 arg0
= TREE_VALUE (arglist
);
8069 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8070 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8075 if (TREE_CODE (arg0
) == VECTOR_CST
8076 && TREE_CODE (arg1
) == VECTOR_CST
8077 && TREE_CODE (arg2
) == INTEGER_CST
)
8080 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
8081 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
8082 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8083 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8085 for (; elts0
&& elts1
;
8086 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
8088 unsigned HOST_WIDE_INT
8089 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
8090 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
8091 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
8092 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
8094 unsigned HOST_WIDE_INT l
;
8097 overflow
|= neg_double (low1
, high1
, &l
, &h
);
8098 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
8100 overflow
|= neg_double (l
, h
, &l
, &h
);
8102 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
8105 gcc_assert (overflow
== 0);
8107 return build_int_cst_wide (rtype
, low
, high
);
8117 sparc_extra_constraint_check (rtx op
, int c
, int strict
)
8122 && (c
== 'T' || c
== 'U'))
8128 return fp_sethi_p (op
);
8131 return fp_mov_p (op
);
8134 return fp_high_losum_p (op
);
8138 || (GET_CODE (op
) == REG
8139 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8140 || reg_renumber
[REGNO (op
)] >= 0)))
8141 return register_ok_for_ldd (op
);
8150 return const_zero_operand (op
, GET_MODE (op
));
8156 /* Our memory extra constraints have to emulate the
8157 behavior of 'm' and 'o' in order for reload to work
8159 if (GET_CODE (op
) == MEM
)
8162 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8164 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8169 reload_ok_mem
= (reload_in_progress
8170 && GET_CODE (op
) == REG
8171 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8172 && reg_renumber
[REGNO (op
)] < 0);
8175 return reload_ok_mem
;
8178 /* ??? This duplicates information provided to the compiler by the
8179 ??? scheduler description. Some day, teach genautomata to output
8180 ??? the latencies and then CSE will just use that. */
8183 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
8185 enum machine_mode mode
= GET_MODE (x
);
8186 bool float_mode_p
= FLOAT_MODE_P (mode
);
8191 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8209 if (GET_MODE (x
) == VOIDmode
8210 && ((CONST_DOUBLE_HIGH (x
) == 0
8211 && CONST_DOUBLE_LOW (x
) < 0x1000)
8212 || (CONST_DOUBLE_HIGH (x
) == -1
8213 && CONST_DOUBLE_LOW (x
) < 0
8214 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
8221 /* If outer-code was a sign or zero extension, a cost
8222 of COSTS_N_INSNS (1) was already added in. This is
8223 why we are subtracting it back out. */
8224 if (outer_code
== ZERO_EXTEND
)
8226 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
8228 else if (outer_code
== SIGN_EXTEND
)
8230 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
8232 else if (float_mode_p
)
8234 *total
= sparc_costs
->float_load
;
8238 *total
= sparc_costs
->int_load
;
8246 *total
= sparc_costs
->float_plusminus
;
8248 *total
= COSTS_N_INSNS (1);
8253 *total
= sparc_costs
->float_mul
;
8254 else if (! TARGET_HARD_MUL
)
8255 *total
= COSTS_N_INSNS (25);
8261 if (sparc_costs
->int_mul_bit_factor
)
8265 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8267 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
8268 for (nbits
= 0; value
!= 0; value
&= value
- 1)
8271 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
8272 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
8274 rtx x1
= XEXP (x
, 1);
8275 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
8276 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
8278 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
8280 for (; value2
!= 0; value2
&= value2
- 1)
8288 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
8289 bit_cost
= COSTS_N_INSNS (bit_cost
);
8293 *total
= sparc_costs
->int_mulX
+ bit_cost
;
8295 *total
= sparc_costs
->int_mul
+ bit_cost
;
8302 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
8312 *total
= sparc_costs
->float_div_df
;
8314 *total
= sparc_costs
->float_div_sf
;
8319 *total
= sparc_costs
->int_divX
;
8321 *total
= sparc_costs
->int_div
;
8328 *total
= COSTS_N_INSNS (1);
8335 case UNSIGNED_FLOAT
:
8339 case FLOAT_TRUNCATE
:
8340 *total
= sparc_costs
->float_move
;
8345 *total
= sparc_costs
->float_sqrt_df
;
8347 *total
= sparc_costs
->float_sqrt_sf
;
8352 *total
= sparc_costs
->float_cmp
;
8354 *total
= COSTS_N_INSNS (1);
8359 *total
= sparc_costs
->float_cmove
;
8361 *total
= sparc_costs
->int_cmove
;
8365 /* Handle the NAND vector patterns. */
8366 if (sparc_vector_mode_supported_p (GET_MODE (x
))
8367 && GET_CODE (XEXP (x
, 0)) == NOT
8368 && GET_CODE (XEXP (x
, 1)) == NOT
)
8370 *total
= COSTS_N_INSNS (1);
8381 /* Emit the sequence of insns SEQ while preserving the registers. */
8384 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
8386 /* STACK_BOUNDARY guarantees that this is a 2-word slot. */
8387 rtx slot
= gen_rtx_MEM (word_mode
,
8388 plus_constant (stack_pointer_rtx
, SPARC_STACK_BIAS
));
8390 emit_insn (gen_stack_pointer_dec (GEN_INT (STACK_BOUNDARY
/BITS_PER_UNIT
)));
8391 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
8393 emit_insn (gen_rtx_SET (VOIDmode
,
8394 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
8398 emit_insn (gen_rtx_SET (VOIDmode
,
8400 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
8401 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
8402 emit_insn (gen_stack_pointer_inc (GEN_INT (STACK_BOUNDARY
/BITS_PER_UNIT
)));
8405 /* Output the assembler code for a thunk function. THUNK_DECL is the
8406 declaration for the thunk function itself, FUNCTION is the decl for
8407 the target function. DELTA is an immediate constant offset to be
8408 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8409 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
8412 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8413 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8416 rtx
this, insn
, funexp
;
8417 unsigned int int_arg_first
;
8419 reload_completed
= 1;
8420 epilogue_completed
= 1;
8422 reset_block_changes ();
8424 emit_note (NOTE_INSN_PROLOGUE_END
);
8426 if (flag_delayed_branch
)
8428 /* We will emit a regular sibcall below, so we need to instruct
8429 output_sibcall that we are in a leaf function. */
8430 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
8432 /* This will cause final.c to invoke leaf_renumber_regs so we
8433 must behave as if we were in a not-yet-leafified function. */
8434 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
8438 /* We will emit the sibcall manually below, so we will need to
8439 manually spill non-leaf registers. */
8440 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
8442 /* We really are in a leaf function. */
8443 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
8446 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8447 returns a structure, the structure return pointer is there instead. */
8448 if (TARGET_ARCH64
&& aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8449 this = gen_rtx_REG (Pmode
, int_arg_first
+ 1);
8451 this = gen_rtx_REG (Pmode
, int_arg_first
);
8453 /* Add DELTA. When possible use a plain add, otherwise load it into
8454 a register first. */
8457 rtx delta_rtx
= GEN_INT (delta
);
8459 if (! SPARC_SIMM13_P (delta
))
8461 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8462 emit_move_insn (scratch
, delta_rtx
);
8463 delta_rtx
= scratch
;
8466 /* THIS += DELTA. */
8467 emit_insn (gen_add2_insn (this, delta_rtx
));
8470 /* Add the word at address (*THIS + VCALL_OFFSET). */
8473 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8474 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8476 gcc_assert (vcall_offset
< 0);
8478 /* SCRATCH = *THIS. */
8479 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this));
8481 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8482 may not have any available scratch register at this point. */
8483 if (SPARC_SIMM13_P (vcall_offset
))
8485 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8486 else if (! fixed_regs
[5]
8487 /* The below sequence is made up of at least 2 insns,
8488 while the default method may need only one. */
8489 && vcall_offset
< -8192)
8491 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
8492 emit_move_insn (scratch2
, vcall_offset_rtx
);
8493 vcall_offset_rtx
= scratch2
;
8497 rtx increment
= GEN_INT (-4096);
8499 /* VCALL_OFFSET is a negative number whose typical range can be
8500 estimated as -32768..0 in 32-bit mode. In almost all cases
8501 it is therefore cheaper to emit multiple add insns than
8502 spilling and loading the constant into a register (at least
8504 while (! SPARC_SIMM13_P (vcall_offset
))
8506 emit_insn (gen_add2_insn (scratch
, increment
));
8507 vcall_offset
+= 4096;
8509 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
8512 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
8513 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
8514 gen_rtx_PLUS (Pmode
,
8516 vcall_offset_rtx
)));
8518 /* THIS += *(*THIS + VCALL_OFFSET). */
8519 emit_insn (gen_add2_insn (this, scratch
));
8522 /* Generate a tail call to the target function. */
8523 if (! TREE_USED (function
))
8525 assemble_external (function
);
8526 TREE_USED (function
) = 1;
8528 funexp
= XEXP (DECL_RTL (function
), 0);
8530 if (flag_delayed_branch
)
8532 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8533 insn
= emit_call_insn (gen_sibcall (funexp
));
8534 SIBLING_CALL_P (insn
) = 1;
8538 /* The hoops we have to jump through in order to generate a sibcall
8539 without using delay slots... */
8540 rtx spill_reg
, spill_reg2
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
8544 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
8545 spill_reg2
= gen_rtx_REG (word_mode
, PIC_OFFSET_TABLE_REGNUM
);
8547 /* Delay emitting the PIC helper function because it needs to
8548 change the section and we are emitting assembly code. */
8549 load_pic_register (true); /* clobbers %o7 */
8550 scratch
= legitimize_pic_address (funexp
, Pmode
, scratch
);
8553 emit_and_preserve (seq
, spill_reg
, spill_reg2
);
8555 else if (TARGET_ARCH32
)
8557 emit_insn (gen_rtx_SET (VOIDmode
,
8559 gen_rtx_HIGH (SImode
, funexp
)));
8560 emit_insn (gen_rtx_SET (VOIDmode
,
8562 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
8564 else /* TARGET_ARCH64 */
8566 switch (sparc_cmodel
)
8570 /* The destination can serve as a temporary. */
8571 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
8576 /* The destination cannot serve as a temporary. */
8577 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
8579 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
8582 emit_and_preserve (seq
, spill_reg
, 0);
8590 emit_jump_insn (gen_indirect_jump (scratch
));
8595 /* Run just enough of rest_of_compilation to get the insns emitted.
8596 There's not really enough bulk here to make other passes such as
8597 instruction scheduling worth while. Note that use_thunk calls
8598 assemble_start_function and assemble_end_function. */
8599 insn
= get_insns ();
8600 insn_locators_initialize ();
8601 shorten_branches (insn
);
8602 final_start_function (insn
, file
, 1);
8603 final (insn
, file
, 1);
8604 final_end_function ();
8606 reload_completed
= 0;
8607 epilogue_completed
= 0;
8611 /* Return true if sparc_output_mi_thunk would be able to output the
8612 assembler code for the thunk function specified by the arguments
8613 it is passed, and false otherwise. */
8615 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED
,
8616 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
8617 HOST_WIDE_INT vcall_offset
,
8618 tree function ATTRIBUTE_UNUSED
)
8620 /* Bound the loop used in the default method above. */
8621 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
8624 /* How to allocate a 'struct machine_function'. */
8626 static struct machine_function
*
8627 sparc_init_machine_status (void)
8629 return ggc_alloc_cleared (sizeof (struct machine_function
));
8632 /* Locate some local-dynamic symbol still in use by this function
8633 so that we can print its name in local-dynamic base patterns. */
8636 get_some_local_dynamic_name (void)
8640 if (cfun
->machine
->some_ld_name
)
8641 return cfun
->machine
->some_ld_name
;
8643 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8645 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
8646 return cfun
->machine
->some_ld_name
;
8652 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
8657 && GET_CODE (x
) == SYMBOL_REF
8658 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
8660 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
8667 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8668 This is called from dwarf2out.c to emit call frame instructions
8669 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8671 sparc_dwarf_handle_frame_unspec (const char *label
,
8672 rtx pattern ATTRIBUTE_UNUSED
,
8673 int index ATTRIBUTE_UNUSED
)
8675 gcc_assert (index
== UNSPECV_SAVEW
);
8676 dwarf2out_window_save (label
);
8679 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8680 We need to emit DTP-relative relocations. */
8683 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8688 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
8691 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
8696 output_addr_const (file
, x
);
8700 /* Do whatever processing is required at the end of a file. */
8703 sparc_file_end (void)
8705 /* If we haven't emitted the special PIC helper function, do so now. */
8706 if (pic_helper_symbol_name
[0] && !pic_helper_emitted_p
)
8709 if (NEED_INDICATE_EXEC_STACK
)
8710 file_end_indicate_exec_stack ();
8713 #include "gt-sparc.h"