1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs
= {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs
= {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs
= {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs
= {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs
= {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs
= {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs
= {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs
= {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs
= {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
278 const struct processor_costs
*sparc_costs
= &cypress_costs
;
280 #ifdef HAVE_AS_RELAX_OPTION
281 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
282 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
283 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
284 somebody does not branch between the sethi and jmp. */
285 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
287 #define LEAF_SIBCALL_SLOT_RESERVED_P \
288 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
291 /* Vector to say how input registers are mapped to output registers.
292 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
293 eliminate it. You must use -fomit-frame-pointer to get that. */
294 char leaf_reg_remap
[] =
295 { 0, 1, 2, 3, 4, 5, 6, 7,
296 -1, -1, -1, -1, -1, -1, 14, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 8, 9, 10, 11, 12, 13, -1, 15,
300 32, 33, 34, 35, 36, 37, 38, 39,
301 40, 41, 42, 43, 44, 45, 46, 47,
302 48, 49, 50, 51, 52, 53, 54, 55,
303 56, 57, 58, 59, 60, 61, 62, 63,
304 64, 65, 66, 67, 68, 69, 70, 71,
305 72, 73, 74, 75, 76, 77, 78, 79,
306 80, 81, 82, 83, 84, 85, 86, 87,
307 88, 89, 90, 91, 92, 93, 94, 95,
308 96, 97, 98, 99, 100};
310 /* Vector, indexed by hard register number, which contains 1
311 for a register that is allowable in a candidate for leaf
312 function treatment. */
313 char sparc_leaf_regs
[] =
314 { 1, 1, 1, 1, 1, 1, 1, 1,
315 0, 0, 0, 0, 0, 0, 1, 0,
316 0, 0, 0, 0, 0, 0, 0, 0,
317 1, 1, 1, 1, 1, 1, 0, 1,
318 1, 1, 1, 1, 1, 1, 1, 1,
319 1, 1, 1, 1, 1, 1, 1, 1,
320 1, 1, 1, 1, 1, 1, 1, 1,
321 1, 1, 1, 1, 1, 1, 1, 1,
322 1, 1, 1, 1, 1, 1, 1, 1,
323 1, 1, 1, 1, 1, 1, 1, 1,
324 1, 1, 1, 1, 1, 1, 1, 1,
325 1, 1, 1, 1, 1, 1, 1, 1,
328 struct GTY(()) machine_function
330 /* Size of the frame of the function. */
331 HOST_WIDE_INT frame_size
;
333 /* Size of the frame of the function minus the register window save area
334 and the outgoing argument area. */
335 HOST_WIDE_INT apparent_frame_size
;
337 /* Register we pretend the frame pointer is allocated to. Normally, this
338 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
339 record "offset" separately as it may be too big for (reg + disp). */
341 HOST_WIDE_INT frame_base_offset
;
343 /* Some local-dynamic TLS symbol name. */
344 const char *some_ld_name
;
346 /* Number of global or FP registers to be saved (as 4-byte quantities). */
347 int n_global_fp_regs
;
349 /* True if the current function is leaf and uses only leaf regs,
350 so that the SPARC leaf function optimization can be applied.
351 Private version of current_function_uses_only_leaf_regs, see
352 sparc_expand_prologue for the rationale. */
355 /* True if the prologue saves local or in registers. */
356 bool save_local_in_regs_p
;
358 /* True if the data calculated by sparc_expand_prologue are valid. */
359 bool prologue_data_valid_p
;
362 #define sparc_frame_size cfun->machine->frame_size
363 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
364 #define sparc_frame_base_reg cfun->machine->frame_base_reg
365 #define sparc_frame_base_offset cfun->machine->frame_base_offset
366 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
367 #define sparc_leaf_function_p cfun->machine->leaf_function_p
368 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
369 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
371 /* 1 if the next opcode is to be specially indented. */
372 int sparc_indent_opcode
= 0;
374 static void sparc_option_override (void);
375 static void sparc_init_modes (void);
376 static void scan_record_type (const_tree
, int *, int *, int *);
377 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
378 const_tree
, bool, bool, int *, int *);
380 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
381 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
383 static void sparc_emit_set_const32 (rtx
, rtx
);
384 static void sparc_emit_set_const64 (rtx
, rtx
);
385 static void sparc_output_addr_vec (rtx
);
386 static void sparc_output_addr_diff_vec (rtx
);
387 static void sparc_output_deferred_case_vectors (void);
388 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
389 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
390 static rtx
sparc_builtin_saveregs (void);
391 static int epilogue_renumber (rtx
*, int);
392 static bool sparc_assemble_integer (rtx
, unsigned int, int);
393 static int set_extends (rtx
);
394 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
395 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
396 #ifdef TARGET_SOLARIS
397 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
398 tree
) ATTRIBUTE_UNUSED
;
400 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
401 static int sparc_issue_rate (void);
402 static void sparc_sched_init (FILE *, int, int);
403 static int sparc_use_sched_lookahead (void);
405 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
406 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
407 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
408 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
409 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
411 static bool sparc_function_ok_for_sibcall (tree
, tree
);
412 static void sparc_init_libfuncs (void);
413 static void sparc_init_builtins (void);
414 static void sparc_vis_init_builtins (void);
415 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
416 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
417 static int sparc_vis_mul8x16 (int, int);
418 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
419 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
420 HOST_WIDE_INT
, tree
);
421 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
422 HOST_WIDE_INT
, const_tree
);
423 static struct machine_function
* sparc_init_machine_status (void);
424 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
425 static rtx
sparc_tls_get_addr (void);
426 static rtx
sparc_tls_got (void);
427 static const char *get_some_local_dynamic_name (void);
428 static int get_some_local_dynamic_name_1 (rtx
*, void *);
429 static int sparc_register_move_cost (enum machine_mode
,
430 reg_class_t
, reg_class_t
);
431 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
432 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
433 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
434 static bool sparc_function_value_regno_p (const unsigned int);
435 static rtx
sparc_struct_value_rtx (tree
, int);
436 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
437 int *, const_tree
, int);
438 static bool sparc_return_in_memory (const_tree
, const_tree
);
439 static bool sparc_strict_argument_naming (cumulative_args_t
);
440 static void sparc_va_start (tree
, rtx
);
441 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
442 static bool sparc_vector_mode_supported_p (enum machine_mode
);
443 static bool sparc_tls_referenced_p (rtx
);
444 static rtx
sparc_legitimize_tls_address (rtx
);
445 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
446 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
447 static rtx
sparc_delegitimize_address (rtx
);
448 static bool sparc_mode_dependent_address_p (const_rtx
);
449 static bool sparc_pass_by_reference (cumulative_args_t
,
450 enum machine_mode
, const_tree
, bool);
451 static void sparc_function_arg_advance (cumulative_args_t
,
452 enum machine_mode
, const_tree
, bool);
453 static rtx
sparc_function_arg_1 (cumulative_args_t
,
454 enum machine_mode
, const_tree
, bool, bool);
455 static rtx
sparc_function_arg (cumulative_args_t
,
456 enum machine_mode
, const_tree
, bool);
457 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
458 enum machine_mode
, const_tree
, bool);
459 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
461 static int sparc_arg_partial_bytes (cumulative_args_t
,
462 enum machine_mode
, tree
, bool);
463 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
464 static void sparc_file_end (void);
465 static bool sparc_frame_pointer_required (void);
466 static bool sparc_can_eliminate (const int, const int);
467 static rtx
sparc_builtin_setjmp_frame_value (void);
468 static void sparc_conditional_register_usage (void);
469 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
470 static const char *sparc_mangle_type (const_tree
);
472 static void sparc_trampoline_init (rtx
, tree
, rtx
);
473 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
474 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
475 static bool sparc_print_operand_punct_valid_p (unsigned char);
476 static void sparc_print_operand (FILE *, rtx
, int);
477 static void sparc_print_operand_address (FILE *, rtx
);
479 #ifdef SUBTARGET_ATTRIBUTE_TABLE
480 /* Table of valid machine attributes. */
481 static const struct attribute_spec sparc_attribute_table
[] =
483 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
485 SUBTARGET_ATTRIBUTE_TABLE
,
486 { NULL
, 0, 0, false, false, false, NULL
, false }
490 /* Option handling. */
493 enum cmodel sparc_cmodel
;
495 char sparc_hard_reg_printed
[8];
497 /* Initialize the GCC target structure. */
499 /* The default is to use .half rather than .short for aligned HI objects. */
500 #undef TARGET_ASM_ALIGNED_HI_OP
501 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
503 #undef TARGET_ASM_UNALIGNED_HI_OP
504 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
505 #undef TARGET_ASM_UNALIGNED_SI_OP
506 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
507 #undef TARGET_ASM_UNALIGNED_DI_OP
508 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
510 /* The target hook has to handle DI-mode values. */
511 #undef TARGET_ASM_INTEGER
512 #define TARGET_ASM_INTEGER sparc_assemble_integer
514 #undef TARGET_ASM_FUNCTION_PROLOGUE
515 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
516 #undef TARGET_ASM_FUNCTION_EPILOGUE
517 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
519 #undef TARGET_SCHED_ADJUST_COST
520 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
521 #undef TARGET_SCHED_ISSUE_RATE
522 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
523 #undef TARGET_SCHED_INIT
524 #define TARGET_SCHED_INIT sparc_sched_init
525 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
526 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
528 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
529 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
531 #undef TARGET_INIT_LIBFUNCS
532 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
533 #undef TARGET_INIT_BUILTINS
534 #define TARGET_INIT_BUILTINS sparc_init_builtins
536 #undef TARGET_LEGITIMIZE_ADDRESS
537 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
538 #undef TARGET_DELEGITIMIZE_ADDRESS
539 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
540 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
541 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
543 #undef TARGET_EXPAND_BUILTIN
544 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
545 #undef TARGET_FOLD_BUILTIN
546 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
549 #undef TARGET_HAVE_TLS
550 #define TARGET_HAVE_TLS true
553 #undef TARGET_CANNOT_FORCE_CONST_MEM
554 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
556 #undef TARGET_ASM_OUTPUT_MI_THUNK
557 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
558 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
559 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
561 #undef TARGET_RTX_COSTS
562 #define TARGET_RTX_COSTS sparc_rtx_costs
563 #undef TARGET_ADDRESS_COST
564 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
565 #undef TARGET_REGISTER_MOVE_COST
566 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
568 #undef TARGET_PROMOTE_FUNCTION_MODE
569 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
571 #undef TARGET_FUNCTION_VALUE
572 #define TARGET_FUNCTION_VALUE sparc_function_value
573 #undef TARGET_LIBCALL_VALUE
574 #define TARGET_LIBCALL_VALUE sparc_libcall_value
575 #undef TARGET_FUNCTION_VALUE_REGNO_P
576 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
578 #undef TARGET_STRUCT_VALUE_RTX
579 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
580 #undef TARGET_RETURN_IN_MEMORY
581 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
582 #undef TARGET_MUST_PASS_IN_STACK
583 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
584 #undef TARGET_PASS_BY_REFERENCE
585 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
586 #undef TARGET_ARG_PARTIAL_BYTES
587 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
588 #undef TARGET_FUNCTION_ARG_ADVANCE
589 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
590 #undef TARGET_FUNCTION_ARG
591 #define TARGET_FUNCTION_ARG sparc_function_arg
592 #undef TARGET_FUNCTION_INCOMING_ARG
593 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
594 #undef TARGET_FUNCTION_ARG_BOUNDARY
595 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
597 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
598 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
599 #undef TARGET_STRICT_ARGUMENT_NAMING
600 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
602 #undef TARGET_EXPAND_BUILTIN_VA_START
603 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
604 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
605 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
607 #undef TARGET_VECTOR_MODE_SUPPORTED_P
608 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
610 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
611 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
613 #ifdef SUBTARGET_INSERT_ATTRIBUTES
614 #undef TARGET_INSERT_ATTRIBUTES
615 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
618 #ifdef SUBTARGET_ATTRIBUTE_TABLE
619 #undef TARGET_ATTRIBUTE_TABLE
620 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
623 #undef TARGET_RELAXED_ORDERING
624 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
626 #undef TARGET_OPTION_OVERRIDE
627 #define TARGET_OPTION_OVERRIDE sparc_option_override
629 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
630 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
631 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
634 #undef TARGET_ASM_FILE_END
635 #define TARGET_ASM_FILE_END sparc_file_end
637 #undef TARGET_FRAME_POINTER_REQUIRED
638 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
640 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
641 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
643 #undef TARGET_CAN_ELIMINATE
644 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
646 #undef TARGET_PREFERRED_RELOAD_CLASS
647 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
649 #undef TARGET_CONDITIONAL_REGISTER_USAGE
650 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
652 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
653 #undef TARGET_MANGLE_TYPE
654 #define TARGET_MANGLE_TYPE sparc_mangle_type
657 #undef TARGET_LEGITIMATE_ADDRESS_P
658 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
660 #undef TARGET_LEGITIMATE_CONSTANT_P
661 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
663 #undef TARGET_TRAMPOLINE_INIT
664 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
666 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
667 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
668 #undef TARGET_PRINT_OPERAND
669 #define TARGET_PRINT_OPERAND sparc_print_operand
670 #undef TARGET_PRINT_OPERAND_ADDRESS
671 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
673 struct gcc_target targetm
= TARGET_INITIALIZER
;
675 /* Validate and override various options, and do some machine dependent
679 sparc_option_override (void)
681 static struct code_model
{
682 const char *const name
;
683 const enum cmodel value
;
684 } const cmodels
[] = {
686 { "medlow", CM_MEDLOW
},
687 { "medmid", CM_MEDMID
},
688 { "medany", CM_MEDANY
},
689 { "embmedany", CM_EMBMEDANY
},
690 { NULL
, (enum cmodel
) 0 }
692 const struct code_model
*cmodel
;
693 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
694 static struct cpu_default
{
696 const enum processor_type processor
;
697 } const cpu_default
[] = {
698 /* There must be one entry here for each TARGET_CPU value. */
699 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
700 { TARGET_CPU_v8
, PROCESSOR_V8
},
701 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
702 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
703 { TARGET_CPU_leon
, PROCESSOR_LEON
},
704 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
705 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
706 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
707 { TARGET_CPU_v9
, PROCESSOR_V9
},
708 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
709 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
710 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
711 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
712 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
713 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
716 const struct cpu_default
*def
;
717 /* Table of values for -m{cpu,tune}=. This must match the order of
718 the PROCESSOR_* enumeration. */
719 static struct cpu_table
{
722 } const cpu_table
[] = {
725 { MASK_ISA
, MASK_V8
},
726 /* TI TMS390Z55 supersparc */
727 { MASK_ISA
, MASK_V8
},
728 { MASK_ISA
, MASK_V8
|MASK_FPU
},
730 { MASK_ISA
, MASK_V8
|MASK_FPU
},
731 { MASK_ISA
, MASK_SPARCLITE
},
732 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
733 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
734 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
735 { MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
736 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
737 { MASK_ISA
, MASK_SPARCLET
},
739 { MASK_ISA
, MASK_SPARCLET
},
740 { MASK_ISA
, MASK_V9
},
741 /* UltraSPARC I, II, IIi */
743 /* Although insns using %y are deprecated, it is a clear win. */
744 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
746 /* ??? Check if %y issue still holds true. */
748 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
751 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
753 { MASK_ISA
, MASK_V9
},
755 { MASK_ISA
, MASK_V9
},
757 { MASK_ISA
, MASK_V9
},
759 const struct cpu_table
*cpu
;
763 #ifdef SUBTARGET_OVERRIDE_OPTIONS
764 SUBTARGET_OVERRIDE_OPTIONS
;
767 #ifndef SPARC_BI_ARCH
768 /* Check for unsupported architecture size. */
769 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
770 error ("%s is not supported by this configuration",
771 DEFAULT_ARCH32_P
? "-m64" : "-m32");
774 /* We force all 64bit archs to use 128 bit long double */
775 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
777 error ("-mlong-double-64 not allowed with -m64");
778 target_flags
|= MASK_LONG_DOUBLE_128
;
781 /* Code model selection. */
782 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
786 sparc_cmodel
= CM_32
;
789 if (sparc_cmodel_string
!= NULL
)
793 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
794 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
796 if (cmodel
->name
== NULL
)
797 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
799 sparc_cmodel
= cmodel
->value
;
802 error ("-mcmodel= is not supported on 32 bit systems");
805 /* Check that -fcall-saved-REG wasn't specified for out registers. */
806 for (i
= 8; i
< 16; i
++)
807 if (!call_used_regs
[i
])
809 error ("-fcall-saved-REG is not supported for out registers");
810 call_used_regs
[i
] = 1;
813 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
815 /* Set the default CPU. */
816 if (!global_options_set
.x_sparc_cpu_and_features
)
818 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
819 if (def
->cpu
== TARGET_CPU_DEFAULT
)
821 gcc_assert (def
->cpu
!= -1);
822 sparc_cpu_and_features
= def
->processor
;
824 if (!global_options_set
.x_sparc_cpu
)
825 sparc_cpu
= sparc_cpu_and_features
;
827 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
828 target_flags
&= ~cpu
->disable
;
829 target_flags
|= cpu
->enable
;
831 /* If -mfpu or -mno-fpu was explicitly used, don't override with
832 the processor default. */
833 if (target_flags_explicit
& MASK_FPU
)
834 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
836 /* Don't allow -mvis if FPU is disabled. */
838 target_flags
&= ~MASK_VIS
;
840 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
842 -m64 also implies v9. */
843 if (TARGET_VIS
|| TARGET_ARCH64
)
845 target_flags
|= MASK_V9
;
846 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
849 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
850 if (TARGET_V9
&& TARGET_ARCH32
)
851 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
853 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
854 if (! TARGET_V9
|| TARGET_ARCH64
)
855 target_flags
&= ~MASK_V8PLUS
;
857 /* Don't use stack biasing in 32 bit mode. */
859 target_flags
&= ~MASK_STACK_BIAS
;
861 /* Supply a default value for align_functions. */
862 if (align_functions
== 0
863 && (sparc_cpu
== PROCESSOR_ULTRASPARC
864 || sparc_cpu
== PROCESSOR_ULTRASPARC3
865 || sparc_cpu
== PROCESSOR_NIAGARA
866 || sparc_cpu
== PROCESSOR_NIAGARA2
867 || sparc_cpu
== PROCESSOR_NIAGARA3
868 || sparc_cpu
== PROCESSOR_NIAGARA4
))
869 align_functions
= 32;
871 /* Validate PCC_STRUCT_RETURN. */
872 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
873 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
875 /* Only use .uaxword when compiling for a 64-bit target. */
877 targetm
.asm_out
.unaligned_op
.di
= NULL
;
879 /* Do various machine dependent initializations. */
882 /* Set up function hooks. */
883 init_machine_status
= sparc_init_machine_status
;
888 case PROCESSOR_CYPRESS
:
889 sparc_costs
= &cypress_costs
;
892 case PROCESSOR_SPARCLITE
:
893 case PROCESSOR_SUPERSPARC
:
894 sparc_costs
= &supersparc_costs
;
898 case PROCESSOR_HYPERSPARC
:
899 case PROCESSOR_SPARCLITE86X
:
900 sparc_costs
= &hypersparc_costs
;
903 sparc_costs
= &leon_costs
;
905 case PROCESSOR_SPARCLET
:
906 case PROCESSOR_TSC701
:
907 sparc_costs
= &sparclet_costs
;
910 case PROCESSOR_ULTRASPARC
:
911 sparc_costs
= &ultrasparc_costs
;
913 case PROCESSOR_ULTRASPARC3
:
914 sparc_costs
= &ultrasparc3_costs
;
916 case PROCESSOR_NIAGARA
:
917 sparc_costs
= &niagara_costs
;
919 case PROCESSOR_NIAGARA2
:
920 case PROCESSOR_NIAGARA3
:
921 case PROCESSOR_NIAGARA4
:
922 sparc_costs
= &niagara2_costs
;
924 case PROCESSOR_NATIVE
:
928 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
929 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
930 target_flags
|= MASK_LONG_DOUBLE_128
;
933 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
934 ((sparc_cpu
== PROCESSOR_ULTRASPARC
935 || sparc_cpu
== PROCESSOR_NIAGARA
936 || sparc_cpu
== PROCESSOR_NIAGARA2
937 || sparc_cpu
== PROCESSOR_NIAGARA3
938 || sparc_cpu
== PROCESSOR_NIAGARA4
)
940 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
942 global_options
.x_param_values
,
943 global_options_set
.x_param_values
);
944 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
945 ((sparc_cpu
== PROCESSOR_ULTRASPARC
946 || sparc_cpu
== PROCESSOR_ULTRASPARC3
947 || sparc_cpu
== PROCESSOR_NIAGARA
948 || sparc_cpu
== PROCESSOR_NIAGARA2
949 || sparc_cpu
== PROCESSOR_NIAGARA3
950 || sparc_cpu
== PROCESSOR_NIAGARA4
)
952 global_options
.x_param_values
,
953 global_options_set
.x_param_values
);
955 /* Disable save slot sharing for call-clobbered registers by default.
956 The IRA sharing algorithm works on single registers only and this
957 pessimizes for double floating-point registers. */
958 if (!global_options_set
.x_flag_ira_share_save_slots
)
959 flag_ira_share_save_slots
= 0;
962 /* Miscellaneous utilities. */
964 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
965 or branch on register contents instructions. */
968 v9_regcmp_p (enum rtx_code code
)
970 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
971 || code
== LE
|| code
== GT
);
974 /* Nonzero if OP is a floating point constant which can
975 be loaded into an integer register using a single
976 sethi instruction. */
981 if (GET_CODE (op
) == CONST_DOUBLE
)
986 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
987 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
988 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
994 /* Nonzero if OP is a floating point constant which can
995 be loaded into an integer register using a single
1001 if (GET_CODE (op
) == CONST_DOUBLE
)
1006 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1007 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1008 return SPARC_SIMM13_P (i
);
1014 /* Nonzero if OP is a floating point constant which can
1015 be loaded into an integer register using a high/losum
1016 instruction sequence. */
1019 fp_high_losum_p (rtx op
)
1021 /* The constraints calling this should only be in
1022 SFmode move insns, so any constant which cannot
1023 be moved using a single insn will do. */
1024 if (GET_CODE (op
) == CONST_DOUBLE
)
1029 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1030 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1031 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1037 /* Return true if the address of LABEL can be loaded by means of the
1038 mov{si,di}_pic_label_ref patterns in PIC mode. */
1041 can_use_mov_pic_label_ref (rtx label
)
1043 /* VxWorks does not impose a fixed gap between segments; the run-time
1044 gap can be different from the object-file gap. We therefore can't
1045 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1046 are absolutely sure that X is in the same segment as the GOT.
1047 Unfortunately, the flexibility of linker scripts means that we
1048 can't be sure of that in general, so assume that GOT-relative
1049 accesses are never valid on VxWorks. */
1050 if (TARGET_VXWORKS_RTP
)
1053 /* Similarly, if the label is non-local, it might end up being placed
1054 in a different section than the current one; now mov_pic_label_ref
1055 requires the label and the code to be in the same section. */
1056 if (LABEL_REF_NONLOCAL_P (label
))
1059 /* Finally, if we are reordering basic blocks and partition into hot
1060 and cold sections, this might happen for any label. */
1061 if (flag_reorder_blocks_and_partition
)
1067 /* Expand a move instruction. Return true if all work is done. */
1070 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1072 /* Handle sets of MEM first. */
1073 if (GET_CODE (operands
[0]) == MEM
)
1075 /* 0 is a register (or a pair of registers) on SPARC. */
1076 if (register_or_zero_operand (operands
[1], mode
))
1079 if (!reload_in_progress
)
1081 operands
[0] = validize_mem (operands
[0]);
1082 operands
[1] = force_reg (mode
, operands
[1]);
1086 /* Fixup TLS cases. */
1088 && CONSTANT_P (operands
[1])
1089 && sparc_tls_referenced_p (operands
[1]))
1091 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1095 /* Fixup PIC cases. */
1096 if (flag_pic
&& CONSTANT_P (operands
[1]))
1098 if (pic_address_needs_scratch (operands
[1]))
1099 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1101 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1102 if (GET_CODE (operands
[1]) == LABEL_REF
1103 && can_use_mov_pic_label_ref (operands
[1]))
1107 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1113 gcc_assert (TARGET_ARCH64
);
1114 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1119 if (symbolic_operand (operands
[1], mode
))
1122 = sparc_legitimize_pic_address (operands
[1],
1124 ? operands
[0] : NULL_RTX
);
1129 /* If we are trying to toss an integer constant into FP registers,
1130 or loading a FP or vector constant, force it into memory. */
1131 if (CONSTANT_P (operands
[1])
1132 && REG_P (operands
[0])
1133 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1134 || SCALAR_FLOAT_MODE_P (mode
)
1135 || VECTOR_MODE_P (mode
)))
1137 /* emit_group_store will send such bogosity to us when it is
1138 not storing directly into memory. So fix this up to avoid
1139 crashes in output_constant_pool. */
1140 if (operands
[1] == const0_rtx
)
1141 operands
[1] = CONST0_RTX (mode
);
1143 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1144 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1145 && const_zero_operand (operands
[1], mode
))
1148 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1149 /* We are able to build any SF constant in integer registers
1150 with at most 2 instructions. */
1152 /* And any DF constant in integer registers. */
1154 && (reload_completed
|| reload_in_progress
))))
1157 operands
[1] = force_const_mem (mode
, operands
[1]);
1158 if (!reload_in_progress
)
1159 operands
[1] = validize_mem (operands
[1]);
1163 /* Accept non-constants and valid constants unmodified. */
1164 if (!CONSTANT_P (operands
[1])
1165 || GET_CODE (operands
[1]) == HIGH
1166 || input_operand (operands
[1], mode
))
1172 /* All QImode constants require only one insn, so proceed. */
1177 sparc_emit_set_const32 (operands
[0], operands
[1]);
1181 /* input_operand should have filtered out 32-bit mode. */
1182 sparc_emit_set_const64 (operands
[0], operands
[1]);
1192 /* Load OP1, a 32-bit constant, into OP0, a register.
1193 We know it can't be done in one insn when we get
1194 here, the move expander guarantees this. */
1197 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1199 enum machine_mode mode
= GET_MODE (op0
);
1202 if (reload_in_progress
|| reload_completed
)
1205 temp
= gen_reg_rtx (mode
);
1207 if (GET_CODE (op1
) == CONST_INT
)
1209 gcc_assert (!small_int_operand (op1
, mode
)
1210 && !const_high_operand (op1
, mode
));
1212 /* Emit them as real moves instead of a HIGH/LO_SUM,
1213 this way CSE can see everything and reuse intermediate
1214 values if it wants. */
1215 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1216 GEN_INT (INTVAL (op1
)
1217 & ~(HOST_WIDE_INT
)0x3ff)));
1219 emit_insn (gen_rtx_SET (VOIDmode
,
1221 gen_rtx_IOR (mode
, temp
,
1222 GEN_INT (INTVAL (op1
) & 0x3ff))));
1226 /* A symbol, emit in the traditional way. */
1227 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1228 gen_rtx_HIGH (mode
, op1
)));
1229 emit_insn (gen_rtx_SET (VOIDmode
,
1230 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1234 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1235 If TEMP is nonzero, we are forbidden to use any other scratch
1236 registers. Otherwise, we are allowed to generate them as needed.
1238 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1239 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1242 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1244 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1247 if (temp
&& GET_MODE (temp
) == TImode
)
1250 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1253 /* SPARC-V9 code-model support. */
1254 switch (sparc_cmodel
)
1257 /* The range spanned by all instructions in the object is less
1258 than 2^31 bytes (2GB) and the distance from any instruction
1259 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1260 than 2^31 bytes (2GB).
1262 The executable must be in the low 4TB of the virtual address
1265 sethi %hi(symbol), %temp1
1266 or %temp1, %lo(symbol), %reg */
1268 temp1
= temp
; /* op0 is allowed. */
1270 temp1
= gen_reg_rtx (DImode
);
1272 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1273 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1277 /* The range spanned by all instructions in the object is less
1278 than 2^31 bytes (2GB) and the distance from any instruction
1279 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1280 than 2^31 bytes (2GB).
1282 The executable must be in the low 16TB of the virtual address
1285 sethi %h44(symbol), %temp1
1286 or %temp1, %m44(symbol), %temp2
1287 sllx %temp2, 12, %temp3
1288 or %temp3, %l44(symbol), %reg */
1293 temp3
= temp
; /* op0 is allowed. */
1297 temp1
= gen_reg_rtx (DImode
);
1298 temp2
= gen_reg_rtx (DImode
);
1299 temp3
= gen_reg_rtx (DImode
);
1302 emit_insn (gen_seth44 (temp1
, op1
));
1303 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1304 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1305 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1306 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1310 /* The range spanned by all instructions in the object is less
1311 than 2^31 bytes (2GB) and the distance from any instruction
1312 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1313 than 2^31 bytes (2GB).
1315 The executable can be placed anywhere in the virtual address
1318 sethi %hh(symbol), %temp1
1319 sethi %lm(symbol), %temp2
1320 or %temp1, %hm(symbol), %temp3
1321 sllx %temp3, 32, %temp4
1322 or %temp4, %temp2, %temp5
1323 or %temp5, %lo(symbol), %reg */
1326 /* It is possible that one of the registers we got for operands[2]
1327 might coincide with that of operands[0] (which is why we made
1328 it TImode). Pick the other one to use as our scratch. */
1329 if (rtx_equal_p (temp
, op0
))
1331 gcc_assert (ti_temp
);
1332 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1335 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1342 temp1
= gen_reg_rtx (DImode
);
1343 temp2
= gen_reg_rtx (DImode
);
1344 temp3
= gen_reg_rtx (DImode
);
1345 temp4
= gen_reg_rtx (DImode
);
1346 temp5
= gen_reg_rtx (DImode
);
1349 emit_insn (gen_sethh (temp1
, op1
));
1350 emit_insn (gen_setlm (temp2
, op1
));
1351 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1352 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1353 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1354 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1355 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1356 emit_insn (gen_setlo (op0
, temp5
, op1
));
1360 /* Old old old backwards compatibility kruft here.
1361 Essentially it is MEDLOW with a fixed 64-bit
1362 virtual base added to all data segment addresses.
1363 Text-segment stuff is computed like MEDANY, we can't
1364 reuse the code above because the relocation knobs
1367 Data segment: sethi %hi(symbol), %temp1
1368 add %temp1, EMBMEDANY_BASE_REG, %temp2
1369 or %temp2, %lo(symbol), %reg */
1370 if (data_segment_operand (op1
, GET_MODE (op1
)))
1374 temp1
= temp
; /* op0 is allowed. */
1379 temp1
= gen_reg_rtx (DImode
);
1380 temp2
= gen_reg_rtx (DImode
);
1383 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1384 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1385 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1388 /* Text segment: sethi %uhi(symbol), %temp1
1389 sethi %hi(symbol), %temp2
1390 or %temp1, %ulo(symbol), %temp3
1391 sllx %temp3, 32, %temp4
1392 or %temp4, %temp2, %temp5
1393 or %temp5, %lo(symbol), %reg */
1398 /* It is possible that one of the registers we got for operands[2]
1399 might coincide with that of operands[0] (which is why we made
1400 it TImode). Pick the other one to use as our scratch. */
1401 if (rtx_equal_p (temp
, op0
))
1403 gcc_assert (ti_temp
);
1404 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1407 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1414 temp1
= gen_reg_rtx (DImode
);
1415 temp2
= gen_reg_rtx (DImode
);
1416 temp3
= gen_reg_rtx (DImode
);
1417 temp4
= gen_reg_rtx (DImode
);
1418 temp5
= gen_reg_rtx (DImode
);
1421 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1422 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1423 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1424 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1425 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1426 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1427 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1428 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1437 #if HOST_BITS_PER_WIDE_INT == 32
1439 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1444 /* These avoid problems when cross compiling. If we do not
1445 go through all this hair then the optimizer will see
1446 invalid REG_EQUAL notes or in some cases none at all. */
1447 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1448 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1449 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1450 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1452 /* The optimizer is not to assume anything about exactly
1453 which bits are set for a HIGH, they are unspecified.
1454 Unfortunately this leads to many missed optimizations
1455 during CSE. We mask out the non-HIGH bits, and matches
1456 a plain movdi, to alleviate this problem. */
1458 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1460 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1464 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1466 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1470 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1472 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1476 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1478 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1481 /* Worker routines for 64-bit constant formation on arch64.
1482 One of the key things to be doing in these emissions is
1483 to create as many temp REGs as possible. This makes it
1484 possible for half-built constants to be used later when
1485 such values are similar to something required later on.
1486 Without doing this, the optimizer cannot see such
1489 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1490 unsigned HOST_WIDE_INT
, int);
1493 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1494 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1496 unsigned HOST_WIDE_INT high_bits
;
1499 high_bits
= (~low_bits
) & 0xffffffff;
1501 high_bits
= low_bits
;
1503 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1506 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1507 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1511 /* If we are XOR'ing with -1, then we should emit a one's complement
1512 instead. This way the combiner will notice logical operations
1513 such as ANDN later on and substitute. */
1514 if ((low_bits
& 0x3ff) == 0x3ff)
1516 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1517 gen_rtx_NOT (DImode
, temp
)));
1521 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1522 gen_safe_XOR64 (temp
,
1523 (-(HOST_WIDE_INT
)0x400
1524 | (low_bits
& 0x3ff)))));
1529 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1530 unsigned HOST_WIDE_INT
, int);
1533 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1534 unsigned HOST_WIDE_INT high_bits
,
1535 unsigned HOST_WIDE_INT low_immediate
,
1540 if ((high_bits
& 0xfffffc00) != 0)
1542 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1543 if ((high_bits
& ~0xfffffc00) != 0)
1544 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1545 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1551 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1555 /* Now shift it up into place. */
1556 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1557 gen_rtx_ASHIFT (DImode
, temp2
,
1558 GEN_INT (shift_count
))));
1560 /* If there is a low immediate part piece, finish up by
1561 putting that in as well. */
1562 if (low_immediate
!= 0)
1563 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1564 gen_safe_OR64 (op0
, low_immediate
)));
1567 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1568 unsigned HOST_WIDE_INT
);
1570 /* Full 64-bit constant decomposition. Even though this is the
1571 'worst' case, we still optimize a few things away. */
1573 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1574 unsigned HOST_WIDE_INT high_bits
,
1575 unsigned HOST_WIDE_INT low_bits
)
1579 if (reload_in_progress
|| reload_completed
)
1582 sub_temp
= gen_reg_rtx (DImode
);
1584 if ((high_bits
& 0xfffffc00) != 0)
1586 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1587 if ((high_bits
& ~0xfffffc00) != 0)
1588 emit_insn (gen_rtx_SET (VOIDmode
,
1590 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1596 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1600 if (!reload_in_progress
&& !reload_completed
)
1602 rtx temp2
= gen_reg_rtx (DImode
);
1603 rtx temp3
= gen_reg_rtx (DImode
);
1604 rtx temp4
= gen_reg_rtx (DImode
);
1606 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1607 gen_rtx_ASHIFT (DImode
, sub_temp
,
1610 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1611 if ((low_bits
& ~0xfffffc00) != 0)
1613 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1614 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1615 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1616 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1620 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1621 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1626 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1627 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1628 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1631 /* We are in the middle of reload, so this is really
1632 painful. However we do still make an attempt to
1633 avoid emitting truly stupid code. */
1634 if (low1
!= const0_rtx
)
1636 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1637 gen_rtx_ASHIFT (DImode
, sub_temp
,
1638 GEN_INT (to_shift
))));
1639 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1640 gen_rtx_IOR (DImode
, op0
, low1
)));
1648 if (low2
!= const0_rtx
)
1650 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1651 gen_rtx_ASHIFT (DImode
, sub_temp
,
1652 GEN_INT (to_shift
))));
1653 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1654 gen_rtx_IOR (DImode
, op0
, low2
)));
1662 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1663 gen_rtx_ASHIFT (DImode
, sub_temp
,
1664 GEN_INT (to_shift
))));
1665 if (low3
!= const0_rtx
)
1666 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1667 gen_rtx_IOR (DImode
, op0
, low3
)));
1672 /* Analyze a 64-bit constant for certain properties. */
1673 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1674 unsigned HOST_WIDE_INT
,
1675 int *, int *, int *);
1678 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1679 unsigned HOST_WIDE_INT low_bits
,
1680 int *hbsp
, int *lbsp
, int *abbasp
)
1682 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1685 lowest_bit_set
= highest_bit_set
= -1;
1689 if ((lowest_bit_set
== -1)
1690 && ((low_bits
>> i
) & 1))
1692 if ((highest_bit_set
== -1)
1693 && ((high_bits
>> (32 - i
- 1)) & 1))
1694 highest_bit_set
= (64 - i
- 1);
1697 && ((highest_bit_set
== -1)
1698 || (lowest_bit_set
== -1)));
1704 if ((lowest_bit_set
== -1)
1705 && ((high_bits
>> i
) & 1))
1706 lowest_bit_set
= i
+ 32;
1707 if ((highest_bit_set
== -1)
1708 && ((low_bits
>> (32 - i
- 1)) & 1))
1709 highest_bit_set
= 32 - i
- 1;
1712 && ((highest_bit_set
== -1)
1713 || (lowest_bit_set
== -1)));
1715 /* If there are no bits set this should have gone out
1716 as one instruction! */
1717 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1718 all_bits_between_are_set
= 1;
1719 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1723 if ((low_bits
& (1 << i
)) != 0)
1728 if ((high_bits
& (1 << (i
- 32))) != 0)
1731 all_bits_between_are_set
= 0;
1734 *hbsp
= highest_bit_set
;
1735 *lbsp
= lowest_bit_set
;
1736 *abbasp
= all_bits_between_are_set
;
1739 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1742 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1743 unsigned HOST_WIDE_INT low_bits
)
1745 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1748 || high_bits
== 0xffffffff)
1751 analyze_64bit_constant (high_bits
, low_bits
,
1752 &highest_bit_set
, &lowest_bit_set
,
1753 &all_bits_between_are_set
);
1755 if ((highest_bit_set
== 63
1756 || lowest_bit_set
== 0)
1757 && all_bits_between_are_set
!= 0)
1760 if ((highest_bit_set
- lowest_bit_set
) < 21)
1766 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1767 unsigned HOST_WIDE_INT
,
1770 static unsigned HOST_WIDE_INT
1771 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1772 unsigned HOST_WIDE_INT low_bits
,
1773 int lowest_bit_set
, int shift
)
1775 HOST_WIDE_INT hi
, lo
;
1777 if (lowest_bit_set
< 32)
1779 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1780 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1785 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1787 gcc_assert (! (hi
& lo
));
1791 /* Here we are sure to be arch64 and this is an integer constant
1792 being loaded into a register. Emit the most efficient
1793 insn sequence possible. Detection of all the 1-insn cases
1794 has been done already. */
1796 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1798 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1799 int lowest_bit_set
, highest_bit_set
;
1800 int all_bits_between_are_set
;
1803 /* Sanity check that we know what we are working with. */
1804 gcc_assert (TARGET_ARCH64
1805 && (GET_CODE (op0
) == SUBREG
1806 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1808 if (reload_in_progress
|| reload_completed
)
1811 if (GET_CODE (op1
) != CONST_INT
)
1813 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1818 temp
= gen_reg_rtx (DImode
);
1820 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1821 low_bits
= (INTVAL (op1
) & 0xffffffff);
1823 /* low_bits bits 0 --> 31
1824 high_bits bits 32 --> 63 */
1826 analyze_64bit_constant (high_bits
, low_bits
,
1827 &highest_bit_set
, &lowest_bit_set
,
1828 &all_bits_between_are_set
);
1830 /* First try for a 2-insn sequence. */
1832 /* These situations are preferred because the optimizer can
1833 * do more things with them:
1835 * sllx %reg, shift, %reg
1837 * srlx %reg, shift, %reg
1838 * 3) mov some_small_const, %reg
1839 * sllx %reg, shift, %reg
1841 if (((highest_bit_set
== 63
1842 || lowest_bit_set
== 0)
1843 && all_bits_between_are_set
!= 0)
1844 || ((highest_bit_set
- lowest_bit_set
) < 12))
1846 HOST_WIDE_INT the_const
= -1;
1847 int shift
= lowest_bit_set
;
1849 if ((highest_bit_set
!= 63
1850 && lowest_bit_set
!= 0)
1851 || all_bits_between_are_set
== 0)
1854 create_simple_focus_bits (high_bits
, low_bits
,
1857 else if (lowest_bit_set
== 0)
1858 shift
= -(63 - highest_bit_set
);
1860 gcc_assert (SPARC_SIMM13_P (the_const
));
1861 gcc_assert (shift
!= 0);
1863 emit_insn (gen_safe_SET64 (temp
, the_const
));
1865 emit_insn (gen_rtx_SET (VOIDmode
,
1867 gen_rtx_ASHIFT (DImode
,
1871 emit_insn (gen_rtx_SET (VOIDmode
,
1873 gen_rtx_LSHIFTRT (DImode
,
1875 GEN_INT (-shift
))));
1879 /* Now a range of 22 or less bits set somewhere.
1880 * 1) sethi %hi(focus_bits), %reg
1881 * sllx %reg, shift, %reg
1882 * 2) sethi %hi(focus_bits), %reg
1883 * srlx %reg, shift, %reg
1885 if ((highest_bit_set
- lowest_bit_set
) < 21)
1887 unsigned HOST_WIDE_INT focus_bits
=
1888 create_simple_focus_bits (high_bits
, low_bits
,
1889 lowest_bit_set
, 10);
1891 gcc_assert (SPARC_SETHI_P (focus_bits
));
1892 gcc_assert (lowest_bit_set
!= 10);
1894 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1896 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1897 if (lowest_bit_set
< 10)
1898 emit_insn (gen_rtx_SET (VOIDmode
,
1900 gen_rtx_LSHIFTRT (DImode
, temp
,
1901 GEN_INT (10 - lowest_bit_set
))));
1902 else if (lowest_bit_set
> 10)
1903 emit_insn (gen_rtx_SET (VOIDmode
,
1905 gen_rtx_ASHIFT (DImode
, temp
,
1906 GEN_INT (lowest_bit_set
- 10))));
1910 /* 1) sethi %hi(low_bits), %reg
1911 * or %reg, %lo(low_bits), %reg
1912 * 2) sethi %hi(~low_bits), %reg
1913 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1916 || high_bits
== 0xffffffff)
1918 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1919 (high_bits
== 0xffffffff));
1923 /* Now, try 3-insn sequences. */
1925 /* 1) sethi %hi(high_bits), %reg
1926 * or %reg, %lo(high_bits), %reg
1927 * sllx %reg, 32, %reg
1931 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1935 /* We may be able to do something quick
1936 when the constant is negated, so try that. */
1937 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1938 (~low_bits
) & 0xfffffc00))
1940 /* NOTE: The trailing bits get XOR'd so we need the
1941 non-negated bits, not the negated ones. */
1942 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1944 if ((((~high_bits
) & 0xffffffff) == 0
1945 && ((~low_bits
) & 0x80000000) == 0)
1946 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1947 && ((~low_bits
) & 0x80000000) != 0))
1949 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1951 if ((SPARC_SETHI_P (fast_int
)
1952 && (~high_bits
& 0xffffffff) == 0)
1953 || SPARC_SIMM13_P (fast_int
))
1954 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1956 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
1961 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1962 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1963 sparc_emit_set_const64 (temp
, negated_const
);
1966 /* If we are XOR'ing with -1, then we should emit a one's complement
1967 instead. This way the combiner will notice logical operations
1968 such as ANDN later on and substitute. */
1969 if (trailing_bits
== 0x3ff)
1971 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1972 gen_rtx_NOT (DImode
, temp
)));
1976 emit_insn (gen_rtx_SET (VOIDmode
,
1978 gen_safe_XOR64 (temp
,
1979 (-0x400 | trailing_bits
))));
1984 /* 1) sethi %hi(xxx), %reg
1985 * or %reg, %lo(xxx), %reg
1986 * sllx %reg, yyy, %reg
1988 * ??? This is just a generalized version of the low_bits==0
1989 * thing above, FIXME...
1991 if ((highest_bit_set
- lowest_bit_set
) < 32)
1993 unsigned HOST_WIDE_INT focus_bits
=
1994 create_simple_focus_bits (high_bits
, low_bits
,
1997 /* We can't get here in this state. */
1998 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2000 /* So what we know is that the set bits straddle the
2001 middle of the 64-bit word. */
2002 sparc_emit_set_const64_quick2 (op0
, temp
,
2008 /* 1) sethi %hi(high_bits), %reg
2009 * or %reg, %lo(high_bits), %reg
2010 * sllx %reg, 32, %reg
2011 * or %reg, low_bits, %reg
2013 if (SPARC_SIMM13_P(low_bits
)
2014 && ((int)low_bits
> 0))
2016 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2020 /* The easiest way when all else fails, is full decomposition. */
2021 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2023 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2025 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2026 return the mode to be used for the comparison. For floating-point,
2027 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2028 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2029 processing is needed. */
2032 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2034 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2060 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2061 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2063 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2064 return CCX_NOOVmode
;
2070 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2077 /* Emit the compare insn and return the CC reg for a CODE comparison
2078 with operands X and Y. */
2081 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2083 enum machine_mode mode
;
2086 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2089 mode
= SELECT_CC_MODE (code
, x
, y
);
2091 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2092 fcc regs (cse can't tell they're really call clobbered regs and will
2093 remove a duplicate comparison even if there is an intervening function
2094 call - it will then try to reload the cc reg via an int reg which is why
2095 we need the movcc patterns). It is possible to provide the movcc
2096 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2097 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2098 to tell cse that CCFPE mode registers (even pseudos) are call
2101 /* ??? This is an experiment. Rather than making changes to cse which may
2102 or may not be easy/clean, we do our own cse. This is possible because
2103 we will generate hard registers. Cse knows they're call clobbered (it
2104 doesn't know the same thing about pseudos). If we guess wrong, no big
2105 deal, but if we win, great! */
2107 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2108 #if 1 /* experiment */
2111 /* We cycle through the registers to ensure they're all exercised. */
2112 static int next_fcc_reg
= 0;
2113 /* Previous x,y for each fcc reg. */
2114 static rtx prev_args
[4][2];
2116 /* Scan prev_args for x,y. */
2117 for (reg
= 0; reg
< 4; reg
++)
2118 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2123 prev_args
[reg
][0] = x
;
2124 prev_args
[reg
][1] = y
;
2125 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2127 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2130 cc_reg
= gen_reg_rtx (mode
);
2131 #endif /* ! experiment */
2132 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2133 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2135 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2137 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2138 will only result in an unrecognizable insn so no point in asserting. */
2139 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2145 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2148 gen_compare_reg (rtx cmp
)
2150 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2153 /* This function is used for v9 only.
2154 DEST is the target of the Scc insn.
2155 CODE is the code for an Scc's comparison.
2156 X and Y are the values we compare.
2158 This function is needed to turn
2161 (gt (reg:CCX 100 %icc)
2165 (gt:DI (reg:CCX 100 %icc)
2168 IE: The instruction recognizer needs to see the mode of the comparison to
2169 find the right instruction. We could use "gt:DI" right in the
2170 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2173 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2176 && (GET_MODE (x
) == DImode
2177 || GET_MODE (dest
) == DImode
))
2180 /* Try to use the movrCC insns. */
2182 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2184 && v9_regcmp_p (compare_code
))
2189 /* Special case for op0 != 0. This can be done with one instruction if
2192 if (compare_code
== NE
2193 && GET_MODE (dest
) == DImode
2194 && rtx_equal_p (op0
, dest
))
2196 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2197 gen_rtx_IF_THEN_ELSE (DImode
,
2198 gen_rtx_fmt_ee (compare_code
, DImode
,
2205 if (reg_overlap_mentioned_p (dest
, op0
))
2207 /* Handle the case where dest == x.
2208 We "early clobber" the result. */
2209 op0
= gen_reg_rtx (GET_MODE (x
));
2210 emit_move_insn (op0
, x
);
2213 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2214 if (GET_MODE (op0
) != DImode
)
2216 temp
= gen_reg_rtx (DImode
);
2217 convert_move (temp
, op0
, 0);
2221 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2222 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2223 gen_rtx_fmt_ee (compare_code
, DImode
,
2231 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2234 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2235 && GET_MODE (x
) != CCX_NOOVmode
);
2237 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2238 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2239 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2240 gen_rtx_fmt_ee (compare_code
,
2241 GET_MODE (x
), x
, y
),
2242 const1_rtx
, dest
)));
2248 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2249 without jumps using the addx/subx instructions. */
2252 emit_scc_insn (rtx operands
[])
2259 /* The quad-word fp compare library routines all return nonzero to indicate
2260 true, which is different from the equivalent libgcc routines, so we must
2261 handle them specially here. */
2262 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2264 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2265 GET_CODE (operands
[1]));
2266 operands
[2] = XEXP (operands
[1], 0);
2267 operands
[3] = XEXP (operands
[1], 1);
2270 code
= GET_CODE (operands
[1]);
2274 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2275 more applications). The exception to this is "reg != 0" which can
2276 be done in one instruction on v9 (so we do it). */
2279 if (GET_MODE (x
) == SImode
)
2281 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2285 else if (GET_MODE (x
) == DImode
)
2287 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2295 if (GET_MODE (x
) == SImode
)
2297 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2301 else if (GET_MODE (x
) == DImode
)
2303 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2309 /* For the rest, on v9 we can use conditional moves. */
2313 if (gen_v9_scc (operands
[0], code
, x
, y
))
2317 /* We can do LTU and GEU using the addx/subx instructions too. And
2318 for GTU/LEU, if both operands are registers swap them and fall
2319 back to the easy case. */
2320 if (code
== GTU
|| code
== LEU
)
2322 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2323 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2328 code
= swap_condition (code
);
2332 if (code
== LTU
|| code
== GEU
)
2334 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2335 gen_rtx_fmt_ee (code
, SImode
,
2336 gen_compare_reg_1 (code
, x
, y
),
2341 /* Nope, do branches. */
2345 /* Emit a conditional jump insn for the v9 architecture using comparison code
2346 CODE and jump target LABEL.
2347 This function exists to take advantage of the v9 brxx insns. */
2350 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2352 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2354 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2355 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2357 gen_rtx_LABEL_REF (VOIDmode
, label
),
2362 emit_conditional_branch_insn (rtx operands
[])
2364 /* The quad-word fp compare library routines all return nonzero to indicate
2365 true, which is different from the equivalent libgcc routines, so we must
2366 handle them specially here. */
2367 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2369 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2370 GET_CODE (operands
[0]));
2371 operands
[1] = XEXP (operands
[0], 0);
2372 operands
[2] = XEXP (operands
[0], 1);
2375 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2376 && GET_CODE (operands
[1]) == REG
2377 && GET_MODE (operands
[1]) == DImode
)
2379 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2383 operands
[1] = gen_compare_reg (operands
[0]);
2384 operands
[2] = const0_rtx
;
2385 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2386 operands
[1], operands
[2]);
2387 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2392 /* Generate a DFmode part of a hard TFmode register.
2393 REG is the TFmode hard register, LOW is 1 for the
2394 low 64bit of the register and 0 otherwise.
2397 gen_df_reg (rtx reg
, int low
)
2399 int regno
= REGNO (reg
);
2401 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2402 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2403 return gen_rtx_REG (DFmode
, regno
);
2406 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2407 Unlike normal calls, TFmode operands are passed by reference. It is
2408 assumed that no more than 3 operands are required. */
2411 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2413 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2416 /* We only expect to be called for conversions, unary, and binary ops. */
2417 gcc_assert (nargs
== 2 || nargs
== 3);
2419 for (i
= 0; i
< nargs
; ++i
)
2421 rtx this_arg
= operands
[i
];
2424 /* TFmode arguments and return values are passed by reference. */
2425 if (GET_MODE (this_arg
) == TFmode
)
2427 int force_stack_temp
;
2429 force_stack_temp
= 0;
2430 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2431 force_stack_temp
= 1;
2433 if (GET_CODE (this_arg
) == MEM
2434 && ! force_stack_temp
)
2435 this_arg
= XEXP (this_arg
, 0);
2436 else if (CONSTANT_P (this_arg
)
2437 && ! force_stack_temp
)
2439 this_slot
= force_const_mem (TFmode
, this_arg
);
2440 this_arg
= XEXP (this_slot
, 0);
2444 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2446 /* Operand 0 is the return value. We'll copy it out later. */
2448 emit_move_insn (this_slot
, this_arg
);
2450 ret_slot
= this_slot
;
2452 this_arg
= XEXP (this_slot
, 0);
2459 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2461 if (GET_MODE (operands
[0]) == TFmode
)
2464 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2465 arg
[0], GET_MODE (arg
[0]),
2466 arg
[1], GET_MODE (arg
[1]));
2468 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2469 arg
[0], GET_MODE (arg
[0]),
2470 arg
[1], GET_MODE (arg
[1]),
2471 arg
[2], GET_MODE (arg
[2]));
2474 emit_move_insn (operands
[0], ret_slot
);
2480 gcc_assert (nargs
== 2);
2482 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2483 GET_MODE (operands
[0]), 1,
2484 arg
[1], GET_MODE (arg
[1]));
2486 if (ret
!= operands
[0])
2487 emit_move_insn (operands
[0], ret
);
2491 /* Expand soft-float TFmode calls to sparc abi routines. */
2494 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2516 emit_soft_tfmode_libcall (func
, 3, operands
);
2520 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2524 gcc_assert (code
== SQRT
);
2527 emit_soft_tfmode_libcall (func
, 2, operands
);
2531 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2538 switch (GET_MODE (operands
[1]))
2551 case FLOAT_TRUNCATE
:
2552 switch (GET_MODE (operands
[0]))
2566 switch (GET_MODE (operands
[1]))
2571 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2581 case UNSIGNED_FLOAT
:
2582 switch (GET_MODE (operands
[1]))
2587 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2598 switch (GET_MODE (operands
[0]))
2612 switch (GET_MODE (operands
[0]))
2629 emit_soft_tfmode_libcall (func
, 2, operands
);
2632 /* Expand a hard-float tfmode operation. All arguments must be in
2636 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2640 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2642 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2643 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2647 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2648 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2649 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2650 operands
[1], operands
[2]);
2653 if (register_operand (operands
[0], VOIDmode
))
2656 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2658 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2660 if (dest
!= operands
[0])
2661 emit_move_insn (operands
[0], dest
);
2665 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2667 if (TARGET_HARD_QUAD
)
2668 emit_hard_tfmode_operation (code
, operands
);
2670 emit_soft_tfmode_binop (code
, operands
);
2674 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2676 if (TARGET_HARD_QUAD
)
2677 emit_hard_tfmode_operation (code
, operands
);
2679 emit_soft_tfmode_unop (code
, operands
);
2683 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2685 if (TARGET_HARD_QUAD
)
2686 emit_hard_tfmode_operation (code
, operands
);
2688 emit_soft_tfmode_cvt (code
, operands
);
2691 /* Return nonzero if a branch/jump/call instruction will be emitting
2692 nop into its delay slot. */
2695 empty_delay_slot (rtx insn
)
2699 /* If no previous instruction (should not happen), return true. */
2700 if (PREV_INSN (insn
) == NULL
)
2703 seq
= NEXT_INSN (PREV_INSN (insn
));
2704 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2710 /* Return nonzero if TRIAL can go into the call delay slot. */
2713 tls_call_delay (rtx trial
)
2718 call __tls_get_addr, %tgd_call (foo)
2719 add %l7, %o0, %o0, %tgd_add (foo)
2720 while Sun as/ld does not. */
2721 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2724 pat
= PATTERN (trial
);
2726 /* We must reject tgd_add{32|64}, i.e.
2727 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2728 and tldm_add{32|64}, i.e.
2729 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2731 if (GET_CODE (pat
) == SET
2732 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2734 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2736 if (GET_CODE (unspec
) == UNSPEC
2737 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2738 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2745 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2746 instruction. RETURN_P is true if the v9 variant 'return' is to be
2747 considered in the test too.
2749 TRIAL must be a SET whose destination is a REG appropriate for the
2750 'restore' instruction or, if RETURN_P is true, for the 'return'
2754 eligible_for_restore_insn (rtx trial
, bool return_p
)
2756 rtx pat
= PATTERN (trial
);
2757 rtx src
= SET_SRC (pat
);
2759 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2760 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2761 && arith_operand (src
, GET_MODE (src
)))
2764 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2766 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2769 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2770 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2771 && arith_double_operand (src
, GET_MODE (src
)))
2772 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2774 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2775 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2778 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2779 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2782 /* If we have the 'return' instruction, anything that does not use
2783 local or output registers and can go into a delay slot wins. */
2786 && !epilogue_renumber (&pat
, 1)
2787 && get_attr_in_uncond_branch_delay (trial
)
2788 == IN_UNCOND_BRANCH_DELAY_TRUE
)
2791 /* The 'restore src1,src2,dest' pattern for SImode. */
2792 else if (GET_CODE (src
) == PLUS
2793 && register_operand (XEXP (src
, 0), SImode
)
2794 && arith_operand (XEXP (src
, 1), SImode
))
2797 /* The 'restore src1,src2,dest' pattern for DImode. */
2798 else if (GET_CODE (src
) == PLUS
2799 && register_operand (XEXP (src
, 0), DImode
)
2800 && arith_double_operand (XEXP (src
, 1), DImode
))
2803 /* The 'restore src1,%lo(src2),dest' pattern. */
2804 else if (GET_CODE (src
) == LO_SUM
2805 && ! TARGET_CM_MEDMID
2806 && ((register_operand (XEXP (src
, 0), SImode
)
2807 && immediate_operand (XEXP (src
, 1), SImode
))
2809 && register_operand (XEXP (src
, 0), DImode
)
2810 && immediate_operand (XEXP (src
, 1), DImode
))))
2813 /* The 'restore src,src,dest' pattern. */
2814 else if (GET_CODE (src
) == ASHIFT
2815 && (register_operand (XEXP (src
, 0), SImode
)
2816 || register_operand (XEXP (src
, 0), DImode
))
2817 && XEXP (src
, 1) == const1_rtx
)
2823 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2826 eligible_for_return_delay (rtx trial
)
2830 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2833 if (get_attr_length (trial
) != 1)
2836 /* If the function uses __builtin_eh_return, the eh_return machinery
2837 occupies the delay slot. */
2838 if (crtl
->calls_eh_return
)
2841 /* In the case of a leaf or flat function, anything can go into the slot. */
2842 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2844 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
2846 pat
= PATTERN (trial
);
2848 /* Otherwise, only operations which can be done in tandem with
2849 a `restore' or `return' insn can go into the delay slot. */
2850 if (GET_CODE (SET_DEST (pat
)) != REG
2851 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24))
2854 /* If this instruction sets up floating point register and we have a return
2855 instruction, it can probably go in. But restore will not work
2857 if (REGNO (SET_DEST (pat
)) >= 32)
2859 && !epilogue_renumber (&pat
, 1)
2860 && get_attr_in_uncond_branch_delay (trial
)
2861 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2863 return eligible_for_restore_insn (trial
, true);
2866 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
2869 eligible_for_sibcall_delay (rtx trial
)
2873 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2876 if (get_attr_length (trial
) != 1)
2879 pat
= PATTERN (trial
);
2881 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2883 /* If the tail call is done using the call instruction,
2884 we have to restore %o7 in the delay slot. */
2885 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2888 /* %g1 is used to build the function address */
2889 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2895 /* Otherwise, only operations which can be done in tandem with
2896 a `restore' insn can go into the delay slot. */
2897 if (GET_CODE (SET_DEST (pat
)) != REG
2898 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2899 || REGNO (SET_DEST (pat
)) >= 32)
2902 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2904 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2907 return eligible_for_restore_insn (trial
, false);
2911 short_branch (int uid1
, int uid2
)
2913 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2915 /* Leave a few words of "slop". */
2916 if (delta
>= -1023 && delta
<= 1022)
2922 /* Return nonzero if REG is not used after INSN.
2923 We assume REG is a reload reg, and therefore does
2924 not live past labels or calls or jumps. */
2926 reg_unused_after (rtx reg
, rtx insn
)
2928 enum rtx_code code
, prev_code
= UNKNOWN
;
2930 while ((insn
= NEXT_INSN (insn
)))
2932 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2935 code
= GET_CODE (insn
);
2936 if (GET_CODE (insn
) == CODE_LABEL
)
2941 rtx set
= single_set (insn
);
2942 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2945 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2947 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2955 /* Determine if it's legal to put X into the constant pool. This
2956 is not possible if X contains the address of a symbol that is
2957 not constant (TLS) or not known at final link time (PIC). */
2960 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2962 switch (GET_CODE (x
))
2967 /* Accept all non-symbolic constants. */
2971 /* Labels are OK iff we are non-PIC. */
2972 return flag_pic
!= 0;
2975 /* 'Naked' TLS symbol references are never OK,
2976 non-TLS symbols are OK iff we are non-PIC. */
2977 if (SYMBOL_REF_TLS_MODEL (x
))
2980 return flag_pic
!= 0;
2983 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
2986 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
2987 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
2995 /* Global Offset Table support. */
2996 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
2997 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
2999 /* Return the SYMBOL_REF for the Global Offset Table. */
3001 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3006 if (!sparc_got_symbol
)
3007 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3009 return sparc_got_symbol
;
3012 /* Ensure that we are not using patterns that are not OK with PIC. */
3022 op
= recog_data
.operand
[i
];
3023 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3024 && (GET_CODE (op
) != CONST
3025 || (GET_CODE (XEXP (op
, 0)) == MINUS
3026 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3027 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3034 /* Return true if X is an address which needs a temporary register when
3035 reloaded while generating PIC code. */
3038 pic_address_needs_scratch (rtx x
)
3040 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3041 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3042 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3043 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3044 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3050 /* Determine if a given RTX is a valid constant. We already know this
3051 satisfies CONSTANT_P. */
3054 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3056 switch (GET_CODE (x
))
3060 if (sparc_tls_referenced_p (x
))
3065 if (GET_MODE (x
) == VOIDmode
)
3068 /* Floating point constants are generally not ok.
3069 The only exception is 0.0 in VIS. */
3071 && SCALAR_FLOAT_MODE_P (mode
)
3072 && const_zero_operand (x
, mode
))
3078 /* Vector constants are generally not ok.
3079 The only exception is 0 in VIS. */
3081 && const_zero_operand (x
, mode
))
3093 /* Determine if a given RTX is a valid constant address. */
3096 constant_address_p (rtx x
)
3098 switch (GET_CODE (x
))
3106 if (flag_pic
&& pic_address_needs_scratch (x
))
3108 return sparc_legitimate_constant_p (Pmode
, x
);
3111 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3118 /* Nonzero if the constant value X is a legitimate general operand
3119 when generating PIC code. It is given that flag_pic is on and
3120 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3123 legitimate_pic_operand_p (rtx x
)
3125 if (pic_address_needs_scratch (x
))
3127 if (sparc_tls_referenced_p (x
))
3132 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3134 && INTVAL (X) >= -0x1000 \
3135 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3137 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3139 && INTVAL (X) >= -0x1000 \
3140 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3142 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3144 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3145 ordinarily. This changes a bit when generating PIC. */
3148 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3150 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3152 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3154 else if (GET_CODE (addr
) == PLUS
)
3156 rs1
= XEXP (addr
, 0);
3157 rs2
= XEXP (addr
, 1);
3159 /* Canonicalize. REG comes first, if there are no regs,
3160 LO_SUM comes first. */
3162 && GET_CODE (rs1
) != SUBREG
3164 || GET_CODE (rs2
) == SUBREG
3165 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3167 rs1
= XEXP (addr
, 1);
3168 rs2
= XEXP (addr
, 0);
3172 && rs1
== pic_offset_table_rtx
3174 && GET_CODE (rs2
) != SUBREG
3175 && GET_CODE (rs2
) != LO_SUM
3176 && GET_CODE (rs2
) != MEM
3177 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3178 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3179 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3181 || GET_CODE (rs1
) == SUBREG
)
3182 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3187 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3188 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3190 /* We prohibit REG + REG for TFmode when there are no quad move insns
3191 and we consequently need to split. We do this because REG+REG
3192 is not an offsettable address. If we get the situation in reload
3193 where source and destination of a movtf pattern are both MEMs with
3194 REG+REG address, then only one of them gets converted to an
3195 offsettable address. */
3197 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3200 /* We prohibit REG + REG on ARCH32 if not optimizing for
3201 DFmode/DImode because then mem_min_alignment is likely to be zero
3202 after reload and the forced split would lack a matching splitter
3204 if (TARGET_ARCH32
&& !optimize
3205 && (mode
== DFmode
|| mode
== DImode
))
3208 else if (USE_AS_OFFSETABLE_LO10
3209 && GET_CODE (rs1
) == LO_SUM
3211 && ! TARGET_CM_MEDMID
3212 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3215 imm1
= XEXP (rs1
, 1);
3216 rs1
= XEXP (rs1
, 0);
3217 if (!CONSTANT_P (imm1
)
3218 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3222 else if (GET_CODE (addr
) == LO_SUM
)
3224 rs1
= XEXP (addr
, 0);
3225 imm1
= XEXP (addr
, 1);
3227 if (!CONSTANT_P (imm1
)
3228 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3231 /* We can't allow TFmode in 32-bit mode, because an offset greater
3232 than the alignment (8) may cause the LO_SUM to overflow. */
3233 if (mode
== TFmode
&& TARGET_ARCH32
)
3236 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3241 if (GET_CODE (rs1
) == SUBREG
)
3242 rs1
= SUBREG_REG (rs1
);
3248 if (GET_CODE (rs2
) == SUBREG
)
3249 rs2
= SUBREG_REG (rs2
);
3256 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3257 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3262 if ((REGNO (rs1
) >= 32
3263 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3264 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3266 && (REGNO (rs2
) >= 32
3267 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3268 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3274 /* Return the SYMBOL_REF for the tls_get_addr function. */
3276 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3279 sparc_tls_get_addr (void)
3281 if (!sparc_tls_symbol
)
3282 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3284 return sparc_tls_symbol
;
3287 /* Return the Global Offset Table to be used in TLS mode. */
3290 sparc_tls_got (void)
3292 /* In PIC mode, this is just the PIC offset table. */
3295 crtl
->uses_pic_offset_table
= 1;
3296 return pic_offset_table_rtx
;
3299 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3300 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3301 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3303 load_got_register ();
3304 return global_offset_table_rtx
;
3307 /* In all other cases, we load a new pseudo with the GOT symbol. */
3308 return copy_to_reg (sparc_got ());
3311 /* Return true if X contains a thread-local symbol. */
3314 sparc_tls_referenced_p (rtx x
)
3316 if (!TARGET_HAVE_TLS
)
3319 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3320 x
= XEXP (XEXP (x
, 0), 0);
3322 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3325 /* That's all we handle in sparc_legitimize_tls_address for now. */
3329 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3330 this (thread-local) address. */
3333 sparc_legitimize_tls_address (rtx addr
)
3335 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3337 gcc_assert (can_create_pseudo_p ());
3339 if (GET_CODE (addr
) == SYMBOL_REF
)
3340 switch (SYMBOL_REF_TLS_MODEL (addr
))
3342 case TLS_MODEL_GLOBAL_DYNAMIC
:
3344 temp1
= gen_reg_rtx (SImode
);
3345 temp2
= gen_reg_rtx (SImode
);
3346 ret
= gen_reg_rtx (Pmode
);
3347 o0
= gen_rtx_REG (Pmode
, 8);
3348 got
= sparc_tls_got ();
3349 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3350 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3353 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3354 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3359 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3360 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3363 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3364 insn
= get_insns ();
3366 emit_libcall_block (insn
, ret
, o0
, addr
);
3369 case TLS_MODEL_LOCAL_DYNAMIC
:
3371 temp1
= gen_reg_rtx (SImode
);
3372 temp2
= gen_reg_rtx (SImode
);
3373 temp3
= gen_reg_rtx (Pmode
);
3374 ret
= gen_reg_rtx (Pmode
);
3375 o0
= gen_rtx_REG (Pmode
, 8);
3376 got
= sparc_tls_got ();
3377 emit_insn (gen_tldm_hi22 (temp1
));
3378 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3381 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3382 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3387 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3388 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3391 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3392 insn
= get_insns ();
3394 emit_libcall_block (insn
, temp3
, o0
,
3395 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3396 UNSPEC_TLSLD_BASE
));
3397 temp1
= gen_reg_rtx (SImode
);
3398 temp2
= gen_reg_rtx (SImode
);
3399 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3400 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3402 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3404 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3407 case TLS_MODEL_INITIAL_EXEC
:
3408 temp1
= gen_reg_rtx (SImode
);
3409 temp2
= gen_reg_rtx (SImode
);
3410 temp3
= gen_reg_rtx (Pmode
);
3411 got
= sparc_tls_got ();
3412 emit_insn (gen_tie_hi22 (temp1
, addr
));
3413 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3415 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3417 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3420 ret
= gen_reg_rtx (Pmode
);
3422 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3425 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3429 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3432 case TLS_MODEL_LOCAL_EXEC
:
3433 temp1
= gen_reg_rtx (Pmode
);
3434 temp2
= gen_reg_rtx (Pmode
);
3437 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3438 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3442 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3443 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3445 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3452 else if (GET_CODE (addr
) == CONST
)
3456 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3458 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3459 offset
= XEXP (XEXP (addr
, 0), 1);
3461 base
= force_operand (base
, NULL_RTX
);
3462 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3463 offset
= force_reg (Pmode
, offset
);
3464 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3468 gcc_unreachable (); /* for now ... */
3473 /* Legitimize PIC addresses. If the address is already position-independent,
3474 we return ORIG. Newly generated position-independent addresses go into a
3475 reg. This is REG if nonzero, otherwise we allocate register(s) as
3479 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3481 bool gotdata_op
= false;
3483 if (GET_CODE (orig
) == SYMBOL_REF
3484 /* See the comment in sparc_expand_move. */
3485 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3487 rtx pic_ref
, address
;
3492 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3493 reg
= gen_reg_rtx (Pmode
);
3498 /* If not during reload, allocate another temp reg here for loading
3499 in the address, so that these instructions can be optimized
3501 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3502 ? reg
: gen_reg_rtx (Pmode
));
3504 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3505 won't get confused into thinking that these two instructions
3506 are loading in the true address of the symbol. If in the
3507 future a PIC rtx exists, that should be used instead. */
3510 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3511 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3515 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3516 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3524 crtl
->uses_pic_offset_table
= 1;
3528 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3529 pic_offset_table_rtx
,
3532 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3533 pic_offset_table_rtx
,
3539 = gen_const_mem (Pmode
,
3540 gen_rtx_PLUS (Pmode
,
3541 pic_offset_table_rtx
, address
));
3542 insn
= emit_move_insn (reg
, pic_ref
);
3545 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3547 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3550 else if (GET_CODE (orig
) == CONST
)
3554 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3555 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3560 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3561 reg
= gen_reg_rtx (Pmode
);
3564 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3565 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3566 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3567 base
== reg
? NULL_RTX
: reg
);
3569 if (GET_CODE (offset
) == CONST_INT
)
3571 if (SMALL_INT (offset
))
3572 return plus_constant (base
, INTVAL (offset
));
3573 else if (! reload_in_progress
&& ! reload_completed
)
3574 offset
= force_reg (Pmode
, offset
);
3576 /* If we reach here, then something is seriously wrong. */
3579 return gen_rtx_PLUS (Pmode
, base
, offset
);
3581 else if (GET_CODE (orig
) == LABEL_REF
)
3582 /* ??? We ought to be checking that the register is live instead, in case
3583 it is eliminated. */
3584 crtl
->uses_pic_offset_table
= 1;
3589 /* Try machine-dependent ways of modifying an illegitimate address X
3590 to be legitimate. If we find one, return the new, valid address.
3592 OLDX is the address as it was before break_out_memory_refs was called.
3593 In some cases it is useful to look at this to decide what needs to be done.
3595 MODE is the mode of the operand pointed to by X.
3597 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3600 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3601 enum machine_mode mode
)
3605 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3606 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3607 force_operand (XEXP (x
, 0), NULL_RTX
));
3608 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3609 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3610 force_operand (XEXP (x
, 1), NULL_RTX
));
3611 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3612 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3614 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3615 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3616 force_operand (XEXP (x
, 1), NULL_RTX
));
3618 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3621 if (sparc_tls_referenced_p (x
))
3622 x
= sparc_legitimize_tls_address (x
);
3624 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
3625 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3626 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3627 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3628 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3629 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3630 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3631 else if (GET_CODE (x
) == SYMBOL_REF
3632 || GET_CODE (x
) == CONST
3633 || GET_CODE (x
) == LABEL_REF
)
3634 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3639 /* Delegitimize an address that was legitimized by the above function. */
3642 sparc_delegitimize_address (rtx x
)
3644 x
= delegitimize_mem_from_attrs (x
);
3646 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
3647 switch (XINT (XEXP (x
, 1), 1))
3649 case UNSPEC_MOVE_PIC
:
3651 x
= XVECEXP (XEXP (x
, 1), 0, 0);
3652 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3658 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3659 if (GET_CODE (x
) == MINUS
3660 && REG_P (XEXP (x
, 0))
3661 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
3662 && GET_CODE (XEXP (x
, 1)) == LO_SUM
3663 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
3664 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
3666 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
3667 gcc_assert (GET_CODE (x
) == LABEL_REF
);
3673 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3674 replace the input X, or the original X if no replacement is called for.
3675 The output parameter *WIN is 1 if the calling macro should goto WIN,
3678 For SPARC, we wish to handle addresses by splitting them into
3679 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3680 This cuts the number of extra insns by one.
3682 Do nothing when generating PIC code and the address is a symbolic
3683 operand or requires a scratch register. */
3686 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3687 int opnum
, int type
,
3688 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3690 /* Decompose SImode constants into HIGH+LO_SUM. */
3692 && (mode
!= TFmode
|| TARGET_ARCH64
)
3693 && GET_MODE (x
) == SImode
3694 && GET_CODE (x
) != LO_SUM
3695 && GET_CODE (x
) != HIGH
3696 && sparc_cmodel
<= CM_MEDLOW
3698 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
3700 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
3701 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3702 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3703 opnum
, (enum reload_type
)type
);
3708 /* We have to recognize what we have already generated above. */
3709 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
3711 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3712 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3713 opnum
, (enum reload_type
)type
);
3722 /* Return true if ADDR (a legitimate address expression)
3723 has an effect that depends on the machine mode it is used for.
3729 is not equivalent to
3731 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3733 because [%l7+a+1] is interpreted as the address of (a+1). */
3737 sparc_mode_dependent_address_p (const_rtx addr
)
3739 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
3741 rtx op0
= XEXP (addr
, 0);
3742 rtx op1
= XEXP (addr
, 1);
3743 if (op0
== pic_offset_table_rtx
3744 && symbolic_operand (op1
, VOIDmode
))
3751 #ifdef HAVE_GAS_HIDDEN
3752 # define USE_HIDDEN_LINKONCE 1
3754 # define USE_HIDDEN_LINKONCE 0
3758 get_pc_thunk_name (char name
[32], unsigned int regno
)
3760 const char *reg_name
= reg_names
[regno
];
3762 /* Skip the leading '%' as that cannot be used in a
3766 if (USE_HIDDEN_LINKONCE
)
3767 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
3769 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3772 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3775 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
3777 int orig_flag_pic
= flag_pic
;
3780 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3783 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
3785 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
3786 flag_pic
= orig_flag_pic
;
3791 /* Emit code to load the GOT register. */
3794 load_got_register (void)
3796 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3797 if (!global_offset_table_rtx
)
3798 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
3800 if (TARGET_VXWORKS_RTP
)
3801 emit_insn (gen_vxworks_load_got ());
3804 /* The GOT symbol is subject to a PC-relative relocation so we need a
3805 helper function to add the PC value and thus get the final value. */
3806 if (!got_helper_rtx
)
3809 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
3810 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3813 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
3815 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
3818 /* Need to emit this whether or not we obey regdecls,
3819 since setjmp/longjmp can cause life info to screw up.
3820 ??? In the case where we don't obey regdecls, this is not sufficient
3821 since we may not fall out the bottom. */
3822 emit_use (global_offset_table_rtx
);
3825 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3826 address of the call target. */
3829 sparc_emit_call_insn (rtx pat
, rtx addr
)
3833 insn
= emit_call_insn (pat
);
3835 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3836 if (TARGET_VXWORKS_RTP
3838 && GET_CODE (addr
) == SYMBOL_REF
3839 && (SYMBOL_REF_DECL (addr
)
3840 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
3841 : !SYMBOL_REF_LOCAL_P (addr
)))
3843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3844 crtl
->uses_pic_offset_table
= 1;
3848 /* Return 1 if RTX is a MEM which is known to be aligned to at
3849 least a DESIRED byte boundary. */
3852 mem_min_alignment (rtx mem
, int desired
)
3854 rtx addr
, base
, offset
;
3856 /* If it's not a MEM we can't accept it. */
3857 if (GET_CODE (mem
) != MEM
)
3861 if (!TARGET_UNALIGNED_DOUBLES
3862 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3865 /* ??? The rest of the function predates MEM_ALIGN so
3866 there is probably a bit of redundancy. */
3867 addr
= XEXP (mem
, 0);
3868 base
= offset
= NULL_RTX
;
3869 if (GET_CODE (addr
) == PLUS
)
3871 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3873 base
= XEXP (addr
, 0);
3875 /* What we are saying here is that if the base
3876 REG is aligned properly, the compiler will make
3877 sure any REG based index upon it will be so
3879 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3880 offset
= XEXP (addr
, 1);
3882 offset
= const0_rtx
;
3885 else if (GET_CODE (addr
) == REG
)
3888 offset
= const0_rtx
;
3891 if (base
!= NULL_RTX
)
3893 int regno
= REGNO (base
);
3895 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3897 /* Check if the compiler has recorded some information
3898 about the alignment of the base REG. If reload has
3899 completed, we already matched with proper alignments.
3900 If not running global_alloc, reload might give us
3901 unaligned pointer to local stack though. */
3903 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3904 || (optimize
&& reload_completed
))
3905 && (INTVAL (offset
) & (desired
- 1)) == 0)
3910 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3914 else if (! TARGET_UNALIGNED_DOUBLES
3915 || CONSTANT_P (addr
)
3916 || GET_CODE (addr
) == LO_SUM
)
3918 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3919 is true, in which case we can only assume that an access is aligned if
3920 it is to a constant address, or the address involves a LO_SUM. */
3924 /* An obviously unaligned address. */
3929 /* Vectors to keep interesting information about registers where it can easily
3930 be got. We used to use the actual mode value as the bit number, but there
3931 are more than 32 modes now. Instead we use two tables: one indexed by
3932 hard register number, and one indexed by mode. */
3934 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3935 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
3936 mapped into one sparc_mode_class mode. */
3938 enum sparc_mode_class
{
3939 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3940 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3944 /* Modes for single-word and smaller quantities. */
3945 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3947 /* Modes for double-word and smaller quantities. */
3948 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3950 /* Modes for quad-word and smaller quantities. */
3951 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3953 /* Modes for 8-word and smaller quantities. */
3954 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3956 /* Modes for single-float quantities. We must allow any single word or
3957 smaller quantity. This is because the fix/float conversion instructions
3958 take integer inputs/outputs from the float registers. */
3959 #define SF_MODES (S_MODES)
3961 /* Modes for double-float and smaller quantities. */
3962 #define DF_MODES (D_MODES)
3964 /* Modes for quad-float and smaller quantities. */
3965 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
3967 /* Modes for quad-float pairs and smaller quantities. */
3968 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
3970 /* Modes for double-float only quantities. */
3971 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3973 /* Modes for quad-float and double-float only quantities. */
3974 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
3976 /* Modes for quad-float pairs and double-float only quantities. */
3977 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
3979 /* Modes for condition codes. */
3980 #define CC_MODES (1 << (int) CC_MODE)
3981 #define CCFP_MODES (1 << (int) CCFP_MODE)
3983 /* Value is 1 if register/mode pair is acceptable on sparc.
3984 The funny mixture of D and T modes is because integer operations
3985 do not specially operate on tetra quantities, so non-quad-aligned
3986 registers can hold quadword quantities (except %o4 and %i4 because
3987 they cross fixed registers). */
3989 /* This points to either the 32 bit or the 64 bit version. */
3990 const int *hard_regno_mode_classes
;
3992 static const int hard_32bit_mode_classes
[] = {
3993 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3994 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3995 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3996 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3998 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3999 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4000 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4001 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4003 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4004 and none can hold SFmode/SImode values. */
4005 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4006 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4007 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4008 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4011 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4017 static const int hard_64bit_mode_classes
[] = {
4018 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4019 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4020 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4021 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4023 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4024 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4025 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4026 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4028 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4029 and none can hold SFmode/SImode values. */
4030 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4031 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4032 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4033 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4036 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4042 int sparc_mode_class
[NUM_MACHINE_MODES
];
4044 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4047 sparc_init_modes (void)
4051 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4053 switch (GET_MODE_CLASS (i
))
4056 case MODE_PARTIAL_INT
:
4057 case MODE_COMPLEX_INT
:
4058 if (GET_MODE_SIZE (i
) <= 4)
4059 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4060 else if (GET_MODE_SIZE (i
) == 8)
4061 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4062 else if (GET_MODE_SIZE (i
) == 16)
4063 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4064 else if (GET_MODE_SIZE (i
) == 32)
4065 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4067 sparc_mode_class
[i
] = 0;
4069 case MODE_VECTOR_INT
:
4070 if (GET_MODE_SIZE (i
) <= 4)
4071 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4072 else if (GET_MODE_SIZE (i
) == 8)
4073 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4076 case MODE_COMPLEX_FLOAT
:
4077 if (GET_MODE_SIZE (i
) <= 4)
4078 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4079 else if (GET_MODE_SIZE (i
) == 8)
4080 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4081 else if (GET_MODE_SIZE (i
) == 16)
4082 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4083 else if (GET_MODE_SIZE (i
) == 32)
4084 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4086 sparc_mode_class
[i
] = 0;
4089 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4090 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4092 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4095 sparc_mode_class
[i
] = 0;
4101 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4103 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4105 /* Initialize the array used by REGNO_REG_CLASS. */
4106 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4108 if (i
< 16 && TARGET_V8PLUS
)
4109 sparc_regno_reg_class
[i
] = I64_REGS
;
4110 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4111 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4113 sparc_regno_reg_class
[i
] = FP_REGS
;
4115 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4117 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4119 sparc_regno_reg_class
[i
] = NO_REGS
;
4123 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4126 save_global_or_fp_reg_p (unsigned int regno
,
4127 int leaf_function ATTRIBUTE_UNUSED
)
4129 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4132 /* Return whether the return address register (%i7) is needed. */
4135 return_addr_reg_needed_p (int leaf_function
)
4137 /* If it is live, for example because of __builtin_return_address (0). */
4138 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4141 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4143 /* Loading the GOT register clobbers %o7. */
4144 || crtl
->uses_pic_offset_table
4145 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4151 /* Return whether REGNO, a local or in register, must be saved/restored. */
4154 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4156 /* General case: call-saved registers live at some point. */
4157 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4160 /* Frame pointer register (%fp) if needed. */
4161 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4164 /* Return address register (%i7) if needed. */
4165 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4168 /* GOT register (%l7) if needed. */
4169 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4172 /* If the function accesses prior frames, the frame pointer and the return
4173 address of the previous frame must be saved on the stack. */
4174 if (crtl
->accesses_prior_frames
4175 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4181 /* Compute the frame size required by the function. This function is called
4182 during the reload pass and also by sparc_expand_prologue. */
4185 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4187 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4188 int args_size
, n_global_fp_regs
= 0;
4189 bool save_local_in_regs_p
= false;
4192 /* If the function allocates dynamic stack space, the dynamic offset is
4193 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4194 if (leaf_function
&& !cfun
->calls_alloca
)
4197 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4199 /* Calculate space needed for global registers. */
4201 for (i
= 0; i
< 8; i
++)
4202 if (save_global_or_fp_reg_p (i
, 0))
4203 n_global_fp_regs
+= 2;
4205 for (i
= 0; i
< 8; i
+= 2)
4206 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4207 n_global_fp_regs
+= 2;
4209 /* In the flat window model, find out which local and in registers need to
4210 be saved. We don't reserve space in the current frame for them as they
4211 will be spilled into the register window save area of the caller's frame.
4212 However, as soon as we use this register window save area, we must create
4213 that of the current frame to make it the live one. */
4215 for (i
= 16; i
< 32; i
++)
4216 if (save_local_or_in_reg_p (i
, leaf_function
))
4218 save_local_in_regs_p
= true;
4222 /* Calculate space needed for FP registers. */
4223 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4224 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4225 n_global_fp_regs
+= 2;
4228 && n_global_fp_regs
== 0
4230 && !save_local_in_regs_p
)
4231 frame_size
= apparent_frame_size
= 0;
4234 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4235 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4236 apparent_frame_size
+= n_global_fp_regs
* 4;
4238 /* We need to add the size of the outgoing argument area. */
4239 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4241 /* And that of the register window save area. */
4242 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4244 /* Finally, bump to the appropriate alignment. */
4245 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4248 /* Set up values for use in prologue and epilogue. */
4249 sparc_frame_size
= frame_size
;
4250 sparc_apparent_frame_size
= apparent_frame_size
;
4251 sparc_n_global_fp_regs
= n_global_fp_regs
;
4252 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4257 /* Output any necessary .register pseudo-ops. */
4260 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4262 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4268 /* Check if %g[2367] were used without
4269 .register being printed for them already. */
4270 for (i
= 2; i
< 8; i
++)
4272 if (df_regs_ever_live_p (i
)
4273 && ! sparc_hard_reg_printed
[i
])
4275 sparc_hard_reg_printed
[i
] = 1;
4276 /* %g7 is used as TLS base register, use #ignore
4277 for it instead of #scratch. */
4278 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4279 i
== 7 ? "ignore" : "scratch");
4286 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4288 #if PROBE_INTERVAL > 4096
4289 #error Cannot use indexed addressing mode for stack probing
4292 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4293 inclusive. These are offsets from the current stack pointer.
4295 Note that we don't use the REG+REG addressing mode for the probes because
4296 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4297 so the advantages of having a single code win here. */
4300 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4302 rtx g1
= gen_rtx_REG (Pmode
, 1);
4304 /* See if we have a constant small number of probes to generate. If so,
4305 that's the easy case. */
4306 if (size
<= PROBE_INTERVAL
)
4308 emit_move_insn (g1
, GEN_INT (first
));
4309 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4310 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4311 emit_stack_probe (plus_constant (g1
, -size
));
4314 /* The run-time loop is made up of 10 insns in the generic case while the
4315 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4316 else if (size
<= 5 * PROBE_INTERVAL
)
4320 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4321 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4322 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4323 emit_stack_probe (g1
);
4325 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4326 it exceeds SIZE. If only two probes are needed, this will not
4327 generate any code. Then probe at FIRST + SIZE. */
4328 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4330 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4331 plus_constant (g1
, -PROBE_INTERVAL
)));
4332 emit_stack_probe (g1
);
4335 emit_stack_probe (plus_constant (g1
, (i
- PROBE_INTERVAL
) - size
));
4338 /* Otherwise, do the same as above, but in a loop. Note that we must be
4339 extra careful with variables wrapping around because we might be at
4340 the very top (or the very bottom) of the address space and we have
4341 to be able to handle this case properly; in particular, we use an
4342 equality test for the loop condition. */
4345 HOST_WIDE_INT rounded_size
;
4346 rtx g4
= gen_rtx_REG (Pmode
, 4);
4348 emit_move_insn (g1
, GEN_INT (first
));
4351 /* Step 1: round SIZE to the previous multiple of the interval. */
4353 rounded_size
= size
& -PROBE_INTERVAL
;
4354 emit_move_insn (g4
, GEN_INT (rounded_size
));
4357 /* Step 2: compute initial and final value of the loop counter. */
4359 /* TEST_ADDR = SP + FIRST. */
4360 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4361 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4363 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4364 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4369 while (TEST_ADDR != LAST_ADDR)
4371 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4375 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4376 until it is equal to ROUNDED_SIZE. */
4379 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4381 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4384 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4385 that SIZE is equal to ROUNDED_SIZE. */
4387 if (size
!= rounded_size
)
4388 emit_stack_probe (plus_constant (g4
, rounded_size
- size
));
4391 /* Make sure nothing is scheduled before we are done. */
4392 emit_insn (gen_blockage ());
4395 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4396 absolute addresses. */
4399 output_probe_stack_range (rtx reg1
, rtx reg2
)
4401 static int labelno
= 0;
4402 char loop_lab
[32], end_lab
[32];
4405 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4406 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4408 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4410 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4413 output_asm_insn ("cmp\t%0, %1", xops
);
4415 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4417 fputs ("\tbe\t", asm_out_file
);
4418 assemble_name_raw (asm_out_file
, end_lab
);
4419 fputc ('\n', asm_out_file
);
4421 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4422 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4423 output_asm_insn (" add\t%0, %1, %0", xops
);
4425 /* Probe at TEST_ADDR and branch. */
4427 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4429 fputs ("\tba\t", asm_out_file
);
4430 assemble_name_raw (asm_out_file
, loop_lab
);
4431 fputc ('\n', asm_out_file
);
4432 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4433 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4435 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4440 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4441 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4442 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4443 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4444 the action to be performed if it returns false. Return the new offset. */
4446 typedef bool (*sorr_pred_t
) (unsigned int, int);
4447 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4450 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4451 int offset
, int leaf_function
, sorr_pred_t save_p
,
4452 sorr_act_t action_true
, sorr_act_t action_false
)
4457 if (TARGET_ARCH64
&& high
<= 32)
4461 for (i
= low
; i
< high
; i
++)
4463 if (save_p (i
, leaf_function
))
4465 mem
= gen_frame_mem (DImode
, plus_constant (base
, offset
));
4466 if (action_true
== SORR_SAVE
)
4468 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4469 RTX_FRAME_RELATED_P (insn
) = 1;
4471 else /* action_true == SORR_RESTORE */
4473 /* The frame pointer must be restored last since its old
4474 value may be used as base address for the frame. This
4475 is problematic in 64-bit mode only because of the lack
4476 of double-word load instruction. */
4477 if (i
== HARD_FRAME_POINTER_REGNUM
)
4480 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4484 else if (action_false
== SORR_ADVANCE
)
4490 mem
= gen_frame_mem (DImode
, plus_constant (base
, fp_offset
));
4491 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4496 for (i
= low
; i
< high
; i
+= 2)
4498 bool reg0
= save_p (i
, leaf_function
);
4499 bool reg1
= save_p (i
+ 1, leaf_function
);
4500 enum machine_mode mode
;
4505 mode
= i
< 32 ? DImode
: DFmode
;
4510 mode
= i
< 32 ? SImode
: SFmode
;
4515 mode
= i
< 32 ? SImode
: SFmode
;
4521 if (action_false
== SORR_ADVANCE
)
4526 mem
= gen_frame_mem (mode
, plus_constant (base
, offset
));
4527 if (action_true
== SORR_SAVE
)
4529 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4530 RTX_FRAME_RELATED_P (insn
) = 1;
4534 mem
= gen_frame_mem (SImode
, plus_constant (base
, offset
));
4535 set1
= gen_rtx_SET (VOIDmode
, mem
,
4536 gen_rtx_REG (SImode
, regno
));
4537 RTX_FRAME_RELATED_P (set1
) = 1;
4539 = gen_frame_mem (SImode
, plus_constant (base
, offset
+ 4));
4540 set2
= gen_rtx_SET (VOIDmode
, mem
,
4541 gen_rtx_REG (SImode
, regno
+ 1));
4542 RTX_FRAME_RELATED_P (set2
) = 1;
4543 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4544 gen_rtx_PARALLEL (VOIDmode
,
4545 gen_rtvec (2, set1
, set2
)));
4548 else /* action_true == SORR_RESTORE */
4549 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4551 /* Always preserve double-word alignment. */
4552 offset
= (offset
+ 8) & -8;
4559 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4562 emit_adjust_base_to_offset (rtx base
, int offset
)
4564 /* ??? This might be optimized a little as %g1 might already have a
4565 value close enough that a single add insn will do. */
4566 /* ??? Although, all of this is probably only a temporary fix because
4567 if %g1 can hold a function result, then sparc_expand_epilogue will
4568 lose (the result will be clobbered). */
4569 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4570 emit_move_insn (new_base
, GEN_INT (offset
));
4571 emit_insn (gen_rtx_SET (VOIDmode
,
4572 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4576 /* Emit code to save/restore call-saved global and FP registers. */
4579 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4581 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4583 base
= emit_adjust_base_to_offset (base
, offset
);
4588 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4589 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4590 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4591 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4594 /* Emit code to save/restore call-saved local and in registers. */
4597 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
4599 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
4601 base
= emit_adjust_base_to_offset (base
, offset
);
4605 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
4606 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
4609 /* Emit a window_save insn. */
4612 emit_window_save (rtx increment
)
4614 rtx insn
= emit_insn (gen_window_save (increment
));
4615 RTX_FRAME_RELATED_P (insn
) = 1;
4617 /* The incoming return address (%o7) is saved in %i7. */
4618 add_reg_note (insn
, REG_CFA_REGISTER
,
4619 gen_rtx_SET (VOIDmode
,
4620 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
4622 INCOMING_RETURN_ADDR_REGNUM
)));
4624 /* The window save event. */
4625 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
4627 /* The CFA is %fp, the hard frame pointer. */
4628 add_reg_note (insn
, REG_CFA_DEF_CFA
,
4629 plus_constant (hard_frame_pointer_rtx
,
4630 INCOMING_FRAME_SP_OFFSET
));
4635 /* Generate an increment for the stack pointer. */
4638 gen_stack_pointer_inc (rtx increment
)
4640 return gen_rtx_SET (VOIDmode
,
4642 gen_rtx_PLUS (Pmode
,
4647 /* Generate a decrement for the stack pointer. */
4650 gen_stack_pointer_dec (rtx decrement
)
4652 return gen_rtx_SET (VOIDmode
,
4654 gen_rtx_MINUS (Pmode
,
4659 /* Expand the function prologue. The prologue is responsible for reserving
4660 storage for the frame, saving the call-saved registers and loading the
4661 GOT register if needed. */
4664 sparc_expand_prologue (void)
4669 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4670 on the final value of the flag means deferring the prologue/epilogue
4671 expansion until just before the second scheduling pass, which is too
4672 late to emit multiple epilogues or return insns.
4674 Of course we are making the assumption that the value of the flag
4675 will not change between now and its final value. Of the three parts
4676 of the formula, only the last one can reasonably vary. Let's take a
4677 closer look, after assuming that the first two ones are set to true
4678 (otherwise the last value is effectively silenced).
4680 If only_leaf_regs_used returns false, the global predicate will also
4681 be false so the actual frame size calculated below will be positive.
4682 As a consequence, the save_register_window insn will be emitted in
4683 the instruction stream; now this insn explicitly references %fp
4684 which is not a leaf register so only_leaf_regs_used will always
4685 return false subsequently.
4687 If only_leaf_regs_used returns true, we hope that the subsequent
4688 optimization passes won't cause non-leaf registers to pop up. For
4689 example, the regrename pass has special provisions to not rename to
4690 non-leaf registers in a leaf function. */
4691 sparc_leaf_function_p
4692 = optimize
> 0 && current_function_is_leaf
&& only_leaf_regs_used ();
4694 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4696 if (flag_stack_usage_info
)
4697 current_function_static_stack_size
= size
;
4699 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4700 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4704 else if (sparc_leaf_function_p
)
4706 rtx size_int_rtx
= GEN_INT (-size
);
4709 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4710 else if (size
<= 8192)
4712 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4713 /* %sp is still the CFA register. */
4714 RTX_FRAME_RELATED_P (insn
) = 1;
4715 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4719 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4720 emit_move_insn (size_rtx
, size_int_rtx
);
4721 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4722 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4723 gen_stack_pointer_inc (size_int_rtx
));
4726 RTX_FRAME_RELATED_P (insn
) = 1;
4730 rtx size_int_rtx
= GEN_INT (-size
);
4733 emit_window_save (size_int_rtx
);
4734 else if (size
<= 8192)
4736 emit_window_save (GEN_INT (-4096));
4737 /* %sp is not the CFA register anymore. */
4738 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4742 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4743 emit_move_insn (size_rtx
, size_int_rtx
);
4744 emit_window_save (size_rtx
);
4748 if (sparc_leaf_function_p
)
4750 sparc_frame_base_reg
= stack_pointer_rtx
;
4751 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4755 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4756 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4759 if (sparc_n_global_fp_regs
> 0)
4760 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4761 sparc_frame_base_offset
4762 - sparc_apparent_frame_size
,
4765 /* Load the GOT register if needed. */
4766 if (crtl
->uses_pic_offset_table
)
4767 load_got_register ();
4769 /* Advertise that the data calculated just above are now valid. */
4770 sparc_prologue_data_valid_p
= true;
4773 /* Expand the function prologue. The prologue is responsible for reserving
4774 storage for the frame, saving the call-saved registers and loading the
4775 GOT register if needed. */
4778 sparc_flat_expand_prologue (void)
4783 sparc_leaf_function_p
= optimize
> 0 && current_function_is_leaf
;
4785 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4787 if (flag_stack_usage_info
)
4788 current_function_static_stack_size
= size
;
4790 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4791 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4793 if (sparc_save_local_in_regs_p
)
4794 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
4801 rtx size_int_rtx
, size_rtx
;
4803 size_rtx
= size_int_rtx
= GEN_INT (-size
);
4805 /* We establish the frame (i.e. decrement the stack pointer) first, even
4806 if we use a frame pointer, because we cannot clobber any call-saved
4807 registers, including the frame pointer, if we haven't created a new
4808 register save area, for the sake of compatibility with the ABI. */
4810 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4811 else if (size
<= 8192 && !frame_pointer_needed
)
4813 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4814 RTX_FRAME_RELATED_P (insn
) = 1;
4815 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4819 size_rtx
= gen_rtx_REG (Pmode
, 1);
4820 emit_move_insn (size_rtx
, size_int_rtx
);
4821 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4822 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4823 gen_stack_pointer_inc (size_int_rtx
));
4825 RTX_FRAME_RELATED_P (insn
) = 1;
4827 /* Ensure nothing is scheduled until after the frame is established. */
4828 emit_insn (gen_blockage ());
4830 if (frame_pointer_needed
)
4832 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4833 gen_rtx_MINUS (Pmode
,
4836 RTX_FRAME_RELATED_P (insn
) = 1;
4838 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4839 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4840 plus_constant (stack_pointer_rtx
,
4844 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4846 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
4847 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4849 insn
= emit_move_insn (i7
, o7
);
4850 RTX_FRAME_RELATED_P (insn
) = 1;
4852 add_reg_note (insn
, REG_CFA_REGISTER
,
4853 gen_rtx_SET (VOIDmode
, i7
, o7
));
4855 /* Prevent this instruction from ever being considered dead,
4856 even if this function has no epilogue. */
4857 emit_insn (gen_rtx_USE (VOIDmode
, i7
));
4861 if (frame_pointer_needed
)
4863 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4864 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4868 sparc_frame_base_reg
= stack_pointer_rtx
;
4869 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4872 if (sparc_n_global_fp_regs
> 0)
4873 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4874 sparc_frame_base_offset
4875 - sparc_apparent_frame_size
,
4878 /* Load the GOT register if needed. */
4879 if (crtl
->uses_pic_offset_table
)
4880 load_got_register ();
4882 /* Advertise that the data calculated just above are now valid. */
4883 sparc_prologue_data_valid_p
= true;
4886 /* This function generates the assembly code for function entry, which boils
4887 down to emitting the necessary .register directives. */
4890 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4892 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4894 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
4896 sparc_output_scratch_registers (file
);
4899 /* Expand the function epilogue, either normal or part of a sibcall.
4900 We emit all the instructions except the return or the call. */
4903 sparc_expand_epilogue (bool for_eh
)
4905 HOST_WIDE_INT size
= sparc_frame_size
;
4907 if (sparc_n_global_fp_regs
> 0)
4908 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4909 sparc_frame_base_offset
4910 - sparc_apparent_frame_size
,
4913 if (size
== 0 || for_eh
)
4915 else if (sparc_leaf_function_p
)
4918 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
4919 else if (size
<= 8192)
4921 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4922 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
4926 rtx reg
= gen_rtx_REG (Pmode
, 1);
4927 emit_move_insn (reg
, GEN_INT (-size
));
4928 emit_insn (gen_stack_pointer_dec (reg
));
4933 /* Expand the function epilogue, either normal or part of a sibcall.
4934 We emit all the instructions except the return or the call. */
4937 sparc_flat_expand_epilogue (bool for_eh
)
4939 HOST_WIDE_INT size
= sparc_frame_size
;
4941 if (sparc_n_global_fp_regs
> 0)
4942 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4943 sparc_frame_base_offset
4944 - sparc_apparent_frame_size
,
4947 /* If we have a frame pointer, we'll need both to restore it before the
4948 frame is destroyed and use its current value in destroying the frame.
4949 Since we don't have an atomic way to do that in the flat window model,
4950 we save the current value into a temporary register (%g1). */
4951 if (frame_pointer_needed
&& !for_eh
)
4952 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
4954 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4955 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
4956 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
4958 if (sparc_save_local_in_regs_p
)
4959 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
4960 sparc_frame_base_offset
,
4963 if (size
== 0 || for_eh
)
4965 else if (frame_pointer_needed
)
4967 /* Make sure the frame is destroyed after everything else is done. */
4968 emit_insn (gen_blockage ());
4970 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
4975 emit_insn (gen_blockage ());
4978 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
4979 else if (size
<= 8192)
4981 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4982 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
4986 rtx reg
= gen_rtx_REG (Pmode
, 1);
4987 emit_move_insn (reg
, GEN_INT (-size
));
4988 emit_insn (gen_stack_pointer_dec (reg
));
4993 /* Return true if it is appropriate to emit `return' instructions in the
4994 body of a function. */
4997 sparc_can_use_return_insn_p (void)
4999 return sparc_prologue_data_valid_p
5000 && sparc_n_global_fp_regs
== 0
5002 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5003 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5006 /* This function generates the assembly code for function exit. */
5009 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5011 /* If the last two instructions of a function are "call foo; dslot;"
5012 the return address might point to the first instruction in the next
5013 function and we have to output a dummy nop for the sake of sane
5014 backtraces in such cases. This is pointless for sibling calls since
5015 the return address is explicitly adjusted. */
5017 rtx insn
, last_real_insn
;
5019 insn
= get_last_insn ();
5021 last_real_insn
= prev_real_insn (insn
);
5023 && GET_CODE (last_real_insn
) == INSN
5024 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5025 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5028 && CALL_P (last_real_insn
)
5029 && !SIBLING_CALL_P (last_real_insn
))
5030 fputs("\tnop\n", file
);
5032 sparc_output_deferred_case_vectors ();
5035 /* Output a 'restore' instruction. */
5038 output_restore (rtx pat
)
5044 fputs ("\t restore\n", asm_out_file
);
5048 gcc_assert (GET_CODE (pat
) == SET
);
5050 operands
[0] = SET_DEST (pat
);
5051 pat
= SET_SRC (pat
);
5053 switch (GET_CODE (pat
))
5056 operands
[1] = XEXP (pat
, 0);
5057 operands
[2] = XEXP (pat
, 1);
5058 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5061 operands
[1] = XEXP (pat
, 0);
5062 operands
[2] = XEXP (pat
, 1);
5063 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5066 operands
[1] = XEXP (pat
, 0);
5067 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5068 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5072 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5077 /* Output a return. */
5080 output_return (rtx insn
)
5082 if (crtl
->calls_eh_return
)
5084 /* If the function uses __builtin_eh_return, the eh_return
5085 machinery occupies the delay slot. */
5086 gcc_assert (!final_sequence
);
5088 if (flag_delayed_branch
)
5090 if (!TARGET_FLAT
&& TARGET_V9
)
5091 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5095 fputs ("\trestore\n", asm_out_file
);
5097 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5100 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5105 fputs ("\trestore\n", asm_out_file
);
5107 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5108 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5111 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5113 /* This is a leaf or flat function so we don't have to bother restoring
5114 the register window, which frees us from dealing with the convoluted
5115 semantics of restore/return. We simply output the jump to the
5116 return address and the insn in the delay slot (if any). */
5118 return "jmp\t%%o7+%)%#";
5122 /* This is a regular function so we have to restore the register window.
5123 We may have a pending insn for the delay slot, which will be either
5124 combined with the 'restore' instruction or put in the delay slot of
5125 the 'return' instruction. */
5131 delay
= NEXT_INSN (insn
);
5134 pat
= PATTERN (delay
);
5136 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5138 epilogue_renumber (&pat
, 0);
5139 return "return\t%%i7+%)%#";
5143 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5144 output_restore (pat
);
5145 PATTERN (delay
) = gen_blockage ();
5146 INSN_CODE (delay
) = -1;
5151 /* The delay slot is empty. */
5153 return "return\t%%i7+%)\n\t nop";
5154 else if (flag_delayed_branch
)
5155 return "jmp\t%%i7+%)\n\t restore";
5157 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5164 /* Output a sibling call. */
5167 output_sibcall (rtx insn
, rtx call_operand
)
5171 gcc_assert (flag_delayed_branch
);
5173 operands
[0] = call_operand
;
5175 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5177 /* This is a leaf or flat function so we don't have to bother restoring
5178 the register window. We simply output the jump to the function and
5179 the insn in the delay slot (if any). */
5181 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5184 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5187 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5188 it into branch if possible. */
5189 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5194 /* This is a regular function so we have to restore the register window.
5195 We may have a pending insn for the delay slot, which will be combined
5196 with the 'restore' instruction. */
5198 output_asm_insn ("call\t%a0, 0", operands
);
5202 rtx delay
= NEXT_INSN (insn
);
5205 output_restore (PATTERN (delay
));
5207 PATTERN (delay
) = gen_blockage ();
5208 INSN_CODE (delay
) = -1;
5211 output_restore (NULL_RTX
);
5217 /* Functions for handling argument passing.
5219 For 32-bit, the first 6 args are normally in registers and the rest are
5220 pushed. Any arg that starts within the first 6 words is at least
5221 partially passed in a register unless its data type forbids.
5223 For 64-bit, the argument registers are laid out as an array of 16 elements
5224 and arguments are added sequentially. The first 6 int args and up to the
5225 first 16 fp args (depending on size) are passed in regs.
5227 Slot Stack Integral Float Float in structure Double Long Double
5228 ---- ----- -------- ----- ------------------ ------ -----------
5229 15 [SP+248] %f31 %f30,%f31 %d30
5230 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5231 13 [SP+232] %f27 %f26,%f27 %d26
5232 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5233 11 [SP+216] %f23 %f22,%f23 %d22
5234 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5235 9 [SP+200] %f19 %f18,%f19 %d18
5236 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5237 7 [SP+184] %f15 %f14,%f15 %d14
5238 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5239 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5240 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5241 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5242 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5243 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5244 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5246 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5248 Integral arguments are always passed as 64-bit quantities appropriately
5251 Passing of floating point values is handled as follows.
5252 If a prototype is in scope:
5253 If the value is in a named argument (i.e. not a stdarg function or a
5254 value not part of the `...') then the value is passed in the appropriate
5256 If the value is part of the `...' and is passed in one of the first 6
5257 slots then the value is passed in the appropriate int reg.
5258 If the value is part of the `...' and is not passed in one of the first 6
5259 slots then the value is passed in memory.
5260 If a prototype is not in scope:
5261 If the value is one of the first 6 arguments the value is passed in the
5262 appropriate integer reg and the appropriate fp reg.
5263 If the value is not one of the first 6 arguments the value is passed in
5264 the appropriate fp reg and in memory.
5267 Summary of the calling conventions implemented by GCC on the SPARC:
5270 size argument return value
5272 small integer <4 int. reg. int. reg.
5273 word 4 int. reg. int. reg.
5274 double word 8 int. reg. int. reg.
5276 _Complex small integer <8 int. reg. int. reg.
5277 _Complex word 8 int. reg. int. reg.
5278 _Complex double word 16 memory int. reg.
5280 vector integer <=8 int. reg. FP reg.
5281 vector integer >8 memory memory
5283 float 4 int. reg. FP reg.
5284 double 8 int. reg. FP reg.
5285 long double 16 memory memory
5287 _Complex float 8 memory FP reg.
5288 _Complex double 16 memory FP reg.
5289 _Complex long double 32 memory FP reg.
5291 vector float any memory memory
5293 aggregate any memory memory
5298 size argument return value
5300 small integer <8 int. reg. int. reg.
5301 word 8 int. reg. int. reg.
5302 double word 16 int. reg. int. reg.
5304 _Complex small integer <16 int. reg. int. reg.
5305 _Complex word 16 int. reg. int. reg.
5306 _Complex double word 32 memory int. reg.
5308 vector integer <=16 FP reg. FP reg.
5309 vector integer 16<s<=32 memory FP reg.
5310 vector integer >32 memory memory
5312 float 4 FP reg. FP reg.
5313 double 8 FP reg. FP reg.
5314 long double 16 FP reg. FP reg.
5316 _Complex float 8 FP reg. FP reg.
5317 _Complex double 16 FP reg. FP reg.
5318 _Complex long double 32 memory FP reg.
5320 vector float <=16 FP reg. FP reg.
5321 vector float 16<s<=32 memory FP reg.
5322 vector float >32 memory memory
5324 aggregate <=16 reg. reg.
5325 aggregate 16<s<=32 memory reg.
5326 aggregate >32 memory memory
5330 Note #1: complex floating-point types follow the extended SPARC ABIs as
5331 implemented by the Sun compiler.
5333 Note #2: integral vector types follow the scalar floating-point types
5334 conventions to match what is implemented by the Sun VIS SDK.
5336 Note #3: floating-point vector types follow the aggregate types
5340 /* Maximum number of int regs for args. */
5341 #define SPARC_INT_ARG_MAX 6
5342 /* Maximum number of fp regs for args. */
5343 #define SPARC_FP_ARG_MAX 16
5345 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5347 /* Handle the INIT_CUMULATIVE_ARGS macro.
5348 Initialize a variable CUM of type CUMULATIVE_ARGS
5349 for a call to a function whose data type is FNTYPE.
5350 For a library call, FNTYPE is 0. */
5353 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5354 rtx libname ATTRIBUTE_UNUSED
,
5355 tree fndecl ATTRIBUTE_UNUSED
)
5358 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5359 cum
->libcall_p
= fntype
== 0;
5362 /* Handle promotion of pointer and integer arguments. */
5364 static enum machine_mode
5365 sparc_promote_function_mode (const_tree type
,
5366 enum machine_mode mode
,
5368 const_tree fntype ATTRIBUTE_UNUSED
,
5369 int for_return ATTRIBUTE_UNUSED
)
5371 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5373 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5377 /* Integral arguments are passed as full words, as per the ABI. */
5378 if (GET_MODE_CLASS (mode
) == MODE_INT
5379 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5385 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5388 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5390 return TARGET_ARCH64
? true : false;
5393 /* Scan the record type TYPE and return the following predicates:
5394 - INTREGS_P: the record contains at least one field or sub-field
5395 that is eligible for promotion in integer registers.
5396 - FP_REGS_P: the record contains at least one field or sub-field
5397 that is eligible for promotion in floating-point registers.
5398 - PACKED_P: the record contains at least one field that is packed.
5400 Sub-fields are not taken into account for the PACKED_P predicate. */
5403 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5408 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5410 if (TREE_CODE (field
) == FIELD_DECL
)
5412 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5413 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5414 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5415 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5421 if (packed_p
&& DECL_PACKED (field
))
5427 /* Compute the slot number to pass an argument in.
5428 Return the slot number or -1 if passing on the stack.
5430 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5431 the preceding args and about the function being called.
5432 MODE is the argument's machine mode.
5433 TYPE is the data type of the argument (as a tree).
5434 This is null for libcalls where that information may
5436 NAMED is nonzero if this argument is a named parameter
5437 (otherwise it is an extra parameter matching an ellipsis).
5438 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5439 *PREGNO records the register number to use if scalar type.
5440 *PPADDING records the amount of padding needed in words. */
5443 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5444 const_tree type
, bool named
, bool incoming_p
,
5445 int *pregno
, int *ppadding
)
5447 int regbase
= (incoming_p
5448 ? SPARC_INCOMING_INT_ARG_FIRST
5449 : SPARC_OUTGOING_INT_ARG_FIRST
);
5450 int slotno
= cum
->words
;
5451 enum mode_class mclass
;
5456 if (type
&& TREE_ADDRESSABLE (type
))
5462 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5465 /* For SPARC64, objects requiring 16-byte alignment get it. */
5467 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5468 && (slotno
& 1) != 0)
5469 slotno
++, *ppadding
= 1;
5471 mclass
= GET_MODE_CLASS (mode
);
5472 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5474 /* Vector types deserve special treatment because they are
5475 polymorphic wrt their mode, depending upon whether VIS
5476 instructions are enabled. */
5477 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5479 /* The SPARC port defines no floating-point vector modes. */
5480 gcc_assert (mode
== BLKmode
);
5484 /* Integral vector types should either have a vector
5485 mode or an integral mode, because we are guaranteed
5486 by pass_by_reference that their size is not greater
5487 than 16 bytes and TImode is 16-byte wide. */
5488 gcc_assert (mode
!= BLKmode
);
5490 /* Vector integers are handled like floats according to
5492 mclass
= MODE_FLOAT
;
5499 case MODE_COMPLEX_FLOAT
:
5500 case MODE_VECTOR_INT
:
5501 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5503 if (slotno
>= SPARC_FP_ARG_MAX
)
5505 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5506 /* Arguments filling only one single FP register are
5507 right-justified in the outer double FP register. */
5508 if (GET_MODE_SIZE (mode
) <= 4)
5515 case MODE_COMPLEX_INT
:
5516 if (slotno
>= SPARC_INT_ARG_MAX
)
5518 regno
= regbase
+ slotno
;
5522 if (mode
== VOIDmode
)
5523 /* MODE is VOIDmode when generating the actual call. */
5526 gcc_assert (mode
== BLKmode
);
5530 || (TREE_CODE (type
) != VECTOR_TYPE
5531 && TREE_CODE (type
) != RECORD_TYPE
))
5533 if (slotno
>= SPARC_INT_ARG_MAX
)
5535 regno
= regbase
+ slotno
;
5537 else /* TARGET_ARCH64 && type */
5539 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5541 /* First see what kinds of registers we would need. */
5542 if (TREE_CODE (type
) == VECTOR_TYPE
)
5545 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5547 /* The ABI obviously doesn't specify how packed structures
5548 are passed. These are defined to be passed in int regs
5549 if possible, otherwise memory. */
5550 if (packed_p
|| !named
)
5551 fpregs_p
= 0, intregs_p
= 1;
5553 /* If all arg slots are filled, then must pass on stack. */
5554 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5557 /* If there are only int args and all int arg slots are filled,
5558 then must pass on stack. */
5559 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5562 /* Note that even if all int arg slots are filled, fp members may
5563 still be passed in regs if such regs are available.
5564 *PREGNO isn't set because there may be more than one, it's up
5565 to the caller to compute them. */
5578 /* Handle recursive register counting for structure field layout. */
5580 struct function_arg_record_value_parms
5582 rtx ret
; /* return expression being built. */
5583 int slotno
; /* slot number of the argument. */
5584 int named
; /* whether the argument is named. */
5585 int regbase
; /* regno of the base register. */
5586 int stack
; /* 1 if part of the argument is on the stack. */
5587 int intoffset
; /* offset of the first pending integer field. */
5588 unsigned int nregs
; /* number of words passed in registers. */
5591 static void function_arg_record_value_3
5592 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5593 static void function_arg_record_value_2
5594 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5595 static void function_arg_record_value_1
5596 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5597 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
5598 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5600 /* A subroutine of function_arg_record_value. Traverse the structure
5601 recursively and determine how many registers will be required. */
5604 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
5605 struct function_arg_record_value_parms
*parms
,
5610 /* We need to compute how many registers are needed so we can
5611 allocate the PARALLEL but before we can do that we need to know
5612 whether there are any packed fields. The ABI obviously doesn't
5613 specify how structures are passed in this case, so they are
5614 defined to be passed in int regs if possible, otherwise memory,
5615 regardless of whether there are fp values present. */
5618 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5620 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5627 /* Compute how many registers we need. */
5628 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5630 if (TREE_CODE (field
) == FIELD_DECL
)
5632 HOST_WIDE_INT bitpos
= startbitpos
;
5634 if (DECL_SIZE (field
) != 0)
5636 if (integer_zerop (DECL_SIZE (field
)))
5639 if (host_integerp (bit_position (field
), 1))
5640 bitpos
+= int_bit_position (field
);
5643 /* ??? FIXME: else assume zero offset. */
5645 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5646 function_arg_record_value_1 (TREE_TYPE (field
),
5650 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5651 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5656 if (parms
->intoffset
!= -1)
5658 unsigned int startbit
, endbit
;
5659 int intslots
, this_slotno
;
5661 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5662 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5664 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5665 this_slotno
= parms
->slotno
+ parms
->intoffset
5668 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5670 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5671 /* We need to pass this field on the stack. */
5675 parms
->nregs
+= intslots
;
5676 parms
->intoffset
= -1;
5679 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5680 If it wasn't true we wouldn't be here. */
5681 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5682 && DECL_MODE (field
) == BLKmode
)
5683 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5684 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5691 if (parms
->intoffset
== -1)
5692 parms
->intoffset
= bitpos
;
5698 /* A subroutine of function_arg_record_value. Assign the bits of the
5699 structure between parms->intoffset and bitpos to integer registers. */
5702 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5703 struct function_arg_record_value_parms
*parms
)
5705 enum machine_mode mode
;
5707 unsigned int startbit
, endbit
;
5708 int this_slotno
, intslots
, intoffset
;
5711 if (parms
->intoffset
== -1)
5714 intoffset
= parms
->intoffset
;
5715 parms
->intoffset
= -1;
5717 startbit
= intoffset
& -BITS_PER_WORD
;
5718 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5719 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5720 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5722 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5726 /* If this is the trailing part of a word, only load that much into
5727 the register. Otherwise load the whole register. Note that in
5728 the latter case we may pick up unwanted bits. It's not a problem
5729 at the moment but may wish to revisit. */
5731 if (intoffset
% BITS_PER_WORD
!= 0)
5732 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5737 intoffset
/= BITS_PER_UNIT
;
5740 regno
= parms
->regbase
+ this_slotno
;
5741 reg
= gen_rtx_REG (mode
, regno
);
5742 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5743 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5746 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5751 while (intslots
> 0);
5754 /* A subroutine of function_arg_record_value. Traverse the structure
5755 recursively and assign bits to floating point registers. Track which
5756 bits in between need integer registers; invoke function_arg_record_value_3
5757 to make that happen. */
5760 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5761 struct function_arg_record_value_parms
*parms
,
5767 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5769 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5776 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5778 if (TREE_CODE (field
) == FIELD_DECL
)
5780 HOST_WIDE_INT bitpos
= startbitpos
;
5782 if (DECL_SIZE (field
) != 0)
5784 if (integer_zerop (DECL_SIZE (field
)))
5787 if (host_integerp (bit_position (field
), 1))
5788 bitpos
+= int_bit_position (field
);
5791 /* ??? FIXME: else assume zero offset. */
5793 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5794 function_arg_record_value_2 (TREE_TYPE (field
),
5798 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5799 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5804 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5805 int regno
, nregs
, pos
;
5806 enum machine_mode mode
= DECL_MODE (field
);
5809 function_arg_record_value_3 (bitpos
, parms
);
5811 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5814 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5815 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5817 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5819 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5825 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5826 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5828 reg
= gen_rtx_REG (mode
, regno
);
5829 pos
= bitpos
/ BITS_PER_UNIT
;
5830 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5831 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5835 regno
+= GET_MODE_SIZE (mode
) / 4;
5836 reg
= gen_rtx_REG (mode
, regno
);
5837 pos
+= GET_MODE_SIZE (mode
);
5838 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5839 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5845 if (parms
->intoffset
== -1)
5846 parms
->intoffset
= bitpos
;
5852 /* Used by function_arg and sparc_function_value_1 to implement the complex
5853 conventions of the 64-bit ABI for passing and returning structures.
5854 Return an expression valid as a return value for the FUNCTION_ARG
5855 and TARGET_FUNCTION_VALUE.
5857 TYPE is the data type of the argument (as a tree).
5858 This is null for libcalls where that information may
5860 MODE is the argument's machine mode.
5861 SLOTNO is the index number of the argument's slot in the parameter array.
5862 NAMED is nonzero if this argument is a named parameter
5863 (otherwise it is an extra parameter matching an ellipsis).
5864 REGBASE is the regno of the base register for the parameter array. */
5867 function_arg_record_value (const_tree type
, enum machine_mode mode
,
5868 int slotno
, int named
, int regbase
)
5870 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5871 struct function_arg_record_value_parms parms
;
5874 parms
.ret
= NULL_RTX
;
5875 parms
.slotno
= slotno
;
5876 parms
.named
= named
;
5877 parms
.regbase
= regbase
;
5880 /* Compute how many registers we need. */
5882 parms
.intoffset
= 0;
5883 function_arg_record_value_1 (type
, 0, &parms
, false);
5885 /* Take into account pending integer fields. */
5886 if (parms
.intoffset
!= -1)
5888 unsigned int startbit
, endbit
;
5889 int intslots
, this_slotno
;
5891 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5892 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5893 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5894 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5896 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5898 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5899 /* We need to pass this field on the stack. */
5903 parms
.nregs
+= intslots
;
5905 nregs
= parms
.nregs
;
5907 /* Allocate the vector and handle some annoying special cases. */
5910 /* ??? Empty structure has no value? Duh? */
5913 /* Though there's nothing really to store, return a word register
5914 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5915 leads to breakage due to the fact that there are zero bytes to
5917 return gen_rtx_REG (mode
, regbase
);
5921 /* ??? C++ has structures with no fields, and yet a size. Give up
5922 for now and pass everything back in integer registers. */
5923 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5925 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5926 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5928 gcc_assert (nregs
!= 0);
5930 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
5932 /* If at least one field must be passed on the stack, generate
5933 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5934 also be passed on the stack. We can't do much better because the
5935 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5936 of structures for which the fields passed exclusively in registers
5937 are not at the beginning of the structure. */
5939 XVECEXP (parms
.ret
, 0, 0)
5940 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5942 /* Fill in the entries. */
5944 parms
.intoffset
= 0;
5945 function_arg_record_value_2 (type
, 0, &parms
, false);
5946 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
5948 gcc_assert (parms
.nregs
== nregs
);
5953 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5954 of the 64-bit ABI for passing and returning unions.
5955 Return an expression valid as a return value for the FUNCTION_ARG
5956 and TARGET_FUNCTION_VALUE.
5958 SIZE is the size in bytes of the union.
5959 MODE is the argument's machine mode.
5960 REGNO is the hard register the union will be passed in. */
5963 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
5966 int nwords
= ROUND_ADVANCE (size
), i
;
5969 /* See comment in previous function for empty structures. */
5971 return gen_rtx_REG (mode
, regno
);
5973 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5976 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
5978 for (i
= 0; i
< nwords
; i
++)
5980 /* Unions are passed left-justified. */
5981 XVECEXP (regs
, 0, i
)
5982 = gen_rtx_EXPR_LIST (VOIDmode
,
5983 gen_rtx_REG (word_mode
, regno
),
5984 GEN_INT (UNITS_PER_WORD
* i
));
5991 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5992 for passing and returning large (BLKmode) vectors.
5993 Return an expression valid as a return value for the FUNCTION_ARG
5994 and TARGET_FUNCTION_VALUE.
5996 SIZE is the size in bytes of the vector (at least 8 bytes).
5997 REGNO is the FP hard register the vector will be passed in. */
6000 function_arg_vector_value (int size
, int regno
)
6002 int i
, nregs
= size
/ 8;
6005 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6007 for (i
= 0; i
< nregs
; i
++)
6009 XVECEXP (regs
, 0, i
)
6010 = gen_rtx_EXPR_LIST (VOIDmode
,
6011 gen_rtx_REG (DImode
, regno
+ 2*i
),
6018 /* Determine where to put an argument to a function.
6019 Value is zero to push the argument on the stack,
6020 or a hard register in which to store the argument.
6022 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6023 the preceding args and about the function being called.
6024 MODE is the argument's machine mode.
6025 TYPE is the data type of the argument (as a tree).
6026 This is null for libcalls where that information may
6028 NAMED is true if this argument is a named parameter
6029 (otherwise it is an extra parameter matching an ellipsis).
6030 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6031 TARGET_FUNCTION_INCOMING_ARG. */
6034 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6035 const_tree type
, bool named
, bool incoming_p
)
6037 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6039 int regbase
= (incoming_p
6040 ? SPARC_INCOMING_INT_ARG_FIRST
6041 : SPARC_OUTGOING_INT_ARG_FIRST
);
6042 int slotno
, regno
, padding
;
6043 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6045 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6050 /* Vector types deserve special treatment because they are polymorphic wrt
6051 their mode, depending upon whether VIS instructions are enabled. */
6052 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6054 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6055 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6056 || (TARGET_ARCH64
&& size
<= 16));
6058 if (mode
== BLKmode
)
6059 return function_arg_vector_value (size
,
6060 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6062 mclass
= MODE_FLOAT
;
6066 return gen_rtx_REG (mode
, regno
);
6068 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6069 and are promoted to registers if possible. */
6070 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6072 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6073 gcc_assert (size
<= 16);
6075 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6078 /* Unions up to 16 bytes in size are passed in integer registers. */
6079 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6081 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6082 gcc_assert (size
<= 16);
6084 return function_arg_union_value (size
, mode
, slotno
, regno
);
6087 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6088 but also have the slot allocated for them.
6089 If no prototype is in scope fp values in register slots get passed
6090 in two places, either fp regs and int regs or fp regs and memory. */
6091 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6092 && SPARC_FP_REG_P (regno
))
6094 rtx reg
= gen_rtx_REG (mode
, regno
);
6095 if (cum
->prototype_p
|| cum
->libcall_p
)
6097 /* "* 2" because fp reg numbers are recorded in 4 byte
6100 /* ??? This will cause the value to be passed in the fp reg and
6101 in the stack. When a prototype exists we want to pass the
6102 value in the reg but reserve space on the stack. That's an
6103 optimization, and is deferred [for a bit]. */
6104 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6105 return gen_rtx_PARALLEL (mode
,
6107 gen_rtx_EXPR_LIST (VOIDmode
,
6108 NULL_RTX
, const0_rtx
),
6109 gen_rtx_EXPR_LIST (VOIDmode
,
6113 /* ??? It seems that passing back a register even when past
6114 the area declared by REG_PARM_STACK_SPACE will allocate
6115 space appropriately, and will not copy the data onto the
6116 stack, exactly as we desire.
6118 This is due to locate_and_pad_parm being called in
6119 expand_call whenever reg_parm_stack_space > 0, which
6120 while beneficial to our example here, would seem to be
6121 in error from what had been intended. Ho hum... -- r~ */
6129 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6133 /* On incoming, we don't need to know that the value
6134 is passed in %f0 and %i0, and it confuses other parts
6135 causing needless spillage even on the simplest cases. */
6139 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6140 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6142 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6143 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6145 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6149 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6150 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6151 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6156 /* All other aggregate types are passed in an integer register in a mode
6157 corresponding to the size of the type. */
6158 else if (type
&& AGGREGATE_TYPE_P (type
))
6160 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6161 gcc_assert (size
<= 16);
6163 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6166 return gen_rtx_REG (mode
, regno
);
6169 /* Handle the TARGET_FUNCTION_ARG target hook. */
6172 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6173 const_tree type
, bool named
)
6175 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6178 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6181 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6182 const_tree type
, bool named
)
6184 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6187 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6190 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6192 return ((TARGET_ARCH64
6193 && (GET_MODE_ALIGNMENT (mode
) == 128
6194 || (type
&& TYPE_ALIGN (type
) == 128)))
6199 /* For an arg passed partly in registers and partly in memory,
6200 this is the number of bytes of registers used.
6201 For args passed entirely in registers or entirely in memory, zero.
6203 Any arg that starts in the first 6 regs but won't entirely fit in them
6204 needs partial registers on v8. On v9, structures with integer
6205 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6206 values that begin in the last fp reg [where "last fp reg" varies with the
6207 mode] will be split between that reg and memory. */
6210 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6211 tree type
, bool named
)
6213 int slotno
, regno
, padding
;
6215 /* We pass false for incoming_p here, it doesn't matter. */
6216 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6217 false, ®no
, &padding
);
6224 if ((slotno
+ (mode
== BLKmode
6225 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6226 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6227 > SPARC_INT_ARG_MAX
)
6228 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6232 /* We are guaranteed by pass_by_reference that the size of the
6233 argument is not greater than 16 bytes, so we only need to return
6234 one word if the argument is partially passed in registers. */
6236 if (type
&& AGGREGATE_TYPE_P (type
))
6238 int size
= int_size_in_bytes (type
);
6240 if (size
> UNITS_PER_WORD
6241 && slotno
== SPARC_INT_ARG_MAX
- 1)
6242 return UNITS_PER_WORD
;
6244 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6245 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6246 && ! (TARGET_FPU
&& named
)))
6248 /* The complex types are passed as packed types. */
6249 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6250 && slotno
== SPARC_INT_ARG_MAX
- 1)
6251 return UNITS_PER_WORD
;
6253 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6255 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6257 return UNITS_PER_WORD
;
6264 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6265 Specify whether to pass the argument by reference. */
6268 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6269 enum machine_mode mode
, const_tree type
,
6270 bool named ATTRIBUTE_UNUSED
)
6273 /* Original SPARC 32-bit ABI says that structures and unions,
6274 and quad-precision floats are passed by reference. For Pascal,
6275 also pass arrays by reference. All other base types are passed
6278 Extended ABI (as implemented by the Sun compiler) says that all
6279 complex floats are passed by reference. Pass complex integers
6280 in registers up to 8 bytes. More generally, enforce the 2-word
6281 cap for passing arguments in registers.
6283 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6284 integers are passed like floats of the same size, that is in
6285 registers up to 8 bytes. Pass all vector floats by reference
6286 like structure and unions. */
6287 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6289 /* Catch CDImode, TFmode, DCmode and TCmode. */
6290 || GET_MODE_SIZE (mode
) > 8
6292 && TREE_CODE (type
) == VECTOR_TYPE
6293 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6295 /* Original SPARC 64-bit ABI says that structures and unions
6296 smaller than 16 bytes are passed in registers, as well as
6297 all other base types.
6299 Extended ABI (as implemented by the Sun compiler) says that
6300 complex floats are passed in registers up to 16 bytes. Pass
6301 all complex integers in registers up to 16 bytes. More generally,
6302 enforce the 2-word cap for passing arguments in registers.
6304 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6305 integers are passed like floats of the same size, that is in
6306 registers (up to 16 bytes). Pass all vector floats like structure
6309 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6310 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6311 /* Catch CTImode and TCmode. */
6312 || GET_MODE_SIZE (mode
) > 16);
6315 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6316 Update the data in CUM to advance over an argument
6317 of mode MODE and data type TYPE.
6318 TYPE is null for libcalls where that information may not be available. */
6321 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6322 const_tree type
, bool named
)
6324 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6327 /* We pass false for incoming_p here, it doesn't matter. */
6328 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6330 /* If argument requires leading padding, add it. */
6331 cum
->words
+= padding
;
6335 cum
->words
+= (mode
!= BLKmode
6336 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6337 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6341 if (type
&& AGGREGATE_TYPE_P (type
))
6343 int size
= int_size_in_bytes (type
);
6347 else if (size
<= 16)
6349 else /* passed by reference */
6354 cum
->words
+= (mode
!= BLKmode
6355 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6356 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6361 /* Handle the FUNCTION_ARG_PADDING macro.
6362 For the 64 bit ABI structs are always stored left shifted in their
6366 function_arg_padding (enum machine_mode mode
, const_tree type
)
6368 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6371 /* Fall back to the default. */
6372 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6375 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6376 Specify whether to return the return value in memory. */
6379 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6382 /* Original SPARC 32-bit ABI says that structures and unions,
6383 and quad-precision floats are returned in memory. All other
6384 base types are returned in registers.
6386 Extended ABI (as implemented by the Sun compiler) says that
6387 all complex floats are returned in registers (8 FP registers
6388 at most for '_Complex long double'). Return all complex integers
6389 in registers (4 at most for '_Complex long long').
6391 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6392 integers are returned like floats of the same size, that is in
6393 registers up to 8 bytes and in memory otherwise. Return all
6394 vector floats in memory like structure and unions; note that
6395 they always have BLKmode like the latter. */
6396 return (TYPE_MODE (type
) == BLKmode
6397 || TYPE_MODE (type
) == TFmode
6398 || (TREE_CODE (type
) == VECTOR_TYPE
6399 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6401 /* Original SPARC 64-bit ABI says that structures and unions
6402 smaller than 32 bytes are returned in registers, as well as
6403 all other base types.
6405 Extended ABI (as implemented by the Sun compiler) says that all
6406 complex floats are returned in registers (8 FP registers at most
6407 for '_Complex long double'). Return all complex integers in
6408 registers (4 at most for '_Complex TItype').
6410 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6411 integers are returned like floats of the same size, that is in
6412 registers. Return all vector floats like structure and unions;
6413 note that they always have BLKmode like the latter. */
6414 return (TYPE_MODE (type
) == BLKmode
6415 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6418 /* Handle the TARGET_STRUCT_VALUE target hook.
6419 Return where to find the structure return value address. */
6422 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6431 mem
= gen_frame_mem (Pmode
, plus_constant (frame_pointer_rtx
,
6432 STRUCT_VALUE_OFFSET
));
6434 mem
= gen_frame_mem (Pmode
, plus_constant (stack_pointer_rtx
,
6435 STRUCT_VALUE_OFFSET
));
6437 /* Only follow the SPARC ABI for fixed-size structure returns.
6438 Variable size structure returns are handled per the normal
6439 procedures in GCC. This is enabled by -mstd-struct-return */
6441 && sparc_std_struct_return
6442 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6443 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6445 /* We must check and adjust the return address, as it is
6446 optional as to whether the return object is really
6448 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6449 rtx scratch
= gen_reg_rtx (SImode
);
6450 rtx endlab
= gen_label_rtx ();
6452 /* Calculate the return object size */
6453 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6454 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6455 /* Construct a temporary return value */
6457 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6459 /* Implement SPARC 32-bit psABI callee return struct checking:
6461 Fetch the instruction where we will return to and see if
6462 it's an unimp instruction (the most significant 10 bits
6464 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6465 plus_constant (ret_reg
, 8)));
6466 /* Assume the size is valid and pre-adjust */
6467 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6468 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6470 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6471 /* Write the address of the memory pointed to by temp_val into
6472 the memory pointed to by mem */
6473 emit_move_insn (mem
, XEXP (temp_val
, 0));
6474 emit_label (endlab
);
6481 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6482 For v9, function return values are subject to the same rules as arguments,
6483 except that up to 32 bytes may be returned in registers. */
6486 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6489 /* Beware that the two values are swapped here wrt function_arg. */
6490 int regbase
= (outgoing
6491 ? SPARC_INCOMING_INT_ARG_FIRST
6492 : SPARC_OUTGOING_INT_ARG_FIRST
);
6493 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6496 /* Vector types deserve special treatment because they are polymorphic wrt
6497 their mode, depending upon whether VIS instructions are enabled. */
6498 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6500 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6501 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6502 || (TARGET_ARCH64
&& size
<= 32));
6504 if (mode
== BLKmode
)
6505 return function_arg_vector_value (size
,
6506 SPARC_FP_ARG_FIRST
);
6508 mclass
= MODE_FLOAT
;
6511 if (TARGET_ARCH64
&& type
)
6513 /* Structures up to 32 bytes in size are returned in registers. */
6514 if (TREE_CODE (type
) == RECORD_TYPE
)
6516 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6517 gcc_assert (size
<= 32);
6519 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6522 /* Unions up to 32 bytes in size are returned in integer registers. */
6523 else if (TREE_CODE (type
) == UNION_TYPE
)
6525 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6526 gcc_assert (size
<= 32);
6528 return function_arg_union_value (size
, mode
, 0, regbase
);
6531 /* Objects that require it are returned in FP registers. */
6532 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6535 /* All other aggregate types are returned in an integer register in a
6536 mode corresponding to the size of the type. */
6537 else if (AGGREGATE_TYPE_P (type
))
6539 /* All other aggregate types are passed in an integer register
6540 in a mode corresponding to the size of the type. */
6541 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6542 gcc_assert (size
<= 32);
6544 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6546 /* ??? We probably should have made the same ABI change in
6547 3.4.0 as the one we made for unions. The latter was
6548 required by the SCD though, while the former is not
6549 specified, so we favored compatibility and efficiency.
6551 Now we're stuck for aggregates larger than 16 bytes,
6552 because OImode vanished in the meantime. Let's not
6553 try to be unduly clever, and simply follow the ABI
6554 for unions in that case. */
6555 if (mode
== BLKmode
)
6556 return function_arg_union_value (size
, mode
, 0, regbase
);
6561 /* We should only have pointer and integer types at this point. This
6562 must match sparc_promote_function_mode. */
6563 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6567 /* We should only have pointer and integer types at this point. This must
6568 match sparc_promote_function_mode. */
6569 else if (TARGET_ARCH32
6570 && mclass
== MODE_INT
6571 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6574 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6575 regno
= SPARC_FP_ARG_FIRST
;
6579 return gen_rtx_REG (mode
, regno
);
6582 /* Handle TARGET_FUNCTION_VALUE.
6583 On the SPARC, the value is found in the first "output" register, but the
6584 called function leaves it in the first "input" register. */
6587 sparc_function_value (const_tree valtype
,
6588 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6591 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
6594 /* Handle TARGET_LIBCALL_VALUE. */
6597 sparc_libcall_value (enum machine_mode mode
,
6598 const_rtx fun ATTRIBUTE_UNUSED
)
6600 return sparc_function_value_1 (NULL_TREE
, mode
, false);
6603 /* Handle FUNCTION_VALUE_REGNO_P.
6604 On the SPARC, the first "output" reg is used for integer values, and the
6605 first floating point register is used for floating point values. */
6608 sparc_function_value_regno_p (const unsigned int regno
)
6610 return (regno
== 8 || regno
== 32);
6613 /* Do what is necessary for `va_start'. We look at the current function
6614 to determine if stdarg or varargs is used and return the address of
6615 the first unnamed parameter. */
6618 sparc_builtin_saveregs (void)
6620 int first_reg
= crtl
->args
.info
.words
;
6624 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6625 emit_move_insn (gen_rtx_MEM (word_mode
,
6626 gen_rtx_PLUS (Pmode
,
6628 GEN_INT (FIRST_PARM_OFFSET (0)
6631 gen_rtx_REG (word_mode
,
6632 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6634 address
= gen_rtx_PLUS (Pmode
,
6636 GEN_INT (FIRST_PARM_OFFSET (0)
6637 + UNITS_PER_WORD
* first_reg
));
6642 /* Implement `va_start' for stdarg. */
6645 sparc_va_start (tree valist
, rtx nextarg
)
6647 nextarg
= expand_builtin_saveregs ();
6648 std_expand_builtin_va_start (valist
, nextarg
);
6651 /* Implement `va_arg' for stdarg. */
6654 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6657 HOST_WIDE_INT size
, rsize
, align
;
6660 tree ptrtype
= build_pointer_type (type
);
6662 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6665 size
= rsize
= UNITS_PER_WORD
;
6671 size
= int_size_in_bytes (type
);
6672 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6677 /* For SPARC64, objects requiring 16-byte alignment get it. */
6678 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6679 align
= 2 * UNITS_PER_WORD
;
6681 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6682 are left-justified in their slots. */
6683 if (AGGREGATE_TYPE_P (type
))
6686 size
= rsize
= UNITS_PER_WORD
;
6696 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
6697 incr
= fold_convert (sizetype
, incr
);
6698 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
6700 incr
= fold_convert (ptr_type_node
, incr
);
6703 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6706 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6707 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
6711 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6712 addr
= build_va_arg_indirect_ref (addr
);
6715 /* If the address isn't aligned properly for the type, we need a temporary.
6716 FIXME: This is inefficient, usually we can do this in registers. */
6717 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6719 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6720 tree dest_addr
= build_fold_addr_expr (tmp
);
6721 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6722 3, dest_addr
, addr
, size_int (rsize
));
6723 TREE_ADDRESSABLE (tmp
) = 1;
6724 gimplify_and_add (copy
, pre_p
);
6729 addr
= fold_convert (ptrtype
, addr
);
6731 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
6732 gimplify_assign (valist
, incr
, post_p
);
6734 return build_va_arg_indirect_ref (addr
);
6737 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6738 Specify whether the vector mode is supported by the hardware. */
6741 sparc_vector_mode_supported_p (enum machine_mode mode
)
6743 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6746 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6748 static enum machine_mode
6749 sparc_preferred_simd_mode (enum machine_mode mode
)
6767 /* Return the string to output an unconditional branch to LABEL, which is
6768 the operand number of the label.
6770 DEST is the destination insn (i.e. the label), INSN is the source. */
6773 output_ubranch (rtx dest
, int label
, rtx insn
)
6775 static char string
[64];
6776 bool v9_form
= false;
6779 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6781 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6782 - INSN_ADDRESSES (INSN_UID (insn
)));
6783 /* Leave some instructions for "slop". */
6784 if (delta
>= -260000 && delta
< 260000)
6789 strcpy (string
, "ba%*,pt\t%%xcc, ");
6791 strcpy (string
, "b%*\t");
6793 p
= strchr (string
, '\0');
6804 /* Return the string to output a conditional branch to LABEL, which is
6805 the operand number of the label. OP is the conditional expression.
6806 XEXP (OP, 0) is assumed to be a condition code register (integer or
6807 floating point) and its mode specifies what kind of comparison we made.
6809 DEST is the destination insn (i.e. the label), INSN is the source.
6811 REVERSED is nonzero if we should reverse the sense of the comparison.
6813 ANNUL is nonzero if we should generate an annulling branch. */
6816 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6819 static char string
[64];
6820 enum rtx_code code
= GET_CODE (op
);
6821 rtx cc_reg
= XEXP (op
, 0);
6822 enum machine_mode mode
= GET_MODE (cc_reg
);
6823 const char *labelno
, *branch
;
6824 int spaces
= 8, far
;
6827 /* v9 branches are limited to +-1MB. If it is too far away,
6840 fbne,a,pn %fcc2, .LC29
6848 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6851 /* Reversal of FP compares takes care -- an ordered compare
6852 becomes an unordered compare and vice versa. */
6853 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6854 code
= reverse_condition_maybe_unordered (code
);
6856 code
= reverse_condition (code
);
6859 /* Start by writing the branch condition. */
6860 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6911 /* ??? !v9: FP branches cannot be preceded by another floating point
6912 insn. Because there is currently no concept of pre-delay slots,
6913 we can fix this only by always emitting a nop before a floating
6918 strcpy (string
, "nop\n\t");
6919 strcat (string
, branch
);
6932 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6944 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6965 strcpy (string
, branch
);
6967 spaces
-= strlen (branch
);
6968 p
= strchr (string
, '\0');
6970 /* Now add the annulling, the label, and a possible noop. */
6983 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
6985 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6986 - INSN_ADDRESSES (INSN_UID (insn
)));
6987 /* Leave some instructions for "slop". */
6988 if (delta
< -260000 || delta
>= 260000)
6992 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6994 static char v9_fcc_labelno
[] = "%%fccX, ";
6995 /* Set the char indicating the number of the fcc reg to use. */
6996 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
6997 labelno
= v9_fcc_labelno
;
7000 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7004 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7006 labelno
= "%%xcc, ";
7011 labelno
= "%%icc, ";
7016 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7019 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7032 strcpy (p
, labelno
);
7033 p
= strchr (p
, '\0');
7036 strcpy (p
, ".+12\n\t nop\n\tb\t");
7037 /* Skip the next insn if requested or
7038 if we know that it will be a nop. */
7039 if (annul
|| ! final_sequence
)
7053 /* Emit a library call comparison between floating point X and Y.
7054 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7055 Return the new operator to be used in the comparison sequence.
7057 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7058 values as arguments instead of the TFmode registers themselves,
7059 that's why we cannot call emit_float_lib_cmp. */
7062 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7065 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7066 enum machine_mode mode
;
7067 enum rtx_code new_comparison
;
7072 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7076 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7080 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7084 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7088 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7092 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7103 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7116 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7117 emit_move_insn (slot0
, x
);
7124 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7125 emit_move_insn (slot1
, y
);
7128 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7129 emit_library_call (libfunc
, LCT_NORMAL
,
7131 XEXP (slot0
, 0), Pmode
,
7132 XEXP (slot1
, 0), Pmode
);
7137 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7138 emit_library_call (libfunc
, LCT_NORMAL
,
7140 x
, TFmode
, y
, TFmode
);
7145 /* Immediately move the result of the libcall into a pseudo
7146 register so reload doesn't clobber the value if it needs
7147 the return register for a spill reg. */
7148 result
= gen_reg_rtx (mode
);
7149 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7154 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7157 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7158 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7161 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7162 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7164 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7166 tem
= gen_reg_rtx (mode
);
7168 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7170 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7171 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7174 tem
= gen_reg_rtx (mode
);
7176 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7178 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7179 tem2
= gen_reg_rtx (mode
);
7181 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7183 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7184 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7185 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7191 /* Generate an unsigned DImode to FP conversion. This is the same code
7192 optabs would emit if we didn't have TFmode patterns. */
7195 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7197 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7200 in
= force_reg (DImode
, operands
[1]);
7201 neglab
= gen_label_rtx ();
7202 donelab
= gen_label_rtx ();
7203 i0
= gen_reg_rtx (DImode
);
7204 i1
= gen_reg_rtx (DImode
);
7205 f0
= gen_reg_rtx (mode
);
7207 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7209 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7210 emit_jump_insn (gen_jump (donelab
));
7213 emit_label (neglab
);
7215 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7216 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7217 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7218 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7219 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7221 emit_label (donelab
);
7224 /* Generate an FP to unsigned DImode conversion. This is the same code
7225 optabs would emit if we didn't have TFmode patterns. */
7228 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7230 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7233 in
= force_reg (mode
, operands
[1]);
7234 neglab
= gen_label_rtx ();
7235 donelab
= gen_label_rtx ();
7236 i0
= gen_reg_rtx (DImode
);
7237 i1
= gen_reg_rtx (DImode
);
7238 limit
= gen_reg_rtx (mode
);
7239 f0
= gen_reg_rtx (mode
);
7241 emit_move_insn (limit
,
7242 CONST_DOUBLE_FROM_REAL_VALUE (
7243 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7244 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7246 emit_insn (gen_rtx_SET (VOIDmode
,
7248 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7249 emit_jump_insn (gen_jump (donelab
));
7252 emit_label (neglab
);
7254 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7255 emit_insn (gen_rtx_SET (VOIDmode
,
7257 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7258 emit_insn (gen_movdi (i1
, const1_rtx
));
7259 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7260 emit_insn (gen_xordi3 (out
, i0
, i1
));
7262 emit_label (donelab
);
7265 /* Return the string to output a conditional branch to LABEL, testing
7266 register REG. LABEL is the operand number of the label; REG is the
7267 operand number of the reg. OP is the conditional expression. The mode
7268 of REG says what kind of comparison we made.
7270 DEST is the destination insn (i.e. the label), INSN is the source.
7272 REVERSED is nonzero if we should reverse the sense of the comparison.
7274 ANNUL is nonzero if we should generate an annulling branch. */
7277 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7278 int annul
, rtx insn
)
7280 static char string
[64];
7281 enum rtx_code code
= GET_CODE (op
);
7282 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7287 /* branch on register are limited to +-128KB. If it is too far away,
7300 brgez,a,pn %o1, .LC29
7306 ba,pt %xcc, .LC29 */
7308 far
= get_attr_length (insn
) >= 3;
7310 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7312 code
= reverse_condition (code
);
7314 /* Only 64 bit versions of these instructions exist. */
7315 gcc_assert (mode
== DImode
);
7317 /* Start by writing the branch condition. */
7322 strcpy (string
, "brnz");
7326 strcpy (string
, "brz");
7330 strcpy (string
, "brgez");
7334 strcpy (string
, "brlz");
7338 strcpy (string
, "brlez");
7342 strcpy (string
, "brgz");
7349 p
= strchr (string
, '\0');
7351 /* Now add the annulling, reg, label, and nop. */
7358 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7361 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7366 *p
= p
< string
+ 8 ? '\t' : ' ';
7374 int veryfar
= 1, delta
;
7376 if (INSN_ADDRESSES_SET_P ())
7378 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7379 - INSN_ADDRESSES (INSN_UID (insn
)));
7380 /* Leave some instructions for "slop". */
7381 if (delta
>= -260000 && delta
< 260000)
7385 strcpy (p
, ".+12\n\t nop\n\t");
7386 /* Skip the next insn if requested or
7387 if we know that it will be a nop. */
7388 if (annul
|| ! final_sequence
)
7398 strcpy (p
, "ba,pt\t%%xcc, ");
7412 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7413 Such instructions cannot be used in the delay slot of return insn on v9.
7414 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7418 epilogue_renumber (register rtx
*where
, int test
)
7420 register const char *fmt
;
7422 register enum rtx_code code
;
7427 code
= GET_CODE (*where
);
7432 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7434 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7435 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7443 /* Do not replace the frame pointer with the stack pointer because
7444 it can cause the delayed instruction to load below the stack.
7445 This occurs when instructions like:
7447 (set (reg/i:SI 24 %i0)
7448 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7449 (const_int -20 [0xffffffec])) 0))
7451 are in the return delayed slot. */
7453 if (GET_CODE (XEXP (*where
, 0)) == REG
7454 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7455 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7456 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7461 if (SPARC_STACK_BIAS
7462 && GET_CODE (XEXP (*where
, 0)) == REG
7463 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7471 fmt
= GET_RTX_FORMAT (code
);
7473 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7478 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7479 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7482 else if (fmt
[i
] == 'e'
7483 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7489 /* Leaf functions and non-leaf functions have different needs. */
7492 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7495 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7497 static const int *const reg_alloc_orders
[] = {
7498 reg_leaf_alloc_order
,
7499 reg_nonleaf_alloc_order
};
7502 order_regs_for_local_alloc (void)
7504 static int last_order_nonleaf
= 1;
7506 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
7508 last_order_nonleaf
= !last_order_nonleaf
;
7509 memcpy ((char *) reg_alloc_order
,
7510 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7511 FIRST_PSEUDO_REGISTER
* sizeof (int));
7515 /* Return 1 if REG and MEM are legitimate enough to allow the various
7516 mem<-->reg splits to be run. */
7519 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7521 /* Punt if we are here by mistake. */
7522 gcc_assert (reload_completed
);
7524 /* We must have an offsettable memory reference. */
7525 if (! offsettable_memref_p (mem
))
7528 /* If we have legitimate args for ldd/std, we do not want
7529 the split to happen. */
7530 if ((REGNO (reg
) % 2) == 0
7531 && mem_min_alignment (mem
, 8))
7538 /* Return 1 if x and y are some kind of REG and they refer to
7539 different hard registers. This test is guaranteed to be
7540 run after reload. */
7543 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7545 if (GET_CODE (x
) != REG
)
7547 if (GET_CODE (y
) != REG
)
7549 if (REGNO (x
) == REGNO (y
))
7554 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7555 This makes them candidates for using ldd and std insns.
7557 Note reg1 and reg2 *must* be hard registers. */
7560 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7562 /* We might have been passed a SUBREG. */
7563 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7566 if (REGNO (reg1
) % 2 != 0)
7569 /* Integer ldd is deprecated in SPARC V9 */
7570 if (TARGET_V9
&& REGNO (reg1
) < 32)
7573 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7576 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7579 This can only happen when addr1 and addr2, the addresses in mem1
7580 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7581 addr1 must also be aligned on a 64-bit boundary.
7583 Also iff dependent_reg_rtx is not null it should not be used to
7584 compute the address for mem1, i.e. we cannot optimize a sequence
7596 But, note that the transformation from:
7601 is perfectly fine. Thus, the peephole2 patterns always pass us
7602 the destination register of the first load, never the second one.
7604 For stores we don't have a similar problem, so dependent_reg_rtx is
7608 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7612 HOST_WIDE_INT offset1
;
7614 /* The mems cannot be volatile. */
7615 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7618 /* MEM1 should be aligned on a 64-bit boundary. */
7619 if (MEM_ALIGN (mem1
) < 64)
7622 addr1
= XEXP (mem1
, 0);
7623 addr2
= XEXP (mem2
, 0);
7625 /* Extract a register number and offset (if used) from the first addr. */
7626 if (GET_CODE (addr1
) == PLUS
)
7628 /* If not a REG, return zero. */
7629 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7633 reg1
= REGNO (XEXP (addr1
, 0));
7634 /* The offset must be constant! */
7635 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7637 offset1
= INTVAL (XEXP (addr1
, 1));
7640 else if (GET_CODE (addr1
) != REG
)
7644 reg1
= REGNO (addr1
);
7645 /* This was a simple (mem (reg)) expression. Offset is 0. */
7649 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7650 if (GET_CODE (addr2
) != PLUS
)
7653 if (GET_CODE (XEXP (addr2
, 0)) != REG
7654 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7657 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7660 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7663 /* The first offset must be evenly divisible by 8 to ensure the
7664 address is 64 bit aligned. */
7665 if (offset1
% 8 != 0)
7668 /* The offset for the second addr must be 4 more than the first addr. */
7669 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7672 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7677 /* Return 1 if reg is a pseudo, or is the first register in
7678 a hard register pair. This makes it suitable for use in
7679 ldd and std insns. */
7682 register_ok_for_ldd (rtx reg
)
7684 /* We might have been passed a SUBREG. */
7688 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7689 return (REGNO (reg
) % 2 == 0);
7694 /* Return 1 if OP is a memory whose address is known to be
7695 aligned to 8-byte boundary, or a pseudo during reload.
7696 This makes it suitable for use in ldd and std insns. */
7699 memory_ok_for_ldd (rtx op
)
7703 /* In 64-bit mode, we assume that the address is word-aligned. */
7704 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
7707 if ((reload_in_progress
|| reload_completed
)
7708 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
7711 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7713 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
7722 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7725 sparc_print_operand_punct_valid_p (unsigned char code
)
7738 /* Implement TARGET_PRINT_OPERAND.
7739 Print operand X (an rtx) in assembler syntax to file FILE.
7740 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7741 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7744 sparc_print_operand (FILE *file
, rtx x
, int code
)
7749 /* Output an insn in a delay slot. */
7751 sparc_indent_opcode
= 1;
7753 fputs ("\n\t nop", file
);
7756 /* Output an annul flag if there's nothing for the delay slot and we
7757 are optimizing. This is always used with '(' below.
7758 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7759 this is a dbx bug. So, we only do this when optimizing.
7760 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7761 Always emit a nop in case the next instruction is a branch. */
7762 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7766 /* Output a 'nop' if there's nothing for the delay slot and we are
7767 not optimizing. This is always used with '*' above. */
7768 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7769 fputs ("\n\t nop", file
);
7770 else if (final_sequence
)
7771 sparc_indent_opcode
= 1;
7774 /* Output the right displacement from the saved PC on function return.
7775 The caller may have placed an "unimp" insn immediately after the call
7776 so we have to account for it. This insn is used in the 32-bit ABI
7777 when calling a function that returns a non zero-sized structure. The
7778 64-bit ABI doesn't have it. Be careful to have this test be the same
7779 as that for the call. The exception is when sparc_std_struct_return
7780 is enabled, the psABI is followed exactly and the adjustment is made
7781 by the code in sparc_struct_value_rtx. The call emitted is the same
7782 when sparc_std_struct_return is enabled. */
7784 && cfun
->returns_struct
7785 && !sparc_std_struct_return
7786 && DECL_SIZE (DECL_RESULT (current_function_decl
))
7787 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7789 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7795 /* Output the Embedded Medium/Anywhere code model base register. */
7796 fputs (EMBMEDANY_BASE_REG
, file
);
7799 /* Print some local dynamic TLS name. */
7800 assemble_name (file
, get_some_local_dynamic_name ());
7804 /* Adjust the operand to take into account a RESTORE operation. */
7805 if (GET_CODE (x
) == CONST_INT
)
7807 else if (GET_CODE (x
) != REG
)
7808 output_operand_lossage ("invalid %%Y operand");
7809 else if (REGNO (x
) < 8)
7810 fputs (reg_names
[REGNO (x
)], file
);
7811 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
7812 fputs (reg_names
[REGNO (x
)-16], file
);
7814 output_operand_lossage ("invalid %%Y operand");
7817 /* Print out the low order register name of a register pair. */
7818 if (WORDS_BIG_ENDIAN
)
7819 fputs (reg_names
[REGNO (x
)+1], file
);
7821 fputs (reg_names
[REGNO (x
)], file
);
7824 /* Print out the high order register name of a register pair. */
7825 if (WORDS_BIG_ENDIAN
)
7826 fputs (reg_names
[REGNO (x
)], file
);
7828 fputs (reg_names
[REGNO (x
)+1], file
);
7831 /* Print out the second register name of a register pair or quad.
7832 I.e., R (%o0) => %o1. */
7833 fputs (reg_names
[REGNO (x
)+1], file
);
7836 /* Print out the third register name of a register quad.
7837 I.e., S (%o0) => %o2. */
7838 fputs (reg_names
[REGNO (x
)+2], file
);
7841 /* Print out the fourth register name of a register quad.
7842 I.e., T (%o0) => %o3. */
7843 fputs (reg_names
[REGNO (x
)+3], file
);
7846 /* Print a condition code register. */
7847 if (REGNO (x
) == SPARC_ICC_REG
)
7849 /* We don't handle CC[X]_NOOVmode because they're not supposed
7851 if (GET_MODE (x
) == CCmode
)
7852 fputs ("%icc", file
);
7853 else if (GET_MODE (x
) == CCXmode
)
7854 fputs ("%xcc", file
);
7859 /* %fccN register */
7860 fputs (reg_names
[REGNO (x
)], file
);
7863 /* Print the operand's address only. */
7864 output_address (XEXP (x
, 0));
7867 /* In this case we need a register. Use %g0 if the
7868 operand is const0_rtx. */
7870 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7872 fputs ("%g0", file
);
7879 switch (GET_CODE (x
))
7881 case IOR
: fputs ("or", file
); break;
7882 case AND
: fputs ("and", file
); break;
7883 case XOR
: fputs ("xor", file
); break;
7884 default: output_operand_lossage ("invalid %%A operand");
7889 switch (GET_CODE (x
))
7891 case IOR
: fputs ("orn", file
); break;
7892 case AND
: fputs ("andn", file
); break;
7893 case XOR
: fputs ("xnor", file
); break;
7894 default: output_operand_lossage ("invalid %%B operand");
7898 /* These are used by the conditional move instructions. */
7902 enum rtx_code rc
= GET_CODE (x
);
7906 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7907 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7908 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7910 rc
= reverse_condition (GET_CODE (x
));
7914 case NE
: fputs ("ne", file
); break;
7915 case EQ
: fputs ("e", file
); break;
7916 case GE
: fputs ("ge", file
); break;
7917 case GT
: fputs ("g", file
); break;
7918 case LE
: fputs ("le", file
); break;
7919 case LT
: fputs ("l", file
); break;
7920 case GEU
: fputs ("geu", file
); break;
7921 case GTU
: fputs ("gu", file
); break;
7922 case LEU
: fputs ("leu", file
); break;
7923 case LTU
: fputs ("lu", file
); break;
7924 case LTGT
: fputs ("lg", file
); break;
7925 case UNORDERED
: fputs ("u", file
); break;
7926 case ORDERED
: fputs ("o", file
); break;
7927 case UNLT
: fputs ("ul", file
); break;
7928 case UNLE
: fputs ("ule", file
); break;
7929 case UNGT
: fputs ("ug", file
); break;
7930 case UNGE
: fputs ("uge", file
); break;
7931 case UNEQ
: fputs ("ue", file
); break;
7932 default: output_operand_lossage (code
== 'c'
7933 ? "invalid %%c operand"
7934 : "invalid %%C operand");
7939 /* These are used by the movr instruction pattern. */
7943 enum rtx_code rc
= (code
== 'd'
7944 ? reverse_condition (GET_CODE (x
))
7948 case NE
: fputs ("ne", file
); break;
7949 case EQ
: fputs ("e", file
); break;
7950 case GE
: fputs ("gez", file
); break;
7951 case LT
: fputs ("lz", file
); break;
7952 case LE
: fputs ("lez", file
); break;
7953 case GT
: fputs ("gz", file
); break;
7954 default: output_operand_lossage (code
== 'd'
7955 ? "invalid %%d operand"
7956 : "invalid %%D operand");
7963 /* Print a sign-extended character. */
7964 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
7965 fprintf (file
, "%d", i
);
7970 /* Operand must be a MEM; write its address. */
7971 if (GET_CODE (x
) != MEM
)
7972 output_operand_lossage ("invalid %%f operand");
7973 output_address (XEXP (x
, 0));
7978 /* Print a sign-extended 32-bit value. */
7980 if (GET_CODE(x
) == CONST_INT
)
7982 else if (GET_CODE(x
) == CONST_DOUBLE
)
7983 i
= CONST_DOUBLE_LOW (x
);
7986 output_operand_lossage ("invalid %%s operand");
7989 i
= trunc_int_for_mode (i
, SImode
);
7990 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
7995 /* Do nothing special. */
7999 /* Undocumented flag. */
8000 output_operand_lossage ("invalid operand output code");
8003 if (GET_CODE (x
) == REG
)
8004 fputs (reg_names
[REGNO (x
)], file
);
8005 else if (GET_CODE (x
) == MEM
)
8008 /* Poor Sun assembler doesn't understand absolute addressing. */
8009 if (CONSTANT_P (XEXP (x
, 0)))
8010 fputs ("%g0+", file
);
8011 output_address (XEXP (x
, 0));
8014 else if (GET_CODE (x
) == HIGH
)
8016 fputs ("%hi(", file
);
8017 output_addr_const (file
, XEXP (x
, 0));
8020 else if (GET_CODE (x
) == LO_SUM
)
8022 sparc_print_operand (file
, XEXP (x
, 0), 0);
8023 if (TARGET_CM_MEDMID
)
8024 fputs ("+%l44(", file
);
8026 fputs ("+%lo(", file
);
8027 output_addr_const (file
, XEXP (x
, 1));
8030 else if (GET_CODE (x
) == CONST_DOUBLE
8031 && (GET_MODE (x
) == VOIDmode
8032 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8034 if (CONST_DOUBLE_HIGH (x
) == 0)
8035 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8036 else if (CONST_DOUBLE_HIGH (x
) == -1
8037 && CONST_DOUBLE_LOW (x
) < 0)
8038 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8040 output_operand_lossage ("long long constant not a valid immediate operand");
8042 else if (GET_CODE (x
) == CONST_DOUBLE
)
8043 output_operand_lossage ("floating point constant not a valid immediate operand");
8044 else { output_addr_const (file
, x
); }
8047 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8050 sparc_print_operand_address (FILE *file
, rtx x
)
8052 register rtx base
, index
= 0;
8054 register rtx addr
= x
;
8057 fputs (reg_names
[REGNO (addr
)], file
);
8058 else if (GET_CODE (addr
) == PLUS
)
8060 if (CONST_INT_P (XEXP (addr
, 0)))
8061 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8062 else if (CONST_INT_P (XEXP (addr
, 1)))
8063 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8065 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8066 if (GET_CODE (base
) == LO_SUM
)
8068 gcc_assert (USE_AS_OFFSETABLE_LO10
8070 && ! TARGET_CM_MEDMID
);
8071 output_operand (XEXP (base
, 0), 0);
8072 fputs ("+%lo(", file
);
8073 output_address (XEXP (base
, 1));
8074 fprintf (file
, ")+%d", offset
);
8078 fputs (reg_names
[REGNO (base
)], file
);
8080 fprintf (file
, "%+d", offset
);
8081 else if (REG_P (index
))
8082 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8083 else if (GET_CODE (index
) == SYMBOL_REF
8084 || GET_CODE (index
) == LABEL_REF
8085 || GET_CODE (index
) == CONST
)
8086 fputc ('+', file
), output_addr_const (file
, index
);
8087 else gcc_unreachable ();
8090 else if (GET_CODE (addr
) == MINUS
8091 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8093 output_addr_const (file
, XEXP (addr
, 0));
8095 output_addr_const (file
, XEXP (addr
, 1));
8096 fputs ("-.)", file
);
8098 else if (GET_CODE (addr
) == LO_SUM
)
8100 output_operand (XEXP (addr
, 0), 0);
8101 if (TARGET_CM_MEDMID
)
8102 fputs ("+%l44(", file
);
8104 fputs ("+%lo(", file
);
8105 output_address (XEXP (addr
, 1));
8109 && GET_CODE (addr
) == CONST
8110 && GET_CODE (XEXP (addr
, 0)) == MINUS
8111 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8112 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8113 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8115 addr
= XEXP (addr
, 0);
8116 output_addr_const (file
, XEXP (addr
, 0));
8117 /* Group the args of the second CONST in parenthesis. */
8119 /* Skip past the second CONST--it does nothing for us. */
8120 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8121 /* Close the parenthesis. */
8126 output_addr_const (file
, addr
);
8130 /* Target hook for assembling integer objects. The sparc version has
8131 special handling for aligned DI-mode objects. */
8134 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8136 /* ??? We only output .xword's for symbols and only then in environments
8137 where the assembler can handle them. */
8138 if (aligned_p
&& size
== 8
8139 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8143 assemble_integer_with_op ("\t.xword\t", x
);
8148 assemble_aligned_integer (4, const0_rtx
);
8149 assemble_aligned_integer (4, x
);
8153 return default_assemble_integer (x
, size
, aligned_p
);
8156 /* Return the value of a code used in the .proc pseudo-op that says
8157 what kind of result this function returns. For non-C types, we pick
8158 the closest C type. */
8160 #ifndef SHORT_TYPE_SIZE
8161 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8164 #ifndef INT_TYPE_SIZE
8165 #define INT_TYPE_SIZE BITS_PER_WORD
8168 #ifndef LONG_TYPE_SIZE
8169 #define LONG_TYPE_SIZE BITS_PER_WORD
8172 #ifndef LONG_LONG_TYPE_SIZE
8173 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8176 #ifndef FLOAT_TYPE_SIZE
8177 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8180 #ifndef DOUBLE_TYPE_SIZE
8181 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8184 #ifndef LONG_DOUBLE_TYPE_SIZE
8185 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8189 sparc_type_code (register tree type
)
8191 register unsigned long qualifiers
= 0;
8192 register unsigned shift
;
8194 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8195 setting more, since some assemblers will give an error for this. Also,
8196 we must be careful to avoid shifts of 32 bits or more to avoid getting
8197 unpredictable results. */
8199 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8201 switch (TREE_CODE (type
))
8207 qualifiers
|= (3 << shift
);
8212 qualifiers
|= (2 << shift
);
8216 case REFERENCE_TYPE
:
8218 qualifiers
|= (1 << shift
);
8222 return (qualifiers
| 8);
8225 case QUAL_UNION_TYPE
:
8226 return (qualifiers
| 9);
8229 return (qualifiers
| 10);
8232 return (qualifiers
| 16);
8235 /* If this is a range type, consider it to be the underlying
8237 if (TREE_TYPE (type
) != 0)
8240 /* Carefully distinguish all the standard types of C,
8241 without messing up if the language is not C. We do this by
8242 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8243 look at both the names and the above fields, but that's redundant.
8244 Any type whose size is between two C types will be considered
8245 to be the wider of the two types. Also, we do not have a
8246 special code to use for "long long", so anything wider than
8247 long is treated the same. Note that we can't distinguish
8248 between "int" and "long" in this code if they are the same
8249 size, but that's fine, since neither can the assembler. */
8251 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8252 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8254 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8255 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8257 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8258 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8261 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8264 /* If this is a range type, consider it to be the underlying
8266 if (TREE_TYPE (type
) != 0)
8269 /* Carefully distinguish all the standard types of C,
8270 without messing up if the language is not C. */
8272 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8273 return (qualifiers
| 6);
8276 return (qualifiers
| 7);
8278 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8279 /* ??? We need to distinguish between double and float complex types,
8280 but I don't know how yet because I can't reach this code from
8281 existing front-ends. */
8282 return (qualifiers
| 7); /* Who knows? */
8285 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8291 gcc_unreachable (); /* Not a type! */
8298 /* Nested function support. */
8300 /* Emit RTL insns to initialize the variable parts of a trampoline.
8301 FNADDR is an RTX for the address of the function's pure code.
8302 CXT is an RTX for the static chain value for the function.
8304 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8305 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8306 (to store insns). This is a bit excessive. Perhaps a different
8307 mechanism would be better here.
8309 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8312 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8314 /* SPARC 32-bit trampoline:
8317 sethi %hi(static), %g2
8319 or %g2, %lo(static), %g2
8321 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8322 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8326 (adjust_address (m_tramp
, SImode
, 0),
8327 expand_binop (SImode
, ior_optab
,
8328 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8329 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8330 NULL_RTX
, 1, OPTAB_DIRECT
));
8333 (adjust_address (m_tramp
, SImode
, 4),
8334 expand_binop (SImode
, ior_optab
,
8335 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8336 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8337 NULL_RTX
, 1, OPTAB_DIRECT
));
8340 (adjust_address (m_tramp
, SImode
, 8),
8341 expand_binop (SImode
, ior_optab
,
8342 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8343 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8344 NULL_RTX
, 1, OPTAB_DIRECT
));
8347 (adjust_address (m_tramp
, SImode
, 12),
8348 expand_binop (SImode
, ior_optab
,
8349 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8350 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8351 NULL_RTX
, 1, OPTAB_DIRECT
));
8353 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8354 aligned on a 16 byte boundary so one flush clears it all. */
8355 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8356 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8357 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8358 && sparc_cpu
!= PROCESSOR_NIAGARA
8359 && sparc_cpu
!= PROCESSOR_NIAGARA2
8360 && sparc_cpu
!= PROCESSOR_NIAGARA3
8361 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8362 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8364 /* Call __enable_execute_stack after writing onto the stack to make sure
8365 the stack address is accessible. */
8366 #ifdef HAVE_ENABLE_EXECUTE_STACK
8367 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8368 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8373 /* The 64-bit version is simpler because it makes more sense to load the
8374 values as "immediate" data out of the trampoline. It's also easier since
8375 we can read the PC without clobbering a register. */
8378 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8380 /* SPARC 64-bit trampoline:
8389 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8390 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8391 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8392 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8393 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8394 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8395 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8396 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8397 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8398 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8399 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8401 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8402 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8403 && sparc_cpu
!= PROCESSOR_NIAGARA
8404 && sparc_cpu
!= PROCESSOR_NIAGARA2
8405 && sparc_cpu
!= PROCESSOR_NIAGARA3
8406 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8407 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8409 /* Call __enable_execute_stack after writing onto the stack to make sure
8410 the stack address is accessible. */
8411 #ifdef HAVE_ENABLE_EXECUTE_STACK
8412 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8413 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8417 /* Worker for TARGET_TRAMPOLINE_INIT. */
8420 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8422 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8423 cxt
= force_reg (Pmode
, cxt
);
8425 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8427 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8430 /* Adjust the cost of a scheduling dependency. Return the new cost of
8431 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8434 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8436 enum attr_type insn_type
;
8438 if (! recog_memoized (insn
))
8441 insn_type
= get_attr_type (insn
);
8443 if (REG_NOTE_KIND (link
) == 0)
8445 /* Data dependency; DEP_INSN writes a register that INSN reads some
8448 /* if a load, then the dependence must be on the memory address;
8449 add an extra "cycle". Note that the cost could be two cycles
8450 if the reg was written late in an instruction group; we ca not tell
8452 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
8455 /* Get the delay only if the address of the store is the dependence. */
8456 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
8458 rtx pat
= PATTERN(insn
);
8459 rtx dep_pat
= PATTERN (dep_insn
);
8461 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8462 return cost
; /* This should not happen! */
8464 /* The dependency between the two instructions was on the data that
8465 is being stored. Assume that this implies that the address of the
8466 store is not dependent. */
8467 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8470 return cost
+ 3; /* An approximation. */
8473 /* A shift instruction cannot receive its data from an instruction
8474 in the same cycle; add a one cycle penalty. */
8475 if (insn_type
== TYPE_SHIFT
)
8476 return cost
+ 3; /* Split before cascade into shift. */
8480 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8481 INSN writes some cycles later. */
8483 /* These are only significant for the fpu unit; writing a fp reg before
8484 the fpu has finished with it stalls the processor. */
8486 /* Reusing an integer register causes no problems. */
8487 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8495 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8497 enum attr_type insn_type
, dep_type
;
8498 rtx pat
= PATTERN(insn
);
8499 rtx dep_pat
= PATTERN (dep_insn
);
8501 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
8504 insn_type
= get_attr_type (insn
);
8505 dep_type
= get_attr_type (dep_insn
);
8507 switch (REG_NOTE_KIND (link
))
8510 /* Data dependency; DEP_INSN writes a register that INSN reads some
8517 /* Get the delay iff the address of the store is the dependence. */
8518 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8521 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8528 /* If a load, then the dependence must be on the memory address. If
8529 the addresses aren't equal, then it might be a false dependency */
8530 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
8532 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
8533 || GET_CODE (SET_DEST (dep_pat
)) != MEM
8534 || GET_CODE (SET_SRC (pat
)) != MEM
8535 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
8536 XEXP (SET_SRC (pat
), 0)))
8544 /* Compare to branch latency is 0. There is no benefit from
8545 separating compare and branch. */
8546 if (dep_type
== TYPE_COMPARE
)
8548 /* Floating point compare to branch latency is less than
8549 compare to conditional move. */
8550 if (dep_type
== TYPE_FPCMP
)
8559 /* Anti-dependencies only penalize the fpu unit. */
8560 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8572 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
8576 case PROCESSOR_SUPERSPARC
:
8577 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
8579 case PROCESSOR_HYPERSPARC
:
8580 case PROCESSOR_SPARCLITE86X
:
8581 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8590 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8591 int sched_verbose ATTRIBUTE_UNUSED
,
8592 int max_ready ATTRIBUTE_UNUSED
)
8596 sparc_use_sched_lookahead (void)
8598 if (sparc_cpu
== PROCESSOR_NIAGARA
8599 || sparc_cpu
== PROCESSOR_NIAGARA2
8600 || sparc_cpu
== PROCESSOR_NIAGARA3
8601 || sparc_cpu
== PROCESSOR_NIAGARA4
)
8603 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8604 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8606 if ((1 << sparc_cpu
) &
8607 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8608 (1 << PROCESSOR_SPARCLITE86X
)))
8614 sparc_issue_rate (void)
8618 case PROCESSOR_NIAGARA
:
8619 case PROCESSOR_NIAGARA2
:
8620 case PROCESSOR_NIAGARA3
:
8621 case PROCESSOR_NIAGARA4
:
8625 /* Assume V9 processors are capable of at least dual-issue. */
8627 case PROCESSOR_SUPERSPARC
:
8629 case PROCESSOR_HYPERSPARC
:
8630 case PROCESSOR_SPARCLITE86X
:
8632 case PROCESSOR_ULTRASPARC
:
8633 case PROCESSOR_ULTRASPARC3
:
8639 set_extends (rtx insn
)
8641 register rtx pat
= PATTERN (insn
);
8643 switch (GET_CODE (SET_SRC (pat
)))
8645 /* Load and some shift instructions zero extend. */
8648 /* sethi clears the high bits */
8650 /* LO_SUM is used with sethi. sethi cleared the high
8651 bits and the values used with lo_sum are positive */
8653 /* Store flag stores 0 or 1 */
8663 rtx op0
= XEXP (SET_SRC (pat
), 0);
8664 rtx op1
= XEXP (SET_SRC (pat
), 1);
8665 if (GET_CODE (op1
) == CONST_INT
)
8666 return INTVAL (op1
) >= 0;
8667 if (GET_CODE (op0
) != REG
)
8669 if (sparc_check_64 (op0
, insn
) == 1)
8671 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8676 rtx op0
= XEXP (SET_SRC (pat
), 0);
8677 rtx op1
= XEXP (SET_SRC (pat
), 1);
8678 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8680 if (GET_CODE (op1
) == CONST_INT
)
8681 return INTVAL (op1
) >= 0;
8682 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8685 return GET_MODE (SET_SRC (pat
)) == SImode
;
8686 /* Positive integers leave the high bits zero. */
8688 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8690 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8693 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8695 return sparc_check_64 (SET_SRC (pat
), insn
);
8701 /* We _ought_ to have only one kind per function, but... */
8702 static GTY(()) rtx sparc_addr_diff_list
;
8703 static GTY(()) rtx sparc_addr_list
;
8706 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8708 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8710 sparc_addr_diff_list
8711 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8713 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8717 sparc_output_addr_vec (rtx vec
)
8719 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8720 int idx
, vlen
= XVECLEN (body
, 0);
8722 #ifdef ASM_OUTPUT_ADDR_VEC_START
8723 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8726 #ifdef ASM_OUTPUT_CASE_LABEL
8727 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8730 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8733 for (idx
= 0; idx
< vlen
; idx
++)
8735 ASM_OUTPUT_ADDR_VEC_ELT
8736 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8739 #ifdef ASM_OUTPUT_ADDR_VEC_END
8740 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8745 sparc_output_addr_diff_vec (rtx vec
)
8747 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8748 rtx base
= XEXP (XEXP (body
, 0), 0);
8749 int idx
, vlen
= XVECLEN (body
, 1);
8751 #ifdef ASM_OUTPUT_ADDR_VEC_START
8752 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8755 #ifdef ASM_OUTPUT_CASE_LABEL
8756 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8759 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8762 for (idx
= 0; idx
< vlen
; idx
++)
8764 ASM_OUTPUT_ADDR_DIFF_ELT
8767 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8768 CODE_LABEL_NUMBER (base
));
8771 #ifdef ASM_OUTPUT_ADDR_VEC_END
8772 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8777 sparc_output_deferred_case_vectors (void)
8782 if (sparc_addr_list
== NULL_RTX
8783 && sparc_addr_diff_list
== NULL_RTX
)
8786 /* Align to cache line in the function's code section. */
8787 switch_to_section (current_function_section ());
8789 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8791 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8793 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8794 sparc_output_addr_vec (XEXP (t
, 0));
8795 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8796 sparc_output_addr_diff_vec (XEXP (t
, 0));
8798 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8801 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8802 unknown. Return 1 if the high bits are zero, -1 if the register is
8805 sparc_check_64 (rtx x
, rtx insn
)
8807 /* If a register is set only once it is safe to ignore insns this
8808 code does not know how to handle. The loop will either recognize
8809 the single set and return the correct value or fail to recognize
8814 gcc_assert (GET_CODE (x
) == REG
);
8816 if (GET_MODE (x
) == DImode
)
8817 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
8819 if (flag_expensive_optimizations
8820 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
8826 insn
= get_last_insn_anywhere ();
8831 while ((insn
= PREV_INSN (insn
)))
8833 switch (GET_CODE (insn
))
8846 rtx pat
= PATTERN (insn
);
8847 if (GET_CODE (pat
) != SET
)
8849 if (rtx_equal_p (x
, SET_DEST (pat
)))
8850 return set_extends (insn
);
8851 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
8852 return set_extends (insn
);
8853 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8861 /* Returns assembly code to perform a DImode shift using
8862 a 64-bit global or out register on SPARC-V8+. */
8864 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
8866 static char asm_code
[60];
8868 /* The scratch register is only required when the destination
8869 register is not a 64-bit global or out register. */
8870 if (which_alternative
!= 2)
8871 operands
[3] = operands
[0];
8873 /* We can only shift by constants <= 63. */
8874 if (GET_CODE (operands
[2]) == CONST_INT
)
8875 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
8877 if (GET_CODE (operands
[1]) == CONST_INT
)
8879 output_asm_insn ("mov\t%1, %3", operands
);
8883 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8884 if (sparc_check_64 (operands
[1], insn
) <= 0)
8885 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8886 output_asm_insn ("or\t%L1, %3, %3", operands
);
8889 strcpy(asm_code
, opcode
);
8891 if (which_alternative
!= 2)
8892 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8894 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8897 /* Output rtl to increment the profiler label LABELNO
8898 for profiling a function entry. */
8901 sparc_profile_hook (int labelno
)
8906 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8907 if (NO_PROFILE_COUNTERS
)
8909 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
8913 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8914 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8915 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8919 #ifdef TARGET_SOLARIS
8920 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8923 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
8924 tree decl ATTRIBUTE_UNUSED
)
8926 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
8928 solaris_elf_asm_comdat_section (name
, flags
, decl
);
8932 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8934 if (!(flags
& SECTION_DEBUG
))
8935 fputs (",#alloc", asm_out_file
);
8936 if (flags
& SECTION_WRITE
)
8937 fputs (",#write", asm_out_file
);
8938 if (flags
& SECTION_TLS
)
8939 fputs (",#tls", asm_out_file
);
8940 if (flags
& SECTION_CODE
)
8941 fputs (",#execinstr", asm_out_file
);
8943 /* ??? Handle SECTION_BSS. */
8945 fputc ('\n', asm_out_file
);
8947 #endif /* TARGET_SOLARIS */
8949 /* We do not allow indirect calls to be optimized into sibling calls.
8951 We cannot use sibling calls when delayed branches are disabled
8952 because they will likely require the call delay slot to be filled.
8954 Also, on SPARC 32-bit we cannot emit a sibling call when the
8955 current function returns a structure. This is because the "unimp
8956 after call" convention would cause the callee to return to the
8957 wrong place. The generic code already disallows cases where the
8958 function being called returns a structure.
8960 It may seem strange how this last case could occur. Usually there
8961 is code after the call which jumps to epilogue code which dumps the
8962 return value into the struct return area. That ought to invalidate
8963 the sibling call right? Well, in the C++ case we can end up passing
8964 the pointer to the struct return area to a constructor (which returns
8965 void) and then nothing else happens. Such a sibling call would look
8966 valid without the added check here.
8968 VxWorks PIC PLT entries require the global pointer to be initialized
8969 on entry. We therefore can't emit sibling calls to them. */
8971 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
8974 && flag_delayed_branch
8975 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
8976 && !(TARGET_VXWORKS_RTP
8978 && !targetm
.binds_local_p (decl
)));
8981 /* libfunc renaming. */
8984 sparc_init_libfuncs (void)
8988 /* Use the subroutines that Sun's library provides for integer
8989 multiply and divide. The `*' prevents an underscore from
8990 being prepended by the compiler. .umul is a little faster
8992 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
8993 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
8994 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
8995 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
8996 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
8998 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8999 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9000 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9001 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9002 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9003 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9005 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9006 is because with soft-float, the SFmode and DFmode sqrt
9007 instructions will be absent, and the compiler will notice and
9008 try to use the TFmode sqrt instruction for calls to the
9009 builtin function sqrt, but this fails. */
9011 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9013 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9014 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9015 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9016 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9017 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9018 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9020 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9021 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9022 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9023 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9025 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9026 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9027 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9028 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9030 if (DITF_CONVERSION_LIBFUNCS
)
9032 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9033 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9034 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9035 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9038 if (SUN_CONVERSION_LIBFUNCS
)
9040 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9041 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9042 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9043 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9048 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9049 do not exist in the library. Make sure the compiler does not
9050 emit calls to them by accident. (It should always use the
9051 hardware instructions.) */
9052 set_optab_libfunc (smul_optab
, SImode
, 0);
9053 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9054 set_optab_libfunc (udiv_optab
, SImode
, 0);
9055 set_optab_libfunc (smod_optab
, SImode
, 0);
9056 set_optab_libfunc (umod_optab
, SImode
, 0);
9058 if (SUN_INTEGER_MULTIPLY_64
)
9060 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9061 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9062 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9063 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9064 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9067 if (SUN_CONVERSION_LIBFUNCS
)
9069 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9070 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9071 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9072 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9077 #define def_builtin(NAME, CODE, TYPE) \
9078 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
9081 /* Implement the TARGET_INIT_BUILTINS target hook.
9082 Create builtin functions for special SPARC instructions. */
9085 sparc_init_builtins (void)
9088 sparc_vis_init_builtins ();
9091 /* Create builtin functions for VIS 1.0 instructions. */
9094 sparc_vis_init_builtins (void)
9096 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9097 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9098 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9099 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9100 tree v2si
= build_vector_type (intSI_type_node
, 2);
9102 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9103 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9104 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9105 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9106 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9107 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9108 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9109 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9110 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9111 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9112 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9113 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9114 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9116 intDI_type_node
, 0);
9117 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9119 intDI_type_node
, 0);
9120 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9122 intSI_type_node
, 0);
9123 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9125 intDI_type_node
, 0);
9127 /* Packing and expanding vectors. */
9128 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
, v4qi_ftype_v4hi
);
9129 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9130 v8qi_ftype_v2si_v8qi
);
9131 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9133 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
, v4hi_ftype_v4qi
);
9134 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9135 v8qi_ftype_v4qi_v4qi
);
9137 /* Multiplications. */
9138 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9139 v4hi_ftype_v4qi_v4hi
);
9140 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9141 v4hi_ftype_v4qi_v2hi
);
9142 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9143 v4hi_ftype_v4qi_v2hi
);
9144 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9145 v4hi_ftype_v8qi_v4hi
);
9146 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9147 v4hi_ftype_v8qi_v4hi
);
9148 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9149 v2si_ftype_v4qi_v2hi
);
9150 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9151 v2si_ftype_v4qi_v2hi
);
9153 /* Data aligning. */
9154 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9155 v4hi_ftype_v4hi_v4hi
);
9156 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9157 v8qi_ftype_v8qi_v8qi
);
9158 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9159 v2si_ftype_v2si_v2si
);
9160 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
9163 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9166 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9169 /* Pixel distance. */
9170 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9171 di_ftype_v8qi_v8qi_di
);
9173 /* Edge handling. */
9174 def_builtin ("__builtin_vis_edge8", CODE_FOR_edge8_vis
,
9176 def_builtin ("__builtin_vis_edge8l", CODE_FOR_edge8l_vis
,
9178 def_builtin ("__builtin_vis_edge16", CODE_FOR_edge16_vis
,
9180 def_builtin ("__builtin_vis_edge16l", CODE_FOR_edge16l_vis
,
9182 def_builtin ("__builtin_vis_edge32", CODE_FOR_edge32_vis
,
9184 def_builtin ("__builtin_vis_edge32l", CODE_FOR_edge32l_vis
,
9188 /* Handle TARGET_EXPAND_BUILTIN target hook.
9189 Expand builtin functions for sparc intrinsics. */
9192 sparc_expand_builtin (tree exp
, rtx target
,
9193 rtx subtarget ATTRIBUTE_UNUSED
,
9194 enum machine_mode tmode ATTRIBUTE_UNUSED
,
9195 int ignore ATTRIBUTE_UNUSED
)
9198 call_expr_arg_iterator iter
;
9199 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9200 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
9202 enum machine_mode mode
[4];
9205 mode
[0] = insn_data
[icode
].operand
[0].mode
;
9207 || GET_MODE (target
) != mode
[0]
9208 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
[0]))
9209 op
[0] = gen_reg_rtx (mode
[0]);
9213 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9216 mode
[arg_count
] = insn_data
[icode
].operand
[arg_count
].mode
;
9217 op
[arg_count
] = expand_normal (arg
);
9219 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
9221 op
[arg_count
] = copy_to_mode_reg (mode
[arg_count
], op
[arg_count
]);
9227 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
9230 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
9233 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
9248 sparc_vis_mul8x16 (int e8
, int e16
)
9250 return (e8
* e16
+ 128) / 256;
9253 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9254 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9255 constants. A tree list with the results of the multiplications is returned,
9256 and each element in the list is of INNER_TYPE. */
9259 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
9261 tree n_elts
= NULL_TREE
;
9266 case CODE_FOR_fmul8x16_vis
:
9267 for (; elts0
&& elts1
;
9268 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9271 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9272 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
9273 n_elts
= tree_cons (NULL_TREE
,
9274 build_int_cst (inner_type
, val
),
9279 case CODE_FOR_fmul8x16au_vis
:
9280 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9282 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9285 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9287 n_elts
= tree_cons (NULL_TREE
,
9288 build_int_cst (inner_type
, val
),
9293 case CODE_FOR_fmul8x16al_vis
:
9294 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
9296 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9299 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9301 n_elts
= tree_cons (NULL_TREE
,
9302 build_int_cst (inner_type
, val
),
9311 return nreverse (n_elts
);
9314 /* Handle TARGET_FOLD_BUILTIN target hook.
9315 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9316 result of the function call is ignored. NULL_TREE is returned if the
9317 function could not be folded. */
9320 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
9321 tree
*args
, bool ignore
)
9323 tree arg0
, arg1
, arg2
;
9324 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
9325 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
9328 && icode
!= CODE_FOR_alignaddrsi_vis
9329 && icode
!= CODE_FOR_alignaddrdi_vis
)
9330 return build_zero_cst (rtype
);
9334 case CODE_FOR_fexpand_vis
:
9338 if (TREE_CODE (arg0
) == VECTOR_CST
)
9340 tree inner_type
= TREE_TYPE (rtype
);
9341 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
9342 tree n_elts
= NULL_TREE
;
9344 for (; elts
; elts
= TREE_CHAIN (elts
))
9346 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
9347 n_elts
= tree_cons (NULL_TREE
,
9348 build_int_cst (inner_type
, val
),
9351 return build_vector (rtype
, nreverse (n_elts
));
9355 case CODE_FOR_fmul8x16_vis
:
9356 case CODE_FOR_fmul8x16au_vis
:
9357 case CODE_FOR_fmul8x16al_vis
:
9363 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9365 tree inner_type
= TREE_TYPE (rtype
);
9366 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9367 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9368 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
9371 return build_vector (rtype
, n_elts
);
9375 case CODE_FOR_fpmerge_vis
:
9381 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9383 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9384 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9385 tree n_elts
= NULL_TREE
;
9387 for (; elts0
&& elts1
;
9388 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9390 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
9391 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
9394 return build_vector (rtype
, nreverse (n_elts
));
9398 case CODE_FOR_pdist_vis
:
9406 if (TREE_CODE (arg0
) == VECTOR_CST
9407 && TREE_CODE (arg1
) == VECTOR_CST
9408 && TREE_CODE (arg2
) == INTEGER_CST
)
9411 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
9412 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
9413 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9414 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9416 for (; elts0
&& elts1
;
9417 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9419 unsigned HOST_WIDE_INT
9420 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9421 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9422 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
9423 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
9425 unsigned HOST_WIDE_INT l
;
9428 overflow
|= neg_double (low1
, high1
, &l
, &h
);
9429 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
9431 overflow
|= neg_double (l
, h
, &l
, &h
);
9433 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
9436 gcc_assert (overflow
== 0);
9438 return build_int_cst_wide (rtype
, low
, high
);
9448 /* ??? This duplicates information provided to the compiler by the
9449 ??? scheduler description. Some day, teach genautomata to output
9450 ??? the latencies and then CSE will just use that. */
9453 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
9454 int *total
, bool speed ATTRIBUTE_UNUSED
)
9456 enum machine_mode mode
= GET_MODE (x
);
9457 bool float_mode_p
= FLOAT_MODE_P (mode
);
9462 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
9480 if (GET_MODE (x
) == VOIDmode
9481 && ((CONST_DOUBLE_HIGH (x
) == 0
9482 && CONST_DOUBLE_LOW (x
) < 0x1000)
9483 || (CONST_DOUBLE_HIGH (x
) == -1
9484 && CONST_DOUBLE_LOW (x
) < 0
9485 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
9492 /* If outer-code was a sign or zero extension, a cost
9493 of COSTS_N_INSNS (1) was already added in. This is
9494 why we are subtracting it back out. */
9495 if (outer_code
== ZERO_EXTEND
)
9497 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
9499 else if (outer_code
== SIGN_EXTEND
)
9501 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
9503 else if (float_mode_p
)
9505 *total
= sparc_costs
->float_load
;
9509 *total
= sparc_costs
->int_load
;
9517 *total
= sparc_costs
->float_plusminus
;
9519 *total
= COSTS_N_INSNS (1);
9524 *total
= sparc_costs
->float_mul
;
9525 else if (! TARGET_HARD_MUL
)
9526 *total
= COSTS_N_INSNS (25);
9532 if (sparc_costs
->int_mul_bit_factor
)
9536 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9538 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
9539 for (nbits
= 0; value
!= 0; value
&= value
- 1)
9542 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
9543 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
9545 rtx x1
= XEXP (x
, 1);
9546 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
9547 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
9549 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
9551 for (; value2
!= 0; value2
&= value2
- 1)
9559 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
9560 bit_cost
= COSTS_N_INSNS (bit_cost
);
9564 *total
= sparc_costs
->int_mulX
+ bit_cost
;
9566 *total
= sparc_costs
->int_mul
+ bit_cost
;
9573 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
9583 *total
= sparc_costs
->float_div_df
;
9585 *total
= sparc_costs
->float_div_sf
;
9590 *total
= sparc_costs
->int_divX
;
9592 *total
= sparc_costs
->int_div
;
9599 *total
= COSTS_N_INSNS (1);
9606 case UNSIGNED_FLOAT
:
9610 case FLOAT_TRUNCATE
:
9611 *total
= sparc_costs
->float_move
;
9616 *total
= sparc_costs
->float_sqrt_df
;
9618 *total
= sparc_costs
->float_sqrt_sf
;
9623 *total
= sparc_costs
->float_cmp
;
9625 *total
= COSTS_N_INSNS (1);
9630 *total
= sparc_costs
->float_cmove
;
9632 *total
= sparc_costs
->int_cmove
;
9636 /* Handle the NAND vector patterns. */
9637 if (sparc_vector_mode_supported_p (GET_MODE (x
))
9638 && GET_CODE (XEXP (x
, 0)) == NOT
9639 && GET_CODE (XEXP (x
, 1)) == NOT
)
9641 *total
= COSTS_N_INSNS (1);
9652 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
9655 general_or_i64_p (reg_class_t rclass
)
9657 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
9660 /* Implement TARGET_REGISTER_MOVE_COST. */
9663 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
9664 reg_class_t from
, reg_class_t to
)
9666 if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
9667 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
))
9668 || from
== FPCC_REGS
9671 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9672 || sparc_cpu
== PROCESSOR_ULTRASPARC3
9673 || sparc_cpu
== PROCESSOR_NIAGARA
9674 || sparc_cpu
== PROCESSOR_NIAGARA2
9675 || sparc_cpu
== PROCESSOR_NIAGARA3
9676 || sparc_cpu
== PROCESSOR_NIAGARA4
)
9685 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
9686 This is achieved by means of a manual dynamic stack space allocation in
9687 the current frame. We make the assumption that SEQ doesn't contain any
9688 function calls, with the possible exception of calls to the GOT helper. */
9691 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
9693 /* We must preserve the lowest 16 words for the register save area. */
9694 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
9695 /* We really need only 2 words of fresh stack space. */
9696 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
9699 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
9700 SPARC_STACK_BIAS
+ offset
));
9702 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
9703 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
9705 emit_insn (gen_rtx_SET (VOIDmode
,
9706 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
9710 emit_insn (gen_rtx_SET (VOIDmode
,
9712 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
9713 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
9714 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
9717 /* Output the assembler code for a thunk function. THUNK_DECL is the
9718 declaration for the thunk function itself, FUNCTION is the decl for
9719 the target function. DELTA is an immediate constant offset to be
9720 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9721 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9724 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
9725 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9728 rtx this_rtx
, insn
, funexp
;
9729 unsigned int int_arg_first
;
9731 reload_completed
= 1;
9732 epilogue_completed
= 1;
9734 emit_note (NOTE_INSN_PROLOGUE_END
);
9738 sparc_leaf_function_p
= 1;
9740 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9742 else if (flag_delayed_branch
)
9744 /* We will emit a regular sibcall below, so we need to instruct
9745 output_sibcall that we are in a leaf function. */
9746 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
9748 /* This will cause final.c to invoke leaf_renumber_regs so we
9749 must behave as if we were in a not-yet-leafified function. */
9750 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
9754 /* We will emit the sibcall manually below, so we will need to
9755 manually spill non-leaf registers. */
9756 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
9758 /* We really are in a leaf function. */
9759 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9762 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9763 returns a structure, the structure return pointer is there instead. */
9765 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9766 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
9768 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
9770 /* Add DELTA. When possible use a plain add, otherwise load it into
9771 a register first. */
9774 rtx delta_rtx
= GEN_INT (delta
);
9776 if (! SPARC_SIMM13_P (delta
))
9778 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9779 emit_move_insn (scratch
, delta_rtx
);
9780 delta_rtx
= scratch
;
9783 /* THIS_RTX += DELTA. */
9784 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
9787 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
9790 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
9791 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9793 gcc_assert (vcall_offset
< 0);
9795 /* SCRATCH = *THIS_RTX. */
9796 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
9798 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9799 may not have any available scratch register at this point. */
9800 if (SPARC_SIMM13_P (vcall_offset
))
9802 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9803 else if (! fixed_regs
[5]
9804 /* The below sequence is made up of at least 2 insns,
9805 while the default method may need only one. */
9806 && vcall_offset
< -8192)
9808 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
9809 emit_move_insn (scratch2
, vcall_offset_rtx
);
9810 vcall_offset_rtx
= scratch2
;
9814 rtx increment
= GEN_INT (-4096);
9816 /* VCALL_OFFSET is a negative number whose typical range can be
9817 estimated as -32768..0 in 32-bit mode. In almost all cases
9818 it is therefore cheaper to emit multiple add insns than
9819 spilling and loading the constant into a register (at least
9821 while (! SPARC_SIMM13_P (vcall_offset
))
9823 emit_insn (gen_add2_insn (scratch
, increment
));
9824 vcall_offset
+= 4096;
9826 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
9829 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
9830 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
9831 gen_rtx_PLUS (Pmode
,
9833 vcall_offset_rtx
)));
9835 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
9836 emit_insn (gen_add2_insn (this_rtx
, scratch
));
9839 /* Generate a tail call to the target function. */
9840 if (! TREE_USED (function
))
9842 assemble_external (function
);
9843 TREE_USED (function
) = 1;
9845 funexp
= XEXP (DECL_RTL (function
), 0);
9847 if (flag_delayed_branch
)
9849 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
9850 insn
= emit_call_insn (gen_sibcall (funexp
));
9851 SIBLING_CALL_P (insn
) = 1;
9855 /* The hoops we have to jump through in order to generate a sibcall
9856 without using delay slots... */
9857 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
9861 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
9863 load_got_register (); /* clobbers %o7 */
9864 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
9867 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
9869 else if (TARGET_ARCH32
)
9871 emit_insn (gen_rtx_SET (VOIDmode
,
9873 gen_rtx_HIGH (SImode
, funexp
)));
9874 emit_insn (gen_rtx_SET (VOIDmode
,
9876 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
9878 else /* TARGET_ARCH64 */
9880 switch (sparc_cmodel
)
9884 /* The destination can serve as a temporary. */
9885 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
9890 /* The destination cannot serve as a temporary. */
9891 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
9893 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
9896 emit_and_preserve (seq
, spill_reg
, 0);
9904 emit_jump_insn (gen_indirect_jump (scratch
));
9909 /* Run just enough of rest_of_compilation to get the insns emitted.
9910 There's not really enough bulk here to make other passes such as
9911 instruction scheduling worth while. Note that use_thunk calls
9912 assemble_start_function and assemble_end_function. */
9913 insn
= get_insns ();
9914 insn_locators_alloc ();
9915 shorten_branches (insn
);
9916 final_start_function (insn
, file
, 1);
9917 final (insn
, file
, 1);
9918 final_end_function ();
9920 reload_completed
= 0;
9921 epilogue_completed
= 0;
9924 /* Return true if sparc_output_mi_thunk would be able to output the
9925 assembler code for the thunk function specified by the arguments
9926 it is passed, and false otherwise. */
9928 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
9929 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
9930 HOST_WIDE_INT vcall_offset
,
9931 const_tree function ATTRIBUTE_UNUSED
)
9933 /* Bound the loop used in the default method above. */
9934 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
9937 /* How to allocate a 'struct machine_function'. */
9939 static struct machine_function
*
9940 sparc_init_machine_status (void)
9942 return ggc_alloc_cleared_machine_function ();
9945 /* Locate some local-dynamic symbol still in use by this function
9946 so that we can print its name in local-dynamic base patterns. */
9949 get_some_local_dynamic_name (void)
9953 if (cfun
->machine
->some_ld_name
)
9954 return cfun
->machine
->some_ld_name
;
9956 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9958 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
9959 return cfun
->machine
->some_ld_name
;
9965 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
9970 && GET_CODE (x
) == SYMBOL_REF
9971 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
9973 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
9980 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9981 We need to emit DTP-relative relocations. */
9984 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9989 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
9992 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
9997 output_addr_const (file
, x
);
10001 /* Do whatever processing is required at the end of a file. */
10004 sparc_file_end (void)
10006 /* If we need to emit the special GOT helper function, do so now. */
10007 if (got_helper_rtx
)
10009 const char *name
= XSTR (got_helper_rtx
, 0);
10010 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
10011 #ifdef DWARF2_UNWIND_INFO
10015 if (USE_HIDDEN_LINKONCE
)
10017 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
10018 get_identifier (name
),
10019 build_function_type_list (void_type_node
,
10021 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
10022 NULL_TREE
, void_type_node
);
10023 TREE_STATIC (decl
) = 1;
10024 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
10025 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
10026 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
10027 resolve_unique_section (decl
, 0, flag_function_sections
);
10028 allocate_struct_function (decl
, true);
10029 cfun
->is_thunk
= 1;
10030 current_function_decl
= decl
;
10031 init_varasm_status ();
10032 assemble_start_function (decl
, name
);
10036 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10037 switch_to_section (text_section
);
10039 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10040 ASM_OUTPUT_LABEL (asm_out_file
, name
);
10043 #ifdef DWARF2_UNWIND_INFO
10044 do_cfi
= dwarf2out_do_cfi_asm ();
10046 fprintf (asm_out_file
, "\t.cfi_startproc\n");
10048 if (flag_delayed_branch
)
10049 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10050 reg_name
, reg_name
);
10052 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10053 reg_name
, reg_name
);
10054 #ifdef DWARF2_UNWIND_INFO
10056 fprintf (asm_out_file
, "\t.cfi_endproc\n");
10060 if (NEED_INDICATE_EXEC_STACK
)
10061 file_end_indicate_exec_stack ();
10063 #ifdef TARGET_SOLARIS
10064 solaris_file_end ();
10068 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10069 /* Implement TARGET_MANGLE_TYPE. */
10071 static const char *
10072 sparc_mangle_type (const_tree type
)
10075 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
10076 && TARGET_LONG_DOUBLE_128
)
10079 /* For all other types, use normal C++ mangling. */
10084 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10085 compare and swap on the word containing the byte or half-word. */
10088 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
10090 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10091 rtx addr
= gen_reg_rtx (Pmode
);
10092 rtx off
= gen_reg_rtx (SImode
);
10093 rtx oldv
= gen_reg_rtx (SImode
);
10094 rtx newv
= gen_reg_rtx (SImode
);
10095 rtx oldvalue
= gen_reg_rtx (SImode
);
10096 rtx newvalue
= gen_reg_rtx (SImode
);
10097 rtx res
= gen_reg_rtx (SImode
);
10098 rtx resv
= gen_reg_rtx (SImode
);
10099 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
10101 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
10102 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10104 if (Pmode
!= SImode
)
10105 addr1
= gen_lowpart (SImode
, addr1
);
10106 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10107 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10109 memsi
= gen_rtx_MEM (SImode
, addr
);
10110 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10111 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10113 val
= force_reg (SImode
, memsi
);
10115 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10116 gen_rtx_XOR (SImode
, off
,
10117 GEN_INT (GET_MODE (mem
) == QImode
10120 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10121 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10123 if (GET_MODE (mem
) == QImode
)
10124 mask
= force_reg (SImode
, GEN_INT (0xff));
10126 mask
= force_reg (SImode
, GEN_INT (0xffff));
10128 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10129 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10131 emit_insn (gen_rtx_SET (VOIDmode
, val
,
10132 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10135 oldval
= gen_lowpart (SImode
, oldval
);
10136 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10137 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10139 newval
= gen_lowpart_common (SImode
, newval
);
10140 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10141 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10143 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10144 gen_rtx_AND (SImode
, oldv
, mask
)));
10146 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10147 gen_rtx_AND (SImode
, newv
, mask
)));
10149 end_label
= gen_label_rtx ();
10150 loop_label
= gen_label_rtx ();
10151 emit_label (loop_label
);
10153 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
10154 gen_rtx_IOR (SImode
, oldv
, val
)));
10156 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
10157 gen_rtx_IOR (SImode
, newv
, val
)));
10159 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
10161 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
10163 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
10164 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10167 cc
= gen_compare_reg_1 (NE
, resv
, val
);
10168 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
10170 /* Use cbranchcc4 to separate the compare and branch! */
10171 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
10172 cc
, const0_rtx
, loop_label
));
10174 emit_label (end_label
);
10176 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10177 gen_rtx_AND (SImode
, res
, mask
)));
10179 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10180 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10182 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10185 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10188 sparc_frame_pointer_required (void)
10190 /* If the stack pointer is dynamically modified in the function, it cannot
10191 serve as the frame pointer. */
10192 if (cfun
->calls_alloca
)
10195 /* If the function receives nonlocal gotos, it needs to save the frame
10196 pointer in the nonlocal_goto_save_area object. */
10197 if (cfun
->has_nonlocal_label
)
10200 /* In flat mode, that's it. */
10204 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10205 return !(current_function_is_leaf
&& only_leaf_regs_used ());
10208 /* The way this is structured, we can't eliminate SFP in favor of SP
10209 if the frame pointer is required: we want to use the SFP->HFP elimination
10210 in that case. But the test in update_eliminables doesn't know we are
10211 assuming below that we only do the former elimination. */
10214 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10216 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
10219 /* Return the hard frame pointer directly to bypass the stack bias. */
10222 sparc_builtin_setjmp_frame_value (void)
10224 return hard_frame_pointer_rtx
;
10227 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10228 they won't be allocated. */
10231 sparc_conditional_register_usage (void)
10233 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
10235 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10236 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10238 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10239 /* then honor it. */
10240 if (TARGET_ARCH32
&& fixed_regs
[5])
10242 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
10247 for (regno
= SPARC_FIRST_V9_FP_REG
;
10248 regno
<= SPARC_LAST_V9_FP_REG
;
10250 fixed_regs
[regno
] = 1;
10251 /* %fcc0 is used by v8 and v9. */
10252 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
10253 regno
<= SPARC_LAST_V9_FCC_REG
;
10255 fixed_regs
[regno
] = 1;
10260 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
10261 fixed_regs
[regno
] = 1;
10263 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10264 /* then honor it. Likewise with g3 and g4. */
10265 if (fixed_regs
[2] == 2)
10266 fixed_regs
[2] = ! TARGET_APP_REGS
;
10267 if (fixed_regs
[3] == 2)
10268 fixed_regs
[3] = ! TARGET_APP_REGS
;
10269 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
10270 fixed_regs
[4] = ! TARGET_APP_REGS
;
10271 else if (TARGET_CM_EMBMEDANY
)
10273 else if (fixed_regs
[4] == 2)
10278 /* Disable leaf functions. */
10279 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
10280 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
10281 leaf_reg_remap
[regno
] = regno
;
10285 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10287 - We can't load constants into FP registers.
10288 - We can't load FP constants into integer registers when soft-float,
10289 because there is no soft-float pattern with a r/F constraint.
10290 - We can't load FP constants into integer registers for TFmode unless
10291 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10292 - Try and reload integer constants (symbolic or otherwise) back into
10293 registers directly, rather than having them dumped to memory. */
10296 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
10298 if (CONSTANT_P (x
))
10300 if (FP_REG_CLASS_P (rclass
)
10301 || rclass
== GENERAL_OR_FP_REGS
10302 || rclass
== GENERAL_OR_EXTRA_FP_REGS
10303 || (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
&& ! TARGET_FPU
)
10304 || (GET_MODE (x
) == TFmode
&& ! const_zero_operand (x
, TFmode
)))
10307 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
10308 return GENERAL_REGS
;
10314 #include "gt-sparc.h"