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[gcc.git] / gcc / config / sparc / sparc.c
1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 at Cygnus Support.
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26 #include "config.h"
27 #include "system.h"
28 #include "coretypes.h"
29 #include "tm.h"
30 #include "tree.h"
31 #include "rtl.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
37 #include "output.h"
38 #include "insn-attr.h"
39 #include "flags.h"
40 #include "function.h"
41 #include "except.h"
42 #include "expr.h"
43 #include "optabs.h"
44 #include "recog.h"
45 #include "diagnostic-core.h"
46 #include "ggc.h"
47 #include "tm_p.h"
48 #include "debug.h"
49 #include "target.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
53 #include "gimple.h"
54 #include "langhooks.h"
55 #include "reload.h"
56 #include "params.h"
57 #include "df.h"
58 #include "dwarf2out.h"
59 #include "opts.h"
60
61 /* Processor costs */
62 static const
63 struct processor_costs cypress_costs = {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
84 };
85
86 static const
87 struct processor_costs supersparc_costs = {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
108 };
109
110 static const
111 struct processor_costs hypersparc_costs = {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
132 };
133
134 static const
135 struct processor_costs leon_costs = {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
156 };
157
158 static const
159 struct processor_costs sparclet_costs = {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
180 };
181
182 static const
183 struct processor_costs ultrasparc_costs = {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
204 };
205
206 static const
207 struct processor_costs ultrasparc3_costs = {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
228 };
229
230 static const
231 struct processor_costs niagara_costs = {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
252 };
253
254 static const
255 struct processor_costs niagara2_costs = {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
276 };
277
278 const struct processor_costs *sparc_costs = &cypress_costs;
279
280 #ifdef HAVE_AS_RELAX_OPTION
281 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
282 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
283 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
284 somebody does not branch between the sethi and jmp. */
285 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
286 #else
287 #define LEAF_SIBCALL_SLOT_RESERVED_P \
288 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
289 #endif
290
291 /* Vector to say how input registers are mapped to output registers.
292 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
293 eliminate it. You must use -fomit-frame-pointer to get that. */
294 char leaf_reg_remap[] =
295 { 0, 1, 2, 3, 4, 5, 6, 7,
296 -1, -1, -1, -1, -1, -1, 14, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 8, 9, 10, 11, 12, 13, -1, 15,
299
300 32, 33, 34, 35, 36, 37, 38, 39,
301 40, 41, 42, 43, 44, 45, 46, 47,
302 48, 49, 50, 51, 52, 53, 54, 55,
303 56, 57, 58, 59, 60, 61, 62, 63,
304 64, 65, 66, 67, 68, 69, 70, 71,
305 72, 73, 74, 75, 76, 77, 78, 79,
306 80, 81, 82, 83, 84, 85, 86, 87,
307 88, 89, 90, 91, 92, 93, 94, 95,
308 96, 97, 98, 99, 100};
309
310 /* Vector, indexed by hard register number, which contains 1
311 for a register that is allowable in a candidate for leaf
312 function treatment. */
313 char sparc_leaf_regs[] =
314 { 1, 1, 1, 1, 1, 1, 1, 1,
315 0, 0, 0, 0, 0, 0, 1, 0,
316 0, 0, 0, 0, 0, 0, 0, 0,
317 1, 1, 1, 1, 1, 1, 0, 1,
318 1, 1, 1, 1, 1, 1, 1, 1,
319 1, 1, 1, 1, 1, 1, 1, 1,
320 1, 1, 1, 1, 1, 1, 1, 1,
321 1, 1, 1, 1, 1, 1, 1, 1,
322 1, 1, 1, 1, 1, 1, 1, 1,
323 1, 1, 1, 1, 1, 1, 1, 1,
324 1, 1, 1, 1, 1, 1, 1, 1,
325 1, 1, 1, 1, 1, 1, 1, 1,
326 1, 1, 1, 1, 1};
327
328 struct GTY(()) machine_function
329 {
330 /* Size of the frame of the function. */
331 HOST_WIDE_INT frame_size;
332
333 /* Size of the frame of the function minus the register window save area
334 and the outgoing argument area. */
335 HOST_WIDE_INT apparent_frame_size;
336
337 /* Register we pretend the frame pointer is allocated to. Normally, this
338 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
339 record "offset" separately as it may be too big for (reg + disp). */
340 rtx frame_base_reg;
341 HOST_WIDE_INT frame_base_offset;
342
343 /* Some local-dynamic TLS symbol name. */
344 const char *some_ld_name;
345
346 /* Number of global or FP registers to be saved (as 4-byte quantities). */
347 int n_global_fp_regs;
348
349 /* True if the current function is leaf and uses only leaf regs,
350 so that the SPARC leaf function optimization can be applied.
351 Private version of current_function_uses_only_leaf_regs, see
352 sparc_expand_prologue for the rationale. */
353 int leaf_function_p;
354
355 /* True if the prologue saves local or in registers. */
356 bool save_local_in_regs_p;
357
358 /* True if the data calculated by sparc_expand_prologue are valid. */
359 bool prologue_data_valid_p;
360 };
361
362 #define sparc_frame_size cfun->machine->frame_size
363 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
364 #define sparc_frame_base_reg cfun->machine->frame_base_reg
365 #define sparc_frame_base_offset cfun->machine->frame_base_offset
366 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
367 #define sparc_leaf_function_p cfun->machine->leaf_function_p
368 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
369 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
370
371 /* 1 if the next opcode is to be specially indented. */
372 int sparc_indent_opcode = 0;
373
374 static void sparc_option_override (void);
375 static void sparc_init_modes (void);
376 static void scan_record_type (const_tree, int *, int *, int *);
377 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
378 const_tree, bool, bool, int *, int *);
379
380 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
381 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
382
383 static void sparc_emit_set_const32 (rtx, rtx);
384 static void sparc_emit_set_const64 (rtx, rtx);
385 static void sparc_output_addr_vec (rtx);
386 static void sparc_output_addr_diff_vec (rtx);
387 static void sparc_output_deferred_case_vectors (void);
388 static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
389 static bool sparc_legitimate_constant_p (enum machine_mode, rtx);
390 static rtx sparc_builtin_saveregs (void);
391 static int epilogue_renumber (rtx *, int);
392 static bool sparc_assemble_integer (rtx, unsigned int, int);
393 static int set_extends (rtx);
394 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
395 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
396 #ifdef TARGET_SOLARIS
397 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
398 tree) ATTRIBUTE_UNUSED;
399 #endif
400 static int sparc_adjust_cost (rtx, rtx, rtx, int);
401 static int sparc_issue_rate (void);
402 static void sparc_sched_init (FILE *, int, int);
403 static int sparc_use_sched_lookahead (void);
404
405 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
406 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
407 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
408 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
409 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
410
411 static bool sparc_function_ok_for_sibcall (tree, tree);
412 static void sparc_init_libfuncs (void);
413 static void sparc_init_builtins (void);
414 static void sparc_vis_init_builtins (void);
415 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
416 static tree sparc_fold_builtin (tree, int, tree *, bool);
417 static int sparc_vis_mul8x16 (int, int);
418 static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
419 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
420 HOST_WIDE_INT, tree);
421 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
422 HOST_WIDE_INT, const_tree);
423 static struct machine_function * sparc_init_machine_status (void);
424 static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
425 static rtx sparc_tls_get_addr (void);
426 static rtx sparc_tls_got (void);
427 static const char *get_some_local_dynamic_name (void);
428 static int get_some_local_dynamic_name_1 (rtx *, void *);
429 static int sparc_register_move_cost (enum machine_mode,
430 reg_class_t, reg_class_t);
431 static bool sparc_rtx_costs (rtx, int, int, int *, bool);
432 static rtx sparc_function_value (const_tree, const_tree, bool);
433 static rtx sparc_libcall_value (enum machine_mode, const_rtx);
434 static bool sparc_function_value_regno_p (const unsigned int);
435 static rtx sparc_struct_value_rtx (tree, int);
436 static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
437 int *, const_tree, int);
438 static bool sparc_return_in_memory (const_tree, const_tree);
439 static bool sparc_strict_argument_naming (cumulative_args_t);
440 static void sparc_va_start (tree, rtx);
441 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
442 static bool sparc_vector_mode_supported_p (enum machine_mode);
443 static bool sparc_tls_referenced_p (rtx);
444 static rtx sparc_legitimize_tls_address (rtx);
445 static rtx sparc_legitimize_pic_address (rtx, rtx);
446 static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
447 static rtx sparc_delegitimize_address (rtx);
448 static bool sparc_mode_dependent_address_p (const_rtx);
449 static bool sparc_pass_by_reference (cumulative_args_t,
450 enum machine_mode, const_tree, bool);
451 static void sparc_function_arg_advance (cumulative_args_t,
452 enum machine_mode, const_tree, bool);
453 static rtx sparc_function_arg_1 (cumulative_args_t,
454 enum machine_mode, const_tree, bool, bool);
455 static rtx sparc_function_arg (cumulative_args_t,
456 enum machine_mode, const_tree, bool);
457 static rtx sparc_function_incoming_arg (cumulative_args_t,
458 enum machine_mode, const_tree, bool);
459 static unsigned int sparc_function_arg_boundary (enum machine_mode,
460 const_tree);
461 static int sparc_arg_partial_bytes (cumulative_args_t,
462 enum machine_mode, tree, bool);
463 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
464 static void sparc_file_end (void);
465 static bool sparc_frame_pointer_required (void);
466 static bool sparc_can_eliminate (const int, const int);
467 static rtx sparc_builtin_setjmp_frame_value (void);
468 static void sparc_conditional_register_usage (void);
469 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
470 static const char *sparc_mangle_type (const_tree);
471 #endif
472 static void sparc_trampoline_init (rtx, tree, rtx);
473 static enum machine_mode sparc_preferred_simd_mode (enum machine_mode);
474 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
475 static bool sparc_print_operand_punct_valid_p (unsigned char);
476 static void sparc_print_operand (FILE *, rtx, int);
477 static void sparc_print_operand_address (FILE *, rtx);
478 \f
479 #ifdef SUBTARGET_ATTRIBUTE_TABLE
480 /* Table of valid machine attributes. */
481 static const struct attribute_spec sparc_attribute_table[] =
482 {
483 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
484 do_diagnostic } */
485 SUBTARGET_ATTRIBUTE_TABLE,
486 { NULL, 0, 0, false, false, false, NULL, false }
487 };
488 #endif
489 \f
490 /* Option handling. */
491
492 /* Parsed value. */
493 enum cmodel sparc_cmodel;
494
495 char sparc_hard_reg_printed[8];
496
497 /* Initialize the GCC target structure. */
498
499 /* The default is to use .half rather than .short for aligned HI objects. */
500 #undef TARGET_ASM_ALIGNED_HI_OP
501 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
502
503 #undef TARGET_ASM_UNALIGNED_HI_OP
504 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
505 #undef TARGET_ASM_UNALIGNED_SI_OP
506 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
507 #undef TARGET_ASM_UNALIGNED_DI_OP
508 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
509
510 /* The target hook has to handle DI-mode values. */
511 #undef TARGET_ASM_INTEGER
512 #define TARGET_ASM_INTEGER sparc_assemble_integer
513
514 #undef TARGET_ASM_FUNCTION_PROLOGUE
515 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
516 #undef TARGET_ASM_FUNCTION_EPILOGUE
517 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
518
519 #undef TARGET_SCHED_ADJUST_COST
520 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
521 #undef TARGET_SCHED_ISSUE_RATE
522 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
523 #undef TARGET_SCHED_INIT
524 #define TARGET_SCHED_INIT sparc_sched_init
525 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
526 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
527
528 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
529 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
530
531 #undef TARGET_INIT_LIBFUNCS
532 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
533 #undef TARGET_INIT_BUILTINS
534 #define TARGET_INIT_BUILTINS sparc_init_builtins
535
536 #undef TARGET_LEGITIMIZE_ADDRESS
537 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
538 #undef TARGET_DELEGITIMIZE_ADDRESS
539 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
540 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
541 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
542
543 #undef TARGET_EXPAND_BUILTIN
544 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
545 #undef TARGET_FOLD_BUILTIN
546 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
547
548 #if TARGET_TLS
549 #undef TARGET_HAVE_TLS
550 #define TARGET_HAVE_TLS true
551 #endif
552
553 #undef TARGET_CANNOT_FORCE_CONST_MEM
554 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
555
556 #undef TARGET_ASM_OUTPUT_MI_THUNK
557 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
558 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
559 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
560
561 #undef TARGET_RTX_COSTS
562 #define TARGET_RTX_COSTS sparc_rtx_costs
563 #undef TARGET_ADDRESS_COST
564 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
565 #undef TARGET_REGISTER_MOVE_COST
566 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
567
568 #undef TARGET_PROMOTE_FUNCTION_MODE
569 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
570
571 #undef TARGET_FUNCTION_VALUE
572 #define TARGET_FUNCTION_VALUE sparc_function_value
573 #undef TARGET_LIBCALL_VALUE
574 #define TARGET_LIBCALL_VALUE sparc_libcall_value
575 #undef TARGET_FUNCTION_VALUE_REGNO_P
576 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
577
578 #undef TARGET_STRUCT_VALUE_RTX
579 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
580 #undef TARGET_RETURN_IN_MEMORY
581 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
582 #undef TARGET_MUST_PASS_IN_STACK
583 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
584 #undef TARGET_PASS_BY_REFERENCE
585 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
586 #undef TARGET_ARG_PARTIAL_BYTES
587 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
588 #undef TARGET_FUNCTION_ARG_ADVANCE
589 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
590 #undef TARGET_FUNCTION_ARG
591 #define TARGET_FUNCTION_ARG sparc_function_arg
592 #undef TARGET_FUNCTION_INCOMING_ARG
593 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
594 #undef TARGET_FUNCTION_ARG_BOUNDARY
595 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
596
597 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
598 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
599 #undef TARGET_STRICT_ARGUMENT_NAMING
600 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
601
602 #undef TARGET_EXPAND_BUILTIN_VA_START
603 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
604 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
605 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
606
607 #undef TARGET_VECTOR_MODE_SUPPORTED_P
608 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
609
610 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
611 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
612
613 #ifdef SUBTARGET_INSERT_ATTRIBUTES
614 #undef TARGET_INSERT_ATTRIBUTES
615 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
616 #endif
617
618 #ifdef SUBTARGET_ATTRIBUTE_TABLE
619 #undef TARGET_ATTRIBUTE_TABLE
620 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
621 #endif
622
623 #undef TARGET_RELAXED_ORDERING
624 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
625
626 #undef TARGET_OPTION_OVERRIDE
627 #define TARGET_OPTION_OVERRIDE sparc_option_override
628
629 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
630 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
631 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
632 #endif
633
634 #undef TARGET_ASM_FILE_END
635 #define TARGET_ASM_FILE_END sparc_file_end
636
637 #undef TARGET_FRAME_POINTER_REQUIRED
638 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
639
640 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
641 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
642
643 #undef TARGET_CAN_ELIMINATE
644 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
645
646 #undef TARGET_PREFERRED_RELOAD_CLASS
647 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
648
649 #undef TARGET_CONDITIONAL_REGISTER_USAGE
650 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
651
652 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
653 #undef TARGET_MANGLE_TYPE
654 #define TARGET_MANGLE_TYPE sparc_mangle_type
655 #endif
656
657 #undef TARGET_LEGITIMATE_ADDRESS_P
658 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
659
660 #undef TARGET_LEGITIMATE_CONSTANT_P
661 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
662
663 #undef TARGET_TRAMPOLINE_INIT
664 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
665
666 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
667 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
668 #undef TARGET_PRINT_OPERAND
669 #define TARGET_PRINT_OPERAND sparc_print_operand
670 #undef TARGET_PRINT_OPERAND_ADDRESS
671 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
672
673 struct gcc_target targetm = TARGET_INITIALIZER;
674
675 /* Validate and override various options, and do some machine dependent
676 initialization. */
677
678 static void
679 sparc_option_override (void)
680 {
681 static struct code_model {
682 const char *const name;
683 const enum cmodel value;
684 } const cmodels[] = {
685 { "32", CM_32 },
686 { "medlow", CM_MEDLOW },
687 { "medmid", CM_MEDMID },
688 { "medany", CM_MEDANY },
689 { "embmedany", CM_EMBMEDANY },
690 { NULL, (enum cmodel) 0 }
691 };
692 const struct code_model *cmodel;
693 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
694 static struct cpu_default {
695 const int cpu;
696 const enum processor_type processor;
697 } const cpu_default[] = {
698 /* There must be one entry here for each TARGET_CPU value. */
699 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
700 { TARGET_CPU_v8, PROCESSOR_V8 },
701 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
702 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
703 { TARGET_CPU_leon, PROCESSOR_LEON },
704 { TARGET_CPU_sparclite, PROCESSOR_F930 },
705 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
706 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
707 { TARGET_CPU_v9, PROCESSOR_V9 },
708 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
709 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
710 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
711 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
712 { -1, PROCESSOR_V7 }
713 };
714 const struct cpu_default *def;
715 /* Table of values for -m{cpu,tune}=. This must match the order of
716 the PROCESSOR_* enumeration. */
717 static struct cpu_table {
718 const int disable;
719 const int enable;
720 } const cpu_table[] = {
721 { MASK_ISA, 0 },
722 { MASK_ISA, 0 },
723 { MASK_ISA, MASK_V8 },
724 /* TI TMS390Z55 supersparc */
725 { MASK_ISA, MASK_V8 },
726 { MASK_ISA, MASK_V8|MASK_FPU },
727 /* LEON */
728 { MASK_ISA, MASK_V8|MASK_FPU },
729 { MASK_ISA, MASK_SPARCLITE },
730 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
731 { MASK_ISA|MASK_FPU, MASK_SPARCLITE },
732 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
733 { MASK_ISA, MASK_SPARCLITE|MASK_FPU },
734 { MASK_ISA|MASK_FPU, MASK_SPARCLITE },
735 { MASK_ISA, MASK_SPARCLET },
736 /* TEMIC sparclet */
737 { MASK_ISA, MASK_SPARCLET },
738 { MASK_ISA, MASK_V9 },
739 /* UltraSPARC I, II, IIi */
740 { MASK_ISA,
741 /* Although insns using %y are deprecated, it is a clear win. */
742 MASK_V9|MASK_DEPRECATED_V8_INSNS},
743 /* UltraSPARC III */
744 /* ??? Check if %y issue still holds true. */
745 { MASK_ISA,
746 MASK_V9|MASK_DEPRECATED_V8_INSNS},
747 /* UltraSPARC T1 */
748 { MASK_ISA,
749 MASK_V9|MASK_DEPRECATED_V8_INSNS},
750 /* UltraSPARC T2 */
751 { MASK_ISA, MASK_V9},
752 };
753 const struct cpu_table *cpu;
754 unsigned int i;
755 int fpu;
756
757 #ifdef SUBTARGET_OVERRIDE_OPTIONS
758 SUBTARGET_OVERRIDE_OPTIONS;
759 #endif
760
761 #ifndef SPARC_BI_ARCH
762 /* Check for unsupported architecture size. */
763 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
764 error ("%s is not supported by this configuration",
765 DEFAULT_ARCH32_P ? "-m64" : "-m32");
766 #endif
767
768 /* We force all 64bit archs to use 128 bit long double */
769 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
770 {
771 error ("-mlong-double-64 not allowed with -m64");
772 target_flags |= MASK_LONG_DOUBLE_128;
773 }
774
775 /* Code model selection. */
776 sparc_cmodel = SPARC_DEFAULT_CMODEL;
777
778 #ifdef SPARC_BI_ARCH
779 if (TARGET_ARCH32)
780 sparc_cmodel = CM_32;
781 #endif
782
783 if (sparc_cmodel_string != NULL)
784 {
785 if (TARGET_ARCH64)
786 {
787 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
788 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
789 break;
790 if (cmodel->name == NULL)
791 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
792 else
793 sparc_cmodel = cmodel->value;
794 }
795 else
796 error ("-mcmodel= is not supported on 32 bit systems");
797 }
798
799 /* Check that -fcall-saved-REG wasn't specified for out registers. */
800 for (i = 8; i < 16; i++)
801 if (!call_used_regs [i])
802 {
803 error ("-fcall-saved-REG is not supported for out registers");
804 call_used_regs [i] = 1;
805 }
806
807 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
808
809 /* Set the default CPU. */
810 if (!global_options_set.x_sparc_cpu_and_features)
811 {
812 for (def = &cpu_default[0]; def->cpu != -1; ++def)
813 if (def->cpu == TARGET_CPU_DEFAULT)
814 break;
815 gcc_assert (def->cpu != -1);
816 sparc_cpu_and_features = def->processor;
817 }
818 if (!global_options_set.x_sparc_cpu)
819 sparc_cpu = sparc_cpu_and_features;
820
821 cpu = &cpu_table[(int) sparc_cpu_and_features];
822 target_flags &= ~cpu->disable;
823 target_flags |= cpu->enable;
824
825 /* If -mfpu or -mno-fpu was explicitly used, don't override with
826 the processor default. */
827 if (target_flags_explicit & MASK_FPU)
828 target_flags = (target_flags & ~MASK_FPU) | fpu;
829
830 /* Don't allow -mvis if FPU is disabled. */
831 if (! TARGET_FPU)
832 target_flags &= ~MASK_VIS;
833
834 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
835 are available.
836 -m64 also implies v9. */
837 if (TARGET_VIS || TARGET_ARCH64)
838 {
839 target_flags |= MASK_V9;
840 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
841 }
842
843 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
844 if (TARGET_V9 && TARGET_ARCH32)
845 target_flags |= MASK_DEPRECATED_V8_INSNS;
846
847 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
848 if (! TARGET_V9 || TARGET_ARCH64)
849 target_flags &= ~MASK_V8PLUS;
850
851 /* Don't use stack biasing in 32 bit mode. */
852 if (TARGET_ARCH32)
853 target_flags &= ~MASK_STACK_BIAS;
854
855 /* Supply a default value for align_functions. */
856 if (align_functions == 0
857 && (sparc_cpu == PROCESSOR_ULTRASPARC
858 || sparc_cpu == PROCESSOR_ULTRASPARC3
859 || sparc_cpu == PROCESSOR_NIAGARA
860 || sparc_cpu == PROCESSOR_NIAGARA2))
861 align_functions = 32;
862
863 /* Validate PCC_STRUCT_RETURN. */
864 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
865 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
866
867 /* Only use .uaxword when compiling for a 64-bit target. */
868 if (!TARGET_ARCH64)
869 targetm.asm_out.unaligned_op.di = NULL;
870
871 /* Do various machine dependent initializations. */
872 sparc_init_modes ();
873
874 /* Set up function hooks. */
875 init_machine_status = sparc_init_machine_status;
876
877 switch (sparc_cpu)
878 {
879 case PROCESSOR_V7:
880 case PROCESSOR_CYPRESS:
881 sparc_costs = &cypress_costs;
882 break;
883 case PROCESSOR_V8:
884 case PROCESSOR_SPARCLITE:
885 case PROCESSOR_SUPERSPARC:
886 sparc_costs = &supersparc_costs;
887 break;
888 case PROCESSOR_F930:
889 case PROCESSOR_F934:
890 case PROCESSOR_HYPERSPARC:
891 case PROCESSOR_SPARCLITE86X:
892 sparc_costs = &hypersparc_costs;
893 break;
894 case PROCESSOR_LEON:
895 sparc_costs = &leon_costs;
896 break;
897 case PROCESSOR_SPARCLET:
898 case PROCESSOR_TSC701:
899 sparc_costs = &sparclet_costs;
900 break;
901 case PROCESSOR_V9:
902 case PROCESSOR_ULTRASPARC:
903 sparc_costs = &ultrasparc_costs;
904 break;
905 case PROCESSOR_ULTRASPARC3:
906 sparc_costs = &ultrasparc3_costs;
907 break;
908 case PROCESSOR_NIAGARA:
909 sparc_costs = &niagara_costs;
910 break;
911 case PROCESSOR_NIAGARA2:
912 sparc_costs = &niagara2_costs;
913 break;
914 };
915
916 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
917 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
918 target_flags |= MASK_LONG_DOUBLE_128;
919 #endif
920
921 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
922 ((sparc_cpu == PROCESSOR_ULTRASPARC
923 || sparc_cpu == PROCESSOR_NIAGARA
924 || sparc_cpu == PROCESSOR_NIAGARA2)
925 ? 2
926 : (sparc_cpu == PROCESSOR_ULTRASPARC3
927 ? 8 : 3)),
928 global_options.x_param_values,
929 global_options_set.x_param_values);
930 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
931 ((sparc_cpu == PROCESSOR_ULTRASPARC
932 || sparc_cpu == PROCESSOR_ULTRASPARC3
933 || sparc_cpu == PROCESSOR_NIAGARA
934 || sparc_cpu == PROCESSOR_NIAGARA2)
935 ? 64 : 32),
936 global_options.x_param_values,
937 global_options_set.x_param_values);
938
939 /* Disable save slot sharing for call-clobbered registers by default.
940 The IRA sharing algorithm works on single registers only and this
941 pessimizes for double floating-point registers. */
942 if (!global_options_set.x_flag_ira_share_save_slots)
943 flag_ira_share_save_slots = 0;
944 }
945 \f
946 /* Miscellaneous utilities. */
947
948 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
949 or branch on register contents instructions. */
950
951 int
952 v9_regcmp_p (enum rtx_code code)
953 {
954 return (code == EQ || code == NE || code == GE || code == LT
955 || code == LE || code == GT);
956 }
957
958 /* Nonzero if OP is a floating point constant which can
959 be loaded into an integer register using a single
960 sethi instruction. */
961
962 int
963 fp_sethi_p (rtx op)
964 {
965 if (GET_CODE (op) == CONST_DOUBLE)
966 {
967 REAL_VALUE_TYPE r;
968 long i;
969
970 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
971 REAL_VALUE_TO_TARGET_SINGLE (r, i);
972 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
973 }
974
975 return 0;
976 }
977
978 /* Nonzero if OP is a floating point constant which can
979 be loaded into an integer register using a single
980 mov instruction. */
981
982 int
983 fp_mov_p (rtx op)
984 {
985 if (GET_CODE (op) == CONST_DOUBLE)
986 {
987 REAL_VALUE_TYPE r;
988 long i;
989
990 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
991 REAL_VALUE_TO_TARGET_SINGLE (r, i);
992 return SPARC_SIMM13_P (i);
993 }
994
995 return 0;
996 }
997
998 /* Nonzero if OP is a floating point constant which can
999 be loaded into an integer register using a high/losum
1000 instruction sequence. */
1001
1002 int
1003 fp_high_losum_p (rtx op)
1004 {
1005 /* The constraints calling this should only be in
1006 SFmode move insns, so any constant which cannot
1007 be moved using a single insn will do. */
1008 if (GET_CODE (op) == CONST_DOUBLE)
1009 {
1010 REAL_VALUE_TYPE r;
1011 long i;
1012
1013 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1014 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1015 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
1016 }
1017
1018 return 0;
1019 }
1020
1021 /* Return true if the address of LABEL can be loaded by means of the
1022 mov{si,di}_pic_label_ref patterns in PIC mode. */
1023
1024 static bool
1025 can_use_mov_pic_label_ref (rtx label)
1026 {
1027 /* VxWorks does not impose a fixed gap between segments; the run-time
1028 gap can be different from the object-file gap. We therefore can't
1029 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1030 are absolutely sure that X is in the same segment as the GOT.
1031 Unfortunately, the flexibility of linker scripts means that we
1032 can't be sure of that in general, so assume that GOT-relative
1033 accesses are never valid on VxWorks. */
1034 if (TARGET_VXWORKS_RTP)
1035 return false;
1036
1037 /* Similarly, if the label is non-local, it might end up being placed
1038 in a different section than the current one; now mov_pic_label_ref
1039 requires the label and the code to be in the same section. */
1040 if (LABEL_REF_NONLOCAL_P (label))
1041 return false;
1042
1043 /* Finally, if we are reordering basic blocks and partition into hot
1044 and cold sections, this might happen for any label. */
1045 if (flag_reorder_blocks_and_partition)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 /* Expand a move instruction. Return true if all work is done. */
1052
1053 bool
1054 sparc_expand_move (enum machine_mode mode, rtx *operands)
1055 {
1056 /* Handle sets of MEM first. */
1057 if (GET_CODE (operands[0]) == MEM)
1058 {
1059 /* 0 is a register (or a pair of registers) on SPARC. */
1060 if (register_or_zero_operand (operands[1], mode))
1061 return false;
1062
1063 if (!reload_in_progress)
1064 {
1065 operands[0] = validize_mem (operands[0]);
1066 operands[1] = force_reg (mode, operands[1]);
1067 }
1068 }
1069
1070 /* Fixup TLS cases. */
1071 if (TARGET_HAVE_TLS
1072 && CONSTANT_P (operands[1])
1073 && sparc_tls_referenced_p (operands [1]))
1074 {
1075 operands[1] = sparc_legitimize_tls_address (operands[1]);
1076 return false;
1077 }
1078
1079 /* Fixup PIC cases. */
1080 if (flag_pic && CONSTANT_P (operands[1]))
1081 {
1082 if (pic_address_needs_scratch (operands[1]))
1083 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
1084
1085 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1086 if (GET_CODE (operands[1]) == LABEL_REF
1087 && can_use_mov_pic_label_ref (operands[1]))
1088 {
1089 if (mode == SImode)
1090 {
1091 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1092 return true;
1093 }
1094
1095 if (mode == DImode)
1096 {
1097 gcc_assert (TARGET_ARCH64);
1098 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1099 return true;
1100 }
1101 }
1102
1103 if (symbolic_operand (operands[1], mode))
1104 {
1105 operands[1]
1106 = sparc_legitimize_pic_address (operands[1],
1107 reload_in_progress
1108 ? operands[0] : NULL_RTX);
1109 return false;
1110 }
1111 }
1112
1113 /* If we are trying to toss an integer constant into FP registers,
1114 or loading a FP or vector constant, force it into memory. */
1115 if (CONSTANT_P (operands[1])
1116 && REG_P (operands[0])
1117 && (SPARC_FP_REG_P (REGNO (operands[0]))
1118 || SCALAR_FLOAT_MODE_P (mode)
1119 || VECTOR_MODE_P (mode)))
1120 {
1121 /* emit_group_store will send such bogosity to us when it is
1122 not storing directly into memory. So fix this up to avoid
1123 crashes in output_constant_pool. */
1124 if (operands [1] == const0_rtx)
1125 operands[1] = CONST0_RTX (mode);
1126
1127 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1128 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1129 && const_zero_operand (operands[1], mode))
1130 return false;
1131
1132 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1133 /* We are able to build any SF constant in integer registers
1134 with at most 2 instructions. */
1135 && (mode == SFmode
1136 /* And any DF constant in integer registers. */
1137 || (mode == DFmode
1138 && (reload_completed || reload_in_progress))))
1139 return false;
1140
1141 operands[1] = force_const_mem (mode, operands[1]);
1142 if (!reload_in_progress)
1143 operands[1] = validize_mem (operands[1]);
1144 return false;
1145 }
1146
1147 /* Accept non-constants and valid constants unmodified. */
1148 if (!CONSTANT_P (operands[1])
1149 || GET_CODE (operands[1]) == HIGH
1150 || input_operand (operands[1], mode))
1151 return false;
1152
1153 switch (mode)
1154 {
1155 case QImode:
1156 /* All QImode constants require only one insn, so proceed. */
1157 break;
1158
1159 case HImode:
1160 case SImode:
1161 sparc_emit_set_const32 (operands[0], operands[1]);
1162 return true;
1163
1164 case DImode:
1165 /* input_operand should have filtered out 32-bit mode. */
1166 sparc_emit_set_const64 (operands[0], operands[1]);
1167 return true;
1168
1169 default:
1170 gcc_unreachable ();
1171 }
1172
1173 return false;
1174 }
1175
1176 /* Load OP1, a 32-bit constant, into OP0, a register.
1177 We know it can't be done in one insn when we get
1178 here, the move expander guarantees this. */
1179
1180 static void
1181 sparc_emit_set_const32 (rtx op0, rtx op1)
1182 {
1183 enum machine_mode mode = GET_MODE (op0);
1184 rtx temp;
1185
1186 if (reload_in_progress || reload_completed)
1187 temp = op0;
1188 else
1189 temp = gen_reg_rtx (mode);
1190
1191 if (GET_CODE (op1) == CONST_INT)
1192 {
1193 gcc_assert (!small_int_operand (op1, mode)
1194 && !const_high_operand (op1, mode));
1195
1196 /* Emit them as real moves instead of a HIGH/LO_SUM,
1197 this way CSE can see everything and reuse intermediate
1198 values if it wants. */
1199 emit_insn (gen_rtx_SET (VOIDmode, temp,
1200 GEN_INT (INTVAL (op1)
1201 & ~(HOST_WIDE_INT)0x3ff)));
1202
1203 emit_insn (gen_rtx_SET (VOIDmode,
1204 op0,
1205 gen_rtx_IOR (mode, temp,
1206 GEN_INT (INTVAL (op1) & 0x3ff))));
1207 }
1208 else
1209 {
1210 /* A symbol, emit in the traditional way. */
1211 emit_insn (gen_rtx_SET (VOIDmode, temp,
1212 gen_rtx_HIGH (mode, op1)));
1213 emit_insn (gen_rtx_SET (VOIDmode,
1214 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1215 }
1216 }
1217
1218 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1219 If TEMP is nonzero, we are forbidden to use any other scratch
1220 registers. Otherwise, we are allowed to generate them as needed.
1221
1222 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1223 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1224
1225 void
1226 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1227 {
1228 rtx temp1, temp2, temp3, temp4, temp5;
1229 rtx ti_temp = 0;
1230
1231 if (temp && GET_MODE (temp) == TImode)
1232 {
1233 ti_temp = temp;
1234 temp = gen_rtx_REG (DImode, REGNO (temp));
1235 }
1236
1237 /* SPARC-V9 code-model support. */
1238 switch (sparc_cmodel)
1239 {
1240 case CM_MEDLOW:
1241 /* The range spanned by all instructions in the object is less
1242 than 2^31 bytes (2GB) and the distance from any instruction
1243 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1244 than 2^31 bytes (2GB).
1245
1246 The executable must be in the low 4TB of the virtual address
1247 space.
1248
1249 sethi %hi(symbol), %temp1
1250 or %temp1, %lo(symbol), %reg */
1251 if (temp)
1252 temp1 = temp; /* op0 is allowed. */
1253 else
1254 temp1 = gen_reg_rtx (DImode);
1255
1256 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1257 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1258 break;
1259
1260 case CM_MEDMID:
1261 /* The range spanned by all instructions in the object is less
1262 than 2^31 bytes (2GB) and the distance from any instruction
1263 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1264 than 2^31 bytes (2GB).
1265
1266 The executable must be in the low 16TB of the virtual address
1267 space.
1268
1269 sethi %h44(symbol), %temp1
1270 or %temp1, %m44(symbol), %temp2
1271 sllx %temp2, 12, %temp3
1272 or %temp3, %l44(symbol), %reg */
1273 if (temp)
1274 {
1275 temp1 = op0;
1276 temp2 = op0;
1277 temp3 = temp; /* op0 is allowed. */
1278 }
1279 else
1280 {
1281 temp1 = gen_reg_rtx (DImode);
1282 temp2 = gen_reg_rtx (DImode);
1283 temp3 = gen_reg_rtx (DImode);
1284 }
1285
1286 emit_insn (gen_seth44 (temp1, op1));
1287 emit_insn (gen_setm44 (temp2, temp1, op1));
1288 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1289 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1290 emit_insn (gen_setl44 (op0, temp3, op1));
1291 break;
1292
1293 case CM_MEDANY:
1294 /* The range spanned by all instructions in the object is less
1295 than 2^31 bytes (2GB) and the distance from any instruction
1296 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1297 than 2^31 bytes (2GB).
1298
1299 The executable can be placed anywhere in the virtual address
1300 space.
1301
1302 sethi %hh(symbol), %temp1
1303 sethi %lm(symbol), %temp2
1304 or %temp1, %hm(symbol), %temp3
1305 sllx %temp3, 32, %temp4
1306 or %temp4, %temp2, %temp5
1307 or %temp5, %lo(symbol), %reg */
1308 if (temp)
1309 {
1310 /* It is possible that one of the registers we got for operands[2]
1311 might coincide with that of operands[0] (which is why we made
1312 it TImode). Pick the other one to use as our scratch. */
1313 if (rtx_equal_p (temp, op0))
1314 {
1315 gcc_assert (ti_temp);
1316 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1317 }
1318 temp1 = op0;
1319 temp2 = temp; /* op0 is _not_ allowed, see above. */
1320 temp3 = op0;
1321 temp4 = op0;
1322 temp5 = op0;
1323 }
1324 else
1325 {
1326 temp1 = gen_reg_rtx (DImode);
1327 temp2 = gen_reg_rtx (DImode);
1328 temp3 = gen_reg_rtx (DImode);
1329 temp4 = gen_reg_rtx (DImode);
1330 temp5 = gen_reg_rtx (DImode);
1331 }
1332
1333 emit_insn (gen_sethh (temp1, op1));
1334 emit_insn (gen_setlm (temp2, op1));
1335 emit_insn (gen_sethm (temp3, temp1, op1));
1336 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1337 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1338 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1339 gen_rtx_PLUS (DImode, temp4, temp2)));
1340 emit_insn (gen_setlo (op0, temp5, op1));
1341 break;
1342
1343 case CM_EMBMEDANY:
1344 /* Old old old backwards compatibility kruft here.
1345 Essentially it is MEDLOW with a fixed 64-bit
1346 virtual base added to all data segment addresses.
1347 Text-segment stuff is computed like MEDANY, we can't
1348 reuse the code above because the relocation knobs
1349 look different.
1350
1351 Data segment: sethi %hi(symbol), %temp1
1352 add %temp1, EMBMEDANY_BASE_REG, %temp2
1353 or %temp2, %lo(symbol), %reg */
1354 if (data_segment_operand (op1, GET_MODE (op1)))
1355 {
1356 if (temp)
1357 {
1358 temp1 = temp; /* op0 is allowed. */
1359 temp2 = op0;
1360 }
1361 else
1362 {
1363 temp1 = gen_reg_rtx (DImode);
1364 temp2 = gen_reg_rtx (DImode);
1365 }
1366
1367 emit_insn (gen_embmedany_sethi (temp1, op1));
1368 emit_insn (gen_embmedany_brsum (temp2, temp1));
1369 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1370 }
1371
1372 /* Text segment: sethi %uhi(symbol), %temp1
1373 sethi %hi(symbol), %temp2
1374 or %temp1, %ulo(symbol), %temp3
1375 sllx %temp3, 32, %temp4
1376 or %temp4, %temp2, %temp5
1377 or %temp5, %lo(symbol), %reg */
1378 else
1379 {
1380 if (temp)
1381 {
1382 /* It is possible that one of the registers we got for operands[2]
1383 might coincide with that of operands[0] (which is why we made
1384 it TImode). Pick the other one to use as our scratch. */
1385 if (rtx_equal_p (temp, op0))
1386 {
1387 gcc_assert (ti_temp);
1388 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1389 }
1390 temp1 = op0;
1391 temp2 = temp; /* op0 is _not_ allowed, see above. */
1392 temp3 = op0;
1393 temp4 = op0;
1394 temp5 = op0;
1395 }
1396 else
1397 {
1398 temp1 = gen_reg_rtx (DImode);
1399 temp2 = gen_reg_rtx (DImode);
1400 temp3 = gen_reg_rtx (DImode);
1401 temp4 = gen_reg_rtx (DImode);
1402 temp5 = gen_reg_rtx (DImode);
1403 }
1404
1405 emit_insn (gen_embmedany_textuhi (temp1, op1));
1406 emit_insn (gen_embmedany_texthi (temp2, op1));
1407 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1408 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1409 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1410 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1411 gen_rtx_PLUS (DImode, temp4, temp2)));
1412 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1413 }
1414 break;
1415
1416 default:
1417 gcc_unreachable ();
1418 }
1419 }
1420
1421 #if HOST_BITS_PER_WIDE_INT == 32
1422 static void
1423 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1424 {
1425 gcc_unreachable ();
1426 }
1427 #else
1428 /* These avoid problems when cross compiling. If we do not
1429 go through all this hair then the optimizer will see
1430 invalid REG_EQUAL notes or in some cases none at all. */
1431 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
1432 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1433 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1434 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1435
1436 /* The optimizer is not to assume anything about exactly
1437 which bits are set for a HIGH, they are unspecified.
1438 Unfortunately this leads to many missed optimizations
1439 during CSE. We mask out the non-HIGH bits, and matches
1440 a plain movdi, to alleviate this problem. */
1441 static rtx
1442 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1443 {
1444 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
1445 }
1446
1447 static rtx
1448 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1449 {
1450 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
1451 }
1452
1453 static rtx
1454 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1455 {
1456 return gen_rtx_IOR (DImode, src, GEN_INT (val));
1457 }
1458
1459 static rtx
1460 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1461 {
1462 return gen_rtx_XOR (DImode, src, GEN_INT (val));
1463 }
1464
1465 /* Worker routines for 64-bit constant formation on arch64.
1466 One of the key things to be doing in these emissions is
1467 to create as many temp REGs as possible. This makes it
1468 possible for half-built constants to be used later when
1469 such values are similar to something required later on.
1470 Without doing this, the optimizer cannot see such
1471 opportunities. */
1472
1473 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1474 unsigned HOST_WIDE_INT, int);
1475
1476 static void
1477 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1478 unsigned HOST_WIDE_INT low_bits, int is_neg)
1479 {
1480 unsigned HOST_WIDE_INT high_bits;
1481
1482 if (is_neg)
1483 high_bits = (~low_bits) & 0xffffffff;
1484 else
1485 high_bits = low_bits;
1486
1487 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1488 if (!is_neg)
1489 {
1490 emit_insn (gen_rtx_SET (VOIDmode, op0,
1491 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1492 }
1493 else
1494 {
1495 /* If we are XOR'ing with -1, then we should emit a one's complement
1496 instead. This way the combiner will notice logical operations
1497 such as ANDN later on and substitute. */
1498 if ((low_bits & 0x3ff) == 0x3ff)
1499 {
1500 emit_insn (gen_rtx_SET (VOIDmode, op0,
1501 gen_rtx_NOT (DImode, temp)));
1502 }
1503 else
1504 {
1505 emit_insn (gen_rtx_SET (VOIDmode, op0,
1506 gen_safe_XOR64 (temp,
1507 (-(HOST_WIDE_INT)0x400
1508 | (low_bits & 0x3ff)))));
1509 }
1510 }
1511 }
1512
1513 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1514 unsigned HOST_WIDE_INT, int);
1515
1516 static void
1517 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1518 unsigned HOST_WIDE_INT high_bits,
1519 unsigned HOST_WIDE_INT low_immediate,
1520 int shift_count)
1521 {
1522 rtx temp2 = op0;
1523
1524 if ((high_bits & 0xfffffc00) != 0)
1525 {
1526 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1527 if ((high_bits & ~0xfffffc00) != 0)
1528 emit_insn (gen_rtx_SET (VOIDmode, op0,
1529 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1530 else
1531 temp2 = temp;
1532 }
1533 else
1534 {
1535 emit_insn (gen_safe_SET64 (temp, high_bits));
1536 temp2 = temp;
1537 }
1538
1539 /* Now shift it up into place. */
1540 emit_insn (gen_rtx_SET (VOIDmode, op0,
1541 gen_rtx_ASHIFT (DImode, temp2,
1542 GEN_INT (shift_count))));
1543
1544 /* If there is a low immediate part piece, finish up by
1545 putting that in as well. */
1546 if (low_immediate != 0)
1547 emit_insn (gen_rtx_SET (VOIDmode, op0,
1548 gen_safe_OR64 (op0, low_immediate)));
1549 }
1550
1551 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1552 unsigned HOST_WIDE_INT);
1553
1554 /* Full 64-bit constant decomposition. Even though this is the
1555 'worst' case, we still optimize a few things away. */
1556 static void
1557 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1558 unsigned HOST_WIDE_INT high_bits,
1559 unsigned HOST_WIDE_INT low_bits)
1560 {
1561 rtx sub_temp;
1562
1563 if (reload_in_progress || reload_completed)
1564 sub_temp = op0;
1565 else
1566 sub_temp = gen_reg_rtx (DImode);
1567
1568 if ((high_bits & 0xfffffc00) != 0)
1569 {
1570 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1571 if ((high_bits & ~0xfffffc00) != 0)
1572 emit_insn (gen_rtx_SET (VOIDmode,
1573 sub_temp,
1574 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1575 else
1576 sub_temp = temp;
1577 }
1578 else
1579 {
1580 emit_insn (gen_safe_SET64 (temp, high_bits));
1581 sub_temp = temp;
1582 }
1583
1584 if (!reload_in_progress && !reload_completed)
1585 {
1586 rtx temp2 = gen_reg_rtx (DImode);
1587 rtx temp3 = gen_reg_rtx (DImode);
1588 rtx temp4 = gen_reg_rtx (DImode);
1589
1590 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1591 gen_rtx_ASHIFT (DImode, sub_temp,
1592 GEN_INT (32))));
1593
1594 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
1595 if ((low_bits & ~0xfffffc00) != 0)
1596 {
1597 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1598 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1599 emit_insn (gen_rtx_SET (VOIDmode, op0,
1600 gen_rtx_PLUS (DImode, temp4, temp3)));
1601 }
1602 else
1603 {
1604 emit_insn (gen_rtx_SET (VOIDmode, op0,
1605 gen_rtx_PLUS (DImode, temp4, temp2)));
1606 }
1607 }
1608 else
1609 {
1610 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1611 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1612 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1613 int to_shift = 12;
1614
1615 /* We are in the middle of reload, so this is really
1616 painful. However we do still make an attempt to
1617 avoid emitting truly stupid code. */
1618 if (low1 != const0_rtx)
1619 {
1620 emit_insn (gen_rtx_SET (VOIDmode, op0,
1621 gen_rtx_ASHIFT (DImode, sub_temp,
1622 GEN_INT (to_shift))));
1623 emit_insn (gen_rtx_SET (VOIDmode, op0,
1624 gen_rtx_IOR (DImode, op0, low1)));
1625 sub_temp = op0;
1626 to_shift = 12;
1627 }
1628 else
1629 {
1630 to_shift += 12;
1631 }
1632 if (low2 != const0_rtx)
1633 {
1634 emit_insn (gen_rtx_SET (VOIDmode, op0,
1635 gen_rtx_ASHIFT (DImode, sub_temp,
1636 GEN_INT (to_shift))));
1637 emit_insn (gen_rtx_SET (VOIDmode, op0,
1638 gen_rtx_IOR (DImode, op0, low2)));
1639 sub_temp = op0;
1640 to_shift = 8;
1641 }
1642 else
1643 {
1644 to_shift += 8;
1645 }
1646 emit_insn (gen_rtx_SET (VOIDmode, op0,
1647 gen_rtx_ASHIFT (DImode, sub_temp,
1648 GEN_INT (to_shift))));
1649 if (low3 != const0_rtx)
1650 emit_insn (gen_rtx_SET (VOIDmode, op0,
1651 gen_rtx_IOR (DImode, op0, low3)));
1652 /* phew... */
1653 }
1654 }
1655
1656 /* Analyze a 64-bit constant for certain properties. */
1657 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1658 unsigned HOST_WIDE_INT,
1659 int *, int *, int *);
1660
1661 static void
1662 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1663 unsigned HOST_WIDE_INT low_bits,
1664 int *hbsp, int *lbsp, int *abbasp)
1665 {
1666 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1667 int i;
1668
1669 lowest_bit_set = highest_bit_set = -1;
1670 i = 0;
1671 do
1672 {
1673 if ((lowest_bit_set == -1)
1674 && ((low_bits >> i) & 1))
1675 lowest_bit_set = i;
1676 if ((highest_bit_set == -1)
1677 && ((high_bits >> (32 - i - 1)) & 1))
1678 highest_bit_set = (64 - i - 1);
1679 }
1680 while (++i < 32
1681 && ((highest_bit_set == -1)
1682 || (lowest_bit_set == -1)));
1683 if (i == 32)
1684 {
1685 i = 0;
1686 do
1687 {
1688 if ((lowest_bit_set == -1)
1689 && ((high_bits >> i) & 1))
1690 lowest_bit_set = i + 32;
1691 if ((highest_bit_set == -1)
1692 && ((low_bits >> (32 - i - 1)) & 1))
1693 highest_bit_set = 32 - i - 1;
1694 }
1695 while (++i < 32
1696 && ((highest_bit_set == -1)
1697 || (lowest_bit_set == -1)));
1698 }
1699 /* If there are no bits set this should have gone out
1700 as one instruction! */
1701 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
1702 all_bits_between_are_set = 1;
1703 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1704 {
1705 if (i < 32)
1706 {
1707 if ((low_bits & (1 << i)) != 0)
1708 continue;
1709 }
1710 else
1711 {
1712 if ((high_bits & (1 << (i - 32))) != 0)
1713 continue;
1714 }
1715 all_bits_between_are_set = 0;
1716 break;
1717 }
1718 *hbsp = highest_bit_set;
1719 *lbsp = lowest_bit_set;
1720 *abbasp = all_bits_between_are_set;
1721 }
1722
1723 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1724
1725 static int
1726 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1727 unsigned HOST_WIDE_INT low_bits)
1728 {
1729 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1730
1731 if (high_bits == 0
1732 || high_bits == 0xffffffff)
1733 return 1;
1734
1735 analyze_64bit_constant (high_bits, low_bits,
1736 &highest_bit_set, &lowest_bit_set,
1737 &all_bits_between_are_set);
1738
1739 if ((highest_bit_set == 63
1740 || lowest_bit_set == 0)
1741 && all_bits_between_are_set != 0)
1742 return 1;
1743
1744 if ((highest_bit_set - lowest_bit_set) < 21)
1745 return 1;
1746
1747 return 0;
1748 }
1749
1750 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1751 unsigned HOST_WIDE_INT,
1752 int, int);
1753
1754 static unsigned HOST_WIDE_INT
1755 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1756 unsigned HOST_WIDE_INT low_bits,
1757 int lowest_bit_set, int shift)
1758 {
1759 HOST_WIDE_INT hi, lo;
1760
1761 if (lowest_bit_set < 32)
1762 {
1763 lo = (low_bits >> lowest_bit_set) << shift;
1764 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1765 }
1766 else
1767 {
1768 lo = 0;
1769 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1770 }
1771 gcc_assert (! (hi & lo));
1772 return (hi | lo);
1773 }
1774
1775 /* Here we are sure to be arch64 and this is an integer constant
1776 being loaded into a register. Emit the most efficient
1777 insn sequence possible. Detection of all the 1-insn cases
1778 has been done already. */
1779 static void
1780 sparc_emit_set_const64 (rtx op0, rtx op1)
1781 {
1782 unsigned HOST_WIDE_INT high_bits, low_bits;
1783 int lowest_bit_set, highest_bit_set;
1784 int all_bits_between_are_set;
1785 rtx temp = 0;
1786
1787 /* Sanity check that we know what we are working with. */
1788 gcc_assert (TARGET_ARCH64
1789 && (GET_CODE (op0) == SUBREG
1790 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
1791
1792 if (reload_in_progress || reload_completed)
1793 temp = op0;
1794
1795 if (GET_CODE (op1) != CONST_INT)
1796 {
1797 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1798 return;
1799 }
1800
1801 if (! temp)
1802 temp = gen_reg_rtx (DImode);
1803
1804 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1805 low_bits = (INTVAL (op1) & 0xffffffff);
1806
1807 /* low_bits bits 0 --> 31
1808 high_bits bits 32 --> 63 */
1809
1810 analyze_64bit_constant (high_bits, low_bits,
1811 &highest_bit_set, &lowest_bit_set,
1812 &all_bits_between_are_set);
1813
1814 /* First try for a 2-insn sequence. */
1815
1816 /* These situations are preferred because the optimizer can
1817 * do more things with them:
1818 * 1) mov -1, %reg
1819 * sllx %reg, shift, %reg
1820 * 2) mov -1, %reg
1821 * srlx %reg, shift, %reg
1822 * 3) mov some_small_const, %reg
1823 * sllx %reg, shift, %reg
1824 */
1825 if (((highest_bit_set == 63
1826 || lowest_bit_set == 0)
1827 && all_bits_between_are_set != 0)
1828 || ((highest_bit_set - lowest_bit_set) < 12))
1829 {
1830 HOST_WIDE_INT the_const = -1;
1831 int shift = lowest_bit_set;
1832
1833 if ((highest_bit_set != 63
1834 && lowest_bit_set != 0)
1835 || all_bits_between_are_set == 0)
1836 {
1837 the_const =
1838 create_simple_focus_bits (high_bits, low_bits,
1839 lowest_bit_set, 0);
1840 }
1841 else if (lowest_bit_set == 0)
1842 shift = -(63 - highest_bit_set);
1843
1844 gcc_assert (SPARC_SIMM13_P (the_const));
1845 gcc_assert (shift != 0);
1846
1847 emit_insn (gen_safe_SET64 (temp, the_const));
1848 if (shift > 0)
1849 emit_insn (gen_rtx_SET (VOIDmode,
1850 op0,
1851 gen_rtx_ASHIFT (DImode,
1852 temp,
1853 GEN_INT (shift))));
1854 else if (shift < 0)
1855 emit_insn (gen_rtx_SET (VOIDmode,
1856 op0,
1857 gen_rtx_LSHIFTRT (DImode,
1858 temp,
1859 GEN_INT (-shift))));
1860 return;
1861 }
1862
1863 /* Now a range of 22 or less bits set somewhere.
1864 * 1) sethi %hi(focus_bits), %reg
1865 * sllx %reg, shift, %reg
1866 * 2) sethi %hi(focus_bits), %reg
1867 * srlx %reg, shift, %reg
1868 */
1869 if ((highest_bit_set - lowest_bit_set) < 21)
1870 {
1871 unsigned HOST_WIDE_INT focus_bits =
1872 create_simple_focus_bits (high_bits, low_bits,
1873 lowest_bit_set, 10);
1874
1875 gcc_assert (SPARC_SETHI_P (focus_bits));
1876 gcc_assert (lowest_bit_set != 10);
1877
1878 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
1879
1880 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1881 if (lowest_bit_set < 10)
1882 emit_insn (gen_rtx_SET (VOIDmode,
1883 op0,
1884 gen_rtx_LSHIFTRT (DImode, temp,
1885 GEN_INT (10 - lowest_bit_set))));
1886 else if (lowest_bit_set > 10)
1887 emit_insn (gen_rtx_SET (VOIDmode,
1888 op0,
1889 gen_rtx_ASHIFT (DImode, temp,
1890 GEN_INT (lowest_bit_set - 10))));
1891 return;
1892 }
1893
1894 /* 1) sethi %hi(low_bits), %reg
1895 * or %reg, %lo(low_bits), %reg
1896 * 2) sethi %hi(~low_bits), %reg
1897 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1898 */
1899 if (high_bits == 0
1900 || high_bits == 0xffffffff)
1901 {
1902 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1903 (high_bits == 0xffffffff));
1904 return;
1905 }
1906
1907 /* Now, try 3-insn sequences. */
1908
1909 /* 1) sethi %hi(high_bits), %reg
1910 * or %reg, %lo(high_bits), %reg
1911 * sllx %reg, 32, %reg
1912 */
1913 if (low_bits == 0)
1914 {
1915 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1916 return;
1917 }
1918
1919 /* We may be able to do something quick
1920 when the constant is negated, so try that. */
1921 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1922 (~low_bits) & 0xfffffc00))
1923 {
1924 /* NOTE: The trailing bits get XOR'd so we need the
1925 non-negated bits, not the negated ones. */
1926 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1927
1928 if ((((~high_bits) & 0xffffffff) == 0
1929 && ((~low_bits) & 0x80000000) == 0)
1930 || (((~high_bits) & 0xffffffff) == 0xffffffff
1931 && ((~low_bits) & 0x80000000) != 0))
1932 {
1933 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
1934
1935 if ((SPARC_SETHI_P (fast_int)
1936 && (~high_bits & 0xffffffff) == 0)
1937 || SPARC_SIMM13_P (fast_int))
1938 emit_insn (gen_safe_SET64 (temp, fast_int));
1939 else
1940 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
1941 }
1942 else
1943 {
1944 rtx negated_const;
1945 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1946 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1947 sparc_emit_set_const64 (temp, negated_const);
1948 }
1949
1950 /* If we are XOR'ing with -1, then we should emit a one's complement
1951 instead. This way the combiner will notice logical operations
1952 such as ANDN later on and substitute. */
1953 if (trailing_bits == 0x3ff)
1954 {
1955 emit_insn (gen_rtx_SET (VOIDmode, op0,
1956 gen_rtx_NOT (DImode, temp)));
1957 }
1958 else
1959 {
1960 emit_insn (gen_rtx_SET (VOIDmode,
1961 op0,
1962 gen_safe_XOR64 (temp,
1963 (-0x400 | trailing_bits))));
1964 }
1965 return;
1966 }
1967
1968 /* 1) sethi %hi(xxx), %reg
1969 * or %reg, %lo(xxx), %reg
1970 * sllx %reg, yyy, %reg
1971 *
1972 * ??? This is just a generalized version of the low_bits==0
1973 * thing above, FIXME...
1974 */
1975 if ((highest_bit_set - lowest_bit_set) < 32)
1976 {
1977 unsigned HOST_WIDE_INT focus_bits =
1978 create_simple_focus_bits (high_bits, low_bits,
1979 lowest_bit_set, 0);
1980
1981 /* We can't get here in this state. */
1982 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
1983
1984 /* So what we know is that the set bits straddle the
1985 middle of the 64-bit word. */
1986 sparc_emit_set_const64_quick2 (op0, temp,
1987 focus_bits, 0,
1988 lowest_bit_set);
1989 return;
1990 }
1991
1992 /* 1) sethi %hi(high_bits), %reg
1993 * or %reg, %lo(high_bits), %reg
1994 * sllx %reg, 32, %reg
1995 * or %reg, low_bits, %reg
1996 */
1997 if (SPARC_SIMM13_P(low_bits)
1998 && ((int)low_bits > 0))
1999 {
2000 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2001 return;
2002 }
2003
2004 /* The easiest way when all else fails, is full decomposition. */
2005 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2006 }
2007 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2008
2009 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2010 return the mode to be used for the comparison. For floating-point,
2011 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2012 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2013 processing is needed. */
2014
2015 enum machine_mode
2016 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2017 {
2018 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2019 {
2020 switch (op)
2021 {
2022 case EQ:
2023 case NE:
2024 case UNORDERED:
2025 case ORDERED:
2026 case UNLT:
2027 case UNLE:
2028 case UNGT:
2029 case UNGE:
2030 case UNEQ:
2031 case LTGT:
2032 return CCFPmode;
2033
2034 case LT:
2035 case LE:
2036 case GT:
2037 case GE:
2038 return CCFPEmode;
2039
2040 default:
2041 gcc_unreachable ();
2042 }
2043 }
2044 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2045 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2046 {
2047 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2048 return CCX_NOOVmode;
2049 else
2050 return CC_NOOVmode;
2051 }
2052 else
2053 {
2054 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2055 return CCXmode;
2056 else
2057 return CCmode;
2058 }
2059 }
2060
2061 /* Emit the compare insn and return the CC reg for a CODE comparison
2062 with operands X and Y. */
2063
2064 static rtx
2065 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
2066 {
2067 enum machine_mode mode;
2068 rtx cc_reg;
2069
2070 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2071 return x;
2072
2073 mode = SELECT_CC_MODE (code, x, y);
2074
2075 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2076 fcc regs (cse can't tell they're really call clobbered regs and will
2077 remove a duplicate comparison even if there is an intervening function
2078 call - it will then try to reload the cc reg via an int reg which is why
2079 we need the movcc patterns). It is possible to provide the movcc
2080 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2081 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2082 to tell cse that CCFPE mode registers (even pseudos) are call
2083 clobbered. */
2084
2085 /* ??? This is an experiment. Rather than making changes to cse which may
2086 or may not be easy/clean, we do our own cse. This is possible because
2087 we will generate hard registers. Cse knows they're call clobbered (it
2088 doesn't know the same thing about pseudos). If we guess wrong, no big
2089 deal, but if we win, great! */
2090
2091 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2092 #if 1 /* experiment */
2093 {
2094 int reg;
2095 /* We cycle through the registers to ensure they're all exercised. */
2096 static int next_fcc_reg = 0;
2097 /* Previous x,y for each fcc reg. */
2098 static rtx prev_args[4][2];
2099
2100 /* Scan prev_args for x,y. */
2101 for (reg = 0; reg < 4; reg++)
2102 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2103 break;
2104 if (reg == 4)
2105 {
2106 reg = next_fcc_reg;
2107 prev_args[reg][0] = x;
2108 prev_args[reg][1] = y;
2109 next_fcc_reg = (next_fcc_reg + 1) & 3;
2110 }
2111 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2112 }
2113 #else
2114 cc_reg = gen_reg_rtx (mode);
2115 #endif /* ! experiment */
2116 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2117 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2118 else
2119 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2120
2121 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2122 will only result in an unrecognizable insn so no point in asserting. */
2123 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
2124
2125 return cc_reg;
2126 }
2127
2128
2129 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2130
2131 rtx
2132 gen_compare_reg (rtx cmp)
2133 {
2134 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
2135 }
2136
2137 /* This function is used for v9 only.
2138 DEST is the target of the Scc insn.
2139 CODE is the code for an Scc's comparison.
2140 X and Y are the values we compare.
2141
2142 This function is needed to turn
2143
2144 (set (reg:SI 110)
2145 (gt (reg:CCX 100 %icc)
2146 (const_int 0)))
2147 into
2148 (set (reg:SI 110)
2149 (gt:DI (reg:CCX 100 %icc)
2150 (const_int 0)))
2151
2152 IE: The instruction recognizer needs to see the mode of the comparison to
2153 find the right instruction. We could use "gt:DI" right in the
2154 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2155
2156 static int
2157 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
2158 {
2159 if (! TARGET_ARCH64
2160 && (GET_MODE (x) == DImode
2161 || GET_MODE (dest) == DImode))
2162 return 0;
2163
2164 /* Try to use the movrCC insns. */
2165 if (TARGET_ARCH64
2166 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2167 && y == const0_rtx
2168 && v9_regcmp_p (compare_code))
2169 {
2170 rtx op0 = x;
2171 rtx temp;
2172
2173 /* Special case for op0 != 0. This can be done with one instruction if
2174 dest == x. */
2175
2176 if (compare_code == NE
2177 && GET_MODE (dest) == DImode
2178 && rtx_equal_p (op0, dest))
2179 {
2180 emit_insn (gen_rtx_SET (VOIDmode, dest,
2181 gen_rtx_IF_THEN_ELSE (DImode,
2182 gen_rtx_fmt_ee (compare_code, DImode,
2183 op0, const0_rtx),
2184 const1_rtx,
2185 dest)));
2186 return 1;
2187 }
2188
2189 if (reg_overlap_mentioned_p (dest, op0))
2190 {
2191 /* Handle the case where dest == x.
2192 We "early clobber" the result. */
2193 op0 = gen_reg_rtx (GET_MODE (x));
2194 emit_move_insn (op0, x);
2195 }
2196
2197 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2198 if (GET_MODE (op0) != DImode)
2199 {
2200 temp = gen_reg_rtx (DImode);
2201 convert_move (temp, op0, 0);
2202 }
2203 else
2204 temp = op0;
2205 emit_insn (gen_rtx_SET (VOIDmode, dest,
2206 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2207 gen_rtx_fmt_ee (compare_code, DImode,
2208 temp, const0_rtx),
2209 const1_rtx,
2210 dest)));
2211 return 1;
2212 }
2213 else
2214 {
2215 x = gen_compare_reg_1 (compare_code, x, y);
2216 y = const0_rtx;
2217
2218 gcc_assert (GET_MODE (x) != CC_NOOVmode
2219 && GET_MODE (x) != CCX_NOOVmode);
2220
2221 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2222 emit_insn (gen_rtx_SET (VOIDmode, dest,
2223 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2224 gen_rtx_fmt_ee (compare_code,
2225 GET_MODE (x), x, y),
2226 const1_rtx, dest)));
2227 return 1;
2228 }
2229 }
2230
2231
2232 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2233 without jumps using the addx/subx instructions. */
2234
2235 bool
2236 emit_scc_insn (rtx operands[])
2237 {
2238 rtx tem;
2239 rtx x;
2240 rtx y;
2241 enum rtx_code code;
2242
2243 /* The quad-word fp compare library routines all return nonzero to indicate
2244 true, which is different from the equivalent libgcc routines, so we must
2245 handle them specially here. */
2246 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2247 {
2248 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2249 GET_CODE (operands[1]));
2250 operands[2] = XEXP (operands[1], 0);
2251 operands[3] = XEXP (operands[1], 1);
2252 }
2253
2254 code = GET_CODE (operands[1]);
2255 x = operands[2];
2256 y = operands[3];
2257
2258 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2259 more applications). The exception to this is "reg != 0" which can
2260 be done in one instruction on v9 (so we do it). */
2261 if (code == EQ)
2262 {
2263 if (GET_MODE (x) == SImode)
2264 {
2265 rtx pat = gen_seqsi_special (operands[0], x, y);
2266 emit_insn (pat);
2267 return true;
2268 }
2269 else if (GET_MODE (x) == DImode)
2270 {
2271 rtx pat = gen_seqdi_special (operands[0], x, y);
2272 emit_insn (pat);
2273 return true;
2274 }
2275 }
2276
2277 if (code == NE)
2278 {
2279 if (GET_MODE (x) == SImode)
2280 {
2281 rtx pat = gen_snesi_special (operands[0], x, y);
2282 emit_insn (pat);
2283 return true;
2284 }
2285 else if (GET_MODE (x) == DImode)
2286 {
2287 rtx pat = gen_snedi_special (operands[0], x, y);
2288 emit_insn (pat);
2289 return true;
2290 }
2291 }
2292
2293 /* For the rest, on v9 we can use conditional moves. */
2294
2295 if (TARGET_V9)
2296 {
2297 if (gen_v9_scc (operands[0], code, x, y))
2298 return true;
2299 }
2300
2301 /* We can do LTU and GEU using the addx/subx instructions too. And
2302 for GTU/LEU, if both operands are registers swap them and fall
2303 back to the easy case. */
2304 if (code == GTU || code == LEU)
2305 {
2306 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2307 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2308 {
2309 tem = x;
2310 x = y;
2311 y = tem;
2312 code = swap_condition (code);
2313 }
2314 }
2315
2316 if (code == LTU || code == GEU)
2317 {
2318 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2319 gen_rtx_fmt_ee (code, SImode,
2320 gen_compare_reg_1 (code, x, y),
2321 const0_rtx)));
2322 return true;
2323 }
2324
2325 /* Nope, do branches. */
2326 return false;
2327 }
2328
2329 /* Emit a conditional jump insn for the v9 architecture using comparison code
2330 CODE and jump target LABEL.
2331 This function exists to take advantage of the v9 brxx insns. */
2332
2333 static void
2334 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2335 {
2336 emit_jump_insn (gen_rtx_SET (VOIDmode,
2337 pc_rtx,
2338 gen_rtx_IF_THEN_ELSE (VOIDmode,
2339 gen_rtx_fmt_ee (code, GET_MODE (op0),
2340 op0, const0_rtx),
2341 gen_rtx_LABEL_REF (VOIDmode, label),
2342 pc_rtx)));
2343 }
2344
2345 void
2346 emit_conditional_branch_insn (rtx operands[])
2347 {
2348 /* The quad-word fp compare library routines all return nonzero to indicate
2349 true, which is different from the equivalent libgcc routines, so we must
2350 handle them specially here. */
2351 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
2352 {
2353 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
2354 GET_CODE (operands[0]));
2355 operands[1] = XEXP (operands[0], 0);
2356 operands[2] = XEXP (operands[0], 1);
2357 }
2358
2359 if (TARGET_ARCH64 && operands[2] == const0_rtx
2360 && GET_CODE (operands[1]) == REG
2361 && GET_MODE (operands[1]) == DImode)
2362 {
2363 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
2364 return;
2365 }
2366
2367 operands[1] = gen_compare_reg (operands[0]);
2368 operands[2] = const0_rtx;
2369 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
2370 operands[1], operands[2]);
2371 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
2372 operands[3]));
2373 }
2374
2375
2376 /* Generate a DFmode part of a hard TFmode register.
2377 REG is the TFmode hard register, LOW is 1 for the
2378 low 64bit of the register and 0 otherwise.
2379 */
2380 rtx
2381 gen_df_reg (rtx reg, int low)
2382 {
2383 int regno = REGNO (reg);
2384
2385 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2386 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2387 return gen_rtx_REG (DFmode, regno);
2388 }
2389 \f
2390 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2391 Unlike normal calls, TFmode operands are passed by reference. It is
2392 assumed that no more than 3 operands are required. */
2393
2394 static void
2395 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2396 {
2397 rtx ret_slot = NULL, arg[3], func_sym;
2398 int i;
2399
2400 /* We only expect to be called for conversions, unary, and binary ops. */
2401 gcc_assert (nargs == 2 || nargs == 3);
2402
2403 for (i = 0; i < nargs; ++i)
2404 {
2405 rtx this_arg = operands[i];
2406 rtx this_slot;
2407
2408 /* TFmode arguments and return values are passed by reference. */
2409 if (GET_MODE (this_arg) == TFmode)
2410 {
2411 int force_stack_temp;
2412
2413 force_stack_temp = 0;
2414 if (TARGET_BUGGY_QP_LIB && i == 0)
2415 force_stack_temp = 1;
2416
2417 if (GET_CODE (this_arg) == MEM
2418 && ! force_stack_temp)
2419 this_arg = XEXP (this_arg, 0);
2420 else if (CONSTANT_P (this_arg)
2421 && ! force_stack_temp)
2422 {
2423 this_slot = force_const_mem (TFmode, this_arg);
2424 this_arg = XEXP (this_slot, 0);
2425 }
2426 else
2427 {
2428 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2429
2430 /* Operand 0 is the return value. We'll copy it out later. */
2431 if (i > 0)
2432 emit_move_insn (this_slot, this_arg);
2433 else
2434 ret_slot = this_slot;
2435
2436 this_arg = XEXP (this_slot, 0);
2437 }
2438 }
2439
2440 arg[i] = this_arg;
2441 }
2442
2443 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2444
2445 if (GET_MODE (operands[0]) == TFmode)
2446 {
2447 if (nargs == 2)
2448 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2449 arg[0], GET_MODE (arg[0]),
2450 arg[1], GET_MODE (arg[1]));
2451 else
2452 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2453 arg[0], GET_MODE (arg[0]),
2454 arg[1], GET_MODE (arg[1]),
2455 arg[2], GET_MODE (arg[2]));
2456
2457 if (ret_slot)
2458 emit_move_insn (operands[0], ret_slot);
2459 }
2460 else
2461 {
2462 rtx ret;
2463
2464 gcc_assert (nargs == 2);
2465
2466 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2467 GET_MODE (operands[0]), 1,
2468 arg[1], GET_MODE (arg[1]));
2469
2470 if (ret != operands[0])
2471 emit_move_insn (operands[0], ret);
2472 }
2473 }
2474
2475 /* Expand soft-float TFmode calls to sparc abi routines. */
2476
2477 static void
2478 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2479 {
2480 const char *func;
2481
2482 switch (code)
2483 {
2484 case PLUS:
2485 func = "_Qp_add";
2486 break;
2487 case MINUS:
2488 func = "_Qp_sub";
2489 break;
2490 case MULT:
2491 func = "_Qp_mul";
2492 break;
2493 case DIV:
2494 func = "_Qp_div";
2495 break;
2496 default:
2497 gcc_unreachable ();
2498 }
2499
2500 emit_soft_tfmode_libcall (func, 3, operands);
2501 }
2502
2503 static void
2504 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2505 {
2506 const char *func;
2507
2508 gcc_assert (code == SQRT);
2509 func = "_Qp_sqrt";
2510
2511 emit_soft_tfmode_libcall (func, 2, operands);
2512 }
2513
2514 static void
2515 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2516 {
2517 const char *func;
2518
2519 switch (code)
2520 {
2521 case FLOAT_EXTEND:
2522 switch (GET_MODE (operands[1]))
2523 {
2524 case SFmode:
2525 func = "_Qp_stoq";
2526 break;
2527 case DFmode:
2528 func = "_Qp_dtoq";
2529 break;
2530 default:
2531 gcc_unreachable ();
2532 }
2533 break;
2534
2535 case FLOAT_TRUNCATE:
2536 switch (GET_MODE (operands[0]))
2537 {
2538 case SFmode:
2539 func = "_Qp_qtos";
2540 break;
2541 case DFmode:
2542 func = "_Qp_qtod";
2543 break;
2544 default:
2545 gcc_unreachable ();
2546 }
2547 break;
2548
2549 case FLOAT:
2550 switch (GET_MODE (operands[1]))
2551 {
2552 case SImode:
2553 func = "_Qp_itoq";
2554 if (TARGET_ARCH64)
2555 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
2556 break;
2557 case DImode:
2558 func = "_Qp_xtoq";
2559 break;
2560 default:
2561 gcc_unreachable ();
2562 }
2563 break;
2564
2565 case UNSIGNED_FLOAT:
2566 switch (GET_MODE (operands[1]))
2567 {
2568 case SImode:
2569 func = "_Qp_uitoq";
2570 if (TARGET_ARCH64)
2571 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2572 break;
2573 case DImode:
2574 func = "_Qp_uxtoq";
2575 break;
2576 default:
2577 gcc_unreachable ();
2578 }
2579 break;
2580
2581 case FIX:
2582 switch (GET_MODE (operands[0]))
2583 {
2584 case SImode:
2585 func = "_Qp_qtoi";
2586 break;
2587 case DImode:
2588 func = "_Qp_qtox";
2589 break;
2590 default:
2591 gcc_unreachable ();
2592 }
2593 break;
2594
2595 case UNSIGNED_FIX:
2596 switch (GET_MODE (operands[0]))
2597 {
2598 case SImode:
2599 func = "_Qp_qtoui";
2600 break;
2601 case DImode:
2602 func = "_Qp_qtoux";
2603 break;
2604 default:
2605 gcc_unreachable ();
2606 }
2607 break;
2608
2609 default:
2610 gcc_unreachable ();
2611 }
2612
2613 emit_soft_tfmode_libcall (func, 2, operands);
2614 }
2615
2616 /* Expand a hard-float tfmode operation. All arguments must be in
2617 registers. */
2618
2619 static void
2620 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2621 {
2622 rtx op, dest;
2623
2624 if (GET_RTX_CLASS (code) == RTX_UNARY)
2625 {
2626 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2627 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2628 }
2629 else
2630 {
2631 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2632 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2633 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2634 operands[1], operands[2]);
2635 }
2636
2637 if (register_operand (operands[0], VOIDmode))
2638 dest = operands[0];
2639 else
2640 dest = gen_reg_rtx (GET_MODE (operands[0]));
2641
2642 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2643
2644 if (dest != operands[0])
2645 emit_move_insn (operands[0], dest);
2646 }
2647
2648 void
2649 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2650 {
2651 if (TARGET_HARD_QUAD)
2652 emit_hard_tfmode_operation (code, operands);
2653 else
2654 emit_soft_tfmode_binop (code, operands);
2655 }
2656
2657 void
2658 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2659 {
2660 if (TARGET_HARD_QUAD)
2661 emit_hard_tfmode_operation (code, operands);
2662 else
2663 emit_soft_tfmode_unop (code, operands);
2664 }
2665
2666 void
2667 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2668 {
2669 if (TARGET_HARD_QUAD)
2670 emit_hard_tfmode_operation (code, operands);
2671 else
2672 emit_soft_tfmode_cvt (code, operands);
2673 }
2674 \f
2675 /* Return nonzero if a branch/jump/call instruction will be emitting
2676 nop into its delay slot. */
2677
2678 int
2679 empty_delay_slot (rtx insn)
2680 {
2681 rtx seq;
2682
2683 /* If no previous instruction (should not happen), return true. */
2684 if (PREV_INSN (insn) == NULL)
2685 return 1;
2686
2687 seq = NEXT_INSN (PREV_INSN (insn));
2688 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2689 return 0;
2690
2691 return 1;
2692 }
2693
2694 /* Return nonzero if TRIAL can go into the call delay slot. */
2695
2696 int
2697 tls_call_delay (rtx trial)
2698 {
2699 rtx pat;
2700
2701 /* Binutils allows
2702 call __tls_get_addr, %tgd_call (foo)
2703 add %l7, %o0, %o0, %tgd_add (foo)
2704 while Sun as/ld does not. */
2705 if (TARGET_GNU_TLS || !TARGET_TLS)
2706 return 1;
2707
2708 pat = PATTERN (trial);
2709
2710 /* We must reject tgd_add{32|64}, i.e.
2711 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2712 and tldm_add{32|64}, i.e.
2713 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2714 for Sun as/ld. */
2715 if (GET_CODE (pat) == SET
2716 && GET_CODE (SET_SRC (pat)) == PLUS)
2717 {
2718 rtx unspec = XEXP (SET_SRC (pat), 1);
2719
2720 if (GET_CODE (unspec) == UNSPEC
2721 && (XINT (unspec, 1) == UNSPEC_TLSGD
2722 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2723 return 0;
2724 }
2725
2726 return 1;
2727 }
2728
2729 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2730 instruction. RETURN_P is true if the v9 variant 'return' is to be
2731 considered in the test too.
2732
2733 TRIAL must be a SET whose destination is a REG appropriate for the
2734 'restore' instruction or, if RETURN_P is true, for the 'return'
2735 instruction. */
2736
2737 static int
2738 eligible_for_restore_insn (rtx trial, bool return_p)
2739 {
2740 rtx pat = PATTERN (trial);
2741 rtx src = SET_SRC (pat);
2742
2743 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2744 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2745 && arith_operand (src, GET_MODE (src)))
2746 {
2747 if (TARGET_ARCH64)
2748 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2749 else
2750 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2751 }
2752
2753 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2754 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2755 && arith_double_operand (src, GET_MODE (src)))
2756 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2757
2758 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2759 else if (! TARGET_FPU && register_operand (src, SFmode))
2760 return 1;
2761
2762 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2763 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
2764 return 1;
2765
2766 /* If we have the 'return' instruction, anything that does not use
2767 local or output registers and can go into a delay slot wins. */
2768 else if (return_p
2769 && TARGET_V9
2770 && !epilogue_renumber (&pat, 1)
2771 && get_attr_in_uncond_branch_delay (trial)
2772 == IN_UNCOND_BRANCH_DELAY_TRUE)
2773 return 1;
2774
2775 /* The 'restore src1,src2,dest' pattern for SImode. */
2776 else if (GET_CODE (src) == PLUS
2777 && register_operand (XEXP (src, 0), SImode)
2778 && arith_operand (XEXP (src, 1), SImode))
2779 return 1;
2780
2781 /* The 'restore src1,src2,dest' pattern for DImode. */
2782 else if (GET_CODE (src) == PLUS
2783 && register_operand (XEXP (src, 0), DImode)
2784 && arith_double_operand (XEXP (src, 1), DImode))
2785 return 1;
2786
2787 /* The 'restore src1,%lo(src2),dest' pattern. */
2788 else if (GET_CODE (src) == LO_SUM
2789 && ! TARGET_CM_MEDMID
2790 && ((register_operand (XEXP (src, 0), SImode)
2791 && immediate_operand (XEXP (src, 1), SImode))
2792 || (TARGET_ARCH64
2793 && register_operand (XEXP (src, 0), DImode)
2794 && immediate_operand (XEXP (src, 1), DImode))))
2795 return 1;
2796
2797 /* The 'restore src,src,dest' pattern. */
2798 else if (GET_CODE (src) == ASHIFT
2799 && (register_operand (XEXP (src, 0), SImode)
2800 || register_operand (XEXP (src, 0), DImode))
2801 && XEXP (src, 1) == const1_rtx)
2802 return 1;
2803
2804 return 0;
2805 }
2806
2807 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2808
2809 int
2810 eligible_for_return_delay (rtx trial)
2811 {
2812 rtx pat;
2813
2814 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2815 return 0;
2816
2817 if (get_attr_length (trial) != 1)
2818 return 0;
2819
2820 /* If the function uses __builtin_eh_return, the eh_return machinery
2821 occupies the delay slot. */
2822 if (crtl->calls_eh_return)
2823 return 0;
2824
2825 /* In the case of a leaf or flat function, anything can go into the slot. */
2826 if (sparc_leaf_function_p || TARGET_FLAT)
2827 return
2828 get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;
2829
2830 pat = PATTERN (trial);
2831
2832 /* Otherwise, only operations which can be done in tandem with
2833 a `restore' or `return' insn can go into the delay slot. */
2834 if (GET_CODE (SET_DEST (pat)) != REG
2835 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2836 return 0;
2837
2838 /* If this instruction sets up floating point register and we have a return
2839 instruction, it can probably go in. But restore will not work
2840 with FP_REGS. */
2841 if (REGNO (SET_DEST (pat)) >= 32)
2842 return (TARGET_V9
2843 && !epilogue_renumber (&pat, 1)
2844 && get_attr_in_uncond_branch_delay (trial)
2845 == IN_UNCOND_BRANCH_DELAY_TRUE);
2846
2847 return eligible_for_restore_insn (trial, true);
2848 }
2849
2850 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
2851
2852 int
2853 eligible_for_sibcall_delay (rtx trial)
2854 {
2855 rtx pat;
2856
2857 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2858 return 0;
2859
2860 if (get_attr_length (trial) != 1)
2861 return 0;
2862
2863 pat = PATTERN (trial);
2864
2865 if (sparc_leaf_function_p || TARGET_FLAT)
2866 {
2867 /* If the tail call is done using the call instruction,
2868 we have to restore %o7 in the delay slot. */
2869 if (LEAF_SIBCALL_SLOT_RESERVED_P)
2870 return 0;
2871
2872 /* %g1 is used to build the function address */
2873 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2874 return 0;
2875
2876 return 1;
2877 }
2878
2879 /* Otherwise, only operations which can be done in tandem with
2880 a `restore' insn can go into the delay slot. */
2881 if (GET_CODE (SET_DEST (pat)) != REG
2882 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
2883 || REGNO (SET_DEST (pat)) >= 32)
2884 return 0;
2885
2886 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2887 in most cases. */
2888 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2889 return 0;
2890
2891 return eligible_for_restore_insn (trial, false);
2892 }
2893
2894 int
2895 short_branch (int uid1, int uid2)
2896 {
2897 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
2898
2899 /* Leave a few words of "slop". */
2900 if (delta >= -1023 && delta <= 1022)
2901 return 1;
2902
2903 return 0;
2904 }
2905
2906 /* Return nonzero if REG is not used after INSN.
2907 We assume REG is a reload reg, and therefore does
2908 not live past labels or calls or jumps. */
2909 int
2910 reg_unused_after (rtx reg, rtx insn)
2911 {
2912 enum rtx_code code, prev_code = UNKNOWN;
2913
2914 while ((insn = NEXT_INSN (insn)))
2915 {
2916 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2917 return 1;
2918
2919 code = GET_CODE (insn);
2920 if (GET_CODE (insn) == CODE_LABEL)
2921 return 1;
2922
2923 if (INSN_P (insn))
2924 {
2925 rtx set = single_set (insn);
2926 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2927 if (set && in_src)
2928 return 0;
2929 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2930 return 1;
2931 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2932 return 0;
2933 }
2934 prev_code = code;
2935 }
2936 return 1;
2937 }
2938 \f
2939 /* Determine if it's legal to put X into the constant pool. This
2940 is not possible if X contains the address of a symbol that is
2941 not constant (TLS) or not known at final link time (PIC). */
2942
2943 static bool
2944 sparc_cannot_force_const_mem (enum machine_mode mode, rtx x)
2945 {
2946 switch (GET_CODE (x))
2947 {
2948 case CONST_INT:
2949 case CONST_DOUBLE:
2950 case CONST_VECTOR:
2951 /* Accept all non-symbolic constants. */
2952 return false;
2953
2954 case LABEL_REF:
2955 /* Labels are OK iff we are non-PIC. */
2956 return flag_pic != 0;
2957
2958 case SYMBOL_REF:
2959 /* 'Naked' TLS symbol references are never OK,
2960 non-TLS symbols are OK iff we are non-PIC. */
2961 if (SYMBOL_REF_TLS_MODEL (x))
2962 return true;
2963 else
2964 return flag_pic != 0;
2965
2966 case CONST:
2967 return sparc_cannot_force_const_mem (mode, XEXP (x, 0));
2968 case PLUS:
2969 case MINUS:
2970 return sparc_cannot_force_const_mem (mode, XEXP (x, 0))
2971 || sparc_cannot_force_const_mem (mode, XEXP (x, 1));
2972 case UNSPEC:
2973 return true;
2974 default:
2975 gcc_unreachable ();
2976 }
2977 }
2978 \f
2979 /* Global Offset Table support. */
2980 static GTY(()) rtx got_helper_rtx = NULL_RTX;
2981 static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
2982
2983 /* Return the SYMBOL_REF for the Global Offset Table. */
2984
2985 static GTY(()) rtx sparc_got_symbol = NULL_RTX;
2986
2987 static rtx
2988 sparc_got (void)
2989 {
2990 if (!sparc_got_symbol)
2991 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2992
2993 return sparc_got_symbol;
2994 }
2995
2996 /* Ensure that we are not using patterns that are not OK with PIC. */
2997
2998 int
2999 check_pic (int i)
3000 {
3001 rtx op;
3002
3003 switch (flag_pic)
3004 {
3005 case 1:
3006 op = recog_data.operand[i];
3007 gcc_assert (GET_CODE (op) != SYMBOL_REF
3008 && (GET_CODE (op) != CONST
3009 || (GET_CODE (XEXP (op, 0)) == MINUS
3010 && XEXP (XEXP (op, 0), 0) == sparc_got ()
3011 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
3012 case 2:
3013 default:
3014 return 1;
3015 }
3016 }
3017
3018 /* Return true if X is an address which needs a temporary register when
3019 reloaded while generating PIC code. */
3020
3021 int
3022 pic_address_needs_scratch (rtx x)
3023 {
3024 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3025 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3026 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3027 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3028 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3029 return 1;
3030
3031 return 0;
3032 }
3033
3034 /* Determine if a given RTX is a valid constant. We already know this
3035 satisfies CONSTANT_P. */
3036
3037 static bool
3038 sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
3039 {
3040 switch (GET_CODE (x))
3041 {
3042 case CONST:
3043 case SYMBOL_REF:
3044 if (sparc_tls_referenced_p (x))
3045 return false;
3046 break;
3047
3048 case CONST_DOUBLE:
3049 if (GET_MODE (x) == VOIDmode)
3050 return true;
3051
3052 /* Floating point constants are generally not ok.
3053 The only exception is 0.0 in VIS. */
3054 if (TARGET_VIS
3055 && SCALAR_FLOAT_MODE_P (mode)
3056 && const_zero_operand (x, mode))
3057 return true;
3058
3059 return false;
3060
3061 case CONST_VECTOR:
3062 /* Vector constants are generally not ok.
3063 The only exception is 0 in VIS. */
3064 if (TARGET_VIS
3065 && const_zero_operand (x, mode))
3066 return true;
3067
3068 return false;
3069
3070 default:
3071 break;
3072 }
3073
3074 return true;
3075 }
3076
3077 /* Determine if a given RTX is a valid constant address. */
3078
3079 bool
3080 constant_address_p (rtx x)
3081 {
3082 switch (GET_CODE (x))
3083 {
3084 case LABEL_REF:
3085 case CONST_INT:
3086 case HIGH:
3087 return true;
3088
3089 case CONST:
3090 if (flag_pic && pic_address_needs_scratch (x))
3091 return false;
3092 return sparc_legitimate_constant_p (Pmode, x);
3093
3094 case SYMBOL_REF:
3095 return !flag_pic && sparc_legitimate_constant_p (Pmode, x);
3096
3097 default:
3098 return false;
3099 }
3100 }
3101
3102 /* Nonzero if the constant value X is a legitimate general operand
3103 when generating PIC code. It is given that flag_pic is on and
3104 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3105
3106 bool
3107 legitimate_pic_operand_p (rtx x)
3108 {
3109 if (pic_address_needs_scratch (x))
3110 return false;
3111 if (sparc_tls_referenced_p (x))
3112 return false;
3113 return true;
3114 }
3115
3116 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3117 (CONST_INT_P (X) \
3118 && INTVAL (X) >= -0x1000 \
3119 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3120
3121 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3122 (CONST_INT_P (X) \
3123 && INTVAL (X) >= -0x1000 \
3124 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3125
3126 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3127
3128 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3129 ordinarily. This changes a bit when generating PIC. */
3130
3131 static bool
3132 sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3133 {
3134 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3135
3136 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3137 rs1 = addr;
3138 else if (GET_CODE (addr) == PLUS)
3139 {
3140 rs1 = XEXP (addr, 0);
3141 rs2 = XEXP (addr, 1);
3142
3143 /* Canonicalize. REG comes first, if there are no regs,
3144 LO_SUM comes first. */
3145 if (!REG_P (rs1)
3146 && GET_CODE (rs1) != SUBREG
3147 && (REG_P (rs2)
3148 || GET_CODE (rs2) == SUBREG
3149 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3150 {
3151 rs1 = XEXP (addr, 1);
3152 rs2 = XEXP (addr, 0);
3153 }
3154
3155 if ((flag_pic == 1
3156 && rs1 == pic_offset_table_rtx
3157 && !REG_P (rs2)
3158 && GET_CODE (rs2) != SUBREG
3159 && GET_CODE (rs2) != LO_SUM
3160 && GET_CODE (rs2) != MEM
3161 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
3162 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3163 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3164 || ((REG_P (rs1)
3165 || GET_CODE (rs1) == SUBREG)
3166 && RTX_OK_FOR_OFFSET_P (rs2, mode)))
3167 {
3168 imm1 = rs2;
3169 rs2 = NULL;
3170 }
3171 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3172 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3173 {
3174 /* We prohibit REG + REG for TFmode when there are no quad move insns
3175 and we consequently need to split. We do this because REG+REG
3176 is not an offsettable address. If we get the situation in reload
3177 where source and destination of a movtf pattern are both MEMs with
3178 REG+REG address, then only one of them gets converted to an
3179 offsettable address. */
3180 if (mode == TFmode
3181 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3182 return 0;
3183
3184 /* We prohibit REG + REG on ARCH32 if not optimizing for
3185 DFmode/DImode because then mem_min_alignment is likely to be zero
3186 after reload and the forced split would lack a matching splitter
3187 pattern. */
3188 if (TARGET_ARCH32 && !optimize
3189 && (mode == DFmode || mode == DImode))
3190 return 0;
3191 }
3192 else if (USE_AS_OFFSETABLE_LO10
3193 && GET_CODE (rs1) == LO_SUM
3194 && TARGET_ARCH64
3195 && ! TARGET_CM_MEDMID
3196 && RTX_OK_FOR_OLO10_P (rs2, mode))
3197 {
3198 rs2 = NULL;
3199 imm1 = XEXP (rs1, 1);
3200 rs1 = XEXP (rs1, 0);
3201 if (!CONSTANT_P (imm1)
3202 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3203 return 0;
3204 }
3205 }
3206 else if (GET_CODE (addr) == LO_SUM)
3207 {
3208 rs1 = XEXP (addr, 0);
3209 imm1 = XEXP (addr, 1);
3210
3211 if (!CONSTANT_P (imm1)
3212 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3213 return 0;
3214
3215 /* We can't allow TFmode in 32-bit mode, because an offset greater
3216 than the alignment (8) may cause the LO_SUM to overflow. */
3217 if (mode == TFmode && TARGET_ARCH32)
3218 return 0;
3219 }
3220 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3221 return 1;
3222 else
3223 return 0;
3224
3225 if (GET_CODE (rs1) == SUBREG)
3226 rs1 = SUBREG_REG (rs1);
3227 if (!REG_P (rs1))
3228 return 0;
3229
3230 if (rs2)
3231 {
3232 if (GET_CODE (rs2) == SUBREG)
3233 rs2 = SUBREG_REG (rs2);
3234 if (!REG_P (rs2))
3235 return 0;
3236 }
3237
3238 if (strict)
3239 {
3240 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3241 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3242 return 0;
3243 }
3244 else
3245 {
3246 if ((REGNO (rs1) >= 32
3247 && REGNO (rs1) != FRAME_POINTER_REGNUM
3248 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3249 || (rs2
3250 && (REGNO (rs2) >= 32
3251 && REGNO (rs2) != FRAME_POINTER_REGNUM
3252 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3253 return 0;
3254 }
3255 return 1;
3256 }
3257
3258 /* Return the SYMBOL_REF for the tls_get_addr function. */
3259
3260 static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
3261
3262 static rtx
3263 sparc_tls_get_addr (void)
3264 {
3265 if (!sparc_tls_symbol)
3266 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3267
3268 return sparc_tls_symbol;
3269 }
3270
3271 /* Return the Global Offset Table to be used in TLS mode. */
3272
3273 static rtx
3274 sparc_tls_got (void)
3275 {
3276 /* In PIC mode, this is just the PIC offset table. */
3277 if (flag_pic)
3278 {
3279 crtl->uses_pic_offset_table = 1;
3280 return pic_offset_table_rtx;
3281 }
3282
3283 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3284 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3285 if (TARGET_SUN_TLS && TARGET_ARCH32)
3286 {
3287 load_got_register ();
3288 return global_offset_table_rtx;
3289 }
3290
3291 /* In all other cases, we load a new pseudo with the GOT symbol. */
3292 return copy_to_reg (sparc_got ());
3293 }
3294
3295 /* Return true if X contains a thread-local symbol. */
3296
3297 static bool
3298 sparc_tls_referenced_p (rtx x)
3299 {
3300 if (!TARGET_HAVE_TLS)
3301 return false;
3302
3303 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
3304 x = XEXP (XEXP (x, 0), 0);
3305
3306 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
3307 return true;
3308
3309 /* That's all we handle in sparc_legitimize_tls_address for now. */
3310 return false;
3311 }
3312
3313 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3314 this (thread-local) address. */
3315
3316 static rtx
3317 sparc_legitimize_tls_address (rtx addr)
3318 {
3319 rtx temp1, temp2, temp3, ret, o0, got, insn;
3320
3321 gcc_assert (can_create_pseudo_p ());
3322
3323 if (GET_CODE (addr) == SYMBOL_REF)
3324 switch (SYMBOL_REF_TLS_MODEL (addr))
3325 {
3326 case TLS_MODEL_GLOBAL_DYNAMIC:
3327 start_sequence ();
3328 temp1 = gen_reg_rtx (SImode);
3329 temp2 = gen_reg_rtx (SImode);
3330 ret = gen_reg_rtx (Pmode);
3331 o0 = gen_rtx_REG (Pmode, 8);
3332 got = sparc_tls_got ();
3333 emit_insn (gen_tgd_hi22 (temp1, addr));
3334 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3335 if (TARGET_ARCH32)
3336 {
3337 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3338 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3339 addr, const1_rtx));
3340 }
3341 else
3342 {
3343 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3344 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3345 addr, const1_rtx));
3346 }
3347 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3348 insn = get_insns ();
3349 end_sequence ();
3350 emit_libcall_block (insn, ret, o0, addr);
3351 break;
3352
3353 case TLS_MODEL_LOCAL_DYNAMIC:
3354 start_sequence ();
3355 temp1 = gen_reg_rtx (SImode);
3356 temp2 = gen_reg_rtx (SImode);
3357 temp3 = gen_reg_rtx (Pmode);
3358 ret = gen_reg_rtx (Pmode);
3359 o0 = gen_rtx_REG (Pmode, 8);
3360 got = sparc_tls_got ();
3361 emit_insn (gen_tldm_hi22 (temp1));
3362 emit_insn (gen_tldm_lo10 (temp2, temp1));
3363 if (TARGET_ARCH32)
3364 {
3365 emit_insn (gen_tldm_add32 (o0, got, temp2));
3366 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3367 const1_rtx));
3368 }
3369 else
3370 {
3371 emit_insn (gen_tldm_add64 (o0, got, temp2));
3372 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3373 const1_rtx));
3374 }
3375 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3376 insn = get_insns ();
3377 end_sequence ();
3378 emit_libcall_block (insn, temp3, o0,
3379 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3380 UNSPEC_TLSLD_BASE));
3381 temp1 = gen_reg_rtx (SImode);
3382 temp2 = gen_reg_rtx (SImode);
3383 emit_insn (gen_tldo_hix22 (temp1, addr));
3384 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3385 if (TARGET_ARCH32)
3386 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3387 else
3388 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3389 break;
3390
3391 case TLS_MODEL_INITIAL_EXEC:
3392 temp1 = gen_reg_rtx (SImode);
3393 temp2 = gen_reg_rtx (SImode);
3394 temp3 = gen_reg_rtx (Pmode);
3395 got = sparc_tls_got ();
3396 emit_insn (gen_tie_hi22 (temp1, addr));
3397 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3398 if (TARGET_ARCH32)
3399 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3400 else
3401 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3402 if (TARGET_SUN_TLS)
3403 {
3404 ret = gen_reg_rtx (Pmode);
3405 if (TARGET_ARCH32)
3406 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3407 temp3, addr));
3408 else
3409 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3410 temp3, addr));
3411 }
3412 else
3413 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3414 break;
3415
3416 case TLS_MODEL_LOCAL_EXEC:
3417 temp1 = gen_reg_rtx (Pmode);
3418 temp2 = gen_reg_rtx (Pmode);
3419 if (TARGET_ARCH32)
3420 {
3421 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3422 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3423 }
3424 else
3425 {
3426 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3427 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3428 }
3429 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3430 break;
3431
3432 default:
3433 gcc_unreachable ();
3434 }
3435
3436 else if (GET_CODE (addr) == CONST)
3437 {
3438 rtx base, offset;
3439
3440 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
3441
3442 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
3443 offset = XEXP (XEXP (addr, 0), 1);
3444
3445 base = force_operand (base, NULL_RTX);
3446 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
3447 offset = force_reg (Pmode, offset);
3448 ret = gen_rtx_PLUS (Pmode, base, offset);
3449 }
3450
3451 else
3452 gcc_unreachable (); /* for now ... */
3453
3454 return ret;
3455 }
3456
3457 /* Legitimize PIC addresses. If the address is already position-independent,
3458 we return ORIG. Newly generated position-independent addresses go into a
3459 reg. This is REG if nonzero, otherwise we allocate register(s) as
3460 necessary. */
3461
3462 static rtx
3463 sparc_legitimize_pic_address (rtx orig, rtx reg)
3464 {
3465 bool gotdata_op = false;
3466
3467 if (GET_CODE (orig) == SYMBOL_REF
3468 /* See the comment in sparc_expand_move. */
3469 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
3470 {
3471 rtx pic_ref, address;
3472 rtx insn;
3473
3474 if (reg == 0)
3475 {
3476 gcc_assert (! reload_in_progress && ! reload_completed);
3477 reg = gen_reg_rtx (Pmode);
3478 }
3479
3480 if (flag_pic == 2)
3481 {
3482 /* If not during reload, allocate another temp reg here for loading
3483 in the address, so that these instructions can be optimized
3484 properly. */
3485 rtx temp_reg = ((reload_in_progress || reload_completed)
3486 ? reg : gen_reg_rtx (Pmode));
3487
3488 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3489 won't get confused into thinking that these two instructions
3490 are loading in the true address of the symbol. If in the
3491 future a PIC rtx exists, that should be used instead. */
3492 if (TARGET_ARCH64)
3493 {
3494 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3495 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3496 }
3497 else
3498 {
3499 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3500 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3501 }
3502 address = temp_reg;
3503 gotdata_op = true;
3504 }
3505 else
3506 address = orig;
3507
3508 crtl->uses_pic_offset_table = 1;
3509 if (gotdata_op)
3510 {
3511 if (TARGET_ARCH64)
3512 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
3513 pic_offset_table_rtx,
3514 address, orig));
3515 else
3516 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
3517 pic_offset_table_rtx,
3518 address, orig));
3519 }
3520 else
3521 {
3522 pic_ref
3523 = gen_const_mem (Pmode,
3524 gen_rtx_PLUS (Pmode,
3525 pic_offset_table_rtx, address));
3526 insn = emit_move_insn (reg, pic_ref);
3527 }
3528
3529 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3530 by loop. */
3531 set_unique_reg_note (insn, REG_EQUAL, orig);
3532 return reg;
3533 }
3534 else if (GET_CODE (orig) == CONST)
3535 {
3536 rtx base, offset;
3537
3538 if (GET_CODE (XEXP (orig, 0)) == PLUS
3539 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3540 return orig;
3541
3542 if (reg == 0)
3543 {
3544 gcc_assert (! reload_in_progress && ! reload_completed);
3545 reg = gen_reg_rtx (Pmode);
3546 }
3547
3548 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3549 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
3550 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
3551 base == reg ? NULL_RTX : reg);
3552
3553 if (GET_CODE (offset) == CONST_INT)
3554 {
3555 if (SMALL_INT (offset))
3556 return plus_constant (base, INTVAL (offset));
3557 else if (! reload_in_progress && ! reload_completed)
3558 offset = force_reg (Pmode, offset);
3559 else
3560 /* If we reach here, then something is seriously wrong. */
3561 gcc_unreachable ();
3562 }
3563 return gen_rtx_PLUS (Pmode, base, offset);
3564 }
3565 else if (GET_CODE (orig) == LABEL_REF)
3566 /* ??? We ought to be checking that the register is live instead, in case
3567 it is eliminated. */
3568 crtl->uses_pic_offset_table = 1;
3569
3570 return orig;
3571 }
3572
3573 /* Try machine-dependent ways of modifying an illegitimate address X
3574 to be legitimate. If we find one, return the new, valid address.
3575
3576 OLDX is the address as it was before break_out_memory_refs was called.
3577 In some cases it is useful to look at this to decide what needs to be done.
3578
3579 MODE is the mode of the operand pointed to by X.
3580
3581 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3582
3583 static rtx
3584 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3585 enum machine_mode mode)
3586 {
3587 rtx orig_x = x;
3588
3589 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3590 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3591 force_operand (XEXP (x, 0), NULL_RTX));
3592 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3593 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3594 force_operand (XEXP (x, 1), NULL_RTX));
3595 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3596 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3597 XEXP (x, 1));
3598 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3599 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3600 force_operand (XEXP (x, 1), NULL_RTX));
3601
3602 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
3603 return x;
3604
3605 if (sparc_tls_referenced_p (x))
3606 x = sparc_legitimize_tls_address (x);
3607 else if (flag_pic)
3608 x = sparc_legitimize_pic_address (x, NULL_RTX);
3609 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3610 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3611 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3612 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3613 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3614 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3615 else if (GET_CODE (x) == SYMBOL_REF
3616 || GET_CODE (x) == CONST
3617 || GET_CODE (x) == LABEL_REF)
3618 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3619
3620 return x;
3621 }
3622
3623 /* Delegitimize an address that was legitimized by the above function. */
3624
3625 static rtx
3626 sparc_delegitimize_address (rtx x)
3627 {
3628 x = delegitimize_mem_from_attrs (x);
3629
3630 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
3631 switch (XINT (XEXP (x, 1), 1))
3632 {
3633 case UNSPEC_MOVE_PIC:
3634 case UNSPEC_TLSLE:
3635 x = XVECEXP (XEXP (x, 1), 0, 0);
3636 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3637 break;
3638 default:
3639 break;
3640 }
3641
3642 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3643 if (GET_CODE (x) == MINUS
3644 && REG_P (XEXP (x, 0))
3645 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
3646 && GET_CODE (XEXP (x, 1)) == LO_SUM
3647 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
3648 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
3649 {
3650 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
3651 gcc_assert (GET_CODE (x) == LABEL_REF);
3652 }
3653
3654 return x;
3655 }
3656
3657 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3658 replace the input X, or the original X if no replacement is called for.
3659 The output parameter *WIN is 1 if the calling macro should goto WIN,
3660 0 if it should not.
3661
3662 For SPARC, we wish to handle addresses by splitting them into
3663 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3664 This cuts the number of extra insns by one.
3665
3666 Do nothing when generating PIC code and the address is a symbolic
3667 operand or requires a scratch register. */
3668
3669 rtx
3670 sparc_legitimize_reload_address (rtx x, enum machine_mode mode,
3671 int opnum, int type,
3672 int ind_levels ATTRIBUTE_UNUSED, int *win)
3673 {
3674 /* Decompose SImode constants into HIGH+LO_SUM. */
3675 if (CONSTANT_P (x)
3676 && (mode != TFmode || TARGET_ARCH64)
3677 && GET_MODE (x) == SImode
3678 && GET_CODE (x) != LO_SUM
3679 && GET_CODE (x) != HIGH
3680 && sparc_cmodel <= CM_MEDLOW
3681 && !(flag_pic
3682 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
3683 {
3684 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
3685 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3686 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3687 opnum, (enum reload_type)type);
3688 *win = 1;
3689 return x;
3690 }
3691
3692 /* We have to recognize what we have already generated above. */
3693 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
3694 {
3695 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3696 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3697 opnum, (enum reload_type)type);
3698 *win = 1;
3699 return x;
3700 }
3701
3702 *win = 0;
3703 return x;
3704 }
3705
3706 /* Return true if ADDR (a legitimate address expression)
3707 has an effect that depends on the machine mode it is used for.
3708
3709 In PIC mode,
3710
3711 (mem:HI [%l7+a])
3712
3713 is not equivalent to
3714
3715 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3716
3717 because [%l7+a+1] is interpreted as the address of (a+1). */
3718
3719
3720 static bool
3721 sparc_mode_dependent_address_p (const_rtx addr)
3722 {
3723 if (flag_pic && GET_CODE (addr) == PLUS)
3724 {
3725 rtx op0 = XEXP (addr, 0);
3726 rtx op1 = XEXP (addr, 1);
3727 if (op0 == pic_offset_table_rtx
3728 && symbolic_operand (op1, VOIDmode))
3729 return true;
3730 }
3731
3732 return false;
3733 }
3734
3735 #ifdef HAVE_GAS_HIDDEN
3736 # define USE_HIDDEN_LINKONCE 1
3737 #else
3738 # define USE_HIDDEN_LINKONCE 0
3739 #endif
3740
3741 static void
3742 get_pc_thunk_name (char name[32], unsigned int regno)
3743 {
3744 const char *reg_name = reg_names[regno];
3745
3746 /* Skip the leading '%' as that cannot be used in a
3747 symbol name. */
3748 reg_name += 1;
3749
3750 if (USE_HIDDEN_LINKONCE)
3751 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
3752 else
3753 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
3754 }
3755
3756 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3757
3758 static rtx
3759 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
3760 {
3761 int orig_flag_pic = flag_pic;
3762 rtx insn;
3763
3764 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3765 flag_pic = 0;
3766 if (TARGET_ARCH64)
3767 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
3768 else
3769 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
3770 flag_pic = orig_flag_pic;
3771
3772 return insn;
3773 }
3774
3775 /* Emit code to load the GOT register. */
3776
3777 void
3778 load_got_register (void)
3779 {
3780 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3781 if (!global_offset_table_rtx)
3782 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
3783
3784 if (TARGET_VXWORKS_RTP)
3785 emit_insn (gen_vxworks_load_got ());
3786 else
3787 {
3788 /* The GOT symbol is subject to a PC-relative relocation so we need a
3789 helper function to add the PC value and thus get the final value. */
3790 if (!got_helper_rtx)
3791 {
3792 char name[32];
3793 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
3794 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
3795 }
3796
3797 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
3798 got_helper_rtx,
3799 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
3800 }
3801
3802 /* Need to emit this whether or not we obey regdecls,
3803 since setjmp/longjmp can cause life info to screw up.
3804 ??? In the case where we don't obey regdecls, this is not sufficient
3805 since we may not fall out the bottom. */
3806 emit_use (global_offset_table_rtx);
3807 }
3808
3809 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3810 address of the call target. */
3811
3812 void
3813 sparc_emit_call_insn (rtx pat, rtx addr)
3814 {
3815 rtx insn;
3816
3817 insn = emit_call_insn (pat);
3818
3819 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3820 if (TARGET_VXWORKS_RTP
3821 && flag_pic
3822 && GET_CODE (addr) == SYMBOL_REF
3823 && (SYMBOL_REF_DECL (addr)
3824 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
3825 : !SYMBOL_REF_LOCAL_P (addr)))
3826 {
3827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3828 crtl->uses_pic_offset_table = 1;
3829 }
3830 }
3831 \f
3832 /* Return 1 if RTX is a MEM which is known to be aligned to at
3833 least a DESIRED byte boundary. */
3834
3835 int
3836 mem_min_alignment (rtx mem, int desired)
3837 {
3838 rtx addr, base, offset;
3839
3840 /* If it's not a MEM we can't accept it. */
3841 if (GET_CODE (mem) != MEM)
3842 return 0;
3843
3844 /* Obviously... */
3845 if (!TARGET_UNALIGNED_DOUBLES
3846 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
3847 return 1;
3848
3849 /* ??? The rest of the function predates MEM_ALIGN so
3850 there is probably a bit of redundancy. */
3851 addr = XEXP (mem, 0);
3852 base = offset = NULL_RTX;
3853 if (GET_CODE (addr) == PLUS)
3854 {
3855 if (GET_CODE (XEXP (addr, 0)) == REG)
3856 {
3857 base = XEXP (addr, 0);
3858
3859 /* What we are saying here is that if the base
3860 REG is aligned properly, the compiler will make
3861 sure any REG based index upon it will be so
3862 as well. */
3863 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3864 offset = XEXP (addr, 1);
3865 else
3866 offset = const0_rtx;
3867 }
3868 }
3869 else if (GET_CODE (addr) == REG)
3870 {
3871 base = addr;
3872 offset = const0_rtx;
3873 }
3874
3875 if (base != NULL_RTX)
3876 {
3877 int regno = REGNO (base);
3878
3879 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3880 {
3881 /* Check if the compiler has recorded some information
3882 about the alignment of the base REG. If reload has
3883 completed, we already matched with proper alignments.
3884 If not running global_alloc, reload might give us
3885 unaligned pointer to local stack though. */
3886 if (((cfun != 0
3887 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3888 || (optimize && reload_completed))
3889 && (INTVAL (offset) & (desired - 1)) == 0)
3890 return 1;
3891 }
3892 else
3893 {
3894 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3895 return 1;
3896 }
3897 }
3898 else if (! TARGET_UNALIGNED_DOUBLES
3899 || CONSTANT_P (addr)
3900 || GET_CODE (addr) == LO_SUM)
3901 {
3902 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3903 is true, in which case we can only assume that an access is aligned if
3904 it is to a constant address, or the address involves a LO_SUM. */
3905 return 1;
3906 }
3907
3908 /* An obviously unaligned address. */
3909 return 0;
3910 }
3911
3912 \f
3913 /* Vectors to keep interesting information about registers where it can easily
3914 be got. We used to use the actual mode value as the bit number, but there
3915 are more than 32 modes now. Instead we use two tables: one indexed by
3916 hard register number, and one indexed by mode. */
3917
3918 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3919 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
3920 mapped into one sparc_mode_class mode. */
3921
3922 enum sparc_mode_class {
3923 S_MODE, D_MODE, T_MODE, O_MODE,
3924 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3925 CC_MODE, CCFP_MODE
3926 };
3927
3928 /* Modes for single-word and smaller quantities. */
3929 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3930
3931 /* Modes for double-word and smaller quantities. */
3932 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3933
3934 /* Modes for quad-word and smaller quantities. */
3935 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3936
3937 /* Modes for 8-word and smaller quantities. */
3938 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3939
3940 /* Modes for single-float quantities. We must allow any single word or
3941 smaller quantity. This is because the fix/float conversion instructions
3942 take integer inputs/outputs from the float registers. */
3943 #define SF_MODES (S_MODES)
3944
3945 /* Modes for double-float and smaller quantities. */
3946 #define DF_MODES (D_MODES)
3947
3948 /* Modes for quad-float and smaller quantities. */
3949 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
3950
3951 /* Modes for quad-float pairs and smaller quantities. */
3952 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
3953
3954 /* Modes for double-float only quantities. */
3955 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3956
3957 /* Modes for quad-float and double-float only quantities. */
3958 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
3959
3960 /* Modes for quad-float pairs and double-float only quantities. */
3961 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
3962
3963 /* Modes for condition codes. */
3964 #define CC_MODES (1 << (int) CC_MODE)
3965 #define CCFP_MODES (1 << (int) CCFP_MODE)
3966
3967 /* Value is 1 if register/mode pair is acceptable on sparc.
3968 The funny mixture of D and T modes is because integer operations
3969 do not specially operate on tetra quantities, so non-quad-aligned
3970 registers can hold quadword quantities (except %o4 and %i4 because
3971 they cross fixed registers). */
3972
3973 /* This points to either the 32 bit or the 64 bit version. */
3974 const int *hard_regno_mode_classes;
3975
3976 static const int hard_32bit_mode_classes[] = {
3977 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3978 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3979 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3980 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3981
3982 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3983 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3984 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3985 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3986
3987 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3988 and none can hold SFmode/SImode values. */
3989 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3990 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3991 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3992 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3993
3994 /* %fcc[0123] */
3995 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3996
3997 /* %icc */
3998 CC_MODES
3999 };
4000
4001 static const int hard_64bit_mode_classes[] = {
4002 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4003 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4004 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4005 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4006
4007 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4008 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4009 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4010 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4011
4012 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4013 and none can hold SFmode/SImode values. */
4014 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4015 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4016 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4017 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4018
4019 /* %fcc[0123] */
4020 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4021
4022 /* %icc */
4023 CC_MODES
4024 };
4025
4026 int sparc_mode_class [NUM_MACHINE_MODES];
4027
4028 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4029
4030 static void
4031 sparc_init_modes (void)
4032 {
4033 int i;
4034
4035 for (i = 0; i < NUM_MACHINE_MODES; i++)
4036 {
4037 switch (GET_MODE_CLASS (i))
4038 {
4039 case MODE_INT:
4040 case MODE_PARTIAL_INT:
4041 case MODE_COMPLEX_INT:
4042 if (GET_MODE_SIZE (i) <= 4)
4043 sparc_mode_class[i] = 1 << (int) S_MODE;
4044 else if (GET_MODE_SIZE (i) == 8)
4045 sparc_mode_class[i] = 1 << (int) D_MODE;
4046 else if (GET_MODE_SIZE (i) == 16)
4047 sparc_mode_class[i] = 1 << (int) T_MODE;
4048 else if (GET_MODE_SIZE (i) == 32)
4049 sparc_mode_class[i] = 1 << (int) O_MODE;
4050 else
4051 sparc_mode_class[i] = 0;
4052 break;
4053 case MODE_VECTOR_INT:
4054 if (GET_MODE_SIZE (i) <= 4)
4055 sparc_mode_class[i] = 1 << (int)SF_MODE;
4056 else if (GET_MODE_SIZE (i) == 8)
4057 sparc_mode_class[i] = 1 << (int)DF_MODE;
4058 break;
4059 case MODE_FLOAT:
4060 case MODE_COMPLEX_FLOAT:
4061 if (GET_MODE_SIZE (i) <= 4)
4062 sparc_mode_class[i] = 1 << (int) SF_MODE;
4063 else if (GET_MODE_SIZE (i) == 8)
4064 sparc_mode_class[i] = 1 << (int) DF_MODE;
4065 else if (GET_MODE_SIZE (i) == 16)
4066 sparc_mode_class[i] = 1 << (int) TF_MODE;
4067 else if (GET_MODE_SIZE (i) == 32)
4068 sparc_mode_class[i] = 1 << (int) OF_MODE;
4069 else
4070 sparc_mode_class[i] = 0;
4071 break;
4072 case MODE_CC:
4073 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4074 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4075 else
4076 sparc_mode_class[i] = 1 << (int) CC_MODE;
4077 break;
4078 default:
4079 sparc_mode_class[i] = 0;
4080 break;
4081 }
4082 }
4083
4084 if (TARGET_ARCH64)
4085 hard_regno_mode_classes = hard_64bit_mode_classes;
4086 else
4087 hard_regno_mode_classes = hard_32bit_mode_classes;
4088
4089 /* Initialize the array used by REGNO_REG_CLASS. */
4090 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4091 {
4092 if (i < 16 && TARGET_V8PLUS)
4093 sparc_regno_reg_class[i] = I64_REGS;
4094 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4095 sparc_regno_reg_class[i] = GENERAL_REGS;
4096 else if (i < 64)
4097 sparc_regno_reg_class[i] = FP_REGS;
4098 else if (i < 96)
4099 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4100 else if (i < 100)
4101 sparc_regno_reg_class[i] = FPCC_REGS;
4102 else
4103 sparc_regno_reg_class[i] = NO_REGS;
4104 }
4105 }
4106 \f
4107 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4108
4109 static inline bool
4110 save_global_or_fp_reg_p (unsigned int regno,
4111 int leaf_function ATTRIBUTE_UNUSED)
4112 {
4113 return !call_used_regs[regno] && df_regs_ever_live_p (regno);
4114 }
4115
4116 /* Return whether the return address register (%i7) is needed. */
4117
4118 static inline bool
4119 return_addr_reg_needed_p (int leaf_function)
4120 {
4121 /* If it is live, for example because of __builtin_return_address (0). */
4122 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM))
4123 return true;
4124
4125 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4126 if (!leaf_function
4127 /* Loading the GOT register clobbers %o7. */
4128 || crtl->uses_pic_offset_table
4129 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM))
4130 return true;
4131
4132 return false;
4133 }
4134
4135 /* Return whether REGNO, a local or in register, must be saved/restored. */
4136
4137 static bool
4138 save_local_or_in_reg_p (unsigned int regno, int leaf_function)
4139 {
4140 /* General case: call-saved registers live at some point. */
4141 if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
4142 return true;
4143
4144 /* Frame pointer register (%fp) if needed. */
4145 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
4146 return true;
4147
4148 /* Return address register (%i7) if needed. */
4149 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function))
4150 return true;
4151
4152 /* GOT register (%l7) if needed. */
4153 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
4154 return true;
4155
4156 /* If the function accesses prior frames, the frame pointer and the return
4157 address of the previous frame must be saved on the stack. */
4158 if (crtl->accesses_prior_frames
4159 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM))
4160 return true;
4161
4162 return false;
4163 }
4164
4165 /* Compute the frame size required by the function. This function is called
4166 during the reload pass and also by sparc_expand_prologue. */
4167
4168 HOST_WIDE_INT
4169 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4170 {
4171 HOST_WIDE_INT frame_size, apparent_frame_size;
4172 int args_size, n_global_fp_regs = 0;
4173 bool save_local_in_regs_p = false;
4174 unsigned int i;
4175
4176 /* If the function allocates dynamic stack space, the dynamic offset is
4177 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4178 if (leaf_function && !cfun->calls_alloca)
4179 args_size = 0;
4180 else
4181 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl);
4182
4183 /* Calculate space needed for global registers. */
4184 if (TARGET_ARCH64)
4185 for (i = 0; i < 8; i++)
4186 if (save_global_or_fp_reg_p (i, 0))
4187 n_global_fp_regs += 2;
4188 else
4189 for (i = 0; i < 8; i += 2)
4190 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4191 n_global_fp_regs += 2;
4192
4193 /* In the flat window model, find out which local and in registers need to
4194 be saved. We don't reserve space in the current frame for them as they
4195 will be spilled into the register window save area of the caller's frame.
4196 However, as soon as we use this register window save area, we must create
4197 that of the current frame to make it the live one. */
4198 if (TARGET_FLAT)
4199 for (i = 16; i < 32; i++)
4200 if (save_local_or_in_reg_p (i, leaf_function))
4201 {
4202 save_local_in_regs_p = true;
4203 break;
4204 }
4205
4206 /* Calculate space needed for FP registers. */
4207 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4208 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4209 n_global_fp_regs += 2;
4210
4211 if (size == 0
4212 && n_global_fp_regs == 0
4213 && args_size == 0
4214 && !save_local_in_regs_p)
4215 frame_size = apparent_frame_size = 0;
4216 else
4217 {
4218 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4219 apparent_frame_size = (size - STARTING_FRAME_OFFSET + 7) & -8;
4220 apparent_frame_size += n_global_fp_regs * 4;
4221
4222 /* We need to add the size of the outgoing argument area. */
4223 frame_size = apparent_frame_size + ((args_size + 7) & -8);
4224
4225 /* And that of the register window save area. */
4226 frame_size += FIRST_PARM_OFFSET (cfun->decl);
4227
4228 /* Finally, bump to the appropriate alignment. */
4229 frame_size = SPARC_STACK_ALIGN (frame_size);
4230 }
4231
4232 /* Set up values for use in prologue and epilogue. */
4233 sparc_frame_size = frame_size;
4234 sparc_apparent_frame_size = apparent_frame_size;
4235 sparc_n_global_fp_regs = n_global_fp_regs;
4236 sparc_save_local_in_regs_p = save_local_in_regs_p;
4237
4238 return frame_size;
4239 }
4240
4241 /* Output any necessary .register pseudo-ops. */
4242
4243 void
4244 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4245 {
4246 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4247 int i;
4248
4249 if (TARGET_ARCH32)
4250 return;
4251
4252 /* Check if %g[2367] were used without
4253 .register being printed for them already. */
4254 for (i = 2; i < 8; i++)
4255 {
4256 if (df_regs_ever_live_p (i)
4257 && ! sparc_hard_reg_printed [i])
4258 {
4259 sparc_hard_reg_printed [i] = 1;
4260 /* %g7 is used as TLS base register, use #ignore
4261 for it instead of #scratch. */
4262 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
4263 i == 7 ? "ignore" : "scratch");
4264 }
4265 if (i == 3) i = 5;
4266 }
4267 #endif
4268 }
4269
4270 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4271
4272 #if PROBE_INTERVAL > 4096
4273 #error Cannot use indexed addressing mode for stack probing
4274 #endif
4275
4276 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4277 inclusive. These are offsets from the current stack pointer.
4278
4279 Note that we don't use the REG+REG addressing mode for the probes because
4280 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4281 so the advantages of having a single code win here. */
4282
4283 static void
4284 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
4285 {
4286 rtx g1 = gen_rtx_REG (Pmode, 1);
4287
4288 /* See if we have a constant small number of probes to generate. If so,
4289 that's the easy case. */
4290 if (size <= PROBE_INTERVAL)
4291 {
4292 emit_move_insn (g1, GEN_INT (first));
4293 emit_insn (gen_rtx_SET (VOIDmode, g1,
4294 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4295 emit_stack_probe (plus_constant (g1, -size));
4296 }
4297
4298 /* The run-time loop is made up of 10 insns in the generic case while the
4299 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4300 else if (size <= 5 * PROBE_INTERVAL)
4301 {
4302 HOST_WIDE_INT i;
4303
4304 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
4305 emit_insn (gen_rtx_SET (VOIDmode, g1,
4306 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4307 emit_stack_probe (g1);
4308
4309 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4310 it exceeds SIZE. If only two probes are needed, this will not
4311 generate any code. Then probe at FIRST + SIZE. */
4312 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
4313 {
4314 emit_insn (gen_rtx_SET (VOIDmode, g1,
4315 plus_constant (g1, -PROBE_INTERVAL)));
4316 emit_stack_probe (g1);
4317 }
4318
4319 emit_stack_probe (plus_constant (g1, (i - PROBE_INTERVAL) - size));
4320 }
4321
4322 /* Otherwise, do the same as above, but in a loop. Note that we must be
4323 extra careful with variables wrapping around because we might be at
4324 the very top (or the very bottom) of the address space and we have
4325 to be able to handle this case properly; in particular, we use an
4326 equality test for the loop condition. */
4327 else
4328 {
4329 HOST_WIDE_INT rounded_size;
4330 rtx g4 = gen_rtx_REG (Pmode, 4);
4331
4332 emit_move_insn (g1, GEN_INT (first));
4333
4334
4335 /* Step 1: round SIZE to the previous multiple of the interval. */
4336
4337 rounded_size = size & -PROBE_INTERVAL;
4338 emit_move_insn (g4, GEN_INT (rounded_size));
4339
4340
4341 /* Step 2: compute initial and final value of the loop counter. */
4342
4343 /* TEST_ADDR = SP + FIRST. */
4344 emit_insn (gen_rtx_SET (VOIDmode, g1,
4345 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4346
4347 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4348 emit_insn (gen_rtx_SET (VOIDmode, g4, gen_rtx_MINUS (Pmode, g1, g4)));
4349
4350
4351 /* Step 3: the loop
4352
4353 while (TEST_ADDR != LAST_ADDR)
4354 {
4355 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4356 probe at TEST_ADDR
4357 }
4358
4359 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4360 until it is equal to ROUNDED_SIZE. */
4361
4362 if (TARGET_64BIT)
4363 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
4364 else
4365 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
4366
4367
4368 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4369 that SIZE is equal to ROUNDED_SIZE. */
4370
4371 if (size != rounded_size)
4372 emit_stack_probe (plus_constant (g4, rounded_size - size));
4373 }
4374
4375 /* Make sure nothing is scheduled before we are done. */
4376 emit_insn (gen_blockage ());
4377 }
4378
4379 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4380 absolute addresses. */
4381
4382 const char *
4383 output_probe_stack_range (rtx reg1, rtx reg2)
4384 {
4385 static int labelno = 0;
4386 char loop_lab[32], end_lab[32];
4387 rtx xops[2];
4388
4389 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
4390 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
4391
4392 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
4393
4394 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4395 xops[0] = reg1;
4396 xops[1] = reg2;
4397 output_asm_insn ("cmp\t%0, %1", xops);
4398 if (TARGET_ARCH64)
4399 fputs ("\tbe,pn\t%xcc,", asm_out_file);
4400 else
4401 fputs ("\tbe\t", asm_out_file);
4402 assemble_name_raw (asm_out_file, end_lab);
4403 fputc ('\n', asm_out_file);
4404
4405 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4406 xops[1] = GEN_INT (-PROBE_INTERVAL);
4407 output_asm_insn (" add\t%0, %1, %0", xops);
4408
4409 /* Probe at TEST_ADDR and branch. */
4410 if (TARGET_ARCH64)
4411 fputs ("\tba,pt\t%xcc,", asm_out_file);
4412 else
4413 fputs ("\tba\t", asm_out_file);
4414 assemble_name_raw (asm_out_file, loop_lab);
4415 fputc ('\n', asm_out_file);
4416 xops[1] = GEN_INT (SPARC_STACK_BIAS);
4417 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
4418
4419 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
4420
4421 return "";
4422 }
4423
4424 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4425 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4426 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4427 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4428 the action to be performed if it returns false. Return the new offset. */
4429
4430 typedef bool (*sorr_pred_t) (unsigned int, int);
4431 typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t;
4432
4433 static int
4434 emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base,
4435 int offset, int leaf_function, sorr_pred_t save_p,
4436 sorr_act_t action_true, sorr_act_t action_false)
4437 {
4438 unsigned int i;
4439 rtx mem, insn;
4440
4441 if (TARGET_ARCH64 && high <= 32)
4442 {
4443 int fp_offset = -1;
4444
4445 for (i = low; i < high; i++)
4446 {
4447 if (save_p (i, leaf_function))
4448 {
4449 mem = gen_frame_mem (DImode, plus_constant (base, offset));
4450 if (action_true == SORR_SAVE)
4451 {
4452 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4453 RTX_FRAME_RELATED_P (insn) = 1;
4454 }
4455 else /* action_true == SORR_RESTORE */
4456 {
4457 /* The frame pointer must be restored last since its old
4458 value may be used as base address for the frame. This
4459 is problematic in 64-bit mode only because of the lack
4460 of double-word load instruction. */
4461 if (i == HARD_FRAME_POINTER_REGNUM)
4462 fp_offset = offset;
4463 else
4464 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4465 }
4466 offset += 8;
4467 }
4468 else if (action_false == SORR_ADVANCE)
4469 offset += 8;
4470 }
4471
4472 if (fp_offset >= 0)
4473 {
4474 mem = gen_frame_mem (DImode, plus_constant (base, fp_offset));
4475 emit_move_insn (hard_frame_pointer_rtx, mem);
4476 }
4477 }
4478 else
4479 {
4480 for (i = low; i < high; i += 2)
4481 {
4482 bool reg0 = save_p (i, leaf_function);
4483 bool reg1 = save_p (i + 1, leaf_function);
4484 enum machine_mode mode;
4485 int regno;
4486
4487 if (reg0 && reg1)
4488 {
4489 mode = i < 32 ? DImode : DFmode;
4490 regno = i;
4491 }
4492 else if (reg0)
4493 {
4494 mode = i < 32 ? SImode : SFmode;
4495 regno = i;
4496 }
4497 else if (reg1)
4498 {
4499 mode = i < 32 ? SImode : SFmode;
4500 regno = i + 1;
4501 offset += 4;
4502 }
4503 else
4504 {
4505 if (action_false == SORR_ADVANCE)
4506 offset += 8;
4507 continue;
4508 }
4509
4510 mem = gen_frame_mem (mode, plus_constant (base, offset));
4511 if (action_true == SORR_SAVE)
4512 {
4513 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4514 RTX_FRAME_RELATED_P (insn) = 1;
4515 if (mode == DImode)
4516 {
4517 rtx set1, set2;
4518 mem = gen_frame_mem (SImode, plus_constant (base, offset));
4519 set1 = gen_rtx_SET (VOIDmode, mem,
4520 gen_rtx_REG (SImode, regno));
4521 RTX_FRAME_RELATED_P (set1) = 1;
4522 mem
4523 = gen_frame_mem (SImode, plus_constant (base, offset + 4));
4524 set2 = gen_rtx_SET (VOIDmode, mem,
4525 gen_rtx_REG (SImode, regno + 1));
4526 RTX_FRAME_RELATED_P (set2) = 1;
4527 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4528 gen_rtx_PARALLEL (VOIDmode,
4529 gen_rtvec (2, set1, set2)));
4530 }
4531 }
4532 else /* action_true == SORR_RESTORE */
4533 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4534
4535 /* Always preserve double-word alignment. */
4536 offset = (offset + 8) & -8;
4537 }
4538 }
4539
4540 return offset;
4541 }
4542
4543 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4544
4545 static rtx
4546 emit_adjust_base_to_offset (rtx base, int offset)
4547 {
4548 /* ??? This might be optimized a little as %g1 might already have a
4549 value close enough that a single add insn will do. */
4550 /* ??? Although, all of this is probably only a temporary fix because
4551 if %g1 can hold a function result, then sparc_expand_epilogue will
4552 lose (the result will be clobbered). */
4553 rtx new_base = gen_rtx_REG (Pmode, 1);
4554 emit_move_insn (new_base, GEN_INT (offset));
4555 emit_insn (gen_rtx_SET (VOIDmode,
4556 new_base, gen_rtx_PLUS (Pmode, base, new_base)));
4557 return new_base;
4558 }
4559
4560 /* Emit code to save/restore call-saved global and FP registers. */
4561
4562 static void
4563 emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action)
4564 {
4565 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095)
4566 {
4567 base = emit_adjust_base_to_offset (base, offset);
4568 offset = 0;
4569 }
4570
4571 offset
4572 = emit_save_or_restore_regs (0, 8, base, offset, 0,
4573 save_global_or_fp_reg_p, action, SORR_NONE);
4574 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0,
4575 save_global_or_fp_reg_p, action, SORR_NONE);
4576 }
4577
4578 /* Emit code to save/restore call-saved local and in registers. */
4579
4580 static void
4581 emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action)
4582 {
4583 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095)
4584 {
4585 base = emit_adjust_base_to_offset (base, offset);
4586 offset = 0;
4587 }
4588
4589 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p,
4590 save_local_or_in_reg_p, action, SORR_ADVANCE);
4591 }
4592
4593 /* Generate a save_register_window insn. */
4594
4595 static rtx
4596 emit_save_register_window (rtx increment)
4597 {
4598 rtx insn;
4599
4600 insn = emit_insn (gen_save_register_window_1 (increment));
4601 RTX_FRAME_RELATED_P (insn) = 1;
4602
4603 /* The incoming return address (%o7) is saved in %i7. */
4604 add_reg_note (insn, REG_CFA_REGISTER,
4605 gen_rtx_SET (VOIDmode,
4606 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM),
4607 gen_rtx_REG (Pmode,
4608 INCOMING_RETURN_ADDR_REGNUM)));
4609
4610 /* The window save event. */
4611 add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx);
4612
4613 /* The CFA is %fp, the hard frame pointer. */
4614 add_reg_note (insn, REG_CFA_DEF_CFA,
4615 plus_constant (hard_frame_pointer_rtx,
4616 INCOMING_FRAME_SP_OFFSET));
4617
4618 return insn;
4619 }
4620
4621 /* Generate an increment for the stack pointer. */
4622
4623 static rtx
4624 gen_stack_pointer_inc (rtx increment)
4625 {
4626 return gen_rtx_SET (VOIDmode,
4627 stack_pointer_rtx,
4628 gen_rtx_PLUS (Pmode,
4629 stack_pointer_rtx,
4630 increment));
4631 }
4632
4633 /* Generate a decrement for the stack pointer. */
4634
4635 static rtx
4636 gen_stack_pointer_dec (rtx decrement)
4637 {
4638 return gen_rtx_SET (VOIDmode,
4639 stack_pointer_rtx,
4640 gen_rtx_MINUS (Pmode,
4641 stack_pointer_rtx,
4642 decrement));
4643 }
4644
4645 /* Expand the function prologue. The prologue is responsible for reserving
4646 storage for the frame, saving the call-saved registers and loading the
4647 GOT register if needed. */
4648
4649 void
4650 sparc_expand_prologue (void)
4651 {
4652 HOST_WIDE_INT size;
4653 rtx insn;
4654
4655 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4656 on the final value of the flag means deferring the prologue/epilogue
4657 expansion until just before the second scheduling pass, which is too
4658 late to emit multiple epilogues or return insns.
4659
4660 Of course we are making the assumption that the value of the flag
4661 will not change between now and its final value. Of the three parts
4662 of the formula, only the last one can reasonably vary. Let's take a
4663 closer look, after assuming that the first two ones are set to true
4664 (otherwise the last value is effectively silenced).
4665
4666 If only_leaf_regs_used returns false, the global predicate will also
4667 be false so the actual frame size calculated below will be positive.
4668 As a consequence, the save_register_window insn will be emitted in
4669 the instruction stream; now this insn explicitly references %fp
4670 which is not a leaf register so only_leaf_regs_used will always
4671 return false subsequently.
4672
4673 If only_leaf_regs_used returns true, we hope that the subsequent
4674 optimization passes won't cause non-leaf registers to pop up. For
4675 example, the regrename pass has special provisions to not rename to
4676 non-leaf registers in a leaf function. */
4677 sparc_leaf_function_p
4678 = optimize > 0 && current_function_is_leaf && only_leaf_regs_used ();
4679
4680 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4681
4682 if (flag_stack_usage_info)
4683 current_function_static_stack_size = size;
4684
4685 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4686 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
4687
4688 if (size == 0)
4689 ; /* do nothing. */
4690 else if (sparc_leaf_function_p)
4691 {
4692 rtx size_int_rtx = GEN_INT (-size);
4693
4694 if (size <= 4096)
4695 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
4696 else if (size <= 8192)
4697 {
4698 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4699 /* %sp is still the CFA register. */
4700 RTX_FRAME_RELATED_P (insn) = 1;
4701 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4702 }
4703 else
4704 {
4705 rtx size_rtx = gen_rtx_REG (Pmode, 1);
4706 emit_move_insn (size_rtx, size_int_rtx);
4707 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
4708 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4709 gen_stack_pointer_inc (size_int_rtx));
4710 }
4711
4712 RTX_FRAME_RELATED_P (insn) = 1;
4713 }
4714 else
4715 {
4716 rtx size_int_rtx = GEN_INT (-size);
4717
4718 if (size <= 4096)
4719 emit_save_register_window (size_int_rtx);
4720 else if (size <= 8192)
4721 {
4722 emit_save_register_window (GEN_INT (-4096));
4723 /* %sp is not the CFA register anymore. */
4724 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4725 }
4726 else
4727 {
4728 rtx size_rtx = gen_rtx_REG (Pmode, 1);
4729 emit_move_insn (size_rtx, size_int_rtx);
4730 emit_save_register_window (size_rtx);
4731 }
4732 }
4733
4734 if (sparc_leaf_function_p)
4735 {
4736 sparc_frame_base_reg = stack_pointer_rtx;
4737 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
4738 }
4739 else
4740 {
4741 sparc_frame_base_reg = hard_frame_pointer_rtx;
4742 sparc_frame_base_offset = SPARC_STACK_BIAS;
4743 }
4744
4745 if (sparc_n_global_fp_regs > 0)
4746 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4747 sparc_frame_base_offset
4748 - sparc_apparent_frame_size,
4749 SORR_SAVE);
4750
4751 /* Load the GOT register if needed. */
4752 if (crtl->uses_pic_offset_table)
4753 load_got_register ();
4754
4755 /* Advertise that the data calculated just above are now valid. */
4756 sparc_prologue_data_valid_p = true;
4757 }
4758
4759 /* Expand the function prologue. The prologue is responsible for reserving
4760 storage for the frame, saving the call-saved registers and loading the
4761 GOT register if needed. */
4762
4763 void
4764 sparc_flat_expand_prologue (void)
4765 {
4766 HOST_WIDE_INT size;
4767 rtx insn;
4768
4769 sparc_leaf_function_p = optimize > 0 && current_function_is_leaf;
4770
4771 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4772
4773 if (flag_stack_usage_info)
4774 current_function_static_stack_size = size;
4775
4776 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4777 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
4778
4779 if (sparc_save_local_in_regs_p)
4780 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS,
4781 SORR_SAVE);
4782
4783 if (size == 0)
4784 ; /* do nothing. */
4785 else
4786 {
4787 rtx size_int_rtx, size_rtx;
4788
4789 size_rtx = size_int_rtx = GEN_INT (-size);
4790
4791 /* We establish the frame (i.e. decrement the stack pointer) first, even
4792 if we use a frame pointer, because we cannot clobber any call-saved
4793 registers, including the frame pointer, if we haven't created a new
4794 register save area, for the sake of compatibility with the ABI. */
4795 if (size <= 4096)
4796 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
4797 else if (size <= 8192 && !frame_pointer_needed)
4798 {
4799 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4800 RTX_FRAME_RELATED_P (insn) = 1;
4801 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4802 }
4803 else
4804 {
4805 size_rtx = gen_rtx_REG (Pmode, 1);
4806 emit_move_insn (size_rtx, size_int_rtx);
4807 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
4808 add_reg_note (insn, REG_CFA_ADJUST_CFA,
4809 gen_stack_pointer_inc (size_int_rtx));
4810 }
4811 RTX_FRAME_RELATED_P (insn) = 1;
4812
4813 /* Ensure nothing is scheduled until after the frame is established. */
4814 emit_insn (gen_blockage ());
4815
4816 if (frame_pointer_needed)
4817 {
4818 insn = emit_insn (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
4819 gen_rtx_MINUS (Pmode,
4820 stack_pointer_rtx,
4821 size_rtx)));
4822 RTX_FRAME_RELATED_P (insn) = 1;
4823
4824 add_reg_note (insn, REG_CFA_ADJUST_CFA,
4825 gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
4826 plus_constant (stack_pointer_rtx,
4827 size)));
4828 }
4829
4830 if (return_addr_reg_needed_p (sparc_leaf_function_p))
4831 {
4832 rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM);
4833 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
4834
4835 insn = emit_move_insn (i7, o7);
4836 RTX_FRAME_RELATED_P (insn) = 1;
4837
4838 add_reg_note (insn, REG_CFA_REGISTER,
4839 gen_rtx_SET (VOIDmode, i7, o7));
4840
4841 /* Prevent this instruction from ever being considered dead,
4842 even if this function has no epilogue. */
4843 emit_insn (gen_rtx_USE (VOIDmode, i7));
4844 }
4845 }
4846
4847 if (frame_pointer_needed)
4848 {
4849 sparc_frame_base_reg = hard_frame_pointer_rtx;
4850 sparc_frame_base_offset = SPARC_STACK_BIAS;
4851 }
4852 else
4853 {
4854 sparc_frame_base_reg = stack_pointer_rtx;
4855 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
4856 }
4857
4858 if (sparc_n_global_fp_regs > 0)
4859 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4860 sparc_frame_base_offset
4861 - sparc_apparent_frame_size,
4862 SORR_SAVE);
4863
4864 /* Load the GOT register if needed. */
4865 if (crtl->uses_pic_offset_table)
4866 load_got_register ();
4867
4868 /* Advertise that the data calculated just above are now valid. */
4869 sparc_prologue_data_valid_p = true;
4870 }
4871
4872 /* This function generates the assembly code for function entry, which boils
4873 down to emitting the necessary .register directives. */
4874
4875 static void
4876 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4877 {
4878 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4879 if (!TARGET_FLAT)
4880 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
4881
4882 sparc_output_scratch_registers (file);
4883 }
4884
4885 /* Expand the function epilogue, either normal or part of a sibcall.
4886 We emit all the instructions except the return or the call. */
4887
4888 void
4889 sparc_expand_epilogue (bool for_eh)
4890 {
4891 HOST_WIDE_INT size = sparc_frame_size;
4892
4893 if (sparc_n_global_fp_regs > 0)
4894 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4895 sparc_frame_base_offset
4896 - sparc_apparent_frame_size,
4897 SORR_RESTORE);
4898
4899 if (size == 0 || for_eh)
4900 ; /* do nothing. */
4901 else if (sparc_leaf_function_p)
4902 {
4903 if (size <= 4096)
4904 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
4905 else if (size <= 8192)
4906 {
4907 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4908 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
4909 }
4910 else
4911 {
4912 rtx reg = gen_rtx_REG (Pmode, 1);
4913 emit_move_insn (reg, GEN_INT (-size));
4914 emit_insn (gen_stack_pointer_dec (reg));
4915 }
4916 }
4917 }
4918
4919 /* Expand the function epilogue, either normal or part of a sibcall.
4920 We emit all the instructions except the return or the call. */
4921
4922 void
4923 sparc_flat_expand_epilogue (bool for_eh)
4924 {
4925 HOST_WIDE_INT size = sparc_frame_size;
4926
4927 if (sparc_n_global_fp_regs > 0)
4928 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4929 sparc_frame_base_offset
4930 - sparc_apparent_frame_size,
4931 SORR_RESTORE);
4932
4933 /* If we have a frame pointer, we'll need both to restore it before the
4934 frame is destroyed and use its current value in destroying the frame.
4935 Since we don't have an atomic way to do that in the flat window model,
4936 we save the current value into a temporary register (%g1). */
4937 if (frame_pointer_needed && !for_eh)
4938 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx);
4939
4940 if (return_addr_reg_needed_p (sparc_leaf_function_p))
4941 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM),
4942 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM));
4943
4944 if (sparc_save_local_in_regs_p)
4945 emit_save_or_restore_local_in_regs (sparc_frame_base_reg,
4946 sparc_frame_base_offset,
4947 SORR_RESTORE);
4948
4949 if (size == 0 || for_eh)
4950 ; /* do nothing. */
4951 else if (frame_pointer_needed)
4952 {
4953 /* Make sure the frame is destroyed after everything else is done. */
4954 emit_insn (gen_blockage ());
4955
4956 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1));
4957 }
4958 else
4959 {
4960 /* Likewise. */
4961 emit_insn (gen_blockage ());
4962
4963 if (size <= 4096)
4964 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
4965 else if (size <= 8192)
4966 {
4967 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4968 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
4969 }
4970 else
4971 {
4972 rtx reg = gen_rtx_REG (Pmode, 1);
4973 emit_move_insn (reg, GEN_INT (-size));
4974 emit_insn (gen_stack_pointer_dec (reg));
4975 }
4976 }
4977 }
4978
4979 /* Return true if it is appropriate to emit `return' instructions in the
4980 body of a function. */
4981
4982 bool
4983 sparc_can_use_return_insn_p (void)
4984 {
4985 return sparc_prologue_data_valid_p
4986 && sparc_n_global_fp_regs == 0
4987 && TARGET_FLAT
4988 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p)
4989 : (sparc_frame_size == 0 || !sparc_leaf_function_p);
4990 }
4991
4992 /* This function generates the assembly code for function exit. */
4993
4994 static void
4995 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4996 {
4997 /* If the last two instructions of a function are "call foo; dslot;"
4998 the return address might point to the first instruction in the next
4999 function and we have to output a dummy nop for the sake of sane
5000 backtraces in such cases. This is pointless for sibling calls since
5001 the return address is explicitly adjusted. */
5002
5003 rtx insn, last_real_insn;
5004
5005 insn = get_last_insn ();
5006
5007 last_real_insn = prev_real_insn (insn);
5008 if (last_real_insn
5009 && GET_CODE (last_real_insn) == INSN
5010 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
5011 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
5012
5013 if (last_real_insn
5014 && CALL_P (last_real_insn)
5015 && !SIBLING_CALL_P (last_real_insn))
5016 fputs("\tnop\n", file);
5017
5018 sparc_output_deferred_case_vectors ();
5019 }
5020
5021 /* Output a 'restore' instruction. */
5022
5023 static void
5024 output_restore (rtx pat)
5025 {
5026 rtx operands[3];
5027
5028 if (! pat)
5029 {
5030 fputs ("\t restore\n", asm_out_file);
5031 return;
5032 }
5033
5034 gcc_assert (GET_CODE (pat) == SET);
5035
5036 operands[0] = SET_DEST (pat);
5037 pat = SET_SRC (pat);
5038
5039 switch (GET_CODE (pat))
5040 {
5041 case PLUS:
5042 operands[1] = XEXP (pat, 0);
5043 operands[2] = XEXP (pat, 1);
5044 output_asm_insn (" restore %r1, %2, %Y0", operands);
5045 break;
5046 case LO_SUM:
5047 operands[1] = XEXP (pat, 0);
5048 operands[2] = XEXP (pat, 1);
5049 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
5050 break;
5051 case ASHIFT:
5052 operands[1] = XEXP (pat, 0);
5053 gcc_assert (XEXP (pat, 1) == const1_rtx);
5054 output_asm_insn (" restore %r1, %r1, %Y0", operands);
5055 break;
5056 default:
5057 operands[1] = pat;
5058 output_asm_insn (" restore %%g0, %1, %Y0", operands);
5059 break;
5060 }
5061 }
5062
5063 /* Output a return. */
5064
5065 const char *
5066 output_return (rtx insn)
5067 {
5068 if (crtl->calls_eh_return)
5069 {
5070 /* If the function uses __builtin_eh_return, the eh_return
5071 machinery occupies the delay slot. */
5072 gcc_assert (!final_sequence);
5073
5074 if (flag_delayed_branch)
5075 {
5076 if (!TARGET_FLAT && TARGET_V9)
5077 fputs ("\treturn\t%i7+8\n", asm_out_file);
5078 else
5079 {
5080 if (!TARGET_FLAT)
5081 fputs ("\trestore\n", asm_out_file);
5082
5083 fputs ("\tjmp\t%o7+8\n", asm_out_file);
5084 }
5085
5086 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
5087 }
5088 else
5089 {
5090 if (!TARGET_FLAT)
5091 fputs ("\trestore\n", asm_out_file);
5092
5093 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file);
5094 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
5095 }
5096 }
5097 else if (sparc_leaf_function_p || TARGET_FLAT)
5098 {
5099 /* This is a leaf or flat function so we don't have to bother restoring
5100 the register window, which frees us from dealing with the convoluted
5101 semantics of restore/return. We simply output the jump to the
5102 return address and the insn in the delay slot (if any). */
5103
5104 return "jmp\t%%o7+%)%#";
5105 }
5106 else
5107 {
5108 /* This is a regular function so we have to restore the register window.
5109 We may have a pending insn for the delay slot, which will be either
5110 combined with the 'restore' instruction or put in the delay slot of
5111 the 'return' instruction. */
5112
5113 if (final_sequence)
5114 {
5115 rtx delay, pat;
5116
5117 delay = NEXT_INSN (insn);
5118 gcc_assert (delay);
5119
5120 pat = PATTERN (delay);
5121
5122 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
5123 {
5124 epilogue_renumber (&pat, 0);
5125 return "return\t%%i7+%)%#";
5126 }
5127 else
5128 {
5129 output_asm_insn ("jmp\t%%i7+%)", NULL);
5130 output_restore (pat);
5131 PATTERN (delay) = gen_blockage ();
5132 INSN_CODE (delay) = -1;
5133 }
5134 }
5135 else
5136 {
5137 /* The delay slot is empty. */
5138 if (TARGET_V9)
5139 return "return\t%%i7+%)\n\t nop";
5140 else if (flag_delayed_branch)
5141 return "jmp\t%%i7+%)\n\t restore";
5142 else
5143 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5144 }
5145 }
5146
5147 return "";
5148 }
5149
5150 /* Output a sibling call. */
5151
5152 const char *
5153 output_sibcall (rtx insn, rtx call_operand)
5154 {
5155 rtx operands[1];
5156
5157 gcc_assert (flag_delayed_branch);
5158
5159 operands[0] = call_operand;
5160
5161 if (sparc_leaf_function_p || TARGET_FLAT)
5162 {
5163 /* This is a leaf or flat function so we don't have to bother restoring
5164 the register window. We simply output the jump to the function and
5165 the insn in the delay slot (if any). */
5166
5167 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
5168
5169 if (final_sequence)
5170 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5171 operands);
5172 else
5173 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5174 it into branch if possible. */
5175 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5176 operands);
5177 }
5178 else
5179 {
5180 /* This is a regular function so we have to restore the register window.
5181 We may have a pending insn for the delay slot, which will be combined
5182 with the 'restore' instruction. */
5183
5184 output_asm_insn ("call\t%a0, 0", operands);
5185
5186 if (final_sequence)
5187 {
5188 rtx delay = NEXT_INSN (insn);
5189 gcc_assert (delay);
5190
5191 output_restore (PATTERN (delay));
5192
5193 PATTERN (delay) = gen_blockage ();
5194 INSN_CODE (delay) = -1;
5195 }
5196 else
5197 output_restore (NULL_RTX);
5198 }
5199
5200 return "";
5201 }
5202 \f
5203 /* Functions for handling argument passing.
5204
5205 For 32-bit, the first 6 args are normally in registers and the rest are
5206 pushed. Any arg that starts within the first 6 words is at least
5207 partially passed in a register unless its data type forbids.
5208
5209 For 64-bit, the argument registers are laid out as an array of 16 elements
5210 and arguments are added sequentially. The first 6 int args and up to the
5211 first 16 fp args (depending on size) are passed in regs.
5212
5213 Slot Stack Integral Float Float in structure Double Long Double
5214 ---- ----- -------- ----- ------------------ ------ -----------
5215 15 [SP+248] %f31 %f30,%f31 %d30
5216 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5217 13 [SP+232] %f27 %f26,%f27 %d26
5218 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5219 11 [SP+216] %f23 %f22,%f23 %d22
5220 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5221 9 [SP+200] %f19 %f18,%f19 %d18
5222 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5223 7 [SP+184] %f15 %f14,%f15 %d14
5224 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5225 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5226 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5227 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5228 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5229 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5230 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5231
5232 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5233
5234 Integral arguments are always passed as 64-bit quantities appropriately
5235 extended.
5236
5237 Passing of floating point values is handled as follows.
5238 If a prototype is in scope:
5239 If the value is in a named argument (i.e. not a stdarg function or a
5240 value not part of the `...') then the value is passed in the appropriate
5241 fp reg.
5242 If the value is part of the `...' and is passed in one of the first 6
5243 slots then the value is passed in the appropriate int reg.
5244 If the value is part of the `...' and is not passed in one of the first 6
5245 slots then the value is passed in memory.
5246 If a prototype is not in scope:
5247 If the value is one of the first 6 arguments the value is passed in the
5248 appropriate integer reg and the appropriate fp reg.
5249 If the value is not one of the first 6 arguments the value is passed in
5250 the appropriate fp reg and in memory.
5251
5252
5253 Summary of the calling conventions implemented by GCC on the SPARC:
5254
5255 32-bit ABI:
5256 size argument return value
5257
5258 small integer <4 int. reg. int. reg.
5259 word 4 int. reg. int. reg.
5260 double word 8 int. reg. int. reg.
5261
5262 _Complex small integer <8 int. reg. int. reg.
5263 _Complex word 8 int. reg. int. reg.
5264 _Complex double word 16 memory int. reg.
5265
5266 vector integer <=8 int. reg. FP reg.
5267 vector integer >8 memory memory
5268
5269 float 4 int. reg. FP reg.
5270 double 8 int. reg. FP reg.
5271 long double 16 memory memory
5272
5273 _Complex float 8 memory FP reg.
5274 _Complex double 16 memory FP reg.
5275 _Complex long double 32 memory FP reg.
5276
5277 vector float any memory memory
5278
5279 aggregate any memory memory
5280
5281
5282
5283 64-bit ABI:
5284 size argument return value
5285
5286 small integer <8 int. reg. int. reg.
5287 word 8 int. reg. int. reg.
5288 double word 16 int. reg. int. reg.
5289
5290 _Complex small integer <16 int. reg. int. reg.
5291 _Complex word 16 int. reg. int. reg.
5292 _Complex double word 32 memory int. reg.
5293
5294 vector integer <=16 FP reg. FP reg.
5295 vector integer 16<s<=32 memory FP reg.
5296 vector integer >32 memory memory
5297
5298 float 4 FP reg. FP reg.
5299 double 8 FP reg. FP reg.
5300 long double 16 FP reg. FP reg.
5301
5302 _Complex float 8 FP reg. FP reg.
5303 _Complex double 16 FP reg. FP reg.
5304 _Complex long double 32 memory FP reg.
5305
5306 vector float <=16 FP reg. FP reg.
5307 vector float 16<s<=32 memory FP reg.
5308 vector float >32 memory memory
5309
5310 aggregate <=16 reg. reg.
5311 aggregate 16<s<=32 memory reg.
5312 aggregate >32 memory memory
5313
5314
5315
5316 Note #1: complex floating-point types follow the extended SPARC ABIs as
5317 implemented by the Sun compiler.
5318
5319 Note #2: integral vector types follow the scalar floating-point types
5320 conventions to match what is implemented by the Sun VIS SDK.
5321
5322 Note #3: floating-point vector types follow the aggregate types
5323 conventions. */
5324
5325
5326 /* Maximum number of int regs for args. */
5327 #define SPARC_INT_ARG_MAX 6
5328 /* Maximum number of fp regs for args. */
5329 #define SPARC_FP_ARG_MAX 16
5330
5331 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5332
5333 /* Handle the INIT_CUMULATIVE_ARGS macro.
5334 Initialize a variable CUM of type CUMULATIVE_ARGS
5335 for a call to a function whose data type is FNTYPE.
5336 For a library call, FNTYPE is 0. */
5337
5338 void
5339 init_cumulative_args (struct sparc_args *cum, tree fntype,
5340 rtx libname ATTRIBUTE_UNUSED,
5341 tree fndecl ATTRIBUTE_UNUSED)
5342 {
5343 cum->words = 0;
5344 cum->prototype_p = fntype && prototype_p (fntype);
5345 cum->libcall_p = fntype == 0;
5346 }
5347
5348 /* Handle promotion of pointer and integer arguments. */
5349
5350 static enum machine_mode
5351 sparc_promote_function_mode (const_tree type,
5352 enum machine_mode mode,
5353 int *punsignedp,
5354 const_tree fntype ATTRIBUTE_UNUSED,
5355 int for_return ATTRIBUTE_UNUSED)
5356 {
5357 if (type != NULL_TREE && POINTER_TYPE_P (type))
5358 {
5359 *punsignedp = POINTERS_EXTEND_UNSIGNED;
5360 return Pmode;
5361 }
5362
5363 /* Integral arguments are passed as full words, as per the ABI. */
5364 if (GET_MODE_CLASS (mode) == MODE_INT
5365 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5366 return word_mode;
5367
5368 return mode;
5369 }
5370
5371 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5372
5373 static bool
5374 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5375 {
5376 return TARGET_ARCH64 ? true : false;
5377 }
5378
5379 /* Scan the record type TYPE and return the following predicates:
5380 - INTREGS_P: the record contains at least one field or sub-field
5381 that is eligible for promotion in integer registers.
5382 - FP_REGS_P: the record contains at least one field or sub-field
5383 that is eligible for promotion in floating-point registers.
5384 - PACKED_P: the record contains at least one field that is packed.
5385
5386 Sub-fields are not taken into account for the PACKED_P predicate. */
5387
5388 static void
5389 scan_record_type (const_tree type, int *intregs_p, int *fpregs_p,
5390 int *packed_p)
5391 {
5392 tree field;
5393
5394 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5395 {
5396 if (TREE_CODE (field) == FIELD_DECL)
5397 {
5398 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5399 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5400 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5401 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5402 && TARGET_FPU)
5403 *fpregs_p = 1;
5404 else
5405 *intregs_p = 1;
5406
5407 if (packed_p && DECL_PACKED (field))
5408 *packed_p = 1;
5409 }
5410 }
5411 }
5412
5413 /* Compute the slot number to pass an argument in.
5414 Return the slot number or -1 if passing on the stack.
5415
5416 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5417 the preceding args and about the function being called.
5418 MODE is the argument's machine mode.
5419 TYPE is the data type of the argument (as a tree).
5420 This is null for libcalls where that information may
5421 not be available.
5422 NAMED is nonzero if this argument is a named parameter
5423 (otherwise it is an extra parameter matching an ellipsis).
5424 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5425 *PREGNO records the register number to use if scalar type.
5426 *PPADDING records the amount of padding needed in words. */
5427
5428 static int
5429 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5430 const_tree type, bool named, bool incoming_p,
5431 int *pregno, int *ppadding)
5432 {
5433 int regbase = (incoming_p
5434 ? SPARC_INCOMING_INT_ARG_FIRST
5435 : SPARC_OUTGOING_INT_ARG_FIRST);
5436 int slotno = cum->words;
5437 enum mode_class mclass;
5438 int regno;
5439
5440 *ppadding = 0;
5441
5442 if (type && TREE_ADDRESSABLE (type))
5443 return -1;
5444
5445 if (TARGET_ARCH32
5446 && mode == BLKmode
5447 && type
5448 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5449 return -1;
5450
5451 /* For SPARC64, objects requiring 16-byte alignment get it. */
5452 if (TARGET_ARCH64
5453 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
5454 && (slotno & 1) != 0)
5455 slotno++, *ppadding = 1;
5456
5457 mclass = GET_MODE_CLASS (mode);
5458 if (type && TREE_CODE (type) == VECTOR_TYPE)
5459 {
5460 /* Vector types deserve special treatment because they are
5461 polymorphic wrt their mode, depending upon whether VIS
5462 instructions are enabled. */
5463 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5464 {
5465 /* The SPARC port defines no floating-point vector modes. */
5466 gcc_assert (mode == BLKmode);
5467 }
5468 else
5469 {
5470 /* Integral vector types should either have a vector
5471 mode or an integral mode, because we are guaranteed
5472 by pass_by_reference that their size is not greater
5473 than 16 bytes and TImode is 16-byte wide. */
5474 gcc_assert (mode != BLKmode);
5475
5476 /* Vector integers are handled like floats according to
5477 the Sun VIS SDK. */
5478 mclass = MODE_FLOAT;
5479 }
5480 }
5481
5482 switch (mclass)
5483 {
5484 case MODE_FLOAT:
5485 case MODE_COMPLEX_FLOAT:
5486 case MODE_VECTOR_INT:
5487 if (TARGET_ARCH64 && TARGET_FPU && named)
5488 {
5489 if (slotno >= SPARC_FP_ARG_MAX)
5490 return -1;
5491 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5492 /* Arguments filling only one single FP register are
5493 right-justified in the outer double FP register. */
5494 if (GET_MODE_SIZE (mode) <= 4)
5495 regno++;
5496 break;
5497 }
5498 /* fallthrough */
5499
5500 case MODE_INT:
5501 case MODE_COMPLEX_INT:
5502 if (slotno >= SPARC_INT_ARG_MAX)
5503 return -1;
5504 regno = regbase + slotno;
5505 break;
5506
5507 case MODE_RANDOM:
5508 if (mode == VOIDmode)
5509 /* MODE is VOIDmode when generating the actual call. */
5510 return -1;
5511
5512 gcc_assert (mode == BLKmode);
5513
5514 if (TARGET_ARCH32
5515 || !type
5516 || (TREE_CODE (type) != VECTOR_TYPE
5517 && TREE_CODE (type) != RECORD_TYPE))
5518 {
5519 if (slotno >= SPARC_INT_ARG_MAX)
5520 return -1;
5521 regno = regbase + slotno;
5522 }
5523 else /* TARGET_ARCH64 && type */
5524 {
5525 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5526
5527 /* First see what kinds of registers we would need. */
5528 if (TREE_CODE (type) == VECTOR_TYPE)
5529 fpregs_p = 1;
5530 else
5531 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5532
5533 /* The ABI obviously doesn't specify how packed structures
5534 are passed. These are defined to be passed in int regs
5535 if possible, otherwise memory. */
5536 if (packed_p || !named)
5537 fpregs_p = 0, intregs_p = 1;
5538
5539 /* If all arg slots are filled, then must pass on stack. */
5540 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5541 return -1;
5542
5543 /* If there are only int args and all int arg slots are filled,
5544 then must pass on stack. */
5545 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5546 return -1;
5547
5548 /* Note that even if all int arg slots are filled, fp members may
5549 still be passed in regs if such regs are available.
5550 *PREGNO isn't set because there may be more than one, it's up
5551 to the caller to compute them. */
5552 return slotno;
5553 }
5554 break;
5555
5556 default :
5557 gcc_unreachable ();
5558 }
5559
5560 *pregno = regno;
5561 return slotno;
5562 }
5563
5564 /* Handle recursive register counting for structure field layout. */
5565
5566 struct function_arg_record_value_parms
5567 {
5568 rtx ret; /* return expression being built. */
5569 int slotno; /* slot number of the argument. */
5570 int named; /* whether the argument is named. */
5571 int regbase; /* regno of the base register. */
5572 int stack; /* 1 if part of the argument is on the stack. */
5573 int intoffset; /* offset of the first pending integer field. */
5574 unsigned int nregs; /* number of words passed in registers. */
5575 };
5576
5577 static void function_arg_record_value_3
5578 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5579 static void function_arg_record_value_2
5580 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5581 static void function_arg_record_value_1
5582 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5583 static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
5584 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5585
5586 /* A subroutine of function_arg_record_value. Traverse the structure
5587 recursively and determine how many registers will be required. */
5588
5589 static void
5590 function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
5591 struct function_arg_record_value_parms *parms,
5592 bool packed_p)
5593 {
5594 tree field;
5595
5596 /* We need to compute how many registers are needed so we can
5597 allocate the PARALLEL but before we can do that we need to know
5598 whether there are any packed fields. The ABI obviously doesn't
5599 specify how structures are passed in this case, so they are
5600 defined to be passed in int regs if possible, otherwise memory,
5601 regardless of whether there are fp values present. */
5602
5603 if (! packed_p)
5604 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5605 {
5606 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5607 {
5608 packed_p = true;
5609 break;
5610 }
5611 }
5612
5613 /* Compute how many registers we need. */
5614 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5615 {
5616 if (TREE_CODE (field) == FIELD_DECL)
5617 {
5618 HOST_WIDE_INT bitpos = startbitpos;
5619
5620 if (DECL_SIZE (field) != 0)
5621 {
5622 if (integer_zerop (DECL_SIZE (field)))
5623 continue;
5624
5625 if (host_integerp (bit_position (field), 1))
5626 bitpos += int_bit_position (field);
5627 }
5628
5629 /* ??? FIXME: else assume zero offset. */
5630
5631 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5632 function_arg_record_value_1 (TREE_TYPE (field),
5633 bitpos,
5634 parms,
5635 packed_p);
5636 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5637 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5638 && TARGET_FPU
5639 && parms->named
5640 && ! packed_p)
5641 {
5642 if (parms->intoffset != -1)
5643 {
5644 unsigned int startbit, endbit;
5645 int intslots, this_slotno;
5646
5647 startbit = parms->intoffset & -BITS_PER_WORD;
5648 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5649
5650 intslots = (endbit - startbit) / BITS_PER_WORD;
5651 this_slotno = parms->slotno + parms->intoffset
5652 / BITS_PER_WORD;
5653
5654 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5655 {
5656 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5657 /* We need to pass this field on the stack. */
5658 parms->stack = 1;
5659 }
5660
5661 parms->nregs += intslots;
5662 parms->intoffset = -1;
5663 }
5664
5665 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5666 If it wasn't true we wouldn't be here. */
5667 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5668 && DECL_MODE (field) == BLKmode)
5669 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5670 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5671 parms->nregs += 2;
5672 else
5673 parms->nregs += 1;
5674 }
5675 else
5676 {
5677 if (parms->intoffset == -1)
5678 parms->intoffset = bitpos;
5679 }
5680 }
5681 }
5682 }
5683
5684 /* A subroutine of function_arg_record_value. Assign the bits of the
5685 structure between parms->intoffset and bitpos to integer registers. */
5686
5687 static void
5688 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5689 struct function_arg_record_value_parms *parms)
5690 {
5691 enum machine_mode mode;
5692 unsigned int regno;
5693 unsigned int startbit, endbit;
5694 int this_slotno, intslots, intoffset;
5695 rtx reg;
5696
5697 if (parms->intoffset == -1)
5698 return;
5699
5700 intoffset = parms->intoffset;
5701 parms->intoffset = -1;
5702
5703 startbit = intoffset & -BITS_PER_WORD;
5704 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5705 intslots = (endbit - startbit) / BITS_PER_WORD;
5706 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5707
5708 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5709 if (intslots <= 0)
5710 return;
5711
5712 /* If this is the trailing part of a word, only load that much into
5713 the register. Otherwise load the whole register. Note that in
5714 the latter case we may pick up unwanted bits. It's not a problem
5715 at the moment but may wish to revisit. */
5716
5717 if (intoffset % BITS_PER_WORD != 0)
5718 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5719 MODE_INT);
5720 else
5721 mode = word_mode;
5722
5723 intoffset /= BITS_PER_UNIT;
5724 do
5725 {
5726 regno = parms->regbase + this_slotno;
5727 reg = gen_rtx_REG (mode, regno);
5728 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5729 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5730
5731 this_slotno += 1;
5732 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5733 mode = word_mode;
5734 parms->nregs += 1;
5735 intslots -= 1;
5736 }
5737 while (intslots > 0);
5738 }
5739
5740 /* A subroutine of function_arg_record_value. Traverse the structure
5741 recursively and assign bits to floating point registers. Track which
5742 bits in between need integer registers; invoke function_arg_record_value_3
5743 to make that happen. */
5744
5745 static void
5746 function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
5747 struct function_arg_record_value_parms *parms,
5748 bool packed_p)
5749 {
5750 tree field;
5751
5752 if (! packed_p)
5753 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5754 {
5755 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5756 {
5757 packed_p = true;
5758 break;
5759 }
5760 }
5761
5762 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5763 {
5764 if (TREE_CODE (field) == FIELD_DECL)
5765 {
5766 HOST_WIDE_INT bitpos = startbitpos;
5767
5768 if (DECL_SIZE (field) != 0)
5769 {
5770 if (integer_zerop (DECL_SIZE (field)))
5771 continue;
5772
5773 if (host_integerp (bit_position (field), 1))
5774 bitpos += int_bit_position (field);
5775 }
5776
5777 /* ??? FIXME: else assume zero offset. */
5778
5779 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5780 function_arg_record_value_2 (TREE_TYPE (field),
5781 bitpos,
5782 parms,
5783 packed_p);
5784 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5785 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5786 && TARGET_FPU
5787 && parms->named
5788 && ! packed_p)
5789 {
5790 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5791 int regno, nregs, pos;
5792 enum machine_mode mode = DECL_MODE (field);
5793 rtx reg;
5794
5795 function_arg_record_value_3 (bitpos, parms);
5796
5797 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5798 && mode == BLKmode)
5799 {
5800 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5801 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5802 }
5803 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5804 {
5805 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5806 nregs = 2;
5807 }
5808 else
5809 nregs = 1;
5810
5811 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5812 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5813 regno++;
5814 reg = gen_rtx_REG (mode, regno);
5815 pos = bitpos / BITS_PER_UNIT;
5816 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5817 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5818 parms->nregs += 1;
5819 while (--nregs > 0)
5820 {
5821 regno += GET_MODE_SIZE (mode) / 4;
5822 reg = gen_rtx_REG (mode, regno);
5823 pos += GET_MODE_SIZE (mode);
5824 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5825 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5826 parms->nregs += 1;
5827 }
5828 }
5829 else
5830 {
5831 if (parms->intoffset == -1)
5832 parms->intoffset = bitpos;
5833 }
5834 }
5835 }
5836 }
5837
5838 /* Used by function_arg and sparc_function_value_1 to implement the complex
5839 conventions of the 64-bit ABI for passing and returning structures.
5840 Return an expression valid as a return value for the FUNCTION_ARG
5841 and TARGET_FUNCTION_VALUE.
5842
5843 TYPE is the data type of the argument (as a tree).
5844 This is null for libcalls where that information may
5845 not be available.
5846 MODE is the argument's machine mode.
5847 SLOTNO is the index number of the argument's slot in the parameter array.
5848 NAMED is nonzero if this argument is a named parameter
5849 (otherwise it is an extra parameter matching an ellipsis).
5850 REGBASE is the regno of the base register for the parameter array. */
5851
5852 static rtx
5853 function_arg_record_value (const_tree type, enum machine_mode mode,
5854 int slotno, int named, int regbase)
5855 {
5856 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5857 struct function_arg_record_value_parms parms;
5858 unsigned int nregs;
5859
5860 parms.ret = NULL_RTX;
5861 parms.slotno = slotno;
5862 parms.named = named;
5863 parms.regbase = regbase;
5864 parms.stack = 0;
5865
5866 /* Compute how many registers we need. */
5867 parms.nregs = 0;
5868 parms.intoffset = 0;
5869 function_arg_record_value_1 (type, 0, &parms, false);
5870
5871 /* Take into account pending integer fields. */
5872 if (parms.intoffset != -1)
5873 {
5874 unsigned int startbit, endbit;
5875 int intslots, this_slotno;
5876
5877 startbit = parms.intoffset & -BITS_PER_WORD;
5878 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5879 intslots = (endbit - startbit) / BITS_PER_WORD;
5880 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5881
5882 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5883 {
5884 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5885 /* We need to pass this field on the stack. */
5886 parms.stack = 1;
5887 }
5888
5889 parms.nregs += intslots;
5890 }
5891 nregs = parms.nregs;
5892
5893 /* Allocate the vector and handle some annoying special cases. */
5894 if (nregs == 0)
5895 {
5896 /* ??? Empty structure has no value? Duh? */
5897 if (typesize <= 0)
5898 {
5899 /* Though there's nothing really to store, return a word register
5900 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5901 leads to breakage due to the fact that there are zero bytes to
5902 load. */
5903 return gen_rtx_REG (mode, regbase);
5904 }
5905 else
5906 {
5907 /* ??? C++ has structures with no fields, and yet a size. Give up
5908 for now and pass everything back in integer registers. */
5909 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5910 }
5911 if (nregs + slotno > SPARC_INT_ARG_MAX)
5912 nregs = SPARC_INT_ARG_MAX - slotno;
5913 }
5914 gcc_assert (nregs != 0);
5915
5916 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5917
5918 /* If at least one field must be passed on the stack, generate
5919 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5920 also be passed on the stack. We can't do much better because the
5921 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5922 of structures for which the fields passed exclusively in registers
5923 are not at the beginning of the structure. */
5924 if (parms.stack)
5925 XVECEXP (parms.ret, 0, 0)
5926 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5927
5928 /* Fill in the entries. */
5929 parms.nregs = 0;
5930 parms.intoffset = 0;
5931 function_arg_record_value_2 (type, 0, &parms, false);
5932 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5933
5934 gcc_assert (parms.nregs == nregs);
5935
5936 return parms.ret;
5937 }
5938
5939 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5940 of the 64-bit ABI for passing and returning unions.
5941 Return an expression valid as a return value for the FUNCTION_ARG
5942 and TARGET_FUNCTION_VALUE.
5943
5944 SIZE is the size in bytes of the union.
5945 MODE is the argument's machine mode.
5946 REGNO is the hard register the union will be passed in. */
5947
5948 static rtx
5949 function_arg_union_value (int size, enum machine_mode mode, int slotno,
5950 int regno)
5951 {
5952 int nwords = ROUND_ADVANCE (size), i;
5953 rtx regs;
5954
5955 /* See comment in previous function for empty structures. */
5956 if (nwords == 0)
5957 return gen_rtx_REG (mode, regno);
5958
5959 if (slotno == SPARC_INT_ARG_MAX - 1)
5960 nwords = 1;
5961
5962 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5963
5964 for (i = 0; i < nwords; i++)
5965 {
5966 /* Unions are passed left-justified. */
5967 XVECEXP (regs, 0, i)
5968 = gen_rtx_EXPR_LIST (VOIDmode,
5969 gen_rtx_REG (word_mode, regno),
5970 GEN_INT (UNITS_PER_WORD * i));
5971 regno++;
5972 }
5973
5974 return regs;
5975 }
5976
5977 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5978 for passing and returning large (BLKmode) vectors.
5979 Return an expression valid as a return value for the FUNCTION_ARG
5980 and TARGET_FUNCTION_VALUE.
5981
5982 SIZE is the size in bytes of the vector (at least 8 bytes).
5983 REGNO is the FP hard register the vector will be passed in. */
5984
5985 static rtx
5986 function_arg_vector_value (int size, int regno)
5987 {
5988 int i, nregs = size / 8;
5989 rtx regs;
5990
5991 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
5992
5993 for (i = 0; i < nregs; i++)
5994 {
5995 XVECEXP (regs, 0, i)
5996 = gen_rtx_EXPR_LIST (VOIDmode,
5997 gen_rtx_REG (DImode, regno + 2*i),
5998 GEN_INT (i*8));
5999 }
6000
6001 return regs;
6002 }
6003
6004 /* Determine where to put an argument to a function.
6005 Value is zero to push the argument on the stack,
6006 or a hard register in which to store the argument.
6007
6008 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6009 the preceding args and about the function being called.
6010 MODE is the argument's machine mode.
6011 TYPE is the data type of the argument (as a tree).
6012 This is null for libcalls where that information may
6013 not be available.
6014 NAMED is true if this argument is a named parameter
6015 (otherwise it is an extra parameter matching an ellipsis).
6016 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6017 TARGET_FUNCTION_INCOMING_ARG. */
6018
6019 static rtx
6020 sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
6021 const_tree type, bool named, bool incoming_p)
6022 {
6023 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6024
6025 int regbase = (incoming_p
6026 ? SPARC_INCOMING_INT_ARG_FIRST
6027 : SPARC_OUTGOING_INT_ARG_FIRST);
6028 int slotno, regno, padding;
6029 enum mode_class mclass = GET_MODE_CLASS (mode);
6030
6031 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
6032 &regno, &padding);
6033 if (slotno == -1)
6034 return 0;
6035
6036 /* Vector types deserve special treatment because they are polymorphic wrt
6037 their mode, depending upon whether VIS instructions are enabled. */
6038 if (type && TREE_CODE (type) == VECTOR_TYPE)
6039 {
6040 HOST_WIDE_INT size = int_size_in_bytes (type);
6041 gcc_assert ((TARGET_ARCH32 && size <= 8)
6042 || (TARGET_ARCH64 && size <= 16));
6043
6044 if (mode == BLKmode)
6045 return function_arg_vector_value (size,
6046 SPARC_FP_ARG_FIRST + 2*slotno);
6047 else
6048 mclass = MODE_FLOAT;
6049 }
6050
6051 if (TARGET_ARCH32)
6052 return gen_rtx_REG (mode, regno);
6053
6054 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6055 and are promoted to registers if possible. */
6056 if (type && TREE_CODE (type) == RECORD_TYPE)
6057 {
6058 HOST_WIDE_INT size = int_size_in_bytes (type);
6059 gcc_assert (size <= 16);
6060
6061 return function_arg_record_value (type, mode, slotno, named, regbase);
6062 }
6063
6064 /* Unions up to 16 bytes in size are passed in integer registers. */
6065 else if (type && TREE_CODE (type) == UNION_TYPE)
6066 {
6067 HOST_WIDE_INT size = int_size_in_bytes (type);
6068 gcc_assert (size <= 16);
6069
6070 return function_arg_union_value (size, mode, slotno, regno);
6071 }
6072
6073 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6074 but also have the slot allocated for them.
6075 If no prototype is in scope fp values in register slots get passed
6076 in two places, either fp regs and int regs or fp regs and memory. */
6077 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6078 && SPARC_FP_REG_P (regno))
6079 {
6080 rtx reg = gen_rtx_REG (mode, regno);
6081 if (cum->prototype_p || cum->libcall_p)
6082 {
6083 /* "* 2" because fp reg numbers are recorded in 4 byte
6084 quantities. */
6085 #if 0
6086 /* ??? This will cause the value to be passed in the fp reg and
6087 in the stack. When a prototype exists we want to pass the
6088 value in the reg but reserve space on the stack. That's an
6089 optimization, and is deferred [for a bit]. */
6090 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
6091 return gen_rtx_PARALLEL (mode,
6092 gen_rtvec (2,
6093 gen_rtx_EXPR_LIST (VOIDmode,
6094 NULL_RTX, const0_rtx),
6095 gen_rtx_EXPR_LIST (VOIDmode,
6096 reg, const0_rtx)));
6097 else
6098 #else
6099 /* ??? It seems that passing back a register even when past
6100 the area declared by REG_PARM_STACK_SPACE will allocate
6101 space appropriately, and will not copy the data onto the
6102 stack, exactly as we desire.
6103
6104 This is due to locate_and_pad_parm being called in
6105 expand_call whenever reg_parm_stack_space > 0, which
6106 while beneficial to our example here, would seem to be
6107 in error from what had been intended. Ho hum... -- r~ */
6108 #endif
6109 return reg;
6110 }
6111 else
6112 {
6113 rtx v0, v1;
6114
6115 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
6116 {
6117 int intreg;
6118
6119 /* On incoming, we don't need to know that the value
6120 is passed in %f0 and %i0, and it confuses other parts
6121 causing needless spillage even on the simplest cases. */
6122 if (incoming_p)
6123 return reg;
6124
6125 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
6126 + (regno - SPARC_FP_ARG_FIRST) / 2);
6127
6128 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6129 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
6130 const0_rtx);
6131 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6132 }
6133 else
6134 {
6135 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6136 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6137 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6138 }
6139 }
6140 }
6141
6142 /* All other aggregate types are passed in an integer register in a mode
6143 corresponding to the size of the type. */
6144 else if (type && AGGREGATE_TYPE_P (type))
6145 {
6146 HOST_WIDE_INT size = int_size_in_bytes (type);
6147 gcc_assert (size <= 16);
6148
6149 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6150 }
6151
6152 return gen_rtx_REG (mode, regno);
6153 }
6154
6155 /* Handle the TARGET_FUNCTION_ARG target hook. */
6156
6157 static rtx
6158 sparc_function_arg (cumulative_args_t cum, enum machine_mode mode,
6159 const_tree type, bool named)
6160 {
6161 return sparc_function_arg_1 (cum, mode, type, named, false);
6162 }
6163
6164 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6165
6166 static rtx
6167 sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
6168 const_tree type, bool named)
6169 {
6170 return sparc_function_arg_1 (cum, mode, type, named, true);
6171 }
6172
6173 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6174
6175 static unsigned int
6176 sparc_function_arg_boundary (enum machine_mode mode, const_tree type)
6177 {
6178 return ((TARGET_ARCH64
6179 && (GET_MODE_ALIGNMENT (mode) == 128
6180 || (type && TYPE_ALIGN (type) == 128)))
6181 ? 128
6182 : PARM_BOUNDARY);
6183 }
6184
6185 /* For an arg passed partly in registers and partly in memory,
6186 this is the number of bytes of registers used.
6187 For args passed entirely in registers or entirely in memory, zero.
6188
6189 Any arg that starts in the first 6 regs but won't entirely fit in them
6190 needs partial registers on v8. On v9, structures with integer
6191 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6192 values that begin in the last fp reg [where "last fp reg" varies with the
6193 mode] will be split between that reg and memory. */
6194
6195 static int
6196 sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode,
6197 tree type, bool named)
6198 {
6199 int slotno, regno, padding;
6200
6201 /* We pass false for incoming_p here, it doesn't matter. */
6202 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
6203 false, &regno, &padding);
6204
6205 if (slotno == -1)
6206 return 0;
6207
6208 if (TARGET_ARCH32)
6209 {
6210 if ((slotno + (mode == BLKmode
6211 ? ROUND_ADVANCE (int_size_in_bytes (type))
6212 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
6213 > SPARC_INT_ARG_MAX)
6214 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
6215 }
6216 else
6217 {
6218 /* We are guaranteed by pass_by_reference that the size of the
6219 argument is not greater than 16 bytes, so we only need to return
6220 one word if the argument is partially passed in registers. */
6221
6222 if (type && AGGREGATE_TYPE_P (type))
6223 {
6224 int size = int_size_in_bytes (type);
6225
6226 if (size > UNITS_PER_WORD
6227 && slotno == SPARC_INT_ARG_MAX - 1)
6228 return UNITS_PER_WORD;
6229 }
6230 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
6231 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6232 && ! (TARGET_FPU && named)))
6233 {
6234 /* The complex types are passed as packed types. */
6235 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
6236 && slotno == SPARC_INT_ARG_MAX - 1)
6237 return UNITS_PER_WORD;
6238 }
6239 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6240 {
6241 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
6242 > SPARC_FP_ARG_MAX)
6243 return UNITS_PER_WORD;
6244 }
6245 }
6246
6247 return 0;
6248 }
6249
6250 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6251 Specify whether to pass the argument by reference. */
6252
6253 static bool
6254 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
6255 enum machine_mode mode, const_tree type,
6256 bool named ATTRIBUTE_UNUSED)
6257 {
6258 if (TARGET_ARCH32)
6259 /* Original SPARC 32-bit ABI says that structures and unions,
6260 and quad-precision floats are passed by reference. For Pascal,
6261 also pass arrays by reference. All other base types are passed
6262 in registers.
6263
6264 Extended ABI (as implemented by the Sun compiler) says that all
6265 complex floats are passed by reference. Pass complex integers
6266 in registers up to 8 bytes. More generally, enforce the 2-word
6267 cap for passing arguments in registers.
6268
6269 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6270 integers are passed like floats of the same size, that is in
6271 registers up to 8 bytes. Pass all vector floats by reference
6272 like structure and unions. */
6273 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
6274 || mode == SCmode
6275 /* Catch CDImode, TFmode, DCmode and TCmode. */
6276 || GET_MODE_SIZE (mode) > 8
6277 || (type
6278 && TREE_CODE (type) == VECTOR_TYPE
6279 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6280 else
6281 /* Original SPARC 64-bit ABI says that structures and unions
6282 smaller than 16 bytes are passed in registers, as well as
6283 all other base types.
6284
6285 Extended ABI (as implemented by the Sun compiler) says that
6286 complex floats are passed in registers up to 16 bytes. Pass
6287 all complex integers in registers up to 16 bytes. More generally,
6288 enforce the 2-word cap for passing arguments in registers.
6289
6290 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6291 integers are passed like floats of the same size, that is in
6292 registers (up to 16 bytes). Pass all vector floats like structure
6293 and unions. */
6294 return ((type
6295 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
6296 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
6297 /* Catch CTImode and TCmode. */
6298 || GET_MODE_SIZE (mode) > 16);
6299 }
6300
6301 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6302 Update the data in CUM to advance over an argument
6303 of mode MODE and data type TYPE.
6304 TYPE is null for libcalls where that information may not be available. */
6305
6306 static void
6307 sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
6308 const_tree type, bool named)
6309 {
6310 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6311 int regno, padding;
6312
6313 /* We pass false for incoming_p here, it doesn't matter. */
6314 function_arg_slotno (cum, mode, type, named, false, &regno, &padding);
6315
6316 /* If argument requires leading padding, add it. */
6317 cum->words += padding;
6318
6319 if (TARGET_ARCH32)
6320 {
6321 cum->words += (mode != BLKmode
6322 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6323 : ROUND_ADVANCE (int_size_in_bytes (type)));
6324 }
6325 else
6326 {
6327 if (type && AGGREGATE_TYPE_P (type))
6328 {
6329 int size = int_size_in_bytes (type);
6330
6331 if (size <= 8)
6332 ++cum->words;
6333 else if (size <= 16)
6334 cum->words += 2;
6335 else /* passed by reference */
6336 ++cum->words;
6337 }
6338 else
6339 {
6340 cum->words += (mode != BLKmode
6341 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6342 : ROUND_ADVANCE (int_size_in_bytes (type)));
6343 }
6344 }
6345 }
6346
6347 /* Handle the FUNCTION_ARG_PADDING macro.
6348 For the 64 bit ABI structs are always stored left shifted in their
6349 argument slot. */
6350
6351 enum direction
6352 function_arg_padding (enum machine_mode mode, const_tree type)
6353 {
6354 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
6355 return upward;
6356
6357 /* Fall back to the default. */
6358 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
6359 }
6360
6361 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6362 Specify whether to return the return value in memory. */
6363
6364 static bool
6365 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6366 {
6367 if (TARGET_ARCH32)
6368 /* Original SPARC 32-bit ABI says that structures and unions,
6369 and quad-precision floats are returned in memory. All other
6370 base types are returned in registers.
6371
6372 Extended ABI (as implemented by the Sun compiler) says that
6373 all complex floats are returned in registers (8 FP registers
6374 at most for '_Complex long double'). Return all complex integers
6375 in registers (4 at most for '_Complex long long').
6376
6377 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6378 integers are returned like floats of the same size, that is in
6379 registers up to 8 bytes and in memory otherwise. Return all
6380 vector floats in memory like structure and unions; note that
6381 they always have BLKmode like the latter. */
6382 return (TYPE_MODE (type) == BLKmode
6383 || TYPE_MODE (type) == TFmode
6384 || (TREE_CODE (type) == VECTOR_TYPE
6385 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6386 else
6387 /* Original SPARC 64-bit ABI says that structures and unions
6388 smaller than 32 bytes are returned in registers, as well as
6389 all other base types.
6390
6391 Extended ABI (as implemented by the Sun compiler) says that all
6392 complex floats are returned in registers (8 FP registers at most
6393 for '_Complex long double'). Return all complex integers in
6394 registers (4 at most for '_Complex TItype').
6395
6396 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6397 integers are returned like floats of the same size, that is in
6398 registers. Return all vector floats like structure and unions;
6399 note that they always have BLKmode like the latter. */
6400 return (TYPE_MODE (type) == BLKmode
6401 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
6402 }
6403
6404 /* Handle the TARGET_STRUCT_VALUE target hook.
6405 Return where to find the structure return value address. */
6406
6407 static rtx
6408 sparc_struct_value_rtx (tree fndecl, int incoming)
6409 {
6410 if (TARGET_ARCH64)
6411 return 0;
6412 else
6413 {
6414 rtx mem;
6415
6416 if (incoming)
6417 mem = gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx,
6418 STRUCT_VALUE_OFFSET));
6419 else
6420 mem = gen_frame_mem (Pmode, plus_constant (stack_pointer_rtx,
6421 STRUCT_VALUE_OFFSET));
6422
6423 /* Only follow the SPARC ABI for fixed-size structure returns.
6424 Variable size structure returns are handled per the normal
6425 procedures in GCC. This is enabled by -mstd-struct-return */
6426 if (incoming == 2
6427 && sparc_std_struct_return
6428 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
6429 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
6430 {
6431 /* We must check and adjust the return address, as it is
6432 optional as to whether the return object is really
6433 provided. */
6434 rtx ret_reg = gen_rtx_REG (Pmode, 31);
6435 rtx scratch = gen_reg_rtx (SImode);
6436 rtx endlab = gen_label_rtx ();
6437
6438 /* Calculate the return object size */
6439 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
6440 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
6441 /* Construct a temporary return value */
6442 rtx temp_val
6443 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
6444
6445 /* Implement SPARC 32-bit psABI callee return struct checking:
6446
6447 Fetch the instruction where we will return to and see if
6448 it's an unimp instruction (the most significant 10 bits
6449 will be zero). */
6450 emit_move_insn (scratch, gen_rtx_MEM (SImode,
6451 plus_constant (ret_reg, 8)));
6452 /* Assume the size is valid and pre-adjust */
6453 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4)));
6454 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
6455 0, endlab);
6456 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4)));
6457 /* Write the address of the memory pointed to by temp_val into
6458 the memory pointed to by mem */
6459 emit_move_insn (mem, XEXP (temp_val, 0));
6460 emit_label (endlab);
6461 }
6462
6463 return mem;
6464 }
6465 }
6466
6467 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6468 For v9, function return values are subject to the same rules as arguments,
6469 except that up to 32 bytes may be returned in registers. */
6470
6471 static rtx
6472 sparc_function_value_1 (const_tree type, enum machine_mode mode,
6473 bool outgoing)
6474 {
6475 /* Beware that the two values are swapped here wrt function_arg. */
6476 int regbase = (outgoing
6477 ? SPARC_INCOMING_INT_ARG_FIRST
6478 : SPARC_OUTGOING_INT_ARG_FIRST);
6479 enum mode_class mclass = GET_MODE_CLASS (mode);
6480 int regno;
6481
6482 /* Vector types deserve special treatment because they are polymorphic wrt
6483 their mode, depending upon whether VIS instructions are enabled. */
6484 if (type && TREE_CODE (type) == VECTOR_TYPE)
6485 {
6486 HOST_WIDE_INT size = int_size_in_bytes (type);
6487 gcc_assert ((TARGET_ARCH32 && size <= 8)
6488 || (TARGET_ARCH64 && size <= 32));
6489
6490 if (mode == BLKmode)
6491 return function_arg_vector_value (size,
6492 SPARC_FP_ARG_FIRST);
6493 else
6494 mclass = MODE_FLOAT;
6495 }
6496
6497 if (TARGET_ARCH64 && type)
6498 {
6499 /* Structures up to 32 bytes in size are returned in registers. */
6500 if (TREE_CODE (type) == RECORD_TYPE)
6501 {
6502 HOST_WIDE_INT size = int_size_in_bytes (type);
6503 gcc_assert (size <= 32);
6504
6505 return function_arg_record_value (type, mode, 0, 1, regbase);
6506 }
6507
6508 /* Unions up to 32 bytes in size are returned in integer registers. */
6509 else if (TREE_CODE (type) == UNION_TYPE)
6510 {
6511 HOST_WIDE_INT size = int_size_in_bytes (type);
6512 gcc_assert (size <= 32);
6513
6514 return function_arg_union_value (size, mode, 0, regbase);
6515 }
6516
6517 /* Objects that require it are returned in FP registers. */
6518 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6519 ;
6520
6521 /* All other aggregate types are returned in an integer register in a
6522 mode corresponding to the size of the type. */
6523 else if (AGGREGATE_TYPE_P (type))
6524 {
6525 /* All other aggregate types are passed in an integer register
6526 in a mode corresponding to the size of the type. */
6527 HOST_WIDE_INT size = int_size_in_bytes (type);
6528 gcc_assert (size <= 32);
6529
6530 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6531
6532 /* ??? We probably should have made the same ABI change in
6533 3.4.0 as the one we made for unions. The latter was
6534 required by the SCD though, while the former is not
6535 specified, so we favored compatibility and efficiency.
6536
6537 Now we're stuck for aggregates larger than 16 bytes,
6538 because OImode vanished in the meantime. Let's not
6539 try to be unduly clever, and simply follow the ABI
6540 for unions in that case. */
6541 if (mode == BLKmode)
6542 return function_arg_union_value (size, mode, 0, regbase);
6543 else
6544 mclass = MODE_INT;
6545 }
6546
6547 /* We should only have pointer and integer types at this point. This
6548 must match sparc_promote_function_mode. */
6549 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6550 mode = word_mode;
6551 }
6552
6553 /* We should only have pointer and integer types at this point. This must
6554 match sparc_promote_function_mode. */
6555 else if (TARGET_ARCH32
6556 && mclass == MODE_INT
6557 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6558 mode = word_mode;
6559
6560 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
6561 regno = SPARC_FP_ARG_FIRST;
6562 else
6563 regno = regbase;
6564
6565 return gen_rtx_REG (mode, regno);
6566 }
6567
6568 /* Handle TARGET_FUNCTION_VALUE.
6569 On the SPARC, the value is found in the first "output" register, but the
6570 called function leaves it in the first "input" register. */
6571
6572 static rtx
6573 sparc_function_value (const_tree valtype,
6574 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
6575 bool outgoing)
6576 {
6577 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
6578 }
6579
6580 /* Handle TARGET_LIBCALL_VALUE. */
6581
6582 static rtx
6583 sparc_libcall_value (enum machine_mode mode,
6584 const_rtx fun ATTRIBUTE_UNUSED)
6585 {
6586 return sparc_function_value_1 (NULL_TREE, mode, false);
6587 }
6588
6589 /* Handle FUNCTION_VALUE_REGNO_P.
6590 On the SPARC, the first "output" reg is used for integer values, and the
6591 first floating point register is used for floating point values. */
6592
6593 static bool
6594 sparc_function_value_regno_p (const unsigned int regno)
6595 {
6596 return (regno == 8 || regno == 32);
6597 }
6598
6599 /* Do what is necessary for `va_start'. We look at the current function
6600 to determine if stdarg or varargs is used and return the address of
6601 the first unnamed parameter. */
6602
6603 static rtx
6604 sparc_builtin_saveregs (void)
6605 {
6606 int first_reg = crtl->args.info.words;
6607 rtx address;
6608 int regno;
6609
6610 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
6611 emit_move_insn (gen_rtx_MEM (word_mode,
6612 gen_rtx_PLUS (Pmode,
6613 frame_pointer_rtx,
6614 GEN_INT (FIRST_PARM_OFFSET (0)
6615 + (UNITS_PER_WORD
6616 * regno)))),
6617 gen_rtx_REG (word_mode,
6618 SPARC_INCOMING_INT_ARG_FIRST + regno));
6619
6620 address = gen_rtx_PLUS (Pmode,
6621 frame_pointer_rtx,
6622 GEN_INT (FIRST_PARM_OFFSET (0)
6623 + UNITS_PER_WORD * first_reg));
6624
6625 return address;
6626 }
6627
6628 /* Implement `va_start' for stdarg. */
6629
6630 static void
6631 sparc_va_start (tree valist, rtx nextarg)
6632 {
6633 nextarg = expand_builtin_saveregs ();
6634 std_expand_builtin_va_start (valist, nextarg);
6635 }
6636
6637 /* Implement `va_arg' for stdarg. */
6638
6639 static tree
6640 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6641 gimple_seq *post_p)
6642 {
6643 HOST_WIDE_INT size, rsize, align;
6644 tree addr, incr;
6645 bool indirect;
6646 tree ptrtype = build_pointer_type (type);
6647
6648 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6649 {
6650 indirect = true;
6651 size = rsize = UNITS_PER_WORD;
6652 align = 0;
6653 }
6654 else
6655 {
6656 indirect = false;
6657 size = int_size_in_bytes (type);
6658 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6659 align = 0;
6660
6661 if (TARGET_ARCH64)
6662 {
6663 /* For SPARC64, objects requiring 16-byte alignment get it. */
6664 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6665 align = 2 * UNITS_PER_WORD;
6666
6667 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6668 are left-justified in their slots. */
6669 if (AGGREGATE_TYPE_P (type))
6670 {
6671 if (size == 0)
6672 size = rsize = UNITS_PER_WORD;
6673 else
6674 size = rsize;
6675 }
6676 }
6677 }
6678
6679 incr = valist;
6680 if (align)
6681 {
6682 incr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
6683 size_int (align - 1));
6684 incr = fold_convert (sizetype, incr);
6685 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
6686 size_int (-align));
6687 incr = fold_convert (ptr_type_node, incr);
6688 }
6689
6690 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6691 addr = incr;
6692
6693 if (BYTES_BIG_ENDIAN && size < rsize)
6694 addr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
6695 size_int (rsize - size));
6696
6697 if (indirect)
6698 {
6699 addr = fold_convert (build_pointer_type (ptrtype), addr);
6700 addr = build_va_arg_indirect_ref (addr);
6701 }
6702
6703 /* If the address isn't aligned properly for the type, we need a temporary.
6704 FIXME: This is inefficient, usually we can do this in registers. */
6705 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
6706 {
6707 tree tmp = create_tmp_var (type, "va_arg_tmp");
6708 tree dest_addr = build_fold_addr_expr (tmp);
6709 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6710 3, dest_addr, addr, size_int (rsize));
6711 TREE_ADDRESSABLE (tmp) = 1;
6712 gimplify_and_add (copy, pre_p);
6713 addr = dest_addr;
6714 }
6715
6716 else
6717 addr = fold_convert (ptrtype, addr);
6718
6719 incr
6720 = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, size_int (rsize));
6721 gimplify_assign (valist, incr, post_p);
6722
6723 return build_va_arg_indirect_ref (addr);
6724 }
6725 \f
6726 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6727 Specify whether the vector mode is supported by the hardware. */
6728
6729 static bool
6730 sparc_vector_mode_supported_p (enum machine_mode mode)
6731 {
6732 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
6733 }
6734 \f
6735 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6736
6737 static enum machine_mode
6738 sparc_preferred_simd_mode (enum machine_mode mode)
6739 {
6740 if (TARGET_VIS)
6741 switch (mode)
6742 {
6743 case SImode:
6744 return V2SImode;
6745 case HImode:
6746 return V4HImode;
6747 case QImode:
6748 return V8QImode;
6749
6750 default:;
6751 }
6752
6753 return word_mode;
6754 }
6755 \f
6756 /* Return the string to output an unconditional branch to LABEL, which is
6757 the operand number of the label.
6758
6759 DEST is the destination insn (i.e. the label), INSN is the source. */
6760
6761 const char *
6762 output_ubranch (rtx dest, int label, rtx insn)
6763 {
6764 static char string[64];
6765 bool v9_form = false;
6766 char *p;
6767
6768 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6769 {
6770 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6771 - INSN_ADDRESSES (INSN_UID (insn)));
6772 /* Leave some instructions for "slop". */
6773 if (delta >= -260000 && delta < 260000)
6774 v9_form = true;
6775 }
6776
6777 if (v9_form)
6778 strcpy (string, "ba%*,pt\t%%xcc, ");
6779 else
6780 strcpy (string, "b%*\t");
6781
6782 p = strchr (string, '\0');
6783 *p++ = '%';
6784 *p++ = 'l';
6785 *p++ = '0' + label;
6786 *p++ = '%';
6787 *p++ = '(';
6788 *p = '\0';
6789
6790 return string;
6791 }
6792
6793 /* Return the string to output a conditional branch to LABEL, which is
6794 the operand number of the label. OP is the conditional expression.
6795 XEXP (OP, 0) is assumed to be a condition code register (integer or
6796 floating point) and its mode specifies what kind of comparison we made.
6797
6798 DEST is the destination insn (i.e. the label), INSN is the source.
6799
6800 REVERSED is nonzero if we should reverse the sense of the comparison.
6801
6802 ANNUL is nonzero if we should generate an annulling branch. */
6803
6804 const char *
6805 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6806 rtx insn)
6807 {
6808 static char string[64];
6809 enum rtx_code code = GET_CODE (op);
6810 rtx cc_reg = XEXP (op, 0);
6811 enum machine_mode mode = GET_MODE (cc_reg);
6812 const char *labelno, *branch;
6813 int spaces = 8, far;
6814 char *p;
6815
6816 /* v9 branches are limited to +-1MB. If it is too far away,
6817 change
6818
6819 bne,pt %xcc, .LC30
6820
6821 to
6822
6823 be,pn %xcc, .+12
6824 nop
6825 ba .LC30
6826
6827 and
6828
6829 fbne,a,pn %fcc2, .LC29
6830
6831 to
6832
6833 fbe,pt %fcc2, .+16
6834 nop
6835 ba .LC29 */
6836
6837 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6838 if (reversed ^ far)
6839 {
6840 /* Reversal of FP compares takes care -- an ordered compare
6841 becomes an unordered compare and vice versa. */
6842 if (mode == CCFPmode || mode == CCFPEmode)
6843 code = reverse_condition_maybe_unordered (code);
6844 else
6845 code = reverse_condition (code);
6846 }
6847
6848 /* Start by writing the branch condition. */
6849 if (mode == CCFPmode || mode == CCFPEmode)
6850 {
6851 switch (code)
6852 {
6853 case NE:
6854 branch = "fbne";
6855 break;
6856 case EQ:
6857 branch = "fbe";
6858 break;
6859 case GE:
6860 branch = "fbge";
6861 break;
6862 case GT:
6863 branch = "fbg";
6864 break;
6865 case LE:
6866 branch = "fble";
6867 break;
6868 case LT:
6869 branch = "fbl";
6870 break;
6871 case UNORDERED:
6872 branch = "fbu";
6873 break;
6874 case ORDERED:
6875 branch = "fbo";
6876 break;
6877 case UNGT:
6878 branch = "fbug";
6879 break;
6880 case UNLT:
6881 branch = "fbul";
6882 break;
6883 case UNEQ:
6884 branch = "fbue";
6885 break;
6886 case UNGE:
6887 branch = "fbuge";
6888 break;
6889 case UNLE:
6890 branch = "fbule";
6891 break;
6892 case LTGT:
6893 branch = "fblg";
6894 break;
6895
6896 default:
6897 gcc_unreachable ();
6898 }
6899
6900 /* ??? !v9: FP branches cannot be preceded by another floating point
6901 insn. Because there is currently no concept of pre-delay slots,
6902 we can fix this only by always emitting a nop before a floating
6903 point branch. */
6904
6905 string[0] = '\0';
6906 if (! TARGET_V9)
6907 strcpy (string, "nop\n\t");
6908 strcat (string, branch);
6909 }
6910 else
6911 {
6912 switch (code)
6913 {
6914 case NE:
6915 branch = "bne";
6916 break;
6917 case EQ:
6918 branch = "be";
6919 break;
6920 case GE:
6921 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6922 branch = "bpos";
6923 else
6924 branch = "bge";
6925 break;
6926 case GT:
6927 branch = "bg";
6928 break;
6929 case LE:
6930 branch = "ble";
6931 break;
6932 case LT:
6933 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6934 branch = "bneg";
6935 else
6936 branch = "bl";
6937 break;
6938 case GEU:
6939 branch = "bgeu";
6940 break;
6941 case GTU:
6942 branch = "bgu";
6943 break;
6944 case LEU:
6945 branch = "bleu";
6946 break;
6947 case LTU:
6948 branch = "blu";
6949 break;
6950
6951 default:
6952 gcc_unreachable ();
6953 }
6954 strcpy (string, branch);
6955 }
6956 spaces -= strlen (branch);
6957 p = strchr (string, '\0');
6958
6959 /* Now add the annulling, the label, and a possible noop. */
6960 if (annul && ! far)
6961 {
6962 strcpy (p, ",a");
6963 p += 2;
6964 spaces -= 2;
6965 }
6966
6967 if (TARGET_V9)
6968 {
6969 rtx note;
6970 int v8 = 0;
6971
6972 if (! far && insn && INSN_ADDRESSES_SET_P ())
6973 {
6974 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6975 - INSN_ADDRESSES (INSN_UID (insn)));
6976 /* Leave some instructions for "slop". */
6977 if (delta < -260000 || delta >= 260000)
6978 v8 = 1;
6979 }
6980
6981 if (mode == CCFPmode || mode == CCFPEmode)
6982 {
6983 static char v9_fcc_labelno[] = "%%fccX, ";
6984 /* Set the char indicating the number of the fcc reg to use. */
6985 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6986 labelno = v9_fcc_labelno;
6987 if (v8)
6988 {
6989 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
6990 labelno = "";
6991 }
6992 }
6993 else if (mode == CCXmode || mode == CCX_NOOVmode)
6994 {
6995 labelno = "%%xcc, ";
6996 gcc_assert (! v8);
6997 }
6998 else
6999 {
7000 labelno = "%%icc, ";
7001 if (v8)
7002 labelno = "";
7003 }
7004
7005 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7006 {
7007 strcpy (p,
7008 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7009 ? ",pt" : ",pn");
7010 p += 3;
7011 spaces -= 3;
7012 }
7013 }
7014 else
7015 labelno = "";
7016
7017 if (spaces > 0)
7018 *p++ = '\t';
7019 else
7020 *p++ = ' ';
7021 strcpy (p, labelno);
7022 p = strchr (p, '\0');
7023 if (far)
7024 {
7025 strcpy (p, ".+12\n\t nop\n\tb\t");
7026 /* Skip the next insn if requested or
7027 if we know that it will be a nop. */
7028 if (annul || ! final_sequence)
7029 p[3] = '6';
7030 p += 14;
7031 }
7032 *p++ = '%';
7033 *p++ = 'l';
7034 *p++ = label + '0';
7035 *p++ = '%';
7036 *p++ = '#';
7037 *p = '\0';
7038
7039 return string;
7040 }
7041
7042 /* Emit a library call comparison between floating point X and Y.
7043 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7044 Return the new operator to be used in the comparison sequence.
7045
7046 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7047 values as arguments instead of the TFmode registers themselves,
7048 that's why we cannot call emit_float_lib_cmp. */
7049
7050 rtx
7051 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
7052 {
7053 const char *qpfunc;
7054 rtx slot0, slot1, result, tem, tem2, libfunc;
7055 enum machine_mode mode;
7056 enum rtx_code new_comparison;
7057
7058 switch (comparison)
7059 {
7060 case EQ:
7061 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
7062 break;
7063
7064 case NE:
7065 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
7066 break;
7067
7068 case GT:
7069 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
7070 break;
7071
7072 case GE:
7073 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
7074 break;
7075
7076 case LT:
7077 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
7078 break;
7079
7080 case LE:
7081 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
7082 break;
7083
7084 case ORDERED:
7085 case UNORDERED:
7086 case UNGT:
7087 case UNLT:
7088 case UNEQ:
7089 case UNGE:
7090 case UNLE:
7091 case LTGT:
7092 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
7093 break;
7094
7095 default:
7096 gcc_unreachable ();
7097 }
7098
7099 if (TARGET_ARCH64)
7100 {
7101 if (MEM_P (x))
7102 slot0 = x;
7103 else
7104 {
7105 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7106 emit_move_insn (slot0, x);
7107 }
7108
7109 if (MEM_P (y))
7110 slot1 = y;
7111 else
7112 {
7113 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7114 emit_move_insn (slot1, y);
7115 }
7116
7117 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7118 emit_library_call (libfunc, LCT_NORMAL,
7119 DImode, 2,
7120 XEXP (slot0, 0), Pmode,
7121 XEXP (slot1, 0), Pmode);
7122 mode = DImode;
7123 }
7124 else
7125 {
7126 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7127 emit_library_call (libfunc, LCT_NORMAL,
7128 SImode, 2,
7129 x, TFmode, y, TFmode);
7130 mode = SImode;
7131 }
7132
7133
7134 /* Immediately move the result of the libcall into a pseudo
7135 register so reload doesn't clobber the value if it needs
7136 the return register for a spill reg. */
7137 result = gen_reg_rtx (mode);
7138 emit_move_insn (result, hard_libcall_value (mode, libfunc));
7139
7140 switch (comparison)
7141 {
7142 default:
7143 return gen_rtx_NE (VOIDmode, result, const0_rtx);
7144 case ORDERED:
7145 case UNORDERED:
7146 new_comparison = (comparison == UNORDERED ? EQ : NE);
7147 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
7148 case UNGT:
7149 case UNGE:
7150 new_comparison = (comparison == UNGT ? GT : NE);
7151 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
7152 case UNLE:
7153 return gen_rtx_NE (VOIDmode, result, const2_rtx);
7154 case UNLT:
7155 tem = gen_reg_rtx (mode);
7156 if (TARGET_ARCH32)
7157 emit_insn (gen_andsi3 (tem, result, const1_rtx));
7158 else
7159 emit_insn (gen_anddi3 (tem, result, const1_rtx));
7160 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
7161 case UNEQ:
7162 case LTGT:
7163 tem = gen_reg_rtx (mode);
7164 if (TARGET_ARCH32)
7165 emit_insn (gen_addsi3 (tem, result, const1_rtx));
7166 else
7167 emit_insn (gen_adddi3 (tem, result, const1_rtx));
7168 tem2 = gen_reg_rtx (mode);
7169 if (TARGET_ARCH32)
7170 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
7171 else
7172 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
7173 new_comparison = (comparison == UNEQ ? EQ : NE);
7174 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
7175 }
7176
7177 gcc_unreachable ();
7178 }
7179
7180 /* Generate an unsigned DImode to FP conversion. This is the same code
7181 optabs would emit if we didn't have TFmode patterns. */
7182
7183 void
7184 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
7185 {
7186 rtx neglab, donelab, i0, i1, f0, in, out;
7187
7188 out = operands[0];
7189 in = force_reg (DImode, operands[1]);
7190 neglab = gen_label_rtx ();
7191 donelab = gen_label_rtx ();
7192 i0 = gen_reg_rtx (DImode);
7193 i1 = gen_reg_rtx (DImode);
7194 f0 = gen_reg_rtx (mode);
7195
7196 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
7197
7198 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
7199 emit_jump_insn (gen_jump (donelab));
7200 emit_barrier ();
7201
7202 emit_label (neglab);
7203
7204 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
7205 emit_insn (gen_anddi3 (i1, in, const1_rtx));
7206 emit_insn (gen_iordi3 (i0, i0, i1));
7207 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
7208 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
7209
7210 emit_label (donelab);
7211 }
7212
7213 /* Generate an FP to unsigned DImode conversion. This is the same code
7214 optabs would emit if we didn't have TFmode patterns. */
7215
7216 void
7217 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
7218 {
7219 rtx neglab, donelab, i0, i1, f0, in, out, limit;
7220
7221 out = operands[0];
7222 in = force_reg (mode, operands[1]);
7223 neglab = gen_label_rtx ();
7224 donelab = gen_label_rtx ();
7225 i0 = gen_reg_rtx (DImode);
7226 i1 = gen_reg_rtx (DImode);
7227 limit = gen_reg_rtx (mode);
7228 f0 = gen_reg_rtx (mode);
7229
7230 emit_move_insn (limit,
7231 CONST_DOUBLE_FROM_REAL_VALUE (
7232 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
7233 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
7234
7235 emit_insn (gen_rtx_SET (VOIDmode,
7236 out,
7237 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
7238 emit_jump_insn (gen_jump (donelab));
7239 emit_barrier ();
7240
7241 emit_label (neglab);
7242
7243 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
7244 emit_insn (gen_rtx_SET (VOIDmode,
7245 i0,
7246 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
7247 emit_insn (gen_movdi (i1, const1_rtx));
7248 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
7249 emit_insn (gen_xordi3 (out, i0, i1));
7250
7251 emit_label (donelab);
7252 }
7253
7254 /* Return the string to output a conditional branch to LABEL, testing
7255 register REG. LABEL is the operand number of the label; REG is the
7256 operand number of the reg. OP is the conditional expression. The mode
7257 of REG says what kind of comparison we made.
7258
7259 DEST is the destination insn (i.e. the label), INSN is the source.
7260
7261 REVERSED is nonzero if we should reverse the sense of the comparison.
7262
7263 ANNUL is nonzero if we should generate an annulling branch. */
7264
7265 const char *
7266 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
7267 int annul, rtx insn)
7268 {
7269 static char string[64];
7270 enum rtx_code code = GET_CODE (op);
7271 enum machine_mode mode = GET_MODE (XEXP (op, 0));
7272 rtx note;
7273 int far;
7274 char *p;
7275
7276 /* branch on register are limited to +-128KB. If it is too far away,
7277 change
7278
7279 brnz,pt %g1, .LC30
7280
7281 to
7282
7283 brz,pn %g1, .+12
7284 nop
7285 ba,pt %xcc, .LC30
7286
7287 and
7288
7289 brgez,a,pn %o1, .LC29
7290
7291 to
7292
7293 brlz,pt %o1, .+16
7294 nop
7295 ba,pt %xcc, .LC29 */
7296
7297 far = get_attr_length (insn) >= 3;
7298
7299 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7300 if (reversed ^ far)
7301 code = reverse_condition (code);
7302
7303 /* Only 64 bit versions of these instructions exist. */
7304 gcc_assert (mode == DImode);
7305
7306 /* Start by writing the branch condition. */
7307
7308 switch (code)
7309 {
7310 case NE:
7311 strcpy (string, "brnz");
7312 break;
7313
7314 case EQ:
7315 strcpy (string, "brz");
7316 break;
7317
7318 case GE:
7319 strcpy (string, "brgez");
7320 break;
7321
7322 case LT:
7323 strcpy (string, "brlz");
7324 break;
7325
7326 case LE:
7327 strcpy (string, "brlez");
7328 break;
7329
7330 case GT:
7331 strcpy (string, "brgz");
7332 break;
7333
7334 default:
7335 gcc_unreachable ();
7336 }
7337
7338 p = strchr (string, '\0');
7339
7340 /* Now add the annulling, reg, label, and nop. */
7341 if (annul && ! far)
7342 {
7343 strcpy (p, ",a");
7344 p += 2;
7345 }
7346
7347 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7348 {
7349 strcpy (p,
7350 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7351 ? ",pt" : ",pn");
7352 p += 3;
7353 }
7354
7355 *p = p < string + 8 ? '\t' : ' ';
7356 p++;
7357 *p++ = '%';
7358 *p++ = '0' + reg;
7359 *p++ = ',';
7360 *p++ = ' ';
7361 if (far)
7362 {
7363 int veryfar = 1, delta;
7364
7365 if (INSN_ADDRESSES_SET_P ())
7366 {
7367 delta = (INSN_ADDRESSES (INSN_UID (dest))
7368 - INSN_ADDRESSES (INSN_UID (insn)));
7369 /* Leave some instructions for "slop". */
7370 if (delta >= -260000 && delta < 260000)
7371 veryfar = 0;
7372 }
7373
7374 strcpy (p, ".+12\n\t nop\n\t");
7375 /* Skip the next insn if requested or
7376 if we know that it will be a nop. */
7377 if (annul || ! final_sequence)
7378 p[3] = '6';
7379 p += 12;
7380 if (veryfar)
7381 {
7382 strcpy (p, "b\t");
7383 p += 2;
7384 }
7385 else
7386 {
7387 strcpy (p, "ba,pt\t%%xcc, ");
7388 p += 13;
7389 }
7390 }
7391 *p++ = '%';
7392 *p++ = 'l';
7393 *p++ = '0' + label;
7394 *p++ = '%';
7395 *p++ = '#';
7396 *p = '\0';
7397
7398 return string;
7399 }
7400
7401 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7402 Such instructions cannot be used in the delay slot of return insn on v9.
7403 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7404 */
7405
7406 static int
7407 epilogue_renumber (register rtx *where, int test)
7408 {
7409 register const char *fmt;
7410 register int i;
7411 register enum rtx_code code;
7412
7413 if (*where == 0)
7414 return 0;
7415
7416 code = GET_CODE (*where);
7417
7418 switch (code)
7419 {
7420 case REG:
7421 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
7422 return 1;
7423 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
7424 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
7425 case SCRATCH:
7426 case CC0:
7427 case PC:
7428 case CONST_INT:
7429 case CONST_DOUBLE:
7430 return 0;
7431
7432 /* Do not replace the frame pointer with the stack pointer because
7433 it can cause the delayed instruction to load below the stack.
7434 This occurs when instructions like:
7435
7436 (set (reg/i:SI 24 %i0)
7437 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7438 (const_int -20 [0xffffffec])) 0))
7439
7440 are in the return delayed slot. */
7441 case PLUS:
7442 if (GET_CODE (XEXP (*where, 0)) == REG
7443 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
7444 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
7445 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
7446 return 1;
7447 break;
7448
7449 case MEM:
7450 if (SPARC_STACK_BIAS
7451 && GET_CODE (XEXP (*where, 0)) == REG
7452 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
7453 return 1;
7454 break;
7455
7456 default:
7457 break;
7458 }
7459
7460 fmt = GET_RTX_FORMAT (code);
7461
7462 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7463 {
7464 if (fmt[i] == 'E')
7465 {
7466 register int j;
7467 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7468 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7469 return 1;
7470 }
7471 else if (fmt[i] == 'e'
7472 && epilogue_renumber (&(XEXP (*where, i)), test))
7473 return 1;
7474 }
7475 return 0;
7476 }
7477 \f
7478 /* Leaf functions and non-leaf functions have different needs. */
7479
7480 static const int
7481 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7482
7483 static const int
7484 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7485
7486 static const int *const reg_alloc_orders[] = {
7487 reg_leaf_alloc_order,
7488 reg_nonleaf_alloc_order};
7489
7490 void
7491 order_regs_for_local_alloc (void)
7492 {
7493 static int last_order_nonleaf = 1;
7494
7495 if (df_regs_ever_live_p (15) != last_order_nonleaf)
7496 {
7497 last_order_nonleaf = !last_order_nonleaf;
7498 memcpy ((char *) reg_alloc_order,
7499 (const char *) reg_alloc_orders[last_order_nonleaf],
7500 FIRST_PSEUDO_REGISTER * sizeof (int));
7501 }
7502 }
7503 \f
7504 /* Return 1 if REG and MEM are legitimate enough to allow the various
7505 mem<-->reg splits to be run. */
7506
7507 int
7508 sparc_splitdi_legitimate (rtx reg, rtx mem)
7509 {
7510 /* Punt if we are here by mistake. */
7511 gcc_assert (reload_completed);
7512
7513 /* We must have an offsettable memory reference. */
7514 if (! offsettable_memref_p (mem))
7515 return 0;
7516
7517 /* If we have legitimate args for ldd/std, we do not want
7518 the split to happen. */
7519 if ((REGNO (reg) % 2) == 0
7520 && mem_min_alignment (mem, 8))
7521 return 0;
7522
7523 /* Success. */
7524 return 1;
7525 }
7526
7527 /* Return 1 if x and y are some kind of REG and they refer to
7528 different hard registers. This test is guaranteed to be
7529 run after reload. */
7530
7531 int
7532 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
7533 {
7534 if (GET_CODE (x) != REG)
7535 return 0;
7536 if (GET_CODE (y) != REG)
7537 return 0;
7538 if (REGNO (x) == REGNO (y))
7539 return 0;
7540 return 1;
7541 }
7542
7543 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7544 This makes them candidates for using ldd and std insns.
7545
7546 Note reg1 and reg2 *must* be hard registers. */
7547
7548 int
7549 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
7550 {
7551 /* We might have been passed a SUBREG. */
7552 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7553 return 0;
7554
7555 if (REGNO (reg1) % 2 != 0)
7556 return 0;
7557
7558 /* Integer ldd is deprecated in SPARC V9 */
7559 if (TARGET_V9 && REGNO (reg1) < 32)
7560 return 0;
7561
7562 return (REGNO (reg1) == REGNO (reg2) - 1);
7563 }
7564
7565 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7566 an ldd or std insn.
7567
7568 This can only happen when addr1 and addr2, the addresses in mem1
7569 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7570 addr1 must also be aligned on a 64-bit boundary.
7571
7572 Also iff dependent_reg_rtx is not null it should not be used to
7573 compute the address for mem1, i.e. we cannot optimize a sequence
7574 like:
7575 ld [%o0], %o0
7576 ld [%o0 + 4], %o1
7577 to
7578 ldd [%o0], %o0
7579 nor:
7580 ld [%g3 + 4], %g3
7581 ld [%g3], %g2
7582 to
7583 ldd [%g3], %g2
7584
7585 But, note that the transformation from:
7586 ld [%g2 + 4], %g3
7587 ld [%g2], %g2
7588 to
7589 ldd [%g2], %g2
7590 is perfectly fine. Thus, the peephole2 patterns always pass us
7591 the destination register of the first load, never the second one.
7592
7593 For stores we don't have a similar problem, so dependent_reg_rtx is
7594 NULL_RTX. */
7595
7596 int
7597 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
7598 {
7599 rtx addr1, addr2;
7600 unsigned int reg1;
7601 HOST_WIDE_INT offset1;
7602
7603 /* The mems cannot be volatile. */
7604 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7605 return 0;
7606
7607 /* MEM1 should be aligned on a 64-bit boundary. */
7608 if (MEM_ALIGN (mem1) < 64)
7609 return 0;
7610
7611 addr1 = XEXP (mem1, 0);
7612 addr2 = XEXP (mem2, 0);
7613
7614 /* Extract a register number and offset (if used) from the first addr. */
7615 if (GET_CODE (addr1) == PLUS)
7616 {
7617 /* If not a REG, return zero. */
7618 if (GET_CODE (XEXP (addr1, 0)) != REG)
7619 return 0;
7620 else
7621 {
7622 reg1 = REGNO (XEXP (addr1, 0));
7623 /* The offset must be constant! */
7624 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7625 return 0;
7626 offset1 = INTVAL (XEXP (addr1, 1));
7627 }
7628 }
7629 else if (GET_CODE (addr1) != REG)
7630 return 0;
7631 else
7632 {
7633 reg1 = REGNO (addr1);
7634 /* This was a simple (mem (reg)) expression. Offset is 0. */
7635 offset1 = 0;
7636 }
7637
7638 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7639 if (GET_CODE (addr2) != PLUS)
7640 return 0;
7641
7642 if (GET_CODE (XEXP (addr2, 0)) != REG
7643 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7644 return 0;
7645
7646 if (reg1 != REGNO (XEXP (addr2, 0)))
7647 return 0;
7648
7649 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7650 return 0;
7651
7652 /* The first offset must be evenly divisible by 8 to ensure the
7653 address is 64 bit aligned. */
7654 if (offset1 % 8 != 0)
7655 return 0;
7656
7657 /* The offset for the second addr must be 4 more than the first addr. */
7658 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7659 return 0;
7660
7661 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7662 instructions. */
7663 return 1;
7664 }
7665
7666 /* Return 1 if reg is a pseudo, or is the first register in
7667 a hard register pair. This makes it suitable for use in
7668 ldd and std insns. */
7669
7670 int
7671 register_ok_for_ldd (rtx reg)
7672 {
7673 /* We might have been passed a SUBREG. */
7674 if (!REG_P (reg))
7675 return 0;
7676
7677 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7678 return (REGNO (reg) % 2 == 0);
7679
7680 return 1;
7681 }
7682
7683 /* Return 1 if OP is a memory whose address is known to be
7684 aligned to 8-byte boundary, or a pseudo during reload.
7685 This makes it suitable for use in ldd and std insns. */
7686
7687 int
7688 memory_ok_for_ldd (rtx op)
7689 {
7690 if (MEM_P (op))
7691 {
7692 /* In 64-bit mode, we assume that the address is word-aligned. */
7693 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
7694 return 0;
7695
7696 if ((reload_in_progress || reload_completed)
7697 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
7698 return 0;
7699 }
7700 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
7701 {
7702 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
7703 return 0;
7704 }
7705 else
7706 return 0;
7707
7708 return 1;
7709 }
7710 \f
7711 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7712
7713 static bool
7714 sparc_print_operand_punct_valid_p (unsigned char code)
7715 {
7716 if (code == '#'
7717 || code == '*'
7718 || code == '('
7719 || code == ')'
7720 || code == '_'
7721 || code == '&')
7722 return true;
7723
7724 return false;
7725 }
7726
7727 /* Implement TARGET_PRINT_OPERAND.
7728 Print operand X (an rtx) in assembler syntax to file FILE.
7729 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7730 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7731
7732 static void
7733 sparc_print_operand (FILE *file, rtx x, int code)
7734 {
7735 switch (code)
7736 {
7737 case '#':
7738 /* Output an insn in a delay slot. */
7739 if (final_sequence)
7740 sparc_indent_opcode = 1;
7741 else
7742 fputs ("\n\t nop", file);
7743 return;
7744 case '*':
7745 /* Output an annul flag if there's nothing for the delay slot and we
7746 are optimizing. This is always used with '(' below.
7747 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7748 this is a dbx bug. So, we only do this when optimizing.
7749 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7750 Always emit a nop in case the next instruction is a branch. */
7751 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7752 fputs (",a", file);
7753 return;
7754 case '(':
7755 /* Output a 'nop' if there's nothing for the delay slot and we are
7756 not optimizing. This is always used with '*' above. */
7757 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7758 fputs ("\n\t nop", file);
7759 else if (final_sequence)
7760 sparc_indent_opcode = 1;
7761 return;
7762 case ')':
7763 /* Output the right displacement from the saved PC on function return.
7764 The caller may have placed an "unimp" insn immediately after the call
7765 so we have to account for it. This insn is used in the 32-bit ABI
7766 when calling a function that returns a non zero-sized structure. The
7767 64-bit ABI doesn't have it. Be careful to have this test be the same
7768 as that for the call. The exception is when sparc_std_struct_return
7769 is enabled, the psABI is followed exactly and the adjustment is made
7770 by the code in sparc_struct_value_rtx. The call emitted is the same
7771 when sparc_std_struct_return is enabled. */
7772 if (!TARGET_ARCH64
7773 && cfun->returns_struct
7774 && !sparc_std_struct_return
7775 && DECL_SIZE (DECL_RESULT (current_function_decl))
7776 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
7777 == INTEGER_CST
7778 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
7779 fputs ("12", file);
7780 else
7781 fputc ('8', file);
7782 return;
7783 case '_':
7784 /* Output the Embedded Medium/Anywhere code model base register. */
7785 fputs (EMBMEDANY_BASE_REG, file);
7786 return;
7787 case '&':
7788 /* Print some local dynamic TLS name. */
7789 assemble_name (file, get_some_local_dynamic_name ());
7790 return;
7791
7792 case 'Y':
7793 /* Adjust the operand to take into account a RESTORE operation. */
7794 if (GET_CODE (x) == CONST_INT)
7795 break;
7796 else if (GET_CODE (x) != REG)
7797 output_operand_lossage ("invalid %%Y operand");
7798 else if (REGNO (x) < 8)
7799 fputs (reg_names[REGNO (x)], file);
7800 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7801 fputs (reg_names[REGNO (x)-16], file);
7802 else
7803 output_operand_lossage ("invalid %%Y operand");
7804 return;
7805 case 'L':
7806 /* Print out the low order register name of a register pair. */
7807 if (WORDS_BIG_ENDIAN)
7808 fputs (reg_names[REGNO (x)+1], file);
7809 else
7810 fputs (reg_names[REGNO (x)], file);
7811 return;
7812 case 'H':
7813 /* Print out the high order register name of a register pair. */
7814 if (WORDS_BIG_ENDIAN)
7815 fputs (reg_names[REGNO (x)], file);
7816 else
7817 fputs (reg_names[REGNO (x)+1], file);
7818 return;
7819 case 'R':
7820 /* Print out the second register name of a register pair or quad.
7821 I.e., R (%o0) => %o1. */
7822 fputs (reg_names[REGNO (x)+1], file);
7823 return;
7824 case 'S':
7825 /* Print out the third register name of a register quad.
7826 I.e., S (%o0) => %o2. */
7827 fputs (reg_names[REGNO (x)+2], file);
7828 return;
7829 case 'T':
7830 /* Print out the fourth register name of a register quad.
7831 I.e., T (%o0) => %o3. */
7832 fputs (reg_names[REGNO (x)+3], file);
7833 return;
7834 case 'x':
7835 /* Print a condition code register. */
7836 if (REGNO (x) == SPARC_ICC_REG)
7837 {
7838 /* We don't handle CC[X]_NOOVmode because they're not supposed
7839 to occur here. */
7840 if (GET_MODE (x) == CCmode)
7841 fputs ("%icc", file);
7842 else if (GET_MODE (x) == CCXmode)
7843 fputs ("%xcc", file);
7844 else
7845 gcc_unreachable ();
7846 }
7847 else
7848 /* %fccN register */
7849 fputs (reg_names[REGNO (x)], file);
7850 return;
7851 case 'm':
7852 /* Print the operand's address only. */
7853 output_address (XEXP (x, 0));
7854 return;
7855 case 'r':
7856 /* In this case we need a register. Use %g0 if the
7857 operand is const0_rtx. */
7858 if (x == const0_rtx
7859 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7860 {
7861 fputs ("%g0", file);
7862 return;
7863 }
7864 else
7865 break;
7866
7867 case 'A':
7868 switch (GET_CODE (x))
7869 {
7870 case IOR: fputs ("or", file); break;
7871 case AND: fputs ("and", file); break;
7872 case XOR: fputs ("xor", file); break;
7873 default: output_operand_lossage ("invalid %%A operand");
7874 }
7875 return;
7876
7877 case 'B':
7878 switch (GET_CODE (x))
7879 {
7880 case IOR: fputs ("orn", file); break;
7881 case AND: fputs ("andn", file); break;
7882 case XOR: fputs ("xnor", file); break;
7883 default: output_operand_lossage ("invalid %%B operand");
7884 }
7885 return;
7886
7887 /* These are used by the conditional move instructions. */
7888 case 'c' :
7889 case 'C':
7890 {
7891 enum rtx_code rc = GET_CODE (x);
7892
7893 if (code == 'c')
7894 {
7895 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7896 if (mode == CCFPmode || mode == CCFPEmode)
7897 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7898 else
7899 rc = reverse_condition (GET_CODE (x));
7900 }
7901 switch (rc)
7902 {
7903 case NE: fputs ("ne", file); break;
7904 case EQ: fputs ("e", file); break;
7905 case GE: fputs ("ge", file); break;
7906 case GT: fputs ("g", file); break;
7907 case LE: fputs ("le", file); break;
7908 case LT: fputs ("l", file); break;
7909 case GEU: fputs ("geu", file); break;
7910 case GTU: fputs ("gu", file); break;
7911 case LEU: fputs ("leu", file); break;
7912 case LTU: fputs ("lu", file); break;
7913 case LTGT: fputs ("lg", file); break;
7914 case UNORDERED: fputs ("u", file); break;
7915 case ORDERED: fputs ("o", file); break;
7916 case UNLT: fputs ("ul", file); break;
7917 case UNLE: fputs ("ule", file); break;
7918 case UNGT: fputs ("ug", file); break;
7919 case UNGE: fputs ("uge", file); break;
7920 case UNEQ: fputs ("ue", file); break;
7921 default: output_operand_lossage (code == 'c'
7922 ? "invalid %%c operand"
7923 : "invalid %%C operand");
7924 }
7925 return;
7926 }
7927
7928 /* These are used by the movr instruction pattern. */
7929 case 'd':
7930 case 'D':
7931 {
7932 enum rtx_code rc = (code == 'd'
7933 ? reverse_condition (GET_CODE (x))
7934 : GET_CODE (x));
7935 switch (rc)
7936 {
7937 case NE: fputs ("ne", file); break;
7938 case EQ: fputs ("e", file); break;
7939 case GE: fputs ("gez", file); break;
7940 case LT: fputs ("lz", file); break;
7941 case LE: fputs ("lez", file); break;
7942 case GT: fputs ("gz", file); break;
7943 default: output_operand_lossage (code == 'd'
7944 ? "invalid %%d operand"
7945 : "invalid %%D operand");
7946 }
7947 return;
7948 }
7949
7950 case 'b':
7951 {
7952 /* Print a sign-extended character. */
7953 int i = trunc_int_for_mode (INTVAL (x), QImode);
7954 fprintf (file, "%d", i);
7955 return;
7956 }
7957
7958 case 'f':
7959 /* Operand must be a MEM; write its address. */
7960 if (GET_CODE (x) != MEM)
7961 output_operand_lossage ("invalid %%f operand");
7962 output_address (XEXP (x, 0));
7963 return;
7964
7965 case 's':
7966 {
7967 /* Print a sign-extended 32-bit value. */
7968 HOST_WIDE_INT i;
7969 if (GET_CODE(x) == CONST_INT)
7970 i = INTVAL (x);
7971 else if (GET_CODE(x) == CONST_DOUBLE)
7972 i = CONST_DOUBLE_LOW (x);
7973 else
7974 {
7975 output_operand_lossage ("invalid %%s operand");
7976 return;
7977 }
7978 i = trunc_int_for_mode (i, SImode);
7979 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7980 return;
7981 }
7982
7983 case 0:
7984 /* Do nothing special. */
7985 break;
7986
7987 default:
7988 /* Undocumented flag. */
7989 output_operand_lossage ("invalid operand output code");
7990 }
7991
7992 if (GET_CODE (x) == REG)
7993 fputs (reg_names[REGNO (x)], file);
7994 else if (GET_CODE (x) == MEM)
7995 {
7996 fputc ('[', file);
7997 /* Poor Sun assembler doesn't understand absolute addressing. */
7998 if (CONSTANT_P (XEXP (x, 0)))
7999 fputs ("%g0+", file);
8000 output_address (XEXP (x, 0));
8001 fputc (']', file);
8002 }
8003 else if (GET_CODE (x) == HIGH)
8004 {
8005 fputs ("%hi(", file);
8006 output_addr_const (file, XEXP (x, 0));
8007 fputc (')', file);
8008 }
8009 else if (GET_CODE (x) == LO_SUM)
8010 {
8011 sparc_print_operand (file, XEXP (x, 0), 0);
8012 if (TARGET_CM_MEDMID)
8013 fputs ("+%l44(", file);
8014 else
8015 fputs ("+%lo(", file);
8016 output_addr_const (file, XEXP (x, 1));
8017 fputc (')', file);
8018 }
8019 else if (GET_CODE (x) == CONST_DOUBLE
8020 && (GET_MODE (x) == VOIDmode
8021 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
8022 {
8023 if (CONST_DOUBLE_HIGH (x) == 0)
8024 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
8025 else if (CONST_DOUBLE_HIGH (x) == -1
8026 && CONST_DOUBLE_LOW (x) < 0)
8027 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
8028 else
8029 output_operand_lossage ("long long constant not a valid immediate operand");
8030 }
8031 else if (GET_CODE (x) == CONST_DOUBLE)
8032 output_operand_lossage ("floating point constant not a valid immediate operand");
8033 else { output_addr_const (file, x); }
8034 }
8035
8036 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8037
8038 static void
8039 sparc_print_operand_address (FILE *file, rtx x)
8040 {
8041 register rtx base, index = 0;
8042 int offset = 0;
8043 register rtx addr = x;
8044
8045 if (REG_P (addr))
8046 fputs (reg_names[REGNO (addr)], file);
8047 else if (GET_CODE (addr) == PLUS)
8048 {
8049 if (CONST_INT_P (XEXP (addr, 0)))
8050 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
8051 else if (CONST_INT_P (XEXP (addr, 1)))
8052 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
8053 else
8054 base = XEXP (addr, 0), index = XEXP (addr, 1);
8055 if (GET_CODE (base) == LO_SUM)
8056 {
8057 gcc_assert (USE_AS_OFFSETABLE_LO10
8058 && TARGET_ARCH64
8059 && ! TARGET_CM_MEDMID);
8060 output_operand (XEXP (base, 0), 0);
8061 fputs ("+%lo(", file);
8062 output_address (XEXP (base, 1));
8063 fprintf (file, ")+%d", offset);
8064 }
8065 else
8066 {
8067 fputs (reg_names[REGNO (base)], file);
8068 if (index == 0)
8069 fprintf (file, "%+d", offset);
8070 else if (REG_P (index))
8071 fprintf (file, "+%s", reg_names[REGNO (index)]);
8072 else if (GET_CODE (index) == SYMBOL_REF
8073 || GET_CODE (index) == LABEL_REF
8074 || GET_CODE (index) == CONST)
8075 fputc ('+', file), output_addr_const (file, index);
8076 else gcc_unreachable ();
8077 }
8078 }
8079 else if (GET_CODE (addr) == MINUS
8080 && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
8081 {
8082 output_addr_const (file, XEXP (addr, 0));
8083 fputs ("-(", file);
8084 output_addr_const (file, XEXP (addr, 1));
8085 fputs ("-.)", file);
8086 }
8087 else if (GET_CODE (addr) == LO_SUM)
8088 {
8089 output_operand (XEXP (addr, 0), 0);
8090 if (TARGET_CM_MEDMID)
8091 fputs ("+%l44(", file);
8092 else
8093 fputs ("+%lo(", file);
8094 output_address (XEXP (addr, 1));
8095 fputc (')', file);
8096 }
8097 else if (flag_pic
8098 && GET_CODE (addr) == CONST
8099 && GET_CODE (XEXP (addr, 0)) == MINUS
8100 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST
8101 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS
8102 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)
8103 {
8104 addr = XEXP (addr, 0);
8105 output_addr_const (file, XEXP (addr, 0));
8106 /* Group the args of the second CONST in parenthesis. */
8107 fputs ("-(", file);
8108 /* Skip past the second CONST--it does nothing for us. */
8109 output_addr_const (file, XEXP (XEXP (addr, 1), 0));
8110 /* Close the parenthesis. */
8111 fputc (')', file);
8112 }
8113 else
8114 {
8115 output_addr_const (file, addr);
8116 }
8117 }
8118 \f
8119 /* Target hook for assembling integer objects. The sparc version has
8120 special handling for aligned DI-mode objects. */
8121
8122 static bool
8123 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
8124 {
8125 /* ??? We only output .xword's for symbols and only then in environments
8126 where the assembler can handle them. */
8127 if (aligned_p && size == 8
8128 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
8129 {
8130 if (TARGET_V9)
8131 {
8132 assemble_integer_with_op ("\t.xword\t", x);
8133 return true;
8134 }
8135 else
8136 {
8137 assemble_aligned_integer (4, const0_rtx);
8138 assemble_aligned_integer (4, x);
8139 return true;
8140 }
8141 }
8142 return default_assemble_integer (x, size, aligned_p);
8143 }
8144 \f
8145 /* Return the value of a code used in the .proc pseudo-op that says
8146 what kind of result this function returns. For non-C types, we pick
8147 the closest C type. */
8148
8149 #ifndef SHORT_TYPE_SIZE
8150 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8151 #endif
8152
8153 #ifndef INT_TYPE_SIZE
8154 #define INT_TYPE_SIZE BITS_PER_WORD
8155 #endif
8156
8157 #ifndef LONG_TYPE_SIZE
8158 #define LONG_TYPE_SIZE BITS_PER_WORD
8159 #endif
8160
8161 #ifndef LONG_LONG_TYPE_SIZE
8162 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8163 #endif
8164
8165 #ifndef FLOAT_TYPE_SIZE
8166 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8167 #endif
8168
8169 #ifndef DOUBLE_TYPE_SIZE
8170 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8171 #endif
8172
8173 #ifndef LONG_DOUBLE_TYPE_SIZE
8174 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8175 #endif
8176
8177 unsigned long
8178 sparc_type_code (register tree type)
8179 {
8180 register unsigned long qualifiers = 0;
8181 register unsigned shift;
8182
8183 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8184 setting more, since some assemblers will give an error for this. Also,
8185 we must be careful to avoid shifts of 32 bits or more to avoid getting
8186 unpredictable results. */
8187
8188 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
8189 {
8190 switch (TREE_CODE (type))
8191 {
8192 case ERROR_MARK:
8193 return qualifiers;
8194
8195 case ARRAY_TYPE:
8196 qualifiers |= (3 << shift);
8197 break;
8198
8199 case FUNCTION_TYPE:
8200 case METHOD_TYPE:
8201 qualifiers |= (2 << shift);
8202 break;
8203
8204 case POINTER_TYPE:
8205 case REFERENCE_TYPE:
8206 case OFFSET_TYPE:
8207 qualifiers |= (1 << shift);
8208 break;
8209
8210 case RECORD_TYPE:
8211 return (qualifiers | 8);
8212
8213 case UNION_TYPE:
8214 case QUAL_UNION_TYPE:
8215 return (qualifiers | 9);
8216
8217 case ENUMERAL_TYPE:
8218 return (qualifiers | 10);
8219
8220 case VOID_TYPE:
8221 return (qualifiers | 16);
8222
8223 case INTEGER_TYPE:
8224 /* If this is a range type, consider it to be the underlying
8225 type. */
8226 if (TREE_TYPE (type) != 0)
8227 break;
8228
8229 /* Carefully distinguish all the standard types of C,
8230 without messing up if the language is not C. We do this by
8231 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8232 look at both the names and the above fields, but that's redundant.
8233 Any type whose size is between two C types will be considered
8234 to be the wider of the two types. Also, we do not have a
8235 special code to use for "long long", so anything wider than
8236 long is treated the same. Note that we can't distinguish
8237 between "int" and "long" in this code if they are the same
8238 size, but that's fine, since neither can the assembler. */
8239
8240 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
8241 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
8242
8243 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
8244 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
8245
8246 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
8247 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
8248
8249 else
8250 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
8251
8252 case REAL_TYPE:
8253 /* If this is a range type, consider it to be the underlying
8254 type. */
8255 if (TREE_TYPE (type) != 0)
8256 break;
8257
8258 /* Carefully distinguish all the standard types of C,
8259 without messing up if the language is not C. */
8260
8261 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
8262 return (qualifiers | 6);
8263
8264 else
8265 return (qualifiers | 7);
8266
8267 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
8268 /* ??? We need to distinguish between double and float complex types,
8269 but I don't know how yet because I can't reach this code from
8270 existing front-ends. */
8271 return (qualifiers | 7); /* Who knows? */
8272
8273 case VECTOR_TYPE:
8274 case BOOLEAN_TYPE: /* Boolean truth value type. */
8275 case LANG_TYPE:
8276 case NULLPTR_TYPE:
8277 return qualifiers;
8278
8279 default:
8280 gcc_unreachable (); /* Not a type! */
8281 }
8282 }
8283
8284 return qualifiers;
8285 }
8286 \f
8287 /* Nested function support. */
8288
8289 /* Emit RTL insns to initialize the variable parts of a trampoline.
8290 FNADDR is an RTX for the address of the function's pure code.
8291 CXT is an RTX for the static chain value for the function.
8292
8293 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8294 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8295 (to store insns). This is a bit excessive. Perhaps a different
8296 mechanism would be better here.
8297
8298 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8299
8300 static void
8301 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8302 {
8303 /* SPARC 32-bit trampoline:
8304
8305 sethi %hi(fn), %g1
8306 sethi %hi(static), %g2
8307 jmp %g1+%lo(fn)
8308 or %g2, %lo(static), %g2
8309
8310 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8311 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8312 */
8313
8314 emit_move_insn
8315 (adjust_address (m_tramp, SImode, 0),
8316 expand_binop (SImode, ior_optab,
8317 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1),
8318 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
8319 NULL_RTX, 1, OPTAB_DIRECT));
8320
8321 emit_move_insn
8322 (adjust_address (m_tramp, SImode, 4),
8323 expand_binop (SImode, ior_optab,
8324 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1),
8325 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
8326 NULL_RTX, 1, OPTAB_DIRECT));
8327
8328 emit_move_insn
8329 (adjust_address (m_tramp, SImode, 8),
8330 expand_binop (SImode, ior_optab,
8331 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
8332 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
8333 NULL_RTX, 1, OPTAB_DIRECT));
8334
8335 emit_move_insn
8336 (adjust_address (m_tramp, SImode, 12),
8337 expand_binop (SImode, ior_optab,
8338 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
8339 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
8340 NULL_RTX, 1, OPTAB_DIRECT));
8341
8342 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8343 aligned on a 16 byte boundary so one flush clears it all. */
8344 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
8345 if (sparc_cpu != PROCESSOR_ULTRASPARC
8346 && sparc_cpu != PROCESSOR_ULTRASPARC3
8347 && sparc_cpu != PROCESSOR_NIAGARA
8348 && sparc_cpu != PROCESSOR_NIAGARA2)
8349 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
8350
8351 /* Call __enable_execute_stack after writing onto the stack to make sure
8352 the stack address is accessible. */
8353 #ifdef HAVE_ENABLE_EXECUTE_STACK
8354 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8355 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8356 #endif
8357
8358 }
8359
8360 /* The 64-bit version is simpler because it makes more sense to load the
8361 values as "immediate" data out of the trampoline. It's also easier since
8362 we can read the PC without clobbering a register. */
8363
8364 static void
8365 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8366 {
8367 /* SPARC 64-bit trampoline:
8368
8369 rd %pc, %g1
8370 ldx [%g1+24], %g5
8371 jmp %g5
8372 ldx [%g1+16], %g5
8373 +16 bytes data
8374 */
8375
8376 emit_move_insn (adjust_address (m_tramp, SImode, 0),
8377 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
8378 emit_move_insn (adjust_address (m_tramp, SImode, 4),
8379 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
8380 emit_move_insn (adjust_address (m_tramp, SImode, 8),
8381 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
8382 emit_move_insn (adjust_address (m_tramp, SImode, 12),
8383 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
8384 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
8385 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
8386 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
8387
8388 if (sparc_cpu != PROCESSOR_ULTRASPARC
8389 && sparc_cpu != PROCESSOR_ULTRASPARC3
8390 && sparc_cpu != PROCESSOR_NIAGARA
8391 && sparc_cpu != PROCESSOR_NIAGARA2)
8392 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
8393
8394 /* Call __enable_execute_stack after writing onto the stack to make sure
8395 the stack address is accessible. */
8396 #ifdef HAVE_ENABLE_EXECUTE_STACK
8397 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8398 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8399 #endif
8400 }
8401
8402 /* Worker for TARGET_TRAMPOLINE_INIT. */
8403
8404 static void
8405 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
8406 {
8407 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
8408 cxt = force_reg (Pmode, cxt);
8409 if (TARGET_ARCH64)
8410 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
8411 else
8412 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
8413 }
8414 \f
8415 /* Adjust the cost of a scheduling dependency. Return the new cost of
8416 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8417
8418 static int
8419 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8420 {
8421 enum attr_type insn_type;
8422
8423 if (! recog_memoized (insn))
8424 return 0;
8425
8426 insn_type = get_attr_type (insn);
8427
8428 if (REG_NOTE_KIND (link) == 0)
8429 {
8430 /* Data dependency; DEP_INSN writes a register that INSN reads some
8431 cycles later. */
8432
8433 /* if a load, then the dependence must be on the memory address;
8434 add an extra "cycle". Note that the cost could be two cycles
8435 if the reg was written late in an instruction group; we ca not tell
8436 here. */
8437 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8438 return cost + 3;
8439
8440 /* Get the delay only if the address of the store is the dependence. */
8441 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8442 {
8443 rtx pat = PATTERN(insn);
8444 rtx dep_pat = PATTERN (dep_insn);
8445
8446 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8447 return cost; /* This should not happen! */
8448
8449 /* The dependency between the two instructions was on the data that
8450 is being stored. Assume that this implies that the address of the
8451 store is not dependent. */
8452 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8453 return cost;
8454
8455 return cost + 3; /* An approximation. */
8456 }
8457
8458 /* A shift instruction cannot receive its data from an instruction
8459 in the same cycle; add a one cycle penalty. */
8460 if (insn_type == TYPE_SHIFT)
8461 return cost + 3; /* Split before cascade into shift. */
8462 }
8463 else
8464 {
8465 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8466 INSN writes some cycles later. */
8467
8468 /* These are only significant for the fpu unit; writing a fp reg before
8469 the fpu has finished with it stalls the processor. */
8470
8471 /* Reusing an integer register causes no problems. */
8472 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8473 return 0;
8474 }
8475
8476 return cost;
8477 }
8478
8479 static int
8480 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8481 {
8482 enum attr_type insn_type, dep_type;
8483 rtx pat = PATTERN(insn);
8484 rtx dep_pat = PATTERN (dep_insn);
8485
8486 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8487 return cost;
8488
8489 insn_type = get_attr_type (insn);
8490 dep_type = get_attr_type (dep_insn);
8491
8492 switch (REG_NOTE_KIND (link))
8493 {
8494 case 0:
8495 /* Data dependency; DEP_INSN writes a register that INSN reads some
8496 cycles later. */
8497
8498 switch (insn_type)
8499 {
8500 case TYPE_STORE:
8501 case TYPE_FPSTORE:
8502 /* Get the delay iff the address of the store is the dependence. */
8503 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8504 return cost;
8505
8506 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8507 return cost;
8508 return cost + 3;
8509
8510 case TYPE_LOAD:
8511 case TYPE_SLOAD:
8512 case TYPE_FPLOAD:
8513 /* If a load, then the dependence must be on the memory address. If
8514 the addresses aren't equal, then it might be a false dependency */
8515 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8516 {
8517 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8518 || GET_CODE (SET_DEST (dep_pat)) != MEM
8519 || GET_CODE (SET_SRC (pat)) != MEM
8520 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8521 XEXP (SET_SRC (pat), 0)))
8522 return cost + 2;
8523
8524 return cost + 8;
8525 }
8526 break;
8527
8528 case TYPE_BRANCH:
8529 /* Compare to branch latency is 0. There is no benefit from
8530 separating compare and branch. */
8531 if (dep_type == TYPE_COMPARE)
8532 return 0;
8533 /* Floating point compare to branch latency is less than
8534 compare to conditional move. */
8535 if (dep_type == TYPE_FPCMP)
8536 return cost - 1;
8537 break;
8538 default:
8539 break;
8540 }
8541 break;
8542
8543 case REG_DEP_ANTI:
8544 /* Anti-dependencies only penalize the fpu unit. */
8545 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8546 return 0;
8547 break;
8548
8549 default:
8550 break;
8551 }
8552
8553 return cost;
8554 }
8555
8556 static int
8557 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8558 {
8559 switch (sparc_cpu)
8560 {
8561 case PROCESSOR_SUPERSPARC:
8562 cost = supersparc_adjust_cost (insn, link, dep, cost);
8563 break;
8564 case PROCESSOR_HYPERSPARC:
8565 case PROCESSOR_SPARCLITE86X:
8566 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8567 break;
8568 default:
8569 break;
8570 }
8571 return cost;
8572 }
8573
8574 static void
8575 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8576 int sched_verbose ATTRIBUTE_UNUSED,
8577 int max_ready ATTRIBUTE_UNUSED)
8578 {}
8579
8580 static int
8581 sparc_use_sched_lookahead (void)
8582 {
8583 if (sparc_cpu == PROCESSOR_NIAGARA
8584 || sparc_cpu == PROCESSOR_NIAGARA2)
8585 return 0;
8586 if (sparc_cpu == PROCESSOR_ULTRASPARC
8587 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8588 return 4;
8589 if ((1 << sparc_cpu) &
8590 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8591 (1 << PROCESSOR_SPARCLITE86X)))
8592 return 3;
8593 return 0;
8594 }
8595
8596 static int
8597 sparc_issue_rate (void)
8598 {
8599 switch (sparc_cpu)
8600 {
8601 case PROCESSOR_NIAGARA:
8602 case PROCESSOR_NIAGARA2:
8603 default:
8604 return 1;
8605 case PROCESSOR_V9:
8606 /* Assume V9 processors are capable of at least dual-issue. */
8607 return 2;
8608 case PROCESSOR_SUPERSPARC:
8609 return 3;
8610 case PROCESSOR_HYPERSPARC:
8611 case PROCESSOR_SPARCLITE86X:
8612 return 2;
8613 case PROCESSOR_ULTRASPARC:
8614 case PROCESSOR_ULTRASPARC3:
8615 return 4;
8616 }
8617 }
8618
8619 static int
8620 set_extends (rtx insn)
8621 {
8622 register rtx pat = PATTERN (insn);
8623
8624 switch (GET_CODE (SET_SRC (pat)))
8625 {
8626 /* Load and some shift instructions zero extend. */
8627 case MEM:
8628 case ZERO_EXTEND:
8629 /* sethi clears the high bits */
8630 case HIGH:
8631 /* LO_SUM is used with sethi. sethi cleared the high
8632 bits and the values used with lo_sum are positive */
8633 case LO_SUM:
8634 /* Store flag stores 0 or 1 */
8635 case LT: case LTU:
8636 case GT: case GTU:
8637 case LE: case LEU:
8638 case GE: case GEU:
8639 case EQ:
8640 case NE:
8641 return 1;
8642 case AND:
8643 {
8644 rtx op0 = XEXP (SET_SRC (pat), 0);
8645 rtx op1 = XEXP (SET_SRC (pat), 1);
8646 if (GET_CODE (op1) == CONST_INT)
8647 return INTVAL (op1) >= 0;
8648 if (GET_CODE (op0) != REG)
8649 return 0;
8650 if (sparc_check_64 (op0, insn) == 1)
8651 return 1;
8652 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8653 }
8654 case IOR:
8655 case XOR:
8656 {
8657 rtx op0 = XEXP (SET_SRC (pat), 0);
8658 rtx op1 = XEXP (SET_SRC (pat), 1);
8659 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8660 return 0;
8661 if (GET_CODE (op1) == CONST_INT)
8662 return INTVAL (op1) >= 0;
8663 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8664 }
8665 case LSHIFTRT:
8666 return GET_MODE (SET_SRC (pat)) == SImode;
8667 /* Positive integers leave the high bits zero. */
8668 case CONST_DOUBLE:
8669 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8670 case CONST_INT:
8671 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8672 case ASHIFTRT:
8673 case SIGN_EXTEND:
8674 return - (GET_MODE (SET_SRC (pat)) == SImode);
8675 case REG:
8676 return sparc_check_64 (SET_SRC (pat), insn);
8677 default:
8678 return 0;
8679 }
8680 }
8681
8682 /* We _ought_ to have only one kind per function, but... */
8683 static GTY(()) rtx sparc_addr_diff_list;
8684 static GTY(()) rtx sparc_addr_list;
8685
8686 void
8687 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8688 {
8689 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8690 if (diff)
8691 sparc_addr_diff_list
8692 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8693 else
8694 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8695 }
8696
8697 static void
8698 sparc_output_addr_vec (rtx vec)
8699 {
8700 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8701 int idx, vlen = XVECLEN (body, 0);
8702
8703 #ifdef ASM_OUTPUT_ADDR_VEC_START
8704 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8705 #endif
8706
8707 #ifdef ASM_OUTPUT_CASE_LABEL
8708 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8709 NEXT_INSN (lab));
8710 #else
8711 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8712 #endif
8713
8714 for (idx = 0; idx < vlen; idx++)
8715 {
8716 ASM_OUTPUT_ADDR_VEC_ELT
8717 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8718 }
8719
8720 #ifdef ASM_OUTPUT_ADDR_VEC_END
8721 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8722 #endif
8723 }
8724
8725 static void
8726 sparc_output_addr_diff_vec (rtx vec)
8727 {
8728 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8729 rtx base = XEXP (XEXP (body, 0), 0);
8730 int idx, vlen = XVECLEN (body, 1);
8731
8732 #ifdef ASM_OUTPUT_ADDR_VEC_START
8733 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8734 #endif
8735
8736 #ifdef ASM_OUTPUT_CASE_LABEL
8737 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8738 NEXT_INSN (lab));
8739 #else
8740 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8741 #endif
8742
8743 for (idx = 0; idx < vlen; idx++)
8744 {
8745 ASM_OUTPUT_ADDR_DIFF_ELT
8746 (asm_out_file,
8747 body,
8748 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8749 CODE_LABEL_NUMBER (base));
8750 }
8751
8752 #ifdef ASM_OUTPUT_ADDR_VEC_END
8753 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8754 #endif
8755 }
8756
8757 static void
8758 sparc_output_deferred_case_vectors (void)
8759 {
8760 rtx t;
8761 int align;
8762
8763 if (sparc_addr_list == NULL_RTX
8764 && sparc_addr_diff_list == NULL_RTX)
8765 return;
8766
8767 /* Align to cache line in the function's code section. */
8768 switch_to_section (current_function_section ());
8769
8770 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8771 if (align > 0)
8772 ASM_OUTPUT_ALIGN (asm_out_file, align);
8773
8774 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8775 sparc_output_addr_vec (XEXP (t, 0));
8776 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8777 sparc_output_addr_diff_vec (XEXP (t, 0));
8778
8779 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8780 }
8781
8782 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8783 unknown. Return 1 if the high bits are zero, -1 if the register is
8784 sign extended. */
8785 int
8786 sparc_check_64 (rtx x, rtx insn)
8787 {
8788 /* If a register is set only once it is safe to ignore insns this
8789 code does not know how to handle. The loop will either recognize
8790 the single set and return the correct value or fail to recognize
8791 it and return 0. */
8792 int set_once = 0;
8793 rtx y = x;
8794
8795 gcc_assert (GET_CODE (x) == REG);
8796
8797 if (GET_MODE (x) == DImode)
8798 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8799
8800 if (flag_expensive_optimizations
8801 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
8802 set_once = 1;
8803
8804 if (insn == 0)
8805 {
8806 if (set_once)
8807 insn = get_last_insn_anywhere ();
8808 else
8809 return 0;
8810 }
8811
8812 while ((insn = PREV_INSN (insn)))
8813 {
8814 switch (GET_CODE (insn))
8815 {
8816 case JUMP_INSN:
8817 case NOTE:
8818 break;
8819 case CODE_LABEL:
8820 case CALL_INSN:
8821 default:
8822 if (! set_once)
8823 return 0;
8824 break;
8825 case INSN:
8826 {
8827 rtx pat = PATTERN (insn);
8828 if (GET_CODE (pat) != SET)
8829 return 0;
8830 if (rtx_equal_p (x, SET_DEST (pat)))
8831 return set_extends (insn);
8832 if (y && rtx_equal_p (y, SET_DEST (pat)))
8833 return set_extends (insn);
8834 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8835 return 0;
8836 }
8837 }
8838 }
8839 return 0;
8840 }
8841
8842 /* Returns assembly code to perform a DImode shift using
8843 a 64-bit global or out register on SPARC-V8+. */
8844 const char *
8845 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8846 {
8847 static char asm_code[60];
8848
8849 /* The scratch register is only required when the destination
8850 register is not a 64-bit global or out register. */
8851 if (which_alternative != 2)
8852 operands[3] = operands[0];
8853
8854 /* We can only shift by constants <= 63. */
8855 if (GET_CODE (operands[2]) == CONST_INT)
8856 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8857
8858 if (GET_CODE (operands[1]) == CONST_INT)
8859 {
8860 output_asm_insn ("mov\t%1, %3", operands);
8861 }
8862 else
8863 {
8864 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8865 if (sparc_check_64 (operands[1], insn) <= 0)
8866 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8867 output_asm_insn ("or\t%L1, %3, %3", operands);
8868 }
8869
8870 strcpy(asm_code, opcode);
8871
8872 if (which_alternative != 2)
8873 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8874 else
8875 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8876 }
8877 \f
8878 /* Output rtl to increment the profiler label LABELNO
8879 for profiling a function entry. */
8880
8881 void
8882 sparc_profile_hook (int labelno)
8883 {
8884 char buf[32];
8885 rtx lab, fun;
8886
8887 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8888 if (NO_PROFILE_COUNTERS)
8889 {
8890 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
8891 }
8892 else
8893 {
8894 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8895 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8896 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8897 }
8898 }
8899 \f
8900 #ifdef TARGET_SOLARIS
8901 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8902
8903 static void
8904 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
8905 tree decl ATTRIBUTE_UNUSED)
8906 {
8907 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
8908 {
8909 solaris_elf_asm_comdat_section (name, flags, decl);
8910 return;
8911 }
8912
8913 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8914
8915 if (!(flags & SECTION_DEBUG))
8916 fputs (",#alloc", asm_out_file);
8917 if (flags & SECTION_WRITE)
8918 fputs (",#write", asm_out_file);
8919 if (flags & SECTION_TLS)
8920 fputs (",#tls", asm_out_file);
8921 if (flags & SECTION_CODE)
8922 fputs (",#execinstr", asm_out_file);
8923
8924 /* ??? Handle SECTION_BSS. */
8925
8926 fputc ('\n', asm_out_file);
8927 }
8928 #endif /* TARGET_SOLARIS */
8929
8930 /* We do not allow indirect calls to be optimized into sibling calls.
8931
8932 We cannot use sibling calls when delayed branches are disabled
8933 because they will likely require the call delay slot to be filled.
8934
8935 Also, on SPARC 32-bit we cannot emit a sibling call when the
8936 current function returns a structure. This is because the "unimp
8937 after call" convention would cause the callee to return to the
8938 wrong place. The generic code already disallows cases where the
8939 function being called returns a structure.
8940
8941 It may seem strange how this last case could occur. Usually there
8942 is code after the call which jumps to epilogue code which dumps the
8943 return value into the struct return area. That ought to invalidate
8944 the sibling call right? Well, in the C++ case we can end up passing
8945 the pointer to the struct return area to a constructor (which returns
8946 void) and then nothing else happens. Such a sibling call would look
8947 valid without the added check here.
8948
8949 VxWorks PIC PLT entries require the global pointer to be initialized
8950 on entry. We therefore can't emit sibling calls to them. */
8951 static bool
8952 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8953 {
8954 return (decl
8955 && flag_delayed_branch
8956 && (TARGET_ARCH64 || ! cfun->returns_struct)
8957 && !(TARGET_VXWORKS_RTP
8958 && flag_pic
8959 && !targetm.binds_local_p (decl)));
8960 }
8961 \f
8962 /* libfunc renaming. */
8963
8964 static void
8965 sparc_init_libfuncs (void)
8966 {
8967 if (TARGET_ARCH32)
8968 {
8969 /* Use the subroutines that Sun's library provides for integer
8970 multiply and divide. The `*' prevents an underscore from
8971 being prepended by the compiler. .umul is a little faster
8972 than .mul. */
8973 set_optab_libfunc (smul_optab, SImode, "*.umul");
8974 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8975 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8976 set_optab_libfunc (smod_optab, SImode, "*.rem");
8977 set_optab_libfunc (umod_optab, SImode, "*.urem");
8978
8979 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8980 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8981 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8982 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8983 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8984 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8985
8986 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8987 is because with soft-float, the SFmode and DFmode sqrt
8988 instructions will be absent, and the compiler will notice and
8989 try to use the TFmode sqrt instruction for calls to the
8990 builtin function sqrt, but this fails. */
8991 if (TARGET_FPU)
8992 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8993
8994 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8995 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8996 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8997 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8998 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8999 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
9000
9001 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
9002 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
9003 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
9004 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
9005
9006 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
9007 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
9008 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9009 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
9010
9011 if (DITF_CONVERSION_LIBFUNCS)
9012 {
9013 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
9014 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
9015 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9016 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
9017 }
9018
9019 if (SUN_CONVERSION_LIBFUNCS)
9020 {
9021 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9022 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9023 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9024 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9025 }
9026 }
9027 if (TARGET_ARCH64)
9028 {
9029 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9030 do not exist in the library. Make sure the compiler does not
9031 emit calls to them by accident. (It should always use the
9032 hardware instructions.) */
9033 set_optab_libfunc (smul_optab, SImode, 0);
9034 set_optab_libfunc (sdiv_optab, SImode, 0);
9035 set_optab_libfunc (udiv_optab, SImode, 0);
9036 set_optab_libfunc (smod_optab, SImode, 0);
9037 set_optab_libfunc (umod_optab, SImode, 0);
9038
9039 if (SUN_INTEGER_MULTIPLY_64)
9040 {
9041 set_optab_libfunc (smul_optab, DImode, "__mul64");
9042 set_optab_libfunc (sdiv_optab, DImode, "__div64");
9043 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
9044 set_optab_libfunc (smod_optab, DImode, "__rem64");
9045 set_optab_libfunc (umod_optab, DImode, "__urem64");
9046 }
9047
9048 if (SUN_CONVERSION_LIBFUNCS)
9049 {
9050 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
9051 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
9052 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
9053 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
9054 }
9055 }
9056 }
9057 \f
9058 #define def_builtin(NAME, CODE, TYPE) \
9059 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
9060 NULL_TREE)
9061
9062 /* Implement the TARGET_INIT_BUILTINS target hook.
9063 Create builtin functions for special SPARC instructions. */
9064
9065 static void
9066 sparc_init_builtins (void)
9067 {
9068 if (TARGET_VIS)
9069 sparc_vis_init_builtins ();
9070 }
9071
9072 /* Create builtin functions for VIS 1.0 instructions. */
9073
9074 static void
9075 sparc_vis_init_builtins (void)
9076 {
9077 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
9078 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
9079 tree v4hi = build_vector_type (intHI_type_node, 4);
9080 tree v2hi = build_vector_type (intHI_type_node, 2);
9081 tree v2si = build_vector_type (intSI_type_node, 2);
9082
9083 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
9084 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
9085 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
9086 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
9087 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
9088 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
9089 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
9090 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
9091 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
9092 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
9093 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
9094 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
9095 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
9096 v8qi, v8qi,
9097 intDI_type_node, 0);
9098 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
9099 intDI_type_node,
9100 intDI_type_node, 0);
9101 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
9102 ptr_type_node,
9103 intSI_type_node, 0);
9104 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
9105 ptr_type_node,
9106 intDI_type_node, 0);
9107
9108 /* Packing and expanding vectors. */
9109 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
9110 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
9111 v8qi_ftype_v2si_v8qi);
9112 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
9113 v2hi_ftype_v2si);
9114 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
9115 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
9116 v8qi_ftype_v4qi_v4qi);
9117
9118 /* Multiplications. */
9119 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
9120 v4hi_ftype_v4qi_v4hi);
9121 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
9122 v4hi_ftype_v4qi_v2hi);
9123 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
9124 v4hi_ftype_v4qi_v2hi);
9125 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
9126 v4hi_ftype_v8qi_v4hi);
9127 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
9128 v4hi_ftype_v8qi_v4hi);
9129 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
9130 v2si_ftype_v4qi_v2hi);
9131 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
9132 v2si_ftype_v4qi_v2hi);
9133
9134 /* Data aligning. */
9135 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
9136 v4hi_ftype_v4hi_v4hi);
9137 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
9138 v8qi_ftype_v8qi_v8qi);
9139 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
9140 v2si_ftype_v2si_v2si);
9141 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
9142 di_ftype_di_di);
9143 if (TARGET_ARCH64)
9144 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
9145 ptr_ftype_ptr_di);
9146 else
9147 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
9148 ptr_ftype_ptr_si);
9149
9150 /* Pixel distance. */
9151 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
9152 di_ftype_v8qi_v8qi_di);
9153 }
9154
9155 /* Handle TARGET_EXPAND_BUILTIN target hook.
9156 Expand builtin functions for sparc intrinsics. */
9157
9158 static rtx
9159 sparc_expand_builtin (tree exp, rtx target,
9160 rtx subtarget ATTRIBUTE_UNUSED,
9161 enum machine_mode tmode ATTRIBUTE_UNUSED,
9162 int ignore ATTRIBUTE_UNUSED)
9163 {
9164 tree arg;
9165 call_expr_arg_iterator iter;
9166 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9167 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
9168 rtx pat, op[4];
9169 enum machine_mode mode[4];
9170 int arg_count = 0;
9171
9172 mode[0] = insn_data[icode].operand[0].mode;
9173 if (!target
9174 || GET_MODE (target) != mode[0]
9175 || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
9176 op[0] = gen_reg_rtx (mode[0]);
9177 else
9178 op[0] = target;
9179
9180 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9181 {
9182 arg_count++;
9183 mode[arg_count] = insn_data[icode].operand[arg_count].mode;
9184 op[arg_count] = expand_normal (arg);
9185
9186 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
9187 mode[arg_count]))
9188 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
9189 }
9190
9191 switch (arg_count)
9192 {
9193 case 1:
9194 pat = GEN_FCN (icode) (op[0], op[1]);
9195 break;
9196 case 2:
9197 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9198 break;
9199 case 3:
9200 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9201 break;
9202 default:
9203 gcc_unreachable ();
9204 }
9205
9206 if (!pat)
9207 return NULL_RTX;
9208
9209 emit_insn (pat);
9210
9211 return op[0];
9212 }
9213
9214 static int
9215 sparc_vis_mul8x16 (int e8, int e16)
9216 {
9217 return (e8 * e16 + 128) / 256;
9218 }
9219
9220 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9221 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9222 constants. A tree list with the results of the multiplications is returned,
9223 and each element in the list is of INNER_TYPE. */
9224
9225 static tree
9226 sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
9227 {
9228 tree n_elts = NULL_TREE;
9229 int scale;
9230
9231 switch (fncode)
9232 {
9233 case CODE_FOR_fmul8x16_vis:
9234 for (; elts0 && elts1;
9235 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9236 {
9237 int val
9238 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9239 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
9240 n_elts = tree_cons (NULL_TREE,
9241 build_int_cst (inner_type, val),
9242 n_elts);
9243 }
9244 break;
9245
9246 case CODE_FOR_fmul8x16au_vis:
9247 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9248
9249 for (; elts0; elts0 = TREE_CHAIN (elts0))
9250 {
9251 int val
9252 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9253 scale);
9254 n_elts = tree_cons (NULL_TREE,
9255 build_int_cst (inner_type, val),
9256 n_elts);
9257 }
9258 break;
9259
9260 case CODE_FOR_fmul8x16al_vis:
9261 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
9262
9263 for (; elts0; elts0 = TREE_CHAIN (elts0))
9264 {
9265 int val
9266 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9267 scale);
9268 n_elts = tree_cons (NULL_TREE,
9269 build_int_cst (inner_type, val),
9270 n_elts);
9271 }
9272 break;
9273
9274 default:
9275 gcc_unreachable ();
9276 }
9277
9278 return nreverse (n_elts);
9279
9280 }
9281 /* Handle TARGET_FOLD_BUILTIN target hook.
9282 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9283 result of the function call is ignored. NULL_TREE is returned if the
9284 function could not be folded. */
9285
9286 static tree
9287 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
9288 tree *args, bool ignore)
9289 {
9290 tree arg0, arg1, arg2;
9291 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
9292 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
9293
9294 if (ignore
9295 && icode != CODE_FOR_alignaddrsi_vis
9296 && icode != CODE_FOR_alignaddrdi_vis)
9297 return build_zero_cst (rtype);
9298
9299 switch (icode)
9300 {
9301 case CODE_FOR_fexpand_vis:
9302 arg0 = args[0];
9303 STRIP_NOPS (arg0);
9304
9305 if (TREE_CODE (arg0) == VECTOR_CST)
9306 {
9307 tree inner_type = TREE_TYPE (rtype);
9308 tree elts = TREE_VECTOR_CST_ELTS (arg0);
9309 tree n_elts = NULL_TREE;
9310
9311 for (; elts; elts = TREE_CHAIN (elts))
9312 {
9313 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
9314 n_elts = tree_cons (NULL_TREE,
9315 build_int_cst (inner_type, val),
9316 n_elts);
9317 }
9318 return build_vector (rtype, nreverse (n_elts));
9319 }
9320 break;
9321
9322 case CODE_FOR_fmul8x16_vis:
9323 case CODE_FOR_fmul8x16au_vis:
9324 case CODE_FOR_fmul8x16al_vis:
9325 arg0 = args[0];
9326 arg1 = args[1];
9327 STRIP_NOPS (arg0);
9328 STRIP_NOPS (arg1);
9329
9330 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9331 {
9332 tree inner_type = TREE_TYPE (rtype);
9333 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9334 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9335 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
9336 elts1);
9337
9338 return build_vector (rtype, n_elts);
9339 }
9340 break;
9341
9342 case CODE_FOR_fpmerge_vis:
9343 arg0 = args[0];
9344 arg1 = args[1];
9345 STRIP_NOPS (arg0);
9346 STRIP_NOPS (arg1);
9347
9348 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9349 {
9350 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9351 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9352 tree n_elts = NULL_TREE;
9353
9354 for (; elts0 && elts1;
9355 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9356 {
9357 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
9358 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
9359 }
9360
9361 return build_vector (rtype, nreverse (n_elts));
9362 }
9363 break;
9364
9365 case CODE_FOR_pdist_vis:
9366 arg0 = args[0];
9367 arg1 = args[1];
9368 arg2 = args[2];
9369 STRIP_NOPS (arg0);
9370 STRIP_NOPS (arg1);
9371 STRIP_NOPS (arg2);
9372
9373 if (TREE_CODE (arg0) == VECTOR_CST
9374 && TREE_CODE (arg1) == VECTOR_CST
9375 && TREE_CODE (arg2) == INTEGER_CST)
9376 {
9377 int overflow = 0;
9378 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
9379 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
9380 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9381 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9382
9383 for (; elts0 && elts1;
9384 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9385 {
9386 unsigned HOST_WIDE_INT
9387 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9388 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9389 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
9390 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
9391
9392 unsigned HOST_WIDE_INT l;
9393 HOST_WIDE_INT h;
9394
9395 overflow |= neg_double (low1, high1, &l, &h);
9396 overflow |= add_double (low0, high0, l, h, &l, &h);
9397 if (h < 0)
9398 overflow |= neg_double (l, h, &l, &h);
9399
9400 overflow |= add_double (low, high, l, h, &low, &high);
9401 }
9402
9403 gcc_assert (overflow == 0);
9404
9405 return build_int_cst_wide (rtype, low, high);
9406 }
9407
9408 default:
9409 break;
9410 }
9411
9412 return NULL_TREE;
9413 }
9414 \f
9415 /* ??? This duplicates information provided to the compiler by the
9416 ??? scheduler description. Some day, teach genautomata to output
9417 ??? the latencies and then CSE will just use that. */
9418
9419 static bool
9420 sparc_rtx_costs (rtx x, int code, int outer_code, int *total,
9421 bool speed ATTRIBUTE_UNUSED)
9422 {
9423 enum machine_mode mode = GET_MODE (x);
9424 bool float_mode_p = FLOAT_MODE_P (mode);
9425
9426 switch (code)
9427 {
9428 case CONST_INT:
9429 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
9430 {
9431 *total = 0;
9432 return true;
9433 }
9434 /* FALLTHRU */
9435
9436 case HIGH:
9437 *total = 2;
9438 return true;
9439
9440 case CONST:
9441 case LABEL_REF:
9442 case SYMBOL_REF:
9443 *total = 4;
9444 return true;
9445
9446 case CONST_DOUBLE:
9447 if (GET_MODE (x) == VOIDmode
9448 && ((CONST_DOUBLE_HIGH (x) == 0
9449 && CONST_DOUBLE_LOW (x) < 0x1000)
9450 || (CONST_DOUBLE_HIGH (x) == -1
9451 && CONST_DOUBLE_LOW (x) < 0
9452 && CONST_DOUBLE_LOW (x) >= -0x1000)))
9453 *total = 0;
9454 else
9455 *total = 8;
9456 return true;
9457
9458 case MEM:
9459 /* If outer-code was a sign or zero extension, a cost
9460 of COSTS_N_INSNS (1) was already added in. This is
9461 why we are subtracting it back out. */
9462 if (outer_code == ZERO_EXTEND)
9463 {
9464 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
9465 }
9466 else if (outer_code == SIGN_EXTEND)
9467 {
9468 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
9469 }
9470 else if (float_mode_p)
9471 {
9472 *total = sparc_costs->float_load;
9473 }
9474 else
9475 {
9476 *total = sparc_costs->int_load;
9477 }
9478
9479 return true;
9480
9481 case PLUS:
9482 case MINUS:
9483 if (float_mode_p)
9484 *total = sparc_costs->float_plusminus;
9485 else
9486 *total = COSTS_N_INSNS (1);
9487 return false;
9488
9489 case MULT:
9490 if (float_mode_p)
9491 *total = sparc_costs->float_mul;
9492 else if (! TARGET_HARD_MUL)
9493 *total = COSTS_N_INSNS (25);
9494 else
9495 {
9496 int bit_cost;
9497
9498 bit_cost = 0;
9499 if (sparc_costs->int_mul_bit_factor)
9500 {
9501 int nbits;
9502
9503 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
9504 {
9505 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
9506 for (nbits = 0; value != 0; value &= value - 1)
9507 nbits++;
9508 }
9509 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
9510 && GET_MODE (XEXP (x, 1)) == VOIDmode)
9511 {
9512 rtx x1 = XEXP (x, 1);
9513 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
9514 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
9515
9516 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
9517 nbits++;
9518 for (; value2 != 0; value2 &= value2 - 1)
9519 nbits++;
9520 }
9521 else
9522 nbits = 7;
9523
9524 if (nbits < 3)
9525 nbits = 3;
9526 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
9527 bit_cost = COSTS_N_INSNS (bit_cost);
9528 }
9529
9530 if (mode == DImode)
9531 *total = sparc_costs->int_mulX + bit_cost;
9532 else
9533 *total = sparc_costs->int_mul + bit_cost;
9534 }
9535 return false;
9536
9537 case ASHIFT:
9538 case ASHIFTRT:
9539 case LSHIFTRT:
9540 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
9541 return false;
9542
9543 case DIV:
9544 case UDIV:
9545 case MOD:
9546 case UMOD:
9547 if (float_mode_p)
9548 {
9549 if (mode == DFmode)
9550 *total = sparc_costs->float_div_df;
9551 else
9552 *total = sparc_costs->float_div_sf;
9553 }
9554 else
9555 {
9556 if (mode == DImode)
9557 *total = sparc_costs->int_divX;
9558 else
9559 *total = sparc_costs->int_div;
9560 }
9561 return false;
9562
9563 case NEG:
9564 if (! float_mode_p)
9565 {
9566 *total = COSTS_N_INSNS (1);
9567 return false;
9568 }
9569 /* FALLTHRU */
9570
9571 case ABS:
9572 case FLOAT:
9573 case UNSIGNED_FLOAT:
9574 case FIX:
9575 case UNSIGNED_FIX:
9576 case FLOAT_EXTEND:
9577 case FLOAT_TRUNCATE:
9578 *total = sparc_costs->float_move;
9579 return false;
9580
9581 case SQRT:
9582 if (mode == DFmode)
9583 *total = sparc_costs->float_sqrt_df;
9584 else
9585 *total = sparc_costs->float_sqrt_sf;
9586 return false;
9587
9588 case COMPARE:
9589 if (float_mode_p)
9590 *total = sparc_costs->float_cmp;
9591 else
9592 *total = COSTS_N_INSNS (1);
9593 return false;
9594
9595 case IF_THEN_ELSE:
9596 if (float_mode_p)
9597 *total = sparc_costs->float_cmove;
9598 else
9599 *total = sparc_costs->int_cmove;
9600 return false;
9601
9602 case IOR:
9603 /* Handle the NAND vector patterns. */
9604 if (sparc_vector_mode_supported_p (GET_MODE (x))
9605 && GET_CODE (XEXP (x, 0)) == NOT
9606 && GET_CODE (XEXP (x, 1)) == NOT)
9607 {
9608 *total = COSTS_N_INSNS (1);
9609 return true;
9610 }
9611 else
9612 return false;
9613
9614 default:
9615 return false;
9616 }
9617 }
9618
9619 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
9620
9621 static inline bool
9622 general_or_i64_p (reg_class_t rclass)
9623 {
9624 return (rclass == GENERAL_REGS || rclass == I64_REGS);
9625 }
9626
9627 /* Implement TARGET_REGISTER_MOVE_COST. */
9628
9629 static int
9630 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9631 reg_class_t from, reg_class_t to)
9632 {
9633 if ((FP_REG_CLASS_P (from) && general_or_i64_p (to))
9634 || (general_or_i64_p (from) && FP_REG_CLASS_P (to))
9635 || from == FPCC_REGS
9636 || to == FPCC_REGS)
9637 {
9638 if (sparc_cpu == PROCESSOR_ULTRASPARC
9639 || sparc_cpu == PROCESSOR_ULTRASPARC3
9640 || sparc_cpu == PROCESSOR_NIAGARA
9641 || sparc_cpu == PROCESSOR_NIAGARA2)
9642 return 12;
9643
9644 return 6;
9645 }
9646
9647 return 2;
9648 }
9649
9650 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
9651 This is achieved by means of a manual dynamic stack space allocation in
9652 the current frame. We make the assumption that SEQ doesn't contain any
9653 function calls, with the possible exception of calls to the GOT helper. */
9654
9655 static void
9656 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
9657 {
9658 /* We must preserve the lowest 16 words for the register save area. */
9659 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
9660 /* We really need only 2 words of fresh stack space. */
9661 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
9662
9663 rtx slot
9664 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
9665 SPARC_STACK_BIAS + offset));
9666
9667 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
9668 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
9669 if (reg2)
9670 emit_insn (gen_rtx_SET (VOIDmode,
9671 adjust_address (slot, word_mode, UNITS_PER_WORD),
9672 reg2));
9673 emit_insn (seq);
9674 if (reg2)
9675 emit_insn (gen_rtx_SET (VOIDmode,
9676 reg2,
9677 adjust_address (slot, word_mode, UNITS_PER_WORD)));
9678 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
9679 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
9680 }
9681
9682 /* Output the assembler code for a thunk function. THUNK_DECL is the
9683 declaration for the thunk function itself, FUNCTION is the decl for
9684 the target function. DELTA is an immediate constant offset to be
9685 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9686 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9687
9688 static void
9689 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9690 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9691 tree function)
9692 {
9693 rtx this_rtx, insn, funexp;
9694 unsigned int int_arg_first;
9695
9696 reload_completed = 1;
9697 epilogue_completed = 1;
9698
9699 emit_note (NOTE_INSN_PROLOGUE_END);
9700
9701 if (TARGET_FLAT)
9702 {
9703 sparc_leaf_function_p = 1;
9704
9705 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
9706 }
9707 else if (flag_delayed_branch)
9708 {
9709 /* We will emit a regular sibcall below, so we need to instruct
9710 output_sibcall that we are in a leaf function. */
9711 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
9712
9713 /* This will cause final.c to invoke leaf_renumber_regs so we
9714 must behave as if we were in a not-yet-leafified function. */
9715 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
9716 }
9717 else
9718 {
9719 /* We will emit the sibcall manually below, so we will need to
9720 manually spill non-leaf registers. */
9721 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
9722
9723 /* We really are in a leaf function. */
9724 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
9725 }
9726
9727 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9728 returns a structure, the structure return pointer is there instead. */
9729 if (TARGET_ARCH64
9730 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9731 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
9732 else
9733 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
9734
9735 /* Add DELTA. When possible use a plain add, otherwise load it into
9736 a register first. */
9737 if (delta)
9738 {
9739 rtx delta_rtx = GEN_INT (delta);
9740
9741 if (! SPARC_SIMM13_P (delta))
9742 {
9743 rtx scratch = gen_rtx_REG (Pmode, 1);
9744 emit_move_insn (scratch, delta_rtx);
9745 delta_rtx = scratch;
9746 }
9747
9748 /* THIS_RTX += DELTA. */
9749 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
9750 }
9751
9752 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
9753 if (vcall_offset)
9754 {
9755 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
9756 rtx scratch = gen_rtx_REG (Pmode, 1);
9757
9758 gcc_assert (vcall_offset < 0);
9759
9760 /* SCRATCH = *THIS_RTX. */
9761 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
9762
9763 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9764 may not have any available scratch register at this point. */
9765 if (SPARC_SIMM13_P (vcall_offset))
9766 ;
9767 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9768 else if (! fixed_regs[5]
9769 /* The below sequence is made up of at least 2 insns,
9770 while the default method may need only one. */
9771 && vcall_offset < -8192)
9772 {
9773 rtx scratch2 = gen_rtx_REG (Pmode, 5);
9774 emit_move_insn (scratch2, vcall_offset_rtx);
9775 vcall_offset_rtx = scratch2;
9776 }
9777 else
9778 {
9779 rtx increment = GEN_INT (-4096);
9780
9781 /* VCALL_OFFSET is a negative number whose typical range can be
9782 estimated as -32768..0 in 32-bit mode. In almost all cases
9783 it is therefore cheaper to emit multiple add insns than
9784 spilling and loading the constant into a register (at least
9785 6 insns). */
9786 while (! SPARC_SIMM13_P (vcall_offset))
9787 {
9788 emit_insn (gen_add2_insn (scratch, increment));
9789 vcall_offset += 4096;
9790 }
9791 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
9792 }
9793
9794 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
9795 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
9796 gen_rtx_PLUS (Pmode,
9797 scratch,
9798 vcall_offset_rtx)));
9799
9800 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
9801 emit_insn (gen_add2_insn (this_rtx, scratch));
9802 }
9803
9804 /* Generate a tail call to the target function. */
9805 if (! TREE_USED (function))
9806 {
9807 assemble_external (function);
9808 TREE_USED (function) = 1;
9809 }
9810 funexp = XEXP (DECL_RTL (function), 0);
9811
9812 if (flag_delayed_branch)
9813 {
9814 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9815 insn = emit_call_insn (gen_sibcall (funexp));
9816 SIBLING_CALL_P (insn) = 1;
9817 }
9818 else
9819 {
9820 /* The hoops we have to jump through in order to generate a sibcall
9821 without using delay slots... */
9822 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
9823
9824 if (flag_pic)
9825 {
9826 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
9827 start_sequence ();
9828 load_got_register (); /* clobbers %o7 */
9829 scratch = sparc_legitimize_pic_address (funexp, scratch);
9830 seq = get_insns ();
9831 end_sequence ();
9832 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
9833 }
9834 else if (TARGET_ARCH32)
9835 {
9836 emit_insn (gen_rtx_SET (VOIDmode,
9837 scratch,
9838 gen_rtx_HIGH (SImode, funexp)));
9839 emit_insn (gen_rtx_SET (VOIDmode,
9840 scratch,
9841 gen_rtx_LO_SUM (SImode, scratch, funexp)));
9842 }
9843 else /* TARGET_ARCH64 */
9844 {
9845 switch (sparc_cmodel)
9846 {
9847 case CM_MEDLOW:
9848 case CM_MEDMID:
9849 /* The destination can serve as a temporary. */
9850 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
9851 break;
9852
9853 case CM_MEDANY:
9854 case CM_EMBMEDANY:
9855 /* The destination cannot serve as a temporary. */
9856 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
9857 start_sequence ();
9858 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
9859 seq = get_insns ();
9860 end_sequence ();
9861 emit_and_preserve (seq, spill_reg, 0);
9862 break;
9863
9864 default:
9865 gcc_unreachable ();
9866 }
9867 }
9868
9869 emit_jump_insn (gen_indirect_jump (scratch));
9870 }
9871
9872 emit_barrier ();
9873
9874 /* Run just enough of rest_of_compilation to get the insns emitted.
9875 There's not really enough bulk here to make other passes such as
9876 instruction scheduling worth while. Note that use_thunk calls
9877 assemble_start_function and assemble_end_function. */
9878 insn = get_insns ();
9879 insn_locators_alloc ();
9880 shorten_branches (insn);
9881 final_start_function (insn, file, 1);
9882 final (insn, file, 1);
9883 final_end_function ();
9884
9885 reload_completed = 0;
9886 epilogue_completed = 0;
9887 }
9888
9889 /* Return true if sparc_output_mi_thunk would be able to output the
9890 assembler code for the thunk function specified by the arguments
9891 it is passed, and false otherwise. */
9892 static bool
9893 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
9894 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
9895 HOST_WIDE_INT vcall_offset,
9896 const_tree function ATTRIBUTE_UNUSED)
9897 {
9898 /* Bound the loop used in the default method above. */
9899 return (vcall_offset >= -32768 || ! fixed_regs[5]);
9900 }
9901
9902 /* How to allocate a 'struct machine_function'. */
9903
9904 static struct machine_function *
9905 sparc_init_machine_status (void)
9906 {
9907 return ggc_alloc_cleared_machine_function ();
9908 }
9909
9910 /* Locate some local-dynamic symbol still in use by this function
9911 so that we can print its name in local-dynamic base patterns. */
9912
9913 static const char *
9914 get_some_local_dynamic_name (void)
9915 {
9916 rtx insn;
9917
9918 if (cfun->machine->some_ld_name)
9919 return cfun->machine->some_ld_name;
9920
9921 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9922 if (INSN_P (insn)
9923 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9924 return cfun->machine->some_ld_name;
9925
9926 gcc_unreachable ();
9927 }
9928
9929 static int
9930 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9931 {
9932 rtx x = *px;
9933
9934 if (x
9935 && GET_CODE (x) == SYMBOL_REF
9936 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9937 {
9938 cfun->machine->some_ld_name = XSTR (x, 0);
9939 return 1;
9940 }
9941
9942 return 0;
9943 }
9944
9945 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9946 We need to emit DTP-relative relocations. */
9947
9948 static void
9949 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9950 {
9951 switch (size)
9952 {
9953 case 4:
9954 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9955 break;
9956 case 8:
9957 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9958 break;
9959 default:
9960 gcc_unreachable ();
9961 }
9962 output_addr_const (file, x);
9963 fputs (")", file);
9964 }
9965
9966 /* Do whatever processing is required at the end of a file. */
9967
9968 static void
9969 sparc_file_end (void)
9970 {
9971 /* If we need to emit the special GOT helper function, do so now. */
9972 if (got_helper_rtx)
9973 {
9974 const char *name = XSTR (got_helper_rtx, 0);
9975 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
9976 #ifdef DWARF2_UNWIND_INFO
9977 bool do_cfi;
9978 #endif
9979
9980 if (USE_HIDDEN_LINKONCE)
9981 {
9982 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
9983 get_identifier (name),
9984 build_function_type_list (void_type_node,
9985 NULL_TREE));
9986 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
9987 NULL_TREE, void_type_node);
9988 TREE_STATIC (decl) = 1;
9989 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
9990 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
9991 DECL_VISIBILITY_SPECIFIED (decl) = 1;
9992 resolve_unique_section (decl, 0, flag_function_sections);
9993 allocate_struct_function (decl, true);
9994 cfun->is_thunk = 1;
9995 current_function_decl = decl;
9996 init_varasm_status ();
9997 assemble_start_function (decl, name);
9998 }
9999 else
10000 {
10001 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
10002 switch_to_section (text_section);
10003 if (align > 0)
10004 ASM_OUTPUT_ALIGN (asm_out_file, align);
10005 ASM_OUTPUT_LABEL (asm_out_file, name);
10006 }
10007
10008 #ifdef DWARF2_UNWIND_INFO
10009 do_cfi = dwarf2out_do_cfi_asm ();
10010 if (do_cfi)
10011 fprintf (asm_out_file, "\t.cfi_startproc\n");
10012 #endif
10013 if (flag_delayed_branch)
10014 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10015 reg_name, reg_name);
10016 else
10017 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10018 reg_name, reg_name);
10019 #ifdef DWARF2_UNWIND_INFO
10020 if (do_cfi)
10021 fprintf (asm_out_file, "\t.cfi_endproc\n");
10022 #endif
10023 }
10024
10025 if (NEED_INDICATE_EXEC_STACK)
10026 file_end_indicate_exec_stack ();
10027 }
10028
10029 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10030 /* Implement TARGET_MANGLE_TYPE. */
10031
10032 static const char *
10033 sparc_mangle_type (const_tree type)
10034 {
10035 if (!TARGET_64BIT
10036 && TYPE_MAIN_VARIANT (type) == long_double_type_node
10037 && TARGET_LONG_DOUBLE_128)
10038 return "g";
10039
10040 /* For all other types, use normal C++ mangling. */
10041 return NULL;
10042 }
10043 #endif
10044
10045 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10046 compare and swap on the word containing the byte or half-word. */
10047
10048 void
10049 sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
10050 {
10051 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
10052 rtx addr = gen_reg_rtx (Pmode);
10053 rtx off = gen_reg_rtx (SImode);
10054 rtx oldv = gen_reg_rtx (SImode);
10055 rtx newv = gen_reg_rtx (SImode);
10056 rtx oldvalue = gen_reg_rtx (SImode);
10057 rtx newvalue = gen_reg_rtx (SImode);
10058 rtx res = gen_reg_rtx (SImode);
10059 rtx resv = gen_reg_rtx (SImode);
10060 rtx memsi, val, mask, end_label, loop_label, cc;
10061
10062 emit_insn (gen_rtx_SET (VOIDmode, addr,
10063 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
10064
10065 if (Pmode != SImode)
10066 addr1 = gen_lowpart (SImode, addr1);
10067 emit_insn (gen_rtx_SET (VOIDmode, off,
10068 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
10069
10070 memsi = gen_rtx_MEM (SImode, addr);
10071 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
10072 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
10073
10074 val = force_reg (SImode, memsi);
10075
10076 emit_insn (gen_rtx_SET (VOIDmode, off,
10077 gen_rtx_XOR (SImode, off,
10078 GEN_INT (GET_MODE (mem) == QImode
10079 ? 3 : 2))));
10080
10081 emit_insn (gen_rtx_SET (VOIDmode, off,
10082 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
10083
10084 if (GET_MODE (mem) == QImode)
10085 mask = force_reg (SImode, GEN_INT (0xff));
10086 else
10087 mask = force_reg (SImode, GEN_INT (0xffff));
10088
10089 emit_insn (gen_rtx_SET (VOIDmode, mask,
10090 gen_rtx_ASHIFT (SImode, mask, off)));
10091
10092 emit_insn (gen_rtx_SET (VOIDmode, val,
10093 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10094 val)));
10095
10096 oldval = gen_lowpart (SImode, oldval);
10097 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10098 gen_rtx_ASHIFT (SImode, oldval, off)));
10099
10100 newval = gen_lowpart_common (SImode, newval);
10101 emit_insn (gen_rtx_SET (VOIDmode, newv,
10102 gen_rtx_ASHIFT (SImode, newval, off)));
10103
10104 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10105 gen_rtx_AND (SImode, oldv, mask)));
10106
10107 emit_insn (gen_rtx_SET (VOIDmode, newv,
10108 gen_rtx_AND (SImode, newv, mask)));
10109
10110 end_label = gen_label_rtx ();
10111 loop_label = gen_label_rtx ();
10112 emit_label (loop_label);
10113
10114 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
10115 gen_rtx_IOR (SImode, oldv, val)));
10116
10117 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
10118 gen_rtx_IOR (SImode, newv, val)));
10119
10120 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue));
10121
10122 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
10123
10124 emit_insn (gen_rtx_SET (VOIDmode, resv,
10125 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10126 res)));
10127
10128 cc = gen_compare_reg_1 (NE, resv, val);
10129 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
10130
10131 /* Use cbranchcc4 to separate the compare and branch! */
10132 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
10133 cc, const0_rtx, loop_label));
10134
10135 emit_label (end_label);
10136
10137 emit_insn (gen_rtx_SET (VOIDmode, res,
10138 gen_rtx_AND (SImode, res, mask)));
10139
10140 emit_insn (gen_rtx_SET (VOIDmode, res,
10141 gen_rtx_LSHIFTRT (SImode, res, off)));
10142
10143 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
10144 }
10145
10146 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10147
10148 static bool
10149 sparc_frame_pointer_required (void)
10150 {
10151 /* If the stack pointer is dynamically modified in the function, it cannot
10152 serve as the frame pointer. */
10153 if (cfun->calls_alloca)
10154 return true;
10155
10156 /* If the function receives nonlocal gotos, it needs to save the frame
10157 pointer in the nonlocal_goto_save_area object. */
10158 if (cfun->has_nonlocal_label)
10159 return true;
10160
10161 /* In flat mode, that's it. */
10162 if (TARGET_FLAT)
10163 return false;
10164
10165 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10166 return !(current_function_is_leaf && only_leaf_regs_used ());
10167 }
10168
10169 /* The way this is structured, we can't eliminate SFP in favor of SP
10170 if the frame pointer is required: we want to use the SFP->HFP elimination
10171 in that case. But the test in update_eliminables doesn't know we are
10172 assuming below that we only do the former elimination. */
10173
10174 static bool
10175 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10176 {
10177 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
10178 }
10179
10180 /* Return the hard frame pointer directly to bypass the stack bias. */
10181
10182 static rtx
10183 sparc_builtin_setjmp_frame_value (void)
10184 {
10185 return hard_frame_pointer_rtx;
10186 }
10187
10188 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10189 they won't be allocated. */
10190
10191 static void
10192 sparc_conditional_register_usage (void)
10193 {
10194 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
10195 {
10196 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10197 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10198 }
10199 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10200 /* then honor it. */
10201 if (TARGET_ARCH32 && fixed_regs[5])
10202 fixed_regs[5] = 1;
10203 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
10204 fixed_regs[5] = 0;
10205 if (! TARGET_V9)
10206 {
10207 int regno;
10208 for (regno = SPARC_FIRST_V9_FP_REG;
10209 regno <= SPARC_LAST_V9_FP_REG;
10210 regno++)
10211 fixed_regs[regno] = 1;
10212 /* %fcc0 is used by v8 and v9. */
10213 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
10214 regno <= SPARC_LAST_V9_FCC_REG;
10215 regno++)
10216 fixed_regs[regno] = 1;
10217 }
10218 if (! TARGET_FPU)
10219 {
10220 int regno;
10221 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
10222 fixed_regs[regno] = 1;
10223 }
10224 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10225 /* then honor it. Likewise with g3 and g4. */
10226 if (fixed_regs[2] == 2)
10227 fixed_regs[2] = ! TARGET_APP_REGS;
10228 if (fixed_regs[3] == 2)
10229 fixed_regs[3] = ! TARGET_APP_REGS;
10230 if (TARGET_ARCH32 && fixed_regs[4] == 2)
10231 fixed_regs[4] = ! TARGET_APP_REGS;
10232 else if (TARGET_CM_EMBMEDANY)
10233 fixed_regs[4] = 1;
10234 else if (fixed_regs[4] == 2)
10235 fixed_regs[4] = 0;
10236 if (TARGET_FLAT)
10237 {
10238 int regno;
10239 /* Disable leaf functions. */
10240 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
10241 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
10242 leaf_reg_remap [regno] = regno;
10243 }
10244 }
10245
10246 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10247
10248 - We can't load constants into FP registers.
10249 - We can't load FP constants into integer registers when soft-float,
10250 because there is no soft-float pattern with a r/F constraint.
10251 - We can't load FP constants into integer registers for TFmode unless
10252 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10253 - Try and reload integer constants (symbolic or otherwise) back into
10254 registers directly, rather than having them dumped to memory. */
10255
10256 static reg_class_t
10257 sparc_preferred_reload_class (rtx x, reg_class_t rclass)
10258 {
10259 if (CONSTANT_P (x))
10260 {
10261 if (FP_REG_CLASS_P (rclass)
10262 || rclass == GENERAL_OR_FP_REGS
10263 || rclass == GENERAL_OR_EXTRA_FP_REGS
10264 || (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT && ! TARGET_FPU)
10265 || (GET_MODE (x) == TFmode && ! const_zero_operand (x, TFmode)))
10266 return NO_REGS;
10267
10268 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10269 return GENERAL_REGS;
10270 }
10271
10272 return rclass;
10273 }
10274
10275 #include "gt-sparc.h"