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[gcc.git] / gcc / config / sparc / sparc.c
1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "tree.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
37 #include "output.h"
38 #include "insn-attr.h"
39 #include "flags.h"
40 #include "function.h"
41 #include "expr.h"
42 #include "optabs.h"
43 #include "recog.h"
44 #include "toplev.h"
45 #include "ggc.h"
46 #include "tm_p.h"
47 #include "debug.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
51 #include "tree-gimple.h"
52 #include "langhooks.h"
53
54 /* Processor costs */
55 static const
56 struct processor_costs cypress_costs = {
57 COSTS_N_INSNS (2), /* int load */
58 COSTS_N_INSNS (2), /* int signed load */
59 COSTS_N_INSNS (2), /* int zeroed load */
60 COSTS_N_INSNS (2), /* float load */
61 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
62 COSTS_N_INSNS (5), /* fadd, fsub */
63 COSTS_N_INSNS (1), /* fcmp */
64 COSTS_N_INSNS (1), /* fmov, fmovr */
65 COSTS_N_INSNS (7), /* fmul */
66 COSTS_N_INSNS (37), /* fdivs */
67 COSTS_N_INSNS (37), /* fdivd */
68 COSTS_N_INSNS (63), /* fsqrts */
69 COSTS_N_INSNS (63), /* fsqrtd */
70 COSTS_N_INSNS (1), /* imul */
71 COSTS_N_INSNS (1), /* imulX */
72 0, /* imul bit factor */
73 COSTS_N_INSNS (1), /* idiv */
74 COSTS_N_INSNS (1), /* idivX */
75 COSTS_N_INSNS (1), /* movcc/movr */
76 0, /* shift penalty */
77 };
78
79 static const
80 struct processor_costs supersparc_costs = {
81 COSTS_N_INSNS (1), /* int load */
82 COSTS_N_INSNS (1), /* int signed load */
83 COSTS_N_INSNS (1), /* int zeroed load */
84 COSTS_N_INSNS (0), /* float load */
85 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
86 COSTS_N_INSNS (3), /* fadd, fsub */
87 COSTS_N_INSNS (3), /* fcmp */
88 COSTS_N_INSNS (1), /* fmov, fmovr */
89 COSTS_N_INSNS (3), /* fmul */
90 COSTS_N_INSNS (6), /* fdivs */
91 COSTS_N_INSNS (9), /* fdivd */
92 COSTS_N_INSNS (12), /* fsqrts */
93 COSTS_N_INSNS (12), /* fsqrtd */
94 COSTS_N_INSNS (4), /* imul */
95 COSTS_N_INSNS (4), /* imulX */
96 0, /* imul bit factor */
97 COSTS_N_INSNS (4), /* idiv */
98 COSTS_N_INSNS (4), /* idivX */
99 COSTS_N_INSNS (1), /* movcc/movr */
100 1, /* shift penalty */
101 };
102
103 static const
104 struct processor_costs hypersparc_costs = {
105 COSTS_N_INSNS (1), /* int load */
106 COSTS_N_INSNS (1), /* int signed load */
107 COSTS_N_INSNS (1), /* int zeroed load */
108 COSTS_N_INSNS (1), /* float load */
109 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
110 COSTS_N_INSNS (1), /* fadd, fsub */
111 COSTS_N_INSNS (1), /* fcmp */
112 COSTS_N_INSNS (1), /* fmov, fmovr */
113 COSTS_N_INSNS (1), /* fmul */
114 COSTS_N_INSNS (8), /* fdivs */
115 COSTS_N_INSNS (12), /* fdivd */
116 COSTS_N_INSNS (17), /* fsqrts */
117 COSTS_N_INSNS (17), /* fsqrtd */
118 COSTS_N_INSNS (17), /* imul */
119 COSTS_N_INSNS (17), /* imulX */
120 0, /* imul bit factor */
121 COSTS_N_INSNS (17), /* idiv */
122 COSTS_N_INSNS (17), /* idivX */
123 COSTS_N_INSNS (1), /* movcc/movr */
124 0, /* shift penalty */
125 };
126
127 static const
128 struct processor_costs sparclet_costs = {
129 COSTS_N_INSNS (3), /* int load */
130 COSTS_N_INSNS (3), /* int signed load */
131 COSTS_N_INSNS (1), /* int zeroed load */
132 COSTS_N_INSNS (1), /* float load */
133 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
134 COSTS_N_INSNS (1), /* fadd, fsub */
135 COSTS_N_INSNS (1), /* fcmp */
136 COSTS_N_INSNS (1), /* fmov, fmovr */
137 COSTS_N_INSNS (1), /* fmul */
138 COSTS_N_INSNS (1), /* fdivs */
139 COSTS_N_INSNS (1), /* fdivd */
140 COSTS_N_INSNS (1), /* fsqrts */
141 COSTS_N_INSNS (1), /* fsqrtd */
142 COSTS_N_INSNS (5), /* imul */
143 COSTS_N_INSNS (5), /* imulX */
144 0, /* imul bit factor */
145 COSTS_N_INSNS (5), /* idiv */
146 COSTS_N_INSNS (5), /* idivX */
147 COSTS_N_INSNS (1), /* movcc/movr */
148 0, /* shift penalty */
149 };
150
151 static const
152 struct processor_costs ultrasparc_costs = {
153 COSTS_N_INSNS (2), /* int load */
154 COSTS_N_INSNS (3), /* int signed load */
155 COSTS_N_INSNS (2), /* int zeroed load */
156 COSTS_N_INSNS (2), /* float load */
157 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
158 COSTS_N_INSNS (4), /* fadd, fsub */
159 COSTS_N_INSNS (1), /* fcmp */
160 COSTS_N_INSNS (2), /* fmov, fmovr */
161 COSTS_N_INSNS (4), /* fmul */
162 COSTS_N_INSNS (13), /* fdivs */
163 COSTS_N_INSNS (23), /* fdivd */
164 COSTS_N_INSNS (13), /* fsqrts */
165 COSTS_N_INSNS (23), /* fsqrtd */
166 COSTS_N_INSNS (4), /* imul */
167 COSTS_N_INSNS (4), /* imulX */
168 2, /* imul bit factor */
169 COSTS_N_INSNS (37), /* idiv */
170 COSTS_N_INSNS (68), /* idivX */
171 COSTS_N_INSNS (2), /* movcc/movr */
172 2, /* shift penalty */
173 };
174
175 static const
176 struct processor_costs ultrasparc3_costs = {
177 COSTS_N_INSNS (2), /* int load */
178 COSTS_N_INSNS (3), /* int signed load */
179 COSTS_N_INSNS (3), /* int zeroed load */
180 COSTS_N_INSNS (2), /* float load */
181 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
182 COSTS_N_INSNS (4), /* fadd, fsub */
183 COSTS_N_INSNS (5), /* fcmp */
184 COSTS_N_INSNS (3), /* fmov, fmovr */
185 COSTS_N_INSNS (4), /* fmul */
186 COSTS_N_INSNS (17), /* fdivs */
187 COSTS_N_INSNS (20), /* fdivd */
188 COSTS_N_INSNS (20), /* fsqrts */
189 COSTS_N_INSNS (29), /* fsqrtd */
190 COSTS_N_INSNS (6), /* imul */
191 COSTS_N_INSNS (6), /* imulX */
192 0, /* imul bit factor */
193 COSTS_N_INSNS (40), /* idiv */
194 COSTS_N_INSNS (71), /* idivX */
195 COSTS_N_INSNS (2), /* movcc/movr */
196 0, /* shift penalty */
197 };
198
199 const struct processor_costs *sparc_costs = &cypress_costs;
200
201 #ifdef HAVE_AS_RELAX_OPTION
202 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
203 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
204 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
205 somebody does not branch between the sethi and jmp. */
206 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
207 #else
208 #define LEAF_SIBCALL_SLOT_RESERVED_P \
209 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
210 #endif
211
212 /* Global variables for machine-dependent things. */
213
214 /* Size of frame. Need to know this to emit return insns from leaf procedures.
215 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
216 reload pass. This is important as the value is later used for scheduling
217 (to see what can go in a delay slot).
218 APPARENT_FSIZE is the size of the stack less the register save area and less
219 the outgoing argument area. It is used when saving call preserved regs. */
220 static HOST_WIDE_INT apparent_fsize;
221 static HOST_WIDE_INT actual_fsize;
222
223 /* Number of live general or floating point registers needed to be
224 saved (as 4-byte quantities). */
225 static int num_gfregs;
226
227 /* The alias set for prologue/epilogue register save/restore. */
228 static GTY(()) int sparc_sr_alias_set;
229
230 /* The alias set for the structure return value. */
231 static GTY(()) int struct_value_alias_set;
232
233 /* Save the operands last given to a compare for use when we
234 generate a scc or bcc insn. */
235 rtx sparc_compare_op0, sparc_compare_op1;
236
237 /* Vector to say how input registers are mapped to output registers.
238 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
239 eliminate it. You must use -fomit-frame-pointer to get that. */
240 char leaf_reg_remap[] =
241 { 0, 1, 2, 3, 4, 5, 6, 7,
242 -1, -1, -1, -1, -1, -1, 14, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1,
244 8, 9, 10, 11, 12, 13, -1, 15,
245
246 32, 33, 34, 35, 36, 37, 38, 39,
247 40, 41, 42, 43, 44, 45, 46, 47,
248 48, 49, 50, 51, 52, 53, 54, 55,
249 56, 57, 58, 59, 60, 61, 62, 63,
250 64, 65, 66, 67, 68, 69, 70, 71,
251 72, 73, 74, 75, 76, 77, 78, 79,
252 80, 81, 82, 83, 84, 85, 86, 87,
253 88, 89, 90, 91, 92, 93, 94, 95,
254 96, 97, 98, 99, 100};
255
256 /* Vector, indexed by hard register number, which contains 1
257 for a register that is allowable in a candidate for leaf
258 function treatment. */
259 char sparc_leaf_regs[] =
260 { 1, 1, 1, 1, 1, 1, 1, 1,
261 0, 0, 0, 0, 0, 0, 1, 0,
262 0, 0, 0, 0, 0, 0, 0, 0,
263 1, 1, 1, 1, 1, 1, 0, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1, 1, 1, 1,
268 1, 1, 1, 1, 1, 1, 1, 1,
269 1, 1, 1, 1, 1, 1, 1, 1,
270 1, 1, 1, 1, 1, 1, 1, 1,
271 1, 1, 1, 1, 1, 1, 1, 1,
272 1, 1, 1, 1, 1};
273
274 struct machine_function GTY(())
275 {
276 /* Some local-dynamic TLS symbol name. */
277 const char *some_ld_name;
278
279 /* True if the current function is leaf and uses only leaf regs,
280 so that the SPARC leaf function optimization can be applied.
281 Private version of current_function_uses_only_leaf_regs, see
282 sparc_expand_prologue for the rationale. */
283 int leaf_function_p;
284
285 /* True if the data calculated by sparc_expand_prologue are valid. */
286 bool prologue_data_valid_p;
287 };
288
289 #define sparc_leaf_function_p cfun->machine->leaf_function_p
290 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
291
292 /* Register we pretend to think the frame pointer is allocated to.
293 Normally, this is %fp, but if we are in a leaf procedure, this
294 is %sp+"something". We record "something" separately as it may
295 be too big for reg+constant addressing. */
296 static rtx frame_base_reg;
297 static HOST_WIDE_INT frame_base_offset;
298
299 /* 1 if the next opcode is to be specially indented. */
300 int sparc_indent_opcode = 0;
301
302 static bool sparc_handle_option (size_t, const char *, int);
303 static void sparc_init_modes (void);
304 static void scan_record_type (tree, int *, int *, int *);
305 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
306 tree, int, int, int *, int *);
307
308 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
309 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
310
311 static void sparc_output_addr_vec (rtx);
312 static void sparc_output_addr_diff_vec (rtx);
313 static void sparc_output_deferred_case_vectors (void);
314 static rtx sparc_builtin_saveregs (void);
315 static int epilogue_renumber (rtx *, int);
316 static bool sparc_assemble_integer (rtx, unsigned int, int);
317 static int set_extends (rtx);
318 static void emit_pic_helper (void);
319 static void load_pic_register (bool);
320 static int save_or_restore_regs (int, int, rtx, int, int);
321 static void emit_save_regs (void);
322 static void emit_restore_regs (void);
323 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
324 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
325 #ifdef OBJECT_FORMAT_ELF
326 static void sparc_elf_asm_named_section (const char *, unsigned int, tree);
327 #endif
328
329 static int sparc_adjust_cost (rtx, rtx, rtx, int);
330 static int sparc_issue_rate (void);
331 static void sparc_sched_init (FILE *, int, int);
332 static int sparc_use_sched_lookahead (void);
333
334 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
335 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
336 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
337 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
338 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
339
340 static bool sparc_function_ok_for_sibcall (tree, tree);
341 static void sparc_init_libfuncs (void);
342 static void sparc_init_builtins (void);
343 static void sparc_vis_init_builtins (void);
344 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
345 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
346 HOST_WIDE_INT, tree);
347 static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT,
348 HOST_WIDE_INT, tree);
349 static struct machine_function * sparc_init_machine_status (void);
350 static bool sparc_cannot_force_const_mem (rtx);
351 static rtx sparc_tls_get_addr (void);
352 static rtx sparc_tls_got (void);
353 static const char *get_some_local_dynamic_name (void);
354 static int get_some_local_dynamic_name_1 (rtx *, void *);
355 static bool sparc_rtx_costs (rtx, int, int, int *);
356 static bool sparc_promote_prototypes (tree);
357 static rtx sparc_struct_value_rtx (tree, int);
358 static bool sparc_return_in_memory (tree, tree);
359 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
360 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
361 static bool sparc_vector_mode_supported_p (enum machine_mode);
362 static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
363 enum machine_mode, tree, bool);
364 static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *,
365 enum machine_mode, tree, bool);
366 static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int);
367 static void sparc_file_end (void);
368 #ifdef SUBTARGET_ATTRIBUTE_TABLE
369 const struct attribute_spec sparc_attribute_table[];
370 #endif
371 \f
372 /* Option handling. */
373
374 /* Code model option as passed by user. */
375 const char *sparc_cmodel_string;
376
377 /* Parsed value. */
378 enum cmodel sparc_cmodel;
379
380 char sparc_hard_reg_printed[8];
381
382 struct sparc_cpu_select sparc_select[] =
383 {
384 /* switch name, tune arch */
385 { (char *)0, "default", 1, 1 },
386 { (char *)0, "-mcpu=", 1, 1 },
387 { (char *)0, "-mtune=", 1, 0 },
388 { 0, 0, 0, 0 }
389 };
390
391 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
392 enum processor_type sparc_cpu;
393
394 /* Whether\fan FPU option was specified. */
395 static bool fpu_option_set = false;
396
397 /* Initialize the GCC target structure. */
398
399 /* The sparc default is to use .half rather than .short for aligned
400 HI objects. Use .word instead of .long on non-ELF systems. */
401 #undef TARGET_ASM_ALIGNED_HI_OP
402 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
403 #ifndef OBJECT_FORMAT_ELF
404 #undef TARGET_ASM_ALIGNED_SI_OP
405 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
406 #endif
407
408 #undef TARGET_ASM_UNALIGNED_HI_OP
409 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
410 #undef TARGET_ASM_UNALIGNED_SI_OP
411 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
412 #undef TARGET_ASM_UNALIGNED_DI_OP
413 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
414
415 /* The target hook has to handle DI-mode values. */
416 #undef TARGET_ASM_INTEGER
417 #define TARGET_ASM_INTEGER sparc_assemble_integer
418
419 #undef TARGET_ASM_FUNCTION_PROLOGUE
420 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
421 #undef TARGET_ASM_FUNCTION_EPILOGUE
422 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
423
424 #undef TARGET_SCHED_ADJUST_COST
425 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
426 #undef TARGET_SCHED_ISSUE_RATE
427 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
428 #undef TARGET_SCHED_INIT
429 #define TARGET_SCHED_INIT sparc_sched_init
430 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
431 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
432
433 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
434 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
435
436 #undef TARGET_INIT_LIBFUNCS
437 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
438 #undef TARGET_INIT_BUILTINS
439 #define TARGET_INIT_BUILTINS sparc_init_builtins
440
441 #undef TARGET_EXPAND_BUILTIN
442 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
443
444 #ifdef HAVE_AS_TLS
445 #undef TARGET_HAVE_TLS
446 #define TARGET_HAVE_TLS true
447 #endif
448 #undef TARGET_CANNOT_FORCE_CONST_MEM
449 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
450
451 #undef TARGET_ASM_OUTPUT_MI_THUNK
452 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
453 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
454 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
455
456 #undef TARGET_RTX_COSTS
457 #define TARGET_RTX_COSTS sparc_rtx_costs
458 #undef TARGET_ADDRESS_COST
459 #define TARGET_ADDRESS_COST hook_int_rtx_0
460
461 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
462 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
463 test for this value. */
464 #undef TARGET_PROMOTE_FUNCTION_ARGS
465 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
466
467 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
468 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
469 test for this value. */
470 #undef TARGET_PROMOTE_FUNCTION_RETURN
471 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
472
473 #undef TARGET_PROMOTE_PROTOTYPES
474 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
475
476 #undef TARGET_STRUCT_VALUE_RTX
477 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
478 #undef TARGET_RETURN_IN_MEMORY
479 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
480 #undef TARGET_MUST_PASS_IN_STACK
481 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
482 #undef TARGET_PASS_BY_REFERENCE
483 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
484 #undef TARGET_ARG_PARTIAL_BYTES
485 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
486
487 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
488 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
489 #undef TARGET_STRICT_ARGUMENT_NAMING
490 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
491
492 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
493 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
494
495 #undef TARGET_VECTOR_MODE_SUPPORTED_P
496 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
497
498 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
499 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
500
501 #ifdef SUBTARGET_INSERT_ATTRIBUTES
502 #undef TARGET_INSERT_ATTRIBUTES
503 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
504 #endif
505
506 #ifdef SUBTARGET_ATTRIBUTE_TABLE
507 #undef TARGET_ATTRIBUTE_TABLE
508 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
509 #endif
510
511 #undef TARGET_RELAXED_ORDERING
512 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
513
514 #undef TARGET_DEFAULT_TARGET_FLAGS
515 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
516 #undef TARGET_HANDLE_OPTION
517 #define TARGET_HANDLE_OPTION sparc_handle_option
518
519 #undef TARGET_ASM_FILE_END
520 #define TARGET_ASM_FILE_END sparc_file_end
521
522 struct gcc_target targetm = TARGET_INITIALIZER;
523
524 /* Implement TARGET_HANDLE_OPTION. */
525
526 static bool
527 sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
528 {
529 switch (code)
530 {
531 case OPT_mfpu:
532 case OPT_mhard_float:
533 case OPT_msoft_float:
534 fpu_option_set = true;
535 break;
536
537 case OPT_mcpu_:
538 sparc_select[1].string = arg;
539 break;
540
541 case OPT_mtune_:
542 sparc_select[2].string = arg;
543 break;
544
545 case OPT_mcmodel_:
546 sparc_cmodel_string = arg;
547 break;
548 }
549
550 return true;
551 }
552
553 /* Validate and override various options, and do some machine dependent
554 initialization. */
555
556 void
557 sparc_override_options (void)
558 {
559 static struct code_model {
560 const char *const name;
561 const int value;
562 } const cmodels[] = {
563 { "32", CM_32 },
564 { "medlow", CM_MEDLOW },
565 { "medmid", CM_MEDMID },
566 { "medany", CM_MEDANY },
567 { "embmedany", CM_EMBMEDANY },
568 { 0, 0 }
569 };
570 const struct code_model *cmodel;
571 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
572 static struct cpu_default {
573 const int cpu;
574 const char *const name;
575 } const cpu_default[] = {
576 /* There must be one entry here for each TARGET_CPU value. */
577 { TARGET_CPU_sparc, "cypress" },
578 { TARGET_CPU_sparclet, "tsc701" },
579 { TARGET_CPU_sparclite, "f930" },
580 { TARGET_CPU_v8, "v8" },
581 { TARGET_CPU_hypersparc, "hypersparc" },
582 { TARGET_CPU_sparclite86x, "sparclite86x" },
583 { TARGET_CPU_supersparc, "supersparc" },
584 { TARGET_CPU_v9, "v9" },
585 { TARGET_CPU_ultrasparc, "ultrasparc" },
586 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
587 { 0, 0 }
588 };
589 const struct cpu_default *def;
590 /* Table of values for -m{cpu,tune}=. */
591 static struct cpu_table {
592 const char *const name;
593 const enum processor_type processor;
594 const int disable;
595 const int enable;
596 } const cpu_table[] = {
597 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
598 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
599 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
600 /* TI TMS390Z55 supersparc */
601 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
602 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
603 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
604 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
605 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
606 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
607 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
608 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
609 MASK_SPARCLITE },
610 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
611 /* TEMIC sparclet */
612 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
613 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
614 /* TI ultrasparc I, II, IIi */
615 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
616 /* Although insns using %y are deprecated, it is a clear win on current
617 ultrasparcs. */
618 |MASK_DEPRECATED_V8_INSNS},
619 /* TI ultrasparc III */
620 /* ??? Check if %y issue still holds true in ultra3. */
621 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
622 { 0, 0, 0, 0 }
623 };
624 const struct cpu_table *cpu;
625 const struct sparc_cpu_select *sel;
626 int fpu;
627
628 #ifndef SPARC_BI_ARCH
629 /* Check for unsupported architecture size. */
630 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
631 error ("%s is not supported by this configuration",
632 DEFAULT_ARCH32_P ? "-m64" : "-m32");
633 #endif
634
635 /* We force all 64bit archs to use 128 bit long double */
636 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
637 {
638 error ("-mlong-double-64 not allowed with -m64");
639 target_flags |= MASK_LONG_DOUBLE_128;
640 }
641
642 /* Code model selection. */
643 sparc_cmodel = SPARC_DEFAULT_CMODEL;
644
645 #ifdef SPARC_BI_ARCH
646 if (TARGET_ARCH32)
647 sparc_cmodel = CM_32;
648 #endif
649
650 if (sparc_cmodel_string != NULL)
651 {
652 if (TARGET_ARCH64)
653 {
654 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
655 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
656 break;
657 if (cmodel->name == NULL)
658 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
659 else
660 sparc_cmodel = cmodel->value;
661 }
662 else
663 error ("-mcmodel= is not supported on 32 bit systems");
664 }
665
666 fpu = TARGET_FPU; /* save current -mfpu status */
667
668 /* Set the default CPU. */
669 for (def = &cpu_default[0]; def->name; ++def)
670 if (def->cpu == TARGET_CPU_DEFAULT)
671 break;
672 gcc_assert (def->name);
673 sparc_select[0].string = def->name;
674
675 for (sel = &sparc_select[0]; sel->name; ++sel)
676 {
677 if (sel->string)
678 {
679 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
680 if (! strcmp (sel->string, cpu->name))
681 {
682 if (sel->set_tune_p)
683 sparc_cpu = cpu->processor;
684
685 if (sel->set_arch_p)
686 {
687 target_flags &= ~cpu->disable;
688 target_flags |= cpu->enable;
689 }
690 break;
691 }
692
693 if (! cpu->name)
694 error ("bad value (%s) for %s switch", sel->string, sel->name);
695 }
696 }
697
698 /* If -mfpu or -mno-fpu was explicitly used, don't override with
699 the processor default. */
700 if (fpu_option_set)
701 target_flags = (target_flags & ~MASK_FPU) | fpu;
702
703 /* Don't allow -mvis if FPU is disabled. */
704 if (! TARGET_FPU)
705 target_flags &= ~MASK_VIS;
706
707 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
708 are available.
709 -m64 also implies v9. */
710 if (TARGET_VIS || TARGET_ARCH64)
711 {
712 target_flags |= MASK_V9;
713 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
714 }
715
716 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
717 if (TARGET_V9 && TARGET_ARCH32)
718 target_flags |= MASK_DEPRECATED_V8_INSNS;
719
720 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
721 if (! TARGET_V9 || TARGET_ARCH64)
722 target_flags &= ~MASK_V8PLUS;
723
724 /* Don't use stack biasing in 32 bit mode. */
725 if (TARGET_ARCH32)
726 target_flags &= ~MASK_STACK_BIAS;
727
728 /* Supply a default value for align_functions. */
729 if (align_functions == 0
730 && (sparc_cpu == PROCESSOR_ULTRASPARC
731 || sparc_cpu == PROCESSOR_ULTRASPARC3))
732 align_functions = 32;
733
734 /* Validate PCC_STRUCT_RETURN. */
735 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
736 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
737
738 /* Only use .uaxword when compiling for a 64-bit target. */
739 if (!TARGET_ARCH64)
740 targetm.asm_out.unaligned_op.di = NULL;
741
742 /* Do various machine dependent initializations. */
743 sparc_init_modes ();
744
745 /* Acquire unique alias sets for our private stuff. */
746 sparc_sr_alias_set = new_alias_set ();
747 struct_value_alias_set = new_alias_set ();
748
749 /* Set up function hooks. */
750 init_machine_status = sparc_init_machine_status;
751
752 switch (sparc_cpu)
753 {
754 case PROCESSOR_V7:
755 case PROCESSOR_CYPRESS:
756 sparc_costs = &cypress_costs;
757 break;
758 case PROCESSOR_V8:
759 case PROCESSOR_SPARCLITE:
760 case PROCESSOR_SUPERSPARC:
761 sparc_costs = &supersparc_costs;
762 break;
763 case PROCESSOR_F930:
764 case PROCESSOR_F934:
765 case PROCESSOR_HYPERSPARC:
766 case PROCESSOR_SPARCLITE86X:
767 sparc_costs = &hypersparc_costs;
768 break;
769 case PROCESSOR_SPARCLET:
770 case PROCESSOR_TSC701:
771 sparc_costs = &sparclet_costs;
772 break;
773 case PROCESSOR_V9:
774 case PROCESSOR_ULTRASPARC:
775 sparc_costs = &ultrasparc_costs;
776 break;
777 case PROCESSOR_ULTRASPARC3:
778 sparc_costs = &ultrasparc3_costs;
779 break;
780 };
781 }
782 \f
783 #ifdef SUBTARGET_ATTRIBUTE_TABLE
784 /* Table of valid machine attributes. */
785 const struct attribute_spec sparc_attribute_table[] =
786 {
787 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
788 SUBTARGET_ATTRIBUTE_TABLE,
789 { NULL, 0, 0, false, false, false, NULL }
790 };
791 #endif
792 \f
793 /* Miscellaneous utilities. */
794
795 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
796 or branch on register contents instructions. */
797
798 int
799 v9_regcmp_p (enum rtx_code code)
800 {
801 return (code == EQ || code == NE || code == GE || code == LT
802 || code == LE || code == GT);
803 }
804
805 \f
806 /* Operand constraints. */
807
808 /* Nonzero if OP is a floating point constant which can
809 be loaded into an integer register using a single
810 sethi instruction. */
811
812 int
813 fp_sethi_p (rtx op)
814 {
815 if (GET_CODE (op) == CONST_DOUBLE)
816 {
817 REAL_VALUE_TYPE r;
818 long i;
819
820 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
821 if (REAL_VALUES_EQUAL (r, dconst0) &&
822 ! REAL_VALUE_MINUS_ZERO (r))
823 return 0;
824 REAL_VALUE_TO_TARGET_SINGLE (r, i);
825 if (SPARC_SETHI_P (i))
826 return 1;
827 }
828
829 return 0;
830 }
831
832 /* Nonzero if OP is a floating point constant which can
833 be loaded into an integer register using a single
834 mov instruction. */
835
836 int
837 fp_mov_p (rtx op)
838 {
839 if (GET_CODE (op) == CONST_DOUBLE)
840 {
841 REAL_VALUE_TYPE r;
842 long i;
843
844 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
845 if (REAL_VALUES_EQUAL (r, dconst0) &&
846 ! REAL_VALUE_MINUS_ZERO (r))
847 return 0;
848 REAL_VALUE_TO_TARGET_SINGLE (r, i);
849 if (SPARC_SIMM13_P (i))
850 return 1;
851 }
852
853 return 0;
854 }
855
856 /* Nonzero if OP is a floating point constant which can
857 be loaded into an integer register using a high/losum
858 instruction sequence. */
859
860 int
861 fp_high_losum_p (rtx op)
862 {
863 /* The constraints calling this should only be in
864 SFmode move insns, so any constant which cannot
865 be moved using a single insn will do. */
866 if (GET_CODE (op) == CONST_DOUBLE)
867 {
868 REAL_VALUE_TYPE r;
869 long i;
870
871 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
872 if (REAL_VALUES_EQUAL (r, dconst0) &&
873 ! REAL_VALUE_MINUS_ZERO (r))
874 return 0;
875 REAL_VALUE_TO_TARGET_SINGLE (r, i);
876 if (! SPARC_SETHI_P (i)
877 && ! SPARC_SIMM13_P (i))
878 return 1;
879 }
880
881 return 0;
882 }
883
884 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
885 otherwise return 0. */
886
887 int
888 tls_symbolic_operand (rtx op)
889 {
890 if (GET_CODE (op) != SYMBOL_REF)
891 return 0;
892 return SYMBOL_REF_TLS_MODEL (op);
893 }
894 \f
895 /* We know it can't be done in one insn when we get here,
896 the movsi expander guarantees this. */
897 void
898 sparc_emit_set_const32 (rtx op0, rtx op1)
899 {
900 enum machine_mode mode = GET_MODE (op0);
901 rtx temp;
902
903 if (reload_in_progress || reload_completed)
904 temp = op0;
905 else
906 temp = gen_reg_rtx (mode);
907
908 if (GET_CODE (op1) == CONST_INT)
909 {
910 gcc_assert (!small_int_operand (op1, mode)
911 && !const_high_operand (op1, mode));
912
913 /* Emit them as real moves instead of a HIGH/LO_SUM,
914 this way CSE can see everything and reuse intermediate
915 values if it wants. */
916 emit_insn (gen_rtx_SET (VOIDmode, temp,
917 GEN_INT (INTVAL (op1)
918 & ~(HOST_WIDE_INT)0x3ff)));
919
920 emit_insn (gen_rtx_SET (VOIDmode,
921 op0,
922 gen_rtx_IOR (mode, temp,
923 GEN_INT (INTVAL (op1) & 0x3ff))));
924 }
925 else
926 {
927 /* A symbol, emit in the traditional way. */
928 emit_insn (gen_rtx_SET (VOIDmode, temp,
929 gen_rtx_HIGH (mode, op1)));
930 emit_insn (gen_rtx_SET (VOIDmode,
931 op0, gen_rtx_LO_SUM (mode, temp, op1)));
932 }
933 }
934
935 \f
936 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
937 If TEMP is nonzero, we are forbidden to use any other scratch
938 registers. Otherwise, we are allowed to generate them as needed.
939
940 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
941 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
942 void
943 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
944 {
945 rtx temp1, temp2, temp3, temp4, temp5;
946 rtx ti_temp = 0;
947
948 if (temp && GET_MODE (temp) == TImode)
949 {
950 ti_temp = temp;
951 temp = gen_rtx_REG (DImode, REGNO (temp));
952 }
953
954 /* SPARC-V9 code-model support. */
955 switch (sparc_cmodel)
956 {
957 case CM_MEDLOW:
958 /* The range spanned by all instructions in the object is less
959 than 2^31 bytes (2GB) and the distance from any instruction
960 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
961 than 2^31 bytes (2GB).
962
963 The executable must be in the low 4TB of the virtual address
964 space.
965
966 sethi %hi(symbol), %temp1
967 or %temp1, %lo(symbol), %reg */
968 if (temp)
969 temp1 = temp; /* op0 is allowed. */
970 else
971 temp1 = gen_reg_rtx (DImode);
972
973 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
974 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
975 break;
976
977 case CM_MEDMID:
978 /* The range spanned by all instructions in the object is less
979 than 2^31 bytes (2GB) and the distance from any instruction
980 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
981 than 2^31 bytes (2GB).
982
983 The executable must be in the low 16TB of the virtual address
984 space.
985
986 sethi %h44(symbol), %temp1
987 or %temp1, %m44(symbol), %temp2
988 sllx %temp2, 12, %temp3
989 or %temp3, %l44(symbol), %reg */
990 if (temp)
991 {
992 temp1 = op0;
993 temp2 = op0;
994 temp3 = temp; /* op0 is allowed. */
995 }
996 else
997 {
998 temp1 = gen_reg_rtx (DImode);
999 temp2 = gen_reg_rtx (DImode);
1000 temp3 = gen_reg_rtx (DImode);
1001 }
1002
1003 emit_insn (gen_seth44 (temp1, op1));
1004 emit_insn (gen_setm44 (temp2, temp1, op1));
1005 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1006 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1007 emit_insn (gen_setl44 (op0, temp3, op1));
1008 break;
1009
1010 case CM_MEDANY:
1011 /* The range spanned by all instructions in the object is less
1012 than 2^31 bytes (2GB) and the distance from any instruction
1013 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1014 than 2^31 bytes (2GB).
1015
1016 The executable can be placed anywhere in the virtual address
1017 space.
1018
1019 sethi %hh(symbol), %temp1
1020 sethi %lm(symbol), %temp2
1021 or %temp1, %hm(symbol), %temp3
1022 sllx %temp3, 32, %temp4
1023 or %temp4, %temp2, %temp5
1024 or %temp5, %lo(symbol), %reg */
1025 if (temp)
1026 {
1027 /* It is possible that one of the registers we got for operands[2]
1028 might coincide with that of operands[0] (which is why we made
1029 it TImode). Pick the other one to use as our scratch. */
1030 if (rtx_equal_p (temp, op0))
1031 {
1032 gcc_assert (ti_temp);
1033 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1034 }
1035 temp1 = op0;
1036 temp2 = temp; /* op0 is _not_ allowed, see above. */
1037 temp3 = op0;
1038 temp4 = op0;
1039 temp5 = op0;
1040 }
1041 else
1042 {
1043 temp1 = gen_reg_rtx (DImode);
1044 temp2 = gen_reg_rtx (DImode);
1045 temp3 = gen_reg_rtx (DImode);
1046 temp4 = gen_reg_rtx (DImode);
1047 temp5 = gen_reg_rtx (DImode);
1048 }
1049
1050 emit_insn (gen_sethh (temp1, op1));
1051 emit_insn (gen_setlm (temp2, op1));
1052 emit_insn (gen_sethm (temp3, temp1, op1));
1053 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1054 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1055 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1056 gen_rtx_PLUS (DImode, temp4, temp2)));
1057 emit_insn (gen_setlo (op0, temp5, op1));
1058 break;
1059
1060 case CM_EMBMEDANY:
1061 /* Old old old backwards compatibility kruft here.
1062 Essentially it is MEDLOW with a fixed 64-bit
1063 virtual base added to all data segment addresses.
1064 Text-segment stuff is computed like MEDANY, we can't
1065 reuse the code above because the relocation knobs
1066 look different.
1067
1068 Data segment: sethi %hi(symbol), %temp1
1069 add %temp1, EMBMEDANY_BASE_REG, %temp2
1070 or %temp2, %lo(symbol), %reg */
1071 if (data_segment_operand (op1, GET_MODE (op1)))
1072 {
1073 if (temp)
1074 {
1075 temp1 = temp; /* op0 is allowed. */
1076 temp2 = op0;
1077 }
1078 else
1079 {
1080 temp1 = gen_reg_rtx (DImode);
1081 temp2 = gen_reg_rtx (DImode);
1082 }
1083
1084 emit_insn (gen_embmedany_sethi (temp1, op1));
1085 emit_insn (gen_embmedany_brsum (temp2, temp1));
1086 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1087 }
1088
1089 /* Text segment: sethi %uhi(symbol), %temp1
1090 sethi %hi(symbol), %temp2
1091 or %temp1, %ulo(symbol), %temp3
1092 sllx %temp3, 32, %temp4
1093 or %temp4, %temp2, %temp5
1094 or %temp5, %lo(symbol), %reg */
1095 else
1096 {
1097 if (temp)
1098 {
1099 /* It is possible that one of the registers we got for operands[2]
1100 might coincide with that of operands[0] (which is why we made
1101 it TImode). Pick the other one to use as our scratch. */
1102 if (rtx_equal_p (temp, op0))
1103 {
1104 gcc_assert (ti_temp);
1105 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1106 }
1107 temp1 = op0;
1108 temp2 = temp; /* op0 is _not_ allowed, see above. */
1109 temp3 = op0;
1110 temp4 = op0;
1111 temp5 = op0;
1112 }
1113 else
1114 {
1115 temp1 = gen_reg_rtx (DImode);
1116 temp2 = gen_reg_rtx (DImode);
1117 temp3 = gen_reg_rtx (DImode);
1118 temp4 = gen_reg_rtx (DImode);
1119 temp5 = gen_reg_rtx (DImode);
1120 }
1121
1122 emit_insn (gen_embmedany_textuhi (temp1, op1));
1123 emit_insn (gen_embmedany_texthi (temp2, op1));
1124 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1125 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1126 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1127 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1128 gen_rtx_PLUS (DImode, temp4, temp2)));
1129 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1130 }
1131 break;
1132
1133 default:
1134 gcc_unreachable ();
1135 }
1136 }
1137
1138 #if HOST_BITS_PER_WIDE_INT == 32
1139 void
1140 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1141 {
1142 gcc_unreachable ();
1143 }
1144 #else
1145 /* These avoid problems when cross compiling. If we do not
1146 go through all this hair then the optimizer will see
1147 invalid REG_EQUAL notes or in some cases none at all. */
1148 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1149 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1150 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1151 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1152
1153 /* The optimizer is not to assume anything about exactly
1154 which bits are set for a HIGH, they are unspecified.
1155 Unfortunately this leads to many missed optimizations
1156 during CSE. We mask out the non-HIGH bits, and matches
1157 a plain movdi, to alleviate this problem. */
1158 static void
1159 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1160 {
1161 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff)));
1162 }
1163
1164 static rtx
1165 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1166 {
1167 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
1168 }
1169
1170 static rtx
1171 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1172 {
1173 return gen_rtx_IOR (DImode, src, GEN_INT (val));
1174 }
1175
1176 static rtx
1177 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1178 {
1179 return gen_rtx_XOR (DImode, src, GEN_INT (val));
1180 }
1181
1182 /* Worker routines for 64-bit constant formation on arch64.
1183 One of the key things to be doing in these emissions is
1184 to create as many temp REGs as possible. This makes it
1185 possible for half-built constants to be used later when
1186 such values are similar to something required later on.
1187 Without doing this, the optimizer cannot see such
1188 opportunities. */
1189
1190 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1191 unsigned HOST_WIDE_INT, int);
1192
1193 static void
1194 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1195 unsigned HOST_WIDE_INT low_bits, int is_neg)
1196 {
1197 unsigned HOST_WIDE_INT high_bits;
1198
1199 if (is_neg)
1200 high_bits = (~low_bits) & 0xffffffff;
1201 else
1202 high_bits = low_bits;
1203
1204 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1205 if (!is_neg)
1206 {
1207 emit_insn (gen_rtx_SET (VOIDmode, op0,
1208 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1209 }
1210 else
1211 {
1212 /* If we are XOR'ing with -1, then we should emit a one's complement
1213 instead. This way the combiner will notice logical operations
1214 such as ANDN later on and substitute. */
1215 if ((low_bits & 0x3ff) == 0x3ff)
1216 {
1217 emit_insn (gen_rtx_SET (VOIDmode, op0,
1218 gen_rtx_NOT (DImode, temp)));
1219 }
1220 else
1221 {
1222 emit_insn (gen_rtx_SET (VOIDmode, op0,
1223 gen_safe_XOR64 (temp,
1224 (-(HOST_WIDE_INT)0x400
1225 | (low_bits & 0x3ff)))));
1226 }
1227 }
1228 }
1229
1230 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1231 unsigned HOST_WIDE_INT, int);
1232
1233 static void
1234 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1235 unsigned HOST_WIDE_INT high_bits,
1236 unsigned HOST_WIDE_INT low_immediate,
1237 int shift_count)
1238 {
1239 rtx temp2 = op0;
1240
1241 if ((high_bits & 0xfffffc00) != 0)
1242 {
1243 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1244 if ((high_bits & ~0xfffffc00) != 0)
1245 emit_insn (gen_rtx_SET (VOIDmode, op0,
1246 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1247 else
1248 temp2 = temp;
1249 }
1250 else
1251 {
1252 emit_insn (gen_safe_SET64 (temp, high_bits));
1253 temp2 = temp;
1254 }
1255
1256 /* Now shift it up into place. */
1257 emit_insn (gen_rtx_SET (VOIDmode, op0,
1258 gen_rtx_ASHIFT (DImode, temp2,
1259 GEN_INT (shift_count))));
1260
1261 /* If there is a low immediate part piece, finish up by
1262 putting that in as well. */
1263 if (low_immediate != 0)
1264 emit_insn (gen_rtx_SET (VOIDmode, op0,
1265 gen_safe_OR64 (op0, low_immediate)));
1266 }
1267
1268 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1269 unsigned HOST_WIDE_INT);
1270
1271 /* Full 64-bit constant decomposition. Even though this is the
1272 'worst' case, we still optimize a few things away. */
1273 static void
1274 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1275 unsigned HOST_WIDE_INT high_bits,
1276 unsigned HOST_WIDE_INT low_bits)
1277 {
1278 rtx sub_temp;
1279
1280 if (reload_in_progress || reload_completed)
1281 sub_temp = op0;
1282 else
1283 sub_temp = gen_reg_rtx (DImode);
1284
1285 if ((high_bits & 0xfffffc00) != 0)
1286 {
1287 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1288 if ((high_bits & ~0xfffffc00) != 0)
1289 emit_insn (gen_rtx_SET (VOIDmode,
1290 sub_temp,
1291 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1292 else
1293 sub_temp = temp;
1294 }
1295 else
1296 {
1297 emit_insn (gen_safe_SET64 (temp, high_bits));
1298 sub_temp = temp;
1299 }
1300
1301 if (!reload_in_progress && !reload_completed)
1302 {
1303 rtx temp2 = gen_reg_rtx (DImode);
1304 rtx temp3 = gen_reg_rtx (DImode);
1305 rtx temp4 = gen_reg_rtx (DImode);
1306
1307 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1308 gen_rtx_ASHIFT (DImode, sub_temp,
1309 GEN_INT (32))));
1310
1311 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1312 if ((low_bits & ~0xfffffc00) != 0)
1313 {
1314 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1315 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1316 emit_insn (gen_rtx_SET (VOIDmode, op0,
1317 gen_rtx_PLUS (DImode, temp4, temp3)));
1318 }
1319 else
1320 {
1321 emit_insn (gen_rtx_SET (VOIDmode, op0,
1322 gen_rtx_PLUS (DImode, temp4, temp2)));
1323 }
1324 }
1325 else
1326 {
1327 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1328 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1329 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1330 int to_shift = 12;
1331
1332 /* We are in the middle of reload, so this is really
1333 painful. However we do still make an attempt to
1334 avoid emitting truly stupid code. */
1335 if (low1 != const0_rtx)
1336 {
1337 emit_insn (gen_rtx_SET (VOIDmode, op0,
1338 gen_rtx_ASHIFT (DImode, sub_temp,
1339 GEN_INT (to_shift))));
1340 emit_insn (gen_rtx_SET (VOIDmode, op0,
1341 gen_rtx_IOR (DImode, op0, low1)));
1342 sub_temp = op0;
1343 to_shift = 12;
1344 }
1345 else
1346 {
1347 to_shift += 12;
1348 }
1349 if (low2 != const0_rtx)
1350 {
1351 emit_insn (gen_rtx_SET (VOIDmode, op0,
1352 gen_rtx_ASHIFT (DImode, sub_temp,
1353 GEN_INT (to_shift))));
1354 emit_insn (gen_rtx_SET (VOIDmode, op0,
1355 gen_rtx_IOR (DImode, op0, low2)));
1356 sub_temp = op0;
1357 to_shift = 8;
1358 }
1359 else
1360 {
1361 to_shift += 8;
1362 }
1363 emit_insn (gen_rtx_SET (VOIDmode, op0,
1364 gen_rtx_ASHIFT (DImode, sub_temp,
1365 GEN_INT (to_shift))));
1366 if (low3 != const0_rtx)
1367 emit_insn (gen_rtx_SET (VOIDmode, op0,
1368 gen_rtx_IOR (DImode, op0, low3)));
1369 /* phew... */
1370 }
1371 }
1372
1373 /* Analyze a 64-bit constant for certain properties. */
1374 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1375 unsigned HOST_WIDE_INT,
1376 int *, int *, int *);
1377
1378 static void
1379 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1380 unsigned HOST_WIDE_INT low_bits,
1381 int *hbsp, int *lbsp, int *abbasp)
1382 {
1383 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1384 int i;
1385
1386 lowest_bit_set = highest_bit_set = -1;
1387 i = 0;
1388 do
1389 {
1390 if ((lowest_bit_set == -1)
1391 && ((low_bits >> i) & 1))
1392 lowest_bit_set = i;
1393 if ((highest_bit_set == -1)
1394 && ((high_bits >> (32 - i - 1)) & 1))
1395 highest_bit_set = (64 - i - 1);
1396 }
1397 while (++i < 32
1398 && ((highest_bit_set == -1)
1399 || (lowest_bit_set == -1)));
1400 if (i == 32)
1401 {
1402 i = 0;
1403 do
1404 {
1405 if ((lowest_bit_set == -1)
1406 && ((high_bits >> i) & 1))
1407 lowest_bit_set = i + 32;
1408 if ((highest_bit_set == -1)
1409 && ((low_bits >> (32 - i - 1)) & 1))
1410 highest_bit_set = 32 - i - 1;
1411 }
1412 while (++i < 32
1413 && ((highest_bit_set == -1)
1414 || (lowest_bit_set == -1)));
1415 }
1416 /* If there are no bits set this should have gone out
1417 as one instruction! */
1418 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
1419 all_bits_between_are_set = 1;
1420 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1421 {
1422 if (i < 32)
1423 {
1424 if ((low_bits & (1 << i)) != 0)
1425 continue;
1426 }
1427 else
1428 {
1429 if ((high_bits & (1 << (i - 32))) != 0)
1430 continue;
1431 }
1432 all_bits_between_are_set = 0;
1433 break;
1434 }
1435 *hbsp = highest_bit_set;
1436 *lbsp = lowest_bit_set;
1437 *abbasp = all_bits_between_are_set;
1438 }
1439
1440 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1441
1442 static int
1443 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1444 unsigned HOST_WIDE_INT low_bits)
1445 {
1446 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1447
1448 if (high_bits == 0
1449 || high_bits == 0xffffffff)
1450 return 1;
1451
1452 analyze_64bit_constant (high_bits, low_bits,
1453 &highest_bit_set, &lowest_bit_set,
1454 &all_bits_between_are_set);
1455
1456 if ((highest_bit_set == 63
1457 || lowest_bit_set == 0)
1458 && all_bits_between_are_set != 0)
1459 return 1;
1460
1461 if ((highest_bit_set - lowest_bit_set) < 21)
1462 return 1;
1463
1464 return 0;
1465 }
1466
1467 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1468 unsigned HOST_WIDE_INT,
1469 int, int);
1470
1471 static unsigned HOST_WIDE_INT
1472 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1473 unsigned HOST_WIDE_INT low_bits,
1474 int lowest_bit_set, int shift)
1475 {
1476 HOST_WIDE_INT hi, lo;
1477
1478 if (lowest_bit_set < 32)
1479 {
1480 lo = (low_bits >> lowest_bit_set) << shift;
1481 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1482 }
1483 else
1484 {
1485 lo = 0;
1486 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1487 }
1488 gcc_assert (! (hi & lo));
1489 return (hi | lo);
1490 }
1491
1492 /* Here we are sure to be arch64 and this is an integer constant
1493 being loaded into a register. Emit the most efficient
1494 insn sequence possible. Detection of all the 1-insn cases
1495 has been done already. */
1496 void
1497 sparc_emit_set_const64 (rtx op0, rtx op1)
1498 {
1499 unsigned HOST_WIDE_INT high_bits, low_bits;
1500 int lowest_bit_set, highest_bit_set;
1501 int all_bits_between_are_set;
1502 rtx temp = 0;
1503
1504 /* Sanity check that we know what we are working with. */
1505 gcc_assert (TARGET_ARCH64);
1506
1507 if (GET_CODE (op0) != SUBREG)
1508 {
1509 gcc_assert (GET_CODE (op0) == REG
1510 && (REGNO (op0) < SPARC_FIRST_FP_REG
1511 || REGNO (op0) > SPARC_LAST_V9_FP_REG));
1512 }
1513
1514 if (reload_in_progress || reload_completed)
1515 temp = op0;
1516
1517 if (GET_CODE (op1) != CONST_INT)
1518 {
1519 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1520 return;
1521 }
1522
1523 if (! temp)
1524 temp = gen_reg_rtx (DImode);
1525
1526 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1527 low_bits = (INTVAL (op1) & 0xffffffff);
1528
1529 /* low_bits bits 0 --> 31
1530 high_bits bits 32 --> 63 */
1531
1532 analyze_64bit_constant (high_bits, low_bits,
1533 &highest_bit_set, &lowest_bit_set,
1534 &all_bits_between_are_set);
1535
1536 /* First try for a 2-insn sequence. */
1537
1538 /* These situations are preferred because the optimizer can
1539 * do more things with them:
1540 * 1) mov -1, %reg
1541 * sllx %reg, shift, %reg
1542 * 2) mov -1, %reg
1543 * srlx %reg, shift, %reg
1544 * 3) mov some_small_const, %reg
1545 * sllx %reg, shift, %reg
1546 */
1547 if (((highest_bit_set == 63
1548 || lowest_bit_set == 0)
1549 && all_bits_between_are_set != 0)
1550 || ((highest_bit_set - lowest_bit_set) < 12))
1551 {
1552 HOST_WIDE_INT the_const = -1;
1553 int shift = lowest_bit_set;
1554
1555 if ((highest_bit_set != 63
1556 && lowest_bit_set != 0)
1557 || all_bits_between_are_set == 0)
1558 {
1559 the_const =
1560 create_simple_focus_bits (high_bits, low_bits,
1561 lowest_bit_set, 0);
1562 }
1563 else if (lowest_bit_set == 0)
1564 shift = -(63 - highest_bit_set);
1565
1566 gcc_assert (SPARC_SIMM13_P (the_const));
1567 gcc_assert (shift != 0);
1568
1569 emit_insn (gen_safe_SET64 (temp, the_const));
1570 if (shift > 0)
1571 emit_insn (gen_rtx_SET (VOIDmode,
1572 op0,
1573 gen_rtx_ASHIFT (DImode,
1574 temp,
1575 GEN_INT (shift))));
1576 else if (shift < 0)
1577 emit_insn (gen_rtx_SET (VOIDmode,
1578 op0,
1579 gen_rtx_LSHIFTRT (DImode,
1580 temp,
1581 GEN_INT (-shift))));
1582 return;
1583 }
1584
1585 /* Now a range of 22 or less bits set somewhere.
1586 * 1) sethi %hi(focus_bits), %reg
1587 * sllx %reg, shift, %reg
1588 * 2) sethi %hi(focus_bits), %reg
1589 * srlx %reg, shift, %reg
1590 */
1591 if ((highest_bit_set - lowest_bit_set) < 21)
1592 {
1593 unsigned HOST_WIDE_INT focus_bits =
1594 create_simple_focus_bits (high_bits, low_bits,
1595 lowest_bit_set, 10);
1596
1597 gcc_assert (SPARC_SETHI_P (focus_bits));
1598 gcc_assert (lowest_bit_set != 10);
1599
1600 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
1601
1602 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1603 if (lowest_bit_set < 10)
1604 emit_insn (gen_rtx_SET (VOIDmode,
1605 op0,
1606 gen_rtx_LSHIFTRT (DImode, temp,
1607 GEN_INT (10 - lowest_bit_set))));
1608 else if (lowest_bit_set > 10)
1609 emit_insn (gen_rtx_SET (VOIDmode,
1610 op0,
1611 gen_rtx_ASHIFT (DImode, temp,
1612 GEN_INT (lowest_bit_set - 10))));
1613 return;
1614 }
1615
1616 /* 1) sethi %hi(low_bits), %reg
1617 * or %reg, %lo(low_bits), %reg
1618 * 2) sethi %hi(~low_bits), %reg
1619 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1620 */
1621 if (high_bits == 0
1622 || high_bits == 0xffffffff)
1623 {
1624 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1625 (high_bits == 0xffffffff));
1626 return;
1627 }
1628
1629 /* Now, try 3-insn sequences. */
1630
1631 /* 1) sethi %hi(high_bits), %reg
1632 * or %reg, %lo(high_bits), %reg
1633 * sllx %reg, 32, %reg
1634 */
1635 if (low_bits == 0)
1636 {
1637 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
1638 return;
1639 }
1640
1641 /* We may be able to do something quick
1642 when the constant is negated, so try that. */
1643 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1644 (~low_bits) & 0xfffffc00))
1645 {
1646 /* NOTE: The trailing bits get XOR'd so we need the
1647 non-negated bits, not the negated ones. */
1648 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
1649
1650 if ((((~high_bits) & 0xffffffff) == 0
1651 && ((~low_bits) & 0x80000000) == 0)
1652 || (((~high_bits) & 0xffffffff) == 0xffffffff
1653 && ((~low_bits) & 0x80000000) != 0))
1654 {
1655 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
1656
1657 if ((SPARC_SETHI_P (fast_int)
1658 && (~high_bits & 0xffffffff) == 0)
1659 || SPARC_SIMM13_P (fast_int))
1660 emit_insn (gen_safe_SET64 (temp, fast_int));
1661 else
1662 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
1663 }
1664 else
1665 {
1666 rtx negated_const;
1667 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1668 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1669 sparc_emit_set_const64 (temp, negated_const);
1670 }
1671
1672 /* If we are XOR'ing with -1, then we should emit a one's complement
1673 instead. This way the combiner will notice logical operations
1674 such as ANDN later on and substitute. */
1675 if (trailing_bits == 0x3ff)
1676 {
1677 emit_insn (gen_rtx_SET (VOIDmode, op0,
1678 gen_rtx_NOT (DImode, temp)));
1679 }
1680 else
1681 {
1682 emit_insn (gen_rtx_SET (VOIDmode,
1683 op0,
1684 gen_safe_XOR64 (temp,
1685 (-0x400 | trailing_bits))));
1686 }
1687 return;
1688 }
1689
1690 /* 1) sethi %hi(xxx), %reg
1691 * or %reg, %lo(xxx), %reg
1692 * sllx %reg, yyy, %reg
1693 *
1694 * ??? This is just a generalized version of the low_bits==0
1695 * thing above, FIXME...
1696 */
1697 if ((highest_bit_set - lowest_bit_set) < 32)
1698 {
1699 unsigned HOST_WIDE_INT focus_bits =
1700 create_simple_focus_bits (high_bits, low_bits,
1701 lowest_bit_set, 0);
1702
1703 /* We can't get here in this state. */
1704 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
1705
1706 /* So what we know is that the set bits straddle the
1707 middle of the 64-bit word. */
1708 sparc_emit_set_const64_quick2 (op0, temp,
1709 focus_bits, 0,
1710 lowest_bit_set);
1711 return;
1712 }
1713
1714 /* 1) sethi %hi(high_bits), %reg
1715 * or %reg, %lo(high_bits), %reg
1716 * sllx %reg, 32, %reg
1717 * or %reg, low_bits, %reg
1718 */
1719 if (SPARC_SIMM13_P(low_bits)
1720 && ((int)low_bits > 0))
1721 {
1722 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1723 return;
1724 }
1725
1726 /* The easiest way when all else fails, is full decomposition. */
1727 #if 0
1728 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1729 high_bits, low_bits, ~high_bits, ~low_bits);
1730 #endif
1731 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
1732 }
1733 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
1734
1735 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1736 return the mode to be used for the comparison. For floating-point,
1737 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1738 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1739 processing is needed. */
1740
1741 enum machine_mode
1742 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
1743 {
1744 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1745 {
1746 switch (op)
1747 {
1748 case EQ:
1749 case NE:
1750 case UNORDERED:
1751 case ORDERED:
1752 case UNLT:
1753 case UNLE:
1754 case UNGT:
1755 case UNGE:
1756 case UNEQ:
1757 case LTGT:
1758 return CCFPmode;
1759
1760 case LT:
1761 case LE:
1762 case GT:
1763 case GE:
1764 return CCFPEmode;
1765
1766 default:
1767 gcc_unreachable ();
1768 }
1769 }
1770 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
1771 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
1772 {
1773 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
1774 return CCX_NOOVmode;
1775 else
1776 return CC_NOOVmode;
1777 }
1778 else
1779 {
1780 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
1781 return CCXmode;
1782 else
1783 return CCmode;
1784 }
1785 }
1786
1787 /* X and Y are two things to compare using CODE. Emit the compare insn and
1788 return the rtx for the cc reg in the proper mode. */
1789
1790 rtx
1791 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
1792 {
1793 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1794 rtx cc_reg;
1795
1796 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1797 fcc regs (cse can't tell they're really call clobbered regs and will
1798 remove a duplicate comparison even if there is an intervening function
1799 call - it will then try to reload the cc reg via an int reg which is why
1800 we need the movcc patterns). It is possible to provide the movcc
1801 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1802 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1803 to tell cse that CCFPE mode registers (even pseudos) are call
1804 clobbered. */
1805
1806 /* ??? This is an experiment. Rather than making changes to cse which may
1807 or may not be easy/clean, we do our own cse. This is possible because
1808 we will generate hard registers. Cse knows they're call clobbered (it
1809 doesn't know the same thing about pseudos). If we guess wrong, no big
1810 deal, but if we win, great! */
1811
1812 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1813 #if 1 /* experiment */
1814 {
1815 int reg;
1816 /* We cycle through the registers to ensure they're all exercised. */
1817 static int next_fcc_reg = 0;
1818 /* Previous x,y for each fcc reg. */
1819 static rtx prev_args[4][2];
1820
1821 /* Scan prev_args for x,y. */
1822 for (reg = 0; reg < 4; reg++)
1823 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
1824 break;
1825 if (reg == 4)
1826 {
1827 reg = next_fcc_reg;
1828 prev_args[reg][0] = x;
1829 prev_args[reg][1] = y;
1830 next_fcc_reg = (next_fcc_reg + 1) & 3;
1831 }
1832 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
1833 }
1834 #else
1835 cc_reg = gen_reg_rtx (mode);
1836 #endif /* ! experiment */
1837 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1838 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
1839 else
1840 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
1841
1842 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
1843 gen_rtx_COMPARE (mode, x, y)));
1844
1845 return cc_reg;
1846 }
1847
1848 /* This function is used for v9 only.
1849 CODE is the code for an Scc's comparison.
1850 OPERANDS[0] is the target of the Scc insn.
1851 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1852 been generated yet).
1853
1854 This function is needed to turn
1855
1856 (set (reg:SI 110)
1857 (gt (reg:CCX 100 %icc)
1858 (const_int 0)))
1859 into
1860 (set (reg:SI 110)
1861 (gt:DI (reg:CCX 100 %icc)
1862 (const_int 0)))
1863
1864 IE: The instruction recognizer needs to see the mode of the comparison to
1865 find the right instruction. We could use "gt:DI" right in the
1866 define_expand, but leaving it out allows us to handle DI, SI, etc.
1867
1868 We refer to the global sparc compare operands sparc_compare_op0 and
1869 sparc_compare_op1. */
1870
1871 int
1872 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
1873 {
1874 rtx temp, op0, op1;
1875
1876 if (! TARGET_ARCH64
1877 && (GET_MODE (sparc_compare_op0) == DImode
1878 || GET_MODE (operands[0]) == DImode))
1879 return 0;
1880
1881 op0 = sparc_compare_op0;
1882 op1 = sparc_compare_op1;
1883
1884 /* Try to use the movrCC insns. */
1885 if (TARGET_ARCH64
1886 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
1887 && op1 == const0_rtx
1888 && v9_regcmp_p (compare_code))
1889 {
1890 /* Special case for op0 != 0. This can be done with one instruction if
1891 operands[0] == sparc_compare_op0. */
1892
1893 if (compare_code == NE
1894 && GET_MODE (operands[0]) == DImode
1895 && rtx_equal_p (op0, operands[0]))
1896 {
1897 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1898 gen_rtx_IF_THEN_ELSE (DImode,
1899 gen_rtx_fmt_ee (compare_code, DImode,
1900 op0, const0_rtx),
1901 const1_rtx,
1902 operands[0])));
1903 return 1;
1904 }
1905
1906 if (reg_overlap_mentioned_p (operands[0], op0))
1907 {
1908 /* Handle the case where operands[0] == sparc_compare_op0.
1909 We "early clobber" the result. */
1910 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
1911 emit_move_insn (op0, sparc_compare_op0);
1912 }
1913
1914 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
1915 if (GET_MODE (op0) != DImode)
1916 {
1917 temp = gen_reg_rtx (DImode);
1918 convert_move (temp, op0, 0);
1919 }
1920 else
1921 temp = op0;
1922 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1923 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
1924 gen_rtx_fmt_ee (compare_code, DImode,
1925 temp, const0_rtx),
1926 const1_rtx,
1927 operands[0])));
1928 return 1;
1929 }
1930 else
1931 {
1932 operands[1] = gen_compare_reg (compare_code, op0, op1);
1933
1934 switch (GET_MODE (operands[1]))
1935 {
1936 case CCmode :
1937 case CCXmode :
1938 case CCFPEmode :
1939 case CCFPmode :
1940 break;
1941 default :
1942 gcc_unreachable ();
1943 }
1944 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
1945 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1946 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
1947 gen_rtx_fmt_ee (compare_code,
1948 GET_MODE (operands[1]),
1949 operands[1], const0_rtx),
1950 const1_rtx, operands[0])));
1951 return 1;
1952 }
1953 }
1954
1955 /* Emit a conditional jump insn for the v9 architecture using comparison code
1956 CODE and jump target LABEL.
1957 This function exists to take advantage of the v9 brxx insns. */
1958
1959 void
1960 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
1961 {
1962 emit_jump_insn (gen_rtx_SET (VOIDmode,
1963 pc_rtx,
1964 gen_rtx_IF_THEN_ELSE (VOIDmode,
1965 gen_rtx_fmt_ee (code, GET_MODE (op0),
1966 op0, const0_rtx),
1967 gen_rtx_LABEL_REF (VOIDmode, label),
1968 pc_rtx)));
1969 }
1970
1971 /* Generate a DFmode part of a hard TFmode register.
1972 REG is the TFmode hard register, LOW is 1 for the
1973 low 64bit of the register and 0 otherwise.
1974 */
1975 rtx
1976 gen_df_reg (rtx reg, int low)
1977 {
1978 int regno = REGNO (reg);
1979
1980 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
1981 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
1982 return gen_rtx_REG (DFmode, regno);
1983 }
1984 \f
1985 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
1986 Unlike normal calls, TFmode operands are passed by reference. It is
1987 assumed that no more than 3 operands are required. */
1988
1989 static void
1990 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
1991 {
1992 rtx ret_slot = NULL, arg[3], func_sym;
1993 int i;
1994
1995 /* We only expect to be called for conversions, unary, and binary ops. */
1996 gcc_assert (nargs == 2 || nargs == 3);
1997
1998 for (i = 0; i < nargs; ++i)
1999 {
2000 rtx this_arg = operands[i];
2001 rtx this_slot;
2002
2003 /* TFmode arguments and return values are passed by reference. */
2004 if (GET_MODE (this_arg) == TFmode)
2005 {
2006 int force_stack_temp;
2007
2008 force_stack_temp = 0;
2009 if (TARGET_BUGGY_QP_LIB && i == 0)
2010 force_stack_temp = 1;
2011
2012 if (GET_CODE (this_arg) == MEM
2013 && ! force_stack_temp)
2014 this_arg = XEXP (this_arg, 0);
2015 else if (CONSTANT_P (this_arg)
2016 && ! force_stack_temp)
2017 {
2018 this_slot = force_const_mem (TFmode, this_arg);
2019 this_arg = XEXP (this_slot, 0);
2020 }
2021 else
2022 {
2023 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2024
2025 /* Operand 0 is the return value. We'll copy it out later. */
2026 if (i > 0)
2027 emit_move_insn (this_slot, this_arg);
2028 else
2029 ret_slot = this_slot;
2030
2031 this_arg = XEXP (this_slot, 0);
2032 }
2033 }
2034
2035 arg[i] = this_arg;
2036 }
2037
2038 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2039
2040 if (GET_MODE (operands[0]) == TFmode)
2041 {
2042 if (nargs == 2)
2043 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2044 arg[0], GET_MODE (arg[0]),
2045 arg[1], GET_MODE (arg[1]));
2046 else
2047 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2048 arg[0], GET_MODE (arg[0]),
2049 arg[1], GET_MODE (arg[1]),
2050 arg[2], GET_MODE (arg[2]));
2051
2052 if (ret_slot)
2053 emit_move_insn (operands[0], ret_slot);
2054 }
2055 else
2056 {
2057 rtx ret;
2058
2059 gcc_assert (nargs == 2);
2060
2061 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2062 GET_MODE (operands[0]), 1,
2063 arg[1], GET_MODE (arg[1]));
2064
2065 if (ret != operands[0])
2066 emit_move_insn (operands[0], ret);
2067 }
2068 }
2069
2070 /* Expand soft-float TFmode calls to sparc abi routines. */
2071
2072 static void
2073 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2074 {
2075 const char *func;
2076
2077 switch (code)
2078 {
2079 case PLUS:
2080 func = "_Qp_add";
2081 break;
2082 case MINUS:
2083 func = "_Qp_sub";
2084 break;
2085 case MULT:
2086 func = "_Qp_mul";
2087 break;
2088 case DIV:
2089 func = "_Qp_div";
2090 break;
2091 default:
2092 gcc_unreachable ();
2093 }
2094
2095 emit_soft_tfmode_libcall (func, 3, operands);
2096 }
2097
2098 static void
2099 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2100 {
2101 const char *func;
2102
2103 gcc_assert (code == SQRT);
2104 func = "_Qp_sqrt";
2105
2106 emit_soft_tfmode_libcall (func, 2, operands);
2107 }
2108
2109 static void
2110 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2111 {
2112 const char *func;
2113
2114 switch (code)
2115 {
2116 case FLOAT_EXTEND:
2117 switch (GET_MODE (operands[1]))
2118 {
2119 case SFmode:
2120 func = "_Qp_stoq";
2121 break;
2122 case DFmode:
2123 func = "_Qp_dtoq";
2124 break;
2125 default:
2126 gcc_unreachable ();
2127 }
2128 break;
2129
2130 case FLOAT_TRUNCATE:
2131 switch (GET_MODE (operands[0]))
2132 {
2133 case SFmode:
2134 func = "_Qp_qtos";
2135 break;
2136 case DFmode:
2137 func = "_Qp_qtod";
2138 break;
2139 default:
2140 gcc_unreachable ();
2141 }
2142 break;
2143
2144 case FLOAT:
2145 switch (GET_MODE (operands[1]))
2146 {
2147 case SImode:
2148 func = "_Qp_itoq";
2149 break;
2150 case DImode:
2151 func = "_Qp_xtoq";
2152 break;
2153 default:
2154 gcc_unreachable ();
2155 }
2156 break;
2157
2158 case UNSIGNED_FLOAT:
2159 switch (GET_MODE (operands[1]))
2160 {
2161 case SImode:
2162 func = "_Qp_uitoq";
2163 break;
2164 case DImode:
2165 func = "_Qp_uxtoq";
2166 break;
2167 default:
2168 gcc_unreachable ();
2169 }
2170 break;
2171
2172 case FIX:
2173 switch (GET_MODE (operands[0]))
2174 {
2175 case SImode:
2176 func = "_Qp_qtoi";
2177 break;
2178 case DImode:
2179 func = "_Qp_qtox";
2180 break;
2181 default:
2182 gcc_unreachable ();
2183 }
2184 break;
2185
2186 case UNSIGNED_FIX:
2187 switch (GET_MODE (operands[0]))
2188 {
2189 case SImode:
2190 func = "_Qp_qtoui";
2191 break;
2192 case DImode:
2193 func = "_Qp_qtoux";
2194 break;
2195 default:
2196 gcc_unreachable ();
2197 }
2198 break;
2199
2200 default:
2201 gcc_unreachable ();
2202 }
2203
2204 emit_soft_tfmode_libcall (func, 2, operands);
2205 }
2206
2207 /* Expand a hard-float tfmode operation. All arguments must be in
2208 registers. */
2209
2210 static void
2211 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2212 {
2213 rtx op, dest;
2214
2215 if (GET_RTX_CLASS (code) == RTX_UNARY)
2216 {
2217 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2218 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2219 }
2220 else
2221 {
2222 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2223 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2224 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2225 operands[1], operands[2]);
2226 }
2227
2228 if (register_operand (operands[0], VOIDmode))
2229 dest = operands[0];
2230 else
2231 dest = gen_reg_rtx (GET_MODE (operands[0]));
2232
2233 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2234
2235 if (dest != operands[0])
2236 emit_move_insn (operands[0], dest);
2237 }
2238
2239 void
2240 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2241 {
2242 if (TARGET_HARD_QUAD)
2243 emit_hard_tfmode_operation (code, operands);
2244 else
2245 emit_soft_tfmode_binop (code, operands);
2246 }
2247
2248 void
2249 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2250 {
2251 if (TARGET_HARD_QUAD)
2252 emit_hard_tfmode_operation (code, operands);
2253 else
2254 emit_soft_tfmode_unop (code, operands);
2255 }
2256
2257 void
2258 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2259 {
2260 if (TARGET_HARD_QUAD)
2261 emit_hard_tfmode_operation (code, operands);
2262 else
2263 emit_soft_tfmode_cvt (code, operands);
2264 }
2265 \f
2266 /* Return nonzero if a branch/jump/call instruction will be emitting
2267 nop into its delay slot. */
2268
2269 int
2270 empty_delay_slot (rtx insn)
2271 {
2272 rtx seq;
2273
2274 /* If no previous instruction (should not happen), return true. */
2275 if (PREV_INSN (insn) == NULL)
2276 return 1;
2277
2278 seq = NEXT_INSN (PREV_INSN (insn));
2279 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2280 return 0;
2281
2282 return 1;
2283 }
2284
2285 /* Return nonzero if TRIAL can go into the call delay slot. */
2286
2287 int
2288 tls_call_delay (rtx trial)
2289 {
2290 rtx pat, unspec;
2291
2292 /* Binutils allows
2293 call __tls_get_addr, %tgd_call (foo)
2294 add %l7, %o0, %o0, %tgd_add (foo)
2295 while Sun as/ld does not. */
2296 if (TARGET_GNU_TLS || !TARGET_TLS)
2297 return 1;
2298
2299 pat = PATTERN (trial);
2300 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2301 return 1;
2302
2303 unspec = XEXP (SET_DEST (pat), 1);
2304 if (GET_CODE (unspec) != UNSPEC
2305 || (XINT (unspec, 1) != UNSPEC_TLSGD
2306 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2307 return 1;
2308
2309 return 0;
2310 }
2311
2312 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2313 instruction. RETURN_P is true if the v9 variant 'return' is to be
2314 considered in the test too.
2315
2316 TRIAL must be a SET whose destination is a REG appropriate for the
2317 'restore' instruction or, if RETURN_P is true, for the 'return'
2318 instruction. */
2319
2320 static int
2321 eligible_for_restore_insn (rtx trial, bool return_p)
2322 {
2323 rtx pat = PATTERN (trial);
2324 rtx src = SET_SRC (pat);
2325
2326 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2327 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2328 && arith_operand (src, GET_MODE (src)))
2329 {
2330 if (TARGET_ARCH64)
2331 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2332 else
2333 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2334 }
2335
2336 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2337 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2338 && arith_double_operand (src, GET_MODE (src)))
2339 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2340
2341 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2342 else if (! TARGET_FPU && register_operand (src, SFmode))
2343 return 1;
2344
2345 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2346 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
2347 return 1;
2348
2349 /* If we have the 'return' instruction, anything that does not use
2350 local or output registers and can go into a delay slot wins. */
2351 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
2352 && (get_attr_in_uncond_branch_delay (trial)
2353 == IN_UNCOND_BRANCH_DELAY_TRUE))
2354 return 1;
2355
2356 /* The 'restore src1,src2,dest' pattern for SImode. */
2357 else if (GET_CODE (src) == PLUS
2358 && register_operand (XEXP (src, 0), SImode)
2359 && arith_operand (XEXP (src, 1), SImode))
2360 return 1;
2361
2362 /* The 'restore src1,src2,dest' pattern for DImode. */
2363 else if (GET_CODE (src) == PLUS
2364 && register_operand (XEXP (src, 0), DImode)
2365 && arith_double_operand (XEXP (src, 1), DImode))
2366 return 1;
2367
2368 /* The 'restore src1,%lo(src2),dest' pattern. */
2369 else if (GET_CODE (src) == LO_SUM
2370 && ! TARGET_CM_MEDMID
2371 && ((register_operand (XEXP (src, 0), SImode)
2372 && immediate_operand (XEXP (src, 1), SImode))
2373 || (TARGET_ARCH64
2374 && register_operand (XEXP (src, 0), DImode)
2375 && immediate_operand (XEXP (src, 1), DImode))))
2376 return 1;
2377
2378 /* The 'restore src,src,dest' pattern. */
2379 else if (GET_CODE (src) == ASHIFT
2380 && (register_operand (XEXP (src, 0), SImode)
2381 || register_operand (XEXP (src, 0), DImode))
2382 && XEXP (src, 1) == const1_rtx)
2383 return 1;
2384
2385 return 0;
2386 }
2387
2388 /* Return nonzero if TRIAL can go into the function return's
2389 delay slot. */
2390
2391 int
2392 eligible_for_return_delay (rtx trial)
2393 {
2394 rtx pat;
2395
2396 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2397 return 0;
2398
2399 if (get_attr_length (trial) != 1)
2400 return 0;
2401
2402 /* If there are any call-saved registers, we should scan TRIAL if it
2403 does not reference them. For now just make it easy. */
2404 if (num_gfregs)
2405 return 0;
2406
2407 /* If the function uses __builtin_eh_return, the eh_return machinery
2408 occupies the delay slot. */
2409 if (current_function_calls_eh_return)
2410 return 0;
2411
2412 /* In the case of a true leaf function, anything can go into the slot. */
2413 if (sparc_leaf_function_p)
2414 return get_attr_in_uncond_branch_delay (trial)
2415 == IN_UNCOND_BRANCH_DELAY_TRUE;
2416
2417 pat = PATTERN (trial);
2418
2419 /* Otherwise, only operations which can be done in tandem with
2420 a `restore' or `return' insn can go into the delay slot. */
2421 if (GET_CODE (SET_DEST (pat)) != REG
2422 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2423 return 0;
2424
2425 /* If this instruction sets up floating point register and we have a return
2426 instruction, it can probably go in. But restore will not work
2427 with FP_REGS. */
2428 if (REGNO (SET_DEST (pat)) >= 32)
2429 return (TARGET_V9
2430 && ! epilogue_renumber (&pat, 1)
2431 && (get_attr_in_uncond_branch_delay (trial)
2432 == IN_UNCOND_BRANCH_DELAY_TRUE));
2433
2434 return eligible_for_restore_insn (trial, true);
2435 }
2436
2437 /* Return nonzero if TRIAL can go into the sibling call's
2438 delay slot. */
2439
2440 int
2441 eligible_for_sibcall_delay (rtx trial)
2442 {
2443 rtx pat;
2444
2445 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2446 return 0;
2447
2448 if (get_attr_length (trial) != 1)
2449 return 0;
2450
2451 pat = PATTERN (trial);
2452
2453 if (sparc_leaf_function_p)
2454 {
2455 /* If the tail call is done using the call instruction,
2456 we have to restore %o7 in the delay slot. */
2457 if (LEAF_SIBCALL_SLOT_RESERVED_P)
2458 return 0;
2459
2460 /* %g1 is used to build the function address */
2461 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2462 return 0;
2463
2464 return 1;
2465 }
2466
2467 /* Otherwise, only operations which can be done in tandem with
2468 a `restore' insn can go into the delay slot. */
2469 if (GET_CODE (SET_DEST (pat)) != REG
2470 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
2471 || REGNO (SET_DEST (pat)) >= 32)
2472 return 0;
2473
2474 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2475 in most cases. */
2476 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2477 return 0;
2478
2479 return eligible_for_restore_insn (trial, false);
2480 }
2481
2482 int
2483 short_branch (int uid1, int uid2)
2484 {
2485 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
2486
2487 /* Leave a few words of "slop". */
2488 if (delta >= -1023 && delta <= 1022)
2489 return 1;
2490
2491 return 0;
2492 }
2493
2494 /* Return nonzero if REG is not used after INSN.
2495 We assume REG is a reload reg, and therefore does
2496 not live past labels or calls or jumps. */
2497 int
2498 reg_unused_after (rtx reg, rtx insn)
2499 {
2500 enum rtx_code code, prev_code = UNKNOWN;
2501
2502 while ((insn = NEXT_INSN (insn)))
2503 {
2504 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2505 return 1;
2506
2507 code = GET_CODE (insn);
2508 if (GET_CODE (insn) == CODE_LABEL)
2509 return 1;
2510
2511 if (INSN_P (insn))
2512 {
2513 rtx set = single_set (insn);
2514 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2515 if (set && in_src)
2516 return 0;
2517 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2518 return 1;
2519 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2520 return 0;
2521 }
2522 prev_code = code;
2523 }
2524 return 1;
2525 }
2526 \f
2527 /* Determine if it's legal to put X into the constant pool. This
2528 is not possible if X contains the address of a symbol that is
2529 not constant (TLS) or not known at final link time (PIC). */
2530
2531 static bool
2532 sparc_cannot_force_const_mem (rtx x)
2533 {
2534 switch (GET_CODE (x))
2535 {
2536 case CONST_INT:
2537 case CONST_DOUBLE:
2538 case CONST_VECTOR:
2539 /* Accept all non-symbolic constants. */
2540 return false;
2541
2542 case LABEL_REF:
2543 /* Labels are OK iff we are non-PIC. */
2544 return flag_pic != 0;
2545
2546 case SYMBOL_REF:
2547 /* 'Naked' TLS symbol references are never OK,
2548 non-TLS symbols are OK iff we are non-PIC. */
2549 if (SYMBOL_REF_TLS_MODEL (x))
2550 return true;
2551 else
2552 return flag_pic != 0;
2553
2554 case CONST:
2555 return sparc_cannot_force_const_mem (XEXP (x, 0));
2556 case PLUS:
2557 case MINUS:
2558 return sparc_cannot_force_const_mem (XEXP (x, 0))
2559 || sparc_cannot_force_const_mem (XEXP (x, 1));
2560 case UNSPEC:
2561 return true;
2562 default:
2563 gcc_unreachable ();
2564 }
2565 }
2566 \f
2567 /* PIC support. */
2568 static GTY(()) char pic_helper_symbol_name[256];
2569 static GTY(()) rtx pic_helper_symbol;
2570 static GTY(()) bool pic_helper_emitted_p = false;
2571 static GTY(()) rtx global_offset_table;
2572
2573 /* Ensure that we are not using patterns that are not OK with PIC. */
2574
2575 int
2576 check_pic (int i)
2577 {
2578 switch (flag_pic)
2579 {
2580 case 1:
2581 gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF
2582 && (GET_CODE (recog_data.operand[i]) != CONST
2583 || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2584 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
2585 == global_offset_table)
2586 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
2587 == CONST))));
2588 case 2:
2589 default:
2590 return 1;
2591 }
2592 }
2593
2594 /* Return true if X is an address which needs a temporary register when
2595 reloaded while generating PIC code. */
2596
2597 int
2598 pic_address_needs_scratch (rtx x)
2599 {
2600 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2601 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2602 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2603 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2604 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2605 return 1;
2606
2607 return 0;
2608 }
2609
2610 /* Determine if a given RTX is a valid constant. We already know this
2611 satisfies CONSTANT_P. */
2612
2613 bool
2614 legitimate_constant_p (rtx x)
2615 {
2616 rtx inner;
2617
2618 switch (GET_CODE (x))
2619 {
2620 case SYMBOL_REF:
2621 /* TLS symbols are not constant. */
2622 if (SYMBOL_REF_TLS_MODEL (x))
2623 return false;
2624 break;
2625
2626 case CONST:
2627 inner = XEXP (x, 0);
2628
2629 /* Offsets of TLS symbols are never valid.
2630 Discourage CSE from creating them. */
2631 if (GET_CODE (inner) == PLUS
2632 && tls_symbolic_operand (XEXP (inner, 0)))
2633 return false;
2634 break;
2635
2636 case CONST_DOUBLE:
2637 if (GET_MODE (x) == VOIDmode)
2638 return true;
2639
2640 /* Floating point constants are generally not ok.
2641 The only exception is 0.0 in VIS. */
2642 if (TARGET_VIS
2643 && (GET_MODE (x) == SFmode
2644 || GET_MODE (x) == DFmode
2645 || GET_MODE (x) == TFmode)
2646 && const_zero_operand (x, GET_MODE (x)))
2647 return true;
2648
2649 return false;
2650
2651 default:
2652 break;
2653 }
2654
2655 return true;
2656 }
2657
2658 /* Determine if a given RTX is a valid constant address. */
2659
2660 bool
2661 constant_address_p (rtx x)
2662 {
2663 switch (GET_CODE (x))
2664 {
2665 case LABEL_REF:
2666 case CONST_INT:
2667 case HIGH:
2668 return true;
2669
2670 case CONST:
2671 if (flag_pic && pic_address_needs_scratch (x))
2672 return false;
2673 return legitimate_constant_p (x);
2674
2675 case SYMBOL_REF:
2676 return !flag_pic && legitimate_constant_p (x);
2677
2678 default:
2679 return false;
2680 }
2681 }
2682
2683 /* Nonzero if the constant value X is a legitimate general operand
2684 when generating PIC code. It is given that flag_pic is on and
2685 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2686
2687 bool
2688 legitimate_pic_operand_p (rtx x)
2689 {
2690 if (pic_address_needs_scratch (x))
2691 return false;
2692 if (tls_symbolic_operand (x)
2693 || (GET_CODE (x) == CONST
2694 && GET_CODE (XEXP (x, 0)) == PLUS
2695 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
2696 return false;
2697 return true;
2698 }
2699
2700 /* Return nonzero if ADDR is a valid memory address.
2701 STRICT specifies whether strict register checking applies. */
2702
2703 int
2704 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
2705 {
2706 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
2707
2708 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
2709 rs1 = addr;
2710 else if (GET_CODE (addr) == PLUS)
2711 {
2712 rs1 = XEXP (addr, 0);
2713 rs2 = XEXP (addr, 1);
2714
2715 /* Canonicalize. REG comes first, if there are no regs,
2716 LO_SUM comes first. */
2717 if (!REG_P (rs1)
2718 && GET_CODE (rs1) != SUBREG
2719 && (REG_P (rs2)
2720 || GET_CODE (rs2) == SUBREG
2721 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
2722 {
2723 rs1 = XEXP (addr, 1);
2724 rs2 = XEXP (addr, 0);
2725 }
2726
2727 if ((flag_pic == 1
2728 && rs1 == pic_offset_table_rtx
2729 && !REG_P (rs2)
2730 && GET_CODE (rs2) != SUBREG
2731 && GET_CODE (rs2) != LO_SUM
2732 && GET_CODE (rs2) != MEM
2733 && !tls_symbolic_operand (rs2)
2734 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
2735 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
2736 || ((REG_P (rs1)
2737 || GET_CODE (rs1) == SUBREG)
2738 && RTX_OK_FOR_OFFSET_P (rs2)))
2739 {
2740 imm1 = rs2;
2741 rs2 = NULL;
2742 }
2743 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
2744 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
2745 {
2746 /* We prohibit REG + REG for TFmode when there are no quad move insns
2747 and we consequently need to split. We do this because REG+REG
2748 is not an offsettable address. If we get the situation in reload
2749 where source and destination of a movtf pattern are both MEMs with
2750 REG+REG address, then only one of them gets converted to an
2751 offsettable address. */
2752 if (mode == TFmode
2753 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
2754 return 0;
2755
2756 /* We prohibit REG + REG on ARCH32 if not optimizing for
2757 DFmode/DImode because then mem_min_alignment is likely to be zero
2758 after reload and the forced split would lack a matching splitter
2759 pattern. */
2760 if (TARGET_ARCH32 && !optimize
2761 && (mode == DFmode || mode == DImode))
2762 return 0;
2763 }
2764 else if (USE_AS_OFFSETABLE_LO10
2765 && GET_CODE (rs1) == LO_SUM
2766 && TARGET_ARCH64
2767 && ! TARGET_CM_MEDMID
2768 && RTX_OK_FOR_OLO10_P (rs2))
2769 {
2770 rs2 = NULL;
2771 imm1 = XEXP (rs1, 1);
2772 rs1 = XEXP (rs1, 0);
2773 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
2774 return 0;
2775 }
2776 }
2777 else if (GET_CODE (addr) == LO_SUM)
2778 {
2779 rs1 = XEXP (addr, 0);
2780 imm1 = XEXP (addr, 1);
2781
2782 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
2783 return 0;
2784
2785 /* We can't allow TFmode in 32-bit mode, because an offset greater
2786 than the alignment (8) may cause the LO_SUM to overflow. */
2787 if (mode == TFmode && TARGET_ARCH32)
2788 return 0;
2789 }
2790 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
2791 return 1;
2792 else
2793 return 0;
2794
2795 if (GET_CODE (rs1) == SUBREG)
2796 rs1 = SUBREG_REG (rs1);
2797 if (!REG_P (rs1))
2798 return 0;
2799
2800 if (rs2)
2801 {
2802 if (GET_CODE (rs2) == SUBREG)
2803 rs2 = SUBREG_REG (rs2);
2804 if (!REG_P (rs2))
2805 return 0;
2806 }
2807
2808 if (strict)
2809 {
2810 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
2811 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
2812 return 0;
2813 }
2814 else
2815 {
2816 if ((REGNO (rs1) >= 32
2817 && REGNO (rs1) != FRAME_POINTER_REGNUM
2818 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
2819 || (rs2
2820 && (REGNO (rs2) >= 32
2821 && REGNO (rs2) != FRAME_POINTER_REGNUM
2822 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
2823 return 0;
2824 }
2825 return 1;
2826 }
2827
2828 /* Construct the SYMBOL_REF for the tls_get_offset function. */
2829
2830 static GTY(()) rtx sparc_tls_symbol;
2831 static rtx
2832 sparc_tls_get_addr (void)
2833 {
2834 if (!sparc_tls_symbol)
2835 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
2836
2837 return sparc_tls_symbol;
2838 }
2839
2840 static rtx
2841 sparc_tls_got (void)
2842 {
2843 rtx temp;
2844 if (flag_pic)
2845 {
2846 current_function_uses_pic_offset_table = 1;
2847 return pic_offset_table_rtx;
2848 }
2849
2850 if (!global_offset_table)
2851 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2852 temp = gen_reg_rtx (Pmode);
2853 emit_move_insn (temp, global_offset_table);
2854 return temp;
2855 }
2856
2857
2858 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2859 this (thread-local) address. */
2860
2861 rtx
2862 legitimize_tls_address (rtx addr)
2863 {
2864 rtx temp1, temp2, temp3, ret, o0, got, insn;
2865
2866 gcc_assert (! no_new_pseudos);
2867
2868 if (GET_CODE (addr) == SYMBOL_REF)
2869 switch (SYMBOL_REF_TLS_MODEL (addr))
2870 {
2871 case TLS_MODEL_GLOBAL_DYNAMIC:
2872 start_sequence ();
2873 temp1 = gen_reg_rtx (SImode);
2874 temp2 = gen_reg_rtx (SImode);
2875 ret = gen_reg_rtx (Pmode);
2876 o0 = gen_rtx_REG (Pmode, 8);
2877 got = sparc_tls_got ();
2878 emit_insn (gen_tgd_hi22 (temp1, addr));
2879 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
2880 if (TARGET_ARCH32)
2881 {
2882 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
2883 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
2884 addr, const1_rtx));
2885 }
2886 else
2887 {
2888 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
2889 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
2890 addr, const1_rtx));
2891 }
2892 CALL_INSN_FUNCTION_USAGE (insn)
2893 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
2894 CALL_INSN_FUNCTION_USAGE (insn));
2895 insn = get_insns ();
2896 end_sequence ();
2897 emit_libcall_block (insn, ret, o0, addr);
2898 break;
2899
2900 case TLS_MODEL_LOCAL_DYNAMIC:
2901 start_sequence ();
2902 temp1 = gen_reg_rtx (SImode);
2903 temp2 = gen_reg_rtx (SImode);
2904 temp3 = gen_reg_rtx (Pmode);
2905 ret = gen_reg_rtx (Pmode);
2906 o0 = gen_rtx_REG (Pmode, 8);
2907 got = sparc_tls_got ();
2908 emit_insn (gen_tldm_hi22 (temp1));
2909 emit_insn (gen_tldm_lo10 (temp2, temp1));
2910 if (TARGET_ARCH32)
2911 {
2912 emit_insn (gen_tldm_add32 (o0, got, temp2));
2913 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
2914 const1_rtx));
2915 }
2916 else
2917 {
2918 emit_insn (gen_tldm_add64 (o0, got, temp2));
2919 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
2920 const1_rtx));
2921 }
2922 CALL_INSN_FUNCTION_USAGE (insn)
2923 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
2924 CALL_INSN_FUNCTION_USAGE (insn));
2925 insn = get_insns ();
2926 end_sequence ();
2927 emit_libcall_block (insn, temp3, o0,
2928 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2929 UNSPEC_TLSLD_BASE));
2930 temp1 = gen_reg_rtx (SImode);
2931 temp2 = gen_reg_rtx (SImode);
2932 emit_insn (gen_tldo_hix22 (temp1, addr));
2933 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
2934 if (TARGET_ARCH32)
2935 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
2936 else
2937 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
2938 break;
2939
2940 case TLS_MODEL_INITIAL_EXEC:
2941 temp1 = gen_reg_rtx (SImode);
2942 temp2 = gen_reg_rtx (SImode);
2943 temp3 = gen_reg_rtx (Pmode);
2944 got = sparc_tls_got ();
2945 emit_insn (gen_tie_hi22 (temp1, addr));
2946 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
2947 if (TARGET_ARCH32)
2948 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
2949 else
2950 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
2951 if (TARGET_SUN_TLS)
2952 {
2953 ret = gen_reg_rtx (Pmode);
2954 if (TARGET_ARCH32)
2955 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
2956 temp3, addr));
2957 else
2958 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
2959 temp3, addr));
2960 }
2961 else
2962 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
2963 break;
2964
2965 case TLS_MODEL_LOCAL_EXEC:
2966 temp1 = gen_reg_rtx (Pmode);
2967 temp2 = gen_reg_rtx (Pmode);
2968 if (TARGET_ARCH32)
2969 {
2970 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
2971 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
2972 }
2973 else
2974 {
2975 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
2976 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
2977 }
2978 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
2979 break;
2980
2981 default:
2982 gcc_unreachable ();
2983 }
2984
2985 else
2986 gcc_unreachable (); /* for now ... */
2987
2988 return ret;
2989 }
2990
2991
2992 /* Legitimize PIC addresses. If the address is already position-independent,
2993 we return ORIG. Newly generated position-independent addresses go into a
2994 reg. This is REG if nonzero, otherwise we allocate register(s) as
2995 necessary. */
2996
2997 rtx
2998 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
2999 rtx reg)
3000 {
3001 if (GET_CODE (orig) == SYMBOL_REF)
3002 {
3003 rtx pic_ref, address;
3004 rtx insn;
3005
3006 if (reg == 0)
3007 {
3008 gcc_assert (! reload_in_progress && ! reload_completed);
3009 reg = gen_reg_rtx (Pmode);
3010 }
3011
3012 if (flag_pic == 2)
3013 {
3014 /* If not during reload, allocate another temp reg here for loading
3015 in the address, so that these instructions can be optimized
3016 properly. */
3017 rtx temp_reg = ((reload_in_progress || reload_completed)
3018 ? reg : gen_reg_rtx (Pmode));
3019
3020 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3021 won't get confused into thinking that these two instructions
3022 are loading in the true address of the symbol. If in the
3023 future a PIC rtx exists, that should be used instead. */
3024 if (Pmode == SImode)
3025 {
3026 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3027 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3028 }
3029 else
3030 {
3031 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3032 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3033 }
3034 address = temp_reg;
3035 }
3036 else
3037 address = orig;
3038
3039 pic_ref = gen_const_mem (Pmode,
3040 gen_rtx_PLUS (Pmode,
3041 pic_offset_table_rtx, address));
3042 current_function_uses_pic_offset_table = 1;
3043 insn = emit_move_insn (reg, pic_ref);
3044 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3045 by loop. */
3046 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3047 REG_NOTES (insn));
3048 return reg;
3049 }
3050 else if (GET_CODE (orig) == CONST)
3051 {
3052 rtx base, offset;
3053
3054 if (GET_CODE (XEXP (orig, 0)) == PLUS
3055 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3056 return orig;
3057
3058 if (reg == 0)
3059 {
3060 gcc_assert (! reload_in_progress && ! reload_completed);
3061 reg = gen_reg_rtx (Pmode);
3062 }
3063
3064 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3065 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3066 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3067 base == reg ? 0 : reg);
3068
3069 if (GET_CODE (offset) == CONST_INT)
3070 {
3071 if (SMALL_INT (offset))
3072 return plus_constant (base, INTVAL (offset));
3073 else if (! reload_in_progress && ! reload_completed)
3074 offset = force_reg (Pmode, offset);
3075 else
3076 /* If we reach here, then something is seriously wrong. */
3077 gcc_unreachable ();
3078 }
3079 return gen_rtx_PLUS (Pmode, base, offset);
3080 }
3081 else if (GET_CODE (orig) == LABEL_REF)
3082 /* ??? Why do we do this? */
3083 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3084 the register is live instead, in case it is eliminated. */
3085 current_function_uses_pic_offset_table = 1;
3086
3087 return orig;
3088 }
3089
3090 /* Try machine-dependent ways of modifying an illegitimate address X
3091 to be legitimate. If we find one, return the new, valid address.
3092
3093 OLDX is the address as it was before break_out_memory_refs was called.
3094 In some cases it is useful to look at this to decide what needs to be done.
3095
3096 MODE is the mode of the operand pointed to by X. */
3097
3098 rtx
3099 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3100 {
3101 rtx orig_x = x;
3102
3103 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3104 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3105 force_operand (XEXP (x, 0), NULL_RTX));
3106 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3107 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3108 force_operand (XEXP (x, 1), NULL_RTX));
3109 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3110 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3111 XEXP (x, 1));
3112 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3113 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3114 force_operand (XEXP (x, 1), NULL_RTX));
3115
3116 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3117 return x;
3118
3119 if (tls_symbolic_operand (x))
3120 x = legitimize_tls_address (x);
3121 else if (flag_pic)
3122 x = legitimize_pic_address (x, mode, 0);
3123 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3124 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3125 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3126 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3127 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3128 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3129 else if (GET_CODE (x) == SYMBOL_REF
3130 || GET_CODE (x) == CONST
3131 || GET_CODE (x) == LABEL_REF)
3132 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3133 return x;
3134 }
3135
3136 /* Emit the special PIC helper function. */
3137
3138 static void
3139 emit_pic_helper (void)
3140 {
3141 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3142 int align;
3143
3144 text_section ();
3145
3146 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3147 if (align > 0)
3148 ASM_OUTPUT_ALIGN (asm_out_file, align);
3149 ASM_OUTPUT_LABEL (asm_out_file, pic_helper_symbol_name);
3150 if (flag_delayed_branch)
3151 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
3152 pic_name, pic_name);
3153 else
3154 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
3155 pic_name, pic_name);
3156
3157 pic_helper_emitted_p = true;
3158 }
3159
3160 /* Emit code to load the PIC register. */
3161
3162 static void
3163 load_pic_register (bool delay_pic_helper)
3164 {
3165 int orig_flag_pic = flag_pic;
3166
3167 /* If we haven't initialized the special PIC symbols, do so now. */
3168 if (!pic_helper_symbol_name[0])
3169 {
3170 ASM_GENERATE_INTERNAL_LABEL (pic_helper_symbol_name, "LADDPC", 0);
3171 pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, pic_helper_symbol_name);
3172 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3173 }
3174
3175 /* If we haven't emitted the special PIC helper function, do so now unless
3176 we are requested to delay it. */
3177 if (!delay_pic_helper && !pic_helper_emitted_p)
3178 emit_pic_helper ();
3179
3180 flag_pic = 0;
3181 if (TARGET_ARCH64)
3182 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
3183 pic_helper_symbol));
3184 else
3185 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
3186 pic_helper_symbol));
3187 flag_pic = orig_flag_pic;
3188
3189 /* Need to emit this whether or not we obey regdecls,
3190 since setjmp/longjmp can cause life info to screw up.
3191 ??? In the case where we don't obey regdecls, this is not sufficient
3192 since we may not fall out the bottom. */
3193 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3194 }
3195 \f
3196 /* Return 1 if RTX is a MEM which is known to be aligned to at
3197 least a DESIRED byte boundary. */
3198
3199 int
3200 mem_min_alignment (rtx mem, int desired)
3201 {
3202 rtx addr, base, offset;
3203
3204 /* If it's not a MEM we can't accept it. */
3205 if (GET_CODE (mem) != MEM)
3206 return 0;
3207
3208 /* Obviously... */
3209 if (MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
3210 return 1;
3211
3212 /* ??? The rest of the function predates MEM_ALIGN so
3213 there is probably a bit of redundancy. */
3214 addr = XEXP (mem, 0);
3215 base = offset = NULL_RTX;
3216 if (GET_CODE (addr) == PLUS)
3217 {
3218 if (GET_CODE (XEXP (addr, 0)) == REG)
3219 {
3220 base = XEXP (addr, 0);
3221
3222 /* What we are saying here is that if the base
3223 REG is aligned properly, the compiler will make
3224 sure any REG based index upon it will be so
3225 as well. */
3226 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3227 offset = XEXP (addr, 1);
3228 else
3229 offset = const0_rtx;
3230 }
3231 }
3232 else if (GET_CODE (addr) == REG)
3233 {
3234 base = addr;
3235 offset = const0_rtx;
3236 }
3237
3238 if (base != NULL_RTX)
3239 {
3240 int regno = REGNO (base);
3241
3242 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3243 {
3244 /* Check if the compiler has recorded some information
3245 about the alignment of the base REG. If reload has
3246 completed, we already matched with proper alignments.
3247 If not running global_alloc, reload might give us
3248 unaligned pointer to local stack though. */
3249 if (((cfun != 0
3250 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3251 || (optimize && reload_completed))
3252 && (INTVAL (offset) & (desired - 1)) == 0)
3253 return 1;
3254 }
3255 else
3256 {
3257 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3258 return 1;
3259 }
3260 }
3261 else if (! TARGET_UNALIGNED_DOUBLES
3262 || CONSTANT_P (addr)
3263 || GET_CODE (addr) == LO_SUM)
3264 {
3265 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3266 is true, in which case we can only assume that an access is aligned if
3267 it is to a constant address, or the address involves a LO_SUM. */
3268 return 1;
3269 }
3270
3271 /* An obviously unaligned address. */
3272 return 0;
3273 }
3274
3275 \f
3276 /* Vectors to keep interesting information about registers where it can easily
3277 be got. We used to use the actual mode value as the bit number, but there
3278 are more than 32 modes now. Instead we use two tables: one indexed by
3279 hard register number, and one indexed by mode. */
3280
3281 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3282 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3283 mapped into one sparc_mode_class mode. */
3284
3285 enum sparc_mode_class {
3286 S_MODE, D_MODE, T_MODE, O_MODE,
3287 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3288 CC_MODE, CCFP_MODE
3289 };
3290
3291 /* Modes for single-word and smaller quantities. */
3292 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3293
3294 /* Modes for double-word and smaller quantities. */
3295 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3296
3297 /* Modes for quad-word and smaller quantities. */
3298 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3299
3300 /* Modes for 8-word and smaller quantities. */
3301 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3302
3303 /* Modes for single-float quantities. We must allow any single word or
3304 smaller quantity. This is because the fix/float conversion instructions
3305 take integer inputs/outputs from the float registers. */
3306 #define SF_MODES (S_MODES)
3307
3308 /* Modes for double-float and smaller quantities. */
3309 #define DF_MODES (S_MODES | D_MODES)
3310
3311 /* Modes for double-float only quantities. */
3312 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3313
3314 /* Modes for quad-float only quantities. */
3315 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3316
3317 /* Modes for quad-float and smaller quantities. */
3318 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3319
3320 /* Modes for quad-float and double-float quantities. */
3321 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3322
3323 /* Modes for quad-float pair only quantities. */
3324 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3325
3326 /* Modes for quad-float pairs and smaller quantities. */
3327 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3328
3329 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3330
3331 /* Modes for condition codes. */
3332 #define CC_MODES (1 << (int) CC_MODE)
3333 #define CCFP_MODES (1 << (int) CCFP_MODE)
3334
3335 /* Value is 1 if register/mode pair is acceptable on sparc.
3336 The funny mixture of D and T modes is because integer operations
3337 do not specially operate on tetra quantities, so non-quad-aligned
3338 registers can hold quadword quantities (except %o4 and %i4 because
3339 they cross fixed registers). */
3340
3341 /* This points to either the 32 bit or the 64 bit version. */
3342 const int *hard_regno_mode_classes;
3343
3344 static const int hard_32bit_mode_classes[] = {
3345 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3346 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3347 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3348 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3349
3350 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3351 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3352 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3353 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3354
3355 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3356 and none can hold SFmode/SImode values. */
3357 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3358 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3359 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3360 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3361
3362 /* %fcc[0123] */
3363 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3364
3365 /* %icc */
3366 CC_MODES
3367 };
3368
3369 static const int hard_64bit_mode_classes[] = {
3370 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3371 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3372 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3373 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3374
3375 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3376 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3377 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3378 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3379
3380 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3381 and none can hold SFmode/SImode values. */
3382 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3383 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3384 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3385 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3386
3387 /* %fcc[0123] */
3388 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3389
3390 /* %icc */
3391 CC_MODES
3392 };
3393
3394 int sparc_mode_class [NUM_MACHINE_MODES];
3395
3396 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3397
3398 static void
3399 sparc_init_modes (void)
3400 {
3401 int i;
3402
3403 for (i = 0; i < NUM_MACHINE_MODES; i++)
3404 {
3405 switch (GET_MODE_CLASS (i))
3406 {
3407 case MODE_INT:
3408 case MODE_PARTIAL_INT:
3409 case MODE_COMPLEX_INT:
3410 if (GET_MODE_SIZE (i) <= 4)
3411 sparc_mode_class[i] = 1 << (int) S_MODE;
3412 else if (GET_MODE_SIZE (i) == 8)
3413 sparc_mode_class[i] = 1 << (int) D_MODE;
3414 else if (GET_MODE_SIZE (i) == 16)
3415 sparc_mode_class[i] = 1 << (int) T_MODE;
3416 else if (GET_MODE_SIZE (i) == 32)
3417 sparc_mode_class[i] = 1 << (int) O_MODE;
3418 else
3419 sparc_mode_class[i] = 0;
3420 break;
3421 case MODE_VECTOR_INT:
3422 if (GET_MODE_SIZE (i) <= 4)
3423 sparc_mode_class[i] = 1 << (int)SF_MODE;
3424 else if (GET_MODE_SIZE (i) == 8)
3425 sparc_mode_class[i] = 1 << (int)DF_MODE;
3426 break;
3427 case MODE_FLOAT:
3428 case MODE_COMPLEX_FLOAT:
3429 if (GET_MODE_SIZE (i) <= 4)
3430 sparc_mode_class[i] = 1 << (int) SF_MODE;
3431 else if (GET_MODE_SIZE (i) == 8)
3432 sparc_mode_class[i] = 1 << (int) DF_MODE;
3433 else if (GET_MODE_SIZE (i) == 16)
3434 sparc_mode_class[i] = 1 << (int) TF_MODE;
3435 else if (GET_MODE_SIZE (i) == 32)
3436 sparc_mode_class[i] = 1 << (int) OF_MODE;
3437 else
3438 sparc_mode_class[i] = 0;
3439 break;
3440 case MODE_CC:
3441 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3442 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3443 else
3444 sparc_mode_class[i] = 1 << (int) CC_MODE;
3445 break;
3446 default:
3447 sparc_mode_class[i] = 0;
3448 break;
3449 }
3450 }
3451
3452 if (TARGET_ARCH64)
3453 hard_regno_mode_classes = hard_64bit_mode_classes;
3454 else
3455 hard_regno_mode_classes = hard_32bit_mode_classes;
3456
3457 /* Initialize the array used by REGNO_REG_CLASS. */
3458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3459 {
3460 if (i < 16 && TARGET_V8PLUS)
3461 sparc_regno_reg_class[i] = I64_REGS;
3462 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3463 sparc_regno_reg_class[i] = GENERAL_REGS;
3464 else if (i < 64)
3465 sparc_regno_reg_class[i] = FP_REGS;
3466 else if (i < 96)
3467 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3468 else if (i < 100)
3469 sparc_regno_reg_class[i] = FPCC_REGS;
3470 else
3471 sparc_regno_reg_class[i] = NO_REGS;
3472 }
3473 }
3474 \f
3475 /* Compute the frame size required by the function. This function is called
3476 during the reload pass and also by sparc_expand_prologue. */
3477
3478 HOST_WIDE_INT
3479 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
3480 {
3481 int outgoing_args_size = (current_function_outgoing_args_size
3482 + REG_PARM_STACK_SPACE (current_function_decl));
3483 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
3484 int i;
3485
3486 if (TARGET_ARCH64)
3487 {
3488 for (i = 0; i < 8; i++)
3489 if (regs_ever_live[i] && ! call_used_regs[i])
3490 n_regs += 2;
3491 }
3492 else
3493 {
3494 for (i = 0; i < 8; i += 2)
3495 if ((regs_ever_live[i] && ! call_used_regs[i])
3496 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3497 n_regs += 2;
3498 }
3499
3500 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3501 if ((regs_ever_live[i] && ! call_used_regs[i])
3502 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3503 n_regs += 2;
3504
3505 /* Set up values for use in prologue and epilogue. */
3506 num_gfregs = n_regs;
3507
3508 if (leaf_function_p
3509 && n_regs == 0
3510 && size == 0
3511 && current_function_outgoing_args_size == 0)
3512 actual_fsize = apparent_fsize = 0;
3513 else
3514 {
3515 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3516 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3517 apparent_fsize += n_regs * 4;
3518 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3519 }
3520
3521 /* Make sure nothing can clobber our register windows.
3522 If a SAVE must be done, or there is a stack-local variable,
3523 the register window area must be allocated.
3524 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3525 if (! leaf_function_p || size > 0)
3526 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3527
3528 return SPARC_STACK_ALIGN (actual_fsize);
3529 }
3530
3531 /* Output any necessary .register pseudo-ops. */
3532
3533 void
3534 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
3535 {
3536 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3537 int i;
3538
3539 if (TARGET_ARCH32)
3540 return;
3541
3542 /* Check if %g[2367] were used without
3543 .register being printed for them already. */
3544 for (i = 2; i < 8; i++)
3545 {
3546 if (regs_ever_live [i]
3547 && ! sparc_hard_reg_printed [i])
3548 {
3549 sparc_hard_reg_printed [i] = 1;
3550 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3551 }
3552 if (i == 3) i = 5;
3553 }
3554 #endif
3555 }
3556
3557 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
3558 as needed. LOW should be double-word aligned for 32-bit registers.
3559 Return the new OFFSET. */
3560
3561 #define SORR_SAVE 0
3562 #define SORR_RESTORE 1
3563
3564 static int
3565 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
3566 {
3567 rtx mem, insn;
3568 int i;
3569
3570 if (TARGET_ARCH64 && high <= 32)
3571 {
3572 for (i = low; i < high; i++)
3573 {
3574 if (regs_ever_live[i] && ! call_used_regs[i])
3575 {
3576 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
3577 set_mem_alias_set (mem, sparc_sr_alias_set);
3578 if (action == SORR_SAVE)
3579 {
3580 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
3581 RTX_FRAME_RELATED_P (insn) = 1;
3582 }
3583 else /* action == SORR_RESTORE */
3584 emit_move_insn (gen_rtx_REG (DImode, i), mem);
3585 offset += 8;
3586 }
3587 }
3588 }
3589 else
3590 {
3591 for (i = low; i < high; i += 2)
3592 {
3593 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
3594 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
3595 enum machine_mode mode;
3596 int regno;
3597
3598 if (reg0 && reg1)
3599 {
3600 mode = i < 32 ? DImode : DFmode;
3601 regno = i;
3602 }
3603 else if (reg0)
3604 {
3605 mode = i < 32 ? SImode : SFmode;
3606 regno = i;
3607 }
3608 else if (reg1)
3609 {
3610 mode = i < 32 ? SImode : SFmode;
3611 regno = i + 1;
3612 offset += 4;
3613 }
3614 else
3615 continue;
3616
3617 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
3618 set_mem_alias_set (mem, sparc_sr_alias_set);
3619 if (action == SORR_SAVE)
3620 {
3621 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
3622 RTX_FRAME_RELATED_P (insn) = 1;
3623 }
3624 else /* action == SORR_RESTORE */
3625 emit_move_insn (gen_rtx_REG (mode, regno), mem);
3626
3627 /* Always preserve double-word alignment. */
3628 offset = (offset + 7) & -8;
3629 }
3630 }
3631
3632 return offset;
3633 }
3634
3635 /* Emit code to save call-saved registers. */
3636
3637 static void
3638 emit_save_regs (void)
3639 {
3640 HOST_WIDE_INT offset;
3641 rtx base;
3642
3643 offset = frame_base_offset - apparent_fsize;
3644
3645 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3646 {
3647 /* ??? This might be optimized a little as %g1 might already have a
3648 value close enough that a single add insn will do. */
3649 /* ??? Although, all of this is probably only a temporary fix
3650 because if %g1 can hold a function result, then
3651 sparc_expand_epilogue will lose (the result will be
3652 clobbered). */
3653 base = gen_rtx_REG (Pmode, 1);
3654 emit_move_insn (base, GEN_INT (offset));
3655 emit_insn (gen_rtx_SET (VOIDmode,
3656 base,
3657 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
3658 offset = 0;
3659 }
3660 else
3661 base = frame_base_reg;
3662
3663 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
3664 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
3665 }
3666
3667 /* Emit code to restore call-saved registers. */
3668
3669 static void
3670 emit_restore_regs (void)
3671 {
3672 HOST_WIDE_INT offset;
3673 rtx base;
3674
3675 offset = frame_base_offset - apparent_fsize;
3676
3677 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3678 {
3679 base = gen_rtx_REG (Pmode, 1);
3680 emit_move_insn (base, GEN_INT (offset));
3681 emit_insn (gen_rtx_SET (VOIDmode,
3682 base,
3683 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
3684 offset = 0;
3685 }
3686 else
3687 base = frame_base_reg;
3688
3689 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
3690 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
3691 }
3692
3693 /* Generate a save_register_window insn. */
3694
3695 static rtx
3696 gen_save_register_window (rtx increment)
3697 {
3698 if (TARGET_ARCH64)
3699 return gen_save_register_windowdi (increment);
3700 else
3701 return gen_save_register_windowsi (increment);
3702 }
3703
3704 /* Generate an increment for the stack pointer. */
3705
3706 static rtx
3707 gen_stack_pointer_inc (rtx increment)
3708 {
3709 if (TARGET_ARCH64)
3710 return gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment);
3711 else
3712 return gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment);
3713 }
3714
3715 /* Generate a decrement for the stack pointer. */
3716
3717 static rtx
3718 gen_stack_pointer_dec (rtx decrement)
3719 {
3720 if (TARGET_ARCH64)
3721 return gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement);
3722 else
3723 return gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement);
3724 }
3725
3726 /* Expand the function prologue. The prologue is responsible for reserving
3727 storage for the frame, saving the call-saved registers and loading the
3728 PIC register if needed. */
3729
3730 void
3731 sparc_expand_prologue (void)
3732 {
3733 rtx insn;
3734 int i;
3735
3736 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
3737 on the final value of the flag means deferring the prologue/epilogue
3738 expansion until just before the second scheduling pass, which is too
3739 late to emit multiple epilogues or return insns.
3740
3741 Of course we are making the assumption that the value of the flag
3742 will not change between now and its final value. Of the three parts
3743 of the formula, only the last one can reasonably vary. Let's take a
3744 closer look, after assuming that the first two ones are set to true
3745 (otherwise the last value is effectively silenced).
3746
3747 If only_leaf_regs_used returns false, the global predicate will also
3748 be false so the actual frame size calculated below will be positive.
3749 As a consequence, the save_register_window insn will be emitted in
3750 the instruction stream; now this insn explicitly references %fp
3751 which is not a leaf register so only_leaf_regs_used will always
3752 return false subsequently.
3753
3754 If only_leaf_regs_used returns true, we hope that the subsequent
3755 optimization passes won't cause non-leaf registers to pop up. For
3756 example, the regrename pass has special provisions to not rename to
3757 non-leaf registers in a leaf function. */
3758 sparc_leaf_function_p
3759 = optimize > 0 && leaf_function_p () && only_leaf_regs_used ();
3760
3761 /* Need to use actual_fsize, since we are also allocating
3762 space for our callee (and our own register save area). */
3763 actual_fsize
3764 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
3765
3766 /* Advertise that the data calculated just above are now valid. */
3767 sparc_prologue_data_valid_p = true;
3768
3769 if (sparc_leaf_function_p)
3770 {
3771 frame_base_reg = stack_pointer_rtx;
3772 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3773 }
3774 else
3775 {
3776 frame_base_reg = hard_frame_pointer_rtx;
3777 frame_base_offset = SPARC_STACK_BIAS;
3778 }
3779
3780 if (actual_fsize == 0)
3781 /* do nothing. */ ;
3782 else if (sparc_leaf_function_p)
3783 {
3784 if (actual_fsize <= 4096)
3785 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
3786 else if (actual_fsize <= 8192)
3787 {
3788 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
3789 /* %sp is still the CFA register. */
3790 RTX_FRAME_RELATED_P (insn) = 1;
3791 insn
3792 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
3793 }
3794 else
3795 {
3796 rtx reg = gen_rtx_REG (Pmode, 1);
3797 emit_move_insn (reg, GEN_INT (-actual_fsize));
3798 insn = emit_insn (gen_stack_pointer_inc (reg));
3799 REG_NOTES (insn) =
3800 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3801 PATTERN (gen_stack_pointer_inc (GEN_INT (-actual_fsize))),
3802 REG_NOTES (insn));
3803 }
3804
3805 RTX_FRAME_RELATED_P (insn) = 1;
3806 }
3807 else
3808 {
3809 if (actual_fsize <= 4096)
3810 insn = emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
3811 else if (actual_fsize <= 8192)
3812 {
3813 insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
3814 /* %sp is not the CFA register anymore. */
3815 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
3816 }
3817 else
3818 {
3819 rtx reg = gen_rtx_REG (Pmode, 1);
3820 emit_move_insn (reg, GEN_INT (-actual_fsize));
3821 insn = emit_insn (gen_save_register_window (reg));
3822 }
3823
3824 RTX_FRAME_RELATED_P (insn) = 1;
3825 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
3826 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
3827 }
3828
3829 /* Call-saved registers are saved just above the outgoing argument area. */
3830 if (num_gfregs)
3831 emit_save_regs ();
3832
3833 /* Load the PIC register if needed. */
3834 if (flag_pic && current_function_uses_pic_offset_table)
3835 load_pic_register (false);
3836 }
3837
3838 /* This function generates the assembly code for function entry, which boils
3839 down to emitting the necessary .register directives.
3840
3841 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
3842 an 8-byte block of memory. If any fpu reg is used in the function, we
3843 allocate such a block here, at the bottom of the frame, just in case it's
3844 needed." Could this explain the -8 in emit_restore_regs? */
3845
3846 static void
3847 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3848 {
3849 /* Check that the assumption we made in sparc_expand_prologue is valid. */
3850 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
3851
3852 sparc_output_scratch_registers (file);
3853 }
3854
3855 /* Expand the function epilogue, either normal or part of a sibcall.
3856 We emit all the instructions except the return or the call. */
3857
3858 void
3859 sparc_expand_epilogue (void)
3860 {
3861 if (num_gfregs)
3862 emit_restore_regs ();
3863
3864 if (actual_fsize == 0)
3865 /* do nothing. */ ;
3866 else if (sparc_leaf_function_p)
3867 {
3868 if (actual_fsize <= 4096)
3869 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize)));
3870 else if (actual_fsize <= 8192)
3871 {
3872 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
3873 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize)));
3874 }
3875 else
3876 {
3877 rtx reg = gen_rtx_REG (Pmode, 1);
3878 emit_move_insn (reg, GEN_INT (-actual_fsize));
3879 emit_insn (gen_stack_pointer_dec (reg));
3880 }
3881 }
3882 }
3883
3884 /* Return true if it is appropriate to emit `return' instructions in the
3885 body of a function. */
3886
3887 bool
3888 sparc_can_use_return_insn_p (void)
3889 {
3890 return sparc_prologue_data_valid_p
3891 && (actual_fsize == 0 || !sparc_leaf_function_p);
3892 }
3893
3894 /* This function generates the assembly code for function exit. */
3895
3896 static void
3897 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3898 {
3899 /* If code does not drop into the epilogue, we have to still output
3900 a dummy nop for the sake of sane backtraces. Otherwise, if the
3901 last two instructions of a function were "call foo; dslot;" this
3902 can make the return PC of foo (i.e. address of call instruction
3903 plus 8) point to the first instruction in the next function. */
3904
3905 rtx insn, last_real_insn;
3906
3907 insn = get_last_insn ();
3908
3909 last_real_insn = prev_real_insn (insn);
3910 if (last_real_insn
3911 && GET_CODE (last_real_insn) == INSN
3912 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
3913 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
3914
3915 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
3916 fputs("\tnop\n", file);
3917
3918 sparc_output_deferred_case_vectors ();
3919 }
3920
3921 /* Output a 'restore' instruction. */
3922
3923 static void
3924 output_restore (rtx pat)
3925 {
3926 rtx operands[3];
3927
3928 if (! pat)
3929 {
3930 fputs ("\t restore\n", asm_out_file);
3931 return;
3932 }
3933
3934 gcc_assert (GET_CODE (pat) == SET);
3935
3936 operands[0] = SET_DEST (pat);
3937 pat = SET_SRC (pat);
3938
3939 switch (GET_CODE (pat))
3940 {
3941 case PLUS:
3942 operands[1] = XEXP (pat, 0);
3943 operands[2] = XEXP (pat, 1);
3944 output_asm_insn (" restore %r1, %2, %Y0", operands);
3945 break;
3946 case LO_SUM:
3947 operands[1] = XEXP (pat, 0);
3948 operands[2] = XEXP (pat, 1);
3949 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
3950 break;
3951 case ASHIFT:
3952 operands[1] = XEXP (pat, 0);
3953 gcc_assert (XEXP (pat, 1) == const1_rtx);
3954 output_asm_insn (" restore %r1, %r1, %Y0", operands);
3955 break;
3956 default:
3957 operands[1] = pat;
3958 output_asm_insn (" restore %%g0, %1, %Y0", operands);
3959 break;
3960 }
3961 }
3962
3963 /* Output a return. */
3964
3965 const char *
3966 output_return (rtx insn)
3967 {
3968 if (sparc_leaf_function_p)
3969 {
3970 /* This is a leaf function so we don't have to bother restoring the
3971 register window, which frees us from dealing with the convoluted
3972 semantics of restore/return. We simply output the jump to the
3973 return address and the insn in the delay slot (if any). */
3974
3975 gcc_assert (! current_function_calls_eh_return);
3976
3977 return "jmp\t%%o7+%)%#";
3978 }
3979 else
3980 {
3981 /* This is a regular function so we have to restore the register window.
3982 We may have a pending insn for the delay slot, which will be either
3983 combined with the 'restore' instruction or put in the delay slot of
3984 the 'return' instruction. */
3985
3986 if (current_function_calls_eh_return)
3987 {
3988 /* If the function uses __builtin_eh_return, the eh_return
3989 machinery occupies the delay slot. */
3990 gcc_assert (! final_sequence);
3991
3992 if (! flag_delayed_branch)
3993 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
3994
3995 if (TARGET_V9)
3996 fputs ("\treturn\t%i7+8\n", asm_out_file);
3997 else
3998 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
3999
4000 if (flag_delayed_branch)
4001 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4002 else
4003 fputs ("\t nop\n", asm_out_file);
4004 }
4005 else if (final_sequence)
4006 {
4007 rtx delay, pat;
4008
4009 delay = NEXT_INSN (insn);
4010 gcc_assert (delay);
4011
4012 pat = PATTERN (delay);
4013
4014 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4015 {
4016 epilogue_renumber (&pat, 0);
4017 return "return\t%%i7+%)%#";
4018 }
4019 else
4020 {
4021 output_asm_insn ("jmp\t%%i7+%)", NULL);
4022 output_restore (pat);
4023 PATTERN (delay) = gen_blockage ();
4024 INSN_CODE (delay) = -1;
4025 }
4026 }
4027 else
4028 {
4029 /* The delay slot is empty. */
4030 if (TARGET_V9)
4031 return "return\t%%i7+%)\n\t nop";
4032 else if (flag_delayed_branch)
4033 return "jmp\t%%i7+%)\n\t restore";
4034 else
4035 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4036 }
4037 }
4038
4039 return "";
4040 }
4041
4042 /* Output a sibling call. */
4043
4044 const char *
4045 output_sibcall (rtx insn, rtx call_operand)
4046 {
4047 rtx operands[1];
4048
4049 gcc_assert (flag_delayed_branch);
4050
4051 operands[0] = call_operand;
4052
4053 if (sparc_leaf_function_p)
4054 {
4055 /* This is a leaf function so we don't have to bother restoring the
4056 register window. We simply output the jump to the function and
4057 the insn in the delay slot (if any). */
4058
4059 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
4060
4061 if (final_sequence)
4062 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4063 operands);
4064 else
4065 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4066 it into branch if possible. */
4067 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4068 operands);
4069 }
4070 else
4071 {
4072 /* This is a regular function so we have to restore the register window.
4073 We may have a pending insn for the delay slot, which will be combined
4074 with the 'restore' instruction. */
4075
4076 output_asm_insn ("call\t%a0, 0", operands);
4077
4078 if (final_sequence)
4079 {
4080 rtx delay = NEXT_INSN (insn);
4081 gcc_assert (delay);
4082
4083 output_restore (PATTERN (delay));
4084
4085 PATTERN (delay) = gen_blockage ();
4086 INSN_CODE (delay) = -1;
4087 }
4088 else
4089 output_restore (NULL_RTX);
4090 }
4091
4092 return "";
4093 }
4094 \f
4095 /* Functions for handling argument passing.
4096
4097 For 32-bit, the first 6 args are normally in registers and the rest are
4098 pushed. Any arg that starts within the first 6 words is at least
4099 partially passed in a register unless its data type forbids.
4100
4101 For 64-bit, the argument registers are laid out as an array of 16 elements
4102 and arguments are added sequentially. The first 6 int args and up to the
4103 first 16 fp args (depending on size) are passed in regs.
4104
4105 Slot Stack Integral Float Float in structure Double Long Double
4106 ---- ----- -------- ----- ------------------ ------ -----------
4107 15 [SP+248] %f31 %f30,%f31 %d30
4108 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4109 13 [SP+232] %f27 %f26,%f27 %d26
4110 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4111 11 [SP+216] %f23 %f22,%f23 %d22
4112 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4113 9 [SP+200] %f19 %f18,%f19 %d18
4114 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4115 7 [SP+184] %f15 %f14,%f15 %d14
4116 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4117 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4118 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4119 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4120 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4121 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4122 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4123
4124 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4125
4126 Integral arguments are always passed as 64-bit quantities appropriately
4127 extended.
4128
4129 Passing of floating point values is handled as follows.
4130 If a prototype is in scope:
4131 If the value is in a named argument (i.e. not a stdarg function or a
4132 value not part of the `...') then the value is passed in the appropriate
4133 fp reg.
4134 If the value is part of the `...' and is passed in one of the first 6
4135 slots then the value is passed in the appropriate int reg.
4136 If the value is part of the `...' and is not passed in one of the first 6
4137 slots then the value is passed in memory.
4138 If a prototype is not in scope:
4139 If the value is one of the first 6 arguments the value is passed in the
4140 appropriate integer reg and the appropriate fp reg.
4141 If the value is not one of the first 6 arguments the value is passed in
4142 the appropriate fp reg and in memory.
4143
4144
4145 Summary of the calling conventions implemented by GCC on SPARC:
4146
4147 32-bit ABI:
4148 size argument return value
4149
4150 small integer <4 int. reg. int. reg.
4151 word 4 int. reg. int. reg.
4152 double word 8 int. reg. int. reg.
4153
4154 _Complex small integer <8 int. reg. int. reg.
4155 _Complex word 8 int. reg. int. reg.
4156 _Complex double word 16 memory int. reg.
4157
4158 vector integer <=8 int. reg. FP reg.
4159 vector integer >8 memory memory
4160
4161 float 4 int. reg. FP reg.
4162 double 8 int. reg. FP reg.
4163 long double 16 memory memory
4164
4165 _Complex float 8 memory FP reg.
4166 _Complex double 16 memory FP reg.
4167 _Complex long double 32 memory FP reg.
4168
4169 vector float any memory memory
4170
4171 aggregate any memory memory
4172
4173
4174
4175 64-bit ABI:
4176 size argument return value
4177
4178 small integer <8 int. reg. int. reg.
4179 word 8 int. reg. int. reg.
4180 double word 16 int. reg. int. reg.
4181
4182 _Complex small integer <16 int. reg. int. reg.
4183 _Complex word 16 int. reg. int. reg.
4184 _Complex double word 32 memory int. reg.
4185
4186 vector integer <=16 FP reg. FP reg.
4187 vector integer 16<s<=32 memory FP reg.
4188 vector integer >32 memory memory
4189
4190 float 4 FP reg. FP reg.
4191 double 8 FP reg. FP reg.
4192 long double 16 FP reg. FP reg.
4193
4194 _Complex float 8 FP reg. FP reg.
4195 _Complex double 16 FP reg. FP reg.
4196 _Complex long double 32 memory FP reg.
4197
4198 vector float <=16 FP reg. FP reg.
4199 vector float 16<s<=32 memory FP reg.
4200 vector float >32 memory memory
4201
4202 aggregate <=16 reg. reg.
4203 aggregate 16<s<=32 memory reg.
4204 aggregate >32 memory memory
4205
4206
4207
4208 Note #1: complex floating-point types follow the extended SPARC ABIs as
4209 implemented by the Sun compiler.
4210
4211 Note #2: integral vector types follow the scalar floating-point types
4212 conventions to match what is implemented by the Sun VIS SDK.
4213
4214 Note #3: floating-point vector types follow the aggregate types
4215 conventions. */
4216
4217
4218 /* Maximum number of int regs for args. */
4219 #define SPARC_INT_ARG_MAX 6
4220 /* Maximum number of fp regs for args. */
4221 #define SPARC_FP_ARG_MAX 16
4222
4223 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4224
4225 /* Handle the INIT_CUMULATIVE_ARGS macro.
4226 Initialize a variable CUM of type CUMULATIVE_ARGS
4227 for a call to a function whose data type is FNTYPE.
4228 For a library call, FNTYPE is 0. */
4229
4230 void
4231 init_cumulative_args (struct sparc_args *cum, tree fntype,
4232 rtx libname ATTRIBUTE_UNUSED,
4233 tree fndecl ATTRIBUTE_UNUSED)
4234 {
4235 cum->words = 0;
4236 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4237 cum->libcall_p = fntype == 0;
4238 }
4239
4240 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4241 When a prototype says `char' or `short', really pass an `int'. */
4242
4243 static bool
4244 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4245 {
4246 return TARGET_ARCH32 ? true : false;
4247 }
4248
4249 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4250
4251 static bool
4252 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4253 {
4254 return TARGET_ARCH64 ? true : false;
4255 }
4256
4257 /* Scan the record type TYPE and return the following predicates:
4258 - INTREGS_P: the record contains at least one field or sub-field
4259 that is eligible for promotion in integer registers.
4260 - FP_REGS_P: the record contains at least one field or sub-field
4261 that is eligible for promotion in floating-point registers.
4262 - PACKED_P: the record contains at least one field that is packed.
4263
4264 Sub-fields are not taken into account for the PACKED_P predicate. */
4265
4266 static void
4267 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4268 {
4269 tree field;
4270
4271 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4272 {
4273 if (TREE_CODE (field) == FIELD_DECL)
4274 {
4275 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4276 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4277 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4278 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
4279 && TARGET_FPU)
4280 *fpregs_p = 1;
4281 else
4282 *intregs_p = 1;
4283
4284 if (packed_p && DECL_PACKED (field))
4285 *packed_p = 1;
4286 }
4287 }
4288 }
4289
4290 /* Compute the slot number to pass an argument in.
4291 Return the slot number or -1 if passing on the stack.
4292
4293 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4294 the preceding args and about the function being called.
4295 MODE is the argument's machine mode.
4296 TYPE is the data type of the argument (as a tree).
4297 This is null for libcalls where that information may
4298 not be available.
4299 NAMED is nonzero if this argument is a named parameter
4300 (otherwise it is an extra parameter matching an ellipsis).
4301 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4302 *PREGNO records the register number to use if scalar type.
4303 *PPADDING records the amount of padding needed in words. */
4304
4305 static int
4306 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4307 tree type, int named, int incoming_p,
4308 int *pregno, int *ppadding)
4309 {
4310 int regbase = (incoming_p
4311 ? SPARC_INCOMING_INT_ARG_FIRST
4312 : SPARC_OUTGOING_INT_ARG_FIRST);
4313 int slotno = cum->words;
4314 enum mode_class mclass;
4315 int regno;
4316
4317 *ppadding = 0;
4318
4319 if (type && TREE_ADDRESSABLE (type))
4320 return -1;
4321
4322 if (TARGET_ARCH32
4323 && mode == BLKmode
4324 && type
4325 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4326 return -1;
4327
4328 /* For SPARC64, objects requiring 16-byte alignment get it. */
4329 if (TARGET_ARCH64
4330 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
4331 && (slotno & 1) != 0)
4332 slotno++, *ppadding = 1;
4333
4334 mclass = GET_MODE_CLASS (mode);
4335 if (type && TREE_CODE (type) == VECTOR_TYPE)
4336 {
4337 /* Vector types deserve special treatment because they are
4338 polymorphic wrt their mode, depending upon whether VIS
4339 instructions are enabled. */
4340 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4341 {
4342 /* The SPARC port defines no floating-point vector modes. */
4343 gcc_assert (mode == BLKmode);
4344 }
4345 else
4346 {
4347 /* Integral vector types should either have a vector
4348 mode or an integral mode, because we are guaranteed
4349 by pass_by_reference that their size is not greater
4350 than 16 bytes and TImode is 16-byte wide. */
4351 gcc_assert (mode != BLKmode);
4352
4353 /* Vector integers are handled like floats according to
4354 the Sun VIS SDK. */
4355 mclass = MODE_FLOAT;
4356 }
4357 }
4358
4359 switch (mclass)
4360 {
4361 case MODE_FLOAT:
4362 case MODE_COMPLEX_FLOAT:
4363 if (TARGET_ARCH64 && TARGET_FPU && named)
4364 {
4365 if (slotno >= SPARC_FP_ARG_MAX)
4366 return -1;
4367 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4368 /* Arguments filling only one single FP register are
4369 right-justified in the outer double FP register. */
4370 if (GET_MODE_SIZE (mode) <= 4)
4371 regno++;
4372 break;
4373 }
4374 /* fallthrough */
4375
4376 case MODE_INT:
4377 case MODE_COMPLEX_INT:
4378 if (slotno >= SPARC_INT_ARG_MAX)
4379 return -1;
4380 regno = regbase + slotno;
4381 break;
4382
4383 case MODE_RANDOM:
4384 if (mode == VOIDmode)
4385 /* MODE is VOIDmode when generating the actual call. */
4386 return -1;
4387
4388 gcc_assert (mode == BLKmode);
4389
4390 /* For SPARC64, objects requiring 16-byte alignment get it. */
4391 if (TARGET_ARCH64
4392 && type
4393 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4394 && (slotno & 1) != 0)
4395 slotno++, *ppadding = 1;
4396
4397 if (TARGET_ARCH32 || !type || (TREE_CODE (type) == UNION_TYPE))
4398 {
4399 if (slotno >= SPARC_INT_ARG_MAX)
4400 return -1;
4401 regno = regbase + slotno;
4402 }
4403 else /* TARGET_ARCH64 && type */
4404 {
4405 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
4406
4407 /* First see what kinds of registers we would need. */
4408 if (TREE_CODE (type) == VECTOR_TYPE)
4409 fpregs_p = 1;
4410 else
4411 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
4412
4413 /* The ABI obviously doesn't specify how packed structures
4414 are passed. These are defined to be passed in int regs
4415 if possible, otherwise memory. */
4416 if (packed_p || !named)
4417 fpregs_p = 0, intregs_p = 1;
4418
4419 /* If all arg slots are filled, then must pass on stack. */
4420 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4421 return -1;
4422
4423 /* If there are only int args and all int arg slots are filled,
4424 then must pass on stack. */
4425 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4426 return -1;
4427
4428 /* Note that even if all int arg slots are filled, fp members may
4429 still be passed in regs if such regs are available.
4430 *PREGNO isn't set because there may be more than one, it's up
4431 to the caller to compute them. */
4432 return slotno;
4433 }
4434 break;
4435
4436 default :
4437 gcc_unreachable ();
4438 }
4439
4440 *pregno = regno;
4441 return slotno;
4442 }
4443
4444 /* Handle recursive register counting for structure field layout. */
4445
4446 struct function_arg_record_value_parms
4447 {
4448 rtx ret; /* return expression being built. */
4449 int slotno; /* slot number of the argument. */
4450 int named; /* whether the argument is named. */
4451 int regbase; /* regno of the base register. */
4452 int stack; /* 1 if part of the argument is on the stack. */
4453 int intoffset; /* offset of the first pending integer field. */
4454 unsigned int nregs; /* number of words passed in registers. */
4455 };
4456
4457 static void function_arg_record_value_3
4458 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4459 static void function_arg_record_value_2
4460 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4461 static void function_arg_record_value_1
4462 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4463 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4464 static rtx function_arg_union_value (int, enum machine_mode, int, int);
4465
4466 /* A subroutine of function_arg_record_value. Traverse the structure
4467 recursively and determine how many registers will be required. */
4468
4469 static void
4470 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
4471 struct function_arg_record_value_parms *parms,
4472 bool packed_p)
4473 {
4474 tree field;
4475
4476 /* We need to compute how many registers are needed so we can
4477 allocate the PARALLEL but before we can do that we need to know
4478 whether there are any packed fields. The ABI obviously doesn't
4479 specify how structures are passed in this case, so they are
4480 defined to be passed in int regs if possible, otherwise memory,
4481 regardless of whether there are fp values present. */
4482
4483 if (! packed_p)
4484 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4485 {
4486 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4487 {
4488 packed_p = true;
4489 break;
4490 }
4491 }
4492
4493 /* Compute how many registers we need. */
4494 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4495 {
4496 if (TREE_CODE (field) == FIELD_DECL)
4497 {
4498 HOST_WIDE_INT bitpos = startbitpos;
4499
4500 if (DECL_SIZE (field) != 0)
4501 {
4502 if (integer_zerop (DECL_SIZE (field)))
4503 continue;
4504
4505 if (host_integerp (bit_position (field), 1))
4506 bitpos += int_bit_position (field);
4507 }
4508
4509 /* ??? FIXME: else assume zero offset. */
4510
4511 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4512 function_arg_record_value_1 (TREE_TYPE (field),
4513 bitpos,
4514 parms,
4515 packed_p);
4516 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4517 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
4518 && TARGET_FPU
4519 && parms->named
4520 && ! packed_p)
4521 {
4522 if (parms->intoffset != -1)
4523 {
4524 unsigned int startbit, endbit;
4525 int intslots, this_slotno;
4526
4527 startbit = parms->intoffset & -BITS_PER_WORD;
4528 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4529
4530 intslots = (endbit - startbit) / BITS_PER_WORD;
4531 this_slotno = parms->slotno + parms->intoffset
4532 / BITS_PER_WORD;
4533
4534 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4535 {
4536 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4537 /* We need to pass this field on the stack. */
4538 parms->stack = 1;
4539 }
4540
4541 parms->nregs += intslots;
4542 parms->intoffset = -1;
4543 }
4544
4545 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4546 If it wasn't true we wouldn't be here. */
4547 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
4548 && DECL_MODE (field) == BLKmode)
4549 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
4550 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4551 parms->nregs += 2;
4552 else
4553 parms->nregs += 1;
4554 }
4555 else
4556 {
4557 if (parms->intoffset == -1)
4558 parms->intoffset = bitpos;
4559 }
4560 }
4561 }
4562 }
4563
4564 /* A subroutine of function_arg_record_value. Assign the bits of the
4565 structure between parms->intoffset and bitpos to integer registers. */
4566
4567 static void
4568 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
4569 struct function_arg_record_value_parms *parms)
4570 {
4571 enum machine_mode mode;
4572 unsigned int regno;
4573 unsigned int startbit, endbit;
4574 int this_slotno, intslots, intoffset;
4575 rtx reg;
4576
4577 if (parms->intoffset == -1)
4578 return;
4579
4580 intoffset = parms->intoffset;
4581 parms->intoffset = -1;
4582
4583 startbit = intoffset & -BITS_PER_WORD;
4584 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4585 intslots = (endbit - startbit) / BITS_PER_WORD;
4586 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4587
4588 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4589 if (intslots <= 0)
4590 return;
4591
4592 /* If this is the trailing part of a word, only load that much into
4593 the register. Otherwise load the whole register. Note that in
4594 the latter case we may pick up unwanted bits. It's not a problem
4595 at the moment but may wish to revisit. */
4596
4597 if (intoffset % BITS_PER_WORD != 0)
4598 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4599 MODE_INT);
4600 else
4601 mode = word_mode;
4602
4603 intoffset /= BITS_PER_UNIT;
4604 do
4605 {
4606 regno = parms->regbase + this_slotno;
4607 reg = gen_rtx_REG (mode, regno);
4608 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
4609 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4610
4611 this_slotno += 1;
4612 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4613 mode = word_mode;
4614 parms->nregs += 1;
4615 intslots -= 1;
4616 }
4617 while (intslots > 0);
4618 }
4619
4620 /* A subroutine of function_arg_record_value. Traverse the structure
4621 recursively and assign bits to floating point registers. Track which
4622 bits in between need integer registers; invoke function_arg_record_value_3
4623 to make that happen. */
4624
4625 static void
4626 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
4627 struct function_arg_record_value_parms *parms,
4628 bool packed_p)
4629 {
4630 tree field;
4631
4632 if (! packed_p)
4633 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4634 {
4635 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4636 {
4637 packed_p = true;
4638 break;
4639 }
4640 }
4641
4642 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4643 {
4644 if (TREE_CODE (field) == FIELD_DECL)
4645 {
4646 HOST_WIDE_INT bitpos = startbitpos;
4647
4648 if (DECL_SIZE (field) != 0)
4649 {
4650 if (integer_zerop (DECL_SIZE (field)))
4651 continue;
4652
4653 if (host_integerp (bit_position (field), 1))
4654 bitpos += int_bit_position (field);
4655 }
4656
4657 /* ??? FIXME: else assume zero offset. */
4658
4659 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4660 function_arg_record_value_2 (TREE_TYPE (field),
4661 bitpos,
4662 parms,
4663 packed_p);
4664 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4665 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
4666 && TARGET_FPU
4667 && parms->named
4668 && ! packed_p)
4669 {
4670 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4671 int regno, nregs, pos;
4672 enum machine_mode mode = DECL_MODE (field);
4673 rtx reg;
4674
4675 function_arg_record_value_3 (bitpos, parms);
4676
4677 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
4678 && mode == BLKmode)
4679 {
4680 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
4681 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
4682 }
4683 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4684 {
4685 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
4686 nregs = 2;
4687 }
4688 else
4689 nregs = 1;
4690
4691 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
4692 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
4693 regno++;
4694 reg = gen_rtx_REG (mode, regno);
4695 pos = bitpos / BITS_PER_UNIT;
4696 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
4697 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
4698 parms->nregs += 1;
4699 while (--nregs > 0)
4700 {
4701 regno += GET_MODE_SIZE (mode) / 4;
4702 reg = gen_rtx_REG (mode, regno);
4703 pos += GET_MODE_SIZE (mode);
4704 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
4705 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
4706 parms->nregs += 1;
4707 }
4708 }
4709 else
4710 {
4711 if (parms->intoffset == -1)
4712 parms->intoffset = bitpos;
4713 }
4714 }
4715 }
4716 }
4717
4718 /* Used by function_arg and function_value to implement the complex
4719 conventions of the 64-bit ABI for passing and returning structures.
4720 Return an expression valid as a return value for the two macros
4721 FUNCTION_ARG and FUNCTION_VALUE.
4722
4723 TYPE is the data type of the argument (as a tree).
4724 This is null for libcalls where that information may
4725 not be available.
4726 MODE is the argument's machine mode.
4727 SLOTNO is the index number of the argument's slot in the parameter array.
4728 NAMED is nonzero if this argument is a named parameter
4729 (otherwise it is an extra parameter matching an ellipsis).
4730 REGBASE is the regno of the base register for the parameter array. */
4731
4732 static rtx
4733 function_arg_record_value (tree type, enum machine_mode mode,
4734 int slotno, int named, int regbase)
4735 {
4736 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4737 struct function_arg_record_value_parms parms;
4738 unsigned int nregs;
4739
4740 parms.ret = NULL_RTX;
4741 parms.slotno = slotno;
4742 parms.named = named;
4743 parms.regbase = regbase;
4744 parms.stack = 0;
4745
4746 /* Compute how many registers we need. */
4747 parms.nregs = 0;
4748 parms.intoffset = 0;
4749 function_arg_record_value_1 (type, 0, &parms, false);
4750
4751 /* Take into account pending integer fields. */
4752 if (parms.intoffset != -1)
4753 {
4754 unsigned int startbit, endbit;
4755 int intslots, this_slotno;
4756
4757 startbit = parms.intoffset & -BITS_PER_WORD;
4758 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4759 intslots = (endbit - startbit) / BITS_PER_WORD;
4760 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4761
4762 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4763 {
4764 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4765 /* We need to pass this field on the stack. */
4766 parms.stack = 1;
4767 }
4768
4769 parms.nregs += intslots;
4770 }
4771 nregs = parms.nregs;
4772
4773 /* Allocate the vector and handle some annoying special cases. */
4774 if (nregs == 0)
4775 {
4776 /* ??? Empty structure has no value? Duh? */
4777 if (typesize <= 0)
4778 {
4779 /* Though there's nothing really to store, return a word register
4780 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4781 leads to breakage due to the fact that there are zero bytes to
4782 load. */
4783 return gen_rtx_REG (mode, regbase);
4784 }
4785 else
4786 {
4787 /* ??? C++ has structures with no fields, and yet a size. Give up
4788 for now and pass everything back in integer registers. */
4789 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4790 }
4791 if (nregs + slotno > SPARC_INT_ARG_MAX)
4792 nregs = SPARC_INT_ARG_MAX - slotno;
4793 }
4794 gcc_assert (nregs != 0);
4795
4796 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
4797
4798 /* If at least one field must be passed on the stack, generate
4799 (parallel [(expr_list (nil) ...) ...]) so that all fields will
4800 also be passed on the stack. We can't do much better because the
4801 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
4802 of structures for which the fields passed exclusively in registers
4803 are not at the beginning of the structure. */
4804 if (parms.stack)
4805 XVECEXP (parms.ret, 0, 0)
4806 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4807
4808 /* Fill in the entries. */
4809 parms.nregs = 0;
4810 parms.intoffset = 0;
4811 function_arg_record_value_2 (type, 0, &parms, false);
4812 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4813
4814 gcc_assert (parms.nregs == nregs);
4815
4816 return parms.ret;
4817 }
4818
4819 /* Used by function_arg and function_value to implement the conventions
4820 of the 64-bit ABI for passing and returning unions.
4821 Return an expression valid as a return value for the two macros
4822 FUNCTION_ARG and FUNCTION_VALUE.
4823
4824 SIZE is the size in bytes of the union.
4825 MODE is the argument's machine mode.
4826 REGNO is the hard register the union will be passed in. */
4827
4828 static rtx
4829 function_arg_union_value (int size, enum machine_mode mode, int slotno,
4830 int regno)
4831 {
4832 int nwords = ROUND_ADVANCE (size), i;
4833 rtx regs;
4834
4835 /* See comment in previous function for empty structures. */
4836 if (nwords == 0)
4837 return gen_rtx_REG (mode, regno);
4838
4839 if (slotno == SPARC_INT_ARG_MAX - 1)
4840 nwords = 1;
4841
4842 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
4843
4844 for (i = 0; i < nwords; i++)
4845 {
4846 /* Unions are passed left-justified. */
4847 XVECEXP (regs, 0, i)
4848 = gen_rtx_EXPR_LIST (VOIDmode,
4849 gen_rtx_REG (word_mode, regno),
4850 GEN_INT (UNITS_PER_WORD * i));
4851 regno++;
4852 }
4853
4854 return regs;
4855 }
4856
4857 /* Used by function_arg and function_value to implement the conventions
4858 for passing and returning large (BLKmode) vectors.
4859 Return an expression valid as a return value for the two macros
4860 FUNCTION_ARG and FUNCTION_VALUE.
4861
4862 SIZE is the size in bytes of the vector.
4863 BASE_MODE is the argument's base machine mode.
4864 REGNO is the FP hard register the vector will be passed in. */
4865
4866 static rtx
4867 function_arg_vector_value (int size, enum machine_mode base_mode, int regno)
4868 {
4869 unsigned short base_mode_size = GET_MODE_SIZE (base_mode);
4870 int nregs = size / base_mode_size, i;
4871 rtx regs;
4872
4873 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
4874
4875 for (i = 0; i < nregs; i++)
4876 {
4877 XVECEXP (regs, 0, i)
4878 = gen_rtx_EXPR_LIST (VOIDmode,
4879 gen_rtx_REG (base_mode, regno),
4880 GEN_INT (base_mode_size * i));
4881 regno += base_mode_size / 4;
4882 }
4883
4884 return regs;
4885 }
4886
4887 /* Handle the FUNCTION_ARG macro.
4888 Determine where to put an argument to a function.
4889 Value is zero to push the argument on the stack,
4890 or a hard register in which to store the argument.
4891
4892 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4893 the preceding args and about the function being called.
4894 MODE is the argument's machine mode.
4895 TYPE is the data type of the argument (as a tree).
4896 This is null for libcalls where that information may
4897 not be available.
4898 NAMED is nonzero if this argument is a named parameter
4899 (otherwise it is an extra parameter matching an ellipsis).
4900 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4901
4902 rtx
4903 function_arg (const struct sparc_args *cum, enum machine_mode mode,
4904 tree type, int named, int incoming_p)
4905 {
4906 int regbase = (incoming_p
4907 ? SPARC_INCOMING_INT_ARG_FIRST
4908 : SPARC_OUTGOING_INT_ARG_FIRST);
4909 int slotno, regno, padding;
4910 enum mode_class mclass = GET_MODE_CLASS (mode);
4911 rtx reg;
4912
4913 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4914 &regno, &padding);
4915
4916 if (slotno == -1)
4917 return 0;
4918
4919 if (TARGET_ARCH32)
4920 {
4921 reg = gen_rtx_REG (mode, regno);
4922 return reg;
4923 }
4924
4925 if (type && TREE_CODE (type) == RECORD_TYPE)
4926 {
4927 /* Structures up to 16 bytes in size are passed in arg slots on the
4928 stack and are promoted to registers where possible. */
4929
4930 gcc_assert (int_size_in_bytes (type) <= 16);
4931
4932 return function_arg_record_value (type, mode, slotno, named, regbase);
4933 }
4934 else if (type && TREE_CODE (type) == UNION_TYPE)
4935 {
4936 HOST_WIDE_INT size = int_size_in_bytes (type);
4937
4938 gcc_assert (size <= 16);
4939
4940 return function_arg_union_value (size, mode, slotno, regno);
4941 }
4942 else if (type && TREE_CODE (type) == VECTOR_TYPE)
4943 {
4944 /* Vector types deserve special treatment because they are
4945 polymorphic wrt their mode, depending upon whether VIS
4946 instructions are enabled. */
4947 HOST_WIDE_INT size = int_size_in_bytes (type);
4948
4949 gcc_assert (size <= 16);
4950
4951 if (mode == BLKmode)
4952 return function_arg_vector_value (size,
4953 TYPE_MODE (TREE_TYPE (type)),
4954 SPARC_FP_ARG_FIRST + 2*slotno);
4955 else
4956 mclass = MODE_FLOAT;
4957 }
4958
4959 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4960 but also have the slot allocated for them.
4961 If no prototype is in scope fp values in register slots get passed
4962 in two places, either fp regs and int regs or fp regs and memory. */
4963 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
4964 && SPARC_FP_REG_P (regno))
4965 {
4966 reg = gen_rtx_REG (mode, regno);
4967 if (cum->prototype_p || cum->libcall_p)
4968 {
4969 /* "* 2" because fp reg numbers are recorded in 4 byte
4970 quantities. */
4971 #if 0
4972 /* ??? This will cause the value to be passed in the fp reg and
4973 in the stack. When a prototype exists we want to pass the
4974 value in the reg but reserve space on the stack. That's an
4975 optimization, and is deferred [for a bit]. */
4976 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4977 return gen_rtx_PARALLEL (mode,
4978 gen_rtvec (2,
4979 gen_rtx_EXPR_LIST (VOIDmode,
4980 NULL_RTX, const0_rtx),
4981 gen_rtx_EXPR_LIST (VOIDmode,
4982 reg, const0_rtx)));
4983 else
4984 #else
4985 /* ??? It seems that passing back a register even when past
4986 the area declared by REG_PARM_STACK_SPACE will allocate
4987 space appropriately, and will not copy the data onto the
4988 stack, exactly as we desire.
4989
4990 This is due to locate_and_pad_parm being called in
4991 expand_call whenever reg_parm_stack_space > 0, which
4992 while beneficial to our example here, would seem to be
4993 in error from what had been intended. Ho hum... -- r~ */
4994 #endif
4995 return reg;
4996 }
4997 else
4998 {
4999 rtx v0, v1;
5000
5001 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5002 {
5003 int intreg;
5004
5005 /* On incoming, we don't need to know that the value
5006 is passed in %f0 and %i0, and it confuses other parts
5007 causing needless spillage even on the simplest cases. */
5008 if (incoming_p)
5009 return reg;
5010
5011 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5012 + (regno - SPARC_FP_ARG_FIRST) / 2);
5013
5014 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5015 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5016 const0_rtx);
5017 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5018 }
5019 else
5020 {
5021 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5022 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5023 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5024 }
5025 }
5026 }
5027 else
5028 {
5029 /* Scalar or complex int. */
5030 reg = gen_rtx_REG (mode, regno);
5031 }
5032
5033 return reg;
5034 }
5035
5036 /* For an arg passed partly in registers and partly in memory,
5037 this is the number of bytes of registers used.
5038 For args passed entirely in registers or entirely in memory, zero.
5039
5040 Any arg that starts in the first 6 regs but won't entirely fit in them
5041 needs partial registers on v8. On v9, structures with integer
5042 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5043 values that begin in the last fp reg [where "last fp reg" varies with the
5044 mode] will be split between that reg and memory. */
5045
5046 static int
5047 sparc_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5048 tree type, bool named)
5049 {
5050 int slotno, regno, padding;
5051
5052 /* We pass 0 for incoming_p here, it doesn't matter. */
5053 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5054
5055 if (slotno == -1)
5056 return 0;
5057
5058 if (TARGET_ARCH32)
5059 {
5060 if ((slotno + (mode == BLKmode
5061 ? ROUND_ADVANCE (int_size_in_bytes (type))
5062 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5063 > SPARC_INT_ARG_MAX)
5064 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
5065 }
5066 else
5067 {
5068 /* We are guaranteed by pass_by_reference that the size of the
5069 argument is not greater than 16 bytes, so we only need to return
5070 one word if the argument is partially passed in registers. */
5071
5072 if (type && AGGREGATE_TYPE_P (type))
5073 {
5074 int size = int_size_in_bytes (type);
5075
5076 if (size > UNITS_PER_WORD
5077 && slotno == SPARC_INT_ARG_MAX - 1)
5078 return UNITS_PER_WORD;
5079 }
5080 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5081 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5082 && ! (TARGET_FPU && named)))
5083 {
5084 /* The complex types are passed as packed types. */
5085 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5086 && slotno == SPARC_INT_ARG_MAX - 1)
5087 return UNITS_PER_WORD;
5088 }
5089 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5090 {
5091 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5092 > SPARC_FP_ARG_MAX)
5093 return UNITS_PER_WORD;
5094 }
5095 }
5096
5097 return 0;
5098 }
5099
5100 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5101 Specify whether to pass the argument by reference. */
5102
5103 static bool
5104 sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5105 enum machine_mode mode, tree type,
5106 bool named ATTRIBUTE_UNUSED)
5107 {
5108 if (TARGET_ARCH32)
5109 {
5110 /* Original SPARC 32-bit ABI says that structures and unions,
5111 and quad-precision floats are passed by reference. For Pascal,
5112 also pass arrays by reference. All other base types are passed
5113 in registers.
5114
5115 Extended ABI (as implemented by the Sun compiler) says that all
5116 complex floats are passed by reference. Pass complex integers
5117 in registers up to 8 bytes. More generally, enforce the 2-word
5118 cap for passing arguments in registers.
5119
5120 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5121 integers are passed like floats of the same size, that is in
5122 registers up to 8 bytes. Pass all vector floats by reference
5123 like structure and unions. */
5124 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
5125 || mode == SCmode
5126 /* Catch CDImode, TFmode, DCmode and TCmode. */
5127 || GET_MODE_SIZE (mode) > 8
5128 || (type
5129 && TREE_CODE (type) == VECTOR_TYPE
5130 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
5131 }
5132 else
5133 {
5134 /* Original SPARC 64-bit ABI says that structures and unions
5135 smaller than 16 bytes are passed in registers, as well as
5136 all other base types. For Pascal, pass arrays by reference.
5137
5138 Extended ABI (as implemented by the Sun compiler) says that
5139 complex floats are passed in registers up to 16 bytes. Pass
5140 all complex integers in registers up to 16 bytes. More generally,
5141 enforce the 2-word cap for passing arguments in registers.
5142
5143 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5144 integers are passed like floats of the same size, that is in
5145 registers (up to 16 bytes). Pass all vector floats like structure
5146 and unions. */
5147 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5148 || (type
5149 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
5150 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5151 /* Catch CTImode and TCmode. */
5152 || GET_MODE_SIZE (mode) > 16);
5153 }
5154 }
5155
5156 /* Handle the FUNCTION_ARG_ADVANCE macro.
5157 Update the data in CUM to advance over an argument
5158 of mode MODE and data type TYPE.
5159 TYPE is null for libcalls where that information may not be available. */
5160
5161 void
5162 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5163 tree type, int named)
5164 {
5165 int slotno, regno, padding;
5166
5167 /* We pass 0 for incoming_p here, it doesn't matter. */
5168 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5169
5170 /* If register required leading padding, add it. */
5171 if (slotno != -1)
5172 cum->words += padding;
5173
5174 if (TARGET_ARCH32)
5175 {
5176 cum->words += (mode != BLKmode
5177 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5178 : ROUND_ADVANCE (int_size_in_bytes (type)));
5179 }
5180 else
5181 {
5182 if (type && AGGREGATE_TYPE_P (type))
5183 {
5184 int size = int_size_in_bytes (type);
5185
5186 if (size <= 8)
5187 ++cum->words;
5188 else if (size <= 16)
5189 cum->words += 2;
5190 else /* passed by reference */
5191 ++cum->words;
5192 }
5193 else
5194 {
5195 cum->words += (mode != BLKmode
5196 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5197 : ROUND_ADVANCE (int_size_in_bytes (type)));
5198 }
5199 }
5200 }
5201
5202 /* Handle the FUNCTION_ARG_PADDING macro.
5203 For the 64 bit ABI structs are always stored left shifted in their
5204 argument slot. */
5205
5206 enum direction
5207 function_arg_padding (enum machine_mode mode, tree type)
5208 {
5209 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5210 return upward;
5211
5212 /* Fall back to the default. */
5213 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5214 }
5215
5216 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5217 Specify whether to return the return value in memory. */
5218
5219 static bool
5220 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5221 {
5222 if (TARGET_ARCH32)
5223 /* Original SPARC 32-bit ABI says that structures and unions,
5224 and quad-precision floats are returned in memory. All other
5225 base types are returned in registers.
5226
5227 Extended ABI (as implemented by the Sun compiler) says that
5228 all complex floats are returned in registers (8 FP registers
5229 at most for '_Complex long double'). Return all complex integers
5230 in registers (4 at most for '_Complex long long').
5231
5232 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5233 integers are returned like floats of the same size, that is in
5234 registers up to 8 bytes and in memory otherwise. Return all
5235 vector floats in memory like structure and unions; note that
5236 they always have BLKmode like the latter. */
5237 return (TYPE_MODE (type) == BLKmode
5238 || TYPE_MODE (type) == TFmode
5239 || (TREE_CODE (type) == VECTOR_TYPE
5240 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
5241 else
5242 /* Original SPARC 64-bit ABI says that structures and unions
5243 smaller than 32 bytes are returned in registers, as well as
5244 all other base types.
5245
5246 Extended ABI (as implemented by the Sun compiler) says that all
5247 complex floats are returned in registers (8 FP registers at most
5248 for '_Complex long double'). Return all complex integers in
5249 registers (4 at most for '_Complex TItype').
5250
5251 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5252 integers are returned like floats of the same size, that is in
5253 registers. Return all vector floats like structure and unions;
5254 note that they always have BLKmode like the latter. */
5255 return ((TYPE_MODE (type) == BLKmode
5256 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32));
5257 }
5258
5259 /* Handle the TARGET_STRUCT_VALUE target hook.
5260 Return where to find the structure return value address. */
5261
5262 static rtx
5263 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5264 {
5265 if (TARGET_ARCH64)
5266 return 0;
5267 else
5268 {
5269 rtx mem;
5270
5271 if (incoming)
5272 mem = gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5273 STRUCT_VALUE_OFFSET));
5274 else
5275 mem = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5276 STRUCT_VALUE_OFFSET));
5277
5278 set_mem_alias_set (mem, struct_value_alias_set);
5279 return mem;
5280 }
5281 }
5282
5283 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5284 For v9, function return values are subject to the same rules as arguments,
5285 except that up to 32 bytes may be returned in registers. */
5286
5287 rtx
5288 function_value (tree type, enum machine_mode mode, int incoming_p)
5289 {
5290 /* Beware that the two values are swapped here wrt function_arg. */
5291 int regbase = (incoming_p
5292 ? SPARC_OUTGOING_INT_ARG_FIRST
5293 : SPARC_INCOMING_INT_ARG_FIRST);
5294 enum mode_class mclass = GET_MODE_CLASS (mode);
5295 int regno;
5296
5297 if (type && TREE_CODE (type) == VECTOR_TYPE)
5298 {
5299 /* Vector types deserve special treatment because they are
5300 polymorphic wrt their mode, depending upon whether VIS
5301 instructions are enabled. */
5302 HOST_WIDE_INT size = int_size_in_bytes (type);
5303
5304 gcc_assert ((TARGET_ARCH32 && size <= 8)
5305 || (TARGET_ARCH64 && size <= 32));
5306
5307 if (mode == BLKmode)
5308 return function_arg_vector_value (size,
5309 TYPE_MODE (TREE_TYPE (type)),
5310 SPARC_FP_ARG_FIRST);
5311 else
5312 mclass = MODE_FLOAT;
5313 }
5314 else if (type && TARGET_ARCH64)
5315 {
5316 if (TREE_CODE (type) == RECORD_TYPE)
5317 {
5318 /* Structures up to 32 bytes in size are passed in registers,
5319 promoted to fp registers where possible. */
5320
5321 gcc_assert (int_size_in_bytes (type) <= 32);
5322
5323 return function_arg_record_value (type, mode, 0, 1, regbase);
5324 }
5325 else if (TREE_CODE (type) == UNION_TYPE)
5326 {
5327 HOST_WIDE_INT size = int_size_in_bytes (type);
5328
5329 gcc_assert (size <= 32);
5330
5331 return function_arg_union_value (size, mode, 0, regbase);
5332 }
5333 else if (AGGREGATE_TYPE_P (type))
5334 {
5335 /* All other aggregate types are passed in an integer register
5336 in a mode corresponding to the size of the type. */
5337 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5338
5339 gcc_assert (bytes <= 32);
5340
5341 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5342
5343 /* ??? We probably should have made the same ABI change in
5344 3.4.0 as the one we made for unions. The latter was
5345 required by the SCD though, while the former is not
5346 specified, so we favored compatibility and efficiency.
5347
5348 Now we're stuck for aggregates larger than 16 bytes,
5349 because OImode vanished in the meantime. Let's not
5350 try to be unduly clever, and simply follow the ABI
5351 for unions in that case. */
5352 if (mode == BLKmode)
5353 return function_arg_union_value (bytes, mode, 0, regbase);
5354 else
5355 mclass = MODE_INT;
5356 }
5357 else if (mclass == MODE_INT
5358 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5359 mode = word_mode;
5360 }
5361
5362 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5363 && TARGET_FPU)
5364 regno = SPARC_FP_ARG_FIRST;
5365 else
5366 regno = regbase;
5367
5368 return gen_rtx_REG (mode, regno);
5369 }
5370
5371 /* Do what is necessary for `va_start'. We look at the current function
5372 to determine if stdarg or varargs is used and return the address of
5373 the first unnamed parameter. */
5374
5375 static rtx
5376 sparc_builtin_saveregs (void)
5377 {
5378 int first_reg = current_function_args_info.words;
5379 rtx address;
5380 int regno;
5381
5382 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5383 emit_move_insn (gen_rtx_MEM (word_mode,
5384 gen_rtx_PLUS (Pmode,
5385 frame_pointer_rtx,
5386 GEN_INT (FIRST_PARM_OFFSET (0)
5387 + (UNITS_PER_WORD
5388 * regno)))),
5389 gen_rtx_REG (word_mode,
5390 SPARC_INCOMING_INT_ARG_FIRST + regno));
5391
5392 address = gen_rtx_PLUS (Pmode,
5393 frame_pointer_rtx,
5394 GEN_INT (FIRST_PARM_OFFSET (0)
5395 + UNITS_PER_WORD * first_reg));
5396
5397 return address;
5398 }
5399
5400 /* Implement `va_start' for stdarg. */
5401
5402 void
5403 sparc_va_start (tree valist, rtx nextarg)
5404 {
5405 nextarg = expand_builtin_saveregs ();
5406 std_expand_builtin_va_start (valist, nextarg);
5407 }
5408
5409 /* Implement `va_arg' for stdarg. */
5410
5411 static tree
5412 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5413 {
5414 HOST_WIDE_INT size, rsize, align;
5415 tree addr, incr;
5416 bool indirect;
5417 tree ptrtype = build_pointer_type (type);
5418
5419 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5420 {
5421 indirect = true;
5422 size = rsize = UNITS_PER_WORD;
5423 align = 0;
5424 }
5425 else
5426 {
5427 indirect = false;
5428 size = int_size_in_bytes (type);
5429 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5430 align = 0;
5431
5432 if (TARGET_ARCH64)
5433 {
5434 /* For SPARC64, objects requiring 16-byte alignment get it. */
5435 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5436 align = 2 * UNITS_PER_WORD;
5437
5438 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5439 are left-justified in their slots. */
5440 if (AGGREGATE_TYPE_P (type))
5441 {
5442 if (size == 0)
5443 size = rsize = UNITS_PER_WORD;
5444 else
5445 size = rsize;
5446 }
5447 }
5448 }
5449
5450 incr = valist;
5451 if (align)
5452 {
5453 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
5454 ssize_int (align - 1)));
5455 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
5456 ssize_int (-align)));
5457 }
5458
5459 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
5460 addr = incr;
5461
5462 if (BYTES_BIG_ENDIAN && size < rsize)
5463 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
5464 ssize_int (rsize - size)));
5465
5466 if (indirect)
5467 {
5468 addr = fold_convert (build_pointer_type (ptrtype), addr);
5469 addr = build_va_arg_indirect_ref (addr);
5470 }
5471 /* If the address isn't aligned properly for the type,
5472 we may need to copy to a temporary.
5473 FIXME: This is inefficient. Usually we can do this
5474 in registers. */
5475 else if (align == 0
5476 && TYPE_ALIGN (type) > BITS_PER_WORD)
5477 {
5478 tree tmp = create_tmp_var (type, "va_arg_tmp");
5479 tree dest_addr = build_fold_addr_expr (tmp);
5480
5481 tree copy = build_function_call_expr
5482 (implicit_built_in_decls[BUILT_IN_MEMCPY],
5483 tree_cons (NULL_TREE, dest_addr,
5484 tree_cons (NULL_TREE, addr,
5485 tree_cons (NULL_TREE, size_int (rsize),
5486 NULL_TREE))));
5487
5488 gimplify_and_add (copy, pre_p);
5489 addr = dest_addr;
5490 }
5491 else
5492 addr = fold_convert (ptrtype, addr);
5493
5494 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
5495 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
5496 gimplify_and_add (incr, post_p);
5497
5498 return build_va_arg_indirect_ref (addr);
5499 }
5500 \f
5501 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
5502 Specify whether the vector mode is supported by the hardware. */
5503
5504 static bool
5505 sparc_vector_mode_supported_p (enum machine_mode mode)
5506 {
5507 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
5508 }
5509 \f
5510 /* Return the string to output an unconditional branch to LABEL, which is
5511 the operand number of the label.
5512
5513 DEST is the destination insn (i.e. the label), INSN is the source. */
5514
5515 const char *
5516 output_ubranch (rtx dest, int label, rtx insn)
5517 {
5518 static char string[64];
5519 bool v9_form = false;
5520 char *p;
5521
5522 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
5523 {
5524 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5525 - INSN_ADDRESSES (INSN_UID (insn)));
5526 /* Leave some instructions for "slop". */
5527 if (delta >= -260000 && delta < 260000)
5528 v9_form = true;
5529 }
5530
5531 if (v9_form)
5532 strcpy (string, "ba%*,pt\t%%xcc, ");
5533 else
5534 strcpy (string, "b%*\t");
5535
5536 p = strchr (string, '\0');
5537 *p++ = '%';
5538 *p++ = 'l';
5539 *p++ = '0' + label;
5540 *p++ = '%';
5541 *p++ = '(';
5542 *p = '\0';
5543
5544 return string;
5545 }
5546
5547 /* Return the string to output a conditional branch to LABEL, which is
5548 the operand number of the label. OP is the conditional expression.
5549 XEXP (OP, 0) is assumed to be a condition code register (integer or
5550 floating point) and its mode specifies what kind of comparison we made.
5551
5552 DEST is the destination insn (i.e. the label), INSN is the source.
5553
5554 REVERSED is nonzero if we should reverse the sense of the comparison.
5555
5556 ANNUL is nonzero if we should generate an annulling branch. */
5557
5558 const char *
5559 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5560 rtx insn)
5561 {
5562 static char string[64];
5563 enum rtx_code code = GET_CODE (op);
5564 rtx cc_reg = XEXP (op, 0);
5565 enum machine_mode mode = GET_MODE (cc_reg);
5566 const char *labelno, *branch;
5567 int spaces = 8, far;
5568 char *p;
5569
5570 /* v9 branches are limited to +-1MB. If it is too far away,
5571 change
5572
5573 bne,pt %xcc, .LC30
5574
5575 to
5576
5577 be,pn %xcc, .+12
5578 nop
5579 ba .LC30
5580
5581 and
5582
5583 fbne,a,pn %fcc2, .LC29
5584
5585 to
5586
5587 fbe,pt %fcc2, .+16
5588 nop
5589 ba .LC29 */
5590
5591 far = TARGET_V9 && (get_attr_length (insn) >= 3);
5592 if (reversed ^ far)
5593 {
5594 /* Reversal of FP compares takes care -- an ordered compare
5595 becomes an unordered compare and vice versa. */
5596 if (mode == CCFPmode || mode == CCFPEmode)
5597 code = reverse_condition_maybe_unordered (code);
5598 else
5599 code = reverse_condition (code);
5600 }
5601
5602 /* Start by writing the branch condition. */
5603 if (mode == CCFPmode || mode == CCFPEmode)
5604 {
5605 switch (code)
5606 {
5607 case NE:
5608 branch = "fbne";
5609 break;
5610 case EQ:
5611 branch = "fbe";
5612 break;
5613 case GE:
5614 branch = "fbge";
5615 break;
5616 case GT:
5617 branch = "fbg";
5618 break;
5619 case LE:
5620 branch = "fble";
5621 break;
5622 case LT:
5623 branch = "fbl";
5624 break;
5625 case UNORDERED:
5626 branch = "fbu";
5627 break;
5628 case ORDERED:
5629 branch = "fbo";
5630 break;
5631 case UNGT:
5632 branch = "fbug";
5633 break;
5634 case UNLT:
5635 branch = "fbul";
5636 break;
5637 case UNEQ:
5638 branch = "fbue";
5639 break;
5640 case UNGE:
5641 branch = "fbuge";
5642 break;
5643 case UNLE:
5644 branch = "fbule";
5645 break;
5646 case LTGT:
5647 branch = "fblg";
5648 break;
5649
5650 default:
5651 gcc_unreachable ();
5652 }
5653
5654 /* ??? !v9: FP branches cannot be preceded by another floating point
5655 insn. Because there is currently no concept of pre-delay slots,
5656 we can fix this only by always emitting a nop before a floating
5657 point branch. */
5658
5659 string[0] = '\0';
5660 if (! TARGET_V9)
5661 strcpy (string, "nop\n\t");
5662 strcat (string, branch);
5663 }
5664 else
5665 {
5666 switch (code)
5667 {
5668 case NE:
5669 branch = "bne";
5670 break;
5671 case EQ:
5672 branch = "be";
5673 break;
5674 case GE:
5675 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5676 branch = "bpos";
5677 else
5678 branch = "bge";
5679 break;
5680 case GT:
5681 branch = "bg";
5682 break;
5683 case LE:
5684 branch = "ble";
5685 break;
5686 case LT:
5687 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5688 branch = "bneg";
5689 else
5690 branch = "bl";
5691 break;
5692 case GEU:
5693 branch = "bgeu";
5694 break;
5695 case GTU:
5696 branch = "bgu";
5697 break;
5698 case LEU:
5699 branch = "bleu";
5700 break;
5701 case LTU:
5702 branch = "blu";
5703 break;
5704
5705 default:
5706 gcc_unreachable ();
5707 }
5708 strcpy (string, branch);
5709 }
5710 spaces -= strlen (branch);
5711 p = strchr (string, '\0');
5712
5713 /* Now add the annulling, the label, and a possible noop. */
5714 if (annul && ! far)
5715 {
5716 strcpy (p, ",a");
5717 p += 2;
5718 spaces -= 2;
5719 }
5720
5721 if (TARGET_V9)
5722 {
5723 rtx note;
5724 int v8 = 0;
5725
5726 if (! far && insn && INSN_ADDRESSES_SET_P ())
5727 {
5728 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5729 - INSN_ADDRESSES (INSN_UID (insn)));
5730 /* Leave some instructions for "slop". */
5731 if (delta < -260000 || delta >= 260000)
5732 v8 = 1;
5733 }
5734
5735 if (mode == CCFPmode || mode == CCFPEmode)
5736 {
5737 static char v9_fcc_labelno[] = "%%fccX, ";
5738 /* Set the char indicating the number of the fcc reg to use. */
5739 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5740 labelno = v9_fcc_labelno;
5741 if (v8)
5742 {
5743 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
5744 labelno = "";
5745 }
5746 }
5747 else if (mode == CCXmode || mode == CCX_NOOVmode)
5748 {
5749 labelno = "%%xcc, ";
5750 gcc_assert (! v8);
5751 }
5752 else
5753 {
5754 labelno = "%%icc, ";
5755 if (v8)
5756 labelno = "";
5757 }
5758
5759 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5760 {
5761 strcpy (p,
5762 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5763 ? ",pt" : ",pn");
5764 p += 3;
5765 spaces -= 3;
5766 }
5767 }
5768 else
5769 labelno = "";
5770
5771 if (spaces > 0)
5772 *p++ = '\t';
5773 else
5774 *p++ = ' ';
5775 strcpy (p, labelno);
5776 p = strchr (p, '\0');
5777 if (far)
5778 {
5779 strcpy (p, ".+12\n\t nop\n\tb\t");
5780 /* Skip the next insn if requested or
5781 if we know that it will be a nop. */
5782 if (annul || ! final_sequence)
5783 p[3] = '6';
5784 p += 14;
5785 }
5786 *p++ = '%';
5787 *p++ = 'l';
5788 *p++ = label + '0';
5789 *p++ = '%';
5790 *p++ = '#';
5791 *p = '\0';
5792
5793 return string;
5794 }
5795
5796 /* Emit a library call comparison between floating point X and Y.
5797 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5798 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5799 values as arguments instead of the TFmode registers themselves,
5800 that's why we cannot call emit_float_lib_cmp. */
5801 void
5802 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
5803 {
5804 const char *qpfunc;
5805 rtx slot0, slot1, result, tem, tem2;
5806 enum machine_mode mode;
5807
5808 switch (comparison)
5809 {
5810 case EQ:
5811 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5812 break;
5813
5814 case NE:
5815 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5816 break;
5817
5818 case GT:
5819 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5820 break;
5821
5822 case GE:
5823 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5824 break;
5825
5826 case LT:
5827 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5828 break;
5829
5830 case LE:
5831 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5832 break;
5833
5834 case ORDERED:
5835 case UNORDERED:
5836 case UNGT:
5837 case UNLT:
5838 case UNEQ:
5839 case UNGE:
5840 case UNLE:
5841 case LTGT:
5842 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5843 break;
5844
5845 default:
5846 gcc_unreachable ();
5847 }
5848
5849 if (TARGET_ARCH64)
5850 {
5851 if (GET_CODE (x) != MEM)
5852 {
5853 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5854 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5855 }
5856 else
5857 slot0 = x;
5858
5859 if (GET_CODE (y) != MEM)
5860 {
5861 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5862 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5863 }
5864 else
5865 slot1 = y;
5866
5867 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5868 DImode, 2,
5869 XEXP (slot0, 0), Pmode,
5870 XEXP (slot1, 0), Pmode);
5871
5872 mode = DImode;
5873 }
5874 else
5875 {
5876 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5877 SImode, 2,
5878 x, TFmode, y, TFmode);
5879
5880 mode = SImode;
5881 }
5882
5883
5884 /* Immediately move the result of the libcall into a pseudo
5885 register so reload doesn't clobber the value if it needs
5886 the return register for a spill reg. */
5887 result = gen_reg_rtx (mode);
5888 emit_move_insn (result, hard_libcall_value (mode));
5889
5890 switch (comparison)
5891 {
5892 default:
5893 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
5894 break;
5895 case ORDERED:
5896 case UNORDERED:
5897 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5898 NULL_RTX, mode, 0);
5899 break;
5900 case UNGT:
5901 case UNGE:
5902 emit_cmp_insn (result, const1_rtx,
5903 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
5904 break;
5905 case UNLE:
5906 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
5907 break;
5908 case UNLT:
5909 tem = gen_reg_rtx (mode);
5910 if (TARGET_ARCH32)
5911 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5912 else
5913 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5914 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
5915 break;
5916 case UNEQ:
5917 case LTGT:
5918 tem = gen_reg_rtx (mode);
5919 if (TARGET_ARCH32)
5920 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5921 else
5922 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5923 tem2 = gen_reg_rtx (mode);
5924 if (TARGET_ARCH32)
5925 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5926 else
5927 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5928 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5929 NULL_RTX, mode, 0);
5930 break;
5931 }
5932 }
5933
5934 /* Generate an unsigned DImode to FP conversion. This is the same code
5935 optabs would emit if we didn't have TFmode patterns. */
5936
5937 void
5938 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
5939 {
5940 rtx neglab, donelab, i0, i1, f0, in, out;
5941
5942 out = operands[0];
5943 in = force_reg (DImode, operands[1]);
5944 neglab = gen_label_rtx ();
5945 donelab = gen_label_rtx ();
5946 i0 = gen_reg_rtx (DImode);
5947 i1 = gen_reg_rtx (DImode);
5948 f0 = gen_reg_rtx (mode);
5949
5950 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5951
5952 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5953 emit_jump_insn (gen_jump (donelab));
5954 emit_barrier ();
5955
5956 emit_label (neglab);
5957
5958 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5959 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5960 emit_insn (gen_iordi3 (i0, i0, i1));
5961 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5962 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5963
5964 emit_label (donelab);
5965 }
5966
5967 /* Generate an FP to unsigned DImode conversion. This is the same code
5968 optabs would emit if we didn't have TFmode patterns. */
5969
5970 void
5971 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
5972 {
5973 rtx neglab, donelab, i0, i1, f0, in, out, limit;
5974
5975 out = operands[0];
5976 in = force_reg (mode, operands[1]);
5977 neglab = gen_label_rtx ();
5978 donelab = gen_label_rtx ();
5979 i0 = gen_reg_rtx (DImode);
5980 i1 = gen_reg_rtx (DImode);
5981 limit = gen_reg_rtx (mode);
5982 f0 = gen_reg_rtx (mode);
5983
5984 emit_move_insn (limit,
5985 CONST_DOUBLE_FROM_REAL_VALUE (
5986 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
5987 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
5988
5989 emit_insn (gen_rtx_SET (VOIDmode,
5990 out,
5991 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
5992 emit_jump_insn (gen_jump (donelab));
5993 emit_barrier ();
5994
5995 emit_label (neglab);
5996
5997 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
5998 emit_insn (gen_rtx_SET (VOIDmode,
5999 i0,
6000 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6001 emit_insn (gen_movdi (i1, const1_rtx));
6002 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6003 emit_insn (gen_xordi3 (out, i0, i1));
6004
6005 emit_label (donelab);
6006 }
6007
6008 /* Return the string to output a conditional branch to LABEL, testing
6009 register REG. LABEL is the operand number of the label; REG is the
6010 operand number of the reg. OP is the conditional expression. The mode
6011 of REG says what kind of comparison we made.
6012
6013 DEST is the destination insn (i.e. the label), INSN is the source.
6014
6015 REVERSED is nonzero if we should reverse the sense of the comparison.
6016
6017 ANNUL is nonzero if we should generate an annulling branch. */
6018
6019 const char *
6020 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6021 int annul, rtx insn)
6022 {
6023 static char string[64];
6024 enum rtx_code code = GET_CODE (op);
6025 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6026 rtx note;
6027 int far;
6028 char *p;
6029
6030 /* branch on register are limited to +-128KB. If it is too far away,
6031 change
6032
6033 brnz,pt %g1, .LC30
6034
6035 to
6036
6037 brz,pn %g1, .+12
6038 nop
6039 ba,pt %xcc, .LC30
6040
6041 and
6042
6043 brgez,a,pn %o1, .LC29
6044
6045 to
6046
6047 brlz,pt %o1, .+16
6048 nop
6049 ba,pt %xcc, .LC29 */
6050
6051 far = get_attr_length (insn) >= 3;
6052
6053 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6054 if (reversed ^ far)
6055 code = reverse_condition (code);
6056
6057 /* Only 64 bit versions of these instructions exist. */
6058 gcc_assert (mode == DImode);
6059
6060 /* Start by writing the branch condition. */
6061
6062 switch (code)
6063 {
6064 case NE:
6065 strcpy (string, "brnz");
6066 break;
6067
6068 case EQ:
6069 strcpy (string, "brz");
6070 break;
6071
6072 case GE:
6073 strcpy (string, "brgez");
6074 break;
6075
6076 case LT:
6077 strcpy (string, "brlz");
6078 break;
6079
6080 case LE:
6081 strcpy (string, "brlez");
6082 break;
6083
6084 case GT:
6085 strcpy (string, "brgz");
6086 break;
6087
6088 default:
6089 gcc_unreachable ();
6090 }
6091
6092 p = strchr (string, '\0');
6093
6094 /* Now add the annulling, reg, label, and nop. */
6095 if (annul && ! far)
6096 {
6097 strcpy (p, ",a");
6098 p += 2;
6099 }
6100
6101 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6102 {
6103 strcpy (p,
6104 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6105 ? ",pt" : ",pn");
6106 p += 3;
6107 }
6108
6109 *p = p < string + 8 ? '\t' : ' ';
6110 p++;
6111 *p++ = '%';
6112 *p++ = '0' + reg;
6113 *p++ = ',';
6114 *p++ = ' ';
6115 if (far)
6116 {
6117 int veryfar = 1, delta;
6118
6119 if (INSN_ADDRESSES_SET_P ())
6120 {
6121 delta = (INSN_ADDRESSES (INSN_UID (dest))
6122 - INSN_ADDRESSES (INSN_UID (insn)));
6123 /* Leave some instructions for "slop". */
6124 if (delta >= -260000 && delta < 260000)
6125 veryfar = 0;
6126 }
6127
6128 strcpy (p, ".+12\n\t nop\n\t");
6129 /* Skip the next insn if requested or
6130 if we know that it will be a nop. */
6131 if (annul || ! final_sequence)
6132 p[3] = '6';
6133 p += 12;
6134 if (veryfar)
6135 {
6136 strcpy (p, "b\t");
6137 p += 2;
6138 }
6139 else
6140 {
6141 strcpy (p, "ba,pt\t%%xcc, ");
6142 p += 13;
6143 }
6144 }
6145 *p++ = '%';
6146 *p++ = 'l';
6147 *p++ = '0' + label;
6148 *p++ = '%';
6149 *p++ = '#';
6150 *p = '\0';
6151
6152 return string;
6153 }
6154
6155 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6156 Such instructions cannot be used in the delay slot of return insn on v9.
6157 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6158 */
6159
6160 static int
6161 epilogue_renumber (register rtx *where, int test)
6162 {
6163 register const char *fmt;
6164 register int i;
6165 register enum rtx_code code;
6166
6167 if (*where == 0)
6168 return 0;
6169
6170 code = GET_CODE (*where);
6171
6172 switch (code)
6173 {
6174 case REG:
6175 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6176 return 1;
6177 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6178 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6179 case SCRATCH:
6180 case CC0:
6181 case PC:
6182 case CONST_INT:
6183 case CONST_DOUBLE:
6184 return 0;
6185
6186 /* Do not replace the frame pointer with the stack pointer because
6187 it can cause the delayed instruction to load below the stack.
6188 This occurs when instructions like:
6189
6190 (set (reg/i:SI 24 %i0)
6191 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6192 (const_int -20 [0xffffffec])) 0))
6193
6194 are in the return delayed slot. */
6195 case PLUS:
6196 if (GET_CODE (XEXP (*where, 0)) == REG
6197 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6198 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6199 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6200 return 1;
6201 break;
6202
6203 case MEM:
6204 if (SPARC_STACK_BIAS
6205 && GET_CODE (XEXP (*where, 0)) == REG
6206 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6207 return 1;
6208 break;
6209
6210 default:
6211 break;
6212 }
6213
6214 fmt = GET_RTX_FORMAT (code);
6215
6216 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6217 {
6218 if (fmt[i] == 'E')
6219 {
6220 register int j;
6221 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6222 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6223 return 1;
6224 }
6225 else if (fmt[i] == 'e'
6226 && epilogue_renumber (&(XEXP (*where, i)), test))
6227 return 1;
6228 }
6229 return 0;
6230 }
6231 \f
6232 /* Leaf functions and non-leaf functions have different needs. */
6233
6234 static const int
6235 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6236
6237 static const int
6238 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6239
6240 static const int *const reg_alloc_orders[] = {
6241 reg_leaf_alloc_order,
6242 reg_nonleaf_alloc_order};
6243
6244 void
6245 order_regs_for_local_alloc (void)
6246 {
6247 static int last_order_nonleaf = 1;
6248
6249 if (regs_ever_live[15] != last_order_nonleaf)
6250 {
6251 last_order_nonleaf = !last_order_nonleaf;
6252 memcpy ((char *) reg_alloc_order,
6253 (const char *) reg_alloc_orders[last_order_nonleaf],
6254 FIRST_PSEUDO_REGISTER * sizeof (int));
6255 }
6256 }
6257 \f
6258 /* Return 1 if REG and MEM are legitimate enough to allow the various
6259 mem<-->reg splits to be run. */
6260
6261 int
6262 sparc_splitdi_legitimate (rtx reg, rtx mem)
6263 {
6264 /* Punt if we are here by mistake. */
6265 gcc_assert (reload_completed);
6266
6267 /* We must have an offsettable memory reference. */
6268 if (! offsettable_memref_p (mem))
6269 return 0;
6270
6271 /* If we have legitimate args for ldd/std, we do not want
6272 the split to happen. */
6273 if ((REGNO (reg) % 2) == 0
6274 && mem_min_alignment (mem, 8))
6275 return 0;
6276
6277 /* Success. */
6278 return 1;
6279 }
6280
6281 /* Return 1 if x and y are some kind of REG and they refer to
6282 different hard registers. This test is guaranteed to be
6283 run after reload. */
6284
6285 int
6286 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6287 {
6288 if (GET_CODE (x) != REG)
6289 return 0;
6290 if (GET_CODE (y) != REG)
6291 return 0;
6292 if (REGNO (x) == REGNO (y))
6293 return 0;
6294 return 1;
6295 }
6296
6297 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6298 This makes them candidates for using ldd and std insns.
6299
6300 Note reg1 and reg2 *must* be hard registers. */
6301
6302 int
6303 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6304 {
6305 /* We might have been passed a SUBREG. */
6306 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6307 return 0;
6308
6309 if (REGNO (reg1) % 2 != 0)
6310 return 0;
6311
6312 /* Integer ldd is deprecated in SPARC V9 */
6313 if (TARGET_V9 && REGNO (reg1) < 32)
6314 return 0;
6315
6316 return (REGNO (reg1) == REGNO (reg2) - 1);
6317 }
6318
6319 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6320 an ldd or std insn.
6321
6322 This can only happen when addr1 and addr2, the addresses in mem1
6323 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6324 addr1 must also be aligned on a 64-bit boundary.
6325
6326 Also iff dependent_reg_rtx is not null it should not be used to
6327 compute the address for mem1, i.e. we cannot optimize a sequence
6328 like:
6329 ld [%o0], %o0
6330 ld [%o0 + 4], %o1
6331 to
6332 ldd [%o0], %o0
6333 nor:
6334 ld [%g3 + 4], %g3
6335 ld [%g3], %g2
6336 to
6337 ldd [%g3], %g2
6338
6339 But, note that the transformation from:
6340 ld [%g2 + 4], %g3
6341 ld [%g2], %g2
6342 to
6343 ldd [%g2], %g2
6344 is perfectly fine. Thus, the peephole2 patterns always pass us
6345 the destination register of the first load, never the second one.
6346
6347 For stores we don't have a similar problem, so dependent_reg_rtx is
6348 NULL_RTX. */
6349
6350 int
6351 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6352 {
6353 rtx addr1, addr2;
6354 unsigned int reg1;
6355 HOST_WIDE_INT offset1;
6356
6357 /* The mems cannot be volatile. */
6358 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6359 return 0;
6360
6361 /* MEM1 should be aligned on a 64-bit boundary. */
6362 if (MEM_ALIGN (mem1) < 64)
6363 return 0;
6364
6365 addr1 = XEXP (mem1, 0);
6366 addr2 = XEXP (mem2, 0);
6367
6368 /* Extract a register number and offset (if used) from the first addr. */
6369 if (GET_CODE (addr1) == PLUS)
6370 {
6371 /* If not a REG, return zero. */
6372 if (GET_CODE (XEXP (addr1, 0)) != REG)
6373 return 0;
6374 else
6375 {
6376 reg1 = REGNO (XEXP (addr1, 0));
6377 /* The offset must be constant! */
6378 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6379 return 0;
6380 offset1 = INTVAL (XEXP (addr1, 1));
6381 }
6382 }
6383 else if (GET_CODE (addr1) != REG)
6384 return 0;
6385 else
6386 {
6387 reg1 = REGNO (addr1);
6388 /* This was a simple (mem (reg)) expression. Offset is 0. */
6389 offset1 = 0;
6390 }
6391
6392 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6393 if (GET_CODE (addr2) != PLUS)
6394 return 0;
6395
6396 if (GET_CODE (XEXP (addr2, 0)) != REG
6397 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6398 return 0;
6399
6400 if (reg1 != REGNO (XEXP (addr2, 0)))
6401 return 0;
6402
6403 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6404 return 0;
6405
6406 /* The first offset must be evenly divisible by 8 to ensure the
6407 address is 64 bit aligned. */
6408 if (offset1 % 8 != 0)
6409 return 0;
6410
6411 /* The offset for the second addr must be 4 more than the first addr. */
6412 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6413 return 0;
6414
6415 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6416 instructions. */
6417 return 1;
6418 }
6419
6420 /* Return 1 if reg is a pseudo, or is the first register in
6421 a hard register pair. This makes it a candidate for use in
6422 ldd and std insns. */
6423
6424 int
6425 register_ok_for_ldd (rtx reg)
6426 {
6427 /* We might have been passed a SUBREG. */
6428 if (GET_CODE (reg) != REG)
6429 return 0;
6430
6431 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6432 return (REGNO (reg) % 2 == 0);
6433 else
6434 return 1;
6435 }
6436 \f
6437 /* Print operand X (an rtx) in assembler syntax to file FILE.
6438 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6439 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6440
6441 void
6442 print_operand (FILE *file, rtx x, int code)
6443 {
6444 switch (code)
6445 {
6446 case '#':
6447 /* Output an insn in a delay slot. */
6448 if (final_sequence)
6449 sparc_indent_opcode = 1;
6450 else
6451 fputs ("\n\t nop", file);
6452 return;
6453 case '*':
6454 /* Output an annul flag if there's nothing for the delay slot and we
6455 are optimizing. This is always used with '(' below.
6456 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6457 this is a dbx bug. So, we only do this when optimizing.
6458 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6459 Always emit a nop in case the next instruction is a branch. */
6460 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6461 fputs (",a", file);
6462 return;
6463 case '(':
6464 /* Output a 'nop' if there's nothing for the delay slot and we are
6465 not optimizing. This is always used with '*' above. */
6466 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6467 fputs ("\n\t nop", file);
6468 else if (final_sequence)
6469 sparc_indent_opcode = 1;
6470 return;
6471 case ')':
6472 /* Output the right displacement from the saved PC on function return.
6473 The caller may have placed an "unimp" insn immediately after the call
6474 so we have to account for it. This insn is used in the 32-bit ABI
6475 when calling a function that returns a non zero-sized structure. The
6476 64-bit ABI doesn't have it. Be careful to have this test be the same
6477 as that used on the call. */
6478 if (! TARGET_ARCH64
6479 && current_function_returns_struct
6480 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
6481 == INTEGER_CST)
6482 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
6483 fputs ("12", file);
6484 else
6485 fputc ('8', file);
6486 return;
6487 case '_':
6488 /* Output the Embedded Medium/Anywhere code model base register. */
6489 fputs (EMBMEDANY_BASE_REG, file);
6490 return;
6491 case '&':
6492 /* Print some local dynamic TLS name. */
6493 assemble_name (file, get_some_local_dynamic_name ());
6494 return;
6495
6496 case 'Y':
6497 /* Adjust the operand to take into account a RESTORE operation. */
6498 if (GET_CODE (x) == CONST_INT)
6499 break;
6500 else if (GET_CODE (x) != REG)
6501 output_operand_lossage ("invalid %%Y operand");
6502 else if (REGNO (x) < 8)
6503 fputs (reg_names[REGNO (x)], file);
6504 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6505 fputs (reg_names[REGNO (x)-16], file);
6506 else
6507 output_operand_lossage ("invalid %%Y operand");
6508 return;
6509 case 'L':
6510 /* Print out the low order register name of a register pair. */
6511 if (WORDS_BIG_ENDIAN)
6512 fputs (reg_names[REGNO (x)+1], file);
6513 else
6514 fputs (reg_names[REGNO (x)], file);
6515 return;
6516 case 'H':
6517 /* Print out the high order register name of a register pair. */
6518 if (WORDS_BIG_ENDIAN)
6519 fputs (reg_names[REGNO (x)], file);
6520 else
6521 fputs (reg_names[REGNO (x)+1], file);
6522 return;
6523 case 'R':
6524 /* Print out the second register name of a register pair or quad.
6525 I.e., R (%o0) => %o1. */
6526 fputs (reg_names[REGNO (x)+1], file);
6527 return;
6528 case 'S':
6529 /* Print out the third register name of a register quad.
6530 I.e., S (%o0) => %o2. */
6531 fputs (reg_names[REGNO (x)+2], file);
6532 return;
6533 case 'T':
6534 /* Print out the fourth register name of a register quad.
6535 I.e., T (%o0) => %o3. */
6536 fputs (reg_names[REGNO (x)+3], file);
6537 return;
6538 case 'x':
6539 /* Print a condition code register. */
6540 if (REGNO (x) == SPARC_ICC_REG)
6541 {
6542 /* We don't handle CC[X]_NOOVmode because they're not supposed
6543 to occur here. */
6544 if (GET_MODE (x) == CCmode)
6545 fputs ("%icc", file);
6546 else if (GET_MODE (x) == CCXmode)
6547 fputs ("%xcc", file);
6548 else
6549 gcc_unreachable ();
6550 }
6551 else
6552 /* %fccN register */
6553 fputs (reg_names[REGNO (x)], file);
6554 return;
6555 case 'm':
6556 /* Print the operand's address only. */
6557 output_address (XEXP (x, 0));
6558 return;
6559 case 'r':
6560 /* In this case we need a register. Use %g0 if the
6561 operand is const0_rtx. */
6562 if (x == const0_rtx
6563 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6564 {
6565 fputs ("%g0", file);
6566 return;
6567 }
6568 else
6569 break;
6570
6571 case 'A':
6572 switch (GET_CODE (x))
6573 {
6574 case IOR: fputs ("or", file); break;
6575 case AND: fputs ("and", file); break;
6576 case XOR: fputs ("xor", file); break;
6577 default: output_operand_lossage ("invalid %%A operand");
6578 }
6579 return;
6580
6581 case 'B':
6582 switch (GET_CODE (x))
6583 {
6584 case IOR: fputs ("orn", file); break;
6585 case AND: fputs ("andn", file); break;
6586 case XOR: fputs ("xnor", file); break;
6587 default: output_operand_lossage ("invalid %%B operand");
6588 }
6589 return;
6590
6591 /* These are used by the conditional move instructions. */
6592 case 'c' :
6593 case 'C':
6594 {
6595 enum rtx_code rc = GET_CODE (x);
6596
6597 if (code == 'c')
6598 {
6599 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6600 if (mode == CCFPmode || mode == CCFPEmode)
6601 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6602 else
6603 rc = reverse_condition (GET_CODE (x));
6604 }
6605 switch (rc)
6606 {
6607 case NE: fputs ("ne", file); break;
6608 case EQ: fputs ("e", file); break;
6609 case GE: fputs ("ge", file); break;
6610 case GT: fputs ("g", file); break;
6611 case LE: fputs ("le", file); break;
6612 case LT: fputs ("l", file); break;
6613 case GEU: fputs ("geu", file); break;
6614 case GTU: fputs ("gu", file); break;
6615 case LEU: fputs ("leu", file); break;
6616 case LTU: fputs ("lu", file); break;
6617 case LTGT: fputs ("lg", file); break;
6618 case UNORDERED: fputs ("u", file); break;
6619 case ORDERED: fputs ("o", file); break;
6620 case UNLT: fputs ("ul", file); break;
6621 case UNLE: fputs ("ule", file); break;
6622 case UNGT: fputs ("ug", file); break;
6623 case UNGE: fputs ("uge", file); break;
6624 case UNEQ: fputs ("ue", file); break;
6625 default: output_operand_lossage (code == 'c'
6626 ? "invalid %%c operand"
6627 : "invalid %%C operand");
6628 }
6629 return;
6630 }
6631
6632 /* These are used by the movr instruction pattern. */
6633 case 'd':
6634 case 'D':
6635 {
6636 enum rtx_code rc = (code == 'd'
6637 ? reverse_condition (GET_CODE (x))
6638 : GET_CODE (x));
6639 switch (rc)
6640 {
6641 case NE: fputs ("ne", file); break;
6642 case EQ: fputs ("e", file); break;
6643 case GE: fputs ("gez", file); break;
6644 case LT: fputs ("lz", file); break;
6645 case LE: fputs ("lez", file); break;
6646 case GT: fputs ("gz", file); break;
6647 default: output_operand_lossage (code == 'd'
6648 ? "invalid %%d operand"
6649 : "invalid %%D operand");
6650 }
6651 return;
6652 }
6653
6654 case 'b':
6655 {
6656 /* Print a sign-extended character. */
6657 int i = trunc_int_for_mode (INTVAL (x), QImode);
6658 fprintf (file, "%d", i);
6659 return;
6660 }
6661
6662 case 'f':
6663 /* Operand must be a MEM; write its address. */
6664 if (GET_CODE (x) != MEM)
6665 output_operand_lossage ("invalid %%f operand");
6666 output_address (XEXP (x, 0));
6667 return;
6668
6669 case 's':
6670 {
6671 /* Print a sign-extended 32-bit value. */
6672 HOST_WIDE_INT i;
6673 if (GET_CODE(x) == CONST_INT)
6674 i = INTVAL (x);
6675 else if (GET_CODE(x) == CONST_DOUBLE)
6676 i = CONST_DOUBLE_LOW (x);
6677 else
6678 {
6679 output_operand_lossage ("invalid %%s operand");
6680 return;
6681 }
6682 i = trunc_int_for_mode (i, SImode);
6683 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6684 return;
6685 }
6686
6687 case 0:
6688 /* Do nothing special. */
6689 break;
6690
6691 default:
6692 /* Undocumented flag. */
6693 output_operand_lossage ("invalid operand output code");
6694 }
6695
6696 if (GET_CODE (x) == REG)
6697 fputs (reg_names[REGNO (x)], file);
6698 else if (GET_CODE (x) == MEM)
6699 {
6700 fputc ('[', file);
6701 /* Poor Sun assembler doesn't understand absolute addressing. */
6702 if (CONSTANT_P (XEXP (x, 0)))
6703 fputs ("%g0+", file);
6704 output_address (XEXP (x, 0));
6705 fputc (']', file);
6706 }
6707 else if (GET_CODE (x) == HIGH)
6708 {
6709 fputs ("%hi(", file);
6710 output_addr_const (file, XEXP (x, 0));
6711 fputc (')', file);
6712 }
6713 else if (GET_CODE (x) == LO_SUM)
6714 {
6715 print_operand (file, XEXP (x, 0), 0);
6716 if (TARGET_CM_MEDMID)
6717 fputs ("+%l44(", file);
6718 else
6719 fputs ("+%lo(", file);
6720 output_addr_const (file, XEXP (x, 1));
6721 fputc (')', file);
6722 }
6723 else if (GET_CODE (x) == CONST_DOUBLE
6724 && (GET_MODE (x) == VOIDmode
6725 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6726 {
6727 if (CONST_DOUBLE_HIGH (x) == 0)
6728 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6729 else if (CONST_DOUBLE_HIGH (x) == -1
6730 && CONST_DOUBLE_LOW (x) < 0)
6731 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6732 else
6733 output_operand_lossage ("long long constant not a valid immediate operand");
6734 }
6735 else if (GET_CODE (x) == CONST_DOUBLE)
6736 output_operand_lossage ("floating point constant not a valid immediate operand");
6737 else { output_addr_const (file, x); }
6738 }
6739 \f
6740 /* Target hook for assembling integer objects. The sparc version has
6741 special handling for aligned DI-mode objects. */
6742
6743 static bool
6744 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
6745 {
6746 /* ??? We only output .xword's for symbols and only then in environments
6747 where the assembler can handle them. */
6748 if (aligned_p && size == 8
6749 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6750 {
6751 if (TARGET_V9)
6752 {
6753 assemble_integer_with_op ("\t.xword\t", x);
6754 return true;
6755 }
6756 else
6757 {
6758 assemble_aligned_integer (4, const0_rtx);
6759 assemble_aligned_integer (4, x);
6760 return true;
6761 }
6762 }
6763 return default_assemble_integer (x, size, aligned_p);
6764 }
6765 \f
6766 /* Return the value of a code used in the .proc pseudo-op that says
6767 what kind of result this function returns. For non-C types, we pick
6768 the closest C type. */
6769
6770 #ifndef SHORT_TYPE_SIZE
6771 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6772 #endif
6773
6774 #ifndef INT_TYPE_SIZE
6775 #define INT_TYPE_SIZE BITS_PER_WORD
6776 #endif
6777
6778 #ifndef LONG_TYPE_SIZE
6779 #define LONG_TYPE_SIZE BITS_PER_WORD
6780 #endif
6781
6782 #ifndef LONG_LONG_TYPE_SIZE
6783 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6784 #endif
6785
6786 #ifndef FLOAT_TYPE_SIZE
6787 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6788 #endif
6789
6790 #ifndef DOUBLE_TYPE_SIZE
6791 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6792 #endif
6793
6794 #ifndef LONG_DOUBLE_TYPE_SIZE
6795 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6796 #endif
6797
6798 unsigned long
6799 sparc_type_code (register tree type)
6800 {
6801 register unsigned long qualifiers = 0;
6802 register unsigned shift;
6803
6804 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6805 setting more, since some assemblers will give an error for this. Also,
6806 we must be careful to avoid shifts of 32 bits or more to avoid getting
6807 unpredictable results. */
6808
6809 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6810 {
6811 switch (TREE_CODE (type))
6812 {
6813 case ERROR_MARK:
6814 return qualifiers;
6815
6816 case ARRAY_TYPE:
6817 qualifiers |= (3 << shift);
6818 break;
6819
6820 case FUNCTION_TYPE:
6821 case METHOD_TYPE:
6822 qualifiers |= (2 << shift);
6823 break;
6824
6825 case POINTER_TYPE:
6826 case REFERENCE_TYPE:
6827 case OFFSET_TYPE:
6828 qualifiers |= (1 << shift);
6829 break;
6830
6831 case RECORD_TYPE:
6832 return (qualifiers | 8);
6833
6834 case UNION_TYPE:
6835 case QUAL_UNION_TYPE:
6836 return (qualifiers | 9);
6837
6838 case ENUMERAL_TYPE:
6839 return (qualifiers | 10);
6840
6841 case VOID_TYPE:
6842 return (qualifiers | 16);
6843
6844 case INTEGER_TYPE:
6845 /* If this is a range type, consider it to be the underlying
6846 type. */
6847 if (TREE_TYPE (type) != 0)
6848 break;
6849
6850 /* Carefully distinguish all the standard types of C,
6851 without messing up if the language is not C. We do this by
6852 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
6853 look at both the names and the above fields, but that's redundant.
6854 Any type whose size is between two C types will be considered
6855 to be the wider of the two types. Also, we do not have a
6856 special code to use for "long long", so anything wider than
6857 long is treated the same. Note that we can't distinguish
6858 between "int" and "long" in this code if they are the same
6859 size, but that's fine, since neither can the assembler. */
6860
6861 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6862 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
6863
6864 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6865 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
6866
6867 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6868 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
6869
6870 else
6871 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
6872
6873 case REAL_TYPE:
6874 /* If this is a range type, consider it to be the underlying
6875 type. */
6876 if (TREE_TYPE (type) != 0)
6877 break;
6878
6879 /* Carefully distinguish all the standard types of C,
6880 without messing up if the language is not C. */
6881
6882 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6883 return (qualifiers | 6);
6884
6885 else
6886 return (qualifiers | 7);
6887
6888 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6889 /* ??? We need to distinguish between double and float complex types,
6890 but I don't know how yet because I can't reach this code from
6891 existing front-ends. */
6892 return (qualifiers | 7); /* Who knows? */
6893
6894 case VECTOR_TYPE:
6895 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6896 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6897 case LANG_TYPE: /* ? */
6898 return qualifiers;
6899
6900 default:
6901 gcc_unreachable (); /* Not a type! */
6902 }
6903 }
6904
6905 return qualifiers;
6906 }
6907 \f
6908 /* Nested function support. */
6909
6910 /* Emit RTL insns to initialize the variable parts of a trampoline.
6911 FNADDR is an RTX for the address of the function's pure code.
6912 CXT is an RTX for the static chain value for the function.
6913
6914 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6915 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6916 (to store insns). This is a bit excessive. Perhaps a different
6917 mechanism would be better here.
6918
6919 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6920
6921 void
6922 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
6923 {
6924 /* SPARC 32-bit trampoline:
6925
6926 sethi %hi(fn), %g1
6927 sethi %hi(static), %g2
6928 jmp %g1+%lo(fn)
6929 or %g2, %lo(static), %g2
6930
6931 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6932 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6933 */
6934
6935 emit_move_insn
6936 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6937 expand_binop (SImode, ior_optab,
6938 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6939 size_int (10), 0, 1),
6940 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6941 NULL_RTX, 1, OPTAB_DIRECT));
6942
6943 emit_move_insn
6944 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6945 expand_binop (SImode, ior_optab,
6946 expand_shift (RSHIFT_EXPR, SImode, cxt,
6947 size_int (10), 0, 1),
6948 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6949 NULL_RTX, 1, OPTAB_DIRECT));
6950
6951 emit_move_insn
6952 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6953 expand_binop (SImode, ior_optab,
6954 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6955 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6956 NULL_RTX, 1, OPTAB_DIRECT));
6957
6958 emit_move_insn
6959 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6960 expand_binop (SImode, ior_optab,
6961 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6962 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6963 NULL_RTX, 1, OPTAB_DIRECT));
6964
6965 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6966 aligned on a 16 byte boundary so one flush clears it all. */
6967 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6968 if (sparc_cpu != PROCESSOR_ULTRASPARC
6969 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6970 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6971 plus_constant (tramp, 8)))));
6972
6973 /* Call __enable_execute_stack after writing onto the stack to make sure
6974 the stack address is accessible. */
6975 #ifdef ENABLE_EXECUTE_STACK
6976 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
6977 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6978 #endif
6979
6980 }
6981
6982 /* The 64-bit version is simpler because it makes more sense to load the
6983 values as "immediate" data out of the trampoline. It's also easier since
6984 we can read the PC without clobbering a register. */
6985
6986 void
6987 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
6988 {
6989 /* SPARC 64-bit trampoline:
6990
6991 rd %pc, %g1
6992 ldx [%g1+24], %g5
6993 jmp %g5
6994 ldx [%g1+16], %g5
6995 +16 bytes data
6996 */
6997
6998 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6999 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7000 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7001 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7002 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7003 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7004 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7005 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7006 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7007 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7008 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7009
7010 if (sparc_cpu != PROCESSOR_ULTRASPARC
7011 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7012 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7013
7014 /* Call __enable_execute_stack after writing onto the stack to make sure
7015 the stack address is accessible. */
7016 #ifdef ENABLE_EXECUTE_STACK
7017 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7018 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7019 #endif
7020 }
7021 \f
7022 /* Adjust the cost of a scheduling dependency. Return the new cost of
7023 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7024
7025 static int
7026 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7027 {
7028 enum attr_type insn_type;
7029
7030 if (! recog_memoized (insn))
7031 return 0;
7032
7033 insn_type = get_attr_type (insn);
7034
7035 if (REG_NOTE_KIND (link) == 0)
7036 {
7037 /* Data dependency; DEP_INSN writes a register that INSN reads some
7038 cycles later. */
7039
7040 /* if a load, then the dependence must be on the memory address;
7041 add an extra "cycle". Note that the cost could be two cycles
7042 if the reg was written late in an instruction group; we ca not tell
7043 here. */
7044 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7045 return cost + 3;
7046
7047 /* Get the delay only if the address of the store is the dependence. */
7048 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7049 {
7050 rtx pat = PATTERN(insn);
7051 rtx dep_pat = PATTERN (dep_insn);
7052
7053 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7054 return cost; /* This should not happen! */
7055
7056 /* The dependency between the two instructions was on the data that
7057 is being stored. Assume that this implies that the address of the
7058 store is not dependent. */
7059 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7060 return cost;
7061
7062 return cost + 3; /* An approximation. */
7063 }
7064
7065 /* A shift instruction cannot receive its data from an instruction
7066 in the same cycle; add a one cycle penalty. */
7067 if (insn_type == TYPE_SHIFT)
7068 return cost + 3; /* Split before cascade into shift. */
7069 }
7070 else
7071 {
7072 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7073 INSN writes some cycles later. */
7074
7075 /* These are only significant for the fpu unit; writing a fp reg before
7076 the fpu has finished with it stalls the processor. */
7077
7078 /* Reusing an integer register causes no problems. */
7079 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7080 return 0;
7081 }
7082
7083 return cost;
7084 }
7085
7086 static int
7087 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7088 {
7089 enum attr_type insn_type, dep_type;
7090 rtx pat = PATTERN(insn);
7091 rtx dep_pat = PATTERN (dep_insn);
7092
7093 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7094 return cost;
7095
7096 insn_type = get_attr_type (insn);
7097 dep_type = get_attr_type (dep_insn);
7098
7099 switch (REG_NOTE_KIND (link))
7100 {
7101 case 0:
7102 /* Data dependency; DEP_INSN writes a register that INSN reads some
7103 cycles later. */
7104
7105 switch (insn_type)
7106 {
7107 case TYPE_STORE:
7108 case TYPE_FPSTORE:
7109 /* Get the delay iff the address of the store is the dependence. */
7110 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7111 return cost;
7112
7113 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7114 return cost;
7115 return cost + 3;
7116
7117 case TYPE_LOAD:
7118 case TYPE_SLOAD:
7119 case TYPE_FPLOAD:
7120 /* If a load, then the dependence must be on the memory address. If
7121 the addresses aren't equal, then it might be a false dependency */
7122 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7123 {
7124 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7125 || GET_CODE (SET_DEST (dep_pat)) != MEM
7126 || GET_CODE (SET_SRC (pat)) != MEM
7127 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7128 XEXP (SET_SRC (pat), 0)))
7129 return cost + 2;
7130
7131 return cost + 8;
7132 }
7133 break;
7134
7135 case TYPE_BRANCH:
7136 /* Compare to branch latency is 0. There is no benefit from
7137 separating compare and branch. */
7138 if (dep_type == TYPE_COMPARE)
7139 return 0;
7140 /* Floating point compare to branch latency is less than
7141 compare to conditional move. */
7142 if (dep_type == TYPE_FPCMP)
7143 return cost - 1;
7144 break;
7145 default:
7146 break;
7147 }
7148 break;
7149
7150 case REG_DEP_ANTI:
7151 /* Anti-dependencies only penalize the fpu unit. */
7152 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7153 return 0;
7154 break;
7155
7156 default:
7157 break;
7158 }
7159
7160 return cost;
7161 }
7162
7163 static int
7164 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7165 {
7166 switch (sparc_cpu)
7167 {
7168 case PROCESSOR_SUPERSPARC:
7169 cost = supersparc_adjust_cost (insn, link, dep, cost);
7170 break;
7171 case PROCESSOR_HYPERSPARC:
7172 case PROCESSOR_SPARCLITE86X:
7173 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7174 break;
7175 default:
7176 break;
7177 }
7178 return cost;
7179 }
7180
7181 static void
7182 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7183 int sched_verbose ATTRIBUTE_UNUSED,
7184 int max_ready ATTRIBUTE_UNUSED)
7185 {
7186 }
7187
7188 static int
7189 sparc_use_sched_lookahead (void)
7190 {
7191 if (sparc_cpu == PROCESSOR_ULTRASPARC
7192 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7193 return 4;
7194 if ((1 << sparc_cpu) &
7195 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7196 (1 << PROCESSOR_SPARCLITE86X)))
7197 return 3;
7198 return 0;
7199 }
7200
7201 static int
7202 sparc_issue_rate (void)
7203 {
7204 switch (sparc_cpu)
7205 {
7206 default:
7207 return 1;
7208 case PROCESSOR_V9:
7209 /* Assume V9 processors are capable of at least dual-issue. */
7210 return 2;
7211 case PROCESSOR_SUPERSPARC:
7212 return 3;
7213 case PROCESSOR_HYPERSPARC:
7214 case PROCESSOR_SPARCLITE86X:
7215 return 2;
7216 case PROCESSOR_ULTRASPARC:
7217 case PROCESSOR_ULTRASPARC3:
7218 return 4;
7219 }
7220 }
7221
7222 static int
7223 set_extends (rtx insn)
7224 {
7225 register rtx pat = PATTERN (insn);
7226
7227 switch (GET_CODE (SET_SRC (pat)))
7228 {
7229 /* Load and some shift instructions zero extend. */
7230 case MEM:
7231 case ZERO_EXTEND:
7232 /* sethi clears the high bits */
7233 case HIGH:
7234 /* LO_SUM is used with sethi. sethi cleared the high
7235 bits and the values used with lo_sum are positive */
7236 case LO_SUM:
7237 /* Store flag stores 0 or 1 */
7238 case LT: case LTU:
7239 case GT: case GTU:
7240 case LE: case LEU:
7241 case GE: case GEU:
7242 case EQ:
7243 case NE:
7244 return 1;
7245 case AND:
7246 {
7247 rtx op0 = XEXP (SET_SRC (pat), 0);
7248 rtx op1 = XEXP (SET_SRC (pat), 1);
7249 if (GET_CODE (op1) == CONST_INT)
7250 return INTVAL (op1) >= 0;
7251 if (GET_CODE (op0) != REG)
7252 return 0;
7253 if (sparc_check_64 (op0, insn) == 1)
7254 return 1;
7255 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7256 }
7257 case IOR:
7258 case XOR:
7259 {
7260 rtx op0 = XEXP (SET_SRC (pat), 0);
7261 rtx op1 = XEXP (SET_SRC (pat), 1);
7262 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7263 return 0;
7264 if (GET_CODE (op1) == CONST_INT)
7265 return INTVAL (op1) >= 0;
7266 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7267 }
7268 case LSHIFTRT:
7269 return GET_MODE (SET_SRC (pat)) == SImode;
7270 /* Positive integers leave the high bits zero. */
7271 case CONST_DOUBLE:
7272 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7273 case CONST_INT:
7274 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7275 case ASHIFTRT:
7276 case SIGN_EXTEND:
7277 return - (GET_MODE (SET_SRC (pat)) == SImode);
7278 case REG:
7279 return sparc_check_64 (SET_SRC (pat), insn);
7280 default:
7281 return 0;
7282 }
7283 }
7284
7285 /* We _ought_ to have only one kind per function, but... */
7286 static GTY(()) rtx sparc_addr_diff_list;
7287 static GTY(()) rtx sparc_addr_list;
7288
7289 void
7290 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7291 {
7292 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7293 if (diff)
7294 sparc_addr_diff_list
7295 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7296 else
7297 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7298 }
7299
7300 static void
7301 sparc_output_addr_vec (rtx vec)
7302 {
7303 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7304 int idx, vlen = XVECLEN (body, 0);
7305
7306 #ifdef ASM_OUTPUT_ADDR_VEC_START
7307 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7308 #endif
7309
7310 #ifdef ASM_OUTPUT_CASE_LABEL
7311 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7312 NEXT_INSN (lab));
7313 #else
7314 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7315 #endif
7316
7317 for (idx = 0; idx < vlen; idx++)
7318 {
7319 ASM_OUTPUT_ADDR_VEC_ELT
7320 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7321 }
7322
7323 #ifdef ASM_OUTPUT_ADDR_VEC_END
7324 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7325 #endif
7326 }
7327
7328 static void
7329 sparc_output_addr_diff_vec (rtx vec)
7330 {
7331 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7332 rtx base = XEXP (XEXP (body, 0), 0);
7333 int idx, vlen = XVECLEN (body, 1);
7334
7335 #ifdef ASM_OUTPUT_ADDR_VEC_START
7336 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7337 #endif
7338
7339 #ifdef ASM_OUTPUT_CASE_LABEL
7340 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7341 NEXT_INSN (lab));
7342 #else
7343 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7344 #endif
7345
7346 for (idx = 0; idx < vlen; idx++)
7347 {
7348 ASM_OUTPUT_ADDR_DIFF_ELT
7349 (asm_out_file,
7350 body,
7351 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7352 CODE_LABEL_NUMBER (base));
7353 }
7354
7355 #ifdef ASM_OUTPUT_ADDR_VEC_END
7356 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7357 #endif
7358 }
7359
7360 static void
7361 sparc_output_deferred_case_vectors (void)
7362 {
7363 rtx t;
7364 int align;
7365
7366 if (sparc_addr_list == NULL_RTX
7367 && sparc_addr_diff_list == NULL_RTX)
7368 return;
7369
7370 /* Align to cache line in the function's code section. */
7371 current_function_section (current_function_decl);
7372
7373 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7374 if (align > 0)
7375 ASM_OUTPUT_ALIGN (asm_out_file, align);
7376
7377 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7378 sparc_output_addr_vec (XEXP (t, 0));
7379 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7380 sparc_output_addr_diff_vec (XEXP (t, 0));
7381
7382 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7383 }
7384
7385 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7386 unknown. Return 1 if the high bits are zero, -1 if the register is
7387 sign extended. */
7388 int
7389 sparc_check_64 (rtx x, rtx insn)
7390 {
7391 /* If a register is set only once it is safe to ignore insns this
7392 code does not know how to handle. The loop will either recognize
7393 the single set and return the correct value or fail to recognize
7394 it and return 0. */
7395 int set_once = 0;
7396 rtx y = x;
7397
7398 gcc_assert (GET_CODE (x) == REG);
7399
7400 if (GET_MODE (x) == DImode)
7401 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7402
7403 if (flag_expensive_optimizations
7404 && REG_N_SETS (REGNO (y)) == 1)
7405 set_once = 1;
7406
7407 if (insn == 0)
7408 {
7409 if (set_once)
7410 insn = get_last_insn_anywhere ();
7411 else
7412 return 0;
7413 }
7414
7415 while ((insn = PREV_INSN (insn)))
7416 {
7417 switch (GET_CODE (insn))
7418 {
7419 case JUMP_INSN:
7420 case NOTE:
7421 break;
7422 case CODE_LABEL:
7423 case CALL_INSN:
7424 default:
7425 if (! set_once)
7426 return 0;
7427 break;
7428 case INSN:
7429 {
7430 rtx pat = PATTERN (insn);
7431 if (GET_CODE (pat) != SET)
7432 return 0;
7433 if (rtx_equal_p (x, SET_DEST (pat)))
7434 return set_extends (insn);
7435 if (y && rtx_equal_p (y, SET_DEST (pat)))
7436 return set_extends (insn);
7437 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7438 return 0;
7439 }
7440 }
7441 }
7442 return 0;
7443 }
7444
7445 /* Returns assembly code to perform a DImode shift using
7446 a 64-bit global or out register on SPARC-V8+. */
7447 const char *
7448 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
7449 {
7450 static char asm_code[60];
7451
7452 /* The scratch register is only required when the destination
7453 register is not a 64-bit global or out register. */
7454 if (which_alternative != 2)
7455 operands[3] = operands[0];
7456
7457 /* We can only shift by constants <= 63. */
7458 if (GET_CODE (operands[2]) == CONST_INT)
7459 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7460
7461 if (GET_CODE (operands[1]) == CONST_INT)
7462 {
7463 output_asm_insn ("mov\t%1, %3", operands);
7464 }
7465 else
7466 {
7467 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7468 if (sparc_check_64 (operands[1], insn) <= 0)
7469 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7470 output_asm_insn ("or\t%L1, %3, %3", operands);
7471 }
7472
7473 strcpy(asm_code, opcode);
7474
7475 if (which_alternative != 2)
7476 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7477 else
7478 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7479 }
7480 \f
7481 /* Output rtl to increment the profiler label LABELNO
7482 for profiling a function entry. */
7483
7484 void
7485 sparc_profile_hook (int labelno)
7486 {
7487 char buf[32];
7488 rtx lab, fun;
7489
7490 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7491 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7492 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
7493
7494 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7495 }
7496 \f
7497 #ifdef OBJECT_FORMAT_ELF
7498 static void
7499 sparc_elf_asm_named_section (const char *name, unsigned int flags,
7500 tree decl)
7501 {
7502 if (flags & SECTION_MERGE)
7503 {
7504 /* entsize cannot be expressed in this section attributes
7505 encoding style. */
7506 default_elf_asm_named_section (name, flags, decl);
7507 return;
7508 }
7509
7510 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
7511
7512 if (!(flags & SECTION_DEBUG))
7513 fputs (",#alloc", asm_out_file);
7514 if (flags & SECTION_WRITE)
7515 fputs (",#write", asm_out_file);
7516 if (flags & SECTION_TLS)
7517 fputs (",#tls", asm_out_file);
7518 if (flags & SECTION_CODE)
7519 fputs (",#execinstr", asm_out_file);
7520
7521 /* ??? Handle SECTION_BSS. */
7522
7523 fputc ('\n', asm_out_file);
7524 }
7525 #endif /* OBJECT_FORMAT_ELF */
7526
7527 /* We do not allow indirect calls to be optimized into sibling calls.
7528
7529 We cannot use sibling calls when delayed branches are disabled
7530 because they will likely require the call delay slot to be filled.
7531
7532 Also, on SPARC 32-bit we cannot emit a sibling call when the
7533 current function returns a structure. This is because the "unimp
7534 after call" convention would cause the callee to return to the
7535 wrong place. The generic code already disallows cases where the
7536 function being called returns a structure.
7537
7538 It may seem strange how this last case could occur. Usually there
7539 is code after the call which jumps to epilogue code which dumps the
7540 return value into the struct return area. That ought to invalidate
7541 the sibling call right? Well, in the C++ case we can end up passing
7542 the pointer to the struct return area to a constructor (which returns
7543 void) and then nothing else happens. Such a sibling call would look
7544 valid without the added check here. */
7545 static bool
7546 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7547 {
7548 return (decl
7549 && flag_delayed_branch
7550 && (TARGET_ARCH64 || ! current_function_returns_struct));
7551 }
7552 \f
7553 /* libfunc renaming. */
7554 #include "config/gofast.h"
7555
7556 static void
7557 sparc_init_libfuncs (void)
7558 {
7559 if (TARGET_ARCH32)
7560 {
7561 /* Use the subroutines that Sun's library provides for integer
7562 multiply and divide. The `*' prevents an underscore from
7563 being prepended by the compiler. .umul is a little faster
7564 than .mul. */
7565 set_optab_libfunc (smul_optab, SImode, "*.umul");
7566 set_optab_libfunc (sdiv_optab, SImode, "*.div");
7567 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
7568 set_optab_libfunc (smod_optab, SImode, "*.rem");
7569 set_optab_libfunc (umod_optab, SImode, "*.urem");
7570
7571 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
7572 set_optab_libfunc (add_optab, TFmode, "_Q_add");
7573 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
7574 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
7575 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
7576 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
7577
7578 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
7579 is because with soft-float, the SFmode and DFmode sqrt
7580 instructions will be absent, and the compiler will notice and
7581 try to use the TFmode sqrt instruction for calls to the
7582 builtin function sqrt, but this fails. */
7583 if (TARGET_FPU)
7584 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
7585
7586 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
7587 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
7588 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
7589 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
7590 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
7591 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
7592
7593 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
7594 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
7595 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
7596 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
7597
7598 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
7599 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
7600 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
7601
7602 if (DITF_CONVERSION_LIBFUNCS)
7603 {
7604 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
7605 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
7606 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
7607 }
7608
7609 if (SUN_CONVERSION_LIBFUNCS)
7610 {
7611 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
7612 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
7613 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
7614 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
7615 }
7616 }
7617 if (TARGET_ARCH64)
7618 {
7619 /* In the SPARC 64bit ABI, SImode multiply and divide functions
7620 do not exist in the library. Make sure the compiler does not
7621 emit calls to them by accident. (It should always use the
7622 hardware instructions.) */
7623 set_optab_libfunc (smul_optab, SImode, 0);
7624 set_optab_libfunc (sdiv_optab, SImode, 0);
7625 set_optab_libfunc (udiv_optab, SImode, 0);
7626 set_optab_libfunc (smod_optab, SImode, 0);
7627 set_optab_libfunc (umod_optab, SImode, 0);
7628
7629 if (SUN_INTEGER_MULTIPLY_64)
7630 {
7631 set_optab_libfunc (smul_optab, DImode, "__mul64");
7632 set_optab_libfunc (sdiv_optab, DImode, "__div64");
7633 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
7634 set_optab_libfunc (smod_optab, DImode, "__rem64");
7635 set_optab_libfunc (umod_optab, DImode, "__urem64");
7636 }
7637
7638 if (SUN_CONVERSION_LIBFUNCS)
7639 {
7640 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
7641 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
7642 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
7643 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
7644 }
7645 }
7646
7647 gofast_maybe_init_libfuncs ();
7648 }
7649 \f
7650 #define def_builtin(NAME, CODE, TYPE) \
7651 lang_hooks.builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
7652 NULL_TREE)
7653
7654 /* Implement the TARGET_INIT_BUILTINS target hook.
7655 Create builtin functions for special SPARC instructions. */
7656
7657 static void
7658 sparc_init_builtins (void)
7659 {
7660 if (TARGET_VIS)
7661 sparc_vis_init_builtins ();
7662 }
7663
7664 /* Create builtin functions for VIS 1.0 instructions. */
7665
7666 static void
7667 sparc_vis_init_builtins (void)
7668 {
7669 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
7670 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
7671 tree v4hi = build_vector_type (intHI_type_node, 4);
7672 tree v2hi = build_vector_type (intHI_type_node, 2);
7673 tree v2si = build_vector_type (intSI_type_node, 2);
7674
7675 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
7676 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
7677 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
7678 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
7679 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
7680 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
7681 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
7682 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
7683 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
7684 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
7685 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
7686 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
7687 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
7688 v8qi, v8qi,
7689 intDI_type_node, 0);
7690 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
7691 intDI_type_node,
7692 intDI_type_node, 0);
7693 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
7694 ptr_type_node,
7695 intSI_type_node, 0);
7696 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
7697 ptr_type_node,
7698 intDI_type_node, 0);
7699
7700 /* Packing and expanding vectors. */
7701 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
7702 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
7703 v8qi_ftype_v2si_v8qi);
7704 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
7705 v2hi_ftype_v2si);
7706 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
7707 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
7708 v8qi_ftype_v4qi_v4qi);
7709
7710 /* Multiplications. */
7711 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
7712 v4hi_ftype_v4qi_v4hi);
7713 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
7714 v4hi_ftype_v4qi_v2hi);
7715 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
7716 v4hi_ftype_v4qi_v2hi);
7717 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
7718 v4hi_ftype_v8qi_v4hi);
7719 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
7720 v4hi_ftype_v8qi_v4hi);
7721 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
7722 v2si_ftype_v4qi_v2hi);
7723 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
7724 v2si_ftype_v4qi_v2hi);
7725
7726 /* Data aligning. */
7727 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
7728 v4hi_ftype_v4hi_v4hi);
7729 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
7730 v8qi_ftype_v8qi_v8qi);
7731 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
7732 v2si_ftype_v2si_v2si);
7733 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
7734 di_ftype_di_di);
7735 if (TARGET_ARCH64)
7736 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
7737 ptr_ftype_ptr_di);
7738 else
7739 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
7740 ptr_ftype_ptr_si);
7741
7742 /* Pixel distance. */
7743 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
7744 di_ftype_v8qi_v8qi_di);
7745 }
7746
7747 /* Handle TARGET_EXPAND_BUILTIN target hook.
7748 Expand builtin functions for sparc instrinsics. */
7749
7750 static rtx
7751 sparc_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7752 enum machine_mode tmode, int ignore ATTRIBUTE_UNUSED)
7753 {
7754 tree arglist;
7755 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7756 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
7757 rtx pat, op[4];
7758 enum machine_mode mode[4];
7759 int arg_count = 0;
7760
7761 mode[arg_count] = tmode;
7762
7763 if (target == 0
7764 || GET_MODE (target) != tmode
7765 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7766 op[arg_count] = gen_reg_rtx (tmode);
7767 else
7768 op[arg_count] = target;
7769
7770 for (arglist = TREE_OPERAND (exp, 1); arglist;
7771 arglist = TREE_CHAIN (arglist))
7772 {
7773 tree arg = TREE_VALUE (arglist);
7774
7775 arg_count++;
7776 mode[arg_count] = insn_data[icode].operand[arg_count].mode;
7777 op[arg_count] = expand_expr (arg, NULL_RTX, VOIDmode, 0);
7778
7779 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
7780 mode[arg_count]))
7781 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
7782 }
7783
7784 switch (arg_count)
7785 {
7786 case 1:
7787 pat = GEN_FCN (icode) (op[0], op[1]);
7788 break;
7789 case 2:
7790 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
7791 break;
7792 case 3:
7793 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
7794 break;
7795 default:
7796 gcc_unreachable ();
7797 }
7798
7799 if (!pat)
7800 return NULL_RTX;
7801
7802 emit_insn (pat);
7803
7804 return op[0];
7805 }
7806 \f
7807 int
7808 sparc_extra_constraint_check (rtx op, int c, int strict)
7809 {
7810 int reload_ok_mem;
7811
7812 if (TARGET_ARCH64
7813 && (c == 'T' || c == 'U'))
7814 return 0;
7815
7816 switch (c)
7817 {
7818 case 'Q':
7819 return fp_sethi_p (op);
7820
7821 case 'R':
7822 return fp_mov_p (op);
7823
7824 case 'S':
7825 return fp_high_losum_p (op);
7826
7827 case 'U':
7828 if (! strict
7829 || (GET_CODE (op) == REG
7830 && (REGNO (op) < FIRST_PSEUDO_REGISTER
7831 || reg_renumber[REGNO (op)] >= 0)))
7832 return register_ok_for_ldd (op);
7833
7834 return 0;
7835
7836 case 'W':
7837 case 'T':
7838 break;
7839
7840 case 'Y':
7841 return const_zero_operand (op, GET_MODE (op));
7842
7843 default:
7844 return 0;
7845 }
7846
7847 /* Our memory extra constraints have to emulate the
7848 behavior of 'm' and 'o' in order for reload to work
7849 correctly. */
7850 if (GET_CODE (op) == MEM)
7851 {
7852 reload_ok_mem = 0;
7853 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
7854 && (! strict
7855 || strict_memory_address_p (Pmode, XEXP (op, 0))))
7856 reload_ok_mem = 1;
7857 }
7858 else
7859 {
7860 reload_ok_mem = (reload_in_progress
7861 && GET_CODE (op) == REG
7862 && REGNO (op) >= FIRST_PSEUDO_REGISTER
7863 && reg_renumber [REGNO (op)] < 0);
7864 }
7865
7866 return reload_ok_mem;
7867 }
7868
7869 /* ??? This duplicates information provided to the compiler by the
7870 ??? scheduler description. Some day, teach genautomata to output
7871 ??? the latencies and then CSE will just use that. */
7872
7873 static bool
7874 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
7875 {
7876 enum machine_mode mode = GET_MODE (x);
7877 bool float_mode_p = FLOAT_MODE_P (mode);
7878
7879 switch (code)
7880 {
7881 case CONST_INT:
7882 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
7883 {
7884 *total = 0;
7885 return true;
7886 }
7887 /* FALLTHRU */
7888
7889 case HIGH:
7890 *total = 2;
7891 return true;
7892
7893 case CONST:
7894 case LABEL_REF:
7895 case SYMBOL_REF:
7896 *total = 4;
7897 return true;
7898
7899 case CONST_DOUBLE:
7900 if (GET_MODE (x) == DImode
7901 && ((XINT (x, 3) == 0
7902 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
7903 || (XINT (x, 3) == -1
7904 && XINT (x, 2) < 0
7905 && XINT (x, 2) >= -0x1000)))
7906 *total = 0;
7907 else
7908 *total = 8;
7909 return true;
7910
7911 case MEM:
7912 /* If outer-code was a sign or zero extension, a cost
7913 of COSTS_N_INSNS (1) was already added in. This is
7914 why we are subtracting it back out. */
7915 if (outer_code == ZERO_EXTEND)
7916 {
7917 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
7918 }
7919 else if (outer_code == SIGN_EXTEND)
7920 {
7921 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
7922 }
7923 else if (float_mode_p)
7924 {
7925 *total = sparc_costs->float_load;
7926 }
7927 else
7928 {
7929 *total = sparc_costs->int_load;
7930 }
7931
7932 return true;
7933
7934 case PLUS:
7935 case MINUS:
7936 if (float_mode_p)
7937 *total = sparc_costs->float_plusminus;
7938 else
7939 *total = COSTS_N_INSNS (1);
7940 return false;
7941
7942 case MULT:
7943 if (float_mode_p)
7944 *total = sparc_costs->float_mul;
7945 else if (! TARGET_HARD_MUL)
7946 *total = COSTS_N_INSNS (25);
7947 else
7948 {
7949 int bit_cost;
7950
7951 bit_cost = 0;
7952 if (sparc_costs->int_mul_bit_factor)
7953 {
7954 int nbits;
7955
7956 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7957 {
7958 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
7959 for (nbits = 0; value != 0; value &= value - 1)
7960 nbits++;
7961 }
7962 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
7963 && GET_MODE (XEXP (x, 1)) == DImode)
7964 {
7965 rtx x1 = XEXP (x, 1);
7966 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
7967 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
7968
7969 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
7970 nbits++;
7971 for (; value2 != 0; value2 &= value2 - 1)
7972 nbits++;
7973 }
7974 else
7975 nbits = 7;
7976
7977 if (nbits < 3)
7978 nbits = 3;
7979 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
7980 bit_cost = COSTS_N_INSNS (bit_cost);
7981 }
7982
7983 if (mode == DImode)
7984 *total = sparc_costs->int_mulX + bit_cost;
7985 else
7986 *total = sparc_costs->int_mul + bit_cost;
7987 }
7988 return false;
7989
7990 case ASHIFT:
7991 case ASHIFTRT:
7992 case LSHIFTRT:
7993 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
7994 return false;
7995
7996 case DIV:
7997 case UDIV:
7998 case MOD:
7999 case UMOD:
8000 if (float_mode_p)
8001 {
8002 if (mode == DFmode)
8003 *total = sparc_costs->float_div_df;
8004 else
8005 *total = sparc_costs->float_div_sf;
8006 }
8007 else
8008 {
8009 if (mode == DImode)
8010 *total = sparc_costs->int_divX;
8011 else
8012 *total = sparc_costs->int_div;
8013 }
8014 return false;
8015
8016 case NEG:
8017 if (! float_mode_p)
8018 {
8019 *total = COSTS_N_INSNS (1);
8020 return false;
8021 }
8022 /* FALLTHRU */
8023
8024 case ABS:
8025 case FLOAT:
8026 case UNSIGNED_FLOAT:
8027 case FIX:
8028 case UNSIGNED_FIX:
8029 case FLOAT_EXTEND:
8030 case FLOAT_TRUNCATE:
8031 *total = sparc_costs->float_move;
8032 return false;
8033
8034 case SQRT:
8035 if (mode == DFmode)
8036 *total = sparc_costs->float_sqrt_df;
8037 else
8038 *total = sparc_costs->float_sqrt_sf;
8039 return false;
8040
8041 case COMPARE:
8042 if (float_mode_p)
8043 *total = sparc_costs->float_cmp;
8044 else
8045 *total = COSTS_N_INSNS (1);
8046 return false;
8047
8048 case IF_THEN_ELSE:
8049 if (float_mode_p)
8050 *total = sparc_costs->float_cmove;
8051 else
8052 *total = sparc_costs->int_cmove;
8053 return false;
8054
8055 case IOR:
8056 /* Handle the NAND vector patterns. */
8057 if (sparc_vector_mode_supported_p (GET_MODE (x))
8058 && GET_CODE (XEXP (x, 0)) == NOT
8059 && GET_CODE (XEXP (x, 1)) == NOT)
8060 {
8061 *total = COSTS_N_INSNS (1);
8062 return true;
8063 }
8064 else
8065 return false;
8066
8067 default:
8068 return false;
8069 }
8070 }
8071
8072 /* Emit the sequence of insns SEQ while preserving the register REG. */
8073
8074 static void
8075 emit_and_preserve (rtx seq, rtx reg)
8076 {
8077 rtx slot = gen_rtx_MEM (word_mode,
8078 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8079
8080 emit_insn (gen_stack_pointer_dec (GEN_INT (STACK_BOUNDARY/BITS_PER_UNIT)));
8081 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8082 emit_insn (seq);
8083 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8084 emit_insn (gen_stack_pointer_inc (GEN_INT (STACK_BOUNDARY/BITS_PER_UNIT)));
8085 }
8086
8087 /* Output the assembler code for a thunk function. THUNK_DECL is the
8088 declaration for the thunk function itself, FUNCTION is the decl for
8089 the target function. DELTA is an immediate constant offset to be
8090 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8091 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
8092
8093 static void
8094 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8095 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8096 tree function)
8097 {
8098 rtx this, insn, funexp;
8099 unsigned int int_arg_first;
8100
8101 reload_completed = 1;
8102 epilogue_completed = 1;
8103 no_new_pseudos = 1;
8104 reset_block_changes ();
8105
8106 emit_note (NOTE_INSN_PROLOGUE_END);
8107
8108 if (flag_delayed_branch)
8109 {
8110 /* We will emit a regular sibcall below, so we need to instruct
8111 output_sibcall that we are in a leaf function. */
8112 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
8113
8114 /* This will cause final.c to invoke leaf_renumber_regs so we
8115 must behave as if we were in a not-yet-leafified function. */
8116 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8117 }
8118 else
8119 {
8120 /* We will emit the sibcall manually below, so we will need to
8121 manually spill non-leaf registers. */
8122 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
8123
8124 /* We really are in a leaf function. */
8125 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8126 }
8127
8128 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8129 returns a structure, the structure return pointer is there instead. */
8130 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8131 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8132 else
8133 this = gen_rtx_REG (Pmode, int_arg_first);
8134
8135 /* Add DELTA. When possible use a plain add, otherwise load it into
8136 a register first. */
8137 if (delta)
8138 {
8139 rtx delta_rtx = GEN_INT (delta);
8140
8141 if (! SPARC_SIMM13_P (delta))
8142 {
8143 rtx scratch = gen_rtx_REG (Pmode, 1);
8144 emit_move_insn (scratch, delta_rtx);
8145 delta_rtx = scratch;
8146 }
8147
8148 /* THIS += DELTA. */
8149 emit_insn (gen_add2_insn (this, delta_rtx));
8150 }
8151
8152 /* Add the word at address (*THIS + VCALL_OFFSET). */
8153 if (vcall_offset)
8154 {
8155 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8156 rtx scratch = gen_rtx_REG (Pmode, 1);
8157
8158 gcc_assert (vcall_offset < 0);
8159
8160 /* SCRATCH = *THIS. */
8161 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this));
8162
8163 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8164 may not have any available scratch register at this point. */
8165 if (SPARC_SIMM13_P (vcall_offset))
8166 ;
8167 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8168 else if (! fixed_regs[5]
8169 /* The below sequence is made up of at least 2 insns,
8170 while the default method may need only one. */
8171 && vcall_offset < -8192)
8172 {
8173 rtx scratch2 = gen_rtx_REG (Pmode, 5);
8174 emit_move_insn (scratch2, vcall_offset_rtx);
8175 vcall_offset_rtx = scratch2;
8176 }
8177 else
8178 {
8179 rtx increment = GEN_INT (-4096);
8180
8181 /* VCALL_OFFSET is a negative number whose typical range can be
8182 estimated as -32768..0 in 32-bit mode. In almost all cases
8183 it is therefore cheaper to emit multiple add insns than
8184 spilling and loading the constant into a register (at least
8185 6 insns). */
8186 while (! SPARC_SIMM13_P (vcall_offset))
8187 {
8188 emit_insn (gen_add2_insn (scratch, increment));
8189 vcall_offset += 4096;
8190 }
8191 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
8192 }
8193
8194 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
8195 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
8196 gen_rtx_PLUS (Pmode,
8197 scratch,
8198 vcall_offset_rtx)));
8199
8200 /* THIS += *(*THIS + VCALL_OFFSET). */
8201 emit_insn (gen_add2_insn (this, scratch));
8202 }
8203
8204 /* Generate a tail call to the target function. */
8205 if (! TREE_USED (function))
8206 {
8207 assemble_external (function);
8208 TREE_USED (function) = 1;
8209 }
8210 funexp = XEXP (DECL_RTL (function), 0);
8211
8212 if (flag_delayed_branch)
8213 {
8214 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8215 insn = emit_call_insn (gen_sibcall (funexp));
8216 SIBLING_CALL_P (insn) = 1;
8217 }
8218 else
8219 {
8220 /* The hoops we have to jump through in order to generate a sibcall
8221 without using delay slots... */
8222 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
8223
8224 if (flag_pic)
8225 {
8226 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
8227 start_sequence ();
8228 /* Delay emitting the PIC helper function because it needs to
8229 change the section and we are emitting assembly code. */
8230 load_pic_register (true); /* clobbers %o7 */
8231 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8232 seq = get_insns ();
8233 end_sequence ();
8234 emit_and_preserve (seq, spill_reg);
8235 }
8236 else if (TARGET_ARCH32)
8237 {
8238 emit_insn (gen_rtx_SET (VOIDmode,
8239 scratch,
8240 gen_rtx_HIGH (SImode, funexp)));
8241 emit_insn (gen_rtx_SET (VOIDmode,
8242 scratch,
8243 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8244 }
8245 else /* TARGET_ARCH64 */
8246 {
8247 switch (sparc_cmodel)
8248 {
8249 case CM_MEDLOW:
8250 case CM_MEDMID:
8251 /* The destination can serve as a temporary. */
8252 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8253 break;
8254
8255 case CM_MEDANY:
8256 case CM_EMBMEDANY:
8257 /* The destination cannot serve as a temporary. */
8258 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8259 start_sequence ();
8260 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8261 seq = get_insns ();
8262 end_sequence ();
8263 emit_and_preserve (seq, spill_reg);
8264 break;
8265
8266 default:
8267 gcc_unreachable ();
8268 }
8269 }
8270
8271 emit_jump_insn (gen_indirect_jump (scratch));
8272 }
8273
8274 emit_barrier ();
8275
8276 /* Run just enough of rest_of_compilation to get the insns emitted.
8277 There's not really enough bulk here to make other passes such as
8278 instruction scheduling worth while. Note that use_thunk calls
8279 assemble_start_function and assemble_end_function. */
8280 insn = get_insns ();
8281 insn_locators_initialize ();
8282 shorten_branches (insn);
8283 final_start_function (insn, file, 1);
8284 final (insn, file, 1);
8285 final_end_function ();
8286
8287 reload_completed = 0;
8288 epilogue_completed = 0;
8289 no_new_pseudos = 0;
8290 }
8291
8292 /* Return true if sparc_output_mi_thunk would be able to output the
8293 assembler code for the thunk function specified by the arguments
8294 it is passed, and false otherwise. */
8295 static bool
8296 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED,
8297 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
8298 HOST_WIDE_INT vcall_offset,
8299 tree function ATTRIBUTE_UNUSED)
8300 {
8301 /* Bound the loop used in the default method above. */
8302 return (vcall_offset >= -32768 || ! fixed_regs[5]);
8303 }
8304
8305 /* How to allocate a 'struct machine_function'. */
8306
8307 static struct machine_function *
8308 sparc_init_machine_status (void)
8309 {
8310 return ggc_alloc_cleared (sizeof (struct machine_function));
8311 }
8312
8313 /* Locate some local-dynamic symbol still in use by this function
8314 so that we can print its name in local-dynamic base patterns. */
8315
8316 static const char *
8317 get_some_local_dynamic_name (void)
8318 {
8319 rtx insn;
8320
8321 if (cfun->machine->some_ld_name)
8322 return cfun->machine->some_ld_name;
8323
8324 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8325 if (INSN_P (insn)
8326 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8327 return cfun->machine->some_ld_name;
8328
8329 gcc_unreachable ();
8330 }
8331
8332 static int
8333 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8334 {
8335 rtx x = *px;
8336
8337 if (x
8338 && GET_CODE (x) == SYMBOL_REF
8339 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8340 {
8341 cfun->machine->some_ld_name = XSTR (x, 0);
8342 return 1;
8343 }
8344
8345 return 0;
8346 }
8347
8348 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8349 This is called from dwarf2out.c to emit call frame instructions
8350 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8351 static void
8352 sparc_dwarf_handle_frame_unspec (const char *label,
8353 rtx pattern ATTRIBUTE_UNUSED,
8354 int index ATTRIBUTE_UNUSED)
8355 {
8356 gcc_assert (index == UNSPECV_SAVEW);
8357 dwarf2out_window_save (label);
8358 }
8359
8360 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8361 We need to emit DTP-relative relocations. */
8362
8363 void
8364 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8365 {
8366 switch (size)
8367 {
8368 case 4:
8369 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8370 break;
8371 case 8:
8372 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8373 break;
8374 default:
8375 gcc_unreachable ();
8376 }
8377 output_addr_const (file, x);
8378 fputs (")", file);
8379 }
8380
8381 static
8382 void sparc_file_end (void)
8383 {
8384 /* If we haven't emitted the special PIC helper function, do so now. */
8385 if (pic_helper_symbol_name[0] && !pic_helper_emitted_p)
8386 emit_pic_helper ();
8387
8388 if (NEED_INDICATE_EXEC_STACK)
8389 file_end_indicate_exec_stack ();
8390 }
8391
8392 #include "gt-sparc.h"