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[gcc.git] / gcc / config / sparc / sparc.c
1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "tree.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "function.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "recog.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "tm_p.h"
46 #include "debug.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
51
52 /* Processor costs */
53 static const
54 struct processor_costs cypress_costs = {
55 COSTS_N_INSNS (2), /* int load */
56 COSTS_N_INSNS (2), /* int signed load */
57 COSTS_N_INSNS (2), /* int zeroed load */
58 COSTS_N_INSNS (2), /* float load */
59 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
60 COSTS_N_INSNS (5), /* fadd, fsub */
61 COSTS_N_INSNS (1), /* fcmp */
62 COSTS_N_INSNS (1), /* fmov, fmovr */
63 COSTS_N_INSNS (7), /* fmul */
64 COSTS_N_INSNS (37), /* fdivs */
65 COSTS_N_INSNS (37), /* fdivd */
66 COSTS_N_INSNS (63), /* fsqrts */
67 COSTS_N_INSNS (63), /* fsqrtd */
68 COSTS_N_INSNS (1), /* imul */
69 COSTS_N_INSNS (1), /* imulX */
70 0, /* imul bit factor */
71 COSTS_N_INSNS (1), /* idiv */
72 COSTS_N_INSNS (1), /* idivX */
73 COSTS_N_INSNS (1), /* movcc/movr */
74 0, /* shift penalty */
75 };
76
77 static const
78 struct processor_costs supersparc_costs = {
79 COSTS_N_INSNS (1), /* int load */
80 COSTS_N_INSNS (1), /* int signed load */
81 COSTS_N_INSNS (1), /* int zeroed load */
82 COSTS_N_INSNS (0), /* float load */
83 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
84 COSTS_N_INSNS (3), /* fadd, fsub */
85 COSTS_N_INSNS (3), /* fcmp */
86 COSTS_N_INSNS (1), /* fmov, fmovr */
87 COSTS_N_INSNS (3), /* fmul */
88 COSTS_N_INSNS (6), /* fdivs */
89 COSTS_N_INSNS (9), /* fdivd */
90 COSTS_N_INSNS (12), /* fsqrts */
91 COSTS_N_INSNS (12), /* fsqrtd */
92 COSTS_N_INSNS (4), /* imul */
93 COSTS_N_INSNS (4), /* imulX */
94 0, /* imul bit factor */
95 COSTS_N_INSNS (4), /* idiv */
96 COSTS_N_INSNS (4), /* idivX */
97 COSTS_N_INSNS (1), /* movcc/movr */
98 1, /* shift penalty */
99 };
100
101 static const
102 struct processor_costs hypersparc_costs = {
103 COSTS_N_INSNS (1), /* int load */
104 COSTS_N_INSNS (1), /* int signed load */
105 COSTS_N_INSNS (1), /* int zeroed load */
106 COSTS_N_INSNS (1), /* float load */
107 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
108 COSTS_N_INSNS (1), /* fadd, fsub */
109 COSTS_N_INSNS (1), /* fcmp */
110 COSTS_N_INSNS (1), /* fmov, fmovr */
111 COSTS_N_INSNS (1), /* fmul */
112 COSTS_N_INSNS (8), /* fdivs */
113 COSTS_N_INSNS (12), /* fdivd */
114 COSTS_N_INSNS (17), /* fsqrts */
115 COSTS_N_INSNS (17), /* fsqrtd */
116 COSTS_N_INSNS (17), /* imul */
117 COSTS_N_INSNS (17), /* imulX */
118 0, /* imul bit factor */
119 COSTS_N_INSNS (17), /* idiv */
120 COSTS_N_INSNS (17), /* idivX */
121 COSTS_N_INSNS (1), /* movcc/movr */
122 0, /* shift penalty */
123 };
124
125 static const
126 struct processor_costs sparclet_costs = {
127 COSTS_N_INSNS (3), /* int load */
128 COSTS_N_INSNS (3), /* int signed load */
129 COSTS_N_INSNS (1), /* int zeroed load */
130 COSTS_N_INSNS (1), /* float load */
131 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
132 COSTS_N_INSNS (1), /* fadd, fsub */
133 COSTS_N_INSNS (1), /* fcmp */
134 COSTS_N_INSNS (1), /* fmov, fmovr */
135 COSTS_N_INSNS (1), /* fmul */
136 COSTS_N_INSNS (1), /* fdivs */
137 COSTS_N_INSNS (1), /* fdivd */
138 COSTS_N_INSNS (1), /* fsqrts */
139 COSTS_N_INSNS (1), /* fsqrtd */
140 COSTS_N_INSNS (5), /* imul */
141 COSTS_N_INSNS (5), /* imulX */
142 0, /* imul bit factor */
143 COSTS_N_INSNS (5), /* idiv */
144 COSTS_N_INSNS (5), /* idivX */
145 COSTS_N_INSNS (1), /* movcc/movr */
146 0, /* shift penalty */
147 };
148
149 static const
150 struct processor_costs ultrasparc_costs = {
151 COSTS_N_INSNS (2), /* int load */
152 COSTS_N_INSNS (3), /* int signed load */
153 COSTS_N_INSNS (2), /* int zeroed load */
154 COSTS_N_INSNS (2), /* float load */
155 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
156 COSTS_N_INSNS (4), /* fadd, fsub */
157 COSTS_N_INSNS (1), /* fcmp */
158 COSTS_N_INSNS (2), /* fmov, fmovr */
159 COSTS_N_INSNS (4), /* fmul */
160 COSTS_N_INSNS (13), /* fdivs */
161 COSTS_N_INSNS (23), /* fdivd */
162 COSTS_N_INSNS (13), /* fsqrts */
163 COSTS_N_INSNS (23), /* fsqrtd */
164 COSTS_N_INSNS (4), /* imul */
165 COSTS_N_INSNS (4), /* imulX */
166 2, /* imul bit factor */
167 COSTS_N_INSNS (37), /* idiv */
168 COSTS_N_INSNS (68), /* idivX */
169 COSTS_N_INSNS (2), /* movcc/movr */
170 2, /* shift penalty */
171 };
172
173 static const
174 struct processor_costs ultrasparc3_costs = {
175 COSTS_N_INSNS (2), /* int load */
176 COSTS_N_INSNS (3), /* int signed load */
177 COSTS_N_INSNS (3), /* int zeroed load */
178 COSTS_N_INSNS (2), /* float load */
179 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
180 COSTS_N_INSNS (4), /* fadd, fsub */
181 COSTS_N_INSNS (5), /* fcmp */
182 COSTS_N_INSNS (3), /* fmov, fmovr */
183 COSTS_N_INSNS (4), /* fmul */
184 COSTS_N_INSNS (17), /* fdivs */
185 COSTS_N_INSNS (20), /* fdivd */
186 COSTS_N_INSNS (20), /* fsqrts */
187 COSTS_N_INSNS (29), /* fsqrtd */
188 COSTS_N_INSNS (6), /* imul */
189 COSTS_N_INSNS (6), /* imulX */
190 0, /* imul bit factor */
191 COSTS_N_INSNS (40), /* idiv */
192 COSTS_N_INSNS (71), /* idivX */
193 COSTS_N_INSNS (2), /* movcc/movr */
194 0, /* shift penalty */
195 };
196
197 const struct processor_costs *sparc_costs = &cypress_costs;
198
199 #ifdef HAVE_AS_RELAX_OPTION
200 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
201 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
202 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
203 somebody does not branch between the sethi and jmp. */
204 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
205 #else
206 #define LEAF_SIBCALL_SLOT_RESERVED_P \
207 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
208 #endif
209
210 /* Global variables for machine-dependent things. */
211
212 /* Size of frame. Need to know this to emit return insns from leaf procedures.
213 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
214 reload pass. This is important as the value is later used for scheduling
215 (to see what can go in a delay slot).
216 APPARENT_FSIZE is the size of the stack less the register save area and less
217 the outgoing argument area. It is used when saving call preserved regs. */
218 static HOST_WIDE_INT apparent_fsize;
219 static HOST_WIDE_INT actual_fsize;
220
221 /* Number of live general or floating point registers needed to be
222 saved (as 4-byte quantities). */
223 static int num_gfregs;
224
225 /* The alias set for prologue/epilogue register save/restore. */
226 static GTY(()) int sparc_sr_alias_set;
227
228 /* Save the operands last given to a compare for use when we
229 generate a scc or bcc insn. */
230 rtx sparc_compare_op0, sparc_compare_op1;
231
232 /* Vector to say how input registers are mapped to output registers.
233 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
234 eliminate it. You must use -fomit-frame-pointer to get that. */
235 char leaf_reg_remap[] =
236 { 0, 1, 2, 3, 4, 5, 6, 7,
237 -1, -1, -1, -1, -1, -1, 14, -1,
238 -1, -1, -1, -1, -1, -1, -1, -1,
239 8, 9, 10, 11, 12, 13, -1, 15,
240
241 32, 33, 34, 35, 36, 37, 38, 39,
242 40, 41, 42, 43, 44, 45, 46, 47,
243 48, 49, 50, 51, 52, 53, 54, 55,
244 56, 57, 58, 59, 60, 61, 62, 63,
245 64, 65, 66, 67, 68, 69, 70, 71,
246 72, 73, 74, 75, 76, 77, 78, 79,
247 80, 81, 82, 83, 84, 85, 86, 87,
248 88, 89, 90, 91, 92, 93, 94, 95,
249 96, 97, 98, 99, 100};
250
251 /* Vector, indexed by hard register number, which contains 1
252 for a register that is allowable in a candidate for leaf
253 function treatment. */
254 char sparc_leaf_regs[] =
255 { 1, 1, 1, 1, 1, 1, 1, 1,
256 0, 0, 0, 0, 0, 0, 1, 0,
257 0, 0, 0, 0, 0, 0, 0, 0,
258 1, 1, 1, 1, 1, 1, 0, 1,
259 1, 1, 1, 1, 1, 1, 1, 1,
260 1, 1, 1, 1, 1, 1, 1, 1,
261 1, 1, 1, 1, 1, 1, 1, 1,
262 1, 1, 1, 1, 1, 1, 1, 1,
263 1, 1, 1, 1, 1, 1, 1, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1};
268
269 struct machine_function GTY(())
270 {
271 /* Some local-dynamic TLS symbol name. */
272 const char *some_ld_name;
273 };
274
275 /* Register we pretend to think the frame pointer is allocated to.
276 Normally, this is %fp, but if we are in a leaf procedure, this
277 is %sp+"something". We record "something" separately as it may
278 be too big for reg+constant addressing. */
279
280 static rtx frame_base_reg;
281 static HOST_WIDE_INT frame_base_offset;
282
283 static void sparc_init_modes (void);
284 static void scan_record_type (tree, int *, int *, int *);
285 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
286 tree, int, int, int *, int *);
287
288 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
289 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
290
291 static void sparc_output_addr_vec (rtx);
292 static void sparc_output_addr_diff_vec (rtx);
293 static void sparc_output_deferred_case_vectors (void);
294 static rtx sparc_builtin_saveregs (void);
295 static int epilogue_renumber (rtx *, int);
296 static bool sparc_assemble_integer (rtx, unsigned int, int);
297 static int set_extends (rtx);
298 static void load_pic_register (void);
299 static int save_or_restore_regs (int, int, rtx, int, int);
300 static void emit_save_regs (void);
301 static void emit_restore_regs (void);
302 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
303 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
304 #ifdef OBJECT_FORMAT_ELF
305 static void sparc_elf_asm_named_section (const char *, unsigned int);
306 #endif
307
308 static int sparc_adjust_cost (rtx, rtx, rtx, int);
309 static int sparc_issue_rate (void);
310 static void sparc_sched_init (FILE *, int, int);
311 static int sparc_use_sched_lookahead (void);
312
313 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
314 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
315 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
316 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
317 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
318
319 static bool sparc_function_ok_for_sibcall (tree, tree);
320 static void sparc_init_libfuncs (void);
321 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
322 HOST_WIDE_INT, tree);
323 static struct machine_function * sparc_init_machine_status (void);
324 static bool sparc_cannot_force_const_mem (rtx);
325 static rtx sparc_tls_get_addr (void);
326 static rtx sparc_tls_got (void);
327 static const char *get_some_local_dynamic_name (void);
328 static int get_some_local_dynamic_name_1 (rtx *, void *);
329 static bool sparc_rtx_costs (rtx, int, int, int *);
330 static bool sparc_promote_prototypes (tree);
331 static rtx sparc_struct_value_rtx (tree, int);
332 static bool sparc_return_in_memory (tree, tree);
333 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
334 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
335 static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
336 enum machine_mode, tree, bool);
337 \f
338 /* Option handling. */
339
340 /* Code model option as passed by user. */
341 const char *sparc_cmodel_string;
342 /* Parsed value. */
343 enum cmodel sparc_cmodel;
344
345 char sparc_hard_reg_printed[8];
346
347 struct sparc_cpu_select sparc_select[] =
348 {
349 /* switch name, tune arch */
350 { (char *)0, "default", 1, 1 },
351 { (char *)0, "-mcpu=", 1, 1 },
352 { (char *)0, "-mtune=", 1, 0 },
353 { 0, 0, 0, 0 }
354 };
355
356 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
357 enum processor_type sparc_cpu;
358 \f
359 /* Initialize the GCC target structure. */
360
361 /* The sparc default is to use .half rather than .short for aligned
362 HI objects. Use .word instead of .long on non-ELF systems. */
363 #undef TARGET_ASM_ALIGNED_HI_OP
364 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
365 #ifndef OBJECT_FORMAT_ELF
366 #undef TARGET_ASM_ALIGNED_SI_OP
367 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
368 #endif
369
370 #undef TARGET_ASM_UNALIGNED_HI_OP
371 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
372 #undef TARGET_ASM_UNALIGNED_SI_OP
373 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
374 #undef TARGET_ASM_UNALIGNED_DI_OP
375 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
376
377 /* The target hook has to handle DI-mode values. */
378 #undef TARGET_ASM_INTEGER
379 #define TARGET_ASM_INTEGER sparc_assemble_integer
380
381 #undef TARGET_ASM_FUNCTION_PROLOGUE
382 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
383 #undef TARGET_ASM_FUNCTION_EPILOGUE
384 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
385
386 #undef TARGET_SCHED_ADJUST_COST
387 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
388 #undef TARGET_SCHED_ISSUE_RATE
389 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
390 #undef TARGET_SCHED_INIT
391 #define TARGET_SCHED_INIT sparc_sched_init
392 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
393 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
394
395 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
396 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
397
398 #undef TARGET_INIT_LIBFUNCS
399 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
400
401 #ifdef HAVE_AS_TLS
402 #undef TARGET_HAVE_TLS
403 #define TARGET_HAVE_TLS true
404 #endif
405 #undef TARGET_CANNOT_FORCE_CONST_MEM
406 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
407
408 #undef TARGET_ASM_OUTPUT_MI_THUNK
409 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
410 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
411 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
412
413 #undef TARGET_RTX_COSTS
414 #define TARGET_RTX_COSTS sparc_rtx_costs
415 #undef TARGET_ADDRESS_COST
416 #define TARGET_ADDRESS_COST hook_int_rtx_0
417
418 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
419 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
420 test for this value. */
421 #undef TARGET_PROMOTE_FUNCTION_ARGS
422 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
423
424 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
425 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
426 test for this value. */
427 #undef TARGET_PROMOTE_FUNCTION_RETURN
428 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
429
430 #undef TARGET_PROMOTE_PROTOTYPES
431 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
432
433 #undef TARGET_STRUCT_VALUE_RTX
434 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
435 #undef TARGET_RETURN_IN_MEMORY
436 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
437 #undef TARGET_MUST_PASS_IN_STACK
438 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
439 #undef TARGET_PASS_BY_REFERENCE
440 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
441
442 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
443 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
444 #undef TARGET_STRICT_ARGUMENT_NAMING
445 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
446
447 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
448 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
449
450 #undef TARGET_LATE_RTL_PROLOGUE_EPILOGUE
451 #define TARGET_LATE_RTL_PROLOGUE_EPILOGUE true
452
453 struct gcc_target targetm = TARGET_INITIALIZER;
454 \f
455 /* Validate and override various options, and do some machine dependent
456 initialization. */
457
458 void
459 sparc_override_options (void)
460 {
461 static struct code_model {
462 const char *const name;
463 const int value;
464 } const cmodels[] = {
465 { "32", CM_32 },
466 { "medlow", CM_MEDLOW },
467 { "medmid", CM_MEDMID },
468 { "medany", CM_MEDANY },
469 { "embmedany", CM_EMBMEDANY },
470 { 0, 0 }
471 };
472 const struct code_model *cmodel;
473 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
474 static struct cpu_default {
475 const int cpu;
476 const char *const name;
477 } const cpu_default[] = {
478 /* There must be one entry here for each TARGET_CPU value. */
479 { TARGET_CPU_sparc, "cypress" },
480 { TARGET_CPU_sparclet, "tsc701" },
481 { TARGET_CPU_sparclite, "f930" },
482 { TARGET_CPU_v8, "v8" },
483 { TARGET_CPU_hypersparc, "hypersparc" },
484 { TARGET_CPU_sparclite86x, "sparclite86x" },
485 { TARGET_CPU_supersparc, "supersparc" },
486 { TARGET_CPU_v9, "v9" },
487 { TARGET_CPU_ultrasparc, "ultrasparc" },
488 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
489 { 0, 0 }
490 };
491 const struct cpu_default *def;
492 /* Table of values for -m{cpu,tune}=. */
493 static struct cpu_table {
494 const char *const name;
495 const enum processor_type processor;
496 const int disable;
497 const int enable;
498 } const cpu_table[] = {
499 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
500 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
501 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
502 /* TI TMS390Z55 supersparc */
503 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
504 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
505 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
506 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
507 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
508 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
509 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
510 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
511 MASK_SPARCLITE },
512 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
513 /* TEMIC sparclet */
514 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
515 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
516 /* TI ultrasparc I, II, IIi */
517 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
518 /* Although insns using %y are deprecated, it is a clear win on current
519 ultrasparcs. */
520 |MASK_DEPRECATED_V8_INSNS},
521 /* TI ultrasparc III */
522 /* ??? Check if %y issue still holds true in ultra3. */
523 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
524 { 0, 0, 0, 0 }
525 };
526 const struct cpu_table *cpu;
527 const struct sparc_cpu_select *sel;
528 int fpu;
529
530 #ifndef SPARC_BI_ARCH
531 /* Check for unsupported architecture size. */
532 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
533 error ("%s is not supported by this configuration",
534 DEFAULT_ARCH32_P ? "-m64" : "-m32");
535 #endif
536
537 /* We force all 64bit archs to use 128 bit long double */
538 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
539 {
540 error ("-mlong-double-64 not allowed with -m64");
541 target_flags |= MASK_LONG_DOUBLE_128;
542 }
543
544 /* Code model selection. */
545 sparc_cmodel = SPARC_DEFAULT_CMODEL;
546
547 #ifdef SPARC_BI_ARCH
548 if (TARGET_ARCH32)
549 sparc_cmodel = CM_32;
550 #endif
551
552 if (sparc_cmodel_string != NULL)
553 {
554 if (TARGET_ARCH64)
555 {
556 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
557 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
558 break;
559 if (cmodel->name == NULL)
560 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
561 else
562 sparc_cmodel = cmodel->value;
563 }
564 else
565 error ("-mcmodel= is not supported on 32 bit systems");
566 }
567
568 fpu = TARGET_FPU; /* save current -mfpu status */
569
570 /* Set the default CPU. */
571 for (def = &cpu_default[0]; def->name; ++def)
572 if (def->cpu == TARGET_CPU_DEFAULT)
573 break;
574 if (! def->name)
575 abort ();
576 sparc_select[0].string = def->name;
577
578 for (sel = &sparc_select[0]; sel->name; ++sel)
579 {
580 if (sel->string)
581 {
582 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
583 if (! strcmp (sel->string, cpu->name))
584 {
585 if (sel->set_tune_p)
586 sparc_cpu = cpu->processor;
587
588 if (sel->set_arch_p)
589 {
590 target_flags &= ~cpu->disable;
591 target_flags |= cpu->enable;
592 }
593 break;
594 }
595
596 if (! cpu->name)
597 error ("bad value (%s) for %s switch", sel->string, sel->name);
598 }
599 }
600
601 /* If -mfpu or -mno-fpu was explicitly used, don't override with
602 the processor default. Clear MASK_FPU_SET to avoid confusing
603 the reverse mapping from switch values to names. */
604 if (TARGET_FPU_SET)
605 {
606 target_flags = (target_flags & ~MASK_FPU) | fpu;
607 target_flags &= ~MASK_FPU_SET;
608 }
609
610 /* Don't allow -mvis if FPU is disabled. */
611 if (! TARGET_FPU)
612 target_flags &= ~MASK_VIS;
613
614 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
615 are available.
616 -m64 also implies v9. */
617 if (TARGET_VIS || TARGET_ARCH64)
618 {
619 target_flags |= MASK_V9;
620 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
621 }
622
623 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
624 if (TARGET_V9 && TARGET_ARCH32)
625 target_flags |= MASK_DEPRECATED_V8_INSNS;
626
627 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
628 if (! TARGET_V9 || TARGET_ARCH64)
629 target_flags &= ~MASK_V8PLUS;
630
631 /* Don't use stack biasing in 32 bit mode. */
632 if (TARGET_ARCH32)
633 target_flags &= ~MASK_STACK_BIAS;
634
635 /* Supply a default value for align_functions. */
636 if (align_functions == 0
637 && (sparc_cpu == PROCESSOR_ULTRASPARC
638 || sparc_cpu == PROCESSOR_ULTRASPARC3))
639 align_functions = 32;
640
641 /* Validate PCC_STRUCT_RETURN. */
642 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
643 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
644
645 /* Only use .uaxword when compiling for a 64-bit target. */
646 if (!TARGET_ARCH64)
647 targetm.asm_out.unaligned_op.di = NULL;
648
649 /* Do various machine dependent initializations. */
650 sparc_init_modes ();
651
652 /* Acquire a unique set number for our register saves and restores. */
653 sparc_sr_alias_set = new_alias_set ();
654
655 /* Set up function hooks. */
656 init_machine_status = sparc_init_machine_status;
657
658 switch (sparc_cpu)
659 {
660 case PROCESSOR_V7:
661 case PROCESSOR_CYPRESS:
662 sparc_costs = &cypress_costs;
663 break;
664 case PROCESSOR_V8:
665 case PROCESSOR_SPARCLITE:
666 case PROCESSOR_SUPERSPARC:
667 sparc_costs = &supersparc_costs;
668 break;
669 case PROCESSOR_F930:
670 case PROCESSOR_F934:
671 case PROCESSOR_HYPERSPARC:
672 case PROCESSOR_SPARCLITE86X:
673 sparc_costs = &hypersparc_costs;
674 break;
675 case PROCESSOR_SPARCLET:
676 case PROCESSOR_TSC701:
677 sparc_costs = &sparclet_costs;
678 break;
679 case PROCESSOR_V9:
680 case PROCESSOR_ULTRASPARC:
681 sparc_costs = &ultrasparc_costs;
682 break;
683 case PROCESSOR_ULTRASPARC3:
684 sparc_costs = &ultrasparc3_costs;
685 break;
686 };
687 }
688 \f
689 /* Miscellaneous utilities. */
690
691 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
692 or branch on register contents instructions. */
693
694 int
695 v9_regcmp_p (enum rtx_code code)
696 {
697 return (code == EQ || code == NE || code == GE || code == LT
698 || code == LE || code == GT);
699 }
700
701 \f
702 /* Operand constraints. */
703
704 /* Return nonzero only if OP is a register of mode MODE,
705 or const0_rtx. */
706
707 int
708 reg_or_0_operand (rtx op, enum machine_mode mode)
709 {
710 if (register_operand (op, mode))
711 return 1;
712 if (op == const0_rtx)
713 return 1;
714 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
715 && CONST_DOUBLE_HIGH (op) == 0
716 && CONST_DOUBLE_LOW (op) == 0)
717 return 1;
718 if (fp_zero_operand (op, mode))
719 return 1;
720 return 0;
721 }
722
723 /* Return nonzero only if OP is const1_rtx. */
724
725 int
726 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
727 {
728 return op == const1_rtx;
729 }
730
731 /* Nonzero if OP is a floating point value with value 0.0. */
732
733 int
734 fp_zero_operand (rtx op, enum machine_mode mode)
735 {
736 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
737 return 0;
738 return op == CONST0_RTX (mode);
739 }
740
741 /* Nonzero if OP is a register operand in floating point register. */
742
743 int
744 fp_register_operand (rtx op, enum machine_mode mode)
745 {
746 if (! register_operand (op, mode))
747 return 0;
748 if (GET_CODE (op) == SUBREG)
749 op = SUBREG_REG (op);
750 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
751 }
752
753 /* Nonzero if OP is a floating point constant which can
754 be loaded into an integer register using a single
755 sethi instruction. */
756
757 int
758 fp_sethi_p (rtx op)
759 {
760 if (GET_CODE (op) == CONST_DOUBLE)
761 {
762 REAL_VALUE_TYPE r;
763 long i;
764
765 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
766 if (REAL_VALUES_EQUAL (r, dconst0) &&
767 ! REAL_VALUE_MINUS_ZERO (r))
768 return 0;
769 REAL_VALUE_TO_TARGET_SINGLE (r, i);
770 if (SPARC_SETHI_P (i))
771 return 1;
772 }
773
774 return 0;
775 }
776
777 /* Nonzero if OP is a floating point constant which can
778 be loaded into an integer register using a single
779 mov instruction. */
780
781 int
782 fp_mov_p (rtx op)
783 {
784 if (GET_CODE (op) == CONST_DOUBLE)
785 {
786 REAL_VALUE_TYPE r;
787 long i;
788
789 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
790 if (REAL_VALUES_EQUAL (r, dconst0) &&
791 ! REAL_VALUE_MINUS_ZERO (r))
792 return 0;
793 REAL_VALUE_TO_TARGET_SINGLE (r, i);
794 if (SPARC_SIMM13_P (i))
795 return 1;
796 }
797
798 return 0;
799 }
800
801 /* Nonzero if OP is a floating point constant which can
802 be loaded into an integer register using a high/losum
803 instruction sequence. */
804
805 int
806 fp_high_losum_p (rtx op)
807 {
808 /* The constraints calling this should only be in
809 SFmode move insns, so any constant which cannot
810 be moved using a single insn will do. */
811 if (GET_CODE (op) == CONST_DOUBLE)
812 {
813 REAL_VALUE_TYPE r;
814 long i;
815
816 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
817 if (REAL_VALUES_EQUAL (r, dconst0) &&
818 ! REAL_VALUE_MINUS_ZERO (r))
819 return 0;
820 REAL_VALUE_TO_TARGET_SINGLE (r, i);
821 if (! SPARC_SETHI_P (i)
822 && ! SPARC_SIMM13_P (i))
823 return 1;
824 }
825
826 return 0;
827 }
828
829 /* Nonzero if OP is an integer register. */
830
831 int
832 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
833 {
834 return (register_operand (op, SImode)
835 || (TARGET_ARCH64 && register_operand (op, DImode)));
836 }
837
838 /* Nonzero if OP is a floating point condition code register. */
839
840 int
841 fcc_reg_operand (rtx op, enum machine_mode mode)
842 {
843 /* This can happen when recog is called from combine. Op may be a MEM.
844 Fail instead of calling abort in this case. */
845 if (GET_CODE (op) != REG)
846 return 0;
847
848 if (mode != VOIDmode && mode != GET_MODE (op))
849 return 0;
850 if (mode == VOIDmode
851 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
852 return 0;
853
854 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
855 if (reg_renumber == 0)
856 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
857 return REGNO_OK_FOR_CCFP_P (REGNO (op));
858 #else
859 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
860 #endif
861 }
862
863 /* Nonzero if OP is a floating point condition code fcc0 register. */
864
865 int
866 fcc0_reg_operand (rtx op, enum machine_mode mode)
867 {
868 /* This can happen when recog is called from combine. Op may be a MEM.
869 Fail instead of calling abort in this case. */
870 if (GET_CODE (op) != REG)
871 return 0;
872
873 if (mode != VOIDmode && mode != GET_MODE (op))
874 return 0;
875 if (mode == VOIDmode
876 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
877 return 0;
878
879 return REGNO (op) == SPARC_FCC_REG;
880 }
881
882 /* Nonzero if OP is an integer or floating point condition code register. */
883
884 int
885 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
886 {
887 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
888 {
889 if (mode != VOIDmode && mode != GET_MODE (op))
890 return 0;
891 if (mode == VOIDmode
892 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
893 return 0;
894 return 1;
895 }
896
897 return fcc_reg_operand (op, mode);
898 }
899
900 /* Call insn on SPARC can take a PC-relative constant address, or any regular
901 memory address. */
902
903 int
904 call_operand (rtx op, enum machine_mode mode)
905 {
906 if (GET_CODE (op) != MEM)
907 abort ();
908 op = XEXP (op, 0);
909 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
910 }
911
912 int
913 call_operand_address (rtx op, enum machine_mode mode)
914 {
915 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
916 }
917
918 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
919 otherwise return 0. */
920
921 int
922 tls_symbolic_operand (rtx op)
923 {
924 if (GET_CODE (op) != SYMBOL_REF)
925 return 0;
926 return SYMBOL_REF_TLS_MODEL (op);
927 }
928
929 int
930 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
931 {
932 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
933 }
934
935 int
936 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
937 {
938 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
939 }
940
941 int
942 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
943 {
944 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
945 }
946
947 int
948 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
949 {
950 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
951 }
952
953 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
954 reference and a constant. */
955
956 int
957 symbolic_operand (register rtx op, enum machine_mode mode)
958 {
959 enum machine_mode omode = GET_MODE (op);
960
961 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
962 return 0;
963
964 switch (GET_CODE (op))
965 {
966 case SYMBOL_REF:
967 return !SYMBOL_REF_TLS_MODEL (op);
968
969 case LABEL_REF:
970 return 1;
971
972 case CONST:
973 op = XEXP (op, 0);
974 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
975 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
976 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
977 && GET_CODE (XEXP (op, 1)) == CONST_INT);
978
979 default:
980 return 0;
981 }
982 }
983
984 /* Return truth value of statement that OP is a symbolic memory
985 operand of mode MODE. */
986
987 int
988 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
989 {
990 if (GET_CODE (op) == SUBREG)
991 op = SUBREG_REG (op);
992 if (GET_CODE (op) != MEM)
993 return 0;
994 op = XEXP (op, 0);
995 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
996 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
997 || GET_CODE (op) == LABEL_REF);
998 }
999
1000 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
1001
1002 int
1003 label_ref_operand (rtx op, enum machine_mode mode)
1004 {
1005 if (GET_CODE (op) != LABEL_REF)
1006 return 0;
1007 if (GET_MODE (op) != mode)
1008 return 0;
1009 return 1;
1010 }
1011
1012 /* Return 1 if the operand is an argument used in generating pic references
1013 in either the medium/low or medium/anywhere code models of sparc64. */
1014
1015 int
1016 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1017 {
1018 /* Check for (const (minus (symbol_ref:GOT)
1019 (const (minus (label) (pc))))). */
1020 if (GET_CODE (op) != CONST)
1021 return 0;
1022 op = XEXP (op, 0);
1023 if (GET_CODE (op) != MINUS)
1024 return 0;
1025 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
1026 return 0;
1027 /* ??? Ensure symbol is GOT. */
1028 if (GET_CODE (XEXP (op, 1)) != CONST)
1029 return 0;
1030 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
1031 return 0;
1032 return 1;
1033 }
1034
1035 /* Return 1 if the operand is a data segment reference. This includes
1036 the readonly data segment, or in other words anything but the text segment.
1037 This is needed in the medium/anywhere code model on v9. These values
1038 are accessed with EMBMEDANY_BASE_REG. */
1039
1040 int
1041 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1042 {
1043 switch (GET_CODE (op))
1044 {
1045 case SYMBOL_REF :
1046 return ! SYMBOL_REF_FUNCTION_P (op);
1047 case PLUS :
1048 /* Assume canonical format of symbol + constant.
1049 Fall through. */
1050 case CONST :
1051 return data_segment_operand (XEXP (op, 0), VOIDmode);
1052 default :
1053 return 0;
1054 }
1055 }
1056
1057 /* Return 1 if the operand is a text segment reference.
1058 This is needed in the medium/anywhere code model on v9. */
1059
1060 int
1061 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1062 {
1063 switch (GET_CODE (op))
1064 {
1065 case LABEL_REF :
1066 return 1;
1067 case SYMBOL_REF :
1068 return SYMBOL_REF_FUNCTION_P (op);
1069 case PLUS :
1070 /* Assume canonical format of symbol + constant.
1071 Fall through. */
1072 case CONST :
1073 return text_segment_operand (XEXP (op, 0), VOIDmode);
1074 default :
1075 return 0;
1076 }
1077 }
1078
1079 /* Return 1 if the operand is either a register or a memory operand that is
1080 not symbolic. */
1081
1082 int
1083 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
1084 {
1085 if (register_operand (op, mode))
1086 return 1;
1087
1088 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
1089 return 1;
1090
1091 return 0;
1092 }
1093
1094 int
1095 splittable_symbolic_memory_operand (rtx op,
1096 enum machine_mode mode ATTRIBUTE_UNUSED)
1097 {
1098 if (GET_CODE (op) != MEM)
1099 return 0;
1100 if (! symbolic_operand (XEXP (op, 0), Pmode))
1101 return 0;
1102 return 1;
1103 }
1104
1105 int
1106 splittable_immediate_memory_operand (rtx op,
1107 enum machine_mode mode ATTRIBUTE_UNUSED)
1108 {
1109 if (GET_CODE (op) != MEM)
1110 return 0;
1111 if (! immediate_operand (XEXP (op, 0), Pmode))
1112 return 0;
1113 return 1;
1114 }
1115
1116 /* Return truth value of whether OP is EQ or NE. */
1117
1118 int
1119 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1120 {
1121 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
1122 }
1123
1124 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1125 or LTU for non-floating-point. We handle those specially. */
1126
1127 int
1128 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1129 {
1130 enum rtx_code code;
1131
1132 if (!COMPARISON_P (op))
1133 return 0;
1134
1135 if (GET_MODE (XEXP (op, 0)) == CCFPmode
1136 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
1137 return 1;
1138
1139 code = GET_CODE (op);
1140 return (code != NE && code != EQ && code != GEU && code != LTU);
1141 }
1142
1143 /* Return 1 if this is a comparison operator. This allows the use of
1144 MATCH_OPERATOR to recognize all the branch insns. */
1145
1146 int
1147 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1148 {
1149 enum rtx_code code;
1150
1151 if (!COMPARISON_P (op))
1152 return 0;
1153
1154 code = GET_CODE (op);
1155 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
1156 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1157 /* These are the only branches which work with CC_NOOVmode. */
1158 return (code == EQ || code == NE || code == GE || code == LT);
1159 return 1;
1160 }
1161
1162 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1163 MATCH_OPERATOR to recognize all the branch insns. */
1164
1165 int
1166 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1167 {
1168 enum rtx_code code;
1169
1170 if (! TARGET_V9)
1171 return 0;
1172
1173 if (!COMPARISON_P (op))
1174 return 0;
1175
1176 code = GET_CODE (op);
1177 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1178 /* These are the only branches which work with CCX_NOOVmode. */
1179 return (code == EQ || code == NE || code == GE || code == LT);
1180 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1181 }
1182
1183 /* Nonzero if OP is a comparison operator suitable for use in v9
1184 conditional move or branch on register contents instructions. */
1185
1186 int
1187 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1188 {
1189 enum rtx_code code;
1190
1191 if (!COMPARISON_P (op))
1192 return 0;
1193
1194 code = GET_CODE (op);
1195 return v9_regcmp_p (code);
1196 }
1197
1198 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1199
1200 int
1201 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1202 {
1203 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1204 }
1205
1206 /* Return nonzero if OP is an operator of mode MODE which can set
1207 the condition codes explicitly. We do not include PLUS and MINUS
1208 because these require CC_NOOVmode, which we handle explicitly. */
1209
1210 int
1211 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1212 {
1213 if (GET_CODE (op) == AND
1214 || GET_CODE (op) == IOR
1215 || GET_CODE (op) == XOR)
1216 return 1;
1217
1218 return 0;
1219 }
1220
1221 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1222 complement its second operand and set the condition codes explicitly. */
1223
1224 int
1225 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1226 {
1227 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1228 and (xor ... (not ...)) to (not (xor ...)). */
1229 return (GET_CODE (op) == AND
1230 || GET_CODE (op) == IOR);
1231 }
1232 \f
1233 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1234 signed 13 bit immediate field. This is an acceptable SImode operand for
1235 most 3 address instructions. */
1236
1237 int
1238 arith_operand (rtx op, enum machine_mode mode)
1239 {
1240 if (register_operand (op, mode))
1241 return 1;
1242 if (GET_CODE (op) != CONST_INT)
1243 return 0;
1244 return SMALL_INT32 (op);
1245 }
1246
1247 /* Return true if OP is a constant 4096 */
1248
1249 int
1250 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1251 {
1252 if (GET_CODE (op) != CONST_INT)
1253 return 0;
1254 else
1255 return INTVAL (op) == 4096;
1256 }
1257
1258 /* Return true if OP is suitable as second operand for add/sub */
1259
1260 int
1261 arith_add_operand (rtx op, enum machine_mode mode)
1262 {
1263 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1264 }
1265
1266 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1267 immediate field of OR and XOR instructions. Used for 64-bit
1268 constant formation patterns. */
1269 int
1270 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1271 {
1272 return ((GET_CODE (op) == CONST_INT
1273 && SPARC_SIMM13_P (INTVAL (op)))
1274 #if HOST_BITS_PER_WIDE_INT != 64
1275 || (GET_CODE (op) == CONST_DOUBLE
1276 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1277 && (CONST_DOUBLE_HIGH (op) ==
1278 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1279 (HOST_WIDE_INT)-1 : 0)))
1280 #endif
1281 );
1282 }
1283
1284 /* The same, but only for sethi instructions. */
1285 int
1286 const64_high_operand (rtx op, enum machine_mode mode)
1287 {
1288 return ((GET_CODE (op) == CONST_INT
1289 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1290 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1291 )
1292 || (GET_CODE (op) == CONST_DOUBLE
1293 && CONST_DOUBLE_HIGH (op) == 0
1294 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1295 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1296 }
1297
1298 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1299 signed 11 bit immediate field. This is an acceptable SImode operand for
1300 the movcc instructions. */
1301
1302 int
1303 arith11_operand (rtx op, enum machine_mode mode)
1304 {
1305 return (register_operand (op, mode)
1306 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1307 }
1308
1309 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1310 signed 10 bit immediate field. This is an acceptable SImode operand for
1311 the movrcc instructions. */
1312
1313 int
1314 arith10_operand (rtx op, enum machine_mode mode)
1315 {
1316 return (register_operand (op, mode)
1317 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1318 }
1319
1320 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1321 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1322 immediate field.
1323 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1324 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1325 for most 3 address instructions. */
1326
1327 int
1328 arith_double_operand (rtx op, enum machine_mode mode)
1329 {
1330 return (register_operand (op, mode)
1331 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1332 || (! TARGET_ARCH64
1333 && GET_CODE (op) == CONST_DOUBLE
1334 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1335 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1336 || (TARGET_ARCH64
1337 && GET_CODE (op) == CONST_DOUBLE
1338 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1339 && ((CONST_DOUBLE_HIGH (op) == -1
1340 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1341 || (CONST_DOUBLE_HIGH (op) == 0
1342 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1343 }
1344
1345 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1346
1347 int
1348 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1349 {
1350 return (TARGET_ARCH64 &&
1351 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1352 (GET_CODE (op) == CONST_DOUBLE &&
1353 CONST_DOUBLE_LOW (op) == 4096 &&
1354 CONST_DOUBLE_HIGH (op) == 0)));
1355 }
1356
1357 /* Return true if OP is suitable as second operand for add/sub in DImode */
1358
1359 int
1360 arith_double_add_operand (rtx op, enum machine_mode mode)
1361 {
1362 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1363 }
1364
1365 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1366 can fit in an 11 bit immediate field. This is an acceptable DImode
1367 operand for the movcc instructions. */
1368 /* ??? Replace with arith11_operand? */
1369
1370 int
1371 arith11_double_operand (rtx op, enum machine_mode mode)
1372 {
1373 return (register_operand (op, mode)
1374 || (GET_CODE (op) == CONST_DOUBLE
1375 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1376 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1377 && ((CONST_DOUBLE_HIGH (op) == -1
1378 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1379 || (CONST_DOUBLE_HIGH (op) == 0
1380 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1381 || (GET_CODE (op) == CONST_INT
1382 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1383 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1384 }
1385
1386 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1387 can fit in an 10 bit immediate field. This is an acceptable DImode
1388 operand for the movrcc instructions. */
1389 /* ??? Replace with arith10_operand? */
1390
1391 int
1392 arith10_double_operand (rtx op, enum machine_mode mode)
1393 {
1394 return (register_operand (op, mode)
1395 || (GET_CODE (op) == CONST_DOUBLE
1396 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1397 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1398 && ((CONST_DOUBLE_HIGH (op) == -1
1399 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1400 || (CONST_DOUBLE_HIGH (op) == 0
1401 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1402 || (GET_CODE (op) == CONST_INT
1403 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1404 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1405 }
1406
1407 /* Return truth value of whether OP is an integer which fits the
1408 range constraining immediate operands in most three-address insns,
1409 which have a 13 bit immediate field. */
1410
1411 int
1412 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1413 {
1414 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1415 }
1416
1417 int
1418 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1419 {
1420 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1421 || (GET_CODE (op) == CONST_DOUBLE
1422 && CONST_DOUBLE_HIGH (op) == 0
1423 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1424 }
1425
1426 /* Recognize operand values for the umul instruction. That instruction sign
1427 extends immediate values just like all other sparc instructions, but
1428 interprets the extended result as an unsigned number. */
1429
1430 int
1431 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1432 {
1433 #if HOST_BITS_PER_WIDE_INT > 32
1434 /* All allowed constants will fit a CONST_INT. */
1435 return (GET_CODE (op) == CONST_INT
1436 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1437 || (INTVAL (op) >= 0xFFFFF000
1438 && INTVAL (op) <= 0xFFFFFFFF)));
1439 #else
1440 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1441 || (GET_CODE (op) == CONST_DOUBLE
1442 && CONST_DOUBLE_HIGH (op) == 0
1443 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1444 #endif
1445 }
1446
1447 int
1448 uns_arith_operand (rtx op, enum machine_mode mode)
1449 {
1450 return register_operand (op, mode) || uns_small_int (op, mode);
1451 }
1452
1453 /* Return truth value of statement that OP is a call-clobbered register. */
1454 int
1455 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1456 {
1457 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1458 }
1459
1460 /* Return 1 if OP is a valid operand for the source of a move insn. */
1461
1462 int
1463 input_operand (rtx op, enum machine_mode mode)
1464 {
1465 /* If both modes are non-void they must be the same. */
1466 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1467 return 0;
1468
1469 /* Allow any one instruction integer constant, and all CONST_INT
1470 variants when we are working in DImode and !arch64. */
1471 if (GET_MODE_CLASS (mode) == MODE_INT
1472 && ((GET_CODE (op) == CONST_INT
1473 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1474 || SPARC_SIMM13_P (INTVAL (op))
1475 || (mode == DImode
1476 && ! TARGET_ARCH64)))
1477 || (TARGET_ARCH64
1478 && GET_CODE (op) == CONST_DOUBLE
1479 && ((CONST_DOUBLE_HIGH (op) == 0
1480 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1481 ||
1482 #if HOST_BITS_PER_WIDE_INT == 64
1483 (CONST_DOUBLE_HIGH (op) == 0
1484 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1485 #else
1486 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1487 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1488 && CONST_DOUBLE_HIGH (op) == 0)
1489 || (CONST_DOUBLE_HIGH (op) == -1
1490 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1491 #endif
1492 ))))
1493 return 1;
1494
1495 /* If !arch64 and this is a DImode const, allow it so that
1496 the splits can be generated. */
1497 if (! TARGET_ARCH64
1498 && mode == DImode
1499 && GET_CODE (op) == CONST_DOUBLE)
1500 return 1;
1501
1502 if (register_operand (op, mode))
1503 return 1;
1504
1505 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1506 && GET_CODE (op) == CONST_DOUBLE)
1507 return 1;
1508
1509 /* If this is a SUBREG, look inside so that we handle
1510 paradoxical ones. */
1511 if (GET_CODE (op) == SUBREG)
1512 op = SUBREG_REG (op);
1513
1514 /* Check for valid MEM forms. */
1515 if (GET_CODE (op) == MEM)
1516 {
1517 rtx inside = XEXP (op, 0);
1518
1519 if (GET_CODE (inside) == LO_SUM)
1520 {
1521 /* We can't allow these because all of the splits
1522 (eventually as they trickle down into DFmode
1523 splits) require offsettable memory references. */
1524 if (! TARGET_V9
1525 && GET_MODE (op) == TFmode)
1526 return 0;
1527
1528 return (register_operand (XEXP (inside, 0), Pmode)
1529 && CONSTANT_P (XEXP (inside, 1)));
1530 }
1531 return memory_address_p (mode, inside);
1532 }
1533
1534 return 0;
1535 }
1536
1537 /* Return 1 if OP is valid for the lhs of a compare insn. */
1538
1539 int
1540 compare_operand (rtx op, enum machine_mode mode)
1541 {
1542 if (GET_CODE (op) == ZERO_EXTRACT)
1543 return (register_operand (XEXP (op, 0), mode)
1544 && small_int_or_double (XEXP (op, 1), mode)
1545 && small_int_or_double (XEXP (op, 2), mode)
1546 /* This matches cmp_zero_extract. */
1547 && ((mode == SImode
1548 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1549 && INTVAL (XEXP (op, 2)) > 19)
1550 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1551 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1552 /* This matches cmp_zero_extract_sp64. */
1553 || (mode == DImode
1554 && TARGET_ARCH64
1555 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1556 && INTVAL (XEXP (op, 2)) > 51)
1557 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1558 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1559 else
1560 return register_operand (op, mode);
1561 }
1562
1563 \f
1564 /* We know it can't be done in one insn when we get here,
1565 the movsi expander guarantees this. */
1566 void
1567 sparc_emit_set_const32 (rtx op0, rtx op1)
1568 {
1569 enum machine_mode mode = GET_MODE (op0);
1570 rtx temp;
1571
1572 if (GET_CODE (op1) == CONST_INT)
1573 {
1574 HOST_WIDE_INT value = INTVAL (op1);
1575
1576 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1577 || SPARC_SIMM13_P (value))
1578 abort ();
1579 }
1580
1581 /* Full 2-insn decomposition is needed. */
1582 if (reload_in_progress || reload_completed)
1583 temp = op0;
1584 else
1585 temp = gen_reg_rtx (mode);
1586
1587 if (GET_CODE (op1) == CONST_INT)
1588 {
1589 /* Emit them as real moves instead of a HIGH/LO_SUM,
1590 this way CSE can see everything and reuse intermediate
1591 values if it wants. */
1592 if (TARGET_ARCH64
1593 && HOST_BITS_PER_WIDE_INT != 64
1594 && (INTVAL (op1) & 0x80000000) != 0)
1595 emit_insn (gen_rtx_SET
1596 (VOIDmode, temp,
1597 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1598 0, DImode)));
1599 else
1600 emit_insn (gen_rtx_SET (VOIDmode, temp,
1601 GEN_INT (INTVAL (op1)
1602 & ~(HOST_WIDE_INT)0x3ff)));
1603
1604 emit_insn (gen_rtx_SET (VOIDmode,
1605 op0,
1606 gen_rtx_IOR (mode, temp,
1607 GEN_INT (INTVAL (op1) & 0x3ff))));
1608 }
1609 else
1610 {
1611 /* A symbol, emit in the traditional way. */
1612 emit_insn (gen_rtx_SET (VOIDmode, temp,
1613 gen_rtx_HIGH (mode, op1)));
1614 emit_insn (gen_rtx_SET (VOIDmode,
1615 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1616
1617 }
1618 }
1619
1620 \f
1621 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1622 If TEMP is non-zero, we are forbidden to use any other scratch
1623 registers. Otherwise, we are allowed to generate them as needed.
1624
1625 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1626 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1627 void
1628 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1629 {
1630 rtx temp1, temp2, temp3, temp4, temp5;
1631 rtx ti_temp = 0;
1632
1633 if (temp && GET_MODE (temp) == TImode)
1634 {
1635 ti_temp = temp;
1636 temp = gen_rtx_REG (DImode, REGNO (temp));
1637 }
1638
1639 /* SPARC-V9 code-model support. */
1640 switch (sparc_cmodel)
1641 {
1642 case CM_MEDLOW:
1643 /* The range spanned by all instructions in the object is less
1644 than 2^31 bytes (2GB) and the distance from any instruction
1645 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1646 than 2^31 bytes (2GB).
1647
1648 The executable must be in the low 4TB of the virtual address
1649 space.
1650
1651 sethi %hi(symbol), %temp1
1652 or %temp1, %lo(symbol), %reg */
1653 if (temp)
1654 temp1 = temp; /* op0 is allowed. */
1655 else
1656 temp1 = gen_reg_rtx (DImode);
1657
1658 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1659 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1660 break;
1661
1662 case CM_MEDMID:
1663 /* The range spanned by all instructions in the object is less
1664 than 2^31 bytes (2GB) and the distance from any instruction
1665 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1666 than 2^31 bytes (2GB).
1667
1668 The executable must be in the low 16TB of the virtual address
1669 space.
1670
1671 sethi %h44(symbol), %temp1
1672 or %temp1, %m44(symbol), %temp2
1673 sllx %temp2, 12, %temp3
1674 or %temp3, %l44(symbol), %reg */
1675 if (temp)
1676 {
1677 temp1 = op0;
1678 temp2 = op0;
1679 temp3 = temp; /* op0 is allowed. */
1680 }
1681 else
1682 {
1683 temp1 = gen_reg_rtx (DImode);
1684 temp2 = gen_reg_rtx (DImode);
1685 temp3 = gen_reg_rtx (DImode);
1686 }
1687
1688 emit_insn (gen_seth44 (temp1, op1));
1689 emit_insn (gen_setm44 (temp2, temp1, op1));
1690 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1691 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1692 emit_insn (gen_setl44 (op0, temp3, op1));
1693 break;
1694
1695 case CM_MEDANY:
1696 /* The range spanned by all instructions in the object is less
1697 than 2^31 bytes (2GB) and the distance from any instruction
1698 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1699 than 2^31 bytes (2GB).
1700
1701 The executable can be placed anywhere in the virtual address
1702 space.
1703
1704 sethi %hh(symbol), %temp1
1705 sethi %lm(symbol), %temp2
1706 or %temp1, %hm(symbol), %temp3
1707 sllx %temp3, 32, %temp4
1708 or %temp4, %temp2, %temp5
1709 or %temp5, %lo(symbol), %reg */
1710 if (temp)
1711 {
1712 /* It is possible that one of the registers we got for operands[2]
1713 might coincide with that of operands[0] (which is why we made
1714 it TImode). Pick the other one to use as our scratch. */
1715 if (rtx_equal_p (temp, op0))
1716 {
1717 if (ti_temp)
1718 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1719 else
1720 abort();
1721 }
1722 temp1 = op0;
1723 temp2 = temp; /* op0 is _not_ allowed, see above. */
1724 temp3 = op0;
1725 temp4 = op0;
1726 temp5 = op0;
1727 }
1728 else
1729 {
1730 temp1 = gen_reg_rtx (DImode);
1731 temp2 = gen_reg_rtx (DImode);
1732 temp3 = gen_reg_rtx (DImode);
1733 temp4 = gen_reg_rtx (DImode);
1734 temp5 = gen_reg_rtx (DImode);
1735 }
1736
1737 emit_insn (gen_sethh (temp1, op1));
1738 emit_insn (gen_setlm (temp2, op1));
1739 emit_insn (gen_sethm (temp3, temp1, op1));
1740 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1741 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1742 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1743 gen_rtx_PLUS (DImode, temp4, temp2)));
1744 emit_insn (gen_setlo (op0, temp5, op1));
1745 break;
1746
1747 case CM_EMBMEDANY:
1748 /* Old old old backwards compatibility kruft here.
1749 Essentially it is MEDLOW with a fixed 64-bit
1750 virtual base added to all data segment addresses.
1751 Text-segment stuff is computed like MEDANY, we can't
1752 reuse the code above because the relocation knobs
1753 look different.
1754
1755 Data segment: sethi %hi(symbol), %temp1
1756 add %temp1, EMBMEDANY_BASE_REG, %temp2
1757 or %temp2, %lo(symbol), %reg */
1758 if (data_segment_operand (op1, GET_MODE (op1)))
1759 {
1760 if (temp)
1761 {
1762 temp1 = temp; /* op0 is allowed. */
1763 temp2 = op0;
1764 }
1765 else
1766 {
1767 temp1 = gen_reg_rtx (DImode);
1768 temp2 = gen_reg_rtx (DImode);
1769 }
1770
1771 emit_insn (gen_embmedany_sethi (temp1, op1));
1772 emit_insn (gen_embmedany_brsum (temp2, temp1));
1773 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1774 }
1775
1776 /* Text segment: sethi %uhi(symbol), %temp1
1777 sethi %hi(symbol), %temp2
1778 or %temp1, %ulo(symbol), %temp3
1779 sllx %temp3, 32, %temp4
1780 or %temp4, %temp2, %temp5
1781 or %temp5, %lo(symbol), %reg */
1782 else
1783 {
1784 if (temp)
1785 {
1786 /* It is possible that one of the registers we got for operands[2]
1787 might coincide with that of operands[0] (which is why we made
1788 it TImode). Pick the other one to use as our scratch. */
1789 if (rtx_equal_p (temp, op0))
1790 {
1791 if (ti_temp)
1792 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1793 else
1794 abort();
1795 }
1796 temp1 = op0;
1797 temp2 = temp; /* op0 is _not_ allowed, see above. */
1798 temp3 = op0;
1799 temp4 = op0;
1800 temp5 = op0;
1801 }
1802 else
1803 {
1804 temp1 = gen_reg_rtx (DImode);
1805 temp2 = gen_reg_rtx (DImode);
1806 temp3 = gen_reg_rtx (DImode);
1807 temp4 = gen_reg_rtx (DImode);
1808 temp5 = gen_reg_rtx (DImode);
1809 }
1810
1811 emit_insn (gen_embmedany_textuhi (temp1, op1));
1812 emit_insn (gen_embmedany_texthi (temp2, op1));
1813 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1814 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1815 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1816 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1817 gen_rtx_PLUS (DImode, temp4, temp2)));
1818 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1819 }
1820 break;
1821
1822 default:
1823 abort();
1824 }
1825 }
1826
1827 /* These avoid problems when cross compiling. If we do not
1828 go through all this hair then the optimizer will see
1829 invalid REG_EQUAL notes or in some cases none at all. */
1830 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1831 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1832 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1833 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1834
1835 #if HOST_BITS_PER_WIDE_INT == 64
1836 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1837 #define GEN_INT64(__x) GEN_INT (__x)
1838 #else
1839 #define GEN_HIGHINT64(__x) \
1840 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1841 #define GEN_INT64(__x) \
1842 immed_double_const ((__x) & 0xffffffff, \
1843 ((__x) & 0x80000000 ? -1 : 0), DImode)
1844 #endif
1845
1846 /* The optimizer is not to assume anything about exactly
1847 which bits are set for a HIGH, they are unspecified.
1848 Unfortunately this leads to many missed optimizations
1849 during CSE. We mask out the non-HIGH bits, and matches
1850 a plain movdi, to alleviate this problem. */
1851 static void
1852 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1853 {
1854 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1855 }
1856
1857 static rtx
1858 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1859 {
1860 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1861 }
1862
1863 static rtx
1864 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1865 {
1866 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1867 }
1868
1869 static rtx
1870 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1871 {
1872 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1873 }
1874
1875 /* Worker routines for 64-bit constant formation on arch64.
1876 One of the key things to be doing in these emissions is
1877 to create as many temp REGs as possible. This makes it
1878 possible for half-built constants to be used later when
1879 such values are similar to something required later on.
1880 Without doing this, the optimizer cannot see such
1881 opportunities. */
1882
1883 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1884 unsigned HOST_WIDE_INT, int);
1885
1886 static void
1887 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1888 unsigned HOST_WIDE_INT low_bits, int is_neg)
1889 {
1890 unsigned HOST_WIDE_INT high_bits;
1891
1892 if (is_neg)
1893 high_bits = (~low_bits) & 0xffffffff;
1894 else
1895 high_bits = low_bits;
1896
1897 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1898 if (!is_neg)
1899 {
1900 emit_insn (gen_rtx_SET (VOIDmode, op0,
1901 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1902 }
1903 else
1904 {
1905 /* If we are XOR'ing with -1, then we should emit a one's complement
1906 instead. This way the combiner will notice logical operations
1907 such as ANDN later on and substitute. */
1908 if ((low_bits & 0x3ff) == 0x3ff)
1909 {
1910 emit_insn (gen_rtx_SET (VOIDmode, op0,
1911 gen_rtx_NOT (DImode, temp)));
1912 }
1913 else
1914 {
1915 emit_insn (gen_rtx_SET (VOIDmode, op0,
1916 gen_safe_XOR64 (temp,
1917 (-(HOST_WIDE_INT)0x400
1918 | (low_bits & 0x3ff)))));
1919 }
1920 }
1921 }
1922
1923 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1924 unsigned HOST_WIDE_INT, int);
1925
1926 static void
1927 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1928 unsigned HOST_WIDE_INT high_bits,
1929 unsigned HOST_WIDE_INT low_immediate,
1930 int shift_count)
1931 {
1932 rtx temp2 = op0;
1933
1934 if ((high_bits & 0xfffffc00) != 0)
1935 {
1936 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1937 if ((high_bits & ~0xfffffc00) != 0)
1938 emit_insn (gen_rtx_SET (VOIDmode, op0,
1939 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1940 else
1941 temp2 = temp;
1942 }
1943 else
1944 {
1945 emit_insn (gen_safe_SET64 (temp, high_bits));
1946 temp2 = temp;
1947 }
1948
1949 /* Now shift it up into place. */
1950 emit_insn (gen_rtx_SET (VOIDmode, op0,
1951 gen_rtx_ASHIFT (DImode, temp2,
1952 GEN_INT (shift_count))));
1953
1954 /* If there is a low immediate part piece, finish up by
1955 putting that in as well. */
1956 if (low_immediate != 0)
1957 emit_insn (gen_rtx_SET (VOIDmode, op0,
1958 gen_safe_OR64 (op0, low_immediate)));
1959 }
1960
1961 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1962 unsigned HOST_WIDE_INT);
1963
1964 /* Full 64-bit constant decomposition. Even though this is the
1965 'worst' case, we still optimize a few things away. */
1966 static void
1967 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1968 unsigned HOST_WIDE_INT high_bits,
1969 unsigned HOST_WIDE_INT low_bits)
1970 {
1971 rtx sub_temp;
1972
1973 if (reload_in_progress || reload_completed)
1974 sub_temp = op0;
1975 else
1976 sub_temp = gen_reg_rtx (DImode);
1977
1978 if ((high_bits & 0xfffffc00) != 0)
1979 {
1980 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1981 if ((high_bits & ~0xfffffc00) != 0)
1982 emit_insn (gen_rtx_SET (VOIDmode,
1983 sub_temp,
1984 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1985 else
1986 sub_temp = temp;
1987 }
1988 else
1989 {
1990 emit_insn (gen_safe_SET64 (temp, high_bits));
1991 sub_temp = temp;
1992 }
1993
1994 if (!reload_in_progress && !reload_completed)
1995 {
1996 rtx temp2 = gen_reg_rtx (DImode);
1997 rtx temp3 = gen_reg_rtx (DImode);
1998 rtx temp4 = gen_reg_rtx (DImode);
1999
2000 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2001 gen_rtx_ASHIFT (DImode, sub_temp,
2002 GEN_INT (32))));
2003
2004 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
2005 if ((low_bits & ~0xfffffc00) != 0)
2006 {
2007 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2008 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2009 emit_insn (gen_rtx_SET (VOIDmode, op0,
2010 gen_rtx_PLUS (DImode, temp4, temp3)));
2011 }
2012 else
2013 {
2014 emit_insn (gen_rtx_SET (VOIDmode, op0,
2015 gen_rtx_PLUS (DImode, temp4, temp2)));
2016 }
2017 }
2018 else
2019 {
2020 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2021 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2022 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2023 int to_shift = 12;
2024
2025 /* We are in the middle of reload, so this is really
2026 painful. However we do still make an attempt to
2027 avoid emitting truly stupid code. */
2028 if (low1 != const0_rtx)
2029 {
2030 emit_insn (gen_rtx_SET (VOIDmode, op0,
2031 gen_rtx_ASHIFT (DImode, sub_temp,
2032 GEN_INT (to_shift))));
2033 emit_insn (gen_rtx_SET (VOIDmode, op0,
2034 gen_rtx_IOR (DImode, op0, low1)));
2035 sub_temp = op0;
2036 to_shift = 12;
2037 }
2038 else
2039 {
2040 to_shift += 12;
2041 }
2042 if (low2 != const0_rtx)
2043 {
2044 emit_insn (gen_rtx_SET (VOIDmode, op0,
2045 gen_rtx_ASHIFT (DImode, sub_temp,
2046 GEN_INT (to_shift))));
2047 emit_insn (gen_rtx_SET (VOIDmode, op0,
2048 gen_rtx_IOR (DImode, op0, low2)));
2049 sub_temp = op0;
2050 to_shift = 8;
2051 }
2052 else
2053 {
2054 to_shift += 8;
2055 }
2056 emit_insn (gen_rtx_SET (VOIDmode, op0,
2057 gen_rtx_ASHIFT (DImode, sub_temp,
2058 GEN_INT (to_shift))));
2059 if (low3 != const0_rtx)
2060 emit_insn (gen_rtx_SET (VOIDmode, op0,
2061 gen_rtx_IOR (DImode, op0, low3)));
2062 /* phew... */
2063 }
2064 }
2065
2066 /* Analyze a 64-bit constant for certain properties. */
2067 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2068 unsigned HOST_WIDE_INT,
2069 int *, int *, int *);
2070
2071 static void
2072 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2073 unsigned HOST_WIDE_INT low_bits,
2074 int *hbsp, int *lbsp, int *abbasp)
2075 {
2076 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2077 int i;
2078
2079 lowest_bit_set = highest_bit_set = -1;
2080 i = 0;
2081 do
2082 {
2083 if ((lowest_bit_set == -1)
2084 && ((low_bits >> i) & 1))
2085 lowest_bit_set = i;
2086 if ((highest_bit_set == -1)
2087 && ((high_bits >> (32 - i - 1)) & 1))
2088 highest_bit_set = (64 - i - 1);
2089 }
2090 while (++i < 32
2091 && ((highest_bit_set == -1)
2092 || (lowest_bit_set == -1)));
2093 if (i == 32)
2094 {
2095 i = 0;
2096 do
2097 {
2098 if ((lowest_bit_set == -1)
2099 && ((high_bits >> i) & 1))
2100 lowest_bit_set = i + 32;
2101 if ((highest_bit_set == -1)
2102 && ((low_bits >> (32 - i - 1)) & 1))
2103 highest_bit_set = 32 - i - 1;
2104 }
2105 while (++i < 32
2106 && ((highest_bit_set == -1)
2107 || (lowest_bit_set == -1)));
2108 }
2109 /* If there are no bits set this should have gone out
2110 as one instruction! */
2111 if (lowest_bit_set == -1
2112 || highest_bit_set == -1)
2113 abort ();
2114 all_bits_between_are_set = 1;
2115 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2116 {
2117 if (i < 32)
2118 {
2119 if ((low_bits & (1 << i)) != 0)
2120 continue;
2121 }
2122 else
2123 {
2124 if ((high_bits & (1 << (i - 32))) != 0)
2125 continue;
2126 }
2127 all_bits_between_are_set = 0;
2128 break;
2129 }
2130 *hbsp = highest_bit_set;
2131 *lbsp = lowest_bit_set;
2132 *abbasp = all_bits_between_are_set;
2133 }
2134
2135 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2136
2137 static int
2138 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2139 unsigned HOST_WIDE_INT low_bits)
2140 {
2141 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2142
2143 if (high_bits == 0
2144 || high_bits == 0xffffffff)
2145 return 1;
2146
2147 analyze_64bit_constant (high_bits, low_bits,
2148 &highest_bit_set, &lowest_bit_set,
2149 &all_bits_between_are_set);
2150
2151 if ((highest_bit_set == 63
2152 || lowest_bit_set == 0)
2153 && all_bits_between_are_set != 0)
2154 return 1;
2155
2156 if ((highest_bit_set - lowest_bit_set) < 21)
2157 return 1;
2158
2159 return 0;
2160 }
2161
2162 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2163 unsigned HOST_WIDE_INT,
2164 int, int);
2165
2166 static unsigned HOST_WIDE_INT
2167 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2168 unsigned HOST_WIDE_INT low_bits,
2169 int lowest_bit_set, int shift)
2170 {
2171 HOST_WIDE_INT hi, lo;
2172
2173 if (lowest_bit_set < 32)
2174 {
2175 lo = (low_bits >> lowest_bit_set) << shift;
2176 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2177 }
2178 else
2179 {
2180 lo = 0;
2181 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2182 }
2183 if (hi & lo)
2184 abort ();
2185 return (hi | lo);
2186 }
2187
2188 /* Here we are sure to be arch64 and this is an integer constant
2189 being loaded into a register. Emit the most efficient
2190 insn sequence possible. Detection of all the 1-insn cases
2191 has been done already. */
2192 void
2193 sparc_emit_set_const64 (rtx op0, rtx op1)
2194 {
2195 unsigned HOST_WIDE_INT high_bits, low_bits;
2196 int lowest_bit_set, highest_bit_set;
2197 int all_bits_between_are_set;
2198 rtx temp = 0;
2199
2200 /* Sanity check that we know what we are working with. */
2201 if (! TARGET_ARCH64)
2202 abort ();
2203
2204 if (GET_CODE (op0) != SUBREG)
2205 {
2206 if (GET_CODE (op0) != REG
2207 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2208 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2209 abort ();
2210 }
2211
2212 if (reload_in_progress || reload_completed)
2213 temp = op0;
2214
2215 if (GET_CODE (op1) != CONST_DOUBLE
2216 && GET_CODE (op1) != CONST_INT)
2217 {
2218 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2219 return;
2220 }
2221
2222 if (! temp)
2223 temp = gen_reg_rtx (DImode);
2224
2225 if (GET_CODE (op1) == CONST_DOUBLE)
2226 {
2227 #if HOST_BITS_PER_WIDE_INT == 64
2228 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2229 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2230 #else
2231 high_bits = CONST_DOUBLE_HIGH (op1);
2232 low_bits = CONST_DOUBLE_LOW (op1);
2233 #endif
2234 }
2235 else
2236 {
2237 #if HOST_BITS_PER_WIDE_INT == 64
2238 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2239 low_bits = (INTVAL (op1) & 0xffffffff);
2240 #else
2241 high_bits = ((INTVAL (op1) < 0) ?
2242 0xffffffff :
2243 0x00000000);
2244 low_bits = INTVAL (op1);
2245 #endif
2246 }
2247
2248 /* low_bits bits 0 --> 31
2249 high_bits bits 32 --> 63 */
2250
2251 analyze_64bit_constant (high_bits, low_bits,
2252 &highest_bit_set, &lowest_bit_set,
2253 &all_bits_between_are_set);
2254
2255 /* First try for a 2-insn sequence. */
2256
2257 /* These situations are preferred because the optimizer can
2258 * do more things with them:
2259 * 1) mov -1, %reg
2260 * sllx %reg, shift, %reg
2261 * 2) mov -1, %reg
2262 * srlx %reg, shift, %reg
2263 * 3) mov some_small_const, %reg
2264 * sllx %reg, shift, %reg
2265 */
2266 if (((highest_bit_set == 63
2267 || lowest_bit_set == 0)
2268 && all_bits_between_are_set != 0)
2269 || ((highest_bit_set - lowest_bit_set) < 12))
2270 {
2271 HOST_WIDE_INT the_const = -1;
2272 int shift = lowest_bit_set;
2273
2274 if ((highest_bit_set != 63
2275 && lowest_bit_set != 0)
2276 || all_bits_between_are_set == 0)
2277 {
2278 the_const =
2279 create_simple_focus_bits (high_bits, low_bits,
2280 lowest_bit_set, 0);
2281 }
2282 else if (lowest_bit_set == 0)
2283 shift = -(63 - highest_bit_set);
2284
2285 if (! SPARC_SIMM13_P (the_const))
2286 abort ();
2287
2288 emit_insn (gen_safe_SET64 (temp, the_const));
2289 if (shift > 0)
2290 emit_insn (gen_rtx_SET (VOIDmode,
2291 op0,
2292 gen_rtx_ASHIFT (DImode,
2293 temp,
2294 GEN_INT (shift))));
2295 else if (shift < 0)
2296 emit_insn (gen_rtx_SET (VOIDmode,
2297 op0,
2298 gen_rtx_LSHIFTRT (DImode,
2299 temp,
2300 GEN_INT (-shift))));
2301 else
2302 abort ();
2303 return;
2304 }
2305
2306 /* Now a range of 22 or less bits set somewhere.
2307 * 1) sethi %hi(focus_bits), %reg
2308 * sllx %reg, shift, %reg
2309 * 2) sethi %hi(focus_bits), %reg
2310 * srlx %reg, shift, %reg
2311 */
2312 if ((highest_bit_set - lowest_bit_set) < 21)
2313 {
2314 unsigned HOST_WIDE_INT focus_bits =
2315 create_simple_focus_bits (high_bits, low_bits,
2316 lowest_bit_set, 10);
2317
2318 if (! SPARC_SETHI_P (focus_bits))
2319 abort ();
2320
2321 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2322
2323 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2324 if (lowest_bit_set < 10)
2325 emit_insn (gen_rtx_SET (VOIDmode,
2326 op0,
2327 gen_rtx_LSHIFTRT (DImode, temp,
2328 GEN_INT (10 - lowest_bit_set))));
2329 else if (lowest_bit_set > 10)
2330 emit_insn (gen_rtx_SET (VOIDmode,
2331 op0,
2332 gen_rtx_ASHIFT (DImode, temp,
2333 GEN_INT (lowest_bit_set - 10))));
2334 else
2335 abort ();
2336 return;
2337 }
2338
2339 /* 1) sethi %hi(low_bits), %reg
2340 * or %reg, %lo(low_bits), %reg
2341 * 2) sethi %hi(~low_bits), %reg
2342 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2343 */
2344 if (high_bits == 0
2345 || high_bits == 0xffffffff)
2346 {
2347 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2348 (high_bits == 0xffffffff));
2349 return;
2350 }
2351
2352 /* Now, try 3-insn sequences. */
2353
2354 /* 1) sethi %hi(high_bits), %reg
2355 * or %reg, %lo(high_bits), %reg
2356 * sllx %reg, 32, %reg
2357 */
2358 if (low_bits == 0)
2359 {
2360 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2361 return;
2362 }
2363
2364 /* We may be able to do something quick
2365 when the constant is negated, so try that. */
2366 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2367 (~low_bits) & 0xfffffc00))
2368 {
2369 /* NOTE: The trailing bits get XOR'd so we need the
2370 non-negated bits, not the negated ones. */
2371 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2372
2373 if ((((~high_bits) & 0xffffffff) == 0
2374 && ((~low_bits) & 0x80000000) == 0)
2375 || (((~high_bits) & 0xffffffff) == 0xffffffff
2376 && ((~low_bits) & 0x80000000) != 0))
2377 {
2378 int fast_int = (~low_bits & 0xffffffff);
2379
2380 if ((SPARC_SETHI_P (fast_int)
2381 && (~high_bits & 0xffffffff) == 0)
2382 || SPARC_SIMM13_P (fast_int))
2383 emit_insn (gen_safe_SET64 (temp, fast_int));
2384 else
2385 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2386 }
2387 else
2388 {
2389 rtx negated_const;
2390 #if HOST_BITS_PER_WIDE_INT == 64
2391 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2392 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2393 #else
2394 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2395 (~high_bits) & 0xffffffff,
2396 DImode);
2397 #endif
2398 sparc_emit_set_const64 (temp, negated_const);
2399 }
2400
2401 /* If we are XOR'ing with -1, then we should emit a one's complement
2402 instead. This way the combiner will notice logical operations
2403 such as ANDN later on and substitute. */
2404 if (trailing_bits == 0x3ff)
2405 {
2406 emit_insn (gen_rtx_SET (VOIDmode, op0,
2407 gen_rtx_NOT (DImode, temp)));
2408 }
2409 else
2410 {
2411 emit_insn (gen_rtx_SET (VOIDmode,
2412 op0,
2413 gen_safe_XOR64 (temp,
2414 (-0x400 | trailing_bits))));
2415 }
2416 return;
2417 }
2418
2419 /* 1) sethi %hi(xxx), %reg
2420 * or %reg, %lo(xxx), %reg
2421 * sllx %reg, yyy, %reg
2422 *
2423 * ??? This is just a generalized version of the low_bits==0
2424 * thing above, FIXME...
2425 */
2426 if ((highest_bit_set - lowest_bit_set) < 32)
2427 {
2428 unsigned HOST_WIDE_INT focus_bits =
2429 create_simple_focus_bits (high_bits, low_bits,
2430 lowest_bit_set, 0);
2431
2432 /* We can't get here in this state. */
2433 if (highest_bit_set < 32
2434 || lowest_bit_set >= 32)
2435 abort ();
2436
2437 /* So what we know is that the set bits straddle the
2438 middle of the 64-bit word. */
2439 sparc_emit_set_const64_quick2 (op0, temp,
2440 focus_bits, 0,
2441 lowest_bit_set);
2442 return;
2443 }
2444
2445 /* 1) sethi %hi(high_bits), %reg
2446 * or %reg, %lo(high_bits), %reg
2447 * sllx %reg, 32, %reg
2448 * or %reg, low_bits, %reg
2449 */
2450 if (SPARC_SIMM13_P(low_bits)
2451 && ((int)low_bits > 0))
2452 {
2453 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2454 return;
2455 }
2456
2457 /* The easiest way when all else fails, is full decomposition. */
2458 #if 0
2459 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2460 high_bits, low_bits, ~high_bits, ~low_bits);
2461 #endif
2462 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2463 }
2464
2465 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2466 return the mode to be used for the comparison. For floating-point,
2467 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2468 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2469 processing is needed. */
2470
2471 enum machine_mode
2472 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2473 {
2474 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2475 {
2476 switch (op)
2477 {
2478 case EQ:
2479 case NE:
2480 case UNORDERED:
2481 case ORDERED:
2482 case UNLT:
2483 case UNLE:
2484 case UNGT:
2485 case UNGE:
2486 case UNEQ:
2487 case LTGT:
2488 return CCFPmode;
2489
2490 case LT:
2491 case LE:
2492 case GT:
2493 case GE:
2494 return CCFPEmode;
2495
2496 default:
2497 abort ();
2498 }
2499 }
2500 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2501 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2502 {
2503 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2504 return CCX_NOOVmode;
2505 else
2506 return CC_NOOVmode;
2507 }
2508 else
2509 {
2510 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2511 return CCXmode;
2512 else
2513 return CCmode;
2514 }
2515 }
2516
2517 /* X and Y are two things to compare using CODE. Emit the compare insn and
2518 return the rtx for the cc reg in the proper mode. */
2519
2520 rtx
2521 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2522 {
2523 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2524 rtx cc_reg;
2525
2526 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2527 fcc regs (cse can't tell they're really call clobbered regs and will
2528 remove a duplicate comparison even if there is an intervening function
2529 call - it will then try to reload the cc reg via an int reg which is why
2530 we need the movcc patterns). It is possible to provide the movcc
2531 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2532 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2533 to tell cse that CCFPE mode registers (even pseudos) are call
2534 clobbered. */
2535
2536 /* ??? This is an experiment. Rather than making changes to cse which may
2537 or may not be easy/clean, we do our own cse. This is possible because
2538 we will generate hard registers. Cse knows they're call clobbered (it
2539 doesn't know the same thing about pseudos). If we guess wrong, no big
2540 deal, but if we win, great! */
2541
2542 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2543 #if 1 /* experiment */
2544 {
2545 int reg;
2546 /* We cycle through the registers to ensure they're all exercised. */
2547 static int next_fcc_reg = 0;
2548 /* Previous x,y for each fcc reg. */
2549 static rtx prev_args[4][2];
2550
2551 /* Scan prev_args for x,y. */
2552 for (reg = 0; reg < 4; reg++)
2553 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2554 break;
2555 if (reg == 4)
2556 {
2557 reg = next_fcc_reg;
2558 prev_args[reg][0] = x;
2559 prev_args[reg][1] = y;
2560 next_fcc_reg = (next_fcc_reg + 1) & 3;
2561 }
2562 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2563 }
2564 #else
2565 cc_reg = gen_reg_rtx (mode);
2566 #endif /* ! experiment */
2567 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2568 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2569 else
2570 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2571
2572 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2573 gen_rtx_COMPARE (mode, x, y)));
2574
2575 return cc_reg;
2576 }
2577
2578 /* This function is used for v9 only.
2579 CODE is the code for an Scc's comparison.
2580 OPERANDS[0] is the target of the Scc insn.
2581 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2582 been generated yet).
2583
2584 This function is needed to turn
2585
2586 (set (reg:SI 110)
2587 (gt (reg:CCX 100 %icc)
2588 (const_int 0)))
2589 into
2590 (set (reg:SI 110)
2591 (gt:DI (reg:CCX 100 %icc)
2592 (const_int 0)))
2593
2594 IE: The instruction recognizer needs to see the mode of the comparison to
2595 find the right instruction. We could use "gt:DI" right in the
2596 define_expand, but leaving it out allows us to handle DI, SI, etc.
2597
2598 We refer to the global sparc compare operands sparc_compare_op0 and
2599 sparc_compare_op1. */
2600
2601 int
2602 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2603 {
2604 rtx temp, op0, op1;
2605
2606 if (! TARGET_ARCH64
2607 && (GET_MODE (sparc_compare_op0) == DImode
2608 || GET_MODE (operands[0]) == DImode))
2609 return 0;
2610
2611 op0 = sparc_compare_op0;
2612 op1 = sparc_compare_op1;
2613
2614 /* Try to use the movrCC insns. */
2615 if (TARGET_ARCH64
2616 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2617 && op1 == const0_rtx
2618 && v9_regcmp_p (compare_code))
2619 {
2620 /* Special case for op0 != 0. This can be done with one instruction if
2621 operands[0] == sparc_compare_op0. */
2622
2623 if (compare_code == NE
2624 && GET_MODE (operands[0]) == DImode
2625 && rtx_equal_p (op0, operands[0]))
2626 {
2627 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2628 gen_rtx_IF_THEN_ELSE (DImode,
2629 gen_rtx_fmt_ee (compare_code, DImode,
2630 op0, const0_rtx),
2631 const1_rtx,
2632 operands[0])));
2633 return 1;
2634 }
2635
2636 if (reg_overlap_mentioned_p (operands[0], op0))
2637 {
2638 /* Handle the case where operands[0] == sparc_compare_op0.
2639 We "early clobber" the result. */
2640 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2641 emit_move_insn (op0, sparc_compare_op0);
2642 }
2643
2644 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2645 if (GET_MODE (op0) != DImode)
2646 {
2647 temp = gen_reg_rtx (DImode);
2648 convert_move (temp, op0, 0);
2649 }
2650 else
2651 temp = op0;
2652 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2653 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2654 gen_rtx_fmt_ee (compare_code, DImode,
2655 temp, const0_rtx),
2656 const1_rtx,
2657 operands[0])));
2658 return 1;
2659 }
2660 else
2661 {
2662 operands[1] = gen_compare_reg (compare_code, op0, op1);
2663
2664 switch (GET_MODE (operands[1]))
2665 {
2666 case CCmode :
2667 case CCXmode :
2668 case CCFPEmode :
2669 case CCFPmode :
2670 break;
2671 default :
2672 abort ();
2673 }
2674 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2675 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2676 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2677 gen_rtx_fmt_ee (compare_code,
2678 GET_MODE (operands[1]),
2679 operands[1], const0_rtx),
2680 const1_rtx, operands[0])));
2681 return 1;
2682 }
2683 }
2684
2685 /* Emit a conditional jump insn for the v9 architecture using comparison code
2686 CODE and jump target LABEL.
2687 This function exists to take advantage of the v9 brxx insns. */
2688
2689 void
2690 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2691 {
2692 emit_jump_insn (gen_rtx_SET (VOIDmode,
2693 pc_rtx,
2694 gen_rtx_IF_THEN_ELSE (VOIDmode,
2695 gen_rtx_fmt_ee (code, GET_MODE (op0),
2696 op0, const0_rtx),
2697 gen_rtx_LABEL_REF (VOIDmode, label),
2698 pc_rtx)));
2699 }
2700
2701 /* Generate a DFmode part of a hard TFmode register.
2702 REG is the TFmode hard register, LOW is 1 for the
2703 low 64bit of the register and 0 otherwise.
2704 */
2705 rtx
2706 gen_df_reg (rtx reg, int low)
2707 {
2708 int regno = REGNO (reg);
2709
2710 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2711 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2712 return gen_rtx_REG (DFmode, regno);
2713 }
2714 \f
2715 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2716 Unlike normal calls, TFmode operands are passed by reference. It is
2717 assumed that no more than 3 operands are required. */
2718
2719 static void
2720 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2721 {
2722 rtx ret_slot = NULL, arg[3], func_sym;
2723 int i;
2724
2725 /* We only expect to be called for conversions, unary, and binary ops. */
2726 if (nargs < 2 || nargs > 3)
2727 abort ();
2728
2729 for (i = 0; i < nargs; ++i)
2730 {
2731 rtx this_arg = operands[i];
2732 rtx this_slot;
2733
2734 /* TFmode arguments and return values are passed by reference. */
2735 if (GET_MODE (this_arg) == TFmode)
2736 {
2737 int force_stack_temp;
2738
2739 force_stack_temp = 0;
2740 if (TARGET_BUGGY_QP_LIB && i == 0)
2741 force_stack_temp = 1;
2742
2743 if (GET_CODE (this_arg) == MEM
2744 && ! force_stack_temp)
2745 this_arg = XEXP (this_arg, 0);
2746 else if (CONSTANT_P (this_arg)
2747 && ! force_stack_temp)
2748 {
2749 this_slot = force_const_mem (TFmode, this_arg);
2750 this_arg = XEXP (this_slot, 0);
2751 }
2752 else
2753 {
2754 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2755
2756 /* Operand 0 is the return value. We'll copy it out later. */
2757 if (i > 0)
2758 emit_move_insn (this_slot, this_arg);
2759 else
2760 ret_slot = this_slot;
2761
2762 this_arg = XEXP (this_slot, 0);
2763 }
2764 }
2765
2766 arg[i] = this_arg;
2767 }
2768
2769 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2770
2771 if (GET_MODE (operands[0]) == TFmode)
2772 {
2773 if (nargs == 2)
2774 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2775 arg[0], GET_MODE (arg[0]),
2776 arg[1], GET_MODE (arg[1]));
2777 else
2778 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2779 arg[0], GET_MODE (arg[0]),
2780 arg[1], GET_MODE (arg[1]),
2781 arg[2], GET_MODE (arg[2]));
2782
2783 if (ret_slot)
2784 emit_move_insn (operands[0], ret_slot);
2785 }
2786 else
2787 {
2788 rtx ret;
2789
2790 if (nargs != 2)
2791 abort ();
2792
2793 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2794 GET_MODE (operands[0]), 1,
2795 arg[1], GET_MODE (arg[1]));
2796
2797 if (ret != operands[0])
2798 emit_move_insn (operands[0], ret);
2799 }
2800 }
2801
2802 /* Expand soft-float TFmode calls to sparc abi routines. */
2803
2804 static void
2805 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2806 {
2807 const char *func;
2808
2809 switch (code)
2810 {
2811 case PLUS:
2812 func = "_Qp_add";
2813 break;
2814 case MINUS:
2815 func = "_Qp_sub";
2816 break;
2817 case MULT:
2818 func = "_Qp_mul";
2819 break;
2820 case DIV:
2821 func = "_Qp_div";
2822 break;
2823 default:
2824 abort ();
2825 }
2826
2827 emit_soft_tfmode_libcall (func, 3, operands);
2828 }
2829
2830 static void
2831 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2832 {
2833 const char *func;
2834
2835 switch (code)
2836 {
2837 case SQRT:
2838 func = "_Qp_sqrt";
2839 break;
2840 default:
2841 abort ();
2842 }
2843
2844 emit_soft_tfmode_libcall (func, 2, operands);
2845 }
2846
2847 static void
2848 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2849 {
2850 const char *func;
2851
2852 switch (code)
2853 {
2854 case FLOAT_EXTEND:
2855 switch (GET_MODE (operands[1]))
2856 {
2857 case SFmode:
2858 func = "_Qp_stoq";
2859 break;
2860 case DFmode:
2861 func = "_Qp_dtoq";
2862 break;
2863 default:
2864 abort ();
2865 }
2866 break;
2867
2868 case FLOAT_TRUNCATE:
2869 switch (GET_MODE (operands[0]))
2870 {
2871 case SFmode:
2872 func = "_Qp_qtos";
2873 break;
2874 case DFmode:
2875 func = "_Qp_qtod";
2876 break;
2877 default:
2878 abort ();
2879 }
2880 break;
2881
2882 case FLOAT:
2883 switch (GET_MODE (operands[1]))
2884 {
2885 case SImode:
2886 func = "_Qp_itoq";
2887 break;
2888 case DImode:
2889 func = "_Qp_xtoq";
2890 break;
2891 default:
2892 abort ();
2893 }
2894 break;
2895
2896 case UNSIGNED_FLOAT:
2897 switch (GET_MODE (operands[1]))
2898 {
2899 case SImode:
2900 func = "_Qp_uitoq";
2901 break;
2902 case DImode:
2903 func = "_Qp_uxtoq";
2904 break;
2905 default:
2906 abort ();
2907 }
2908 break;
2909
2910 case FIX:
2911 switch (GET_MODE (operands[0]))
2912 {
2913 case SImode:
2914 func = "_Qp_qtoi";
2915 break;
2916 case DImode:
2917 func = "_Qp_qtox";
2918 break;
2919 default:
2920 abort ();
2921 }
2922 break;
2923
2924 case UNSIGNED_FIX:
2925 switch (GET_MODE (operands[0]))
2926 {
2927 case SImode:
2928 func = "_Qp_qtoui";
2929 break;
2930 case DImode:
2931 func = "_Qp_qtoux";
2932 break;
2933 default:
2934 abort ();
2935 }
2936 break;
2937
2938 default:
2939 abort ();
2940 }
2941
2942 emit_soft_tfmode_libcall (func, 2, operands);
2943 }
2944
2945 /* Expand a hard-float tfmode operation. All arguments must be in
2946 registers. */
2947
2948 static void
2949 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2950 {
2951 rtx op, dest;
2952
2953 if (GET_RTX_CLASS (code) == RTX_UNARY)
2954 {
2955 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2956 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2957 }
2958 else
2959 {
2960 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2961 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2962 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2963 operands[1], operands[2]);
2964 }
2965
2966 if (register_operand (operands[0], VOIDmode))
2967 dest = operands[0];
2968 else
2969 dest = gen_reg_rtx (GET_MODE (operands[0]));
2970
2971 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2972
2973 if (dest != operands[0])
2974 emit_move_insn (operands[0], dest);
2975 }
2976
2977 void
2978 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2979 {
2980 if (TARGET_HARD_QUAD)
2981 emit_hard_tfmode_operation (code, operands);
2982 else
2983 emit_soft_tfmode_binop (code, operands);
2984 }
2985
2986 void
2987 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2988 {
2989 if (TARGET_HARD_QUAD)
2990 emit_hard_tfmode_operation (code, operands);
2991 else
2992 emit_soft_tfmode_unop (code, operands);
2993 }
2994
2995 void
2996 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2997 {
2998 if (TARGET_HARD_QUAD)
2999 emit_hard_tfmode_operation (code, operands);
3000 else
3001 emit_soft_tfmode_cvt (code, operands);
3002 }
3003 \f
3004 /* Return nonzero if a branch/jump/call instruction will be emitting
3005 nop into its delay slot. */
3006
3007 int
3008 empty_delay_slot (rtx insn)
3009 {
3010 rtx seq;
3011
3012 /* If no previous instruction (should not happen), return true. */
3013 if (PREV_INSN (insn) == NULL)
3014 return 1;
3015
3016 seq = NEXT_INSN (PREV_INSN (insn));
3017 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3018 return 0;
3019
3020 return 1;
3021 }
3022
3023 /* Return nonzero if TRIAL can go into the call delay slot. */
3024
3025 int
3026 tls_call_delay (rtx trial)
3027 {
3028 rtx pat, unspec;
3029
3030 /* Binutils allows
3031 call __tls_get_addr, %tgd_call (foo)
3032 add %l7, %o0, %o0, %tgd_add (foo)
3033 while Sun as/ld does not. */
3034 if (TARGET_GNU_TLS || !TARGET_TLS)
3035 return 1;
3036
3037 pat = PATTERN (trial);
3038 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
3039 return 1;
3040
3041 unspec = XEXP (SET_DEST (pat), 1);
3042 if (GET_CODE (unspec) != UNSPEC
3043 || (XINT (unspec, 1) != UNSPEC_TLSGD
3044 && XINT (unspec, 1) != UNSPEC_TLSLDM))
3045 return 1;
3046
3047 return 0;
3048 }
3049
3050 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3051 instruction. RETURN_P is true if the v9 variant 'return' is to be
3052 considered in the test too.
3053
3054 TRIAL must be a SET whose destination is a REG appropriate for the
3055 'restore' instruction or, if RETURN_P is true, for the 'return'
3056 instruction. */
3057
3058 static int
3059 eligible_for_restore_insn (rtx trial, bool return_p)
3060 {
3061 rtx pat = PATTERN (trial);
3062 rtx src = SET_SRC (pat);
3063
3064 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3065 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3066 && arith_operand (src, GET_MODE (src)))
3067 {
3068 if (TARGET_ARCH64)
3069 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3070 else
3071 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3072 }
3073
3074 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3075 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3076 && arith_double_operand (src, GET_MODE (src)))
3077 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3078
3079 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3080 else if (! TARGET_FPU && register_operand (src, SFmode))
3081 return 1;
3082
3083 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3084 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3085 return 1;
3086
3087 /* If we have the 'return' instruction, anything that does not use
3088 local or output registers and can go into a delay slot wins. */
3089 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
3090 && (get_attr_in_uncond_branch_delay (trial)
3091 == IN_UNCOND_BRANCH_DELAY_TRUE))
3092 return 1;
3093
3094 /* The 'restore src1,src2,dest' pattern for SImode. */
3095 else if (GET_CODE (src) == PLUS
3096 && register_operand (XEXP (src, 0), SImode)
3097 && arith_operand (XEXP (src, 1), SImode))
3098 return 1;
3099
3100 /* The 'restore src1,src2,dest' pattern for DImode. */
3101 else if (GET_CODE (src) == PLUS
3102 && register_operand (XEXP (src, 0), DImode)
3103 && arith_double_operand (XEXP (src, 1), DImode))
3104 return 1;
3105
3106 /* The 'restore src1,%lo(src2),dest' pattern. */
3107 else if (GET_CODE (src) == LO_SUM
3108 && ! TARGET_CM_MEDMID
3109 && ((register_operand (XEXP (src, 0), SImode)
3110 && immediate_operand (XEXP (src, 1), SImode))
3111 || (TARGET_ARCH64
3112 && register_operand (XEXP (src, 0), DImode)
3113 && immediate_operand (XEXP (src, 1), DImode))))
3114 return 1;
3115
3116 /* The 'restore src,src,dest' pattern. */
3117 else if (GET_CODE (src) == ASHIFT
3118 && (register_operand (XEXP (src, 0), SImode)
3119 || register_operand (XEXP (src, 0), DImode))
3120 && XEXP (src, 1) == const1_rtx)
3121 return 1;
3122
3123 return 0;
3124 }
3125
3126 /* Return nonzero if TRIAL can go into the function return's
3127 delay slot. */
3128
3129 int
3130 eligible_for_return_delay (rtx trial)
3131 {
3132 int leaf_function_p = current_function_uses_only_leaf_regs;
3133 rtx pat;
3134
3135 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3136 return 0;
3137
3138 if (get_attr_length (trial) != 1)
3139 return 0;
3140
3141 /* If there are any call-saved registers, we should scan TRIAL if it
3142 does not reference them. For now just make it easy. */
3143 if (num_gfregs)
3144 return 0;
3145
3146 /* If the function uses __builtin_eh_return, the eh_return machinery
3147 occupies the delay slot. */
3148 if (current_function_calls_eh_return)
3149 return 0;
3150
3151 /* In the case of a true leaf function, anything can go into the slot. */
3152 if (leaf_function_p)
3153 return get_attr_in_uncond_branch_delay (trial)
3154 == IN_UNCOND_BRANCH_DELAY_TRUE;
3155
3156 pat = PATTERN (trial);
3157
3158 /* Otherwise, only operations which can be done in tandem with
3159 a `restore' or `return' insn can go into the delay slot. */
3160 if (GET_CODE (SET_DEST (pat)) != REG
3161 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
3162 return 0;
3163
3164 /* If this instruction sets up floating point register and we have a return
3165 instruction, it can probably go in. But restore will not work
3166 with FP_REGS. */
3167 if (REGNO (SET_DEST (pat)) >= 32)
3168 return (TARGET_V9
3169 && ! epilogue_renumber (&pat, 1)
3170 && (get_attr_in_uncond_branch_delay (trial)
3171 == IN_UNCOND_BRANCH_DELAY_TRUE));
3172
3173 return eligible_for_restore_insn (trial, true);
3174 }
3175
3176 /* Return nonzero if TRIAL can go into the sibling call's
3177 delay slot. */
3178
3179 int
3180 eligible_for_sibcall_delay (rtx trial)
3181 {
3182 int leaf_function_p = current_function_uses_only_leaf_regs;
3183 rtx pat;
3184
3185 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3186 return 0;
3187
3188 if (get_attr_length (trial) != 1)
3189 return 0;
3190
3191 pat = PATTERN (trial);
3192
3193 if (leaf_function_p)
3194 {
3195 /* If the tail call is done using the call instruction,
3196 we have to restore %o7 in the delay slot. */
3197 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3198 return 0;
3199
3200 /* %g1 is used to build the function address */
3201 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3202 return 0;
3203
3204 return 1;
3205 }
3206
3207 /* Otherwise, only operations which can be done in tandem with
3208 a `restore' insn can go into the delay slot. */
3209 if (GET_CODE (SET_DEST (pat)) != REG
3210 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3211 || REGNO (SET_DEST (pat)) >= 32)
3212 return 0;
3213
3214 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3215 in most cases. */
3216 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3217 return 0;
3218
3219 return eligible_for_restore_insn (trial, false);
3220 }
3221
3222 int
3223 short_branch (int uid1, int uid2)
3224 {
3225 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3226
3227 /* Leave a few words of "slop". */
3228 if (delta >= -1023 && delta <= 1022)
3229 return 1;
3230
3231 return 0;
3232 }
3233
3234 /* Return nonzero if REG is not used after INSN.
3235 We assume REG is a reload reg, and therefore does
3236 not live past labels or calls or jumps. */
3237 int
3238 reg_unused_after (rtx reg, rtx insn)
3239 {
3240 enum rtx_code code, prev_code = UNKNOWN;
3241
3242 while ((insn = NEXT_INSN (insn)))
3243 {
3244 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3245 return 1;
3246
3247 code = GET_CODE (insn);
3248 if (GET_CODE (insn) == CODE_LABEL)
3249 return 1;
3250
3251 if (INSN_P (insn))
3252 {
3253 rtx set = single_set (insn);
3254 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3255 if (set && in_src)
3256 return 0;
3257 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3258 return 1;
3259 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3260 return 0;
3261 }
3262 prev_code = code;
3263 }
3264 return 1;
3265 }
3266 \f
3267 /* Determine if it's legal to put X into the constant pool. This
3268 is not possible if X contains the address of a symbol that is
3269 not constant (TLS) or not known at final link time (PIC). */
3270
3271 static bool
3272 sparc_cannot_force_const_mem (rtx x)
3273 {
3274 switch (GET_CODE (x))
3275 {
3276 case CONST_INT:
3277 case CONST_DOUBLE:
3278 /* Accept all non-symbolic constants. */
3279 return false;
3280
3281 case LABEL_REF:
3282 /* Labels are OK iff we are non-PIC. */
3283 return flag_pic != 0;
3284
3285 case SYMBOL_REF:
3286 /* 'Naked' TLS symbol references are never OK,
3287 non-TLS symbols are OK iff we are non-PIC. */
3288 if (SYMBOL_REF_TLS_MODEL (x))
3289 return true;
3290 else
3291 return flag_pic != 0;
3292
3293 case CONST:
3294 return sparc_cannot_force_const_mem (XEXP (x, 0));
3295 case PLUS:
3296 case MINUS:
3297 return sparc_cannot_force_const_mem (XEXP (x, 0))
3298 || sparc_cannot_force_const_mem (XEXP (x, 1));
3299 case UNSPEC:
3300 return true;
3301 default:
3302 abort ();
3303 }
3304 }
3305 \f
3306 /* The table we use to reference PIC data. */
3307 static GTY(()) rtx global_offset_table;
3308
3309 /* The function we use to get at it. */
3310 static GTY(()) rtx add_pc_to_pic_symbol;
3311 static GTY(()) char add_pc_to_pic_symbol_name[256];
3312
3313 /* Ensure that we are not using patterns that are not OK with PIC. */
3314
3315 int
3316 check_pic (int i)
3317 {
3318 switch (flag_pic)
3319 {
3320 case 1:
3321 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3322 || (GET_CODE (recog_data.operand[i]) == CONST
3323 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3324 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3325 == global_offset_table)
3326 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3327 == CONST))))
3328 abort ();
3329 case 2:
3330 default:
3331 return 1;
3332 }
3333 }
3334
3335 /* Return true if X is an address which needs a temporary register when
3336 reloaded while generating PIC code. */
3337
3338 int
3339 pic_address_needs_scratch (rtx x)
3340 {
3341 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3342 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3343 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3344 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3345 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3346 return 1;
3347
3348 return 0;
3349 }
3350
3351 /* Determine if a given RTX is a valid constant. We already know this
3352 satisfies CONSTANT_P. */
3353
3354 bool
3355 legitimate_constant_p (rtx x)
3356 {
3357 rtx inner;
3358
3359 switch (GET_CODE (x))
3360 {
3361 case SYMBOL_REF:
3362 /* TLS symbols are not constant. */
3363 if (SYMBOL_REF_TLS_MODEL (x))
3364 return false;
3365 break;
3366
3367 case CONST:
3368 inner = XEXP (x, 0);
3369
3370 /* Offsets of TLS symbols are never valid.
3371 Discourage CSE from creating them. */
3372 if (GET_CODE (inner) == PLUS
3373 && tls_symbolic_operand (XEXP (inner, 0)))
3374 return false;
3375 break;
3376
3377 case CONST_DOUBLE:
3378 if (GET_MODE (x) == VOIDmode)
3379 return true;
3380
3381 /* Floating point constants are generally not ok.
3382 The only exception is 0.0 in VIS. */
3383 if (TARGET_VIS
3384 && (GET_MODE (x) == SFmode
3385 || GET_MODE (x) == DFmode
3386 || GET_MODE (x) == TFmode)
3387 && fp_zero_operand (x, GET_MODE (x)))
3388 return true;
3389
3390 return false;
3391
3392 default:
3393 break;
3394 }
3395
3396 return true;
3397 }
3398
3399 /* Determine if a given RTX is a valid constant address. */
3400
3401 bool
3402 constant_address_p (rtx x)
3403 {
3404 switch (GET_CODE (x))
3405 {
3406 case LABEL_REF:
3407 case CONST_INT:
3408 case HIGH:
3409 return true;
3410
3411 case CONST:
3412 if (flag_pic && pic_address_needs_scratch (x))
3413 return false;
3414 return legitimate_constant_p (x);
3415
3416 case SYMBOL_REF:
3417 return !flag_pic && legitimate_constant_p (x);
3418
3419 default:
3420 return false;
3421 }
3422 }
3423
3424 /* Nonzero if the constant value X is a legitimate general operand
3425 when generating PIC code. It is given that flag_pic is on and
3426 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3427
3428 bool
3429 legitimate_pic_operand_p (rtx x)
3430 {
3431 if (pic_address_needs_scratch (x))
3432 return false;
3433 if (tls_symbolic_operand (x)
3434 || (GET_CODE (x) == CONST
3435 && GET_CODE (XEXP (x, 0)) == PLUS
3436 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3437 return false;
3438 return true;
3439 }
3440
3441 /* Return nonzero if ADDR is a valid memory address.
3442 STRICT specifies whether strict register checking applies. */
3443
3444 int
3445 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3446 {
3447 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3448
3449 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3450 rs1 = addr;
3451 else if (GET_CODE (addr) == PLUS)
3452 {
3453 rs1 = XEXP (addr, 0);
3454 rs2 = XEXP (addr, 1);
3455
3456 /* Canonicalize. REG comes first, if there are no regs,
3457 LO_SUM comes first. */
3458 if (!REG_P (rs1)
3459 && GET_CODE (rs1) != SUBREG
3460 && (REG_P (rs2)
3461 || GET_CODE (rs2) == SUBREG
3462 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3463 {
3464 rs1 = XEXP (addr, 1);
3465 rs2 = XEXP (addr, 0);
3466 }
3467
3468 if ((flag_pic == 1
3469 && rs1 == pic_offset_table_rtx
3470 && !REG_P (rs2)
3471 && GET_CODE (rs2) != SUBREG
3472 && GET_CODE (rs2) != LO_SUM
3473 && GET_CODE (rs2) != MEM
3474 && !tls_symbolic_operand (rs2)
3475 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3476 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3477 || ((REG_P (rs1)
3478 || GET_CODE (rs1) == SUBREG)
3479 && RTX_OK_FOR_OFFSET_P (rs2)))
3480 {
3481 imm1 = rs2;
3482 rs2 = NULL;
3483 }
3484 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3485 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3486 {
3487 /* We prohibit REG + REG for TFmode when there are no instructions
3488 which accept REG+REG instructions. We do this because REG+REG
3489 is not an offsetable address. If we get the situation in reload
3490 where source and destination of a movtf pattern are both MEMs with
3491 REG+REG address, then only one of them gets converted to an
3492 offsetable address. */
3493 if (mode == TFmode
3494 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3495 && TARGET_HARD_QUAD))
3496 return 0;
3497
3498 /* We prohibit REG + REG on ARCH32 if not optimizing for
3499 DFmode/DImode because then mem_min_alignment is likely to be zero
3500 after reload and the forced split would lack a matching splitter
3501 pattern. */
3502 if (TARGET_ARCH32 && !optimize
3503 && (mode == DFmode || mode == DImode))
3504 return 0;
3505 }
3506 else if (USE_AS_OFFSETABLE_LO10
3507 && GET_CODE (rs1) == LO_SUM
3508 && TARGET_ARCH64
3509 && ! TARGET_CM_MEDMID
3510 && RTX_OK_FOR_OLO10_P (rs2))
3511 {
3512 imm2 = rs2;
3513 rs2 = NULL;
3514 imm1 = XEXP (rs1, 1);
3515 rs1 = XEXP (rs1, 0);
3516 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3517 return 0;
3518 }
3519 }
3520 else if (GET_CODE (addr) == LO_SUM)
3521 {
3522 rs1 = XEXP (addr, 0);
3523 imm1 = XEXP (addr, 1);
3524
3525 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3526 return 0;
3527
3528 /* We can't allow TFmode, because an offset greater than or equal to the
3529 alignment (8) may cause the LO_SUM to overflow if !v9. */
3530 if (mode == TFmode && !TARGET_V9)
3531 return 0;
3532 }
3533 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3534 return 1;
3535 else
3536 return 0;
3537
3538 if (GET_CODE (rs1) == SUBREG)
3539 rs1 = SUBREG_REG (rs1);
3540 if (!REG_P (rs1))
3541 return 0;
3542
3543 if (rs2)
3544 {
3545 if (GET_CODE (rs2) == SUBREG)
3546 rs2 = SUBREG_REG (rs2);
3547 if (!REG_P (rs2))
3548 return 0;
3549 }
3550
3551 if (strict)
3552 {
3553 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3554 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3555 return 0;
3556 }
3557 else
3558 {
3559 if ((REGNO (rs1) >= 32
3560 && REGNO (rs1) != FRAME_POINTER_REGNUM
3561 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3562 || (rs2
3563 && (REGNO (rs2) >= 32
3564 && REGNO (rs2) != FRAME_POINTER_REGNUM
3565 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3566 return 0;
3567 }
3568 return 1;
3569 }
3570
3571 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3572
3573 static GTY(()) rtx sparc_tls_symbol;
3574 static rtx
3575 sparc_tls_get_addr (void)
3576 {
3577 if (!sparc_tls_symbol)
3578 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3579
3580 return sparc_tls_symbol;
3581 }
3582
3583 static rtx
3584 sparc_tls_got (void)
3585 {
3586 rtx temp;
3587 if (flag_pic)
3588 {
3589 current_function_uses_pic_offset_table = 1;
3590 return pic_offset_table_rtx;
3591 }
3592
3593 if (!global_offset_table)
3594 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3595 temp = gen_reg_rtx (Pmode);
3596 emit_move_insn (temp, global_offset_table);
3597 return temp;
3598 }
3599
3600
3601 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3602 this (thread-local) address. */
3603
3604 rtx
3605 legitimize_tls_address (rtx addr)
3606 {
3607 rtx temp1, temp2, temp3, ret, o0, got, insn;
3608
3609 if (no_new_pseudos)
3610 abort ();
3611
3612 if (GET_CODE (addr) == SYMBOL_REF)
3613 switch (SYMBOL_REF_TLS_MODEL (addr))
3614 {
3615 case TLS_MODEL_GLOBAL_DYNAMIC:
3616 start_sequence ();
3617 temp1 = gen_reg_rtx (SImode);
3618 temp2 = gen_reg_rtx (SImode);
3619 ret = gen_reg_rtx (Pmode);
3620 o0 = gen_rtx_REG (Pmode, 8);
3621 got = sparc_tls_got ();
3622 emit_insn (gen_tgd_hi22 (temp1, addr));
3623 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3624 if (TARGET_ARCH32)
3625 {
3626 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3627 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3628 addr, const1_rtx));
3629 }
3630 else
3631 {
3632 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3633 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3634 addr, const1_rtx));
3635 }
3636 CALL_INSN_FUNCTION_USAGE (insn)
3637 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3638 CALL_INSN_FUNCTION_USAGE (insn));
3639 insn = get_insns ();
3640 end_sequence ();
3641 emit_libcall_block (insn, ret, o0, addr);
3642 break;
3643
3644 case TLS_MODEL_LOCAL_DYNAMIC:
3645 start_sequence ();
3646 temp1 = gen_reg_rtx (SImode);
3647 temp2 = gen_reg_rtx (SImode);
3648 temp3 = gen_reg_rtx (Pmode);
3649 ret = gen_reg_rtx (Pmode);
3650 o0 = gen_rtx_REG (Pmode, 8);
3651 got = sparc_tls_got ();
3652 emit_insn (gen_tldm_hi22 (temp1));
3653 emit_insn (gen_tldm_lo10 (temp2, temp1));
3654 if (TARGET_ARCH32)
3655 {
3656 emit_insn (gen_tldm_add32 (o0, got, temp2));
3657 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3658 const1_rtx));
3659 }
3660 else
3661 {
3662 emit_insn (gen_tldm_add64 (o0, got, temp2));
3663 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3664 const1_rtx));
3665 }
3666 CALL_INSN_FUNCTION_USAGE (insn)
3667 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3668 CALL_INSN_FUNCTION_USAGE (insn));
3669 insn = get_insns ();
3670 end_sequence ();
3671 emit_libcall_block (insn, temp3, o0,
3672 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3673 UNSPEC_TLSLD_BASE));
3674 temp1 = gen_reg_rtx (SImode);
3675 temp2 = gen_reg_rtx (SImode);
3676 emit_insn (gen_tldo_hix22 (temp1, addr));
3677 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3678 if (TARGET_ARCH32)
3679 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3680 else
3681 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3682 break;
3683
3684 case TLS_MODEL_INITIAL_EXEC:
3685 temp1 = gen_reg_rtx (SImode);
3686 temp2 = gen_reg_rtx (SImode);
3687 temp3 = gen_reg_rtx (Pmode);
3688 got = sparc_tls_got ();
3689 emit_insn (gen_tie_hi22 (temp1, addr));
3690 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3691 if (TARGET_ARCH32)
3692 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3693 else
3694 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3695 if (TARGET_SUN_TLS)
3696 {
3697 ret = gen_reg_rtx (Pmode);
3698 if (TARGET_ARCH32)
3699 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3700 temp3, addr));
3701 else
3702 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3703 temp3, addr));
3704 }
3705 else
3706 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3707 break;
3708
3709 case TLS_MODEL_LOCAL_EXEC:
3710 temp1 = gen_reg_rtx (Pmode);
3711 temp2 = gen_reg_rtx (Pmode);
3712 if (TARGET_ARCH32)
3713 {
3714 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3715 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3716 }
3717 else
3718 {
3719 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3720 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3721 }
3722 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3723 break;
3724
3725 default:
3726 abort ();
3727 }
3728
3729 else
3730 abort (); /* for now ... */
3731
3732 return ret;
3733 }
3734
3735
3736 /* Legitimize PIC addresses. If the address is already position-independent,
3737 we return ORIG. Newly generated position-independent addresses go into a
3738 reg. This is REG if nonzero, otherwise we allocate register(s) as
3739 necessary. */
3740
3741 rtx
3742 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3743 rtx reg)
3744 {
3745 if (GET_CODE (orig) == SYMBOL_REF)
3746 {
3747 rtx pic_ref, address;
3748 rtx insn;
3749
3750 if (reg == 0)
3751 {
3752 if (reload_in_progress || reload_completed)
3753 abort ();
3754 else
3755 reg = gen_reg_rtx (Pmode);
3756 }
3757
3758 if (flag_pic == 2)
3759 {
3760 /* If not during reload, allocate another temp reg here for loading
3761 in the address, so that these instructions can be optimized
3762 properly. */
3763 rtx temp_reg = ((reload_in_progress || reload_completed)
3764 ? reg : gen_reg_rtx (Pmode));
3765
3766 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3767 won't get confused into thinking that these two instructions
3768 are loading in the true address of the symbol. If in the
3769 future a PIC rtx exists, that should be used instead. */
3770 if (Pmode == SImode)
3771 {
3772 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3773 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3774 }
3775 else
3776 {
3777 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3778 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3779 }
3780 address = temp_reg;
3781 }
3782 else
3783 address = orig;
3784
3785 pic_ref = gen_rtx_MEM (Pmode,
3786 gen_rtx_PLUS (Pmode,
3787 pic_offset_table_rtx, address));
3788 current_function_uses_pic_offset_table = 1;
3789 RTX_UNCHANGING_P (pic_ref) = 1;
3790 insn = emit_move_insn (reg, pic_ref);
3791 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3792 by loop. */
3793 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3794 REG_NOTES (insn));
3795 return reg;
3796 }
3797 else if (GET_CODE (orig) == CONST)
3798 {
3799 rtx base, offset;
3800
3801 if (GET_CODE (XEXP (orig, 0)) == PLUS
3802 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3803 return orig;
3804
3805 if (reg == 0)
3806 {
3807 if (reload_in_progress || reload_completed)
3808 abort ();
3809 else
3810 reg = gen_reg_rtx (Pmode);
3811 }
3812
3813 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3814 {
3815 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3816 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3817 base == reg ? 0 : reg);
3818 }
3819 else
3820 abort ();
3821
3822 if (GET_CODE (offset) == CONST_INT)
3823 {
3824 if (SMALL_INT (offset))
3825 return plus_constant (base, INTVAL (offset));
3826 else if (! reload_in_progress && ! reload_completed)
3827 offset = force_reg (Pmode, offset);
3828 else
3829 /* If we reach here, then something is seriously wrong. */
3830 abort ();
3831 }
3832 return gen_rtx_PLUS (Pmode, base, offset);
3833 }
3834 else if (GET_CODE (orig) == LABEL_REF)
3835 /* ??? Why do we do this? */
3836 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3837 the register is live instead, in case it is eliminated. */
3838 current_function_uses_pic_offset_table = 1;
3839
3840 return orig;
3841 }
3842
3843 /* Try machine-dependent ways of modifying an illegitimate address X
3844 to be legitimate. If we find one, return the new, valid address.
3845
3846 OLDX is the address as it was before break_out_memory_refs was called.
3847 In some cases it is useful to look at this to decide what needs to be done.
3848
3849 MODE is the mode of the operand pointed to by X. */
3850
3851 rtx
3852 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3853 {
3854 rtx orig_x = x;
3855
3856 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3857 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3858 force_operand (XEXP (x, 0), NULL_RTX));
3859 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3860 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3861 force_operand (XEXP (x, 1), NULL_RTX));
3862 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3863 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3864 XEXP (x, 1));
3865 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3866 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3867 force_operand (XEXP (x, 1), NULL_RTX));
3868
3869 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3870 return x;
3871
3872 if (tls_symbolic_operand (x))
3873 x = legitimize_tls_address (x);
3874 else if (flag_pic)
3875 x = legitimize_pic_address (x, mode, 0);
3876 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3877 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3878 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3879 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3880 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3881 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3882 else if (GET_CODE (x) == SYMBOL_REF
3883 || GET_CODE (x) == CONST
3884 || GET_CODE (x) == LABEL_REF)
3885 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3886 return x;
3887 }
3888
3889 /* Emit the special PIC prologue. */
3890
3891 static void
3892 load_pic_register (void)
3893 {
3894 int orig_flag_pic = flag_pic;
3895
3896 /* If we haven't emitted the special helper function, do so now. */
3897 if (add_pc_to_pic_symbol_name[0] == 0)
3898 {
3899 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3900 int align;
3901
3902 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name, "LADDPC", 0);
3903 text_section ();
3904
3905 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3906 if (align > 0)
3907 ASM_OUTPUT_ALIGN (asm_out_file, align);
3908 ASM_OUTPUT_LABEL (asm_out_file, add_pc_to_pic_symbol_name);
3909 if (flag_delayed_branch)
3910 fprintf (asm_out_file, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3911 pic_name, pic_name);
3912 else
3913 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp %%o7+8\n\t nop\n",
3914 pic_name, pic_name);
3915 }
3916
3917 /* Initialize every time through, since we can't easily
3918 know this to be permanent. */
3919 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3920 add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
3921
3922 flag_pic = 0;
3923 emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
3924 add_pc_to_pic_symbol));
3925 flag_pic = orig_flag_pic;
3926
3927 /* Need to emit this whether or not we obey regdecls,
3928 since setjmp/longjmp can cause life info to screw up.
3929 ??? In the case where we don't obey regdecls, this is not sufficient
3930 since we may not fall out the bottom. */
3931 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3932 }
3933 \f
3934 /* Return 1 if RTX is a MEM which is known to be aligned to at
3935 least a DESIRED byte boundary. */
3936
3937 int
3938 mem_min_alignment (rtx mem, int desired)
3939 {
3940 rtx addr, base, offset;
3941
3942 /* If it's not a MEM we can't accept it. */
3943 if (GET_CODE (mem) != MEM)
3944 return 0;
3945
3946 addr = XEXP (mem, 0);
3947 base = offset = NULL_RTX;
3948 if (GET_CODE (addr) == PLUS)
3949 {
3950 if (GET_CODE (XEXP (addr, 0)) == REG)
3951 {
3952 base = XEXP (addr, 0);
3953
3954 /* What we are saying here is that if the base
3955 REG is aligned properly, the compiler will make
3956 sure any REG based index upon it will be so
3957 as well. */
3958 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3959 offset = XEXP (addr, 1);
3960 else
3961 offset = const0_rtx;
3962 }
3963 }
3964 else if (GET_CODE (addr) == REG)
3965 {
3966 base = addr;
3967 offset = const0_rtx;
3968 }
3969
3970 if (base != NULL_RTX)
3971 {
3972 int regno = REGNO (base);
3973
3974 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3975 {
3976 /* Check if the compiler has recorded some information
3977 about the alignment of the base REG. If reload has
3978 completed, we already matched with proper alignments.
3979 If not running global_alloc, reload might give us
3980 unaligned pointer to local stack though. */
3981 if (((cfun != 0
3982 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3983 || (optimize && reload_completed))
3984 && (INTVAL (offset) & (desired - 1)) == 0)
3985 return 1;
3986 }
3987 else
3988 {
3989 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3990 return 1;
3991 }
3992 }
3993 else if (! TARGET_UNALIGNED_DOUBLES
3994 || CONSTANT_P (addr)
3995 || GET_CODE (addr) == LO_SUM)
3996 {
3997 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3998 is true, in which case we can only assume that an access is aligned if
3999 it is to a constant address, or the address involves a LO_SUM. */
4000 return 1;
4001 }
4002
4003 /* An obviously unaligned address. */
4004 return 0;
4005 }
4006
4007 \f
4008 /* Vectors to keep interesting information about registers where it can easily
4009 be got. We used to use the actual mode value as the bit number, but there
4010 are more than 32 modes now. Instead we use two tables: one indexed by
4011 hard register number, and one indexed by mode. */
4012
4013 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4014 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4015 mapped into one sparc_mode_class mode. */
4016
4017 enum sparc_mode_class {
4018 S_MODE, D_MODE, T_MODE, O_MODE,
4019 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4020 CC_MODE, CCFP_MODE
4021 };
4022
4023 /* Modes for single-word and smaller quantities. */
4024 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4025
4026 /* Modes for double-word and smaller quantities. */
4027 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4028
4029 /* Modes for quad-word and smaller quantities. */
4030 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4031
4032 /* Modes for 8-word and smaller quantities. */
4033 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4034
4035 /* Modes for single-float quantities. We must allow any single word or
4036 smaller quantity. This is because the fix/float conversion instructions
4037 take integer inputs/outputs from the float registers. */
4038 #define SF_MODES (S_MODES)
4039
4040 /* Modes for double-float and smaller quantities. */
4041 #define DF_MODES (S_MODES | D_MODES)
4042
4043 /* Modes for double-float only quantities. */
4044 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4045
4046 /* Modes for quad-float only quantities. */
4047 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4048
4049 /* Modes for quad-float and smaller quantities. */
4050 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4051
4052 /* Modes for quad-float and double-float quantities. */
4053 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4054
4055 /* Modes for quad-float pair only quantities. */
4056 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4057
4058 /* Modes for quad-float pairs and smaller quantities. */
4059 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4060
4061 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4062
4063 /* Modes for condition codes. */
4064 #define CC_MODES (1 << (int) CC_MODE)
4065 #define CCFP_MODES (1 << (int) CCFP_MODE)
4066
4067 /* Value is 1 if register/mode pair is acceptable on sparc.
4068 The funny mixture of D and T modes is because integer operations
4069 do not specially operate on tetra quantities, so non-quad-aligned
4070 registers can hold quadword quantities (except %o4 and %i4 because
4071 they cross fixed registers). */
4072
4073 /* This points to either the 32 bit or the 64 bit version. */
4074 const int *hard_regno_mode_classes;
4075
4076 static const int hard_32bit_mode_classes[] = {
4077 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4078 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4079 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4080 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4081
4082 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4083 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4084 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4085 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4086
4087 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4088 and none can hold SFmode/SImode values. */
4089 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4090 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4091 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4092 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4093
4094 /* %fcc[0123] */
4095 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4096
4097 /* %icc */
4098 CC_MODES
4099 };
4100
4101 static const int hard_64bit_mode_classes[] = {
4102 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4103 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4104 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4105 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4106
4107 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4108 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4109 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4110 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4111
4112 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4113 and none can hold SFmode/SImode values. */
4114 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4115 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4116 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4117 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4118
4119 /* %fcc[0123] */
4120 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4121
4122 /* %icc */
4123 CC_MODES
4124 };
4125
4126 int sparc_mode_class [NUM_MACHINE_MODES];
4127
4128 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4129
4130 static void
4131 sparc_init_modes (void)
4132 {
4133 int i;
4134
4135 for (i = 0; i < NUM_MACHINE_MODES; i++)
4136 {
4137 switch (GET_MODE_CLASS (i))
4138 {
4139 case MODE_INT:
4140 case MODE_PARTIAL_INT:
4141 case MODE_COMPLEX_INT:
4142 if (GET_MODE_SIZE (i) <= 4)
4143 sparc_mode_class[i] = 1 << (int) S_MODE;
4144 else if (GET_MODE_SIZE (i) == 8)
4145 sparc_mode_class[i] = 1 << (int) D_MODE;
4146 else if (GET_MODE_SIZE (i) == 16)
4147 sparc_mode_class[i] = 1 << (int) T_MODE;
4148 else if (GET_MODE_SIZE (i) == 32)
4149 sparc_mode_class[i] = 1 << (int) O_MODE;
4150 else
4151 sparc_mode_class[i] = 0;
4152 break;
4153 case MODE_FLOAT:
4154 case MODE_COMPLEX_FLOAT:
4155 if (GET_MODE_SIZE (i) <= 4)
4156 sparc_mode_class[i] = 1 << (int) SF_MODE;
4157 else if (GET_MODE_SIZE (i) == 8)
4158 sparc_mode_class[i] = 1 << (int) DF_MODE;
4159 else if (GET_MODE_SIZE (i) == 16)
4160 sparc_mode_class[i] = 1 << (int) TF_MODE;
4161 else if (GET_MODE_SIZE (i) == 32)
4162 sparc_mode_class[i] = 1 << (int) OF_MODE;
4163 else
4164 sparc_mode_class[i] = 0;
4165 break;
4166 case MODE_CC:
4167 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4168 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4169 else
4170 sparc_mode_class[i] = 1 << (int) CC_MODE;
4171 break;
4172 default:
4173 sparc_mode_class[i] = 0;
4174 break;
4175 }
4176 }
4177
4178 if (TARGET_ARCH64)
4179 hard_regno_mode_classes = hard_64bit_mode_classes;
4180 else
4181 hard_regno_mode_classes = hard_32bit_mode_classes;
4182
4183 /* Initialize the array used by REGNO_REG_CLASS. */
4184 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4185 {
4186 if (i < 16 && TARGET_V8PLUS)
4187 sparc_regno_reg_class[i] = I64_REGS;
4188 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4189 sparc_regno_reg_class[i] = GENERAL_REGS;
4190 else if (i < 64)
4191 sparc_regno_reg_class[i] = FP_REGS;
4192 else if (i < 96)
4193 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4194 else if (i < 100)
4195 sparc_regno_reg_class[i] = FPCC_REGS;
4196 else
4197 sparc_regno_reg_class[i] = NO_REGS;
4198 }
4199 }
4200 \f
4201 /* Compute the frame size required by the function. This function is called
4202 during the reload pass and also by sparc_expand_prologue. */
4203
4204 HOST_WIDE_INT
4205 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4206 {
4207 int outgoing_args_size = (current_function_outgoing_args_size
4208 + REG_PARM_STACK_SPACE (current_function_decl));
4209 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4210 int i;
4211
4212 if (TARGET_ARCH64)
4213 {
4214 for (i = 0; i < 8; i++)
4215 if (regs_ever_live[i] && ! call_used_regs[i])
4216 n_regs += 2;
4217 }
4218 else
4219 {
4220 for (i = 0; i < 8; i += 2)
4221 if ((regs_ever_live[i] && ! call_used_regs[i])
4222 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4223 n_regs += 2;
4224 }
4225
4226 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4227 if ((regs_ever_live[i] && ! call_used_regs[i])
4228 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4229 n_regs += 2;
4230
4231 /* Set up values for use in prologue and epilogue. */
4232 num_gfregs = n_regs;
4233
4234 if (leaf_function_p
4235 && n_regs == 0
4236 && size == 0
4237 && current_function_outgoing_args_size == 0)
4238 actual_fsize = apparent_fsize = 0;
4239 else
4240 {
4241 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4242 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4243 apparent_fsize += n_regs * 4;
4244 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4245 }
4246
4247 /* Make sure nothing can clobber our register windows.
4248 If a SAVE must be done, or there is a stack-local variable,
4249 the register window area must be allocated.
4250 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4251 if (! leaf_function_p || size > 0)
4252 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4253
4254 return SPARC_STACK_ALIGN (actual_fsize);
4255 }
4256
4257 /* Output any necessary .register pseudo-ops. */
4258
4259 void
4260 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4261 {
4262 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4263 int i;
4264
4265 if (TARGET_ARCH32)
4266 return;
4267
4268 /* Check if %g[2367] were used without
4269 .register being printed for them already. */
4270 for (i = 2; i < 8; i++)
4271 {
4272 if (regs_ever_live [i]
4273 && ! sparc_hard_reg_printed [i])
4274 {
4275 sparc_hard_reg_printed [i] = 1;
4276 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4277 }
4278 if (i == 3) i = 5;
4279 }
4280 #endif
4281 }
4282
4283 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4284 as needed. LOW should be double-word aligned for 32-bit registers.
4285 Return the new OFFSET. */
4286
4287 #define SORR_SAVE 0
4288 #define SORR_RESTORE 1
4289
4290 static int
4291 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4292 {
4293 rtx mem, insn;
4294 int i;
4295
4296 if (TARGET_ARCH64 && high <= 32)
4297 {
4298 for (i = low; i < high; i++)
4299 {
4300 if (regs_ever_live[i] && ! call_used_regs[i])
4301 {
4302 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4303 set_mem_alias_set (mem, sparc_sr_alias_set);
4304 if (action == SORR_SAVE)
4305 {
4306 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4307 RTX_FRAME_RELATED_P (insn) = 1;
4308 }
4309 else /* action == SORR_RESTORE */
4310 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4311 offset += 8;
4312 }
4313 }
4314 }
4315 else
4316 {
4317 for (i = low; i < high; i += 2)
4318 {
4319 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4320 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4321 enum machine_mode mode;
4322 int regno;
4323
4324 if (reg0 && reg1)
4325 {
4326 mode = i < 32 ? DImode : DFmode;
4327 regno = i;
4328 }
4329 else if (reg0)
4330 {
4331 mode = i < 32 ? SImode : SFmode;
4332 regno = i;
4333 }
4334 else if (reg1)
4335 {
4336 mode = i < 32 ? SImode : SFmode;
4337 regno = i + 1;
4338 offset += 4;
4339 }
4340 else
4341 continue;
4342
4343 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4344 set_mem_alias_set (mem, sparc_sr_alias_set);
4345 if (action == SORR_SAVE)
4346 {
4347 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4348 RTX_FRAME_RELATED_P (insn) = 1;
4349 }
4350 else /* action == SORR_RESTORE */
4351 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4352
4353 /* Always preserve double-word alignment. */
4354 offset = (offset + 7) & -8;
4355 }
4356 }
4357
4358 return offset;
4359 }
4360
4361 /* Emit code to save call-saved registers. */
4362
4363 static void
4364 emit_save_regs (void)
4365 {
4366 HOST_WIDE_INT offset;
4367 rtx base;
4368
4369 offset = frame_base_offset - apparent_fsize;
4370
4371 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4372 {
4373 /* ??? This might be optimized a little as %g1 might already have a
4374 value close enough that a single add insn will do. */
4375 /* ??? Although, all of this is probably only a temporary fix
4376 because if %g1 can hold a function result, then
4377 sparc_expand_epilogue will lose (the result will be
4378 clobbered). */
4379 base = gen_rtx_REG (Pmode, 1);
4380 emit_move_insn (base, GEN_INT (offset));
4381 emit_insn (gen_rtx_SET (VOIDmode,
4382 base,
4383 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4384 offset = 0;
4385 }
4386 else
4387 base = frame_base_reg;
4388
4389 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4390 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4391 }
4392
4393 /* Emit code to restore call-saved registers. */
4394
4395 static void
4396 emit_restore_regs (void)
4397 {
4398 HOST_WIDE_INT offset;
4399 rtx base;
4400
4401 offset = frame_base_offset - apparent_fsize;
4402
4403 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4404 {
4405 base = gen_rtx_REG (Pmode, 1);
4406 emit_move_insn (base, GEN_INT (offset));
4407 emit_insn (gen_rtx_SET (VOIDmode,
4408 base,
4409 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4410 offset = 0;
4411 }
4412 else
4413 base = frame_base_reg;
4414
4415 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4416 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4417 }
4418
4419 /* Emit an increment for the stack pointer. */
4420
4421 static void
4422 emit_stack_pointer_increment (rtx increment)
4423 {
4424 if (TARGET_ARCH64)
4425 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4426 else
4427 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4428 }
4429
4430 /* Emit a decrement for the stack pointer. */
4431
4432 static void
4433 emit_stack_pointer_decrement (rtx decrement)
4434 {
4435 if (TARGET_ARCH64)
4436 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4437 else
4438 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4439 }
4440
4441 /* Expand the function prologue. The prologue is responsible for reserving
4442 storage for the frame, saving the call-saved registers and loading the
4443 PIC register if needed. */
4444
4445 void
4446 sparc_expand_prologue (void)
4447 {
4448 int leaf_function_p = current_function_uses_only_leaf_regs;
4449
4450 /* Need to use actual_fsize, since we are also allocating
4451 space for our callee (and our own register save area). */
4452 actual_fsize = sparc_compute_frame_size (get_frame_size(), leaf_function_p);
4453
4454 if (leaf_function_p)
4455 {
4456 frame_base_reg = stack_pointer_rtx;
4457 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4458 }
4459 else
4460 {
4461 frame_base_reg = hard_frame_pointer_rtx;
4462 frame_base_offset = SPARC_STACK_BIAS;
4463 }
4464
4465 if (actual_fsize == 0)
4466 /* do nothing. */ ;
4467 else if (leaf_function_p)
4468 {
4469 if (actual_fsize <= 4096)
4470 emit_stack_pointer_increment (GEN_INT (- actual_fsize));
4471 else if (actual_fsize <= 8192)
4472 {
4473 emit_stack_pointer_increment (GEN_INT (-4096));
4474 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4475 }
4476 else
4477 {
4478 rtx reg = gen_rtx_REG (Pmode, 1);
4479 emit_move_insn (reg, GEN_INT (-actual_fsize));
4480 emit_stack_pointer_increment (reg);
4481 }
4482 }
4483 else
4484 {
4485 if (actual_fsize <= 4096)
4486 emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4487 else if (actual_fsize <= 8192)
4488 {
4489 emit_insn (gen_save_register_window (GEN_INT (-4096)));
4490 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4491 }
4492 else
4493 {
4494 rtx reg = gen_rtx_REG (Pmode, 1);
4495 emit_move_insn (reg, GEN_INT (-actual_fsize));
4496 emit_insn (gen_save_register_window (reg));
4497 }
4498 }
4499
4500 /* Call-saved registers are saved just above the outgoing argument area. */
4501 if (num_gfregs)
4502 emit_save_regs ();
4503
4504 /* Load the PIC register if needed. */
4505 if (flag_pic && current_function_uses_pic_offset_table)
4506 load_pic_register ();
4507 }
4508
4509 /* This function generates the assembly code for function entry, which boils
4510 down to emitting the necessary .register directives. It also informs the
4511 DWARF-2 back-end on the layout of the frame.
4512
4513 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4514 an 8-byte block of memory. If any fpu reg is used in the function, we
4515 allocate such a block here, at the bottom of the frame, just in case it's
4516 needed." Could this explain the -8 in emit_restore_regs? */
4517
4518 static void
4519 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4520 {
4521 int leaf_function_p = current_function_uses_only_leaf_regs;
4522
4523 sparc_output_scratch_registers (file);
4524
4525 if (dwarf2out_do_frame () && actual_fsize)
4526 {
4527 char *label = dwarf2out_cfi_label ();
4528
4529 /* The canonical frame address refers to the top of the frame. */
4530 dwarf2out_def_cfa (label,
4531 leaf_function_p
4532 ? STACK_POINTER_REGNUM
4533 : HARD_FRAME_POINTER_REGNUM,
4534 frame_base_offset);
4535
4536 if (! leaf_function_p)
4537 {
4538 /* Note the register window save. This tells the unwinder that
4539 it needs to restore the window registers from the previous
4540 frame's window save area at 0(cfa). */
4541 dwarf2out_window_save (label);
4542
4543 /* The return address (-8) is now in %i7. */
4544 dwarf2out_return_reg (label, 31);
4545 }
4546 }
4547 }
4548
4549 /* Expand the function epilogue, either normal or part of a sibcall.
4550 We emit all the instructions except the return or the call. */
4551
4552 void
4553 sparc_expand_epilogue (void)
4554 {
4555 int leaf_function_p = current_function_uses_only_leaf_regs;
4556
4557 if (num_gfregs)
4558 emit_restore_regs ();
4559
4560 if (actual_fsize == 0)
4561 /* do nothing. */ ;
4562 else if (leaf_function_p)
4563 {
4564 if (actual_fsize <= 4096)
4565 emit_stack_pointer_decrement (GEN_INT (- actual_fsize));
4566 else if (actual_fsize <= 8192)
4567 {
4568 emit_stack_pointer_decrement (GEN_INT (-4096));
4569 emit_stack_pointer_decrement (GEN_INT (4096 - actual_fsize));
4570 }
4571 else
4572 {
4573 rtx reg = gen_rtx_REG (Pmode, 1);
4574 emit_move_insn (reg, GEN_INT (-actual_fsize));
4575 emit_stack_pointer_decrement (reg);
4576 }
4577 }
4578 }
4579
4580 /* This function generates the assembly code for function exit. */
4581
4582 static void
4583 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4584 {
4585 /* If code does not drop into the epilogue, we have to still output
4586 a dummy nop for the sake of sane backtraces. Otherwise, if the
4587 last two instructions of a function were "call foo; dslot;" this
4588 can make the return PC of foo (ie. address of call instruction
4589 plus 8) point to the first instruction in the next function. */
4590
4591 rtx insn, last_real_insn;
4592
4593 insn = get_last_insn ();
4594
4595 last_real_insn = prev_real_insn (insn);
4596 if (last_real_insn
4597 && GET_CODE (last_real_insn) == INSN
4598 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4599 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4600
4601 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4602 fputs("\tnop\n", file);
4603
4604 sparc_output_deferred_case_vectors ();
4605 }
4606
4607 /* Output a 'restore' instruction. */
4608
4609 static void
4610 output_restore (rtx pat)
4611 {
4612 rtx operands[3];
4613
4614 if (! pat)
4615 {
4616 fputs ("\t restore\n", asm_out_file);
4617 return;
4618 }
4619
4620 if (GET_CODE (pat) != SET)
4621 abort ();
4622
4623 operands[0] = SET_DEST (pat);
4624 pat = SET_SRC (pat);
4625
4626 switch (GET_CODE (pat))
4627 {
4628 case PLUS:
4629 operands[1] = XEXP (pat, 0);
4630 operands[2] = XEXP (pat, 1);
4631 output_asm_insn (" restore %r1, %2, %Y0", operands);
4632 break;
4633 case LO_SUM:
4634 operands[1] = XEXP (pat, 0);
4635 operands[2] = XEXP (pat, 1);
4636 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4637 break;
4638 case ASHIFT:
4639 operands[1] = XEXP (pat, 0);
4640 if (XEXP (pat, 1) != const1_rtx)
4641 abort();
4642 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4643 break;
4644 default:
4645 operands[1] = pat;
4646 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4647 break;
4648 }
4649 }
4650
4651 /* Output a return. */
4652
4653 const char *
4654 output_return (rtx insn)
4655 {
4656 int leaf_function_p = current_function_uses_only_leaf_regs;
4657 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4658 /* True if the caller has placed an "unimp" insn immediately after the call.
4659 This insn is used in the 32-bit ABI when calling a function that returns
4660 a non zero-sized structure. The 64-bit ABI doesn't have it. Be careful
4661 to have this test be the same as that used on the call. */
4662 bool sparc_skip_caller_unimp
4663 = ! TARGET_ARCH64
4664 && current_function_returns_struct
4665 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
4666 == INTEGER_CST)
4667 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)));
4668
4669 if (leaf_function_p)
4670 {
4671 /* This is a leaf function so we don't have to bother restoring the
4672 register window, which frees us from dealing with the convoluted
4673 semantics of restore/return. We simply output the jump to the
4674 return address and the insn in the delay slot, which usually is
4675 the substraction restoring the stack pointer %sp. */
4676
4677 if (current_function_calls_eh_return)
4678 abort ();
4679
4680 fprintf (asm_out_file, "\tjmp\t%%o7+%d\n", sparc_skip_caller_unimp ? 12 : 8);
4681
4682 if (delay_slot_filled_p)
4683 {
4684 rtx delay = NEXT_INSN (insn);
4685 if (! delay)
4686 abort ();
4687
4688 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4689 PATTERN (delay) = gen_blockage ();
4690 INSN_CODE (delay) = -1;
4691 }
4692 else
4693 fputs ("\t nop\n", asm_out_file);
4694 }
4695 else
4696 {
4697 /* This is a regular function so we have to restore the register window.
4698 We may have a pending insn for the delay slot, which will be either
4699 combined with the 'restore' instruction or put in the delay slot of
4700 the 'return' instruction. */
4701
4702 if (current_function_calls_eh_return)
4703 {
4704 /* If the function uses __builtin_eh_return, the eh_return
4705 machinery occupies the delay slot. */
4706 if (delay_slot_filled_p || sparc_skip_caller_unimp)
4707 abort ();
4708
4709 if (! flag_delayed_branch)
4710 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4711
4712 if (TARGET_V9)
4713 fputs ("\treturn\t%i7+8\n", asm_out_file);
4714 else
4715 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4716
4717 if (flag_delayed_branch)
4718 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4719 else
4720 fputs ("\t nop\n", asm_out_file);
4721 }
4722 else if (delay_slot_filled_p)
4723 {
4724 rtx delay, pat;
4725
4726 delay = NEXT_INSN (insn);
4727 if (! delay)
4728 abort ();
4729
4730 pat = PATTERN (delay);
4731
4732 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4733 {
4734 epilogue_renumber (&pat, 0);
4735 fprintf (asm_out_file, "\treturn\t%%i7+%d\n",
4736 sparc_skip_caller_unimp ? 12 : 8);
4737 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4738 }
4739 else
4740 {
4741 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n",
4742 sparc_skip_caller_unimp ? 12 : 8);
4743 output_restore (pat);
4744 }
4745
4746 PATTERN (delay) = gen_blockage ();
4747 INSN_CODE (delay) = -1;
4748 }
4749 else
4750 {
4751 /* The delay slot is empty. */
4752 if (TARGET_V9)
4753 fprintf (asm_out_file, "\treturn\t%%i7+%d\n\t nop\n",
4754 sparc_skip_caller_unimp ? 12 : 8);
4755 else if (flag_delayed_branch)
4756 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n\t restore\n",
4757 sparc_skip_caller_unimp ? 12 : 8);
4758 else
4759 fprintf (asm_out_file, "\trestore\n\tjmp\t%%o7+%d\n\t nop\n",
4760 sparc_skip_caller_unimp ? 12 : 8);
4761 }
4762 }
4763
4764 return "";
4765 }
4766
4767 /* Output a sibling call. */
4768
4769 const char *
4770 output_sibcall (rtx insn, rtx call_operand)
4771 {
4772 int leaf_function_p = current_function_uses_only_leaf_regs;
4773 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4774 rtx operands[1];
4775
4776 if (! flag_delayed_branch)
4777 abort();
4778
4779 operands[0] = call_operand;
4780
4781 if (leaf_function_p)
4782 {
4783 /* This is a leaf function so we don't have to bother restoring the
4784 register window. We simply output the jump to the function and
4785 the insn in the delay slot (if any). */
4786
4787 if (LEAF_SIBCALL_SLOT_RESERVED_P && delay_slot_filled_p)
4788 abort();
4789
4790 if (delay_slot_filled_p)
4791 {
4792 rtx delay = NEXT_INSN (insn);
4793 if (! delay)
4794 abort ();
4795
4796 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4797 output_asm_insn ("jmp\t%%g1 + %%lo(%a0)", operands);
4798 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4799
4800 PATTERN (delay) = gen_blockage ();
4801 INSN_CODE (delay) = -1;
4802 }
4803 else
4804 {
4805 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4806 it into branch if possible. */
4807 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4808 output_asm_insn ("call\t%a0, 0", operands);
4809 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4810 }
4811 }
4812 else
4813 {
4814 /* This is a regular function so we have to restore the register window.
4815 We may have a pending insn for the delay slot, which will be combined
4816 with the 'restore' instruction. */
4817
4818 output_asm_insn ("call\t%a0, 0", operands);
4819
4820 if (delay_slot_filled_p)
4821 {
4822 rtx delay = NEXT_INSN (insn);
4823 if (! delay)
4824 abort ();
4825
4826 output_restore (PATTERN (delay));
4827
4828 PATTERN (delay) = gen_blockage ();
4829 INSN_CODE (delay) = -1;
4830 }
4831 else
4832 output_restore (NULL_RTX);
4833 }
4834
4835 return "";
4836 }
4837 \f
4838 /* Functions for handling argument passing.
4839
4840 For 32-bit, the first 6 args are normally in registers and the rest are
4841 pushed. Any arg that starts within the first 6 words is at least
4842 partially passed in a register unless its data type forbids.
4843
4844 For 64-bit, the argument registers are laid out as an array of 16 elements
4845 and arguments are added sequentially. The first 6 int args and up to the
4846 first 16 fp args (depending on size) are passed in regs.
4847
4848 Slot Stack Integral Float Float in structure Double Long Double
4849 ---- ----- -------- ----- ------------------ ------ -----------
4850 15 [SP+248] %f31 %f30,%f31 %d30
4851 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4852 13 [SP+232] %f27 %f26,%f27 %d26
4853 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4854 11 [SP+216] %f23 %f22,%f23 %d22
4855 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4856 9 [SP+200] %f19 %f18,%f19 %d18
4857 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4858 7 [SP+184] %f15 %f14,%f15 %d14
4859 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4860 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4861 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4862 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4863 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4864 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4865 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4866
4867 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4868
4869 Integral arguments are always passed as 64-bit quantities appropriately
4870 extended.
4871
4872 Passing of floating point values is handled as follows.
4873 If a prototype is in scope:
4874 If the value is in a named argument (i.e. not a stdarg function or a
4875 value not part of the `...') then the value is passed in the appropriate
4876 fp reg.
4877 If the value is part of the `...' and is passed in one of the first 6
4878 slots then the value is passed in the appropriate int reg.
4879 If the value is part of the `...' and is not passed in one of the first 6
4880 slots then the value is passed in memory.
4881 If a prototype is not in scope:
4882 If the value is one of the first 6 arguments the value is passed in the
4883 appropriate integer reg and the appropriate fp reg.
4884 If the value is not one of the first 6 arguments the value is passed in
4885 the appropriate fp reg and in memory.
4886
4887
4888 Summary of the calling conventions implemented by GCC on SPARC:
4889
4890 32-bit ABI:
4891 size argument return value
4892
4893 small integer <4 int. reg. int. reg.
4894 word 4 int. reg. int. reg.
4895 double word 8 int. reg. int. reg.
4896
4897 _Complex small integer <8 int. reg. int. reg.
4898 _Complex word 8 int. reg. int. reg.
4899 _Complex double word 16 memory int. reg.
4900
4901 vector integer <=8 int. reg. FP reg.
4902 vector integer >8 memory memory
4903
4904 float 4 int. reg. FP reg.
4905 double 8 int. reg. FP reg.
4906 long double 16 memory memory
4907
4908 _Complex float 8 memory FP reg.
4909 _Complex double 16 memory FP reg.
4910 _Complex long double 32 memory FP reg.
4911
4912 vector float <=32 memory FP reg.
4913 vector float >32 memory memory
4914
4915 aggregate any memory memory
4916
4917
4918
4919 64-bit ABI:
4920 size argument return value
4921
4922 small integer <8 int. reg. int. reg.
4923 word 8 int. reg. int. reg.
4924 double word 16 int. reg. int. reg.
4925
4926 _Complex small integer <16 int. reg. int. reg.
4927 _Complex word 16 int. reg. int. reg.
4928 _Complex double word 32 memory int. reg.
4929
4930 vector integer <=16 FP reg. FP reg.
4931 vector integer 16<s<=32 memory FP reg.
4932 vector integer >32 memory memory
4933
4934 float 4 FP reg. FP reg.
4935 double 8 FP reg. FP reg.
4936 long double 16 FP reg. FP reg.
4937
4938 _Complex float 8 FP reg. FP reg.
4939 _Complex double 16 FP reg. FP reg.
4940 _Complex long double 32 memory FP reg.
4941
4942 vector float <=16 FP reg. FP reg.
4943 vector float 16<s<=32 memory FP reg.
4944 vector float >32 memory memory
4945
4946 aggregate <=16 reg. reg.
4947 aggregate 16<s<=32 memory reg.
4948 aggregate >32 memory memory
4949
4950
4951
4952 Note #1: complex floating-point types follow the extended SPARC ABIs as
4953 implemented by the Sun compiler.
4954
4955 Note #2: integral vector types follow the scalar floating-point types
4956 conventions to match what is implemented by the Sun VIS SDK.
4957
4958 Note #3: floating-point vector types follow the complex floating-point
4959 types conventions. */
4960
4961
4962 /* Maximum number of int regs for args. */
4963 #define SPARC_INT_ARG_MAX 6
4964 /* Maximum number of fp regs for args. */
4965 #define SPARC_FP_ARG_MAX 16
4966
4967 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4968
4969 /* Handle the INIT_CUMULATIVE_ARGS macro.
4970 Initialize a variable CUM of type CUMULATIVE_ARGS
4971 for a call to a function whose data type is FNTYPE.
4972 For a library call, FNTYPE is 0. */
4973
4974 void
4975 init_cumulative_args (struct sparc_args *cum, tree fntype,
4976 rtx libname ATTRIBUTE_UNUSED,
4977 tree fndecl ATTRIBUTE_UNUSED)
4978 {
4979 cum->words = 0;
4980 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4981 cum->libcall_p = fntype == 0;
4982 }
4983
4984 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4985 When a prototype says `char' or `short', really pass an `int'. */
4986
4987 static bool
4988 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4989 {
4990 return TARGET_ARCH32 ? true : false;
4991 }
4992
4993 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4994
4995 static bool
4996 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4997 {
4998 return TARGET_ARCH64 ? true : false;
4999 }
5000
5001 /* Scan the record type TYPE and return the following predicates:
5002 - INTREGS_P: the record contains at least one field or sub-field
5003 that is eligible for promotion in integer registers.
5004 - FP_REGS_P: the record contains at least one field or sub-field
5005 that is eligible for promotion in floating-point registers.
5006 - PACKED_P: the record contains at least one field that is packed.
5007
5008 Sub-fields are not taken into account for the PACKED_P predicate. */
5009
5010 static void
5011 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5012 {
5013 tree field;
5014
5015 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5016 {
5017 if (TREE_CODE (field) == FIELD_DECL)
5018 {
5019 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5020 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5021 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
5022 *fpregs_p = 1;
5023 else
5024 *intregs_p = 1;
5025
5026 if (packed_p && DECL_PACKED (field))
5027 *packed_p = 1;
5028 }
5029 }
5030 }
5031
5032 /* Compute the slot number to pass an argument in.
5033 Return the slot number or -1 if passing on the stack.
5034
5035 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5036 the preceding args and about the function being called.
5037 MODE is the argument's machine mode.
5038 TYPE is the data type of the argument (as a tree).
5039 This is null for libcalls where that information may
5040 not be available.
5041 NAMED is nonzero if this argument is a named parameter
5042 (otherwise it is an extra parameter matching an ellipsis).
5043 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5044 *PREGNO records the register number to use if scalar type.
5045 *PPADDING records the amount of padding needed in words. */
5046
5047 static int
5048 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5049 tree type, int named, int incoming_p,
5050 int *pregno, int *ppadding)
5051 {
5052 int regbase = (incoming_p
5053 ? SPARC_INCOMING_INT_ARG_FIRST
5054 : SPARC_OUTGOING_INT_ARG_FIRST);
5055 int slotno = cum->words;
5056 int regno;
5057
5058 *ppadding = 0;
5059
5060 if (type && TREE_ADDRESSABLE (type))
5061 return -1;
5062
5063 if (TARGET_ARCH32
5064 && mode == BLKmode
5065 && type
5066 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5067 return -1;
5068
5069 /* For SPARC64, objects requiring 16-byte alignment get it. */
5070 if (TARGET_ARCH64
5071 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5072 && (slotno & 1) != 0)
5073 slotno++, *ppadding = 1;
5074
5075 switch (GET_MODE_CLASS (mode))
5076 {
5077 case MODE_FLOAT:
5078 case MODE_COMPLEX_FLOAT:
5079 case MODE_VECTOR_INT:
5080 case MODE_VECTOR_FLOAT:
5081 if (TARGET_ARCH64 && TARGET_FPU && named)
5082 {
5083 if (slotno >= SPARC_FP_ARG_MAX)
5084 return -1;
5085 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5086 /* Arguments filling only one single FP register are
5087 right-justified in the outer double FP register. */
5088 if (GET_MODE_SIZE (mode) <= 4)
5089 regno++;
5090 break;
5091 }
5092 /* fallthrough */
5093
5094 case MODE_INT:
5095 case MODE_COMPLEX_INT:
5096 if (slotno >= SPARC_INT_ARG_MAX)
5097 return -1;
5098 regno = regbase + slotno;
5099 break;
5100
5101 case MODE_RANDOM:
5102 if (mode == VOIDmode)
5103 /* MODE is VOIDmode when generating the actual call. */
5104 return -1;
5105
5106 if (mode != BLKmode)
5107 abort ();
5108
5109 /* For SPARC64, objects requiring 16-byte alignment get it. */
5110 if (TARGET_ARCH64
5111 && type
5112 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5113 && (slotno & 1) != 0)
5114 slotno++, *ppadding = 1;
5115
5116 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
5117 {
5118 if (slotno >= SPARC_INT_ARG_MAX)
5119 return -1;
5120 regno = regbase + slotno;
5121 }
5122 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
5123 {
5124 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5125
5126 /* First see what kinds of registers we would need. */
5127 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5128
5129 /* The ABI obviously doesn't specify how packed structures
5130 are passed. These are defined to be passed in int regs
5131 if possible, otherwise memory. */
5132 if (packed_p || !named)
5133 fpregs_p = 0, intregs_p = 1;
5134
5135 /* If all arg slots are filled, then must pass on stack. */
5136 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5137 return -1;
5138
5139 /* If there are only int args and all int arg slots are filled,
5140 then must pass on stack. */
5141 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5142 return -1;
5143
5144 /* Note that even if all int arg slots are filled, fp members may
5145 still be passed in regs if such regs are available.
5146 *PREGNO isn't set because there may be more than one, it's up
5147 to the caller to compute them. */
5148 return slotno;
5149 }
5150 break;
5151
5152 default :
5153 abort ();
5154 }
5155
5156 *pregno = regno;
5157 return slotno;
5158 }
5159
5160 /* Handle recursive register counting for structure field layout. */
5161
5162 struct function_arg_record_value_parms
5163 {
5164 rtx ret; /* return expression being built. */
5165 int slotno; /* slot number of the argument. */
5166 int named; /* whether the argument is named. */
5167 int regbase; /* regno of the base register. */
5168 int stack; /* 1 if part of the argument is on the stack. */
5169 int intoffset; /* offset of the first pending integer field. */
5170 unsigned int nregs; /* number of words passed in registers. */
5171 };
5172
5173 static void function_arg_record_value_3
5174 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5175 static void function_arg_record_value_2
5176 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5177 static void function_arg_record_value_1
5178 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5179 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5180 static rtx function_arg_union_value (int, enum machine_mode, int);
5181
5182 /* A subroutine of function_arg_record_value. Traverse the structure
5183 recursively and determine how many registers will be required. */
5184
5185 static void
5186 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5187 struct function_arg_record_value_parms *parms,
5188 bool packed_p)
5189 {
5190 tree field;
5191
5192 /* We need to compute how many registers are needed so we can
5193 allocate the PARALLEL but before we can do that we need to know
5194 whether there are any packed fields. The ABI obviously doesn't
5195 specify how structures are passed in this case, so they are
5196 defined to be passed in int regs if possible, otherwise memory,
5197 regardless of whether there are fp values present. */
5198
5199 if (! packed_p)
5200 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5201 {
5202 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5203 {
5204 packed_p = true;
5205 break;
5206 }
5207 }
5208
5209 /* Compute how many registers we need. */
5210 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5211 {
5212 if (TREE_CODE (field) == FIELD_DECL)
5213 {
5214 HOST_WIDE_INT bitpos = startbitpos;
5215
5216 if (DECL_SIZE (field) != 0
5217 && host_integerp (bit_position (field), 1))
5218 bitpos += int_bit_position (field);
5219
5220 /* ??? FIXME: else assume zero offset. */
5221
5222 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5223 function_arg_record_value_1 (TREE_TYPE (field),
5224 bitpos,
5225 parms,
5226 packed_p);
5227 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5228 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5229 && TARGET_FPU
5230 && parms->named
5231 && ! packed_p)
5232 {
5233 if (parms->intoffset != -1)
5234 {
5235 unsigned int startbit, endbit;
5236 int intslots, this_slotno;
5237
5238 startbit = parms->intoffset & -BITS_PER_WORD;
5239 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5240
5241 intslots = (endbit - startbit) / BITS_PER_WORD;
5242 this_slotno = parms->slotno + parms->intoffset
5243 / BITS_PER_WORD;
5244
5245 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5246 {
5247 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5248 /* We need to pass this field on the stack. */
5249 parms->stack = 1;
5250 }
5251
5252 parms->nregs += intslots;
5253 parms->intoffset = -1;
5254 }
5255
5256 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5257 If it wasn't true we wouldn't be here. */
5258 parms->nregs += 1;
5259 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5260 parms->nregs += 1;
5261 }
5262 else
5263 {
5264 if (parms->intoffset == -1)
5265 parms->intoffset = bitpos;
5266 }
5267 }
5268 }
5269 }
5270
5271 /* A subroutine of function_arg_record_value. Assign the bits of the
5272 structure between parms->intoffset and bitpos to integer registers. */
5273
5274 static void
5275 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5276 struct function_arg_record_value_parms *parms)
5277 {
5278 enum machine_mode mode;
5279 unsigned int regno;
5280 unsigned int startbit, endbit;
5281 int this_slotno, intslots, intoffset;
5282 rtx reg;
5283
5284 if (parms->intoffset == -1)
5285 return;
5286
5287 intoffset = parms->intoffset;
5288 parms->intoffset = -1;
5289
5290 startbit = intoffset & -BITS_PER_WORD;
5291 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5292 intslots = (endbit - startbit) / BITS_PER_WORD;
5293 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5294
5295 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5296 if (intslots <= 0)
5297 return;
5298
5299 /* If this is the trailing part of a word, only load that much into
5300 the register. Otherwise load the whole register. Note that in
5301 the latter case we may pick up unwanted bits. It's not a problem
5302 at the moment but may wish to revisit. */
5303
5304 if (intoffset % BITS_PER_WORD != 0)
5305 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5306 MODE_INT, 0);
5307 else
5308 mode = word_mode;
5309
5310 intoffset /= BITS_PER_UNIT;
5311 do
5312 {
5313 regno = parms->regbase + this_slotno;
5314 reg = gen_rtx_REG (mode, regno);
5315 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5316 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5317
5318 this_slotno += 1;
5319 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5320 mode = word_mode;
5321 parms->nregs += 1;
5322 intslots -= 1;
5323 }
5324 while (intslots > 0);
5325 }
5326
5327 /* A subroutine of function_arg_record_value. Traverse the structure
5328 recursively and assign bits to floating point registers. Track which
5329 bits in between need integer registers; invoke function_arg_record_value_3
5330 to make that happen. */
5331
5332 static void
5333 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5334 struct function_arg_record_value_parms *parms,
5335 bool packed_p)
5336 {
5337 tree field;
5338
5339 if (! packed_p)
5340 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5341 {
5342 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5343 {
5344 packed_p = true;
5345 break;
5346 }
5347 }
5348
5349 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5350 {
5351 if (TREE_CODE (field) == FIELD_DECL)
5352 {
5353 HOST_WIDE_INT bitpos = startbitpos;
5354
5355 if (DECL_SIZE (field) != 0
5356 && host_integerp (bit_position (field), 1))
5357 bitpos += int_bit_position (field);
5358
5359 /* ??? FIXME: else assume zero offset. */
5360
5361 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5362 function_arg_record_value_2 (TREE_TYPE (field),
5363 bitpos,
5364 parms,
5365 packed_p);
5366 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5367 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5368 && TARGET_FPU
5369 && parms->named
5370 && ! packed_p)
5371 {
5372 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5373 int regno;
5374 enum machine_mode mode = DECL_MODE (field);
5375 rtx reg;
5376
5377 function_arg_record_value_3 (bitpos, parms);
5378 switch (mode)
5379 {
5380 case SCmode: mode = SFmode; break;
5381 case DCmode: mode = DFmode; break;
5382 case TCmode: mode = TFmode; break;
5383 default: break;
5384 }
5385 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5386 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5387 regno++;
5388 reg = gen_rtx_REG (mode, regno);
5389 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5390 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5391 GEN_INT (bitpos / BITS_PER_UNIT));
5392 parms->nregs += 1;
5393 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5394 {
5395 regno += GET_MODE_SIZE (mode) / 4;
5396 reg = gen_rtx_REG (mode, regno);
5397 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5398 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5399 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5400 / BITS_PER_UNIT));
5401 parms->nregs += 1;
5402 }
5403 }
5404 else
5405 {
5406 if (parms->intoffset == -1)
5407 parms->intoffset = bitpos;
5408 }
5409 }
5410 }
5411 }
5412
5413 /* Used by function_arg and function_value to implement the complex
5414 conventions of the 64-bit ABI for passing and returning structures.
5415 Return an expression valid as a return value for the two macros
5416 FUNCTION_ARG and FUNCTION_VALUE.
5417
5418 TYPE is the data type of the argument (as a tree).
5419 This is null for libcalls where that information may
5420 not be available.
5421 MODE is the argument's machine mode.
5422 SLOTNO is the index number of the argument's slot in the parameter array.
5423 NAMED is nonzero if this argument is a named parameter
5424 (otherwise it is an extra parameter matching an ellipsis).
5425 REGBASE is the regno of the base register for the parameter array. */
5426
5427 static rtx
5428 function_arg_record_value (tree type, enum machine_mode mode,
5429 int slotno, int named, int regbase)
5430 {
5431 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5432 struct function_arg_record_value_parms parms;
5433 unsigned int nregs;
5434
5435 parms.ret = NULL_RTX;
5436 parms.slotno = slotno;
5437 parms.named = named;
5438 parms.regbase = regbase;
5439 parms.stack = 0;
5440
5441 /* Compute how many registers we need. */
5442 parms.nregs = 0;
5443 parms.intoffset = 0;
5444 function_arg_record_value_1 (type, 0, &parms, false);
5445
5446 /* Take into account pending integer fields. */
5447 if (parms.intoffset != -1)
5448 {
5449 unsigned int startbit, endbit;
5450 int intslots, this_slotno;
5451
5452 startbit = parms.intoffset & -BITS_PER_WORD;
5453 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5454 intslots = (endbit - startbit) / BITS_PER_WORD;
5455 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5456
5457 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5458 {
5459 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5460 /* We need to pass this field on the stack. */
5461 parms.stack = 1;
5462 }
5463
5464 parms.nregs += intslots;
5465 }
5466 nregs = parms.nregs;
5467
5468 /* Allocate the vector and handle some annoying special cases. */
5469 if (nregs == 0)
5470 {
5471 /* ??? Empty structure has no value? Duh? */
5472 if (typesize <= 0)
5473 {
5474 /* Though there's nothing really to store, return a word register
5475 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5476 leads to breakage due to the fact that there are zero bytes to
5477 load. */
5478 return gen_rtx_REG (mode, regbase);
5479 }
5480 else
5481 {
5482 /* ??? C++ has structures with no fields, and yet a size. Give up
5483 for now and pass everything back in integer registers. */
5484 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5485 }
5486 if (nregs + slotno > SPARC_INT_ARG_MAX)
5487 nregs = SPARC_INT_ARG_MAX - slotno;
5488 }
5489 if (nregs == 0)
5490 abort ();
5491
5492 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5493
5494 /* If at least one field must be passed on the stack, generate
5495 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5496 also be passed on the stack. We can't do much better because the
5497 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5498 of structures for which the fields passed exclusively in registers
5499 are not at the beginning of the structure. */
5500 if (parms.stack)
5501 XVECEXP (parms.ret, 0, 0)
5502 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5503
5504 /* Fill in the entries. */
5505 parms.nregs = 0;
5506 parms.intoffset = 0;
5507 function_arg_record_value_2 (type, 0, &parms, false);
5508 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5509
5510 if (parms.nregs != nregs)
5511 abort ();
5512
5513 return parms.ret;
5514 }
5515
5516 /* Used by function_arg and function_value to implement the conventions
5517 of the 64-bit ABI for passing and returning unions.
5518 Return an expression valid as a return value for the two macros
5519 FUNCTION_ARG and FUNCTION_VALUE.
5520
5521 SIZE is the size in bytes of the union.
5522 MODE is the argument's machine mode.
5523 REGNO is the hard register the union will be passed in. */
5524
5525 static rtx
5526 function_arg_union_value (int size, enum machine_mode mode, int regno)
5527 {
5528 int nwords = ROUND_ADVANCE (size), i;
5529 rtx regs;
5530
5531 /* Unions are passed left-justified. */
5532 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5533
5534 for (i = 0; i < nwords; i++)
5535 XVECEXP (regs, 0, i)
5536 = gen_rtx_EXPR_LIST (VOIDmode,
5537 gen_rtx_REG (word_mode, regno + i),
5538 GEN_INT (UNITS_PER_WORD * i));
5539
5540 return regs;
5541 }
5542
5543 /* Handle the FUNCTION_ARG macro.
5544 Determine where to put an argument to a function.
5545 Value is zero to push the argument on the stack,
5546 or a hard register in which to store the argument.
5547
5548 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5549 the preceding args and about the function being called.
5550 MODE is the argument's machine mode.
5551 TYPE is the data type of the argument (as a tree).
5552 This is null for libcalls where that information may
5553 not be available.
5554 NAMED is nonzero if this argument is a named parameter
5555 (otherwise it is an extra parameter matching an ellipsis).
5556 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5557
5558 rtx
5559 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5560 tree type, int named, int incoming_p)
5561 {
5562 int regbase = (incoming_p
5563 ? SPARC_INCOMING_INT_ARG_FIRST
5564 : SPARC_OUTGOING_INT_ARG_FIRST);
5565 int slotno, regno, padding;
5566 rtx reg;
5567
5568 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5569 &regno, &padding);
5570
5571 if (slotno == -1)
5572 return 0;
5573
5574 if (TARGET_ARCH32)
5575 {
5576 reg = gen_rtx_REG (mode, regno);
5577 return reg;
5578 }
5579
5580 if (type && TREE_CODE (type) == RECORD_TYPE)
5581 {
5582 /* Structures up to 16 bytes in size are passed in arg slots on the
5583 stack and are promoted to registers where possible. */
5584
5585 if (int_size_in_bytes (type) > 16)
5586 abort (); /* shouldn't get here */
5587
5588 return function_arg_record_value (type, mode, slotno, named, regbase);
5589 }
5590 else if (type && TREE_CODE (type) == UNION_TYPE)
5591 {
5592 HOST_WIDE_INT size = int_size_in_bytes (type);
5593
5594 if (size > 16)
5595 abort (); /* shouldn't get here */
5596
5597 return function_arg_union_value (size, mode, regno);
5598 }
5599 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5600 but also have the slot allocated for them.
5601 If no prototype is in scope fp values in register slots get passed
5602 in two places, either fp regs and int regs or fp regs and memory. */
5603 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5604 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5605 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5606 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5607 && SPARC_FP_REG_P (regno))
5608 {
5609 reg = gen_rtx_REG (mode, regno);
5610 if (cum->prototype_p || cum->libcall_p)
5611 {
5612 /* "* 2" because fp reg numbers are recorded in 4 byte
5613 quantities. */
5614 #if 0
5615 /* ??? This will cause the value to be passed in the fp reg and
5616 in the stack. When a prototype exists we want to pass the
5617 value in the reg but reserve space on the stack. That's an
5618 optimization, and is deferred [for a bit]. */
5619 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5620 return gen_rtx_PARALLEL (mode,
5621 gen_rtvec (2,
5622 gen_rtx_EXPR_LIST (VOIDmode,
5623 NULL_RTX, const0_rtx),
5624 gen_rtx_EXPR_LIST (VOIDmode,
5625 reg, const0_rtx)));
5626 else
5627 #else
5628 /* ??? It seems that passing back a register even when past
5629 the area declared by REG_PARM_STACK_SPACE will allocate
5630 space appropriately, and will not copy the data onto the
5631 stack, exactly as we desire.
5632
5633 This is due to locate_and_pad_parm being called in
5634 expand_call whenever reg_parm_stack_space > 0, which
5635 while beneficial to our example here, would seem to be
5636 in error from what had been intended. Ho hum... -- r~ */
5637 #endif
5638 return reg;
5639 }
5640 else
5641 {
5642 rtx v0, v1;
5643
5644 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5645 {
5646 int intreg;
5647
5648 /* On incoming, we don't need to know that the value
5649 is passed in %f0 and %i0, and it confuses other parts
5650 causing needless spillage even on the simplest cases. */
5651 if (incoming_p)
5652 return reg;
5653
5654 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5655 + (regno - SPARC_FP_ARG_FIRST) / 2);
5656
5657 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5658 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5659 const0_rtx);
5660 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5661 }
5662 else
5663 {
5664 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5665 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5666 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5667 }
5668 }
5669 }
5670 else
5671 {
5672 /* Scalar or complex int. */
5673 reg = gen_rtx_REG (mode, regno);
5674 }
5675
5676 return reg;
5677 }
5678
5679 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5680 For an arg passed partly in registers and partly in memory,
5681 this is the number of registers used.
5682 For args passed entirely in registers or entirely in memory, zero.
5683
5684 Any arg that starts in the first 6 regs but won't entirely fit in them
5685 needs partial registers on v8. On v9, structures with integer
5686 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5687 values that begin in the last fp reg [where "last fp reg" varies with the
5688 mode] will be split between that reg and memory. */
5689
5690 int
5691 function_arg_partial_nregs (const struct sparc_args *cum,
5692 enum machine_mode mode, tree type, int named)
5693 {
5694 int slotno, regno, padding;
5695
5696 /* We pass 0 for incoming_p here, it doesn't matter. */
5697 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5698
5699 if (slotno == -1)
5700 return 0;
5701
5702 if (TARGET_ARCH32)
5703 {
5704 if ((slotno + (mode == BLKmode
5705 ? ROUND_ADVANCE (int_size_in_bytes (type))
5706 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5707 > SPARC_INT_ARG_MAX)
5708 return SPARC_INT_ARG_MAX - slotno;
5709 }
5710 else
5711 {
5712 /* We are guaranteed by pass_by_reference that the size of the
5713 argument is not greater than 16 bytes, so we only need to
5714 return 1 if the argument is partially passed in registers. */
5715
5716 if (type && AGGREGATE_TYPE_P (type))
5717 {
5718 int size = int_size_in_bytes (type);
5719
5720 if (size > UNITS_PER_WORD
5721 && slotno == SPARC_INT_ARG_MAX - 1)
5722 return 1;
5723 }
5724 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5725 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5726 && ! (TARGET_FPU && named)))
5727 {
5728 /* The complex types are passed as packed types. */
5729 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5730 && slotno == SPARC_INT_ARG_MAX - 1)
5731 return 1;
5732 }
5733 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5734 {
5735 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5736 > SPARC_FP_ARG_MAX)
5737 return 1;
5738 }
5739 }
5740
5741 return 0;
5742 }
5743
5744 /* Return true if the argument should be passed by reference.
5745 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5746 quad-precision floats by invisible reference.
5747 v9: Aggregates greater than 16 bytes are passed by reference.
5748 For Pascal, also pass arrays by reference. */
5749
5750 static bool
5751 sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5752 enum machine_mode mode, tree type,
5753 bool named ATTRIBUTE_UNUSED)
5754 {
5755 if (TARGET_ARCH32)
5756 {
5757 return ((type && AGGREGATE_TYPE_P (type))
5758 /* Extended ABI (as implemented by the Sun compiler) says
5759 that all complex floats are passed in memory. */
5760 || mode == SCmode
5761 /* Enforce the 2-word cap for passing arguments in registers.
5762 This affects CDImode, TFmode, DCmode, TCmode and large
5763 vector modes. */
5764 || GET_MODE_SIZE (mode) > 8);
5765 }
5766 else
5767 {
5768 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5769 || (type
5770 && AGGREGATE_TYPE_P (type)
5771 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5772 /* Enforce the 2-word cap for passing arguments in registers.
5773 This affects CTImode, TCmode and large vector modes. */
5774 || GET_MODE_SIZE (mode) > 16);
5775 }
5776 }
5777
5778 /* Handle the FUNCTION_ARG_ADVANCE macro.
5779 Update the data in CUM to advance over an argument
5780 of mode MODE and data type TYPE.
5781 TYPE is null for libcalls where that information may not be available. */
5782
5783 void
5784 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5785 tree type, int named)
5786 {
5787 int slotno, regno, padding;
5788
5789 /* We pass 0 for incoming_p here, it doesn't matter. */
5790 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5791
5792 /* If register required leading padding, add it. */
5793 if (slotno != -1)
5794 cum->words += padding;
5795
5796 if (TARGET_ARCH32)
5797 {
5798 cum->words += (mode != BLKmode
5799 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5800 : ROUND_ADVANCE (int_size_in_bytes (type)));
5801 }
5802 else
5803 {
5804 if (type && AGGREGATE_TYPE_P (type))
5805 {
5806 int size = int_size_in_bytes (type);
5807
5808 if (size <= 8)
5809 ++cum->words;
5810 else if (size <= 16)
5811 cum->words += 2;
5812 else /* passed by reference */
5813 ++cum->words;
5814 }
5815 else
5816 {
5817 cum->words += (mode != BLKmode
5818 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5819 : ROUND_ADVANCE (int_size_in_bytes (type)));
5820 }
5821 }
5822 }
5823
5824 /* Handle the FUNCTION_ARG_PADDING macro.
5825 For the 64 bit ABI structs are always stored left shifted in their
5826 argument slot. */
5827
5828 enum direction
5829 function_arg_padding (enum machine_mode mode, tree type)
5830 {
5831 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5832 return upward;
5833
5834 /* Fall back to the default. */
5835 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5836 }
5837
5838 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5839 Specify whether to return the return value in memory. */
5840
5841 static bool
5842 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5843 {
5844 if (TARGET_ARCH32)
5845 /* Original SPARC 32-bit ABI says that quad-precision floats
5846 and all structures are returned in memory. Extended ABI
5847 (as implemented by the Sun compiler) says that all complex
5848 floats are returned in registers (8 FP registers at most
5849 for '_Complex long double'). Return all complex integers
5850 in registers (4 at most for '_Complex long long'). */
5851 return (TYPE_MODE (type) == BLKmode
5852 || TYPE_MODE (type) == TFmode
5853 /* Integral vector types follow the scalar FP types conventions. */
5854 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5855 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5856 /* FP vector types follow the complex FP types conventions. */
5857 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5858 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5859 else
5860 /* Original SPARC 64-bit ABI says that structures and unions
5861 smaller than 32 bytes are returned in registers. Extended
5862 ABI (as implemented by the Sun compiler) says that all complex
5863 floats are returned in registers (8 FP registers at most
5864 for '_Complex long double'). Return all complex integers
5865 in registers (4 at most for '_Complex TItype'). */
5866 return ((TYPE_MODE (type) == BLKmode
5867 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5868 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5869 }
5870
5871 /* Handle the TARGET_STRUCT_VALUE target hook.
5872 Return where to find the structure return value address. */
5873
5874 static rtx
5875 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5876 {
5877 if (TARGET_ARCH64)
5878 return 0;
5879 else
5880 {
5881 if (incoming)
5882 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5883 STRUCT_VALUE_OFFSET));
5884 else
5885 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5886 STRUCT_VALUE_OFFSET));
5887 }
5888 }
5889
5890 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5891 For v9, function return values are subject to the same rules as arguments,
5892 except that up to 32 bytes may be returned in registers. */
5893
5894 rtx
5895 function_value (tree type, enum machine_mode mode, int incoming_p)
5896 {
5897 /* Beware that the two values are swapped here wrt function_arg. */
5898 int regbase = (incoming_p
5899 ? SPARC_OUTGOING_INT_ARG_FIRST
5900 : SPARC_INCOMING_INT_ARG_FIRST);
5901 int regno;
5902
5903 if (TARGET_ARCH64 && type)
5904 {
5905 if (TREE_CODE (type) == RECORD_TYPE)
5906 {
5907 /* Structures up to 32 bytes in size are passed in registers,
5908 promoted to fp registers where possible. */
5909
5910 if (int_size_in_bytes (type) > 32)
5911 abort (); /* shouldn't get here */
5912
5913 return function_arg_record_value (type, mode, 0, 1, regbase);
5914 }
5915 else if (TREE_CODE (type) == UNION_TYPE)
5916 {
5917 HOST_WIDE_INT size = int_size_in_bytes (type);
5918
5919 if (size > 32)
5920 abort (); /* shouldn't get here */
5921
5922 return function_arg_union_value (size, mode, regbase);
5923 }
5924 else if (AGGREGATE_TYPE_P (type))
5925 {
5926 /* All other aggregate types are passed in an integer register
5927 in a mode corresponding to the size of the type. */
5928 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5929
5930 if (bytes > 32)
5931 abort (); /* shouldn't get here */
5932
5933 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5934
5935 /* ??? We probably should have made the same ABI change in
5936 3.4.0 as the one we made for unions. The latter was
5937 required by the SCD though, while the former is not
5938 specified, so we favored compatibility and efficiency.
5939
5940 Now we're stuck for aggregates larger than 16 bytes,
5941 because OImode vanished in the meantime. Let's not
5942 try to be unduly clever, and simply follow the ABI
5943 for unions in that case. */
5944 if (mode == BLKmode)
5945 return function_arg_union_value (bytes, mode, regbase);
5946 }
5947 else if (GET_MODE_CLASS (mode) == MODE_INT
5948 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5949 mode = word_mode;
5950 }
5951
5952 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5953 regno = SPARC_FP_ARG_FIRST;
5954 else
5955 regno = regbase;
5956
5957 return gen_rtx_REG (mode, regno);
5958 }
5959
5960 /* Do what is necessary for `va_start'. We look at the current function
5961 to determine if stdarg or varargs is used and return the address of
5962 the first unnamed parameter. */
5963
5964 static rtx
5965 sparc_builtin_saveregs (void)
5966 {
5967 int first_reg = current_function_args_info.words;
5968 rtx address;
5969 int regno;
5970
5971 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5972 emit_move_insn (gen_rtx_MEM (word_mode,
5973 gen_rtx_PLUS (Pmode,
5974 frame_pointer_rtx,
5975 GEN_INT (FIRST_PARM_OFFSET (0)
5976 + (UNITS_PER_WORD
5977 * regno)))),
5978 gen_rtx_REG (word_mode,
5979 SPARC_INCOMING_INT_ARG_FIRST + regno));
5980
5981 address = gen_rtx_PLUS (Pmode,
5982 frame_pointer_rtx,
5983 GEN_INT (FIRST_PARM_OFFSET (0)
5984 + UNITS_PER_WORD * first_reg));
5985
5986 return address;
5987 }
5988
5989 /* Implement `va_start' for stdarg. */
5990
5991 void
5992 sparc_va_start (tree valist, rtx nextarg)
5993 {
5994 nextarg = expand_builtin_saveregs ();
5995 std_expand_builtin_va_start (valist, nextarg);
5996 }
5997
5998 /* Implement `va_arg' for stdarg. */
5999
6000 static tree
6001 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6002 {
6003 HOST_WIDE_INT size, rsize, align;
6004 tree addr, incr;
6005 bool indirect;
6006 tree ptrtype = build_pointer_type (type);
6007
6008 if (pass_by_reference (NULL, TYPE_MODE (type), type, 0))
6009 {
6010 indirect = true;
6011 size = rsize = UNITS_PER_WORD;
6012 align = 0;
6013 }
6014 else
6015 {
6016 indirect = false;
6017 size = int_size_in_bytes (type);
6018 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6019 align = 0;
6020
6021 if (TARGET_ARCH64)
6022 {
6023 /* For SPARC64, objects requiring 16-byte alignment get it. */
6024 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6025 align = 2 * UNITS_PER_WORD;
6026
6027 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6028 are given whole slots as needed. */
6029 if (AGGREGATE_TYPE_P (type))
6030 {
6031 if (size == 0)
6032 size = rsize = UNITS_PER_WORD;
6033 else
6034 size = rsize;
6035 }
6036 }
6037 }
6038
6039 incr = valist;
6040 if (align)
6041 {
6042 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6043 ssize_int (align - 1)));
6044 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
6045 ssize_int (-align)));
6046 }
6047
6048 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6049 addr = incr;
6050
6051 if (BYTES_BIG_ENDIAN && size < rsize)
6052 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6053 ssize_int (rsize - size)));
6054
6055 if (indirect)
6056 {
6057 addr = fold_convert (build_pointer_type (ptrtype), addr);
6058 addr = build_fold_indirect_ref (addr);
6059 }
6060 /* If the address isn't aligned properly for the type,
6061 we may need to copy to a temporary.
6062 FIXME: This is inefficient. Usually we can do this
6063 in registers. */
6064 else if (align == 0
6065 && TYPE_ALIGN (type) > BITS_PER_WORD)
6066 {
6067 tree tmp = create_tmp_var (type, "va_arg_tmp");
6068 tree dest_addr = build_fold_addr_expr (tmp);
6069
6070 tree copy = build_function_call_expr
6071 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6072 tree_cons (NULL_TREE, dest_addr,
6073 tree_cons (NULL_TREE, addr,
6074 tree_cons (NULL_TREE, size_int (rsize),
6075 NULL_TREE))));
6076
6077 gimplify_and_add (copy, pre_p);
6078 addr = dest_addr;
6079 }
6080 else
6081 addr = fold_convert (ptrtype, addr);
6082
6083 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6084 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6085 gimplify_and_add (incr, post_p);
6086
6087 return build_fold_indirect_ref (addr);
6088 }
6089 \f
6090 /* Return the string to output an unconditional branch to LABEL, which is
6091 the operand number of the label.
6092
6093 DEST is the destination insn (i.e. the label), INSN is the source. */
6094
6095 const char *
6096 output_ubranch (rtx dest, int label, rtx insn)
6097 {
6098 static char string[64];
6099 bool noop = false;
6100 char *p;
6101
6102 /* TurboSPARC is reported to have problems with
6103 with
6104 foo: b,a foo
6105 i.e. an empty loop with the annul bit set. The workaround is to use
6106 foo: b foo; nop
6107 instead. */
6108
6109 if (! TARGET_V9 && flag_delayed_branch
6110 && (INSN_ADDRESSES (INSN_UID (dest))
6111 == INSN_ADDRESSES (INSN_UID (insn))))
6112 {
6113 strcpy (string, "b\t");
6114 noop = true;
6115 }
6116 else
6117 {
6118 bool v9_form = false;
6119
6120 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6121 {
6122 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6123 - INSN_ADDRESSES (INSN_UID (insn)));
6124 /* Leave some instructions for "slop". */
6125 if (delta >= -260000 && delta < 260000)
6126 v9_form = true;
6127 }
6128
6129 if (v9_form)
6130 strcpy (string, "ba%*,pt\t%%xcc, ");
6131 else
6132 strcpy (string, "b%*\t");
6133 }
6134
6135 p = strchr (string, '\0');
6136 *p++ = '%';
6137 *p++ = 'l';
6138 *p++ = '0' + label;
6139 *p++ = '%';
6140 if (noop)
6141 *p++ = '#';
6142 else
6143 *p++ = '(';
6144 *p = '\0';
6145
6146 return string;
6147 }
6148
6149 /* Return the string to output a conditional branch to LABEL, which is
6150 the operand number of the label. OP is the conditional expression.
6151 XEXP (OP, 0) is assumed to be a condition code register (integer or
6152 floating point) and its mode specifies what kind of comparison we made.
6153
6154 DEST is the destination insn (i.e. the label), INSN is the source.
6155
6156 REVERSED is nonzero if we should reverse the sense of the comparison.
6157
6158 ANNUL is nonzero if we should generate an annulling branch.
6159
6160 NOOP is nonzero if we have to follow this branch by a noop. */
6161
6162 const char *
6163 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6164 int noop, rtx insn)
6165 {
6166 static char string[64];
6167 enum rtx_code code = GET_CODE (op);
6168 rtx cc_reg = XEXP (op, 0);
6169 enum machine_mode mode = GET_MODE (cc_reg);
6170 const char *labelno, *branch;
6171 int spaces = 8, far;
6172 char *p;
6173
6174 /* v9 branches are limited to +-1MB. If it is too far away,
6175 change
6176
6177 bne,pt %xcc, .LC30
6178
6179 to
6180
6181 be,pn %xcc, .+12
6182 nop
6183 ba .LC30
6184
6185 and
6186
6187 fbne,a,pn %fcc2, .LC29
6188
6189 to
6190
6191 fbe,pt %fcc2, .+16
6192 nop
6193 ba .LC29 */
6194
6195 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6196 if (reversed ^ far)
6197 {
6198 /* Reversal of FP compares takes care -- an ordered compare
6199 becomes an unordered compare and vice versa. */
6200 if (mode == CCFPmode || mode == CCFPEmode)
6201 code = reverse_condition_maybe_unordered (code);
6202 else
6203 code = reverse_condition (code);
6204 }
6205
6206 /* Start by writing the branch condition. */
6207 if (mode == CCFPmode || mode == CCFPEmode)
6208 {
6209 switch (code)
6210 {
6211 case NE:
6212 branch = "fbne";
6213 break;
6214 case EQ:
6215 branch = "fbe";
6216 break;
6217 case GE:
6218 branch = "fbge";
6219 break;
6220 case GT:
6221 branch = "fbg";
6222 break;
6223 case LE:
6224 branch = "fble";
6225 break;
6226 case LT:
6227 branch = "fbl";
6228 break;
6229 case UNORDERED:
6230 branch = "fbu";
6231 break;
6232 case ORDERED:
6233 branch = "fbo";
6234 break;
6235 case UNGT:
6236 branch = "fbug";
6237 break;
6238 case UNLT:
6239 branch = "fbul";
6240 break;
6241 case UNEQ:
6242 branch = "fbue";
6243 break;
6244 case UNGE:
6245 branch = "fbuge";
6246 break;
6247 case UNLE:
6248 branch = "fbule";
6249 break;
6250 case LTGT:
6251 branch = "fblg";
6252 break;
6253
6254 default:
6255 abort ();
6256 }
6257
6258 /* ??? !v9: FP branches cannot be preceded by another floating point
6259 insn. Because there is currently no concept of pre-delay slots,
6260 we can fix this only by always emitting a nop before a floating
6261 point branch. */
6262
6263 string[0] = '\0';
6264 if (! TARGET_V9)
6265 strcpy (string, "nop\n\t");
6266 strcat (string, branch);
6267 }
6268 else
6269 {
6270 switch (code)
6271 {
6272 case NE:
6273 branch = "bne";
6274 break;
6275 case EQ:
6276 branch = "be";
6277 break;
6278 case GE:
6279 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6280 branch = "bpos";
6281 else
6282 branch = "bge";
6283 break;
6284 case GT:
6285 branch = "bg";
6286 break;
6287 case LE:
6288 branch = "ble";
6289 break;
6290 case LT:
6291 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6292 branch = "bneg";
6293 else
6294 branch = "bl";
6295 break;
6296 case GEU:
6297 branch = "bgeu";
6298 break;
6299 case GTU:
6300 branch = "bgu";
6301 break;
6302 case LEU:
6303 branch = "bleu";
6304 break;
6305 case LTU:
6306 branch = "blu";
6307 break;
6308
6309 default:
6310 abort ();
6311 }
6312 strcpy (string, branch);
6313 }
6314 spaces -= strlen (branch);
6315 p = strchr (string, '\0');
6316
6317 /* Now add the annulling, the label, and a possible noop. */
6318 if (annul && ! far)
6319 {
6320 strcpy (p, ",a");
6321 p += 2;
6322 spaces -= 2;
6323 }
6324
6325 if (TARGET_V9)
6326 {
6327 rtx note;
6328 int v8 = 0;
6329
6330 if (! far && insn && INSN_ADDRESSES_SET_P ())
6331 {
6332 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6333 - INSN_ADDRESSES (INSN_UID (insn)));
6334 /* Leave some instructions for "slop". */
6335 if (delta < -260000 || delta >= 260000)
6336 v8 = 1;
6337 }
6338
6339 if (mode == CCFPmode || mode == CCFPEmode)
6340 {
6341 static char v9_fcc_labelno[] = "%%fccX, ";
6342 /* Set the char indicating the number of the fcc reg to use. */
6343 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6344 labelno = v9_fcc_labelno;
6345 if (v8)
6346 {
6347 if (REGNO (cc_reg) == SPARC_FCC_REG)
6348 labelno = "";
6349 else
6350 abort ();
6351 }
6352 }
6353 else if (mode == CCXmode || mode == CCX_NOOVmode)
6354 {
6355 labelno = "%%xcc, ";
6356 if (v8)
6357 abort ();
6358 }
6359 else
6360 {
6361 labelno = "%%icc, ";
6362 if (v8)
6363 labelno = "";
6364 }
6365
6366 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6367 {
6368 strcpy (p,
6369 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6370 ? ",pt" : ",pn");
6371 p += 3;
6372 spaces -= 3;
6373 }
6374 }
6375 else
6376 labelno = "";
6377
6378 if (spaces > 0)
6379 *p++ = '\t';
6380 else
6381 *p++ = ' ';
6382 strcpy (p, labelno);
6383 p = strchr (p, '\0');
6384 if (far)
6385 {
6386 strcpy (p, ".+12\n\t nop\n\tb\t");
6387 if (annul || noop)
6388 p[3] = '6';
6389 p += 14;
6390 }
6391 *p++ = '%';
6392 *p++ = 'l';
6393 /* Set the char indicating the number of the operand containing the
6394 label_ref. */
6395 *p++ = label + '0';
6396 *p = '\0';
6397 if (noop)
6398 strcpy (p, "\n\t nop");
6399
6400 return string;
6401 }
6402
6403 /* Emit a library call comparison between floating point X and Y.
6404 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6405 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6406 values as arguments instead of the TFmode registers themselves,
6407 that's why we cannot call emit_float_lib_cmp. */
6408 void
6409 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6410 {
6411 const char *qpfunc;
6412 rtx slot0, slot1, result, tem, tem2;
6413 enum machine_mode mode;
6414
6415 switch (comparison)
6416 {
6417 case EQ:
6418 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6419 break;
6420
6421 case NE:
6422 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6423 break;
6424
6425 case GT:
6426 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6427 break;
6428
6429 case GE:
6430 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6431 break;
6432
6433 case LT:
6434 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6435 break;
6436
6437 case LE:
6438 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6439 break;
6440
6441 case ORDERED:
6442 case UNORDERED:
6443 case UNGT:
6444 case UNLT:
6445 case UNEQ:
6446 case UNGE:
6447 case UNLE:
6448 case LTGT:
6449 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6450 break;
6451
6452 default:
6453 abort();
6454 break;
6455 }
6456
6457 if (TARGET_ARCH64)
6458 {
6459 if (GET_CODE (x) != MEM)
6460 {
6461 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6462 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6463 }
6464 else
6465 slot0 = x;
6466
6467 if (GET_CODE (y) != MEM)
6468 {
6469 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6470 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6471 }
6472 else
6473 slot1 = y;
6474
6475 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6476 DImode, 2,
6477 XEXP (slot0, 0), Pmode,
6478 XEXP (slot1, 0), Pmode);
6479
6480 mode = DImode;
6481 }
6482 else
6483 {
6484 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6485 SImode, 2,
6486 x, TFmode, y, TFmode);
6487
6488 mode = SImode;
6489 }
6490
6491
6492 /* Immediately move the result of the libcall into a pseudo
6493 register so reload doesn't clobber the value if it needs
6494 the return register for a spill reg. */
6495 result = gen_reg_rtx (mode);
6496 emit_move_insn (result, hard_libcall_value (mode));
6497
6498 switch (comparison)
6499 {
6500 default:
6501 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6502 break;
6503 case ORDERED:
6504 case UNORDERED:
6505 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6506 NULL_RTX, mode, 0);
6507 break;
6508 case UNGT:
6509 case UNGE:
6510 emit_cmp_insn (result, const1_rtx,
6511 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6512 break;
6513 case UNLE:
6514 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6515 break;
6516 case UNLT:
6517 tem = gen_reg_rtx (mode);
6518 if (TARGET_ARCH32)
6519 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6520 else
6521 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6522 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6523 break;
6524 case UNEQ:
6525 case LTGT:
6526 tem = gen_reg_rtx (mode);
6527 if (TARGET_ARCH32)
6528 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6529 else
6530 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6531 tem2 = gen_reg_rtx (mode);
6532 if (TARGET_ARCH32)
6533 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6534 else
6535 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6536 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6537 NULL_RTX, mode, 0);
6538 break;
6539 }
6540 }
6541
6542 /* Generate an unsigned DImode to FP conversion. This is the same code
6543 optabs would emit if we didn't have TFmode patterns. */
6544
6545 void
6546 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6547 {
6548 rtx neglab, donelab, i0, i1, f0, in, out;
6549
6550 out = operands[0];
6551 in = force_reg (DImode, operands[1]);
6552 neglab = gen_label_rtx ();
6553 donelab = gen_label_rtx ();
6554 i0 = gen_reg_rtx (DImode);
6555 i1 = gen_reg_rtx (DImode);
6556 f0 = gen_reg_rtx (mode);
6557
6558 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6559
6560 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6561 emit_jump_insn (gen_jump (donelab));
6562 emit_barrier ();
6563
6564 emit_label (neglab);
6565
6566 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6567 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6568 emit_insn (gen_iordi3 (i0, i0, i1));
6569 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6570 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6571
6572 emit_label (donelab);
6573 }
6574
6575 /* Generate an FP to unsigned DImode conversion. This is the same code
6576 optabs would emit if we didn't have TFmode patterns. */
6577
6578 void
6579 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6580 {
6581 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6582
6583 out = operands[0];
6584 in = force_reg (mode, operands[1]);
6585 neglab = gen_label_rtx ();
6586 donelab = gen_label_rtx ();
6587 i0 = gen_reg_rtx (DImode);
6588 i1 = gen_reg_rtx (DImode);
6589 limit = gen_reg_rtx (mode);
6590 f0 = gen_reg_rtx (mode);
6591
6592 emit_move_insn (limit,
6593 CONST_DOUBLE_FROM_REAL_VALUE (
6594 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6595 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6596
6597 emit_insn (gen_rtx_SET (VOIDmode,
6598 out,
6599 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6600 emit_jump_insn (gen_jump (donelab));
6601 emit_barrier ();
6602
6603 emit_label (neglab);
6604
6605 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6606 emit_insn (gen_rtx_SET (VOIDmode,
6607 i0,
6608 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6609 emit_insn (gen_movdi (i1, const1_rtx));
6610 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6611 emit_insn (gen_xordi3 (out, i0, i1));
6612
6613 emit_label (donelab);
6614 }
6615
6616 /* Return the string to output a conditional branch to LABEL, testing
6617 register REG. LABEL is the operand number of the label; REG is the
6618 operand number of the reg. OP is the conditional expression. The mode
6619 of REG says what kind of comparison we made.
6620
6621 DEST is the destination insn (i.e. the label), INSN is the source.
6622
6623 REVERSED is nonzero if we should reverse the sense of the comparison.
6624
6625 ANNUL is nonzero if we should generate an annulling branch.
6626
6627 NOOP is nonzero if we have to follow this branch by a noop. */
6628
6629 const char *
6630 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6631 int annul, int noop, rtx insn)
6632 {
6633 static char string[64];
6634 enum rtx_code code = GET_CODE (op);
6635 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6636 rtx note;
6637 int far;
6638 char *p;
6639
6640 /* branch on register are limited to +-128KB. If it is too far away,
6641 change
6642
6643 brnz,pt %g1, .LC30
6644
6645 to
6646
6647 brz,pn %g1, .+12
6648 nop
6649 ba,pt %xcc, .LC30
6650
6651 and
6652
6653 brgez,a,pn %o1, .LC29
6654
6655 to
6656
6657 brlz,pt %o1, .+16
6658 nop
6659 ba,pt %xcc, .LC29 */
6660
6661 far = get_attr_length (insn) >= 3;
6662
6663 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6664 if (reversed ^ far)
6665 code = reverse_condition (code);
6666
6667 /* Only 64 bit versions of these instructions exist. */
6668 if (mode != DImode)
6669 abort ();
6670
6671 /* Start by writing the branch condition. */
6672
6673 switch (code)
6674 {
6675 case NE:
6676 strcpy (string, "brnz");
6677 break;
6678
6679 case EQ:
6680 strcpy (string, "brz");
6681 break;
6682
6683 case GE:
6684 strcpy (string, "brgez");
6685 break;
6686
6687 case LT:
6688 strcpy (string, "brlz");
6689 break;
6690
6691 case LE:
6692 strcpy (string, "brlez");
6693 break;
6694
6695 case GT:
6696 strcpy (string, "brgz");
6697 break;
6698
6699 default:
6700 abort ();
6701 }
6702
6703 p = strchr (string, '\0');
6704
6705 /* Now add the annulling, reg, label, and nop. */
6706 if (annul && ! far)
6707 {
6708 strcpy (p, ",a");
6709 p += 2;
6710 }
6711
6712 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6713 {
6714 strcpy (p,
6715 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6716 ? ",pt" : ",pn");
6717 p += 3;
6718 }
6719
6720 *p = p < string + 8 ? '\t' : ' ';
6721 p++;
6722 *p++ = '%';
6723 *p++ = '0' + reg;
6724 *p++ = ',';
6725 *p++ = ' ';
6726 if (far)
6727 {
6728 int veryfar = 1, delta;
6729
6730 if (INSN_ADDRESSES_SET_P ())
6731 {
6732 delta = (INSN_ADDRESSES (INSN_UID (dest))
6733 - INSN_ADDRESSES (INSN_UID (insn)));
6734 /* Leave some instructions for "slop". */
6735 if (delta >= -260000 && delta < 260000)
6736 veryfar = 0;
6737 }
6738
6739 strcpy (p, ".+12\n\t nop\n\t");
6740 if (annul || noop)
6741 p[3] = '6';
6742 p += 12;
6743 if (veryfar)
6744 {
6745 strcpy (p, "b\t");
6746 p += 2;
6747 }
6748 else
6749 {
6750 strcpy (p, "ba,pt\t%%xcc, ");
6751 p += 13;
6752 }
6753 }
6754 *p++ = '%';
6755 *p++ = 'l';
6756 *p++ = '0' + label;
6757 *p = '\0';
6758
6759 if (noop)
6760 strcpy (p, "\n\t nop");
6761
6762 return string;
6763 }
6764
6765 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6766 Such instructions cannot be used in the delay slot of return insn on v9.
6767 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6768 */
6769
6770 static int
6771 epilogue_renumber (register rtx *where, int test)
6772 {
6773 register const char *fmt;
6774 register int i;
6775 register enum rtx_code code;
6776
6777 if (*where == 0)
6778 return 0;
6779
6780 code = GET_CODE (*where);
6781
6782 switch (code)
6783 {
6784 case REG:
6785 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6786 return 1;
6787 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6788 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6789 case SCRATCH:
6790 case CC0:
6791 case PC:
6792 case CONST_INT:
6793 case CONST_DOUBLE:
6794 return 0;
6795
6796 /* Do not replace the frame pointer with the stack pointer because
6797 it can cause the delayed instruction to load below the stack.
6798 This occurs when instructions like:
6799
6800 (set (reg/i:SI 24 %i0)
6801 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6802 (const_int -20 [0xffffffec])) 0))
6803
6804 are in the return delayed slot. */
6805 case PLUS:
6806 if (GET_CODE (XEXP (*where, 0)) == REG
6807 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6808 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6809 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6810 return 1;
6811 break;
6812
6813 case MEM:
6814 if (SPARC_STACK_BIAS
6815 && GET_CODE (XEXP (*where, 0)) == REG
6816 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6817 return 1;
6818 break;
6819
6820 default:
6821 break;
6822 }
6823
6824 fmt = GET_RTX_FORMAT (code);
6825
6826 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6827 {
6828 if (fmt[i] == 'E')
6829 {
6830 register int j;
6831 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6832 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6833 return 1;
6834 }
6835 else if (fmt[i] == 'e'
6836 && epilogue_renumber (&(XEXP (*where, i)), test))
6837 return 1;
6838 }
6839 return 0;
6840 }
6841 \f
6842 /* Leaf functions and non-leaf functions have different needs. */
6843
6844 static const int
6845 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6846
6847 static const int
6848 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6849
6850 static const int *const reg_alloc_orders[] = {
6851 reg_leaf_alloc_order,
6852 reg_nonleaf_alloc_order};
6853
6854 void
6855 order_regs_for_local_alloc (void)
6856 {
6857 static int last_order_nonleaf = 1;
6858
6859 if (regs_ever_live[15] != last_order_nonleaf)
6860 {
6861 last_order_nonleaf = !last_order_nonleaf;
6862 memcpy ((char *) reg_alloc_order,
6863 (const char *) reg_alloc_orders[last_order_nonleaf],
6864 FIRST_PSEUDO_REGISTER * sizeof (int));
6865 }
6866 }
6867 \f
6868 /* Return 1 if REG and MEM are legitimate enough to allow the various
6869 mem<-->reg splits to be run. */
6870
6871 int
6872 sparc_splitdi_legitimate (rtx reg, rtx mem)
6873 {
6874 /* Punt if we are here by mistake. */
6875 if (! reload_completed)
6876 abort ();
6877
6878 /* We must have an offsettable memory reference. */
6879 if (! offsettable_memref_p (mem))
6880 return 0;
6881
6882 /* If we have legitimate args for ldd/std, we do not want
6883 the split to happen. */
6884 if ((REGNO (reg) % 2) == 0
6885 && mem_min_alignment (mem, 8))
6886 return 0;
6887
6888 /* Success. */
6889 return 1;
6890 }
6891
6892 /* Return 1 if x and y are some kind of REG and they refer to
6893 different hard registers. This test is guaranteed to be
6894 run after reload. */
6895
6896 int
6897 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6898 {
6899 if (GET_CODE (x) != REG)
6900 return 0;
6901 if (GET_CODE (y) != REG)
6902 return 0;
6903 if (REGNO (x) == REGNO (y))
6904 return 0;
6905 return 1;
6906 }
6907
6908 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6909 This makes them candidates for using ldd and std insns.
6910
6911 Note reg1 and reg2 *must* be hard registers. */
6912
6913 int
6914 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6915 {
6916 /* We might have been passed a SUBREG. */
6917 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6918 return 0;
6919
6920 if (REGNO (reg1) % 2 != 0)
6921 return 0;
6922
6923 /* Integer ldd is deprecated in SPARC V9 */
6924 if (TARGET_V9 && REGNO (reg1) < 32)
6925 return 0;
6926
6927 return (REGNO (reg1) == REGNO (reg2) - 1);
6928 }
6929
6930 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6931 an ldd or std insn.
6932
6933 This can only happen when addr1 and addr2, the addresses in mem1
6934 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6935 addr1 must also be aligned on a 64-bit boundary.
6936
6937 Also iff dependent_reg_rtx is not null it should not be used to
6938 compute the address for mem1, i.e. we cannot optimize a sequence
6939 like:
6940 ld [%o0], %o0
6941 ld [%o0 + 4], %o1
6942 to
6943 ldd [%o0], %o0
6944 nor:
6945 ld [%g3 + 4], %g3
6946 ld [%g3], %g2
6947 to
6948 ldd [%g3], %g2
6949
6950 But, note that the transformation from:
6951 ld [%g2 + 4], %g3
6952 ld [%g2], %g2
6953 to
6954 ldd [%g2], %g2
6955 is perfectly fine. Thus, the peephole2 patterns always pass us
6956 the destination register of the first load, never the second one.
6957
6958 For stores we don't have a similar problem, so dependent_reg_rtx is
6959 NULL_RTX. */
6960
6961 int
6962 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6963 {
6964 rtx addr1, addr2;
6965 unsigned int reg1;
6966 HOST_WIDE_INT offset1;
6967
6968 /* The mems cannot be volatile. */
6969 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6970 return 0;
6971
6972 /* MEM1 should be aligned on a 64-bit boundary. */
6973 if (MEM_ALIGN (mem1) < 64)
6974 return 0;
6975
6976 addr1 = XEXP (mem1, 0);
6977 addr2 = XEXP (mem2, 0);
6978
6979 /* Extract a register number and offset (if used) from the first addr. */
6980 if (GET_CODE (addr1) == PLUS)
6981 {
6982 /* If not a REG, return zero. */
6983 if (GET_CODE (XEXP (addr1, 0)) != REG)
6984 return 0;
6985 else
6986 {
6987 reg1 = REGNO (XEXP (addr1, 0));
6988 /* The offset must be constant! */
6989 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6990 return 0;
6991 offset1 = INTVAL (XEXP (addr1, 1));
6992 }
6993 }
6994 else if (GET_CODE (addr1) != REG)
6995 return 0;
6996 else
6997 {
6998 reg1 = REGNO (addr1);
6999 /* This was a simple (mem (reg)) expression. Offset is 0. */
7000 offset1 = 0;
7001 }
7002
7003 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7004 if (GET_CODE (addr2) != PLUS)
7005 return 0;
7006
7007 if (GET_CODE (XEXP (addr2, 0)) != REG
7008 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7009 return 0;
7010
7011 if (reg1 != REGNO (XEXP (addr2, 0)))
7012 return 0;
7013
7014 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7015 return 0;
7016
7017 /* The first offset must be evenly divisible by 8 to ensure the
7018 address is 64 bit aligned. */
7019 if (offset1 % 8 != 0)
7020 return 0;
7021
7022 /* The offset for the second addr must be 4 more than the first addr. */
7023 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7024 return 0;
7025
7026 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7027 instructions. */
7028 return 1;
7029 }
7030
7031 /* Return 1 if reg is a pseudo, or is the first register in
7032 a hard register pair. This makes it a candidate for use in
7033 ldd and std insns. */
7034
7035 int
7036 register_ok_for_ldd (rtx reg)
7037 {
7038 /* We might have been passed a SUBREG. */
7039 if (GET_CODE (reg) != REG)
7040 return 0;
7041
7042 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7043 return (REGNO (reg) % 2 == 0);
7044 else
7045 return 1;
7046 }
7047 \f
7048 /* Print operand X (an rtx) in assembler syntax to file FILE.
7049 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7050 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7051
7052 void
7053 print_operand (FILE *file, rtx x, int code)
7054 {
7055 switch (code)
7056 {
7057 case '#':
7058 /* Output a 'nop' if there's nothing for the delay slot. */
7059 if (dbr_sequence_length () == 0)
7060 fputs ("\n\t nop", file);
7061 return;
7062 case '*':
7063 /* Output an annul flag if there's nothing for the delay slot and we
7064 are optimizing. This is always used with '(' below. */
7065 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7066 this is a dbx bug. So, we only do this when optimizing. */
7067 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7068 Always emit a nop in case the next instruction is a branch. */
7069 if (dbr_sequence_length () == 0
7070 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7071 fputs (",a", file);
7072 return;
7073 case '(':
7074 /* Output a 'nop' if there's nothing for the delay slot and we are
7075 not optimizing. This is always used with '*' above. */
7076 if (dbr_sequence_length () == 0
7077 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7078 fputs ("\n\t nop", file);
7079 return;
7080 case '_':
7081 /* Output the Embedded Medium/Anywhere code model base register. */
7082 fputs (EMBMEDANY_BASE_REG, file);
7083 return;
7084 case '@':
7085 /* Print out what we are using as the frame pointer. This might
7086 be %fp, or might be %sp+offset. */
7087 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
7088 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC,
7089 reg_names[REGNO (frame_base_reg)], frame_base_offset);
7090 return;
7091 case '&':
7092 /* Print some local dynamic TLS name. */
7093 assemble_name (file, get_some_local_dynamic_name ());
7094 return;
7095 case 'Y':
7096 /* Adjust the operand to take into account a RESTORE operation. */
7097 if (GET_CODE (x) == CONST_INT)
7098 break;
7099 else if (GET_CODE (x) != REG)
7100 output_operand_lossage ("invalid %%Y operand");
7101 else if (REGNO (x) < 8)
7102 fputs (reg_names[REGNO (x)], file);
7103 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7104 fputs (reg_names[REGNO (x)-16], file);
7105 else
7106 output_operand_lossage ("invalid %%Y operand");
7107 return;
7108 case 'L':
7109 /* Print out the low order register name of a register pair. */
7110 if (WORDS_BIG_ENDIAN)
7111 fputs (reg_names[REGNO (x)+1], file);
7112 else
7113 fputs (reg_names[REGNO (x)], file);
7114 return;
7115 case 'H':
7116 /* Print out the high order register name of a register pair. */
7117 if (WORDS_BIG_ENDIAN)
7118 fputs (reg_names[REGNO (x)], file);
7119 else
7120 fputs (reg_names[REGNO (x)+1], file);
7121 return;
7122 case 'R':
7123 /* Print out the second register name of a register pair or quad.
7124 I.e., R (%o0) => %o1. */
7125 fputs (reg_names[REGNO (x)+1], file);
7126 return;
7127 case 'S':
7128 /* Print out the third register name of a register quad.
7129 I.e., S (%o0) => %o2. */
7130 fputs (reg_names[REGNO (x)+2], file);
7131 return;
7132 case 'T':
7133 /* Print out the fourth register name of a register quad.
7134 I.e., T (%o0) => %o3. */
7135 fputs (reg_names[REGNO (x)+3], file);
7136 return;
7137 case 'x':
7138 /* Print a condition code register. */
7139 if (REGNO (x) == SPARC_ICC_REG)
7140 {
7141 /* We don't handle CC[X]_NOOVmode because they're not supposed
7142 to occur here. */
7143 if (GET_MODE (x) == CCmode)
7144 fputs ("%icc", file);
7145 else if (GET_MODE (x) == CCXmode)
7146 fputs ("%xcc", file);
7147 else
7148 abort ();
7149 }
7150 else
7151 /* %fccN register */
7152 fputs (reg_names[REGNO (x)], file);
7153 return;
7154 case 'm':
7155 /* Print the operand's address only. */
7156 output_address (XEXP (x, 0));
7157 return;
7158 case 'r':
7159 /* In this case we need a register. Use %g0 if the
7160 operand is const0_rtx. */
7161 if (x == const0_rtx
7162 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7163 {
7164 fputs ("%g0", file);
7165 return;
7166 }
7167 else
7168 break;
7169
7170 case 'A':
7171 switch (GET_CODE (x))
7172 {
7173 case IOR: fputs ("or", file); break;
7174 case AND: fputs ("and", file); break;
7175 case XOR: fputs ("xor", file); break;
7176 default: output_operand_lossage ("invalid %%A operand");
7177 }
7178 return;
7179
7180 case 'B':
7181 switch (GET_CODE (x))
7182 {
7183 case IOR: fputs ("orn", file); break;
7184 case AND: fputs ("andn", file); break;
7185 case XOR: fputs ("xnor", file); break;
7186 default: output_operand_lossage ("invalid %%B operand");
7187 }
7188 return;
7189
7190 /* These are used by the conditional move instructions. */
7191 case 'c' :
7192 case 'C':
7193 {
7194 enum rtx_code rc = GET_CODE (x);
7195
7196 if (code == 'c')
7197 {
7198 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7199 if (mode == CCFPmode || mode == CCFPEmode)
7200 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7201 else
7202 rc = reverse_condition (GET_CODE (x));
7203 }
7204 switch (rc)
7205 {
7206 case NE: fputs ("ne", file); break;
7207 case EQ: fputs ("e", file); break;
7208 case GE: fputs ("ge", file); break;
7209 case GT: fputs ("g", file); break;
7210 case LE: fputs ("le", file); break;
7211 case LT: fputs ("l", file); break;
7212 case GEU: fputs ("geu", file); break;
7213 case GTU: fputs ("gu", file); break;
7214 case LEU: fputs ("leu", file); break;
7215 case LTU: fputs ("lu", file); break;
7216 case LTGT: fputs ("lg", file); break;
7217 case UNORDERED: fputs ("u", file); break;
7218 case ORDERED: fputs ("o", file); break;
7219 case UNLT: fputs ("ul", file); break;
7220 case UNLE: fputs ("ule", file); break;
7221 case UNGT: fputs ("ug", file); break;
7222 case UNGE: fputs ("uge", file); break;
7223 case UNEQ: fputs ("ue", file); break;
7224 default: output_operand_lossage (code == 'c'
7225 ? "invalid %%c operand"
7226 : "invalid %%C operand");
7227 }
7228 return;
7229 }
7230
7231 /* These are used by the movr instruction pattern. */
7232 case 'd':
7233 case 'D':
7234 {
7235 enum rtx_code rc = (code == 'd'
7236 ? reverse_condition (GET_CODE (x))
7237 : GET_CODE (x));
7238 switch (rc)
7239 {
7240 case NE: fputs ("ne", file); break;
7241 case EQ: fputs ("e", file); break;
7242 case GE: fputs ("gez", file); break;
7243 case LT: fputs ("lz", file); break;
7244 case LE: fputs ("lez", file); break;
7245 case GT: fputs ("gz", file); break;
7246 default: output_operand_lossage (code == 'd'
7247 ? "invalid %%d operand"
7248 : "invalid %%D operand");
7249 }
7250 return;
7251 }
7252
7253 case 'b':
7254 {
7255 /* Print a sign-extended character. */
7256 int i = trunc_int_for_mode (INTVAL (x), QImode);
7257 fprintf (file, "%d", i);
7258 return;
7259 }
7260
7261 case 'f':
7262 /* Operand must be a MEM; write its address. */
7263 if (GET_CODE (x) != MEM)
7264 output_operand_lossage ("invalid %%f operand");
7265 output_address (XEXP (x, 0));
7266 return;
7267
7268 case 's':
7269 {
7270 /* Print a sign-extended 32-bit value. */
7271 HOST_WIDE_INT i;
7272 if (GET_CODE(x) == CONST_INT)
7273 i = INTVAL (x);
7274 else if (GET_CODE(x) == CONST_DOUBLE)
7275 i = CONST_DOUBLE_LOW (x);
7276 else
7277 {
7278 output_operand_lossage ("invalid %%s operand");
7279 return;
7280 }
7281 i = trunc_int_for_mode (i, SImode);
7282 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7283 return;
7284 }
7285
7286 case 0:
7287 /* Do nothing special. */
7288 break;
7289
7290 default:
7291 /* Undocumented flag. */
7292 output_operand_lossage ("invalid operand output code");
7293 }
7294
7295 if (GET_CODE (x) == REG)
7296 fputs (reg_names[REGNO (x)], file);
7297 else if (GET_CODE (x) == MEM)
7298 {
7299 fputc ('[', file);
7300 /* Poor Sun assembler doesn't understand absolute addressing. */
7301 if (CONSTANT_P (XEXP (x, 0)))
7302 fputs ("%g0+", file);
7303 output_address (XEXP (x, 0));
7304 fputc (']', file);
7305 }
7306 else if (GET_CODE (x) == HIGH)
7307 {
7308 fputs ("%hi(", file);
7309 output_addr_const (file, XEXP (x, 0));
7310 fputc (')', file);
7311 }
7312 else if (GET_CODE (x) == LO_SUM)
7313 {
7314 print_operand (file, XEXP (x, 0), 0);
7315 if (TARGET_CM_MEDMID)
7316 fputs ("+%l44(", file);
7317 else
7318 fputs ("+%lo(", file);
7319 output_addr_const (file, XEXP (x, 1));
7320 fputc (')', file);
7321 }
7322 else if (GET_CODE (x) == CONST_DOUBLE
7323 && (GET_MODE (x) == VOIDmode
7324 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7325 {
7326 if (CONST_DOUBLE_HIGH (x) == 0)
7327 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7328 else if (CONST_DOUBLE_HIGH (x) == -1
7329 && CONST_DOUBLE_LOW (x) < 0)
7330 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7331 else
7332 output_operand_lossage ("long long constant not a valid immediate operand");
7333 }
7334 else if (GET_CODE (x) == CONST_DOUBLE)
7335 output_operand_lossage ("floating point constant not a valid immediate operand");
7336 else { output_addr_const (file, x); }
7337 }
7338 \f
7339 /* Target hook for assembling integer objects. The sparc version has
7340 special handling for aligned DI-mode objects. */
7341
7342 static bool
7343 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7344 {
7345 /* ??? We only output .xword's for symbols and only then in environments
7346 where the assembler can handle them. */
7347 if (aligned_p && size == 8
7348 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7349 {
7350 if (TARGET_V9)
7351 {
7352 assemble_integer_with_op ("\t.xword\t", x);
7353 return true;
7354 }
7355 else
7356 {
7357 assemble_aligned_integer (4, const0_rtx);
7358 assemble_aligned_integer (4, x);
7359 return true;
7360 }
7361 }
7362 return default_assemble_integer (x, size, aligned_p);
7363 }
7364 \f
7365 /* Return the value of a code used in the .proc pseudo-op that says
7366 what kind of result this function returns. For non-C types, we pick
7367 the closest C type. */
7368
7369 #ifndef SHORT_TYPE_SIZE
7370 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7371 #endif
7372
7373 #ifndef INT_TYPE_SIZE
7374 #define INT_TYPE_SIZE BITS_PER_WORD
7375 #endif
7376
7377 #ifndef LONG_TYPE_SIZE
7378 #define LONG_TYPE_SIZE BITS_PER_WORD
7379 #endif
7380
7381 #ifndef LONG_LONG_TYPE_SIZE
7382 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7383 #endif
7384
7385 #ifndef FLOAT_TYPE_SIZE
7386 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7387 #endif
7388
7389 #ifndef DOUBLE_TYPE_SIZE
7390 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7391 #endif
7392
7393 #ifndef LONG_DOUBLE_TYPE_SIZE
7394 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7395 #endif
7396
7397 unsigned long
7398 sparc_type_code (register tree type)
7399 {
7400 register unsigned long qualifiers = 0;
7401 register unsigned shift;
7402
7403 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7404 setting more, since some assemblers will give an error for this. Also,
7405 we must be careful to avoid shifts of 32 bits or more to avoid getting
7406 unpredictable results. */
7407
7408 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7409 {
7410 switch (TREE_CODE (type))
7411 {
7412 case ERROR_MARK:
7413 return qualifiers;
7414
7415 case ARRAY_TYPE:
7416 qualifiers |= (3 << shift);
7417 break;
7418
7419 case FUNCTION_TYPE:
7420 case METHOD_TYPE:
7421 qualifiers |= (2 << shift);
7422 break;
7423
7424 case POINTER_TYPE:
7425 case REFERENCE_TYPE:
7426 case OFFSET_TYPE:
7427 qualifiers |= (1 << shift);
7428 break;
7429
7430 case RECORD_TYPE:
7431 return (qualifiers | 8);
7432
7433 case UNION_TYPE:
7434 case QUAL_UNION_TYPE:
7435 return (qualifiers | 9);
7436
7437 case ENUMERAL_TYPE:
7438 return (qualifiers | 10);
7439
7440 case VOID_TYPE:
7441 return (qualifiers | 16);
7442
7443 case INTEGER_TYPE:
7444 /* If this is a range type, consider it to be the underlying
7445 type. */
7446 if (TREE_TYPE (type) != 0)
7447 break;
7448
7449 /* Carefully distinguish all the standard types of C,
7450 without messing up if the language is not C. We do this by
7451 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7452 look at both the names and the above fields, but that's redundant.
7453 Any type whose size is between two C types will be considered
7454 to be the wider of the two types. Also, we do not have a
7455 special code to use for "long long", so anything wider than
7456 long is treated the same. Note that we can't distinguish
7457 between "int" and "long" in this code if they are the same
7458 size, but that's fine, since neither can the assembler. */
7459
7460 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7461 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7462
7463 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7464 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7465
7466 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7467 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7468
7469 else
7470 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7471
7472 case REAL_TYPE:
7473 /* If this is a range type, consider it to be the underlying
7474 type. */
7475 if (TREE_TYPE (type) != 0)
7476 break;
7477
7478 /* Carefully distinguish all the standard types of C,
7479 without messing up if the language is not C. */
7480
7481 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7482 return (qualifiers | 6);
7483
7484 else
7485 return (qualifiers | 7);
7486
7487 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7488 /* ??? We need to distinguish between double and float complex types,
7489 but I don't know how yet because I can't reach this code from
7490 existing front-ends. */
7491 return (qualifiers | 7); /* Who knows? */
7492
7493 case VECTOR_TYPE:
7494 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7495 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7496 case FILE_TYPE: /* GNU Pascal FILE type. */
7497 case SET_TYPE: /* GNU Pascal SET type. */
7498 case LANG_TYPE: /* ? */
7499 return qualifiers;
7500
7501 default:
7502 abort (); /* Not a type! */
7503 }
7504 }
7505
7506 return qualifiers;
7507 }
7508 \f
7509 /* Nested function support. */
7510
7511 /* Emit RTL insns to initialize the variable parts of a trampoline.
7512 FNADDR is an RTX for the address of the function's pure code.
7513 CXT is an RTX for the static chain value for the function.
7514
7515 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7516 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7517 (to store insns). This is a bit excessive. Perhaps a different
7518 mechanism would be better here.
7519
7520 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7521
7522 void
7523 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7524 {
7525 /* SPARC 32-bit trampoline:
7526
7527 sethi %hi(fn), %g1
7528 sethi %hi(static), %g2
7529 jmp %g1+%lo(fn)
7530 or %g2, %lo(static), %g2
7531
7532 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7533 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7534 */
7535
7536 emit_move_insn
7537 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7538 expand_binop (SImode, ior_optab,
7539 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7540 size_int (10), 0, 1),
7541 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7542 NULL_RTX, 1, OPTAB_DIRECT));
7543
7544 emit_move_insn
7545 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7546 expand_binop (SImode, ior_optab,
7547 expand_shift (RSHIFT_EXPR, SImode, cxt,
7548 size_int (10), 0, 1),
7549 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7550 NULL_RTX, 1, OPTAB_DIRECT));
7551
7552 emit_move_insn
7553 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7554 expand_binop (SImode, ior_optab,
7555 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7556 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7557 NULL_RTX, 1, OPTAB_DIRECT));
7558
7559 emit_move_insn
7560 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7561 expand_binop (SImode, ior_optab,
7562 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7563 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7564 NULL_RTX, 1, OPTAB_DIRECT));
7565
7566 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7567 aligned on a 16 byte boundary so one flush clears it all. */
7568 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7569 if (sparc_cpu != PROCESSOR_ULTRASPARC
7570 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7571 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7572 plus_constant (tramp, 8)))));
7573
7574 /* Call __enable_execute_stack after writing onto the stack to make sure
7575 the stack address is accessible. */
7576 #ifdef ENABLE_EXECUTE_STACK
7577 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7578 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7579 #endif
7580
7581 }
7582
7583 /* The 64-bit version is simpler because it makes more sense to load the
7584 values as "immediate" data out of the trampoline. It's also easier since
7585 we can read the PC without clobbering a register. */
7586
7587 void
7588 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7589 {
7590 /* SPARC 64-bit trampoline:
7591
7592 rd %pc, %g1
7593 ldx [%g1+24], %g5
7594 jmp %g5
7595 ldx [%g1+16], %g5
7596 +16 bytes data
7597 */
7598
7599 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7600 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7601 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7602 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7603 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7604 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7605 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7606 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7607 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7608 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7609 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7610
7611 if (sparc_cpu != PROCESSOR_ULTRASPARC
7612 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7613 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7614
7615 /* Call __enable_execute_stack after writing onto the stack to make sure
7616 the stack address is accessible. */
7617 #ifdef ENABLE_EXECUTE_STACK
7618 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7619 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7620 #endif
7621 }
7622 \f
7623 /* Adjust the cost of a scheduling dependency. Return the new cost of
7624 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7625
7626 static int
7627 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7628 {
7629 enum attr_type insn_type;
7630
7631 if (! recog_memoized (insn))
7632 return 0;
7633
7634 insn_type = get_attr_type (insn);
7635
7636 if (REG_NOTE_KIND (link) == 0)
7637 {
7638 /* Data dependency; DEP_INSN writes a register that INSN reads some
7639 cycles later. */
7640
7641 /* if a load, then the dependence must be on the memory address;
7642 add an extra "cycle". Note that the cost could be two cycles
7643 if the reg was written late in an instruction group; we ca not tell
7644 here. */
7645 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7646 return cost + 3;
7647
7648 /* Get the delay only if the address of the store is the dependence. */
7649 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7650 {
7651 rtx pat = PATTERN(insn);
7652 rtx dep_pat = PATTERN (dep_insn);
7653
7654 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7655 return cost; /* This should not happen! */
7656
7657 /* The dependency between the two instructions was on the data that
7658 is being stored. Assume that this implies that the address of the
7659 store is not dependent. */
7660 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7661 return cost;
7662
7663 return cost + 3; /* An approximation. */
7664 }
7665
7666 /* A shift instruction cannot receive its data from an instruction
7667 in the same cycle; add a one cycle penalty. */
7668 if (insn_type == TYPE_SHIFT)
7669 return cost + 3; /* Split before cascade into shift. */
7670 }
7671 else
7672 {
7673 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7674 INSN writes some cycles later. */
7675
7676 /* These are only significant for the fpu unit; writing a fp reg before
7677 the fpu has finished with it stalls the processor. */
7678
7679 /* Reusing an integer register causes no problems. */
7680 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7681 return 0;
7682 }
7683
7684 return cost;
7685 }
7686
7687 static int
7688 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7689 {
7690 enum attr_type insn_type, dep_type;
7691 rtx pat = PATTERN(insn);
7692 rtx dep_pat = PATTERN (dep_insn);
7693
7694 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7695 return cost;
7696
7697 insn_type = get_attr_type (insn);
7698 dep_type = get_attr_type (dep_insn);
7699
7700 switch (REG_NOTE_KIND (link))
7701 {
7702 case 0:
7703 /* Data dependency; DEP_INSN writes a register that INSN reads some
7704 cycles later. */
7705
7706 switch (insn_type)
7707 {
7708 case TYPE_STORE:
7709 case TYPE_FPSTORE:
7710 /* Get the delay iff the address of the store is the dependence. */
7711 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7712 return cost;
7713
7714 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7715 return cost;
7716 return cost + 3;
7717
7718 case TYPE_LOAD:
7719 case TYPE_SLOAD:
7720 case TYPE_FPLOAD:
7721 /* If a load, then the dependence must be on the memory address. If
7722 the addresses aren't equal, then it might be a false dependency */
7723 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7724 {
7725 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7726 || GET_CODE (SET_DEST (dep_pat)) != MEM
7727 || GET_CODE (SET_SRC (pat)) != MEM
7728 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7729 XEXP (SET_SRC (pat), 0)))
7730 return cost + 2;
7731
7732 return cost + 8;
7733 }
7734 break;
7735
7736 case TYPE_BRANCH:
7737 /* Compare to branch latency is 0. There is no benefit from
7738 separating compare and branch. */
7739 if (dep_type == TYPE_COMPARE)
7740 return 0;
7741 /* Floating point compare to branch latency is less than
7742 compare to conditional move. */
7743 if (dep_type == TYPE_FPCMP)
7744 return cost - 1;
7745 break;
7746 default:
7747 break;
7748 }
7749 break;
7750
7751 case REG_DEP_ANTI:
7752 /* Anti-dependencies only penalize the fpu unit. */
7753 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7754 return 0;
7755 break;
7756
7757 default:
7758 break;
7759 }
7760
7761 return cost;
7762 }
7763
7764 static int
7765 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7766 {
7767 switch (sparc_cpu)
7768 {
7769 case PROCESSOR_SUPERSPARC:
7770 cost = supersparc_adjust_cost (insn, link, dep, cost);
7771 break;
7772 case PROCESSOR_HYPERSPARC:
7773 case PROCESSOR_SPARCLITE86X:
7774 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7775 break;
7776 default:
7777 break;
7778 }
7779 return cost;
7780 }
7781
7782 static void
7783 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7784 int sched_verbose ATTRIBUTE_UNUSED,
7785 int max_ready ATTRIBUTE_UNUSED)
7786 {
7787 }
7788
7789 static int
7790 sparc_use_sched_lookahead (void)
7791 {
7792 if (sparc_cpu == PROCESSOR_ULTRASPARC
7793 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7794 return 4;
7795 if ((1 << sparc_cpu) &
7796 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7797 (1 << PROCESSOR_SPARCLITE86X)))
7798 return 3;
7799 return 0;
7800 }
7801
7802 static int
7803 sparc_issue_rate (void)
7804 {
7805 switch (sparc_cpu)
7806 {
7807 default:
7808 return 1;
7809 case PROCESSOR_V9:
7810 /* Assume V9 processors are capable of at least dual-issue. */
7811 return 2;
7812 case PROCESSOR_SUPERSPARC:
7813 return 3;
7814 case PROCESSOR_HYPERSPARC:
7815 case PROCESSOR_SPARCLITE86X:
7816 return 2;
7817 case PROCESSOR_ULTRASPARC:
7818 case PROCESSOR_ULTRASPARC3:
7819 return 4;
7820 }
7821 }
7822
7823 static int
7824 set_extends (rtx insn)
7825 {
7826 register rtx pat = PATTERN (insn);
7827
7828 switch (GET_CODE (SET_SRC (pat)))
7829 {
7830 /* Load and some shift instructions zero extend. */
7831 case MEM:
7832 case ZERO_EXTEND:
7833 /* sethi clears the high bits */
7834 case HIGH:
7835 /* LO_SUM is used with sethi. sethi cleared the high
7836 bits and the values used with lo_sum are positive */
7837 case LO_SUM:
7838 /* Store flag stores 0 or 1 */
7839 case LT: case LTU:
7840 case GT: case GTU:
7841 case LE: case LEU:
7842 case GE: case GEU:
7843 case EQ:
7844 case NE:
7845 return 1;
7846 case AND:
7847 {
7848 rtx op0 = XEXP (SET_SRC (pat), 0);
7849 rtx op1 = XEXP (SET_SRC (pat), 1);
7850 if (GET_CODE (op1) == CONST_INT)
7851 return INTVAL (op1) >= 0;
7852 if (GET_CODE (op0) != REG)
7853 return 0;
7854 if (sparc_check_64 (op0, insn) == 1)
7855 return 1;
7856 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7857 }
7858 case IOR:
7859 case XOR:
7860 {
7861 rtx op0 = XEXP (SET_SRC (pat), 0);
7862 rtx op1 = XEXP (SET_SRC (pat), 1);
7863 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7864 return 0;
7865 if (GET_CODE (op1) == CONST_INT)
7866 return INTVAL (op1) >= 0;
7867 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7868 }
7869 case LSHIFTRT:
7870 return GET_MODE (SET_SRC (pat)) == SImode;
7871 /* Positive integers leave the high bits zero. */
7872 case CONST_DOUBLE:
7873 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7874 case CONST_INT:
7875 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7876 case ASHIFTRT:
7877 case SIGN_EXTEND:
7878 return - (GET_MODE (SET_SRC (pat)) == SImode);
7879 case REG:
7880 return sparc_check_64 (SET_SRC (pat), insn);
7881 default:
7882 return 0;
7883 }
7884 }
7885
7886 /* We _ought_ to have only one kind per function, but... */
7887 static GTY(()) rtx sparc_addr_diff_list;
7888 static GTY(()) rtx sparc_addr_list;
7889
7890 void
7891 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7892 {
7893 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7894 if (diff)
7895 sparc_addr_diff_list
7896 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7897 else
7898 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7899 }
7900
7901 static void
7902 sparc_output_addr_vec (rtx vec)
7903 {
7904 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7905 int idx, vlen = XVECLEN (body, 0);
7906
7907 #ifdef ASM_OUTPUT_ADDR_VEC_START
7908 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7909 #endif
7910
7911 #ifdef ASM_OUTPUT_CASE_LABEL
7912 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7913 NEXT_INSN (lab));
7914 #else
7915 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7916 #endif
7917
7918 for (idx = 0; idx < vlen; idx++)
7919 {
7920 ASM_OUTPUT_ADDR_VEC_ELT
7921 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7922 }
7923
7924 #ifdef ASM_OUTPUT_ADDR_VEC_END
7925 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7926 #endif
7927 }
7928
7929 static void
7930 sparc_output_addr_diff_vec (rtx vec)
7931 {
7932 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7933 rtx base = XEXP (XEXP (body, 0), 0);
7934 int idx, vlen = XVECLEN (body, 1);
7935
7936 #ifdef ASM_OUTPUT_ADDR_VEC_START
7937 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7938 #endif
7939
7940 #ifdef ASM_OUTPUT_CASE_LABEL
7941 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7942 NEXT_INSN (lab));
7943 #else
7944 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7945 #endif
7946
7947 for (idx = 0; idx < vlen; idx++)
7948 {
7949 ASM_OUTPUT_ADDR_DIFF_ELT
7950 (asm_out_file,
7951 body,
7952 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7953 CODE_LABEL_NUMBER (base));
7954 }
7955
7956 #ifdef ASM_OUTPUT_ADDR_VEC_END
7957 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7958 #endif
7959 }
7960
7961 static void
7962 sparc_output_deferred_case_vectors (void)
7963 {
7964 rtx t;
7965 int align;
7966
7967 if (sparc_addr_list == NULL_RTX
7968 && sparc_addr_diff_list == NULL_RTX)
7969 return;
7970
7971 /* Align to cache line in the function's code section. */
7972 function_section (current_function_decl);
7973
7974 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7975 if (align > 0)
7976 ASM_OUTPUT_ALIGN (asm_out_file, align);
7977
7978 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7979 sparc_output_addr_vec (XEXP (t, 0));
7980 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7981 sparc_output_addr_diff_vec (XEXP (t, 0));
7982
7983 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7984 }
7985
7986 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7987 unknown. Return 1 if the high bits are zero, -1 if the register is
7988 sign extended. */
7989 int
7990 sparc_check_64 (rtx x, rtx insn)
7991 {
7992 /* If a register is set only once it is safe to ignore insns this
7993 code does not know how to handle. The loop will either recognize
7994 the single set and return the correct value or fail to recognize
7995 it and return 0. */
7996 int set_once = 0;
7997 rtx y = x;
7998
7999 if (GET_CODE (x) != REG)
8000 abort ();
8001
8002 if (GET_MODE (x) == DImode)
8003 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8004
8005 if (flag_expensive_optimizations
8006 && REG_N_SETS (REGNO (y)) == 1)
8007 set_once = 1;
8008
8009 if (insn == 0)
8010 {
8011 if (set_once)
8012 insn = get_last_insn_anywhere ();
8013 else
8014 return 0;
8015 }
8016
8017 while ((insn = PREV_INSN (insn)))
8018 {
8019 switch (GET_CODE (insn))
8020 {
8021 case JUMP_INSN:
8022 case NOTE:
8023 break;
8024 case CODE_LABEL:
8025 case CALL_INSN:
8026 default:
8027 if (! set_once)
8028 return 0;
8029 break;
8030 case INSN:
8031 {
8032 rtx pat = PATTERN (insn);
8033 if (GET_CODE (pat) != SET)
8034 return 0;
8035 if (rtx_equal_p (x, SET_DEST (pat)))
8036 return set_extends (insn);
8037 if (y && rtx_equal_p (y, SET_DEST (pat)))
8038 return set_extends (insn);
8039 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8040 return 0;
8041 }
8042 }
8043 }
8044 return 0;
8045 }
8046
8047 /* Returns assembly code to perform a DImode shift using
8048 a 64-bit global or out register on SPARC-V8+. */
8049 const char *
8050 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8051 {
8052 static char asm_code[60];
8053
8054 /* The scratch register is only required when the destination
8055 register is not a 64-bit global or out register. */
8056 if (which_alternative != 2)
8057 operands[3] = operands[0];
8058
8059 /* We can only shift by constants <= 63. */
8060 if (GET_CODE (operands[2]) == CONST_INT)
8061 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8062
8063 if (GET_CODE (operands[1]) == CONST_INT)
8064 {
8065 output_asm_insn ("mov\t%1, %3", operands);
8066 }
8067 else
8068 {
8069 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8070 if (sparc_check_64 (operands[1], insn) <= 0)
8071 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8072 output_asm_insn ("or\t%L1, %3, %3", operands);
8073 }
8074
8075 strcpy(asm_code, opcode);
8076
8077 if (which_alternative != 2)
8078 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8079 else
8080 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8081 }
8082 \f
8083 /* Output rtl to increment the profiler label LABELNO
8084 for profiling a function entry. */
8085
8086 void
8087 sparc_profile_hook (int labelno)
8088 {
8089 char buf[32];
8090 rtx lab, fun;
8091
8092 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8093 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8094 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8095
8096 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8097 }
8098 \f
8099 #ifdef OBJECT_FORMAT_ELF
8100 static void
8101 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8102 {
8103 if (flags & SECTION_MERGE)
8104 {
8105 /* entsize cannot be expressed in this section attributes
8106 encoding style. */
8107 default_elf_asm_named_section (name, flags);
8108 return;
8109 }
8110
8111 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8112
8113 if (!(flags & SECTION_DEBUG))
8114 fputs (",#alloc", asm_out_file);
8115 if (flags & SECTION_WRITE)
8116 fputs (",#write", asm_out_file);
8117 if (flags & SECTION_TLS)
8118 fputs (",#tls", asm_out_file);
8119 if (flags & SECTION_CODE)
8120 fputs (",#execinstr", asm_out_file);
8121
8122 /* ??? Handle SECTION_BSS. */
8123
8124 fputc ('\n', asm_out_file);
8125 }
8126 #endif /* OBJECT_FORMAT_ELF */
8127
8128 /* We do not allow indirect calls to be optimized into sibling calls.
8129
8130 We cannot use sibling calls when delayed branches are disabled
8131 because they will likely require the call delay slot to be filled.
8132
8133 Also, on SPARC 32-bit we cannot emit a sibling call when the
8134 current function returns a structure. This is because the "unimp
8135 after call" convention would cause the callee to return to the
8136 wrong place. The generic code already disallows cases where the
8137 function being called returns a structure.
8138
8139 It may seem strange how this last case could occur. Usually there
8140 is code after the call which jumps to epilogue code which dumps the
8141 return value into the struct return area. That ought to invalidate
8142 the sibling call right? Well, in the C++ case we can end up passing
8143 the pointer to the struct return area to a constructor (which returns
8144 void) and then nothing else happens. Such a sibling call would look
8145 valid without the added check here. */
8146 static bool
8147 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8148 {
8149 return (decl
8150 && flag_delayed_branch
8151 && (TARGET_ARCH64 || ! current_function_returns_struct));
8152 }
8153 \f
8154 /* libfunc renaming. */
8155 #include "config/gofast.h"
8156
8157 static void
8158 sparc_init_libfuncs (void)
8159 {
8160 if (TARGET_ARCH32)
8161 {
8162 /* Use the subroutines that Sun's library provides for integer
8163 multiply and divide. The `*' prevents an underscore from
8164 being prepended by the compiler. .umul is a little faster
8165 than .mul. */
8166 set_optab_libfunc (smul_optab, SImode, "*.umul");
8167 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8168 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8169 set_optab_libfunc (smod_optab, SImode, "*.rem");
8170 set_optab_libfunc (umod_optab, SImode, "*.urem");
8171
8172 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8173 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8174 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8175 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8176 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8177 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8178
8179 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8180 is because with soft-float, the SFmode and DFmode sqrt
8181 instructions will be absent, and the compiler will notice and
8182 try to use the TFmode sqrt instruction for calls to the
8183 builtin function sqrt, but this fails. */
8184 if (TARGET_FPU)
8185 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8186
8187 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8188 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8189 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8190 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8191 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8192 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8193
8194 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8195 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8196 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8197 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8198
8199 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8200 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8201 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8202
8203 if (DITF_CONVERSION_LIBFUNCS)
8204 {
8205 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8206 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8207 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8208 }
8209
8210 if (SUN_CONVERSION_LIBFUNCS)
8211 {
8212 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8213 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8214 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8215 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8216 }
8217 }
8218 if (TARGET_ARCH64)
8219 {
8220 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8221 do not exist in the library. Make sure the compiler does not
8222 emit calls to them by accident. (It should always use the
8223 hardware instructions.) */
8224 set_optab_libfunc (smul_optab, SImode, 0);
8225 set_optab_libfunc (sdiv_optab, SImode, 0);
8226 set_optab_libfunc (udiv_optab, SImode, 0);
8227 set_optab_libfunc (smod_optab, SImode, 0);
8228 set_optab_libfunc (umod_optab, SImode, 0);
8229
8230 if (SUN_INTEGER_MULTIPLY_64)
8231 {
8232 set_optab_libfunc (smul_optab, DImode, "__mul64");
8233 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8234 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8235 set_optab_libfunc (smod_optab, DImode, "__rem64");
8236 set_optab_libfunc (umod_optab, DImode, "__urem64");
8237 }
8238
8239 if (SUN_CONVERSION_LIBFUNCS)
8240 {
8241 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8242 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8243 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8244 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8245 }
8246 }
8247
8248 gofast_maybe_init_libfuncs ();
8249 }
8250 \f
8251 int
8252 sparc_extra_constraint_check (rtx op, int c, int strict)
8253 {
8254 int reload_ok_mem;
8255
8256 if (TARGET_ARCH64
8257 && (c == 'T' || c == 'U'))
8258 return 0;
8259
8260 switch (c)
8261 {
8262 case 'Q':
8263 return fp_sethi_p (op);
8264
8265 case 'R':
8266 return fp_mov_p (op);
8267
8268 case 'S':
8269 return fp_high_losum_p (op);
8270
8271 case 'U':
8272 if (! strict
8273 || (GET_CODE (op) == REG
8274 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8275 || reg_renumber[REGNO (op)] >= 0)))
8276 return register_ok_for_ldd (op);
8277
8278 return 0;
8279
8280 case 'W':
8281 case 'T':
8282 break;
8283
8284 default:
8285 return 0;
8286 }
8287
8288 /* Our memory extra constraints have to emulate the
8289 behavior of 'm' and 'o' in order for reload to work
8290 correctly. */
8291 if (GET_CODE (op) == MEM)
8292 {
8293 reload_ok_mem = 0;
8294 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8295 && (! strict
8296 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8297 reload_ok_mem = 1;
8298 }
8299 else
8300 {
8301 reload_ok_mem = (reload_in_progress
8302 && GET_CODE (op) == REG
8303 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8304 && reg_renumber [REGNO (op)] < 0);
8305 }
8306
8307 return reload_ok_mem;
8308 }
8309
8310 /* ??? This duplicates information provided to the compiler by the
8311 ??? scheduler description. Some day, teach genautomata to output
8312 ??? the latencies and then CSE will just use that. */
8313
8314 static bool
8315 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8316 {
8317 enum machine_mode mode = GET_MODE (x);
8318 bool float_mode_p = FLOAT_MODE_P (mode);
8319
8320 switch (code)
8321 {
8322 case CONST_INT:
8323 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8324 {
8325 *total = 0;
8326 return true;
8327 }
8328 /* FALLTHRU */
8329
8330 case HIGH:
8331 *total = 2;
8332 return true;
8333
8334 case CONST:
8335 case LABEL_REF:
8336 case SYMBOL_REF:
8337 *total = 4;
8338 return true;
8339
8340 case CONST_DOUBLE:
8341 if (GET_MODE (x) == DImode
8342 && ((XINT (x, 3) == 0
8343 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8344 || (XINT (x, 3) == -1
8345 && XINT (x, 2) < 0
8346 && XINT (x, 2) >= -0x1000)))
8347 *total = 0;
8348 else
8349 *total = 8;
8350 return true;
8351
8352 case MEM:
8353 /* If outer-code was a sign or zero extension, a cost
8354 of COSTS_N_INSNS (1) was already added in. This is
8355 why we are subtracting it back out. */
8356 if (outer_code == ZERO_EXTEND)
8357 {
8358 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8359 }
8360 else if (outer_code == SIGN_EXTEND)
8361 {
8362 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8363 }
8364 else if (float_mode_p)
8365 {
8366 *total = sparc_costs->float_load;
8367 }
8368 else
8369 {
8370 *total = sparc_costs->int_load;
8371 }
8372
8373 return true;
8374
8375 case PLUS:
8376 case MINUS:
8377 if (float_mode_p)
8378 *total = sparc_costs->float_plusminus;
8379 else
8380 *total = COSTS_N_INSNS (1);
8381 return false;
8382
8383 case MULT:
8384 if (float_mode_p)
8385 *total = sparc_costs->float_mul;
8386 else if (! TARGET_HARD_MUL)
8387 return COSTS_N_INSNS (25);
8388 else
8389 {
8390 int bit_cost;
8391
8392 bit_cost = 0;
8393 if (sparc_costs->int_mul_bit_factor)
8394 {
8395 int nbits;
8396
8397 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8398 {
8399 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8400 for (nbits = 0; value != 0; value &= value - 1)
8401 nbits++;
8402 }
8403 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
8404 && GET_MODE (XEXP (x, 1)) == DImode)
8405 {
8406 rtx x1 = XEXP (x, 1);
8407 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
8408 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
8409
8410 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8411 nbits++;
8412 for (; value2 != 0; value2 &= value2 - 1)
8413 nbits++;
8414 }
8415 else
8416 nbits = 7;
8417
8418 if (nbits < 3)
8419 nbits = 3;
8420 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
8421 bit_cost = COSTS_N_INSNS (bit_cost);
8422 }
8423
8424 if (mode == DImode)
8425 *total = sparc_costs->int_mulX + bit_cost;
8426 else
8427 *total = sparc_costs->int_mul + bit_cost;
8428 }
8429 return false;
8430
8431 case ASHIFT:
8432 case ASHIFTRT:
8433 case LSHIFTRT:
8434 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8435 return false;
8436
8437 case DIV:
8438 case UDIV:
8439 case MOD:
8440 case UMOD:
8441 if (float_mode_p)
8442 {
8443 if (mode == DFmode)
8444 *total = sparc_costs->float_div_df;
8445 else
8446 *total = sparc_costs->float_div_sf;
8447 }
8448 else
8449 {
8450 if (mode == DImode)
8451 *total = sparc_costs->int_divX;
8452 else
8453 *total = sparc_costs->int_div;
8454 }
8455 return false;
8456
8457 case NEG:
8458 if (! float_mode_p)
8459 {
8460 *total = COSTS_N_INSNS (1);
8461 return false;
8462 }
8463 /* FALLTHRU */
8464
8465 case ABS:
8466 case FLOAT:
8467 case UNSIGNED_FLOAT:
8468 case FIX:
8469 case UNSIGNED_FIX:
8470 case FLOAT_EXTEND:
8471 case FLOAT_TRUNCATE:
8472 *total = sparc_costs->float_move;
8473 return false;
8474
8475 case SQRT:
8476 if (mode == DFmode)
8477 *total = sparc_costs->float_sqrt_df;
8478 else
8479 *total = sparc_costs->float_sqrt_sf;
8480 return false;
8481
8482 case COMPARE:
8483 if (float_mode_p)
8484 *total = sparc_costs->float_cmp;
8485 else
8486 *total = COSTS_N_INSNS (1);
8487 return false;
8488
8489 case IF_THEN_ELSE:
8490 if (float_mode_p)
8491 *total = sparc_costs->float_cmove;
8492 else
8493 *total = sparc_costs->int_cmove;
8494 return false;
8495
8496 default:
8497 return false;
8498 }
8499 }
8500
8501 /* Emit the sequence of insns SEQ while preserving the register REG. */
8502
8503 static void
8504 emit_and_preserve (rtx seq, rtx reg)
8505 {
8506 rtx slot = gen_rtx_MEM (word_mode,
8507 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8508
8509 emit_stack_pointer_decrement (GEN_INT (UNITS_PER_WORD));
8510 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8511 emit_insn (seq);
8512 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8513 emit_stack_pointer_increment (GEN_INT (UNITS_PER_WORD));
8514 }
8515
8516 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8517 Used for C++ multiple inheritance. */
8518
8519 static void
8520 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8521 HOST_WIDE_INT delta,
8522 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8523 tree function)
8524 {
8525 rtx this, insn, funexp, delta_rtx;
8526 unsigned int int_arg_first;
8527
8528 reload_completed = 1;
8529 epilogue_completed = 1;
8530 no_new_pseudos = 1;
8531 reset_block_changes ();
8532
8533 emit_note (NOTE_INSN_PROLOGUE_END);
8534
8535 if (flag_delayed_branch)
8536 {
8537 /* We will emit a regular sibcall below, so we need to instruct
8538 output_sibcall that we are in a leaf function. */
8539 current_function_uses_only_leaf_regs = 1;
8540
8541 /* This will cause final.c to invoke leaf_renumber_regs so we
8542 must behave as if we were in a not-yet-leafified function. */
8543 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8544 }
8545 else
8546 {
8547 /* We will emit the sibcall manually below, so we will need to
8548 manually spill non-leaf registers. */
8549 current_function_uses_only_leaf_regs = 0;
8550
8551 /* We really are in a leaf function. */
8552 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8553 }
8554
8555 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8556 returns a structure, the structure return pointer is there instead. */
8557 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8558 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8559 else
8560 this = gen_rtx_REG (Pmode, int_arg_first);
8561
8562 /* Add DELTA. When possible use a plain add, otherwise load it into
8563 a register first. */
8564 delta_rtx = GEN_INT (delta);
8565 if (!SPARC_SIMM13_P (delta))
8566 {
8567 rtx scratch = gen_rtx_REG (Pmode, 1);
8568
8569 if (input_operand (delta_rtx, GET_MODE (scratch)))
8570 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8571 else
8572 {
8573 if (TARGET_ARCH64)
8574 sparc_emit_set_const64 (scratch, delta_rtx);
8575 else
8576 sparc_emit_set_const32 (scratch, delta_rtx);
8577 }
8578
8579 delta_rtx = scratch;
8580 }
8581
8582 emit_insn (gen_rtx_SET (VOIDmode,
8583 this,
8584 gen_rtx_PLUS (Pmode, this, delta_rtx)));
8585
8586 /* Generate a tail call to the target function. */
8587 if (! TREE_USED (function))
8588 {
8589 assemble_external (function);
8590 TREE_USED (function) = 1;
8591 }
8592 funexp = XEXP (DECL_RTL (function), 0);
8593
8594 if (flag_delayed_branch)
8595 {
8596 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8597 insn = emit_call_insn (gen_sibcall (funexp));
8598 SIBLING_CALL_P (insn) = 1;
8599 }
8600 else
8601 {
8602 /* The hoops we have to jump through in order to generate a sibcall
8603 without using delay slots... */
8604 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
8605
8606 if (flag_pic)
8607 {
8608 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
8609 start_sequence ();
8610 load_pic_register (); /* clobbers %o7 */
8611 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8612 seq = get_insns ();
8613 end_sequence ();
8614 emit_and_preserve (seq, spill_reg);
8615 }
8616 else if (TARGET_ARCH32)
8617 {
8618 emit_insn (gen_rtx_SET (VOIDmode,
8619 scratch,
8620 gen_rtx_HIGH (SImode, funexp)));
8621 emit_insn (gen_rtx_SET (VOIDmode,
8622 scratch,
8623 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8624 }
8625 else /* TARGET_ARCH64 */
8626 {
8627 switch (sparc_cmodel)
8628 {
8629 case CM_MEDLOW:
8630 case CM_MEDMID:
8631 /* The destination can serve as a temporary. */
8632 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8633 break;
8634
8635 case CM_MEDANY:
8636 case CM_EMBMEDANY:
8637 /* The destination cannot serve as a temporary. */
8638 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8639 start_sequence ();
8640 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8641 seq = get_insns ();
8642 end_sequence ();
8643 emit_and_preserve (seq, spill_reg);
8644 break;
8645
8646 default:
8647 abort();
8648 }
8649 }
8650
8651 emit_jump_insn (gen_indirect_jump (scratch));
8652 }
8653
8654 emit_barrier ();
8655
8656 /* Run just enough of rest_of_compilation to get the insns emitted.
8657 There's not really enough bulk here to make other passes such as
8658 instruction scheduling worth while. Note that use_thunk calls
8659 assemble_start_function and assemble_end_function. */
8660 insn = get_insns ();
8661 insn_locators_initialize ();
8662 shorten_branches (insn);
8663 final_start_function (insn, file, 1);
8664 final (insn, file, 1, 0);
8665 final_end_function ();
8666
8667 reload_completed = 0;
8668 epilogue_completed = 0;
8669 no_new_pseudos = 0;
8670 }
8671
8672 /* How to allocate a 'struct machine_function'. */
8673
8674 static struct machine_function *
8675 sparc_init_machine_status (void)
8676 {
8677 return ggc_alloc_cleared (sizeof (struct machine_function));
8678 }
8679
8680 /* Locate some local-dynamic symbol still in use by this function
8681 so that we can print its name in local-dynamic base patterns. */
8682
8683 static const char *
8684 get_some_local_dynamic_name (void)
8685 {
8686 rtx insn;
8687
8688 if (cfun->machine->some_ld_name)
8689 return cfun->machine->some_ld_name;
8690
8691 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8692 if (INSN_P (insn)
8693 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8694 return cfun->machine->some_ld_name;
8695
8696 abort ();
8697 }
8698
8699 static int
8700 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8701 {
8702 rtx x = *px;
8703
8704 if (x
8705 && GET_CODE (x) == SYMBOL_REF
8706 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8707 {
8708 cfun->machine->some_ld_name = XSTR (x, 0);
8709 return 1;
8710 }
8711
8712 return 0;
8713 }
8714
8715 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8716 We need to emit DTP-relative relocations. */
8717
8718 void
8719 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8720 {
8721 switch (size)
8722 {
8723 case 4:
8724 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8725 break;
8726 case 8:
8727 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8728 break;
8729 default:
8730 abort ();
8731 }
8732 output_addr_const (file, x);
8733 fputs (")", file);
8734 }
8735
8736 #include "gt-sparc.h"