1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs
= {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs
= {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs
= {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs
= {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs
= {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs
= {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs
= {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs
= {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs
= {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
279 struct processor_costs niagara3_costs
= {
280 COSTS_N_INSNS (3), /* int load */
281 COSTS_N_INSNS (3), /* int signed load */
282 COSTS_N_INSNS (3), /* int zeroed load */
283 COSTS_N_INSNS (3), /* float load */
284 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
285 COSTS_N_INSNS (9), /* fadd, fsub */
286 COSTS_N_INSNS (9), /* fcmp */
287 COSTS_N_INSNS (9), /* fmov, fmovr */
288 COSTS_N_INSNS (9), /* fmul */
289 COSTS_N_INSNS (23), /* fdivs */
290 COSTS_N_INSNS (37), /* fdivd */
291 COSTS_N_INSNS (23), /* fsqrts */
292 COSTS_N_INSNS (37), /* fsqrtd */
293 COSTS_N_INSNS (9), /* imul */
294 COSTS_N_INSNS (9), /* imulX */
295 0, /* imul bit factor */
296 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
297 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
298 COSTS_N_INSNS (1), /* movcc/movr */
299 0, /* shift penalty */
302 const struct processor_costs
*sparc_costs
= &cypress_costs
;
304 #ifdef HAVE_AS_RELAX_OPTION
305 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
306 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
307 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
308 somebody does not branch between the sethi and jmp. */
309 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
311 #define LEAF_SIBCALL_SLOT_RESERVED_P \
312 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
315 /* Vector to say how input registers are mapped to output registers.
316 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
317 eliminate it. You must use -fomit-frame-pointer to get that. */
318 char leaf_reg_remap
[] =
319 { 0, 1, 2, 3, 4, 5, 6, 7,
320 -1, -1, -1, -1, -1, -1, 14, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1,
322 8, 9, 10, 11, 12, 13, -1, 15,
324 32, 33, 34, 35, 36, 37, 38, 39,
325 40, 41, 42, 43, 44, 45, 46, 47,
326 48, 49, 50, 51, 52, 53, 54, 55,
327 56, 57, 58, 59, 60, 61, 62, 63,
328 64, 65, 66, 67, 68, 69, 70, 71,
329 72, 73, 74, 75, 76, 77, 78, 79,
330 80, 81, 82, 83, 84, 85, 86, 87,
331 88, 89, 90, 91, 92, 93, 94, 95,
332 96, 97, 98, 99, 100, 101, 102};
334 /* Vector, indexed by hard register number, which contains 1
335 for a register that is allowable in a candidate for leaf
336 function treatment. */
337 char sparc_leaf_regs
[] =
338 { 1, 1, 1, 1, 1, 1, 1, 1,
339 0, 0, 0, 0, 0, 0, 1, 0,
340 0, 0, 0, 0, 0, 0, 0, 0,
341 1, 1, 1, 1, 1, 1, 0, 1,
342 1, 1, 1, 1, 1, 1, 1, 1,
343 1, 1, 1, 1, 1, 1, 1, 1,
344 1, 1, 1, 1, 1, 1, 1, 1,
345 1, 1, 1, 1, 1, 1, 1, 1,
346 1, 1, 1, 1, 1, 1, 1, 1,
347 1, 1, 1, 1, 1, 1, 1, 1,
348 1, 1, 1, 1, 1, 1, 1, 1,
349 1, 1, 1, 1, 1, 1, 1, 1,
350 1, 1, 1, 1, 1, 1, 1};
352 struct GTY(()) machine_function
354 /* Size of the frame of the function. */
355 HOST_WIDE_INT frame_size
;
357 /* Size of the frame of the function minus the register window save area
358 and the outgoing argument area. */
359 HOST_WIDE_INT apparent_frame_size
;
361 /* Register we pretend the frame pointer is allocated to. Normally, this
362 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
363 record "offset" separately as it may be too big for (reg + disp). */
365 HOST_WIDE_INT frame_base_offset
;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name
;
370 /* Number of global or FP registers to be saved (as 4-byte quantities). */
371 int n_global_fp_regs
;
373 /* True if the current function is leaf and uses only leaf regs,
374 so that the SPARC leaf function optimization can be applied.
375 Private version of current_function_uses_only_leaf_regs, see
376 sparc_expand_prologue for the rationale. */
379 /* True if the prologue saves local or in registers. */
380 bool save_local_in_regs_p
;
382 /* True if the data calculated by sparc_expand_prologue are valid. */
383 bool prologue_data_valid_p
;
386 #define sparc_frame_size cfun->machine->frame_size
387 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
388 #define sparc_frame_base_reg cfun->machine->frame_base_reg
389 #define sparc_frame_base_offset cfun->machine->frame_base_offset
390 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
391 #define sparc_leaf_function_p cfun->machine->leaf_function_p
392 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
393 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
395 /* 1 if the next opcode is to be specially indented. */
396 int sparc_indent_opcode
= 0;
398 static void sparc_option_override (void);
399 static void sparc_init_modes (void);
400 static void scan_record_type (const_tree
, int *, int *, int *);
401 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
402 const_tree
, bool, bool, int *, int *);
404 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
405 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
407 static void sparc_emit_set_const32 (rtx
, rtx
);
408 static void sparc_emit_set_const64 (rtx
, rtx
);
409 static void sparc_output_addr_vec (rtx
);
410 static void sparc_output_addr_diff_vec (rtx
);
411 static void sparc_output_deferred_case_vectors (void);
412 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
413 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
414 static rtx
sparc_builtin_saveregs (void);
415 static int epilogue_renumber (rtx
*, int);
416 static bool sparc_assemble_integer (rtx
, unsigned int, int);
417 static int set_extends (rtx
);
418 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
419 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
420 #ifdef TARGET_SOLARIS
421 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
422 tree
) ATTRIBUTE_UNUSED
;
424 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
425 static int sparc_issue_rate (void);
426 static void sparc_sched_init (FILE *, int, int);
427 static int sparc_use_sched_lookahead (void);
429 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
430 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
431 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
432 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
433 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
435 static bool sparc_function_ok_for_sibcall (tree
, tree
);
436 static void sparc_init_libfuncs (void);
437 static void sparc_init_builtins (void);
438 static void sparc_vis_init_builtins (void);
439 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
440 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
441 static int sparc_vis_mul8x16 (int, int);
442 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
443 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
444 HOST_WIDE_INT
, tree
);
445 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
446 HOST_WIDE_INT
, const_tree
);
447 static void sparc_reorg (void);
448 static struct machine_function
* sparc_init_machine_status (void);
449 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
450 static rtx
sparc_tls_get_addr (void);
451 static rtx
sparc_tls_got (void);
452 static const char *get_some_local_dynamic_name (void);
453 static int get_some_local_dynamic_name_1 (rtx
*, void *);
454 static int sparc_register_move_cost (enum machine_mode
,
455 reg_class_t
, reg_class_t
);
456 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
457 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
458 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
459 static bool sparc_function_value_regno_p (const unsigned int);
460 static rtx
sparc_struct_value_rtx (tree
, int);
461 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
462 int *, const_tree
, int);
463 static bool sparc_return_in_memory (const_tree
, const_tree
);
464 static bool sparc_strict_argument_naming (cumulative_args_t
);
465 static void sparc_va_start (tree
, rtx
);
466 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
467 static bool sparc_vector_mode_supported_p (enum machine_mode
);
468 static bool sparc_tls_referenced_p (rtx
);
469 static rtx
sparc_legitimize_tls_address (rtx
);
470 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
471 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
472 static rtx
sparc_delegitimize_address (rtx
);
473 static bool sparc_mode_dependent_address_p (const_rtx
);
474 static bool sparc_pass_by_reference (cumulative_args_t
,
475 enum machine_mode
, const_tree
, bool);
476 static void sparc_function_arg_advance (cumulative_args_t
,
477 enum machine_mode
, const_tree
, bool);
478 static rtx
sparc_function_arg_1 (cumulative_args_t
,
479 enum machine_mode
, const_tree
, bool, bool);
480 static rtx
sparc_function_arg (cumulative_args_t
,
481 enum machine_mode
, const_tree
, bool);
482 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
483 enum machine_mode
, const_tree
, bool);
484 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
486 static int sparc_arg_partial_bytes (cumulative_args_t
,
487 enum machine_mode
, tree
, bool);
488 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
489 static void sparc_file_end (void);
490 static bool sparc_frame_pointer_required (void);
491 static bool sparc_can_eliminate (const int, const int);
492 static rtx
sparc_builtin_setjmp_frame_value (void);
493 static void sparc_conditional_register_usage (void);
494 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
495 static const char *sparc_mangle_type (const_tree
);
497 static void sparc_trampoline_init (rtx
, tree
, rtx
);
498 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
499 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
500 static bool sparc_print_operand_punct_valid_p (unsigned char);
501 static void sparc_print_operand (FILE *, rtx
, int);
502 static void sparc_print_operand_address (FILE *, rtx
);
504 #ifdef SUBTARGET_ATTRIBUTE_TABLE
505 /* Table of valid machine attributes. */
506 static const struct attribute_spec sparc_attribute_table
[] =
508 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
510 SUBTARGET_ATTRIBUTE_TABLE
,
511 { NULL
, 0, 0, false, false, false, NULL
, false }
515 /* Option handling. */
518 enum cmodel sparc_cmodel
;
520 char sparc_hard_reg_printed
[8];
522 /* Initialize the GCC target structure. */
524 /* The default is to use .half rather than .short for aligned HI objects. */
525 #undef TARGET_ASM_ALIGNED_HI_OP
526 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
528 #undef TARGET_ASM_UNALIGNED_HI_OP
529 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
530 #undef TARGET_ASM_UNALIGNED_SI_OP
531 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
532 #undef TARGET_ASM_UNALIGNED_DI_OP
533 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
535 /* The target hook has to handle DI-mode values. */
536 #undef TARGET_ASM_INTEGER
537 #define TARGET_ASM_INTEGER sparc_assemble_integer
539 #undef TARGET_ASM_FUNCTION_PROLOGUE
540 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
541 #undef TARGET_ASM_FUNCTION_EPILOGUE
542 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
544 #undef TARGET_SCHED_ADJUST_COST
545 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
546 #undef TARGET_SCHED_ISSUE_RATE
547 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
548 #undef TARGET_SCHED_INIT
549 #define TARGET_SCHED_INIT sparc_sched_init
550 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
551 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
553 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
554 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
556 #undef TARGET_INIT_LIBFUNCS
557 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
558 #undef TARGET_INIT_BUILTINS
559 #define TARGET_INIT_BUILTINS sparc_init_builtins
561 #undef TARGET_LEGITIMIZE_ADDRESS
562 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
563 #undef TARGET_DELEGITIMIZE_ADDRESS
564 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
565 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
566 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
568 #undef TARGET_EXPAND_BUILTIN
569 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
570 #undef TARGET_FOLD_BUILTIN
571 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
574 #undef TARGET_HAVE_TLS
575 #define TARGET_HAVE_TLS true
578 #undef TARGET_CANNOT_FORCE_CONST_MEM
579 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
581 #undef TARGET_ASM_OUTPUT_MI_THUNK
582 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
583 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
584 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
586 #undef TARGET_MACHINE_DEPENDENT_REORG
587 #define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
589 #undef TARGET_RTX_COSTS
590 #define TARGET_RTX_COSTS sparc_rtx_costs
591 #undef TARGET_ADDRESS_COST
592 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
593 #undef TARGET_REGISTER_MOVE_COST
594 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
596 #undef TARGET_PROMOTE_FUNCTION_MODE
597 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
599 #undef TARGET_FUNCTION_VALUE
600 #define TARGET_FUNCTION_VALUE sparc_function_value
601 #undef TARGET_LIBCALL_VALUE
602 #define TARGET_LIBCALL_VALUE sparc_libcall_value
603 #undef TARGET_FUNCTION_VALUE_REGNO_P
604 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
606 #undef TARGET_STRUCT_VALUE_RTX
607 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
608 #undef TARGET_RETURN_IN_MEMORY
609 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
610 #undef TARGET_MUST_PASS_IN_STACK
611 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
612 #undef TARGET_PASS_BY_REFERENCE
613 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
614 #undef TARGET_ARG_PARTIAL_BYTES
615 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
616 #undef TARGET_FUNCTION_ARG_ADVANCE
617 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
618 #undef TARGET_FUNCTION_ARG
619 #define TARGET_FUNCTION_ARG sparc_function_arg
620 #undef TARGET_FUNCTION_INCOMING_ARG
621 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
622 #undef TARGET_FUNCTION_ARG_BOUNDARY
623 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
625 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
626 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
627 #undef TARGET_STRICT_ARGUMENT_NAMING
628 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
630 #undef TARGET_EXPAND_BUILTIN_VA_START
631 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
632 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
633 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
635 #undef TARGET_VECTOR_MODE_SUPPORTED_P
636 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
638 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
639 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
641 #ifdef SUBTARGET_INSERT_ATTRIBUTES
642 #undef TARGET_INSERT_ATTRIBUTES
643 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
646 #ifdef SUBTARGET_ATTRIBUTE_TABLE
647 #undef TARGET_ATTRIBUTE_TABLE
648 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
651 #undef TARGET_RELAXED_ORDERING
652 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
654 #undef TARGET_OPTION_OVERRIDE
655 #define TARGET_OPTION_OVERRIDE sparc_option_override
657 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
658 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
659 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
662 #undef TARGET_ASM_FILE_END
663 #define TARGET_ASM_FILE_END sparc_file_end
665 #undef TARGET_FRAME_POINTER_REQUIRED
666 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
668 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
669 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
671 #undef TARGET_CAN_ELIMINATE
672 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
674 #undef TARGET_PREFERRED_RELOAD_CLASS
675 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
677 #undef TARGET_CONDITIONAL_REGISTER_USAGE
678 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
680 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
681 #undef TARGET_MANGLE_TYPE
682 #define TARGET_MANGLE_TYPE sparc_mangle_type
685 #undef TARGET_LEGITIMATE_ADDRESS_P
686 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
688 #undef TARGET_LEGITIMATE_CONSTANT_P
689 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
691 #undef TARGET_TRAMPOLINE_INIT
692 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
694 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
695 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
696 #undef TARGET_PRINT_OPERAND
697 #define TARGET_PRINT_OPERAND sparc_print_operand
698 #undef TARGET_PRINT_OPERAND_ADDRESS
699 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
701 struct gcc_target targetm
= TARGET_INITIALIZER
;
704 dump_target_flag_bits (const int flags
)
706 if (flags
& MASK_64BIT
)
707 fprintf (stderr
, "64BIT ");
708 if (flags
& MASK_APP_REGS
)
709 fprintf (stderr
, "APP_REGS ");
710 if (flags
& MASK_FASTER_STRUCTS
)
711 fprintf (stderr
, "FASTER_STRUCTS ");
712 if (flags
& MASK_FLAT
)
713 fprintf (stderr
, "FLAT ");
714 if (flags
& MASK_FMAF
)
715 fprintf (stderr
, "FMAF ");
716 if (flags
& MASK_FPU
)
717 fprintf (stderr
, "FPU ");
718 if (flags
& MASK_HARD_QUAD
)
719 fprintf (stderr
, "HARD_QUAD ");
720 if (flags
& MASK_POPC
)
721 fprintf (stderr
, "POPC ");
722 if (flags
& MASK_PTR64
)
723 fprintf (stderr
, "PTR64 ");
724 if (flags
& MASK_STACK_BIAS
)
725 fprintf (stderr
, "STACK_BIAS ");
726 if (flags
& MASK_UNALIGNED_DOUBLES
)
727 fprintf (stderr
, "UNALIGNED_DOUBLES ");
728 if (flags
& MASK_V8PLUS
)
729 fprintf (stderr
, "V8PLUS ");
730 if (flags
& MASK_VIS
)
731 fprintf (stderr
, "VIS ");
732 if (flags
& MASK_VIS2
)
733 fprintf (stderr
, "VIS2 ");
734 if (flags
& MASK_VIS3
)
735 fprintf (stderr
, "VIS3 ");
736 if (flags
& MASK_DEPRECATED_V8_INSNS
)
737 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
738 if (flags
& MASK_LITTLE_ENDIAN
)
739 fprintf (stderr
, "LITTLE_ENDIAN ");
740 if (flags
& MASK_SPARCLET
)
741 fprintf (stderr
, "SPARCLET ");
742 if (flags
& MASK_SPARCLITE
)
743 fprintf (stderr
, "SPARCLITE ");
745 fprintf (stderr
, "V8 ");
747 fprintf (stderr
, "V9 ");
751 dump_target_flags (const char *prefix
, const int flags
)
753 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
754 dump_target_flag_bits (flags
);
755 fprintf(stderr
, "]\n");
758 /* Validate and override various options, and do some machine dependent
762 sparc_option_override (void)
764 static struct code_model
{
765 const char *const name
;
766 const enum cmodel value
;
767 } const cmodels
[] = {
769 { "medlow", CM_MEDLOW
},
770 { "medmid", CM_MEDMID
},
771 { "medany", CM_MEDANY
},
772 { "embmedany", CM_EMBMEDANY
},
773 { NULL
, (enum cmodel
) 0 }
775 const struct code_model
*cmodel
;
776 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
777 static struct cpu_default
{
779 const enum processor_type processor
;
780 } const cpu_default
[] = {
781 /* There must be one entry here for each TARGET_CPU value. */
782 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
783 { TARGET_CPU_v8
, PROCESSOR_V8
},
784 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
785 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
786 { TARGET_CPU_leon
, PROCESSOR_LEON
},
787 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
788 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
789 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
790 { TARGET_CPU_v9
, PROCESSOR_V9
},
791 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
792 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
793 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
794 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
795 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
796 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
799 const struct cpu_default
*def
;
800 /* Table of values for -m{cpu,tune}=. This must match the order of
801 the PROCESSOR_* enumeration. */
802 static struct cpu_table
{
803 const char *const name
;
806 } const cpu_table
[] = {
807 { "v7", MASK_ISA
, 0 },
808 { "cypress", MASK_ISA
, 0 },
809 { "v8", MASK_ISA
, MASK_V8
},
810 /* TI TMS390Z55 supersparc */
811 { "supersparc", MASK_ISA
, MASK_V8
},
812 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
814 { "leon", MASK_ISA
, MASK_V8
|MASK_FPU
},
815 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
816 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
817 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
818 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
819 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
820 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
821 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
823 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
824 { "v9", MASK_ISA
, MASK_V9
},
825 /* UltraSPARC I, II, IIi */
826 { "ultrasparc", MASK_ISA
,
827 /* Although insns using %y are deprecated, it is a clear win. */
828 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
830 /* ??? Check if %y issue still holds true. */
831 { "ultrasparc3", MASK_ISA
,
832 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
834 { "niagara", MASK_ISA
,
835 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
837 { "niagara2", MASK_ISA
,
838 MASK_V9
|MASK_POPC
|MASK_VIS2
},
840 { "niagara3", MASK_ISA
,
841 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
843 { "niagara4", MASK_ISA
,
844 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
846 const struct cpu_table
*cpu
;
850 if (sparc_debug_string
!= NULL
)
855 p
= ASTRDUP (sparc_debug_string
);
856 while ((q
= strtok (p
, ",")) != NULL
)
870 if (! strcmp (q
, "all"))
871 mask
= MASK_DEBUG_ALL
;
872 else if (! strcmp (q
, "options"))
873 mask
= MASK_DEBUG_OPTIONS
;
875 error ("unknown -mdebug-%s switch", q
);
878 sparc_debug
&= ~mask
;
884 if (TARGET_DEBUG_OPTIONS
)
886 dump_target_flags("Initial target_flags", target_flags
);
887 dump_target_flags("target_flags_explicit", target_flags_explicit
);
890 #ifdef SUBTARGET_OVERRIDE_OPTIONS
891 SUBTARGET_OVERRIDE_OPTIONS
;
894 #ifndef SPARC_BI_ARCH
895 /* Check for unsupported architecture size. */
896 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
897 error ("%s is not supported by this configuration",
898 DEFAULT_ARCH32_P
? "-m64" : "-m32");
901 /* We force all 64bit archs to use 128 bit long double */
902 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
904 error ("-mlong-double-64 not allowed with -m64");
905 target_flags
|= MASK_LONG_DOUBLE_128
;
908 /* Code model selection. */
909 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
913 sparc_cmodel
= CM_32
;
916 if (sparc_cmodel_string
!= NULL
)
920 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
921 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
923 if (cmodel
->name
== NULL
)
924 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
926 sparc_cmodel
= cmodel
->value
;
929 error ("-mcmodel= is not supported on 32 bit systems");
932 /* Check that -fcall-saved-REG wasn't specified for out registers. */
933 for (i
= 8; i
< 16; i
++)
934 if (!call_used_regs
[i
])
936 error ("-fcall-saved-REG is not supported for out registers");
937 call_used_regs
[i
] = 1;
940 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
942 /* Set the default CPU. */
943 if (!global_options_set
.x_sparc_cpu_and_features
)
945 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
946 if (def
->cpu
== TARGET_CPU_DEFAULT
)
948 gcc_assert (def
->cpu
!= -1);
949 sparc_cpu_and_features
= def
->processor
;
952 if ((target_flags
& MASK_V8PLUS
)
953 && sparc_cpu_and_features
< PROCESSOR_V9
)
954 sparc_cpu_and_features
= PROCESSOR_V9
;
956 if (!global_options_set
.x_sparc_cpu
)
957 sparc_cpu
= sparc_cpu_and_features
;
959 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
961 if (TARGET_DEBUG_OPTIONS
)
963 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
964 fprintf (stderr
, "sparc_cpu: %s\n",
965 cpu_table
[(int) sparc_cpu
].name
);
966 dump_target_flags ("cpu->disable", cpu
->disable
);
967 dump_target_flags ("cpu->enable", cpu
->enable
);
970 target_flags
&= ~cpu
->disable
;
971 target_flags
|= (cpu
->enable
972 #ifndef HAVE_AS_FMAF_HPC_VIS3
973 & ~(MASK_FMAF
| MASK_VIS3
)
977 /* If -mfpu or -mno-fpu was explicitly used, don't override with
978 the processor default. */
979 if (target_flags_explicit
& MASK_FPU
)
980 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
982 /* -mvis2 implies -mvis */
984 target_flags
|= MASK_VIS
;
986 /* -mvis3 implies -mvis2 and -mvis */
988 target_flags
|= MASK_VIS2
| MASK_VIS
;
990 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
992 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_FMAF
);
994 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
996 -m64 also implies v9. */
997 if (TARGET_VIS
|| TARGET_ARCH64
)
999 target_flags
|= MASK_V9
;
1000 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1003 /* -mvis also implies -mv8plus on 32-bit */
1004 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1005 target_flags
|= MASK_V8PLUS
;
1007 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1008 if (TARGET_V9
&& TARGET_ARCH32
)
1009 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1011 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1012 if (! TARGET_V9
|| TARGET_ARCH64
)
1013 target_flags
&= ~MASK_V8PLUS
;
1015 /* Don't use stack biasing in 32 bit mode. */
1017 target_flags
&= ~MASK_STACK_BIAS
;
1019 /* Supply a default value for align_functions. */
1020 if (align_functions
== 0
1021 && (sparc_cpu
== PROCESSOR_ULTRASPARC
1022 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1023 || sparc_cpu
== PROCESSOR_NIAGARA
1024 || sparc_cpu
== PROCESSOR_NIAGARA2
1025 || sparc_cpu
== PROCESSOR_NIAGARA3
1026 || sparc_cpu
== PROCESSOR_NIAGARA4
))
1027 align_functions
= 32;
1029 /* Validate PCC_STRUCT_RETURN. */
1030 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1031 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1033 /* Only use .uaxword when compiling for a 64-bit target. */
1035 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1037 /* Do various machine dependent initializations. */
1038 sparc_init_modes ();
1040 /* Set up function hooks. */
1041 init_machine_status
= sparc_init_machine_status
;
1046 case PROCESSOR_CYPRESS
:
1047 sparc_costs
= &cypress_costs
;
1050 case PROCESSOR_SPARCLITE
:
1051 case PROCESSOR_SUPERSPARC
:
1052 sparc_costs
= &supersparc_costs
;
1054 case PROCESSOR_F930
:
1055 case PROCESSOR_F934
:
1056 case PROCESSOR_HYPERSPARC
:
1057 case PROCESSOR_SPARCLITE86X
:
1058 sparc_costs
= &hypersparc_costs
;
1060 case PROCESSOR_LEON
:
1061 sparc_costs
= &leon_costs
;
1063 case PROCESSOR_SPARCLET
:
1064 case PROCESSOR_TSC701
:
1065 sparc_costs
= &sparclet_costs
;
1068 case PROCESSOR_ULTRASPARC
:
1069 sparc_costs
= &ultrasparc_costs
;
1071 case PROCESSOR_ULTRASPARC3
:
1072 sparc_costs
= &ultrasparc3_costs
;
1074 case PROCESSOR_NIAGARA
:
1075 sparc_costs
= &niagara_costs
;
1077 case PROCESSOR_NIAGARA2
:
1078 sparc_costs
= &niagara2_costs
;
1080 case PROCESSOR_NIAGARA3
:
1081 case PROCESSOR_NIAGARA4
:
1082 sparc_costs
= &niagara3_costs
;
1084 case PROCESSOR_NATIVE
:
1088 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1089 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1090 target_flags
|= MASK_LONG_DOUBLE_128
;
1093 if (TARGET_DEBUG_OPTIONS
)
1094 dump_target_flags ("Final target_flags", target_flags
);
1096 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1097 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1098 || sparc_cpu
== PROCESSOR_NIAGARA
1099 || sparc_cpu
== PROCESSOR_NIAGARA2
1100 || sparc_cpu
== PROCESSOR_NIAGARA3
1101 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1103 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1105 global_options
.x_param_values
,
1106 global_options_set
.x_param_values
);
1107 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1108 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1109 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1110 || sparc_cpu
== PROCESSOR_NIAGARA
1111 || sparc_cpu
== PROCESSOR_NIAGARA2
1112 || sparc_cpu
== PROCESSOR_NIAGARA3
1113 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1115 global_options
.x_param_values
,
1116 global_options_set
.x_param_values
);
1118 /* Disable save slot sharing for call-clobbered registers by default.
1119 The IRA sharing algorithm works on single registers only and this
1120 pessimizes for double floating-point registers. */
1121 if (!global_options_set
.x_flag_ira_share_save_slots
)
1122 flag_ira_share_save_slots
= 0;
1125 /* Miscellaneous utilities. */
1127 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1128 or branch on register contents instructions. */
1131 v9_regcmp_p (enum rtx_code code
)
1133 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1134 || code
== LE
|| code
== GT
);
1137 /* Nonzero if OP is a floating point constant which can
1138 be loaded into an integer register using a single
1139 sethi instruction. */
1144 if (GET_CODE (op
) == CONST_DOUBLE
)
1149 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1150 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1151 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1157 /* Nonzero if OP is a floating point constant which can
1158 be loaded into an integer register using a single
1164 if (GET_CODE (op
) == CONST_DOUBLE
)
1169 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1170 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1171 return SPARC_SIMM13_P (i
);
1177 /* Nonzero if OP is a floating point constant which can
1178 be loaded into an integer register using a high/losum
1179 instruction sequence. */
1182 fp_high_losum_p (rtx op
)
1184 /* The constraints calling this should only be in
1185 SFmode move insns, so any constant which cannot
1186 be moved using a single insn will do. */
1187 if (GET_CODE (op
) == CONST_DOUBLE
)
1192 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1193 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1194 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1200 /* Return true if the address of LABEL can be loaded by means of the
1201 mov{si,di}_pic_label_ref patterns in PIC mode. */
1204 can_use_mov_pic_label_ref (rtx label
)
1206 /* VxWorks does not impose a fixed gap between segments; the run-time
1207 gap can be different from the object-file gap. We therefore can't
1208 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1209 are absolutely sure that X is in the same segment as the GOT.
1210 Unfortunately, the flexibility of linker scripts means that we
1211 can't be sure of that in general, so assume that GOT-relative
1212 accesses are never valid on VxWorks. */
1213 if (TARGET_VXWORKS_RTP
)
1216 /* Similarly, if the label is non-local, it might end up being placed
1217 in a different section than the current one; now mov_pic_label_ref
1218 requires the label and the code to be in the same section. */
1219 if (LABEL_REF_NONLOCAL_P (label
))
1222 /* Finally, if we are reordering basic blocks and partition into hot
1223 and cold sections, this might happen for any label. */
1224 if (flag_reorder_blocks_and_partition
)
1230 /* Expand a move instruction. Return true if all work is done. */
1233 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1235 /* Handle sets of MEM first. */
1236 if (GET_CODE (operands
[0]) == MEM
)
1238 /* 0 is a register (or a pair of registers) on SPARC. */
1239 if (register_or_zero_operand (operands
[1], mode
))
1242 if (!reload_in_progress
)
1244 operands
[0] = validize_mem (operands
[0]);
1245 operands
[1] = force_reg (mode
, operands
[1]);
1249 /* Fixup TLS cases. */
1251 && CONSTANT_P (operands
[1])
1252 && sparc_tls_referenced_p (operands
[1]))
1254 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1258 /* Fixup PIC cases. */
1259 if (flag_pic
&& CONSTANT_P (operands
[1]))
1261 if (pic_address_needs_scratch (operands
[1]))
1262 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1264 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1265 if (GET_CODE (operands
[1]) == LABEL_REF
1266 && can_use_mov_pic_label_ref (operands
[1]))
1270 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1276 gcc_assert (TARGET_ARCH64
);
1277 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1282 if (symbolic_operand (operands
[1], mode
))
1285 = sparc_legitimize_pic_address (operands
[1],
1287 ? operands
[0] : NULL_RTX
);
1292 /* If we are trying to toss an integer constant into FP registers,
1293 or loading a FP or vector constant, force it into memory. */
1294 if (CONSTANT_P (operands
[1])
1295 && REG_P (operands
[0])
1296 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1297 || SCALAR_FLOAT_MODE_P (mode
)
1298 || VECTOR_MODE_P (mode
)))
1300 /* emit_group_store will send such bogosity to us when it is
1301 not storing directly into memory. So fix this up to avoid
1302 crashes in output_constant_pool. */
1303 if (operands
[1] == const0_rtx
)
1304 operands
[1] = CONST0_RTX (mode
);
1306 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1307 always other regs. */
1308 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1309 && (const_zero_operand (operands
[1], mode
)
1310 || const_all_ones_operand (operands
[1], mode
)))
1313 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1314 /* We are able to build any SF constant in integer registers
1315 with at most 2 instructions. */
1317 /* And any DF constant in integer registers. */
1319 && (reload_completed
|| reload_in_progress
))))
1322 operands
[1] = force_const_mem (mode
, operands
[1]);
1323 if (!reload_in_progress
)
1324 operands
[1] = validize_mem (operands
[1]);
1328 /* Accept non-constants and valid constants unmodified. */
1329 if (!CONSTANT_P (operands
[1])
1330 || GET_CODE (operands
[1]) == HIGH
1331 || input_operand (operands
[1], mode
))
1337 /* All QImode constants require only one insn, so proceed. */
1342 sparc_emit_set_const32 (operands
[0], operands
[1]);
1346 /* input_operand should have filtered out 32-bit mode. */
1347 sparc_emit_set_const64 (operands
[0], operands
[1]);
1357 /* Load OP1, a 32-bit constant, into OP0, a register.
1358 We know it can't be done in one insn when we get
1359 here, the move expander guarantees this. */
1362 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1364 enum machine_mode mode
= GET_MODE (op0
);
1367 if (reload_in_progress
|| reload_completed
)
1370 temp
= gen_reg_rtx (mode
);
1372 if (GET_CODE (op1
) == CONST_INT
)
1374 gcc_assert (!small_int_operand (op1
, mode
)
1375 && !const_high_operand (op1
, mode
));
1377 /* Emit them as real moves instead of a HIGH/LO_SUM,
1378 this way CSE can see everything and reuse intermediate
1379 values if it wants. */
1380 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1381 GEN_INT (INTVAL (op1
)
1382 & ~(HOST_WIDE_INT
)0x3ff)));
1384 emit_insn (gen_rtx_SET (VOIDmode
,
1386 gen_rtx_IOR (mode
, temp
,
1387 GEN_INT (INTVAL (op1
) & 0x3ff))));
1391 /* A symbol, emit in the traditional way. */
1392 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1393 gen_rtx_HIGH (mode
, op1
)));
1394 emit_insn (gen_rtx_SET (VOIDmode
,
1395 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1399 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1400 If TEMP is nonzero, we are forbidden to use any other scratch
1401 registers. Otherwise, we are allowed to generate them as needed.
1403 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1404 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1407 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1409 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1412 if (temp
&& GET_MODE (temp
) == TImode
)
1415 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1418 /* SPARC-V9 code-model support. */
1419 switch (sparc_cmodel
)
1422 /* The range spanned by all instructions in the object is less
1423 than 2^31 bytes (2GB) and the distance from any instruction
1424 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1425 than 2^31 bytes (2GB).
1427 The executable must be in the low 4TB of the virtual address
1430 sethi %hi(symbol), %temp1
1431 or %temp1, %lo(symbol), %reg */
1433 temp1
= temp
; /* op0 is allowed. */
1435 temp1
= gen_reg_rtx (DImode
);
1437 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1438 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1442 /* The range spanned by all instructions in the object is less
1443 than 2^31 bytes (2GB) and the distance from any instruction
1444 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1445 than 2^31 bytes (2GB).
1447 The executable must be in the low 16TB of the virtual address
1450 sethi %h44(symbol), %temp1
1451 or %temp1, %m44(symbol), %temp2
1452 sllx %temp2, 12, %temp3
1453 or %temp3, %l44(symbol), %reg */
1458 temp3
= temp
; /* op0 is allowed. */
1462 temp1
= gen_reg_rtx (DImode
);
1463 temp2
= gen_reg_rtx (DImode
);
1464 temp3
= gen_reg_rtx (DImode
);
1467 emit_insn (gen_seth44 (temp1
, op1
));
1468 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1469 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1470 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1471 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1475 /* The range spanned by all instructions in the object is less
1476 than 2^31 bytes (2GB) and the distance from any instruction
1477 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1478 than 2^31 bytes (2GB).
1480 The executable can be placed anywhere in the virtual address
1483 sethi %hh(symbol), %temp1
1484 sethi %lm(symbol), %temp2
1485 or %temp1, %hm(symbol), %temp3
1486 sllx %temp3, 32, %temp4
1487 or %temp4, %temp2, %temp5
1488 or %temp5, %lo(symbol), %reg */
1491 /* It is possible that one of the registers we got for operands[2]
1492 might coincide with that of operands[0] (which is why we made
1493 it TImode). Pick the other one to use as our scratch. */
1494 if (rtx_equal_p (temp
, op0
))
1496 gcc_assert (ti_temp
);
1497 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1500 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1507 temp1
= gen_reg_rtx (DImode
);
1508 temp2
= gen_reg_rtx (DImode
);
1509 temp3
= gen_reg_rtx (DImode
);
1510 temp4
= gen_reg_rtx (DImode
);
1511 temp5
= gen_reg_rtx (DImode
);
1514 emit_insn (gen_sethh (temp1
, op1
));
1515 emit_insn (gen_setlm (temp2
, op1
));
1516 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1517 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1518 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1519 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1520 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1521 emit_insn (gen_setlo (op0
, temp5
, op1
));
1525 /* Old old old backwards compatibility kruft here.
1526 Essentially it is MEDLOW with a fixed 64-bit
1527 virtual base added to all data segment addresses.
1528 Text-segment stuff is computed like MEDANY, we can't
1529 reuse the code above because the relocation knobs
1532 Data segment: sethi %hi(symbol), %temp1
1533 add %temp1, EMBMEDANY_BASE_REG, %temp2
1534 or %temp2, %lo(symbol), %reg */
1535 if (data_segment_operand (op1
, GET_MODE (op1
)))
1539 temp1
= temp
; /* op0 is allowed. */
1544 temp1
= gen_reg_rtx (DImode
);
1545 temp2
= gen_reg_rtx (DImode
);
1548 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1549 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1550 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1553 /* Text segment: sethi %uhi(symbol), %temp1
1554 sethi %hi(symbol), %temp2
1555 or %temp1, %ulo(symbol), %temp3
1556 sllx %temp3, 32, %temp4
1557 or %temp4, %temp2, %temp5
1558 or %temp5, %lo(symbol), %reg */
1563 /* It is possible that one of the registers we got for operands[2]
1564 might coincide with that of operands[0] (which is why we made
1565 it TImode). Pick the other one to use as our scratch. */
1566 if (rtx_equal_p (temp
, op0
))
1568 gcc_assert (ti_temp
);
1569 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1572 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1579 temp1
= gen_reg_rtx (DImode
);
1580 temp2
= gen_reg_rtx (DImode
);
1581 temp3
= gen_reg_rtx (DImode
);
1582 temp4
= gen_reg_rtx (DImode
);
1583 temp5
= gen_reg_rtx (DImode
);
1586 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1587 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1588 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1589 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1590 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1591 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1592 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1593 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1602 #if HOST_BITS_PER_WIDE_INT == 32
1604 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1609 /* These avoid problems when cross compiling. If we do not
1610 go through all this hair then the optimizer will see
1611 invalid REG_EQUAL notes or in some cases none at all. */
1612 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1613 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1614 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1615 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1617 /* The optimizer is not to assume anything about exactly
1618 which bits are set for a HIGH, they are unspecified.
1619 Unfortunately this leads to many missed optimizations
1620 during CSE. We mask out the non-HIGH bits, and matches
1621 a plain movdi, to alleviate this problem. */
1623 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1625 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1629 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1631 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1635 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1637 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1641 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1643 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1646 /* Worker routines for 64-bit constant formation on arch64.
1647 One of the key things to be doing in these emissions is
1648 to create as many temp REGs as possible. This makes it
1649 possible for half-built constants to be used later when
1650 such values are similar to something required later on.
1651 Without doing this, the optimizer cannot see such
1654 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1655 unsigned HOST_WIDE_INT
, int);
1658 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1659 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1661 unsigned HOST_WIDE_INT high_bits
;
1664 high_bits
= (~low_bits
) & 0xffffffff;
1666 high_bits
= low_bits
;
1668 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1671 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1672 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1676 /* If we are XOR'ing with -1, then we should emit a one's complement
1677 instead. This way the combiner will notice logical operations
1678 such as ANDN later on and substitute. */
1679 if ((low_bits
& 0x3ff) == 0x3ff)
1681 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1682 gen_rtx_NOT (DImode
, temp
)));
1686 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1687 gen_safe_XOR64 (temp
,
1688 (-(HOST_WIDE_INT
)0x400
1689 | (low_bits
& 0x3ff)))));
1694 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1695 unsigned HOST_WIDE_INT
, int);
1698 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1699 unsigned HOST_WIDE_INT high_bits
,
1700 unsigned HOST_WIDE_INT low_immediate
,
1705 if ((high_bits
& 0xfffffc00) != 0)
1707 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1708 if ((high_bits
& ~0xfffffc00) != 0)
1709 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1710 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1716 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1720 /* Now shift it up into place. */
1721 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1722 gen_rtx_ASHIFT (DImode
, temp2
,
1723 GEN_INT (shift_count
))));
1725 /* If there is a low immediate part piece, finish up by
1726 putting that in as well. */
1727 if (low_immediate
!= 0)
1728 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1729 gen_safe_OR64 (op0
, low_immediate
)));
1732 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1733 unsigned HOST_WIDE_INT
);
1735 /* Full 64-bit constant decomposition. Even though this is the
1736 'worst' case, we still optimize a few things away. */
1738 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1739 unsigned HOST_WIDE_INT high_bits
,
1740 unsigned HOST_WIDE_INT low_bits
)
1744 if (reload_in_progress
|| reload_completed
)
1747 sub_temp
= gen_reg_rtx (DImode
);
1749 if ((high_bits
& 0xfffffc00) != 0)
1751 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1752 if ((high_bits
& ~0xfffffc00) != 0)
1753 emit_insn (gen_rtx_SET (VOIDmode
,
1755 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1761 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1765 if (!reload_in_progress
&& !reload_completed
)
1767 rtx temp2
= gen_reg_rtx (DImode
);
1768 rtx temp3
= gen_reg_rtx (DImode
);
1769 rtx temp4
= gen_reg_rtx (DImode
);
1771 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1772 gen_rtx_ASHIFT (DImode
, sub_temp
,
1775 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1776 if ((low_bits
& ~0xfffffc00) != 0)
1778 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1779 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1780 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1781 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1785 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1786 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1791 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1792 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1793 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1796 /* We are in the middle of reload, so this is really
1797 painful. However we do still make an attempt to
1798 avoid emitting truly stupid code. */
1799 if (low1
!= const0_rtx
)
1801 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1802 gen_rtx_ASHIFT (DImode
, sub_temp
,
1803 GEN_INT (to_shift
))));
1804 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1805 gen_rtx_IOR (DImode
, op0
, low1
)));
1813 if (low2
!= const0_rtx
)
1815 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1816 gen_rtx_ASHIFT (DImode
, sub_temp
,
1817 GEN_INT (to_shift
))));
1818 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1819 gen_rtx_IOR (DImode
, op0
, low2
)));
1827 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1828 gen_rtx_ASHIFT (DImode
, sub_temp
,
1829 GEN_INT (to_shift
))));
1830 if (low3
!= const0_rtx
)
1831 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1832 gen_rtx_IOR (DImode
, op0
, low3
)));
1837 /* Analyze a 64-bit constant for certain properties. */
1838 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1839 unsigned HOST_WIDE_INT
,
1840 int *, int *, int *);
1843 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1844 unsigned HOST_WIDE_INT low_bits
,
1845 int *hbsp
, int *lbsp
, int *abbasp
)
1847 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1850 lowest_bit_set
= highest_bit_set
= -1;
1854 if ((lowest_bit_set
== -1)
1855 && ((low_bits
>> i
) & 1))
1857 if ((highest_bit_set
== -1)
1858 && ((high_bits
>> (32 - i
- 1)) & 1))
1859 highest_bit_set
= (64 - i
- 1);
1862 && ((highest_bit_set
== -1)
1863 || (lowest_bit_set
== -1)));
1869 if ((lowest_bit_set
== -1)
1870 && ((high_bits
>> i
) & 1))
1871 lowest_bit_set
= i
+ 32;
1872 if ((highest_bit_set
== -1)
1873 && ((low_bits
>> (32 - i
- 1)) & 1))
1874 highest_bit_set
= 32 - i
- 1;
1877 && ((highest_bit_set
== -1)
1878 || (lowest_bit_set
== -1)));
1880 /* If there are no bits set this should have gone out
1881 as one instruction! */
1882 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1883 all_bits_between_are_set
= 1;
1884 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1888 if ((low_bits
& (1 << i
)) != 0)
1893 if ((high_bits
& (1 << (i
- 32))) != 0)
1896 all_bits_between_are_set
= 0;
1899 *hbsp
= highest_bit_set
;
1900 *lbsp
= lowest_bit_set
;
1901 *abbasp
= all_bits_between_are_set
;
1904 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1907 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1908 unsigned HOST_WIDE_INT low_bits
)
1910 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1913 || high_bits
== 0xffffffff)
1916 analyze_64bit_constant (high_bits
, low_bits
,
1917 &highest_bit_set
, &lowest_bit_set
,
1918 &all_bits_between_are_set
);
1920 if ((highest_bit_set
== 63
1921 || lowest_bit_set
== 0)
1922 && all_bits_between_are_set
!= 0)
1925 if ((highest_bit_set
- lowest_bit_set
) < 21)
1931 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1932 unsigned HOST_WIDE_INT
,
1935 static unsigned HOST_WIDE_INT
1936 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1937 unsigned HOST_WIDE_INT low_bits
,
1938 int lowest_bit_set
, int shift
)
1940 HOST_WIDE_INT hi
, lo
;
1942 if (lowest_bit_set
< 32)
1944 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1945 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1950 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1952 gcc_assert (! (hi
& lo
));
1956 /* Here we are sure to be arch64 and this is an integer constant
1957 being loaded into a register. Emit the most efficient
1958 insn sequence possible. Detection of all the 1-insn cases
1959 has been done already. */
1961 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1963 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1964 int lowest_bit_set
, highest_bit_set
;
1965 int all_bits_between_are_set
;
1968 /* Sanity check that we know what we are working with. */
1969 gcc_assert (TARGET_ARCH64
1970 && (GET_CODE (op0
) == SUBREG
1971 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1973 if (reload_in_progress
|| reload_completed
)
1976 if (GET_CODE (op1
) != CONST_INT
)
1978 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1983 temp
= gen_reg_rtx (DImode
);
1985 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1986 low_bits
= (INTVAL (op1
) & 0xffffffff);
1988 /* low_bits bits 0 --> 31
1989 high_bits bits 32 --> 63 */
1991 analyze_64bit_constant (high_bits
, low_bits
,
1992 &highest_bit_set
, &lowest_bit_set
,
1993 &all_bits_between_are_set
);
1995 /* First try for a 2-insn sequence. */
1997 /* These situations are preferred because the optimizer can
1998 * do more things with them:
2000 * sllx %reg, shift, %reg
2002 * srlx %reg, shift, %reg
2003 * 3) mov some_small_const, %reg
2004 * sllx %reg, shift, %reg
2006 if (((highest_bit_set
== 63
2007 || lowest_bit_set
== 0)
2008 && all_bits_between_are_set
!= 0)
2009 || ((highest_bit_set
- lowest_bit_set
) < 12))
2011 HOST_WIDE_INT the_const
= -1;
2012 int shift
= lowest_bit_set
;
2014 if ((highest_bit_set
!= 63
2015 && lowest_bit_set
!= 0)
2016 || all_bits_between_are_set
== 0)
2019 create_simple_focus_bits (high_bits
, low_bits
,
2022 else if (lowest_bit_set
== 0)
2023 shift
= -(63 - highest_bit_set
);
2025 gcc_assert (SPARC_SIMM13_P (the_const
));
2026 gcc_assert (shift
!= 0);
2028 emit_insn (gen_safe_SET64 (temp
, the_const
));
2030 emit_insn (gen_rtx_SET (VOIDmode
,
2032 gen_rtx_ASHIFT (DImode
,
2036 emit_insn (gen_rtx_SET (VOIDmode
,
2038 gen_rtx_LSHIFTRT (DImode
,
2040 GEN_INT (-shift
))));
2044 /* Now a range of 22 or less bits set somewhere.
2045 * 1) sethi %hi(focus_bits), %reg
2046 * sllx %reg, shift, %reg
2047 * 2) sethi %hi(focus_bits), %reg
2048 * srlx %reg, shift, %reg
2050 if ((highest_bit_set
- lowest_bit_set
) < 21)
2052 unsigned HOST_WIDE_INT focus_bits
=
2053 create_simple_focus_bits (high_bits
, low_bits
,
2054 lowest_bit_set
, 10);
2056 gcc_assert (SPARC_SETHI_P (focus_bits
));
2057 gcc_assert (lowest_bit_set
!= 10);
2059 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2061 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2062 if (lowest_bit_set
< 10)
2063 emit_insn (gen_rtx_SET (VOIDmode
,
2065 gen_rtx_LSHIFTRT (DImode
, temp
,
2066 GEN_INT (10 - lowest_bit_set
))));
2067 else if (lowest_bit_set
> 10)
2068 emit_insn (gen_rtx_SET (VOIDmode
,
2070 gen_rtx_ASHIFT (DImode
, temp
,
2071 GEN_INT (lowest_bit_set
- 10))));
2075 /* 1) sethi %hi(low_bits), %reg
2076 * or %reg, %lo(low_bits), %reg
2077 * 2) sethi %hi(~low_bits), %reg
2078 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2081 || high_bits
== 0xffffffff)
2083 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2084 (high_bits
== 0xffffffff));
2088 /* Now, try 3-insn sequences. */
2090 /* 1) sethi %hi(high_bits), %reg
2091 * or %reg, %lo(high_bits), %reg
2092 * sllx %reg, 32, %reg
2096 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2100 /* We may be able to do something quick
2101 when the constant is negated, so try that. */
2102 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2103 (~low_bits
) & 0xfffffc00))
2105 /* NOTE: The trailing bits get XOR'd so we need the
2106 non-negated bits, not the negated ones. */
2107 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2109 if ((((~high_bits
) & 0xffffffff) == 0
2110 && ((~low_bits
) & 0x80000000) == 0)
2111 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2112 && ((~low_bits
) & 0x80000000) != 0))
2114 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2116 if ((SPARC_SETHI_P (fast_int
)
2117 && (~high_bits
& 0xffffffff) == 0)
2118 || SPARC_SIMM13_P (fast_int
))
2119 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2121 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2126 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2127 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2128 sparc_emit_set_const64 (temp
, negated_const
);
2131 /* If we are XOR'ing with -1, then we should emit a one's complement
2132 instead. This way the combiner will notice logical operations
2133 such as ANDN later on and substitute. */
2134 if (trailing_bits
== 0x3ff)
2136 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2137 gen_rtx_NOT (DImode
, temp
)));
2141 emit_insn (gen_rtx_SET (VOIDmode
,
2143 gen_safe_XOR64 (temp
,
2144 (-0x400 | trailing_bits
))));
2149 /* 1) sethi %hi(xxx), %reg
2150 * or %reg, %lo(xxx), %reg
2151 * sllx %reg, yyy, %reg
2153 * ??? This is just a generalized version of the low_bits==0
2154 * thing above, FIXME...
2156 if ((highest_bit_set
- lowest_bit_set
) < 32)
2158 unsigned HOST_WIDE_INT focus_bits
=
2159 create_simple_focus_bits (high_bits
, low_bits
,
2162 /* We can't get here in this state. */
2163 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2165 /* So what we know is that the set bits straddle the
2166 middle of the 64-bit word. */
2167 sparc_emit_set_const64_quick2 (op0
, temp
,
2173 /* 1) sethi %hi(high_bits), %reg
2174 * or %reg, %lo(high_bits), %reg
2175 * sllx %reg, 32, %reg
2176 * or %reg, low_bits, %reg
2178 if (SPARC_SIMM13_P(low_bits
)
2179 && ((int)low_bits
> 0))
2181 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2185 /* The easiest way when all else fails, is full decomposition. */
2186 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2188 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2190 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2191 return the mode to be used for the comparison. For floating-point,
2192 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2193 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2194 processing is needed. */
2197 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2199 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2225 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2226 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2228 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2229 return CCX_NOOVmode
;
2235 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2242 /* Emit the compare insn and return the CC reg for a CODE comparison
2243 with operands X and Y. */
2246 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2248 enum machine_mode mode
;
2251 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2254 mode
= SELECT_CC_MODE (code
, x
, y
);
2256 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2257 fcc regs (cse can't tell they're really call clobbered regs and will
2258 remove a duplicate comparison even if there is an intervening function
2259 call - it will then try to reload the cc reg via an int reg which is why
2260 we need the movcc patterns). It is possible to provide the movcc
2261 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2262 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2263 to tell cse that CCFPE mode registers (even pseudos) are call
2266 /* ??? This is an experiment. Rather than making changes to cse which may
2267 or may not be easy/clean, we do our own cse. This is possible because
2268 we will generate hard registers. Cse knows they're call clobbered (it
2269 doesn't know the same thing about pseudos). If we guess wrong, no big
2270 deal, but if we win, great! */
2272 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2273 #if 1 /* experiment */
2276 /* We cycle through the registers to ensure they're all exercised. */
2277 static int next_fcc_reg
= 0;
2278 /* Previous x,y for each fcc reg. */
2279 static rtx prev_args
[4][2];
2281 /* Scan prev_args for x,y. */
2282 for (reg
= 0; reg
< 4; reg
++)
2283 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2288 prev_args
[reg
][0] = x
;
2289 prev_args
[reg
][1] = y
;
2290 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2292 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2295 cc_reg
= gen_reg_rtx (mode
);
2296 #endif /* ! experiment */
2297 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2298 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2300 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2302 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2303 will only result in an unrecognizable insn so no point in asserting. */
2304 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2310 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2313 gen_compare_reg (rtx cmp
)
2315 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2318 /* This function is used for v9 only.
2319 DEST is the target of the Scc insn.
2320 CODE is the code for an Scc's comparison.
2321 X and Y are the values we compare.
2323 This function is needed to turn
2326 (gt (reg:CCX 100 %icc)
2330 (gt:DI (reg:CCX 100 %icc)
2333 IE: The instruction recognizer needs to see the mode of the comparison to
2334 find the right instruction. We could use "gt:DI" right in the
2335 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2338 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2341 && (GET_MODE (x
) == DImode
2342 || GET_MODE (dest
) == DImode
))
2345 /* Try to use the movrCC insns. */
2347 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2349 && v9_regcmp_p (compare_code
))
2354 /* Special case for op0 != 0. This can be done with one instruction if
2357 if (compare_code
== NE
2358 && GET_MODE (dest
) == DImode
2359 && rtx_equal_p (op0
, dest
))
2361 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2362 gen_rtx_IF_THEN_ELSE (DImode
,
2363 gen_rtx_fmt_ee (compare_code
, DImode
,
2370 if (reg_overlap_mentioned_p (dest
, op0
))
2372 /* Handle the case where dest == x.
2373 We "early clobber" the result. */
2374 op0
= gen_reg_rtx (GET_MODE (x
));
2375 emit_move_insn (op0
, x
);
2378 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2379 if (GET_MODE (op0
) != DImode
)
2381 temp
= gen_reg_rtx (DImode
);
2382 convert_move (temp
, op0
, 0);
2386 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2387 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2388 gen_rtx_fmt_ee (compare_code
, DImode
,
2396 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2399 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2400 && GET_MODE (x
) != CCX_NOOVmode
);
2402 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2403 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2404 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2405 gen_rtx_fmt_ee (compare_code
,
2406 GET_MODE (x
), x
, y
),
2407 const1_rtx
, dest
)));
2413 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2414 without jumps using the addx/subx instructions. */
2417 emit_scc_insn (rtx operands
[])
2424 /* The quad-word fp compare library routines all return nonzero to indicate
2425 true, which is different from the equivalent libgcc routines, so we must
2426 handle them specially here. */
2427 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2429 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2430 GET_CODE (operands
[1]));
2431 operands
[2] = XEXP (operands
[1], 0);
2432 operands
[3] = XEXP (operands
[1], 1);
2435 code
= GET_CODE (operands
[1]);
2439 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2440 more applications). The exception to this is "reg != 0" which can
2441 be done in one instruction on v9 (so we do it). */
2444 if (GET_MODE (x
) == SImode
)
2446 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2450 else if (GET_MODE (x
) == DImode
)
2452 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2460 if (GET_MODE (x
) == SImode
)
2462 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2466 else if (GET_MODE (x
) == DImode
)
2468 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2474 /* For the rest, on v9 we can use conditional moves. */
2478 if (gen_v9_scc (operands
[0], code
, x
, y
))
2482 /* We can do LTU and GEU using the addx/subx instructions too. And
2483 for GTU/LEU, if both operands are registers swap them and fall
2484 back to the easy case. */
2485 if (code
== GTU
|| code
== LEU
)
2487 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2488 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2493 code
= swap_condition (code
);
2497 if (code
== LTU
|| code
== GEU
)
2499 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2500 gen_rtx_fmt_ee (code
, SImode
,
2501 gen_compare_reg_1 (code
, x
, y
),
2506 /* Nope, do branches. */
2510 /* Emit a conditional jump insn for the v9 architecture using comparison code
2511 CODE and jump target LABEL.
2512 This function exists to take advantage of the v9 brxx insns. */
2515 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2517 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2519 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2520 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2522 gen_rtx_LABEL_REF (VOIDmode
, label
),
2527 emit_conditional_branch_insn (rtx operands
[])
2529 /* The quad-word fp compare library routines all return nonzero to indicate
2530 true, which is different from the equivalent libgcc routines, so we must
2531 handle them specially here. */
2532 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2534 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2535 GET_CODE (operands
[0]));
2536 operands
[1] = XEXP (operands
[0], 0);
2537 operands
[2] = XEXP (operands
[0], 1);
2540 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2541 && GET_CODE (operands
[1]) == REG
2542 && GET_MODE (operands
[1]) == DImode
)
2544 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2548 operands
[1] = gen_compare_reg (operands
[0]);
2549 operands
[2] = const0_rtx
;
2550 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2551 operands
[1], operands
[2]);
2552 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2557 /* Generate a DFmode part of a hard TFmode register.
2558 REG is the TFmode hard register, LOW is 1 for the
2559 low 64bit of the register and 0 otherwise.
2562 gen_df_reg (rtx reg
, int low
)
2564 int regno
= REGNO (reg
);
2566 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2567 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2568 return gen_rtx_REG (DFmode
, regno
);
2571 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2572 Unlike normal calls, TFmode operands are passed by reference. It is
2573 assumed that no more than 3 operands are required. */
2576 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2578 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2581 /* We only expect to be called for conversions, unary, and binary ops. */
2582 gcc_assert (nargs
== 2 || nargs
== 3);
2584 for (i
= 0; i
< nargs
; ++i
)
2586 rtx this_arg
= operands
[i
];
2589 /* TFmode arguments and return values are passed by reference. */
2590 if (GET_MODE (this_arg
) == TFmode
)
2592 int force_stack_temp
;
2594 force_stack_temp
= 0;
2595 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2596 force_stack_temp
= 1;
2598 if (GET_CODE (this_arg
) == MEM
2599 && ! force_stack_temp
)
2600 this_arg
= XEXP (this_arg
, 0);
2601 else if (CONSTANT_P (this_arg
)
2602 && ! force_stack_temp
)
2604 this_slot
= force_const_mem (TFmode
, this_arg
);
2605 this_arg
= XEXP (this_slot
, 0);
2609 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2611 /* Operand 0 is the return value. We'll copy it out later. */
2613 emit_move_insn (this_slot
, this_arg
);
2615 ret_slot
= this_slot
;
2617 this_arg
= XEXP (this_slot
, 0);
2624 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2626 if (GET_MODE (operands
[0]) == TFmode
)
2629 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2630 arg
[0], GET_MODE (arg
[0]),
2631 arg
[1], GET_MODE (arg
[1]));
2633 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2634 arg
[0], GET_MODE (arg
[0]),
2635 arg
[1], GET_MODE (arg
[1]),
2636 arg
[2], GET_MODE (arg
[2]));
2639 emit_move_insn (operands
[0], ret_slot
);
2645 gcc_assert (nargs
== 2);
2647 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2648 GET_MODE (operands
[0]), 1,
2649 arg
[1], GET_MODE (arg
[1]));
2651 if (ret
!= operands
[0])
2652 emit_move_insn (operands
[0], ret
);
2656 /* Expand soft-float TFmode calls to sparc abi routines. */
2659 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2681 emit_soft_tfmode_libcall (func
, 3, operands
);
2685 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2689 gcc_assert (code
== SQRT
);
2692 emit_soft_tfmode_libcall (func
, 2, operands
);
2696 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2703 switch (GET_MODE (operands
[1]))
2716 case FLOAT_TRUNCATE
:
2717 switch (GET_MODE (operands
[0]))
2731 switch (GET_MODE (operands
[1]))
2736 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2746 case UNSIGNED_FLOAT
:
2747 switch (GET_MODE (operands
[1]))
2752 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2763 switch (GET_MODE (operands
[0]))
2777 switch (GET_MODE (operands
[0]))
2794 emit_soft_tfmode_libcall (func
, 2, operands
);
2797 /* Expand a hard-float tfmode operation. All arguments must be in
2801 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2805 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2807 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2808 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2812 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2813 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2814 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2815 operands
[1], operands
[2]);
2818 if (register_operand (operands
[0], VOIDmode
))
2821 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2823 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2825 if (dest
!= operands
[0])
2826 emit_move_insn (operands
[0], dest
);
2830 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2832 if (TARGET_HARD_QUAD
)
2833 emit_hard_tfmode_operation (code
, operands
);
2835 emit_soft_tfmode_binop (code
, operands
);
2839 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2841 if (TARGET_HARD_QUAD
)
2842 emit_hard_tfmode_operation (code
, operands
);
2844 emit_soft_tfmode_unop (code
, operands
);
2848 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2850 if (TARGET_HARD_QUAD
)
2851 emit_hard_tfmode_operation (code
, operands
);
2853 emit_soft_tfmode_cvt (code
, operands
);
2856 /* Return nonzero if a branch/jump/call instruction will be emitting
2857 nop into its delay slot. */
2860 empty_delay_slot (rtx insn
)
2864 /* If no previous instruction (should not happen), return true. */
2865 if (PREV_INSN (insn
) == NULL
)
2868 seq
= NEXT_INSN (PREV_INSN (insn
));
2869 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2875 /* Return nonzero if TRIAL can go into the call delay slot. */
2878 tls_call_delay (rtx trial
)
2883 call __tls_get_addr, %tgd_call (foo)
2884 add %l7, %o0, %o0, %tgd_add (foo)
2885 while Sun as/ld does not. */
2886 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2889 pat
= PATTERN (trial
);
2891 /* We must reject tgd_add{32|64}, i.e.
2892 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2893 and tldm_add{32|64}, i.e.
2894 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2896 if (GET_CODE (pat
) == SET
2897 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2899 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2901 if (GET_CODE (unspec
) == UNSPEC
2902 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2903 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2910 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2911 instruction. RETURN_P is true if the v9 variant 'return' is to be
2912 considered in the test too.
2914 TRIAL must be a SET whose destination is a REG appropriate for the
2915 'restore' instruction or, if RETURN_P is true, for the 'return'
2919 eligible_for_restore_insn (rtx trial
, bool return_p
)
2921 rtx pat
= PATTERN (trial
);
2922 rtx src
= SET_SRC (pat
);
2924 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2925 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2926 && arith_operand (src
, GET_MODE (src
)))
2929 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2931 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2934 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2935 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2936 && arith_double_operand (src
, GET_MODE (src
)))
2937 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2939 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2940 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2943 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2944 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2947 /* If we have the 'return' instruction, anything that does not use
2948 local or output registers and can go into a delay slot wins. */
2951 && !epilogue_renumber (&pat
, 1)
2952 && get_attr_in_uncond_branch_delay (trial
)
2953 == IN_UNCOND_BRANCH_DELAY_TRUE
)
2956 /* The 'restore src1,src2,dest' pattern for SImode. */
2957 else if (GET_CODE (src
) == PLUS
2958 && register_operand (XEXP (src
, 0), SImode
)
2959 && arith_operand (XEXP (src
, 1), SImode
))
2962 /* The 'restore src1,src2,dest' pattern for DImode. */
2963 else if (GET_CODE (src
) == PLUS
2964 && register_operand (XEXP (src
, 0), DImode
)
2965 && arith_double_operand (XEXP (src
, 1), DImode
))
2968 /* The 'restore src1,%lo(src2),dest' pattern. */
2969 else if (GET_CODE (src
) == LO_SUM
2970 && ! TARGET_CM_MEDMID
2971 && ((register_operand (XEXP (src
, 0), SImode
)
2972 && immediate_operand (XEXP (src
, 1), SImode
))
2974 && register_operand (XEXP (src
, 0), DImode
)
2975 && immediate_operand (XEXP (src
, 1), DImode
))))
2978 /* The 'restore src,src,dest' pattern. */
2979 else if (GET_CODE (src
) == ASHIFT
2980 && (register_operand (XEXP (src
, 0), SImode
)
2981 || register_operand (XEXP (src
, 0), DImode
))
2982 && XEXP (src
, 1) == const1_rtx
)
2988 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2991 eligible_for_return_delay (rtx trial
)
2996 if (GET_CODE (trial
) != INSN
)
2999 if (get_attr_length (trial
) != 1)
3002 /* If the function uses __builtin_eh_return, the eh_return machinery
3003 occupies the delay slot. */
3004 if (crtl
->calls_eh_return
)
3007 /* In the case of a leaf or flat function, anything can go into the slot. */
3008 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3010 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
3012 pat
= PATTERN (trial
);
3013 if (GET_CODE (pat
) == PARALLEL
)
3019 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3021 rtx expr
= XVECEXP (pat
, 0, i
);
3022 if (GET_CODE (expr
) != SET
)
3024 if (GET_CODE (SET_DEST (expr
)) != REG
)
3026 regno
= REGNO (SET_DEST (expr
));
3027 if (regno
>= 8 && regno
< 24)
3030 return !epilogue_renumber (&pat
, 1)
3031 && (get_attr_in_uncond_branch_delay (trial
)
3032 == IN_UNCOND_BRANCH_DELAY_TRUE
);
3035 if (GET_CODE (pat
) != SET
)
3038 if (GET_CODE (SET_DEST (pat
)) != REG
)
3041 regno
= REGNO (SET_DEST (pat
));
3043 /* Otherwise, only operations which can be done in tandem with
3044 a `restore' or `return' insn can go into the delay slot. */
3045 if (regno
>= 8 && regno
< 24)
3048 /* If this instruction sets up floating point register and we have a return
3049 instruction, it can probably go in. But restore will not work
3053 && !epilogue_renumber (&pat
, 1)
3054 && get_attr_in_uncond_branch_delay (trial
)
3055 == IN_UNCOND_BRANCH_DELAY_TRUE
);
3057 return eligible_for_restore_insn (trial
, true);
3060 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3063 eligible_for_sibcall_delay (rtx trial
)
3067 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
3070 if (get_attr_length (trial
) != 1)
3073 pat
= PATTERN (trial
);
3075 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3077 /* If the tail call is done using the call instruction,
3078 we have to restore %o7 in the delay slot. */
3079 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3082 /* %g1 is used to build the function address */
3083 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3089 /* Otherwise, only operations which can be done in tandem with
3090 a `restore' insn can go into the delay slot. */
3091 if (GET_CODE (SET_DEST (pat
)) != REG
3092 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3093 || REGNO (SET_DEST (pat
)) >= 32)
3096 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3098 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3101 return eligible_for_restore_insn (trial
, false);
3105 short_branch (int uid1
, int uid2
)
3107 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
3109 /* Leave a few words of "slop". */
3110 if (delta
>= -1023 && delta
<= 1022)
3116 /* Return nonzero if REG is not used after INSN.
3117 We assume REG is a reload reg, and therefore does
3118 not live past labels or calls or jumps. */
3120 reg_unused_after (rtx reg
, rtx insn
)
3122 enum rtx_code code
, prev_code
= UNKNOWN
;
3124 while ((insn
= NEXT_INSN (insn
)))
3126 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3129 code
= GET_CODE (insn
);
3130 if (GET_CODE (insn
) == CODE_LABEL
)
3135 rtx set
= single_set (insn
);
3136 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3139 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3141 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3149 /* Determine if it's legal to put X into the constant pool. This
3150 is not possible if X contains the address of a symbol that is
3151 not constant (TLS) or not known at final link time (PIC). */
3154 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
3156 switch (GET_CODE (x
))
3161 /* Accept all non-symbolic constants. */
3165 /* Labels are OK iff we are non-PIC. */
3166 return flag_pic
!= 0;
3169 /* 'Naked' TLS symbol references are never OK,
3170 non-TLS symbols are OK iff we are non-PIC. */
3171 if (SYMBOL_REF_TLS_MODEL (x
))
3174 return flag_pic
!= 0;
3177 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3180 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3181 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3189 /* Global Offset Table support. */
3190 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3191 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3193 /* Return the SYMBOL_REF for the Global Offset Table. */
3195 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3200 if (!sparc_got_symbol
)
3201 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3203 return sparc_got_symbol
;
3206 /* Ensure that we are not using patterns that are not OK with PIC. */
3216 op
= recog_data
.operand
[i
];
3217 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3218 && (GET_CODE (op
) != CONST
3219 || (GET_CODE (XEXP (op
, 0)) == MINUS
3220 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3221 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3228 /* Return true if X is an address which needs a temporary register when
3229 reloaded while generating PIC code. */
3232 pic_address_needs_scratch (rtx x
)
3234 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3235 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3236 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3237 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3238 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3244 /* Determine if a given RTX is a valid constant. We already know this
3245 satisfies CONSTANT_P. */
3248 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3250 switch (GET_CODE (x
))
3254 if (sparc_tls_referenced_p (x
))
3259 if (GET_MODE (x
) == VOIDmode
)
3262 /* Floating point constants are generally not ok.
3263 The only exception is 0.0 and all-ones in VIS. */
3265 && SCALAR_FLOAT_MODE_P (mode
)
3266 && (const_zero_operand (x
, mode
)
3267 || const_all_ones_operand (x
, mode
)))
3273 /* Vector constants are generally not ok.
3274 The only exception is 0 or -1 in VIS. */
3276 && (const_zero_operand (x
, mode
)
3277 || const_all_ones_operand (x
, mode
)))
3289 /* Determine if a given RTX is a valid constant address. */
3292 constant_address_p (rtx x
)
3294 switch (GET_CODE (x
))
3302 if (flag_pic
&& pic_address_needs_scratch (x
))
3304 return sparc_legitimate_constant_p (Pmode
, x
);
3307 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3314 /* Nonzero if the constant value X is a legitimate general operand
3315 when generating PIC code. It is given that flag_pic is on and
3316 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3319 legitimate_pic_operand_p (rtx x
)
3321 if (pic_address_needs_scratch (x
))
3323 if (sparc_tls_referenced_p (x
))
3328 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3330 && INTVAL (X) >= -0x1000 \
3331 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3333 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3335 && INTVAL (X) >= -0x1000 \
3336 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3338 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3340 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3341 ordinarily. This changes a bit when generating PIC. */
3344 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3346 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3348 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3350 else if (GET_CODE (addr
) == PLUS
)
3352 rs1
= XEXP (addr
, 0);
3353 rs2
= XEXP (addr
, 1);
3355 /* Canonicalize. REG comes first, if there are no regs,
3356 LO_SUM comes first. */
3358 && GET_CODE (rs1
) != SUBREG
3360 || GET_CODE (rs2
) == SUBREG
3361 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3363 rs1
= XEXP (addr
, 1);
3364 rs2
= XEXP (addr
, 0);
3368 && rs1
== pic_offset_table_rtx
3370 && GET_CODE (rs2
) != SUBREG
3371 && GET_CODE (rs2
) != LO_SUM
3372 && GET_CODE (rs2
) != MEM
3373 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3374 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3375 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3377 || GET_CODE (rs1
) == SUBREG
)
3378 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3383 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3384 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3386 /* We prohibit REG + REG for TFmode when there are no quad move insns
3387 and we consequently need to split. We do this because REG+REG
3388 is not an offsettable address. If we get the situation in reload
3389 where source and destination of a movtf pattern are both MEMs with
3390 REG+REG address, then only one of them gets converted to an
3391 offsettable address. */
3393 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3396 /* We prohibit REG + REG on ARCH32 if not optimizing for
3397 DFmode/DImode because then mem_min_alignment is likely to be zero
3398 after reload and the forced split would lack a matching splitter
3400 if (TARGET_ARCH32
&& !optimize
3401 && (mode
== DFmode
|| mode
== DImode
))
3404 else if (USE_AS_OFFSETABLE_LO10
3405 && GET_CODE (rs1
) == LO_SUM
3407 && ! TARGET_CM_MEDMID
3408 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3411 imm1
= XEXP (rs1
, 1);
3412 rs1
= XEXP (rs1
, 0);
3413 if (!CONSTANT_P (imm1
)
3414 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3418 else if (GET_CODE (addr
) == LO_SUM
)
3420 rs1
= XEXP (addr
, 0);
3421 imm1
= XEXP (addr
, 1);
3423 if (!CONSTANT_P (imm1
)
3424 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3427 /* We can't allow TFmode in 32-bit mode, because an offset greater
3428 than the alignment (8) may cause the LO_SUM to overflow. */
3429 if (mode
== TFmode
&& TARGET_ARCH32
)
3432 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3437 if (GET_CODE (rs1
) == SUBREG
)
3438 rs1
= SUBREG_REG (rs1
);
3444 if (GET_CODE (rs2
) == SUBREG
)
3445 rs2
= SUBREG_REG (rs2
);
3452 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3453 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3458 if ((REGNO (rs1
) >= 32
3459 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3460 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3462 && (REGNO (rs2
) >= 32
3463 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3464 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3470 /* Return the SYMBOL_REF for the tls_get_addr function. */
3472 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3475 sparc_tls_get_addr (void)
3477 if (!sparc_tls_symbol
)
3478 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3480 return sparc_tls_symbol
;
3483 /* Return the Global Offset Table to be used in TLS mode. */
3486 sparc_tls_got (void)
3488 /* In PIC mode, this is just the PIC offset table. */
3491 crtl
->uses_pic_offset_table
= 1;
3492 return pic_offset_table_rtx
;
3495 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3496 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3497 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3499 load_got_register ();
3500 return global_offset_table_rtx
;
3503 /* In all other cases, we load a new pseudo with the GOT symbol. */
3504 return copy_to_reg (sparc_got ());
3507 /* Return true if X contains a thread-local symbol. */
3510 sparc_tls_referenced_p (rtx x
)
3512 if (!TARGET_HAVE_TLS
)
3515 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3516 x
= XEXP (XEXP (x
, 0), 0);
3518 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3521 /* That's all we handle in sparc_legitimize_tls_address for now. */
3525 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3526 this (thread-local) address. */
3529 sparc_legitimize_tls_address (rtx addr
)
3531 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3533 gcc_assert (can_create_pseudo_p ());
3535 if (GET_CODE (addr
) == SYMBOL_REF
)
3536 switch (SYMBOL_REF_TLS_MODEL (addr
))
3538 case TLS_MODEL_GLOBAL_DYNAMIC
:
3540 temp1
= gen_reg_rtx (SImode
);
3541 temp2
= gen_reg_rtx (SImode
);
3542 ret
= gen_reg_rtx (Pmode
);
3543 o0
= gen_rtx_REG (Pmode
, 8);
3544 got
= sparc_tls_got ();
3545 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3546 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3549 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3550 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3555 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3556 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3559 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3560 insn
= get_insns ();
3562 emit_libcall_block (insn
, ret
, o0
, addr
);
3565 case TLS_MODEL_LOCAL_DYNAMIC
:
3567 temp1
= gen_reg_rtx (SImode
);
3568 temp2
= gen_reg_rtx (SImode
);
3569 temp3
= gen_reg_rtx (Pmode
);
3570 ret
= gen_reg_rtx (Pmode
);
3571 o0
= gen_rtx_REG (Pmode
, 8);
3572 got
= sparc_tls_got ();
3573 emit_insn (gen_tldm_hi22 (temp1
));
3574 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3577 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3578 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3583 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3584 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3587 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3588 insn
= get_insns ();
3590 emit_libcall_block (insn
, temp3
, o0
,
3591 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3592 UNSPEC_TLSLD_BASE
));
3593 temp1
= gen_reg_rtx (SImode
);
3594 temp2
= gen_reg_rtx (SImode
);
3595 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3596 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3598 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3600 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3603 case TLS_MODEL_INITIAL_EXEC
:
3604 temp1
= gen_reg_rtx (SImode
);
3605 temp2
= gen_reg_rtx (SImode
);
3606 temp3
= gen_reg_rtx (Pmode
);
3607 got
= sparc_tls_got ();
3608 emit_insn (gen_tie_hi22 (temp1
, addr
));
3609 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3611 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3613 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3616 ret
= gen_reg_rtx (Pmode
);
3618 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3621 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3625 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3628 case TLS_MODEL_LOCAL_EXEC
:
3629 temp1
= gen_reg_rtx (Pmode
);
3630 temp2
= gen_reg_rtx (Pmode
);
3633 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3634 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3638 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3639 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3641 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3648 else if (GET_CODE (addr
) == CONST
)
3652 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3654 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3655 offset
= XEXP (XEXP (addr
, 0), 1);
3657 base
= force_operand (base
, NULL_RTX
);
3658 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3659 offset
= force_reg (Pmode
, offset
);
3660 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3664 gcc_unreachable (); /* for now ... */
3669 /* Legitimize PIC addresses. If the address is already position-independent,
3670 we return ORIG. Newly generated position-independent addresses go into a
3671 reg. This is REG if nonzero, otherwise we allocate register(s) as
3675 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3677 bool gotdata_op
= false;
3679 if (GET_CODE (orig
) == SYMBOL_REF
3680 /* See the comment in sparc_expand_move. */
3681 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3683 rtx pic_ref
, address
;
3688 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3689 reg
= gen_reg_rtx (Pmode
);
3694 /* If not during reload, allocate another temp reg here for loading
3695 in the address, so that these instructions can be optimized
3697 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3698 ? reg
: gen_reg_rtx (Pmode
));
3700 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3701 won't get confused into thinking that these two instructions
3702 are loading in the true address of the symbol. If in the
3703 future a PIC rtx exists, that should be used instead. */
3706 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3707 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3711 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3712 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3720 crtl
->uses_pic_offset_table
= 1;
3724 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3725 pic_offset_table_rtx
,
3728 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3729 pic_offset_table_rtx
,
3735 = gen_const_mem (Pmode
,
3736 gen_rtx_PLUS (Pmode
,
3737 pic_offset_table_rtx
, address
));
3738 insn
= emit_move_insn (reg
, pic_ref
);
3741 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3743 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3746 else if (GET_CODE (orig
) == CONST
)
3750 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3751 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3756 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3757 reg
= gen_reg_rtx (Pmode
);
3760 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3761 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3762 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3763 base
== reg
? NULL_RTX
: reg
);
3765 if (GET_CODE (offset
) == CONST_INT
)
3767 if (SMALL_INT (offset
))
3768 return plus_constant (base
, INTVAL (offset
));
3769 else if (! reload_in_progress
&& ! reload_completed
)
3770 offset
= force_reg (Pmode
, offset
);
3772 /* If we reach here, then something is seriously wrong. */
3775 return gen_rtx_PLUS (Pmode
, base
, offset
);
3777 else if (GET_CODE (orig
) == LABEL_REF
)
3778 /* ??? We ought to be checking that the register is live instead, in case
3779 it is eliminated. */
3780 crtl
->uses_pic_offset_table
= 1;
3785 /* Try machine-dependent ways of modifying an illegitimate address X
3786 to be legitimate. If we find one, return the new, valid address.
3788 OLDX is the address as it was before break_out_memory_refs was called.
3789 In some cases it is useful to look at this to decide what needs to be done.
3791 MODE is the mode of the operand pointed to by X.
3793 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3796 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3797 enum machine_mode mode
)
3801 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3802 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3803 force_operand (XEXP (x
, 0), NULL_RTX
));
3804 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3805 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3806 force_operand (XEXP (x
, 1), NULL_RTX
));
3807 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3808 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3810 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3811 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3812 force_operand (XEXP (x
, 1), NULL_RTX
));
3814 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3817 if (sparc_tls_referenced_p (x
))
3818 x
= sparc_legitimize_tls_address (x
);
3820 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
3821 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3822 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3823 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3824 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3825 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3826 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3827 else if (GET_CODE (x
) == SYMBOL_REF
3828 || GET_CODE (x
) == CONST
3829 || GET_CODE (x
) == LABEL_REF
)
3830 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3835 /* Delegitimize an address that was legitimized by the above function. */
3838 sparc_delegitimize_address (rtx x
)
3840 x
= delegitimize_mem_from_attrs (x
);
3842 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
3843 switch (XINT (XEXP (x
, 1), 1))
3845 case UNSPEC_MOVE_PIC
:
3847 x
= XVECEXP (XEXP (x
, 1), 0, 0);
3848 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3854 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3855 if (GET_CODE (x
) == MINUS
3856 && REG_P (XEXP (x
, 0))
3857 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
3858 && GET_CODE (XEXP (x
, 1)) == LO_SUM
3859 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
3860 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
3862 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
3863 gcc_assert (GET_CODE (x
) == LABEL_REF
);
3869 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3870 replace the input X, or the original X if no replacement is called for.
3871 The output parameter *WIN is 1 if the calling macro should goto WIN,
3874 For SPARC, we wish to handle addresses by splitting them into
3875 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3876 This cuts the number of extra insns by one.
3878 Do nothing when generating PIC code and the address is a symbolic
3879 operand or requires a scratch register. */
3882 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3883 int opnum
, int type
,
3884 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3886 /* Decompose SImode constants into HIGH+LO_SUM. */
3888 && (mode
!= TFmode
|| TARGET_ARCH64
)
3889 && GET_MODE (x
) == SImode
3890 && GET_CODE (x
) != LO_SUM
3891 && GET_CODE (x
) != HIGH
3892 && sparc_cmodel
<= CM_MEDLOW
3894 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
3896 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
3897 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3898 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3899 opnum
, (enum reload_type
)type
);
3904 /* We have to recognize what we have already generated above. */
3905 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
3907 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3908 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3909 opnum
, (enum reload_type
)type
);
3918 /* Return true if ADDR (a legitimate address expression)
3919 has an effect that depends on the machine mode it is used for.
3925 is not equivalent to
3927 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3929 because [%l7+a+1] is interpreted as the address of (a+1). */
3933 sparc_mode_dependent_address_p (const_rtx addr
)
3935 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
3937 rtx op0
= XEXP (addr
, 0);
3938 rtx op1
= XEXP (addr
, 1);
3939 if (op0
== pic_offset_table_rtx
3940 && symbolic_operand (op1
, VOIDmode
))
3947 #ifdef HAVE_GAS_HIDDEN
3948 # define USE_HIDDEN_LINKONCE 1
3950 # define USE_HIDDEN_LINKONCE 0
3954 get_pc_thunk_name (char name
[32], unsigned int regno
)
3956 const char *reg_name
= reg_names
[regno
];
3958 /* Skip the leading '%' as that cannot be used in a
3962 if (USE_HIDDEN_LINKONCE
)
3963 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
3965 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3968 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3971 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
3973 int orig_flag_pic
= flag_pic
;
3976 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3979 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
3981 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
3982 flag_pic
= orig_flag_pic
;
3987 /* Emit code to load the GOT register. */
3990 load_got_register (void)
3992 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3993 if (!global_offset_table_rtx
)
3994 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
3996 if (TARGET_VXWORKS_RTP
)
3997 emit_insn (gen_vxworks_load_got ());
4000 /* The GOT symbol is subject to a PC-relative relocation so we need a
4001 helper function to add the PC value and thus get the final value. */
4002 if (!got_helper_rtx
)
4005 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4006 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4009 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4011 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4014 /* Need to emit this whether or not we obey regdecls,
4015 since setjmp/longjmp can cause life info to screw up.
4016 ??? In the case where we don't obey regdecls, this is not sufficient
4017 since we may not fall out the bottom. */
4018 emit_use (global_offset_table_rtx
);
4021 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4022 address of the call target. */
4025 sparc_emit_call_insn (rtx pat
, rtx addr
)
4029 insn
= emit_call_insn (pat
);
4031 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4032 if (TARGET_VXWORKS_RTP
4034 && GET_CODE (addr
) == SYMBOL_REF
4035 && (SYMBOL_REF_DECL (addr
)
4036 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4037 : !SYMBOL_REF_LOCAL_P (addr
)))
4039 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4040 crtl
->uses_pic_offset_table
= 1;
4044 /* Return 1 if RTX is a MEM which is known to be aligned to at
4045 least a DESIRED byte boundary. */
4048 mem_min_alignment (rtx mem
, int desired
)
4050 rtx addr
, base
, offset
;
4052 /* If it's not a MEM we can't accept it. */
4053 if (GET_CODE (mem
) != MEM
)
4057 if (!TARGET_UNALIGNED_DOUBLES
4058 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4061 /* ??? The rest of the function predates MEM_ALIGN so
4062 there is probably a bit of redundancy. */
4063 addr
= XEXP (mem
, 0);
4064 base
= offset
= NULL_RTX
;
4065 if (GET_CODE (addr
) == PLUS
)
4067 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4069 base
= XEXP (addr
, 0);
4071 /* What we are saying here is that if the base
4072 REG is aligned properly, the compiler will make
4073 sure any REG based index upon it will be so
4075 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4076 offset
= XEXP (addr
, 1);
4078 offset
= const0_rtx
;
4081 else if (GET_CODE (addr
) == REG
)
4084 offset
= const0_rtx
;
4087 if (base
!= NULL_RTX
)
4089 int regno
= REGNO (base
);
4091 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4093 /* Check if the compiler has recorded some information
4094 about the alignment of the base REG. If reload has
4095 completed, we already matched with proper alignments.
4096 If not running global_alloc, reload might give us
4097 unaligned pointer to local stack though. */
4099 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4100 || (optimize
&& reload_completed
))
4101 && (INTVAL (offset
) & (desired
- 1)) == 0)
4106 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4110 else if (! TARGET_UNALIGNED_DOUBLES
4111 || CONSTANT_P (addr
)
4112 || GET_CODE (addr
) == LO_SUM
)
4114 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4115 is true, in which case we can only assume that an access is aligned if
4116 it is to a constant address, or the address involves a LO_SUM. */
4120 /* An obviously unaligned address. */
4125 /* Vectors to keep interesting information about registers where it can easily
4126 be got. We used to use the actual mode value as the bit number, but there
4127 are more than 32 modes now. Instead we use two tables: one indexed by
4128 hard register number, and one indexed by mode. */
4130 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4131 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4132 mapped into one sparc_mode_class mode. */
4134 enum sparc_mode_class
{
4135 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4136 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4140 /* Modes for single-word and smaller quantities. */
4141 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4143 /* Modes for double-word and smaller quantities. */
4144 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4146 /* Modes for quad-word and smaller quantities. */
4147 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4149 /* Modes for 8-word and smaller quantities. */
4150 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4152 /* Modes for single-float quantities. We must allow any single word or
4153 smaller quantity. This is because the fix/float conversion instructions
4154 take integer inputs/outputs from the float registers. */
4155 #define SF_MODES (S_MODES)
4157 /* Modes for double-float and smaller quantities. */
4158 #define DF_MODES (D_MODES)
4160 /* Modes for quad-float and smaller quantities. */
4161 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4163 /* Modes for quad-float pairs and smaller quantities. */
4164 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4166 /* Modes for double-float only quantities. */
4167 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4169 /* Modes for quad-float and double-float only quantities. */
4170 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4172 /* Modes for quad-float pairs and double-float only quantities. */
4173 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4175 /* Modes for condition codes. */
4176 #define CC_MODES (1 << (int) CC_MODE)
4177 #define CCFP_MODES (1 << (int) CCFP_MODE)
4179 /* Value is 1 if register/mode pair is acceptable on sparc.
4180 The funny mixture of D and T modes is because integer operations
4181 do not specially operate on tetra quantities, so non-quad-aligned
4182 registers can hold quadword quantities (except %o4 and %i4 because
4183 they cross fixed registers). */
4185 /* This points to either the 32 bit or the 64 bit version. */
4186 const int *hard_regno_mode_classes
;
4188 static const int hard_32bit_mode_classes
[] = {
4189 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4190 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4191 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4192 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4194 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4195 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4196 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4197 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4199 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4200 and none can hold SFmode/SImode values. */
4201 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4202 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4203 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4204 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4207 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4209 /* %icc, %sfp, %gsr */
4210 CC_MODES
, 0, D_MODES
4213 static const int hard_64bit_mode_classes
[] = {
4214 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4215 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4216 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4217 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4219 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4220 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4221 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4222 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4224 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4225 and none can hold SFmode/SImode values. */
4226 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4227 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4228 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4229 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4232 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4234 /* %icc, %sfp, %gsr */
4235 CC_MODES
, 0, D_MODES
4238 int sparc_mode_class
[NUM_MACHINE_MODES
];
4240 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4243 sparc_init_modes (void)
4247 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4249 switch (GET_MODE_CLASS (i
))
4252 case MODE_PARTIAL_INT
:
4253 case MODE_COMPLEX_INT
:
4254 if (GET_MODE_SIZE (i
) <= 4)
4255 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4256 else if (GET_MODE_SIZE (i
) == 8)
4257 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4258 else if (GET_MODE_SIZE (i
) == 16)
4259 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4260 else if (GET_MODE_SIZE (i
) == 32)
4261 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4263 sparc_mode_class
[i
] = 0;
4265 case MODE_VECTOR_INT
:
4266 if (GET_MODE_SIZE (i
) <= 4)
4267 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4268 else if (GET_MODE_SIZE (i
) == 8)
4269 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4272 case MODE_COMPLEX_FLOAT
:
4273 if (GET_MODE_SIZE (i
) <= 4)
4274 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4275 else if (GET_MODE_SIZE (i
) == 8)
4276 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4277 else if (GET_MODE_SIZE (i
) == 16)
4278 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4279 else if (GET_MODE_SIZE (i
) == 32)
4280 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4282 sparc_mode_class
[i
] = 0;
4285 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4286 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4288 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4291 sparc_mode_class
[i
] = 0;
4297 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4299 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4301 /* Initialize the array used by REGNO_REG_CLASS. */
4302 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4304 if (i
< 16 && TARGET_V8PLUS
)
4305 sparc_regno_reg_class
[i
] = I64_REGS
;
4306 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4307 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4309 sparc_regno_reg_class
[i
] = FP_REGS
;
4311 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4313 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4315 sparc_regno_reg_class
[i
] = NO_REGS
;
4319 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4322 save_global_or_fp_reg_p (unsigned int regno
,
4323 int leaf_function ATTRIBUTE_UNUSED
)
4325 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4328 /* Return whether the return address register (%i7) is needed. */
4331 return_addr_reg_needed_p (int leaf_function
)
4333 /* If it is live, for example because of __builtin_return_address (0). */
4334 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4337 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4339 /* Loading the GOT register clobbers %o7. */
4340 || crtl
->uses_pic_offset_table
4341 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4347 /* Return whether REGNO, a local or in register, must be saved/restored. */
4350 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4352 /* General case: call-saved registers live at some point. */
4353 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4356 /* Frame pointer register (%fp) if needed. */
4357 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4360 /* Return address register (%i7) if needed. */
4361 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4364 /* GOT register (%l7) if needed. */
4365 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4368 /* If the function accesses prior frames, the frame pointer and the return
4369 address of the previous frame must be saved on the stack. */
4370 if (crtl
->accesses_prior_frames
4371 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4377 /* Compute the frame size required by the function. This function is called
4378 during the reload pass and also by sparc_expand_prologue. */
4381 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4383 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4384 int args_size
, n_global_fp_regs
= 0;
4385 bool save_local_in_regs_p
= false;
4388 /* If the function allocates dynamic stack space, the dynamic offset is
4389 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4390 if (leaf_function
&& !cfun
->calls_alloca
)
4393 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4395 /* Calculate space needed for global registers. */
4397 for (i
= 0; i
< 8; i
++)
4398 if (save_global_or_fp_reg_p (i
, 0))
4399 n_global_fp_regs
+= 2;
4401 for (i
= 0; i
< 8; i
+= 2)
4402 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4403 n_global_fp_regs
+= 2;
4405 /* In the flat window model, find out which local and in registers need to
4406 be saved. We don't reserve space in the current frame for them as they
4407 will be spilled into the register window save area of the caller's frame.
4408 However, as soon as we use this register window save area, we must create
4409 that of the current frame to make it the live one. */
4411 for (i
= 16; i
< 32; i
++)
4412 if (save_local_or_in_reg_p (i
, leaf_function
))
4414 save_local_in_regs_p
= true;
4418 /* Calculate space needed for FP registers. */
4419 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4420 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4421 n_global_fp_regs
+= 2;
4424 && n_global_fp_regs
== 0
4426 && !save_local_in_regs_p
)
4427 frame_size
= apparent_frame_size
= 0;
4430 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4431 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4432 apparent_frame_size
+= n_global_fp_regs
* 4;
4434 /* We need to add the size of the outgoing argument area. */
4435 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4437 /* And that of the register window save area. */
4438 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4440 /* Finally, bump to the appropriate alignment. */
4441 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4444 /* Set up values for use in prologue and epilogue. */
4445 sparc_frame_size
= frame_size
;
4446 sparc_apparent_frame_size
= apparent_frame_size
;
4447 sparc_n_global_fp_regs
= n_global_fp_regs
;
4448 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4453 /* Output any necessary .register pseudo-ops. */
4456 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4458 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4464 /* Check if %g[2367] were used without
4465 .register being printed for them already. */
4466 for (i
= 2; i
< 8; i
++)
4468 if (df_regs_ever_live_p (i
)
4469 && ! sparc_hard_reg_printed
[i
])
4471 sparc_hard_reg_printed
[i
] = 1;
4472 /* %g7 is used as TLS base register, use #ignore
4473 for it instead of #scratch. */
4474 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4475 i
== 7 ? "ignore" : "scratch");
4482 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4484 #if PROBE_INTERVAL > 4096
4485 #error Cannot use indexed addressing mode for stack probing
4488 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4489 inclusive. These are offsets from the current stack pointer.
4491 Note that we don't use the REG+REG addressing mode for the probes because
4492 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4493 so the advantages of having a single code win here. */
4496 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4498 rtx g1
= gen_rtx_REG (Pmode
, 1);
4500 /* See if we have a constant small number of probes to generate. If so,
4501 that's the easy case. */
4502 if (size
<= PROBE_INTERVAL
)
4504 emit_move_insn (g1
, GEN_INT (first
));
4505 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4506 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4507 emit_stack_probe (plus_constant (g1
, -size
));
4510 /* The run-time loop is made up of 10 insns in the generic case while the
4511 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4512 else if (size
<= 5 * PROBE_INTERVAL
)
4516 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4517 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4518 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4519 emit_stack_probe (g1
);
4521 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4522 it exceeds SIZE. If only two probes are needed, this will not
4523 generate any code. Then probe at FIRST + SIZE. */
4524 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4526 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4527 plus_constant (g1
, -PROBE_INTERVAL
)));
4528 emit_stack_probe (g1
);
4531 emit_stack_probe (plus_constant (g1
, (i
- PROBE_INTERVAL
) - size
));
4534 /* Otherwise, do the same as above, but in a loop. Note that we must be
4535 extra careful with variables wrapping around because we might be at
4536 the very top (or the very bottom) of the address space and we have
4537 to be able to handle this case properly; in particular, we use an
4538 equality test for the loop condition. */
4541 HOST_WIDE_INT rounded_size
;
4542 rtx g4
= gen_rtx_REG (Pmode
, 4);
4544 emit_move_insn (g1
, GEN_INT (first
));
4547 /* Step 1: round SIZE to the previous multiple of the interval. */
4549 rounded_size
= size
& -PROBE_INTERVAL
;
4550 emit_move_insn (g4
, GEN_INT (rounded_size
));
4553 /* Step 2: compute initial and final value of the loop counter. */
4555 /* TEST_ADDR = SP + FIRST. */
4556 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4557 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4559 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4560 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4565 while (TEST_ADDR != LAST_ADDR)
4567 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4571 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4572 until it is equal to ROUNDED_SIZE. */
4575 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4577 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4580 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4581 that SIZE is equal to ROUNDED_SIZE. */
4583 if (size
!= rounded_size
)
4584 emit_stack_probe (plus_constant (g4
, rounded_size
- size
));
4587 /* Make sure nothing is scheduled before we are done. */
4588 emit_insn (gen_blockage ());
4591 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4592 absolute addresses. */
4595 output_probe_stack_range (rtx reg1
, rtx reg2
)
4597 static int labelno
= 0;
4598 char loop_lab
[32], end_lab
[32];
4601 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4602 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4604 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4606 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4609 output_asm_insn ("cmp\t%0, %1", xops
);
4611 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4613 fputs ("\tbe\t", asm_out_file
);
4614 assemble_name_raw (asm_out_file
, end_lab
);
4615 fputc ('\n', asm_out_file
);
4617 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4618 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4619 output_asm_insn (" add\t%0, %1, %0", xops
);
4621 /* Probe at TEST_ADDR and branch. */
4623 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4625 fputs ("\tba\t", asm_out_file
);
4626 assemble_name_raw (asm_out_file
, loop_lab
);
4627 fputc ('\n', asm_out_file
);
4628 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4629 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4631 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4636 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4637 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4638 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4639 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4640 the action to be performed if it returns false. Return the new offset. */
4642 typedef bool (*sorr_pred_t
) (unsigned int, int);
4643 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4646 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4647 int offset
, int leaf_function
, sorr_pred_t save_p
,
4648 sorr_act_t action_true
, sorr_act_t action_false
)
4653 if (TARGET_ARCH64
&& high
<= 32)
4657 for (i
= low
; i
< high
; i
++)
4659 if (save_p (i
, leaf_function
))
4661 mem
= gen_frame_mem (DImode
, plus_constant (base
, offset
));
4662 if (action_true
== SORR_SAVE
)
4664 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4665 RTX_FRAME_RELATED_P (insn
) = 1;
4667 else /* action_true == SORR_RESTORE */
4669 /* The frame pointer must be restored last since its old
4670 value may be used as base address for the frame. This
4671 is problematic in 64-bit mode only because of the lack
4672 of double-word load instruction. */
4673 if (i
== HARD_FRAME_POINTER_REGNUM
)
4676 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4680 else if (action_false
== SORR_ADVANCE
)
4686 mem
= gen_frame_mem (DImode
, plus_constant (base
, fp_offset
));
4687 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4692 for (i
= low
; i
< high
; i
+= 2)
4694 bool reg0
= save_p (i
, leaf_function
);
4695 bool reg1
= save_p (i
+ 1, leaf_function
);
4696 enum machine_mode mode
;
4701 mode
= i
< 32 ? DImode
: DFmode
;
4706 mode
= i
< 32 ? SImode
: SFmode
;
4711 mode
= i
< 32 ? SImode
: SFmode
;
4717 if (action_false
== SORR_ADVANCE
)
4722 mem
= gen_frame_mem (mode
, plus_constant (base
, offset
));
4723 if (action_true
== SORR_SAVE
)
4725 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4726 RTX_FRAME_RELATED_P (insn
) = 1;
4730 mem
= gen_frame_mem (SImode
, plus_constant (base
, offset
));
4731 set1
= gen_rtx_SET (VOIDmode
, mem
,
4732 gen_rtx_REG (SImode
, regno
));
4733 RTX_FRAME_RELATED_P (set1
) = 1;
4735 = gen_frame_mem (SImode
, plus_constant (base
, offset
+ 4));
4736 set2
= gen_rtx_SET (VOIDmode
, mem
,
4737 gen_rtx_REG (SImode
, regno
+ 1));
4738 RTX_FRAME_RELATED_P (set2
) = 1;
4739 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4740 gen_rtx_PARALLEL (VOIDmode
,
4741 gen_rtvec (2, set1
, set2
)));
4744 else /* action_true == SORR_RESTORE */
4745 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4747 /* Always preserve double-word alignment. */
4748 offset
= (offset
+ 8) & -8;
4755 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4758 emit_adjust_base_to_offset (rtx base
, int offset
)
4760 /* ??? This might be optimized a little as %g1 might already have a
4761 value close enough that a single add insn will do. */
4762 /* ??? Although, all of this is probably only a temporary fix because
4763 if %g1 can hold a function result, then sparc_expand_epilogue will
4764 lose (the result will be clobbered). */
4765 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4766 emit_move_insn (new_base
, GEN_INT (offset
));
4767 emit_insn (gen_rtx_SET (VOIDmode
,
4768 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4772 /* Emit code to save/restore call-saved global and FP registers. */
4775 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4777 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4779 base
= emit_adjust_base_to_offset (base
, offset
);
4784 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4785 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4786 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4787 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4790 /* Emit code to save/restore call-saved local and in registers. */
4793 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
4795 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
4797 base
= emit_adjust_base_to_offset (base
, offset
);
4801 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
4802 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
4805 /* Emit a window_save insn. */
4808 emit_window_save (rtx increment
)
4810 rtx insn
= emit_insn (gen_window_save (increment
));
4811 RTX_FRAME_RELATED_P (insn
) = 1;
4813 /* The incoming return address (%o7) is saved in %i7. */
4814 add_reg_note (insn
, REG_CFA_REGISTER
,
4815 gen_rtx_SET (VOIDmode
,
4816 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
4818 INCOMING_RETURN_ADDR_REGNUM
)));
4820 /* The window save event. */
4821 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
4823 /* The CFA is %fp, the hard frame pointer. */
4824 add_reg_note (insn
, REG_CFA_DEF_CFA
,
4825 plus_constant (hard_frame_pointer_rtx
,
4826 INCOMING_FRAME_SP_OFFSET
));
4831 /* Generate an increment for the stack pointer. */
4834 gen_stack_pointer_inc (rtx increment
)
4836 return gen_rtx_SET (VOIDmode
,
4838 gen_rtx_PLUS (Pmode
,
4843 /* Generate a decrement for the stack pointer. */
4846 gen_stack_pointer_dec (rtx decrement
)
4848 return gen_rtx_SET (VOIDmode
,
4850 gen_rtx_MINUS (Pmode
,
4855 /* Expand the function prologue. The prologue is responsible for reserving
4856 storage for the frame, saving the call-saved registers and loading the
4857 GOT register if needed. */
4860 sparc_expand_prologue (void)
4865 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4866 on the final value of the flag means deferring the prologue/epilogue
4867 expansion until just before the second scheduling pass, which is too
4868 late to emit multiple epilogues or return insns.
4870 Of course we are making the assumption that the value of the flag
4871 will not change between now and its final value. Of the three parts
4872 of the formula, only the last one can reasonably vary. Let's take a
4873 closer look, after assuming that the first two ones are set to true
4874 (otherwise the last value is effectively silenced).
4876 If only_leaf_regs_used returns false, the global predicate will also
4877 be false so the actual frame size calculated below will be positive.
4878 As a consequence, the save_register_window insn will be emitted in
4879 the instruction stream; now this insn explicitly references %fp
4880 which is not a leaf register so only_leaf_regs_used will always
4881 return false subsequently.
4883 If only_leaf_regs_used returns true, we hope that the subsequent
4884 optimization passes won't cause non-leaf registers to pop up. For
4885 example, the regrename pass has special provisions to not rename to
4886 non-leaf registers in a leaf function. */
4887 sparc_leaf_function_p
4888 = optimize
> 0 && current_function_is_leaf
&& only_leaf_regs_used ();
4890 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4892 if (flag_stack_usage_info
)
4893 current_function_static_stack_size
= size
;
4895 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4896 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4900 else if (sparc_leaf_function_p
)
4902 rtx size_int_rtx
= GEN_INT (-size
);
4905 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4906 else if (size
<= 8192)
4908 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4909 /* %sp is still the CFA register. */
4910 RTX_FRAME_RELATED_P (insn
) = 1;
4911 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4915 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4916 emit_move_insn (size_rtx
, size_int_rtx
);
4917 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4918 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4919 gen_stack_pointer_inc (size_int_rtx
));
4922 RTX_FRAME_RELATED_P (insn
) = 1;
4926 rtx size_int_rtx
= GEN_INT (-size
);
4929 emit_window_save (size_int_rtx
);
4930 else if (size
<= 8192)
4932 emit_window_save (GEN_INT (-4096));
4933 /* %sp is not the CFA register anymore. */
4934 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4938 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4939 emit_move_insn (size_rtx
, size_int_rtx
);
4940 emit_window_save (size_rtx
);
4944 if (sparc_leaf_function_p
)
4946 sparc_frame_base_reg
= stack_pointer_rtx
;
4947 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4951 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4952 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4955 if (sparc_n_global_fp_regs
> 0)
4956 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4957 sparc_frame_base_offset
4958 - sparc_apparent_frame_size
,
4961 /* Load the GOT register if needed. */
4962 if (crtl
->uses_pic_offset_table
)
4963 load_got_register ();
4965 /* Advertise that the data calculated just above are now valid. */
4966 sparc_prologue_data_valid_p
= true;
4969 /* Expand the function prologue. The prologue is responsible for reserving
4970 storage for the frame, saving the call-saved registers and loading the
4971 GOT register if needed. */
4974 sparc_flat_expand_prologue (void)
4979 sparc_leaf_function_p
= optimize
> 0 && current_function_is_leaf
;
4981 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4983 if (flag_stack_usage_info
)
4984 current_function_static_stack_size
= size
;
4986 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4987 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4989 if (sparc_save_local_in_regs_p
)
4990 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
4997 rtx size_int_rtx
, size_rtx
;
4999 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5001 /* We establish the frame (i.e. decrement the stack pointer) first, even
5002 if we use a frame pointer, because we cannot clobber any call-saved
5003 registers, including the frame pointer, if we haven't created a new
5004 register save area, for the sake of compatibility with the ABI. */
5006 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5007 else if (size
<= 8192 && !frame_pointer_needed
)
5009 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5010 RTX_FRAME_RELATED_P (insn
) = 1;
5011 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5015 size_rtx
= gen_rtx_REG (Pmode
, 1);
5016 emit_move_insn (size_rtx
, size_int_rtx
);
5017 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5018 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5019 gen_stack_pointer_inc (size_int_rtx
));
5021 RTX_FRAME_RELATED_P (insn
) = 1;
5023 /* Ensure nothing is scheduled until after the frame is established. */
5024 emit_insn (gen_blockage ());
5026 if (frame_pointer_needed
)
5028 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5029 gen_rtx_MINUS (Pmode
,
5032 RTX_FRAME_RELATED_P (insn
) = 1;
5034 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5035 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5036 plus_constant (stack_pointer_rtx
,
5040 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5042 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5043 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5045 insn
= emit_move_insn (i7
, o7
);
5046 RTX_FRAME_RELATED_P (insn
) = 1;
5048 add_reg_note (insn
, REG_CFA_REGISTER
,
5049 gen_rtx_SET (VOIDmode
, i7
, o7
));
5051 /* Prevent this instruction from ever being considered dead,
5052 even if this function has no epilogue. */
5053 emit_insn (gen_rtx_USE (VOIDmode
, i7
));
5057 if (frame_pointer_needed
)
5059 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5060 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5064 sparc_frame_base_reg
= stack_pointer_rtx
;
5065 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5068 if (sparc_n_global_fp_regs
> 0)
5069 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5070 sparc_frame_base_offset
5071 - sparc_apparent_frame_size
,
5074 /* Load the GOT register if needed. */
5075 if (crtl
->uses_pic_offset_table
)
5076 load_got_register ();
5078 /* Advertise that the data calculated just above are now valid. */
5079 sparc_prologue_data_valid_p
= true;
5082 /* This function generates the assembly code for function entry, which boils
5083 down to emitting the necessary .register directives. */
5086 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5088 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5090 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
5092 sparc_output_scratch_registers (file
);
5095 /* Expand the function epilogue, either normal or part of a sibcall.
5096 We emit all the instructions except the return or the call. */
5099 sparc_expand_epilogue (bool for_eh
)
5101 HOST_WIDE_INT size
= sparc_frame_size
;
5103 if (sparc_n_global_fp_regs
> 0)
5104 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5105 sparc_frame_base_offset
5106 - sparc_apparent_frame_size
,
5109 if (size
== 0 || for_eh
)
5111 else if (sparc_leaf_function_p
)
5114 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
5115 else if (size
<= 8192)
5117 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5118 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5122 rtx reg
= gen_rtx_REG (Pmode
, 1);
5123 emit_move_insn (reg
, GEN_INT (-size
));
5124 emit_insn (gen_stack_pointer_dec (reg
));
5129 /* Expand the function epilogue, either normal or part of a sibcall.
5130 We emit all the instructions except the return or the call. */
5133 sparc_flat_expand_epilogue (bool for_eh
)
5135 HOST_WIDE_INT size
= sparc_frame_size
;
5137 if (sparc_n_global_fp_regs
> 0)
5138 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5139 sparc_frame_base_offset
5140 - sparc_apparent_frame_size
,
5143 /* If we have a frame pointer, we'll need both to restore it before the
5144 frame is destroyed and use its current value in destroying the frame.
5145 Since we don't have an atomic way to do that in the flat window model,
5146 we save the current value into a temporary register (%g1). */
5147 if (frame_pointer_needed
&& !for_eh
)
5148 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5150 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5151 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5152 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5154 if (sparc_save_local_in_regs_p
)
5155 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5156 sparc_frame_base_offset
,
5159 if (size
== 0 || for_eh
)
5161 else if (frame_pointer_needed
)
5163 /* Make sure the frame is destroyed after everything else is done. */
5164 emit_insn (gen_blockage ());
5166 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5171 emit_insn (gen_blockage ());
5174 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
5175 else if (size
<= 8192)
5177 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5178 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5182 rtx reg
= gen_rtx_REG (Pmode
, 1);
5183 emit_move_insn (reg
, GEN_INT (-size
));
5184 emit_insn (gen_stack_pointer_dec (reg
));
5189 /* Return true if it is appropriate to emit `return' instructions in the
5190 body of a function. */
5193 sparc_can_use_return_insn_p (void)
5195 return sparc_prologue_data_valid_p
5196 && sparc_n_global_fp_regs
== 0
5198 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5199 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5202 /* This function generates the assembly code for function exit. */
5205 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5207 /* If the last two instructions of a function are "call foo; dslot;"
5208 the return address might point to the first instruction in the next
5209 function and we have to output a dummy nop for the sake of sane
5210 backtraces in such cases. This is pointless for sibling calls since
5211 the return address is explicitly adjusted. */
5213 rtx insn
, last_real_insn
;
5215 insn
= get_last_insn ();
5217 last_real_insn
= prev_real_insn (insn
);
5219 && GET_CODE (last_real_insn
) == INSN
5220 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5221 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5224 && CALL_P (last_real_insn
)
5225 && !SIBLING_CALL_P (last_real_insn
))
5226 fputs("\tnop\n", file
);
5228 sparc_output_deferred_case_vectors ();
5231 /* Output a 'restore' instruction. */
5234 output_restore (rtx pat
)
5240 fputs ("\t restore\n", asm_out_file
);
5244 gcc_assert (GET_CODE (pat
) == SET
);
5246 operands
[0] = SET_DEST (pat
);
5247 pat
= SET_SRC (pat
);
5249 switch (GET_CODE (pat
))
5252 operands
[1] = XEXP (pat
, 0);
5253 operands
[2] = XEXP (pat
, 1);
5254 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5257 operands
[1] = XEXP (pat
, 0);
5258 operands
[2] = XEXP (pat
, 1);
5259 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5262 operands
[1] = XEXP (pat
, 0);
5263 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5264 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5268 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5273 /* Output a return. */
5276 output_return (rtx insn
)
5278 if (crtl
->calls_eh_return
)
5280 /* If the function uses __builtin_eh_return, the eh_return
5281 machinery occupies the delay slot. */
5282 gcc_assert (!final_sequence
);
5284 if (flag_delayed_branch
)
5286 if (!TARGET_FLAT
&& TARGET_V9
)
5287 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5291 fputs ("\trestore\n", asm_out_file
);
5293 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5296 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5301 fputs ("\trestore\n", asm_out_file
);
5303 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5304 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5307 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5309 /* This is a leaf or flat function so we don't have to bother restoring
5310 the register window, which frees us from dealing with the convoluted
5311 semantics of restore/return. We simply output the jump to the
5312 return address and the insn in the delay slot (if any). */
5314 return "jmp\t%%o7+%)%#";
5318 /* This is a regular function so we have to restore the register window.
5319 We may have a pending insn for the delay slot, which will be either
5320 combined with the 'restore' instruction or put in the delay slot of
5321 the 'return' instruction. */
5327 delay
= NEXT_INSN (insn
);
5330 pat
= PATTERN (delay
);
5332 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5334 epilogue_renumber (&pat
, 0);
5335 return "return\t%%i7+%)%#";
5339 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5340 output_restore (pat
);
5341 PATTERN (delay
) = gen_blockage ();
5342 INSN_CODE (delay
) = -1;
5347 /* The delay slot is empty. */
5349 return "return\t%%i7+%)\n\t nop";
5350 else if (flag_delayed_branch
)
5351 return "jmp\t%%i7+%)\n\t restore";
5353 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5360 /* Output a sibling call. */
5363 output_sibcall (rtx insn
, rtx call_operand
)
5367 gcc_assert (flag_delayed_branch
);
5369 operands
[0] = call_operand
;
5371 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5373 /* This is a leaf or flat function so we don't have to bother restoring
5374 the register window. We simply output the jump to the function and
5375 the insn in the delay slot (if any). */
5377 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5380 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5383 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5384 it into branch if possible. */
5385 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5390 /* This is a regular function so we have to restore the register window.
5391 We may have a pending insn for the delay slot, which will be combined
5392 with the 'restore' instruction. */
5394 output_asm_insn ("call\t%a0, 0", operands
);
5398 rtx delay
= NEXT_INSN (insn
);
5401 output_restore (PATTERN (delay
));
5403 PATTERN (delay
) = gen_blockage ();
5404 INSN_CODE (delay
) = -1;
5407 output_restore (NULL_RTX
);
5413 /* Functions for handling argument passing.
5415 For 32-bit, the first 6 args are normally in registers and the rest are
5416 pushed. Any arg that starts within the first 6 words is at least
5417 partially passed in a register unless its data type forbids.
5419 For 64-bit, the argument registers are laid out as an array of 16 elements
5420 and arguments are added sequentially. The first 6 int args and up to the
5421 first 16 fp args (depending on size) are passed in regs.
5423 Slot Stack Integral Float Float in structure Double Long Double
5424 ---- ----- -------- ----- ------------------ ------ -----------
5425 15 [SP+248] %f31 %f30,%f31 %d30
5426 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5427 13 [SP+232] %f27 %f26,%f27 %d26
5428 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5429 11 [SP+216] %f23 %f22,%f23 %d22
5430 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5431 9 [SP+200] %f19 %f18,%f19 %d18
5432 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5433 7 [SP+184] %f15 %f14,%f15 %d14
5434 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5435 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5436 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5437 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5438 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5439 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5440 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5442 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5444 Integral arguments are always passed as 64-bit quantities appropriately
5447 Passing of floating point values is handled as follows.
5448 If a prototype is in scope:
5449 If the value is in a named argument (i.e. not a stdarg function or a
5450 value not part of the `...') then the value is passed in the appropriate
5452 If the value is part of the `...' and is passed in one of the first 6
5453 slots then the value is passed in the appropriate int reg.
5454 If the value is part of the `...' and is not passed in one of the first 6
5455 slots then the value is passed in memory.
5456 If a prototype is not in scope:
5457 If the value is one of the first 6 arguments the value is passed in the
5458 appropriate integer reg and the appropriate fp reg.
5459 If the value is not one of the first 6 arguments the value is passed in
5460 the appropriate fp reg and in memory.
5463 Summary of the calling conventions implemented by GCC on the SPARC:
5466 size argument return value
5468 small integer <4 int. reg. int. reg.
5469 word 4 int. reg. int. reg.
5470 double word 8 int. reg. int. reg.
5472 _Complex small integer <8 int. reg. int. reg.
5473 _Complex word 8 int. reg. int. reg.
5474 _Complex double word 16 memory int. reg.
5476 vector integer <=8 int. reg. FP reg.
5477 vector integer >8 memory memory
5479 float 4 int. reg. FP reg.
5480 double 8 int. reg. FP reg.
5481 long double 16 memory memory
5483 _Complex float 8 memory FP reg.
5484 _Complex double 16 memory FP reg.
5485 _Complex long double 32 memory FP reg.
5487 vector float any memory memory
5489 aggregate any memory memory
5494 size argument return value
5496 small integer <8 int. reg. int. reg.
5497 word 8 int. reg. int. reg.
5498 double word 16 int. reg. int. reg.
5500 _Complex small integer <16 int. reg. int. reg.
5501 _Complex word 16 int. reg. int. reg.
5502 _Complex double word 32 memory int. reg.
5504 vector integer <=16 FP reg. FP reg.
5505 vector integer 16<s<=32 memory FP reg.
5506 vector integer >32 memory memory
5508 float 4 FP reg. FP reg.
5509 double 8 FP reg. FP reg.
5510 long double 16 FP reg. FP reg.
5512 _Complex float 8 FP reg. FP reg.
5513 _Complex double 16 FP reg. FP reg.
5514 _Complex long double 32 memory FP reg.
5516 vector float <=16 FP reg. FP reg.
5517 vector float 16<s<=32 memory FP reg.
5518 vector float >32 memory memory
5520 aggregate <=16 reg. reg.
5521 aggregate 16<s<=32 memory reg.
5522 aggregate >32 memory memory
5526 Note #1: complex floating-point types follow the extended SPARC ABIs as
5527 implemented by the Sun compiler.
5529 Note #2: integral vector types follow the scalar floating-point types
5530 conventions to match what is implemented by the Sun VIS SDK.
5532 Note #3: floating-point vector types follow the aggregate types
5536 /* Maximum number of int regs for args. */
5537 #define SPARC_INT_ARG_MAX 6
5538 /* Maximum number of fp regs for args. */
5539 #define SPARC_FP_ARG_MAX 16
5541 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5543 /* Handle the INIT_CUMULATIVE_ARGS macro.
5544 Initialize a variable CUM of type CUMULATIVE_ARGS
5545 for a call to a function whose data type is FNTYPE.
5546 For a library call, FNTYPE is 0. */
5549 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5550 rtx libname ATTRIBUTE_UNUSED
,
5551 tree fndecl ATTRIBUTE_UNUSED
)
5554 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5555 cum
->libcall_p
= fntype
== 0;
5558 /* Handle promotion of pointer and integer arguments. */
5560 static enum machine_mode
5561 sparc_promote_function_mode (const_tree type
,
5562 enum machine_mode mode
,
5564 const_tree fntype ATTRIBUTE_UNUSED
,
5565 int for_return ATTRIBUTE_UNUSED
)
5567 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5569 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5573 /* Integral arguments are passed as full words, as per the ABI. */
5574 if (GET_MODE_CLASS (mode
) == MODE_INT
5575 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5581 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5584 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5586 return TARGET_ARCH64
? true : false;
5589 /* Scan the record type TYPE and return the following predicates:
5590 - INTREGS_P: the record contains at least one field or sub-field
5591 that is eligible for promotion in integer registers.
5592 - FP_REGS_P: the record contains at least one field or sub-field
5593 that is eligible for promotion in floating-point registers.
5594 - PACKED_P: the record contains at least one field that is packed.
5596 Sub-fields are not taken into account for the PACKED_P predicate. */
5599 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5604 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5606 if (TREE_CODE (field
) == FIELD_DECL
)
5608 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5609 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5610 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5611 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5617 if (packed_p
&& DECL_PACKED (field
))
5623 /* Compute the slot number to pass an argument in.
5624 Return the slot number or -1 if passing on the stack.
5626 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5627 the preceding args and about the function being called.
5628 MODE is the argument's machine mode.
5629 TYPE is the data type of the argument (as a tree).
5630 This is null for libcalls where that information may
5632 NAMED is nonzero if this argument is a named parameter
5633 (otherwise it is an extra parameter matching an ellipsis).
5634 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5635 *PREGNO records the register number to use if scalar type.
5636 *PPADDING records the amount of padding needed in words. */
5639 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5640 const_tree type
, bool named
, bool incoming_p
,
5641 int *pregno
, int *ppadding
)
5643 int regbase
= (incoming_p
5644 ? SPARC_INCOMING_INT_ARG_FIRST
5645 : SPARC_OUTGOING_INT_ARG_FIRST
);
5646 int slotno
= cum
->words
;
5647 enum mode_class mclass
;
5652 if (type
&& TREE_ADDRESSABLE (type
))
5658 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5661 /* For SPARC64, objects requiring 16-byte alignment get it. */
5663 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5664 && (slotno
& 1) != 0)
5665 slotno
++, *ppadding
= 1;
5667 mclass
= GET_MODE_CLASS (mode
);
5668 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5670 /* Vector types deserve special treatment because they are
5671 polymorphic wrt their mode, depending upon whether VIS
5672 instructions are enabled. */
5673 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5675 /* The SPARC port defines no floating-point vector modes. */
5676 gcc_assert (mode
== BLKmode
);
5680 /* Integral vector types should either have a vector
5681 mode or an integral mode, because we are guaranteed
5682 by pass_by_reference that their size is not greater
5683 than 16 bytes and TImode is 16-byte wide. */
5684 gcc_assert (mode
!= BLKmode
);
5686 /* Vector integers are handled like floats according to
5688 mclass
= MODE_FLOAT
;
5695 case MODE_COMPLEX_FLOAT
:
5696 case MODE_VECTOR_INT
:
5697 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5699 if (slotno
>= SPARC_FP_ARG_MAX
)
5701 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5702 /* Arguments filling only one single FP register are
5703 right-justified in the outer double FP register. */
5704 if (GET_MODE_SIZE (mode
) <= 4)
5711 case MODE_COMPLEX_INT
:
5712 if (slotno
>= SPARC_INT_ARG_MAX
)
5714 regno
= regbase
+ slotno
;
5718 if (mode
== VOIDmode
)
5719 /* MODE is VOIDmode when generating the actual call. */
5722 gcc_assert (mode
== BLKmode
);
5726 || (TREE_CODE (type
) != VECTOR_TYPE
5727 && TREE_CODE (type
) != RECORD_TYPE
))
5729 if (slotno
>= SPARC_INT_ARG_MAX
)
5731 regno
= regbase
+ slotno
;
5733 else /* TARGET_ARCH64 && type */
5735 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5737 /* First see what kinds of registers we would need. */
5738 if (TREE_CODE (type
) == VECTOR_TYPE
)
5741 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5743 /* The ABI obviously doesn't specify how packed structures
5744 are passed. These are defined to be passed in int regs
5745 if possible, otherwise memory. */
5746 if (packed_p
|| !named
)
5747 fpregs_p
= 0, intregs_p
= 1;
5749 /* If all arg slots are filled, then must pass on stack. */
5750 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5753 /* If there are only int args and all int arg slots are filled,
5754 then must pass on stack. */
5755 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5758 /* Note that even if all int arg slots are filled, fp members may
5759 still be passed in regs if such regs are available.
5760 *PREGNO isn't set because there may be more than one, it's up
5761 to the caller to compute them. */
5774 /* Handle recursive register counting for structure field layout. */
5776 struct function_arg_record_value_parms
5778 rtx ret
; /* return expression being built. */
5779 int slotno
; /* slot number of the argument. */
5780 int named
; /* whether the argument is named. */
5781 int regbase
; /* regno of the base register. */
5782 int stack
; /* 1 if part of the argument is on the stack. */
5783 int intoffset
; /* offset of the first pending integer field. */
5784 unsigned int nregs
; /* number of words passed in registers. */
5787 static void function_arg_record_value_3
5788 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5789 static void function_arg_record_value_2
5790 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5791 static void function_arg_record_value_1
5792 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5793 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
5794 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5796 /* A subroutine of function_arg_record_value. Traverse the structure
5797 recursively and determine how many registers will be required. */
5800 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
5801 struct function_arg_record_value_parms
*parms
,
5806 /* We need to compute how many registers are needed so we can
5807 allocate the PARALLEL but before we can do that we need to know
5808 whether there are any packed fields. The ABI obviously doesn't
5809 specify how structures are passed in this case, so they are
5810 defined to be passed in int regs if possible, otherwise memory,
5811 regardless of whether there are fp values present. */
5814 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5816 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5823 /* Compute how many registers we need. */
5824 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5826 if (TREE_CODE (field
) == FIELD_DECL
)
5828 HOST_WIDE_INT bitpos
= startbitpos
;
5830 if (DECL_SIZE (field
) != 0)
5832 if (integer_zerop (DECL_SIZE (field
)))
5835 if (host_integerp (bit_position (field
), 1))
5836 bitpos
+= int_bit_position (field
);
5839 /* ??? FIXME: else assume zero offset. */
5841 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5842 function_arg_record_value_1 (TREE_TYPE (field
),
5846 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5847 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5852 if (parms
->intoffset
!= -1)
5854 unsigned int startbit
, endbit
;
5855 int intslots
, this_slotno
;
5857 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5858 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5860 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5861 this_slotno
= parms
->slotno
+ parms
->intoffset
5864 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5866 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5867 /* We need to pass this field on the stack. */
5871 parms
->nregs
+= intslots
;
5872 parms
->intoffset
= -1;
5875 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5876 If it wasn't true we wouldn't be here. */
5877 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5878 && DECL_MODE (field
) == BLKmode
)
5879 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5880 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5887 if (parms
->intoffset
== -1)
5888 parms
->intoffset
= bitpos
;
5894 /* A subroutine of function_arg_record_value. Assign the bits of the
5895 structure between parms->intoffset and bitpos to integer registers. */
5898 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5899 struct function_arg_record_value_parms
*parms
)
5901 enum machine_mode mode
;
5903 unsigned int startbit
, endbit
;
5904 int this_slotno
, intslots
, intoffset
;
5907 if (parms
->intoffset
== -1)
5910 intoffset
= parms
->intoffset
;
5911 parms
->intoffset
= -1;
5913 startbit
= intoffset
& -BITS_PER_WORD
;
5914 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5915 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5916 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5918 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5922 /* If this is the trailing part of a word, only load that much into
5923 the register. Otherwise load the whole register. Note that in
5924 the latter case we may pick up unwanted bits. It's not a problem
5925 at the moment but may wish to revisit. */
5927 if (intoffset
% BITS_PER_WORD
!= 0)
5928 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5933 intoffset
/= BITS_PER_UNIT
;
5936 regno
= parms
->regbase
+ this_slotno
;
5937 reg
= gen_rtx_REG (mode
, regno
);
5938 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5939 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5942 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5947 while (intslots
> 0);
5950 /* A subroutine of function_arg_record_value. Traverse the structure
5951 recursively and assign bits to floating point registers. Track which
5952 bits in between need integer registers; invoke function_arg_record_value_3
5953 to make that happen. */
5956 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5957 struct function_arg_record_value_parms
*parms
,
5963 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5965 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5972 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5974 if (TREE_CODE (field
) == FIELD_DECL
)
5976 HOST_WIDE_INT bitpos
= startbitpos
;
5978 if (DECL_SIZE (field
) != 0)
5980 if (integer_zerop (DECL_SIZE (field
)))
5983 if (host_integerp (bit_position (field
), 1))
5984 bitpos
+= int_bit_position (field
);
5987 /* ??? FIXME: else assume zero offset. */
5989 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5990 function_arg_record_value_2 (TREE_TYPE (field
),
5994 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5995 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6000 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
6001 int regno
, nregs
, pos
;
6002 enum machine_mode mode
= DECL_MODE (field
);
6005 function_arg_record_value_3 (bitpos
, parms
);
6007 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6010 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6011 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6013 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6015 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6021 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6022 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6024 reg
= gen_rtx_REG (mode
, regno
);
6025 pos
= bitpos
/ BITS_PER_UNIT
;
6026 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6027 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6031 regno
+= GET_MODE_SIZE (mode
) / 4;
6032 reg
= gen_rtx_REG (mode
, regno
);
6033 pos
+= GET_MODE_SIZE (mode
);
6034 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6035 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6041 if (parms
->intoffset
== -1)
6042 parms
->intoffset
= bitpos
;
6048 /* Used by function_arg and sparc_function_value_1 to implement the complex
6049 conventions of the 64-bit ABI for passing and returning structures.
6050 Return an expression valid as a return value for the FUNCTION_ARG
6051 and TARGET_FUNCTION_VALUE.
6053 TYPE is the data type of the argument (as a tree).
6054 This is null for libcalls where that information may
6056 MODE is the argument's machine mode.
6057 SLOTNO is the index number of the argument's slot in the parameter array.
6058 NAMED is nonzero if this argument is a named parameter
6059 (otherwise it is an extra parameter matching an ellipsis).
6060 REGBASE is the regno of the base register for the parameter array. */
6063 function_arg_record_value (const_tree type
, enum machine_mode mode
,
6064 int slotno
, int named
, int regbase
)
6066 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6067 struct function_arg_record_value_parms parms
;
6070 parms
.ret
= NULL_RTX
;
6071 parms
.slotno
= slotno
;
6072 parms
.named
= named
;
6073 parms
.regbase
= regbase
;
6076 /* Compute how many registers we need. */
6078 parms
.intoffset
= 0;
6079 function_arg_record_value_1 (type
, 0, &parms
, false);
6081 /* Take into account pending integer fields. */
6082 if (parms
.intoffset
!= -1)
6084 unsigned int startbit
, endbit
;
6085 int intslots
, this_slotno
;
6087 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
6088 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6089 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6090 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
6092 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6094 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6095 /* We need to pass this field on the stack. */
6099 parms
.nregs
+= intslots
;
6101 nregs
= parms
.nregs
;
6103 /* Allocate the vector and handle some annoying special cases. */
6106 /* ??? Empty structure has no value? Duh? */
6109 /* Though there's nothing really to store, return a word register
6110 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6111 leads to breakage due to the fact that there are zero bytes to
6113 return gen_rtx_REG (mode
, regbase
);
6117 /* ??? C++ has structures with no fields, and yet a size. Give up
6118 for now and pass everything back in integer registers. */
6119 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6121 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6122 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6124 gcc_assert (nregs
!= 0);
6126 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
6128 /* If at least one field must be passed on the stack, generate
6129 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6130 also be passed on the stack. We can't do much better because the
6131 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6132 of structures for which the fields passed exclusively in registers
6133 are not at the beginning of the structure. */
6135 XVECEXP (parms
.ret
, 0, 0)
6136 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6138 /* Fill in the entries. */
6140 parms
.intoffset
= 0;
6141 function_arg_record_value_2 (type
, 0, &parms
, false);
6142 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6144 gcc_assert (parms
.nregs
== nregs
);
6149 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6150 of the 64-bit ABI for passing and returning unions.
6151 Return an expression valid as a return value for the FUNCTION_ARG
6152 and TARGET_FUNCTION_VALUE.
6154 SIZE is the size in bytes of the union.
6155 MODE is the argument's machine mode.
6156 REGNO is the hard register the union will be passed in. */
6159 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6162 int nwords
= ROUND_ADVANCE (size
), i
;
6165 /* See comment in previous function for empty structures. */
6167 return gen_rtx_REG (mode
, regno
);
6169 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6172 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6174 for (i
= 0; i
< nwords
; i
++)
6176 /* Unions are passed left-justified. */
6177 XVECEXP (regs
, 0, i
)
6178 = gen_rtx_EXPR_LIST (VOIDmode
,
6179 gen_rtx_REG (word_mode
, regno
),
6180 GEN_INT (UNITS_PER_WORD
* i
));
6187 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6188 for passing and returning large (BLKmode) vectors.
6189 Return an expression valid as a return value for the FUNCTION_ARG
6190 and TARGET_FUNCTION_VALUE.
6192 SIZE is the size in bytes of the vector (at least 8 bytes).
6193 REGNO is the FP hard register the vector will be passed in. */
6196 function_arg_vector_value (int size
, int regno
)
6198 int i
, nregs
= size
/ 8;
6201 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6203 for (i
= 0; i
< nregs
; i
++)
6205 XVECEXP (regs
, 0, i
)
6206 = gen_rtx_EXPR_LIST (VOIDmode
,
6207 gen_rtx_REG (DImode
, regno
+ 2*i
),
6214 /* Determine where to put an argument to a function.
6215 Value is zero to push the argument on the stack,
6216 or a hard register in which to store the argument.
6218 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6219 the preceding args and about the function being called.
6220 MODE is the argument's machine mode.
6221 TYPE is the data type of the argument (as a tree).
6222 This is null for libcalls where that information may
6224 NAMED is true if this argument is a named parameter
6225 (otherwise it is an extra parameter matching an ellipsis).
6226 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6227 TARGET_FUNCTION_INCOMING_ARG. */
6230 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6231 const_tree type
, bool named
, bool incoming_p
)
6233 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6235 int regbase
= (incoming_p
6236 ? SPARC_INCOMING_INT_ARG_FIRST
6237 : SPARC_OUTGOING_INT_ARG_FIRST
);
6238 int slotno
, regno
, padding
;
6239 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6241 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6246 /* Vector types deserve special treatment because they are polymorphic wrt
6247 their mode, depending upon whether VIS instructions are enabled. */
6248 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6250 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6251 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6252 || (TARGET_ARCH64
&& size
<= 16));
6254 if (mode
== BLKmode
)
6255 return function_arg_vector_value (size
,
6256 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6258 mclass
= MODE_FLOAT
;
6262 return gen_rtx_REG (mode
, regno
);
6264 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6265 and are promoted to registers if possible. */
6266 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6268 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6269 gcc_assert (size
<= 16);
6271 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6274 /* Unions up to 16 bytes in size are passed in integer registers. */
6275 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6277 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6278 gcc_assert (size
<= 16);
6280 return function_arg_union_value (size
, mode
, slotno
, regno
);
6283 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6284 but also have the slot allocated for them.
6285 If no prototype is in scope fp values in register slots get passed
6286 in two places, either fp regs and int regs or fp regs and memory. */
6287 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6288 && SPARC_FP_REG_P (regno
))
6290 rtx reg
= gen_rtx_REG (mode
, regno
);
6291 if (cum
->prototype_p
|| cum
->libcall_p
)
6293 /* "* 2" because fp reg numbers are recorded in 4 byte
6296 /* ??? This will cause the value to be passed in the fp reg and
6297 in the stack. When a prototype exists we want to pass the
6298 value in the reg but reserve space on the stack. That's an
6299 optimization, and is deferred [for a bit]. */
6300 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6301 return gen_rtx_PARALLEL (mode
,
6303 gen_rtx_EXPR_LIST (VOIDmode
,
6304 NULL_RTX
, const0_rtx
),
6305 gen_rtx_EXPR_LIST (VOIDmode
,
6309 /* ??? It seems that passing back a register even when past
6310 the area declared by REG_PARM_STACK_SPACE will allocate
6311 space appropriately, and will not copy the data onto the
6312 stack, exactly as we desire.
6314 This is due to locate_and_pad_parm being called in
6315 expand_call whenever reg_parm_stack_space > 0, which
6316 while beneficial to our example here, would seem to be
6317 in error from what had been intended. Ho hum... -- r~ */
6325 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6329 /* On incoming, we don't need to know that the value
6330 is passed in %f0 and %i0, and it confuses other parts
6331 causing needless spillage even on the simplest cases. */
6335 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6336 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6338 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6339 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6341 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6345 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6346 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6347 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6352 /* All other aggregate types are passed in an integer register in a mode
6353 corresponding to the size of the type. */
6354 else if (type
&& AGGREGATE_TYPE_P (type
))
6356 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6357 gcc_assert (size
<= 16);
6359 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6362 return gen_rtx_REG (mode
, regno
);
6365 /* Handle the TARGET_FUNCTION_ARG target hook. */
6368 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6369 const_tree type
, bool named
)
6371 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6374 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6377 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6378 const_tree type
, bool named
)
6380 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6383 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6386 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6388 return ((TARGET_ARCH64
6389 && (GET_MODE_ALIGNMENT (mode
) == 128
6390 || (type
&& TYPE_ALIGN (type
) == 128)))
6395 /* For an arg passed partly in registers and partly in memory,
6396 this is the number of bytes of registers used.
6397 For args passed entirely in registers or entirely in memory, zero.
6399 Any arg that starts in the first 6 regs but won't entirely fit in them
6400 needs partial registers on v8. On v9, structures with integer
6401 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6402 values that begin in the last fp reg [where "last fp reg" varies with the
6403 mode] will be split between that reg and memory. */
6406 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6407 tree type
, bool named
)
6409 int slotno
, regno
, padding
;
6411 /* We pass false for incoming_p here, it doesn't matter. */
6412 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6413 false, ®no
, &padding
);
6420 if ((slotno
+ (mode
== BLKmode
6421 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6422 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6423 > SPARC_INT_ARG_MAX
)
6424 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6428 /* We are guaranteed by pass_by_reference that the size of the
6429 argument is not greater than 16 bytes, so we only need to return
6430 one word if the argument is partially passed in registers. */
6432 if (type
&& AGGREGATE_TYPE_P (type
))
6434 int size
= int_size_in_bytes (type
);
6436 if (size
> UNITS_PER_WORD
6437 && slotno
== SPARC_INT_ARG_MAX
- 1)
6438 return UNITS_PER_WORD
;
6440 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6441 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6442 && ! (TARGET_FPU
&& named
)))
6444 /* The complex types are passed as packed types. */
6445 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6446 && slotno
== SPARC_INT_ARG_MAX
- 1)
6447 return UNITS_PER_WORD
;
6449 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6451 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6453 return UNITS_PER_WORD
;
6460 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6461 Specify whether to pass the argument by reference. */
6464 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6465 enum machine_mode mode
, const_tree type
,
6466 bool named ATTRIBUTE_UNUSED
)
6469 /* Original SPARC 32-bit ABI says that structures and unions,
6470 and quad-precision floats are passed by reference. For Pascal,
6471 also pass arrays by reference. All other base types are passed
6474 Extended ABI (as implemented by the Sun compiler) says that all
6475 complex floats are passed by reference. Pass complex integers
6476 in registers up to 8 bytes. More generally, enforce the 2-word
6477 cap for passing arguments in registers.
6479 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6480 integers are passed like floats of the same size, that is in
6481 registers up to 8 bytes. Pass all vector floats by reference
6482 like structure and unions. */
6483 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6485 /* Catch CDImode, TFmode, DCmode and TCmode. */
6486 || GET_MODE_SIZE (mode
) > 8
6488 && TREE_CODE (type
) == VECTOR_TYPE
6489 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6491 /* Original SPARC 64-bit ABI says that structures and unions
6492 smaller than 16 bytes are passed in registers, as well as
6493 all other base types.
6495 Extended ABI (as implemented by the Sun compiler) says that
6496 complex floats are passed in registers up to 16 bytes. Pass
6497 all complex integers in registers up to 16 bytes. More generally,
6498 enforce the 2-word cap for passing arguments in registers.
6500 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6501 integers are passed like floats of the same size, that is in
6502 registers (up to 16 bytes). Pass all vector floats like structure
6505 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6506 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6507 /* Catch CTImode and TCmode. */
6508 || GET_MODE_SIZE (mode
) > 16);
6511 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6512 Update the data in CUM to advance over an argument
6513 of mode MODE and data type TYPE.
6514 TYPE is null for libcalls where that information may not be available. */
6517 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6518 const_tree type
, bool named
)
6520 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6523 /* We pass false for incoming_p here, it doesn't matter. */
6524 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6526 /* If argument requires leading padding, add it. */
6527 cum
->words
+= padding
;
6531 cum
->words
+= (mode
!= BLKmode
6532 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6533 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6537 if (type
&& AGGREGATE_TYPE_P (type
))
6539 int size
= int_size_in_bytes (type
);
6543 else if (size
<= 16)
6545 else /* passed by reference */
6550 cum
->words
+= (mode
!= BLKmode
6551 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6552 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6557 /* Handle the FUNCTION_ARG_PADDING macro.
6558 For the 64 bit ABI structs are always stored left shifted in their
6562 function_arg_padding (enum machine_mode mode
, const_tree type
)
6564 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6567 /* Fall back to the default. */
6568 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6571 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6572 Specify whether to return the return value in memory. */
6575 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6578 /* Original SPARC 32-bit ABI says that structures and unions,
6579 and quad-precision floats are returned in memory. All other
6580 base types are returned in registers.
6582 Extended ABI (as implemented by the Sun compiler) says that
6583 all complex floats are returned in registers (8 FP registers
6584 at most for '_Complex long double'). Return all complex integers
6585 in registers (4 at most for '_Complex long long').
6587 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6588 integers are returned like floats of the same size, that is in
6589 registers up to 8 bytes and in memory otherwise. Return all
6590 vector floats in memory like structure and unions; note that
6591 they always have BLKmode like the latter. */
6592 return (TYPE_MODE (type
) == BLKmode
6593 || TYPE_MODE (type
) == TFmode
6594 || (TREE_CODE (type
) == VECTOR_TYPE
6595 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6597 /* Original SPARC 64-bit ABI says that structures and unions
6598 smaller than 32 bytes are returned in registers, as well as
6599 all other base types.
6601 Extended ABI (as implemented by the Sun compiler) says that all
6602 complex floats are returned in registers (8 FP registers at most
6603 for '_Complex long double'). Return all complex integers in
6604 registers (4 at most for '_Complex TItype').
6606 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6607 integers are returned like floats of the same size, that is in
6608 registers. Return all vector floats like structure and unions;
6609 note that they always have BLKmode like the latter. */
6610 return (TYPE_MODE (type
) == BLKmode
6611 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6614 /* Handle the TARGET_STRUCT_VALUE target hook.
6615 Return where to find the structure return value address. */
6618 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6627 mem
= gen_frame_mem (Pmode
, plus_constant (frame_pointer_rtx
,
6628 STRUCT_VALUE_OFFSET
));
6630 mem
= gen_frame_mem (Pmode
, plus_constant (stack_pointer_rtx
,
6631 STRUCT_VALUE_OFFSET
));
6633 /* Only follow the SPARC ABI for fixed-size structure returns.
6634 Variable size structure returns are handled per the normal
6635 procedures in GCC. This is enabled by -mstd-struct-return */
6637 && sparc_std_struct_return
6638 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6639 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6641 /* We must check and adjust the return address, as it is
6642 optional as to whether the return object is really
6644 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6645 rtx scratch
= gen_reg_rtx (SImode
);
6646 rtx endlab
= gen_label_rtx ();
6648 /* Calculate the return object size */
6649 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6650 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6651 /* Construct a temporary return value */
6653 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6655 /* Implement SPARC 32-bit psABI callee return struct checking:
6657 Fetch the instruction where we will return to and see if
6658 it's an unimp instruction (the most significant 10 bits
6660 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6661 plus_constant (ret_reg
, 8)));
6662 /* Assume the size is valid and pre-adjust */
6663 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6664 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6666 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6667 /* Write the address of the memory pointed to by temp_val into
6668 the memory pointed to by mem */
6669 emit_move_insn (mem
, XEXP (temp_val
, 0));
6670 emit_label (endlab
);
6677 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6678 For v9, function return values are subject to the same rules as arguments,
6679 except that up to 32 bytes may be returned in registers. */
6682 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6685 /* Beware that the two values are swapped here wrt function_arg. */
6686 int regbase
= (outgoing
6687 ? SPARC_INCOMING_INT_ARG_FIRST
6688 : SPARC_OUTGOING_INT_ARG_FIRST
);
6689 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6692 /* Vector types deserve special treatment because they are polymorphic wrt
6693 their mode, depending upon whether VIS instructions are enabled. */
6694 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6696 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6697 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6698 || (TARGET_ARCH64
&& size
<= 32));
6700 if (mode
== BLKmode
)
6701 return function_arg_vector_value (size
,
6702 SPARC_FP_ARG_FIRST
);
6704 mclass
= MODE_FLOAT
;
6707 if (TARGET_ARCH64
&& type
)
6709 /* Structures up to 32 bytes in size are returned in registers. */
6710 if (TREE_CODE (type
) == RECORD_TYPE
)
6712 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6713 gcc_assert (size
<= 32);
6715 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6718 /* Unions up to 32 bytes in size are returned in integer registers. */
6719 else if (TREE_CODE (type
) == UNION_TYPE
)
6721 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6722 gcc_assert (size
<= 32);
6724 return function_arg_union_value (size
, mode
, 0, regbase
);
6727 /* Objects that require it are returned in FP registers. */
6728 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6731 /* All other aggregate types are returned in an integer register in a
6732 mode corresponding to the size of the type. */
6733 else if (AGGREGATE_TYPE_P (type
))
6735 /* All other aggregate types are passed in an integer register
6736 in a mode corresponding to the size of the type. */
6737 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6738 gcc_assert (size
<= 32);
6740 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6742 /* ??? We probably should have made the same ABI change in
6743 3.4.0 as the one we made for unions. The latter was
6744 required by the SCD though, while the former is not
6745 specified, so we favored compatibility and efficiency.
6747 Now we're stuck for aggregates larger than 16 bytes,
6748 because OImode vanished in the meantime. Let's not
6749 try to be unduly clever, and simply follow the ABI
6750 for unions in that case. */
6751 if (mode
== BLKmode
)
6752 return function_arg_union_value (size
, mode
, 0, regbase
);
6757 /* We should only have pointer and integer types at this point. This
6758 must match sparc_promote_function_mode. */
6759 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6763 /* We should only have pointer and integer types at this point. This must
6764 match sparc_promote_function_mode. */
6765 else if (TARGET_ARCH32
6766 && mclass
== MODE_INT
6767 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6770 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6771 regno
= SPARC_FP_ARG_FIRST
;
6775 return gen_rtx_REG (mode
, regno
);
6778 /* Handle TARGET_FUNCTION_VALUE.
6779 On the SPARC, the value is found in the first "output" register, but the
6780 called function leaves it in the first "input" register. */
6783 sparc_function_value (const_tree valtype
,
6784 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6787 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
6790 /* Handle TARGET_LIBCALL_VALUE. */
6793 sparc_libcall_value (enum machine_mode mode
,
6794 const_rtx fun ATTRIBUTE_UNUSED
)
6796 return sparc_function_value_1 (NULL_TREE
, mode
, false);
6799 /* Handle FUNCTION_VALUE_REGNO_P.
6800 On the SPARC, the first "output" reg is used for integer values, and the
6801 first floating point register is used for floating point values. */
6804 sparc_function_value_regno_p (const unsigned int regno
)
6806 return (regno
== 8 || regno
== 32);
6809 /* Do what is necessary for `va_start'. We look at the current function
6810 to determine if stdarg or varargs is used and return the address of
6811 the first unnamed parameter. */
6814 sparc_builtin_saveregs (void)
6816 int first_reg
= crtl
->args
.info
.words
;
6820 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6821 emit_move_insn (gen_rtx_MEM (word_mode
,
6822 gen_rtx_PLUS (Pmode
,
6824 GEN_INT (FIRST_PARM_OFFSET (0)
6827 gen_rtx_REG (word_mode
,
6828 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6830 address
= gen_rtx_PLUS (Pmode
,
6832 GEN_INT (FIRST_PARM_OFFSET (0)
6833 + UNITS_PER_WORD
* first_reg
));
6838 /* Implement `va_start' for stdarg. */
6841 sparc_va_start (tree valist
, rtx nextarg
)
6843 nextarg
= expand_builtin_saveregs ();
6844 std_expand_builtin_va_start (valist
, nextarg
);
6847 /* Implement `va_arg' for stdarg. */
6850 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6853 HOST_WIDE_INT size
, rsize
, align
;
6856 tree ptrtype
= build_pointer_type (type
);
6858 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6861 size
= rsize
= UNITS_PER_WORD
;
6867 size
= int_size_in_bytes (type
);
6868 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6873 /* For SPARC64, objects requiring 16-byte alignment get it. */
6874 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6875 align
= 2 * UNITS_PER_WORD
;
6877 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6878 are left-justified in their slots. */
6879 if (AGGREGATE_TYPE_P (type
))
6882 size
= rsize
= UNITS_PER_WORD
;
6892 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
6893 incr
= fold_convert (sizetype
, incr
);
6894 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
6896 incr
= fold_convert (ptr_type_node
, incr
);
6899 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6902 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6903 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
6907 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6908 addr
= build_va_arg_indirect_ref (addr
);
6911 /* If the address isn't aligned properly for the type, we need a temporary.
6912 FIXME: This is inefficient, usually we can do this in registers. */
6913 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6915 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6916 tree dest_addr
= build_fold_addr_expr (tmp
);
6917 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
6918 3, dest_addr
, addr
, size_int (rsize
));
6919 TREE_ADDRESSABLE (tmp
) = 1;
6920 gimplify_and_add (copy
, pre_p
);
6925 addr
= fold_convert (ptrtype
, addr
);
6927 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
6928 gimplify_assign (valist
, incr
, post_p
);
6930 return build_va_arg_indirect_ref (addr
);
6933 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6934 Specify whether the vector mode is supported by the hardware. */
6937 sparc_vector_mode_supported_p (enum machine_mode mode
)
6939 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6942 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6944 static enum machine_mode
6945 sparc_preferred_simd_mode (enum machine_mode mode
)
6963 /* Return the string to output an unconditional branch to LABEL, which is
6964 the operand number of the label.
6966 DEST is the destination insn (i.e. the label), INSN is the source. */
6969 output_ubranch (rtx dest
, int label
, rtx insn
)
6971 static char string
[64];
6972 bool v9_form
= false;
6975 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6977 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6978 - INSN_ADDRESSES (INSN_UID (insn
)));
6979 /* Leave some instructions for "slop". */
6980 if (delta
>= -260000 && delta
< 260000)
6985 strcpy (string
, "ba%*,pt\t%%xcc, ");
6987 strcpy (string
, "b%*\t");
6989 p
= strchr (string
, '\0');
7000 /* Return the string to output a conditional branch to LABEL, which is
7001 the operand number of the label. OP is the conditional expression.
7002 XEXP (OP, 0) is assumed to be a condition code register (integer or
7003 floating point) and its mode specifies what kind of comparison we made.
7005 DEST is the destination insn (i.e. the label), INSN is the source.
7007 REVERSED is nonzero if we should reverse the sense of the comparison.
7009 ANNUL is nonzero if we should generate an annulling branch. */
7012 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7015 static char string
[64];
7016 enum rtx_code code
= GET_CODE (op
);
7017 rtx cc_reg
= XEXP (op
, 0);
7018 enum machine_mode mode
= GET_MODE (cc_reg
);
7019 const char *labelno
, *branch
;
7020 int spaces
= 8, far
;
7023 /* v9 branches are limited to +-1MB. If it is too far away,
7036 fbne,a,pn %fcc2, .LC29
7044 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7047 /* Reversal of FP compares takes care -- an ordered compare
7048 becomes an unordered compare and vice versa. */
7049 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7050 code
= reverse_condition_maybe_unordered (code
);
7052 code
= reverse_condition (code
);
7055 /* Start by writing the branch condition. */
7056 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7107 /* ??? !v9: FP branches cannot be preceded by another floating point
7108 insn. Because there is currently no concept of pre-delay slots,
7109 we can fix this only by always emitting a nop before a floating
7114 strcpy (string
, "nop\n\t");
7115 strcat (string
, branch
);
7128 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7140 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7161 strcpy (string
, branch
);
7163 spaces
-= strlen (branch
);
7164 p
= strchr (string
, '\0');
7166 /* Now add the annulling, the label, and a possible noop. */
7179 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7181 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7182 - INSN_ADDRESSES (INSN_UID (insn
)));
7183 /* Leave some instructions for "slop". */
7184 if (delta
< -260000 || delta
>= 260000)
7188 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7190 static char v9_fcc_labelno
[] = "%%fccX, ";
7191 /* Set the char indicating the number of the fcc reg to use. */
7192 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7193 labelno
= v9_fcc_labelno
;
7196 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7200 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7202 labelno
= "%%xcc, ";
7207 labelno
= "%%icc, ";
7212 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7215 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7228 strcpy (p
, labelno
);
7229 p
= strchr (p
, '\0');
7232 strcpy (p
, ".+12\n\t nop\n\tb\t");
7233 /* Skip the next insn if requested or
7234 if we know that it will be a nop. */
7235 if (annul
|| ! final_sequence
)
7249 /* Emit a library call comparison between floating point X and Y.
7250 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7251 Return the new operator to be used in the comparison sequence.
7253 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7254 values as arguments instead of the TFmode registers themselves,
7255 that's why we cannot call emit_float_lib_cmp. */
7258 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7261 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7262 enum machine_mode mode
;
7263 enum rtx_code new_comparison
;
7268 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7272 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7276 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7280 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7284 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7288 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7299 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7312 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7313 emit_move_insn (slot0
, x
);
7320 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7321 emit_move_insn (slot1
, y
);
7324 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7325 emit_library_call (libfunc
, LCT_NORMAL
,
7327 XEXP (slot0
, 0), Pmode
,
7328 XEXP (slot1
, 0), Pmode
);
7333 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7334 emit_library_call (libfunc
, LCT_NORMAL
,
7336 x
, TFmode
, y
, TFmode
);
7341 /* Immediately move the result of the libcall into a pseudo
7342 register so reload doesn't clobber the value if it needs
7343 the return register for a spill reg. */
7344 result
= gen_reg_rtx (mode
);
7345 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7350 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7353 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7354 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7357 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7358 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7360 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7362 tem
= gen_reg_rtx (mode
);
7364 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7366 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7367 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7370 tem
= gen_reg_rtx (mode
);
7372 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7374 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7375 tem2
= gen_reg_rtx (mode
);
7377 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7379 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7380 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7381 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7387 /* Generate an unsigned DImode to FP conversion. This is the same code
7388 optabs would emit if we didn't have TFmode patterns. */
7391 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7393 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7396 in
= force_reg (DImode
, operands
[1]);
7397 neglab
= gen_label_rtx ();
7398 donelab
= gen_label_rtx ();
7399 i0
= gen_reg_rtx (DImode
);
7400 i1
= gen_reg_rtx (DImode
);
7401 f0
= gen_reg_rtx (mode
);
7403 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7405 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7406 emit_jump_insn (gen_jump (donelab
));
7409 emit_label (neglab
);
7411 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7412 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7413 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7414 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7415 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7417 emit_label (donelab
);
7420 /* Generate an FP to unsigned DImode conversion. This is the same code
7421 optabs would emit if we didn't have TFmode patterns. */
7424 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7426 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7429 in
= force_reg (mode
, operands
[1]);
7430 neglab
= gen_label_rtx ();
7431 donelab
= gen_label_rtx ();
7432 i0
= gen_reg_rtx (DImode
);
7433 i1
= gen_reg_rtx (DImode
);
7434 limit
= gen_reg_rtx (mode
);
7435 f0
= gen_reg_rtx (mode
);
7437 emit_move_insn (limit
,
7438 CONST_DOUBLE_FROM_REAL_VALUE (
7439 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7440 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7442 emit_insn (gen_rtx_SET (VOIDmode
,
7444 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7445 emit_jump_insn (gen_jump (donelab
));
7448 emit_label (neglab
);
7450 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7451 emit_insn (gen_rtx_SET (VOIDmode
,
7453 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7454 emit_insn (gen_movdi (i1
, const1_rtx
));
7455 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7456 emit_insn (gen_xordi3 (out
, i0
, i1
));
7458 emit_label (donelab
);
7461 /* Return the string to output a conditional branch to LABEL, testing
7462 register REG. LABEL is the operand number of the label; REG is the
7463 operand number of the reg. OP is the conditional expression. The mode
7464 of REG says what kind of comparison we made.
7466 DEST is the destination insn (i.e. the label), INSN is the source.
7468 REVERSED is nonzero if we should reverse the sense of the comparison.
7470 ANNUL is nonzero if we should generate an annulling branch. */
7473 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7474 int annul
, rtx insn
)
7476 static char string
[64];
7477 enum rtx_code code
= GET_CODE (op
);
7478 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7483 /* branch on register are limited to +-128KB. If it is too far away,
7496 brgez,a,pn %o1, .LC29
7502 ba,pt %xcc, .LC29 */
7504 far
= get_attr_length (insn
) >= 3;
7506 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7508 code
= reverse_condition (code
);
7510 /* Only 64 bit versions of these instructions exist. */
7511 gcc_assert (mode
== DImode
);
7513 /* Start by writing the branch condition. */
7518 strcpy (string
, "brnz");
7522 strcpy (string
, "brz");
7526 strcpy (string
, "brgez");
7530 strcpy (string
, "brlz");
7534 strcpy (string
, "brlez");
7538 strcpy (string
, "brgz");
7545 p
= strchr (string
, '\0');
7547 /* Now add the annulling, reg, label, and nop. */
7554 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7557 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7562 *p
= p
< string
+ 8 ? '\t' : ' ';
7570 int veryfar
= 1, delta
;
7572 if (INSN_ADDRESSES_SET_P ())
7574 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7575 - INSN_ADDRESSES (INSN_UID (insn
)));
7576 /* Leave some instructions for "slop". */
7577 if (delta
>= -260000 && delta
< 260000)
7581 strcpy (p
, ".+12\n\t nop\n\t");
7582 /* Skip the next insn if requested or
7583 if we know that it will be a nop. */
7584 if (annul
|| ! final_sequence
)
7594 strcpy (p
, "ba,pt\t%%xcc, ");
7608 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7609 Such instructions cannot be used in the delay slot of return insn on v9.
7610 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7614 epilogue_renumber (register rtx
*where
, int test
)
7616 register const char *fmt
;
7618 register enum rtx_code code
;
7623 code
= GET_CODE (*where
);
7628 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7630 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7631 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7639 /* Do not replace the frame pointer with the stack pointer because
7640 it can cause the delayed instruction to load below the stack.
7641 This occurs when instructions like:
7643 (set (reg/i:SI 24 %i0)
7644 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7645 (const_int -20 [0xffffffec])) 0))
7647 are in the return delayed slot. */
7649 if (GET_CODE (XEXP (*where
, 0)) == REG
7650 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7651 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7652 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7657 if (SPARC_STACK_BIAS
7658 && GET_CODE (XEXP (*where
, 0)) == REG
7659 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7667 fmt
= GET_RTX_FORMAT (code
);
7669 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7674 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7675 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7678 else if (fmt
[i
] == 'e'
7679 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7685 /* Leaf functions and non-leaf functions have different needs. */
7688 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7691 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7693 static const int *const reg_alloc_orders
[] = {
7694 reg_leaf_alloc_order
,
7695 reg_nonleaf_alloc_order
};
7698 order_regs_for_local_alloc (void)
7700 static int last_order_nonleaf
= 1;
7702 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
7704 last_order_nonleaf
= !last_order_nonleaf
;
7705 memcpy ((char *) reg_alloc_order
,
7706 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7707 FIRST_PSEUDO_REGISTER
* sizeof (int));
7711 /* Return 1 if REG and MEM are legitimate enough to allow the various
7712 mem<-->reg splits to be run. */
7715 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7717 /* Punt if we are here by mistake. */
7718 gcc_assert (reload_completed
);
7720 /* We must have an offsettable memory reference. */
7721 if (! offsettable_memref_p (mem
))
7724 /* If we have legitimate args for ldd/std, we do not want
7725 the split to happen. */
7726 if ((REGNO (reg
) % 2) == 0
7727 && mem_min_alignment (mem
, 8))
7734 /* Return 1 if x and y are some kind of REG and they refer to
7735 different hard registers. This test is guaranteed to be
7736 run after reload. */
7739 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7741 if (GET_CODE (x
) != REG
)
7743 if (GET_CODE (y
) != REG
)
7745 if (REGNO (x
) == REGNO (y
))
7750 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7751 This makes them candidates for using ldd and std insns.
7753 Note reg1 and reg2 *must* be hard registers. */
7756 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7758 /* We might have been passed a SUBREG. */
7759 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7762 if (REGNO (reg1
) % 2 != 0)
7765 /* Integer ldd is deprecated in SPARC V9 */
7766 if (TARGET_V9
&& REGNO (reg1
) < 32)
7769 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7772 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7775 This can only happen when addr1 and addr2, the addresses in mem1
7776 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7777 addr1 must also be aligned on a 64-bit boundary.
7779 Also iff dependent_reg_rtx is not null it should not be used to
7780 compute the address for mem1, i.e. we cannot optimize a sequence
7792 But, note that the transformation from:
7797 is perfectly fine. Thus, the peephole2 patterns always pass us
7798 the destination register of the first load, never the second one.
7800 For stores we don't have a similar problem, so dependent_reg_rtx is
7804 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7808 HOST_WIDE_INT offset1
;
7810 /* The mems cannot be volatile. */
7811 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7814 /* MEM1 should be aligned on a 64-bit boundary. */
7815 if (MEM_ALIGN (mem1
) < 64)
7818 addr1
= XEXP (mem1
, 0);
7819 addr2
= XEXP (mem2
, 0);
7821 /* Extract a register number and offset (if used) from the first addr. */
7822 if (GET_CODE (addr1
) == PLUS
)
7824 /* If not a REG, return zero. */
7825 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7829 reg1
= REGNO (XEXP (addr1
, 0));
7830 /* The offset must be constant! */
7831 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7833 offset1
= INTVAL (XEXP (addr1
, 1));
7836 else if (GET_CODE (addr1
) != REG
)
7840 reg1
= REGNO (addr1
);
7841 /* This was a simple (mem (reg)) expression. Offset is 0. */
7845 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7846 if (GET_CODE (addr2
) != PLUS
)
7849 if (GET_CODE (XEXP (addr2
, 0)) != REG
7850 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7853 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7856 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7859 /* The first offset must be evenly divisible by 8 to ensure the
7860 address is 64 bit aligned. */
7861 if (offset1
% 8 != 0)
7864 /* The offset for the second addr must be 4 more than the first addr. */
7865 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7868 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7873 /* Return 1 if reg is a pseudo, or is the first register in
7874 a hard register pair. This makes it suitable for use in
7875 ldd and std insns. */
7878 register_ok_for_ldd (rtx reg
)
7880 /* We might have been passed a SUBREG. */
7884 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7885 return (REGNO (reg
) % 2 == 0);
7890 /* Return 1 if OP is a memory whose address is known to be
7891 aligned to 8-byte boundary, or a pseudo during reload.
7892 This makes it suitable for use in ldd and std insns. */
7895 memory_ok_for_ldd (rtx op
)
7899 /* In 64-bit mode, we assume that the address is word-aligned. */
7900 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
7903 if ((reload_in_progress
|| reload_completed
)
7904 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
7907 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7909 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
7918 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7921 sparc_print_operand_punct_valid_p (unsigned char code
)
7934 /* Implement TARGET_PRINT_OPERAND.
7935 Print operand X (an rtx) in assembler syntax to file FILE.
7936 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7937 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7940 sparc_print_operand (FILE *file
, rtx x
, int code
)
7945 /* Output an insn in a delay slot. */
7947 sparc_indent_opcode
= 1;
7949 fputs ("\n\t nop", file
);
7952 /* Output an annul flag if there's nothing for the delay slot and we
7953 are optimizing. This is always used with '(' below.
7954 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7955 this is a dbx bug. So, we only do this when optimizing.
7956 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7957 Always emit a nop in case the next instruction is a branch. */
7958 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7962 /* Output a 'nop' if there's nothing for the delay slot and we are
7963 not optimizing. This is always used with '*' above. */
7964 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7965 fputs ("\n\t nop", file
);
7966 else if (final_sequence
)
7967 sparc_indent_opcode
= 1;
7970 /* Output the right displacement from the saved PC on function return.
7971 The caller may have placed an "unimp" insn immediately after the call
7972 so we have to account for it. This insn is used in the 32-bit ABI
7973 when calling a function that returns a non zero-sized structure. The
7974 64-bit ABI doesn't have it. Be careful to have this test be the same
7975 as that for the call. The exception is when sparc_std_struct_return
7976 is enabled, the psABI is followed exactly and the adjustment is made
7977 by the code in sparc_struct_value_rtx. The call emitted is the same
7978 when sparc_std_struct_return is enabled. */
7980 && cfun
->returns_struct
7981 && !sparc_std_struct_return
7982 && DECL_SIZE (DECL_RESULT (current_function_decl
))
7983 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7985 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7991 /* Output the Embedded Medium/Anywhere code model base register. */
7992 fputs (EMBMEDANY_BASE_REG
, file
);
7995 /* Print some local dynamic TLS name. */
7996 assemble_name (file
, get_some_local_dynamic_name ());
8000 /* Adjust the operand to take into account a RESTORE operation. */
8001 if (GET_CODE (x
) == CONST_INT
)
8003 else if (GET_CODE (x
) != REG
)
8004 output_operand_lossage ("invalid %%Y operand");
8005 else if (REGNO (x
) < 8)
8006 fputs (reg_names
[REGNO (x
)], file
);
8007 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
8008 fputs (reg_names
[REGNO (x
)-16], file
);
8010 output_operand_lossage ("invalid %%Y operand");
8013 /* Print out the low order register name of a register pair. */
8014 if (WORDS_BIG_ENDIAN
)
8015 fputs (reg_names
[REGNO (x
)+1], file
);
8017 fputs (reg_names
[REGNO (x
)], file
);
8020 /* Print out the high order register name of a register pair. */
8021 if (WORDS_BIG_ENDIAN
)
8022 fputs (reg_names
[REGNO (x
)], file
);
8024 fputs (reg_names
[REGNO (x
)+1], file
);
8027 /* Print out the second register name of a register pair or quad.
8028 I.e., R (%o0) => %o1. */
8029 fputs (reg_names
[REGNO (x
)+1], file
);
8032 /* Print out the third register name of a register quad.
8033 I.e., S (%o0) => %o2. */
8034 fputs (reg_names
[REGNO (x
)+2], file
);
8037 /* Print out the fourth register name of a register quad.
8038 I.e., T (%o0) => %o3. */
8039 fputs (reg_names
[REGNO (x
)+3], file
);
8042 /* Print a condition code register. */
8043 if (REGNO (x
) == SPARC_ICC_REG
)
8045 /* We don't handle CC[X]_NOOVmode because they're not supposed
8047 if (GET_MODE (x
) == CCmode
)
8048 fputs ("%icc", file
);
8049 else if (GET_MODE (x
) == CCXmode
)
8050 fputs ("%xcc", file
);
8055 /* %fccN register */
8056 fputs (reg_names
[REGNO (x
)], file
);
8059 /* Print the operand's address only. */
8060 output_address (XEXP (x
, 0));
8063 /* In this case we need a register. Use %g0 if the
8064 operand is const0_rtx. */
8066 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
8068 fputs ("%g0", file
);
8075 switch (GET_CODE (x
))
8077 case IOR
: fputs ("or", file
); break;
8078 case AND
: fputs ("and", file
); break;
8079 case XOR
: fputs ("xor", file
); break;
8080 default: output_operand_lossage ("invalid %%A operand");
8085 switch (GET_CODE (x
))
8087 case IOR
: fputs ("orn", file
); break;
8088 case AND
: fputs ("andn", file
); break;
8089 case XOR
: fputs ("xnor", file
); break;
8090 default: output_operand_lossage ("invalid %%B operand");
8094 /* These are used by the conditional move instructions. */
8098 enum rtx_code rc
= GET_CODE (x
);
8102 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
8103 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8104 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
8106 rc
= reverse_condition (GET_CODE (x
));
8110 case NE
: fputs ("ne", file
); break;
8111 case EQ
: fputs ("e", file
); break;
8112 case GE
: fputs ("ge", file
); break;
8113 case GT
: fputs ("g", file
); break;
8114 case LE
: fputs ("le", file
); break;
8115 case LT
: fputs ("l", file
); break;
8116 case GEU
: fputs ("geu", file
); break;
8117 case GTU
: fputs ("gu", file
); break;
8118 case LEU
: fputs ("leu", file
); break;
8119 case LTU
: fputs ("lu", file
); break;
8120 case LTGT
: fputs ("lg", file
); break;
8121 case UNORDERED
: fputs ("u", file
); break;
8122 case ORDERED
: fputs ("o", file
); break;
8123 case UNLT
: fputs ("ul", file
); break;
8124 case UNLE
: fputs ("ule", file
); break;
8125 case UNGT
: fputs ("ug", file
); break;
8126 case UNGE
: fputs ("uge", file
); break;
8127 case UNEQ
: fputs ("ue", file
); break;
8128 default: output_operand_lossage (code
== 'c'
8129 ? "invalid %%c operand"
8130 : "invalid %%C operand");
8135 /* These are used by the movr instruction pattern. */
8139 enum rtx_code rc
= (code
== 'd'
8140 ? reverse_condition (GET_CODE (x
))
8144 case NE
: fputs ("ne", file
); break;
8145 case EQ
: fputs ("e", file
); break;
8146 case GE
: fputs ("gez", file
); break;
8147 case LT
: fputs ("lz", file
); break;
8148 case LE
: fputs ("lez", file
); break;
8149 case GT
: fputs ("gz", file
); break;
8150 default: output_operand_lossage (code
== 'd'
8151 ? "invalid %%d operand"
8152 : "invalid %%D operand");
8159 /* Print a sign-extended character. */
8160 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8161 fprintf (file
, "%d", i
);
8166 /* Operand must be a MEM; write its address. */
8167 if (GET_CODE (x
) != MEM
)
8168 output_operand_lossage ("invalid %%f operand");
8169 output_address (XEXP (x
, 0));
8174 /* Print a sign-extended 32-bit value. */
8176 if (GET_CODE(x
) == CONST_INT
)
8178 else if (GET_CODE(x
) == CONST_DOUBLE
)
8179 i
= CONST_DOUBLE_LOW (x
);
8182 output_operand_lossage ("invalid %%s operand");
8185 i
= trunc_int_for_mode (i
, SImode
);
8186 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8191 /* Do nothing special. */
8195 /* Undocumented flag. */
8196 output_operand_lossage ("invalid operand output code");
8199 if (GET_CODE (x
) == REG
)
8200 fputs (reg_names
[REGNO (x
)], file
);
8201 else if (GET_CODE (x
) == MEM
)
8204 /* Poor Sun assembler doesn't understand absolute addressing. */
8205 if (CONSTANT_P (XEXP (x
, 0)))
8206 fputs ("%g0+", file
);
8207 output_address (XEXP (x
, 0));
8210 else if (GET_CODE (x
) == HIGH
)
8212 fputs ("%hi(", file
);
8213 output_addr_const (file
, XEXP (x
, 0));
8216 else if (GET_CODE (x
) == LO_SUM
)
8218 sparc_print_operand (file
, XEXP (x
, 0), 0);
8219 if (TARGET_CM_MEDMID
)
8220 fputs ("+%l44(", file
);
8222 fputs ("+%lo(", file
);
8223 output_addr_const (file
, XEXP (x
, 1));
8226 else if (GET_CODE (x
) == CONST_DOUBLE
8227 && (GET_MODE (x
) == VOIDmode
8228 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8230 if (CONST_DOUBLE_HIGH (x
) == 0)
8231 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8232 else if (CONST_DOUBLE_HIGH (x
) == -1
8233 && CONST_DOUBLE_LOW (x
) < 0)
8234 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8236 output_operand_lossage ("long long constant not a valid immediate operand");
8238 else if (GET_CODE (x
) == CONST_DOUBLE
)
8239 output_operand_lossage ("floating point constant not a valid immediate operand");
8240 else { output_addr_const (file
, x
); }
8243 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8246 sparc_print_operand_address (FILE *file
, rtx x
)
8248 register rtx base
, index
= 0;
8250 register rtx addr
= x
;
8253 fputs (reg_names
[REGNO (addr
)], file
);
8254 else if (GET_CODE (addr
) == PLUS
)
8256 if (CONST_INT_P (XEXP (addr
, 0)))
8257 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8258 else if (CONST_INT_P (XEXP (addr
, 1)))
8259 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8261 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8262 if (GET_CODE (base
) == LO_SUM
)
8264 gcc_assert (USE_AS_OFFSETABLE_LO10
8266 && ! TARGET_CM_MEDMID
);
8267 output_operand (XEXP (base
, 0), 0);
8268 fputs ("+%lo(", file
);
8269 output_address (XEXP (base
, 1));
8270 fprintf (file
, ")+%d", offset
);
8274 fputs (reg_names
[REGNO (base
)], file
);
8276 fprintf (file
, "%+d", offset
);
8277 else if (REG_P (index
))
8278 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8279 else if (GET_CODE (index
) == SYMBOL_REF
8280 || GET_CODE (index
) == LABEL_REF
8281 || GET_CODE (index
) == CONST
)
8282 fputc ('+', file
), output_addr_const (file
, index
);
8283 else gcc_unreachable ();
8286 else if (GET_CODE (addr
) == MINUS
8287 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8289 output_addr_const (file
, XEXP (addr
, 0));
8291 output_addr_const (file
, XEXP (addr
, 1));
8292 fputs ("-.)", file
);
8294 else if (GET_CODE (addr
) == LO_SUM
)
8296 output_operand (XEXP (addr
, 0), 0);
8297 if (TARGET_CM_MEDMID
)
8298 fputs ("+%l44(", file
);
8300 fputs ("+%lo(", file
);
8301 output_address (XEXP (addr
, 1));
8305 && GET_CODE (addr
) == CONST
8306 && GET_CODE (XEXP (addr
, 0)) == MINUS
8307 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8308 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8309 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8311 addr
= XEXP (addr
, 0);
8312 output_addr_const (file
, XEXP (addr
, 0));
8313 /* Group the args of the second CONST in parenthesis. */
8315 /* Skip past the second CONST--it does nothing for us. */
8316 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8317 /* Close the parenthesis. */
8322 output_addr_const (file
, addr
);
8326 /* Target hook for assembling integer objects. The sparc version has
8327 special handling for aligned DI-mode objects. */
8330 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8332 /* ??? We only output .xword's for symbols and only then in environments
8333 where the assembler can handle them. */
8334 if (aligned_p
&& size
== 8
8335 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8339 assemble_integer_with_op ("\t.xword\t", x
);
8344 assemble_aligned_integer (4, const0_rtx
);
8345 assemble_aligned_integer (4, x
);
8349 return default_assemble_integer (x
, size
, aligned_p
);
8352 /* Return the value of a code used in the .proc pseudo-op that says
8353 what kind of result this function returns. For non-C types, we pick
8354 the closest C type. */
8356 #ifndef SHORT_TYPE_SIZE
8357 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8360 #ifndef INT_TYPE_SIZE
8361 #define INT_TYPE_SIZE BITS_PER_WORD
8364 #ifndef LONG_TYPE_SIZE
8365 #define LONG_TYPE_SIZE BITS_PER_WORD
8368 #ifndef LONG_LONG_TYPE_SIZE
8369 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8372 #ifndef FLOAT_TYPE_SIZE
8373 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8376 #ifndef DOUBLE_TYPE_SIZE
8377 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8380 #ifndef LONG_DOUBLE_TYPE_SIZE
8381 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8385 sparc_type_code (register tree type
)
8387 register unsigned long qualifiers
= 0;
8388 register unsigned shift
;
8390 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8391 setting more, since some assemblers will give an error for this. Also,
8392 we must be careful to avoid shifts of 32 bits or more to avoid getting
8393 unpredictable results. */
8395 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8397 switch (TREE_CODE (type
))
8403 qualifiers
|= (3 << shift
);
8408 qualifiers
|= (2 << shift
);
8412 case REFERENCE_TYPE
:
8414 qualifiers
|= (1 << shift
);
8418 return (qualifiers
| 8);
8421 case QUAL_UNION_TYPE
:
8422 return (qualifiers
| 9);
8425 return (qualifiers
| 10);
8428 return (qualifiers
| 16);
8431 /* If this is a range type, consider it to be the underlying
8433 if (TREE_TYPE (type
) != 0)
8436 /* Carefully distinguish all the standard types of C,
8437 without messing up if the language is not C. We do this by
8438 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8439 look at both the names and the above fields, but that's redundant.
8440 Any type whose size is between two C types will be considered
8441 to be the wider of the two types. Also, we do not have a
8442 special code to use for "long long", so anything wider than
8443 long is treated the same. Note that we can't distinguish
8444 between "int" and "long" in this code if they are the same
8445 size, but that's fine, since neither can the assembler. */
8447 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8448 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8450 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8451 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8453 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8454 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8457 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8460 /* If this is a range type, consider it to be the underlying
8462 if (TREE_TYPE (type
) != 0)
8465 /* Carefully distinguish all the standard types of C,
8466 without messing up if the language is not C. */
8468 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8469 return (qualifiers
| 6);
8472 return (qualifiers
| 7);
8474 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8475 /* ??? We need to distinguish between double and float complex types,
8476 but I don't know how yet because I can't reach this code from
8477 existing front-ends. */
8478 return (qualifiers
| 7); /* Who knows? */
8481 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8487 gcc_unreachable (); /* Not a type! */
8494 /* Nested function support. */
8496 /* Emit RTL insns to initialize the variable parts of a trampoline.
8497 FNADDR is an RTX for the address of the function's pure code.
8498 CXT is an RTX for the static chain value for the function.
8500 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8501 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8502 (to store insns). This is a bit excessive. Perhaps a different
8503 mechanism would be better here.
8505 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8508 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8510 /* SPARC 32-bit trampoline:
8513 sethi %hi(static), %g2
8515 or %g2, %lo(static), %g2
8517 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8518 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8522 (adjust_address (m_tramp
, SImode
, 0),
8523 expand_binop (SImode
, ior_optab
,
8524 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8525 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8526 NULL_RTX
, 1, OPTAB_DIRECT
));
8529 (adjust_address (m_tramp
, SImode
, 4),
8530 expand_binop (SImode
, ior_optab
,
8531 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8532 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8533 NULL_RTX
, 1, OPTAB_DIRECT
));
8536 (adjust_address (m_tramp
, SImode
, 8),
8537 expand_binop (SImode
, ior_optab
,
8538 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8539 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8540 NULL_RTX
, 1, OPTAB_DIRECT
));
8543 (adjust_address (m_tramp
, SImode
, 12),
8544 expand_binop (SImode
, ior_optab
,
8545 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8546 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8547 NULL_RTX
, 1, OPTAB_DIRECT
));
8549 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8550 aligned on a 16 byte boundary so one flush clears it all. */
8551 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8552 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8553 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8554 && sparc_cpu
!= PROCESSOR_NIAGARA
8555 && sparc_cpu
!= PROCESSOR_NIAGARA2
8556 && sparc_cpu
!= PROCESSOR_NIAGARA3
8557 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8558 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8560 /* Call __enable_execute_stack after writing onto the stack to make sure
8561 the stack address is accessible. */
8562 #ifdef HAVE_ENABLE_EXECUTE_STACK
8563 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8564 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8569 /* The 64-bit version is simpler because it makes more sense to load the
8570 values as "immediate" data out of the trampoline. It's also easier since
8571 we can read the PC without clobbering a register. */
8574 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8576 /* SPARC 64-bit trampoline:
8585 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8586 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8587 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8588 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8589 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8590 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8591 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8592 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8593 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8594 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8595 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8597 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8598 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8599 && sparc_cpu
!= PROCESSOR_NIAGARA
8600 && sparc_cpu
!= PROCESSOR_NIAGARA2
8601 && sparc_cpu
!= PROCESSOR_NIAGARA3
8602 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8603 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8605 /* Call __enable_execute_stack after writing onto the stack to make sure
8606 the stack address is accessible. */
8607 #ifdef HAVE_ENABLE_EXECUTE_STACK
8608 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8609 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8613 /* Worker for TARGET_TRAMPOLINE_INIT. */
8616 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8618 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8619 cxt
= force_reg (Pmode
, cxt
);
8621 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8623 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8626 /* Adjust the cost of a scheduling dependency. Return the new cost of
8627 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8630 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8632 enum attr_type insn_type
;
8634 if (! recog_memoized (insn
))
8637 insn_type
= get_attr_type (insn
);
8639 if (REG_NOTE_KIND (link
) == 0)
8641 /* Data dependency; DEP_INSN writes a register that INSN reads some
8644 /* if a load, then the dependence must be on the memory address;
8645 add an extra "cycle". Note that the cost could be two cycles
8646 if the reg was written late in an instruction group; we ca not tell
8648 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
8651 /* Get the delay only if the address of the store is the dependence. */
8652 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
8654 rtx pat
= PATTERN(insn
);
8655 rtx dep_pat
= PATTERN (dep_insn
);
8657 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8658 return cost
; /* This should not happen! */
8660 /* The dependency between the two instructions was on the data that
8661 is being stored. Assume that this implies that the address of the
8662 store is not dependent. */
8663 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8666 return cost
+ 3; /* An approximation. */
8669 /* A shift instruction cannot receive its data from an instruction
8670 in the same cycle; add a one cycle penalty. */
8671 if (insn_type
== TYPE_SHIFT
)
8672 return cost
+ 3; /* Split before cascade into shift. */
8676 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8677 INSN writes some cycles later. */
8679 /* These are only significant for the fpu unit; writing a fp reg before
8680 the fpu has finished with it stalls the processor. */
8682 /* Reusing an integer register causes no problems. */
8683 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8691 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8693 enum attr_type insn_type
, dep_type
;
8694 rtx pat
= PATTERN(insn
);
8695 rtx dep_pat
= PATTERN (dep_insn
);
8697 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
8700 insn_type
= get_attr_type (insn
);
8701 dep_type
= get_attr_type (dep_insn
);
8703 switch (REG_NOTE_KIND (link
))
8706 /* Data dependency; DEP_INSN writes a register that INSN reads some
8713 /* Get the delay iff the address of the store is the dependence. */
8714 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8717 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8724 /* If a load, then the dependence must be on the memory address. If
8725 the addresses aren't equal, then it might be a false dependency */
8726 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
8728 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
8729 || GET_CODE (SET_DEST (dep_pat
)) != MEM
8730 || GET_CODE (SET_SRC (pat
)) != MEM
8731 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
8732 XEXP (SET_SRC (pat
), 0)))
8740 /* Compare to branch latency is 0. There is no benefit from
8741 separating compare and branch. */
8742 if (dep_type
== TYPE_COMPARE
)
8744 /* Floating point compare to branch latency is less than
8745 compare to conditional move. */
8746 if (dep_type
== TYPE_FPCMP
)
8755 /* Anti-dependencies only penalize the fpu unit. */
8756 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8768 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
8772 case PROCESSOR_SUPERSPARC
:
8773 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
8775 case PROCESSOR_HYPERSPARC
:
8776 case PROCESSOR_SPARCLITE86X
:
8777 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8786 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8787 int sched_verbose ATTRIBUTE_UNUSED
,
8788 int max_ready ATTRIBUTE_UNUSED
)
8792 sparc_use_sched_lookahead (void)
8794 if (sparc_cpu
== PROCESSOR_NIAGARA
8795 || sparc_cpu
== PROCESSOR_NIAGARA2
8796 || sparc_cpu
== PROCESSOR_NIAGARA3
8797 || sparc_cpu
== PROCESSOR_NIAGARA4
)
8799 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8800 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8802 if ((1 << sparc_cpu
) &
8803 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8804 (1 << PROCESSOR_SPARCLITE86X
)))
8810 sparc_issue_rate (void)
8814 case PROCESSOR_NIAGARA
:
8815 case PROCESSOR_NIAGARA2
:
8816 case PROCESSOR_NIAGARA3
:
8817 case PROCESSOR_NIAGARA4
:
8821 /* Assume V9 processors are capable of at least dual-issue. */
8823 case PROCESSOR_SUPERSPARC
:
8825 case PROCESSOR_HYPERSPARC
:
8826 case PROCESSOR_SPARCLITE86X
:
8828 case PROCESSOR_ULTRASPARC
:
8829 case PROCESSOR_ULTRASPARC3
:
8835 set_extends (rtx insn
)
8837 register rtx pat
= PATTERN (insn
);
8839 switch (GET_CODE (SET_SRC (pat
)))
8841 /* Load and some shift instructions zero extend. */
8844 /* sethi clears the high bits */
8846 /* LO_SUM is used with sethi. sethi cleared the high
8847 bits and the values used with lo_sum are positive */
8849 /* Store flag stores 0 or 1 */
8859 rtx op0
= XEXP (SET_SRC (pat
), 0);
8860 rtx op1
= XEXP (SET_SRC (pat
), 1);
8861 if (GET_CODE (op1
) == CONST_INT
)
8862 return INTVAL (op1
) >= 0;
8863 if (GET_CODE (op0
) != REG
)
8865 if (sparc_check_64 (op0
, insn
) == 1)
8867 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8872 rtx op0
= XEXP (SET_SRC (pat
), 0);
8873 rtx op1
= XEXP (SET_SRC (pat
), 1);
8874 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8876 if (GET_CODE (op1
) == CONST_INT
)
8877 return INTVAL (op1
) >= 0;
8878 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8881 return GET_MODE (SET_SRC (pat
)) == SImode
;
8882 /* Positive integers leave the high bits zero. */
8884 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8886 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8889 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8891 return sparc_check_64 (SET_SRC (pat
), insn
);
8897 /* We _ought_ to have only one kind per function, but... */
8898 static GTY(()) rtx sparc_addr_diff_list
;
8899 static GTY(()) rtx sparc_addr_list
;
8902 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8904 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8906 sparc_addr_diff_list
8907 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8909 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8913 sparc_output_addr_vec (rtx vec
)
8915 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8916 int idx
, vlen
= XVECLEN (body
, 0);
8918 #ifdef ASM_OUTPUT_ADDR_VEC_START
8919 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8922 #ifdef ASM_OUTPUT_CASE_LABEL
8923 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8926 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8929 for (idx
= 0; idx
< vlen
; idx
++)
8931 ASM_OUTPUT_ADDR_VEC_ELT
8932 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8935 #ifdef ASM_OUTPUT_ADDR_VEC_END
8936 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8941 sparc_output_addr_diff_vec (rtx vec
)
8943 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8944 rtx base
= XEXP (XEXP (body
, 0), 0);
8945 int idx
, vlen
= XVECLEN (body
, 1);
8947 #ifdef ASM_OUTPUT_ADDR_VEC_START
8948 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8951 #ifdef ASM_OUTPUT_CASE_LABEL
8952 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8955 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8958 for (idx
= 0; idx
< vlen
; idx
++)
8960 ASM_OUTPUT_ADDR_DIFF_ELT
8963 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8964 CODE_LABEL_NUMBER (base
));
8967 #ifdef ASM_OUTPUT_ADDR_VEC_END
8968 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8973 sparc_output_deferred_case_vectors (void)
8978 if (sparc_addr_list
== NULL_RTX
8979 && sparc_addr_diff_list
== NULL_RTX
)
8982 /* Align to cache line in the function's code section. */
8983 switch_to_section (current_function_section ());
8985 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8987 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8989 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8990 sparc_output_addr_vec (XEXP (t
, 0));
8991 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8992 sparc_output_addr_diff_vec (XEXP (t
, 0));
8994 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8997 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8998 unknown. Return 1 if the high bits are zero, -1 if the register is
9001 sparc_check_64 (rtx x
, rtx insn
)
9003 /* If a register is set only once it is safe to ignore insns this
9004 code does not know how to handle. The loop will either recognize
9005 the single set and return the correct value or fail to recognize
9010 gcc_assert (GET_CODE (x
) == REG
);
9012 if (GET_MODE (x
) == DImode
)
9013 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
9015 if (flag_expensive_optimizations
9016 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
9022 insn
= get_last_insn_anywhere ();
9027 while ((insn
= PREV_INSN (insn
)))
9029 switch (GET_CODE (insn
))
9042 rtx pat
= PATTERN (insn
);
9043 if (GET_CODE (pat
) != SET
)
9045 if (rtx_equal_p (x
, SET_DEST (pat
)))
9046 return set_extends (insn
);
9047 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
9048 return set_extends (insn
);
9049 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
9057 /* Returns assembly code to perform a DImode shift using
9058 a 64-bit global or out register on SPARC-V8+. */
9060 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
9062 static char asm_code
[60];
9064 /* The scratch register is only required when the destination
9065 register is not a 64-bit global or out register. */
9066 if (which_alternative
!= 2)
9067 operands
[3] = operands
[0];
9069 /* We can only shift by constants <= 63. */
9070 if (GET_CODE (operands
[2]) == CONST_INT
)
9071 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
9073 if (GET_CODE (operands
[1]) == CONST_INT
)
9075 output_asm_insn ("mov\t%1, %3", operands
);
9079 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
9080 if (sparc_check_64 (operands
[1], insn
) <= 0)
9081 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
9082 output_asm_insn ("or\t%L1, %3, %3", operands
);
9085 strcpy(asm_code
, opcode
);
9087 if (which_alternative
!= 2)
9088 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9090 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9093 /* Output rtl to increment the profiler label LABELNO
9094 for profiling a function entry. */
9097 sparc_profile_hook (int labelno
)
9102 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
9103 if (NO_PROFILE_COUNTERS
)
9105 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
9109 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
9110 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
9111 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
9115 #ifdef TARGET_SOLARIS
9116 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9119 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9120 tree decl ATTRIBUTE_UNUSED
)
9122 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9124 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9128 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9130 if (!(flags
& SECTION_DEBUG
))
9131 fputs (",#alloc", asm_out_file
);
9132 if (flags
& SECTION_WRITE
)
9133 fputs (",#write", asm_out_file
);
9134 if (flags
& SECTION_TLS
)
9135 fputs (",#tls", asm_out_file
);
9136 if (flags
& SECTION_CODE
)
9137 fputs (",#execinstr", asm_out_file
);
9139 /* ??? Handle SECTION_BSS. */
9141 fputc ('\n', asm_out_file
);
9143 #endif /* TARGET_SOLARIS */
9145 /* We do not allow indirect calls to be optimized into sibling calls.
9147 We cannot use sibling calls when delayed branches are disabled
9148 because they will likely require the call delay slot to be filled.
9150 Also, on SPARC 32-bit we cannot emit a sibling call when the
9151 current function returns a structure. This is because the "unimp
9152 after call" convention would cause the callee to return to the
9153 wrong place. The generic code already disallows cases where the
9154 function being called returns a structure.
9156 It may seem strange how this last case could occur. Usually there
9157 is code after the call which jumps to epilogue code which dumps the
9158 return value into the struct return area. That ought to invalidate
9159 the sibling call right? Well, in the C++ case we can end up passing
9160 the pointer to the struct return area to a constructor (which returns
9161 void) and then nothing else happens. Such a sibling call would look
9162 valid without the added check here.
9164 VxWorks PIC PLT entries require the global pointer to be initialized
9165 on entry. We therefore can't emit sibling calls to them. */
9167 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9170 && flag_delayed_branch
9171 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9172 && !(TARGET_VXWORKS_RTP
9174 && !targetm
.binds_local_p (decl
)));
9177 /* libfunc renaming. */
9180 sparc_init_libfuncs (void)
9184 /* Use the subroutines that Sun's library provides for integer
9185 multiply and divide. The `*' prevents an underscore from
9186 being prepended by the compiler. .umul is a little faster
9188 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9189 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9190 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9191 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9192 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9194 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9195 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9196 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9197 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9198 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9199 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9201 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9202 is because with soft-float, the SFmode and DFmode sqrt
9203 instructions will be absent, and the compiler will notice and
9204 try to use the TFmode sqrt instruction for calls to the
9205 builtin function sqrt, but this fails. */
9207 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9209 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9210 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9211 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9212 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9213 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9214 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9216 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9217 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9218 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9219 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9221 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9222 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9223 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9224 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9226 if (DITF_CONVERSION_LIBFUNCS
)
9228 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9229 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9230 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9231 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9234 if (SUN_CONVERSION_LIBFUNCS
)
9236 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9237 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9238 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9239 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9244 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9245 do not exist in the library. Make sure the compiler does not
9246 emit calls to them by accident. (It should always use the
9247 hardware instructions.) */
9248 set_optab_libfunc (smul_optab
, SImode
, 0);
9249 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9250 set_optab_libfunc (udiv_optab
, SImode
, 0);
9251 set_optab_libfunc (smod_optab
, SImode
, 0);
9252 set_optab_libfunc (umod_optab
, SImode
, 0);
9254 if (SUN_INTEGER_MULTIPLY_64
)
9256 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9257 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9258 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9259 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9260 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9263 if (SUN_CONVERSION_LIBFUNCS
)
9265 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9266 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9267 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9268 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9273 static tree
def_builtin(const char *name
, int code
, tree type
)
9275 return add_builtin_function(name
, type
, code
, BUILT_IN_MD
, NULL
,
9279 static tree
def_builtin_const(const char *name
, int code
, tree type
)
9281 tree t
= def_builtin(name
, code
, type
);
9284 TREE_READONLY (t
) = 1;
9289 /* Implement the TARGET_INIT_BUILTINS target hook.
9290 Create builtin functions for special SPARC instructions. */
9293 sparc_init_builtins (void)
9296 sparc_vis_init_builtins ();
9299 /* Create builtin functions for VIS 1.0 instructions. */
9302 sparc_vis_init_builtins (void)
9304 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9305 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9306 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9307 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9308 tree v2si
= build_vector_type (intSI_type_node
, 2);
9309 tree v1si
= build_vector_type (intSI_type_node
, 1);
9311 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9312 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9313 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9314 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9315 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9316 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9317 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9318 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9319 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9320 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9321 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9322 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9323 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
9324 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
9325 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9327 intDI_type_node
, 0);
9328 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
9330 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
9332 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9334 intDI_type_node
, 0);
9335 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
9337 intSI_type_node
, 0);
9338 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9340 intSI_type_node
, 0);
9341 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9343 intDI_type_node
, 0);
9344 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
9347 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
9350 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
9352 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
9354 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
9356 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
9358 tree void_ftype_di
= build_function_type_list (void_type_node
,
9359 intDI_type_node
, 0);
9360 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
9362 tree void_ftype_si
= build_function_type_list (void_type_node
,
9363 intSI_type_node
, 0);
9364 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
9366 float_type_node
, 0);
9367 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
9369 double_type_node
, 0);
9371 /* Packing and expanding vectors. */
9372 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
9374 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9375 v8qi_ftype_v2si_v8qi
);
9376 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9378 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
9380 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9381 v8qi_ftype_v4qi_v4qi
);
9383 /* Multiplications. */
9384 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9385 v4hi_ftype_v4qi_v4hi
);
9386 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9387 v4hi_ftype_v4qi_v2hi
);
9388 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9389 v4hi_ftype_v4qi_v2hi
);
9390 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9391 v4hi_ftype_v8qi_v4hi
);
9392 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9393 v4hi_ftype_v8qi_v4hi
);
9394 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9395 v2si_ftype_v4qi_v2hi
);
9396 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9397 v2si_ftype_v4qi_v2hi
);
9399 /* Data aligning. */
9400 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9401 v4hi_ftype_v4hi_v4hi
);
9402 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9403 v8qi_ftype_v8qi_v8qi
);
9404 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9405 v2si_ftype_v2si_v2si
);
9406 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
9409 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
9411 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
9416 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9418 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
9423 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9425 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
9429 /* Pixel distance. */
9430 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9431 di_ftype_v8qi_v8qi_di
);
9433 /* Edge handling. */
9436 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
9438 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
9440 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
9442 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
9444 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
9446 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
9450 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
9452 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
9454 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
9456 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
9458 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
9460 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
9466 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
9468 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
9470 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
9472 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
9474 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
9476 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
9480 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
9482 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
9484 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
9486 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
9488 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
9490 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
9495 /* Pixel compare. */
9498 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
9499 di_ftype_v4hi_v4hi
);
9500 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
9501 di_ftype_v2si_v2si
);
9502 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
9503 di_ftype_v4hi_v4hi
);
9504 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
9505 di_ftype_v2si_v2si
);
9506 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
9507 di_ftype_v4hi_v4hi
);
9508 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
9509 di_ftype_v2si_v2si
);
9510 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
9511 di_ftype_v4hi_v4hi
);
9512 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
9513 di_ftype_v2si_v2si
);
9517 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
9518 si_ftype_v4hi_v4hi
);
9519 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
9520 si_ftype_v2si_v2si
);
9521 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
9522 si_ftype_v4hi_v4hi
);
9523 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
9524 si_ftype_v2si_v2si
);
9525 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
9526 si_ftype_v4hi_v4hi
);
9527 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
9528 si_ftype_v2si_v2si
);
9529 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
9530 si_ftype_v4hi_v4hi
);
9531 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
9532 si_ftype_v2si_v2si
);
9535 /* Addition and subtraction. */
9536 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
9537 v4hi_ftype_v4hi_v4hi
);
9538 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
9539 v2hi_ftype_v2hi_v2hi
);
9540 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
9541 v2si_ftype_v2si_v2si
);
9542 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
9543 v1si_ftype_v1si_v1si
);
9544 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
9545 v4hi_ftype_v4hi_v4hi
);
9546 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
9547 v2hi_ftype_v2hi_v2hi
);
9548 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
9549 v2si_ftype_v2si_v2si
);
9550 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
9551 v1si_ftype_v1si_v1si
);
9553 /* Three-dimensional array addressing. */
9556 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
9558 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
9560 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
9565 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
9567 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
9569 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
9575 /* Byte mask and shuffle */
9577 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
9580 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
9582 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
9583 v4hi_ftype_v4hi_v4hi
);
9584 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
9585 v8qi_ftype_v8qi_v8qi
);
9586 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
9587 v2si_ftype_v2si_v2si
);
9588 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
9596 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
9598 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
9600 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
9605 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
9607 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
9609 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
9613 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
9614 v4hi_ftype_v4hi_v4hi
);
9616 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
9617 v4hi_ftype_v4hi_v4hi
);
9618 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
9619 v4hi_ftype_v4hi_v4hi
);
9620 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
9621 v4hi_ftype_v4hi_v4hi
);
9622 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
9623 v4hi_ftype_v4hi_v4hi
);
9624 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
9625 v2si_ftype_v2si_v2si
);
9626 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
9627 v2si_ftype_v2si_v2si
);
9628 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
9629 v2si_ftype_v2si_v2si
);
9630 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
9631 v2si_ftype_v2si_v2si
);
9634 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
9635 di_ftype_v8qi_v8qi
);
9637 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
9638 si_ftype_v8qi_v8qi
);
9640 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
9641 v4hi_ftype_v4hi_v4hi
);
9642 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
9644 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
9647 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
9648 v4hi_ftype_v4hi_v4hi
);
9649 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
9650 v2hi_ftype_v2hi_v2hi
);
9651 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
9652 v4hi_ftype_v4hi_v4hi
);
9653 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
9654 v2hi_ftype_v2hi_v2hi
);
9655 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
9656 v2si_ftype_v2si_v2si
);
9657 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
9658 v1si_ftype_v1si_v1si
);
9659 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
9660 v2si_ftype_v2si_v2si
);
9661 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
9662 v1si_ftype_v1si_v1si
);
9666 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
9667 di_ftype_v8qi_v8qi
);
9668 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
9669 di_ftype_v8qi_v8qi
);
9670 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
9671 di_ftype_v8qi_v8qi
);
9672 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
9673 di_ftype_v8qi_v8qi
);
9677 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
9678 si_ftype_v8qi_v8qi
);
9679 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
9680 si_ftype_v8qi_v8qi
);
9681 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
9682 si_ftype_v8qi_v8qi
);
9683 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
9684 si_ftype_v8qi_v8qi
);
9687 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
9689 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
9691 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
9693 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
9695 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
9697 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
9700 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
9702 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
9704 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
9709 /* Handle TARGET_EXPAND_BUILTIN target hook.
9710 Expand builtin functions for sparc intrinsics. */
9713 sparc_expand_builtin (tree exp
, rtx target
,
9714 rtx subtarget ATTRIBUTE_UNUSED
,
9715 enum machine_mode tmode ATTRIBUTE_UNUSED
,
9716 int ignore ATTRIBUTE_UNUSED
)
9719 call_expr_arg_iterator iter
;
9720 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9721 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
9726 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9730 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9732 || GET_MODE (target
) != tmode
9733 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9734 op
[0] = gen_reg_rtx (tmode
);
9738 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9740 const struct insn_operand_data
*insn_op
;
9743 if (arg
== error_mark_node
)
9747 idx
= arg_count
- !nonvoid
;
9748 insn_op
= &insn_data
[icode
].operand
[idx
];
9749 op
[arg_count
] = expand_normal (arg
);
9751 if (insn_op
->mode
== V1DImode
9752 && GET_MODE (op
[arg_count
]) == DImode
)
9753 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
9754 else if (insn_op
->mode
== V1SImode
9755 && GET_MODE (op
[arg_count
]) == SImode
)
9756 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
9758 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
9760 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
9766 pat
= GEN_FCN (icode
) (op
[0]);
9770 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
9772 pat
= GEN_FCN (icode
) (op
[1]);
9775 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
9778 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
9796 sparc_vis_mul8x16 (int e8
, int e16
)
9798 return (e8
* e16
+ 128) / 256;
9801 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9802 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9803 constants. A tree list with the results of the multiplications is returned,
9804 and each element in the list is of INNER_TYPE. */
9807 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
9809 tree n_elts
= NULL_TREE
;
9814 case CODE_FOR_fmul8x16_vis
:
9815 for (; elts0
&& elts1
;
9816 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9819 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9820 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
9821 n_elts
= tree_cons (NULL_TREE
,
9822 build_int_cst (inner_type
, val
),
9827 case CODE_FOR_fmul8x16au_vis
:
9828 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9830 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9833 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9835 n_elts
= tree_cons (NULL_TREE
,
9836 build_int_cst (inner_type
, val
),
9841 case CODE_FOR_fmul8x16al_vis
:
9842 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
9844 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9847 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9849 n_elts
= tree_cons (NULL_TREE
,
9850 build_int_cst (inner_type
, val
),
9859 return nreverse (n_elts
);
9862 /* Handle TARGET_FOLD_BUILTIN target hook.
9863 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9864 result of the function call is ignored. NULL_TREE is returned if the
9865 function could not be folded. */
9868 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
9869 tree
*args
, bool ignore
)
9871 tree arg0
, arg1
, arg2
;
9872 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
9873 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
9877 /* Note that a switch statement instead of the sequence of tests would
9878 be incorrect as many of the CODE_FOR values could be CODE_FOR_nothing
9879 and that would yield multiple alternatives with identical values. */
9880 if (icode
== CODE_FOR_alignaddrsi_vis
9881 || icode
== CODE_FOR_alignaddrdi_vis
9882 || icode
== CODE_FOR_wrgsr_vis
9883 || icode
== CODE_FOR_bmasksi_vis
9884 || icode
== CODE_FOR_bmaskdi_vis
9885 || icode
== CODE_FOR_cmask8si_vis
9886 || icode
== CODE_FOR_cmask8di_vis
9887 || icode
== CODE_FOR_cmask16si_vis
9888 || icode
== CODE_FOR_cmask16di_vis
9889 || icode
== CODE_FOR_cmask32si_vis
9890 || icode
== CODE_FOR_cmask32di_vis
)
9893 return build_zero_cst (rtype
);
9898 case CODE_FOR_fexpand_vis
:
9902 if (TREE_CODE (arg0
) == VECTOR_CST
)
9904 tree inner_type
= TREE_TYPE (rtype
);
9905 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
9906 tree n_elts
= NULL_TREE
;
9908 for (; elts
; elts
= TREE_CHAIN (elts
))
9910 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
9911 n_elts
= tree_cons (NULL_TREE
,
9912 build_int_cst (inner_type
, val
),
9915 return build_vector (rtype
, nreverse (n_elts
));
9919 case CODE_FOR_fmul8x16_vis
:
9920 case CODE_FOR_fmul8x16au_vis
:
9921 case CODE_FOR_fmul8x16al_vis
:
9927 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9929 tree inner_type
= TREE_TYPE (rtype
);
9930 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9931 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9932 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
9935 return build_vector (rtype
, n_elts
);
9939 case CODE_FOR_fpmerge_vis
:
9945 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9947 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9948 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9949 tree n_elts
= NULL_TREE
;
9951 for (; elts0
&& elts1
;
9952 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9954 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
9955 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
9958 return build_vector (rtype
, nreverse (n_elts
));
9962 case CODE_FOR_pdist_vis
:
9970 if (TREE_CODE (arg0
) == VECTOR_CST
9971 && TREE_CODE (arg1
) == VECTOR_CST
9972 && TREE_CODE (arg2
) == INTEGER_CST
)
9975 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
9976 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
9977 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9978 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9980 for (; elts0
&& elts1
;
9981 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9983 unsigned HOST_WIDE_INT
9984 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9985 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9986 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
9987 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
9989 unsigned HOST_WIDE_INT l
;
9992 overflow
|= neg_double (low1
, high1
, &l
, &h
);
9993 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
9995 overflow
|= neg_double (l
, h
, &l
, &h
);
9997 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
10000 gcc_assert (overflow
== 0);
10002 return build_int_cst_wide (rtype
, low
, high
);
10012 /* ??? This duplicates information provided to the compiler by the
10013 ??? scheduler description. Some day, teach genautomata to output
10014 ??? the latencies and then CSE will just use that. */
10017 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
10018 int *total
, bool speed ATTRIBUTE_UNUSED
)
10020 enum machine_mode mode
= GET_MODE (x
);
10021 bool float_mode_p
= FLOAT_MODE_P (mode
);
10026 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
10044 if (GET_MODE (x
) == VOIDmode
10045 && ((CONST_DOUBLE_HIGH (x
) == 0
10046 && CONST_DOUBLE_LOW (x
) < 0x1000)
10047 || (CONST_DOUBLE_HIGH (x
) == -1
10048 && CONST_DOUBLE_LOW (x
) < 0
10049 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
10056 /* If outer-code was a sign or zero extension, a cost
10057 of COSTS_N_INSNS (1) was already added in. This is
10058 why we are subtracting it back out. */
10059 if (outer_code
== ZERO_EXTEND
)
10061 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
10063 else if (outer_code
== SIGN_EXTEND
)
10065 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
10067 else if (float_mode_p
)
10069 *total
= sparc_costs
->float_load
;
10073 *total
= sparc_costs
->int_load
;
10081 *total
= sparc_costs
->float_plusminus
;
10083 *total
= COSTS_N_INSNS (1);
10090 gcc_assert (float_mode_p
);
10091 *total
= sparc_costs
->float_mul
;
10094 if (GET_CODE (sub
) == NEG
)
10095 sub
= XEXP (sub
, 0);
10096 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
10099 if (GET_CODE (sub
) == NEG
)
10100 sub
= XEXP (sub
, 0);
10101 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
10107 *total
= sparc_costs
->float_mul
;
10108 else if (! TARGET_HARD_MUL
)
10109 *total
= COSTS_N_INSNS (25);
10115 if (sparc_costs
->int_mul_bit_factor
)
10119 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
10121 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
10122 for (nbits
= 0; value
!= 0; value
&= value
- 1)
10125 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
10126 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
10128 rtx x1
= XEXP (x
, 1);
10129 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
10130 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
10132 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
10134 for (; value2
!= 0; value2
&= value2
- 1)
10142 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
10143 bit_cost
= COSTS_N_INSNS (bit_cost
);
10146 if (mode
== DImode
)
10147 *total
= sparc_costs
->int_mulX
+ bit_cost
;
10149 *total
= sparc_costs
->int_mul
+ bit_cost
;
10156 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
10165 if (mode
== DFmode
)
10166 *total
= sparc_costs
->float_div_df
;
10168 *total
= sparc_costs
->float_div_sf
;
10172 if (mode
== DImode
)
10173 *total
= sparc_costs
->int_divX
;
10175 *total
= sparc_costs
->int_div
;
10180 if (! float_mode_p
)
10182 *total
= COSTS_N_INSNS (1);
10189 case UNSIGNED_FLOAT
:
10193 case FLOAT_TRUNCATE
:
10194 *total
= sparc_costs
->float_move
;
10198 if (mode
== DFmode
)
10199 *total
= sparc_costs
->float_sqrt_df
;
10201 *total
= sparc_costs
->float_sqrt_sf
;
10206 *total
= sparc_costs
->float_cmp
;
10208 *total
= COSTS_N_INSNS (1);
10213 *total
= sparc_costs
->float_cmove
;
10215 *total
= sparc_costs
->int_cmove
;
10219 /* Handle the NAND vector patterns. */
10220 if (sparc_vector_mode_supported_p (GET_MODE (x
))
10221 && GET_CODE (XEXP (x
, 0)) == NOT
10222 && GET_CODE (XEXP (x
, 1)) == NOT
)
10224 *total
= COSTS_N_INSNS (1);
10235 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
10238 general_or_i64_p (reg_class_t rclass
)
10240 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
10243 /* Implement TARGET_REGISTER_MOVE_COST. */
10246 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10247 reg_class_t from
, reg_class_t to
)
10249 if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
10250 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
))
10251 || from
== FPCC_REGS
10252 || to
== FPCC_REGS
)
10254 if (sparc_cpu
== PROCESSOR_ULTRASPARC
10255 || sparc_cpu
== PROCESSOR_ULTRASPARC3
10256 || sparc_cpu
== PROCESSOR_NIAGARA
10257 || sparc_cpu
== PROCESSOR_NIAGARA2
10258 || sparc_cpu
== PROCESSOR_NIAGARA3
10259 || sparc_cpu
== PROCESSOR_NIAGARA4
)
10268 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
10269 This is achieved by means of a manual dynamic stack space allocation in
10270 the current frame. We make the assumption that SEQ doesn't contain any
10271 function calls, with the possible exception of calls to the GOT helper. */
10274 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
10276 /* We must preserve the lowest 16 words for the register save area. */
10277 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
10278 /* We really need only 2 words of fresh stack space. */
10279 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
10282 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
10283 SPARC_STACK_BIAS
+ offset
));
10285 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
10286 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
10288 emit_insn (gen_rtx_SET (VOIDmode
,
10289 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
10293 emit_insn (gen_rtx_SET (VOIDmode
,
10295 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
10296 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
10297 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
10300 /* Output the assembler code for a thunk function. THUNK_DECL is the
10301 declaration for the thunk function itself, FUNCTION is the decl for
10302 the target function. DELTA is an immediate constant offset to be
10303 added to THIS. If VCALL_OFFSET is nonzero, the word at address
10304 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
10307 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
10308 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10311 rtx this_rtx
, insn
, funexp
;
10312 unsigned int int_arg_first
;
10314 reload_completed
= 1;
10315 epilogue_completed
= 1;
10317 emit_note (NOTE_INSN_PROLOGUE_END
);
10321 sparc_leaf_function_p
= 1;
10323 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10325 else if (flag_delayed_branch
)
10327 /* We will emit a regular sibcall below, so we need to instruct
10328 output_sibcall that we are in a leaf function. */
10329 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
10331 /* This will cause final.c to invoke leaf_renumber_regs so we
10332 must behave as if we were in a not-yet-leafified function. */
10333 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
10337 /* We will emit the sibcall manually below, so we will need to
10338 manually spill non-leaf registers. */
10339 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
10341 /* We really are in a leaf function. */
10342 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10345 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
10346 returns a structure, the structure return pointer is there instead. */
10348 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
10349 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
10351 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
10353 /* Add DELTA. When possible use a plain add, otherwise load it into
10354 a register first. */
10357 rtx delta_rtx
= GEN_INT (delta
);
10359 if (! SPARC_SIMM13_P (delta
))
10361 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10362 emit_move_insn (scratch
, delta_rtx
);
10363 delta_rtx
= scratch
;
10366 /* THIS_RTX += DELTA. */
10367 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
10370 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
10373 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10374 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10376 gcc_assert (vcall_offset
< 0);
10378 /* SCRATCH = *THIS_RTX. */
10379 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
10381 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10382 may not have any available scratch register at this point. */
10383 if (SPARC_SIMM13_P (vcall_offset
))
10385 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10386 else if (! fixed_regs
[5]
10387 /* The below sequence is made up of at least 2 insns,
10388 while the default method may need only one. */
10389 && vcall_offset
< -8192)
10391 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
10392 emit_move_insn (scratch2
, vcall_offset_rtx
);
10393 vcall_offset_rtx
= scratch2
;
10397 rtx increment
= GEN_INT (-4096);
10399 /* VCALL_OFFSET is a negative number whose typical range can be
10400 estimated as -32768..0 in 32-bit mode. In almost all cases
10401 it is therefore cheaper to emit multiple add insns than
10402 spilling and loading the constant into a register (at least
10404 while (! SPARC_SIMM13_P (vcall_offset
))
10406 emit_insn (gen_add2_insn (scratch
, increment
));
10407 vcall_offset
+= 4096;
10409 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
10412 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10413 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
10414 gen_rtx_PLUS (Pmode
,
10416 vcall_offset_rtx
)));
10418 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10419 emit_insn (gen_add2_insn (this_rtx
, scratch
));
10422 /* Generate a tail call to the target function. */
10423 if (! TREE_USED (function
))
10425 assemble_external (function
);
10426 TREE_USED (function
) = 1;
10428 funexp
= XEXP (DECL_RTL (function
), 0);
10430 if (flag_delayed_branch
)
10432 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10433 insn
= emit_call_insn (gen_sibcall (funexp
));
10434 SIBLING_CALL_P (insn
) = 1;
10438 /* The hoops we have to jump through in order to generate a sibcall
10439 without using delay slots... */
10440 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
10444 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
10446 load_got_register (); /* clobbers %o7 */
10447 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
10448 seq
= get_insns ();
10450 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
10452 else if (TARGET_ARCH32
)
10454 emit_insn (gen_rtx_SET (VOIDmode
,
10456 gen_rtx_HIGH (SImode
, funexp
)));
10457 emit_insn (gen_rtx_SET (VOIDmode
,
10459 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
10461 else /* TARGET_ARCH64 */
10463 switch (sparc_cmodel
)
10467 /* The destination can serve as a temporary. */
10468 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
10473 /* The destination cannot serve as a temporary. */
10474 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
10476 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
10477 seq
= get_insns ();
10479 emit_and_preserve (seq
, spill_reg
, 0);
10483 gcc_unreachable ();
10487 emit_jump_insn (gen_indirect_jump (scratch
));
10492 /* Run just enough of rest_of_compilation to get the insns emitted.
10493 There's not really enough bulk here to make other passes such as
10494 instruction scheduling worth while. Note that use_thunk calls
10495 assemble_start_function and assemble_end_function. */
10496 insn
= get_insns ();
10497 insn_locators_alloc ();
10498 shorten_branches (insn
);
10499 final_start_function (insn
, file
, 1);
10500 final (insn
, file
, 1);
10501 final_end_function ();
10503 reload_completed
= 0;
10504 epilogue_completed
= 0;
10507 /* Return true if sparc_output_mi_thunk would be able to output the
10508 assembler code for the thunk function specified by the arguments
10509 it is passed, and false otherwise. */
10511 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
10512 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
10513 HOST_WIDE_INT vcall_offset
,
10514 const_tree function ATTRIBUTE_UNUSED
)
10516 /* Bound the loop used in the default method above. */
10517 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
10520 /* We use the machine specific reorg pass to enable workarounds for errata. */
10527 /* The only erratum we handle for now is that of the AT697F processor. */
10528 if (!sparc_fix_at697f
)
10531 /* We need to have the (essentially) final form of the insn stream in order
10532 to properly detect the various hazards. Run delay slot scheduling. */
10533 if (optimize
> 0 && flag_delayed_branch
)
10534 dbr_schedule (get_insns ());
10536 /* Now look for specific patterns in the insn stream. */
10537 for (insn
= get_insns (); insn
; insn
= next
)
10539 bool insert_nop
= false;
10542 /* Look for a single-word load into an odd-numbered FP register. */
10543 if (NONJUMP_INSN_P (insn
)
10544 && (set
= single_set (insn
)) != NULL_RTX
10545 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
10546 && MEM_P (SET_SRC (set
))
10547 && REG_P (SET_DEST (set
))
10548 && REGNO (SET_DEST (set
)) > 31
10549 && REGNO (SET_DEST (set
)) % 2 != 0)
10551 /* The wrong dependency is on the enclosing double register. */
10552 unsigned int x
= REGNO (SET_DEST (set
)) - 1;
10553 unsigned int src1
, src2
, dest
;
10556 /* If the insn has a delay slot, then it cannot be problematic. */
10557 next
= next_active_insn (insn
);
10558 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
10562 extract_insn (next
);
10563 code
= INSN_CODE (next
);
10568 case CODE_FOR_adddf3
:
10569 case CODE_FOR_subdf3
:
10570 case CODE_FOR_muldf3
:
10571 case CODE_FOR_divdf3
:
10572 dest
= REGNO (recog_data
.operand
[0]);
10573 src1
= REGNO (recog_data
.operand
[1]);
10574 src2
= REGNO (recog_data
.operand
[2]);
10578 ld [address], %fx+1
10579 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
10580 if ((src1
== x
|| src2
== x
)
10581 && (dest
== src1
|| dest
== src2
))
10587 ld [address], %fx+1
10588 FPOPd %fx, %fx, %fx */
10591 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
10596 case CODE_FOR_sqrtdf2
:
10597 dest
= REGNO (recog_data
.operand
[0]);
10598 src1
= REGNO (recog_data
.operand
[1]);
10600 ld [address], %fx+1
10602 if (src1
== x
&& dest
== src1
)
10611 next
= NEXT_INSN (insn
);
10614 emit_insn_after (gen_nop (), insn
);
10618 /* How to allocate a 'struct machine_function'. */
10620 static struct machine_function
*
10621 sparc_init_machine_status (void)
10623 return ggc_alloc_cleared_machine_function ();
10626 /* Locate some local-dynamic symbol still in use by this function
10627 so that we can print its name in local-dynamic base patterns. */
10629 static const char *
10630 get_some_local_dynamic_name (void)
10634 if (cfun
->machine
->some_ld_name
)
10635 return cfun
->machine
->some_ld_name
;
10637 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10639 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
10640 return cfun
->machine
->some_ld_name
;
10642 gcc_unreachable ();
10646 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10651 && GET_CODE (x
) == SYMBOL_REF
10652 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10654 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
10661 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10662 We need to emit DTP-relative relocations. */
10665 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
10670 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
10673 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
10676 gcc_unreachable ();
10678 output_addr_const (file
, x
);
10682 /* Do whatever processing is required at the end of a file. */
10685 sparc_file_end (void)
10687 /* If we need to emit the special GOT helper function, do so now. */
10688 if (got_helper_rtx
)
10690 const char *name
= XSTR (got_helper_rtx
, 0);
10691 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
10692 #ifdef DWARF2_UNWIND_INFO
10696 if (USE_HIDDEN_LINKONCE
)
10698 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
10699 get_identifier (name
),
10700 build_function_type_list (void_type_node
,
10702 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
10703 NULL_TREE
, void_type_node
);
10704 TREE_STATIC (decl
) = 1;
10705 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
10706 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
10707 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
10708 resolve_unique_section (decl
, 0, flag_function_sections
);
10709 allocate_struct_function (decl
, true);
10710 cfun
->is_thunk
= 1;
10711 current_function_decl
= decl
;
10712 init_varasm_status ();
10713 assemble_start_function (decl
, name
);
10717 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10718 switch_to_section (text_section
);
10720 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10721 ASM_OUTPUT_LABEL (asm_out_file
, name
);
10724 #ifdef DWARF2_UNWIND_INFO
10725 do_cfi
= dwarf2out_do_cfi_asm ();
10727 fprintf (asm_out_file
, "\t.cfi_startproc\n");
10729 if (flag_delayed_branch
)
10730 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10731 reg_name
, reg_name
);
10733 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10734 reg_name
, reg_name
);
10735 #ifdef DWARF2_UNWIND_INFO
10737 fprintf (asm_out_file
, "\t.cfi_endproc\n");
10741 if (NEED_INDICATE_EXEC_STACK
)
10742 file_end_indicate_exec_stack ();
10744 #ifdef TARGET_SOLARIS
10745 solaris_file_end ();
10749 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10750 /* Implement TARGET_MANGLE_TYPE. */
10752 static const char *
10753 sparc_mangle_type (const_tree type
)
10756 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
10757 && TARGET_LONG_DOUBLE_128
)
10760 /* For all other types, use normal C++ mangling. */
10765 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10766 compare and swap on the word containing the byte or half-word. */
10769 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
10771 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10772 rtx addr
= gen_reg_rtx (Pmode
);
10773 rtx off
= gen_reg_rtx (SImode
);
10774 rtx oldv
= gen_reg_rtx (SImode
);
10775 rtx newv
= gen_reg_rtx (SImode
);
10776 rtx oldvalue
= gen_reg_rtx (SImode
);
10777 rtx newvalue
= gen_reg_rtx (SImode
);
10778 rtx res
= gen_reg_rtx (SImode
);
10779 rtx resv
= gen_reg_rtx (SImode
);
10780 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
10782 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
10783 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10785 if (Pmode
!= SImode
)
10786 addr1
= gen_lowpart (SImode
, addr1
);
10787 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10788 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10790 memsi
= gen_rtx_MEM (SImode
, addr
);
10791 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10792 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10794 val
= force_reg (SImode
, memsi
);
10796 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10797 gen_rtx_XOR (SImode
, off
,
10798 GEN_INT (GET_MODE (mem
) == QImode
10801 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10802 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10804 if (GET_MODE (mem
) == QImode
)
10805 mask
= force_reg (SImode
, GEN_INT (0xff));
10807 mask
= force_reg (SImode
, GEN_INT (0xffff));
10809 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10810 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10812 emit_insn (gen_rtx_SET (VOIDmode
, val
,
10813 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10816 oldval
= gen_lowpart (SImode
, oldval
);
10817 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10818 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10820 newval
= gen_lowpart_common (SImode
, newval
);
10821 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10822 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10824 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10825 gen_rtx_AND (SImode
, oldv
, mask
)));
10827 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10828 gen_rtx_AND (SImode
, newv
, mask
)));
10830 end_label
= gen_label_rtx ();
10831 loop_label
= gen_label_rtx ();
10832 emit_label (loop_label
);
10834 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
10835 gen_rtx_IOR (SImode
, oldv
, val
)));
10837 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
10838 gen_rtx_IOR (SImode
, newv
, val
)));
10840 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
10842 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
10844 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
10845 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10848 cc
= gen_compare_reg_1 (NE
, resv
, val
);
10849 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
10851 /* Use cbranchcc4 to separate the compare and branch! */
10852 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
10853 cc
, const0_rtx
, loop_label
));
10855 emit_label (end_label
);
10857 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10858 gen_rtx_AND (SImode
, res
, mask
)));
10860 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10861 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10863 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10866 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10869 sparc_frame_pointer_required (void)
10871 /* If the stack pointer is dynamically modified in the function, it cannot
10872 serve as the frame pointer. */
10873 if (cfun
->calls_alloca
)
10876 /* If the function receives nonlocal gotos, it needs to save the frame
10877 pointer in the nonlocal_goto_save_area object. */
10878 if (cfun
->has_nonlocal_label
)
10881 /* In flat mode, that's it. */
10885 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10886 return !(current_function_is_leaf
&& only_leaf_regs_used ());
10889 /* The way this is structured, we can't eliminate SFP in favor of SP
10890 if the frame pointer is required: we want to use the SFP->HFP elimination
10891 in that case. But the test in update_eliminables doesn't know we are
10892 assuming below that we only do the former elimination. */
10895 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10897 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
10900 /* Return the hard frame pointer directly to bypass the stack bias. */
10903 sparc_builtin_setjmp_frame_value (void)
10905 return hard_frame_pointer_rtx
;
10908 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10909 they won't be allocated. */
10912 sparc_conditional_register_usage (void)
10914 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
10916 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10917 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10919 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10920 /* then honor it. */
10921 if (TARGET_ARCH32
&& fixed_regs
[5])
10923 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
10928 for (regno
= SPARC_FIRST_V9_FP_REG
;
10929 regno
<= SPARC_LAST_V9_FP_REG
;
10931 fixed_regs
[regno
] = 1;
10932 /* %fcc0 is used by v8 and v9. */
10933 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
10934 regno
<= SPARC_LAST_V9_FCC_REG
;
10936 fixed_regs
[regno
] = 1;
10941 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
10942 fixed_regs
[regno
] = 1;
10944 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10945 /* then honor it. Likewise with g3 and g4. */
10946 if (fixed_regs
[2] == 2)
10947 fixed_regs
[2] = ! TARGET_APP_REGS
;
10948 if (fixed_regs
[3] == 2)
10949 fixed_regs
[3] = ! TARGET_APP_REGS
;
10950 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
10951 fixed_regs
[4] = ! TARGET_APP_REGS
;
10952 else if (TARGET_CM_EMBMEDANY
)
10954 else if (fixed_regs
[4] == 2)
10959 /* Disable leaf functions. */
10960 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
10961 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
10962 leaf_reg_remap
[regno
] = regno
;
10965 global_regs
[SPARC_GSR_REG
] = 1;
10968 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10970 - We can't load constants into FP registers.
10971 - We can't load FP constants into integer registers when soft-float,
10972 because there is no soft-float pattern with a r/F constraint.
10973 - We can't load FP constants into integer registers for TFmode unless
10974 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10975 - Try and reload integer constants (symbolic or otherwise) back into
10976 registers directly, rather than having them dumped to memory. */
10979 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
10981 if (CONSTANT_P (x
))
10983 if (FP_REG_CLASS_P (rclass
)
10984 || rclass
== GENERAL_OR_FP_REGS
10985 || rclass
== GENERAL_OR_EXTRA_FP_REGS
10986 || (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
&& ! TARGET_FPU
)
10987 || (GET_MODE (x
) == TFmode
&& ! const_zero_operand (x
, TFmode
)))
10990 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
10991 return GENERAL_REGS
;
10998 output_v8plus_mult (rtx insn
, rtx
*operands
, const char *name
)
11002 gcc_assert (! TARGET_ARCH64
);
11004 if (sparc_check_64 (operands
[1], insn
) <= 0)
11005 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
11006 if (which_alternative
== 1)
11007 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
11008 if (GET_CODE (operands
[2]) == CONST_INT
)
11010 if (which_alternative
== 1)
11012 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
11013 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", name
);
11014 output_asm_insn (mulstr
, operands
);
11015 return "srlx\t%L0, 32, %H0";
11019 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
11020 output_asm_insn ("or\t%L1, %3, %3", operands
);
11021 sprintf (mulstr
, "%s\t%%3, %%2, %%3", name
);
11022 output_asm_insn (mulstr
, operands
);
11023 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
11024 return "mov\t%3, %L0";
11027 else if (rtx_equal_p (operands
[1], operands
[2]))
11029 if (which_alternative
== 1)
11031 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
11032 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", name
);
11033 output_asm_insn (mulstr
, operands
);
11034 return "srlx\t%L0, 32, %H0";
11038 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
11039 output_asm_insn ("or\t%L1, %3, %3", operands
);
11040 sprintf (mulstr
, "%s\t%%3, %%3, %%3", name
);
11041 output_asm_insn (mulstr
, operands
);
11042 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
11043 return "mov\t%3, %L0";
11046 if (sparc_check_64 (operands
[2], insn
) <= 0)
11047 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
11048 if (which_alternative
== 1)
11050 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
11051 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
11052 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
11053 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", name
);
11054 output_asm_insn (mulstr
, operands
);
11055 return "srlx\t%L0, 32, %H0";
11059 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
11060 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
11061 output_asm_insn ("or\t%L1, %3, %3", operands
);
11062 output_asm_insn ("or\t%L2, %4, %4", operands
);
11063 sprintf (mulstr
, "%s\t%%3, %%4, %%3", name
);
11064 output_asm_insn (mulstr
, operands
);
11065 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
11066 return "mov\t%3, %L0";
11071 sparc_expand_vector_init (rtx target
, rtx vals
)
11073 enum machine_mode mode
= GET_MODE (target
);
11074 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
11075 int n_elts
= GET_MODE_NUNITS (mode
);
11079 for (i
= 0; i
< n_elts
; i
++)
11081 rtx x
= XVECEXP (vals
, 0, i
);
11082 if (!CONSTANT_P (x
))
11088 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
11092 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
11093 for (i
= 0; i
< n_elts
; i
++)
11094 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
11095 i
* GET_MODE_SIZE (inner_mode
)),
11096 XVECEXP (vals
, 0, i
));
11097 emit_move_insn (target
, mem
);
11100 #include "gt-sparc.h"